1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMISelLowering.h"
18 #include "ARMTargetMachine.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/Constants.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/Intrinsics.h"
24 #include "llvm/LLVMContext.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/SelectionDAGISel.h"
30 #include "llvm/Target/TargetLowering.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Support/Compiler.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
39 //===--------------------------------------------------------------------===//
40 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
41 /// instructions for SelectionDAG operations.
44 class ARMDAGToDAGISel : public SelectionDAGISel {
45 ARMBaseTargetMachine &TM;
47 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
48 /// make the right decision when generating code for different targets.
49 const ARMSubtarget *Subtarget;
52 explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm,
53 CodeGenOpt::Level OptLevel)
54 : SelectionDAGISel(tm, OptLevel), TM(tm),
55 Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
58 virtual const char *getPassName() const {
59 return "ARM Instruction Selection";
62 /// getI32Imm - Return a target constant with the specified value, of type i32.
63 inline SDValue getI32Imm(unsigned Imm) {
64 return CurDAG->getTargetConstant(Imm, MVT::i32);
67 SDNode *Select(SDValue Op);
68 virtual void InstructionSelect();
69 bool SelectShifterOperandReg(SDValue Op, SDValue N, SDValue &A,
70 SDValue &B, SDValue &C);
71 bool SelectAddrMode2(SDValue Op, SDValue N, SDValue &Base,
72 SDValue &Offset, SDValue &Opc);
73 bool SelectAddrMode2Offset(SDValue Op, SDValue N,
74 SDValue &Offset, SDValue &Opc);
75 bool SelectAddrMode3(SDValue Op, SDValue N, SDValue &Base,
76 SDValue &Offset, SDValue &Opc);
77 bool SelectAddrMode3Offset(SDValue Op, SDValue N,
78 SDValue &Offset, SDValue &Opc);
79 bool SelectAddrMode4(SDValue Op, SDValue N, SDValue &Addr,
81 bool SelectAddrMode5(SDValue Op, SDValue N, SDValue &Base,
83 bool SelectAddrMode6(SDValue Op, SDValue N, SDValue &Addr, SDValue &Update,
86 bool SelectAddrModePC(SDValue Op, SDValue N, SDValue &Offset,
89 bool SelectThumbAddrModeRR(SDValue Op, SDValue N, SDValue &Base,
91 bool SelectThumbAddrModeRI5(SDValue Op, SDValue N, unsigned Scale,
92 SDValue &Base, SDValue &OffImm,
94 bool SelectThumbAddrModeS1(SDValue Op, SDValue N, SDValue &Base,
95 SDValue &OffImm, SDValue &Offset);
96 bool SelectThumbAddrModeS2(SDValue Op, SDValue N, SDValue &Base,
97 SDValue &OffImm, SDValue &Offset);
98 bool SelectThumbAddrModeS4(SDValue Op, SDValue N, SDValue &Base,
99 SDValue &OffImm, SDValue &Offset);
100 bool SelectThumbAddrModeSP(SDValue Op, SDValue N, SDValue &Base,
103 bool SelectT2ShifterOperandReg(SDValue Op, SDValue N,
104 SDValue &BaseReg, SDValue &Opc);
105 bool SelectT2AddrModeImm12(SDValue Op, SDValue N, SDValue &Base,
107 bool SelectT2AddrModeImm8(SDValue Op, SDValue N, SDValue &Base,
109 bool SelectT2AddrModeImm8Offset(SDValue Op, SDValue N,
111 bool SelectT2AddrModeImm8s4(SDValue Op, SDValue N, SDValue &Base,
113 bool SelectT2AddrModeSoReg(SDValue Op, SDValue N, SDValue &Base,
114 SDValue &OffReg, SDValue &ShImm);
116 // Include the pieces autogenerated from the target description.
117 #include "ARMGenDAGISel.inc"
120 /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
122 SDNode *SelectARMIndexedLoad(SDValue Op);
123 SDNode *SelectT2IndexedLoad(SDValue Op);
125 /// SelectDYN_ALLOC - Select dynamic alloc for Thumb.
126 SDNode *SelectDYN_ALLOC(SDValue Op);
128 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
129 /// inline asm expressions.
130 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
132 std::vector<SDValue> &OutOps);
134 /// PairDRegs - Insert a pair of double registers into an implicit def to
135 /// form a quad register.
136 SDNode *PairDRegs(EVT VT, SDValue V0, SDValue V1);
140 void ARMDAGToDAGISel::InstructionSelect() {
144 CurDAG->RemoveDeadNodes();
147 bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue Op,
152 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
154 // Don't match base register only case. That is matched to a separate
155 // lower complexity pattern with explicit register operand.
156 if (ShOpcVal == ARM_AM::no_shift) return false;
158 BaseReg = N.getOperand(0);
159 unsigned ShImmVal = 0;
160 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
161 ShReg = CurDAG->getRegister(0, MVT::i32);
162 ShImmVal = RHS->getZExtValue() & 31;
164 ShReg = N.getOperand(1);
166 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
171 bool ARMDAGToDAGISel::SelectAddrMode2(SDValue Op, SDValue N,
172 SDValue &Base, SDValue &Offset,
174 if (N.getOpcode() == ISD::MUL) {
175 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
176 // X * [3,5,9] -> X + X * [2,4,8] etc.
177 int RHSC = (int)RHS->getZExtValue();
180 ARM_AM::AddrOpc AddSub = ARM_AM::add;
182 AddSub = ARM_AM::sub;
185 if (isPowerOf2_32(RHSC)) {
186 unsigned ShAmt = Log2_32(RHSC);
187 Base = Offset = N.getOperand(0);
188 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
197 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
199 if (N.getOpcode() == ISD::FrameIndex) {
200 int FI = cast<FrameIndexSDNode>(N)->getIndex();
201 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
202 } else if (N.getOpcode() == ARMISD::Wrapper) {
203 Base = N.getOperand(0);
205 Offset = CurDAG->getRegister(0, MVT::i32);
206 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
212 // Match simple R +/- imm12 operands.
213 if (N.getOpcode() == ISD::ADD)
214 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
215 int RHSC = (int)RHS->getZExtValue();
216 if ((RHSC >= 0 && RHSC < 0x1000) ||
217 (RHSC < 0 && RHSC > -0x1000)) { // 12 bits.
218 Base = N.getOperand(0);
219 if (Base.getOpcode() == ISD::FrameIndex) {
220 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
221 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
223 Offset = CurDAG->getRegister(0, MVT::i32);
225 ARM_AM::AddrOpc AddSub = ARM_AM::add;
227 AddSub = ARM_AM::sub;
230 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
237 // Otherwise this is R +/- [possibly shifted] R
238 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
239 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
242 Base = N.getOperand(0);
243 Offset = N.getOperand(1);
245 if (ShOpcVal != ARM_AM::no_shift) {
246 // Check to see if the RHS of the shift is a constant, if not, we can't fold
248 if (ConstantSDNode *Sh =
249 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
250 ShAmt = Sh->getZExtValue();
251 Offset = N.getOperand(1).getOperand(0);
253 ShOpcVal = ARM_AM::no_shift;
257 // Try matching (R shl C) + (R).
258 if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift) {
259 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
260 if (ShOpcVal != ARM_AM::no_shift) {
261 // Check to see if the RHS of the shift is a constant, if not, we can't
263 if (ConstantSDNode *Sh =
264 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
265 ShAmt = Sh->getZExtValue();
266 Offset = N.getOperand(0).getOperand(0);
267 Base = N.getOperand(1);
269 ShOpcVal = ARM_AM::no_shift;
274 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
279 bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDValue Op, SDValue N,
280 SDValue &Offset, SDValue &Opc) {
281 unsigned Opcode = Op.getOpcode();
282 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
283 ? cast<LoadSDNode>(Op)->getAddressingMode()
284 : cast<StoreSDNode>(Op)->getAddressingMode();
285 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
286 ? ARM_AM::add : ARM_AM::sub;
287 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
288 int Val = (int)C->getZExtValue();
289 if (Val >= 0 && Val < 0x1000) { // 12 bits.
290 Offset = CurDAG->getRegister(0, MVT::i32);
291 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
299 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
301 if (ShOpcVal != ARM_AM::no_shift) {
302 // Check to see if the RHS of the shift is a constant, if not, we can't fold
304 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
305 ShAmt = Sh->getZExtValue();
306 Offset = N.getOperand(0);
308 ShOpcVal = ARM_AM::no_shift;
312 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
318 bool ARMDAGToDAGISel::SelectAddrMode3(SDValue Op, SDValue N,
319 SDValue &Base, SDValue &Offset,
321 if (N.getOpcode() == ISD::SUB) {
322 // X - C is canonicalize to X + -C, no need to handle it here.
323 Base = N.getOperand(0);
324 Offset = N.getOperand(1);
325 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
329 if (N.getOpcode() != ISD::ADD) {
331 if (N.getOpcode() == ISD::FrameIndex) {
332 int FI = cast<FrameIndexSDNode>(N)->getIndex();
333 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
335 Offset = CurDAG->getRegister(0, MVT::i32);
336 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
340 // If the RHS is +/- imm8, fold into addr mode.
341 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
342 int RHSC = (int)RHS->getZExtValue();
343 if ((RHSC >= 0 && RHSC < 256) ||
344 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
345 Base = N.getOperand(0);
346 if (Base.getOpcode() == ISD::FrameIndex) {
347 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
348 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
350 Offset = CurDAG->getRegister(0, MVT::i32);
352 ARM_AM::AddrOpc AddSub = ARM_AM::add;
354 AddSub = ARM_AM::sub;
357 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
362 Base = N.getOperand(0);
363 Offset = N.getOperand(1);
364 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
368 bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDValue Op, SDValue N,
369 SDValue &Offset, SDValue &Opc) {
370 unsigned Opcode = Op.getOpcode();
371 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
372 ? cast<LoadSDNode>(Op)->getAddressingMode()
373 : cast<StoreSDNode>(Op)->getAddressingMode();
374 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
375 ? ARM_AM::add : ARM_AM::sub;
376 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
377 int Val = (int)C->getZExtValue();
378 if (Val >= 0 && Val < 256) {
379 Offset = CurDAG->getRegister(0, MVT::i32);
380 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
386 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
390 bool ARMDAGToDAGISel::SelectAddrMode4(SDValue Op, SDValue N,
391 SDValue &Addr, SDValue &Mode) {
393 Mode = CurDAG->getTargetConstant(0, MVT::i32);
397 bool ARMDAGToDAGISel::SelectAddrMode5(SDValue Op, SDValue N,
398 SDValue &Base, SDValue &Offset) {
399 if (N.getOpcode() != ISD::ADD) {
401 if (N.getOpcode() == ISD::FrameIndex) {
402 int FI = cast<FrameIndexSDNode>(N)->getIndex();
403 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
404 } else if (N.getOpcode() == ARMISD::Wrapper) {
405 Base = N.getOperand(0);
407 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
412 // If the RHS is +/- imm8, fold into addr mode.
413 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
414 int RHSC = (int)RHS->getZExtValue();
415 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied by 4.
417 if ((RHSC >= 0 && RHSC < 256) ||
418 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
419 Base = N.getOperand(0);
420 if (Base.getOpcode() == ISD::FrameIndex) {
421 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
422 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
425 ARM_AM::AddrOpc AddSub = ARM_AM::add;
427 AddSub = ARM_AM::sub;
430 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
438 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
443 bool ARMDAGToDAGISel::SelectAddrMode6(SDValue Op, SDValue N,
444 SDValue &Addr, SDValue &Update,
447 // Default to no writeback.
448 Update = CurDAG->getRegister(0, MVT::i32);
449 Opc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(false), MVT::i32);
453 bool ARMDAGToDAGISel::SelectAddrModePC(SDValue Op, SDValue N,
454 SDValue &Offset, SDValue &Label) {
455 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
456 Offset = N.getOperand(0);
457 SDValue N1 = N.getOperand(1);
458 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
465 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue Op, SDValue N,
466 SDValue &Base, SDValue &Offset){
467 // FIXME dl should come from the parent load or store, not the address
468 DebugLoc dl = Op.getDebugLoc();
469 if (N.getOpcode() != ISD::ADD) {
470 ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
471 if (!NC || NC->getZExtValue() != 0)
478 Base = N.getOperand(0);
479 Offset = N.getOperand(1);
484 ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDValue Op, SDValue N,
485 unsigned Scale, SDValue &Base,
486 SDValue &OffImm, SDValue &Offset) {
488 SDValue TmpBase, TmpOffImm;
489 if (SelectThumbAddrModeSP(Op, N, TmpBase, TmpOffImm))
490 return false; // We want to select tLDRspi / tSTRspi instead.
491 if (N.getOpcode() == ARMISD::Wrapper &&
492 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
493 return false; // We want to select tLDRpci instead.
496 if (N.getOpcode() != ISD::ADD) {
497 Base = (N.getOpcode() == ARMISD::Wrapper) ? N.getOperand(0) : N;
498 Offset = CurDAG->getRegister(0, MVT::i32);
499 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
503 // Thumb does not have [sp, r] address mode.
504 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
505 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
506 if ((LHSR && LHSR->getReg() == ARM::SP) ||
507 (RHSR && RHSR->getReg() == ARM::SP)) {
509 Offset = CurDAG->getRegister(0, MVT::i32);
510 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
514 // If the RHS is + imm5 * scale, fold into addr mode.
515 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
516 int RHSC = (int)RHS->getZExtValue();
517 if ((RHSC & (Scale-1)) == 0) { // The constant is implicitly multiplied.
519 if (RHSC >= 0 && RHSC < 32) {
520 Base = N.getOperand(0);
521 Offset = CurDAG->getRegister(0, MVT::i32);
522 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
528 Base = N.getOperand(0);
529 Offset = N.getOperand(1);
530 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
534 bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDValue Op, SDValue N,
535 SDValue &Base, SDValue &OffImm,
537 return SelectThumbAddrModeRI5(Op, N, 1, Base, OffImm, Offset);
540 bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDValue Op, SDValue N,
541 SDValue &Base, SDValue &OffImm,
543 return SelectThumbAddrModeRI5(Op, N, 2, Base, OffImm, Offset);
546 bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDValue Op, SDValue N,
547 SDValue &Base, SDValue &OffImm,
549 return SelectThumbAddrModeRI5(Op, N, 4, Base, OffImm, Offset);
552 bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue Op, SDValue N,
553 SDValue &Base, SDValue &OffImm) {
554 if (N.getOpcode() == ISD::FrameIndex) {
555 int FI = cast<FrameIndexSDNode>(N)->getIndex();
556 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
557 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
561 if (N.getOpcode() != ISD::ADD)
564 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
565 if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
566 (LHSR && LHSR->getReg() == ARM::SP)) {
567 // If the RHS is + imm8 * scale, fold into addr mode.
568 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
569 int RHSC = (int)RHS->getZExtValue();
570 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied.
572 if (RHSC >= 0 && RHSC < 256) {
573 Base = N.getOperand(0);
574 if (Base.getOpcode() == ISD::FrameIndex) {
575 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
576 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
578 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
588 bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue Op, SDValue N,
591 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
593 // Don't match base register only case. That is matched to a separate
594 // lower complexity pattern with explicit register operand.
595 if (ShOpcVal == ARM_AM::no_shift) return false;
597 BaseReg = N.getOperand(0);
598 unsigned ShImmVal = 0;
599 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
600 ShImmVal = RHS->getZExtValue() & 31;
601 Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
608 bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue Op, SDValue N,
609 SDValue &Base, SDValue &OffImm) {
610 // Match simple R + imm12 operands.
613 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
614 if (N.getOpcode() == ISD::FrameIndex) {
615 // Match frame index...
616 int FI = cast<FrameIndexSDNode>(N)->getIndex();
617 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
618 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
620 } else if (N.getOpcode() == ARMISD::Wrapper) {
621 Base = N.getOperand(0);
622 if (Base.getOpcode() == ISD::TargetConstantPool)
623 return false; // We want to select t2LDRpci instead.
626 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
630 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
631 if (SelectT2AddrModeImm8(Op, N, Base, OffImm))
632 // Let t2LDRi8 handle (R - imm8).
635 int RHSC = (int)RHS->getZExtValue();
636 if (N.getOpcode() == ISD::SUB)
639 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
640 Base = N.getOperand(0);
641 if (Base.getOpcode() == ISD::FrameIndex) {
642 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
643 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
645 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
652 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
656 bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue Op, SDValue N,
657 SDValue &Base, SDValue &OffImm) {
658 // Match simple R - imm8 operands.
659 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::SUB) {
660 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
661 int RHSC = (int)RHS->getSExtValue();
662 if (N.getOpcode() == ISD::SUB)
665 if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative)
666 Base = N.getOperand(0);
667 if (Base.getOpcode() == ISD::FrameIndex) {
668 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
669 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
671 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
680 bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDValue Op, SDValue N,
682 unsigned Opcode = Op.getOpcode();
683 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
684 ? cast<LoadSDNode>(Op)->getAddressingMode()
685 : cast<StoreSDNode>(Op)->getAddressingMode();
686 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N)) {
687 int RHSC = (int)RHS->getZExtValue();
688 if (RHSC >= 0 && RHSC < 0x100) { // 8 bits.
689 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
690 ? CurDAG->getTargetConstant(RHSC, MVT::i32)
691 : CurDAG->getTargetConstant(-RHSC, MVT::i32);
699 bool ARMDAGToDAGISel::SelectT2AddrModeImm8s4(SDValue Op, SDValue N,
700 SDValue &Base, SDValue &OffImm) {
701 if (N.getOpcode() == ISD::ADD) {
702 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
703 int RHSC = (int)RHS->getZExtValue();
704 if (((RHSC & 0x3) == 0) &&
705 ((RHSC >= 0 && RHSC < 0x400) || (RHSC < 0 && RHSC > -0x400))) { // 8 bits.
706 Base = N.getOperand(0);
707 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
711 } else if (N.getOpcode() == ISD::SUB) {
712 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
713 int RHSC = (int)RHS->getZExtValue();
714 if (((RHSC & 0x3) == 0) && (RHSC >= 0 && RHSC < 0x400)) { // 8 bits.
715 Base = N.getOperand(0);
716 OffImm = CurDAG->getTargetConstant(-RHSC, MVT::i32);
725 bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue Op, SDValue N,
727 SDValue &OffReg, SDValue &ShImm) {
728 // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.
729 if (N.getOpcode() != ISD::ADD)
732 // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8.
733 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
734 int RHSC = (int)RHS->getZExtValue();
735 if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned)
737 else if (RHSC < 0 && RHSC >= -255) // 8 bits
741 // Look for (R + R) or (R + (R << [1,2,3])).
743 Base = N.getOperand(0);
744 OffReg = N.getOperand(1);
746 // Swap if it is ((R << c) + R).
747 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg);
748 if (ShOpcVal != ARM_AM::lsl) {
749 ShOpcVal = ARM_AM::getShiftOpcForNode(Base);
750 if (ShOpcVal == ARM_AM::lsl)
751 std::swap(Base, OffReg);
754 if (ShOpcVal == ARM_AM::lsl) {
755 // Check to see if the RHS of the shift is a constant, if not, we can't fold
757 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
758 ShAmt = Sh->getZExtValue();
761 ShOpcVal = ARM_AM::no_shift;
763 OffReg = OffReg.getOperand(0);
765 ShOpcVal = ARM_AM::no_shift;
769 ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
774 //===--------------------------------------------------------------------===//
776 /// getAL - Returns a ARMCC::AL immediate node.
777 static inline SDValue getAL(SelectionDAG *CurDAG) {
778 return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
781 SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDValue Op) {
782 LoadSDNode *LD = cast<LoadSDNode>(Op);
783 ISD::MemIndexedMode AM = LD->getAddressingMode();
784 if (AM == ISD::UNINDEXED)
787 EVT LoadedVT = LD->getMemoryVT();
788 SDValue Offset, AMOpc;
789 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
792 if (LoadedVT == MVT::i32 &&
793 SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
794 Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST;
796 } else if (LoadedVT == MVT::i16 &&
797 SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
799 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
800 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
801 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
802 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
803 if (LD->getExtensionType() == ISD::SEXTLOAD) {
804 if (SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
806 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
809 if (SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
811 Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST;
817 SDValue Chain = LD->getChain();
818 SDValue Base = LD->getBasePtr();
819 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
820 CurDAG->getRegister(0, MVT::i32), Chain };
821 return CurDAG->getMachineNode(Opcode, Op.getDebugLoc(), MVT::i32, MVT::i32,
828 SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDValue Op) {
829 LoadSDNode *LD = cast<LoadSDNode>(Op);
830 ISD::MemIndexedMode AM = LD->getAddressingMode();
831 if (AM == ISD::UNINDEXED)
834 EVT LoadedVT = LD->getMemoryVT();
835 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
837 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
840 if (SelectT2AddrModeImm8Offset(Op, LD->getOffset(), Offset)) {
841 switch (LoadedVT.getSimpleVT().SimpleTy) {
843 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
847 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
849 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
854 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
856 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
865 SDValue Chain = LD->getChain();
866 SDValue Base = LD->getBasePtr();
867 SDValue Ops[]= { Base, Offset, getAL(CurDAG),
868 CurDAG->getRegister(0, MVT::i32), Chain };
869 return CurDAG->getMachineNode(Opcode, Op.getDebugLoc(), MVT::i32, MVT::i32,
876 SDNode *ARMDAGToDAGISel::SelectDYN_ALLOC(SDValue Op) {
877 SDNode *N = Op.getNode();
878 DebugLoc dl = N->getDebugLoc();
879 EVT VT = Op.getValueType();
880 SDValue Chain = Op.getOperand(0);
881 SDValue Size = Op.getOperand(1);
882 SDValue Align = Op.getOperand(2);
883 SDValue SP = CurDAG->getRegister(ARM::SP, MVT::i32);
884 int32_t AlignVal = cast<ConstantSDNode>(Align)->getSExtValue();
886 // We need to align the stack. Use Thumb1 tAND which is the only thumb
887 // instruction that can read and write SP. This matches to a pseudo
888 // instruction that has a chain to ensure the result is written back to
889 // the stack pointer.
890 SP = SDValue(CurDAG->getMachineNode(ARM::tANDsp, dl, VT, SP, Align), 0);
892 bool isC = isa<ConstantSDNode>(Size);
893 uint32_t C = isC ? cast<ConstantSDNode>(Size)->getZExtValue() : ~0UL;
894 // Handle the most common case for both Thumb1 and Thumb2:
895 // tSUBspi - immediate is between 0 ... 508 inclusive.
896 if (C <= 508 && ((C & 3) == 0))
897 // FIXME: tSUBspi encode scale 4 implicitly.
898 return CurDAG->SelectNodeTo(N, ARM::tSUBspi_, VT, MVT::Other, SP,
899 CurDAG->getTargetConstant(C/4, MVT::i32),
902 if (Subtarget->isThumb1Only()) {
903 // Use tADDspr since Thumb1 does not have a sub r, sp, r. ARMISelLowering
904 // should have negated the size operand already. FIXME: We can't insert
905 // new target independent node at this stage so we are forced to negate
906 // it earlier. Is there a better solution?
907 return CurDAG->SelectNodeTo(N, ARM::tADDspr_, VT, MVT::Other, SP, Size,
909 } else if (Subtarget->isThumb2()) {
910 if (isC && Predicate_t2_so_imm(Size.getNode())) {
912 SDValue Ops[] = { SP, CurDAG->getTargetConstant(C, MVT::i32), Chain };
913 return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPi_, VT, MVT::Other, Ops, 3);
914 } else if (isC && Predicate_imm0_4095(Size.getNode())) {
916 SDValue Ops[] = { SP, CurDAG->getTargetConstant(C, MVT::i32), Chain };
917 return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPi12_, VT, MVT::Other, Ops, 3);
920 SDValue Ops[] = { SP, Size,
921 getI32Imm(ARM_AM::getSORegOpc(ARM_AM::lsl,0)), Chain };
922 return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPs_, VT, MVT::Other, Ops, 4);
926 // FIXME: Add ADD / SUB sp instructions for ARM.
930 /// PairDRegs - Insert a pair of double registers into an implicit def to
931 /// form a quad register.
932 SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) {
933 DebugLoc dl = V0.getNode()->getDebugLoc();
935 SDValue(CurDAG->getMachineNode(TargetInstrInfo::IMPLICIT_DEF, dl, VT), 0);
936 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::DSUBREG_0, MVT::i32);
937 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::DSUBREG_1, MVT::i32);
938 SDNode *Pair = CurDAG->getMachineNode(TargetInstrInfo::INSERT_SUBREG, dl,
939 VT, Undef, V0, SubReg0);
940 return CurDAG->getMachineNode(TargetInstrInfo::INSERT_SUBREG, dl,
941 VT, SDValue(Pair, 0), V1, SubReg1);
944 SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
945 SDNode *N = Op.getNode();
946 DebugLoc dl = N->getDebugLoc();
948 if (N->isMachineOpcode())
949 return NULL; // Already selected.
951 switch (N->getOpcode()) {
953 case ISD::Constant: {
954 unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
956 if (Subtarget->hasThumb2())
957 // Thumb2-aware targets have the MOVT instruction, so all immediates can
958 // be done with MOV + MOVT, at worst.
961 if (Subtarget->isThumb()) {
962 UseCP = (Val > 255 && // MOV
963 ~Val > 255 && // MOV + MVN
964 !ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL
966 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
967 ARM_AM::getSOImmVal(~Val) == -1 && // MVN
968 !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs.
973 CurDAG->getTargetConstantPool(ConstantInt::get(
974 Type::getInt32Ty(*CurDAG->getContext()), Val),
978 if (Subtarget->isThumb1Only()) {
979 SDValue Pred = CurDAG->getTargetConstant(0xEULL, MVT::i32);
980 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
981 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
982 ResNode = CurDAG->getMachineNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other,
987 CurDAG->getRegister(0, MVT::i32),
988 CurDAG->getTargetConstant(0, MVT::i32),
990 CurDAG->getRegister(0, MVT::i32),
991 CurDAG->getEntryNode()
993 ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
996 ReplaceUses(Op, SDValue(ResNode, 0));
1000 // Other cases are autogenerated.
1003 case ISD::FrameIndex: {
1004 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
1005 int FI = cast<FrameIndexSDNode>(N)->getIndex();
1006 SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1007 if (Subtarget->isThumb1Only()) {
1008 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
1009 CurDAG->getTargetConstant(0, MVT::i32));
1011 unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
1012 ARM::t2ADDri : ARM::ADDri);
1013 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
1014 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1015 CurDAG->getRegister(0, MVT::i32) };
1016 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1019 case ARMISD::DYN_ALLOC:
1020 return SelectDYN_ALLOC(Op);
1022 if (Subtarget->isThumb1Only())
1024 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1025 unsigned RHSV = C->getZExtValue();
1027 if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
1028 unsigned ShImm = Log2_32(RHSV-1);
1031 SDValue V = Op.getOperand(0);
1032 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
1033 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
1034 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1035 if (Subtarget->isThumb()) {
1036 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1037 return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
1039 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1040 return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7);
1043 if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
1044 unsigned ShImm = Log2_32(RHSV+1);
1047 SDValue V = Op.getOperand(0);
1048 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
1049 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
1050 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1051 if (Subtarget->isThumb()) {
1052 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0 };
1053 return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 5);
1055 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1056 return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7);
1062 return CurDAG->getMachineNode(ARM::FMRRD, dl, MVT::i32, MVT::i32,
1063 Op.getOperand(0), getAL(CurDAG),
1064 CurDAG->getRegister(0, MVT::i32));
1065 case ISD::UMUL_LOHI: {
1066 if (Subtarget->isThumb1Only())
1068 if (Subtarget->isThumb()) {
1069 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
1070 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1071 CurDAG->getRegister(0, MVT::i32) };
1072 return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32, Ops,4);
1074 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
1075 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1076 CurDAG->getRegister(0, MVT::i32) };
1077 return CurDAG->getMachineNode(ARM::UMULL, dl, MVT::i32, MVT::i32, Ops, 5);
1080 case ISD::SMUL_LOHI: {
1081 if (Subtarget->isThumb1Only())
1083 if (Subtarget->isThumb()) {
1084 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
1085 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
1086 return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32, Ops,4);
1088 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
1089 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1090 CurDAG->getRegister(0, MVT::i32) };
1091 return CurDAG->getMachineNode(ARM::SMULL, dl, MVT::i32, MVT::i32, Ops, 5);
1095 SDNode *ResNode = 0;
1096 if (Subtarget->isThumb() && Subtarget->hasThumb2())
1097 ResNode = SelectT2IndexedLoad(Op);
1099 ResNode = SelectARMIndexedLoad(Op);
1102 // Other cases are autogenerated.
1105 case ARMISD::BRCOND: {
1106 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1107 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
1108 // Pattern complexity = 6 cost = 1 size = 0
1110 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1111 // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
1112 // Pattern complexity = 6 cost = 1 size = 0
1114 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1115 // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
1116 // Pattern complexity = 6 cost = 1 size = 0
1118 unsigned Opc = Subtarget->isThumb() ?
1119 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
1120 SDValue Chain = Op.getOperand(0);
1121 SDValue N1 = Op.getOperand(1);
1122 SDValue N2 = Op.getOperand(2);
1123 SDValue N3 = Op.getOperand(3);
1124 SDValue InFlag = Op.getOperand(4);
1125 assert(N1.getOpcode() == ISD::BasicBlock);
1126 assert(N2.getOpcode() == ISD::Constant);
1127 assert(N3.getOpcode() == ISD::Register);
1129 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1130 cast<ConstantSDNode>(N2)->getZExtValue()),
1132 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
1133 SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,
1135 Chain = SDValue(ResNode, 0);
1136 if (Op.getNode()->getNumValues() == 2) {
1137 InFlag = SDValue(ResNode, 1);
1138 ReplaceUses(SDValue(Op.getNode(), 1), InFlag);
1140 ReplaceUses(SDValue(Op.getNode(), 0), SDValue(Chain.getNode(), Chain.getResNo()));
1143 case ARMISD::CMOV: {
1144 EVT VT = Op.getValueType();
1145 SDValue N0 = Op.getOperand(0);
1146 SDValue N1 = Op.getOperand(1);
1147 SDValue N2 = Op.getOperand(2);
1148 SDValue N3 = Op.getOperand(3);
1149 SDValue InFlag = Op.getOperand(4);
1150 assert(N2.getOpcode() == ISD::Constant);
1151 assert(N3.getOpcode() == ISD::Register);
1153 if (!Subtarget->isThumb1Only() && VT == MVT::i32) {
1154 // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1155 // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1156 // Pattern complexity = 18 cost = 1 size = 0
1160 if (Subtarget->isThumb()) {
1161 if (SelectT2ShifterOperandReg(Op, N1, CPTmp0, CPTmp1)) {
1162 unsigned SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue();
1163 unsigned SOShOp = ARM_AM::getSORegShOp(SOVal);
1166 case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break;
1167 case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break;
1168 case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break;
1169 case ARM_AM::ror: Opc = ARM::t2MOVCCror; break;
1171 llvm_unreachable("Unknown so_reg opcode!");
1175 CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32);
1176 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1177 cast<ConstantSDNode>(N2)->getZExtValue()),
1179 SDValue Ops[] = { N0, CPTmp0, SOShImm, Tmp2, N3, InFlag };
1180 return CurDAG->SelectNodeTo(Op.getNode(), Opc, MVT::i32,Ops, 6);
1183 if (SelectShifterOperandReg(Op, N1, CPTmp0, CPTmp1, CPTmp2)) {
1184 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1185 cast<ConstantSDNode>(N2)->getZExtValue()),
1187 SDValue Ops[] = { N0, CPTmp0, CPTmp1, CPTmp2, Tmp2, N3, InFlag };
1188 return CurDAG->SelectNodeTo(Op.getNode(),
1189 ARM::MOVCCs, MVT::i32, Ops, 7);
1193 // Pattern: (ARMcmov:i32 GPR:i32:$false,
1194 // (imm:i32)<<P:Predicate_so_imm>>:$true,
1196 // Emits: (MOVCCi:i32 GPR:i32:$false,
1197 // (so_imm:i32 (imm:i32):$true), (imm:i32):$cc)
1198 // Pattern complexity = 10 cost = 1 size = 0
1199 if (N3.getOpcode() == ISD::Constant) {
1200 if (Subtarget->isThumb()) {
1201 if (Predicate_t2_so_imm(N3.getNode())) {
1202 SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
1203 cast<ConstantSDNode>(N1)->getZExtValue()),
1205 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1206 cast<ConstantSDNode>(N2)->getZExtValue()),
1208 SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
1209 return CurDAG->SelectNodeTo(Op.getNode(),
1210 ARM::t2MOVCCi, MVT::i32, Ops, 5);
1213 if (Predicate_so_imm(N3.getNode())) {
1214 SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
1215 cast<ConstantSDNode>(N1)->getZExtValue()),
1217 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1218 cast<ConstantSDNode>(N2)->getZExtValue()),
1220 SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
1221 return CurDAG->SelectNodeTo(Op.getNode(),
1222 ARM::MOVCCi, MVT::i32, Ops, 5);
1228 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1229 // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1230 // Pattern complexity = 6 cost = 1 size = 0
1232 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1233 // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1234 // Pattern complexity = 6 cost = 11 size = 0
1236 // Also FCPYScc and FCPYDcc.
1237 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1238 cast<ConstantSDNode>(N2)->getZExtValue()),
1240 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
1242 switch (VT.getSimpleVT().SimpleTy) {
1243 default: assert(false && "Illegal conditional move type!");
1246 Opc = Subtarget->isThumb()
1247 ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo)
1257 return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
1259 case ARMISD::CNEG: {
1260 EVT VT = Op.getValueType();
1261 SDValue N0 = Op.getOperand(0);
1262 SDValue N1 = Op.getOperand(1);
1263 SDValue N2 = Op.getOperand(2);
1264 SDValue N3 = Op.getOperand(3);
1265 SDValue InFlag = Op.getOperand(4);
1266 assert(N2.getOpcode() == ISD::Constant);
1267 assert(N3.getOpcode() == ISD::Register);
1269 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1270 cast<ConstantSDNode>(N2)->getZExtValue()),
1272 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
1274 switch (VT.getSimpleVT().SimpleTy) {
1275 default: assert(false && "Illegal conditional move type!");
1284 return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
1287 case ARMISD::VZIP: {
1289 EVT VT = N->getValueType(0);
1290 switch (VT.getSimpleVT().SimpleTy) {
1291 default: return NULL;
1292 case MVT::v8i8: Opc = ARM::VZIPd8; break;
1293 case MVT::v4i16: Opc = ARM::VZIPd16; break;
1295 case MVT::v2i32: Opc = ARM::VZIPd32; break;
1296 case MVT::v16i8: Opc = ARM::VZIPq8; break;
1297 case MVT::v8i16: Opc = ARM::VZIPq16; break;
1299 case MVT::v4i32: Opc = ARM::VZIPq32; break;
1301 return CurDAG->getMachineNode(Opc, dl, VT, VT,
1302 N->getOperand(0), N->getOperand(1));
1304 case ARMISD::VUZP: {
1306 EVT VT = N->getValueType(0);
1307 switch (VT.getSimpleVT().SimpleTy) {
1308 default: return NULL;
1309 case MVT::v8i8: Opc = ARM::VUZPd8; break;
1310 case MVT::v4i16: Opc = ARM::VUZPd16; break;
1312 case MVT::v2i32: Opc = ARM::VUZPd32; break;
1313 case MVT::v16i8: Opc = ARM::VUZPq8; break;
1314 case MVT::v8i16: Opc = ARM::VUZPq16; break;
1316 case MVT::v4i32: Opc = ARM::VUZPq32; break;
1318 return CurDAG->getMachineNode(Opc, dl, VT, VT,
1319 N->getOperand(0), N->getOperand(1));
1321 case ARMISD::VTRN: {
1323 EVT VT = N->getValueType(0);
1324 switch (VT.getSimpleVT().SimpleTy) {
1325 default: return NULL;
1326 case MVT::v8i8: Opc = ARM::VTRNd8; break;
1327 case MVT::v4i16: Opc = ARM::VTRNd16; break;
1329 case MVT::v2i32: Opc = ARM::VTRNd32; break;
1330 case MVT::v16i8: Opc = ARM::VTRNq8; break;
1331 case MVT::v8i16: Opc = ARM::VTRNq16; break;
1333 case MVT::v4i32: Opc = ARM::VTRNq32; break;
1335 return CurDAG->getMachineNode(Opc, dl, VT, VT,
1336 N->getOperand(0), N->getOperand(1));
1339 case ISD::INTRINSIC_VOID:
1340 case ISD::INTRINSIC_W_CHAIN: {
1341 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
1342 EVT VT = N->getValueType(0);
1349 case Intrinsic::arm_neon_vld2: {
1350 SDValue MemAddr, MemUpdate, MemOpc;
1351 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1353 if (VT.is64BitVector()) {
1354 switch (VT.getSimpleVT().SimpleTy) {
1355 default: llvm_unreachable("unhandled vld2 type");
1356 case MVT::v8i8: Opc = ARM::VLD2d8; break;
1357 case MVT::v4i16: Opc = ARM::VLD2d16; break;
1359 case MVT::v2i32: Opc = ARM::VLD2d32; break;
1360 case MVT::v1i64: Opc = ARM::VLD2d64; break;
1362 SDValue Chain = N->getOperand(0);
1363 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
1364 return CurDAG->getMachineNode(Opc, dl, VT, VT, MVT::Other, Ops, 4);
1366 // Quad registers are loaded as pairs of double registers.
1368 switch (VT.getSimpleVT().SimpleTy) {
1369 default: llvm_unreachable("unhandled vld2 type");
1370 case MVT::v16i8: Opc = ARM::VLD2q8; RegVT = MVT::v8i8; break;
1371 case MVT::v8i16: Opc = ARM::VLD2q16; RegVT = MVT::v4i16; break;
1372 case MVT::v4f32: Opc = ARM::VLD2q32; RegVT = MVT::v2f32; break;
1373 case MVT::v4i32: Opc = ARM::VLD2q32; RegVT = MVT::v2i32; break;
1375 SDValue Chain = N->getOperand(0);
1376 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
1377 std::vector<EVT> ResTys(4, RegVT);
1378 ResTys.push_back(MVT::Other);
1379 SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 4);
1380 SDNode *Q0 = PairDRegs(VT, SDValue(VLd, 0), SDValue(VLd, 1));
1381 SDNode *Q1 = PairDRegs(VT, SDValue(VLd, 2), SDValue(VLd, 3));
1382 ReplaceUses(SDValue(N, 0), SDValue(Q0, 0));
1383 ReplaceUses(SDValue(N, 1), SDValue(Q1, 0));
1384 ReplaceUses(SDValue(N, 2), SDValue(VLd, 4));
1388 case Intrinsic::arm_neon_vld3: {
1389 SDValue MemAddr, MemUpdate, MemOpc;
1390 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1392 if (VT.is64BitVector()) {
1393 switch (VT.getSimpleVT().SimpleTy) {
1394 default: llvm_unreachable("unhandled vld3 type");
1395 case MVT::v8i8: Opc = ARM::VLD3d8; break;
1396 case MVT::v4i16: Opc = ARM::VLD3d16; break;
1398 case MVT::v2i32: Opc = ARM::VLD3d32; break;
1399 case MVT::v1i64: Opc = ARM::VLD3d64; break;
1401 SDValue Chain = N->getOperand(0);
1402 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
1403 return CurDAG->getMachineNode(Opc, dl, VT, VT, VT, MVT::Other, Ops, 4);
1405 // Quad registers are loaded with two separate instructions, where one
1406 // loads the even registers and the other loads the odd registers.
1409 switch (VT.getSimpleVT().SimpleTy) {
1410 default: llvm_unreachable("unhandled vld3 type");
1412 Opc = ARM::VLD3q8a; Opc2 = ARM::VLD3q8b; RegVT = MVT::v8i8; break;
1414 Opc = ARM::VLD3q16a; Opc2 = ARM::VLD3q16b; RegVT = MVT::v4i16; break;
1416 Opc = ARM::VLD3q32a; Opc2 = ARM::VLD3q32b; RegVT = MVT::v2f32; break;
1418 Opc = ARM::VLD3q32a; Opc2 = ARM::VLD3q32b; RegVT = MVT::v2i32; break;
1420 SDValue Chain = N->getOperand(0);
1421 // Enable writeback to the address register.
1422 MemOpc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(true), MVT::i32);
1424 std::vector<EVT> ResTys(3, RegVT);
1425 ResTys.push_back(MemAddr.getValueType());
1426 ResTys.push_back(MVT::Other);
1428 const SDValue OpsA[] = { MemAddr, MemUpdate, MemOpc, Chain };
1429 SDNode *VLdA = CurDAG->getMachineNode(Opc, dl, ResTys, OpsA, 4);
1430 Chain = SDValue(VLdA, 4);
1432 const SDValue OpsB[] = { SDValue(VLdA, 3), MemUpdate, MemOpc, Chain };
1433 SDNode *VLdB = CurDAG->getMachineNode(Opc2, dl, ResTys, OpsB, 4);
1434 Chain = SDValue(VLdB, 4);
1436 SDNode *Q0 = PairDRegs(VT, SDValue(VLdA, 0), SDValue(VLdB, 0));
1437 SDNode *Q1 = PairDRegs(VT, SDValue(VLdA, 1), SDValue(VLdB, 1));
1438 SDNode *Q2 = PairDRegs(VT, SDValue(VLdA, 2), SDValue(VLdB, 2));
1439 ReplaceUses(SDValue(N, 0), SDValue(Q0, 0));
1440 ReplaceUses(SDValue(N, 1), SDValue(Q1, 0));
1441 ReplaceUses(SDValue(N, 2), SDValue(Q2, 0));
1442 ReplaceUses(SDValue(N, 3), Chain);
1446 case Intrinsic::arm_neon_vld4: {
1447 SDValue MemAddr, MemUpdate, MemOpc;
1448 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1450 if (VT.is64BitVector()) {
1451 switch (VT.getSimpleVT().SimpleTy) {
1452 default: llvm_unreachable("unhandled vld4 type");
1453 case MVT::v8i8: Opc = ARM::VLD4d8; break;
1454 case MVT::v4i16: Opc = ARM::VLD4d16; break;
1456 case MVT::v2i32: Opc = ARM::VLD4d32; break;
1458 SDValue Chain = N->getOperand(0);
1459 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
1460 std::vector<EVT> ResTys(4, VT);
1461 ResTys.push_back(MVT::Other);
1462 return CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 4);
1464 // Quad registers are loaded with two separate instructions, where one
1465 // loads the even registers and the other loads the odd registers.
1468 switch (VT.getSimpleVT().SimpleTy) {
1469 default: llvm_unreachable("unhandled vld4 type");
1471 Opc = ARM::VLD4q8a; Opc2 = ARM::VLD4q8b; RegVT = MVT::v8i8; break;
1473 Opc = ARM::VLD4q16a; Opc2 = ARM::VLD4q16b; RegVT = MVT::v4i16; break;
1475 Opc = ARM::VLD4q32a; Opc2 = ARM::VLD4q32b; RegVT = MVT::v2f32; break;
1477 Opc = ARM::VLD4q32a; Opc2 = ARM::VLD4q32b; RegVT = MVT::v2i32; break;
1479 SDValue Chain = N->getOperand(0);
1480 // Enable writeback to the address register.
1481 MemOpc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(true), MVT::i32);
1483 std::vector<EVT> ResTys(4, RegVT);
1484 ResTys.push_back(MemAddr.getValueType());
1485 ResTys.push_back(MVT::Other);
1487 const SDValue OpsA[] = { MemAddr, MemUpdate, MemOpc, Chain };
1488 SDNode *VLdA = CurDAG->getMachineNode(Opc, dl, ResTys, OpsA, 4);
1489 Chain = SDValue(VLdA, 5);
1491 const SDValue OpsB[] = { SDValue(VLdA, 4), MemUpdate, MemOpc, Chain };
1492 SDNode *VLdB = CurDAG->getMachineNode(Opc2, dl, ResTys, OpsB, 4);
1493 Chain = SDValue(VLdB, 5);
1495 SDNode *Q0 = PairDRegs(VT, SDValue(VLdA, 0), SDValue(VLdB, 0));
1496 SDNode *Q1 = PairDRegs(VT, SDValue(VLdA, 1), SDValue(VLdB, 1));
1497 SDNode *Q2 = PairDRegs(VT, SDValue(VLdA, 2), SDValue(VLdB, 2));
1498 SDNode *Q3 = PairDRegs(VT, SDValue(VLdA, 3), SDValue(VLdB, 3));
1499 ReplaceUses(SDValue(N, 0), SDValue(Q0, 0));
1500 ReplaceUses(SDValue(N, 1), SDValue(Q1, 0));
1501 ReplaceUses(SDValue(N, 2), SDValue(Q2, 0));
1502 ReplaceUses(SDValue(N, 3), SDValue(Q3, 0));
1503 ReplaceUses(SDValue(N, 4), Chain);
1507 case Intrinsic::arm_neon_vld2lane: {
1508 SDValue MemAddr, MemUpdate, MemOpc;
1509 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1511 switch (VT.getSimpleVT().SimpleTy) {
1512 default: llvm_unreachable("unhandled vld2lane type");
1513 case MVT::v8i8: Opc = ARM::VLD2LNd8; break;
1514 case MVT::v4i16: Opc = ARM::VLD2LNd16; break;
1516 case MVT::v2i32: Opc = ARM::VLD2LNd32; break;
1518 SDValue Chain = N->getOperand(0);
1519 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1520 N->getOperand(3), N->getOperand(4),
1521 N->getOperand(5), Chain };
1522 return CurDAG->getMachineNode(Opc, dl, VT, VT, MVT::Other, Ops, 7);
1525 case Intrinsic::arm_neon_vld3lane: {
1526 SDValue MemAddr, MemUpdate, MemOpc;
1527 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1529 switch (VT.getSimpleVT().SimpleTy) {
1530 default: llvm_unreachable("unhandled vld3lane type");
1531 case MVT::v8i8: Opc = ARM::VLD3LNd8; break;
1532 case MVT::v4i16: Opc = ARM::VLD3LNd16; break;
1534 case MVT::v2i32: Opc = ARM::VLD3LNd32; break;
1536 SDValue Chain = N->getOperand(0);
1537 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1538 N->getOperand(3), N->getOperand(4),
1539 N->getOperand(5), N->getOperand(6), Chain };
1540 return CurDAG->getMachineNode(Opc, dl, VT, VT, VT, MVT::Other, Ops, 8);
1543 case Intrinsic::arm_neon_vld4lane: {
1544 SDValue MemAddr, MemUpdate, MemOpc;
1545 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1547 switch (VT.getSimpleVT().SimpleTy) {
1548 default: llvm_unreachable("unhandled vld4lane type");
1549 case MVT::v8i8: Opc = ARM::VLD4LNd8; break;
1550 case MVT::v4i16: Opc = ARM::VLD4LNd16; break;
1552 case MVT::v2i32: Opc = ARM::VLD4LNd32; break;
1554 SDValue Chain = N->getOperand(0);
1555 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1556 N->getOperand(3), N->getOperand(4),
1557 N->getOperand(5), N->getOperand(6),
1558 N->getOperand(7), Chain };
1559 std::vector<EVT> ResTys(4, VT);
1560 ResTys.push_back(MVT::Other);
1561 return CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 9);
1564 case Intrinsic::arm_neon_vst2: {
1565 SDValue MemAddr, MemUpdate, MemOpc;
1566 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1568 VT = N->getOperand(3).getValueType();
1569 if (VT.is64BitVector()) {
1570 switch (VT.getSimpleVT().SimpleTy) {
1571 default: llvm_unreachable("unhandled vst2 type");
1572 case MVT::v8i8: Opc = ARM::VST2d8; break;
1573 case MVT::v4i16: Opc = ARM::VST2d16; break;
1575 case MVT::v2i32: Opc = ARM::VST2d32; break;
1577 SDValue Chain = N->getOperand(0);
1578 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1579 N->getOperand(3), N->getOperand(4), Chain };
1580 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 6);
1582 // Quad registers are stored as pairs of double registers.
1584 switch (VT.getSimpleVT().SimpleTy) {
1585 default: llvm_unreachable("unhandled vst2 type");
1586 case MVT::v16i8: Opc = ARM::VST2q8; RegVT = MVT::v8i8; break;
1587 case MVT::v8i16: Opc = ARM::VST2q16; RegVT = MVT::v4i16; break;
1588 case MVT::v4f32: Opc = ARM::VST2q32; RegVT = MVT::v2f32; break;
1589 case MVT::v4i32: Opc = ARM::VST2q32; RegVT = MVT::v2i32; break;
1591 SDValue Chain = N->getOperand(0);
1592 SDValue D0 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
1594 SDValue D1 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
1596 SDValue D2 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
1598 SDValue D3 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
1600 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1601 D0, D1, D2, D3, Chain };
1602 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 8);
1605 case Intrinsic::arm_neon_vst3: {
1606 SDValue MemAddr, MemUpdate, MemOpc;
1607 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1609 VT = N->getOperand(3).getValueType();
1610 if (VT.is64BitVector()) {
1611 switch (VT.getSimpleVT().SimpleTy) {
1612 default: llvm_unreachable("unhandled vst3 type");
1613 case MVT::v8i8: Opc = ARM::VST3d8; break;
1614 case MVT::v4i16: Opc = ARM::VST3d16; break;
1616 case MVT::v2i32: Opc = ARM::VST3d32; break;
1618 SDValue Chain = N->getOperand(0);
1619 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1620 N->getOperand(3), N->getOperand(4),
1621 N->getOperand(5), Chain };
1622 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 7);
1624 // Quad registers are stored with two separate instructions, where one
1625 // stores the even registers and the other stores the odd registers.
1628 switch (VT.getSimpleVT().SimpleTy) {
1629 default: llvm_unreachable("unhandled vst3 type");
1631 Opc = ARM::VST3q8a; Opc2 = ARM::VST3q8b; RegVT = MVT::v8i8; break;
1633 Opc = ARM::VST3q16a; Opc2 = ARM::VST3q16b; RegVT = MVT::v4i16; break;
1635 Opc = ARM::VST3q32a; Opc2 = ARM::VST3q32b; RegVT = MVT::v2f32; break;
1637 Opc = ARM::VST3q32a; Opc2 = ARM::VST3q32b; RegVT = MVT::v2i32; break;
1639 SDValue Chain = N->getOperand(0);
1640 // Enable writeback to the address register.
1641 MemOpc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(true), MVT::i32);
1643 SDValue D0 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
1645 SDValue D2 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
1647 SDValue D4 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
1649 const SDValue OpsA[] = { MemAddr, MemUpdate, MemOpc, D0, D2, D4, Chain };
1650 SDNode *VStA = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
1651 MVT::Other, OpsA, 7);
1652 Chain = SDValue(VStA, 1);
1654 SDValue D1 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
1656 SDValue D3 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
1658 SDValue D5 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
1660 MemAddr = SDValue(VStA, 0);
1661 const SDValue OpsB[] = { MemAddr, MemUpdate, MemOpc, D1, D3, D5, Chain };
1662 SDNode *VStB = CurDAG->getMachineNode(Opc2, dl, MemAddr.getValueType(),
1663 MVT::Other, OpsB, 7);
1664 Chain = SDValue(VStB, 1);
1665 ReplaceUses(SDValue(N, 0), Chain);
1669 case Intrinsic::arm_neon_vst4: {
1670 SDValue MemAddr, MemUpdate, MemOpc;
1671 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1673 VT = N->getOperand(3).getValueType();
1674 if (VT.is64BitVector()) {
1675 switch (VT.getSimpleVT().SimpleTy) {
1676 default: llvm_unreachable("unhandled vst4 type");
1677 case MVT::v8i8: Opc = ARM::VST4d8; break;
1678 case MVT::v4i16: Opc = ARM::VST4d16; break;
1680 case MVT::v2i32: Opc = ARM::VST4d32; break;
1682 SDValue Chain = N->getOperand(0);
1683 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1684 N->getOperand(3), N->getOperand(4),
1685 N->getOperand(5), N->getOperand(6), Chain };
1686 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 8);
1688 // Quad registers are stored with two separate instructions, where one
1689 // stores the even registers and the other stores the odd registers.
1692 switch (VT.getSimpleVT().SimpleTy) {
1693 default: llvm_unreachable("unhandled vst4 type");
1695 Opc = ARM::VST4q8a; Opc2 = ARM::VST4q8b; RegVT = MVT::v8i8; break;
1697 Opc = ARM::VST4q16a; Opc2 = ARM::VST4q16b; RegVT = MVT::v4i16; break;
1699 Opc = ARM::VST4q32a; Opc2 = ARM::VST4q32b; RegVT = MVT::v2f32; break;
1701 Opc = ARM::VST4q32a; Opc2 = ARM::VST4q32b; RegVT = MVT::v2i32; break;
1703 SDValue Chain = N->getOperand(0);
1704 // Enable writeback to the address register.
1705 MemOpc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(true), MVT::i32);
1707 SDValue D0 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
1709 SDValue D2 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
1711 SDValue D4 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
1713 SDValue D6 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
1715 const SDValue OpsA[] = { MemAddr, MemUpdate, MemOpc,
1716 D0, D2, D4, D6, Chain };
1717 SDNode *VStA = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
1718 MVT::Other, OpsA, 8);
1719 Chain = SDValue(VStA, 1);
1721 SDValue D1 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
1723 SDValue D3 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
1725 SDValue D5 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
1727 SDValue D7 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
1729 MemAddr = SDValue(VStA, 0);
1730 const SDValue OpsB[] = { MemAddr, MemUpdate, MemOpc,
1731 D1, D3, D5, D7, Chain };
1732 SDNode *VStB = CurDAG->getMachineNode(Opc2, dl, MemAddr.getValueType(),
1733 MVT::Other, OpsB, 8);
1734 Chain = SDValue(VStB, 1);
1735 ReplaceUses(SDValue(N, 0), Chain);
1739 case Intrinsic::arm_neon_vst2lane: {
1740 SDValue MemAddr, MemUpdate, MemOpc;
1741 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1743 switch (N->getOperand(3).getValueType().getSimpleVT().SimpleTy) {
1744 default: llvm_unreachable("unhandled vst2lane type");
1745 case MVT::v8i8: Opc = ARM::VST2LNd8; break;
1746 case MVT::v4i16: Opc = ARM::VST2LNd16; break;
1748 case MVT::v2i32: Opc = ARM::VST2LNd32; break;
1750 SDValue Chain = N->getOperand(0);
1751 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1752 N->getOperand(3), N->getOperand(4),
1753 N->getOperand(5), Chain };
1754 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 7);
1757 case Intrinsic::arm_neon_vst3lane: {
1758 SDValue MemAddr, MemUpdate, MemOpc;
1759 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1761 switch (N->getOperand(3).getValueType().getSimpleVT().SimpleTy) {
1762 default: llvm_unreachable("unhandled vst3lane type");
1763 case MVT::v8i8: Opc = ARM::VST3LNd8; break;
1764 case MVT::v4i16: Opc = ARM::VST3LNd16; break;
1766 case MVT::v2i32: Opc = ARM::VST3LNd32; break;
1768 SDValue Chain = N->getOperand(0);
1769 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1770 N->getOperand(3), N->getOperand(4),
1771 N->getOperand(5), N->getOperand(6), Chain };
1772 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 8);
1775 case Intrinsic::arm_neon_vst4lane: {
1776 SDValue MemAddr, MemUpdate, MemOpc;
1777 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1779 switch (N->getOperand(3).getValueType().getSimpleVT().SimpleTy) {
1780 default: llvm_unreachable("unhandled vst4lane type");
1781 case MVT::v8i8: Opc = ARM::VST4LNd8; break;
1782 case MVT::v4i16: Opc = ARM::VST4LNd16; break;
1784 case MVT::v2i32: Opc = ARM::VST4LNd32; break;
1786 SDValue Chain = N->getOperand(0);
1787 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1788 N->getOperand(3), N->getOperand(4),
1789 N->getOperand(5), N->getOperand(6),
1790 N->getOperand(7), Chain };
1791 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 9);
1797 return SelectCode(Op);
1800 bool ARMDAGToDAGISel::
1801 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
1802 std::vector<SDValue> &OutOps) {
1803 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
1805 SDValue Base, Offset, Opc;
1806 if (!SelectAddrMode2(Op, Op, Base, Offset, Opc))
1809 OutOps.push_back(Base);
1810 OutOps.push_back(Offset);
1811 OutOps.push_back(Opc);
1815 /// createARMISelDag - This pass converts a legalized DAG into a
1816 /// ARM-specific DAG, ready for instruction scheduling.
1818 FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
1819 CodeGenOpt::Level OptLevel) {
1820 return new ARMDAGToDAGISel(TM, OptLevel);