1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "arm-isel"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMTargetMachine.h"
18 #include "MCTargetDesc/ARMAddressingModes.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/Constants.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/Intrinsics.h"
24 #include "llvm/LLVMContext.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/SelectionDAGISel.h"
30 #include "llvm/Target/TargetLowering.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Compiler.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/raw_ostream.h"
41 DisableShifterOp("disable-shifter-op", cl::Hidden,
42 cl::desc("Disable isel of shifter-op"),
46 CheckVMLxHazard("check-vmlx-hazard", cl::Hidden,
47 cl::desc("Check fp vmla / vmls hazard at isel time"),
50 //===--------------------------------------------------------------------===//
51 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
52 /// instructions for SelectionDAG operations.
57 AM2_BASE, // Simple AM2 (+-imm12)
58 AM2_SHOP // Shifter-op AM2
61 class ARMDAGToDAGISel : public SelectionDAGISel {
62 ARMBaseTargetMachine &TM;
63 const ARMBaseInstrInfo *TII;
65 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
66 /// make the right decision when generating code for different targets.
67 const ARMSubtarget *Subtarget;
70 explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm,
71 CodeGenOpt::Level OptLevel)
72 : SelectionDAGISel(tm, OptLevel), TM(tm),
73 TII(static_cast<const ARMBaseInstrInfo*>(TM.getInstrInfo())),
74 Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
77 virtual const char *getPassName() const {
78 return "ARM Instruction Selection";
81 /// getI32Imm - Return a target constant of type i32 with the specified
83 inline SDValue getI32Imm(unsigned Imm) {
84 return CurDAG->getTargetConstant(Imm, MVT::i32);
87 SDNode *Select(SDNode *N);
90 bool hasNoVMLxHazardUse(SDNode *N) const;
91 bool isShifterOpProfitable(const SDValue &Shift,
92 ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
93 bool SelectRegShifterOperand(SDValue N, SDValue &A,
94 SDValue &B, SDValue &C,
95 bool CheckProfitability = true);
96 bool SelectImmShifterOperand(SDValue N, SDValue &A,
97 SDValue &B, bool CheckProfitability = true);
98 bool SelectShiftRegShifterOperand(SDValue N, SDValue &A,
99 SDValue &B, SDValue &C) {
100 // Don't apply the profitability check
101 return SelectRegShifterOperand(N, A, B, C, false);
103 bool SelectShiftImmShifterOperand(SDValue N, SDValue &A,
105 // Don't apply the profitability check
106 return SelectImmShifterOperand(N, A, B, false);
109 bool SelectAddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
110 bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc);
112 AddrMode2Type SelectAddrMode2Worker(SDValue N, SDValue &Base,
113 SDValue &Offset, SDValue &Opc);
114 bool SelectAddrMode2Base(SDValue N, SDValue &Base, SDValue &Offset,
116 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_BASE;
119 bool SelectAddrMode2ShOp(SDValue N, SDValue &Base, SDValue &Offset,
121 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_SHOP;
124 bool SelectAddrMode2(SDValue N, SDValue &Base, SDValue &Offset,
126 SelectAddrMode2Worker(N, Base, Offset, Opc);
127 // return SelectAddrMode2ShOp(N, Base, Offset, Opc);
128 // This always matches one way or another.
132 bool SelectAddrMode2OffsetReg(SDNode *Op, SDValue N,
133 SDValue &Offset, SDValue &Opc);
134 bool SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
135 SDValue &Offset, SDValue &Opc);
136 bool SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N,
137 SDValue &Offset, SDValue &Opc);
138 bool SelectAddrOffsetNone(SDValue N, SDValue &Base);
139 bool SelectAddrMode3(SDValue N, SDValue &Base,
140 SDValue &Offset, SDValue &Opc);
141 bool SelectAddrMode3Offset(SDNode *Op, SDValue N,
142 SDValue &Offset, SDValue &Opc);
143 bool SelectAddrMode5(SDValue N, SDValue &Base,
145 bool SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,SDValue &Align);
146 bool SelectAddrMode6Offset(SDNode *Op, SDValue N, SDValue &Offset);
148 bool SelectAddrModePC(SDValue N, SDValue &Offset, SDValue &Label);
150 // Thumb Addressing Modes:
151 bool SelectThumbAddrModeRR(SDValue N, SDValue &Base, SDValue &Offset);
152 bool SelectThumbAddrModeRI(SDValue N, SDValue &Base, SDValue &Offset,
154 bool SelectThumbAddrModeRI5S1(SDValue N, SDValue &Base, SDValue &Offset);
155 bool SelectThumbAddrModeRI5S2(SDValue N, SDValue &Base, SDValue &Offset);
156 bool SelectThumbAddrModeRI5S4(SDValue N, SDValue &Base, SDValue &Offset);
157 bool SelectThumbAddrModeImm5S(SDValue N, unsigned Scale, SDValue &Base,
159 bool SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
161 bool SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
163 bool SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
165 bool SelectThumbAddrModeSP(SDValue N, SDValue &Base, SDValue &OffImm);
167 // Thumb 2 Addressing Modes:
168 bool SelectT2ShifterOperandReg(SDValue N,
169 SDValue &BaseReg, SDValue &Opc);
170 bool SelectT2AddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
171 bool SelectT2AddrModeImm8(SDValue N, SDValue &Base,
173 bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
175 bool SelectT2AddrModeSoReg(SDValue N, SDValue &Base,
176 SDValue &OffReg, SDValue &ShImm);
178 inline bool is_so_imm(unsigned Imm) const {
179 return ARM_AM::getSOImmVal(Imm) != -1;
182 inline bool is_so_imm_not(unsigned Imm) const {
183 return ARM_AM::getSOImmVal(~Imm) != -1;
186 inline bool is_t2_so_imm(unsigned Imm) const {
187 return ARM_AM::getT2SOImmVal(Imm) != -1;
190 inline bool is_t2_so_imm_not(unsigned Imm) const {
191 return ARM_AM::getT2SOImmVal(~Imm) != -1;
194 // Include the pieces autogenerated from the target description.
195 #include "ARMGenDAGISel.inc"
198 /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
200 SDNode *SelectARMIndexedLoad(SDNode *N);
201 SDNode *SelectT2IndexedLoad(SDNode *N);
203 /// SelectVLD - Select NEON load intrinsics. NumVecs should be
204 /// 1, 2, 3 or 4. The opcode arrays specify the instructions used for
205 /// loads of D registers and even subregs and odd subregs of Q registers.
206 /// For NumVecs <= 2, QOpcodes1 is not used.
207 SDNode *SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
209 unsigned *QOpcodes0, unsigned *QOpcodes1);
211 /// SelectVST - Select NEON store intrinsics. NumVecs should
212 /// be 1, 2, 3 or 4. The opcode arrays specify the instructions used for
213 /// stores of D registers and even subregs and odd subregs of Q registers.
214 /// For NumVecs <= 2, QOpcodes1 is not used.
215 SDNode *SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
217 unsigned *QOpcodes0, unsigned *QOpcodes1);
219 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should
220 /// be 2, 3 or 4. The opcode arrays specify the instructions used for
221 /// load/store of D registers and Q registers.
222 SDNode *SelectVLDSTLane(SDNode *N, bool IsLoad,
223 bool isUpdating, unsigned NumVecs,
224 unsigned *DOpcodes, unsigned *QOpcodes);
226 /// SelectVLDDup - Select NEON load-duplicate intrinsics. NumVecs
227 /// should be 2, 3 or 4. The opcode array specifies the instructions used
228 /// for loading D registers. (Q registers are not supported.)
229 SDNode *SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs,
232 /// SelectVTBL - Select NEON VTBL and VTBX intrinsics. NumVecs should be 2,
233 /// 3 or 4. These are custom-selected so that a REG_SEQUENCE can be
234 /// generated to force the table registers to be consecutive.
235 SDNode *SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc);
237 /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM.
238 SDNode *SelectV6T2BitfieldExtractOp(SDNode *N, bool isSigned);
240 /// SelectCMOVOp - Select CMOV instructions for ARM.
241 SDNode *SelectCMOVOp(SDNode *N);
242 SDNode *SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
243 ARMCC::CondCodes CCVal, SDValue CCR,
245 SDNode *SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
246 ARMCC::CondCodes CCVal, SDValue CCR,
248 SDNode *SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
249 ARMCC::CondCodes CCVal, SDValue CCR,
251 SDNode *SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
252 ARMCC::CondCodes CCVal, SDValue CCR,
255 SDNode *SelectConcatVector(SDNode *N);
257 SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
259 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
260 /// inline asm expressions.
261 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
263 std::vector<SDValue> &OutOps);
265 // Form pairs of consecutive S, D, or Q registers.
266 SDNode *PairSRegs(EVT VT, SDValue V0, SDValue V1);
267 SDNode *PairDRegs(EVT VT, SDValue V0, SDValue V1);
268 SDNode *PairQRegs(EVT VT, SDValue V0, SDValue V1);
270 // Form sequences of 4 consecutive S, D, or Q registers.
271 SDNode *QuadSRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
272 SDNode *QuadDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
273 SDNode *QuadQRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
275 // Get the alignment operand for a NEON VLD or VST instruction.
276 SDValue GetVLDSTAlign(SDValue Align, unsigned NumVecs, bool is64BitVector);
280 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
281 /// operand. If so Imm will receive the 32-bit value.
282 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
283 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
284 Imm = cast<ConstantSDNode>(N)->getZExtValue();
290 // isInt32Immediate - This method tests to see if a constant operand.
291 // If so Imm will receive the 32 bit value.
292 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
293 return isInt32Immediate(N.getNode(), Imm);
296 // isOpcWithIntImmediate - This method tests to see if the node is a specific
297 // opcode and that it has a immediate integer right operand.
298 // If so Imm will receive the 32 bit value.
299 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
300 return N->getOpcode() == Opc &&
301 isInt32Immediate(N->getOperand(1).getNode(), Imm);
304 /// \brief Check whether a particular node is a constant value representable as
305 /// (N * Scale) where (N in [\arg RangeMin, \arg RangeMax).
307 /// \param ScaledConstant [out] - On success, the pre-scaled constant value.
308 static bool isScaledConstantInRange(SDValue Node, unsigned Scale,
309 int RangeMin, int RangeMax,
310 int &ScaledConstant) {
311 assert(Scale && "Invalid scale!");
313 // Check that this is a constant.
314 const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Node);
318 ScaledConstant = (int) C->getZExtValue();
319 if ((ScaledConstant % Scale) != 0)
322 ScaledConstant /= Scale;
323 return ScaledConstant >= RangeMin && ScaledConstant < RangeMax;
326 /// hasNoVMLxHazardUse - Return true if it's desirable to select a FP MLA / MLS
327 /// node. VFP / NEON fp VMLA / VMLS instructions have special RAW hazards (at
328 /// least on current ARM implementations) which should be avoidded.
329 bool ARMDAGToDAGISel::hasNoVMLxHazardUse(SDNode *N) const {
330 if (OptLevel == CodeGenOpt::None)
333 if (!CheckVMLxHazard)
336 if (!Subtarget->isCortexA8() && !Subtarget->isCortexA9())
342 SDNode *Use = *N->use_begin();
343 if (Use->getOpcode() == ISD::CopyToReg)
345 if (Use->isMachineOpcode()) {
346 const MCInstrDesc &MCID = TII->get(Use->getMachineOpcode());
349 unsigned Opcode = MCID.getOpcode();
350 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
352 // vmlx feeding into another vmlx. We actually want to unfold
353 // the use later in the MLxExpansion pass. e.g.
355 // vmla (stall 8 cycles)
360 // This adds up to about 18 - 19 cycles.
363 // vmul (stall 4 cycles)
364 // vadd adds up to about 14 cycles.
365 return TII->isFpMLxInstruction(Opcode);
371 bool ARMDAGToDAGISel::isShifterOpProfitable(const SDValue &Shift,
372 ARM_AM::ShiftOpc ShOpcVal,
374 if (!Subtarget->isCortexA9())
376 if (Shift.hasOneUse())
379 return ShOpcVal == ARM_AM::lsl && ShAmt == 2;
382 bool ARMDAGToDAGISel::SelectImmShifterOperand(SDValue N,
385 bool CheckProfitability) {
386 if (DisableShifterOp)
389 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
391 // Don't match base register only case. That is matched to a separate
392 // lower complexity pattern with explicit register operand.
393 if (ShOpcVal == ARM_AM::no_shift) return false;
395 BaseReg = N.getOperand(0);
396 unsigned ShImmVal = 0;
397 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
398 if (!RHS) return false;
399 ShImmVal = RHS->getZExtValue() & 31;
400 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
405 bool ARMDAGToDAGISel::SelectRegShifterOperand(SDValue N,
409 bool CheckProfitability) {
410 if (DisableShifterOp)
413 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
415 // Don't match base register only case. That is matched to a separate
416 // lower complexity pattern with explicit register operand.
417 if (ShOpcVal == ARM_AM::no_shift) return false;
419 BaseReg = N.getOperand(0);
420 unsigned ShImmVal = 0;
421 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
422 if (RHS) return false;
424 ShReg = N.getOperand(1);
425 if (CheckProfitability && !isShifterOpProfitable(N, ShOpcVal, ShImmVal))
427 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
433 bool ARMDAGToDAGISel::SelectAddrModeImm12(SDValue N,
436 // Match simple R + imm12 operands.
439 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
440 !CurDAG->isBaseWithConstantOffset(N)) {
441 if (N.getOpcode() == ISD::FrameIndex) {
442 // Match frame index.
443 int FI = cast<FrameIndexSDNode>(N)->getIndex();
444 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
445 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
449 if (N.getOpcode() == ARMISD::Wrapper &&
450 !(Subtarget->useMovt() &&
451 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
452 Base = N.getOperand(0);
455 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
459 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
460 int RHSC = (int)RHS->getZExtValue();
461 if (N.getOpcode() == ISD::SUB)
464 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
465 Base = N.getOperand(0);
466 if (Base.getOpcode() == ISD::FrameIndex) {
467 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
468 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
470 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
477 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
483 bool ARMDAGToDAGISel::SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset,
485 if (N.getOpcode() == ISD::MUL &&
486 (!Subtarget->isCortexA9() || N.hasOneUse())) {
487 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
488 // X * [3,5,9] -> X + X * [2,4,8] etc.
489 int RHSC = (int)RHS->getZExtValue();
492 ARM_AM::AddrOpc AddSub = ARM_AM::add;
494 AddSub = ARM_AM::sub;
497 if (isPowerOf2_32(RHSC)) {
498 unsigned ShAmt = Log2_32(RHSC);
499 Base = Offset = N.getOperand(0);
500 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
509 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
510 // ISD::OR that is equivalent to an ISD::ADD.
511 !CurDAG->isBaseWithConstantOffset(N))
514 // Leave simple R +/- imm12 operands for LDRi12
515 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR) {
517 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
518 -0x1000+1, 0x1000, RHSC)) // 12 bits.
522 if (Subtarget->isCortexA9() && !N.hasOneUse())
523 // Compute R +/- (R << N) and reuse it.
526 // Otherwise this is R +/- [possibly shifted] R.
527 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::SUB ? ARM_AM::sub:ARM_AM::add;
528 ARM_AM::ShiftOpc ShOpcVal =
529 ARM_AM::getShiftOpcForNode(N.getOperand(1).getOpcode());
532 Base = N.getOperand(0);
533 Offset = N.getOperand(1);
535 if (ShOpcVal != ARM_AM::no_shift) {
536 // Check to see if the RHS of the shift is a constant, if not, we can't fold
538 if (ConstantSDNode *Sh =
539 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
540 ShAmt = Sh->getZExtValue();
541 if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
542 Offset = N.getOperand(1).getOperand(0);
545 ShOpcVal = ARM_AM::no_shift;
548 ShOpcVal = ARM_AM::no_shift;
552 // Try matching (R shl C) + (R).
553 if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
554 !(Subtarget->isCortexA9() || N.getOperand(0).hasOneUse())) {
555 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0).getOpcode());
556 if (ShOpcVal != ARM_AM::no_shift) {
557 // Check to see if the RHS of the shift is a constant, if not, we can't
559 if (ConstantSDNode *Sh =
560 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
561 ShAmt = Sh->getZExtValue();
562 if (!Subtarget->isCortexA9() ||
564 isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt))) {
565 Offset = N.getOperand(0).getOperand(0);
566 Base = N.getOperand(1);
569 ShOpcVal = ARM_AM::no_shift;
572 ShOpcVal = ARM_AM::no_shift;
577 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
587 AddrMode2Type ARMDAGToDAGISel::SelectAddrMode2Worker(SDValue N,
591 if (N.getOpcode() == ISD::MUL &&
592 (!Subtarget->isCortexA9() || N.hasOneUse())) {
593 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
594 // X * [3,5,9] -> X + X * [2,4,8] etc.
595 int RHSC = (int)RHS->getZExtValue();
598 ARM_AM::AddrOpc AddSub = ARM_AM::add;
600 AddSub = ARM_AM::sub;
603 if (isPowerOf2_32(RHSC)) {
604 unsigned ShAmt = Log2_32(RHSC);
605 Base = Offset = N.getOperand(0);
606 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
615 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
616 // ISD::OR that is equivalent to an ADD.
617 !CurDAG->isBaseWithConstantOffset(N)) {
619 if (N.getOpcode() == ISD::FrameIndex) {
620 int FI = cast<FrameIndexSDNode>(N)->getIndex();
621 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
622 } else if (N.getOpcode() == ARMISD::Wrapper &&
623 !(Subtarget->useMovt() &&
624 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
625 Base = N.getOperand(0);
627 Offset = CurDAG->getRegister(0, MVT::i32);
628 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
634 // Match simple R +/- imm12 operands.
635 if (N.getOpcode() != ISD::SUB) {
637 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
638 -0x1000+1, 0x1000, RHSC)) { // 12 bits.
639 Base = N.getOperand(0);
640 if (Base.getOpcode() == ISD::FrameIndex) {
641 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
642 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
644 Offset = CurDAG->getRegister(0, MVT::i32);
646 ARM_AM::AddrOpc AddSub = ARM_AM::add;
648 AddSub = ARM_AM::sub;
651 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
658 if (Subtarget->isCortexA9() && !N.hasOneUse()) {
659 // Compute R +/- (R << N) and reuse it.
661 Offset = CurDAG->getRegister(0, MVT::i32);
662 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
668 // Otherwise this is R +/- [possibly shifted] R.
669 ARM_AM::AddrOpc AddSub = N.getOpcode() != ISD::SUB ? ARM_AM::add:ARM_AM::sub;
670 ARM_AM::ShiftOpc ShOpcVal =
671 ARM_AM::getShiftOpcForNode(N.getOperand(1).getOpcode());
674 Base = N.getOperand(0);
675 Offset = N.getOperand(1);
677 if (ShOpcVal != ARM_AM::no_shift) {
678 // Check to see if the RHS of the shift is a constant, if not, we can't fold
680 if (ConstantSDNode *Sh =
681 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
682 ShAmt = Sh->getZExtValue();
683 if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
684 Offset = N.getOperand(1).getOperand(0);
687 ShOpcVal = ARM_AM::no_shift;
690 ShOpcVal = ARM_AM::no_shift;
694 // Try matching (R shl C) + (R).
695 if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
696 !(Subtarget->isCortexA9() || N.getOperand(0).hasOneUse())) {
697 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0).getOpcode());
698 if (ShOpcVal != ARM_AM::no_shift) {
699 // Check to see if the RHS of the shift is a constant, if not, we can't
701 if (ConstantSDNode *Sh =
702 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
703 ShAmt = Sh->getZExtValue();
704 if (!Subtarget->isCortexA9() ||
706 isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt))) {
707 Offset = N.getOperand(0).getOperand(0);
708 Base = N.getOperand(1);
711 ShOpcVal = ARM_AM::no_shift;
714 ShOpcVal = ARM_AM::no_shift;
719 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
724 bool ARMDAGToDAGISel::SelectAddrMode2OffsetReg(SDNode *Op, SDValue N,
725 SDValue &Offset, SDValue &Opc) {
726 unsigned Opcode = Op->getOpcode();
727 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
728 ? cast<LoadSDNode>(Op)->getAddressingMode()
729 : cast<StoreSDNode>(Op)->getAddressingMode();
730 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
731 ? ARM_AM::add : ARM_AM::sub;
733 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val))
737 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
739 if (ShOpcVal != ARM_AM::no_shift) {
740 // Check to see if the RHS of the shift is a constant, if not, we can't fold
742 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
743 ShAmt = Sh->getZExtValue();
744 if (isShifterOpProfitable(N, ShOpcVal, ShAmt))
745 Offset = N.getOperand(0);
748 ShOpcVal = ARM_AM::no_shift;
751 ShOpcVal = ARM_AM::no_shift;
755 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
760 bool ARMDAGToDAGISel::SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N,
761 SDValue &Offset, SDValue &Opc) {
762 unsigned Opcode = Op->getOpcode();
763 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
764 ? cast<LoadSDNode>(Op)->getAddressingMode()
765 : cast<StoreSDNode>(Op)->getAddressingMode();
766 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
767 ? ARM_AM::add : ARM_AM::sub;
769 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits.
770 if (AddSub == ARM_AM::sub) Val *= -1;
771 Offset = CurDAG->getRegister(0, MVT::i32);
772 Opc = CurDAG->getTargetConstant(Val, MVT::i32);
780 bool ARMDAGToDAGISel::SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
781 SDValue &Offset, SDValue &Opc) {
782 unsigned Opcode = Op->getOpcode();
783 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
784 ? cast<LoadSDNode>(Op)->getAddressingMode()
785 : cast<StoreSDNode>(Op)->getAddressingMode();
786 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
787 ? ARM_AM::add : ARM_AM::sub;
789 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits.
790 Offset = CurDAG->getRegister(0, MVT::i32);
791 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
800 bool ARMDAGToDAGISel::SelectAddrOffsetNone(SDValue N, SDValue &Base) {
805 bool ARMDAGToDAGISel::SelectAddrMode3(SDValue N,
806 SDValue &Base, SDValue &Offset,
808 if (N.getOpcode() == ISD::SUB) {
809 // X - C is canonicalize to X + -C, no need to handle it here.
810 Base = N.getOperand(0);
811 Offset = N.getOperand(1);
812 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
816 if (!CurDAG->isBaseWithConstantOffset(N)) {
818 if (N.getOpcode() == ISD::FrameIndex) {
819 int FI = cast<FrameIndexSDNode>(N)->getIndex();
820 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
822 Offset = CurDAG->getRegister(0, MVT::i32);
823 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
827 // If the RHS is +/- imm8, fold into addr mode.
829 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
830 -256 + 1, 256, RHSC)) { // 8 bits.
831 Base = N.getOperand(0);
832 if (Base.getOpcode() == ISD::FrameIndex) {
833 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
834 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
836 Offset = CurDAG->getRegister(0, MVT::i32);
838 ARM_AM::AddrOpc AddSub = ARM_AM::add;
840 AddSub = ARM_AM::sub;
843 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
847 Base = N.getOperand(0);
848 Offset = N.getOperand(1);
849 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
853 bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N,
854 SDValue &Offset, SDValue &Opc) {
855 unsigned Opcode = Op->getOpcode();
856 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
857 ? cast<LoadSDNode>(Op)->getAddressingMode()
858 : cast<StoreSDNode>(Op)->getAddressingMode();
859 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
860 ? ARM_AM::add : ARM_AM::sub;
862 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 256, Val)) { // 12 bits.
863 Offset = CurDAG->getRegister(0, MVT::i32);
864 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
869 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
873 bool ARMDAGToDAGISel::SelectAddrMode5(SDValue N,
874 SDValue &Base, SDValue &Offset) {
875 if (!CurDAG->isBaseWithConstantOffset(N)) {
877 if (N.getOpcode() == ISD::FrameIndex) {
878 int FI = cast<FrameIndexSDNode>(N)->getIndex();
879 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
880 } else if (N.getOpcode() == ARMISD::Wrapper &&
881 !(Subtarget->useMovt() &&
882 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
883 Base = N.getOperand(0);
885 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
890 // If the RHS is +/- imm8, fold into addr mode.
892 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/4,
893 -256 + 1, 256, RHSC)) {
894 Base = N.getOperand(0);
895 if (Base.getOpcode() == ISD::FrameIndex) {
896 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
897 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
900 ARM_AM::AddrOpc AddSub = ARM_AM::add;
902 AddSub = ARM_AM::sub;
905 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
911 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
916 bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,
920 unsigned Alignment = 0;
921 if (LSBaseSDNode *LSN = dyn_cast<LSBaseSDNode>(Parent)) {
922 // This case occurs only for VLD1-lane/dup and VST1-lane instructions.
923 // The maximum alignment is equal to the memory size being referenced.
924 unsigned LSNAlign = LSN->getAlignment();
925 unsigned MemSize = LSN->getMemoryVT().getSizeInBits() / 8;
926 if (LSNAlign > MemSize && MemSize > 1)
929 // All other uses of addrmode6 are for intrinsics. For now just record
930 // the raw alignment value; it will be refined later based on the legal
931 // alignment operands for the intrinsic.
932 Alignment = cast<MemIntrinsicSDNode>(Parent)->getAlignment();
935 Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
939 bool ARMDAGToDAGISel::SelectAddrMode6Offset(SDNode *Op, SDValue N,
941 LSBaseSDNode *LdSt = cast<LSBaseSDNode>(Op);
942 ISD::MemIndexedMode AM = LdSt->getAddressingMode();
943 if (AM != ISD::POST_INC)
946 if (ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N)) {
947 if (NC->getZExtValue() * 8 == LdSt->getMemoryVT().getSizeInBits())
948 Offset = CurDAG->getRegister(0, MVT::i32);
953 bool ARMDAGToDAGISel::SelectAddrModePC(SDValue N,
954 SDValue &Offset, SDValue &Label) {
955 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
956 Offset = N.getOperand(0);
957 SDValue N1 = N.getOperand(1);
958 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
967 //===----------------------------------------------------------------------===//
968 // Thumb Addressing Modes
969 //===----------------------------------------------------------------------===//
971 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue N,
972 SDValue &Base, SDValue &Offset){
973 if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N)) {
974 ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
975 if (!NC || !NC->isNullValue())
982 Base = N.getOperand(0);
983 Offset = N.getOperand(1);
988 ARMDAGToDAGISel::SelectThumbAddrModeRI(SDValue N, SDValue &Base,
989 SDValue &Offset, unsigned Scale) {
991 SDValue TmpBase, TmpOffImm;
992 if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
993 return false; // We want to select tLDRspi / tSTRspi instead.
995 if (N.getOpcode() == ARMISD::Wrapper &&
996 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
997 return false; // We want to select tLDRpci instead.
1000 if (!CurDAG->isBaseWithConstantOffset(N))
1003 // Thumb does not have [sp, r] address mode.
1004 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1005 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
1006 if ((LHSR && LHSR->getReg() == ARM::SP) ||
1007 (RHSR && RHSR->getReg() == ARM::SP))
1010 // FIXME: Why do we explicitly check for a match here and then return false?
1011 // Presumably to allow something else to match, but shouldn't this be
1014 if (isScaledConstantInRange(N.getOperand(1), Scale, 0, 32, RHSC))
1017 Base = N.getOperand(0);
1018 Offset = N.getOperand(1);
1023 ARMDAGToDAGISel::SelectThumbAddrModeRI5S1(SDValue N,
1026 return SelectThumbAddrModeRI(N, Base, Offset, 1);
1030 ARMDAGToDAGISel::SelectThumbAddrModeRI5S2(SDValue N,
1033 return SelectThumbAddrModeRI(N, Base, Offset, 2);
1037 ARMDAGToDAGISel::SelectThumbAddrModeRI5S4(SDValue N,
1040 return SelectThumbAddrModeRI(N, Base, Offset, 4);
1044 ARMDAGToDAGISel::SelectThumbAddrModeImm5S(SDValue N, unsigned Scale,
1045 SDValue &Base, SDValue &OffImm) {
1047 SDValue TmpBase, TmpOffImm;
1048 if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
1049 return false; // We want to select tLDRspi / tSTRspi instead.
1051 if (N.getOpcode() == ARMISD::Wrapper &&
1052 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
1053 return false; // We want to select tLDRpci instead.
1056 if (!CurDAG->isBaseWithConstantOffset(N)) {
1057 if (N.getOpcode() == ARMISD::Wrapper &&
1058 !(Subtarget->useMovt() &&
1059 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
1060 Base = N.getOperand(0);
1065 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1069 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1070 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
1071 if ((LHSR && LHSR->getReg() == ARM::SP) ||
1072 (RHSR && RHSR->getReg() == ARM::SP)) {
1073 ConstantSDNode *LHS = dyn_cast<ConstantSDNode>(N.getOperand(0));
1074 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
1075 unsigned LHSC = LHS ? LHS->getZExtValue() : 0;
1076 unsigned RHSC = RHS ? RHS->getZExtValue() : 0;
1078 // Thumb does not have [sp, #imm5] address mode for non-zero imm5.
1079 if (LHSC != 0 || RHSC != 0) return false;
1082 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1086 // If the RHS is + imm5 * scale, fold into addr mode.
1088 if (isScaledConstantInRange(N.getOperand(1), Scale, 0, 32, RHSC)) {
1089 Base = N.getOperand(0);
1090 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1094 Base = N.getOperand(0);
1095 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1100 ARMDAGToDAGISel::SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
1102 return SelectThumbAddrModeImm5S(N, 4, Base, OffImm);
1106 ARMDAGToDAGISel::SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
1108 return SelectThumbAddrModeImm5S(N, 2, Base, OffImm);
1112 ARMDAGToDAGISel::SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
1114 return SelectThumbAddrModeImm5S(N, 1, Base, OffImm);
1117 bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue N,
1118 SDValue &Base, SDValue &OffImm) {
1119 if (N.getOpcode() == ISD::FrameIndex) {
1120 int FI = cast<FrameIndexSDNode>(N)->getIndex();
1121 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1122 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1126 if (!CurDAG->isBaseWithConstantOffset(N))
1129 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1130 if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
1131 (LHSR && LHSR->getReg() == ARM::SP)) {
1132 // If the RHS is + imm8 * scale, fold into addr mode.
1134 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/4, 0, 256, RHSC)) {
1135 Base = N.getOperand(0);
1136 if (Base.getOpcode() == ISD::FrameIndex) {
1137 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1138 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1140 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1149 //===----------------------------------------------------------------------===//
1150 // Thumb 2 Addressing Modes
1151 //===----------------------------------------------------------------------===//
1154 bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue N, SDValue &BaseReg,
1156 if (DisableShifterOp)
1159 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
1161 // Don't match base register only case. That is matched to a separate
1162 // lower complexity pattern with explicit register operand.
1163 if (ShOpcVal == ARM_AM::no_shift) return false;
1165 BaseReg = N.getOperand(0);
1166 unsigned ShImmVal = 0;
1167 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1168 ShImmVal = RHS->getZExtValue() & 31;
1169 Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
1176 bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue N,
1177 SDValue &Base, SDValue &OffImm) {
1178 // Match simple R + imm12 operands.
1181 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1182 !CurDAG->isBaseWithConstantOffset(N)) {
1183 if (N.getOpcode() == ISD::FrameIndex) {
1184 // Match frame index.
1185 int FI = cast<FrameIndexSDNode>(N)->getIndex();
1186 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1187 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1191 if (N.getOpcode() == ARMISD::Wrapper &&
1192 !(Subtarget->useMovt() &&
1193 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
1194 Base = N.getOperand(0);
1195 if (Base.getOpcode() == ISD::TargetConstantPool)
1196 return false; // We want to select t2LDRpci instead.
1199 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1203 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1204 if (SelectT2AddrModeImm8(N, Base, OffImm))
1205 // Let t2LDRi8 handle (R - imm8).
1208 int RHSC = (int)RHS->getZExtValue();
1209 if (N.getOpcode() == ISD::SUB)
1212 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
1213 Base = N.getOperand(0);
1214 if (Base.getOpcode() == ISD::FrameIndex) {
1215 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1216 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1218 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1225 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1229 bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue N,
1230 SDValue &Base, SDValue &OffImm) {
1231 // Match simple R - imm8 operands.
1232 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1233 !CurDAG->isBaseWithConstantOffset(N))
1236 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1237 int RHSC = (int)RHS->getSExtValue();
1238 if (N.getOpcode() == ISD::SUB)
1241 if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative)
1242 Base = N.getOperand(0);
1243 if (Base.getOpcode() == ISD::FrameIndex) {
1244 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1245 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1247 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1255 bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
1257 unsigned Opcode = Op->getOpcode();
1258 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
1259 ? cast<LoadSDNode>(Op)->getAddressingMode()
1260 : cast<StoreSDNode>(Op)->getAddressingMode();
1262 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x100, RHSC)) { // 8 bits.
1263 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
1264 ? CurDAG->getTargetConstant(RHSC, MVT::i32)
1265 : CurDAG->getTargetConstant(-RHSC, MVT::i32);
1272 bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue N,
1274 SDValue &OffReg, SDValue &ShImm) {
1275 // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.
1276 if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N))
1279 // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8.
1280 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1281 int RHSC = (int)RHS->getZExtValue();
1282 if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned)
1284 else if (RHSC < 0 && RHSC >= -255) // 8 bits
1288 if (Subtarget->isCortexA9() && !N.hasOneUse()) {
1289 // Compute R + (R << [1,2,3]) and reuse it.
1294 // Look for (R + R) or (R + (R << [1,2,3])).
1296 Base = N.getOperand(0);
1297 OffReg = N.getOperand(1);
1299 // Swap if it is ((R << c) + R).
1300 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode());
1301 if (ShOpcVal != ARM_AM::lsl) {
1302 ShOpcVal = ARM_AM::getShiftOpcForNode(Base.getOpcode());
1303 if (ShOpcVal == ARM_AM::lsl)
1304 std::swap(Base, OffReg);
1307 if (ShOpcVal == ARM_AM::lsl) {
1308 // Check to see if the RHS of the shift is a constant, if not, we can't fold
1310 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
1311 ShAmt = Sh->getZExtValue();
1312 if (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt))
1313 OffReg = OffReg.getOperand(0);
1316 ShOpcVal = ARM_AM::no_shift;
1319 ShOpcVal = ARM_AM::no_shift;
1323 ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
1328 //===--------------------------------------------------------------------===//
1330 /// getAL - Returns a ARMCC::AL immediate node.
1331 static inline SDValue getAL(SelectionDAG *CurDAG) {
1332 return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
1335 SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDNode *N) {
1336 LoadSDNode *LD = cast<LoadSDNode>(N);
1337 ISD::MemIndexedMode AM = LD->getAddressingMode();
1338 if (AM == ISD::UNINDEXED)
1341 EVT LoadedVT = LD->getMemoryVT();
1342 SDValue Offset, AMOpc;
1343 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1344 unsigned Opcode = 0;
1346 if (LoadedVT == MVT::i32 && isPre &&
1347 SelectAddrMode2OffsetImmPre(N, LD->getOffset(), Offset, AMOpc)) {
1348 Opcode = ARM::LDR_PRE_IMM;
1350 } else if (LoadedVT == MVT::i32 && !isPre &&
1351 SelectAddrMode2OffsetImm(N, LD->getOffset(), Offset, AMOpc)) {
1352 Opcode = ARM::LDR_POST_IMM;
1354 } else if (LoadedVT == MVT::i32 &&
1355 SelectAddrMode2OffsetReg(N, LD->getOffset(), Offset, AMOpc)) {
1356 Opcode = isPre ? ARM::LDR_PRE_REG : ARM::LDR_POST_REG;
1359 } else if (LoadedVT == MVT::i16 &&
1360 SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1362 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
1363 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
1364 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
1365 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
1366 if (LD->getExtensionType() == ISD::SEXTLOAD) {
1367 if (SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1369 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
1373 SelectAddrMode2OffsetImmPre(N, LD->getOffset(), Offset, AMOpc)) {
1375 Opcode = ARM::LDRB_PRE_IMM;
1376 } else if (!isPre &&
1377 SelectAddrMode2OffsetImm(N, LD->getOffset(), Offset, AMOpc)) {
1379 Opcode = ARM::LDRB_POST_IMM;
1380 } else if (SelectAddrMode2OffsetReg(N, LD->getOffset(), Offset, AMOpc)) {
1382 Opcode = isPre ? ARM::LDRB_PRE_REG : ARM::LDRB_POST_REG;
1388 if (Opcode == ARM::LDR_PRE_IMM || Opcode == ARM::LDRB_PRE_IMM) {
1389 SDValue Chain = LD->getChain();
1390 SDValue Base = LD->getBasePtr();
1391 SDValue Ops[]= { Base, AMOpc, getAL(CurDAG),
1392 CurDAG->getRegister(0, MVT::i32), Chain };
1393 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32,
1394 MVT::i32, MVT::Other, Ops, 5);
1396 SDValue Chain = LD->getChain();
1397 SDValue Base = LD->getBasePtr();
1398 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
1399 CurDAG->getRegister(0, MVT::i32), Chain };
1400 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32,
1401 MVT::i32, MVT::Other, Ops, 6);
1408 SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDNode *N) {
1409 LoadSDNode *LD = cast<LoadSDNode>(N);
1410 ISD::MemIndexedMode AM = LD->getAddressingMode();
1411 if (AM == ISD::UNINDEXED)
1414 EVT LoadedVT = LD->getMemoryVT();
1415 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
1417 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1418 unsigned Opcode = 0;
1420 if (SelectT2AddrModeImm8Offset(N, LD->getOffset(), Offset)) {
1421 switch (LoadedVT.getSimpleVT().SimpleTy) {
1423 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
1427 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
1429 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
1434 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
1436 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
1445 SDValue Chain = LD->getChain();
1446 SDValue Base = LD->getBasePtr();
1447 SDValue Ops[]= { Base, Offset, getAL(CurDAG),
1448 CurDAG->getRegister(0, MVT::i32), Chain };
1449 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32,
1450 MVT::Other, Ops, 5);
1456 /// PairSRegs - Form a D register from a pair of S registers.
1458 SDNode *ARMDAGToDAGISel::PairSRegs(EVT VT, SDValue V0, SDValue V1) {
1459 DebugLoc dl = V0.getNode()->getDebugLoc();
1461 CurDAG->getTargetConstant(ARM::DPR_VFP2RegClassID, MVT::i32);
1462 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1463 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1464 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1465 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5);
1468 /// PairDRegs - Form a quad register from a pair of D registers.
1470 SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) {
1471 DebugLoc dl = V0.getNode()->getDebugLoc();
1472 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, MVT::i32);
1473 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1474 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1475 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1476 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5);
1479 /// PairQRegs - Form 4 consecutive D registers from a pair of Q registers.
1481 SDNode *ARMDAGToDAGISel::PairQRegs(EVT VT, SDValue V0, SDValue V1) {
1482 DebugLoc dl = V0.getNode()->getDebugLoc();
1483 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32);
1484 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1485 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1486 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1487 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5);
1490 /// QuadSRegs - Form 4 consecutive S registers.
1492 SDNode *ARMDAGToDAGISel::QuadSRegs(EVT VT, SDValue V0, SDValue V1,
1493 SDValue V2, SDValue V3) {
1494 DebugLoc dl = V0.getNode()->getDebugLoc();
1496 CurDAG->getTargetConstant(ARM::QPR_VFP2RegClassID, MVT::i32);
1497 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1498 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1499 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, MVT::i32);
1500 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::ssub_3, MVT::i32);
1501 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1502 V2, SubReg2, V3, SubReg3 };
1503 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 9);
1506 /// QuadDRegs - Form 4 consecutive D registers.
1508 SDNode *ARMDAGToDAGISel::QuadDRegs(EVT VT, SDValue V0, SDValue V1,
1509 SDValue V2, SDValue V3) {
1510 DebugLoc dl = V0.getNode()->getDebugLoc();
1511 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32);
1512 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1513 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1514 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, MVT::i32);
1515 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, MVT::i32);
1516 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1517 V2, SubReg2, V3, SubReg3 };
1518 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 9);
1521 /// QuadQRegs - Form 4 consecutive Q registers.
1523 SDNode *ARMDAGToDAGISel::QuadQRegs(EVT VT, SDValue V0, SDValue V1,
1524 SDValue V2, SDValue V3) {
1525 DebugLoc dl = V0.getNode()->getDebugLoc();
1526 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, MVT::i32);
1527 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1528 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1529 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, MVT::i32);
1530 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, MVT::i32);
1531 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1532 V2, SubReg2, V3, SubReg3 };
1533 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 9);
1536 /// GetVLDSTAlign - Get the alignment (in bytes) for the alignment operand
1537 /// of a NEON VLD or VST instruction. The supported values depend on the
1538 /// number of registers being loaded.
1539 SDValue ARMDAGToDAGISel::GetVLDSTAlign(SDValue Align, unsigned NumVecs,
1540 bool is64BitVector) {
1541 unsigned NumRegs = NumVecs;
1542 if (!is64BitVector && NumVecs < 3)
1545 unsigned Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1546 if (Alignment >= 32 && NumRegs == 4)
1548 else if (Alignment >= 16 && (NumRegs == 2 || NumRegs == 4))
1550 else if (Alignment >= 8)
1555 return CurDAG->getTargetConstant(Alignment, MVT::i32);
1558 SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
1559 unsigned *DOpcodes, unsigned *QOpcodes0,
1560 unsigned *QOpcodes1) {
1561 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range");
1562 DebugLoc dl = N->getDebugLoc();
1564 SDValue MemAddr, Align;
1565 unsigned AddrOpIdx = isUpdating ? 1 : 2;
1566 if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1569 SDValue Chain = N->getOperand(0);
1570 EVT VT = N->getValueType(0);
1571 bool is64BitVector = VT.is64BitVector();
1572 Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1574 unsigned OpcodeIndex;
1575 switch (VT.getSimpleVT().SimpleTy) {
1576 default: llvm_unreachable("unhandled vld type");
1577 // Double-register operations:
1578 case MVT::v8i8: OpcodeIndex = 0; break;
1579 case MVT::v4i16: OpcodeIndex = 1; break;
1581 case MVT::v2i32: OpcodeIndex = 2; break;
1582 case MVT::v1i64: OpcodeIndex = 3; break;
1583 // Quad-register operations:
1584 case MVT::v16i8: OpcodeIndex = 0; break;
1585 case MVT::v8i16: OpcodeIndex = 1; break;
1587 case MVT::v4i32: OpcodeIndex = 2; break;
1588 case MVT::v2i64: OpcodeIndex = 3;
1589 assert(NumVecs == 1 && "v2i64 type only supported for VLD1");
1597 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1600 ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts);
1602 std::vector<EVT> ResTys;
1603 ResTys.push_back(ResTy);
1605 ResTys.push_back(MVT::i32);
1606 ResTys.push_back(MVT::Other);
1608 SDValue Pred = getAL(CurDAG);
1609 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1611 SmallVector<SDValue, 7> Ops;
1613 // Double registers and VLD1/VLD2 quad registers are directly supported.
1614 if (is64BitVector || NumVecs <= 2) {
1615 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1616 QOpcodes0[OpcodeIndex]);
1617 Ops.push_back(MemAddr);
1618 Ops.push_back(Align);
1620 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1621 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1623 Ops.push_back(Pred);
1624 Ops.push_back(Reg0);
1625 Ops.push_back(Chain);
1626 VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), Ops.size());
1629 // Otherwise, quad registers are loaded with two separate instructions,
1630 // where one loads the even registers and the other loads the odd registers.
1631 EVT AddrTy = MemAddr.getValueType();
1633 // Load the even subregs. This is always an updating load, so that it
1634 // provides the address to the second load for the odd subregs.
1636 SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy), 0);
1637 const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain };
1638 SDNode *VLdA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl,
1639 ResTy, AddrTy, MVT::Other, OpsA, 7);
1640 Chain = SDValue(VLdA, 2);
1642 // Load the odd subregs.
1643 Ops.push_back(SDValue(VLdA, 1));
1644 Ops.push_back(Align);
1646 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1647 assert(isa<ConstantSDNode>(Inc.getNode()) &&
1648 "only constant post-increment update allowed for VLD3/4");
1650 Ops.push_back(Reg0);
1652 Ops.push_back(SDValue(VLdA, 0));
1653 Ops.push_back(Pred);
1654 Ops.push_back(Reg0);
1655 Ops.push_back(Chain);
1656 VLd = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys,
1657 Ops.data(), Ops.size());
1660 // Transfer memoperands.
1661 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1662 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1663 cast<MachineSDNode>(VLd)->setMemRefs(MemOp, MemOp + 1);
1668 // Extract out the subregisters.
1669 SDValue SuperReg = SDValue(VLd, 0);
1670 assert(ARM::dsub_7 == ARM::dsub_0+7 &&
1671 ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1672 unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0);
1673 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1674 ReplaceUses(SDValue(N, Vec),
1675 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
1676 ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1));
1678 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLd, 2));
1682 SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
1683 unsigned *DOpcodes, unsigned *QOpcodes0,
1684 unsigned *QOpcodes1) {
1685 assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range");
1686 DebugLoc dl = N->getDebugLoc();
1688 SDValue MemAddr, Align;
1689 unsigned AddrOpIdx = isUpdating ? 1 : 2;
1690 unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
1691 if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1694 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1695 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1697 SDValue Chain = N->getOperand(0);
1698 EVT VT = N->getOperand(Vec0Idx).getValueType();
1699 bool is64BitVector = VT.is64BitVector();
1700 Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1702 unsigned OpcodeIndex;
1703 switch (VT.getSimpleVT().SimpleTy) {
1704 default: llvm_unreachable("unhandled vst type");
1705 // Double-register operations:
1706 case MVT::v8i8: OpcodeIndex = 0; break;
1707 case MVT::v4i16: OpcodeIndex = 1; break;
1709 case MVT::v2i32: OpcodeIndex = 2; break;
1710 case MVT::v1i64: OpcodeIndex = 3; break;
1711 // Quad-register operations:
1712 case MVT::v16i8: OpcodeIndex = 0; break;
1713 case MVT::v8i16: OpcodeIndex = 1; break;
1715 case MVT::v4i32: OpcodeIndex = 2; break;
1716 case MVT::v2i64: OpcodeIndex = 3;
1717 assert(NumVecs == 1 && "v2i64 type only supported for VST1");
1721 std::vector<EVT> ResTys;
1723 ResTys.push_back(MVT::i32);
1724 ResTys.push_back(MVT::Other);
1726 SDValue Pred = getAL(CurDAG);
1727 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1728 SmallVector<SDValue, 7> Ops;
1730 // Double registers and VST1/VST2 quad registers are directly supported.
1731 if (is64BitVector || NumVecs <= 2) {
1734 SrcReg = N->getOperand(Vec0Idx);
1735 } else if (is64BitVector) {
1736 // Form a REG_SEQUENCE to force register allocation.
1737 SDValue V0 = N->getOperand(Vec0Idx + 0);
1738 SDValue V1 = N->getOperand(Vec0Idx + 1);
1740 SrcReg = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1742 SDValue V2 = N->getOperand(Vec0Idx + 2);
1743 // If it's a vst3, form a quad D-register and leave the last part as
1745 SDValue V3 = (NumVecs == 3)
1746 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1747 : N->getOperand(Vec0Idx + 3);
1748 SrcReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1751 // Form a QQ register.
1752 SDValue Q0 = N->getOperand(Vec0Idx);
1753 SDValue Q1 = N->getOperand(Vec0Idx + 1);
1754 SrcReg = SDValue(PairQRegs(MVT::v4i64, Q0, Q1), 0);
1757 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1758 QOpcodes0[OpcodeIndex]);
1759 Ops.push_back(MemAddr);
1760 Ops.push_back(Align);
1762 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1763 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1765 Ops.push_back(SrcReg);
1766 Ops.push_back(Pred);
1767 Ops.push_back(Reg0);
1768 Ops.push_back(Chain);
1770 CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), Ops.size());
1772 // Transfer memoperands.
1773 cast<MachineSDNode>(VSt)->setMemRefs(MemOp, MemOp + 1);
1778 // Otherwise, quad registers are stored with two separate instructions,
1779 // where one stores the even registers and the other stores the odd registers.
1781 // Form the QQQQ REG_SEQUENCE.
1782 SDValue V0 = N->getOperand(Vec0Idx + 0);
1783 SDValue V1 = N->getOperand(Vec0Idx + 1);
1784 SDValue V2 = N->getOperand(Vec0Idx + 2);
1785 SDValue V3 = (NumVecs == 3)
1786 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1787 : N->getOperand(Vec0Idx + 3);
1788 SDValue RegSeq = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);
1790 // Store the even D registers. This is always an updating store, so that it
1791 // provides the address to the second store for the odd subregs.
1792 const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain };
1793 SDNode *VStA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl,
1794 MemAddr.getValueType(),
1795 MVT::Other, OpsA, 7);
1796 cast<MachineSDNode>(VStA)->setMemRefs(MemOp, MemOp + 1);
1797 Chain = SDValue(VStA, 1);
1799 // Store the odd D registers.
1800 Ops.push_back(SDValue(VStA, 0));
1801 Ops.push_back(Align);
1803 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1804 assert(isa<ConstantSDNode>(Inc.getNode()) &&
1805 "only constant post-increment update allowed for VST3/4");
1807 Ops.push_back(Reg0);
1809 Ops.push_back(RegSeq);
1810 Ops.push_back(Pred);
1811 Ops.push_back(Reg0);
1812 Ops.push_back(Chain);
1813 SDNode *VStB = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys,
1814 Ops.data(), Ops.size());
1815 cast<MachineSDNode>(VStB)->setMemRefs(MemOp, MemOp + 1);
1819 SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
1820 bool isUpdating, unsigned NumVecs,
1822 unsigned *QOpcodes) {
1823 assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
1824 DebugLoc dl = N->getDebugLoc();
1826 SDValue MemAddr, Align;
1827 unsigned AddrOpIdx = isUpdating ? 1 : 2;
1828 unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
1829 if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1832 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1833 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1835 SDValue Chain = N->getOperand(0);
1837 cast<ConstantSDNode>(N->getOperand(Vec0Idx + NumVecs))->getZExtValue();
1838 EVT VT = N->getOperand(Vec0Idx).getValueType();
1839 bool is64BitVector = VT.is64BitVector();
1841 unsigned Alignment = 0;
1843 Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1844 unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
1845 if (Alignment > NumBytes)
1846 Alignment = NumBytes;
1847 if (Alignment < 8 && Alignment < NumBytes)
1849 // Alignment must be a power of two; make sure of that.
1850 Alignment = (Alignment & -Alignment);
1854 Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
1856 unsigned OpcodeIndex;
1857 switch (VT.getSimpleVT().SimpleTy) {
1858 default: llvm_unreachable("unhandled vld/vst lane type");
1859 // Double-register operations:
1860 case MVT::v8i8: OpcodeIndex = 0; break;
1861 case MVT::v4i16: OpcodeIndex = 1; break;
1863 case MVT::v2i32: OpcodeIndex = 2; break;
1864 // Quad-register operations:
1865 case MVT::v8i16: OpcodeIndex = 0; break;
1867 case MVT::v4i32: OpcodeIndex = 1; break;
1870 std::vector<EVT> ResTys;
1872 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1875 ResTys.push_back(EVT::getVectorVT(*CurDAG->getContext(),
1876 MVT::i64, ResTyElts));
1879 ResTys.push_back(MVT::i32);
1880 ResTys.push_back(MVT::Other);
1882 SDValue Pred = getAL(CurDAG);
1883 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1885 SmallVector<SDValue, 8> Ops;
1886 Ops.push_back(MemAddr);
1887 Ops.push_back(Align);
1889 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1890 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1894 SDValue V0 = N->getOperand(Vec0Idx + 0);
1895 SDValue V1 = N->getOperand(Vec0Idx + 1);
1898 SuperReg = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1900 SuperReg = SDValue(PairQRegs(MVT::v4i64, V0, V1), 0);
1902 SDValue V2 = N->getOperand(Vec0Idx + 2);
1903 SDValue V3 = (NumVecs == 3)
1904 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1905 : N->getOperand(Vec0Idx + 3);
1907 SuperReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1909 SuperReg = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);
1911 Ops.push_back(SuperReg);
1912 Ops.push_back(getI32Imm(Lane));
1913 Ops.push_back(Pred);
1914 Ops.push_back(Reg0);
1915 Ops.push_back(Chain);
1917 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1918 QOpcodes[OpcodeIndex]);
1919 SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTys,
1920 Ops.data(), Ops.size());
1921 cast<MachineSDNode>(VLdLn)->setMemRefs(MemOp, MemOp + 1);
1925 // Extract the subregisters.
1926 SuperReg = SDValue(VLdLn, 0);
1927 assert(ARM::dsub_7 == ARM::dsub_0+7 &&
1928 ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1929 unsigned Sub0 = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;
1930 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1931 ReplaceUses(SDValue(N, Vec),
1932 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
1933 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, 1));
1935 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdLn, 2));
1939 SDNode *ARMDAGToDAGISel::SelectVLDDup(SDNode *N, bool isUpdating,
1940 unsigned NumVecs, unsigned *Opcodes) {
1941 assert(NumVecs >=2 && NumVecs <= 4 && "VLDDup NumVecs out-of-range");
1942 DebugLoc dl = N->getDebugLoc();
1944 SDValue MemAddr, Align;
1945 if (!SelectAddrMode6(N, N->getOperand(1), MemAddr, Align))
1948 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1949 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1951 SDValue Chain = N->getOperand(0);
1952 EVT VT = N->getValueType(0);
1954 unsigned Alignment = 0;
1956 Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1957 unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
1958 if (Alignment > NumBytes)
1959 Alignment = NumBytes;
1960 if (Alignment < 8 && Alignment < NumBytes)
1962 // Alignment must be a power of two; make sure of that.
1963 Alignment = (Alignment & -Alignment);
1967 Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
1969 unsigned OpcodeIndex;
1970 switch (VT.getSimpleVT().SimpleTy) {
1971 default: llvm_unreachable("unhandled vld-dup type");
1972 case MVT::v8i8: OpcodeIndex = 0; break;
1973 case MVT::v4i16: OpcodeIndex = 1; break;
1975 case MVT::v2i32: OpcodeIndex = 2; break;
1978 SDValue Pred = getAL(CurDAG);
1979 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1981 unsigned Opc = Opcodes[OpcodeIndex];
1982 SmallVector<SDValue, 6> Ops;
1983 Ops.push_back(MemAddr);
1984 Ops.push_back(Align);
1986 SDValue Inc = N->getOperand(2);
1987 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1989 Ops.push_back(Pred);
1990 Ops.push_back(Reg0);
1991 Ops.push_back(Chain);
1993 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1994 std::vector<EVT> ResTys;
1995 ResTys.push_back(EVT::getVectorVT(*CurDAG->getContext(), MVT::i64,ResTyElts));
1997 ResTys.push_back(MVT::i32);
1998 ResTys.push_back(MVT::Other);
2000 CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), Ops.size());
2001 cast<MachineSDNode>(VLdDup)->setMemRefs(MemOp, MemOp + 1);
2002 SuperReg = SDValue(VLdDup, 0);
2004 // Extract the subregisters.
2005 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2006 unsigned SubIdx = ARM::dsub_0;
2007 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
2008 ReplaceUses(SDValue(N, Vec),
2009 CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, SuperReg));
2010 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdDup, 1));
2012 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdDup, 2));
2016 SDNode *ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs,
2018 assert(NumVecs >= 2 && NumVecs <= 4 && "VTBL NumVecs out-of-range");
2019 DebugLoc dl = N->getDebugLoc();
2020 EVT VT = N->getValueType(0);
2021 unsigned FirstTblReg = IsExt ? 2 : 1;
2023 // Form a REG_SEQUENCE to force register allocation.
2025 SDValue V0 = N->getOperand(FirstTblReg + 0);
2026 SDValue V1 = N->getOperand(FirstTblReg + 1);
2028 RegSeq = SDValue(PairDRegs(MVT::v16i8, V0, V1), 0);
2030 SDValue V2 = N->getOperand(FirstTblReg + 2);
2031 // If it's a vtbl3, form a quad D-register and leave the last part as
2033 SDValue V3 = (NumVecs == 3)
2034 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
2035 : N->getOperand(FirstTblReg + 3);
2036 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
2039 SmallVector<SDValue, 6> Ops;
2041 Ops.push_back(N->getOperand(1));
2042 Ops.push_back(RegSeq);
2043 Ops.push_back(N->getOperand(FirstTblReg + NumVecs));
2044 Ops.push_back(getAL(CurDAG)); // predicate
2045 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // predicate register
2046 return CurDAG->getMachineNode(Opc, dl, VT, Ops.data(), Ops.size());
2049 SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N,
2051 if (!Subtarget->hasV6T2Ops())
2054 unsigned Opc = isSigned ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX)
2055 : (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX);
2058 // For unsigned extracts, check for a shift right and mask
2059 unsigned And_imm = 0;
2060 if (N->getOpcode() == ISD::AND) {
2061 if (isOpcWithIntImmediate(N, ISD::AND, And_imm)) {
2063 // The immediate is a mask of the low bits iff imm & (imm+1) == 0
2064 if (And_imm & (And_imm + 1))
2067 unsigned Srl_imm = 0;
2068 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL,
2070 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
2072 // Note: The width operand is encoded as width-1.
2073 unsigned Width = CountTrailingOnes_32(And_imm) - 1;
2074 unsigned LSB = Srl_imm;
2075 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2076 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2077 CurDAG->getTargetConstant(LSB, MVT::i32),
2078 CurDAG->getTargetConstant(Width, MVT::i32),
2079 getAL(CurDAG), Reg0 };
2080 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2086 // Otherwise, we're looking for a shift of a shift
2087 unsigned Shl_imm = 0;
2088 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, Shl_imm)) {
2089 assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!");
2090 unsigned Srl_imm = 0;
2091 if (isInt32Immediate(N->getOperand(1), Srl_imm)) {
2092 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
2093 // Note: The width operand is encoded as width-1.
2094 unsigned Width = 32 - Srl_imm - 1;
2095 int LSB = Srl_imm - Shl_imm;
2098 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2099 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2100 CurDAG->getTargetConstant(LSB, MVT::i32),
2101 CurDAG->getTargetConstant(Width, MVT::i32),
2102 getAL(CurDAG), Reg0 };
2103 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2109 SDNode *ARMDAGToDAGISel::
2110 SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2111 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2114 if (SelectT2ShifterOperandReg(TrueVal, CPTmp0, CPTmp1)) {
2115 unsigned SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue();
2116 unsigned SOShOp = ARM_AM::getSORegShOp(SOVal);
2119 case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break;
2120 case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break;
2121 case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break;
2122 case ARM_AM::ror: Opc = ARM::t2MOVCCror; break;
2124 llvm_unreachable("Unknown so_reg opcode!");
2128 CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32);
2129 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2130 SDValue Ops[] = { FalseVal, CPTmp0, SOShImm, CC, CCR, InFlag };
2131 return CurDAG->SelectNodeTo(N, Opc, MVT::i32,Ops, 6);
2136 SDNode *ARMDAGToDAGISel::
2137 SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2138 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2142 if (SelectImmShifterOperand(TrueVal, CPTmp0, CPTmp2)) {
2143 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2144 SDValue Ops[] = { FalseVal, CPTmp0, CPTmp2, CC, CCR, InFlag };
2145 return CurDAG->SelectNodeTo(N, ARM::MOVCCsi, MVT::i32, Ops, 6);
2148 if (SelectRegShifterOperand(TrueVal, CPTmp0, CPTmp1, CPTmp2)) {
2149 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2150 SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CPTmp2, CC, CCR, InFlag };
2151 return CurDAG->SelectNodeTo(N, ARM::MOVCCsr, MVT::i32, Ops, 7);
2156 SDNode *ARMDAGToDAGISel::
2157 SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2158 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2159 ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
2164 unsigned TrueImm = T->getZExtValue();
2165 if (is_t2_so_imm(TrueImm)) {
2166 Opc = ARM::t2MOVCCi;
2167 } else if (TrueImm <= 0xffff) {
2168 Opc = ARM::t2MOVCCi16;
2169 } else if (is_t2_so_imm_not(TrueImm)) {
2171 Opc = ARM::t2MVNCCi;
2172 } else if (TrueVal.getNode()->hasOneUse() && Subtarget->hasV6T2Ops()) {
2174 Opc = ARM::t2MOVCCi32imm;
2178 SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
2179 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2180 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
2181 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2187 SDNode *ARMDAGToDAGISel::
2188 SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2189 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2190 ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
2195 unsigned TrueImm = T->getZExtValue();
2196 bool isSoImm = is_so_imm(TrueImm);
2199 } else if (Subtarget->hasV6T2Ops() && TrueImm <= 0xffff) {
2200 Opc = ARM::MOVCCi16;
2201 } else if (is_so_imm_not(TrueImm)) {
2204 } else if (TrueVal.getNode()->hasOneUse() &&
2205 (Subtarget->hasV6T2Ops() || ARM_AM::isSOImmTwoPartVal(TrueImm))) {
2207 Opc = ARM::MOVCCi32imm;
2211 SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
2212 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2213 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
2214 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2220 SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDNode *N) {
2221 EVT VT = N->getValueType(0);
2222 SDValue FalseVal = N->getOperand(0);
2223 SDValue TrueVal = N->getOperand(1);
2224 SDValue CC = N->getOperand(2);
2225 SDValue CCR = N->getOperand(3);
2226 SDValue InFlag = N->getOperand(4);
2227 assert(CC.getOpcode() == ISD::Constant);
2228 assert(CCR.getOpcode() == ISD::Register);
2229 ARMCC::CondCodes CCVal =
2230 (ARMCC::CondCodes)cast<ConstantSDNode>(CC)->getZExtValue();
2232 if (!Subtarget->isThumb1Only() && VT == MVT::i32) {
2233 // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
2234 // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
2235 // Pattern complexity = 18 cost = 1 size = 0
2239 if (Subtarget->isThumb()) {
2240 SDNode *Res = SelectT2CMOVShiftOp(N, FalseVal, TrueVal,
2241 CCVal, CCR, InFlag);
2243 Res = SelectT2CMOVShiftOp(N, TrueVal, FalseVal,
2244 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2248 SDNode *Res = SelectARMCMOVShiftOp(N, FalseVal, TrueVal,
2249 CCVal, CCR, InFlag);
2251 Res = SelectARMCMOVShiftOp(N, TrueVal, FalseVal,
2252 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2257 // Pattern: (ARMcmov:i32 GPR:i32:$false,
2258 // (imm:i32)<<P:Pred_so_imm>>:$true,
2260 // Emits: (MOVCCi:i32 GPR:i32:$false,
2261 // (so_imm:i32 (imm:i32):$true), (imm:i32):$cc)
2262 // Pattern complexity = 10 cost = 1 size = 0
2263 if (Subtarget->isThumb()) {
2264 SDNode *Res = SelectT2CMOVImmOp(N, FalseVal, TrueVal,
2265 CCVal, CCR, InFlag);
2267 Res = SelectT2CMOVImmOp(N, TrueVal, FalseVal,
2268 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2272 SDNode *Res = SelectARMCMOVImmOp(N, FalseVal, TrueVal,
2273 CCVal, CCR, InFlag);
2275 Res = SelectARMCMOVImmOp(N, TrueVal, FalseVal,
2276 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2282 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2283 // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2284 // Pattern complexity = 6 cost = 1 size = 0
2286 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2287 // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2288 // Pattern complexity = 6 cost = 11 size = 0
2290 // Also VMOVScc and VMOVDcc.
2291 SDValue Tmp2 = CurDAG->getTargetConstant(CCVal, MVT::i32);
2292 SDValue Ops[] = { FalseVal, TrueVal, Tmp2, CCR, InFlag };
2294 switch (VT.getSimpleVT().SimpleTy) {
2295 default: assert(false && "Illegal conditional move type!");
2298 Opc = Subtarget->isThumb()
2299 ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo)
2309 return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
2312 SDNode *ARMDAGToDAGISel::SelectConcatVector(SDNode *N) {
2313 // The only time a CONCAT_VECTORS operation can have legal types is when
2314 // two 64-bit vectors are concatenated to a 128-bit vector.
2315 EVT VT = N->getValueType(0);
2316 if (!VT.is128BitVector() || N->getNumOperands() != 2)
2317 llvm_unreachable("unexpected CONCAT_VECTORS");
2318 return PairDRegs(VT, N->getOperand(0), N->getOperand(1));
2321 SDNode *ARMDAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) {
2322 SmallVector<SDValue, 6> Ops;
2323 Ops.push_back(Node->getOperand(1)); // Ptr
2324 Ops.push_back(Node->getOperand(2)); // Low part of Val1
2325 Ops.push_back(Node->getOperand(3)); // High part of Val1
2326 if (Opc == ARM::ATOMCMPXCHG6432) {
2327 Ops.push_back(Node->getOperand(4)); // Low part of Val2
2328 Ops.push_back(Node->getOperand(5)); // High part of Val2
2330 Ops.push_back(Node->getOperand(0)); // Chain
2331 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2332 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
2333 SDNode *ResNode = CurDAG->getMachineNode(Opc, Node->getDebugLoc(),
2334 MVT::i32, MVT::i32, MVT::Other,
2335 Ops.data() ,Ops.size());
2336 cast<MachineSDNode>(ResNode)->setMemRefs(MemOp, MemOp + 1);
2340 SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
2341 DebugLoc dl = N->getDebugLoc();
2343 if (N->isMachineOpcode())
2344 return NULL; // Already selected.
2346 switch (N->getOpcode()) {
2348 case ISD::Constant: {
2349 unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
2351 if (Subtarget->hasThumb2())
2352 // Thumb2-aware targets have the MOVT instruction, so all immediates can
2353 // be done with MOV + MOVT, at worst.
2356 if (Subtarget->isThumb()) {
2357 UseCP = (Val > 255 && // MOV
2358 ~Val > 255 && // MOV + MVN
2359 !ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL
2361 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
2362 ARM_AM::getSOImmVal(~Val) == -1 && // MVN
2363 !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs.
2368 CurDAG->getTargetConstantPool(ConstantInt::get(
2369 Type::getInt32Ty(*CurDAG->getContext()), Val),
2370 TLI.getPointerTy());
2373 if (Subtarget->isThumb1Only()) {
2374 SDValue Pred = getAL(CurDAG);
2375 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2376 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
2377 ResNode = CurDAG->getMachineNode(ARM::tLDRpci, dl, MVT::i32, MVT::Other,
2382 CurDAG->getTargetConstant(0, MVT::i32),
2384 CurDAG->getRegister(0, MVT::i32),
2385 CurDAG->getEntryNode()
2387 ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
2390 ReplaceUses(SDValue(N, 0), SDValue(ResNode, 0));
2394 // Other cases are autogenerated.
2397 case ISD::FrameIndex: {
2398 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
2399 int FI = cast<FrameIndexSDNode>(N)->getIndex();
2400 SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
2401 if (Subtarget->isThumb1Only()) {
2402 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
2403 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2404 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, Ops, 4);
2406 unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
2407 ARM::t2ADDri : ARM::ADDri);
2408 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
2409 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2410 CurDAG->getRegister(0, MVT::i32) };
2411 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2415 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2419 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, true))
2423 if (Subtarget->isThumb1Only())
2425 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
2426 unsigned RHSV = C->getZExtValue();
2428 if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
2429 unsigned ShImm = Log2_32(RHSV-1);
2432 SDValue V = N->getOperand(0);
2433 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2434 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2435 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2436 if (Subtarget->isThumb()) {
2437 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2438 return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
2440 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2441 return CurDAG->SelectNodeTo(N, ARM::ADDrsi, MVT::i32, Ops, 7);
2444 if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
2445 unsigned ShImm = Log2_32(RHSV+1);
2448 SDValue V = N->getOperand(0);
2449 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2450 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2451 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2452 if (Subtarget->isThumb()) {
2453 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2454 return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 6);
2456 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2457 return CurDAG->SelectNodeTo(N, ARM::RSBrsi, MVT::i32, Ops, 7);
2463 // Check for unsigned bitfield extract
2464 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2467 // (and (or x, c2), c1) and top 16-bits of c1 and c2 match, lower 16-bits
2468 // of c1 are 0xffff, and lower 16-bit of c2 are 0. That is, the top 16-bits
2469 // are entirely contributed by c2 and lower 16-bits are entirely contributed
2470 // by x. That's equal to (or (and x, 0xffff), (and c1, 0xffff0000)).
2471 // Select it to: "movt x, ((c1 & 0xffff) >> 16)
2472 EVT VT = N->getValueType(0);
2475 unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2())
2477 : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0);
2480 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2481 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2484 if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) {
2485 SDValue N2 = N0.getOperand(1);
2486 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2489 unsigned N1CVal = N1C->getZExtValue();
2490 unsigned N2CVal = N2C->getZExtValue();
2491 if ((N1CVal & 0xffff0000U) == (N2CVal & 0xffff0000U) &&
2492 (N1CVal & 0xffffU) == 0xffffU &&
2493 (N2CVal & 0xffffU) == 0x0U) {
2494 SDValue Imm16 = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16,
2496 SDValue Ops[] = { N0.getOperand(0), Imm16,
2497 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2498 return CurDAG->getMachineNode(Opc, dl, VT, Ops, 4);
2503 case ARMISD::VMOVRRD:
2504 return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32,
2505 N->getOperand(0), getAL(CurDAG),
2506 CurDAG->getRegister(0, MVT::i32));
2507 case ISD::UMUL_LOHI: {
2508 if (Subtarget->isThumb1Only())
2510 if (Subtarget->isThumb()) {
2511 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2512 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2513 CurDAG->getRegister(0, MVT::i32) };
2514 return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32,Ops,4);
2516 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2517 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2518 CurDAG->getRegister(0, MVT::i32) };
2519 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2520 ARM::UMULL : ARM::UMULLv5,
2521 dl, MVT::i32, MVT::i32, Ops, 5);
2524 case ISD::SMUL_LOHI: {
2525 if (Subtarget->isThumb1Only())
2527 if (Subtarget->isThumb()) {
2528 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2529 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2530 return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32,Ops,4);
2532 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2533 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2534 CurDAG->getRegister(0, MVT::i32) };
2535 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2536 ARM::SMULL : ARM::SMULLv5,
2537 dl, MVT::i32, MVT::i32, Ops, 5);
2541 SDNode *ResNode = 0;
2542 if (Subtarget->isThumb() && Subtarget->hasThumb2())
2543 ResNode = SelectT2IndexedLoad(N);
2545 ResNode = SelectARMIndexedLoad(N);
2548 // Other cases are autogenerated.
2551 case ARMISD::BRCOND: {
2552 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2553 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2554 // Pattern complexity = 6 cost = 1 size = 0
2556 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2557 // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
2558 // Pattern complexity = 6 cost = 1 size = 0
2560 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2561 // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2562 // Pattern complexity = 6 cost = 1 size = 0
2564 unsigned Opc = Subtarget->isThumb() ?
2565 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
2566 SDValue Chain = N->getOperand(0);
2567 SDValue N1 = N->getOperand(1);
2568 SDValue N2 = N->getOperand(2);
2569 SDValue N3 = N->getOperand(3);
2570 SDValue InFlag = N->getOperand(4);
2571 assert(N1.getOpcode() == ISD::BasicBlock);
2572 assert(N2.getOpcode() == ISD::Constant);
2573 assert(N3.getOpcode() == ISD::Register);
2575 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
2576 cast<ConstantSDNode>(N2)->getZExtValue()),
2578 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
2579 SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,
2581 Chain = SDValue(ResNode, 0);
2582 if (N->getNumValues() == 2) {
2583 InFlag = SDValue(ResNode, 1);
2584 ReplaceUses(SDValue(N, 1), InFlag);
2586 ReplaceUses(SDValue(N, 0),
2587 SDValue(Chain.getNode(), Chain.getResNo()));
2591 return SelectCMOVOp(N);
2592 case ARMISD::VZIP: {
2594 EVT VT = N->getValueType(0);
2595 switch (VT.getSimpleVT().SimpleTy) {
2596 default: return NULL;
2597 case MVT::v8i8: Opc = ARM::VZIPd8; break;
2598 case MVT::v4i16: Opc = ARM::VZIPd16; break;
2600 case MVT::v2i32: Opc = ARM::VZIPd32; break;
2601 case MVT::v16i8: Opc = ARM::VZIPq8; break;
2602 case MVT::v8i16: Opc = ARM::VZIPq16; break;
2604 case MVT::v4i32: Opc = ARM::VZIPq32; break;
2606 SDValue Pred = getAL(CurDAG);
2607 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2608 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2609 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2611 case ARMISD::VUZP: {
2613 EVT VT = N->getValueType(0);
2614 switch (VT.getSimpleVT().SimpleTy) {
2615 default: return NULL;
2616 case MVT::v8i8: Opc = ARM::VUZPd8; break;
2617 case MVT::v4i16: Opc = ARM::VUZPd16; break;
2619 case MVT::v2i32: Opc = ARM::VUZPd32; break;
2620 case MVT::v16i8: Opc = ARM::VUZPq8; break;
2621 case MVT::v8i16: Opc = ARM::VUZPq16; break;
2623 case MVT::v4i32: Opc = ARM::VUZPq32; break;
2625 SDValue Pred = getAL(CurDAG);
2626 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2627 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2628 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2630 case ARMISD::VTRN: {
2632 EVT VT = N->getValueType(0);
2633 switch (VT.getSimpleVT().SimpleTy) {
2634 default: return NULL;
2635 case MVT::v8i8: Opc = ARM::VTRNd8; break;
2636 case MVT::v4i16: Opc = ARM::VTRNd16; break;
2638 case MVT::v2i32: Opc = ARM::VTRNd32; break;
2639 case MVT::v16i8: Opc = ARM::VTRNq8; break;
2640 case MVT::v8i16: Opc = ARM::VTRNq16; break;
2642 case MVT::v4i32: Opc = ARM::VTRNq32; break;
2644 SDValue Pred = getAL(CurDAG);
2645 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2646 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2647 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2649 case ARMISD::BUILD_VECTOR: {
2650 EVT VecVT = N->getValueType(0);
2651 EVT EltVT = VecVT.getVectorElementType();
2652 unsigned NumElts = VecVT.getVectorNumElements();
2653 if (EltVT == MVT::f64) {
2654 assert(NumElts == 2 && "unexpected type for BUILD_VECTOR");
2655 return PairDRegs(VecVT, N->getOperand(0), N->getOperand(1));
2657 assert(EltVT == MVT::f32 && "unexpected type for BUILD_VECTOR");
2659 return PairSRegs(VecVT, N->getOperand(0), N->getOperand(1));
2660 assert(NumElts == 4 && "unexpected type for BUILD_VECTOR");
2661 return QuadSRegs(VecVT, N->getOperand(0), N->getOperand(1),
2662 N->getOperand(2), N->getOperand(3));
2665 case ARMISD::VLD2DUP: {
2666 unsigned Opcodes[] = { ARM::VLD2DUPd8Pseudo, ARM::VLD2DUPd16Pseudo,
2667 ARM::VLD2DUPd32Pseudo };
2668 return SelectVLDDup(N, false, 2, Opcodes);
2671 case ARMISD::VLD3DUP: {
2672 unsigned Opcodes[] = { ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd16Pseudo,
2673 ARM::VLD3DUPd32Pseudo };
2674 return SelectVLDDup(N, false, 3, Opcodes);
2677 case ARMISD::VLD4DUP: {
2678 unsigned Opcodes[] = { ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd16Pseudo,
2679 ARM::VLD4DUPd32Pseudo };
2680 return SelectVLDDup(N, false, 4, Opcodes);
2683 case ARMISD::VLD2DUP_UPD: {
2684 unsigned Opcodes[] = { ARM::VLD2DUPd8Pseudo_UPD, ARM::VLD2DUPd16Pseudo_UPD,
2685 ARM::VLD2DUPd32Pseudo_UPD };
2686 return SelectVLDDup(N, true, 2, Opcodes);
2689 case ARMISD::VLD3DUP_UPD: {
2690 unsigned Opcodes[] = { ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd16Pseudo_UPD,
2691 ARM::VLD3DUPd32Pseudo_UPD };
2692 return SelectVLDDup(N, true, 3, Opcodes);
2695 case ARMISD::VLD4DUP_UPD: {
2696 unsigned Opcodes[] = { ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd16Pseudo_UPD,
2697 ARM::VLD4DUPd32Pseudo_UPD };
2698 return SelectVLDDup(N, true, 4, Opcodes);
2701 case ARMISD::VLD1_UPD: {
2702 unsigned DOpcodes[] = { ARM::VLD1d8_UPD, ARM::VLD1d16_UPD,
2703 ARM::VLD1d32_UPD, ARM::VLD1d64_UPD };
2704 unsigned QOpcodes[] = { ARM::VLD1q8Pseudo_UPD, ARM::VLD1q16Pseudo_UPD,
2705 ARM::VLD1q32Pseudo_UPD, ARM::VLD1q64Pseudo_UPD };
2706 return SelectVLD(N, true, 1, DOpcodes, QOpcodes, 0);
2709 case ARMISD::VLD2_UPD: {
2710 unsigned DOpcodes[] = { ARM::VLD2d8Pseudo_UPD, ARM::VLD2d16Pseudo_UPD,
2711 ARM::VLD2d32Pseudo_UPD, ARM::VLD1q64Pseudo_UPD };
2712 unsigned QOpcodes[] = { ARM::VLD2q8Pseudo_UPD, ARM::VLD2q16Pseudo_UPD,
2713 ARM::VLD2q32Pseudo_UPD };
2714 return SelectVLD(N, true, 2, DOpcodes, QOpcodes, 0);
2717 case ARMISD::VLD3_UPD: {
2718 unsigned DOpcodes[] = { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d16Pseudo_UPD,
2719 ARM::VLD3d32Pseudo_UPD, ARM::VLD1d64TPseudo_UPD };
2720 unsigned QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
2721 ARM::VLD3q16Pseudo_UPD,
2722 ARM::VLD3q32Pseudo_UPD };
2723 unsigned QOpcodes1[] = { ARM::VLD3q8oddPseudo_UPD,
2724 ARM::VLD3q16oddPseudo_UPD,
2725 ARM::VLD3q32oddPseudo_UPD };
2726 return SelectVLD(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
2729 case ARMISD::VLD4_UPD: {
2730 unsigned DOpcodes[] = { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d16Pseudo_UPD,
2731 ARM::VLD4d32Pseudo_UPD, ARM::VLD1d64QPseudo_UPD };
2732 unsigned QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
2733 ARM::VLD4q16Pseudo_UPD,
2734 ARM::VLD4q32Pseudo_UPD };
2735 unsigned QOpcodes1[] = { ARM::VLD4q8oddPseudo_UPD,
2736 ARM::VLD4q16oddPseudo_UPD,
2737 ARM::VLD4q32oddPseudo_UPD };
2738 return SelectVLD(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
2741 case ARMISD::VLD2LN_UPD: {
2742 unsigned DOpcodes[] = { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd16Pseudo_UPD,
2743 ARM::VLD2LNd32Pseudo_UPD };
2744 unsigned QOpcodes[] = { ARM::VLD2LNq16Pseudo_UPD,
2745 ARM::VLD2LNq32Pseudo_UPD };
2746 return SelectVLDSTLane(N, true, true, 2, DOpcodes, QOpcodes);
2749 case ARMISD::VLD3LN_UPD: {
2750 unsigned DOpcodes[] = { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd16Pseudo_UPD,
2751 ARM::VLD3LNd32Pseudo_UPD };
2752 unsigned QOpcodes[] = { ARM::VLD3LNq16Pseudo_UPD,
2753 ARM::VLD3LNq32Pseudo_UPD };
2754 return SelectVLDSTLane(N, true, true, 3, DOpcodes, QOpcodes);
2757 case ARMISD::VLD4LN_UPD: {
2758 unsigned DOpcodes[] = { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd16Pseudo_UPD,
2759 ARM::VLD4LNd32Pseudo_UPD };
2760 unsigned QOpcodes[] = { ARM::VLD4LNq16Pseudo_UPD,
2761 ARM::VLD4LNq32Pseudo_UPD };
2762 return SelectVLDSTLane(N, true, true, 4, DOpcodes, QOpcodes);
2765 case ARMISD::VST1_UPD: {
2766 unsigned DOpcodes[] = { ARM::VST1d8_UPD, ARM::VST1d16_UPD,
2767 ARM::VST1d32_UPD, ARM::VST1d64_UPD };
2768 unsigned QOpcodes[] = { ARM::VST1q8Pseudo_UPD, ARM::VST1q16Pseudo_UPD,
2769 ARM::VST1q32Pseudo_UPD, ARM::VST1q64Pseudo_UPD };
2770 return SelectVST(N, true, 1, DOpcodes, QOpcodes, 0);
2773 case ARMISD::VST2_UPD: {
2774 unsigned DOpcodes[] = { ARM::VST2d8Pseudo_UPD, ARM::VST2d16Pseudo_UPD,
2775 ARM::VST2d32Pseudo_UPD, ARM::VST1q64Pseudo_UPD };
2776 unsigned QOpcodes[] = { ARM::VST2q8Pseudo_UPD, ARM::VST2q16Pseudo_UPD,
2777 ARM::VST2q32Pseudo_UPD };
2778 return SelectVST(N, true, 2, DOpcodes, QOpcodes, 0);
2781 case ARMISD::VST3_UPD: {
2782 unsigned DOpcodes[] = { ARM::VST3d8Pseudo_UPD, ARM::VST3d16Pseudo_UPD,
2783 ARM::VST3d32Pseudo_UPD, ARM::VST1d64TPseudo_UPD };
2784 unsigned QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
2785 ARM::VST3q16Pseudo_UPD,
2786 ARM::VST3q32Pseudo_UPD };
2787 unsigned QOpcodes1[] = { ARM::VST3q8oddPseudo_UPD,
2788 ARM::VST3q16oddPseudo_UPD,
2789 ARM::VST3q32oddPseudo_UPD };
2790 return SelectVST(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
2793 case ARMISD::VST4_UPD: {
2794 unsigned DOpcodes[] = { ARM::VST4d8Pseudo_UPD, ARM::VST4d16Pseudo_UPD,
2795 ARM::VST4d32Pseudo_UPD, ARM::VST1d64QPseudo_UPD };
2796 unsigned QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
2797 ARM::VST4q16Pseudo_UPD,
2798 ARM::VST4q32Pseudo_UPD };
2799 unsigned QOpcodes1[] = { ARM::VST4q8oddPseudo_UPD,
2800 ARM::VST4q16oddPseudo_UPD,
2801 ARM::VST4q32oddPseudo_UPD };
2802 return SelectVST(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
2805 case ARMISD::VST2LN_UPD: {
2806 unsigned DOpcodes[] = { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd16Pseudo_UPD,
2807 ARM::VST2LNd32Pseudo_UPD };
2808 unsigned QOpcodes[] = { ARM::VST2LNq16Pseudo_UPD,
2809 ARM::VST2LNq32Pseudo_UPD };
2810 return SelectVLDSTLane(N, false, true, 2, DOpcodes, QOpcodes);
2813 case ARMISD::VST3LN_UPD: {
2814 unsigned DOpcodes[] = { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd16Pseudo_UPD,
2815 ARM::VST3LNd32Pseudo_UPD };
2816 unsigned QOpcodes[] = { ARM::VST3LNq16Pseudo_UPD,
2817 ARM::VST3LNq32Pseudo_UPD };
2818 return SelectVLDSTLane(N, false, true, 3, DOpcodes, QOpcodes);
2821 case ARMISD::VST4LN_UPD: {
2822 unsigned DOpcodes[] = { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd16Pseudo_UPD,
2823 ARM::VST4LNd32Pseudo_UPD };
2824 unsigned QOpcodes[] = { ARM::VST4LNq16Pseudo_UPD,
2825 ARM::VST4LNq32Pseudo_UPD };
2826 return SelectVLDSTLane(N, false, true, 4, DOpcodes, QOpcodes);
2829 case ISD::INTRINSIC_VOID:
2830 case ISD::INTRINSIC_W_CHAIN: {
2831 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
2836 case Intrinsic::arm_ldrexd: {
2837 SDValue MemAddr = N->getOperand(2);
2838 DebugLoc dl = N->getDebugLoc();
2839 SDValue Chain = N->getOperand(0);
2841 unsigned NewOpc = ARM::LDREXD;
2842 if (Subtarget->isThumb() && Subtarget->hasThumb2())
2843 NewOpc = ARM::t2LDREXD;
2845 // arm_ldrexd returns a i64 value in {i32, i32}
2846 std::vector<EVT> ResTys;
2847 ResTys.push_back(MVT::i32);
2848 ResTys.push_back(MVT::i32);
2849 ResTys.push_back(MVT::Other);
2851 // place arguments in the right order
2852 SmallVector<SDValue, 7> Ops;
2853 Ops.push_back(MemAddr);
2854 Ops.push_back(getAL(CurDAG));
2855 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
2856 Ops.push_back(Chain);
2857 SDNode *Ld = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops.data(),
2859 // Transfer memoperands.
2860 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2861 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
2862 cast<MachineSDNode>(Ld)->setMemRefs(MemOp, MemOp + 1);
2864 // Until there's support for specifing explicit register constraints
2865 // like the use of even/odd register pair, hardcode ldrexd to always
2866 // use the pair [R0, R1] to hold the load result.
2867 Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ARM::R0,
2868 SDValue(Ld, 0), SDValue(0,0));
2869 Chain = CurDAG->getCopyToReg(Chain, dl, ARM::R1,
2870 SDValue(Ld, 1), Chain.getValue(1));
2873 SDValue Glue = Chain.getValue(1);
2874 if (!SDValue(N, 0).use_empty()) {
2875 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2876 ARM::R0, MVT::i32, Glue);
2877 Glue = Result.getValue(2);
2878 ReplaceUses(SDValue(N, 0), Result);
2880 if (!SDValue(N, 1).use_empty()) {
2881 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2882 ARM::R1, MVT::i32, Glue);
2883 Glue = Result.getValue(2);
2884 ReplaceUses(SDValue(N, 1), Result);
2887 ReplaceUses(SDValue(N, 2), SDValue(Ld, 2));
2891 case Intrinsic::arm_strexd: {
2892 DebugLoc dl = N->getDebugLoc();
2893 SDValue Chain = N->getOperand(0);
2894 SDValue Val0 = N->getOperand(2);
2895 SDValue Val1 = N->getOperand(3);
2896 SDValue MemAddr = N->getOperand(4);
2898 // Until there's support for specifing explicit register constraints
2899 // like the use of even/odd register pair, hardcode strexd to always
2900 // use the pair [R2, R3] to hold the i64 (i32, i32) value to be stored.
2901 Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ARM::R2, Val0,
2903 Chain = CurDAG->getCopyToReg(Chain, dl, ARM::R3, Val1, Chain.getValue(1));
2905 SDValue Glue = Chain.getValue(1);
2906 Val0 = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2907 ARM::R2, MVT::i32, Glue);
2908 Glue = Val0.getValue(1);
2909 Val1 = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2910 ARM::R3, MVT::i32, Glue);
2912 // Store exclusive double return a i32 value which is the return status
2913 // of the issued store.
2914 std::vector<EVT> ResTys;
2915 ResTys.push_back(MVT::i32);
2916 ResTys.push_back(MVT::Other);
2918 // place arguments in the right order
2919 SmallVector<SDValue, 7> Ops;
2920 Ops.push_back(Val0);
2921 Ops.push_back(Val1);
2922 Ops.push_back(MemAddr);
2923 Ops.push_back(getAL(CurDAG));
2924 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
2925 Ops.push_back(Chain);
2927 unsigned NewOpc = ARM::STREXD;
2928 if (Subtarget->isThumb() && Subtarget->hasThumb2())
2929 NewOpc = ARM::t2STREXD;
2931 SDNode *St = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops.data(),
2933 // Transfer memoperands.
2934 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2935 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
2936 cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1);
2941 case Intrinsic::arm_neon_vld1: {
2942 unsigned DOpcodes[] = { ARM::VLD1d8, ARM::VLD1d16,
2943 ARM::VLD1d32, ARM::VLD1d64 };
2944 unsigned QOpcodes[] = { ARM::VLD1q8Pseudo, ARM::VLD1q16Pseudo,
2945 ARM::VLD1q32Pseudo, ARM::VLD1q64Pseudo };
2946 return SelectVLD(N, false, 1, DOpcodes, QOpcodes, 0);
2949 case Intrinsic::arm_neon_vld2: {
2950 unsigned DOpcodes[] = { ARM::VLD2d8Pseudo, ARM::VLD2d16Pseudo,
2951 ARM::VLD2d32Pseudo, ARM::VLD1q64Pseudo };
2952 unsigned QOpcodes[] = { ARM::VLD2q8Pseudo, ARM::VLD2q16Pseudo,
2953 ARM::VLD2q32Pseudo };
2954 return SelectVLD(N, false, 2, DOpcodes, QOpcodes, 0);
2957 case Intrinsic::arm_neon_vld3: {
2958 unsigned DOpcodes[] = { ARM::VLD3d8Pseudo, ARM::VLD3d16Pseudo,
2959 ARM::VLD3d32Pseudo, ARM::VLD1d64TPseudo };
2960 unsigned QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
2961 ARM::VLD3q16Pseudo_UPD,
2962 ARM::VLD3q32Pseudo_UPD };
2963 unsigned QOpcodes1[] = { ARM::VLD3q8oddPseudo,
2964 ARM::VLD3q16oddPseudo,
2965 ARM::VLD3q32oddPseudo };
2966 return SelectVLD(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
2969 case Intrinsic::arm_neon_vld4: {
2970 unsigned DOpcodes[] = { ARM::VLD4d8Pseudo, ARM::VLD4d16Pseudo,
2971 ARM::VLD4d32Pseudo, ARM::VLD1d64QPseudo };
2972 unsigned QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
2973 ARM::VLD4q16Pseudo_UPD,
2974 ARM::VLD4q32Pseudo_UPD };
2975 unsigned QOpcodes1[] = { ARM::VLD4q8oddPseudo,
2976 ARM::VLD4q16oddPseudo,
2977 ARM::VLD4q32oddPseudo };
2978 return SelectVLD(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
2981 case Intrinsic::arm_neon_vld2lane: {
2982 unsigned DOpcodes[] = { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd16Pseudo,
2983 ARM::VLD2LNd32Pseudo };
2984 unsigned QOpcodes[] = { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq32Pseudo };
2985 return SelectVLDSTLane(N, true, false, 2, DOpcodes, QOpcodes);
2988 case Intrinsic::arm_neon_vld3lane: {
2989 unsigned DOpcodes[] = { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd16Pseudo,
2990 ARM::VLD3LNd32Pseudo };
2991 unsigned QOpcodes[] = { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq32Pseudo };
2992 return SelectVLDSTLane(N, true, false, 3, DOpcodes, QOpcodes);
2995 case Intrinsic::arm_neon_vld4lane: {
2996 unsigned DOpcodes[] = { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd16Pseudo,
2997 ARM::VLD4LNd32Pseudo };
2998 unsigned QOpcodes[] = { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq32Pseudo };
2999 return SelectVLDSTLane(N, true, false, 4, DOpcodes, QOpcodes);
3002 case Intrinsic::arm_neon_vst1: {
3003 unsigned DOpcodes[] = { ARM::VST1d8, ARM::VST1d16,
3004 ARM::VST1d32, ARM::VST1d64 };
3005 unsigned QOpcodes[] = { ARM::VST1q8Pseudo, ARM::VST1q16Pseudo,
3006 ARM::VST1q32Pseudo, ARM::VST1q64Pseudo };
3007 return SelectVST(N, false, 1, DOpcodes, QOpcodes, 0);
3010 case Intrinsic::arm_neon_vst2: {
3011 unsigned DOpcodes[] = { ARM::VST2d8Pseudo, ARM::VST2d16Pseudo,
3012 ARM::VST2d32Pseudo, ARM::VST1q64Pseudo };
3013 unsigned QOpcodes[] = { ARM::VST2q8Pseudo, ARM::VST2q16Pseudo,
3014 ARM::VST2q32Pseudo };
3015 return SelectVST(N, false, 2, DOpcodes, QOpcodes, 0);
3018 case Intrinsic::arm_neon_vst3: {
3019 unsigned DOpcodes[] = { ARM::VST3d8Pseudo, ARM::VST3d16Pseudo,
3020 ARM::VST3d32Pseudo, ARM::VST1d64TPseudo };
3021 unsigned QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
3022 ARM::VST3q16Pseudo_UPD,
3023 ARM::VST3q32Pseudo_UPD };
3024 unsigned QOpcodes1[] = { ARM::VST3q8oddPseudo,
3025 ARM::VST3q16oddPseudo,
3026 ARM::VST3q32oddPseudo };
3027 return SelectVST(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
3030 case Intrinsic::arm_neon_vst4: {
3031 unsigned DOpcodes[] = { ARM::VST4d8Pseudo, ARM::VST4d16Pseudo,
3032 ARM::VST4d32Pseudo, ARM::VST1d64QPseudo };
3033 unsigned QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
3034 ARM::VST4q16Pseudo_UPD,
3035 ARM::VST4q32Pseudo_UPD };
3036 unsigned QOpcodes1[] = { ARM::VST4q8oddPseudo,
3037 ARM::VST4q16oddPseudo,
3038 ARM::VST4q32oddPseudo };
3039 return SelectVST(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
3042 case Intrinsic::arm_neon_vst2lane: {
3043 unsigned DOpcodes[] = { ARM::VST2LNd8Pseudo, ARM::VST2LNd16Pseudo,
3044 ARM::VST2LNd32Pseudo };
3045 unsigned QOpcodes[] = { ARM::VST2LNq16Pseudo, ARM::VST2LNq32Pseudo };
3046 return SelectVLDSTLane(N, false, false, 2, DOpcodes, QOpcodes);
3049 case Intrinsic::arm_neon_vst3lane: {
3050 unsigned DOpcodes[] = { ARM::VST3LNd8Pseudo, ARM::VST3LNd16Pseudo,
3051 ARM::VST3LNd32Pseudo };
3052 unsigned QOpcodes[] = { ARM::VST3LNq16Pseudo, ARM::VST3LNq32Pseudo };
3053 return SelectVLDSTLane(N, false, false, 3, DOpcodes, QOpcodes);
3056 case Intrinsic::arm_neon_vst4lane: {
3057 unsigned DOpcodes[] = { ARM::VST4LNd8Pseudo, ARM::VST4LNd16Pseudo,
3058 ARM::VST4LNd32Pseudo };
3059 unsigned QOpcodes[] = { ARM::VST4LNq16Pseudo, ARM::VST4LNq32Pseudo };
3060 return SelectVLDSTLane(N, false, false, 4, DOpcodes, QOpcodes);
3066 case ISD::INTRINSIC_WO_CHAIN: {
3067 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
3072 case Intrinsic::arm_neon_vtbl2:
3073 return SelectVTBL(N, false, 2, ARM::VTBL2Pseudo);
3074 case Intrinsic::arm_neon_vtbl3:
3075 return SelectVTBL(N, false, 3, ARM::VTBL3Pseudo);
3076 case Intrinsic::arm_neon_vtbl4:
3077 return SelectVTBL(N, false, 4, ARM::VTBL4Pseudo);
3079 case Intrinsic::arm_neon_vtbx2:
3080 return SelectVTBL(N, true, 2, ARM::VTBX2Pseudo);
3081 case Intrinsic::arm_neon_vtbx3:
3082 return SelectVTBL(N, true, 3, ARM::VTBX3Pseudo);
3083 case Intrinsic::arm_neon_vtbx4:
3084 return SelectVTBL(N, true, 4, ARM::VTBX4Pseudo);
3089 case ARMISD::VTBL1: {
3090 DebugLoc dl = N->getDebugLoc();
3091 EVT VT = N->getValueType(0);
3092 SmallVector<SDValue, 6> Ops;
3094 Ops.push_back(N->getOperand(0));
3095 Ops.push_back(N->getOperand(1));
3096 Ops.push_back(getAL(CurDAG)); // Predicate
3097 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register
3098 return CurDAG->getMachineNode(ARM::VTBL1, dl, VT, Ops.data(), Ops.size());
3100 case ARMISD::VTBL2: {
3101 DebugLoc dl = N->getDebugLoc();
3102 EVT VT = N->getValueType(0);
3104 // Form a REG_SEQUENCE to force register allocation.
3105 SDValue V0 = N->getOperand(0);
3106 SDValue V1 = N->getOperand(1);
3107 SDValue RegSeq = SDValue(PairDRegs(MVT::v16i8, V0, V1), 0);
3109 SmallVector<SDValue, 6> Ops;
3110 Ops.push_back(RegSeq);
3111 Ops.push_back(N->getOperand(2));
3112 Ops.push_back(getAL(CurDAG)); // Predicate
3113 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register
3114 return CurDAG->getMachineNode(ARM::VTBL2Pseudo, dl, VT,
3115 Ops.data(), Ops.size());
3118 case ISD::CONCAT_VECTORS:
3119 return SelectConcatVector(N);
3121 case ARMISD::ATOMOR64_DAG:
3122 return SelectAtomic64(N, ARM::ATOMOR6432);
3123 case ARMISD::ATOMXOR64_DAG:
3124 return SelectAtomic64(N, ARM::ATOMXOR6432);
3125 case ARMISD::ATOMADD64_DAG:
3126 return SelectAtomic64(N, ARM::ATOMADD6432);
3127 case ARMISD::ATOMSUB64_DAG:
3128 return SelectAtomic64(N, ARM::ATOMSUB6432);
3129 case ARMISD::ATOMNAND64_DAG:
3130 return SelectAtomic64(N, ARM::ATOMNAND6432);
3131 case ARMISD::ATOMAND64_DAG:
3132 return SelectAtomic64(N, ARM::ATOMAND6432);
3133 case ARMISD::ATOMSWAP64_DAG:
3134 return SelectAtomic64(N, ARM::ATOMSWAP6432);
3135 case ARMISD::ATOMCMPXCHG64_DAG:
3136 return SelectAtomic64(N, ARM::ATOMCMPXCHG6432);
3139 return SelectCode(N);
3142 bool ARMDAGToDAGISel::
3143 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
3144 std::vector<SDValue> &OutOps) {
3145 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
3146 // Require the address to be in a register. That is safe for all ARM
3147 // variants and it is hard to do anything much smarter without knowing
3148 // how the operand is used.
3149 OutOps.push_back(Op);
3153 /// createARMISelDag - This pass converts a legalized DAG into a
3154 /// ARM-specific DAG, ready for instruction scheduling.
3156 FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
3157 CodeGenOpt::Level OptLevel) {
3158 return new ARMDAGToDAGISel(TM, OptLevel);