1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMTargetMachine.h"
17 #include "MCTargetDesc/ARMAddressingModes.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/IR/CallingConv.h"
25 #include "llvm/IR/Constants.h"
26 #include "llvm/IR/DerivedTypes.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/Intrinsics.h"
29 #include "llvm/IR/LLVMContext.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Compiler.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Target/TargetLowering.h"
35 #include "llvm/Target/TargetOptions.h"
39 #define DEBUG_TYPE "arm-isel"
42 DisableShifterOp("disable-shifter-op", cl::Hidden,
43 cl::desc("Disable isel of shifter-op"),
47 CheckVMLxHazard("check-vmlx-hazard", cl::Hidden,
48 cl::desc("Check fp vmla / vmls hazard at isel time"),
51 //===--------------------------------------------------------------------===//
52 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
53 /// instructions for SelectionDAG operations.
58 AM2_BASE, // Simple AM2 (+-imm12)
59 AM2_SHOP // Shifter-op AM2
62 class ARMDAGToDAGISel : public SelectionDAGISel {
63 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
64 /// make the right decision when generating code for different targets.
65 const ARMSubtarget *Subtarget;
68 explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm, CodeGenOpt::Level OptLevel)
69 : SelectionDAGISel(tm, OptLevel) {}
71 bool runOnMachineFunction(MachineFunction &MF) override {
72 // Reset the subtarget each time through.
73 Subtarget = &MF.getTarget().getSubtarget<ARMSubtarget>();
74 SelectionDAGISel::runOnMachineFunction(MF);
78 const char *getPassName() const override {
79 return "ARM Instruction Selection";
82 void PreprocessISelDAG() override;
84 /// getI32Imm - Return a target constant of type i32 with the specified
86 inline SDValue getI32Imm(unsigned Imm) {
87 return CurDAG->getTargetConstant(Imm, MVT::i32);
90 SDNode *Select(SDNode *N) override;
93 bool hasNoVMLxHazardUse(SDNode *N) const;
94 bool isShifterOpProfitable(const SDValue &Shift,
95 ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
96 bool SelectRegShifterOperand(SDValue N, SDValue &A,
97 SDValue &B, SDValue &C,
98 bool CheckProfitability = true);
99 bool SelectImmShifterOperand(SDValue N, SDValue &A,
100 SDValue &B, bool CheckProfitability = true);
101 bool SelectShiftRegShifterOperand(SDValue N, SDValue &A,
102 SDValue &B, SDValue &C) {
103 // Don't apply the profitability check
104 return SelectRegShifterOperand(N, A, B, C, false);
106 bool SelectShiftImmShifterOperand(SDValue N, SDValue &A,
108 // Don't apply the profitability check
109 return SelectImmShifterOperand(N, A, B, false);
112 bool SelectAddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
113 bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc);
115 AddrMode2Type SelectAddrMode2Worker(SDValue N, SDValue &Base,
116 SDValue &Offset, SDValue &Opc);
117 bool SelectAddrMode2Base(SDValue N, SDValue &Base, SDValue &Offset,
119 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_BASE;
122 bool SelectAddrMode2ShOp(SDValue N, SDValue &Base, SDValue &Offset,
124 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_SHOP;
127 bool SelectAddrMode2(SDValue N, SDValue &Base, SDValue &Offset,
129 SelectAddrMode2Worker(N, Base, Offset, Opc);
130 // return SelectAddrMode2ShOp(N, Base, Offset, Opc);
131 // This always matches one way or another.
135 bool SelectCMOVPred(SDValue N, SDValue &Pred, SDValue &Reg) {
136 const ConstantSDNode *CN = cast<ConstantSDNode>(N);
137 Pred = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
138 Reg = CurDAG->getRegister(ARM::CPSR, MVT::i32);
142 bool SelectAddrMode2OffsetReg(SDNode *Op, SDValue N,
143 SDValue &Offset, SDValue &Opc);
144 bool SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
145 SDValue &Offset, SDValue &Opc);
146 bool SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N,
147 SDValue &Offset, SDValue &Opc);
148 bool SelectAddrOffsetNone(SDValue N, SDValue &Base);
149 bool SelectAddrMode3(SDValue N, SDValue &Base,
150 SDValue &Offset, SDValue &Opc);
151 bool SelectAddrMode3Offset(SDNode *Op, SDValue N,
152 SDValue &Offset, SDValue &Opc);
153 bool SelectAddrMode5(SDValue N, SDValue &Base,
155 bool SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,SDValue &Align);
156 bool SelectAddrMode6Offset(SDNode *Op, SDValue N, SDValue &Offset);
158 bool SelectAddrModePC(SDValue N, SDValue &Offset, SDValue &Label);
160 // Thumb Addressing Modes:
161 bool SelectThumbAddrModeRR(SDValue N, SDValue &Base, SDValue &Offset);
162 bool SelectThumbAddrModeRI(SDValue N, SDValue &Base, SDValue &Offset,
164 bool SelectThumbAddrModeRI5S1(SDValue N, SDValue &Base, SDValue &Offset);
165 bool SelectThumbAddrModeRI5S2(SDValue N, SDValue &Base, SDValue &Offset);
166 bool SelectThumbAddrModeRI5S4(SDValue N, SDValue &Base, SDValue &Offset);
167 bool SelectThumbAddrModeImm5S(SDValue N, unsigned Scale, SDValue &Base,
169 bool SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
171 bool SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
173 bool SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
175 bool SelectThumbAddrModeSP(SDValue N, SDValue &Base, SDValue &OffImm);
177 // Thumb 2 Addressing Modes:
178 bool SelectT2ShifterOperandReg(SDValue N,
179 SDValue &BaseReg, SDValue &Opc);
180 bool SelectT2AddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
181 bool SelectT2AddrModeImm8(SDValue N, SDValue &Base,
183 bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
185 bool SelectT2AddrModeSoReg(SDValue N, SDValue &Base,
186 SDValue &OffReg, SDValue &ShImm);
187 bool SelectT2AddrModeExclusive(SDValue N, SDValue &Base, SDValue &OffImm);
189 inline bool is_so_imm(unsigned Imm) const {
190 return ARM_AM::getSOImmVal(Imm) != -1;
193 inline bool is_so_imm_not(unsigned Imm) const {
194 return ARM_AM::getSOImmVal(~Imm) != -1;
197 inline bool is_t2_so_imm(unsigned Imm) const {
198 return ARM_AM::getT2SOImmVal(Imm) != -1;
201 inline bool is_t2_so_imm_not(unsigned Imm) const {
202 return ARM_AM::getT2SOImmVal(~Imm) != -1;
205 // Include the pieces autogenerated from the target description.
206 #include "ARMGenDAGISel.inc"
209 /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
211 SDNode *SelectARMIndexedLoad(SDNode *N);
212 SDNode *SelectT2IndexedLoad(SDNode *N);
214 /// SelectVLD - Select NEON load intrinsics. NumVecs should be
215 /// 1, 2, 3 or 4. The opcode arrays specify the instructions used for
216 /// loads of D registers and even subregs and odd subregs of Q registers.
217 /// For NumVecs <= 2, QOpcodes1 is not used.
218 SDNode *SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
219 const uint16_t *DOpcodes,
220 const uint16_t *QOpcodes0, const uint16_t *QOpcodes1);
222 /// SelectVST - Select NEON store intrinsics. NumVecs should
223 /// be 1, 2, 3 or 4. The opcode arrays specify the instructions used for
224 /// stores of D registers and even subregs and odd subregs of Q registers.
225 /// For NumVecs <= 2, QOpcodes1 is not used.
226 SDNode *SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
227 const uint16_t *DOpcodes,
228 const uint16_t *QOpcodes0, const uint16_t *QOpcodes1);
230 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should
231 /// be 2, 3 or 4. The opcode arrays specify the instructions used for
232 /// load/store of D registers and Q registers.
233 SDNode *SelectVLDSTLane(SDNode *N, bool IsLoad,
234 bool isUpdating, unsigned NumVecs,
235 const uint16_t *DOpcodes, const uint16_t *QOpcodes);
237 /// SelectVLDDup - Select NEON load-duplicate intrinsics. NumVecs
238 /// should be 2, 3 or 4. The opcode array specifies the instructions used
239 /// for loading D registers. (Q registers are not supported.)
240 SDNode *SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs,
241 const uint16_t *Opcodes);
243 /// SelectVTBL - Select NEON VTBL and VTBX intrinsics. NumVecs should be 2,
244 /// 3 or 4. These are custom-selected so that a REG_SEQUENCE can be
245 /// generated to force the table registers to be consecutive.
246 SDNode *SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc);
248 /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM.
249 SDNode *SelectV6T2BitfieldExtractOp(SDNode *N, bool isSigned);
251 // Select special operations if node forms integer ABS pattern
252 SDNode *SelectABSOp(SDNode *N);
254 SDNode *SelectInlineAsm(SDNode *N);
256 SDNode *SelectConcatVector(SDNode *N);
258 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
259 /// inline asm expressions.
260 bool SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
261 std::vector<SDValue> &OutOps) override;
263 // Form pairs of consecutive R, S, D, or Q registers.
264 SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
265 SDNode *createSRegPairNode(EVT VT, SDValue V0, SDValue V1);
266 SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
267 SDNode *createQRegPairNode(EVT VT, SDValue V0, SDValue V1);
269 // Form sequences of 4 consecutive S, D, or Q registers.
270 SDNode *createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
271 SDNode *createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
272 SDNode *createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
274 // Get the alignment operand for a NEON VLD or VST instruction.
275 SDValue GetVLDSTAlign(SDValue Align, unsigned NumVecs, bool is64BitVector);
279 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
280 /// operand. If so Imm will receive the 32-bit value.
281 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
282 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
283 Imm = cast<ConstantSDNode>(N)->getZExtValue();
289 // isInt32Immediate - This method tests to see if a constant operand.
290 // If so Imm will receive the 32 bit value.
291 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
292 return isInt32Immediate(N.getNode(), Imm);
295 // isOpcWithIntImmediate - This method tests to see if the node is a specific
296 // opcode and that it has a immediate integer right operand.
297 // If so Imm will receive the 32 bit value.
298 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
299 return N->getOpcode() == Opc &&
300 isInt32Immediate(N->getOperand(1).getNode(), Imm);
303 /// \brief Check whether a particular node is a constant value representable as
304 /// (N * Scale) where (N in [\p RangeMin, \p RangeMax).
306 /// \param ScaledConstant [out] - On success, the pre-scaled constant value.
307 static bool isScaledConstantInRange(SDValue Node, int Scale,
308 int RangeMin, int RangeMax,
309 int &ScaledConstant) {
310 assert(Scale > 0 && "Invalid scale!");
312 // Check that this is a constant.
313 const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Node);
317 ScaledConstant = (int) C->getZExtValue();
318 if ((ScaledConstant % Scale) != 0)
321 ScaledConstant /= Scale;
322 return ScaledConstant >= RangeMin && ScaledConstant < RangeMax;
325 void ARMDAGToDAGISel::PreprocessISelDAG() {
326 if (!Subtarget->hasV6T2Ops())
329 bool isThumb2 = Subtarget->isThumb();
330 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
331 E = CurDAG->allnodes_end(); I != E; ) {
332 SDNode *N = I++; // Preincrement iterator to avoid invalidation issues.
334 if (N->getOpcode() != ISD::ADD)
337 // Look for (add X1, (and (srl X2, c1), c2)) where c2 is constant with
338 // leading zeros, followed by consecutive set bits, followed by 1 or 2
339 // trailing zeros, e.g. 1020.
340 // Transform the expression to
341 // (add X1, (shl (and (srl X2, c1), (c2>>tz)), tz)) where tz is the number
342 // of trailing zeros of c2. The left shift would be folded as an shifter
343 // operand of 'add' and the 'and' and 'srl' would become a bits extraction
346 SDValue N0 = N->getOperand(0);
347 SDValue N1 = N->getOperand(1);
348 unsigned And_imm = 0;
349 if (!isOpcWithIntImmediate(N1.getNode(), ISD::AND, And_imm)) {
350 if (isOpcWithIntImmediate(N0.getNode(), ISD::AND, And_imm))
356 // Check if the AND mask is an immediate of the form: 000.....1111111100
357 unsigned TZ = countTrailingZeros(And_imm);
358 if (TZ != 1 && TZ != 2)
359 // Be conservative here. Shifter operands aren't always free. e.g. On
360 // Swift, left shifter operand of 1 / 2 for free but others are not.
362 // ubfx r3, r1, #16, #8
363 // ldr.w r3, [r0, r3, lsl #2]
366 // and.w r2, r9, r1, lsr #14
370 if (And_imm & (And_imm + 1))
373 // Look for (and (srl X, c1), c2).
374 SDValue Srl = N1.getOperand(0);
375 unsigned Srl_imm = 0;
376 if (!isOpcWithIntImmediate(Srl.getNode(), ISD::SRL, Srl_imm) ||
380 // Make sure first operand is not a shifter operand which would prevent
381 // folding of the left shift.
386 if (SelectT2ShifterOperandReg(N0, CPTmp0, CPTmp1))
389 if (SelectImmShifterOperand(N0, CPTmp0, CPTmp1) ||
390 SelectRegShifterOperand(N0, CPTmp0, CPTmp1, CPTmp2))
394 // Now make the transformation.
395 Srl = CurDAG->getNode(ISD::SRL, SDLoc(Srl), MVT::i32,
397 CurDAG->getConstant(Srl_imm+TZ, MVT::i32));
398 N1 = CurDAG->getNode(ISD::AND, SDLoc(N1), MVT::i32,
399 Srl, CurDAG->getConstant(And_imm, MVT::i32));
400 N1 = CurDAG->getNode(ISD::SHL, SDLoc(N1), MVT::i32,
401 N1, CurDAG->getConstant(TZ, MVT::i32));
402 CurDAG->UpdateNodeOperands(N, N0, N1);
406 /// hasNoVMLxHazardUse - Return true if it's desirable to select a FP MLA / MLS
407 /// node. VFP / NEON fp VMLA / VMLS instructions have special RAW hazards (at
408 /// least on current ARM implementations) which should be avoidded.
409 bool ARMDAGToDAGISel::hasNoVMLxHazardUse(SDNode *N) const {
410 if (OptLevel == CodeGenOpt::None)
413 if (!CheckVMLxHazard)
416 if (!Subtarget->isCortexA7() && !Subtarget->isCortexA8() &&
417 !Subtarget->isCortexA9() && !Subtarget->isSwift())
423 SDNode *Use = *N->use_begin();
424 if (Use->getOpcode() == ISD::CopyToReg)
426 if (Use->isMachineOpcode()) {
427 const ARMBaseInstrInfo *TII = static_cast<const ARMBaseInstrInfo *>(
428 CurDAG->getSubtarget().getInstrInfo());
430 const MCInstrDesc &MCID = TII->get(Use->getMachineOpcode());
433 unsigned Opcode = MCID.getOpcode();
434 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
436 // vmlx feeding into another vmlx. We actually want to unfold
437 // the use later in the MLxExpansion pass. e.g.
439 // vmla (stall 8 cycles)
444 // This adds up to about 18 - 19 cycles.
447 // vmul (stall 4 cycles)
448 // vadd adds up to about 14 cycles.
449 return TII->isFpMLxInstruction(Opcode);
455 bool ARMDAGToDAGISel::isShifterOpProfitable(const SDValue &Shift,
456 ARM_AM::ShiftOpc ShOpcVal,
458 if (!Subtarget->isLikeA9() && !Subtarget->isSwift())
460 if (Shift.hasOneUse())
463 return ShOpcVal == ARM_AM::lsl &&
464 (ShAmt == 2 || (Subtarget->isSwift() && ShAmt == 1));
467 bool ARMDAGToDAGISel::SelectImmShifterOperand(SDValue N,
470 bool CheckProfitability) {
471 if (DisableShifterOp)
474 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
476 // Don't match base register only case. That is matched to a separate
477 // lower complexity pattern with explicit register operand.
478 if (ShOpcVal == ARM_AM::no_shift) return false;
480 BaseReg = N.getOperand(0);
481 unsigned ShImmVal = 0;
482 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
483 if (!RHS) return false;
484 ShImmVal = RHS->getZExtValue() & 31;
485 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
490 bool ARMDAGToDAGISel::SelectRegShifterOperand(SDValue N,
494 bool CheckProfitability) {
495 if (DisableShifterOp)
498 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
500 // Don't match base register only case. That is matched to a separate
501 // lower complexity pattern with explicit register operand.
502 if (ShOpcVal == ARM_AM::no_shift) return false;
504 BaseReg = N.getOperand(0);
505 unsigned ShImmVal = 0;
506 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
507 if (RHS) return false;
509 ShReg = N.getOperand(1);
510 if (CheckProfitability && !isShifterOpProfitable(N, ShOpcVal, ShImmVal))
512 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
518 bool ARMDAGToDAGISel::SelectAddrModeImm12(SDValue N,
521 // Match simple R + imm12 operands.
524 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
525 !CurDAG->isBaseWithConstantOffset(N)) {
526 if (N.getOpcode() == ISD::FrameIndex) {
527 // Match frame index.
528 int FI = cast<FrameIndexSDNode>(N)->getIndex();
529 Base = CurDAG->getTargetFrameIndex(FI,
530 getTargetLowering()->getPointerTy());
531 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
535 if (N.getOpcode() == ARMISD::Wrapper &&
536 N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress) {
537 Base = N.getOperand(0);
540 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
544 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
545 int RHSC = (int)RHS->getZExtValue();
546 if (N.getOpcode() == ISD::SUB)
549 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
550 Base = N.getOperand(0);
551 if (Base.getOpcode() == ISD::FrameIndex) {
552 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
553 Base = CurDAG->getTargetFrameIndex(FI,
554 getTargetLowering()->getPointerTy());
556 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
563 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
569 bool ARMDAGToDAGISel::SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset,
571 if (N.getOpcode() == ISD::MUL &&
572 ((!Subtarget->isLikeA9() && !Subtarget->isSwift()) || N.hasOneUse())) {
573 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
574 // X * [3,5,9] -> X + X * [2,4,8] etc.
575 int RHSC = (int)RHS->getZExtValue();
578 ARM_AM::AddrOpc AddSub = ARM_AM::add;
580 AddSub = ARM_AM::sub;
583 if (isPowerOf2_32(RHSC)) {
584 unsigned ShAmt = Log2_32(RHSC);
585 Base = Offset = N.getOperand(0);
586 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
595 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
596 // ISD::OR that is equivalent to an ISD::ADD.
597 !CurDAG->isBaseWithConstantOffset(N))
600 // Leave simple R +/- imm12 operands for LDRi12
601 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR) {
603 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
604 -0x1000+1, 0x1000, RHSC)) // 12 bits.
608 // Otherwise this is R +/- [possibly shifted] R.
609 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::SUB ? ARM_AM::sub:ARM_AM::add;
610 ARM_AM::ShiftOpc ShOpcVal =
611 ARM_AM::getShiftOpcForNode(N.getOperand(1).getOpcode());
614 Base = N.getOperand(0);
615 Offset = N.getOperand(1);
617 if (ShOpcVal != ARM_AM::no_shift) {
618 // Check to see if the RHS of the shift is a constant, if not, we can't fold
620 if (ConstantSDNode *Sh =
621 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
622 ShAmt = Sh->getZExtValue();
623 if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
624 Offset = N.getOperand(1).getOperand(0);
627 ShOpcVal = ARM_AM::no_shift;
630 ShOpcVal = ARM_AM::no_shift;
634 // Try matching (R shl C) + (R).
635 if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
636 !(Subtarget->isLikeA9() || Subtarget->isSwift() ||
637 N.getOperand(0).hasOneUse())) {
638 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0).getOpcode());
639 if (ShOpcVal != ARM_AM::no_shift) {
640 // Check to see if the RHS of the shift is a constant, if not, we can't
642 if (ConstantSDNode *Sh =
643 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
644 ShAmt = Sh->getZExtValue();
645 if (isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt)) {
646 Offset = N.getOperand(0).getOperand(0);
647 Base = N.getOperand(1);
650 ShOpcVal = ARM_AM::no_shift;
653 ShOpcVal = ARM_AM::no_shift;
658 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
666 AddrMode2Type ARMDAGToDAGISel::SelectAddrMode2Worker(SDValue N,
670 if (N.getOpcode() == ISD::MUL &&
671 (!(Subtarget->isLikeA9() || Subtarget->isSwift()) || N.hasOneUse())) {
672 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
673 // X * [3,5,9] -> X + X * [2,4,8] etc.
674 int RHSC = (int)RHS->getZExtValue();
677 ARM_AM::AddrOpc AddSub = ARM_AM::add;
679 AddSub = ARM_AM::sub;
682 if (isPowerOf2_32(RHSC)) {
683 unsigned ShAmt = Log2_32(RHSC);
684 Base = Offset = N.getOperand(0);
685 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
694 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
695 // ISD::OR that is equivalent to an ADD.
696 !CurDAG->isBaseWithConstantOffset(N)) {
698 if (N.getOpcode() == ISD::FrameIndex) {
699 int FI = cast<FrameIndexSDNode>(N)->getIndex();
700 Base = CurDAG->getTargetFrameIndex(FI,
701 getTargetLowering()->getPointerTy());
702 } else if (N.getOpcode() == ARMISD::Wrapper &&
703 N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress) {
704 Base = N.getOperand(0);
706 Offset = CurDAG->getRegister(0, MVT::i32);
707 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
713 // Match simple R +/- imm12 operands.
714 if (N.getOpcode() != ISD::SUB) {
716 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
717 -0x1000+1, 0x1000, RHSC)) { // 12 bits.
718 Base = N.getOperand(0);
719 if (Base.getOpcode() == ISD::FrameIndex) {
720 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
721 Base = CurDAG->getTargetFrameIndex(FI,
722 getTargetLowering()->getPointerTy());
724 Offset = CurDAG->getRegister(0, MVT::i32);
726 ARM_AM::AddrOpc AddSub = ARM_AM::add;
728 AddSub = ARM_AM::sub;
731 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
738 if ((Subtarget->isLikeA9() || Subtarget->isSwift()) && !N.hasOneUse()) {
739 // Compute R +/- (R << N) and reuse it.
741 Offset = CurDAG->getRegister(0, MVT::i32);
742 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
748 // Otherwise this is R +/- [possibly shifted] R.
749 ARM_AM::AddrOpc AddSub = N.getOpcode() != ISD::SUB ? ARM_AM::add:ARM_AM::sub;
750 ARM_AM::ShiftOpc ShOpcVal =
751 ARM_AM::getShiftOpcForNode(N.getOperand(1).getOpcode());
754 Base = N.getOperand(0);
755 Offset = N.getOperand(1);
757 if (ShOpcVal != ARM_AM::no_shift) {
758 // Check to see if the RHS of the shift is a constant, if not, we can't fold
760 if (ConstantSDNode *Sh =
761 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
762 ShAmt = Sh->getZExtValue();
763 if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
764 Offset = N.getOperand(1).getOperand(0);
767 ShOpcVal = ARM_AM::no_shift;
770 ShOpcVal = ARM_AM::no_shift;
774 // Try matching (R shl C) + (R).
775 if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
776 !(Subtarget->isLikeA9() || Subtarget->isSwift() ||
777 N.getOperand(0).hasOneUse())) {
778 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0).getOpcode());
779 if (ShOpcVal != ARM_AM::no_shift) {
780 // Check to see if the RHS of the shift is a constant, if not, we can't
782 if (ConstantSDNode *Sh =
783 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
784 ShAmt = Sh->getZExtValue();
785 if (isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt)) {
786 Offset = N.getOperand(0).getOperand(0);
787 Base = N.getOperand(1);
790 ShOpcVal = ARM_AM::no_shift;
793 ShOpcVal = ARM_AM::no_shift;
798 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
803 bool ARMDAGToDAGISel::SelectAddrMode2OffsetReg(SDNode *Op, SDValue N,
804 SDValue &Offset, SDValue &Opc) {
805 unsigned Opcode = Op->getOpcode();
806 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
807 ? cast<LoadSDNode>(Op)->getAddressingMode()
808 : cast<StoreSDNode>(Op)->getAddressingMode();
809 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
810 ? ARM_AM::add : ARM_AM::sub;
812 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val))
816 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
818 if (ShOpcVal != ARM_AM::no_shift) {
819 // Check to see if the RHS of the shift is a constant, if not, we can't fold
821 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
822 ShAmt = Sh->getZExtValue();
823 if (isShifterOpProfitable(N, ShOpcVal, ShAmt))
824 Offset = N.getOperand(0);
827 ShOpcVal = ARM_AM::no_shift;
830 ShOpcVal = ARM_AM::no_shift;
834 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
839 bool ARMDAGToDAGISel::SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N,
840 SDValue &Offset, SDValue &Opc) {
841 unsigned Opcode = Op->getOpcode();
842 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
843 ? cast<LoadSDNode>(Op)->getAddressingMode()
844 : cast<StoreSDNode>(Op)->getAddressingMode();
845 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
846 ? ARM_AM::add : ARM_AM::sub;
848 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits.
849 if (AddSub == ARM_AM::sub) Val *= -1;
850 Offset = CurDAG->getRegister(0, MVT::i32);
851 Opc = CurDAG->getTargetConstant(Val, MVT::i32);
859 bool ARMDAGToDAGISel::SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
860 SDValue &Offset, SDValue &Opc) {
861 unsigned Opcode = Op->getOpcode();
862 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
863 ? cast<LoadSDNode>(Op)->getAddressingMode()
864 : cast<StoreSDNode>(Op)->getAddressingMode();
865 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
866 ? ARM_AM::add : ARM_AM::sub;
868 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits.
869 Offset = CurDAG->getRegister(0, MVT::i32);
870 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
879 bool ARMDAGToDAGISel::SelectAddrOffsetNone(SDValue N, SDValue &Base) {
884 bool ARMDAGToDAGISel::SelectAddrMode3(SDValue N,
885 SDValue &Base, SDValue &Offset,
887 if (N.getOpcode() == ISD::SUB) {
888 // X - C is canonicalize to X + -C, no need to handle it here.
889 Base = N.getOperand(0);
890 Offset = N.getOperand(1);
891 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
895 if (!CurDAG->isBaseWithConstantOffset(N)) {
897 if (N.getOpcode() == ISD::FrameIndex) {
898 int FI = cast<FrameIndexSDNode>(N)->getIndex();
899 Base = CurDAG->getTargetFrameIndex(FI,
900 getTargetLowering()->getPointerTy());
902 Offset = CurDAG->getRegister(0, MVT::i32);
903 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
907 // If the RHS is +/- imm8, fold into addr mode.
909 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
910 -256 + 1, 256, RHSC)) { // 8 bits.
911 Base = N.getOperand(0);
912 if (Base.getOpcode() == ISD::FrameIndex) {
913 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
914 Base = CurDAG->getTargetFrameIndex(FI,
915 getTargetLowering()->getPointerTy());
917 Offset = CurDAG->getRegister(0, MVT::i32);
919 ARM_AM::AddrOpc AddSub = ARM_AM::add;
921 AddSub = ARM_AM::sub;
924 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
928 Base = N.getOperand(0);
929 Offset = N.getOperand(1);
930 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
934 bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N,
935 SDValue &Offset, SDValue &Opc) {
936 unsigned Opcode = Op->getOpcode();
937 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
938 ? cast<LoadSDNode>(Op)->getAddressingMode()
939 : cast<StoreSDNode>(Op)->getAddressingMode();
940 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
941 ? ARM_AM::add : ARM_AM::sub;
943 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 256, Val)) { // 12 bits.
944 Offset = CurDAG->getRegister(0, MVT::i32);
945 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
950 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
954 bool ARMDAGToDAGISel::SelectAddrMode5(SDValue N,
955 SDValue &Base, SDValue &Offset) {
956 if (!CurDAG->isBaseWithConstantOffset(N)) {
958 if (N.getOpcode() == ISD::FrameIndex) {
959 int FI = cast<FrameIndexSDNode>(N)->getIndex();
960 Base = CurDAG->getTargetFrameIndex(FI,
961 getTargetLowering()->getPointerTy());
962 } else if (N.getOpcode() == ARMISD::Wrapper &&
963 N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress) {
964 Base = N.getOperand(0);
966 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
971 // If the RHS is +/- imm8, fold into addr mode.
973 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/4,
974 -256 + 1, 256, RHSC)) {
975 Base = N.getOperand(0);
976 if (Base.getOpcode() == ISD::FrameIndex) {
977 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
978 Base = CurDAG->getTargetFrameIndex(FI,
979 getTargetLowering()->getPointerTy());
982 ARM_AM::AddrOpc AddSub = ARM_AM::add;
984 AddSub = ARM_AM::sub;
987 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
993 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
998 bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,
1002 unsigned Alignment = 0;
1003 if (LSBaseSDNode *LSN = dyn_cast<LSBaseSDNode>(Parent)) {
1004 // This case occurs only for VLD1-lane/dup and VST1-lane instructions.
1005 // The maximum alignment is equal to the memory size being referenced.
1006 unsigned LSNAlign = LSN->getAlignment();
1007 unsigned MemSize = LSN->getMemoryVT().getSizeInBits() / 8;
1008 if (LSNAlign >= MemSize && MemSize > 1)
1009 Alignment = MemSize;
1011 // All other uses of addrmode6 are for intrinsics. For now just record
1012 // the raw alignment value; it will be refined later based on the legal
1013 // alignment operands for the intrinsic.
1014 Alignment = cast<MemIntrinsicSDNode>(Parent)->getAlignment();
1017 Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
1021 bool ARMDAGToDAGISel::SelectAddrMode6Offset(SDNode *Op, SDValue N,
1023 LSBaseSDNode *LdSt = cast<LSBaseSDNode>(Op);
1024 ISD::MemIndexedMode AM = LdSt->getAddressingMode();
1025 if (AM != ISD::POST_INC)
1028 if (ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N)) {
1029 if (NC->getZExtValue() * 8 == LdSt->getMemoryVT().getSizeInBits())
1030 Offset = CurDAG->getRegister(0, MVT::i32);
1035 bool ARMDAGToDAGISel::SelectAddrModePC(SDValue N,
1036 SDValue &Offset, SDValue &Label) {
1037 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
1038 Offset = N.getOperand(0);
1039 SDValue N1 = N.getOperand(1);
1040 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
1049 //===----------------------------------------------------------------------===//
1050 // Thumb Addressing Modes
1051 //===----------------------------------------------------------------------===//
1053 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue N,
1054 SDValue &Base, SDValue &Offset){
1055 if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N)) {
1056 ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
1057 if (!NC || !NC->isNullValue())
1064 Base = N.getOperand(0);
1065 Offset = N.getOperand(1);
1070 ARMDAGToDAGISel::SelectThumbAddrModeRI(SDValue N, SDValue &Base,
1071 SDValue &Offset, unsigned Scale) {
1073 SDValue TmpBase, TmpOffImm;
1074 if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
1075 return false; // We want to select tLDRspi / tSTRspi instead.
1077 if (N.getOpcode() == ARMISD::Wrapper &&
1078 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
1079 return false; // We want to select tLDRpci instead.
1082 if (!CurDAG->isBaseWithConstantOffset(N))
1085 // Thumb does not have [sp, r] address mode.
1086 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1087 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
1088 if ((LHSR && LHSR->getReg() == ARM::SP) ||
1089 (RHSR && RHSR->getReg() == ARM::SP))
1092 // FIXME: Why do we explicitly check for a match here and then return false?
1093 // Presumably to allow something else to match, but shouldn't this be
1096 if (isScaledConstantInRange(N.getOperand(1), Scale, 0, 32, RHSC))
1099 Base = N.getOperand(0);
1100 Offset = N.getOperand(1);
1105 ARMDAGToDAGISel::SelectThumbAddrModeRI5S1(SDValue N,
1108 return SelectThumbAddrModeRI(N, Base, Offset, 1);
1112 ARMDAGToDAGISel::SelectThumbAddrModeRI5S2(SDValue N,
1115 return SelectThumbAddrModeRI(N, Base, Offset, 2);
1119 ARMDAGToDAGISel::SelectThumbAddrModeRI5S4(SDValue N,
1122 return SelectThumbAddrModeRI(N, Base, Offset, 4);
1126 ARMDAGToDAGISel::SelectThumbAddrModeImm5S(SDValue N, unsigned Scale,
1127 SDValue &Base, SDValue &OffImm) {
1129 SDValue TmpBase, TmpOffImm;
1130 if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
1131 return false; // We want to select tLDRspi / tSTRspi instead.
1133 if (N.getOpcode() == ARMISD::Wrapper &&
1134 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
1135 return false; // We want to select tLDRpci instead.
1138 if (!CurDAG->isBaseWithConstantOffset(N)) {
1139 if (N.getOpcode() == ARMISD::Wrapper &&
1140 N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress) {
1141 Base = N.getOperand(0);
1146 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1150 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1151 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
1152 if ((LHSR && LHSR->getReg() == ARM::SP) ||
1153 (RHSR && RHSR->getReg() == ARM::SP)) {
1154 ConstantSDNode *LHS = dyn_cast<ConstantSDNode>(N.getOperand(0));
1155 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
1156 unsigned LHSC = LHS ? LHS->getZExtValue() : 0;
1157 unsigned RHSC = RHS ? RHS->getZExtValue() : 0;
1159 // Thumb does not have [sp, #imm5] address mode for non-zero imm5.
1160 if (LHSC != 0 || RHSC != 0) return false;
1163 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1167 // If the RHS is + imm5 * scale, fold into addr mode.
1169 if (isScaledConstantInRange(N.getOperand(1), Scale, 0, 32, RHSC)) {
1170 Base = N.getOperand(0);
1171 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1175 Base = N.getOperand(0);
1176 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1181 ARMDAGToDAGISel::SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
1183 return SelectThumbAddrModeImm5S(N, 4, Base, OffImm);
1187 ARMDAGToDAGISel::SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
1189 return SelectThumbAddrModeImm5S(N, 2, Base, OffImm);
1193 ARMDAGToDAGISel::SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
1195 return SelectThumbAddrModeImm5S(N, 1, Base, OffImm);
1198 bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue N,
1199 SDValue &Base, SDValue &OffImm) {
1200 if (N.getOpcode() == ISD::FrameIndex) {
1201 int FI = cast<FrameIndexSDNode>(N)->getIndex();
1202 Base = CurDAG->getTargetFrameIndex(FI,
1203 getTargetLowering()->getPointerTy());
1204 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1208 if (!CurDAG->isBaseWithConstantOffset(N))
1211 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1212 if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
1213 (LHSR && LHSR->getReg() == ARM::SP)) {
1214 // If the RHS is + imm8 * scale, fold into addr mode.
1216 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/4, 0, 256, RHSC)) {
1217 Base = N.getOperand(0);
1218 if (Base.getOpcode() == ISD::FrameIndex) {
1219 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1220 Base = CurDAG->getTargetFrameIndex(FI,
1221 getTargetLowering()->getPointerTy());
1223 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1232 //===----------------------------------------------------------------------===//
1233 // Thumb 2 Addressing Modes
1234 //===----------------------------------------------------------------------===//
1237 bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue N, SDValue &BaseReg,
1239 if (DisableShifterOp)
1242 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
1244 // Don't match base register only case. That is matched to a separate
1245 // lower complexity pattern with explicit register operand.
1246 if (ShOpcVal == ARM_AM::no_shift) return false;
1248 BaseReg = N.getOperand(0);
1249 unsigned ShImmVal = 0;
1250 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1251 ShImmVal = RHS->getZExtValue() & 31;
1252 Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
1259 bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue N,
1260 SDValue &Base, SDValue &OffImm) {
1261 // Match simple R + imm12 operands.
1264 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1265 !CurDAG->isBaseWithConstantOffset(N)) {
1266 if (N.getOpcode() == ISD::FrameIndex) {
1267 // Match frame index.
1268 int FI = cast<FrameIndexSDNode>(N)->getIndex();
1269 Base = CurDAG->getTargetFrameIndex(FI,
1270 getTargetLowering()->getPointerTy());
1271 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1275 if (N.getOpcode() == ARMISD::Wrapper &&
1276 N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress) {
1277 Base = N.getOperand(0);
1278 if (Base.getOpcode() == ISD::TargetConstantPool)
1279 return false; // We want to select t2LDRpci instead.
1282 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1286 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1287 if (SelectT2AddrModeImm8(N, Base, OffImm))
1288 // Let t2LDRi8 handle (R - imm8).
1291 int RHSC = (int)RHS->getZExtValue();
1292 if (N.getOpcode() == ISD::SUB)
1295 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
1296 Base = N.getOperand(0);
1297 if (Base.getOpcode() == ISD::FrameIndex) {
1298 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1299 Base = CurDAG->getTargetFrameIndex(FI,
1300 getTargetLowering()->getPointerTy());
1302 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1309 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1313 bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue N,
1314 SDValue &Base, SDValue &OffImm) {
1315 // Match simple R - imm8 operands.
1316 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1317 !CurDAG->isBaseWithConstantOffset(N))
1320 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1321 int RHSC = (int)RHS->getSExtValue();
1322 if (N.getOpcode() == ISD::SUB)
1325 if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative)
1326 Base = N.getOperand(0);
1327 if (Base.getOpcode() == ISD::FrameIndex) {
1328 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1329 Base = CurDAG->getTargetFrameIndex(FI,
1330 getTargetLowering()->getPointerTy());
1332 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1340 bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
1342 unsigned Opcode = Op->getOpcode();
1343 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
1344 ? cast<LoadSDNode>(Op)->getAddressingMode()
1345 : cast<StoreSDNode>(Op)->getAddressingMode();
1347 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x100, RHSC)) { // 8 bits.
1348 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
1349 ? CurDAG->getTargetConstant(RHSC, MVT::i32)
1350 : CurDAG->getTargetConstant(-RHSC, MVT::i32);
1357 bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue N,
1359 SDValue &OffReg, SDValue &ShImm) {
1360 // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.
1361 if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N))
1364 // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8.
1365 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1366 int RHSC = (int)RHS->getZExtValue();
1367 if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned)
1369 else if (RHSC < 0 && RHSC >= -255) // 8 bits
1373 // Look for (R + R) or (R + (R << [1,2,3])).
1375 Base = N.getOperand(0);
1376 OffReg = N.getOperand(1);
1378 // Swap if it is ((R << c) + R).
1379 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode());
1380 if (ShOpcVal != ARM_AM::lsl) {
1381 ShOpcVal = ARM_AM::getShiftOpcForNode(Base.getOpcode());
1382 if (ShOpcVal == ARM_AM::lsl)
1383 std::swap(Base, OffReg);
1386 if (ShOpcVal == ARM_AM::lsl) {
1387 // Check to see if the RHS of the shift is a constant, if not, we can't fold
1389 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
1390 ShAmt = Sh->getZExtValue();
1391 if (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt))
1392 OffReg = OffReg.getOperand(0);
1395 ShOpcVal = ARM_AM::no_shift;
1398 ShOpcVal = ARM_AM::no_shift;
1402 ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
1407 bool ARMDAGToDAGISel::SelectT2AddrModeExclusive(SDValue N, SDValue &Base,
1409 // This *must* succeed since it's used for the irreplaceable ldrex and strex
1412 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1414 if (N.getOpcode() != ISD::ADD || !CurDAG->isBaseWithConstantOffset(N))
1417 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
1421 uint32_t RHSC = (int)RHS->getZExtValue();
1422 if (RHSC > 1020 || RHSC % 4 != 0)
1425 Base = N.getOperand(0);
1426 if (Base.getOpcode() == ISD::FrameIndex) {
1427 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1428 Base = CurDAG->getTargetFrameIndex(FI, getTargetLowering()->getPointerTy());
1431 OffImm = CurDAG->getTargetConstant(RHSC / 4, MVT::i32);
1435 //===--------------------------------------------------------------------===//
1437 /// getAL - Returns a ARMCC::AL immediate node.
1438 static inline SDValue getAL(SelectionDAG *CurDAG) {
1439 return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
1442 SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDNode *N) {
1443 LoadSDNode *LD = cast<LoadSDNode>(N);
1444 ISD::MemIndexedMode AM = LD->getAddressingMode();
1445 if (AM == ISD::UNINDEXED)
1448 EVT LoadedVT = LD->getMemoryVT();
1449 SDValue Offset, AMOpc;
1450 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1451 unsigned Opcode = 0;
1453 if (LoadedVT == MVT::i32 && isPre &&
1454 SelectAddrMode2OffsetImmPre(N, LD->getOffset(), Offset, AMOpc)) {
1455 Opcode = ARM::LDR_PRE_IMM;
1457 } else if (LoadedVT == MVT::i32 && !isPre &&
1458 SelectAddrMode2OffsetImm(N, LD->getOffset(), Offset, AMOpc)) {
1459 Opcode = ARM::LDR_POST_IMM;
1461 } else if (LoadedVT == MVT::i32 &&
1462 SelectAddrMode2OffsetReg(N, LD->getOffset(), Offset, AMOpc)) {
1463 Opcode = isPre ? ARM::LDR_PRE_REG : ARM::LDR_POST_REG;
1466 } else if (LoadedVT == MVT::i16 &&
1467 SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1469 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
1470 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
1471 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
1472 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
1473 if (LD->getExtensionType() == ISD::SEXTLOAD) {
1474 if (SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1476 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
1480 SelectAddrMode2OffsetImmPre(N, LD->getOffset(), Offset, AMOpc)) {
1482 Opcode = ARM::LDRB_PRE_IMM;
1483 } else if (!isPre &&
1484 SelectAddrMode2OffsetImm(N, LD->getOffset(), Offset, AMOpc)) {
1486 Opcode = ARM::LDRB_POST_IMM;
1487 } else if (SelectAddrMode2OffsetReg(N, LD->getOffset(), Offset, AMOpc)) {
1489 Opcode = isPre ? ARM::LDRB_PRE_REG : ARM::LDRB_POST_REG;
1495 if (Opcode == ARM::LDR_PRE_IMM || Opcode == ARM::LDRB_PRE_IMM) {
1496 SDValue Chain = LD->getChain();
1497 SDValue Base = LD->getBasePtr();
1498 SDValue Ops[]= { Base, AMOpc, getAL(CurDAG),
1499 CurDAG->getRegister(0, MVT::i32), Chain };
1500 return CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i32,
1501 MVT::i32, MVT::Other, Ops);
1503 SDValue Chain = LD->getChain();
1504 SDValue Base = LD->getBasePtr();
1505 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
1506 CurDAG->getRegister(0, MVT::i32), Chain };
1507 return CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i32,
1508 MVT::i32, MVT::Other, Ops);
1515 SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDNode *N) {
1516 LoadSDNode *LD = cast<LoadSDNode>(N);
1517 ISD::MemIndexedMode AM = LD->getAddressingMode();
1518 if (AM == ISD::UNINDEXED)
1521 EVT LoadedVT = LD->getMemoryVT();
1522 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
1524 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1525 unsigned Opcode = 0;
1527 if (SelectT2AddrModeImm8Offset(N, LD->getOffset(), Offset)) {
1528 switch (LoadedVT.getSimpleVT().SimpleTy) {
1530 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
1534 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
1536 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
1541 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
1543 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
1552 SDValue Chain = LD->getChain();
1553 SDValue Base = LD->getBasePtr();
1554 SDValue Ops[]= { Base, Offset, getAL(CurDAG),
1555 CurDAG->getRegister(0, MVT::i32), Chain };
1556 return CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i32, MVT::i32,
1563 /// \brief Form a GPRPair pseudo register from a pair of GPR regs.
1564 SDNode *ARMDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) {
1565 SDLoc dl(V0.getNode());
1567 CurDAG->getTargetConstant(ARM::GPRPairRegClassID, MVT::i32);
1568 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::gsub_0, MVT::i32);
1569 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::gsub_1, MVT::i32);
1570 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1571 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1574 /// \brief Form a D register from a pair of S registers.
1575 SDNode *ARMDAGToDAGISel::createSRegPairNode(EVT VT, SDValue V0, SDValue V1) {
1576 SDLoc dl(V0.getNode());
1578 CurDAG->getTargetConstant(ARM::DPR_VFP2RegClassID, MVT::i32);
1579 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1580 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1581 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1582 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1585 /// \brief Form a quad register from a pair of D registers.
1586 SDNode *ARMDAGToDAGISel::createDRegPairNode(EVT VT, SDValue V0, SDValue V1) {
1587 SDLoc dl(V0.getNode());
1588 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, MVT::i32);
1589 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1590 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1591 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1592 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1595 /// \brief Form 4 consecutive D registers from a pair of Q registers.
1596 SDNode *ARMDAGToDAGISel::createQRegPairNode(EVT VT, SDValue V0, SDValue V1) {
1597 SDLoc dl(V0.getNode());
1598 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32);
1599 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1600 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1601 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1602 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1605 /// \brief Form 4 consecutive S registers.
1606 SDNode *ARMDAGToDAGISel::createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1,
1607 SDValue V2, SDValue V3) {
1608 SDLoc dl(V0.getNode());
1610 CurDAG->getTargetConstant(ARM::QPR_VFP2RegClassID, MVT::i32);
1611 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1612 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1613 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, MVT::i32);
1614 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::ssub_3, MVT::i32);
1615 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1616 V2, SubReg2, V3, SubReg3 };
1617 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1620 /// \brief Form 4 consecutive D registers.
1621 SDNode *ARMDAGToDAGISel::createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1,
1622 SDValue V2, SDValue V3) {
1623 SDLoc dl(V0.getNode());
1624 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32);
1625 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1626 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1627 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, MVT::i32);
1628 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, MVT::i32);
1629 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1630 V2, SubReg2, V3, SubReg3 };
1631 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1634 /// \brief Form 4 consecutive Q registers.
1635 SDNode *ARMDAGToDAGISel::createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1,
1636 SDValue V2, SDValue V3) {
1637 SDLoc dl(V0.getNode());
1638 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, MVT::i32);
1639 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1640 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1641 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, MVT::i32);
1642 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, MVT::i32);
1643 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1644 V2, SubReg2, V3, SubReg3 };
1645 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1648 /// GetVLDSTAlign - Get the alignment (in bytes) for the alignment operand
1649 /// of a NEON VLD or VST instruction. The supported values depend on the
1650 /// number of registers being loaded.
1651 SDValue ARMDAGToDAGISel::GetVLDSTAlign(SDValue Align, unsigned NumVecs,
1652 bool is64BitVector) {
1653 unsigned NumRegs = NumVecs;
1654 if (!is64BitVector && NumVecs < 3)
1657 unsigned Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1658 if (Alignment >= 32 && NumRegs == 4)
1660 else if (Alignment >= 16 && (NumRegs == 2 || NumRegs == 4))
1662 else if (Alignment >= 8)
1667 return CurDAG->getTargetConstant(Alignment, MVT::i32);
1670 static bool isVLDfixed(unsigned Opc)
1673 default: return false;
1674 case ARM::VLD1d8wb_fixed : return true;
1675 case ARM::VLD1d16wb_fixed : return true;
1676 case ARM::VLD1d64Qwb_fixed : return true;
1677 case ARM::VLD1d32wb_fixed : return true;
1678 case ARM::VLD1d64wb_fixed : return true;
1679 case ARM::VLD1d64TPseudoWB_fixed : return true;
1680 case ARM::VLD1d64QPseudoWB_fixed : return true;
1681 case ARM::VLD1q8wb_fixed : return true;
1682 case ARM::VLD1q16wb_fixed : return true;
1683 case ARM::VLD1q32wb_fixed : return true;
1684 case ARM::VLD1q64wb_fixed : return true;
1685 case ARM::VLD2d8wb_fixed : return true;
1686 case ARM::VLD2d16wb_fixed : return true;
1687 case ARM::VLD2d32wb_fixed : return true;
1688 case ARM::VLD2q8PseudoWB_fixed : return true;
1689 case ARM::VLD2q16PseudoWB_fixed : return true;
1690 case ARM::VLD2q32PseudoWB_fixed : return true;
1691 case ARM::VLD2DUPd8wb_fixed : return true;
1692 case ARM::VLD2DUPd16wb_fixed : return true;
1693 case ARM::VLD2DUPd32wb_fixed : return true;
1697 static bool isVSTfixed(unsigned Opc)
1700 default: return false;
1701 case ARM::VST1d8wb_fixed : return true;
1702 case ARM::VST1d16wb_fixed : return true;
1703 case ARM::VST1d32wb_fixed : return true;
1704 case ARM::VST1d64wb_fixed : return true;
1705 case ARM::VST1q8wb_fixed : return true;
1706 case ARM::VST1q16wb_fixed : return true;
1707 case ARM::VST1q32wb_fixed : return true;
1708 case ARM::VST1q64wb_fixed : return true;
1709 case ARM::VST1d64TPseudoWB_fixed : return true;
1710 case ARM::VST1d64QPseudoWB_fixed : return true;
1711 case ARM::VST2d8wb_fixed : return true;
1712 case ARM::VST2d16wb_fixed : return true;
1713 case ARM::VST2d32wb_fixed : return true;
1714 case ARM::VST2q8PseudoWB_fixed : return true;
1715 case ARM::VST2q16PseudoWB_fixed : return true;
1716 case ARM::VST2q32PseudoWB_fixed : return true;
1720 // Get the register stride update opcode of a VLD/VST instruction that
1721 // is otherwise equivalent to the given fixed stride updating instruction.
1722 static unsigned getVLDSTRegisterUpdateOpcode(unsigned Opc) {
1723 assert((isVLDfixed(Opc) || isVSTfixed(Opc))
1724 && "Incorrect fixed stride updating instruction.");
1727 case ARM::VLD1d8wb_fixed: return ARM::VLD1d8wb_register;
1728 case ARM::VLD1d16wb_fixed: return ARM::VLD1d16wb_register;
1729 case ARM::VLD1d32wb_fixed: return ARM::VLD1d32wb_register;
1730 case ARM::VLD1d64wb_fixed: return ARM::VLD1d64wb_register;
1731 case ARM::VLD1q8wb_fixed: return ARM::VLD1q8wb_register;
1732 case ARM::VLD1q16wb_fixed: return ARM::VLD1q16wb_register;
1733 case ARM::VLD1q32wb_fixed: return ARM::VLD1q32wb_register;
1734 case ARM::VLD1q64wb_fixed: return ARM::VLD1q64wb_register;
1735 case ARM::VLD1d64Twb_fixed: return ARM::VLD1d64Twb_register;
1736 case ARM::VLD1d64Qwb_fixed: return ARM::VLD1d64Qwb_register;
1737 case ARM::VLD1d64TPseudoWB_fixed: return ARM::VLD1d64TPseudoWB_register;
1738 case ARM::VLD1d64QPseudoWB_fixed: return ARM::VLD1d64QPseudoWB_register;
1740 case ARM::VST1d8wb_fixed: return ARM::VST1d8wb_register;
1741 case ARM::VST1d16wb_fixed: return ARM::VST1d16wb_register;
1742 case ARM::VST1d32wb_fixed: return ARM::VST1d32wb_register;
1743 case ARM::VST1d64wb_fixed: return ARM::VST1d64wb_register;
1744 case ARM::VST1q8wb_fixed: return ARM::VST1q8wb_register;
1745 case ARM::VST1q16wb_fixed: return ARM::VST1q16wb_register;
1746 case ARM::VST1q32wb_fixed: return ARM::VST1q32wb_register;
1747 case ARM::VST1q64wb_fixed: return ARM::VST1q64wb_register;
1748 case ARM::VST1d64TPseudoWB_fixed: return ARM::VST1d64TPseudoWB_register;
1749 case ARM::VST1d64QPseudoWB_fixed: return ARM::VST1d64QPseudoWB_register;
1751 case ARM::VLD2d8wb_fixed: return ARM::VLD2d8wb_register;
1752 case ARM::VLD2d16wb_fixed: return ARM::VLD2d16wb_register;
1753 case ARM::VLD2d32wb_fixed: return ARM::VLD2d32wb_register;
1754 case ARM::VLD2q8PseudoWB_fixed: return ARM::VLD2q8PseudoWB_register;
1755 case ARM::VLD2q16PseudoWB_fixed: return ARM::VLD2q16PseudoWB_register;
1756 case ARM::VLD2q32PseudoWB_fixed: return ARM::VLD2q32PseudoWB_register;
1758 case ARM::VST2d8wb_fixed: return ARM::VST2d8wb_register;
1759 case ARM::VST2d16wb_fixed: return ARM::VST2d16wb_register;
1760 case ARM::VST2d32wb_fixed: return ARM::VST2d32wb_register;
1761 case ARM::VST2q8PseudoWB_fixed: return ARM::VST2q8PseudoWB_register;
1762 case ARM::VST2q16PseudoWB_fixed: return ARM::VST2q16PseudoWB_register;
1763 case ARM::VST2q32PseudoWB_fixed: return ARM::VST2q32PseudoWB_register;
1765 case ARM::VLD2DUPd8wb_fixed: return ARM::VLD2DUPd8wb_register;
1766 case ARM::VLD2DUPd16wb_fixed: return ARM::VLD2DUPd16wb_register;
1767 case ARM::VLD2DUPd32wb_fixed: return ARM::VLD2DUPd32wb_register;
1769 return Opc; // If not one we handle, return it unchanged.
1772 SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
1773 const uint16_t *DOpcodes,
1774 const uint16_t *QOpcodes0,
1775 const uint16_t *QOpcodes1) {
1776 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range");
1779 SDValue MemAddr, Align;
1780 unsigned AddrOpIdx = isUpdating ? 1 : 2;
1781 if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1784 SDValue Chain = N->getOperand(0);
1785 EVT VT = N->getValueType(0);
1786 bool is64BitVector = VT.is64BitVector();
1787 Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1789 unsigned OpcodeIndex;
1790 switch (VT.getSimpleVT().SimpleTy) {
1791 default: llvm_unreachable("unhandled vld type");
1792 // Double-register operations:
1793 case MVT::v8i8: OpcodeIndex = 0; break;
1794 case MVT::v4i16: OpcodeIndex = 1; break;
1796 case MVT::v2i32: OpcodeIndex = 2; break;
1797 case MVT::v1i64: OpcodeIndex = 3; break;
1798 // Quad-register operations:
1799 case MVT::v16i8: OpcodeIndex = 0; break;
1800 case MVT::v8i16: OpcodeIndex = 1; break;
1802 case MVT::v4i32: OpcodeIndex = 2; break;
1803 case MVT::v2i64: OpcodeIndex = 3;
1804 assert(NumVecs == 1 && "v2i64 type only supported for VLD1");
1812 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1815 ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts);
1817 std::vector<EVT> ResTys;
1818 ResTys.push_back(ResTy);
1820 ResTys.push_back(MVT::i32);
1821 ResTys.push_back(MVT::Other);
1823 SDValue Pred = getAL(CurDAG);
1824 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1826 SmallVector<SDValue, 7> Ops;
1828 // Double registers and VLD1/VLD2 quad registers are directly supported.
1829 if (is64BitVector || NumVecs <= 2) {
1830 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1831 QOpcodes0[OpcodeIndex]);
1832 Ops.push_back(MemAddr);
1833 Ops.push_back(Align);
1835 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1836 // FIXME: VLD1/VLD2 fixed increment doesn't need Reg0. Remove the reg0
1837 // case entirely when the rest are updated to that form, too.
1838 if ((NumVecs <= 2) && !isa<ConstantSDNode>(Inc.getNode()))
1839 Opc = getVLDSTRegisterUpdateOpcode(Opc);
1840 // FIXME: We use a VLD1 for v1i64 even if the pseudo says vld2/3/4, so
1841 // check for that explicitly too. Horribly hacky, but temporary.
1842 if ((NumVecs > 2 && !isVLDfixed(Opc)) ||
1843 !isa<ConstantSDNode>(Inc.getNode()))
1844 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1846 Ops.push_back(Pred);
1847 Ops.push_back(Reg0);
1848 Ops.push_back(Chain);
1849 VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
1852 // Otherwise, quad registers are loaded with two separate instructions,
1853 // where one loads the even registers and the other loads the odd registers.
1854 EVT AddrTy = MemAddr.getValueType();
1856 // Load the even subregs. This is always an updating load, so that it
1857 // provides the address to the second load for the odd subregs.
1859 SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy), 0);
1860 const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain };
1861 SDNode *VLdA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl,
1862 ResTy, AddrTy, MVT::Other, OpsA);
1863 Chain = SDValue(VLdA, 2);
1865 // Load the odd subregs.
1866 Ops.push_back(SDValue(VLdA, 1));
1867 Ops.push_back(Align);
1869 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1870 assert(isa<ConstantSDNode>(Inc.getNode()) &&
1871 "only constant post-increment update allowed for VLD3/4");
1873 Ops.push_back(Reg0);
1875 Ops.push_back(SDValue(VLdA, 0));
1876 Ops.push_back(Pred);
1877 Ops.push_back(Reg0);
1878 Ops.push_back(Chain);
1879 VLd = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys, Ops);
1882 // Transfer memoperands.
1883 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1884 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1885 cast<MachineSDNode>(VLd)->setMemRefs(MemOp, MemOp + 1);
1890 // Extract out the subregisters.
1891 SDValue SuperReg = SDValue(VLd, 0);
1892 assert(ARM::dsub_7 == ARM::dsub_0+7 &&
1893 ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1894 unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0);
1895 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1896 ReplaceUses(SDValue(N, Vec),
1897 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
1898 ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1));
1900 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLd, 2));
1904 SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
1905 const uint16_t *DOpcodes,
1906 const uint16_t *QOpcodes0,
1907 const uint16_t *QOpcodes1) {
1908 assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range");
1911 SDValue MemAddr, Align;
1912 unsigned AddrOpIdx = isUpdating ? 1 : 2;
1913 unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
1914 if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1917 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1918 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1920 SDValue Chain = N->getOperand(0);
1921 EVT VT = N->getOperand(Vec0Idx).getValueType();
1922 bool is64BitVector = VT.is64BitVector();
1923 Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1925 unsigned OpcodeIndex;
1926 switch (VT.getSimpleVT().SimpleTy) {
1927 default: llvm_unreachable("unhandled vst type");
1928 // Double-register operations:
1929 case MVT::v8i8: OpcodeIndex = 0; break;
1930 case MVT::v4i16: OpcodeIndex = 1; break;
1932 case MVT::v2i32: OpcodeIndex = 2; break;
1933 case MVT::v1i64: OpcodeIndex = 3; break;
1934 // Quad-register operations:
1935 case MVT::v16i8: OpcodeIndex = 0; break;
1936 case MVT::v8i16: OpcodeIndex = 1; break;
1938 case MVT::v4i32: OpcodeIndex = 2; break;
1939 case MVT::v2i64: OpcodeIndex = 3;
1940 assert(NumVecs == 1 && "v2i64 type only supported for VST1");
1944 std::vector<EVT> ResTys;
1946 ResTys.push_back(MVT::i32);
1947 ResTys.push_back(MVT::Other);
1949 SDValue Pred = getAL(CurDAG);
1950 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1951 SmallVector<SDValue, 7> Ops;
1953 // Double registers and VST1/VST2 quad registers are directly supported.
1954 if (is64BitVector || NumVecs <= 2) {
1957 SrcReg = N->getOperand(Vec0Idx);
1958 } else if (is64BitVector) {
1959 // Form a REG_SEQUENCE to force register allocation.
1960 SDValue V0 = N->getOperand(Vec0Idx + 0);
1961 SDValue V1 = N->getOperand(Vec0Idx + 1);
1963 SrcReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0);
1965 SDValue V2 = N->getOperand(Vec0Idx + 2);
1966 // If it's a vst3, form a quad D-register and leave the last part as
1968 SDValue V3 = (NumVecs == 3)
1969 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1970 : N->getOperand(Vec0Idx + 3);
1971 SrcReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);
1974 // Form a QQ register.
1975 SDValue Q0 = N->getOperand(Vec0Idx);
1976 SDValue Q1 = N->getOperand(Vec0Idx + 1);
1977 SrcReg = SDValue(createQRegPairNode(MVT::v4i64, Q0, Q1), 0);
1980 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1981 QOpcodes0[OpcodeIndex]);
1982 Ops.push_back(MemAddr);
1983 Ops.push_back(Align);
1985 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1986 // FIXME: VST1/VST2 fixed increment doesn't need Reg0. Remove the reg0
1987 // case entirely when the rest are updated to that form, too.
1988 if (NumVecs <= 2 && !isa<ConstantSDNode>(Inc.getNode()))
1989 Opc = getVLDSTRegisterUpdateOpcode(Opc);
1990 // FIXME: We use a VST1 for v1i64 even if the pseudo says vld2/3/4, so
1991 // check for that explicitly too. Horribly hacky, but temporary.
1992 if (!isa<ConstantSDNode>(Inc.getNode()))
1994 else if (NumVecs > 2 && !isVSTfixed(Opc))
1995 Ops.push_back(Reg0);
1997 Ops.push_back(SrcReg);
1998 Ops.push_back(Pred);
1999 Ops.push_back(Reg0);
2000 Ops.push_back(Chain);
2001 SDNode *VSt = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
2003 // Transfer memoperands.
2004 cast<MachineSDNode>(VSt)->setMemRefs(MemOp, MemOp + 1);
2009 // Otherwise, quad registers are stored with two separate instructions,
2010 // where one stores the even registers and the other stores the odd registers.
2012 // Form the QQQQ REG_SEQUENCE.
2013 SDValue V0 = N->getOperand(Vec0Idx + 0);
2014 SDValue V1 = N->getOperand(Vec0Idx + 1);
2015 SDValue V2 = N->getOperand(Vec0Idx + 2);
2016 SDValue V3 = (NumVecs == 3)
2017 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
2018 : N->getOperand(Vec0Idx + 3);
2019 SDValue RegSeq = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0);
2021 // Store the even D registers. This is always an updating store, so that it
2022 // provides the address to the second store for the odd subregs.
2023 const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain };
2024 SDNode *VStA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl,
2025 MemAddr.getValueType(),
2027 cast<MachineSDNode>(VStA)->setMemRefs(MemOp, MemOp + 1);
2028 Chain = SDValue(VStA, 1);
2030 // Store the odd D registers.
2031 Ops.push_back(SDValue(VStA, 0));
2032 Ops.push_back(Align);
2034 SDValue Inc = N->getOperand(AddrOpIdx + 1);
2035 assert(isa<ConstantSDNode>(Inc.getNode()) &&
2036 "only constant post-increment update allowed for VST3/4");
2038 Ops.push_back(Reg0);
2040 Ops.push_back(RegSeq);
2041 Ops.push_back(Pred);
2042 Ops.push_back(Reg0);
2043 Ops.push_back(Chain);
2044 SDNode *VStB = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys,
2046 cast<MachineSDNode>(VStB)->setMemRefs(MemOp, MemOp + 1);
2050 SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
2051 bool isUpdating, unsigned NumVecs,
2052 const uint16_t *DOpcodes,
2053 const uint16_t *QOpcodes) {
2054 assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
2057 SDValue MemAddr, Align;
2058 unsigned AddrOpIdx = isUpdating ? 1 : 2;
2059 unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
2060 if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
2063 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2064 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
2066 SDValue Chain = N->getOperand(0);
2068 cast<ConstantSDNode>(N->getOperand(Vec0Idx + NumVecs))->getZExtValue();
2069 EVT VT = N->getOperand(Vec0Idx).getValueType();
2070 bool is64BitVector = VT.is64BitVector();
2072 unsigned Alignment = 0;
2074 Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
2075 unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
2076 if (Alignment > NumBytes)
2077 Alignment = NumBytes;
2078 if (Alignment < 8 && Alignment < NumBytes)
2080 // Alignment must be a power of two; make sure of that.
2081 Alignment = (Alignment & -Alignment);
2085 Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
2087 unsigned OpcodeIndex;
2088 switch (VT.getSimpleVT().SimpleTy) {
2089 default: llvm_unreachable("unhandled vld/vst lane type");
2090 // Double-register operations:
2091 case MVT::v8i8: OpcodeIndex = 0; break;
2092 case MVT::v4i16: OpcodeIndex = 1; break;
2094 case MVT::v2i32: OpcodeIndex = 2; break;
2095 // Quad-register operations:
2096 case MVT::v8i16: OpcodeIndex = 0; break;
2098 case MVT::v4i32: OpcodeIndex = 1; break;
2101 std::vector<EVT> ResTys;
2103 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
2106 ResTys.push_back(EVT::getVectorVT(*CurDAG->getContext(),
2107 MVT::i64, ResTyElts));
2110 ResTys.push_back(MVT::i32);
2111 ResTys.push_back(MVT::Other);
2113 SDValue Pred = getAL(CurDAG);
2114 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2116 SmallVector<SDValue, 8> Ops;
2117 Ops.push_back(MemAddr);
2118 Ops.push_back(Align);
2120 SDValue Inc = N->getOperand(AddrOpIdx + 1);
2121 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
2125 SDValue V0 = N->getOperand(Vec0Idx + 0);
2126 SDValue V1 = N->getOperand(Vec0Idx + 1);
2129 SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0);
2131 SuperReg = SDValue(createQRegPairNode(MVT::v4i64, V0, V1), 0);
2133 SDValue V2 = N->getOperand(Vec0Idx + 2);
2134 SDValue V3 = (NumVecs == 3)
2135 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
2136 : N->getOperand(Vec0Idx + 3);
2138 SuperReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);
2140 SuperReg = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0);
2142 Ops.push_back(SuperReg);
2143 Ops.push_back(getI32Imm(Lane));
2144 Ops.push_back(Pred);
2145 Ops.push_back(Reg0);
2146 Ops.push_back(Chain);
2148 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
2149 QOpcodes[OpcodeIndex]);
2150 SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
2151 cast<MachineSDNode>(VLdLn)->setMemRefs(MemOp, MemOp + 1);
2155 // Extract the subregisters.
2156 SuperReg = SDValue(VLdLn, 0);
2157 assert(ARM::dsub_7 == ARM::dsub_0+7 &&
2158 ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
2159 unsigned Sub0 = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;
2160 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
2161 ReplaceUses(SDValue(N, Vec),
2162 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
2163 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, 1));
2165 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdLn, 2));
2169 SDNode *ARMDAGToDAGISel::SelectVLDDup(SDNode *N, bool isUpdating,
2171 const uint16_t *Opcodes) {
2172 assert(NumVecs >=2 && NumVecs <= 4 && "VLDDup NumVecs out-of-range");
2175 SDValue MemAddr, Align;
2176 if (!SelectAddrMode6(N, N->getOperand(1), MemAddr, Align))
2179 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2180 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
2182 SDValue Chain = N->getOperand(0);
2183 EVT VT = N->getValueType(0);
2185 unsigned Alignment = 0;
2187 Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
2188 unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
2189 if (Alignment > NumBytes)
2190 Alignment = NumBytes;
2191 if (Alignment < 8 && Alignment < NumBytes)
2193 // Alignment must be a power of two; make sure of that.
2194 Alignment = (Alignment & -Alignment);
2198 Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
2200 unsigned OpcodeIndex;
2201 switch (VT.getSimpleVT().SimpleTy) {
2202 default: llvm_unreachable("unhandled vld-dup type");
2203 case MVT::v8i8: OpcodeIndex = 0; break;
2204 case MVT::v4i16: OpcodeIndex = 1; break;
2206 case MVT::v2i32: OpcodeIndex = 2; break;
2209 SDValue Pred = getAL(CurDAG);
2210 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2212 unsigned Opc = Opcodes[OpcodeIndex];
2213 SmallVector<SDValue, 6> Ops;
2214 Ops.push_back(MemAddr);
2215 Ops.push_back(Align);
2217 // fixed-stride update instructions don't have an explicit writeback
2218 // operand. It's implicit in the opcode itself.
2219 SDValue Inc = N->getOperand(2);
2220 if (!isa<ConstantSDNode>(Inc.getNode()))
2222 // FIXME: VLD3 and VLD4 haven't been updated to that form yet.
2223 else if (NumVecs > 2)
2224 Ops.push_back(Reg0);
2226 Ops.push_back(Pred);
2227 Ops.push_back(Reg0);
2228 Ops.push_back(Chain);
2230 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
2231 std::vector<EVT> ResTys;
2232 ResTys.push_back(EVT::getVectorVT(*CurDAG->getContext(), MVT::i64,ResTyElts));
2234 ResTys.push_back(MVT::i32);
2235 ResTys.push_back(MVT::Other);
2236 SDNode *VLdDup = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
2237 cast<MachineSDNode>(VLdDup)->setMemRefs(MemOp, MemOp + 1);
2238 SuperReg = SDValue(VLdDup, 0);
2240 // Extract the subregisters.
2241 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2242 unsigned SubIdx = ARM::dsub_0;
2243 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
2244 ReplaceUses(SDValue(N, Vec),
2245 CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, SuperReg));
2246 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdDup, 1));
2248 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdDup, 2));
2252 SDNode *ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs,
2254 assert(NumVecs >= 2 && NumVecs <= 4 && "VTBL NumVecs out-of-range");
2256 EVT VT = N->getValueType(0);
2257 unsigned FirstTblReg = IsExt ? 2 : 1;
2259 // Form a REG_SEQUENCE to force register allocation.
2261 SDValue V0 = N->getOperand(FirstTblReg + 0);
2262 SDValue V1 = N->getOperand(FirstTblReg + 1);
2264 RegSeq = SDValue(createDRegPairNode(MVT::v16i8, V0, V1), 0);
2266 SDValue V2 = N->getOperand(FirstTblReg + 2);
2267 // If it's a vtbl3, form a quad D-register and leave the last part as
2269 SDValue V3 = (NumVecs == 3)
2270 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
2271 : N->getOperand(FirstTblReg + 3);
2272 RegSeq = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);
2275 SmallVector<SDValue, 6> Ops;
2277 Ops.push_back(N->getOperand(1));
2278 Ops.push_back(RegSeq);
2279 Ops.push_back(N->getOperand(FirstTblReg + NumVecs));
2280 Ops.push_back(getAL(CurDAG)); // predicate
2281 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // predicate register
2282 return CurDAG->getMachineNode(Opc, dl, VT, Ops);
2285 SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N,
2287 if (!Subtarget->hasV6T2Ops())
2290 unsigned Opc = isSigned
2291 ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX)
2292 : (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX);
2294 // For unsigned extracts, check for a shift right and mask
2295 unsigned And_imm = 0;
2296 if (N->getOpcode() == ISD::AND) {
2297 if (isOpcWithIntImmediate(N, ISD::AND, And_imm)) {
2299 // The immediate is a mask of the low bits iff imm & (imm+1) == 0
2300 if (And_imm & (And_imm + 1))
2303 unsigned Srl_imm = 0;
2304 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL,
2306 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
2308 // Note: The width operand is encoded as width-1.
2309 unsigned Width = CountTrailingOnes_32(And_imm) - 1;
2310 unsigned LSB = Srl_imm;
2312 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2314 if ((LSB + Width + 1) == N->getValueType(0).getSizeInBits()) {
2315 // It's cheaper to use a right shift to extract the top bits.
2316 if (Subtarget->isThumb()) {
2317 Opc = isSigned ? ARM::t2ASRri : ARM::t2LSRri;
2318 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2319 CurDAG->getTargetConstant(LSB, MVT::i32),
2320 getAL(CurDAG), Reg0, Reg0 };
2321 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
2324 // ARM models shift instructions as MOVsi with shifter operand.
2325 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(ISD::SRL);
2327 CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, LSB),
2329 SDValue Ops[] = { N->getOperand(0).getOperand(0), ShOpc,
2330 getAL(CurDAG), Reg0, Reg0 };
2331 return CurDAG->SelectNodeTo(N, ARM::MOVsi, MVT::i32, Ops);
2334 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2335 CurDAG->getTargetConstant(LSB, MVT::i32),
2336 CurDAG->getTargetConstant(Width, MVT::i32),
2337 getAL(CurDAG), Reg0 };
2338 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
2344 // Otherwise, we're looking for a shift of a shift
2345 unsigned Shl_imm = 0;
2346 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, Shl_imm)) {
2347 assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!");
2348 unsigned Srl_imm = 0;
2349 if (isInt32Immediate(N->getOperand(1), Srl_imm)) {
2350 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
2351 // Note: The width operand is encoded as width-1.
2352 unsigned Width = 32 - Srl_imm - 1;
2353 int LSB = Srl_imm - Shl_imm;
2356 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2357 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2358 CurDAG->getTargetConstant(LSB, MVT::i32),
2359 CurDAG->getTargetConstant(Width, MVT::i32),
2360 getAL(CurDAG), Reg0 };
2361 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
2365 if (N->getOpcode() == ISD::SIGN_EXTEND_INREG) {
2366 unsigned Width = cast<VTSDNode>(N->getOperand(1))->getVT().getSizeInBits();
2368 if (!isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL, LSB) &&
2369 !isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRA, LSB))
2372 if (LSB + Width > 32)
2375 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2376 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2377 CurDAG->getTargetConstant(LSB, MVT::i32),
2378 CurDAG->getTargetConstant(Width - 1, MVT::i32),
2379 getAL(CurDAG), Reg0 };
2380 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
2386 /// Target-specific DAG combining for ISD::XOR.
2387 /// Target-independent combining lowers SELECT_CC nodes of the form
2388 /// select_cc setg[ge] X, 0, X, -X
2389 /// select_cc setgt X, -1, X, -X
2390 /// select_cc setl[te] X, 0, -X, X
2391 /// select_cc setlt X, 1, -X, X
2392 /// which represent Integer ABS into:
2393 /// Y = sra (X, size(X)-1); xor (add (X, Y), Y)
2394 /// ARM instruction selection detects the latter and matches it to
2395 /// ARM::ABS or ARM::t2ABS machine node.
2396 SDNode *ARMDAGToDAGISel::SelectABSOp(SDNode *N){
2397 SDValue XORSrc0 = N->getOperand(0);
2398 SDValue XORSrc1 = N->getOperand(1);
2399 EVT VT = N->getValueType(0);
2401 if (Subtarget->isThumb1Only())
2404 if (XORSrc0.getOpcode() != ISD::ADD || XORSrc1.getOpcode() != ISD::SRA)
2407 SDValue ADDSrc0 = XORSrc0.getOperand(0);
2408 SDValue ADDSrc1 = XORSrc0.getOperand(1);
2409 SDValue SRASrc0 = XORSrc1.getOperand(0);
2410 SDValue SRASrc1 = XORSrc1.getOperand(1);
2411 ConstantSDNode *SRAConstant = dyn_cast<ConstantSDNode>(SRASrc1);
2412 EVT XType = SRASrc0.getValueType();
2413 unsigned Size = XType.getSizeInBits() - 1;
2415 if (ADDSrc1 == XORSrc1 && ADDSrc0 == SRASrc0 &&
2416 XType.isInteger() && SRAConstant != nullptr &&
2417 Size == SRAConstant->getZExtValue()) {
2418 unsigned Opcode = Subtarget->isThumb2() ? ARM::t2ABS : ARM::ABS;
2419 return CurDAG->SelectNodeTo(N, Opcode, VT, ADDSrc0);
2425 SDNode *ARMDAGToDAGISel::SelectConcatVector(SDNode *N) {
2426 // The only time a CONCAT_VECTORS operation can have legal types is when
2427 // two 64-bit vectors are concatenated to a 128-bit vector.
2428 EVT VT = N->getValueType(0);
2429 if (!VT.is128BitVector() || N->getNumOperands() != 2)
2430 llvm_unreachable("unexpected CONCAT_VECTORS");
2431 return createDRegPairNode(VT, N->getOperand(0), N->getOperand(1));
2434 SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
2437 if (N->isMachineOpcode()) {
2439 return nullptr; // Already selected.
2442 switch (N->getOpcode()) {
2444 case ISD::INLINEASM: {
2445 SDNode *ResNode = SelectInlineAsm(N);
2451 // Select special operations if XOR node forms integer ABS pattern
2452 SDNode *ResNode = SelectABSOp(N);
2455 // Other cases are autogenerated.
2458 case ISD::Constant: {
2459 unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
2461 if (Subtarget->useMovt(*MF))
2462 // Thumb2-aware targets have the MOVT instruction, so all immediates can
2463 // be done with MOV + MOVT, at worst.
2466 if (Subtarget->isThumb()) {
2467 UseCP = (Val > 255 && // MOV
2468 ~Val > 255 && // MOV + MVN
2469 !ARM_AM::isThumbImmShiftedVal(Val) && // MOV + LSL
2470 !(Subtarget->hasV6T2Ops() && Val <= 0xffff)); // MOVW
2472 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
2473 ARM_AM::getSOImmVal(~Val) == -1 && // MVN
2474 !ARM_AM::isSOImmTwoPartVal(Val) && // two instrs.
2475 !(Subtarget->hasV6T2Ops() && Val <= 0xffff)); // MOVW
2480 CurDAG->getTargetConstantPool(ConstantInt::get(
2481 Type::getInt32Ty(*CurDAG->getContext()), Val),
2482 getTargetLowering()->getPointerTy());
2485 if (Subtarget->isThumb()) {
2486 SDValue Pred = getAL(CurDAG);
2487 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2488 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
2489 ResNode = CurDAG->getMachineNode(ARM::tLDRpci, dl, MVT::i32, MVT::Other,
2494 CurDAG->getTargetConstant(0, MVT::i32),
2496 CurDAG->getRegister(0, MVT::i32),
2497 CurDAG->getEntryNode()
2499 ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
2502 ReplaceUses(SDValue(N, 0), SDValue(ResNode, 0));
2506 // Other cases are autogenerated.
2509 case ISD::FrameIndex: {
2510 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
2511 int FI = cast<FrameIndexSDNode>(N)->getIndex();
2512 SDValue TFI = CurDAG->getTargetFrameIndex(FI,
2513 getTargetLowering()->getPointerTy());
2514 if (Subtarget->isThumb1Only()) {
2515 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
2516 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2517 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, Ops);
2519 unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
2520 ARM::t2ADDri : ARM::ADDri);
2521 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
2522 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2523 CurDAG->getRegister(0, MVT::i32) };
2524 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
2528 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2531 case ISD::SIGN_EXTEND_INREG:
2533 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, true))
2537 if (Subtarget->isThumb1Only())
2539 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
2540 unsigned RHSV = C->getZExtValue();
2542 if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
2543 unsigned ShImm = Log2_32(RHSV-1);
2546 SDValue V = N->getOperand(0);
2547 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2548 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2549 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2550 if (Subtarget->isThumb()) {
2551 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2552 return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops);
2554 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2555 return CurDAG->SelectNodeTo(N, ARM::ADDrsi, MVT::i32, Ops);
2558 if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
2559 unsigned ShImm = Log2_32(RHSV+1);
2562 SDValue V = N->getOperand(0);
2563 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2564 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2565 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2566 if (Subtarget->isThumb()) {
2567 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2568 return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops);
2570 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2571 return CurDAG->SelectNodeTo(N, ARM::RSBrsi, MVT::i32, Ops);
2577 // Check for unsigned bitfield extract
2578 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2581 // (and (or x, c2), c1) and top 16-bits of c1 and c2 match, lower 16-bits
2582 // of c1 are 0xffff, and lower 16-bit of c2 are 0. That is, the top 16-bits
2583 // are entirely contributed by c2 and lower 16-bits are entirely contributed
2584 // by x. That's equal to (or (and x, 0xffff), (and c1, 0xffff0000)).
2585 // Select it to: "movt x, ((c1 & 0xffff) >> 16)
2586 EVT VT = N->getValueType(0);
2589 unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2())
2591 : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0);
2594 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2595 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2598 if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) {
2599 SDValue N2 = N0.getOperand(1);
2600 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2603 unsigned N1CVal = N1C->getZExtValue();
2604 unsigned N2CVal = N2C->getZExtValue();
2605 if ((N1CVal & 0xffff0000U) == (N2CVal & 0xffff0000U) &&
2606 (N1CVal & 0xffffU) == 0xffffU &&
2607 (N2CVal & 0xffffU) == 0x0U) {
2608 SDValue Imm16 = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16,
2610 SDValue Ops[] = { N0.getOperand(0), Imm16,
2611 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2612 return CurDAG->getMachineNode(Opc, dl, VT, Ops);
2617 case ARMISD::VMOVRRD:
2618 return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32,
2619 N->getOperand(0), getAL(CurDAG),
2620 CurDAG->getRegister(0, MVT::i32));
2621 case ISD::UMUL_LOHI: {
2622 if (Subtarget->isThumb1Only())
2624 if (Subtarget->isThumb()) {
2625 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2626 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2627 return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32, Ops);
2629 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2630 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2631 CurDAG->getRegister(0, MVT::i32) };
2632 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2633 ARM::UMULL : ARM::UMULLv5,
2634 dl, MVT::i32, MVT::i32, Ops);
2637 case ISD::SMUL_LOHI: {
2638 if (Subtarget->isThumb1Only())
2640 if (Subtarget->isThumb()) {
2641 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2642 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2643 return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32, Ops);
2645 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2646 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2647 CurDAG->getRegister(0, MVT::i32) };
2648 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2649 ARM::SMULL : ARM::SMULLv5,
2650 dl, MVT::i32, MVT::i32, Ops);
2653 case ARMISD::UMLAL:{
2654 if (Subtarget->isThumb()) {
2655 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
2656 N->getOperand(3), getAL(CurDAG),
2657 CurDAG->getRegister(0, MVT::i32)};
2658 return CurDAG->getMachineNode(ARM::t2UMLAL, dl, MVT::i32, MVT::i32, Ops);
2660 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
2661 N->getOperand(3), getAL(CurDAG),
2662 CurDAG->getRegister(0, MVT::i32),
2663 CurDAG->getRegister(0, MVT::i32) };
2664 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2665 ARM::UMLAL : ARM::UMLALv5,
2666 dl, MVT::i32, MVT::i32, Ops);
2669 case ARMISD::SMLAL:{
2670 if (Subtarget->isThumb()) {
2671 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
2672 N->getOperand(3), getAL(CurDAG),
2673 CurDAG->getRegister(0, MVT::i32)};
2674 return CurDAG->getMachineNode(ARM::t2SMLAL, dl, MVT::i32, MVT::i32, Ops);
2676 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
2677 N->getOperand(3), getAL(CurDAG),
2678 CurDAG->getRegister(0, MVT::i32),
2679 CurDAG->getRegister(0, MVT::i32) };
2680 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2681 ARM::SMLAL : ARM::SMLALv5,
2682 dl, MVT::i32, MVT::i32, Ops);
2686 SDNode *ResNode = nullptr;
2687 if (Subtarget->isThumb() && Subtarget->hasThumb2())
2688 ResNode = SelectT2IndexedLoad(N);
2690 ResNode = SelectARMIndexedLoad(N);
2693 // Other cases are autogenerated.
2696 case ARMISD::BRCOND: {
2697 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2698 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2699 // Pattern complexity = 6 cost = 1 size = 0
2701 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2702 // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
2703 // Pattern complexity = 6 cost = 1 size = 0
2705 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2706 // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2707 // Pattern complexity = 6 cost = 1 size = 0
2709 unsigned Opc = Subtarget->isThumb() ?
2710 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
2711 SDValue Chain = N->getOperand(0);
2712 SDValue N1 = N->getOperand(1);
2713 SDValue N2 = N->getOperand(2);
2714 SDValue N3 = N->getOperand(3);
2715 SDValue InFlag = N->getOperand(4);
2716 assert(N1.getOpcode() == ISD::BasicBlock);
2717 assert(N2.getOpcode() == ISD::Constant);
2718 assert(N3.getOpcode() == ISD::Register);
2720 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
2721 cast<ConstantSDNode>(N2)->getZExtValue()),
2723 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
2724 SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,
2726 Chain = SDValue(ResNode, 0);
2727 if (N->getNumValues() == 2) {
2728 InFlag = SDValue(ResNode, 1);
2729 ReplaceUses(SDValue(N, 1), InFlag);
2731 ReplaceUses(SDValue(N, 0),
2732 SDValue(Chain.getNode(), Chain.getResNo()));
2735 case ARMISD::VZIP: {
2737 EVT VT = N->getValueType(0);
2738 switch (VT.getSimpleVT().SimpleTy) {
2739 default: return nullptr;
2740 case MVT::v8i8: Opc = ARM::VZIPd8; break;
2741 case MVT::v4i16: Opc = ARM::VZIPd16; break;
2743 // vzip.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.
2744 case MVT::v2i32: Opc = ARM::VTRNd32; break;
2745 case MVT::v16i8: Opc = ARM::VZIPq8; break;
2746 case MVT::v8i16: Opc = ARM::VZIPq16; break;
2748 case MVT::v4i32: Opc = ARM::VZIPq32; break;
2750 SDValue Pred = getAL(CurDAG);
2751 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2752 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2753 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops);
2755 case ARMISD::VUZP: {
2757 EVT VT = N->getValueType(0);
2758 switch (VT.getSimpleVT().SimpleTy) {
2759 default: return nullptr;
2760 case MVT::v8i8: Opc = ARM::VUZPd8; break;
2761 case MVT::v4i16: Opc = ARM::VUZPd16; break;
2763 // vuzp.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.
2764 case MVT::v2i32: Opc = ARM::VTRNd32; break;
2765 case MVT::v16i8: Opc = ARM::VUZPq8; break;
2766 case MVT::v8i16: Opc = ARM::VUZPq16; break;
2768 case MVT::v4i32: Opc = ARM::VUZPq32; break;
2770 SDValue Pred = getAL(CurDAG);
2771 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2772 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2773 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops);
2775 case ARMISD::VTRN: {
2777 EVT VT = N->getValueType(0);
2778 switch (VT.getSimpleVT().SimpleTy) {
2779 default: return nullptr;
2780 case MVT::v8i8: Opc = ARM::VTRNd8; break;
2781 case MVT::v4i16: Opc = ARM::VTRNd16; break;
2783 case MVT::v2i32: Opc = ARM::VTRNd32; break;
2784 case MVT::v16i8: Opc = ARM::VTRNq8; break;
2785 case MVT::v8i16: Opc = ARM::VTRNq16; break;
2787 case MVT::v4i32: Opc = ARM::VTRNq32; break;
2789 SDValue Pred = getAL(CurDAG);
2790 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2791 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2792 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops);
2794 case ARMISD::BUILD_VECTOR: {
2795 EVT VecVT = N->getValueType(0);
2796 EVT EltVT = VecVT.getVectorElementType();
2797 unsigned NumElts = VecVT.getVectorNumElements();
2798 if (EltVT == MVT::f64) {
2799 assert(NumElts == 2 && "unexpected type for BUILD_VECTOR");
2800 return createDRegPairNode(VecVT, N->getOperand(0), N->getOperand(1));
2802 assert(EltVT == MVT::f32 && "unexpected type for BUILD_VECTOR");
2804 return createSRegPairNode(VecVT, N->getOperand(0), N->getOperand(1));
2805 assert(NumElts == 4 && "unexpected type for BUILD_VECTOR");
2806 return createQuadSRegsNode(VecVT, N->getOperand(0), N->getOperand(1),
2807 N->getOperand(2), N->getOperand(3));
2810 case ARMISD::VLD2DUP: {
2811 static const uint16_t Opcodes[] = { ARM::VLD2DUPd8, ARM::VLD2DUPd16,
2813 return SelectVLDDup(N, false, 2, Opcodes);
2816 case ARMISD::VLD3DUP: {
2817 static const uint16_t Opcodes[] = { ARM::VLD3DUPd8Pseudo,
2818 ARM::VLD3DUPd16Pseudo,
2819 ARM::VLD3DUPd32Pseudo };
2820 return SelectVLDDup(N, false, 3, Opcodes);
2823 case ARMISD::VLD4DUP: {
2824 static const uint16_t Opcodes[] = { ARM::VLD4DUPd8Pseudo,
2825 ARM::VLD4DUPd16Pseudo,
2826 ARM::VLD4DUPd32Pseudo };
2827 return SelectVLDDup(N, false, 4, Opcodes);
2830 case ARMISD::VLD2DUP_UPD: {
2831 static const uint16_t Opcodes[] = { ARM::VLD2DUPd8wb_fixed,
2832 ARM::VLD2DUPd16wb_fixed,
2833 ARM::VLD2DUPd32wb_fixed };
2834 return SelectVLDDup(N, true, 2, Opcodes);
2837 case ARMISD::VLD3DUP_UPD: {
2838 static const uint16_t Opcodes[] = { ARM::VLD3DUPd8Pseudo_UPD,
2839 ARM::VLD3DUPd16Pseudo_UPD,
2840 ARM::VLD3DUPd32Pseudo_UPD };
2841 return SelectVLDDup(N, true, 3, Opcodes);
2844 case ARMISD::VLD4DUP_UPD: {
2845 static const uint16_t Opcodes[] = { ARM::VLD4DUPd8Pseudo_UPD,
2846 ARM::VLD4DUPd16Pseudo_UPD,
2847 ARM::VLD4DUPd32Pseudo_UPD };
2848 return SelectVLDDup(N, true, 4, Opcodes);
2851 case ARMISD::VLD1_UPD: {
2852 static const uint16_t DOpcodes[] = { ARM::VLD1d8wb_fixed,
2853 ARM::VLD1d16wb_fixed,
2854 ARM::VLD1d32wb_fixed,
2855 ARM::VLD1d64wb_fixed };
2856 static const uint16_t QOpcodes[] = { ARM::VLD1q8wb_fixed,
2857 ARM::VLD1q16wb_fixed,
2858 ARM::VLD1q32wb_fixed,
2859 ARM::VLD1q64wb_fixed };
2860 return SelectVLD(N, true, 1, DOpcodes, QOpcodes, nullptr);
2863 case ARMISD::VLD2_UPD: {
2864 static const uint16_t DOpcodes[] = { ARM::VLD2d8wb_fixed,
2865 ARM::VLD2d16wb_fixed,
2866 ARM::VLD2d32wb_fixed,
2867 ARM::VLD1q64wb_fixed};
2868 static const uint16_t QOpcodes[] = { ARM::VLD2q8PseudoWB_fixed,
2869 ARM::VLD2q16PseudoWB_fixed,
2870 ARM::VLD2q32PseudoWB_fixed };
2871 return SelectVLD(N, true, 2, DOpcodes, QOpcodes, nullptr);
2874 case ARMISD::VLD3_UPD: {
2875 static const uint16_t DOpcodes[] = { ARM::VLD3d8Pseudo_UPD,
2876 ARM::VLD3d16Pseudo_UPD,
2877 ARM::VLD3d32Pseudo_UPD,
2878 ARM::VLD1d64TPseudoWB_fixed};
2879 static const uint16_t QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
2880 ARM::VLD3q16Pseudo_UPD,
2881 ARM::VLD3q32Pseudo_UPD };
2882 static const uint16_t QOpcodes1[] = { ARM::VLD3q8oddPseudo_UPD,
2883 ARM::VLD3q16oddPseudo_UPD,
2884 ARM::VLD3q32oddPseudo_UPD };
2885 return SelectVLD(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
2888 case ARMISD::VLD4_UPD: {
2889 static const uint16_t DOpcodes[] = { ARM::VLD4d8Pseudo_UPD,
2890 ARM::VLD4d16Pseudo_UPD,
2891 ARM::VLD4d32Pseudo_UPD,
2892 ARM::VLD1d64QPseudoWB_fixed};
2893 static const uint16_t QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
2894 ARM::VLD4q16Pseudo_UPD,
2895 ARM::VLD4q32Pseudo_UPD };
2896 static const uint16_t QOpcodes1[] = { ARM::VLD4q8oddPseudo_UPD,
2897 ARM::VLD4q16oddPseudo_UPD,
2898 ARM::VLD4q32oddPseudo_UPD };
2899 return SelectVLD(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
2902 case ARMISD::VLD2LN_UPD: {
2903 static const uint16_t DOpcodes[] = { ARM::VLD2LNd8Pseudo_UPD,
2904 ARM::VLD2LNd16Pseudo_UPD,
2905 ARM::VLD2LNd32Pseudo_UPD };
2906 static const uint16_t QOpcodes[] = { ARM::VLD2LNq16Pseudo_UPD,
2907 ARM::VLD2LNq32Pseudo_UPD };
2908 return SelectVLDSTLane(N, true, true, 2, DOpcodes, QOpcodes);
2911 case ARMISD::VLD3LN_UPD: {
2912 static const uint16_t DOpcodes[] = { ARM::VLD3LNd8Pseudo_UPD,
2913 ARM::VLD3LNd16Pseudo_UPD,
2914 ARM::VLD3LNd32Pseudo_UPD };
2915 static const uint16_t QOpcodes[] = { ARM::VLD3LNq16Pseudo_UPD,
2916 ARM::VLD3LNq32Pseudo_UPD };
2917 return SelectVLDSTLane(N, true, true, 3, DOpcodes, QOpcodes);
2920 case ARMISD::VLD4LN_UPD: {
2921 static const uint16_t DOpcodes[] = { ARM::VLD4LNd8Pseudo_UPD,
2922 ARM::VLD4LNd16Pseudo_UPD,
2923 ARM::VLD4LNd32Pseudo_UPD };
2924 static const uint16_t QOpcodes[] = { ARM::VLD4LNq16Pseudo_UPD,
2925 ARM::VLD4LNq32Pseudo_UPD };
2926 return SelectVLDSTLane(N, true, true, 4, DOpcodes, QOpcodes);
2929 case ARMISD::VST1_UPD: {
2930 static const uint16_t DOpcodes[] = { ARM::VST1d8wb_fixed,
2931 ARM::VST1d16wb_fixed,
2932 ARM::VST1d32wb_fixed,
2933 ARM::VST1d64wb_fixed };
2934 static const uint16_t QOpcodes[] = { ARM::VST1q8wb_fixed,
2935 ARM::VST1q16wb_fixed,
2936 ARM::VST1q32wb_fixed,
2937 ARM::VST1q64wb_fixed };
2938 return SelectVST(N, true, 1, DOpcodes, QOpcodes, nullptr);
2941 case ARMISD::VST2_UPD: {
2942 static const uint16_t DOpcodes[] = { ARM::VST2d8wb_fixed,
2943 ARM::VST2d16wb_fixed,
2944 ARM::VST2d32wb_fixed,
2945 ARM::VST1q64wb_fixed};
2946 static const uint16_t QOpcodes[] = { ARM::VST2q8PseudoWB_fixed,
2947 ARM::VST2q16PseudoWB_fixed,
2948 ARM::VST2q32PseudoWB_fixed };
2949 return SelectVST(N, true, 2, DOpcodes, QOpcodes, nullptr);
2952 case ARMISD::VST3_UPD: {
2953 static const uint16_t DOpcodes[] = { ARM::VST3d8Pseudo_UPD,
2954 ARM::VST3d16Pseudo_UPD,
2955 ARM::VST3d32Pseudo_UPD,
2956 ARM::VST1d64TPseudoWB_fixed};
2957 static const uint16_t QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
2958 ARM::VST3q16Pseudo_UPD,
2959 ARM::VST3q32Pseudo_UPD };
2960 static const uint16_t QOpcodes1[] = { ARM::VST3q8oddPseudo_UPD,
2961 ARM::VST3q16oddPseudo_UPD,
2962 ARM::VST3q32oddPseudo_UPD };
2963 return SelectVST(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
2966 case ARMISD::VST4_UPD: {
2967 static const uint16_t DOpcodes[] = { ARM::VST4d8Pseudo_UPD,
2968 ARM::VST4d16Pseudo_UPD,
2969 ARM::VST4d32Pseudo_UPD,
2970 ARM::VST1d64QPseudoWB_fixed};
2971 static const uint16_t QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
2972 ARM::VST4q16Pseudo_UPD,
2973 ARM::VST4q32Pseudo_UPD };
2974 static const uint16_t QOpcodes1[] = { ARM::VST4q8oddPseudo_UPD,
2975 ARM::VST4q16oddPseudo_UPD,
2976 ARM::VST4q32oddPseudo_UPD };
2977 return SelectVST(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
2980 case ARMISD::VST2LN_UPD: {
2981 static const uint16_t DOpcodes[] = { ARM::VST2LNd8Pseudo_UPD,
2982 ARM::VST2LNd16Pseudo_UPD,
2983 ARM::VST2LNd32Pseudo_UPD };
2984 static const uint16_t QOpcodes[] = { ARM::VST2LNq16Pseudo_UPD,
2985 ARM::VST2LNq32Pseudo_UPD };
2986 return SelectVLDSTLane(N, false, true, 2, DOpcodes, QOpcodes);
2989 case ARMISD::VST3LN_UPD: {
2990 static const uint16_t DOpcodes[] = { ARM::VST3LNd8Pseudo_UPD,
2991 ARM::VST3LNd16Pseudo_UPD,
2992 ARM::VST3LNd32Pseudo_UPD };
2993 static const uint16_t QOpcodes[] = { ARM::VST3LNq16Pseudo_UPD,
2994 ARM::VST3LNq32Pseudo_UPD };
2995 return SelectVLDSTLane(N, false, true, 3, DOpcodes, QOpcodes);
2998 case ARMISD::VST4LN_UPD: {
2999 static const uint16_t DOpcodes[] = { ARM::VST4LNd8Pseudo_UPD,
3000 ARM::VST4LNd16Pseudo_UPD,
3001 ARM::VST4LNd32Pseudo_UPD };
3002 static const uint16_t QOpcodes[] = { ARM::VST4LNq16Pseudo_UPD,
3003 ARM::VST4LNq32Pseudo_UPD };
3004 return SelectVLDSTLane(N, false, true, 4, DOpcodes, QOpcodes);
3007 case ISD::INTRINSIC_VOID:
3008 case ISD::INTRINSIC_W_CHAIN: {
3009 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
3014 case Intrinsic::arm_ldaexd:
3015 case Intrinsic::arm_ldrexd: {
3017 SDValue Chain = N->getOperand(0);
3018 SDValue MemAddr = N->getOperand(2);
3019 bool isThumb = Subtarget->isThumb() && Subtarget->hasThumb2();
3021 bool IsAcquire = IntNo == Intrinsic::arm_ldaexd;
3022 unsigned NewOpc = isThumb ? (IsAcquire ? ARM::t2LDAEXD : ARM::t2LDREXD)
3023 : (IsAcquire ? ARM::LDAEXD : ARM::LDREXD);
3025 // arm_ldrexd returns a i64 value in {i32, i32}
3026 std::vector<EVT> ResTys;
3028 ResTys.push_back(MVT::i32);
3029 ResTys.push_back(MVT::i32);
3031 ResTys.push_back(MVT::Untyped);
3032 ResTys.push_back(MVT::Other);
3034 // Place arguments in the right order.
3035 SmallVector<SDValue, 7> Ops;
3036 Ops.push_back(MemAddr);
3037 Ops.push_back(getAL(CurDAG));
3038 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
3039 Ops.push_back(Chain);
3040 SDNode *Ld = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops);
3041 // Transfer memoperands.
3042 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
3043 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
3044 cast<MachineSDNode>(Ld)->setMemRefs(MemOp, MemOp + 1);
3047 SDValue OutChain = isThumb ? SDValue(Ld, 2) : SDValue(Ld, 1);
3048 if (!SDValue(N, 0).use_empty()) {
3051 Result = SDValue(Ld, 0);
3053 SDValue SubRegIdx = CurDAG->getTargetConstant(ARM::gsub_0, MVT::i32);
3054 SDNode *ResNode = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
3055 dl, MVT::i32, SDValue(Ld, 0), SubRegIdx);
3056 Result = SDValue(ResNode,0);
3058 ReplaceUses(SDValue(N, 0), Result);
3060 if (!SDValue(N, 1).use_empty()) {
3063 Result = SDValue(Ld, 1);
3065 SDValue SubRegIdx = CurDAG->getTargetConstant(ARM::gsub_1, MVT::i32);
3066 SDNode *ResNode = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
3067 dl, MVT::i32, SDValue(Ld, 0), SubRegIdx);
3068 Result = SDValue(ResNode,0);
3070 ReplaceUses(SDValue(N, 1), Result);
3072 ReplaceUses(SDValue(N, 2), OutChain);
3075 case Intrinsic::arm_stlexd:
3076 case Intrinsic::arm_strexd: {
3078 SDValue Chain = N->getOperand(0);
3079 SDValue Val0 = N->getOperand(2);
3080 SDValue Val1 = N->getOperand(3);
3081 SDValue MemAddr = N->getOperand(4);
3083 // Store exclusive double return a i32 value which is the return status
3084 // of the issued store.
3085 EVT ResTys[] = { MVT::i32, MVT::Other };
3087 bool isThumb = Subtarget->isThumb() && Subtarget->hasThumb2();
3088 // Place arguments in the right order.
3089 SmallVector<SDValue, 7> Ops;
3091 Ops.push_back(Val0);
3092 Ops.push_back(Val1);
3094 // arm_strexd uses GPRPair.
3095 Ops.push_back(SDValue(createGPRPairNode(MVT::Untyped, Val0, Val1), 0));
3096 Ops.push_back(MemAddr);
3097 Ops.push_back(getAL(CurDAG));
3098 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
3099 Ops.push_back(Chain);
3101 bool IsRelease = IntNo == Intrinsic::arm_stlexd;
3102 unsigned NewOpc = isThumb ? (IsRelease ? ARM::t2STLEXD : ARM::t2STREXD)
3103 : (IsRelease ? ARM::STLEXD : ARM::STREXD);
3105 SDNode *St = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops);
3106 // Transfer memoperands.
3107 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
3108 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
3109 cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1);
3114 case Intrinsic::arm_neon_vld1: {
3115 static const uint16_t DOpcodes[] = { ARM::VLD1d8, ARM::VLD1d16,
3116 ARM::VLD1d32, ARM::VLD1d64 };
3117 static const uint16_t QOpcodes[] = { ARM::VLD1q8, ARM::VLD1q16,
3118 ARM::VLD1q32, ARM::VLD1q64};
3119 return SelectVLD(N, false, 1, DOpcodes, QOpcodes, nullptr);
3122 case Intrinsic::arm_neon_vld2: {
3123 static const uint16_t DOpcodes[] = { ARM::VLD2d8, ARM::VLD2d16,
3124 ARM::VLD2d32, ARM::VLD1q64 };
3125 static const uint16_t QOpcodes[] = { ARM::VLD2q8Pseudo, ARM::VLD2q16Pseudo,
3126 ARM::VLD2q32Pseudo };
3127 return SelectVLD(N, false, 2, DOpcodes, QOpcodes, nullptr);
3130 case Intrinsic::arm_neon_vld3: {
3131 static const uint16_t DOpcodes[] = { ARM::VLD3d8Pseudo,
3134 ARM::VLD1d64TPseudo };
3135 static const uint16_t QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
3136 ARM::VLD3q16Pseudo_UPD,
3137 ARM::VLD3q32Pseudo_UPD };
3138 static const uint16_t QOpcodes1[] = { ARM::VLD3q8oddPseudo,
3139 ARM::VLD3q16oddPseudo,
3140 ARM::VLD3q32oddPseudo };
3141 return SelectVLD(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
3144 case Intrinsic::arm_neon_vld4: {
3145 static const uint16_t DOpcodes[] = { ARM::VLD4d8Pseudo,
3148 ARM::VLD1d64QPseudo };
3149 static const uint16_t QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
3150 ARM::VLD4q16Pseudo_UPD,
3151 ARM::VLD4q32Pseudo_UPD };
3152 static const uint16_t QOpcodes1[] = { ARM::VLD4q8oddPseudo,
3153 ARM::VLD4q16oddPseudo,
3154 ARM::VLD4q32oddPseudo };
3155 return SelectVLD(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
3158 case Intrinsic::arm_neon_vld2lane: {
3159 static const uint16_t DOpcodes[] = { ARM::VLD2LNd8Pseudo,
3160 ARM::VLD2LNd16Pseudo,
3161 ARM::VLD2LNd32Pseudo };
3162 static const uint16_t QOpcodes[] = { ARM::VLD2LNq16Pseudo,
3163 ARM::VLD2LNq32Pseudo };
3164 return SelectVLDSTLane(N, true, false, 2, DOpcodes, QOpcodes);
3167 case Intrinsic::arm_neon_vld3lane: {
3168 static const uint16_t DOpcodes[] = { ARM::VLD3LNd8Pseudo,
3169 ARM::VLD3LNd16Pseudo,
3170 ARM::VLD3LNd32Pseudo };
3171 static const uint16_t QOpcodes[] = { ARM::VLD3LNq16Pseudo,
3172 ARM::VLD3LNq32Pseudo };
3173 return SelectVLDSTLane(N, true, false, 3, DOpcodes, QOpcodes);
3176 case Intrinsic::arm_neon_vld4lane: {
3177 static const uint16_t DOpcodes[] = { ARM::VLD4LNd8Pseudo,
3178 ARM::VLD4LNd16Pseudo,
3179 ARM::VLD4LNd32Pseudo };
3180 static const uint16_t QOpcodes[] = { ARM::VLD4LNq16Pseudo,
3181 ARM::VLD4LNq32Pseudo };
3182 return SelectVLDSTLane(N, true, false, 4, DOpcodes, QOpcodes);
3185 case Intrinsic::arm_neon_vst1: {
3186 static const uint16_t DOpcodes[] = { ARM::VST1d8, ARM::VST1d16,
3187 ARM::VST1d32, ARM::VST1d64 };
3188 static const uint16_t QOpcodes[] = { ARM::VST1q8, ARM::VST1q16,
3189 ARM::VST1q32, ARM::VST1q64 };
3190 return SelectVST(N, false, 1, DOpcodes, QOpcodes, nullptr);
3193 case Intrinsic::arm_neon_vst2: {
3194 static const uint16_t DOpcodes[] = { ARM::VST2d8, ARM::VST2d16,
3195 ARM::VST2d32, ARM::VST1q64 };
3196 static uint16_t QOpcodes[] = { ARM::VST2q8Pseudo, ARM::VST2q16Pseudo,
3197 ARM::VST2q32Pseudo };
3198 return SelectVST(N, false, 2, DOpcodes, QOpcodes, nullptr);
3201 case Intrinsic::arm_neon_vst3: {
3202 static const uint16_t DOpcodes[] = { ARM::VST3d8Pseudo,
3205 ARM::VST1d64TPseudo };
3206 static const uint16_t QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
3207 ARM::VST3q16Pseudo_UPD,
3208 ARM::VST3q32Pseudo_UPD };
3209 static const uint16_t QOpcodes1[] = { ARM::VST3q8oddPseudo,
3210 ARM::VST3q16oddPseudo,
3211 ARM::VST3q32oddPseudo };
3212 return SelectVST(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
3215 case Intrinsic::arm_neon_vst4: {
3216 static const uint16_t DOpcodes[] = { ARM::VST4d8Pseudo,
3219 ARM::VST1d64QPseudo };
3220 static const uint16_t QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
3221 ARM::VST4q16Pseudo_UPD,
3222 ARM::VST4q32Pseudo_UPD };
3223 static const uint16_t QOpcodes1[] = { ARM::VST4q8oddPseudo,
3224 ARM::VST4q16oddPseudo,
3225 ARM::VST4q32oddPseudo };
3226 return SelectVST(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
3229 case Intrinsic::arm_neon_vst2lane: {
3230 static const uint16_t DOpcodes[] = { ARM::VST2LNd8Pseudo,
3231 ARM::VST2LNd16Pseudo,
3232 ARM::VST2LNd32Pseudo };
3233 static const uint16_t QOpcodes[] = { ARM::VST2LNq16Pseudo,
3234 ARM::VST2LNq32Pseudo };
3235 return SelectVLDSTLane(N, false, false, 2, DOpcodes, QOpcodes);
3238 case Intrinsic::arm_neon_vst3lane: {
3239 static const uint16_t DOpcodes[] = { ARM::VST3LNd8Pseudo,
3240 ARM::VST3LNd16Pseudo,
3241 ARM::VST3LNd32Pseudo };
3242 static const uint16_t QOpcodes[] = { ARM::VST3LNq16Pseudo,
3243 ARM::VST3LNq32Pseudo };
3244 return SelectVLDSTLane(N, false, false, 3, DOpcodes, QOpcodes);
3247 case Intrinsic::arm_neon_vst4lane: {
3248 static const uint16_t DOpcodes[] = { ARM::VST4LNd8Pseudo,
3249 ARM::VST4LNd16Pseudo,
3250 ARM::VST4LNd32Pseudo };
3251 static const uint16_t QOpcodes[] = { ARM::VST4LNq16Pseudo,
3252 ARM::VST4LNq32Pseudo };
3253 return SelectVLDSTLane(N, false, false, 4, DOpcodes, QOpcodes);
3259 case ISD::INTRINSIC_WO_CHAIN: {
3260 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
3265 case Intrinsic::arm_neon_vtbl2:
3266 return SelectVTBL(N, false, 2, ARM::VTBL2);
3267 case Intrinsic::arm_neon_vtbl3:
3268 return SelectVTBL(N, false, 3, ARM::VTBL3Pseudo);
3269 case Intrinsic::arm_neon_vtbl4:
3270 return SelectVTBL(N, false, 4, ARM::VTBL4Pseudo);
3272 case Intrinsic::arm_neon_vtbx2:
3273 return SelectVTBL(N, true, 2, ARM::VTBX2);
3274 case Intrinsic::arm_neon_vtbx3:
3275 return SelectVTBL(N, true, 3, ARM::VTBX3Pseudo);
3276 case Intrinsic::arm_neon_vtbx4:
3277 return SelectVTBL(N, true, 4, ARM::VTBX4Pseudo);
3282 case ARMISD::VTBL1: {
3284 EVT VT = N->getValueType(0);
3285 SmallVector<SDValue, 6> Ops;
3287 Ops.push_back(N->getOperand(0));
3288 Ops.push_back(N->getOperand(1));
3289 Ops.push_back(getAL(CurDAG)); // Predicate
3290 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register
3291 return CurDAG->getMachineNode(ARM::VTBL1, dl, VT, Ops);
3293 case ARMISD::VTBL2: {
3295 EVT VT = N->getValueType(0);
3297 // Form a REG_SEQUENCE to force register allocation.
3298 SDValue V0 = N->getOperand(0);
3299 SDValue V1 = N->getOperand(1);
3300 SDValue RegSeq = SDValue(createDRegPairNode(MVT::v16i8, V0, V1), 0);
3302 SmallVector<SDValue, 6> Ops;
3303 Ops.push_back(RegSeq);
3304 Ops.push_back(N->getOperand(2));
3305 Ops.push_back(getAL(CurDAG)); // Predicate
3306 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register
3307 return CurDAG->getMachineNode(ARM::VTBL2, dl, VT, Ops);
3310 case ISD::CONCAT_VECTORS:
3311 return SelectConcatVector(N);
3314 return SelectCode(N);
3317 SDNode *ARMDAGToDAGISel::SelectInlineAsm(SDNode *N){
3318 std::vector<SDValue> AsmNodeOperands;
3319 unsigned Flag, Kind;
3320 bool Changed = false;
3321 unsigned NumOps = N->getNumOperands();
3323 // Normally, i64 data is bounded to two arbitrary GRPs for "%r" constraint.
3324 // However, some instrstions (e.g. ldrexd/strexd in ARM mode) require
3325 // (even/even+1) GPRs and use %n and %Hn to refer to the individual regs
3326 // respectively. Since there is no constraint to explicitly specify a
3327 // reg pair, we use GPRPair reg class for "%r" for 64-bit data. For Thumb,
3328 // the 64-bit data may be referred by H, Q, R modifiers, so we still pack
3329 // them into a GPRPair.
3332 SDValue Glue = N->getGluedNode() ? N->getOperand(NumOps-1)
3333 : SDValue(nullptr,0);
3335 SmallVector<bool, 8> OpChanged;
3336 // Glue node will be appended late.
3337 for(unsigned i = 0, e = N->getGluedNode() ? NumOps - 1 : NumOps; i < e; ++i) {
3338 SDValue op = N->getOperand(i);
3339 AsmNodeOperands.push_back(op);
3341 if (i < InlineAsm::Op_FirstOperand)
3344 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(i))) {
3345 Flag = C->getZExtValue();
3346 Kind = InlineAsm::getKind(Flag);
3351 // Immediate operands to inline asm in the SelectionDAG are modeled with
3352 // two operands. The first is a constant of value InlineAsm::Kind_Imm, and
3353 // the second is a constant with the value of the immediate. If we get here
3354 // and we have a Kind_Imm, skip the next operand, and continue.
3355 if (Kind == InlineAsm::Kind_Imm) {
3356 SDValue op = N->getOperand(++i);
3357 AsmNodeOperands.push_back(op);
3361 unsigned NumRegs = InlineAsm::getNumOperandRegisters(Flag);
3363 OpChanged.push_back(false);
3365 unsigned DefIdx = 0;
3366 bool IsTiedToChangedOp = false;
3367 // If it's a use that is tied with a previous def, it has no
3368 // reg class constraint.
3369 if (Changed && InlineAsm::isUseOperandTiedToDef(Flag, DefIdx))
3370 IsTiedToChangedOp = OpChanged[DefIdx];
3372 if (Kind != InlineAsm::Kind_RegUse && Kind != InlineAsm::Kind_RegDef
3373 && Kind != InlineAsm::Kind_RegDefEarlyClobber)
3377 bool HasRC = InlineAsm::hasRegClassConstraint(Flag, RC);
3378 if ((!IsTiedToChangedOp && (!HasRC || RC != ARM::GPRRegClassID))
3382 assert((i+2 < NumOps) && "Invalid number of operands in inline asm");
3383 SDValue V0 = N->getOperand(i+1);
3384 SDValue V1 = N->getOperand(i+2);
3385 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg();
3386 unsigned Reg1 = cast<RegisterSDNode>(V1)->getReg();
3388 MachineRegisterInfo &MRI = MF->getRegInfo();
3390 if (Kind == InlineAsm::Kind_RegDef ||
3391 Kind == InlineAsm::Kind_RegDefEarlyClobber) {
3392 // Replace the two GPRs with 1 GPRPair and copy values from GPRPair to
3393 // the original GPRs.
3395 unsigned GPVR = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
3396 PairedReg = CurDAG->getRegister(GPVR, MVT::Untyped);
3397 SDValue Chain = SDValue(N,0);
3399 SDNode *GU = N->getGluedUser();
3400 SDValue RegCopy = CurDAG->getCopyFromReg(Chain, dl, GPVR, MVT::Untyped,
3403 // Extract values from a GPRPair reg and copy to the original GPR reg.
3404 SDValue Sub0 = CurDAG->getTargetExtractSubreg(ARM::gsub_0, dl, MVT::i32,
3406 SDValue Sub1 = CurDAG->getTargetExtractSubreg(ARM::gsub_1, dl, MVT::i32,
3408 SDValue T0 = CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0,
3409 RegCopy.getValue(1));
3410 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1));
3412 // Update the original glue user.
3413 std::vector<SDValue> Ops(GU->op_begin(), GU->op_end()-1);
3414 Ops.push_back(T1.getValue(1));
3415 CurDAG->UpdateNodeOperands(GU, Ops);
3419 // For Kind == InlineAsm::Kind_RegUse, we first copy two GPRs into a
3420 // GPRPair and then pass the GPRPair to the inline asm.
3421 SDValue Chain = AsmNodeOperands[InlineAsm::Op_InputChain];
3423 // As REG_SEQ doesn't take RegisterSDNode, we copy them first.
3424 SDValue T0 = CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32,
3426 SDValue T1 = CurDAG->getCopyFromReg(Chain, dl, Reg1, MVT::i32,
3428 SDValue Pair = SDValue(createGPRPairNode(MVT::Untyped, T0, T1), 0);
3430 // Copy REG_SEQ into a GPRPair-typed VR and replace the original two
3431 // i32 VRs of inline asm with it.
3432 unsigned GPVR = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
3433 PairedReg = CurDAG->getRegister(GPVR, MVT::Untyped);
3434 Chain = CurDAG->getCopyToReg(T1, dl, GPVR, Pair, T1.getValue(1));
3436 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
3437 Glue = Chain.getValue(1);
3442 if(PairedReg.getNode()) {
3443 OpChanged[OpChanged.size() -1 ] = true;
3444 Flag = InlineAsm::getFlagWord(Kind, 1 /* RegNum*/);
3445 if (IsTiedToChangedOp)
3446 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, DefIdx);
3448 Flag = InlineAsm::getFlagWordForRegClass(Flag, ARM::GPRPairRegClassID);
3449 // Replace the current flag.
3450 AsmNodeOperands[AsmNodeOperands.size() -1] = CurDAG->getTargetConstant(
3452 // Add the new register node and skip the original two GPRs.
3453 AsmNodeOperands.push_back(PairedReg);
3454 // Skip the next two GPRs.
3460 AsmNodeOperands.push_back(Glue);
3464 SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N),
3465 CurDAG->getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
3467 return New.getNode();
3471 bool ARMDAGToDAGISel::
3472 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
3473 std::vector<SDValue> &OutOps) {
3474 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
3475 // Require the address to be in a register. That is safe for all ARM
3476 // variants and it is hard to do anything much smarter without knowing
3477 // how the operand is used.
3478 OutOps.push_back(Op);
3482 /// createARMISelDag - This pass converts a legalized DAG into a
3483 /// ARM-specific DAG, ready for instruction scheduling.
3485 FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
3486 CodeGenOpt::Level OptLevel) {
3487 return new ARMDAGToDAGISel(TM, OptLevel);