1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "arm-isel"
16 #include "ARMAddressingModes.h"
17 #include "ARMTargetMachine.h"
18 #include "llvm/CallingConv.h"
19 #include "llvm/Constants.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/LLVMContext.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CodeGen/SelectionDAGISel.h"
29 #include "llvm/Target/TargetLowering.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Compiler.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
40 DisableShifterOp("disable-shifter-op", cl::Hidden,
41 cl::desc("Disable isel of shifter-op"),
44 //===--------------------------------------------------------------------===//
45 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
46 /// instructions for SelectionDAG operations.
49 class ARMDAGToDAGISel : public SelectionDAGISel {
50 ARMBaseTargetMachine &TM;
52 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
53 /// make the right decision when generating code for different targets.
54 const ARMSubtarget *Subtarget;
57 explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm,
58 CodeGenOpt::Level OptLevel)
59 : SelectionDAGISel(tm, OptLevel), TM(tm),
60 Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
63 virtual const char *getPassName() const {
64 return "ARM Instruction Selection";
67 /// getI32Imm - Return a target constant of type i32 with the specified
69 inline SDValue getI32Imm(unsigned Imm) {
70 return CurDAG->getTargetConstant(Imm, MVT::i32);
73 SDNode *Select(SDNode *N);
75 bool SelectShifterOperandReg(SDNode *Op, SDValue N, SDValue &A,
76 SDValue &B, SDValue &C);
77 bool SelectAddrMode2(SDNode *Op, SDValue N, SDValue &Base,
78 SDValue &Offset, SDValue &Opc);
79 bool SelectAddrMode2Offset(SDNode *Op, SDValue N,
80 SDValue &Offset, SDValue &Opc);
81 bool SelectAddrMode3(SDNode *Op, SDValue N, SDValue &Base,
82 SDValue &Offset, SDValue &Opc);
83 bool SelectAddrMode3Offset(SDNode *Op, SDValue N,
84 SDValue &Offset, SDValue &Opc);
85 bool SelectAddrMode4(SDNode *Op, SDValue N, SDValue &Addr,
87 bool SelectAddrMode5(SDNode *Op, SDValue N, SDValue &Base,
89 bool SelectAddrMode6(SDNode *Op, SDValue N, SDValue &Addr, SDValue &Align);
91 bool SelectAddrModePC(SDNode *Op, SDValue N, SDValue &Offset,
94 bool SelectThumbAddrModeRR(SDNode *Op, SDValue N, SDValue &Base,
96 bool SelectThumbAddrModeRI5(SDNode *Op, SDValue N, unsigned Scale,
97 SDValue &Base, SDValue &OffImm,
99 bool SelectThumbAddrModeS1(SDNode *Op, SDValue N, SDValue &Base,
100 SDValue &OffImm, SDValue &Offset);
101 bool SelectThumbAddrModeS2(SDNode *Op, SDValue N, SDValue &Base,
102 SDValue &OffImm, SDValue &Offset);
103 bool SelectThumbAddrModeS4(SDNode *Op, SDValue N, SDValue &Base,
104 SDValue &OffImm, SDValue &Offset);
105 bool SelectThumbAddrModeSP(SDNode *Op, SDValue N, SDValue &Base,
108 bool SelectT2ShifterOperandReg(SDNode *Op, SDValue N,
109 SDValue &BaseReg, SDValue &Opc);
110 bool SelectT2AddrModeImm12(SDNode *Op, SDValue N, SDValue &Base,
112 bool SelectT2AddrModeImm8(SDNode *Op, SDValue N, SDValue &Base,
114 bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
116 bool SelectT2AddrModeImm8s4(SDNode *Op, SDValue N, SDValue &Base,
118 bool SelectT2AddrModeSoReg(SDNode *Op, SDValue N, SDValue &Base,
119 SDValue &OffReg, SDValue &ShImm);
121 // Include the pieces autogenerated from the target description.
122 #include "ARMGenDAGISel.inc"
125 /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
127 SDNode *SelectARMIndexedLoad(SDNode *N);
128 SDNode *SelectT2IndexedLoad(SDNode *N);
130 /// SelectVLD - Select NEON load intrinsics. NumVecs should be
131 /// 1, 2, 3 or 4. The opcode arrays specify the instructions used for
132 /// loads of D registers and even subregs and odd subregs of Q registers.
133 /// For NumVecs <= 2, QOpcodes1 is not used.
134 SDNode *SelectVLD(SDNode *N, unsigned NumVecs, unsigned *DOpcodes,
135 unsigned *QOpcodes0, unsigned *QOpcodes1);
137 /// SelectVST - Select NEON store intrinsics. NumVecs should
138 /// be 1, 2, 3 or 4. The opcode arrays specify the instructions used for
139 /// stores of D registers and even subregs and odd subregs of Q registers.
140 /// For NumVecs <= 2, QOpcodes1 is not used.
141 SDNode *SelectVST(SDNode *N, unsigned NumVecs, unsigned *DOpcodes,
142 unsigned *QOpcodes0, unsigned *QOpcodes1);
144 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should
145 /// be 2, 3 or 4. The opcode arrays specify the instructions used for
146 /// load/store of D registers and even subregs and odd subregs of Q registers.
147 SDNode *SelectVLDSTLane(SDNode *N, bool IsLoad, unsigned NumVecs,
148 unsigned *DOpcodes, unsigned *QOpcodes0,
149 unsigned *QOpcodes1);
151 /// SelectVTBL - Select NEON VTBL and VTBX intrinsics. NumVecs should be 2,
152 /// 3 or 4. These are custom-selected so that a REG_SEQUENCE can be
153 /// generated to force the table registers to be consecutive.
154 SDNode *SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc);
156 /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM.
157 SDNode *SelectV6T2BitfieldExtractOp(SDNode *N, bool isSigned);
159 /// SelectCMOVOp - Select CMOV instructions for ARM.
160 SDNode *SelectCMOVOp(SDNode *N);
161 SDNode *SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
162 ARMCC::CondCodes CCVal, SDValue CCR,
164 SDNode *SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
165 ARMCC::CondCodes CCVal, SDValue CCR,
167 SDNode *SelectT2CMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
168 ARMCC::CondCodes CCVal, SDValue CCR,
170 SDNode *SelectARMCMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
171 ARMCC::CondCodes CCVal, SDValue CCR,
174 SDNode *SelectConcatVector(SDNode *N);
176 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
177 /// inline asm expressions.
178 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
180 std::vector<SDValue> &OutOps);
182 // Form pairs of consecutive S, D, or Q registers.
183 SDNode *PairSRegs(EVT VT, SDValue V0, SDValue V1);
184 SDNode *PairDRegs(EVT VT, SDValue V0, SDValue V1);
185 SDNode *PairQRegs(EVT VT, SDValue V0, SDValue V1);
187 // Form sequences of 4 consecutive S, D, or Q registers.
188 SDNode *QuadSRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
189 SDNode *QuadDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
190 SDNode *QuadQRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
192 // Form sequences of 8 consecutive D registers.
193 SDNode *OctoDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3,
194 SDValue V4, SDValue V5, SDValue V6, SDValue V7);
198 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
199 /// operand. If so Imm will receive the 32-bit value.
200 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
201 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
202 Imm = cast<ConstantSDNode>(N)->getZExtValue();
208 // isInt32Immediate - This method tests to see if a constant operand.
209 // If so Imm will receive the 32 bit value.
210 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
211 return isInt32Immediate(N.getNode(), Imm);
214 // isOpcWithIntImmediate - This method tests to see if the node is a specific
215 // opcode and that it has a immediate integer right operand.
216 // If so Imm will receive the 32 bit value.
217 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
218 return N->getOpcode() == Opc &&
219 isInt32Immediate(N->getOperand(1).getNode(), Imm);
223 bool ARMDAGToDAGISel::SelectShifterOperandReg(SDNode *Op,
228 if (DisableShifterOp)
231 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
233 // Don't match base register only case. That is matched to a separate
234 // lower complexity pattern with explicit register operand.
235 if (ShOpcVal == ARM_AM::no_shift) return false;
237 BaseReg = N.getOperand(0);
238 unsigned ShImmVal = 0;
239 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
240 ShReg = CurDAG->getRegister(0, MVT::i32);
241 ShImmVal = RHS->getZExtValue() & 31;
243 ShReg = N.getOperand(1);
245 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
250 bool ARMDAGToDAGISel::SelectAddrMode2(SDNode *Op, SDValue N,
251 SDValue &Base, SDValue &Offset,
253 if (N.getOpcode() == ISD::MUL) {
254 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
255 // X * [3,5,9] -> X + X * [2,4,8] etc.
256 int RHSC = (int)RHS->getZExtValue();
259 ARM_AM::AddrOpc AddSub = ARM_AM::add;
261 AddSub = ARM_AM::sub;
264 if (isPowerOf2_32(RHSC)) {
265 unsigned ShAmt = Log2_32(RHSC);
266 Base = Offset = N.getOperand(0);
267 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
276 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
278 if (N.getOpcode() == ISD::FrameIndex) {
279 int FI = cast<FrameIndexSDNode>(N)->getIndex();
280 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
281 } else if (N.getOpcode() == ARMISD::Wrapper &&
282 !(Subtarget->useMovt() &&
283 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
284 Base = N.getOperand(0);
286 Offset = CurDAG->getRegister(0, MVT::i32);
287 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
293 // Match simple R +/- imm12 operands.
294 if (N.getOpcode() == ISD::ADD)
295 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
296 int RHSC = (int)RHS->getZExtValue();
297 if ((RHSC >= 0 && RHSC < 0x1000) ||
298 (RHSC < 0 && RHSC > -0x1000)) { // 12 bits.
299 Base = N.getOperand(0);
300 if (Base.getOpcode() == ISD::FrameIndex) {
301 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
302 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
304 Offset = CurDAG->getRegister(0, MVT::i32);
306 ARM_AM::AddrOpc AddSub = ARM_AM::add;
308 AddSub = ARM_AM::sub;
311 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
318 // Otherwise this is R +/- [possibly shifted] R.
319 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
320 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
323 Base = N.getOperand(0);
324 Offset = N.getOperand(1);
326 if (ShOpcVal != ARM_AM::no_shift) {
327 // Check to see if the RHS of the shift is a constant, if not, we can't fold
329 if (ConstantSDNode *Sh =
330 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
331 ShAmt = Sh->getZExtValue();
332 Offset = N.getOperand(1).getOperand(0);
334 ShOpcVal = ARM_AM::no_shift;
338 // Try matching (R shl C) + (R).
339 if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift) {
340 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
341 if (ShOpcVal != ARM_AM::no_shift) {
342 // Check to see if the RHS of the shift is a constant, if not, we can't
344 if (ConstantSDNode *Sh =
345 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
346 ShAmt = Sh->getZExtValue();
347 Offset = N.getOperand(0).getOperand(0);
348 Base = N.getOperand(1);
350 ShOpcVal = ARM_AM::no_shift;
355 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
360 bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDNode *Op, SDValue N,
361 SDValue &Offset, SDValue &Opc) {
362 unsigned Opcode = Op->getOpcode();
363 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
364 ? cast<LoadSDNode>(Op)->getAddressingMode()
365 : cast<StoreSDNode>(Op)->getAddressingMode();
366 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
367 ? ARM_AM::add : ARM_AM::sub;
368 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
369 int Val = (int)C->getZExtValue();
370 if (Val >= 0 && Val < 0x1000) { // 12 bits.
371 Offset = CurDAG->getRegister(0, MVT::i32);
372 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
380 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
382 if (ShOpcVal != ARM_AM::no_shift) {
383 // Check to see if the RHS of the shift is a constant, if not, we can't fold
385 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
386 ShAmt = Sh->getZExtValue();
387 Offset = N.getOperand(0);
389 ShOpcVal = ARM_AM::no_shift;
393 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
399 bool ARMDAGToDAGISel::SelectAddrMode3(SDNode *Op, SDValue N,
400 SDValue &Base, SDValue &Offset,
402 if (N.getOpcode() == ISD::SUB) {
403 // X - C is canonicalize to X + -C, no need to handle it here.
404 Base = N.getOperand(0);
405 Offset = N.getOperand(1);
406 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
410 if (N.getOpcode() != ISD::ADD) {
412 if (N.getOpcode() == ISD::FrameIndex) {
413 int FI = cast<FrameIndexSDNode>(N)->getIndex();
414 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
416 Offset = CurDAG->getRegister(0, MVT::i32);
417 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
421 // If the RHS is +/- imm8, fold into addr mode.
422 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
423 int RHSC = (int)RHS->getZExtValue();
424 if ((RHSC >= 0 && RHSC < 256) ||
425 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
426 Base = N.getOperand(0);
427 if (Base.getOpcode() == ISD::FrameIndex) {
428 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
429 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
431 Offset = CurDAG->getRegister(0, MVT::i32);
433 ARM_AM::AddrOpc AddSub = ARM_AM::add;
435 AddSub = ARM_AM::sub;
438 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
443 Base = N.getOperand(0);
444 Offset = N.getOperand(1);
445 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
449 bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N,
450 SDValue &Offset, SDValue &Opc) {
451 unsigned Opcode = Op->getOpcode();
452 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
453 ? cast<LoadSDNode>(Op)->getAddressingMode()
454 : cast<StoreSDNode>(Op)->getAddressingMode();
455 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
456 ? ARM_AM::add : ARM_AM::sub;
457 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
458 int Val = (int)C->getZExtValue();
459 if (Val >= 0 && Val < 256) {
460 Offset = CurDAG->getRegister(0, MVT::i32);
461 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
467 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
471 bool ARMDAGToDAGISel::SelectAddrMode4(SDNode *Op, SDValue N,
472 SDValue &Addr, SDValue &Mode) {
474 Mode = CurDAG->getTargetConstant(0, MVT::i32);
478 bool ARMDAGToDAGISel::SelectAddrMode5(SDNode *Op, SDValue N,
479 SDValue &Base, SDValue &Offset) {
480 if (N.getOpcode() != ISD::ADD) {
482 if (N.getOpcode() == ISD::FrameIndex) {
483 int FI = cast<FrameIndexSDNode>(N)->getIndex();
484 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
485 } else if (N.getOpcode() == ARMISD::Wrapper &&
486 !(Subtarget->useMovt() &&
487 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
488 Base = N.getOperand(0);
490 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
495 // If the RHS is +/- imm8, fold into addr mode.
496 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
497 int RHSC = (int)RHS->getZExtValue();
498 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied by 4.
500 if ((RHSC >= 0 && RHSC < 256) ||
501 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
502 Base = N.getOperand(0);
503 if (Base.getOpcode() == ISD::FrameIndex) {
504 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
505 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
508 ARM_AM::AddrOpc AddSub = ARM_AM::add;
510 AddSub = ARM_AM::sub;
513 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
521 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
526 bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Op, SDValue N,
527 SDValue &Addr, SDValue &Align) {
529 // Default to no alignment.
530 Align = CurDAG->getTargetConstant(0, MVT::i32);
534 bool ARMDAGToDAGISel::SelectAddrModePC(SDNode *Op, SDValue N,
535 SDValue &Offset, SDValue &Label) {
536 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
537 Offset = N.getOperand(0);
538 SDValue N1 = N.getOperand(1);
539 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
546 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDNode *Op, SDValue N,
547 SDValue &Base, SDValue &Offset){
548 // FIXME dl should come from the parent load or store, not the address
549 if (N.getOpcode() != ISD::ADD) {
550 ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
551 if (!NC || !NC->isNullValue())
558 Base = N.getOperand(0);
559 Offset = N.getOperand(1);
564 ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDNode *Op, SDValue N,
565 unsigned Scale, SDValue &Base,
566 SDValue &OffImm, SDValue &Offset) {
568 SDValue TmpBase, TmpOffImm;
569 if (SelectThumbAddrModeSP(Op, N, TmpBase, TmpOffImm))
570 return false; // We want to select tLDRspi / tSTRspi instead.
571 if (N.getOpcode() == ARMISD::Wrapper &&
572 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
573 return false; // We want to select tLDRpci instead.
576 if (N.getOpcode() != ISD::ADD) {
577 if (N.getOpcode() == ARMISD::Wrapper &&
578 !(Subtarget->useMovt() &&
579 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
580 Base = N.getOperand(0);
584 Offset = CurDAG->getRegister(0, MVT::i32);
585 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
589 // Thumb does not have [sp, r] address mode.
590 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
591 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
592 if ((LHSR && LHSR->getReg() == ARM::SP) ||
593 (RHSR && RHSR->getReg() == ARM::SP)) {
595 Offset = CurDAG->getRegister(0, MVT::i32);
596 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
600 // If the RHS is + imm5 * scale, fold into addr mode.
601 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
602 int RHSC = (int)RHS->getZExtValue();
603 if ((RHSC & (Scale-1)) == 0) { // The constant is implicitly multiplied.
605 if (RHSC >= 0 && RHSC < 32) {
606 Base = N.getOperand(0);
607 Offset = CurDAG->getRegister(0, MVT::i32);
608 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
614 Base = N.getOperand(0);
615 Offset = N.getOperand(1);
616 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
620 bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDNode *Op, SDValue N,
621 SDValue &Base, SDValue &OffImm,
623 return SelectThumbAddrModeRI5(Op, N, 1, Base, OffImm, Offset);
626 bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDNode *Op, SDValue N,
627 SDValue &Base, SDValue &OffImm,
629 return SelectThumbAddrModeRI5(Op, N, 2, Base, OffImm, Offset);
632 bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDNode *Op, SDValue N,
633 SDValue &Base, SDValue &OffImm,
635 return SelectThumbAddrModeRI5(Op, N, 4, Base, OffImm, Offset);
638 bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDNode *Op, SDValue N,
639 SDValue &Base, SDValue &OffImm) {
640 if (N.getOpcode() == ISD::FrameIndex) {
641 int FI = cast<FrameIndexSDNode>(N)->getIndex();
642 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
643 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
647 if (N.getOpcode() != ISD::ADD)
650 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
651 if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
652 (LHSR && LHSR->getReg() == ARM::SP)) {
653 // If the RHS is + imm8 * scale, fold into addr mode.
654 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
655 int RHSC = (int)RHS->getZExtValue();
656 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied.
658 if (RHSC >= 0 && RHSC < 256) {
659 Base = N.getOperand(0);
660 if (Base.getOpcode() == ISD::FrameIndex) {
661 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
662 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
664 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
674 bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDNode *Op, SDValue N,
677 if (DisableShifterOp)
680 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
682 // Don't match base register only case. That is matched to a separate
683 // lower complexity pattern with explicit register operand.
684 if (ShOpcVal == ARM_AM::no_shift) return false;
686 BaseReg = N.getOperand(0);
687 unsigned ShImmVal = 0;
688 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
689 ShImmVal = RHS->getZExtValue() & 31;
690 Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
697 bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDNode *Op, SDValue N,
698 SDValue &Base, SDValue &OffImm) {
699 // Match simple R + imm12 operands.
702 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
703 if (N.getOpcode() == ISD::FrameIndex) {
704 // Match frame index...
705 int FI = cast<FrameIndexSDNode>(N)->getIndex();
706 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
707 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
709 } else if (N.getOpcode() == ARMISD::Wrapper &&
710 !(Subtarget->useMovt() &&
711 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
712 Base = N.getOperand(0);
713 if (Base.getOpcode() == ISD::TargetConstantPool)
714 return false; // We want to select t2LDRpci instead.
717 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
721 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
722 if (SelectT2AddrModeImm8(Op, N, Base, OffImm))
723 // Let t2LDRi8 handle (R - imm8).
726 int RHSC = (int)RHS->getZExtValue();
727 if (N.getOpcode() == ISD::SUB)
730 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
731 Base = N.getOperand(0);
732 if (Base.getOpcode() == ISD::FrameIndex) {
733 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
734 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
736 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
743 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
747 bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDNode *Op, SDValue N,
748 SDValue &Base, SDValue &OffImm) {
749 // Match simple R - imm8 operands.
750 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::SUB) {
751 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
752 int RHSC = (int)RHS->getSExtValue();
753 if (N.getOpcode() == ISD::SUB)
756 if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative)
757 Base = N.getOperand(0);
758 if (Base.getOpcode() == ISD::FrameIndex) {
759 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
760 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
762 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
771 bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
773 unsigned Opcode = Op->getOpcode();
774 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
775 ? cast<LoadSDNode>(Op)->getAddressingMode()
776 : cast<StoreSDNode>(Op)->getAddressingMode();
777 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N)) {
778 int RHSC = (int)RHS->getZExtValue();
779 if (RHSC >= 0 && RHSC < 0x100) { // 8 bits.
780 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
781 ? CurDAG->getTargetConstant(RHSC, MVT::i32)
782 : CurDAG->getTargetConstant(-RHSC, MVT::i32);
790 bool ARMDAGToDAGISel::SelectT2AddrModeImm8s4(SDNode *Op, SDValue N,
791 SDValue &Base, SDValue &OffImm) {
792 if (N.getOpcode() == ISD::ADD) {
793 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
794 int RHSC = (int)RHS->getZExtValue();
796 if (((RHSC & 0x3) == 0) &&
797 ((RHSC >= 0 && RHSC < 0x400) || (RHSC < 0 && RHSC > -0x400))) {
798 Base = N.getOperand(0);
799 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
803 } else if (N.getOpcode() == ISD::SUB) {
804 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
805 int RHSC = (int)RHS->getZExtValue();
807 if (((RHSC & 0x3) == 0) && (RHSC >= 0 && RHSC < 0x400)) {
808 Base = N.getOperand(0);
809 OffImm = CurDAG->getTargetConstant(-RHSC, MVT::i32);
818 bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDNode *Op, SDValue N,
820 SDValue &OffReg, SDValue &ShImm) {
821 // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.
822 if (N.getOpcode() != ISD::ADD)
825 // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8.
826 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
827 int RHSC = (int)RHS->getZExtValue();
828 if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned)
830 else if (RHSC < 0 && RHSC >= -255) // 8 bits
834 // Look for (R + R) or (R + (R << [1,2,3])).
836 Base = N.getOperand(0);
837 OffReg = N.getOperand(1);
839 // Swap if it is ((R << c) + R).
840 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg);
841 if (ShOpcVal != ARM_AM::lsl) {
842 ShOpcVal = ARM_AM::getShiftOpcForNode(Base);
843 if (ShOpcVal == ARM_AM::lsl)
844 std::swap(Base, OffReg);
847 if (ShOpcVal == ARM_AM::lsl) {
848 // Check to see if the RHS of the shift is a constant, if not, we can't fold
850 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
851 ShAmt = Sh->getZExtValue();
854 ShOpcVal = ARM_AM::no_shift;
856 OffReg = OffReg.getOperand(0);
858 ShOpcVal = ARM_AM::no_shift;
862 ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
867 //===--------------------------------------------------------------------===//
869 /// getAL - Returns a ARMCC::AL immediate node.
870 static inline SDValue getAL(SelectionDAG *CurDAG) {
871 return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
874 SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDNode *N) {
875 LoadSDNode *LD = cast<LoadSDNode>(N);
876 ISD::MemIndexedMode AM = LD->getAddressingMode();
877 if (AM == ISD::UNINDEXED)
880 EVT LoadedVT = LD->getMemoryVT();
881 SDValue Offset, AMOpc;
882 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
885 if (LoadedVT == MVT::i32 &&
886 SelectAddrMode2Offset(N, LD->getOffset(), Offset, AMOpc)) {
887 Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST;
889 } else if (LoadedVT == MVT::i16 &&
890 SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
892 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
893 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
894 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
895 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
896 if (LD->getExtensionType() == ISD::SEXTLOAD) {
897 if (SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
899 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
902 if (SelectAddrMode2Offset(N, LD->getOffset(), Offset, AMOpc)) {
904 Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST;
910 SDValue Chain = LD->getChain();
911 SDValue Base = LD->getBasePtr();
912 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
913 CurDAG->getRegister(0, MVT::i32), Chain };
914 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32,
921 SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDNode *N) {
922 LoadSDNode *LD = cast<LoadSDNode>(N);
923 ISD::MemIndexedMode AM = LD->getAddressingMode();
924 if (AM == ISD::UNINDEXED)
927 EVT LoadedVT = LD->getMemoryVT();
928 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
930 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
933 if (SelectT2AddrModeImm8Offset(N, LD->getOffset(), Offset)) {
934 switch (LoadedVT.getSimpleVT().SimpleTy) {
936 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
940 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
942 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
947 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
949 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
958 SDValue Chain = LD->getChain();
959 SDValue Base = LD->getBasePtr();
960 SDValue Ops[]= { Base, Offset, getAL(CurDAG),
961 CurDAG->getRegister(0, MVT::i32), Chain };
962 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32,
969 /// PairSRegs - Form a D register from a pair of S registers.
971 SDNode *ARMDAGToDAGISel::PairSRegs(EVT VT, SDValue V0, SDValue V1) {
972 DebugLoc dl = V0.getNode()->getDebugLoc();
973 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
974 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
975 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
976 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
979 /// PairDRegs - Form a quad register from a pair of D registers.
981 SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) {
982 DebugLoc dl = V0.getNode()->getDebugLoc();
983 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
984 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
985 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
986 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
989 /// PairQRegs - Form 4 consecutive D registers from a pair of Q registers.
991 SDNode *ARMDAGToDAGISel::PairQRegs(EVT VT, SDValue V0, SDValue V1) {
992 DebugLoc dl = V0.getNode()->getDebugLoc();
993 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
994 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
995 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
996 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
999 /// QuadSRegs - Form 4 consecutive S registers.
1001 SDNode *ARMDAGToDAGISel::QuadSRegs(EVT VT, SDValue V0, SDValue V1,
1002 SDValue V2, SDValue V3) {
1003 DebugLoc dl = V0.getNode()->getDebugLoc();
1004 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1005 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1006 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, MVT::i32);
1007 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::ssub_3, MVT::i32);
1008 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 };
1009 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
1012 /// QuadDRegs - Form 4 consecutive D registers.
1014 SDNode *ARMDAGToDAGISel::QuadDRegs(EVT VT, SDValue V0, SDValue V1,
1015 SDValue V2, SDValue V3) {
1016 DebugLoc dl = V0.getNode()->getDebugLoc();
1017 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1018 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1019 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, MVT::i32);
1020 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, MVT::i32);
1021 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 };
1022 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
1025 /// QuadQRegs - Form 4 consecutive Q registers.
1027 SDNode *ARMDAGToDAGISel::QuadQRegs(EVT VT, SDValue V0, SDValue V1,
1028 SDValue V2, SDValue V3) {
1029 DebugLoc dl = V0.getNode()->getDebugLoc();
1030 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1031 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1032 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, MVT::i32);
1033 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, MVT::i32);
1034 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 };
1035 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
1038 /// OctoDRegs - Form 8 consecutive D registers.
1040 SDNode *ARMDAGToDAGISel::OctoDRegs(EVT VT, SDValue V0, SDValue V1,
1041 SDValue V2, SDValue V3,
1042 SDValue V4, SDValue V5,
1043 SDValue V6, SDValue V7) {
1044 DebugLoc dl = V0.getNode()->getDebugLoc();
1045 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1046 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1047 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, MVT::i32);
1048 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, MVT::i32);
1049 SDValue SubReg4 = CurDAG->getTargetConstant(ARM::dsub_4, MVT::i32);
1050 SDValue SubReg5 = CurDAG->getTargetConstant(ARM::dsub_5, MVT::i32);
1051 SDValue SubReg6 = CurDAG->getTargetConstant(ARM::dsub_6, MVT::i32);
1052 SDValue SubReg7 = CurDAG->getTargetConstant(ARM::dsub_7, MVT::i32);
1053 const SDValue Ops[] ={ V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3,
1054 V4, SubReg4, V5, SubReg5, V6, SubReg6, V7, SubReg7 };
1055 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 16);
1058 /// GetNEONSubregVT - Given a type for a 128-bit NEON vector, return the type
1059 /// for a 64-bit subregister of the vector.
1060 static EVT GetNEONSubregVT(EVT VT) {
1061 switch (VT.getSimpleVT().SimpleTy) {
1062 default: llvm_unreachable("unhandled NEON type");
1063 case MVT::v16i8: return MVT::v8i8;
1064 case MVT::v8i16: return MVT::v4i16;
1065 case MVT::v4f32: return MVT::v2f32;
1066 case MVT::v4i32: return MVT::v2i32;
1067 case MVT::v2i64: return MVT::v1i64;
1071 SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, unsigned NumVecs,
1072 unsigned *DOpcodes, unsigned *QOpcodes0,
1073 unsigned *QOpcodes1) {
1074 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range");
1075 DebugLoc dl = N->getDebugLoc();
1077 SDValue MemAddr, Align;
1078 if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, Align))
1081 SDValue Chain = N->getOperand(0);
1082 EVT VT = N->getValueType(0);
1083 bool is64BitVector = VT.is64BitVector();
1085 unsigned OpcodeIndex;
1086 switch (VT.getSimpleVT().SimpleTy) {
1087 default: llvm_unreachable("unhandled vld type");
1088 // Double-register operations:
1089 case MVT::v8i8: OpcodeIndex = 0; break;
1090 case MVT::v4i16: OpcodeIndex = 1; break;
1092 case MVT::v2i32: OpcodeIndex = 2; break;
1093 case MVT::v1i64: OpcodeIndex = 3; break;
1094 // Quad-register operations:
1095 case MVT::v16i8: OpcodeIndex = 0; break;
1096 case MVT::v8i16: OpcodeIndex = 1; break;
1098 case MVT::v4i32: OpcodeIndex = 2; break;
1099 case MVT::v2i64: OpcodeIndex = 3;
1100 assert(NumVecs == 1 && "v2i64 type only supported for VLD1");
1104 SDValue Pred = getAL(CurDAG);
1105 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1106 if (is64BitVector) {
1107 unsigned Opc = DOpcodes[OpcodeIndex];
1108 const SDValue Ops[] = { MemAddr, Align, Pred, Reg0, Chain };
1109 std::vector<EVT> ResTys(NumVecs, VT);
1110 ResTys.push_back(MVT::Other);
1111 SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 5);
1116 SDValue V0 = SDValue(VLd, 0);
1117 SDValue V1 = SDValue(VLd, 1);
1119 // Form a REG_SEQUENCE to force register allocation.
1121 RegSeq = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1123 SDValue V2 = SDValue(VLd, 2);
1124 // If it's a vld3, form a quad D-register but discard the last part.
1125 SDValue V3 = (NumVecs == 3)
1126 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1128 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1131 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1132 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1133 SDValue D = CurDAG->getTargetExtractSubreg(ARM::dsub_0+Vec,
1135 ReplaceUses(SDValue(N, Vec), D);
1137 ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, NumVecs));
1141 EVT RegVT = GetNEONSubregVT(VT);
1143 // Quad registers are directly supported for VLD1 and VLD2,
1144 // loading pairs of D regs.
1145 unsigned Opc = QOpcodes0[OpcodeIndex];
1146 const SDValue Ops[] = { MemAddr, Align, Pred, Reg0, Chain };
1147 std::vector<EVT> ResTys(2 * NumVecs, RegVT);
1148 ResTys.push_back(MVT::Other);
1149 SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 5);
1150 Chain = SDValue(VLd, 2 * NumVecs);
1152 // Combine the even and odd subregs to produce the result.
1154 SDNode *Q = PairDRegs(VT, SDValue(VLd, 0), SDValue(VLd, 1));
1155 ReplaceUses(SDValue(N, 0), SDValue(Q, 0));
1157 SDValue QQ = SDValue(QuadDRegs(MVT::v4i64,
1158 SDValue(VLd, 0), SDValue(VLd, 1),
1159 SDValue(VLd, 2), SDValue(VLd, 3)), 0);
1160 SDValue Q0 = CurDAG->getTargetExtractSubreg(ARM::qsub_0, dl, VT, QQ);
1161 SDValue Q1 = CurDAG->getTargetExtractSubreg(ARM::qsub_1, dl, VT, QQ);
1162 ReplaceUses(SDValue(N, 0), Q0);
1163 ReplaceUses(SDValue(N, 1), Q1);
1166 // Otherwise, quad registers are loaded with two separate instructions,
1167 // where one loads the even registers and the other loads the odd registers.
1169 std::vector<EVT> ResTys(NumVecs, RegVT);
1170 ResTys.push_back(MemAddr.getValueType());
1171 ResTys.push_back(MVT::Other);
1173 // Load the even subregs.
1174 unsigned Opc = QOpcodes0[OpcodeIndex];
1175 const SDValue OpsA[] = { MemAddr, Align, Reg0, Pred, Reg0, Chain };
1176 SDNode *VLdA = CurDAG->getMachineNode(Opc, dl, ResTys, OpsA, 6);
1177 Chain = SDValue(VLdA, NumVecs+1);
1179 // Load the odd subregs.
1180 Opc = QOpcodes1[OpcodeIndex];
1181 const SDValue OpsB[] = { SDValue(VLdA, NumVecs),
1182 Align, Reg0, Pred, Reg0, Chain };
1183 SDNode *VLdB = CurDAG->getMachineNode(Opc, dl, ResTys, OpsB, 6);
1184 Chain = SDValue(VLdB, NumVecs+1);
1186 SDValue V0 = SDValue(VLdA, 0);
1187 SDValue V1 = SDValue(VLdB, 0);
1188 SDValue V2 = SDValue(VLdA, 1);
1189 SDValue V3 = SDValue(VLdB, 1);
1190 SDValue V4 = SDValue(VLdA, 2);
1191 SDValue V5 = SDValue(VLdB, 2);
1192 SDValue V6 = (NumVecs == 3)
1193 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,RegVT), 0)
1195 SDValue V7 = (NumVecs == 3)
1196 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,RegVT), 0)
1198 SDValue RegSeq = SDValue(OctoDRegs(MVT::v8i64, V0, V1, V2, V3,
1199 V4, V5, V6, V7), 0);
1201 // Extract out the 3 / 4 Q registers.
1202 assert(ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1203 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1204 SDValue Q = CurDAG->getTargetExtractSubreg(ARM::qsub_0+Vec,
1206 ReplaceUses(SDValue(N, Vec), Q);
1209 ReplaceUses(SDValue(N, NumVecs), Chain);
1213 SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, unsigned NumVecs,
1214 unsigned *DOpcodes, unsigned *QOpcodes0,
1215 unsigned *QOpcodes1) {
1216 assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range");
1217 DebugLoc dl = N->getDebugLoc();
1219 SDValue MemAddr, Align;
1220 if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, Align))
1223 SDValue Chain = N->getOperand(0);
1224 EVT VT = N->getOperand(3).getValueType();
1225 bool is64BitVector = VT.is64BitVector();
1227 unsigned OpcodeIndex;
1228 switch (VT.getSimpleVT().SimpleTy) {
1229 default: llvm_unreachable("unhandled vst type");
1230 // Double-register operations:
1231 case MVT::v8i8: OpcodeIndex = 0; break;
1232 case MVT::v4i16: OpcodeIndex = 1; break;
1234 case MVT::v2i32: OpcodeIndex = 2; break;
1235 case MVT::v1i64: OpcodeIndex = 3; break;
1236 // Quad-register operations:
1237 case MVT::v16i8: OpcodeIndex = 0; break;
1238 case MVT::v8i16: OpcodeIndex = 1; break;
1240 case MVT::v4i32: OpcodeIndex = 2; break;
1241 case MVT::v2i64: OpcodeIndex = 3;
1242 assert(NumVecs == 1 && "v2i64 type only supported for VST1");
1246 SDValue Pred = getAL(CurDAG);
1247 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1249 SmallVector<SDValue, 10> Ops;
1250 Ops.push_back(MemAddr);
1251 Ops.push_back(Align);
1253 if (is64BitVector) {
1256 SDValue V0 = N->getOperand(0+3);
1257 SDValue V1 = N->getOperand(1+3);
1259 // Form a REG_SEQUENCE to force register allocation.
1261 RegSeq = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1263 SDValue V2 = N->getOperand(2+3);
1264 // If it's a vld3, form a quad D-register and leave the last part as
1266 SDValue V3 = (NumVecs == 3)
1267 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1268 : N->getOperand(3+3);
1269 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1272 // Now extract the D registers back out.
1273 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_0, dl, VT,
1275 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_1, dl, VT,
1278 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_2, dl, VT,
1281 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_3, dl, VT,
1284 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1285 Ops.push_back(N->getOperand(Vec+3));
1287 Ops.push_back(Pred);
1288 Ops.push_back(Reg0); // predicate register
1289 Ops.push_back(Chain);
1290 unsigned Opc = DOpcodes[OpcodeIndex];
1291 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), NumVecs+5);
1294 EVT RegVT = GetNEONSubregVT(VT);
1296 // Quad registers are directly supported for VST1 and VST2,
1297 // storing pairs of D regs.
1298 unsigned Opc = QOpcodes0[OpcodeIndex];
1300 // First extract the pair of Q registers.
1301 SDValue Q0 = N->getOperand(3);
1302 SDValue Q1 = N->getOperand(4);
1304 // Form a QQ register.
1305 SDValue QQ = SDValue(PairQRegs(MVT::v4i64, Q0, Q1), 0);
1307 // Now extract the D registers back out.
1308 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_0, dl, RegVT,
1310 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_1, dl, RegVT,
1312 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_2, dl, RegVT,
1314 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_3, dl, RegVT,
1316 Ops.push_back(Pred);
1317 Ops.push_back(Reg0); // predicate register
1318 Ops.push_back(Chain);
1319 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 5 + 4);
1321 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1322 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_0, dl, RegVT,
1323 N->getOperand(Vec+3)));
1324 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_1, dl, RegVT,
1325 N->getOperand(Vec+3)));
1327 Ops.push_back(Pred);
1328 Ops.push_back(Reg0); // predicate register
1329 Ops.push_back(Chain);
1330 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(),
1335 // Otherwise, quad registers are stored with two separate instructions,
1336 // where one stores the even registers and the other stores the odd registers.
1338 // Form the QQQQ REG_SEQUENCE.
1340 for (unsigned Vec = 0, i = 0; Vec < NumVecs; ++Vec, i+=2) {
1341 V[i] = CurDAG->getTargetExtractSubreg(ARM::dsub_0, dl, RegVT,
1342 N->getOperand(Vec+3));
1343 V[i+1] = CurDAG->getTargetExtractSubreg(ARM::dsub_1, dl, RegVT,
1344 N->getOperand(Vec+3));
1347 V[6] = V[7] = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
1350 SDValue RegSeq = SDValue(OctoDRegs(MVT::v8i64, V[0], V[1], V[2], V[3],
1351 V[4], V[5], V[6], V[7]), 0);
1353 // Store the even D registers.
1354 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1355 Ops.push_back(Reg0); // post-access address offset
1356 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1357 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_0+Vec*2, dl,
1359 Ops.push_back(Pred);
1360 Ops.push_back(Reg0); // predicate register
1361 Ops.push_back(Chain);
1362 unsigned Opc = QOpcodes0[OpcodeIndex];
1363 SDNode *VStA = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
1364 MVT::Other, Ops.data(), NumVecs+6);
1365 Chain = SDValue(VStA, 1);
1367 // Store the odd D registers.
1368 Ops[0] = SDValue(VStA, 0); // MemAddr
1369 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1370 Ops[Vec+3] = CurDAG->getTargetExtractSubreg(ARM::dsub_1+Vec*2, dl,
1372 Ops[NumVecs+5] = Chain;
1373 Opc = QOpcodes1[OpcodeIndex];
1374 SDNode *VStB = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
1375 MVT::Other, Ops.data(), NumVecs+6);
1376 Chain = SDValue(VStB, 1);
1377 ReplaceUses(SDValue(N, 0), Chain);
1381 SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
1382 unsigned NumVecs, unsigned *DOpcodes,
1383 unsigned *QOpcodes0,
1384 unsigned *QOpcodes1) {
1385 assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
1386 DebugLoc dl = N->getDebugLoc();
1388 SDValue MemAddr, Align;
1389 if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, Align))
1392 SDValue Chain = N->getOperand(0);
1394 cast<ConstantSDNode>(N->getOperand(NumVecs+3))->getZExtValue();
1395 EVT VT = IsLoad ? N->getValueType(0) : N->getOperand(3).getValueType();
1396 bool is64BitVector = VT.is64BitVector();
1398 // Quad registers are handled by load/store of subregs. Find the subreg info.
1399 unsigned NumElts = 0;
1402 if (!is64BitVector) {
1403 RegVT = GetNEONSubregVT(VT);
1404 NumElts = RegVT.getVectorNumElements();
1405 Even = Lane < NumElts;
1408 unsigned OpcodeIndex;
1409 switch (VT.getSimpleVT().SimpleTy) {
1410 default: llvm_unreachable("unhandled vld/vst lane type");
1411 // Double-register operations:
1412 case MVT::v8i8: OpcodeIndex = 0; break;
1413 case MVT::v4i16: OpcodeIndex = 1; break;
1415 case MVT::v2i32: OpcodeIndex = 2; break;
1416 // Quad-register operations:
1417 case MVT::v8i16: OpcodeIndex = 0; break;
1419 case MVT::v4i32: OpcodeIndex = 1; break;
1422 SDValue Pred = getAL(CurDAG);
1423 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1425 SmallVector<SDValue, 10> Ops;
1426 Ops.push_back(MemAddr);
1427 Ops.push_back(Align);
1430 if (is64BitVector) {
1431 Opc = DOpcodes[OpcodeIndex];
1433 SDValue V0 = N->getOperand(0+3);
1434 SDValue V1 = N->getOperand(1+3);
1436 RegSeq = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1438 SDValue V2 = N->getOperand(2+3);
1439 SDValue V3 = (NumVecs == 3)
1440 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1441 : N->getOperand(3+3);
1442 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1445 // Now extract the D registers back out.
1446 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_0, dl, VT, RegSeq));
1447 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_1, dl, VT, RegSeq));
1449 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_2, dl, VT,RegSeq));
1451 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_3, dl, VT,RegSeq));
1453 // Check if this is loading the even or odd subreg of a Q register.
1454 if (Lane < NumElts) {
1455 Opc = QOpcodes0[OpcodeIndex];
1458 Opc = QOpcodes1[OpcodeIndex];
1462 SDValue V0 = N->getOperand(0+3);
1463 SDValue V1 = N->getOperand(1+3);
1465 RegSeq = SDValue(PairQRegs(MVT::v4i64, V0, V1), 0);
1467 SDValue V2 = N->getOperand(2+3);
1468 SDValue V3 = (NumVecs == 3)
1469 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1470 : N->getOperand(3+3);
1471 RegSeq = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);
1474 // Extract the subregs of the input vector.
1475 unsigned SubIdx = Even ? ARM::dsub_0 : ARM::dsub_1;
1476 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1477 Ops.push_back(CurDAG->getTargetExtractSubreg(SubIdx+Vec*2, dl, RegVT,
1480 Ops.push_back(getI32Imm(Lane));
1481 Ops.push_back(Pred);
1482 Ops.push_back(Reg0);
1483 Ops.push_back(Chain);
1486 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), NumVecs+6);
1488 std::vector<EVT> ResTys(NumVecs, RegVT);
1489 ResTys.push_back(MVT::Other);
1490 SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(),NumVecs+6);
1492 // Form a REG_SEQUENCE to force register allocation.
1494 if (is64BitVector) {
1495 SDValue V0 = SDValue(VLdLn, 0);
1496 SDValue V1 = SDValue(VLdLn, 1);
1498 RegSeq = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1500 SDValue V2 = SDValue(VLdLn, 2);
1501 // If it's a vld3, form a quad D-register but discard the last part.
1502 SDValue V3 = (NumVecs == 3)
1503 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1504 : SDValue(VLdLn, 3);
1505 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1508 // For 128-bit vectors, take the 64-bit results of the load and insert
1509 // them as subregs into the result.
1511 for (unsigned Vec = 0, i = 0; Vec < NumVecs; ++Vec, i+=2) {
1513 V[i] = SDValue(VLdLn, Vec);
1514 V[i+1] = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
1517 V[i] = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
1519 V[i+1] = SDValue(VLdLn, Vec);
1523 V[6] = V[7] = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
1527 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V[0], V[1], V[2], V[3]), 0);
1529 RegSeq = SDValue(OctoDRegs(MVT::v8i64, V[0], V[1], V[2], V[3],
1530 V[4], V[5], V[6], V[7]), 0);
1533 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1534 assert(ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1535 unsigned SubIdx = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;
1536 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1537 ReplaceUses(SDValue(N, Vec),
1538 CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, RegSeq));
1539 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, NumVecs));
1543 SDNode *ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs,
1545 assert(NumVecs >= 2 && NumVecs <= 4 && "VTBL NumVecs out-of-range");
1546 DebugLoc dl = N->getDebugLoc();
1547 EVT VT = N->getValueType(0);
1548 unsigned FirstTblReg = IsExt ? 2 : 1;
1550 // Form a REG_SEQUENCE to force register allocation.
1552 SDValue V0 = N->getOperand(FirstTblReg + 0);
1553 SDValue V1 = N->getOperand(FirstTblReg + 1);
1555 RegSeq = SDValue(PairDRegs(MVT::v16i8, V0, V1), 0);
1557 SDValue V2 = N->getOperand(FirstTblReg + 2);
1558 // If it's a vtbl3, form a quad D-register and leave the last part as
1560 SDValue V3 = (NumVecs == 3)
1561 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1562 : N->getOperand(FirstTblReg + 3);
1563 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1566 // Now extract the D registers back out.
1567 SmallVector<SDValue, 6> Ops;
1569 Ops.push_back(N->getOperand(1));
1570 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_0, dl, VT, RegSeq));
1571 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_1, dl, VT, RegSeq));
1573 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_2, dl, VT, RegSeq));
1575 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::dsub_3, dl, VT, RegSeq));
1577 Ops.push_back(N->getOperand(FirstTblReg + NumVecs));
1578 Ops.push_back(getAL(CurDAG)); // predicate
1579 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // predicate register
1580 return CurDAG->getMachineNode(Opc, dl, VT, Ops.data(), Ops.size());
1583 SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N,
1585 if (!Subtarget->hasV6T2Ops())
1588 unsigned Opc = isSigned ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX)
1589 : (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX);
1592 // For unsigned extracts, check for a shift right and mask
1593 unsigned And_imm = 0;
1594 if (N->getOpcode() == ISD::AND) {
1595 if (isOpcWithIntImmediate(N, ISD::AND, And_imm)) {
1597 // The immediate is a mask of the low bits iff imm & (imm+1) == 0
1598 if (And_imm & (And_imm + 1))
1601 unsigned Srl_imm = 0;
1602 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL,
1604 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
1606 unsigned Width = CountTrailingOnes_32(And_imm);
1607 unsigned LSB = Srl_imm;
1608 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1609 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1610 CurDAG->getTargetConstant(LSB, MVT::i32),
1611 CurDAG->getTargetConstant(Width, MVT::i32),
1612 getAL(CurDAG), Reg0 };
1613 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1619 // Otherwise, we're looking for a shift of a shift
1620 unsigned Shl_imm = 0;
1621 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, Shl_imm)) {
1622 assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!");
1623 unsigned Srl_imm = 0;
1624 if (isInt32Immediate(N->getOperand(1), Srl_imm)) {
1625 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
1626 unsigned Width = 32 - Srl_imm;
1627 int LSB = Srl_imm - Shl_imm;
1630 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1631 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1632 CurDAG->getTargetConstant(LSB, MVT::i32),
1633 CurDAG->getTargetConstant(Width, MVT::i32),
1634 getAL(CurDAG), Reg0 };
1635 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1641 SDNode *ARMDAGToDAGISel::
1642 SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1643 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1646 if (SelectT2ShifterOperandReg(N, TrueVal, CPTmp0, CPTmp1)) {
1647 unsigned SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue();
1648 unsigned SOShOp = ARM_AM::getSORegShOp(SOVal);
1651 case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break;
1652 case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break;
1653 case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break;
1654 case ARM_AM::ror: Opc = ARM::t2MOVCCror; break;
1656 llvm_unreachable("Unknown so_reg opcode!");
1660 CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32);
1661 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1662 SDValue Ops[] = { FalseVal, CPTmp0, SOShImm, CC, CCR, InFlag };
1663 return CurDAG->SelectNodeTo(N, Opc, MVT::i32,Ops, 6);
1668 SDNode *ARMDAGToDAGISel::
1669 SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1670 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1674 if (SelectShifterOperandReg(N, TrueVal, CPTmp0, CPTmp1, CPTmp2)) {
1675 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1676 SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CPTmp2, CC, CCR, InFlag };
1677 return CurDAG->SelectNodeTo(N, ARM::MOVCCs, MVT::i32, Ops, 7);
1682 SDNode *ARMDAGToDAGISel::
1683 SelectT2CMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1684 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1685 ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
1689 if (Predicate_t2_so_imm(TrueVal.getNode())) {
1690 SDValue True = CurDAG->getTargetConstant(T->getZExtValue(), MVT::i32);
1691 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1692 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
1693 return CurDAG->SelectNodeTo(N,
1694 ARM::t2MOVCCi, MVT::i32, Ops, 5);
1699 SDNode *ARMDAGToDAGISel::
1700 SelectARMCMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1701 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1702 ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
1706 if (Predicate_so_imm(TrueVal.getNode())) {
1707 SDValue True = CurDAG->getTargetConstant(T->getZExtValue(), MVT::i32);
1708 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1709 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
1710 return CurDAG->SelectNodeTo(N,
1711 ARM::MOVCCi, MVT::i32, Ops, 5);
1716 SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDNode *N) {
1717 EVT VT = N->getValueType(0);
1718 SDValue FalseVal = N->getOperand(0);
1719 SDValue TrueVal = N->getOperand(1);
1720 SDValue CC = N->getOperand(2);
1721 SDValue CCR = N->getOperand(3);
1722 SDValue InFlag = N->getOperand(4);
1723 assert(CC.getOpcode() == ISD::Constant);
1724 assert(CCR.getOpcode() == ISD::Register);
1725 ARMCC::CondCodes CCVal =
1726 (ARMCC::CondCodes)cast<ConstantSDNode>(CC)->getZExtValue();
1728 if (!Subtarget->isThumb1Only() && VT == MVT::i32) {
1729 // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1730 // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1731 // Pattern complexity = 18 cost = 1 size = 0
1735 if (Subtarget->isThumb()) {
1736 SDNode *Res = SelectT2CMOVShiftOp(N, FalseVal, TrueVal,
1737 CCVal, CCR, InFlag);
1739 Res = SelectT2CMOVShiftOp(N, TrueVal, FalseVal,
1740 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1744 SDNode *Res = SelectARMCMOVShiftOp(N, FalseVal, TrueVal,
1745 CCVal, CCR, InFlag);
1747 Res = SelectARMCMOVShiftOp(N, TrueVal, FalseVal,
1748 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1753 // Pattern: (ARMcmov:i32 GPR:i32:$false,
1754 // (imm:i32)<<P:Predicate_so_imm>>:$true,
1756 // Emits: (MOVCCi:i32 GPR:i32:$false,
1757 // (so_imm:i32 (imm:i32):$true), (imm:i32):$cc)
1758 // Pattern complexity = 10 cost = 1 size = 0
1759 if (Subtarget->isThumb()) {
1760 SDNode *Res = SelectT2CMOVSoImmOp(N, FalseVal, TrueVal,
1761 CCVal, CCR, InFlag);
1763 Res = SelectT2CMOVSoImmOp(N, TrueVal, FalseVal,
1764 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1768 SDNode *Res = SelectARMCMOVSoImmOp(N, FalseVal, TrueVal,
1769 CCVal, CCR, InFlag);
1771 Res = SelectARMCMOVSoImmOp(N, TrueVal, FalseVal,
1772 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1778 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1779 // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1780 // Pattern complexity = 6 cost = 1 size = 0
1782 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1783 // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1784 // Pattern complexity = 6 cost = 11 size = 0
1786 // Also FCPYScc and FCPYDcc.
1787 SDValue Tmp2 = CurDAG->getTargetConstant(CCVal, MVT::i32);
1788 SDValue Ops[] = { FalseVal, TrueVal, Tmp2, CCR, InFlag };
1790 switch (VT.getSimpleVT().SimpleTy) {
1791 default: assert(false && "Illegal conditional move type!");
1794 Opc = Subtarget->isThumb()
1795 ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo)
1805 return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
1808 SDNode *ARMDAGToDAGISel::SelectConcatVector(SDNode *N) {
1809 // The only time a CONCAT_VECTORS operation can have legal types is when
1810 // two 64-bit vectors are concatenated to a 128-bit vector.
1811 EVT VT = N->getValueType(0);
1812 if (!VT.is128BitVector() || N->getNumOperands() != 2)
1813 llvm_unreachable("unexpected CONCAT_VECTORS");
1814 DebugLoc dl = N->getDebugLoc();
1815 SDValue V0 = N->getOperand(0);
1816 SDValue V1 = N->getOperand(1);
1817 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1818 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1819 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
1820 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
1823 SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
1824 DebugLoc dl = N->getDebugLoc();
1826 if (N->isMachineOpcode())
1827 return NULL; // Already selected.
1829 switch (N->getOpcode()) {
1831 case ISD::Constant: {
1832 unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
1834 if (Subtarget->hasThumb2())
1835 // Thumb2-aware targets have the MOVT instruction, so all immediates can
1836 // be done with MOV + MOVT, at worst.
1839 if (Subtarget->isThumb()) {
1840 UseCP = (Val > 255 && // MOV
1841 ~Val > 255 && // MOV + MVN
1842 !ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL
1844 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
1845 ARM_AM::getSOImmVal(~Val) == -1 && // MVN
1846 !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs.
1851 CurDAG->getTargetConstantPool(ConstantInt::get(
1852 Type::getInt32Ty(*CurDAG->getContext()), Val),
1853 TLI.getPointerTy());
1856 if (Subtarget->isThumb1Only()) {
1857 SDValue Pred = getAL(CurDAG);
1858 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
1859 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
1860 ResNode = CurDAG->getMachineNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other,
1865 CurDAG->getRegister(0, MVT::i32),
1866 CurDAG->getTargetConstant(0, MVT::i32),
1868 CurDAG->getRegister(0, MVT::i32),
1869 CurDAG->getEntryNode()
1871 ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
1874 ReplaceUses(SDValue(N, 0), SDValue(ResNode, 0));
1878 // Other cases are autogenerated.
1881 case ISD::FrameIndex: {
1882 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
1883 int FI = cast<FrameIndexSDNode>(N)->getIndex();
1884 SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1885 if (Subtarget->isThumb1Only()) {
1886 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
1887 CurDAG->getTargetConstant(0, MVT::i32));
1889 unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
1890 ARM::t2ADDri : ARM::ADDri);
1891 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
1892 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1893 CurDAG->getRegister(0, MVT::i32) };
1894 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1898 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
1902 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, true))
1906 if (Subtarget->isThumb1Only())
1908 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1909 unsigned RHSV = C->getZExtValue();
1911 if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
1912 unsigned ShImm = Log2_32(RHSV-1);
1915 SDValue V = N->getOperand(0);
1916 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
1917 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
1918 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1919 if (Subtarget->isThumb()) {
1920 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1921 return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
1923 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1924 return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7);
1927 if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
1928 unsigned ShImm = Log2_32(RHSV+1);
1931 SDValue V = N->getOperand(0);
1932 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
1933 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
1934 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1935 if (Subtarget->isThumb()) {
1936 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1937 return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 6);
1939 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1940 return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7);
1946 // Check for unsigned bitfield extract
1947 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
1950 // (and (or x, c2), c1) and top 16-bits of c1 and c2 match, lower 16-bits
1951 // of c1 are 0xffff, and lower 16-bit of c2 are 0. That is, the top 16-bits
1952 // are entirely contributed by c2 and lower 16-bits are entirely contributed
1953 // by x. That's equal to (or (and x, 0xffff), (and c1, 0xffff0000)).
1954 // Select it to: "movt x, ((c1 & 0xffff) >> 16)
1955 EVT VT = N->getValueType(0);
1958 unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2())
1960 : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0);
1963 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
1964 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1967 if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) {
1968 SDValue N2 = N0.getOperand(1);
1969 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1972 unsigned N1CVal = N1C->getZExtValue();
1973 unsigned N2CVal = N2C->getZExtValue();
1974 if ((N1CVal & 0xffff0000U) == (N2CVal & 0xffff0000U) &&
1975 (N1CVal & 0xffffU) == 0xffffU &&
1976 (N2CVal & 0xffffU) == 0x0U) {
1977 SDValue Imm16 = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16,
1979 SDValue Ops[] = { N0.getOperand(0), Imm16,
1980 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
1981 return CurDAG->getMachineNode(Opc, dl, VT, Ops, 4);
1986 case ARMISD::VMOVRRD:
1987 return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32,
1988 N->getOperand(0), getAL(CurDAG),
1989 CurDAG->getRegister(0, MVT::i32));
1990 case ISD::UMUL_LOHI: {
1991 if (Subtarget->isThumb1Only())
1993 if (Subtarget->isThumb()) {
1994 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
1995 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1996 CurDAG->getRegister(0, MVT::i32) };
1997 return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32,Ops,4);
1999 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2000 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2001 CurDAG->getRegister(0, MVT::i32) };
2002 return CurDAG->getMachineNode(ARM::UMULL, dl, MVT::i32, MVT::i32, Ops, 5);
2005 case ISD::SMUL_LOHI: {
2006 if (Subtarget->isThumb1Only())
2008 if (Subtarget->isThumb()) {
2009 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2010 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2011 return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32,Ops,4);
2013 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2014 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2015 CurDAG->getRegister(0, MVT::i32) };
2016 return CurDAG->getMachineNode(ARM::SMULL, dl, MVT::i32, MVT::i32, Ops, 5);
2020 SDNode *ResNode = 0;
2021 if (Subtarget->isThumb() && Subtarget->hasThumb2())
2022 ResNode = SelectT2IndexedLoad(N);
2024 ResNode = SelectARMIndexedLoad(N);
2028 // VLDMQ must be custom-selected for "v2f64 load" to set the AM5Opc value.
2029 if (Subtarget->hasVFP2() &&
2030 N->getValueType(0).getSimpleVT().SimpleTy == MVT::v2f64) {
2031 SDValue Chain = N->getOperand(0);
2033 CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::ia, 4), MVT::i32);
2034 SDValue Pred = getAL(CurDAG);
2035 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2036 SDValue Ops[] = { N->getOperand(1), AM5Opc, Pred, PredReg, Chain };
2037 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2038 MemOp[0] = cast<MemSDNode>(N)->getMemOperand();
2039 SDNode *Ret = CurDAG->getMachineNode(ARM::VLDMQ, dl,
2040 MVT::v2f64, MVT::Other, Ops, 5);
2041 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
2044 // Other cases are autogenerated.
2048 // VSTMQ must be custom-selected for "v2f64 store" to set the AM5Opc value.
2049 if (Subtarget->hasVFP2() &&
2050 N->getOperand(1).getValueType().getSimpleVT().SimpleTy == MVT::v2f64) {
2051 SDValue Chain = N->getOperand(0);
2053 CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::ia, 4), MVT::i32);
2054 SDValue Pred = getAL(CurDAG);
2055 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2056 SDValue Ops[] = { N->getOperand(1), N->getOperand(2),
2057 AM5Opc, Pred, PredReg, Chain };
2058 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2059 MemOp[0] = cast<MemSDNode>(N)->getMemOperand();
2060 SDNode *Ret = CurDAG->getMachineNode(ARM::VSTMQ, dl, MVT::Other, Ops, 6);
2061 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
2064 // Other cases are autogenerated.
2067 case ARMISD::BRCOND: {
2068 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2069 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2070 // Pattern complexity = 6 cost = 1 size = 0
2072 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2073 // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
2074 // Pattern complexity = 6 cost = 1 size = 0
2076 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2077 // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2078 // Pattern complexity = 6 cost = 1 size = 0
2080 unsigned Opc = Subtarget->isThumb() ?
2081 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
2082 SDValue Chain = N->getOperand(0);
2083 SDValue N1 = N->getOperand(1);
2084 SDValue N2 = N->getOperand(2);
2085 SDValue N3 = N->getOperand(3);
2086 SDValue InFlag = N->getOperand(4);
2087 assert(N1.getOpcode() == ISD::BasicBlock);
2088 assert(N2.getOpcode() == ISD::Constant);
2089 assert(N3.getOpcode() == ISD::Register);
2091 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
2092 cast<ConstantSDNode>(N2)->getZExtValue()),
2094 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
2095 SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,
2097 Chain = SDValue(ResNode, 0);
2098 if (N->getNumValues() == 2) {
2099 InFlag = SDValue(ResNode, 1);
2100 ReplaceUses(SDValue(N, 1), InFlag);
2102 ReplaceUses(SDValue(N, 0),
2103 SDValue(Chain.getNode(), Chain.getResNo()));
2107 return SelectCMOVOp(N);
2108 case ARMISD::CNEG: {
2109 EVT VT = N->getValueType(0);
2110 SDValue N0 = N->getOperand(0);
2111 SDValue N1 = N->getOperand(1);
2112 SDValue N2 = N->getOperand(2);
2113 SDValue N3 = N->getOperand(3);
2114 SDValue InFlag = N->getOperand(4);
2115 assert(N2.getOpcode() == ISD::Constant);
2116 assert(N3.getOpcode() == ISD::Register);
2118 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
2119 cast<ConstantSDNode>(N2)->getZExtValue()),
2121 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
2123 switch (VT.getSimpleVT().SimpleTy) {
2124 default: assert(false && "Illegal conditional move type!");
2133 return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
2136 case ARMISD::VZIP: {
2138 EVT VT = N->getValueType(0);
2139 switch (VT.getSimpleVT().SimpleTy) {
2140 default: return NULL;
2141 case MVT::v8i8: Opc = ARM::VZIPd8; break;
2142 case MVT::v4i16: Opc = ARM::VZIPd16; break;
2144 case MVT::v2i32: Opc = ARM::VZIPd32; break;
2145 case MVT::v16i8: Opc = ARM::VZIPq8; break;
2146 case MVT::v8i16: Opc = ARM::VZIPq16; break;
2148 case MVT::v4i32: Opc = ARM::VZIPq32; break;
2150 SDValue Pred = getAL(CurDAG);
2151 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2152 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2153 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2155 case ARMISD::VUZP: {
2157 EVT VT = N->getValueType(0);
2158 switch (VT.getSimpleVT().SimpleTy) {
2159 default: return NULL;
2160 case MVT::v8i8: Opc = ARM::VUZPd8; break;
2161 case MVT::v4i16: Opc = ARM::VUZPd16; break;
2163 case MVT::v2i32: Opc = ARM::VUZPd32; break;
2164 case MVT::v16i8: Opc = ARM::VUZPq8; break;
2165 case MVT::v8i16: Opc = ARM::VUZPq16; break;
2167 case MVT::v4i32: Opc = ARM::VUZPq32; break;
2169 SDValue Pred = getAL(CurDAG);
2170 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2171 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2172 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2174 case ARMISD::VTRN: {
2176 EVT VT = N->getValueType(0);
2177 switch (VT.getSimpleVT().SimpleTy) {
2178 default: return NULL;
2179 case MVT::v8i8: Opc = ARM::VTRNd8; break;
2180 case MVT::v4i16: Opc = ARM::VTRNd16; break;
2182 case MVT::v2i32: Opc = ARM::VTRNd32; break;
2183 case MVT::v16i8: Opc = ARM::VTRNq8; break;
2184 case MVT::v8i16: Opc = ARM::VTRNq16; break;
2186 case MVT::v4i32: Opc = ARM::VTRNq32; break;
2188 SDValue Pred = getAL(CurDAG);
2189 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2190 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2191 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2193 case ARMISD::BUILD_VECTOR: {
2194 EVT VecVT = N->getValueType(0);
2195 EVT EltVT = VecVT.getVectorElementType();
2196 unsigned NumElts = VecVT.getVectorNumElements();
2197 if (EltVT.getSimpleVT() == MVT::f64) {
2198 assert(NumElts == 2 && "unexpected type for BUILD_VECTOR");
2199 return PairDRegs(VecVT, N->getOperand(0), N->getOperand(1));
2201 assert(EltVT.getSimpleVT() == MVT::f32 &&
2202 "unexpected type for BUILD_VECTOR");
2204 return PairSRegs(VecVT, N->getOperand(0), N->getOperand(1));
2205 assert(NumElts == 4 && "unexpected type for BUILD_VECTOR");
2206 return QuadSRegs(VecVT, N->getOperand(0), N->getOperand(1),
2207 N->getOperand(2), N->getOperand(3));
2210 case ISD::INTRINSIC_VOID:
2211 case ISD::INTRINSIC_W_CHAIN: {
2212 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
2217 case Intrinsic::arm_neon_vld1: {
2218 unsigned DOpcodes[] = { ARM::VLD1d8, ARM::VLD1d16,
2219 ARM::VLD1d32, ARM::VLD1d64 };
2220 unsigned QOpcodes[] = { ARM::VLD1q8, ARM::VLD1q16,
2221 ARM::VLD1q32, ARM::VLD1q64 };
2222 return SelectVLD(N, 1, DOpcodes, QOpcodes, 0);
2225 case Intrinsic::arm_neon_vld2: {
2226 unsigned DOpcodes[] = { ARM::VLD2d8, ARM::VLD2d16,
2227 ARM::VLD2d32, ARM::VLD1q64 };
2228 unsigned QOpcodes[] = { ARM::VLD2q8, ARM::VLD2q16, ARM::VLD2q32 };
2229 return SelectVLD(N, 2, DOpcodes, QOpcodes, 0);
2232 case Intrinsic::arm_neon_vld3: {
2233 unsigned DOpcodes[] = { ARM::VLD3d8, ARM::VLD3d16,
2234 ARM::VLD3d32, ARM::VLD1d64T };
2235 unsigned QOpcodes0[] = { ARM::VLD3q8_UPD,
2238 unsigned QOpcodes1[] = { ARM::VLD3q8odd_UPD,
2239 ARM::VLD3q16odd_UPD,
2240 ARM::VLD3q32odd_UPD };
2241 return SelectVLD(N, 3, DOpcodes, QOpcodes0, QOpcodes1);
2244 case Intrinsic::arm_neon_vld4: {
2245 unsigned DOpcodes[] = { ARM::VLD4d8, ARM::VLD4d16,
2246 ARM::VLD4d32, ARM::VLD1d64Q };
2247 unsigned QOpcodes0[] = { ARM::VLD4q8_UPD,
2250 unsigned QOpcodes1[] = { ARM::VLD4q8odd_UPD,
2251 ARM::VLD4q16odd_UPD,
2252 ARM::VLD4q32odd_UPD };
2253 return SelectVLD(N, 4, DOpcodes, QOpcodes0, QOpcodes1);
2256 case Intrinsic::arm_neon_vld2lane: {
2257 unsigned DOpcodes[] = { ARM::VLD2LNd8, ARM::VLD2LNd16, ARM::VLD2LNd32 };
2258 unsigned QOpcodes0[] = { ARM::VLD2LNq16, ARM::VLD2LNq32 };
2259 unsigned QOpcodes1[] = { ARM::VLD2LNq16odd, ARM::VLD2LNq32odd };
2260 return SelectVLDSTLane(N, true, 2, DOpcodes, QOpcodes0, QOpcodes1);
2263 case Intrinsic::arm_neon_vld3lane: {
2264 unsigned DOpcodes[] = { ARM::VLD3LNd8, ARM::VLD3LNd16, ARM::VLD3LNd32 };
2265 unsigned QOpcodes0[] = { ARM::VLD3LNq16, ARM::VLD3LNq32 };
2266 unsigned QOpcodes1[] = { ARM::VLD3LNq16odd, ARM::VLD3LNq32odd };
2267 return SelectVLDSTLane(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
2270 case Intrinsic::arm_neon_vld4lane: {
2271 unsigned DOpcodes[] = { ARM::VLD4LNd8, ARM::VLD4LNd16, ARM::VLD4LNd32 };
2272 unsigned QOpcodes0[] = { ARM::VLD4LNq16, ARM::VLD4LNq32 };
2273 unsigned QOpcodes1[] = { ARM::VLD4LNq16odd, ARM::VLD4LNq32odd };
2274 return SelectVLDSTLane(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
2277 case Intrinsic::arm_neon_vst1: {
2278 unsigned DOpcodes[] = { ARM::VST1d8, ARM::VST1d16,
2279 ARM::VST1d32, ARM::VST1d64 };
2280 unsigned QOpcodes[] = { ARM::VST1q8, ARM::VST1q16,
2281 ARM::VST1q32, ARM::VST1q64 };
2282 return SelectVST(N, 1, DOpcodes, QOpcodes, 0);
2285 case Intrinsic::arm_neon_vst2: {
2286 unsigned DOpcodes[] = { ARM::VST2d8, ARM::VST2d16,
2287 ARM::VST2d32, ARM::VST1q64 };
2288 unsigned QOpcodes[] = { ARM::VST2q8, ARM::VST2q16, ARM::VST2q32 };
2289 return SelectVST(N, 2, DOpcodes, QOpcodes, 0);
2292 case Intrinsic::arm_neon_vst3: {
2293 unsigned DOpcodes[] = { ARM::VST3d8, ARM::VST3d16,
2294 ARM::VST3d32, ARM::VST1d64T };
2295 unsigned QOpcodes0[] = { ARM::VST3q8_UPD,
2298 unsigned QOpcodes1[] = { ARM::VST3q8odd_UPD,
2299 ARM::VST3q16odd_UPD,
2300 ARM::VST3q32odd_UPD };
2301 return SelectVST(N, 3, DOpcodes, QOpcodes0, QOpcodes1);
2304 case Intrinsic::arm_neon_vst4: {
2305 unsigned DOpcodes[] = { ARM::VST4d8, ARM::VST4d16,
2306 ARM::VST4d32, ARM::VST1d64Q };
2307 unsigned QOpcodes0[] = { ARM::VST4q8_UPD,
2310 unsigned QOpcodes1[] = { ARM::VST4q8odd_UPD,
2311 ARM::VST4q16odd_UPD,
2312 ARM::VST4q32odd_UPD };
2313 return SelectVST(N, 4, DOpcodes, QOpcodes0, QOpcodes1);
2316 case Intrinsic::arm_neon_vst2lane: {
2317 unsigned DOpcodes[] = { ARM::VST2LNd8, ARM::VST2LNd16, ARM::VST2LNd32 };
2318 unsigned QOpcodes0[] = { ARM::VST2LNq16, ARM::VST2LNq32 };
2319 unsigned QOpcodes1[] = { ARM::VST2LNq16odd, ARM::VST2LNq32odd };
2320 return SelectVLDSTLane(N, false, 2, DOpcodes, QOpcodes0, QOpcodes1);
2323 case Intrinsic::arm_neon_vst3lane: {
2324 unsigned DOpcodes[] = { ARM::VST3LNd8, ARM::VST3LNd16, ARM::VST3LNd32 };
2325 unsigned QOpcodes0[] = { ARM::VST3LNq16, ARM::VST3LNq32 };
2326 unsigned QOpcodes1[] = { ARM::VST3LNq16odd, ARM::VST3LNq32odd };
2327 return SelectVLDSTLane(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
2330 case Intrinsic::arm_neon_vst4lane: {
2331 unsigned DOpcodes[] = { ARM::VST4LNd8, ARM::VST4LNd16, ARM::VST4LNd32 };
2332 unsigned QOpcodes0[] = { ARM::VST4LNq16, ARM::VST4LNq32 };
2333 unsigned QOpcodes1[] = { ARM::VST4LNq16odd, ARM::VST4LNq32odd };
2334 return SelectVLDSTLane(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
2340 case ISD::INTRINSIC_WO_CHAIN: {
2341 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
2346 case Intrinsic::arm_neon_vtbl2:
2347 return SelectVTBL(N, false, 2, ARM::VTBL2);
2348 case Intrinsic::arm_neon_vtbl3:
2349 return SelectVTBL(N, false, 3, ARM::VTBL3);
2350 case Intrinsic::arm_neon_vtbl4:
2351 return SelectVTBL(N, false, 4, ARM::VTBL4);
2353 case Intrinsic::arm_neon_vtbx2:
2354 return SelectVTBL(N, true, 2, ARM::VTBX2);
2355 case Intrinsic::arm_neon_vtbx3:
2356 return SelectVTBL(N, true, 3, ARM::VTBX3);
2357 case Intrinsic::arm_neon_vtbx4:
2358 return SelectVTBL(N, true, 4, ARM::VTBX4);
2363 case ISD::CONCAT_VECTORS:
2364 return SelectConcatVector(N);
2367 return SelectCode(N);
2370 bool ARMDAGToDAGISel::
2371 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
2372 std::vector<SDValue> &OutOps) {
2373 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
2374 // Require the address to be in a register. That is safe for all ARM
2375 // variants and it is hard to do anything much smarter without knowing
2376 // how the operand is used.
2377 OutOps.push_back(Op);
2381 /// createARMISelDag - This pass converts a legalized DAG into a
2382 /// ARM-specific DAG, ready for instruction scheduling.
2384 FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
2385 CodeGenOpt::Level OptLevel) {
2386 return new ARMDAGToDAGISel(TM, OptLevel);