1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "arm-isel"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMAddressingModes.h"
18 #include "ARMTargetMachine.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/Constants.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/Intrinsics.h"
24 #include "llvm/LLVMContext.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/SelectionDAGISel.h"
30 #include "llvm/Target/TargetLowering.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Compiler.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/raw_ostream.h"
41 DisableShifterOp("disable-shifter-op", cl::Hidden,
42 cl::desc("Disable isel of shifter-op"),
46 CheckVMLxHazard("check-vmlx-hazard", cl::Hidden,
47 cl::desc("Check fp vmla / vmls hazard at isel time"),
50 //===--------------------------------------------------------------------===//
51 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
52 /// instructions for SelectionDAG operations.
57 AM2_BASE, // Simple AM2 (+-imm12)
58 AM2_SHOP // Shifter-op AM2
61 class ARMDAGToDAGISel : public SelectionDAGISel {
62 ARMBaseTargetMachine &TM;
63 const ARMBaseInstrInfo *TII;
65 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
66 /// make the right decision when generating code for different targets.
67 const ARMSubtarget *Subtarget;
70 explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm,
71 CodeGenOpt::Level OptLevel)
72 : SelectionDAGISel(tm, OptLevel), TM(tm),
73 TII(static_cast<const ARMBaseInstrInfo*>(TM.getInstrInfo())),
74 Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
77 virtual const char *getPassName() const {
78 return "ARM Instruction Selection";
81 /// getI32Imm - Return a target constant of type i32 with the specified
83 inline SDValue getI32Imm(unsigned Imm) {
84 return CurDAG->getTargetConstant(Imm, MVT::i32);
87 SDNode *Select(SDNode *N);
90 bool hasNoVMLxHazardUse(SDNode *N) const;
91 bool isShifterOpProfitable(const SDValue &Shift,
92 ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
93 bool SelectShifterOperandReg(SDValue N, SDValue &A,
94 SDValue &B, SDValue &C);
95 bool SelectShiftShifterOperandReg(SDValue N, SDValue &A,
96 SDValue &B, SDValue &C);
97 bool SelectAddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
98 bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc);
100 AddrMode2Type SelectAddrMode2Worker(SDValue N, SDValue &Base,
101 SDValue &Offset, SDValue &Opc);
102 bool SelectAddrMode2Base(SDValue N, SDValue &Base, SDValue &Offset,
104 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_BASE;
107 bool SelectAddrMode2ShOp(SDValue N, SDValue &Base, SDValue &Offset,
109 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_SHOP;
112 bool SelectAddrMode2(SDValue N, SDValue &Base, SDValue &Offset,
114 SelectAddrMode2Worker(N, Base, Offset, Opc);
115 // return SelectAddrMode2ShOp(N, Base, Offset, Opc);
116 // This always matches one way or another.
120 bool SelectAddrMode2Offset(SDNode *Op, SDValue N,
121 SDValue &Offset, SDValue &Opc);
122 bool SelectAddrMode3(SDValue N, SDValue &Base,
123 SDValue &Offset, SDValue &Opc);
124 bool SelectAddrMode3Offset(SDNode *Op, SDValue N,
125 SDValue &Offset, SDValue &Opc);
126 bool SelectAddrMode5(SDValue N, SDValue &Base,
128 bool SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,SDValue &Align);
130 bool SelectAddrModePC(SDValue N, SDValue &Offset,
133 bool SelectThumbAddrModeRR(SDValue N, SDValue &Base, SDValue &Offset);
134 bool SelectThumbAddrModeRI5(SDValue N, unsigned Scale,
135 SDValue &Base, SDValue &OffImm,
137 bool SelectThumbAddrModeS1(SDValue N, SDValue &Base,
138 SDValue &OffImm, SDValue &Offset);
139 bool SelectThumbAddrModeS2(SDValue N, SDValue &Base,
140 SDValue &OffImm, SDValue &Offset);
141 bool SelectThumbAddrModeS4(SDValue N, SDValue &Base,
142 SDValue &OffImm, SDValue &Offset);
143 bool SelectThumbAddrModeSP(SDValue N, SDValue &Base, SDValue &OffImm);
145 bool SelectT2ShifterOperandReg(SDValue N,
146 SDValue &BaseReg, SDValue &Opc);
147 bool SelectT2AddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
148 bool SelectT2AddrModeImm8(SDValue N, SDValue &Base,
150 bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
152 bool SelectT2AddrModeSoReg(SDValue N, SDValue &Base,
153 SDValue &OffReg, SDValue &ShImm);
155 inline bool is_so_imm(unsigned Imm) const {
156 return ARM_AM::getSOImmVal(Imm) != -1;
159 inline bool is_so_imm_not(unsigned Imm) const {
160 return ARM_AM::getSOImmVal(~Imm) != -1;
163 inline bool is_t2_so_imm(unsigned Imm) const {
164 return ARM_AM::getT2SOImmVal(Imm) != -1;
167 inline bool is_t2_so_imm_not(unsigned Imm) const {
168 return ARM_AM::getT2SOImmVal(~Imm) != -1;
171 inline bool Pred_so_imm(SDNode *inN) const {
172 ConstantSDNode *N = cast<ConstantSDNode>(inN);
173 return is_so_imm(N->getZExtValue());
176 inline bool Pred_t2_so_imm(SDNode *inN) const {
177 ConstantSDNode *N = cast<ConstantSDNode>(inN);
178 return is_t2_so_imm(N->getZExtValue());
181 // Include the pieces autogenerated from the target description.
182 #include "ARMGenDAGISel.inc"
185 /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
187 SDNode *SelectARMIndexedLoad(SDNode *N);
188 SDNode *SelectT2IndexedLoad(SDNode *N);
190 /// SelectVLD - Select NEON load intrinsics. NumVecs should be
191 /// 1, 2, 3 or 4. The opcode arrays specify the instructions used for
192 /// loads of D registers and even subregs and odd subregs of Q registers.
193 /// For NumVecs <= 2, QOpcodes1 is not used.
194 SDNode *SelectVLD(SDNode *N, unsigned NumVecs, unsigned *DOpcodes,
195 unsigned *QOpcodes0, unsigned *QOpcodes1);
197 /// SelectVST - Select NEON store intrinsics. NumVecs should
198 /// be 1, 2, 3 or 4. The opcode arrays specify the instructions used for
199 /// stores of D registers and even subregs and odd subregs of Q registers.
200 /// For NumVecs <= 2, QOpcodes1 is not used.
201 SDNode *SelectVST(SDNode *N, unsigned NumVecs, unsigned *DOpcodes,
202 unsigned *QOpcodes0, unsigned *QOpcodes1);
204 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should
205 /// be 2, 3 or 4. The opcode arrays specify the instructions used for
206 /// load/store of D registers and Q registers.
207 SDNode *SelectVLDSTLane(SDNode *N, bool IsLoad, unsigned NumVecs,
208 unsigned *DOpcodes, unsigned *QOpcodes);
210 /// SelectVLDDup - Select NEON load-duplicate intrinsics. NumVecs
211 /// should be 2, 3 or 4. The opcode array specifies the instructions used
212 /// for loading D registers. (Q registers are not supported.)
213 SDNode *SelectVLDDup(SDNode *N, unsigned NumVecs, unsigned *Opcodes);
215 /// SelectVTBL - Select NEON VTBL and VTBX intrinsics. NumVecs should be 2,
216 /// 3 or 4. These are custom-selected so that a REG_SEQUENCE can be
217 /// generated to force the table registers to be consecutive.
218 SDNode *SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc);
220 /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM.
221 SDNode *SelectV6T2BitfieldExtractOp(SDNode *N, bool isSigned);
223 /// SelectCMOVOp - Select CMOV instructions for ARM.
224 SDNode *SelectCMOVOp(SDNode *N);
225 SDNode *SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
226 ARMCC::CondCodes CCVal, SDValue CCR,
228 SDNode *SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
229 ARMCC::CondCodes CCVal, SDValue CCR,
231 SDNode *SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
232 ARMCC::CondCodes CCVal, SDValue CCR,
234 SDNode *SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
235 ARMCC::CondCodes CCVal, SDValue CCR,
238 SDNode *SelectConcatVector(SDNode *N);
240 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
241 /// inline asm expressions.
242 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
244 std::vector<SDValue> &OutOps);
246 // Form pairs of consecutive S, D, or Q registers.
247 SDNode *PairSRegs(EVT VT, SDValue V0, SDValue V1);
248 SDNode *PairDRegs(EVT VT, SDValue V0, SDValue V1);
249 SDNode *PairQRegs(EVT VT, SDValue V0, SDValue V1);
251 // Form sequences of 4 consecutive S, D, or Q registers.
252 SDNode *QuadSRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
253 SDNode *QuadDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
254 SDNode *QuadQRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
256 // Get the alignment operand for a NEON VLD or VST instruction.
257 SDValue GetVLDSTAlign(SDValue Align, unsigned NumVecs, bool is64BitVector);
261 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
262 /// operand. If so Imm will receive the 32-bit value.
263 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
264 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
265 Imm = cast<ConstantSDNode>(N)->getZExtValue();
271 // isInt32Immediate - This method tests to see if a constant operand.
272 // If so Imm will receive the 32 bit value.
273 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
274 return isInt32Immediate(N.getNode(), Imm);
277 // isOpcWithIntImmediate - This method tests to see if the node is a specific
278 // opcode and that it has a immediate integer right operand.
279 // If so Imm will receive the 32 bit value.
280 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
281 return N->getOpcode() == Opc &&
282 isInt32Immediate(N->getOperand(1).getNode(), Imm);
285 /// hasNoVMLxHazardUse - Return true if it's desirable to select a FP MLA / MLS
286 /// node. VFP / NEON fp VMLA / VMLS instructions have special RAW hazards (at
287 /// least on current ARM implementations) which should be avoidded.
288 bool ARMDAGToDAGISel::hasNoVMLxHazardUse(SDNode *N) const {
289 if (OptLevel == CodeGenOpt::None)
292 if (!CheckVMLxHazard)
295 if (!Subtarget->isCortexA8() && !Subtarget->isCortexA9())
301 SDNode *Use = *N->use_begin();
302 if (Use->getOpcode() == ISD::CopyToReg)
304 if (Use->isMachineOpcode()) {
305 const TargetInstrDesc &TID = TII->get(Use->getMachineOpcode());
308 unsigned Opcode = TID.getOpcode();
309 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
311 // vmlx feeding into another vmlx. We actually want to unfold
312 // the use later in the MLxExpansion pass. e.g.
314 // vmla (stall 8 cycles)
319 // This adds up to about 18 - 19 cycles.
322 // vmul (stall 4 cycles)
323 // vadd adds up to about 14 cycles.
324 return TII->isFpMLxInstruction(Opcode);
330 bool ARMDAGToDAGISel::isShifterOpProfitable(const SDValue &Shift,
331 ARM_AM::ShiftOpc ShOpcVal,
333 if (!Subtarget->isCortexA9())
335 if (Shift.hasOneUse())
338 return ShOpcVal == ARM_AM::lsl && ShAmt == 2;
341 bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue N,
345 if (DisableShifterOp)
348 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
350 // Don't match base register only case. That is matched to a separate
351 // lower complexity pattern with explicit register operand.
352 if (ShOpcVal == ARM_AM::no_shift) return false;
354 BaseReg = N.getOperand(0);
355 unsigned ShImmVal = 0;
356 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
357 ShReg = CurDAG->getRegister(0, MVT::i32);
358 ShImmVal = RHS->getZExtValue() & 31;
360 ShReg = N.getOperand(1);
361 if (!isShifterOpProfitable(N, ShOpcVal, ShImmVal))
364 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
369 bool ARMDAGToDAGISel::SelectShiftShifterOperandReg(SDValue N,
373 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
375 // Don't match base register only case. That is matched to a separate
376 // lower complexity pattern with explicit register operand.
377 if (ShOpcVal == ARM_AM::no_shift) return false;
379 BaseReg = N.getOperand(0);
380 unsigned ShImmVal = 0;
381 // Do not check isShifterOpProfitable. This must return true.
382 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
383 ShReg = CurDAG->getRegister(0, MVT::i32);
384 ShImmVal = RHS->getZExtValue() & 31;
386 ShReg = N.getOperand(1);
388 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
393 bool ARMDAGToDAGISel::SelectAddrModeImm12(SDValue N,
396 // Match simple R + imm12 operands.
399 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
400 if (N.getOpcode() == ISD::FrameIndex) {
401 // Match frame index...
402 int FI = cast<FrameIndexSDNode>(N)->getIndex();
403 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
404 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
406 } else if (N.getOpcode() == ARMISD::Wrapper &&
407 !(Subtarget->useMovt() &&
408 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
409 Base = N.getOperand(0);
412 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
416 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
417 int RHSC = (int)RHS->getZExtValue();
418 if (N.getOpcode() == ISD::SUB)
421 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
422 Base = N.getOperand(0);
423 if (Base.getOpcode() == ISD::FrameIndex) {
424 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
425 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
427 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
434 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
440 bool ARMDAGToDAGISel::SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset,
442 if (N.getOpcode() == ISD::MUL &&
443 (!Subtarget->isCortexA9() || N.hasOneUse())) {
444 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
445 // X * [3,5,9] -> X + X * [2,4,8] etc.
446 int RHSC = (int)RHS->getZExtValue();
449 ARM_AM::AddrOpc AddSub = ARM_AM::add;
451 AddSub = ARM_AM::sub;
454 if (isPowerOf2_32(RHSC)) {
455 unsigned ShAmt = Log2_32(RHSC);
456 Base = Offset = N.getOperand(0);
457 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
466 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB)
469 // Leave simple R +/- imm12 operands for LDRi12
470 if (N.getOpcode() == ISD::ADD) {
471 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
472 int RHSC = (int)RHS->getZExtValue();
473 if ((RHSC >= 0 && RHSC < 0x1000) ||
474 (RHSC < 0 && RHSC > -0x1000)) // 12 bits.
479 if (Subtarget->isCortexA9() && !N.hasOneUse())
480 // Compute R +/- (R << N) and reuse it.
483 // Otherwise this is R +/- [possibly shifted] R.
484 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
485 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
488 Base = N.getOperand(0);
489 Offset = N.getOperand(1);
491 if (ShOpcVal != ARM_AM::no_shift) {
492 // Check to see if the RHS of the shift is a constant, if not, we can't fold
494 if (ConstantSDNode *Sh =
495 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
496 ShAmt = Sh->getZExtValue();
497 if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
498 Offset = N.getOperand(1).getOperand(0);
501 ShOpcVal = ARM_AM::no_shift;
504 ShOpcVal = ARM_AM::no_shift;
508 // Try matching (R shl C) + (R).
509 if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift &&
510 !(Subtarget->isCortexA9() || N.getOperand(0).hasOneUse())) {
511 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
512 if (ShOpcVal != ARM_AM::no_shift) {
513 // Check to see if the RHS of the shift is a constant, if not, we can't
515 if (ConstantSDNode *Sh =
516 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
517 ShAmt = Sh->getZExtValue();
518 if (!Subtarget->isCortexA9() ||
520 isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt))) {
521 Offset = N.getOperand(0).getOperand(0);
522 Base = N.getOperand(1);
525 ShOpcVal = ARM_AM::no_shift;
528 ShOpcVal = ARM_AM::no_shift;
533 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
543 AddrMode2Type ARMDAGToDAGISel::SelectAddrMode2Worker(SDValue N,
547 if (N.getOpcode() == ISD::MUL &&
548 (!Subtarget->isCortexA9() || N.hasOneUse())) {
549 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
550 // X * [3,5,9] -> X + X * [2,4,8] etc.
551 int RHSC = (int)RHS->getZExtValue();
554 ARM_AM::AddrOpc AddSub = ARM_AM::add;
556 AddSub = ARM_AM::sub;
559 if (isPowerOf2_32(RHSC)) {
560 unsigned ShAmt = Log2_32(RHSC);
561 Base = Offset = N.getOperand(0);
562 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
571 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
573 if (N.getOpcode() == ISD::FrameIndex) {
574 int FI = cast<FrameIndexSDNode>(N)->getIndex();
575 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
576 } else if (N.getOpcode() == ARMISD::Wrapper &&
577 !(Subtarget->useMovt() &&
578 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
579 Base = N.getOperand(0);
581 Offset = CurDAG->getRegister(0, MVT::i32);
582 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
588 // Match simple R +/- imm12 operands.
589 if (N.getOpcode() == ISD::ADD) {
590 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
591 int RHSC = (int)RHS->getZExtValue();
592 if ((RHSC >= 0 && RHSC < 0x1000) ||
593 (RHSC < 0 && RHSC > -0x1000)) { // 12 bits.
594 Base = N.getOperand(0);
595 if (Base.getOpcode() == ISD::FrameIndex) {
596 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
597 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
599 Offset = CurDAG->getRegister(0, MVT::i32);
601 ARM_AM::AddrOpc AddSub = ARM_AM::add;
603 AddSub = ARM_AM::sub;
606 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
614 if (Subtarget->isCortexA9() && !N.hasOneUse()) {
615 // Compute R +/- (R << N) and reuse it.
617 Offset = CurDAG->getRegister(0, MVT::i32);
618 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
624 // Otherwise this is R +/- [possibly shifted] R.
625 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
626 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
629 Base = N.getOperand(0);
630 Offset = N.getOperand(1);
632 if (ShOpcVal != ARM_AM::no_shift) {
633 // Check to see if the RHS of the shift is a constant, if not, we can't fold
635 if (ConstantSDNode *Sh =
636 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
637 ShAmt = Sh->getZExtValue();
638 if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
639 Offset = N.getOperand(1).getOperand(0);
642 ShOpcVal = ARM_AM::no_shift;
645 ShOpcVal = ARM_AM::no_shift;
649 // Try matching (R shl C) + (R).
650 if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift &&
651 !(Subtarget->isCortexA9() || N.getOperand(0).hasOneUse())) {
652 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
653 if (ShOpcVal != ARM_AM::no_shift) {
654 // Check to see if the RHS of the shift is a constant, if not, we can't
656 if (ConstantSDNode *Sh =
657 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
658 ShAmt = Sh->getZExtValue();
659 if (!Subtarget->isCortexA9() ||
661 isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt))) {
662 Offset = N.getOperand(0).getOperand(0);
663 Base = N.getOperand(1);
666 ShOpcVal = ARM_AM::no_shift;
669 ShOpcVal = ARM_AM::no_shift;
674 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
679 bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDNode *Op, SDValue N,
680 SDValue &Offset, SDValue &Opc) {
681 unsigned Opcode = Op->getOpcode();
682 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
683 ? cast<LoadSDNode>(Op)->getAddressingMode()
684 : cast<StoreSDNode>(Op)->getAddressingMode();
685 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
686 ? ARM_AM::add : ARM_AM::sub;
687 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
688 int Val = (int)C->getZExtValue();
689 if (Val >= 0 && Val < 0x1000) { // 12 bits.
690 Offset = CurDAG->getRegister(0, MVT::i32);
691 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
699 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
701 if (ShOpcVal != ARM_AM::no_shift) {
702 // Check to see if the RHS of the shift is a constant, if not, we can't fold
704 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
705 ShAmt = Sh->getZExtValue();
706 if (isShifterOpProfitable(N, ShOpcVal, ShAmt))
707 Offset = N.getOperand(0);
710 ShOpcVal = ARM_AM::no_shift;
713 ShOpcVal = ARM_AM::no_shift;
717 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
723 bool ARMDAGToDAGISel::SelectAddrMode3(SDValue N,
724 SDValue &Base, SDValue &Offset,
726 if (N.getOpcode() == ISD::SUB) {
727 // X - C is canonicalize to X + -C, no need to handle it here.
728 Base = N.getOperand(0);
729 Offset = N.getOperand(1);
730 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
734 if (N.getOpcode() != ISD::ADD) {
736 if (N.getOpcode() == ISD::FrameIndex) {
737 int FI = cast<FrameIndexSDNode>(N)->getIndex();
738 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
740 Offset = CurDAG->getRegister(0, MVT::i32);
741 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
745 // If the RHS is +/- imm8, fold into addr mode.
746 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
747 int RHSC = (int)RHS->getZExtValue();
748 if ((RHSC >= 0 && RHSC < 256) ||
749 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
750 Base = N.getOperand(0);
751 if (Base.getOpcode() == ISD::FrameIndex) {
752 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
753 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
755 Offset = CurDAG->getRegister(0, MVT::i32);
757 ARM_AM::AddrOpc AddSub = ARM_AM::add;
759 AddSub = ARM_AM::sub;
762 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
767 Base = N.getOperand(0);
768 Offset = N.getOperand(1);
769 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
773 bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N,
774 SDValue &Offset, SDValue &Opc) {
775 unsigned Opcode = Op->getOpcode();
776 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
777 ? cast<LoadSDNode>(Op)->getAddressingMode()
778 : cast<StoreSDNode>(Op)->getAddressingMode();
779 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
780 ? ARM_AM::add : ARM_AM::sub;
781 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
782 int Val = (int)C->getZExtValue();
783 if (Val >= 0 && Val < 256) {
784 Offset = CurDAG->getRegister(0, MVT::i32);
785 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
791 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
795 bool ARMDAGToDAGISel::SelectAddrMode5(SDValue N,
796 SDValue &Base, SDValue &Offset) {
797 if (N.getOpcode() != ISD::ADD) {
799 if (N.getOpcode() == ISD::FrameIndex) {
800 int FI = cast<FrameIndexSDNode>(N)->getIndex();
801 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
802 } else if (N.getOpcode() == ARMISD::Wrapper &&
803 !(Subtarget->useMovt() &&
804 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
805 Base = N.getOperand(0);
807 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
812 // If the RHS is +/- imm8, fold into addr mode.
813 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
814 int RHSC = (int)RHS->getZExtValue();
815 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied by 4.
817 if ((RHSC >= 0 && RHSC < 256) ||
818 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
819 Base = N.getOperand(0);
820 if (Base.getOpcode() == ISD::FrameIndex) {
821 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
822 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
825 ARM_AM::AddrOpc AddSub = ARM_AM::add;
827 AddSub = ARM_AM::sub;
830 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
838 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
843 bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,
847 unsigned Alignment = 0;
848 if (LSBaseSDNode *LSN = dyn_cast<LSBaseSDNode>(Parent)) {
849 // This case occurs only for VLD1-lane/dup and VST1-lane instructions.
850 // The maximum alignment is equal to the memory size being referenced.
851 unsigned LSNAlign = LSN->getAlignment();
852 unsigned MemSize = LSN->getMemoryVT().getSizeInBits() / 8;
853 if (LSNAlign > MemSize && MemSize > 1)
856 // All other uses of addrmode6 are for intrinsics. For now just record
857 // the raw alignment value; it will be refined later based on the legal
858 // alignment operands for the intrinsic.
859 Alignment = cast<MemIntrinsicSDNode>(Parent)->getAlignment();
862 Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
866 bool ARMDAGToDAGISel::SelectAddrModePC(SDValue N,
867 SDValue &Offset, SDValue &Label) {
868 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
869 Offset = N.getOperand(0);
870 SDValue N1 = N.getOperand(1);
871 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
878 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue N,
879 SDValue &Base, SDValue &Offset){
880 // FIXME dl should come from the parent load or store, not the address
881 if (N.getOpcode() != ISD::ADD) {
882 ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
883 if (!NC || !NC->isNullValue())
890 Base = N.getOperand(0);
891 Offset = N.getOperand(1);
896 ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDValue N,
897 unsigned Scale, SDValue &Base,
898 SDValue &OffImm, SDValue &Offset) {
900 SDValue TmpBase, TmpOffImm;
901 if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
902 return false; // We want to select tLDRspi / tSTRspi instead.
903 if (N.getOpcode() == ARMISD::Wrapper &&
904 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
905 return false; // We want to select tLDRpci instead.
908 if (N.getOpcode() != ISD::ADD) {
909 if (N.getOpcode() == ARMISD::Wrapper &&
910 !(Subtarget->useMovt() &&
911 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
912 Base = N.getOperand(0);
916 Offset = CurDAG->getRegister(0, MVT::i32);
917 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
921 // Thumb does not have [sp, r] address mode.
922 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
923 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
924 if ((LHSR && LHSR->getReg() == ARM::SP) ||
925 (RHSR && RHSR->getReg() == ARM::SP)) {
927 Offset = CurDAG->getRegister(0, MVT::i32);
928 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
932 // If the RHS is + imm5 * scale, fold into addr mode.
933 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
934 int RHSC = (int)RHS->getZExtValue();
935 if ((RHSC & (Scale-1)) == 0) { // The constant is implicitly multiplied.
937 if (RHSC >= 0 && RHSC < 32) {
938 Base = N.getOperand(0);
939 Offset = CurDAG->getRegister(0, MVT::i32);
940 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
946 Base = N.getOperand(0);
947 Offset = N.getOperand(1);
948 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
952 bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDValue N,
953 SDValue &Base, SDValue &OffImm,
955 return SelectThumbAddrModeRI5(N, 1, Base, OffImm, Offset);
958 bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDValue N,
959 SDValue &Base, SDValue &OffImm,
961 return SelectThumbAddrModeRI5(N, 2, Base, OffImm, Offset);
964 bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDValue N,
965 SDValue &Base, SDValue &OffImm,
967 return SelectThumbAddrModeRI5(N, 4, Base, OffImm, Offset);
970 bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue N,
971 SDValue &Base, SDValue &OffImm) {
972 if (N.getOpcode() == ISD::FrameIndex) {
973 int FI = cast<FrameIndexSDNode>(N)->getIndex();
974 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
975 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
979 if (N.getOpcode() != ISD::ADD)
982 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
983 if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
984 (LHSR && LHSR->getReg() == ARM::SP)) {
985 // If the RHS is + imm8 * scale, fold into addr mode.
986 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
987 int RHSC = (int)RHS->getZExtValue();
988 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied.
990 if (RHSC >= 0 && RHSC < 256) {
991 Base = N.getOperand(0);
992 if (Base.getOpcode() == ISD::FrameIndex) {
993 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
994 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
996 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1006 bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue N, SDValue &BaseReg,
1008 if (DisableShifterOp)
1011 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
1013 // Don't match base register only case. That is matched to a separate
1014 // lower complexity pattern with explicit register operand.
1015 if (ShOpcVal == ARM_AM::no_shift) return false;
1017 BaseReg = N.getOperand(0);
1018 unsigned ShImmVal = 0;
1019 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1020 ShImmVal = RHS->getZExtValue() & 31;
1021 Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
1028 bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue N,
1029 SDValue &Base, SDValue &OffImm) {
1030 // Match simple R + imm12 operands.
1033 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
1034 if (N.getOpcode() == ISD::FrameIndex) {
1035 // Match frame index...
1036 int FI = cast<FrameIndexSDNode>(N)->getIndex();
1037 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1038 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1040 } else if (N.getOpcode() == ARMISD::Wrapper &&
1041 !(Subtarget->useMovt() &&
1042 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
1043 Base = N.getOperand(0);
1044 if (Base.getOpcode() == ISD::TargetConstantPool)
1045 return false; // We want to select t2LDRpci instead.
1048 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1052 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1053 if (SelectT2AddrModeImm8(N, Base, OffImm))
1054 // Let t2LDRi8 handle (R - imm8).
1057 int RHSC = (int)RHS->getZExtValue();
1058 if (N.getOpcode() == ISD::SUB)
1061 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
1062 Base = N.getOperand(0);
1063 if (Base.getOpcode() == ISD::FrameIndex) {
1064 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1065 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1067 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1074 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1078 bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue N,
1079 SDValue &Base, SDValue &OffImm) {
1080 // Match simple R - imm8 operands.
1081 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::SUB) {
1082 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1083 int RHSC = (int)RHS->getSExtValue();
1084 if (N.getOpcode() == ISD::SUB)
1087 if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative)
1088 Base = N.getOperand(0);
1089 if (Base.getOpcode() == ISD::FrameIndex) {
1090 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1091 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1093 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1102 bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
1104 unsigned Opcode = Op->getOpcode();
1105 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
1106 ? cast<LoadSDNode>(Op)->getAddressingMode()
1107 : cast<StoreSDNode>(Op)->getAddressingMode();
1108 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N)) {
1109 int RHSC = (int)RHS->getZExtValue();
1110 if (RHSC >= 0 && RHSC < 0x100) { // 8 bits.
1111 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
1112 ? CurDAG->getTargetConstant(RHSC, MVT::i32)
1113 : CurDAG->getTargetConstant(-RHSC, MVT::i32);
1121 bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue N,
1123 SDValue &OffReg, SDValue &ShImm) {
1124 // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.
1125 if (N.getOpcode() != ISD::ADD)
1128 // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8.
1129 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1130 int RHSC = (int)RHS->getZExtValue();
1131 if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned)
1133 else if (RHSC < 0 && RHSC >= -255) // 8 bits
1137 if (Subtarget->isCortexA9() && !N.hasOneUse()) {
1138 // Compute R + (R << [1,2,3]) and reuse it.
1143 // Look for (R + R) or (R + (R << [1,2,3])).
1145 Base = N.getOperand(0);
1146 OffReg = N.getOperand(1);
1148 // Swap if it is ((R << c) + R).
1149 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg);
1150 if (ShOpcVal != ARM_AM::lsl) {
1151 ShOpcVal = ARM_AM::getShiftOpcForNode(Base);
1152 if (ShOpcVal == ARM_AM::lsl)
1153 std::swap(Base, OffReg);
1156 if (ShOpcVal == ARM_AM::lsl) {
1157 // Check to see if the RHS of the shift is a constant, if not, we can't fold
1159 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
1160 ShAmt = Sh->getZExtValue();
1161 if (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt))
1162 OffReg = OffReg.getOperand(0);
1165 ShOpcVal = ARM_AM::no_shift;
1168 ShOpcVal = ARM_AM::no_shift;
1172 ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
1177 //===--------------------------------------------------------------------===//
1179 /// getAL - Returns a ARMCC::AL immediate node.
1180 static inline SDValue getAL(SelectionDAG *CurDAG) {
1181 return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
1184 SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDNode *N) {
1185 LoadSDNode *LD = cast<LoadSDNode>(N);
1186 ISD::MemIndexedMode AM = LD->getAddressingMode();
1187 if (AM == ISD::UNINDEXED)
1190 EVT LoadedVT = LD->getMemoryVT();
1191 SDValue Offset, AMOpc;
1192 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1193 unsigned Opcode = 0;
1195 if (LoadedVT == MVT::i32 &&
1196 SelectAddrMode2Offset(N, LD->getOffset(), Offset, AMOpc)) {
1197 Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST;
1199 } else if (LoadedVT == MVT::i16 &&
1200 SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1202 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
1203 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
1204 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
1205 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
1206 if (LD->getExtensionType() == ISD::SEXTLOAD) {
1207 if (SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1209 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
1212 if (SelectAddrMode2Offset(N, LD->getOffset(), Offset, AMOpc)) {
1214 Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST;
1220 SDValue Chain = LD->getChain();
1221 SDValue Base = LD->getBasePtr();
1222 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
1223 CurDAG->getRegister(0, MVT::i32), Chain };
1224 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32,
1225 MVT::Other, Ops, 6);
1231 SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDNode *N) {
1232 LoadSDNode *LD = cast<LoadSDNode>(N);
1233 ISD::MemIndexedMode AM = LD->getAddressingMode();
1234 if (AM == ISD::UNINDEXED)
1237 EVT LoadedVT = LD->getMemoryVT();
1238 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
1240 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1241 unsigned Opcode = 0;
1243 if (SelectT2AddrModeImm8Offset(N, LD->getOffset(), Offset)) {
1244 switch (LoadedVT.getSimpleVT().SimpleTy) {
1246 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
1250 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
1252 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
1257 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
1259 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
1268 SDValue Chain = LD->getChain();
1269 SDValue Base = LD->getBasePtr();
1270 SDValue Ops[]= { Base, Offset, getAL(CurDAG),
1271 CurDAG->getRegister(0, MVT::i32), Chain };
1272 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32,
1273 MVT::Other, Ops, 5);
1279 /// PairSRegs - Form a D register from a pair of S registers.
1281 SDNode *ARMDAGToDAGISel::PairSRegs(EVT VT, SDValue V0, SDValue V1) {
1282 DebugLoc dl = V0.getNode()->getDebugLoc();
1283 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1284 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1285 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
1286 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
1289 /// PairDRegs - Form a quad register from a pair of D registers.
1291 SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) {
1292 DebugLoc dl = V0.getNode()->getDebugLoc();
1293 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1294 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1295 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
1296 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
1299 /// PairQRegs - Form 4 consecutive D registers from a pair of Q registers.
1301 SDNode *ARMDAGToDAGISel::PairQRegs(EVT VT, SDValue V0, SDValue V1) {
1302 DebugLoc dl = V0.getNode()->getDebugLoc();
1303 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1304 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1305 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
1306 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
1309 /// QuadSRegs - Form 4 consecutive S registers.
1311 SDNode *ARMDAGToDAGISel::QuadSRegs(EVT VT, SDValue V0, SDValue V1,
1312 SDValue V2, SDValue V3) {
1313 DebugLoc dl = V0.getNode()->getDebugLoc();
1314 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1315 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1316 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, MVT::i32);
1317 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::ssub_3, MVT::i32);
1318 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 };
1319 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
1322 /// QuadDRegs - Form 4 consecutive D registers.
1324 SDNode *ARMDAGToDAGISel::QuadDRegs(EVT VT, SDValue V0, SDValue V1,
1325 SDValue V2, SDValue V3) {
1326 DebugLoc dl = V0.getNode()->getDebugLoc();
1327 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1328 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1329 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, MVT::i32);
1330 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, MVT::i32);
1331 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 };
1332 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
1335 /// QuadQRegs - Form 4 consecutive Q registers.
1337 SDNode *ARMDAGToDAGISel::QuadQRegs(EVT VT, SDValue V0, SDValue V1,
1338 SDValue V2, SDValue V3) {
1339 DebugLoc dl = V0.getNode()->getDebugLoc();
1340 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1341 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1342 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, MVT::i32);
1343 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, MVT::i32);
1344 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 };
1345 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
1348 /// GetVLDSTAlign - Get the alignment (in bytes) for the alignment operand
1349 /// of a NEON VLD or VST instruction. The supported values depend on the
1350 /// number of registers being loaded.
1351 SDValue ARMDAGToDAGISel::GetVLDSTAlign(SDValue Align, unsigned NumVecs,
1352 bool is64BitVector) {
1353 unsigned NumRegs = NumVecs;
1354 if (!is64BitVector && NumVecs < 3)
1357 unsigned Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1358 if (Alignment >= 32 && NumRegs == 4)
1360 else if (Alignment >= 16 && (NumRegs == 2 || NumRegs == 4))
1362 else if (Alignment >= 8)
1367 return CurDAG->getTargetConstant(Alignment, MVT::i32);
1370 SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, unsigned NumVecs,
1371 unsigned *DOpcodes, unsigned *QOpcodes0,
1372 unsigned *QOpcodes1) {
1373 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range");
1374 DebugLoc dl = N->getDebugLoc();
1376 SDValue MemAddr, Align;
1377 if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, Align))
1380 SDValue Chain = N->getOperand(0);
1381 EVT VT = N->getValueType(0);
1382 bool is64BitVector = VT.is64BitVector();
1383 Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1385 unsigned OpcodeIndex;
1386 switch (VT.getSimpleVT().SimpleTy) {
1387 default: llvm_unreachable("unhandled vld type");
1388 // Double-register operations:
1389 case MVT::v8i8: OpcodeIndex = 0; break;
1390 case MVT::v4i16: OpcodeIndex = 1; break;
1392 case MVT::v2i32: OpcodeIndex = 2; break;
1393 case MVT::v1i64: OpcodeIndex = 3; break;
1394 // Quad-register operations:
1395 case MVT::v16i8: OpcodeIndex = 0; break;
1396 case MVT::v8i16: OpcodeIndex = 1; break;
1398 case MVT::v4i32: OpcodeIndex = 2; break;
1399 case MVT::v2i64: OpcodeIndex = 3;
1400 assert(NumVecs == 1 && "v2i64 type only supported for VLD1");
1408 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1411 ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts);
1414 SDValue Pred = getAL(CurDAG);
1415 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1417 if (is64BitVector) {
1418 unsigned Opc = DOpcodes[OpcodeIndex];
1419 const SDValue Ops[] = { MemAddr, Align, Pred, Reg0, Chain };
1420 SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTy, MVT::Other, Ops, 5);
1424 SuperReg = SDValue(VLd, 0);
1425 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1426 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1427 SDValue D = CurDAG->getTargetExtractSubreg(ARM::dsub_0+Vec,
1429 ReplaceUses(SDValue(N, Vec), D);
1431 ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1));
1436 // Quad registers are directly supported for VLD1 and VLD2,
1437 // loading pairs of D regs.
1438 unsigned Opc = QOpcodes0[OpcodeIndex];
1439 const SDValue Ops[] = { MemAddr, Align, Pred, Reg0, Chain };
1440 SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTy, MVT::Other, Ops, 5);
1444 SuperReg = SDValue(VLd, 0);
1445 Chain = SDValue(VLd, 1);
1448 // Otherwise, quad registers are loaded with two separate instructions,
1449 // where one loads the even registers and the other loads the odd registers.
1450 EVT AddrTy = MemAddr.getValueType();
1452 // Load the even subregs.
1453 unsigned Opc = QOpcodes0[OpcodeIndex];
1455 SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy), 0);
1456 const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain };
1458 CurDAG->getMachineNode(Opc, dl, ResTy, AddrTy, MVT::Other, OpsA, 7);
1459 Chain = SDValue(VLdA, 2);
1461 // Load the odd subregs.
1462 Opc = QOpcodes1[OpcodeIndex];
1463 const SDValue OpsB[] = { SDValue(VLdA, 1), Align, Reg0, SDValue(VLdA, 0),
1464 Pred, Reg0, Chain };
1466 CurDAG->getMachineNode(Opc, dl, ResTy, AddrTy, MVT::Other, OpsB, 7);
1467 SuperReg = SDValue(VLdB, 0);
1468 Chain = SDValue(VLdB, 2);
1471 // Extract out the Q registers.
1472 assert(ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1473 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1474 SDValue Q = CurDAG->getTargetExtractSubreg(ARM::qsub_0+Vec,
1476 ReplaceUses(SDValue(N, Vec), Q);
1478 ReplaceUses(SDValue(N, NumVecs), Chain);
1482 SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, unsigned NumVecs,
1483 unsigned *DOpcodes, unsigned *QOpcodes0,
1484 unsigned *QOpcodes1) {
1485 assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range");
1486 DebugLoc dl = N->getDebugLoc();
1488 SDValue MemAddr, Align;
1489 if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, Align))
1492 SDValue Chain = N->getOperand(0);
1493 EVT VT = N->getOperand(3).getValueType();
1494 bool is64BitVector = VT.is64BitVector();
1495 Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1497 unsigned OpcodeIndex;
1498 switch (VT.getSimpleVT().SimpleTy) {
1499 default: llvm_unreachable("unhandled vst type");
1500 // Double-register operations:
1501 case MVT::v8i8: OpcodeIndex = 0; break;
1502 case MVT::v4i16: OpcodeIndex = 1; break;
1504 case MVT::v2i32: OpcodeIndex = 2; break;
1505 case MVT::v1i64: OpcodeIndex = 3; break;
1506 // Quad-register operations:
1507 case MVT::v16i8: OpcodeIndex = 0; break;
1508 case MVT::v8i16: OpcodeIndex = 1; break;
1510 case MVT::v4i32: OpcodeIndex = 2; break;
1511 case MVT::v2i64: OpcodeIndex = 3;
1512 assert(NumVecs == 1 && "v2i64 type only supported for VST1");
1516 SDValue Pred = getAL(CurDAG);
1517 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1519 SmallVector<SDValue, 7> Ops;
1520 Ops.push_back(MemAddr);
1521 Ops.push_back(Align);
1523 if (is64BitVector) {
1525 Ops.push_back(N->getOperand(3));
1528 SDValue V0 = N->getOperand(0+3);
1529 SDValue V1 = N->getOperand(1+3);
1531 // Form a REG_SEQUENCE to force register allocation.
1533 RegSeq = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1535 SDValue V2 = N->getOperand(2+3);
1536 // If it's a vld3, form a quad D-register and leave the last part as
1538 SDValue V3 = (NumVecs == 3)
1539 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1540 : N->getOperand(3+3);
1541 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1543 Ops.push_back(RegSeq);
1545 Ops.push_back(Pred);
1546 Ops.push_back(Reg0); // predicate register
1547 Ops.push_back(Chain);
1548 unsigned Opc = DOpcodes[OpcodeIndex];
1549 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 6);
1553 // Quad registers are directly supported for VST1 and VST2.
1554 unsigned Opc = QOpcodes0[OpcodeIndex];
1556 Ops.push_back(N->getOperand(3));
1558 // Form a QQ register.
1559 SDValue Q0 = N->getOperand(3);
1560 SDValue Q1 = N->getOperand(4);
1561 Ops.push_back(SDValue(PairQRegs(MVT::v4i64, Q0, Q1), 0));
1563 Ops.push_back(Pred);
1564 Ops.push_back(Reg0); // predicate register
1565 Ops.push_back(Chain);
1566 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 6);
1569 // Otherwise, quad registers are stored with two separate instructions,
1570 // where one stores the even registers and the other stores the odd registers.
1572 // Form the QQQQ REG_SEQUENCE.
1573 SDValue V0 = N->getOperand(0+3);
1574 SDValue V1 = N->getOperand(1+3);
1575 SDValue V2 = N->getOperand(2+3);
1576 SDValue V3 = (NumVecs == 3)
1577 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1578 : N->getOperand(3+3);
1579 SDValue RegSeq = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);
1581 // Store the even D registers.
1582 Ops.push_back(Reg0); // post-access address offset
1583 Ops.push_back(RegSeq);
1584 Ops.push_back(Pred);
1585 Ops.push_back(Reg0); // predicate register
1586 Ops.push_back(Chain);
1587 unsigned Opc = QOpcodes0[OpcodeIndex];
1588 SDNode *VStA = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
1589 MVT::Other, Ops.data(), 7);
1590 Chain = SDValue(VStA, 1);
1592 // Store the odd D registers.
1593 Ops[0] = SDValue(VStA, 0); // MemAddr
1595 Opc = QOpcodes1[OpcodeIndex];
1596 SDNode *VStB = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
1597 MVT::Other, Ops.data(), 7);
1598 Chain = SDValue(VStB, 1);
1599 ReplaceUses(SDValue(N, 0), Chain);
1603 SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
1604 unsigned NumVecs, unsigned *DOpcodes,
1605 unsigned *QOpcodes) {
1606 assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
1607 DebugLoc dl = N->getDebugLoc();
1609 SDValue MemAddr, Align;
1610 if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, Align))
1613 SDValue Chain = N->getOperand(0);
1615 cast<ConstantSDNode>(N->getOperand(NumVecs+3))->getZExtValue();
1616 EVT VT = IsLoad ? N->getValueType(0) : N->getOperand(3).getValueType();
1617 bool is64BitVector = VT.is64BitVector();
1619 unsigned Alignment = 0;
1621 Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1622 unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
1623 if (Alignment > NumBytes)
1624 Alignment = NumBytes;
1625 if (Alignment < 8 && Alignment < NumBytes)
1627 // Alignment must be a power of two; make sure of that.
1628 Alignment = (Alignment & -Alignment);
1632 Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
1634 unsigned OpcodeIndex;
1635 switch (VT.getSimpleVT().SimpleTy) {
1636 default: llvm_unreachable("unhandled vld/vst lane type");
1637 // Double-register operations:
1638 case MVT::v8i8: OpcodeIndex = 0; break;
1639 case MVT::v4i16: OpcodeIndex = 1; break;
1641 case MVT::v2i32: OpcodeIndex = 2; break;
1642 // Quad-register operations:
1643 case MVT::v8i16: OpcodeIndex = 0; break;
1645 case MVT::v4i32: OpcodeIndex = 1; break;
1648 SDValue Pred = getAL(CurDAG);
1649 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1651 SmallVector<SDValue, 7> Ops;
1652 Ops.push_back(MemAddr);
1653 Ops.push_back(Align);
1655 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1656 QOpcodes[OpcodeIndex]);
1659 SDValue V0 = N->getOperand(0+3);
1660 SDValue V1 = N->getOperand(1+3);
1663 SuperReg = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1665 SuperReg = SDValue(PairQRegs(MVT::v4i64, V0, V1), 0);
1667 SDValue V2 = N->getOperand(2+3);
1668 SDValue V3 = (NumVecs == 3)
1669 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1670 : N->getOperand(3+3);
1672 SuperReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1674 SuperReg = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);
1676 Ops.push_back(SuperReg);
1677 Ops.push_back(getI32Imm(Lane));
1678 Ops.push_back(Pred);
1679 Ops.push_back(Reg0);
1680 Ops.push_back(Chain);
1683 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 7);
1686 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1689 ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts);
1691 SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTy, MVT::Other,
1693 SuperReg = SDValue(VLdLn, 0);
1694 Chain = SDValue(VLdLn, 1);
1696 // Extract the subregisters.
1697 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1698 assert(ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1699 unsigned SubIdx = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;
1700 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1701 ReplaceUses(SDValue(N, Vec),
1702 CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, SuperReg));
1703 ReplaceUses(SDValue(N, NumVecs), Chain);
1707 SDNode *ARMDAGToDAGISel::SelectVLDDup(SDNode *N, unsigned NumVecs,
1708 unsigned *Opcodes) {
1709 assert(NumVecs >=2 && NumVecs <= 4 && "VLDDup NumVecs out-of-range");
1710 DebugLoc dl = N->getDebugLoc();
1712 SDValue MemAddr, Align;
1713 if (!SelectAddrMode6(N, N->getOperand(1), MemAddr, Align))
1716 SDValue Chain = N->getOperand(0);
1717 EVT VT = N->getValueType(0);
1719 unsigned Alignment = 0;
1721 Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1722 unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
1723 if (Alignment > NumBytes)
1724 Alignment = NumBytes;
1725 if (Alignment < 8 && Alignment < NumBytes)
1727 // Alignment must be a power of two; make sure of that.
1728 Alignment = (Alignment & -Alignment);
1732 Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
1734 unsigned OpcodeIndex;
1735 switch (VT.getSimpleVT().SimpleTy) {
1736 default: llvm_unreachable("unhandled vld-dup type");
1737 case MVT::v8i8: OpcodeIndex = 0; break;
1738 case MVT::v4i16: OpcodeIndex = 1; break;
1740 case MVT::v2i32: OpcodeIndex = 2; break;
1743 SDValue Pred = getAL(CurDAG);
1744 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1746 unsigned Opc = Opcodes[OpcodeIndex];
1747 const SDValue Ops[] = { MemAddr, Align, Pred, Reg0, Chain };
1749 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1750 EVT ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts);
1751 SDNode *VLdDup = CurDAG->getMachineNode(Opc, dl, ResTy, MVT::Other, Ops, 5);
1752 SuperReg = SDValue(VLdDup, 0);
1753 Chain = SDValue(VLdDup, 1);
1755 // Extract the subregisters.
1756 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1757 unsigned SubIdx = ARM::dsub_0;
1758 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1759 ReplaceUses(SDValue(N, Vec),
1760 CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, SuperReg));
1761 ReplaceUses(SDValue(N, NumVecs), Chain);
1765 SDNode *ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs,
1767 assert(NumVecs >= 2 && NumVecs <= 4 && "VTBL NumVecs out-of-range");
1768 DebugLoc dl = N->getDebugLoc();
1769 EVT VT = N->getValueType(0);
1770 unsigned FirstTblReg = IsExt ? 2 : 1;
1772 // Form a REG_SEQUENCE to force register allocation.
1774 SDValue V0 = N->getOperand(FirstTblReg + 0);
1775 SDValue V1 = N->getOperand(FirstTblReg + 1);
1777 RegSeq = SDValue(PairDRegs(MVT::v16i8, V0, V1), 0);
1779 SDValue V2 = N->getOperand(FirstTblReg + 2);
1780 // If it's a vtbl3, form a quad D-register and leave the last part as
1782 SDValue V3 = (NumVecs == 3)
1783 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1784 : N->getOperand(FirstTblReg + 3);
1785 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1788 SmallVector<SDValue, 6> Ops;
1790 Ops.push_back(N->getOperand(1));
1791 Ops.push_back(RegSeq);
1792 Ops.push_back(N->getOperand(FirstTblReg + NumVecs));
1793 Ops.push_back(getAL(CurDAG)); // predicate
1794 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // predicate register
1795 return CurDAG->getMachineNode(Opc, dl, VT, Ops.data(), Ops.size());
1798 SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N,
1800 if (!Subtarget->hasV6T2Ops())
1803 unsigned Opc = isSigned ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX)
1804 : (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX);
1807 // For unsigned extracts, check for a shift right and mask
1808 unsigned And_imm = 0;
1809 if (N->getOpcode() == ISD::AND) {
1810 if (isOpcWithIntImmediate(N, ISD::AND, And_imm)) {
1812 // The immediate is a mask of the low bits iff imm & (imm+1) == 0
1813 if (And_imm & (And_imm + 1))
1816 unsigned Srl_imm = 0;
1817 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL,
1819 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
1821 unsigned Width = CountTrailingOnes_32(And_imm);
1822 unsigned LSB = Srl_imm;
1823 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1824 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1825 CurDAG->getTargetConstant(LSB, MVT::i32),
1826 CurDAG->getTargetConstant(Width, MVT::i32),
1827 getAL(CurDAG), Reg0 };
1828 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1834 // Otherwise, we're looking for a shift of a shift
1835 unsigned Shl_imm = 0;
1836 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, Shl_imm)) {
1837 assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!");
1838 unsigned Srl_imm = 0;
1839 if (isInt32Immediate(N->getOperand(1), Srl_imm)) {
1840 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
1841 unsigned Width = 32 - Srl_imm;
1842 int LSB = Srl_imm - Shl_imm;
1845 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1846 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1847 CurDAG->getTargetConstant(LSB, MVT::i32),
1848 CurDAG->getTargetConstant(Width, MVT::i32),
1849 getAL(CurDAG), Reg0 };
1850 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1856 SDNode *ARMDAGToDAGISel::
1857 SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1858 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1861 if (SelectT2ShifterOperandReg(TrueVal, CPTmp0, CPTmp1)) {
1862 unsigned SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue();
1863 unsigned SOShOp = ARM_AM::getSORegShOp(SOVal);
1866 case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break;
1867 case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break;
1868 case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break;
1869 case ARM_AM::ror: Opc = ARM::t2MOVCCror; break;
1871 llvm_unreachable("Unknown so_reg opcode!");
1875 CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32);
1876 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1877 SDValue Ops[] = { FalseVal, CPTmp0, SOShImm, CC, CCR, InFlag };
1878 return CurDAG->SelectNodeTo(N, Opc, MVT::i32,Ops, 6);
1883 SDNode *ARMDAGToDAGISel::
1884 SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1885 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1889 if (SelectShifterOperandReg(TrueVal, CPTmp0, CPTmp1, CPTmp2)) {
1890 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1891 SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CPTmp2, CC, CCR, InFlag };
1892 return CurDAG->SelectNodeTo(N, ARM::MOVCCs, MVT::i32, Ops, 7);
1897 SDNode *ARMDAGToDAGISel::
1898 SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1899 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1900 ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
1905 unsigned TrueImm = T->getZExtValue();
1906 if (is_t2_so_imm(TrueImm)) {
1907 Opc = ARM::t2MOVCCi;
1908 } else if (TrueImm <= 0xffff) {
1909 Opc = ARM::t2MOVCCi16;
1910 } else if (is_t2_so_imm_not(TrueImm)) {
1912 Opc = ARM::t2MVNCCi;
1913 } else if (TrueVal.getNode()->hasOneUse() && Subtarget->hasV6T2Ops()) {
1915 Opc = ARM::t2MOVCCi32imm;
1919 SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
1920 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1921 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
1922 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1928 SDNode *ARMDAGToDAGISel::
1929 SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1930 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1931 ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
1936 unsigned TrueImm = T->getZExtValue();
1937 bool isSoImm = is_so_imm(TrueImm);
1940 } else if (Subtarget->hasV6T2Ops() && TrueImm <= 0xffff) {
1941 Opc = ARM::MOVCCi16;
1942 } else if (is_so_imm_not(TrueImm)) {
1945 } else if (TrueVal.getNode()->hasOneUse() &&
1946 (Subtarget->hasV6T2Ops() || ARM_AM::isSOImmTwoPartVal(TrueImm))) {
1948 Opc = ARM::MOVCCi32imm;
1952 SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
1953 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1954 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
1955 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1961 SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDNode *N) {
1962 EVT VT = N->getValueType(0);
1963 SDValue FalseVal = N->getOperand(0);
1964 SDValue TrueVal = N->getOperand(1);
1965 SDValue CC = N->getOperand(2);
1966 SDValue CCR = N->getOperand(3);
1967 SDValue InFlag = N->getOperand(4);
1968 assert(CC.getOpcode() == ISD::Constant);
1969 assert(CCR.getOpcode() == ISD::Register);
1970 ARMCC::CondCodes CCVal =
1971 (ARMCC::CondCodes)cast<ConstantSDNode>(CC)->getZExtValue();
1973 if (!Subtarget->isThumb1Only() && VT == MVT::i32) {
1974 // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1975 // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1976 // Pattern complexity = 18 cost = 1 size = 0
1980 if (Subtarget->isThumb()) {
1981 SDNode *Res = SelectT2CMOVShiftOp(N, FalseVal, TrueVal,
1982 CCVal, CCR, InFlag);
1984 Res = SelectT2CMOVShiftOp(N, TrueVal, FalseVal,
1985 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1989 SDNode *Res = SelectARMCMOVShiftOp(N, FalseVal, TrueVal,
1990 CCVal, CCR, InFlag);
1992 Res = SelectARMCMOVShiftOp(N, TrueVal, FalseVal,
1993 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1998 // Pattern: (ARMcmov:i32 GPR:i32:$false,
1999 // (imm:i32)<<P:Pred_so_imm>>:$true,
2001 // Emits: (MOVCCi:i32 GPR:i32:$false,
2002 // (so_imm:i32 (imm:i32):$true), (imm:i32):$cc)
2003 // Pattern complexity = 10 cost = 1 size = 0
2004 if (Subtarget->isThumb()) {
2005 SDNode *Res = SelectT2CMOVImmOp(N, FalseVal, TrueVal,
2006 CCVal, CCR, InFlag);
2008 Res = SelectT2CMOVImmOp(N, TrueVal, FalseVal,
2009 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2013 SDNode *Res = SelectARMCMOVImmOp(N, FalseVal, TrueVal,
2014 CCVal, CCR, InFlag);
2016 Res = SelectARMCMOVImmOp(N, TrueVal, FalseVal,
2017 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2023 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2024 // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2025 // Pattern complexity = 6 cost = 1 size = 0
2027 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2028 // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2029 // Pattern complexity = 6 cost = 11 size = 0
2031 // Also FCPYScc and FCPYDcc.
2032 SDValue Tmp2 = CurDAG->getTargetConstant(CCVal, MVT::i32);
2033 SDValue Ops[] = { FalseVal, TrueVal, Tmp2, CCR, InFlag };
2035 switch (VT.getSimpleVT().SimpleTy) {
2036 default: assert(false && "Illegal conditional move type!");
2039 Opc = Subtarget->isThumb()
2040 ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo)
2050 return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
2053 SDNode *ARMDAGToDAGISel::SelectConcatVector(SDNode *N) {
2054 // The only time a CONCAT_VECTORS operation can have legal types is when
2055 // two 64-bit vectors are concatenated to a 128-bit vector.
2056 EVT VT = N->getValueType(0);
2057 if (!VT.is128BitVector() || N->getNumOperands() != 2)
2058 llvm_unreachable("unexpected CONCAT_VECTORS");
2059 DebugLoc dl = N->getDebugLoc();
2060 SDValue V0 = N->getOperand(0);
2061 SDValue V1 = N->getOperand(1);
2062 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
2063 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
2064 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
2065 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
2068 SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
2069 DebugLoc dl = N->getDebugLoc();
2071 if (N->isMachineOpcode())
2072 return NULL; // Already selected.
2074 switch (N->getOpcode()) {
2076 case ISD::Constant: {
2077 unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
2079 if (Subtarget->hasThumb2())
2080 // Thumb2-aware targets have the MOVT instruction, so all immediates can
2081 // be done with MOV + MOVT, at worst.
2084 if (Subtarget->isThumb()) {
2085 UseCP = (Val > 255 && // MOV
2086 ~Val > 255 && // MOV + MVN
2087 !ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL
2089 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
2090 ARM_AM::getSOImmVal(~Val) == -1 && // MVN
2091 !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs.
2096 CurDAG->getTargetConstantPool(ConstantInt::get(
2097 Type::getInt32Ty(*CurDAG->getContext()), Val),
2098 TLI.getPointerTy());
2101 if (Subtarget->isThumb1Only()) {
2102 SDValue Pred = getAL(CurDAG);
2103 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2104 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
2105 ResNode = CurDAG->getMachineNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other,
2110 CurDAG->getTargetConstant(0, MVT::i32),
2112 CurDAG->getRegister(0, MVT::i32),
2113 CurDAG->getEntryNode()
2115 ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
2118 ReplaceUses(SDValue(N, 0), SDValue(ResNode, 0));
2122 // Other cases are autogenerated.
2125 case ISD::FrameIndex: {
2126 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
2127 int FI = cast<FrameIndexSDNode>(N)->getIndex();
2128 SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
2129 if (Subtarget->isThumb1Only()) {
2130 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
2131 CurDAG->getTargetConstant(0, MVT::i32));
2133 unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
2134 ARM::t2ADDri : ARM::ADDri);
2135 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
2136 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2137 CurDAG->getRegister(0, MVT::i32) };
2138 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2142 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2146 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, true))
2150 if (Subtarget->isThumb1Only())
2152 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
2153 unsigned RHSV = C->getZExtValue();
2155 if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
2156 unsigned ShImm = Log2_32(RHSV-1);
2159 SDValue V = N->getOperand(0);
2160 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2161 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2162 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2163 if (Subtarget->isThumb()) {
2164 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2165 return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
2167 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2168 return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7);
2171 if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
2172 unsigned ShImm = Log2_32(RHSV+1);
2175 SDValue V = N->getOperand(0);
2176 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2177 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2178 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2179 if (Subtarget->isThumb()) {
2180 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2181 return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 6);
2183 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2184 return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7);
2190 // Check for unsigned bitfield extract
2191 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2194 // (and (or x, c2), c1) and top 16-bits of c1 and c2 match, lower 16-bits
2195 // of c1 are 0xffff, and lower 16-bit of c2 are 0. That is, the top 16-bits
2196 // are entirely contributed by c2 and lower 16-bits are entirely contributed
2197 // by x. That's equal to (or (and x, 0xffff), (and c1, 0xffff0000)).
2198 // Select it to: "movt x, ((c1 & 0xffff) >> 16)
2199 EVT VT = N->getValueType(0);
2202 unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2())
2204 : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0);
2207 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2208 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2211 if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) {
2212 SDValue N2 = N0.getOperand(1);
2213 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2216 unsigned N1CVal = N1C->getZExtValue();
2217 unsigned N2CVal = N2C->getZExtValue();
2218 if ((N1CVal & 0xffff0000U) == (N2CVal & 0xffff0000U) &&
2219 (N1CVal & 0xffffU) == 0xffffU &&
2220 (N2CVal & 0xffffU) == 0x0U) {
2221 SDValue Imm16 = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16,
2223 SDValue Ops[] = { N0.getOperand(0), Imm16,
2224 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2225 return CurDAG->getMachineNode(Opc, dl, VT, Ops, 4);
2230 case ARMISD::VMOVRRD:
2231 return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32,
2232 N->getOperand(0), getAL(CurDAG),
2233 CurDAG->getRegister(0, MVT::i32));
2234 case ISD::UMUL_LOHI: {
2235 if (Subtarget->isThumb1Only())
2237 if (Subtarget->isThumb()) {
2238 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2239 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2240 CurDAG->getRegister(0, MVT::i32) };
2241 return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32,Ops,4);
2243 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2244 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2245 CurDAG->getRegister(0, MVT::i32) };
2246 return CurDAG->getMachineNode(ARM::UMULL, dl, MVT::i32, MVT::i32, Ops, 5);
2249 case ISD::SMUL_LOHI: {
2250 if (Subtarget->isThumb1Only())
2252 if (Subtarget->isThumb()) {
2253 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2254 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2255 return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32,Ops,4);
2257 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2258 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2259 CurDAG->getRegister(0, MVT::i32) };
2260 return CurDAG->getMachineNode(ARM::SMULL, dl, MVT::i32, MVT::i32, Ops, 5);
2264 SDNode *ResNode = 0;
2265 if (Subtarget->isThumb() && Subtarget->hasThumb2())
2266 ResNode = SelectT2IndexedLoad(N);
2268 ResNode = SelectARMIndexedLoad(N);
2271 // Other cases are autogenerated.
2274 case ARMISD::BRCOND: {
2275 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2276 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2277 // Pattern complexity = 6 cost = 1 size = 0
2279 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2280 // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
2281 // Pattern complexity = 6 cost = 1 size = 0
2283 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2284 // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2285 // Pattern complexity = 6 cost = 1 size = 0
2287 unsigned Opc = Subtarget->isThumb() ?
2288 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
2289 SDValue Chain = N->getOperand(0);
2290 SDValue N1 = N->getOperand(1);
2291 SDValue N2 = N->getOperand(2);
2292 SDValue N3 = N->getOperand(3);
2293 SDValue InFlag = N->getOperand(4);
2294 assert(N1.getOpcode() == ISD::BasicBlock);
2295 assert(N2.getOpcode() == ISD::Constant);
2296 assert(N3.getOpcode() == ISD::Register);
2298 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
2299 cast<ConstantSDNode>(N2)->getZExtValue()),
2301 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
2302 SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,
2304 Chain = SDValue(ResNode, 0);
2305 if (N->getNumValues() == 2) {
2306 InFlag = SDValue(ResNode, 1);
2307 ReplaceUses(SDValue(N, 1), InFlag);
2309 ReplaceUses(SDValue(N, 0),
2310 SDValue(Chain.getNode(), Chain.getResNo()));
2314 return SelectCMOVOp(N);
2315 case ARMISD::CNEG: {
2316 EVT VT = N->getValueType(0);
2317 SDValue N0 = N->getOperand(0);
2318 SDValue N1 = N->getOperand(1);
2319 SDValue N2 = N->getOperand(2);
2320 SDValue N3 = N->getOperand(3);
2321 SDValue InFlag = N->getOperand(4);
2322 assert(N2.getOpcode() == ISD::Constant);
2323 assert(N3.getOpcode() == ISD::Register);
2325 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
2326 cast<ConstantSDNode>(N2)->getZExtValue()),
2328 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
2330 switch (VT.getSimpleVT().SimpleTy) {
2331 default: assert(false && "Illegal conditional move type!");
2340 return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
2343 case ARMISD::VZIP: {
2345 EVT VT = N->getValueType(0);
2346 switch (VT.getSimpleVT().SimpleTy) {
2347 default: return NULL;
2348 case MVT::v8i8: Opc = ARM::VZIPd8; break;
2349 case MVT::v4i16: Opc = ARM::VZIPd16; break;
2351 case MVT::v2i32: Opc = ARM::VZIPd32; break;
2352 case MVT::v16i8: Opc = ARM::VZIPq8; break;
2353 case MVT::v8i16: Opc = ARM::VZIPq16; break;
2355 case MVT::v4i32: Opc = ARM::VZIPq32; break;
2357 SDValue Pred = getAL(CurDAG);
2358 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2359 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2360 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2362 case ARMISD::VUZP: {
2364 EVT VT = N->getValueType(0);
2365 switch (VT.getSimpleVT().SimpleTy) {
2366 default: return NULL;
2367 case MVT::v8i8: Opc = ARM::VUZPd8; break;
2368 case MVT::v4i16: Opc = ARM::VUZPd16; break;
2370 case MVT::v2i32: Opc = ARM::VUZPd32; break;
2371 case MVT::v16i8: Opc = ARM::VUZPq8; break;
2372 case MVT::v8i16: Opc = ARM::VUZPq16; break;
2374 case MVT::v4i32: Opc = ARM::VUZPq32; break;
2376 SDValue Pred = getAL(CurDAG);
2377 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2378 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2379 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2381 case ARMISD::VTRN: {
2383 EVT VT = N->getValueType(0);
2384 switch (VT.getSimpleVT().SimpleTy) {
2385 default: return NULL;
2386 case MVT::v8i8: Opc = ARM::VTRNd8; break;
2387 case MVT::v4i16: Opc = ARM::VTRNd16; break;
2389 case MVT::v2i32: Opc = ARM::VTRNd32; break;
2390 case MVT::v16i8: Opc = ARM::VTRNq8; break;
2391 case MVT::v8i16: Opc = ARM::VTRNq16; break;
2393 case MVT::v4i32: Opc = ARM::VTRNq32; break;
2395 SDValue Pred = getAL(CurDAG);
2396 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2397 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2398 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2400 case ARMISD::BUILD_VECTOR: {
2401 EVT VecVT = N->getValueType(0);
2402 EVT EltVT = VecVT.getVectorElementType();
2403 unsigned NumElts = VecVT.getVectorNumElements();
2404 if (EltVT == MVT::f64) {
2405 assert(NumElts == 2 && "unexpected type for BUILD_VECTOR");
2406 return PairDRegs(VecVT, N->getOperand(0), N->getOperand(1));
2408 assert(EltVT == MVT::f32 && "unexpected type for BUILD_VECTOR");
2410 return PairSRegs(VecVT, N->getOperand(0), N->getOperand(1));
2411 assert(NumElts == 4 && "unexpected type for BUILD_VECTOR");
2412 return QuadSRegs(VecVT, N->getOperand(0), N->getOperand(1),
2413 N->getOperand(2), N->getOperand(3));
2416 case ARMISD::VLD2DUP: {
2417 unsigned Opcodes[] = { ARM::VLD2DUPd8Pseudo, ARM::VLD2DUPd16Pseudo,
2418 ARM::VLD2DUPd32Pseudo };
2419 return SelectVLDDup(N, 2, Opcodes);
2422 case ARMISD::VLD3DUP: {
2423 unsigned Opcodes[] = { ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd16Pseudo,
2424 ARM::VLD3DUPd32Pseudo };
2425 return SelectVLDDup(N, 3, Opcodes);
2428 case ARMISD::VLD4DUP: {
2429 unsigned Opcodes[] = { ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd16Pseudo,
2430 ARM::VLD4DUPd32Pseudo };
2431 return SelectVLDDup(N, 4, Opcodes);
2434 case ISD::INTRINSIC_VOID:
2435 case ISD::INTRINSIC_W_CHAIN: {
2436 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
2441 case Intrinsic::arm_neon_vld1: {
2442 unsigned DOpcodes[] = { ARM::VLD1d8, ARM::VLD1d16,
2443 ARM::VLD1d32, ARM::VLD1d64 };
2444 unsigned QOpcodes[] = { ARM::VLD1q8Pseudo, ARM::VLD1q16Pseudo,
2445 ARM::VLD1q32Pseudo, ARM::VLD1q64Pseudo };
2446 return SelectVLD(N, 1, DOpcodes, QOpcodes, 0);
2449 case Intrinsic::arm_neon_vld2: {
2450 unsigned DOpcodes[] = { ARM::VLD2d8Pseudo, ARM::VLD2d16Pseudo,
2451 ARM::VLD2d32Pseudo, ARM::VLD1q64Pseudo };
2452 unsigned QOpcodes[] = { ARM::VLD2q8Pseudo, ARM::VLD2q16Pseudo,
2453 ARM::VLD2q32Pseudo };
2454 return SelectVLD(N, 2, DOpcodes, QOpcodes, 0);
2457 case Intrinsic::arm_neon_vld3: {
2458 unsigned DOpcodes[] = { ARM::VLD3d8Pseudo, ARM::VLD3d16Pseudo,
2459 ARM::VLD3d32Pseudo, ARM::VLD1d64TPseudo };
2460 unsigned QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
2461 ARM::VLD3q16Pseudo_UPD,
2462 ARM::VLD3q32Pseudo_UPD };
2463 unsigned QOpcodes1[] = { ARM::VLD3q8oddPseudo_UPD,
2464 ARM::VLD3q16oddPseudo_UPD,
2465 ARM::VLD3q32oddPseudo_UPD };
2466 return SelectVLD(N, 3, DOpcodes, QOpcodes0, QOpcodes1);
2469 case Intrinsic::arm_neon_vld4: {
2470 unsigned DOpcodes[] = { ARM::VLD4d8Pseudo, ARM::VLD4d16Pseudo,
2471 ARM::VLD4d32Pseudo, ARM::VLD1d64QPseudo };
2472 unsigned QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
2473 ARM::VLD4q16Pseudo_UPD,
2474 ARM::VLD4q32Pseudo_UPD };
2475 unsigned QOpcodes1[] = { ARM::VLD4q8oddPseudo_UPD,
2476 ARM::VLD4q16oddPseudo_UPD,
2477 ARM::VLD4q32oddPseudo_UPD };
2478 return SelectVLD(N, 4, DOpcodes, QOpcodes0, QOpcodes1);
2481 case Intrinsic::arm_neon_vld2lane: {
2482 unsigned DOpcodes[] = { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd16Pseudo,
2483 ARM::VLD2LNd32Pseudo };
2484 unsigned QOpcodes[] = { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq32Pseudo };
2485 return SelectVLDSTLane(N, true, 2, DOpcodes, QOpcodes);
2488 case Intrinsic::arm_neon_vld3lane: {
2489 unsigned DOpcodes[] = { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd16Pseudo,
2490 ARM::VLD3LNd32Pseudo };
2491 unsigned QOpcodes[] = { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq32Pseudo };
2492 return SelectVLDSTLane(N, true, 3, DOpcodes, QOpcodes);
2495 case Intrinsic::arm_neon_vld4lane: {
2496 unsigned DOpcodes[] = { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd16Pseudo,
2497 ARM::VLD4LNd32Pseudo };
2498 unsigned QOpcodes[] = { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq32Pseudo };
2499 return SelectVLDSTLane(N, true, 4, DOpcodes, QOpcodes);
2502 case Intrinsic::arm_neon_vst1: {
2503 unsigned DOpcodes[] = { ARM::VST1d8, ARM::VST1d16,
2504 ARM::VST1d32, ARM::VST1d64 };
2505 unsigned QOpcodes[] = { ARM::VST1q8Pseudo, ARM::VST1q16Pseudo,
2506 ARM::VST1q32Pseudo, ARM::VST1q64Pseudo };
2507 return SelectVST(N, 1, DOpcodes, QOpcodes, 0);
2510 case Intrinsic::arm_neon_vst2: {
2511 unsigned DOpcodes[] = { ARM::VST2d8Pseudo, ARM::VST2d16Pseudo,
2512 ARM::VST2d32Pseudo, ARM::VST1q64Pseudo };
2513 unsigned QOpcodes[] = { ARM::VST2q8Pseudo, ARM::VST2q16Pseudo,
2514 ARM::VST2q32Pseudo };
2515 return SelectVST(N, 2, DOpcodes, QOpcodes, 0);
2518 case Intrinsic::arm_neon_vst3: {
2519 unsigned DOpcodes[] = { ARM::VST3d8Pseudo, ARM::VST3d16Pseudo,
2520 ARM::VST3d32Pseudo, ARM::VST1d64TPseudo };
2521 unsigned QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
2522 ARM::VST3q16Pseudo_UPD,
2523 ARM::VST3q32Pseudo_UPD };
2524 unsigned QOpcodes1[] = { ARM::VST3q8oddPseudo_UPD,
2525 ARM::VST3q16oddPseudo_UPD,
2526 ARM::VST3q32oddPseudo_UPD };
2527 return SelectVST(N, 3, DOpcodes, QOpcodes0, QOpcodes1);
2530 case Intrinsic::arm_neon_vst4: {
2531 unsigned DOpcodes[] = { ARM::VST4d8Pseudo, ARM::VST4d16Pseudo,
2532 ARM::VST4d32Pseudo, ARM::VST1d64QPseudo };
2533 unsigned QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
2534 ARM::VST4q16Pseudo_UPD,
2535 ARM::VST4q32Pseudo_UPD };
2536 unsigned QOpcodes1[] = { ARM::VST4q8oddPseudo_UPD,
2537 ARM::VST4q16oddPseudo_UPD,
2538 ARM::VST4q32oddPseudo_UPD };
2539 return SelectVST(N, 4, DOpcodes, QOpcodes0, QOpcodes1);
2542 case Intrinsic::arm_neon_vst2lane: {
2543 unsigned DOpcodes[] = { ARM::VST2LNd8Pseudo, ARM::VST2LNd16Pseudo,
2544 ARM::VST2LNd32Pseudo };
2545 unsigned QOpcodes[] = { ARM::VST2LNq16Pseudo, ARM::VST2LNq32Pseudo };
2546 return SelectVLDSTLane(N, false, 2, DOpcodes, QOpcodes);
2549 case Intrinsic::arm_neon_vst3lane: {
2550 unsigned DOpcodes[] = { ARM::VST3LNd8Pseudo, ARM::VST3LNd16Pseudo,
2551 ARM::VST3LNd32Pseudo };
2552 unsigned QOpcodes[] = { ARM::VST3LNq16Pseudo, ARM::VST3LNq32Pseudo };
2553 return SelectVLDSTLane(N, false, 3, DOpcodes, QOpcodes);
2556 case Intrinsic::arm_neon_vst4lane: {
2557 unsigned DOpcodes[] = { ARM::VST4LNd8Pseudo, ARM::VST4LNd16Pseudo,
2558 ARM::VST4LNd32Pseudo };
2559 unsigned QOpcodes[] = { ARM::VST4LNq16Pseudo, ARM::VST4LNq32Pseudo };
2560 return SelectVLDSTLane(N, false, 4, DOpcodes, QOpcodes);
2566 case ISD::INTRINSIC_WO_CHAIN: {
2567 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
2572 case Intrinsic::arm_neon_vtbl2:
2573 return SelectVTBL(N, false, 2, ARM::VTBL2Pseudo);
2574 case Intrinsic::arm_neon_vtbl3:
2575 return SelectVTBL(N, false, 3, ARM::VTBL3Pseudo);
2576 case Intrinsic::arm_neon_vtbl4:
2577 return SelectVTBL(N, false, 4, ARM::VTBL4Pseudo);
2579 case Intrinsic::arm_neon_vtbx2:
2580 return SelectVTBL(N, true, 2, ARM::VTBX2Pseudo);
2581 case Intrinsic::arm_neon_vtbx3:
2582 return SelectVTBL(N, true, 3, ARM::VTBX3Pseudo);
2583 case Intrinsic::arm_neon_vtbx4:
2584 return SelectVTBL(N, true, 4, ARM::VTBX4Pseudo);
2589 case ISD::CONCAT_VECTORS:
2590 return SelectConcatVector(N);
2593 return SelectCode(N);
2596 bool ARMDAGToDAGISel::
2597 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
2598 std::vector<SDValue> &OutOps) {
2599 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
2600 // Require the address to be in a register. That is safe for all ARM
2601 // variants and it is hard to do anything much smarter without knowing
2602 // how the operand is used.
2603 OutOps.push_back(Op);
2607 /// createARMISelDag - This pass converts a legalized DAG into a
2608 /// ARM-specific DAG, ready for instruction scheduling.
2610 FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
2611 CodeGenOpt::Level OptLevel) {
2612 return new ARMDAGToDAGISel(TM, OptLevel);