1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMISelLowering.h"
17 #include "ARMTargetMachine.h"
18 #include "llvm/CallingConv.h"
19 #include "llvm/Constants.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/LLVMContext.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CodeGen/SelectionDAGISel.h"
29 #include "llvm/Target/TargetLowering.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Support/Compiler.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
38 //===--------------------------------------------------------------------===//
39 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
40 /// instructions for SelectionDAG operations.
43 class ARMDAGToDAGISel : public SelectionDAGISel {
44 ARMBaseTargetMachine &TM;
46 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
47 /// make the right decision when generating code for different targets.
48 const ARMSubtarget *Subtarget;
51 explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm,
52 CodeGenOpt::Level OptLevel)
53 : SelectionDAGISel(tm, OptLevel), TM(tm),
54 Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
57 virtual const char *getPassName() const {
58 return "ARM Instruction Selection";
61 /// getI32Imm - Return a target constant of type i32 with the specified
63 inline SDValue getI32Imm(unsigned Imm) {
64 return CurDAG->getTargetConstant(Imm, MVT::i32);
67 SDNode *Select(SDValue Op);
68 virtual void InstructionSelect();
69 bool SelectShifterOperandReg(SDValue Op, SDValue N, SDValue &A,
70 SDValue &B, SDValue &C);
71 bool SelectAddrMode2(SDValue Op, SDValue N, SDValue &Base,
72 SDValue &Offset, SDValue &Opc);
73 bool SelectAddrMode2Offset(SDValue Op, SDValue N,
74 SDValue &Offset, SDValue &Opc);
75 bool SelectAddrMode3(SDValue Op, SDValue N, SDValue &Base,
76 SDValue &Offset, SDValue &Opc);
77 bool SelectAddrMode3Offset(SDValue Op, SDValue N,
78 SDValue &Offset, SDValue &Opc);
79 bool SelectAddrMode4(SDValue Op, SDValue N, SDValue &Addr,
81 bool SelectAddrMode5(SDValue Op, SDValue N, SDValue &Base,
83 bool SelectAddrMode6(SDValue Op, SDValue N, SDValue &Addr, SDValue &Update,
84 SDValue &Opc, SDValue &Align);
86 bool SelectAddrModePC(SDValue Op, SDValue N, SDValue &Offset,
89 bool SelectThumbAddrModeRR(SDValue Op, SDValue N, SDValue &Base,
91 bool SelectThumbAddrModeRI5(SDValue Op, SDValue N, unsigned Scale,
92 SDValue &Base, SDValue &OffImm,
94 bool SelectThumbAddrModeS1(SDValue Op, SDValue N, SDValue &Base,
95 SDValue &OffImm, SDValue &Offset);
96 bool SelectThumbAddrModeS2(SDValue Op, SDValue N, SDValue &Base,
97 SDValue &OffImm, SDValue &Offset);
98 bool SelectThumbAddrModeS4(SDValue Op, SDValue N, SDValue &Base,
99 SDValue &OffImm, SDValue &Offset);
100 bool SelectThumbAddrModeSP(SDValue Op, SDValue N, SDValue &Base,
103 bool SelectT2ShifterOperandReg(SDValue Op, SDValue N,
104 SDValue &BaseReg, SDValue &Opc);
105 bool SelectT2AddrModeImm12(SDValue Op, SDValue N, SDValue &Base,
107 bool SelectT2AddrModeImm8(SDValue Op, SDValue N, SDValue &Base,
109 bool SelectT2AddrModeImm8Offset(SDValue Op, SDValue N,
111 bool SelectT2AddrModeImm8s4(SDValue Op, SDValue N, SDValue &Base,
113 bool SelectT2AddrModeSoReg(SDValue Op, SDValue N, SDValue &Base,
114 SDValue &OffReg, SDValue &ShImm);
116 // Include the pieces autogenerated from the target description.
117 #include "ARMGenDAGISel.inc"
120 /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
122 SDNode *SelectARMIndexedLoad(SDValue Op);
123 SDNode *SelectT2IndexedLoad(SDValue Op);
125 /// SelectDYN_ALLOC - Select dynamic alloc for Thumb.
126 SDNode *SelectDYN_ALLOC(SDValue Op);
128 /// SelectVLD - Select NEON load intrinsics. NumVecs should
129 /// be 2, 3 or 4. The opcode arrays specify the instructions used for
130 /// loads of D registers and even subregs and odd subregs of Q registers.
131 /// For NumVecs == 2, QOpcodes1 is not used.
132 SDNode *SelectVLD(SDValue Op, unsigned NumVecs, unsigned *DOpcodes,
133 unsigned *QOpcodes0, unsigned *QOpcodes1);
135 /// SelectVST - Select NEON store intrinsics. NumVecs should
136 /// be 2, 3 or 4. The opcode arrays specify the instructions used for
137 /// stores of D registers and even subregs and odd subregs of Q registers.
138 /// For NumVecs == 2, QOpcodes1 is not used.
139 SDNode *SelectVST(SDValue Op, unsigned NumVecs, unsigned *DOpcodes,
140 unsigned *QOpcodes0, unsigned *QOpcodes1);
142 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should
143 /// be 2, 3 or 4. The opcode arrays specify the instructions used for
144 /// load/store of D registers and even subregs and odd subregs of Q registers.
145 SDNode *SelectVLDSTLane(SDValue Op, bool IsLoad, unsigned NumVecs,
146 unsigned *DOpcodes, unsigned *QOpcodes0,
147 unsigned *QOpcodes1);
149 /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM.
150 SDNode *SelectV6T2BitfieldExtractOp(SDValue Op, unsigned Opc);
152 /// SelectCMOVOp - Select CMOV instructions for ARM.
153 SDNode *SelectCMOVOp(SDValue Op);
155 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
156 /// inline asm expressions.
157 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
159 std::vector<SDValue> &OutOps);
161 /// PairDRegs - Insert a pair of double registers into an implicit def to
162 /// form a quad register.
163 SDNode *PairDRegs(EVT VT, SDValue V0, SDValue V1);
167 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
168 /// operand. If so Imm will receive the 32-bit value.
169 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
170 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
171 Imm = cast<ConstantSDNode>(N)->getZExtValue();
177 // isInt32Immediate - This method tests to see if a constant operand.
178 // If so Imm will receive the 32 bit value.
179 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
180 return isInt32Immediate(N.getNode(), Imm);
183 // isOpcWithIntImmediate - This method tests to see if the node is a specific
184 // opcode and that it has a immediate integer right operand.
185 // If so Imm will receive the 32 bit value.
186 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
187 return N->getOpcode() == Opc &&
188 isInt32Immediate(N->getOperand(1).getNode(), Imm);
192 void ARMDAGToDAGISel::InstructionSelect() {
194 CurDAG->RemoveDeadNodes();
197 bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue Op,
202 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
204 // Don't match base register only case. That is matched to a separate
205 // lower complexity pattern with explicit register operand.
206 if (ShOpcVal == ARM_AM::no_shift) return false;
208 BaseReg = N.getOperand(0);
209 unsigned ShImmVal = 0;
210 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
211 ShReg = CurDAG->getRegister(0, MVT::i32);
212 ShImmVal = RHS->getZExtValue() & 31;
214 ShReg = N.getOperand(1);
216 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
221 bool ARMDAGToDAGISel::SelectAddrMode2(SDValue Op, SDValue N,
222 SDValue &Base, SDValue &Offset,
224 if (N.getOpcode() == ISD::MUL) {
225 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
226 // X * [3,5,9] -> X + X * [2,4,8] etc.
227 int RHSC = (int)RHS->getZExtValue();
230 ARM_AM::AddrOpc AddSub = ARM_AM::add;
232 AddSub = ARM_AM::sub;
235 if (isPowerOf2_32(RHSC)) {
236 unsigned ShAmt = Log2_32(RHSC);
237 Base = Offset = N.getOperand(0);
238 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
247 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
249 if (N.getOpcode() == ISD::FrameIndex) {
250 int FI = cast<FrameIndexSDNode>(N)->getIndex();
251 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
252 } else if (N.getOpcode() == ARMISD::Wrapper) {
253 Base = N.getOperand(0);
255 Offset = CurDAG->getRegister(0, MVT::i32);
256 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
262 // Match simple R +/- imm12 operands.
263 if (N.getOpcode() == ISD::ADD)
264 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
265 int RHSC = (int)RHS->getZExtValue();
266 if ((RHSC >= 0 && RHSC < 0x1000) ||
267 (RHSC < 0 && RHSC > -0x1000)) { // 12 bits.
268 Base = N.getOperand(0);
269 if (Base.getOpcode() == ISD::FrameIndex) {
270 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
271 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
273 Offset = CurDAG->getRegister(0, MVT::i32);
275 ARM_AM::AddrOpc AddSub = ARM_AM::add;
277 AddSub = ARM_AM::sub;
280 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
287 // Otherwise this is R +/- [possibly shifted] R.
288 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
289 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
292 Base = N.getOperand(0);
293 Offset = N.getOperand(1);
295 if (ShOpcVal != ARM_AM::no_shift) {
296 // Check to see if the RHS of the shift is a constant, if not, we can't fold
298 if (ConstantSDNode *Sh =
299 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
300 ShAmt = Sh->getZExtValue();
301 Offset = N.getOperand(1).getOperand(0);
303 ShOpcVal = ARM_AM::no_shift;
307 // Try matching (R shl C) + (R).
308 if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift) {
309 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
310 if (ShOpcVal != ARM_AM::no_shift) {
311 // Check to see if the RHS of the shift is a constant, if not, we can't
313 if (ConstantSDNode *Sh =
314 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
315 ShAmt = Sh->getZExtValue();
316 Offset = N.getOperand(0).getOperand(0);
317 Base = N.getOperand(1);
319 ShOpcVal = ARM_AM::no_shift;
324 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
329 bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDValue Op, SDValue N,
330 SDValue &Offset, SDValue &Opc) {
331 unsigned Opcode = Op.getOpcode();
332 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
333 ? cast<LoadSDNode>(Op)->getAddressingMode()
334 : cast<StoreSDNode>(Op)->getAddressingMode();
335 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
336 ? ARM_AM::add : ARM_AM::sub;
337 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
338 int Val = (int)C->getZExtValue();
339 if (Val >= 0 && Val < 0x1000) { // 12 bits.
340 Offset = CurDAG->getRegister(0, MVT::i32);
341 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
349 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
351 if (ShOpcVal != ARM_AM::no_shift) {
352 // Check to see if the RHS of the shift is a constant, if not, we can't fold
354 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
355 ShAmt = Sh->getZExtValue();
356 Offset = N.getOperand(0);
358 ShOpcVal = ARM_AM::no_shift;
362 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
368 bool ARMDAGToDAGISel::SelectAddrMode3(SDValue Op, SDValue N,
369 SDValue &Base, SDValue &Offset,
371 if (N.getOpcode() == ISD::SUB) {
372 // X - C is canonicalize to X + -C, no need to handle it here.
373 Base = N.getOperand(0);
374 Offset = N.getOperand(1);
375 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
379 if (N.getOpcode() != ISD::ADD) {
381 if (N.getOpcode() == ISD::FrameIndex) {
382 int FI = cast<FrameIndexSDNode>(N)->getIndex();
383 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
385 Offset = CurDAG->getRegister(0, MVT::i32);
386 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
390 // If the RHS is +/- imm8, fold into addr mode.
391 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
392 int RHSC = (int)RHS->getZExtValue();
393 if ((RHSC >= 0 && RHSC < 256) ||
394 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
395 Base = N.getOperand(0);
396 if (Base.getOpcode() == ISD::FrameIndex) {
397 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
398 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
400 Offset = CurDAG->getRegister(0, MVT::i32);
402 ARM_AM::AddrOpc AddSub = ARM_AM::add;
404 AddSub = ARM_AM::sub;
407 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
412 Base = N.getOperand(0);
413 Offset = N.getOperand(1);
414 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
418 bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDValue Op, SDValue N,
419 SDValue &Offset, SDValue &Opc) {
420 unsigned Opcode = Op.getOpcode();
421 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
422 ? cast<LoadSDNode>(Op)->getAddressingMode()
423 : cast<StoreSDNode>(Op)->getAddressingMode();
424 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
425 ? ARM_AM::add : ARM_AM::sub;
426 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
427 int Val = (int)C->getZExtValue();
428 if (Val >= 0 && Val < 256) {
429 Offset = CurDAG->getRegister(0, MVT::i32);
430 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
436 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
440 bool ARMDAGToDAGISel::SelectAddrMode4(SDValue Op, SDValue N,
441 SDValue &Addr, SDValue &Mode) {
443 Mode = CurDAG->getTargetConstant(0, MVT::i32);
447 bool ARMDAGToDAGISel::SelectAddrMode5(SDValue Op, SDValue N,
448 SDValue &Base, SDValue &Offset) {
449 if (N.getOpcode() != ISD::ADD) {
451 if (N.getOpcode() == ISD::FrameIndex) {
452 int FI = cast<FrameIndexSDNode>(N)->getIndex();
453 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
454 } else if (N.getOpcode() == ARMISD::Wrapper) {
455 Base = N.getOperand(0);
457 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
462 // If the RHS is +/- imm8, fold into addr mode.
463 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
464 int RHSC = (int)RHS->getZExtValue();
465 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied by 4.
467 if ((RHSC >= 0 && RHSC < 256) ||
468 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
469 Base = N.getOperand(0);
470 if (Base.getOpcode() == ISD::FrameIndex) {
471 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
472 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
475 ARM_AM::AddrOpc AddSub = ARM_AM::add;
477 AddSub = ARM_AM::sub;
480 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
488 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
493 bool ARMDAGToDAGISel::SelectAddrMode6(SDValue Op, SDValue N,
494 SDValue &Addr, SDValue &Update,
495 SDValue &Opc, SDValue &Align) {
497 // Default to no writeback.
498 Update = CurDAG->getRegister(0, MVT::i32);
499 Opc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(false), MVT::i32);
500 // Default to no alignment.
501 Align = CurDAG->getTargetConstant(0, MVT::i32);
505 bool ARMDAGToDAGISel::SelectAddrModePC(SDValue Op, SDValue N,
506 SDValue &Offset, SDValue &Label) {
507 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
508 Offset = N.getOperand(0);
509 SDValue N1 = N.getOperand(1);
510 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
517 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue Op, SDValue N,
518 SDValue &Base, SDValue &Offset){
519 // FIXME dl should come from the parent load or store, not the address
520 DebugLoc dl = Op.getDebugLoc();
521 if (N.getOpcode() != ISD::ADD) {
522 ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
523 if (!NC || NC->getZExtValue() != 0)
530 Base = N.getOperand(0);
531 Offset = N.getOperand(1);
536 ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDValue Op, SDValue N,
537 unsigned Scale, SDValue &Base,
538 SDValue &OffImm, SDValue &Offset) {
540 SDValue TmpBase, TmpOffImm;
541 if (SelectThumbAddrModeSP(Op, N, TmpBase, TmpOffImm))
542 return false; // We want to select tLDRspi / tSTRspi instead.
543 if (N.getOpcode() == ARMISD::Wrapper &&
544 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
545 return false; // We want to select tLDRpci instead.
548 if (N.getOpcode() != ISD::ADD) {
549 Base = (N.getOpcode() == ARMISD::Wrapper) ? N.getOperand(0) : N;
550 Offset = CurDAG->getRegister(0, MVT::i32);
551 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
555 // Thumb does not have [sp, r] address mode.
556 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
557 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
558 if ((LHSR && LHSR->getReg() == ARM::SP) ||
559 (RHSR && RHSR->getReg() == ARM::SP)) {
561 Offset = CurDAG->getRegister(0, MVT::i32);
562 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
566 // If the RHS is + imm5 * scale, fold into addr mode.
567 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
568 int RHSC = (int)RHS->getZExtValue();
569 if ((RHSC & (Scale-1)) == 0) { // The constant is implicitly multiplied.
571 if (RHSC >= 0 && RHSC < 32) {
572 Base = N.getOperand(0);
573 Offset = CurDAG->getRegister(0, MVT::i32);
574 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
580 Base = N.getOperand(0);
581 Offset = N.getOperand(1);
582 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
586 bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDValue Op, SDValue N,
587 SDValue &Base, SDValue &OffImm,
589 return SelectThumbAddrModeRI5(Op, N, 1, Base, OffImm, Offset);
592 bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDValue Op, SDValue N,
593 SDValue &Base, SDValue &OffImm,
595 return SelectThumbAddrModeRI5(Op, N, 2, Base, OffImm, Offset);
598 bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDValue Op, SDValue N,
599 SDValue &Base, SDValue &OffImm,
601 return SelectThumbAddrModeRI5(Op, N, 4, Base, OffImm, Offset);
604 bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue Op, SDValue N,
605 SDValue &Base, SDValue &OffImm) {
606 if (N.getOpcode() == ISD::FrameIndex) {
607 int FI = cast<FrameIndexSDNode>(N)->getIndex();
608 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
609 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
613 if (N.getOpcode() != ISD::ADD)
616 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
617 if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
618 (LHSR && LHSR->getReg() == ARM::SP)) {
619 // If the RHS is + imm8 * scale, fold into addr mode.
620 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
621 int RHSC = (int)RHS->getZExtValue();
622 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied.
624 if (RHSC >= 0 && RHSC < 256) {
625 Base = N.getOperand(0);
626 if (Base.getOpcode() == ISD::FrameIndex) {
627 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
628 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
630 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
640 bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue Op, SDValue N,
643 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
645 // Don't match base register only case. That is matched to a separate
646 // lower complexity pattern with explicit register operand.
647 if (ShOpcVal == ARM_AM::no_shift) return false;
649 BaseReg = N.getOperand(0);
650 unsigned ShImmVal = 0;
651 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
652 ShImmVal = RHS->getZExtValue() & 31;
653 Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
660 bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue Op, SDValue N,
661 SDValue &Base, SDValue &OffImm) {
662 // Match simple R + imm12 operands.
665 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
666 if (N.getOpcode() == ISD::FrameIndex) {
667 // Match frame index...
668 int FI = cast<FrameIndexSDNode>(N)->getIndex();
669 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
670 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
672 } else if (N.getOpcode() == ARMISD::Wrapper) {
673 Base = N.getOperand(0);
674 if (Base.getOpcode() == ISD::TargetConstantPool)
675 return false; // We want to select t2LDRpci instead.
678 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
682 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
683 if (SelectT2AddrModeImm8(Op, N, Base, OffImm))
684 // Let t2LDRi8 handle (R - imm8).
687 int RHSC = (int)RHS->getZExtValue();
688 if (N.getOpcode() == ISD::SUB)
691 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
692 Base = N.getOperand(0);
693 if (Base.getOpcode() == ISD::FrameIndex) {
694 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
695 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
697 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
704 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
708 bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue Op, SDValue N,
709 SDValue &Base, SDValue &OffImm) {
710 // Match simple R - imm8 operands.
711 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::SUB) {
712 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
713 int RHSC = (int)RHS->getSExtValue();
714 if (N.getOpcode() == ISD::SUB)
717 if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative)
718 Base = N.getOperand(0);
719 if (Base.getOpcode() == ISD::FrameIndex) {
720 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
721 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
723 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
732 bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDValue Op, SDValue N,
734 unsigned Opcode = Op.getOpcode();
735 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
736 ? cast<LoadSDNode>(Op)->getAddressingMode()
737 : cast<StoreSDNode>(Op)->getAddressingMode();
738 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N)) {
739 int RHSC = (int)RHS->getZExtValue();
740 if (RHSC >= 0 && RHSC < 0x100) { // 8 bits.
741 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
742 ? CurDAG->getTargetConstant(RHSC, MVT::i32)
743 : CurDAG->getTargetConstant(-RHSC, MVT::i32);
751 bool ARMDAGToDAGISel::SelectT2AddrModeImm8s4(SDValue Op, SDValue N,
752 SDValue &Base, SDValue &OffImm) {
753 if (N.getOpcode() == ISD::ADD) {
754 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
755 int RHSC = (int)RHS->getZExtValue();
756 if (((RHSC & 0x3) == 0) &&
757 ((RHSC >= 0 && RHSC < 0x400) || (RHSC < 0 && RHSC > -0x400))) { // 8 bits.
758 Base = N.getOperand(0);
759 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
763 } else if (N.getOpcode() == ISD::SUB) {
764 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
765 int RHSC = (int)RHS->getZExtValue();
766 if (((RHSC & 0x3) == 0) && (RHSC >= 0 && RHSC < 0x400)) { // 8 bits.
767 Base = N.getOperand(0);
768 OffImm = CurDAG->getTargetConstant(-RHSC, MVT::i32);
777 bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue Op, SDValue N,
779 SDValue &OffReg, SDValue &ShImm) {
780 // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.
781 if (N.getOpcode() != ISD::ADD)
784 // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8.
785 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
786 int RHSC = (int)RHS->getZExtValue();
787 if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned)
789 else if (RHSC < 0 && RHSC >= -255) // 8 bits
793 // Look for (R + R) or (R + (R << [1,2,3])).
795 Base = N.getOperand(0);
796 OffReg = N.getOperand(1);
798 // Swap if it is ((R << c) + R).
799 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg);
800 if (ShOpcVal != ARM_AM::lsl) {
801 ShOpcVal = ARM_AM::getShiftOpcForNode(Base);
802 if (ShOpcVal == ARM_AM::lsl)
803 std::swap(Base, OffReg);
806 if (ShOpcVal == ARM_AM::lsl) {
807 // Check to see if the RHS of the shift is a constant, if not, we can't fold
809 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
810 ShAmt = Sh->getZExtValue();
813 ShOpcVal = ARM_AM::no_shift;
815 OffReg = OffReg.getOperand(0);
817 ShOpcVal = ARM_AM::no_shift;
821 ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
826 //===--------------------------------------------------------------------===//
828 /// getAL - Returns a ARMCC::AL immediate node.
829 static inline SDValue getAL(SelectionDAG *CurDAG) {
830 return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
833 SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDValue Op) {
834 LoadSDNode *LD = cast<LoadSDNode>(Op);
835 ISD::MemIndexedMode AM = LD->getAddressingMode();
836 if (AM == ISD::UNINDEXED)
839 EVT LoadedVT = LD->getMemoryVT();
840 SDValue Offset, AMOpc;
841 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
844 if (LoadedVT == MVT::i32 &&
845 SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
846 Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST;
848 } else if (LoadedVT == MVT::i16 &&
849 SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
851 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
852 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
853 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
854 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
855 if (LD->getExtensionType() == ISD::SEXTLOAD) {
856 if (SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
858 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
861 if (SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
863 Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST;
869 SDValue Chain = LD->getChain();
870 SDValue Base = LD->getBasePtr();
871 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
872 CurDAG->getRegister(0, MVT::i32), Chain };
873 return CurDAG->getMachineNode(Opcode, Op.getDebugLoc(), MVT::i32, MVT::i32,
880 SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDValue Op) {
881 LoadSDNode *LD = cast<LoadSDNode>(Op);
882 ISD::MemIndexedMode AM = LD->getAddressingMode();
883 if (AM == ISD::UNINDEXED)
886 EVT LoadedVT = LD->getMemoryVT();
887 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
889 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
892 if (SelectT2AddrModeImm8Offset(Op, LD->getOffset(), Offset)) {
893 switch (LoadedVT.getSimpleVT().SimpleTy) {
895 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
899 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
901 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
906 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
908 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
917 SDValue Chain = LD->getChain();
918 SDValue Base = LD->getBasePtr();
919 SDValue Ops[]= { Base, Offset, getAL(CurDAG),
920 CurDAG->getRegister(0, MVT::i32), Chain };
921 return CurDAG->getMachineNode(Opcode, Op.getDebugLoc(), MVT::i32, MVT::i32,
928 SDNode *ARMDAGToDAGISel::SelectDYN_ALLOC(SDValue Op) {
929 SDNode *N = Op.getNode();
930 DebugLoc dl = N->getDebugLoc();
931 EVT VT = Op.getValueType();
932 SDValue Chain = Op.getOperand(0);
933 SDValue Size = Op.getOperand(1);
934 SDValue Align = Op.getOperand(2);
935 SDValue SP = CurDAG->getRegister(ARM::SP, MVT::i32);
936 int32_t AlignVal = cast<ConstantSDNode>(Align)->getSExtValue();
938 // We need to align the stack. Use Thumb1 tAND which is the only thumb
939 // instruction that can read and write SP. This matches to a pseudo
940 // instruction that has a chain to ensure the result is written back to
941 // the stack pointer.
942 SP = SDValue(CurDAG->getMachineNode(ARM::tANDsp, dl, VT, SP, Align), 0);
944 bool isC = isa<ConstantSDNode>(Size);
945 uint32_t C = isC ? cast<ConstantSDNode>(Size)->getZExtValue() : ~0UL;
946 // Handle the most common case for both Thumb1 and Thumb2:
947 // tSUBspi - immediate is between 0 ... 508 inclusive.
948 if (C <= 508 && ((C & 3) == 0))
949 // FIXME: tSUBspi encode scale 4 implicitly.
950 return CurDAG->SelectNodeTo(N, ARM::tSUBspi_, VT, MVT::Other, SP,
951 CurDAG->getTargetConstant(C/4, MVT::i32),
954 if (Subtarget->isThumb1Only()) {
955 // Use tADDspr since Thumb1 does not have a sub r, sp, r. ARMISelLowering
956 // should have negated the size operand already. FIXME: We can't insert
957 // new target independent node at this stage so we are forced to negate
958 // it earlier. Is there a better solution?
959 return CurDAG->SelectNodeTo(N, ARM::tADDspr_, VT, MVT::Other, SP, Size,
961 } else if (Subtarget->isThumb2()) {
962 if (isC && Predicate_t2_so_imm(Size.getNode())) {
964 SDValue Ops[] = { SP, CurDAG->getTargetConstant(C, MVT::i32), Chain };
965 return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPi_, VT, MVT::Other, Ops, 3);
966 } else if (isC && Predicate_imm0_4095(Size.getNode())) {
968 SDValue Ops[] = { SP, CurDAG->getTargetConstant(C, MVT::i32), Chain };
969 return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPi12_, VT, MVT::Other, Ops, 3);
972 SDValue Ops[] = { SP, Size,
973 getI32Imm(ARM_AM::getSORegOpc(ARM_AM::lsl,0)), Chain };
974 return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPs_, VT, MVT::Other, Ops, 4);
978 // FIXME: Add ADD / SUB sp instructions for ARM.
982 /// PairDRegs - Insert a pair of double registers into an implicit def to
983 /// form a quad register.
984 SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) {
985 DebugLoc dl = V0.getNode()->getDebugLoc();
987 SDValue(CurDAG->getMachineNode(TargetInstrInfo::IMPLICIT_DEF, dl, VT), 0);
988 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::DSUBREG_0, MVT::i32);
989 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::DSUBREG_1, MVT::i32);
990 SDNode *Pair = CurDAG->getMachineNode(TargetInstrInfo::INSERT_SUBREG, dl,
991 VT, Undef, V0, SubReg0);
992 return CurDAG->getMachineNode(TargetInstrInfo::INSERT_SUBREG, dl,
993 VT, SDValue(Pair, 0), V1, SubReg1);
996 /// GetNEONSubregVT - Given a type for a 128-bit NEON vector, return the type
997 /// for a 64-bit subregister of the vector.
998 static EVT GetNEONSubregVT(EVT VT) {
999 switch (VT.getSimpleVT().SimpleTy) {
1000 default: llvm_unreachable("unhandled NEON type");
1001 case MVT::v16i8: return MVT::v8i8;
1002 case MVT::v8i16: return MVT::v4i16;
1003 case MVT::v4f32: return MVT::v2f32;
1004 case MVT::v4i32: return MVT::v2i32;
1005 case MVT::v2i64: return MVT::v1i64;
1009 SDNode *ARMDAGToDAGISel::SelectVLD(SDValue Op, unsigned NumVecs,
1010 unsigned *DOpcodes, unsigned *QOpcodes0,
1011 unsigned *QOpcodes1) {
1012 assert(NumVecs >=2 && NumVecs <= 4 && "VLD NumVecs out-of-range");
1013 SDNode *N = Op.getNode();
1014 DebugLoc dl = N->getDebugLoc();
1016 SDValue MemAddr, MemUpdate, MemOpc, Align;
1017 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc, Align))
1020 SDValue Chain = N->getOperand(0);
1021 EVT VT = N->getValueType(0);
1022 bool is64BitVector = VT.is64BitVector();
1024 unsigned OpcodeIndex;
1025 switch (VT.getSimpleVT().SimpleTy) {
1026 default: llvm_unreachable("unhandled vld type");
1027 // Double-register operations:
1028 case MVT::v8i8: OpcodeIndex = 0; break;
1029 case MVT::v4i16: OpcodeIndex = 1; break;
1031 case MVT::v2i32: OpcodeIndex = 2; break;
1032 case MVT::v1i64: OpcodeIndex = 3; break;
1033 // Quad-register operations:
1034 case MVT::v16i8: OpcodeIndex = 0; break;
1035 case MVT::v8i16: OpcodeIndex = 1; break;
1037 case MVT::v4i32: OpcodeIndex = 2; break;
1040 if (is64BitVector) {
1041 unsigned Opc = DOpcodes[OpcodeIndex];
1042 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Align, Chain };
1043 std::vector<EVT> ResTys(NumVecs, VT);
1044 ResTys.push_back(MVT::Other);
1045 return CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 5);
1048 EVT RegVT = GetNEONSubregVT(VT);
1050 // Quad registers are directly supported for VLD2,
1051 // loading 2 pairs of D regs.
1052 unsigned Opc = QOpcodes0[OpcodeIndex];
1053 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Align, Chain };
1054 std::vector<EVT> ResTys(4, VT);
1055 ResTys.push_back(MVT::Other);
1056 SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 5);
1057 Chain = SDValue(VLd, 4);
1059 // Combine the even and odd subregs to produce the result.
1060 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1061 SDNode *Q = PairDRegs(VT, SDValue(VLd, 2*Vec), SDValue(VLd, 2*Vec+1));
1062 ReplaceUses(SDValue(N, Vec), SDValue(Q, 0));
1065 // Otherwise, quad registers are loaded with two separate instructions,
1066 // where one loads the even registers and the other loads the odd registers.
1068 // Enable writeback to the address register.
1069 MemOpc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(true), MVT::i32);
1071 std::vector<EVT> ResTys(NumVecs, RegVT);
1072 ResTys.push_back(MemAddr.getValueType());
1073 ResTys.push_back(MVT::Other);
1075 // Load the even subregs.
1076 unsigned Opc = QOpcodes0[OpcodeIndex];
1077 const SDValue OpsA[] = { MemAddr, MemUpdate, MemOpc, Align, Chain };
1078 SDNode *VLdA = CurDAG->getMachineNode(Opc, dl, ResTys, OpsA, 5);
1079 Chain = SDValue(VLdA, NumVecs+1);
1081 // Load the odd subregs.
1082 Opc = QOpcodes1[OpcodeIndex];
1083 const SDValue OpsB[] = { SDValue(VLdA, NumVecs), MemUpdate, MemOpc,
1085 SDNode *VLdB = CurDAG->getMachineNode(Opc, dl, ResTys, OpsB, 5);
1086 Chain = SDValue(VLdB, NumVecs+1);
1088 // Combine the even and odd subregs to produce the result.
1089 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1090 SDNode *Q = PairDRegs(VT, SDValue(VLdA, Vec), SDValue(VLdB, Vec));
1091 ReplaceUses(SDValue(N, Vec), SDValue(Q, 0));
1094 ReplaceUses(SDValue(N, NumVecs), Chain);
1098 SDNode *ARMDAGToDAGISel::SelectVST(SDValue Op, unsigned NumVecs,
1099 unsigned *DOpcodes, unsigned *QOpcodes0,
1100 unsigned *QOpcodes1) {
1101 assert(NumVecs >=2 && NumVecs <= 4 && "VST NumVecs out-of-range");
1102 SDNode *N = Op.getNode();
1103 DebugLoc dl = N->getDebugLoc();
1105 SDValue MemAddr, MemUpdate, MemOpc, Align;
1106 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc, Align))
1109 SDValue Chain = N->getOperand(0);
1110 EVT VT = N->getOperand(3).getValueType();
1111 bool is64BitVector = VT.is64BitVector();
1113 unsigned OpcodeIndex;
1114 switch (VT.getSimpleVT().SimpleTy) {
1115 default: llvm_unreachable("unhandled vst type");
1116 // Double-register operations:
1117 case MVT::v8i8: OpcodeIndex = 0; break;
1118 case MVT::v4i16: OpcodeIndex = 1; break;
1120 case MVT::v2i32: OpcodeIndex = 2; break;
1121 case MVT::v1i64: OpcodeIndex = 3; break;
1122 // Quad-register operations:
1123 case MVT::v16i8: OpcodeIndex = 0; break;
1124 case MVT::v8i16: OpcodeIndex = 1; break;
1126 case MVT::v4i32: OpcodeIndex = 2; break;
1129 SmallVector<SDValue, 8> Ops;
1130 Ops.push_back(MemAddr);
1131 Ops.push_back(MemUpdate);
1132 Ops.push_back(MemOpc);
1133 Ops.push_back(Align);
1135 if (is64BitVector) {
1136 unsigned Opc = DOpcodes[OpcodeIndex];
1137 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1138 Ops.push_back(N->getOperand(Vec+3));
1139 Ops.push_back(Chain);
1140 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), NumVecs+5);
1143 EVT RegVT = GetNEONSubregVT(VT);
1145 // Quad registers are directly supported for VST2,
1146 // storing 2 pairs of D regs.
1147 unsigned Opc = QOpcodes0[OpcodeIndex];
1148 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1149 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
1150 N->getOperand(Vec+3)));
1151 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
1152 N->getOperand(Vec+3)));
1154 Ops.push_back(Chain);
1155 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 9);
1158 // Otherwise, quad registers are stored with two separate instructions,
1159 // where one stores the even registers and the other stores the odd registers.
1161 // Enable writeback to the address register.
1162 MemOpc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(true), MVT::i32);
1164 // Store the even subregs.
1165 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1166 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
1167 N->getOperand(Vec+3)));
1168 Ops.push_back(Chain);
1169 unsigned Opc = QOpcodes0[OpcodeIndex];
1170 SDNode *VStA = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
1171 MVT::Other, Ops.data(), NumVecs+5);
1172 Chain = SDValue(VStA, 1);
1174 // Store the odd subregs.
1175 Ops[0] = SDValue(VStA, 0); // MemAddr
1176 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1177 Ops[Vec+4] = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
1178 N->getOperand(Vec+3));
1179 Ops[NumVecs+4] = Chain;
1180 Opc = QOpcodes1[OpcodeIndex];
1181 SDNode *VStB = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
1182 MVT::Other, Ops.data(), NumVecs+5);
1183 Chain = SDValue(VStB, 1);
1184 ReplaceUses(SDValue(N, 0), Chain);
1188 SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDValue Op, bool IsLoad,
1189 unsigned NumVecs, unsigned *DOpcodes,
1190 unsigned *QOpcodes0,
1191 unsigned *QOpcodes1) {
1192 assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
1193 SDNode *N = Op.getNode();
1194 DebugLoc dl = N->getDebugLoc();
1196 SDValue MemAddr, MemUpdate, MemOpc, Align;
1197 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc, Align))
1200 SDValue Chain = N->getOperand(0);
1202 cast<ConstantSDNode>(N->getOperand(NumVecs+3))->getZExtValue();
1203 EVT VT = IsLoad ? N->getValueType(0) : N->getOperand(3).getValueType();
1204 bool is64BitVector = VT.is64BitVector();
1206 // Quad registers are handled by load/store of subregs. Find the subreg info.
1207 unsigned NumElts = 0;
1210 if (!is64BitVector) {
1211 RegVT = GetNEONSubregVT(VT);
1212 NumElts = RegVT.getVectorNumElements();
1213 SubregIdx = (Lane < NumElts) ? ARM::DSUBREG_0 : ARM::DSUBREG_1;
1216 unsigned OpcodeIndex;
1217 switch (VT.getSimpleVT().SimpleTy) {
1218 default: llvm_unreachable("unhandled vld/vst lane type");
1219 // Double-register operations:
1220 case MVT::v8i8: OpcodeIndex = 0; break;
1221 case MVT::v4i16: OpcodeIndex = 1; break;
1223 case MVT::v2i32: OpcodeIndex = 2; break;
1224 // Quad-register operations:
1225 case MVT::v8i16: OpcodeIndex = 0; break;
1227 case MVT::v4i32: OpcodeIndex = 1; break;
1230 SmallVector<SDValue, 9> Ops;
1231 Ops.push_back(MemAddr);
1232 Ops.push_back(MemUpdate);
1233 Ops.push_back(MemOpc);
1234 Ops.push_back(Align);
1237 if (is64BitVector) {
1238 Opc = DOpcodes[OpcodeIndex];
1239 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1240 Ops.push_back(N->getOperand(Vec+3));
1242 // Check if this is loading the even or odd subreg of a Q register.
1243 if (Lane < NumElts) {
1244 Opc = QOpcodes0[OpcodeIndex];
1247 Opc = QOpcodes1[OpcodeIndex];
1249 // Extract the subregs of the input vector.
1250 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1251 Ops.push_back(CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
1252 N->getOperand(Vec+3)));
1254 Ops.push_back(getI32Imm(Lane));
1255 Ops.push_back(Chain);
1258 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), NumVecs+5);
1260 std::vector<EVT> ResTys(NumVecs, RegVT);
1261 ResTys.push_back(MVT::Other);
1263 CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), NumVecs+5);
1264 // For a 64-bit vector load to D registers, nothing more needs to be done.
1268 // For 128-bit vectors, take the 64-bit results of the load and insert them
1269 // as subregs into the result.
1270 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1271 SDValue QuadVec = CurDAG->getTargetInsertSubreg(SubregIdx, dl, VT,
1272 N->getOperand(Vec+3),
1273 SDValue(VLdLn, Vec));
1274 ReplaceUses(SDValue(N, Vec), QuadVec);
1277 Chain = SDValue(VLdLn, NumVecs);
1278 ReplaceUses(SDValue(N, NumVecs), Chain);
1282 SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDValue Op,
1284 if (!Subtarget->hasV6T2Ops())
1287 unsigned Shl_imm = 0;
1288 if (isOpcWithIntImmediate(Op.getOperand(0).getNode(), ISD::SHL, Shl_imm)){
1289 assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!");
1290 unsigned Srl_imm = 0;
1291 if (isInt32Immediate(Op.getOperand(1), Srl_imm)) {
1292 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
1293 unsigned Width = 32 - Srl_imm;
1294 int LSB = Srl_imm - Shl_imm;
1297 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1298 SDValue Ops[] = { Op.getOperand(0).getOperand(0),
1299 CurDAG->getTargetConstant(LSB, MVT::i32),
1300 CurDAG->getTargetConstant(Width, MVT::i32),
1301 getAL(CurDAG), Reg0 };
1302 return CurDAG->SelectNodeTo(Op.getNode(), Opc, MVT::i32, Ops, 5);
1308 SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDValue Op) {
1309 EVT VT = Op.getValueType();
1310 SDValue N0 = Op.getOperand(0);
1311 SDValue N1 = Op.getOperand(1);
1312 SDValue N2 = Op.getOperand(2);
1313 SDValue N3 = Op.getOperand(3);
1314 SDValue InFlag = Op.getOperand(4);
1315 assert(N2.getOpcode() == ISD::Constant);
1316 assert(N3.getOpcode() == ISD::Register);
1318 if (!Subtarget->isThumb1Only() && VT == MVT::i32) {
1319 // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1320 // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1321 // Pattern complexity = 18 cost = 1 size = 0
1325 if (Subtarget->isThumb()) {
1326 if (SelectT2ShifterOperandReg(Op, N1, CPTmp0, CPTmp1)) {
1327 unsigned SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue();
1328 unsigned SOShOp = ARM_AM::getSORegShOp(SOVal);
1331 case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break;
1332 case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break;
1333 case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break;
1334 case ARM_AM::ror: Opc = ARM::t2MOVCCror; break;
1336 llvm_unreachable("Unknown so_reg opcode!");
1340 CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32);
1341 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1342 cast<ConstantSDNode>(N2)->getZExtValue()),
1344 SDValue Ops[] = { N0, CPTmp0, SOShImm, Tmp2, N3, InFlag };
1345 return CurDAG->SelectNodeTo(Op.getNode(), Opc, MVT::i32,Ops, 6);
1348 if (SelectShifterOperandReg(Op, N1, CPTmp0, CPTmp1, CPTmp2)) {
1349 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1350 cast<ConstantSDNode>(N2)->getZExtValue()),
1352 SDValue Ops[] = { N0, CPTmp0, CPTmp1, CPTmp2, Tmp2, N3, InFlag };
1353 return CurDAG->SelectNodeTo(Op.getNode(),
1354 ARM::MOVCCs, MVT::i32, Ops, 7);
1358 // Pattern: (ARMcmov:i32 GPR:i32:$false,
1359 // (imm:i32)<<P:Predicate_so_imm>>:$true,
1361 // Emits: (MOVCCi:i32 GPR:i32:$false,
1362 // (so_imm:i32 (imm:i32):$true), (imm:i32):$cc)
1363 // Pattern complexity = 10 cost = 1 size = 0
1364 if (N3.getOpcode() == ISD::Constant) {
1365 if (Subtarget->isThumb()) {
1366 if (Predicate_t2_so_imm(N3.getNode())) {
1367 SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
1368 cast<ConstantSDNode>(N1)->getZExtValue()),
1370 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1371 cast<ConstantSDNode>(N2)->getZExtValue()),
1373 SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
1374 return CurDAG->SelectNodeTo(Op.getNode(),
1375 ARM::t2MOVCCi, MVT::i32, Ops, 5);
1378 if (Predicate_so_imm(N3.getNode())) {
1379 SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
1380 cast<ConstantSDNode>(N1)->getZExtValue()),
1382 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1383 cast<ConstantSDNode>(N2)->getZExtValue()),
1385 SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
1386 return CurDAG->SelectNodeTo(Op.getNode(),
1387 ARM::MOVCCi, MVT::i32, Ops, 5);
1393 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1394 // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1395 // Pattern complexity = 6 cost = 1 size = 0
1397 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1398 // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1399 // Pattern complexity = 6 cost = 11 size = 0
1401 // Also FCPYScc and FCPYDcc.
1402 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1403 cast<ConstantSDNode>(N2)->getZExtValue()),
1405 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
1407 switch (VT.getSimpleVT().SimpleTy) {
1408 default: assert(false && "Illegal conditional move type!");
1411 Opc = Subtarget->isThumb()
1412 ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo)
1422 return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
1425 SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
1426 SDNode *N = Op.getNode();
1427 DebugLoc dl = N->getDebugLoc();
1429 if (N->isMachineOpcode())
1430 return NULL; // Already selected.
1432 switch (N->getOpcode()) {
1434 case ISD::Constant: {
1435 unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
1437 if (Subtarget->hasThumb2())
1438 // Thumb2-aware targets have the MOVT instruction, so all immediates can
1439 // be done with MOV + MOVT, at worst.
1442 if (Subtarget->isThumb()) {
1443 UseCP = (Val > 255 && // MOV
1444 ~Val > 255 && // MOV + MVN
1445 !ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL
1447 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
1448 ARM_AM::getSOImmVal(~Val) == -1 && // MVN
1449 !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs.
1454 CurDAG->getTargetConstantPool(ConstantInt::get(
1455 Type::getInt32Ty(*CurDAG->getContext()), Val),
1456 TLI.getPointerTy());
1459 if (Subtarget->isThumb1Only()) {
1460 SDValue Pred = CurDAG->getTargetConstant(0xEULL, MVT::i32);
1461 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
1462 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
1463 ResNode = CurDAG->getMachineNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other,
1468 CurDAG->getRegister(0, MVT::i32),
1469 CurDAG->getTargetConstant(0, MVT::i32),
1471 CurDAG->getRegister(0, MVT::i32),
1472 CurDAG->getEntryNode()
1474 ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
1477 ReplaceUses(Op, SDValue(ResNode, 0));
1481 // Other cases are autogenerated.
1484 case ISD::FrameIndex: {
1485 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
1486 int FI = cast<FrameIndexSDNode>(N)->getIndex();
1487 SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1488 if (Subtarget->isThumb1Only()) {
1489 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
1490 CurDAG->getTargetConstant(0, MVT::i32));
1492 unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
1493 ARM::t2ADDri : ARM::ADDri);
1494 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
1495 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1496 CurDAG->getRegister(0, MVT::i32) };
1497 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1500 case ARMISD::DYN_ALLOC:
1501 return SelectDYN_ALLOC(Op);
1503 if (SDNode *I = SelectV6T2BitfieldExtractOp(Op,
1504 Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX))
1508 if (SDNode *I = SelectV6T2BitfieldExtractOp(Op,
1509 Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX))
1513 if (Subtarget->isThumb1Only())
1515 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1516 unsigned RHSV = C->getZExtValue();
1518 if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
1519 unsigned ShImm = Log2_32(RHSV-1);
1522 SDValue V = Op.getOperand(0);
1523 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
1524 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
1525 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1526 if (Subtarget->isThumb()) {
1527 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1528 return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
1530 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1531 return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7);
1534 if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
1535 unsigned ShImm = Log2_32(RHSV+1);
1538 SDValue V = Op.getOperand(0);
1539 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
1540 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
1541 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1542 if (Subtarget->isThumb()) {
1543 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0 };
1544 return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 5);
1546 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1547 return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7);
1553 // (and (or x, c2), c1) and top 16-bits of c1 and c2 match, lower 16-bits
1554 // of c1 are 0xffff, and lower 16-bit of c2 are 0. That is, the top 16-bits
1555 // are entirely contributed by c2 and lower 16-bits are entirely contributed
1556 // by x. That's equal to (or (and x, 0xffff), (and c1, 0xffff0000)).
1557 // Select it to: "movt x, ((c1 & 0xffff) >> 16)
1558 EVT VT = Op.getValueType();
1561 unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2())
1563 : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0);
1566 SDValue N0 = Op.getOperand(0), N1 = Op.getOperand(1);
1567 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1570 if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) {
1571 SDValue N2 = N0.getOperand(1);
1572 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1575 unsigned N1CVal = N1C->getZExtValue();
1576 unsigned N2CVal = N2C->getZExtValue();
1577 if ((N1CVal & 0xffff0000U) == (N2CVal & 0xffff0000U) &&
1578 (N1CVal & 0xffffU) == 0xffffU &&
1579 (N2CVal & 0xffffU) == 0x0U) {
1580 SDValue Imm16 = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16,
1582 SDValue Ops[] = { N0.getOperand(0), Imm16,
1583 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
1584 return CurDAG->getMachineNode(Opc, dl, VT, Ops, 4);
1589 case ARMISD::VMOVRRD:
1590 return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32,
1591 Op.getOperand(0), getAL(CurDAG),
1592 CurDAG->getRegister(0, MVT::i32));
1593 case ISD::UMUL_LOHI: {
1594 if (Subtarget->isThumb1Only())
1596 if (Subtarget->isThumb()) {
1597 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
1598 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1599 CurDAG->getRegister(0, MVT::i32) };
1600 return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32, Ops,4);
1602 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
1603 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1604 CurDAG->getRegister(0, MVT::i32) };
1605 return CurDAG->getMachineNode(ARM::UMULL, dl, MVT::i32, MVT::i32, Ops, 5);
1608 case ISD::SMUL_LOHI: {
1609 if (Subtarget->isThumb1Only())
1611 if (Subtarget->isThumb()) {
1612 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
1613 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
1614 return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32, Ops,4);
1616 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
1617 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1618 CurDAG->getRegister(0, MVT::i32) };
1619 return CurDAG->getMachineNode(ARM::SMULL, dl, MVT::i32, MVT::i32, Ops, 5);
1623 SDNode *ResNode = 0;
1624 if (Subtarget->isThumb() && Subtarget->hasThumb2())
1625 ResNode = SelectT2IndexedLoad(Op);
1627 ResNode = SelectARMIndexedLoad(Op);
1630 // Other cases are autogenerated.
1633 case ARMISD::BRCOND: {
1634 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1635 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
1636 // Pattern complexity = 6 cost = 1 size = 0
1638 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1639 // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
1640 // Pattern complexity = 6 cost = 1 size = 0
1642 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1643 // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
1644 // Pattern complexity = 6 cost = 1 size = 0
1646 unsigned Opc = Subtarget->isThumb() ?
1647 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
1648 SDValue Chain = Op.getOperand(0);
1649 SDValue N1 = Op.getOperand(1);
1650 SDValue N2 = Op.getOperand(2);
1651 SDValue N3 = Op.getOperand(3);
1652 SDValue InFlag = Op.getOperand(4);
1653 assert(N1.getOpcode() == ISD::BasicBlock);
1654 assert(N2.getOpcode() == ISD::Constant);
1655 assert(N3.getOpcode() == ISD::Register);
1657 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1658 cast<ConstantSDNode>(N2)->getZExtValue()),
1660 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
1661 SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,
1663 Chain = SDValue(ResNode, 0);
1664 if (Op.getNode()->getNumValues() == 2) {
1665 InFlag = SDValue(ResNode, 1);
1666 ReplaceUses(SDValue(Op.getNode(), 1), InFlag);
1668 ReplaceUses(SDValue(Op.getNode(), 0),
1669 SDValue(Chain.getNode(), Chain.getResNo()));
1673 return SelectCMOVOp(Op);
1674 case ARMISD::CNEG: {
1675 EVT VT = Op.getValueType();
1676 SDValue N0 = Op.getOperand(0);
1677 SDValue N1 = Op.getOperand(1);
1678 SDValue N2 = Op.getOperand(2);
1679 SDValue N3 = Op.getOperand(3);
1680 SDValue InFlag = Op.getOperand(4);
1681 assert(N2.getOpcode() == ISD::Constant);
1682 assert(N3.getOpcode() == ISD::Register);
1684 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1685 cast<ConstantSDNode>(N2)->getZExtValue()),
1687 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
1689 switch (VT.getSimpleVT().SimpleTy) {
1690 default: assert(false && "Illegal conditional move type!");
1699 return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
1702 case ARMISD::VZIP: {
1704 EVT VT = N->getValueType(0);
1705 switch (VT.getSimpleVT().SimpleTy) {
1706 default: return NULL;
1707 case MVT::v8i8: Opc = ARM::VZIPd8; break;
1708 case MVT::v4i16: Opc = ARM::VZIPd16; break;
1710 case MVT::v2i32: Opc = ARM::VZIPd32; break;
1711 case MVT::v16i8: Opc = ARM::VZIPq8; break;
1712 case MVT::v8i16: Opc = ARM::VZIPq16; break;
1714 case MVT::v4i32: Opc = ARM::VZIPq32; break;
1716 return CurDAG->getMachineNode(Opc, dl, VT, VT,
1717 N->getOperand(0), N->getOperand(1));
1719 case ARMISD::VUZP: {
1721 EVT VT = N->getValueType(0);
1722 switch (VT.getSimpleVT().SimpleTy) {
1723 default: return NULL;
1724 case MVT::v8i8: Opc = ARM::VUZPd8; break;
1725 case MVT::v4i16: Opc = ARM::VUZPd16; break;
1727 case MVT::v2i32: Opc = ARM::VUZPd32; break;
1728 case MVT::v16i8: Opc = ARM::VUZPq8; break;
1729 case MVT::v8i16: Opc = ARM::VUZPq16; break;
1731 case MVT::v4i32: Opc = ARM::VUZPq32; break;
1733 return CurDAG->getMachineNode(Opc, dl, VT, VT,
1734 N->getOperand(0), N->getOperand(1));
1736 case ARMISD::VTRN: {
1738 EVT VT = N->getValueType(0);
1739 switch (VT.getSimpleVT().SimpleTy) {
1740 default: return NULL;
1741 case MVT::v8i8: Opc = ARM::VTRNd8; break;
1742 case MVT::v4i16: Opc = ARM::VTRNd16; break;
1744 case MVT::v2i32: Opc = ARM::VTRNd32; break;
1745 case MVT::v16i8: Opc = ARM::VTRNq8; break;
1746 case MVT::v8i16: Opc = ARM::VTRNq16; break;
1748 case MVT::v4i32: Opc = ARM::VTRNq32; break;
1750 return CurDAG->getMachineNode(Opc, dl, VT, VT,
1751 N->getOperand(0), N->getOperand(1));
1754 case ISD::INTRINSIC_VOID:
1755 case ISD::INTRINSIC_W_CHAIN: {
1756 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
1761 case Intrinsic::arm_neon_vld2: {
1762 unsigned DOpcodes[] = { ARM::VLD2d8, ARM::VLD2d16,
1763 ARM::VLD2d32, ARM::VLD2d64 };
1764 unsigned QOpcodes[] = { ARM::VLD2q8, ARM::VLD2q16, ARM::VLD2q32 };
1765 return SelectVLD(Op, 2, DOpcodes, QOpcodes, 0);
1768 case Intrinsic::arm_neon_vld3: {
1769 unsigned DOpcodes[] = { ARM::VLD3d8, ARM::VLD3d16,
1770 ARM::VLD3d32, ARM::VLD3d64 };
1771 unsigned QOpcodes0[] = { ARM::VLD3q8a, ARM::VLD3q16a, ARM::VLD3q32a };
1772 unsigned QOpcodes1[] = { ARM::VLD3q8b, ARM::VLD3q16b, ARM::VLD3q32b };
1773 return SelectVLD(Op, 3, DOpcodes, QOpcodes0, QOpcodes1);
1776 case Intrinsic::arm_neon_vld4: {
1777 unsigned DOpcodes[] = { ARM::VLD4d8, ARM::VLD4d16,
1778 ARM::VLD4d32, ARM::VLD4d64 };
1779 unsigned QOpcodes0[] = { ARM::VLD4q8a, ARM::VLD4q16a, ARM::VLD4q32a };
1780 unsigned QOpcodes1[] = { ARM::VLD4q8b, ARM::VLD4q16b, ARM::VLD4q32b };
1781 return SelectVLD(Op, 4, DOpcodes, QOpcodes0, QOpcodes1);
1784 case Intrinsic::arm_neon_vld2lane: {
1785 unsigned DOpcodes[] = { ARM::VLD2LNd8, ARM::VLD2LNd16, ARM::VLD2LNd32 };
1786 unsigned QOpcodes0[] = { ARM::VLD2LNq16a, ARM::VLD2LNq32a };
1787 unsigned QOpcodes1[] = { ARM::VLD2LNq16b, ARM::VLD2LNq32b };
1788 return SelectVLDSTLane(Op, true, 2, DOpcodes, QOpcodes0, QOpcodes1);
1791 case Intrinsic::arm_neon_vld3lane: {
1792 unsigned DOpcodes[] = { ARM::VLD3LNd8, ARM::VLD3LNd16, ARM::VLD3LNd32 };
1793 unsigned QOpcodes0[] = { ARM::VLD3LNq16a, ARM::VLD3LNq32a };
1794 unsigned QOpcodes1[] = { ARM::VLD3LNq16b, ARM::VLD3LNq32b };
1795 return SelectVLDSTLane(Op, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
1798 case Intrinsic::arm_neon_vld4lane: {
1799 unsigned DOpcodes[] = { ARM::VLD4LNd8, ARM::VLD4LNd16, ARM::VLD4LNd32 };
1800 unsigned QOpcodes0[] = { ARM::VLD4LNq16a, ARM::VLD4LNq32a };
1801 unsigned QOpcodes1[] = { ARM::VLD4LNq16b, ARM::VLD4LNq32b };
1802 return SelectVLDSTLane(Op, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
1805 case Intrinsic::arm_neon_vst2: {
1806 unsigned DOpcodes[] = { ARM::VST2d8, ARM::VST2d16,
1807 ARM::VST2d32, ARM::VST2d64 };
1808 unsigned QOpcodes[] = { ARM::VST2q8, ARM::VST2q16, ARM::VST2q32 };
1809 return SelectVST(Op, 2, DOpcodes, QOpcodes, 0);
1812 case Intrinsic::arm_neon_vst3: {
1813 unsigned DOpcodes[] = { ARM::VST3d8, ARM::VST3d16,
1814 ARM::VST3d32, ARM::VST3d64 };
1815 unsigned QOpcodes0[] = { ARM::VST3q8a, ARM::VST3q16a, ARM::VST3q32a };
1816 unsigned QOpcodes1[] = { ARM::VST3q8b, ARM::VST3q16b, ARM::VST3q32b };
1817 return SelectVST(Op, 3, DOpcodes, QOpcodes0, QOpcodes1);
1820 case Intrinsic::arm_neon_vst4: {
1821 unsigned DOpcodes[] = { ARM::VST4d8, ARM::VST4d16,
1822 ARM::VST4d32, ARM::VST4d64 };
1823 unsigned QOpcodes0[] = { ARM::VST4q8a, ARM::VST4q16a, ARM::VST4q32a };
1824 unsigned QOpcodes1[] = { ARM::VST4q8b, ARM::VST4q16b, ARM::VST4q32b };
1825 return SelectVST(Op, 4, DOpcodes, QOpcodes0, QOpcodes1);
1828 case Intrinsic::arm_neon_vst2lane: {
1829 unsigned DOpcodes[] = { ARM::VST2LNd8, ARM::VST2LNd16, ARM::VST2LNd32 };
1830 unsigned QOpcodes0[] = { ARM::VST2LNq16a, ARM::VST2LNq32a };
1831 unsigned QOpcodes1[] = { ARM::VST2LNq16b, ARM::VST2LNq32b };
1832 return SelectVLDSTLane(Op, false, 2, DOpcodes, QOpcodes0, QOpcodes1);
1835 case Intrinsic::arm_neon_vst3lane: {
1836 unsigned DOpcodes[] = { ARM::VST3LNd8, ARM::VST3LNd16, ARM::VST3LNd32 };
1837 unsigned QOpcodes0[] = { ARM::VST3LNq16a, ARM::VST3LNq32a };
1838 unsigned QOpcodes1[] = { ARM::VST3LNq16b, ARM::VST3LNq32b };
1839 return SelectVLDSTLane(Op, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
1842 case Intrinsic::arm_neon_vst4lane: {
1843 unsigned DOpcodes[] = { ARM::VST4LNd8, ARM::VST4LNd16, ARM::VST4LNd32 };
1844 unsigned QOpcodes0[] = { ARM::VST4LNq16a, ARM::VST4LNq32a };
1845 unsigned QOpcodes1[] = { ARM::VST4LNq16b, ARM::VST4LNq32b };
1846 return SelectVLDSTLane(Op, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
1852 return SelectCode(Op);
1855 bool ARMDAGToDAGISel::
1856 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
1857 std::vector<SDValue> &OutOps) {
1858 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
1859 // Require the address to be in a register. That is safe for all ARM
1860 // variants and it is hard to do anything much smarter without knowing
1861 // how the operand is used.
1862 OutOps.push_back(Op);
1866 /// createARMISelDag - This pass converts a legalized DAG into a
1867 /// ARM-specific DAG, ready for instruction scheduling.
1869 FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
1870 CodeGenOpt::Level OptLevel) {
1871 return new ARMDAGToDAGISel(TM, OptLevel);