1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMISelLowering.h"
17 #include "ARMTargetMachine.h"
18 #include "llvm/CallingConv.h"
19 #include "llvm/Constants.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/LLVMContext.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CodeGen/SelectionDAGISel.h"
29 #include "llvm/Target/TargetLowering.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Support/Compiler.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
38 //===--------------------------------------------------------------------===//
39 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
40 /// instructions for SelectionDAG operations.
43 class ARMDAGToDAGISel : public SelectionDAGISel {
44 ARMBaseTargetMachine &TM;
46 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
47 /// make the right decision when generating code for different targets.
48 const ARMSubtarget *Subtarget;
51 explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm,
52 CodeGenOpt::Level OptLevel)
53 : SelectionDAGISel(tm, OptLevel), TM(tm),
54 Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
57 virtual const char *getPassName() const {
58 return "ARM Instruction Selection";
61 /// getI32Imm - Return a target constant of type i32 with the specified
63 inline SDValue getI32Imm(unsigned Imm) {
64 return CurDAG->getTargetConstant(Imm, MVT::i32);
67 SDNode *Select(SDNode *N);
68 virtual void InstructionSelect();
69 bool SelectShifterOperandReg(SDNode *Op, SDValue N, SDValue &A,
70 SDValue &B, SDValue &C);
71 bool SelectAddrMode2(SDNode *Op, SDValue N, SDValue &Base,
72 SDValue &Offset, SDValue &Opc);
73 bool SelectAddrMode2Offset(SDNode *Op, SDValue N,
74 SDValue &Offset, SDValue &Opc);
75 bool SelectAddrMode3(SDNode *Op, SDValue N, SDValue &Base,
76 SDValue &Offset, SDValue &Opc);
77 bool SelectAddrMode3Offset(SDNode *Op, SDValue N,
78 SDValue &Offset, SDValue &Opc);
79 bool SelectAddrMode4(SDNode *Op, SDValue N, SDValue &Addr,
81 bool SelectAddrMode5(SDNode *Op, SDValue N, SDValue &Base,
83 bool SelectAddrMode6(SDNode *Op, SDValue N, SDValue &Addr, SDValue &Update,
84 SDValue &Opc, SDValue &Align);
86 bool SelectAddrModePC(SDNode *Op, SDValue N, SDValue &Offset,
89 bool SelectThumbAddrModeRR(SDNode *Op, SDValue N, SDValue &Base,
91 bool SelectThumbAddrModeRI5(SDNode *Op, SDValue N, unsigned Scale,
92 SDValue &Base, SDValue &OffImm,
94 bool SelectThumbAddrModeS1(SDNode *Op, SDValue N, SDValue &Base,
95 SDValue &OffImm, SDValue &Offset);
96 bool SelectThumbAddrModeS2(SDNode *Op, SDValue N, SDValue &Base,
97 SDValue &OffImm, SDValue &Offset);
98 bool SelectThumbAddrModeS4(SDNode *Op, SDValue N, SDValue &Base,
99 SDValue &OffImm, SDValue &Offset);
100 bool SelectThumbAddrModeSP(SDNode *Op, SDValue N, SDValue &Base,
103 bool SelectT2ShifterOperandReg(SDNode *Op, SDValue N,
104 SDValue &BaseReg, SDValue &Opc);
105 bool SelectT2AddrModeImm12(SDNode *Op, SDValue N, SDValue &Base,
107 bool SelectT2AddrModeImm8(SDNode *Op, SDValue N, SDValue &Base,
109 bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
111 bool SelectT2AddrModeImm8s4(SDNode *Op, SDValue N, SDValue &Base,
113 bool SelectT2AddrModeSoReg(SDNode *Op, SDValue N, SDValue &Base,
114 SDValue &OffReg, SDValue &ShImm);
116 // Include the pieces autogenerated from the target description.
117 #include "ARMGenDAGISel.inc"
120 /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
122 SDNode *SelectARMIndexedLoad(SDNode *N);
123 SDNode *SelectT2IndexedLoad(SDNode *N);
125 /// SelectDYN_ALLOC - Select dynamic alloc for Thumb.
126 SDNode *SelectDYN_ALLOC(SDNode *N);
128 /// SelectVLD - Select NEON load intrinsics. NumVecs should
129 /// be 2, 3 or 4. The opcode arrays specify the instructions used for
130 /// loads of D registers and even subregs and odd subregs of Q registers.
131 /// For NumVecs == 2, QOpcodes1 is not used.
132 SDNode *SelectVLD(SDNode *N, unsigned NumVecs, unsigned *DOpcodes,
133 unsigned *QOpcodes0, unsigned *QOpcodes1);
135 /// SelectVST - Select NEON store intrinsics. NumVecs should
136 /// be 2, 3 or 4. The opcode arrays specify the instructions used for
137 /// stores of D registers and even subregs and odd subregs of Q registers.
138 /// For NumVecs == 2, QOpcodes1 is not used.
139 SDNode *SelectVST(SDNode *N, unsigned NumVecs, unsigned *DOpcodes,
140 unsigned *QOpcodes0, unsigned *QOpcodes1);
142 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should
143 /// be 2, 3 or 4. The opcode arrays specify the instructions used for
144 /// load/store of D registers and even subregs and odd subregs of Q registers.
145 SDNode *SelectVLDSTLane(SDNode *N, bool IsLoad, unsigned NumVecs,
146 unsigned *DOpcodes, unsigned *QOpcodes0,
147 unsigned *QOpcodes1);
149 /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM.
150 SDNode *SelectV6T2BitfieldExtractOp(SDNode *N, unsigned Opc);
152 /// SelectCMOVOp - Select CMOV instructions for ARM.
153 SDNode *SelectCMOVOp(SDNode *N);
154 SDNode *SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
155 ARMCC::CondCodes CCVal, SDValue CCR,
157 SDNode *SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
158 ARMCC::CondCodes CCVal, SDValue CCR,
160 SDNode *SelectT2CMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
161 ARMCC::CondCodes CCVal, SDValue CCR,
163 SDNode *SelectARMCMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
164 ARMCC::CondCodes CCVal, SDValue CCR,
167 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
168 /// inline asm expressions.
169 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
171 std::vector<SDValue> &OutOps);
173 /// PairDRegs - Insert a pair of double registers into an implicit def to
174 /// form a quad register.
175 SDNode *PairDRegs(EVT VT, SDValue V0, SDValue V1);
179 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
180 /// operand. If so Imm will receive the 32-bit value.
181 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
182 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
183 Imm = cast<ConstantSDNode>(N)->getZExtValue();
189 // isInt32Immediate - This method tests to see if a constant operand.
190 // If so Imm will receive the 32 bit value.
191 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
192 return isInt32Immediate(N.getNode(), Imm);
195 // isOpcWithIntImmediate - This method tests to see if the node is a specific
196 // opcode and that it has a immediate integer right operand.
197 // If so Imm will receive the 32 bit value.
198 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
199 return N->getOpcode() == Opc &&
200 isInt32Immediate(N->getOperand(1).getNode(), Imm);
204 void ARMDAGToDAGISel::InstructionSelect() {
206 CurDAG->RemoveDeadNodes();
209 bool ARMDAGToDAGISel::SelectShifterOperandReg(SDNode *Op,
214 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
216 // Don't match base register only case. That is matched to a separate
217 // lower complexity pattern with explicit register operand.
218 if (ShOpcVal == ARM_AM::no_shift) return false;
220 BaseReg = N.getOperand(0);
221 unsigned ShImmVal = 0;
222 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
223 ShReg = CurDAG->getRegister(0, MVT::i32);
224 ShImmVal = RHS->getZExtValue() & 31;
226 ShReg = N.getOperand(1);
228 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
233 bool ARMDAGToDAGISel::SelectAddrMode2(SDNode *Op, SDValue N,
234 SDValue &Base, SDValue &Offset,
236 if (N.getOpcode() == ISD::MUL) {
237 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
238 // X * [3,5,9] -> X + X * [2,4,8] etc.
239 int RHSC = (int)RHS->getZExtValue();
242 ARM_AM::AddrOpc AddSub = ARM_AM::add;
244 AddSub = ARM_AM::sub;
247 if (isPowerOf2_32(RHSC)) {
248 unsigned ShAmt = Log2_32(RHSC);
249 Base = Offset = N.getOperand(0);
250 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
259 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
261 if (N.getOpcode() == ISD::FrameIndex) {
262 int FI = cast<FrameIndexSDNode>(N)->getIndex();
263 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
264 } else if (N.getOpcode() == ARMISD::Wrapper &&
265 !(Subtarget->useMovt() &&
266 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
267 Base = N.getOperand(0);
269 Offset = CurDAG->getRegister(0, MVT::i32);
270 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
276 // Match simple R +/- imm12 operands.
277 if (N.getOpcode() == ISD::ADD)
278 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
279 int RHSC = (int)RHS->getZExtValue();
280 if ((RHSC >= 0 && RHSC < 0x1000) ||
281 (RHSC < 0 && RHSC > -0x1000)) { // 12 bits.
282 Base = N.getOperand(0);
283 if (Base.getOpcode() == ISD::FrameIndex) {
284 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
285 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
287 Offset = CurDAG->getRegister(0, MVT::i32);
289 ARM_AM::AddrOpc AddSub = ARM_AM::add;
291 AddSub = ARM_AM::sub;
294 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
301 // Otherwise this is R +/- [possibly shifted] R.
302 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
303 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
306 Base = N.getOperand(0);
307 Offset = N.getOperand(1);
309 if (ShOpcVal != ARM_AM::no_shift) {
310 // Check to see if the RHS of the shift is a constant, if not, we can't fold
312 if (ConstantSDNode *Sh =
313 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
314 ShAmt = Sh->getZExtValue();
315 Offset = N.getOperand(1).getOperand(0);
317 ShOpcVal = ARM_AM::no_shift;
321 // Try matching (R shl C) + (R).
322 if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift) {
323 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
324 if (ShOpcVal != ARM_AM::no_shift) {
325 // Check to see if the RHS of the shift is a constant, if not, we can't
327 if (ConstantSDNode *Sh =
328 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
329 ShAmt = Sh->getZExtValue();
330 Offset = N.getOperand(0).getOperand(0);
331 Base = N.getOperand(1);
333 ShOpcVal = ARM_AM::no_shift;
338 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
343 bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDNode *Op, SDValue N,
344 SDValue &Offset, SDValue &Opc) {
345 unsigned Opcode = Op->getOpcode();
346 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
347 ? cast<LoadSDNode>(Op)->getAddressingMode()
348 : cast<StoreSDNode>(Op)->getAddressingMode();
349 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
350 ? ARM_AM::add : ARM_AM::sub;
351 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
352 int Val = (int)C->getZExtValue();
353 if (Val >= 0 && Val < 0x1000) { // 12 bits.
354 Offset = CurDAG->getRegister(0, MVT::i32);
355 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
363 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
365 if (ShOpcVal != ARM_AM::no_shift) {
366 // Check to see if the RHS of the shift is a constant, if not, we can't fold
368 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
369 ShAmt = Sh->getZExtValue();
370 Offset = N.getOperand(0);
372 ShOpcVal = ARM_AM::no_shift;
376 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
382 bool ARMDAGToDAGISel::SelectAddrMode3(SDNode *Op, SDValue N,
383 SDValue &Base, SDValue &Offset,
385 if (N.getOpcode() == ISD::SUB) {
386 // X - C is canonicalize to X + -C, no need to handle it here.
387 Base = N.getOperand(0);
388 Offset = N.getOperand(1);
389 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
393 if (N.getOpcode() != ISD::ADD) {
395 if (N.getOpcode() == ISD::FrameIndex) {
396 int FI = cast<FrameIndexSDNode>(N)->getIndex();
397 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
399 Offset = CurDAG->getRegister(0, MVT::i32);
400 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
404 // If the RHS is +/- imm8, fold into addr mode.
405 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
406 int RHSC = (int)RHS->getZExtValue();
407 if ((RHSC >= 0 && RHSC < 256) ||
408 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
409 Base = N.getOperand(0);
410 if (Base.getOpcode() == ISD::FrameIndex) {
411 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
412 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
414 Offset = CurDAG->getRegister(0, MVT::i32);
416 ARM_AM::AddrOpc AddSub = ARM_AM::add;
418 AddSub = ARM_AM::sub;
421 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
426 Base = N.getOperand(0);
427 Offset = N.getOperand(1);
428 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
432 bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N,
433 SDValue &Offset, SDValue &Opc) {
434 unsigned Opcode = Op->getOpcode();
435 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
436 ? cast<LoadSDNode>(Op)->getAddressingMode()
437 : cast<StoreSDNode>(Op)->getAddressingMode();
438 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
439 ? ARM_AM::add : ARM_AM::sub;
440 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
441 int Val = (int)C->getZExtValue();
442 if (Val >= 0 && Val < 256) {
443 Offset = CurDAG->getRegister(0, MVT::i32);
444 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
450 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
454 bool ARMDAGToDAGISel::SelectAddrMode4(SDNode *Op, SDValue N,
455 SDValue &Addr, SDValue &Mode) {
457 Mode = CurDAG->getTargetConstant(0, MVT::i32);
461 bool ARMDAGToDAGISel::SelectAddrMode5(SDNode *Op, SDValue N,
462 SDValue &Base, SDValue &Offset) {
463 if (N.getOpcode() != ISD::ADD) {
465 if (N.getOpcode() == ISD::FrameIndex) {
466 int FI = cast<FrameIndexSDNode>(N)->getIndex();
467 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
468 } else if (N.getOpcode() == ARMISD::Wrapper &&
469 !(Subtarget->useMovt() &&
470 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
471 Base = N.getOperand(0);
473 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
478 // If the RHS is +/- imm8, fold into addr mode.
479 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
480 int RHSC = (int)RHS->getZExtValue();
481 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied by 4.
483 if ((RHSC >= 0 && RHSC < 256) ||
484 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
485 Base = N.getOperand(0);
486 if (Base.getOpcode() == ISD::FrameIndex) {
487 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
488 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
491 ARM_AM::AddrOpc AddSub = ARM_AM::add;
493 AddSub = ARM_AM::sub;
496 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
504 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
509 bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Op, SDValue N,
510 SDValue &Addr, SDValue &Update,
511 SDValue &Opc, SDValue &Align) {
513 // Default to no writeback.
514 Update = CurDAG->getRegister(0, MVT::i32);
515 Opc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(false), MVT::i32);
516 // Default to no alignment.
517 Align = CurDAG->getTargetConstant(0, MVT::i32);
521 bool ARMDAGToDAGISel::SelectAddrModePC(SDNode *Op, SDValue N,
522 SDValue &Offset, SDValue &Label) {
523 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
524 Offset = N.getOperand(0);
525 SDValue N1 = N.getOperand(1);
526 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
533 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDNode *Op, SDValue N,
534 SDValue &Base, SDValue &Offset){
535 // FIXME dl should come from the parent load or store, not the address
536 DebugLoc dl = Op->getDebugLoc();
537 if (N.getOpcode() != ISD::ADD) {
538 ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
539 if (!NC || NC->getZExtValue() != 0)
546 Base = N.getOperand(0);
547 Offset = N.getOperand(1);
552 ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDNode *Op, SDValue N,
553 unsigned Scale, SDValue &Base,
554 SDValue &OffImm, SDValue &Offset) {
556 SDValue TmpBase, TmpOffImm;
557 if (SelectThumbAddrModeSP(Op, N, TmpBase, TmpOffImm))
558 return false; // We want to select tLDRspi / tSTRspi instead.
559 if (N.getOpcode() == ARMISD::Wrapper &&
560 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
561 return false; // We want to select tLDRpci instead.
564 if (N.getOpcode() != ISD::ADD) {
565 if (N.getOpcode() == ARMISD::Wrapper &&
566 !(Subtarget->useMovt() &&
567 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
568 Base = N.getOperand(0);
572 Offset = CurDAG->getRegister(0, MVT::i32);
573 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
577 // Thumb does not have [sp, r] address mode.
578 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
579 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
580 if ((LHSR && LHSR->getReg() == ARM::SP) ||
581 (RHSR && RHSR->getReg() == ARM::SP)) {
583 Offset = CurDAG->getRegister(0, MVT::i32);
584 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
588 // If the RHS is + imm5 * scale, fold into addr mode.
589 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
590 int RHSC = (int)RHS->getZExtValue();
591 if ((RHSC & (Scale-1)) == 0) { // The constant is implicitly multiplied.
593 if (RHSC >= 0 && RHSC < 32) {
594 Base = N.getOperand(0);
595 Offset = CurDAG->getRegister(0, MVT::i32);
596 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
602 Base = N.getOperand(0);
603 Offset = N.getOperand(1);
604 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
608 bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDNode *Op, SDValue N,
609 SDValue &Base, SDValue &OffImm,
611 return SelectThumbAddrModeRI5(Op, N, 1, Base, OffImm, Offset);
614 bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDNode *Op, SDValue N,
615 SDValue &Base, SDValue &OffImm,
617 return SelectThumbAddrModeRI5(Op, N, 2, Base, OffImm, Offset);
620 bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDNode *Op, SDValue N,
621 SDValue &Base, SDValue &OffImm,
623 return SelectThumbAddrModeRI5(Op, N, 4, Base, OffImm, Offset);
626 bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDNode *Op, SDValue N,
627 SDValue &Base, SDValue &OffImm) {
628 if (N.getOpcode() == ISD::FrameIndex) {
629 int FI = cast<FrameIndexSDNode>(N)->getIndex();
630 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
631 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
635 if (N.getOpcode() != ISD::ADD)
638 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
639 if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
640 (LHSR && LHSR->getReg() == ARM::SP)) {
641 // If the RHS is + imm8 * scale, fold into addr mode.
642 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
643 int RHSC = (int)RHS->getZExtValue();
644 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied.
646 if (RHSC >= 0 && RHSC < 256) {
647 Base = N.getOperand(0);
648 if (Base.getOpcode() == ISD::FrameIndex) {
649 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
650 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
652 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
662 bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDNode *Op, SDValue N,
665 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
667 // Don't match base register only case. That is matched to a separate
668 // lower complexity pattern with explicit register operand.
669 if (ShOpcVal == ARM_AM::no_shift) return false;
671 BaseReg = N.getOperand(0);
672 unsigned ShImmVal = 0;
673 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
674 ShImmVal = RHS->getZExtValue() & 31;
675 Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
682 bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDNode *Op, SDValue N,
683 SDValue &Base, SDValue &OffImm) {
684 // Match simple R + imm12 operands.
687 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
688 if (N.getOpcode() == ISD::FrameIndex) {
689 // Match frame index...
690 int FI = cast<FrameIndexSDNode>(N)->getIndex();
691 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
692 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
694 } else if (N.getOpcode() == ARMISD::Wrapper &&
695 !(Subtarget->useMovt() &&
696 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
697 Base = N.getOperand(0);
698 if (Base.getOpcode() == ISD::TargetConstantPool)
699 return false; // We want to select t2LDRpci instead.
702 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
706 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
707 if (SelectT2AddrModeImm8(Op, N, Base, OffImm))
708 // Let t2LDRi8 handle (R - imm8).
711 int RHSC = (int)RHS->getZExtValue();
712 if (N.getOpcode() == ISD::SUB)
715 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
716 Base = N.getOperand(0);
717 if (Base.getOpcode() == ISD::FrameIndex) {
718 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
719 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
721 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
728 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
732 bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDNode *Op, SDValue N,
733 SDValue &Base, SDValue &OffImm) {
734 // Match simple R - imm8 operands.
735 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::SUB) {
736 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
737 int RHSC = (int)RHS->getSExtValue();
738 if (N.getOpcode() == ISD::SUB)
741 if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative)
742 Base = N.getOperand(0);
743 if (Base.getOpcode() == ISD::FrameIndex) {
744 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
745 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
747 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
756 bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
758 unsigned Opcode = Op->getOpcode();
759 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
760 ? cast<LoadSDNode>(Op)->getAddressingMode()
761 : cast<StoreSDNode>(Op)->getAddressingMode();
762 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N)) {
763 int RHSC = (int)RHS->getZExtValue();
764 if (RHSC >= 0 && RHSC < 0x100) { // 8 bits.
765 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
766 ? CurDAG->getTargetConstant(RHSC, MVT::i32)
767 : CurDAG->getTargetConstant(-RHSC, MVT::i32);
775 bool ARMDAGToDAGISel::SelectT2AddrModeImm8s4(SDNode *Op, SDValue N,
776 SDValue &Base, SDValue &OffImm) {
777 if (N.getOpcode() == ISD::ADD) {
778 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
779 int RHSC = (int)RHS->getZExtValue();
780 if (((RHSC & 0x3) == 0) &&
781 ((RHSC >= 0 && RHSC < 0x400) || (RHSC < 0 && RHSC > -0x400))) { // 8 bits.
782 Base = N.getOperand(0);
783 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
787 } else if (N.getOpcode() == ISD::SUB) {
788 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
789 int RHSC = (int)RHS->getZExtValue();
790 if (((RHSC & 0x3) == 0) && (RHSC >= 0 && RHSC < 0x400)) { // 8 bits.
791 Base = N.getOperand(0);
792 OffImm = CurDAG->getTargetConstant(-RHSC, MVT::i32);
801 bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDNode *Op, SDValue N,
803 SDValue &OffReg, SDValue &ShImm) {
804 // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.
805 if (N.getOpcode() != ISD::ADD)
808 // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8.
809 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
810 int RHSC = (int)RHS->getZExtValue();
811 if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned)
813 else if (RHSC < 0 && RHSC >= -255) // 8 bits
817 // Look for (R + R) or (R + (R << [1,2,3])).
819 Base = N.getOperand(0);
820 OffReg = N.getOperand(1);
822 // Swap if it is ((R << c) + R).
823 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg);
824 if (ShOpcVal != ARM_AM::lsl) {
825 ShOpcVal = ARM_AM::getShiftOpcForNode(Base);
826 if (ShOpcVal == ARM_AM::lsl)
827 std::swap(Base, OffReg);
830 if (ShOpcVal == ARM_AM::lsl) {
831 // Check to see if the RHS of the shift is a constant, if not, we can't fold
833 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
834 ShAmt = Sh->getZExtValue();
837 ShOpcVal = ARM_AM::no_shift;
839 OffReg = OffReg.getOperand(0);
841 ShOpcVal = ARM_AM::no_shift;
845 ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
850 //===--------------------------------------------------------------------===//
852 /// getAL - Returns a ARMCC::AL immediate node.
853 static inline SDValue getAL(SelectionDAG *CurDAG) {
854 return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
857 SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDNode *N) {
858 LoadSDNode *LD = cast<LoadSDNode>(N);
859 ISD::MemIndexedMode AM = LD->getAddressingMode();
860 if (AM == ISD::UNINDEXED)
863 EVT LoadedVT = LD->getMemoryVT();
864 SDValue Offset, AMOpc;
865 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
868 if (LoadedVT == MVT::i32 &&
869 SelectAddrMode2Offset(N, LD->getOffset(), Offset, AMOpc)) {
870 Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST;
872 } else if (LoadedVT == MVT::i16 &&
873 SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
875 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
876 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
877 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
878 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
879 if (LD->getExtensionType() == ISD::SEXTLOAD) {
880 if (SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
882 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
885 if (SelectAddrMode2Offset(N, LD->getOffset(), Offset, AMOpc)) {
887 Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST;
893 SDValue Chain = LD->getChain();
894 SDValue Base = LD->getBasePtr();
895 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
896 CurDAG->getRegister(0, MVT::i32), Chain };
897 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32,
904 SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDNode *N) {
905 LoadSDNode *LD = cast<LoadSDNode>(N);
906 ISD::MemIndexedMode AM = LD->getAddressingMode();
907 if (AM == ISD::UNINDEXED)
910 EVT LoadedVT = LD->getMemoryVT();
911 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
913 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
916 if (SelectT2AddrModeImm8Offset(N, LD->getOffset(), Offset)) {
917 switch (LoadedVT.getSimpleVT().SimpleTy) {
919 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
923 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
925 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
930 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
932 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
941 SDValue Chain = LD->getChain();
942 SDValue Base = LD->getBasePtr();
943 SDValue Ops[]= { Base, Offset, getAL(CurDAG),
944 CurDAG->getRegister(0, MVT::i32), Chain };
945 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32,
952 SDNode *ARMDAGToDAGISel::SelectDYN_ALLOC(SDNode *N) {
953 DebugLoc dl = N->getDebugLoc();
954 EVT VT = N->getValueType(0);
955 SDValue Chain = N->getOperand(0);
956 SDValue Size = N->getOperand(1);
957 SDValue Align = N->getOperand(2);
958 SDValue SP = CurDAG->getRegister(ARM::SP, MVT::i32);
959 int32_t AlignVal = cast<ConstantSDNode>(Align)->getSExtValue();
961 // We need to align the stack. Use Thumb1 tAND which is the only thumb
962 // instruction that can read and write SP. This matches to a pseudo
963 // instruction that has a chain to ensure the result is written back to
964 // the stack pointer.
965 SP = SDValue(CurDAG->getMachineNode(ARM::tANDsp, dl, VT, SP, Align), 0);
967 bool isC = isa<ConstantSDNode>(Size);
968 uint32_t C = isC ? cast<ConstantSDNode>(Size)->getZExtValue() : ~0UL;
969 // Handle the most common case for both Thumb1 and Thumb2:
970 // tSUBspi - immediate is between 0 ... 508 inclusive.
971 if (C <= 508 && ((C & 3) == 0))
972 // FIXME: tSUBspi encode scale 4 implicitly.
973 return CurDAG->SelectNodeTo(N, ARM::tSUBspi_, VT, MVT::Other, SP,
974 CurDAG->getTargetConstant(C/4, MVT::i32),
977 if (Subtarget->isThumb1Only()) {
978 // Use tADDspr since Thumb1 does not have a sub r, sp, r. ARMISelLowering
979 // should have negated the size operand already. FIXME: We can't insert
980 // new target independent node at this stage so we are forced to negate
981 // it earlier. Is there a better solution?
982 return CurDAG->SelectNodeTo(N, ARM::tADDspr_, VT, MVT::Other, SP, Size,
984 } else if (Subtarget->isThumb2()) {
985 if (isC && Predicate_t2_so_imm(Size.getNode())) {
987 SDValue Ops[] = { SP, CurDAG->getTargetConstant(C, MVT::i32), Chain };
988 return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPi_, VT, MVT::Other, Ops, 3);
989 } else if (isC && Predicate_imm0_4095(Size.getNode())) {
991 SDValue Ops[] = { SP, CurDAG->getTargetConstant(C, MVT::i32), Chain };
992 return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPi12_, VT, MVT::Other, Ops, 3);
995 SDValue Ops[] = { SP, Size,
996 getI32Imm(ARM_AM::getSORegOpc(ARM_AM::lsl,0)), Chain };
997 return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPs_, VT, MVT::Other, Ops, 4);
1001 // FIXME: Add ADD / SUB sp instructions for ARM.
1005 /// PairDRegs - Insert a pair of double registers into an implicit def to
1006 /// form a quad register.
1007 SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) {
1008 DebugLoc dl = V0.getNode()->getDebugLoc();
1010 SDValue(CurDAG->getMachineNode(TargetInstrInfo::IMPLICIT_DEF, dl, VT), 0);
1011 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::DSUBREG_0, MVT::i32);
1012 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::DSUBREG_1, MVT::i32);
1013 SDNode *Pair = CurDAG->getMachineNode(TargetInstrInfo::INSERT_SUBREG, dl,
1014 VT, Undef, V0, SubReg0);
1015 return CurDAG->getMachineNode(TargetInstrInfo::INSERT_SUBREG, dl,
1016 VT, SDValue(Pair, 0), V1, SubReg1);
1019 /// GetNEONSubregVT - Given a type for a 128-bit NEON vector, return the type
1020 /// for a 64-bit subregister of the vector.
1021 static EVT GetNEONSubregVT(EVT VT) {
1022 switch (VT.getSimpleVT().SimpleTy) {
1023 default: llvm_unreachable("unhandled NEON type");
1024 case MVT::v16i8: return MVT::v8i8;
1025 case MVT::v8i16: return MVT::v4i16;
1026 case MVT::v4f32: return MVT::v2f32;
1027 case MVT::v4i32: return MVT::v2i32;
1028 case MVT::v2i64: return MVT::v1i64;
1032 SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, unsigned NumVecs,
1033 unsigned *DOpcodes, unsigned *QOpcodes0,
1034 unsigned *QOpcodes1) {
1035 assert(NumVecs >=2 && NumVecs <= 4 && "VLD NumVecs out-of-range");
1036 DebugLoc dl = N->getDebugLoc();
1038 SDValue MemAddr, MemUpdate, MemOpc, Align;
1039 if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, MemUpdate, MemOpc, Align))
1042 SDValue Chain = N->getOperand(0);
1043 EVT VT = N->getValueType(0);
1044 bool is64BitVector = VT.is64BitVector();
1046 unsigned OpcodeIndex;
1047 switch (VT.getSimpleVT().SimpleTy) {
1048 default: llvm_unreachable("unhandled vld type");
1049 // Double-register operations:
1050 case MVT::v8i8: OpcodeIndex = 0; break;
1051 case MVT::v4i16: OpcodeIndex = 1; break;
1053 case MVT::v2i32: OpcodeIndex = 2; break;
1054 case MVT::v1i64: OpcodeIndex = 3; break;
1055 // Quad-register operations:
1056 case MVT::v16i8: OpcodeIndex = 0; break;
1057 case MVT::v8i16: OpcodeIndex = 1; break;
1059 case MVT::v4i32: OpcodeIndex = 2; break;
1062 SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32);
1063 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
1064 if (is64BitVector) {
1065 unsigned Opc = DOpcodes[OpcodeIndex];
1066 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Align,
1067 Pred, PredReg, Chain };
1068 std::vector<EVT> ResTys(NumVecs, VT);
1069 ResTys.push_back(MVT::Other);
1070 return CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 7);
1073 EVT RegVT = GetNEONSubregVT(VT);
1075 // Quad registers are directly supported for VLD2,
1076 // loading 2 pairs of D regs.
1077 unsigned Opc = QOpcodes0[OpcodeIndex];
1078 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Align,
1079 Pred, PredReg, Chain };
1080 std::vector<EVT> ResTys(4, VT);
1081 ResTys.push_back(MVT::Other);
1082 SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 7);
1083 Chain = SDValue(VLd, 4);
1085 // Combine the even and odd subregs to produce the result.
1086 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1087 SDNode *Q = PairDRegs(VT, SDValue(VLd, 2*Vec), SDValue(VLd, 2*Vec+1));
1088 ReplaceUses(SDValue(N, Vec), SDValue(Q, 0));
1091 // Otherwise, quad registers are loaded with two separate instructions,
1092 // where one loads the even registers and the other loads the odd registers.
1094 // Enable writeback to the address register.
1095 MemOpc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(true), MVT::i32);
1097 std::vector<EVT> ResTys(NumVecs, RegVT);
1098 ResTys.push_back(MemAddr.getValueType());
1099 ResTys.push_back(MVT::Other);
1101 // Load the even subregs.
1102 unsigned Opc = QOpcodes0[OpcodeIndex];
1103 const SDValue OpsA[] = { MemAddr, MemUpdate, MemOpc, Align,
1104 Pred, PredReg, Chain };
1105 SDNode *VLdA = CurDAG->getMachineNode(Opc, dl, ResTys, OpsA, 7);
1106 Chain = SDValue(VLdA, NumVecs+1);
1108 // Load the odd subregs.
1109 Opc = QOpcodes1[OpcodeIndex];
1110 const SDValue OpsB[] = { SDValue(VLdA, NumVecs), MemUpdate, MemOpc,
1111 Align, Pred, PredReg, Chain };
1112 SDNode *VLdB = CurDAG->getMachineNode(Opc, dl, ResTys, OpsB, 7);
1113 Chain = SDValue(VLdB, NumVecs+1);
1115 // Combine the even and odd subregs to produce the result.
1116 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1117 SDNode *Q = PairDRegs(VT, SDValue(VLdA, Vec), SDValue(VLdB, Vec));
1118 ReplaceUses(SDValue(N, Vec), SDValue(Q, 0));
1121 ReplaceUses(SDValue(N, NumVecs), Chain);
1125 SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, unsigned NumVecs,
1126 unsigned *DOpcodes, unsigned *QOpcodes0,
1127 unsigned *QOpcodes1) {
1128 assert(NumVecs >=2 && NumVecs <= 4 && "VST NumVecs out-of-range");
1129 DebugLoc dl = N->getDebugLoc();
1131 SDValue MemAddr, MemUpdate, MemOpc, Align;
1132 if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, MemUpdate, MemOpc, Align))
1135 SDValue Chain = N->getOperand(0);
1136 EVT VT = N->getOperand(3).getValueType();
1137 bool is64BitVector = VT.is64BitVector();
1139 unsigned OpcodeIndex;
1140 switch (VT.getSimpleVT().SimpleTy) {
1141 default: llvm_unreachable("unhandled vst type");
1142 // Double-register operations:
1143 case MVT::v8i8: OpcodeIndex = 0; break;
1144 case MVT::v4i16: OpcodeIndex = 1; break;
1146 case MVT::v2i32: OpcodeIndex = 2; break;
1147 case MVT::v1i64: OpcodeIndex = 3; break;
1148 // Quad-register operations:
1149 case MVT::v16i8: OpcodeIndex = 0; break;
1150 case MVT::v8i16: OpcodeIndex = 1; break;
1152 case MVT::v4i32: OpcodeIndex = 2; break;
1155 SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32);
1156 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
1158 SmallVector<SDValue, 8> Ops;
1159 Ops.push_back(MemAddr);
1160 Ops.push_back(MemUpdate);
1161 Ops.push_back(MemOpc);
1162 Ops.push_back(Align);
1164 if (is64BitVector) {
1165 unsigned Opc = DOpcodes[OpcodeIndex];
1166 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1167 Ops.push_back(N->getOperand(Vec+3));
1168 Ops.push_back(Pred);
1169 Ops.push_back(PredReg);
1170 Ops.push_back(Chain);
1171 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), NumVecs+7);
1174 EVT RegVT = GetNEONSubregVT(VT);
1176 // Quad registers are directly supported for VST2,
1177 // storing 2 pairs of D regs.
1178 unsigned Opc = QOpcodes0[OpcodeIndex];
1179 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1180 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
1181 N->getOperand(Vec+3)));
1182 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
1183 N->getOperand(Vec+3)));
1185 Ops.push_back(Pred);
1186 Ops.push_back(PredReg);
1187 Ops.push_back(Chain);
1188 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 11);
1191 // Otherwise, quad registers are stored with two separate instructions,
1192 // where one stores the even registers and the other stores the odd registers.
1194 // Enable writeback to the address register.
1195 MemOpc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(true), MVT::i32);
1197 // Store the even subregs.
1198 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1199 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
1200 N->getOperand(Vec+3)));
1201 Ops.push_back(Pred);
1202 Ops.push_back(PredReg);
1203 Ops.push_back(Chain);
1204 unsigned Opc = QOpcodes0[OpcodeIndex];
1205 SDNode *VStA = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
1206 MVT::Other, Ops.data(), NumVecs+7);
1207 Chain = SDValue(VStA, 1);
1209 // Store the odd subregs.
1210 Ops[0] = SDValue(VStA, 0); // MemAddr
1211 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1212 Ops[Vec+4] = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
1213 N->getOperand(Vec+3));
1214 Ops[NumVecs+4] = Pred;
1215 Ops[NumVecs+5] = PredReg;
1216 Ops[NumVecs+6] = Chain;
1217 Opc = QOpcodes1[OpcodeIndex];
1218 SDNode *VStB = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
1219 MVT::Other, Ops.data(), NumVecs+7);
1220 Chain = SDValue(VStB, 1);
1221 ReplaceUses(SDValue(N, 0), Chain);
1225 SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
1226 unsigned NumVecs, unsigned *DOpcodes,
1227 unsigned *QOpcodes0,
1228 unsigned *QOpcodes1) {
1229 assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
1230 DebugLoc dl = N->getDebugLoc();
1232 SDValue MemAddr, MemUpdate, MemOpc, Align;
1233 if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, MemUpdate, MemOpc, Align))
1236 SDValue Chain = N->getOperand(0);
1238 cast<ConstantSDNode>(N->getOperand(NumVecs+3))->getZExtValue();
1239 EVT VT = IsLoad ? N->getValueType(0) : N->getOperand(3).getValueType();
1240 bool is64BitVector = VT.is64BitVector();
1242 // Quad registers are handled by load/store of subregs. Find the subreg info.
1243 unsigned NumElts = 0;
1246 if (!is64BitVector) {
1247 RegVT = GetNEONSubregVT(VT);
1248 NumElts = RegVT.getVectorNumElements();
1249 SubregIdx = (Lane < NumElts) ? ARM::DSUBREG_0 : ARM::DSUBREG_1;
1252 unsigned OpcodeIndex;
1253 switch (VT.getSimpleVT().SimpleTy) {
1254 default: llvm_unreachable("unhandled vld/vst lane type");
1255 // Double-register operations:
1256 case MVT::v8i8: OpcodeIndex = 0; break;
1257 case MVT::v4i16: OpcodeIndex = 1; break;
1259 case MVT::v2i32: OpcodeIndex = 2; break;
1260 // Quad-register operations:
1261 case MVT::v8i16: OpcodeIndex = 0; break;
1263 case MVT::v4i32: OpcodeIndex = 1; break;
1266 SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32);
1267 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
1269 SmallVector<SDValue, 9> Ops;
1270 Ops.push_back(MemAddr);
1271 Ops.push_back(MemUpdate);
1272 Ops.push_back(MemOpc);
1273 Ops.push_back(Align);
1276 if (is64BitVector) {
1277 Opc = DOpcodes[OpcodeIndex];
1278 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1279 Ops.push_back(N->getOperand(Vec+3));
1281 // Check if this is loading the even or odd subreg of a Q register.
1282 if (Lane < NumElts) {
1283 Opc = QOpcodes0[OpcodeIndex];
1286 Opc = QOpcodes1[OpcodeIndex];
1288 // Extract the subregs of the input vector.
1289 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1290 Ops.push_back(CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
1291 N->getOperand(Vec+3)));
1293 Ops.push_back(getI32Imm(Lane));
1294 Ops.push_back(Pred);
1295 Ops.push_back(PredReg);
1296 Ops.push_back(Chain);
1299 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), NumVecs+8);
1301 std::vector<EVT> ResTys(NumVecs, RegVT);
1302 ResTys.push_back(MVT::Other);
1304 CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), NumVecs+8);
1305 // For a 64-bit vector load to D registers, nothing more needs to be done.
1309 // For 128-bit vectors, take the 64-bit results of the load and insert them
1310 // as subregs into the result.
1311 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1312 SDValue QuadVec = CurDAG->getTargetInsertSubreg(SubregIdx, dl, VT,
1313 N->getOperand(Vec+3),
1314 SDValue(VLdLn, Vec));
1315 ReplaceUses(SDValue(N, Vec), QuadVec);
1318 Chain = SDValue(VLdLn, NumVecs);
1319 ReplaceUses(SDValue(N, NumVecs), Chain);
1323 SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N,
1325 if (!Subtarget->hasV6T2Ops())
1328 unsigned Shl_imm = 0;
1329 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, Shl_imm)) {
1330 assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!");
1331 unsigned Srl_imm = 0;
1332 if (isInt32Immediate(N->getOperand(1), Srl_imm)) {
1333 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
1334 unsigned Width = 32 - Srl_imm;
1335 int LSB = Srl_imm - Shl_imm;
1338 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1339 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1340 CurDAG->getTargetConstant(LSB, MVT::i32),
1341 CurDAG->getTargetConstant(Width, MVT::i32),
1342 getAL(CurDAG), Reg0 };
1343 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1349 SDNode *ARMDAGToDAGISel::
1350 SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1351 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1354 if (SelectT2ShifterOperandReg(N, TrueVal, CPTmp0, CPTmp1)) {
1355 unsigned SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue();
1356 unsigned SOShOp = ARM_AM::getSORegShOp(SOVal);
1359 case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break;
1360 case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break;
1361 case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break;
1362 case ARM_AM::ror: Opc = ARM::t2MOVCCror; break;
1364 llvm_unreachable("Unknown so_reg opcode!");
1368 CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32);
1369 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1370 SDValue Ops[] = { FalseVal, CPTmp0, SOShImm, CC, CCR, InFlag };
1371 return CurDAG->SelectNodeTo(N, Opc, MVT::i32,Ops, 6);
1376 SDNode *ARMDAGToDAGISel::
1377 SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1378 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1382 if (SelectShifterOperandReg(N, TrueVal, CPTmp0, CPTmp1, CPTmp2)) {
1383 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1384 SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CPTmp2, CC, CCR, InFlag };
1385 return CurDAG->SelectNodeTo(N, ARM::MOVCCs, MVT::i32, Ops, 7);
1390 SDNode *ARMDAGToDAGISel::
1391 SelectT2CMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1392 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1393 ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
1397 if (Predicate_t2_so_imm(TrueVal.getNode())) {
1398 SDValue True = CurDAG->getTargetConstant(T->getZExtValue(), MVT::i32);
1399 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1400 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
1401 return CurDAG->SelectNodeTo(N,
1402 ARM::t2MOVCCi, MVT::i32, Ops, 5);
1407 SDNode *ARMDAGToDAGISel::
1408 SelectARMCMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1409 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1410 ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
1414 if (Predicate_so_imm(TrueVal.getNode())) {
1415 SDValue True = CurDAG->getTargetConstant(T->getZExtValue(), MVT::i32);
1416 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1417 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
1418 return CurDAG->SelectNodeTo(N,
1419 ARM::MOVCCi, MVT::i32, Ops, 5);
1424 SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDNode *N) {
1425 EVT VT = N->getValueType(0);
1426 SDValue FalseVal = N->getOperand(0);
1427 SDValue TrueVal = N->getOperand(1);
1428 SDValue CC = N->getOperand(2);
1429 SDValue CCR = N->getOperand(3);
1430 SDValue InFlag = N->getOperand(4);
1431 assert(CC.getOpcode() == ISD::Constant);
1432 assert(CCR.getOpcode() == ISD::Register);
1433 ARMCC::CondCodes CCVal =
1434 (ARMCC::CondCodes)cast<ConstantSDNode>(CC)->getZExtValue();
1436 if (!Subtarget->isThumb1Only() && VT == MVT::i32) {
1437 // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1438 // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1439 // Pattern complexity = 18 cost = 1 size = 0
1443 if (Subtarget->isThumb()) {
1444 SDNode *Res = SelectT2CMOVShiftOp(N, FalseVal, TrueVal,
1445 CCVal, CCR, InFlag);
1447 Res = SelectT2CMOVShiftOp(N, TrueVal, FalseVal,
1448 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1452 SDNode *Res = SelectARMCMOVShiftOp(N, FalseVal, TrueVal,
1453 CCVal, CCR, InFlag);
1455 Res = SelectARMCMOVShiftOp(N, TrueVal, FalseVal,
1456 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1461 // Pattern: (ARMcmov:i32 GPR:i32:$false,
1462 // (imm:i32)<<P:Predicate_so_imm>>:$true,
1464 // Emits: (MOVCCi:i32 GPR:i32:$false,
1465 // (so_imm:i32 (imm:i32):$true), (imm:i32):$cc)
1466 // Pattern complexity = 10 cost = 1 size = 0
1467 if (Subtarget->isThumb()) {
1468 SDNode *Res = SelectT2CMOVSoImmOp(N, FalseVal, TrueVal,
1469 CCVal, CCR, InFlag);
1471 Res = SelectT2CMOVSoImmOp(N, TrueVal, FalseVal,
1472 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1476 SDNode *Res = SelectARMCMOVSoImmOp(N, FalseVal, TrueVal,
1477 CCVal, CCR, InFlag);
1479 Res = SelectARMCMOVSoImmOp(N, TrueVal, FalseVal,
1480 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1486 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1487 // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1488 // Pattern complexity = 6 cost = 1 size = 0
1490 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1491 // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1492 // Pattern complexity = 6 cost = 11 size = 0
1494 // Also FCPYScc and FCPYDcc.
1495 SDValue Tmp2 = CurDAG->getTargetConstant(CCVal, MVT::i32);
1496 SDValue Ops[] = { FalseVal, TrueVal, Tmp2, CCR, InFlag };
1498 switch (VT.getSimpleVT().SimpleTy) {
1499 default: assert(false && "Illegal conditional move type!");
1502 Opc = Subtarget->isThumb()
1503 ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo)
1513 return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
1516 SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
1517 DebugLoc dl = N->getDebugLoc();
1519 if (N->isMachineOpcode())
1520 return NULL; // Already selected.
1522 switch (N->getOpcode()) {
1524 case ISD::Constant: {
1525 unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
1527 if (Subtarget->hasThumb2())
1528 // Thumb2-aware targets have the MOVT instruction, so all immediates can
1529 // be done with MOV + MOVT, at worst.
1532 if (Subtarget->isThumb()) {
1533 UseCP = (Val > 255 && // MOV
1534 ~Val > 255 && // MOV + MVN
1535 !ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL
1537 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
1538 ARM_AM::getSOImmVal(~Val) == -1 && // MVN
1539 !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs.
1544 CurDAG->getTargetConstantPool(ConstantInt::get(
1545 Type::getInt32Ty(*CurDAG->getContext()), Val),
1546 TLI.getPointerTy());
1549 if (Subtarget->isThumb1Only()) {
1550 SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32);
1551 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
1552 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
1553 ResNode = CurDAG->getMachineNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other,
1558 CurDAG->getRegister(0, MVT::i32),
1559 CurDAG->getTargetConstant(0, MVT::i32),
1561 CurDAG->getRegister(0, MVT::i32),
1562 CurDAG->getEntryNode()
1564 ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
1567 ReplaceUses(SDValue(N, 0), SDValue(ResNode, 0));
1571 // Other cases are autogenerated.
1574 case ISD::FrameIndex: {
1575 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
1576 int FI = cast<FrameIndexSDNode>(N)->getIndex();
1577 SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1578 if (Subtarget->isThumb1Only()) {
1579 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
1580 CurDAG->getTargetConstant(0, MVT::i32));
1582 unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
1583 ARM::t2ADDri : ARM::ADDri);
1584 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
1585 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1586 CurDAG->getRegister(0, MVT::i32) };
1587 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1590 case ARMISD::DYN_ALLOC:
1591 return SelectDYN_ALLOC(N);
1593 if (SDNode *I = SelectV6T2BitfieldExtractOp(N,
1594 Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX))
1598 if (SDNode *I = SelectV6T2BitfieldExtractOp(N,
1599 Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX))
1603 if (Subtarget->isThumb1Only())
1605 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1606 unsigned RHSV = C->getZExtValue();
1608 if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
1609 unsigned ShImm = Log2_32(RHSV-1);
1612 SDValue V = N->getOperand(0);
1613 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
1614 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
1615 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1616 if (Subtarget->isThumb()) {
1617 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1618 return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
1620 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1621 return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7);
1624 if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
1625 unsigned ShImm = Log2_32(RHSV+1);
1628 SDValue V = N->getOperand(0);
1629 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
1630 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
1631 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1632 if (Subtarget->isThumb()) {
1633 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0 };
1634 return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 5);
1636 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1637 return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7);
1643 // (and (or x, c2), c1) and top 16-bits of c1 and c2 match, lower 16-bits
1644 // of c1 are 0xffff, and lower 16-bit of c2 are 0. That is, the top 16-bits
1645 // are entirely contributed by c2 and lower 16-bits are entirely contributed
1646 // by x. That's equal to (or (and x, 0xffff), (and c1, 0xffff0000)).
1647 // Select it to: "movt x, ((c1 & 0xffff) >> 16)
1648 EVT VT = N->getValueType(0);
1651 unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2())
1653 : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0);
1656 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
1657 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1660 if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) {
1661 SDValue N2 = N0.getOperand(1);
1662 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1665 unsigned N1CVal = N1C->getZExtValue();
1666 unsigned N2CVal = N2C->getZExtValue();
1667 if ((N1CVal & 0xffff0000U) == (N2CVal & 0xffff0000U) &&
1668 (N1CVal & 0xffffU) == 0xffffU &&
1669 (N2CVal & 0xffffU) == 0x0U) {
1670 SDValue Imm16 = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16,
1672 SDValue Ops[] = { N0.getOperand(0), Imm16,
1673 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
1674 return CurDAG->getMachineNode(Opc, dl, VT, Ops, 4);
1679 case ARMISD::VMOVRRD:
1680 return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32,
1681 N->getOperand(0), getAL(CurDAG),
1682 CurDAG->getRegister(0, MVT::i32));
1683 case ARMISD::RBIT: {
1684 EVT VT = N->getValueType(0);
1685 SDValue Ops[] = { N->getOperand(0),
1686 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
1687 return CurDAG->getMachineNode(ARM::RBIT, dl, VT, Ops, 3);
1689 case ISD::UMUL_LOHI: {
1690 if (Subtarget->isThumb1Only())
1692 if (Subtarget->isThumb()) {
1693 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
1694 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1695 CurDAG->getRegister(0, MVT::i32) };
1696 return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32, Ops,4);
1698 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
1699 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1700 CurDAG->getRegister(0, MVT::i32) };
1701 return CurDAG->getMachineNode(ARM::UMULL, dl, MVT::i32, MVT::i32, Ops, 5);
1704 case ISD::SMUL_LOHI: {
1705 if (Subtarget->isThumb1Only())
1707 if (Subtarget->isThumb()) {
1708 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
1709 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
1710 return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32, Ops,4);
1712 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
1713 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1714 CurDAG->getRegister(0, MVT::i32) };
1715 return CurDAG->getMachineNode(ARM::SMULL, dl, MVT::i32, MVT::i32, Ops, 5);
1719 SDNode *ResNode = 0;
1720 if (Subtarget->isThumb() && Subtarget->hasThumb2())
1721 ResNode = SelectT2IndexedLoad(N);
1723 ResNode = SelectARMIndexedLoad(N);
1726 // Other cases are autogenerated.
1729 case ARMISD::BRCOND: {
1730 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1731 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
1732 // Pattern complexity = 6 cost = 1 size = 0
1734 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1735 // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
1736 // Pattern complexity = 6 cost = 1 size = 0
1738 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1739 // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
1740 // Pattern complexity = 6 cost = 1 size = 0
1742 unsigned Opc = Subtarget->isThumb() ?
1743 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
1744 SDValue Chain = N->getOperand(0);
1745 SDValue N1 = N->getOperand(1);
1746 SDValue N2 = N->getOperand(2);
1747 SDValue N3 = N->getOperand(3);
1748 SDValue InFlag = N->getOperand(4);
1749 assert(N1.getOpcode() == ISD::BasicBlock);
1750 assert(N2.getOpcode() == ISD::Constant);
1751 assert(N3.getOpcode() == ISD::Register);
1753 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1754 cast<ConstantSDNode>(N2)->getZExtValue()),
1756 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
1757 SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,
1759 Chain = SDValue(ResNode, 0);
1760 if (N->getNumValues() == 2) {
1761 InFlag = SDValue(ResNode, 1);
1762 ReplaceUses(SDValue(N, 1), InFlag);
1764 ReplaceUses(SDValue(N, 0),
1765 SDValue(Chain.getNode(), Chain.getResNo()));
1769 return SelectCMOVOp(N);
1770 case ARMISD::CNEG: {
1771 EVT VT = N->getValueType(0);
1772 SDValue N0 = N->getOperand(0);
1773 SDValue N1 = N->getOperand(1);
1774 SDValue N2 = N->getOperand(2);
1775 SDValue N3 = N->getOperand(3);
1776 SDValue InFlag = N->getOperand(4);
1777 assert(N2.getOpcode() == ISD::Constant);
1778 assert(N3.getOpcode() == ISD::Register);
1780 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1781 cast<ConstantSDNode>(N2)->getZExtValue()),
1783 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
1785 switch (VT.getSimpleVT().SimpleTy) {
1786 default: assert(false && "Illegal conditional move type!");
1795 return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
1798 case ARMISD::VZIP: {
1800 EVT VT = N->getValueType(0);
1801 switch (VT.getSimpleVT().SimpleTy) {
1802 default: return NULL;
1803 case MVT::v8i8: Opc = ARM::VZIPd8; break;
1804 case MVT::v4i16: Opc = ARM::VZIPd16; break;
1806 case MVT::v2i32: Opc = ARM::VZIPd32; break;
1807 case MVT::v16i8: Opc = ARM::VZIPq8; break;
1808 case MVT::v8i16: Opc = ARM::VZIPq16; break;
1810 case MVT::v4i32: Opc = ARM::VZIPq32; break;
1812 SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32);
1813 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
1814 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
1815 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
1817 case ARMISD::VUZP: {
1819 EVT VT = N->getValueType(0);
1820 switch (VT.getSimpleVT().SimpleTy) {
1821 default: return NULL;
1822 case MVT::v8i8: Opc = ARM::VUZPd8; break;
1823 case MVT::v4i16: Opc = ARM::VUZPd16; break;
1825 case MVT::v2i32: Opc = ARM::VUZPd32; break;
1826 case MVT::v16i8: Opc = ARM::VUZPq8; break;
1827 case MVT::v8i16: Opc = ARM::VUZPq16; break;
1829 case MVT::v4i32: Opc = ARM::VUZPq32; break;
1831 SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32);
1832 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
1833 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
1834 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
1836 case ARMISD::VTRN: {
1838 EVT VT = N->getValueType(0);
1839 switch (VT.getSimpleVT().SimpleTy) {
1840 default: return NULL;
1841 case MVT::v8i8: Opc = ARM::VTRNd8; break;
1842 case MVT::v4i16: Opc = ARM::VTRNd16; break;
1844 case MVT::v2i32: Opc = ARM::VTRNd32; break;
1845 case MVT::v16i8: Opc = ARM::VTRNq8; break;
1846 case MVT::v8i16: Opc = ARM::VTRNq16; break;
1848 case MVT::v4i32: Opc = ARM::VTRNq32; break;
1850 SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32);
1851 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
1852 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
1853 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
1856 case ISD::INTRINSIC_VOID:
1857 case ISD::INTRINSIC_W_CHAIN: {
1858 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
1863 case Intrinsic::arm_neon_vld2: {
1864 unsigned DOpcodes[] = { ARM::VLD2d8, ARM::VLD2d16,
1865 ARM::VLD2d32, ARM::VLD2d64 };
1866 unsigned QOpcodes[] = { ARM::VLD2q8, ARM::VLD2q16, ARM::VLD2q32 };
1867 return SelectVLD(N, 2, DOpcodes, QOpcodes, 0);
1870 case Intrinsic::arm_neon_vld3: {
1871 unsigned DOpcodes[] = { ARM::VLD3d8, ARM::VLD3d16,
1872 ARM::VLD3d32, ARM::VLD3d64 };
1873 unsigned QOpcodes0[] = { ARM::VLD3q8a, ARM::VLD3q16a, ARM::VLD3q32a };
1874 unsigned QOpcodes1[] = { ARM::VLD3q8b, ARM::VLD3q16b, ARM::VLD3q32b };
1875 return SelectVLD(N, 3, DOpcodes, QOpcodes0, QOpcodes1);
1878 case Intrinsic::arm_neon_vld4: {
1879 unsigned DOpcodes[] = { ARM::VLD4d8, ARM::VLD4d16,
1880 ARM::VLD4d32, ARM::VLD4d64 };
1881 unsigned QOpcodes0[] = { ARM::VLD4q8a, ARM::VLD4q16a, ARM::VLD4q32a };
1882 unsigned QOpcodes1[] = { ARM::VLD4q8b, ARM::VLD4q16b, ARM::VLD4q32b };
1883 return SelectVLD(N, 4, DOpcodes, QOpcodes0, QOpcodes1);
1886 case Intrinsic::arm_neon_vld2lane: {
1887 unsigned DOpcodes[] = { ARM::VLD2LNd8, ARM::VLD2LNd16, ARM::VLD2LNd32 };
1888 unsigned QOpcodes0[] = { ARM::VLD2LNq16a, ARM::VLD2LNq32a };
1889 unsigned QOpcodes1[] = { ARM::VLD2LNq16b, ARM::VLD2LNq32b };
1890 return SelectVLDSTLane(N, true, 2, DOpcodes, QOpcodes0, QOpcodes1);
1893 case Intrinsic::arm_neon_vld3lane: {
1894 unsigned DOpcodes[] = { ARM::VLD3LNd8, ARM::VLD3LNd16, ARM::VLD3LNd32 };
1895 unsigned QOpcodes0[] = { ARM::VLD3LNq16a, ARM::VLD3LNq32a };
1896 unsigned QOpcodes1[] = { ARM::VLD3LNq16b, ARM::VLD3LNq32b };
1897 return SelectVLDSTLane(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
1900 case Intrinsic::arm_neon_vld4lane: {
1901 unsigned DOpcodes[] = { ARM::VLD4LNd8, ARM::VLD4LNd16, ARM::VLD4LNd32 };
1902 unsigned QOpcodes0[] = { ARM::VLD4LNq16a, ARM::VLD4LNq32a };
1903 unsigned QOpcodes1[] = { ARM::VLD4LNq16b, ARM::VLD4LNq32b };
1904 return SelectVLDSTLane(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
1907 case Intrinsic::arm_neon_vst2: {
1908 unsigned DOpcodes[] = { ARM::VST2d8, ARM::VST2d16,
1909 ARM::VST2d32, ARM::VST2d64 };
1910 unsigned QOpcodes[] = { ARM::VST2q8, ARM::VST2q16, ARM::VST2q32 };
1911 return SelectVST(N, 2, DOpcodes, QOpcodes, 0);
1914 case Intrinsic::arm_neon_vst3: {
1915 unsigned DOpcodes[] = { ARM::VST3d8, ARM::VST3d16,
1916 ARM::VST3d32, ARM::VST3d64 };
1917 unsigned QOpcodes0[] = { ARM::VST3q8a, ARM::VST3q16a, ARM::VST3q32a };
1918 unsigned QOpcodes1[] = { ARM::VST3q8b, ARM::VST3q16b, ARM::VST3q32b };
1919 return SelectVST(N, 3, DOpcodes, QOpcodes0, QOpcodes1);
1922 case Intrinsic::arm_neon_vst4: {
1923 unsigned DOpcodes[] = { ARM::VST4d8, ARM::VST4d16,
1924 ARM::VST4d32, ARM::VST4d64 };
1925 unsigned QOpcodes0[] = { ARM::VST4q8a, ARM::VST4q16a, ARM::VST4q32a };
1926 unsigned QOpcodes1[] = { ARM::VST4q8b, ARM::VST4q16b, ARM::VST4q32b };
1927 return SelectVST(N, 4, DOpcodes, QOpcodes0, QOpcodes1);
1930 case Intrinsic::arm_neon_vst2lane: {
1931 unsigned DOpcodes[] = { ARM::VST2LNd8, ARM::VST2LNd16, ARM::VST2LNd32 };
1932 unsigned QOpcodes0[] = { ARM::VST2LNq16a, ARM::VST2LNq32a };
1933 unsigned QOpcodes1[] = { ARM::VST2LNq16b, ARM::VST2LNq32b };
1934 return SelectVLDSTLane(N, false, 2, DOpcodes, QOpcodes0, QOpcodes1);
1937 case Intrinsic::arm_neon_vst3lane: {
1938 unsigned DOpcodes[] = { ARM::VST3LNd8, ARM::VST3LNd16, ARM::VST3LNd32 };
1939 unsigned QOpcodes0[] = { ARM::VST3LNq16a, ARM::VST3LNq32a };
1940 unsigned QOpcodes1[] = { ARM::VST3LNq16b, ARM::VST3LNq32b };
1941 return SelectVLDSTLane(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
1944 case Intrinsic::arm_neon_vst4lane: {
1945 unsigned DOpcodes[] = { ARM::VST4LNd8, ARM::VST4LNd16, ARM::VST4LNd32 };
1946 unsigned QOpcodes0[] = { ARM::VST4LNq16a, ARM::VST4LNq32a };
1947 unsigned QOpcodes1[] = { ARM::VST4LNq16b, ARM::VST4LNq32b };
1948 return SelectVLDSTLane(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
1954 return SelectCode(N);
1957 bool ARMDAGToDAGISel::
1958 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
1959 std::vector<SDValue> &OutOps) {
1960 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
1961 // Require the address to be in a register. That is safe for all ARM
1962 // variants and it is hard to do anything much smarter without knowing
1963 // how the operand is used.
1964 OutOps.push_back(Op);
1968 /// createARMISelDag - This pass converts a legalized DAG into a
1969 /// ARM-specific DAG, ready for instruction scheduling.
1971 FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
1972 CodeGenOpt::Level OptLevel) {
1973 return new ARMDAGToDAGISel(TM, OptLevel);