1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
15 #include "ARMTargetMachine.h"
16 #include "llvm/DerivedTypes.h"
17 #include "llvm/Function.h"
18 #include "llvm/Intrinsics.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/CodeGen/SSARegMap.h"
25 #include "llvm/Target/TargetLowering.h"
26 #include "llvm/Support/Debug.h"
33 FIRST_NUMBER = ISD::BUILTIN_OP_END+ARM::INSTRUCTION_LIST_END,
39 class ARMTargetLowering : public TargetLowering {
41 ARMTargetLowering(TargetMachine &TM);
42 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
47 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
48 : TargetLowering(TM) {
49 setOperationAction(ISD::RET, MVT::Other, Custom);
52 static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
53 assert(0 && "Not implemented");
57 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
59 switch(Op.getNumOperands()) {
61 assert(0 && "Do not know how to return this many arguments!");
64 return SDOperand(); // ret void is legal
66 Copy = DAG.getCopyToReg(Op.getOperand(0), ARM::R0, Op.getOperand(2), SDOperand());
70 return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
73 static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
74 MachineFunction &MF = DAG.getMachineFunction();
75 SSARegMap *RegMap = MF.getSSARegMap();
76 std::vector<SDOperand> ArgValues;
77 SDOperand Root = Op.getOperand(0);
80 unsigned num_regs = 4;
82 static const unsigned REGS[] = {
83 ARM::R0, ARM::R1, ARM::R2, ARM::R3
86 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
89 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
90 assert (ObjectVT == MVT::i32);
92 assert(reg_idx < num_regs);
93 unsigned VReg = RegMap->createVirtualRegister(&ARM::IntRegsRegClass);
94 MF.addLiveIn(REGS[reg_idx], VReg);
95 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32);
98 ArgValues.push_back(ArgVal);
101 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
104 ArgValues.push_back(Root);
106 // Return the new list of results.
107 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
108 Op.Val->value_end());
109 return DAG.getNode(ISD::MERGE_VALUES, RetVT, ArgValues);
112 SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
113 switch (Op.getOpcode()) {
115 assert(0 && "Should not custom lower this!");
117 case ISD::FORMAL_ARGUMENTS:
118 return LowerFORMAL_ARGUMENTS(Op, DAG);
120 return LowerCALL(Op, DAG);
122 return LowerRET(Op, DAG);
126 //===----------------------------------------------------------------------===//
127 // Instruction Selector Implementation
128 //===----------------------------------------------------------------------===//
130 //===--------------------------------------------------------------------===//
131 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
132 /// instructions for SelectionDAG operations.
135 class ARMDAGToDAGISel : public SelectionDAGISel {
136 ARMTargetLowering Lowering;
139 ARMDAGToDAGISel(TargetMachine &TM)
140 : SelectionDAGISel(Lowering), Lowering(TM) {
143 void Select(SDOperand &Result, SDOperand Op);
144 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
146 // Include the pieces autogenerated from the target description.
147 #include "ARMGenDAGISel.inc"
150 void ARMDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
153 DAG.setRoot(SelectRoot(DAG.getRoot()));
154 assert(InFlightSet.empty() && "ISel InFlightSet has not been emptied!");
158 DAG.RemoveDeadNodes();
160 ScheduleAndEmitDAG(DAG);
163 void ARMDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
164 SelectCode(Result, Op);
167 } // end anonymous namespace
169 /// createARMISelDag - This pass converts a legalized DAG into a
170 /// ARM-specific DAG, ready for instruction scheduling.
172 FunctionPass *llvm::createARMISelDag(TargetMachine &TM) {
173 return new ARMDAGToDAGISel(TM);