1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "arm-isel"
16 #include "ARMAddressingModes.h"
17 #include "ARMTargetMachine.h"
18 #include "llvm/CallingConv.h"
19 #include "llvm/Constants.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/LLVMContext.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CodeGen/SelectionDAGISel.h"
29 #include "llvm/Target/TargetLowering.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Compiler.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
40 DisableShifterOp("disable-shifter-op", cl::Hidden,
41 cl::desc("Disable isel of shifter-op"),
44 //===--------------------------------------------------------------------===//
45 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
46 /// instructions for SelectionDAG operations.
51 AM2_BASE, // Simple AM2 (+-imm12)
52 AM2_SHOP // Shifter-op AM2
55 class ARMDAGToDAGISel : public SelectionDAGISel {
56 ARMBaseTargetMachine &TM;
58 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
59 /// make the right decision when generating code for different targets.
60 const ARMSubtarget *Subtarget;
63 explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm,
64 CodeGenOpt::Level OptLevel)
65 : SelectionDAGISel(tm, OptLevel), TM(tm),
66 Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
69 virtual const char *getPassName() const {
70 return "ARM Instruction Selection";
73 /// getI32Imm - Return a target constant of type i32 with the specified
75 inline SDValue getI32Imm(unsigned Imm) {
76 return CurDAG->getTargetConstant(Imm, MVT::i32);
79 SDNode *Select(SDNode *N);
81 bool isShifterOpProfitable(const SDValue &Shift,
82 ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
83 bool SelectShifterOperandReg(SDValue N, SDValue &A,
84 SDValue &B, SDValue &C);
85 bool SelectShiftShifterOperandReg(SDValue N, SDValue &A,
86 SDValue &B, SDValue &C);
87 bool SelectAddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
88 bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc);
90 AddrMode2Type SelectAddrMode2Worker(SDValue N, SDValue &Base,
91 SDValue &Offset, SDValue &Opc);
92 bool SelectAddrMode2Base(SDValue N, SDValue &Base, SDValue &Offset,
94 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_BASE;
97 bool SelectAddrMode2ShOp(SDValue N, SDValue &Base, SDValue &Offset,
99 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_SHOP;
102 bool SelectAddrMode2(SDValue N, SDValue &Base, SDValue &Offset,
104 SelectAddrMode2Worker(N, Base, Offset, Opc);
105 // return SelectAddrMode2ShOp(N, Base, Offset, Opc);
106 // This always matches one way or another.
110 bool SelectAddrMode2Offset(SDNode *Op, SDValue N,
111 SDValue &Offset, SDValue &Opc);
112 bool SelectAddrMode3(SDValue N, SDValue &Base,
113 SDValue &Offset, SDValue &Opc);
114 bool SelectAddrMode3Offset(SDNode *Op, SDValue N,
115 SDValue &Offset, SDValue &Opc);
116 bool SelectAddrMode5(SDValue N, SDValue &Base,
118 bool SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,SDValue &Align);
120 bool SelectAddrModePC(SDValue N, SDValue &Offset,
123 bool SelectThumbAddrModeRR(SDValue N, SDValue &Base, SDValue &Offset);
124 bool SelectThumbAddrModeRI5(SDValue N, unsigned Scale,
125 SDValue &Base, SDValue &OffImm,
127 bool SelectThumbAddrModeS1(SDValue N, SDValue &Base,
128 SDValue &OffImm, SDValue &Offset);
129 bool SelectThumbAddrModeS2(SDValue N, SDValue &Base,
130 SDValue &OffImm, SDValue &Offset);
131 bool SelectThumbAddrModeS4(SDValue N, SDValue &Base,
132 SDValue &OffImm, SDValue &Offset);
133 bool SelectThumbAddrModeSP(SDValue N, SDValue &Base, SDValue &OffImm);
135 bool SelectT2ShifterOperandReg(SDValue N,
136 SDValue &BaseReg, SDValue &Opc);
137 bool SelectT2AddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
138 bool SelectT2AddrModeImm8(SDValue N, SDValue &Base,
140 bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
142 bool SelectT2AddrModeSoReg(SDValue N, SDValue &Base,
143 SDValue &OffReg, SDValue &ShImm);
145 inline bool is_so_imm(unsigned Imm) const {
146 return ARM_AM::getSOImmVal(Imm) != -1;
149 inline bool is_so_imm_not(unsigned Imm) const {
150 return ARM_AM::getSOImmVal(~Imm) != -1;
153 inline bool is_t2_so_imm(unsigned Imm) const {
154 return ARM_AM::getT2SOImmVal(Imm) != -1;
157 inline bool is_t2_so_imm_not(unsigned Imm) const {
158 return ARM_AM::getT2SOImmVal(~Imm) != -1;
161 inline bool Pred_so_imm(SDNode *inN) const {
162 ConstantSDNode *N = cast<ConstantSDNode>(inN);
163 return is_so_imm(N->getZExtValue());
166 inline bool Pred_t2_so_imm(SDNode *inN) const {
167 ConstantSDNode *N = cast<ConstantSDNode>(inN);
168 return is_t2_so_imm(N->getZExtValue());
171 // Include the pieces autogenerated from the target description.
172 #include "ARMGenDAGISel.inc"
175 /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
177 SDNode *SelectARMIndexedLoad(SDNode *N);
178 SDNode *SelectT2IndexedLoad(SDNode *N);
180 /// SelectVLD - Select NEON load intrinsics. NumVecs should be
181 /// 1, 2, 3 or 4. The opcode arrays specify the instructions used for
182 /// loads of D registers and even subregs and odd subregs of Q registers.
183 /// For NumVecs <= 2, QOpcodes1 is not used.
184 SDNode *SelectVLD(SDNode *N, unsigned NumVecs, unsigned *DOpcodes,
185 unsigned *QOpcodes0, unsigned *QOpcodes1);
187 /// SelectVST - Select NEON store intrinsics. NumVecs should
188 /// be 1, 2, 3 or 4. The opcode arrays specify the instructions used for
189 /// stores of D registers and even subregs and odd subregs of Q registers.
190 /// For NumVecs <= 2, QOpcodes1 is not used.
191 SDNode *SelectVST(SDNode *N, unsigned NumVecs, unsigned *DOpcodes,
192 unsigned *QOpcodes0, unsigned *QOpcodes1);
194 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should
195 /// be 2, 3 or 4. The opcode arrays specify the instructions used for
196 /// load/store of D registers and Q registers.
197 SDNode *SelectVLDSTLane(SDNode *N, bool IsLoad, unsigned NumVecs,
198 unsigned *DOpcodes, unsigned *QOpcodes);
200 /// SelectVTBL - Select NEON VTBL and VTBX intrinsics. NumVecs should be 2,
201 /// 3 or 4. These are custom-selected so that a REG_SEQUENCE can be
202 /// generated to force the table registers to be consecutive.
203 SDNode *SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc);
205 /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM.
206 SDNode *SelectV6T2BitfieldExtractOp(SDNode *N, bool isSigned);
208 /// SelectCMOVOp - Select CMOV instructions for ARM.
209 SDNode *SelectCMOVOp(SDNode *N);
210 SDNode *SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
211 ARMCC::CondCodes CCVal, SDValue CCR,
213 SDNode *SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
214 ARMCC::CondCodes CCVal, SDValue CCR,
216 SDNode *SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
217 ARMCC::CondCodes CCVal, SDValue CCR,
219 SDNode *SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
220 ARMCC::CondCodes CCVal, SDValue CCR,
223 SDNode *SelectConcatVector(SDNode *N);
225 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
226 /// inline asm expressions.
227 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
229 std::vector<SDValue> &OutOps);
231 // Form pairs of consecutive S, D, or Q registers.
232 SDNode *PairSRegs(EVT VT, SDValue V0, SDValue V1);
233 SDNode *PairDRegs(EVT VT, SDValue V0, SDValue V1);
234 SDNode *PairQRegs(EVT VT, SDValue V0, SDValue V1);
236 // Form sequences of 4 consecutive S, D, or Q registers.
237 SDNode *QuadSRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
238 SDNode *QuadDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
239 SDNode *QuadQRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
241 // Get the alignment operand for a NEON VLD or VST instruction.
242 SDValue GetVLDSTAlign(SDValue Align, unsigned NumVecs, bool is64BitVector);
246 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
247 /// operand. If so Imm will receive the 32-bit value.
248 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
249 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
250 Imm = cast<ConstantSDNode>(N)->getZExtValue();
256 // isInt32Immediate - This method tests to see if a constant operand.
257 // If so Imm will receive the 32 bit value.
258 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
259 return isInt32Immediate(N.getNode(), Imm);
262 // isOpcWithIntImmediate - This method tests to see if the node is a specific
263 // opcode and that it has a immediate integer right operand.
264 // If so Imm will receive the 32 bit value.
265 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
266 return N->getOpcode() == Opc &&
267 isInt32Immediate(N->getOperand(1).getNode(), Imm);
271 bool ARMDAGToDAGISel::isShifterOpProfitable(const SDValue &Shift,
272 ARM_AM::ShiftOpc ShOpcVal,
274 if (!Subtarget->isCortexA9())
276 if (Shift.hasOneUse())
279 return ShOpcVal == ARM_AM::lsl && ShAmt == 2;
282 bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue N,
286 if (DisableShifterOp)
289 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
291 // Don't match base register only case. That is matched to a separate
292 // lower complexity pattern with explicit register operand.
293 if (ShOpcVal == ARM_AM::no_shift) return false;
295 BaseReg = N.getOperand(0);
296 unsigned ShImmVal = 0;
297 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
298 ShReg = CurDAG->getRegister(0, MVT::i32);
299 ShImmVal = RHS->getZExtValue() & 31;
301 ShReg = N.getOperand(1);
302 if (!isShifterOpProfitable(N, ShOpcVal, ShImmVal))
305 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
310 bool ARMDAGToDAGISel::SelectShiftShifterOperandReg(SDValue N,
314 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
316 // Don't match base register only case. That is matched to a separate
317 // lower complexity pattern with explicit register operand.
318 if (ShOpcVal == ARM_AM::no_shift) return false;
320 BaseReg = N.getOperand(0);
321 unsigned ShImmVal = 0;
322 // Do not check isShifterOpProfitable. This must return true.
323 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
324 ShReg = CurDAG->getRegister(0, MVT::i32);
325 ShImmVal = RHS->getZExtValue() & 31;
327 ShReg = N.getOperand(1);
329 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
334 bool ARMDAGToDAGISel::SelectAddrModeImm12(SDValue N,
337 // Match simple R + imm12 operands.
340 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
341 if (N.getOpcode() == ISD::FrameIndex) {
342 // Match frame index...
343 int FI = cast<FrameIndexSDNode>(N)->getIndex();
344 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
345 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
347 } else if (N.getOpcode() == ARMISD::Wrapper &&
348 !(Subtarget->useMovt() &&
349 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
350 Base = N.getOperand(0);
353 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
357 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
358 int RHSC = (int)RHS->getZExtValue();
359 if (N.getOpcode() == ISD::SUB)
362 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
363 Base = N.getOperand(0);
364 if (Base.getOpcode() == ISD::FrameIndex) {
365 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
366 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
368 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
375 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
381 bool ARMDAGToDAGISel::SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset,
383 if (N.getOpcode() == ISD::MUL &&
384 (!Subtarget->isCortexA9() || N.hasOneUse())) {
385 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
386 // X * [3,5,9] -> X + X * [2,4,8] etc.
387 int RHSC = (int)RHS->getZExtValue();
390 ARM_AM::AddrOpc AddSub = ARM_AM::add;
392 AddSub = ARM_AM::sub;
395 if (isPowerOf2_32(RHSC)) {
396 unsigned ShAmt = Log2_32(RHSC);
397 Base = Offset = N.getOperand(0);
398 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
407 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB)
410 // Leave simple R +/- imm12 operands for LDRi12
411 if (N.getOpcode() == ISD::ADD) {
412 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
413 int RHSC = (int)RHS->getZExtValue();
414 if ((RHSC >= 0 && RHSC < 0x1000) ||
415 (RHSC < 0 && RHSC > -0x1000)) // 12 bits.
420 if (Subtarget->isCortexA9() && !N.hasOneUse())
421 // Compute R +/- (R << N) and reuse it.
424 // Otherwise this is R +/- [possibly shifted] R.
425 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
426 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
429 Base = N.getOperand(0);
430 Offset = N.getOperand(1);
432 if (ShOpcVal != ARM_AM::no_shift) {
433 // Check to see if the RHS of the shift is a constant, if not, we can't fold
435 if (ConstantSDNode *Sh =
436 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
437 ShAmt = Sh->getZExtValue();
438 if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
439 Offset = N.getOperand(1).getOperand(0);
442 ShOpcVal = ARM_AM::no_shift;
445 ShOpcVal = ARM_AM::no_shift;
449 // Try matching (R shl C) + (R).
450 if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift &&
451 !(Subtarget->isCortexA9() || N.getOperand(0).hasOneUse())) {
452 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
453 if (ShOpcVal != ARM_AM::no_shift) {
454 // Check to see if the RHS of the shift is a constant, if not, we can't
456 if (ConstantSDNode *Sh =
457 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
458 ShAmt = Sh->getZExtValue();
459 if (!Subtarget->isCortexA9() ||
461 isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt))) {
462 Offset = N.getOperand(0).getOperand(0);
463 Base = N.getOperand(1);
466 ShOpcVal = ARM_AM::no_shift;
469 ShOpcVal = ARM_AM::no_shift;
474 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
484 AddrMode2Type ARMDAGToDAGISel::SelectAddrMode2Worker(SDValue N,
488 if (N.getOpcode() == ISD::MUL &&
489 (!Subtarget->isCortexA9() || N.hasOneUse())) {
490 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
491 // X * [3,5,9] -> X + X * [2,4,8] etc.
492 int RHSC = (int)RHS->getZExtValue();
495 ARM_AM::AddrOpc AddSub = ARM_AM::add;
497 AddSub = ARM_AM::sub;
500 if (isPowerOf2_32(RHSC)) {
501 unsigned ShAmt = Log2_32(RHSC);
502 Base = Offset = N.getOperand(0);
503 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
512 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
514 if (N.getOpcode() == ISD::FrameIndex) {
515 int FI = cast<FrameIndexSDNode>(N)->getIndex();
516 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
517 } else if (N.getOpcode() == ARMISD::Wrapper &&
518 !(Subtarget->useMovt() &&
519 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
520 Base = N.getOperand(0);
522 Offset = CurDAG->getRegister(0, MVT::i32);
523 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
529 // Match simple R +/- imm12 operands.
530 if (N.getOpcode() == ISD::ADD) {
531 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
532 int RHSC = (int)RHS->getZExtValue();
533 if ((RHSC >= 0 && RHSC < 0x1000) ||
534 (RHSC < 0 && RHSC > -0x1000)) { // 12 bits.
535 Base = N.getOperand(0);
536 if (Base.getOpcode() == ISD::FrameIndex) {
537 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
538 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
540 Offset = CurDAG->getRegister(0, MVT::i32);
542 ARM_AM::AddrOpc AddSub = ARM_AM::add;
544 AddSub = ARM_AM::sub;
547 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
555 if (Subtarget->isCortexA9() && !N.hasOneUse()) {
556 // Compute R +/- (R << N) and reuse it.
558 Offset = CurDAG->getRegister(0, MVT::i32);
559 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
565 // Otherwise this is R +/- [possibly shifted] R.
566 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
567 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
570 Base = N.getOperand(0);
571 Offset = N.getOperand(1);
573 if (ShOpcVal != ARM_AM::no_shift) {
574 // Check to see if the RHS of the shift is a constant, if not, we can't fold
576 if (ConstantSDNode *Sh =
577 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
578 ShAmt = Sh->getZExtValue();
579 if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
580 Offset = N.getOperand(1).getOperand(0);
583 ShOpcVal = ARM_AM::no_shift;
586 ShOpcVal = ARM_AM::no_shift;
590 // Try matching (R shl C) + (R).
591 if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift &&
592 !(Subtarget->isCortexA9() || N.getOperand(0).hasOneUse())) {
593 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
594 if (ShOpcVal != ARM_AM::no_shift) {
595 // Check to see if the RHS of the shift is a constant, if not, we can't
597 if (ConstantSDNode *Sh =
598 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
599 ShAmt = Sh->getZExtValue();
600 if (!Subtarget->isCortexA9() ||
602 isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt))) {
603 Offset = N.getOperand(0).getOperand(0);
604 Base = N.getOperand(1);
607 ShOpcVal = ARM_AM::no_shift;
610 ShOpcVal = ARM_AM::no_shift;
615 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
620 bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDNode *Op, SDValue N,
621 SDValue &Offset, SDValue &Opc) {
622 unsigned Opcode = Op->getOpcode();
623 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
624 ? cast<LoadSDNode>(Op)->getAddressingMode()
625 : cast<StoreSDNode>(Op)->getAddressingMode();
626 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
627 ? ARM_AM::add : ARM_AM::sub;
628 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
629 int Val = (int)C->getZExtValue();
630 if (Val >= 0 && Val < 0x1000) { // 12 bits.
631 Offset = CurDAG->getRegister(0, MVT::i32);
632 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
640 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
642 if (ShOpcVal != ARM_AM::no_shift) {
643 // Check to see if the RHS of the shift is a constant, if not, we can't fold
645 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
646 ShAmt = Sh->getZExtValue();
647 if (isShifterOpProfitable(N, ShOpcVal, ShAmt))
648 Offset = N.getOperand(0);
651 ShOpcVal = ARM_AM::no_shift;
654 ShOpcVal = ARM_AM::no_shift;
658 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
664 bool ARMDAGToDAGISel::SelectAddrMode3(SDValue N,
665 SDValue &Base, SDValue &Offset,
667 if (N.getOpcode() == ISD::SUB) {
668 // X - C is canonicalize to X + -C, no need to handle it here.
669 Base = N.getOperand(0);
670 Offset = N.getOperand(1);
671 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
675 if (N.getOpcode() != ISD::ADD) {
677 if (N.getOpcode() == ISD::FrameIndex) {
678 int FI = cast<FrameIndexSDNode>(N)->getIndex();
679 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
681 Offset = CurDAG->getRegister(0, MVT::i32);
682 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
686 // If the RHS is +/- imm8, fold into addr mode.
687 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
688 int RHSC = (int)RHS->getZExtValue();
689 if ((RHSC >= 0 && RHSC < 256) ||
690 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
691 Base = N.getOperand(0);
692 if (Base.getOpcode() == ISD::FrameIndex) {
693 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
694 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
696 Offset = CurDAG->getRegister(0, MVT::i32);
698 ARM_AM::AddrOpc AddSub = ARM_AM::add;
700 AddSub = ARM_AM::sub;
703 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
708 Base = N.getOperand(0);
709 Offset = N.getOperand(1);
710 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
714 bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N,
715 SDValue &Offset, SDValue &Opc) {
716 unsigned Opcode = Op->getOpcode();
717 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
718 ? cast<LoadSDNode>(Op)->getAddressingMode()
719 : cast<StoreSDNode>(Op)->getAddressingMode();
720 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
721 ? ARM_AM::add : ARM_AM::sub;
722 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
723 int Val = (int)C->getZExtValue();
724 if (Val >= 0 && Val < 256) {
725 Offset = CurDAG->getRegister(0, MVT::i32);
726 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
732 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
736 bool ARMDAGToDAGISel::SelectAddrMode5(SDValue N,
737 SDValue &Base, SDValue &Offset) {
738 if (N.getOpcode() != ISD::ADD) {
740 if (N.getOpcode() == ISD::FrameIndex) {
741 int FI = cast<FrameIndexSDNode>(N)->getIndex();
742 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
743 } else if (N.getOpcode() == ARMISD::Wrapper &&
744 !(Subtarget->useMovt() &&
745 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
746 Base = N.getOperand(0);
748 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
753 // If the RHS is +/- imm8, fold into addr mode.
754 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
755 int RHSC = (int)RHS->getZExtValue();
756 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied by 4.
758 if ((RHSC >= 0 && RHSC < 256) ||
759 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
760 Base = N.getOperand(0);
761 if (Base.getOpcode() == ISD::FrameIndex) {
762 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
763 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
766 ARM_AM::AddrOpc AddSub = ARM_AM::add;
768 AddSub = ARM_AM::sub;
771 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
779 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
784 bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,
788 unsigned Alignment = 0;
789 if (LSBaseSDNode *LSN = dyn_cast<LSBaseSDNode>(Parent)) {
790 // This case occurs only for VLD1-lane/dup and VST1-lane instructions.
791 // The maximum alignment is equal to the memory size being referenced.
792 unsigned LSNAlign = LSN->getAlignment();
793 unsigned MemSize = LSN->getMemoryVT().getSizeInBits() / 8;
794 if (LSNAlign > MemSize && MemSize > 1)
797 // All other uses of addrmode6 are for intrinsics. For now just record
798 // the raw alignment value; it will be refined later based on the legal
799 // alignment operands for the intrinsic.
800 Alignment = cast<MemIntrinsicSDNode>(Parent)->getAlignment();
803 Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
807 bool ARMDAGToDAGISel::SelectAddrModePC(SDValue N,
808 SDValue &Offset, SDValue &Label) {
809 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
810 Offset = N.getOperand(0);
811 SDValue N1 = N.getOperand(1);
812 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
819 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue N,
820 SDValue &Base, SDValue &Offset){
821 // FIXME dl should come from the parent load or store, not the address
822 if (N.getOpcode() != ISD::ADD) {
823 ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
824 if (!NC || !NC->isNullValue())
831 Base = N.getOperand(0);
832 Offset = N.getOperand(1);
837 ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDValue N,
838 unsigned Scale, SDValue &Base,
839 SDValue &OffImm, SDValue &Offset) {
841 SDValue TmpBase, TmpOffImm;
842 if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
843 return false; // We want to select tLDRspi / tSTRspi instead.
844 if (N.getOpcode() == ARMISD::Wrapper &&
845 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
846 return false; // We want to select tLDRpci instead.
849 if (N.getOpcode() != ISD::ADD) {
850 if (N.getOpcode() == ARMISD::Wrapper &&
851 !(Subtarget->useMovt() &&
852 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
853 Base = N.getOperand(0);
857 Offset = CurDAG->getRegister(0, MVT::i32);
858 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
862 // Thumb does not have [sp, r] address mode.
863 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
864 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
865 if ((LHSR && LHSR->getReg() == ARM::SP) ||
866 (RHSR && RHSR->getReg() == ARM::SP)) {
868 Offset = CurDAG->getRegister(0, MVT::i32);
869 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
873 // If the RHS is + imm5 * scale, fold into addr mode.
874 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
875 int RHSC = (int)RHS->getZExtValue();
876 if ((RHSC & (Scale-1)) == 0) { // The constant is implicitly multiplied.
878 if (RHSC >= 0 && RHSC < 32) {
879 Base = N.getOperand(0);
880 Offset = CurDAG->getRegister(0, MVT::i32);
881 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
887 Base = N.getOperand(0);
888 Offset = N.getOperand(1);
889 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
893 bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDValue N,
894 SDValue &Base, SDValue &OffImm,
896 return SelectThumbAddrModeRI5(N, 1, Base, OffImm, Offset);
899 bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDValue N,
900 SDValue &Base, SDValue &OffImm,
902 return SelectThumbAddrModeRI5(N, 2, Base, OffImm, Offset);
905 bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDValue N,
906 SDValue &Base, SDValue &OffImm,
908 return SelectThumbAddrModeRI5(N, 4, Base, OffImm, Offset);
911 bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue N,
912 SDValue &Base, SDValue &OffImm) {
913 if (N.getOpcode() == ISD::FrameIndex) {
914 int FI = cast<FrameIndexSDNode>(N)->getIndex();
915 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
916 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
920 if (N.getOpcode() != ISD::ADD)
923 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
924 if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
925 (LHSR && LHSR->getReg() == ARM::SP)) {
926 // If the RHS is + imm8 * scale, fold into addr mode.
927 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
928 int RHSC = (int)RHS->getZExtValue();
929 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied.
931 if (RHSC >= 0 && RHSC < 256) {
932 Base = N.getOperand(0);
933 if (Base.getOpcode() == ISD::FrameIndex) {
934 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
935 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
937 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
947 bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue N, SDValue &BaseReg,
949 if (DisableShifterOp)
952 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
954 // Don't match base register only case. That is matched to a separate
955 // lower complexity pattern with explicit register operand.
956 if (ShOpcVal == ARM_AM::no_shift) return false;
958 BaseReg = N.getOperand(0);
959 unsigned ShImmVal = 0;
960 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
961 ShImmVal = RHS->getZExtValue() & 31;
962 Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
969 bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue N,
970 SDValue &Base, SDValue &OffImm) {
971 // Match simple R + imm12 operands.
974 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
975 if (N.getOpcode() == ISD::FrameIndex) {
976 // Match frame index...
977 int FI = cast<FrameIndexSDNode>(N)->getIndex();
978 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
979 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
981 } else if (N.getOpcode() == ARMISD::Wrapper &&
982 !(Subtarget->useMovt() &&
983 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
984 Base = N.getOperand(0);
985 if (Base.getOpcode() == ISD::TargetConstantPool)
986 return false; // We want to select t2LDRpci instead.
989 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
993 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
994 if (SelectT2AddrModeImm8(N, Base, OffImm))
995 // Let t2LDRi8 handle (R - imm8).
998 int RHSC = (int)RHS->getZExtValue();
999 if (N.getOpcode() == ISD::SUB)
1002 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
1003 Base = N.getOperand(0);
1004 if (Base.getOpcode() == ISD::FrameIndex) {
1005 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1006 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1008 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1015 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1019 bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue N,
1020 SDValue &Base, SDValue &OffImm) {
1021 // Match simple R - imm8 operands.
1022 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::SUB) {
1023 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1024 int RHSC = (int)RHS->getSExtValue();
1025 if (N.getOpcode() == ISD::SUB)
1028 if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative)
1029 Base = N.getOperand(0);
1030 if (Base.getOpcode() == ISD::FrameIndex) {
1031 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1032 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1034 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1043 bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
1045 unsigned Opcode = Op->getOpcode();
1046 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
1047 ? cast<LoadSDNode>(Op)->getAddressingMode()
1048 : cast<StoreSDNode>(Op)->getAddressingMode();
1049 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N)) {
1050 int RHSC = (int)RHS->getZExtValue();
1051 if (RHSC >= 0 && RHSC < 0x100) { // 8 bits.
1052 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
1053 ? CurDAG->getTargetConstant(RHSC, MVT::i32)
1054 : CurDAG->getTargetConstant(-RHSC, MVT::i32);
1062 bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue N,
1064 SDValue &OffReg, SDValue &ShImm) {
1065 // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.
1066 if (N.getOpcode() != ISD::ADD)
1069 // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8.
1070 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1071 int RHSC = (int)RHS->getZExtValue();
1072 if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned)
1074 else if (RHSC < 0 && RHSC >= -255) // 8 bits
1078 if (Subtarget->isCortexA9() && !N.hasOneUse()) {
1079 // Compute R + (R << [1,2,3]) and reuse it.
1084 // Look for (R + R) or (R + (R << [1,2,3])).
1086 Base = N.getOperand(0);
1087 OffReg = N.getOperand(1);
1089 // Swap if it is ((R << c) + R).
1090 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg);
1091 if (ShOpcVal != ARM_AM::lsl) {
1092 ShOpcVal = ARM_AM::getShiftOpcForNode(Base);
1093 if (ShOpcVal == ARM_AM::lsl)
1094 std::swap(Base, OffReg);
1097 if (ShOpcVal == ARM_AM::lsl) {
1098 // Check to see if the RHS of the shift is a constant, if not, we can't fold
1100 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
1101 ShAmt = Sh->getZExtValue();
1102 if (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt))
1103 OffReg = OffReg.getOperand(0);
1106 ShOpcVal = ARM_AM::no_shift;
1109 ShOpcVal = ARM_AM::no_shift;
1113 ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
1118 //===--------------------------------------------------------------------===//
1120 /// getAL - Returns a ARMCC::AL immediate node.
1121 static inline SDValue getAL(SelectionDAG *CurDAG) {
1122 return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
1125 SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDNode *N) {
1126 LoadSDNode *LD = cast<LoadSDNode>(N);
1127 ISD::MemIndexedMode AM = LD->getAddressingMode();
1128 if (AM == ISD::UNINDEXED)
1131 EVT LoadedVT = LD->getMemoryVT();
1132 SDValue Offset, AMOpc;
1133 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1134 unsigned Opcode = 0;
1136 if (LoadedVT == MVT::i32 &&
1137 SelectAddrMode2Offset(N, LD->getOffset(), Offset, AMOpc)) {
1138 Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST;
1140 } else if (LoadedVT == MVT::i16 &&
1141 SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1143 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
1144 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
1145 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
1146 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
1147 if (LD->getExtensionType() == ISD::SEXTLOAD) {
1148 if (SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1150 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
1153 if (SelectAddrMode2Offset(N, LD->getOffset(), Offset, AMOpc)) {
1155 Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST;
1161 SDValue Chain = LD->getChain();
1162 SDValue Base = LD->getBasePtr();
1163 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
1164 CurDAG->getRegister(0, MVT::i32), Chain };
1165 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32,
1166 MVT::Other, Ops, 6);
1172 SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDNode *N) {
1173 LoadSDNode *LD = cast<LoadSDNode>(N);
1174 ISD::MemIndexedMode AM = LD->getAddressingMode();
1175 if (AM == ISD::UNINDEXED)
1178 EVT LoadedVT = LD->getMemoryVT();
1179 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
1181 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1182 unsigned Opcode = 0;
1184 if (SelectT2AddrModeImm8Offset(N, LD->getOffset(), Offset)) {
1185 switch (LoadedVT.getSimpleVT().SimpleTy) {
1187 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
1191 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
1193 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
1198 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
1200 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
1209 SDValue Chain = LD->getChain();
1210 SDValue Base = LD->getBasePtr();
1211 SDValue Ops[]= { Base, Offset, getAL(CurDAG),
1212 CurDAG->getRegister(0, MVT::i32), Chain };
1213 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32,
1214 MVT::Other, Ops, 5);
1220 /// PairSRegs - Form a D register from a pair of S registers.
1222 SDNode *ARMDAGToDAGISel::PairSRegs(EVT VT, SDValue V0, SDValue V1) {
1223 DebugLoc dl = V0.getNode()->getDebugLoc();
1224 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1225 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1226 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
1227 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
1230 /// PairDRegs - Form a quad register from a pair of D registers.
1232 SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) {
1233 DebugLoc dl = V0.getNode()->getDebugLoc();
1234 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1235 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1236 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
1237 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
1240 /// PairQRegs - Form 4 consecutive D registers from a pair of Q registers.
1242 SDNode *ARMDAGToDAGISel::PairQRegs(EVT VT, SDValue V0, SDValue V1) {
1243 DebugLoc dl = V0.getNode()->getDebugLoc();
1244 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1245 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1246 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
1247 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
1250 /// QuadSRegs - Form 4 consecutive S registers.
1252 SDNode *ARMDAGToDAGISel::QuadSRegs(EVT VT, SDValue V0, SDValue V1,
1253 SDValue V2, SDValue V3) {
1254 DebugLoc dl = V0.getNode()->getDebugLoc();
1255 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1256 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1257 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, MVT::i32);
1258 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::ssub_3, MVT::i32);
1259 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 };
1260 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
1263 /// QuadDRegs - Form 4 consecutive D registers.
1265 SDNode *ARMDAGToDAGISel::QuadDRegs(EVT VT, SDValue V0, SDValue V1,
1266 SDValue V2, SDValue V3) {
1267 DebugLoc dl = V0.getNode()->getDebugLoc();
1268 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1269 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1270 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, MVT::i32);
1271 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, MVT::i32);
1272 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 };
1273 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
1276 /// QuadQRegs - Form 4 consecutive Q registers.
1278 SDNode *ARMDAGToDAGISel::QuadQRegs(EVT VT, SDValue V0, SDValue V1,
1279 SDValue V2, SDValue V3) {
1280 DebugLoc dl = V0.getNode()->getDebugLoc();
1281 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1282 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1283 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, MVT::i32);
1284 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, MVT::i32);
1285 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 };
1286 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
1289 /// GetVLDSTAlign - Get the alignment (in bytes) for the alignment operand
1290 /// of a NEON VLD or VST instruction. The supported values depend on the
1291 /// number of registers being loaded.
1292 SDValue ARMDAGToDAGISel::GetVLDSTAlign(SDValue Align, unsigned NumVecs,
1293 bool is64BitVector) {
1294 unsigned NumRegs = NumVecs;
1295 if (!is64BitVector && NumVecs < 3)
1298 unsigned Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1299 if (Alignment >= 32 && NumRegs == 4)
1301 else if (Alignment >= 16 && (NumRegs == 2 || NumRegs == 4))
1303 else if (Alignment >= 8)
1308 return CurDAG->getTargetConstant(Alignment, MVT::i32);
1311 SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, unsigned NumVecs,
1312 unsigned *DOpcodes, unsigned *QOpcodes0,
1313 unsigned *QOpcodes1) {
1314 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range");
1315 DebugLoc dl = N->getDebugLoc();
1317 SDValue MemAddr, Align;
1318 if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, Align))
1321 SDValue Chain = N->getOperand(0);
1322 EVT VT = N->getValueType(0);
1323 bool is64BitVector = VT.is64BitVector();
1324 Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1326 unsigned OpcodeIndex;
1327 switch (VT.getSimpleVT().SimpleTy) {
1328 default: llvm_unreachable("unhandled vld type");
1329 // Double-register operations:
1330 case MVT::v8i8: OpcodeIndex = 0; break;
1331 case MVT::v4i16: OpcodeIndex = 1; break;
1333 case MVT::v2i32: OpcodeIndex = 2; break;
1334 case MVT::v1i64: OpcodeIndex = 3; break;
1335 // Quad-register operations:
1336 case MVT::v16i8: OpcodeIndex = 0; break;
1337 case MVT::v8i16: OpcodeIndex = 1; break;
1339 case MVT::v4i32: OpcodeIndex = 2; break;
1340 case MVT::v2i64: OpcodeIndex = 3;
1341 assert(NumVecs == 1 && "v2i64 type only supported for VLD1");
1349 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1352 ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts);
1355 SDValue Pred = getAL(CurDAG);
1356 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1358 if (is64BitVector) {
1359 unsigned Opc = DOpcodes[OpcodeIndex];
1360 const SDValue Ops[] = { MemAddr, Align, Pred, Reg0, Chain };
1361 SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTy, MVT::Other, Ops, 5);
1365 SuperReg = SDValue(VLd, 0);
1366 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1367 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1368 SDValue D = CurDAG->getTargetExtractSubreg(ARM::dsub_0+Vec,
1370 ReplaceUses(SDValue(N, Vec), D);
1372 ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1));
1377 // Quad registers are directly supported for VLD1 and VLD2,
1378 // loading pairs of D regs.
1379 unsigned Opc = QOpcodes0[OpcodeIndex];
1380 const SDValue Ops[] = { MemAddr, Align, Pred, Reg0, Chain };
1381 SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTy, MVT::Other, Ops, 5);
1385 SuperReg = SDValue(VLd, 0);
1386 Chain = SDValue(VLd, 1);
1389 // Otherwise, quad registers are loaded with two separate instructions,
1390 // where one loads the even registers and the other loads the odd registers.
1391 EVT AddrTy = MemAddr.getValueType();
1393 // Load the even subregs.
1394 unsigned Opc = QOpcodes0[OpcodeIndex];
1396 SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy), 0);
1397 const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain };
1399 CurDAG->getMachineNode(Opc, dl, ResTy, AddrTy, MVT::Other, OpsA, 7);
1400 Chain = SDValue(VLdA, 2);
1402 // Load the odd subregs.
1403 Opc = QOpcodes1[OpcodeIndex];
1404 const SDValue OpsB[] = { SDValue(VLdA, 1), Align, Reg0, SDValue(VLdA, 0),
1405 Pred, Reg0, Chain };
1407 CurDAG->getMachineNode(Opc, dl, ResTy, AddrTy, MVT::Other, OpsB, 7);
1408 SuperReg = SDValue(VLdB, 0);
1409 Chain = SDValue(VLdB, 2);
1412 // Extract out the Q registers.
1413 assert(ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1414 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1415 SDValue Q = CurDAG->getTargetExtractSubreg(ARM::qsub_0+Vec,
1417 ReplaceUses(SDValue(N, Vec), Q);
1419 ReplaceUses(SDValue(N, NumVecs), Chain);
1423 SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, unsigned NumVecs,
1424 unsigned *DOpcodes, unsigned *QOpcodes0,
1425 unsigned *QOpcodes1) {
1426 assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range");
1427 DebugLoc dl = N->getDebugLoc();
1429 SDValue MemAddr, Align;
1430 if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, Align))
1433 SDValue Chain = N->getOperand(0);
1434 EVT VT = N->getOperand(3).getValueType();
1435 bool is64BitVector = VT.is64BitVector();
1436 Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1438 unsigned OpcodeIndex;
1439 switch (VT.getSimpleVT().SimpleTy) {
1440 default: llvm_unreachable("unhandled vst type");
1441 // Double-register operations:
1442 case MVT::v8i8: OpcodeIndex = 0; break;
1443 case MVT::v4i16: OpcodeIndex = 1; break;
1445 case MVT::v2i32: OpcodeIndex = 2; break;
1446 case MVT::v1i64: OpcodeIndex = 3; break;
1447 // Quad-register operations:
1448 case MVT::v16i8: OpcodeIndex = 0; break;
1449 case MVT::v8i16: OpcodeIndex = 1; break;
1451 case MVT::v4i32: OpcodeIndex = 2; break;
1452 case MVT::v2i64: OpcodeIndex = 3;
1453 assert(NumVecs == 1 && "v2i64 type only supported for VST1");
1457 SDValue Pred = getAL(CurDAG);
1458 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1460 SmallVector<SDValue, 7> Ops;
1461 Ops.push_back(MemAddr);
1462 Ops.push_back(Align);
1464 if (is64BitVector) {
1466 Ops.push_back(N->getOperand(3));
1469 SDValue V0 = N->getOperand(0+3);
1470 SDValue V1 = N->getOperand(1+3);
1472 // Form a REG_SEQUENCE to force register allocation.
1474 RegSeq = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1476 SDValue V2 = N->getOperand(2+3);
1477 // If it's a vld3, form a quad D-register and leave the last part as
1479 SDValue V3 = (NumVecs == 3)
1480 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1481 : N->getOperand(3+3);
1482 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1484 Ops.push_back(RegSeq);
1486 Ops.push_back(Pred);
1487 Ops.push_back(Reg0); // predicate register
1488 Ops.push_back(Chain);
1489 unsigned Opc = DOpcodes[OpcodeIndex];
1490 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 6);
1494 // Quad registers are directly supported for VST1 and VST2.
1495 unsigned Opc = QOpcodes0[OpcodeIndex];
1497 Ops.push_back(N->getOperand(3));
1499 // Form a QQ register.
1500 SDValue Q0 = N->getOperand(3);
1501 SDValue Q1 = N->getOperand(4);
1502 Ops.push_back(SDValue(PairQRegs(MVT::v4i64, Q0, Q1), 0));
1504 Ops.push_back(Pred);
1505 Ops.push_back(Reg0); // predicate register
1506 Ops.push_back(Chain);
1507 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 6);
1510 // Otherwise, quad registers are stored with two separate instructions,
1511 // where one stores the even registers and the other stores the odd registers.
1513 // Form the QQQQ REG_SEQUENCE.
1514 SDValue V0 = N->getOperand(0+3);
1515 SDValue V1 = N->getOperand(1+3);
1516 SDValue V2 = N->getOperand(2+3);
1517 SDValue V3 = (NumVecs == 3)
1518 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1519 : N->getOperand(3+3);
1520 SDValue RegSeq = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);
1522 // Store the even D registers.
1523 Ops.push_back(Reg0); // post-access address offset
1524 Ops.push_back(RegSeq);
1525 Ops.push_back(Pred);
1526 Ops.push_back(Reg0); // predicate register
1527 Ops.push_back(Chain);
1528 unsigned Opc = QOpcodes0[OpcodeIndex];
1529 SDNode *VStA = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
1530 MVT::Other, Ops.data(), 7);
1531 Chain = SDValue(VStA, 1);
1533 // Store the odd D registers.
1534 Ops[0] = SDValue(VStA, 0); // MemAddr
1536 Opc = QOpcodes1[OpcodeIndex];
1537 SDNode *VStB = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
1538 MVT::Other, Ops.data(), 7);
1539 Chain = SDValue(VStB, 1);
1540 ReplaceUses(SDValue(N, 0), Chain);
1544 SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
1545 unsigned NumVecs, unsigned *DOpcodes,
1546 unsigned *QOpcodes) {
1547 assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
1548 DebugLoc dl = N->getDebugLoc();
1550 SDValue MemAddr, Align;
1551 if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, Align))
1554 SDValue Chain = N->getOperand(0);
1556 cast<ConstantSDNode>(N->getOperand(NumVecs+3))->getZExtValue();
1557 EVT VT = IsLoad ? N->getValueType(0) : N->getOperand(3).getValueType();
1558 bool is64BitVector = VT.is64BitVector();
1560 unsigned Alignment = 0;
1562 Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1563 unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
1564 if (Alignment > NumBytes)
1565 Alignment = NumBytes;
1566 // Alignment must be a power of two; make sure of that.
1567 Alignment = (Alignment & -Alignment);
1571 Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
1573 unsigned OpcodeIndex;
1574 switch (VT.getSimpleVT().SimpleTy) {
1575 default: llvm_unreachable("unhandled vld/vst lane type");
1576 // Double-register operations:
1577 case MVT::v8i8: OpcodeIndex = 0; break;
1578 case MVT::v4i16: OpcodeIndex = 1; break;
1580 case MVT::v2i32: OpcodeIndex = 2; break;
1581 // Quad-register operations:
1582 case MVT::v8i16: OpcodeIndex = 0; break;
1584 case MVT::v4i32: OpcodeIndex = 1; break;
1587 SDValue Pred = getAL(CurDAG);
1588 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1590 SmallVector<SDValue, 7> Ops;
1591 Ops.push_back(MemAddr);
1592 Ops.push_back(Align);
1594 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1595 QOpcodes[OpcodeIndex]);
1598 SDValue V0 = N->getOperand(0+3);
1599 SDValue V1 = N->getOperand(1+3);
1602 SuperReg = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1604 SuperReg = SDValue(PairQRegs(MVT::v4i64, V0, V1), 0);
1606 SDValue V2 = N->getOperand(2+3);
1607 SDValue V3 = (NumVecs == 3)
1608 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1609 : N->getOperand(3+3);
1611 SuperReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1613 SuperReg = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);
1615 Ops.push_back(SuperReg);
1616 Ops.push_back(getI32Imm(Lane));
1617 Ops.push_back(Pred);
1618 Ops.push_back(Reg0);
1619 Ops.push_back(Chain);
1622 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 7);
1625 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1628 ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts);
1630 SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTy, MVT::Other,
1632 SuperReg = SDValue(VLdLn, 0);
1633 Chain = SDValue(VLdLn, 1);
1635 // Extract the subregisters.
1636 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1637 assert(ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1638 unsigned SubIdx = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;
1639 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1640 ReplaceUses(SDValue(N, Vec),
1641 CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, SuperReg));
1642 ReplaceUses(SDValue(N, NumVecs), Chain);
1646 SDNode *ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs,
1648 assert(NumVecs >= 2 && NumVecs <= 4 && "VTBL NumVecs out-of-range");
1649 DebugLoc dl = N->getDebugLoc();
1650 EVT VT = N->getValueType(0);
1651 unsigned FirstTblReg = IsExt ? 2 : 1;
1653 // Form a REG_SEQUENCE to force register allocation.
1655 SDValue V0 = N->getOperand(FirstTblReg + 0);
1656 SDValue V1 = N->getOperand(FirstTblReg + 1);
1658 RegSeq = SDValue(PairDRegs(MVT::v16i8, V0, V1), 0);
1660 SDValue V2 = N->getOperand(FirstTblReg + 2);
1661 // If it's a vtbl3, form a quad D-register and leave the last part as
1663 SDValue V3 = (NumVecs == 3)
1664 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1665 : N->getOperand(FirstTblReg + 3);
1666 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1669 SmallVector<SDValue, 6> Ops;
1671 Ops.push_back(N->getOperand(1));
1672 Ops.push_back(RegSeq);
1673 Ops.push_back(N->getOperand(FirstTblReg + NumVecs));
1674 Ops.push_back(getAL(CurDAG)); // predicate
1675 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // predicate register
1676 return CurDAG->getMachineNode(Opc, dl, VT, Ops.data(), Ops.size());
1679 SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N,
1681 if (!Subtarget->hasV6T2Ops())
1684 unsigned Opc = isSigned ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX)
1685 : (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX);
1688 // For unsigned extracts, check for a shift right and mask
1689 unsigned And_imm = 0;
1690 if (N->getOpcode() == ISD::AND) {
1691 if (isOpcWithIntImmediate(N, ISD::AND, And_imm)) {
1693 // The immediate is a mask of the low bits iff imm & (imm+1) == 0
1694 if (And_imm & (And_imm + 1))
1697 unsigned Srl_imm = 0;
1698 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL,
1700 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
1702 unsigned Width = CountTrailingOnes_32(And_imm);
1703 unsigned LSB = Srl_imm;
1704 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1705 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1706 CurDAG->getTargetConstant(LSB, MVT::i32),
1707 CurDAG->getTargetConstant(Width, MVT::i32),
1708 getAL(CurDAG), Reg0 };
1709 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1715 // Otherwise, we're looking for a shift of a shift
1716 unsigned Shl_imm = 0;
1717 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, Shl_imm)) {
1718 assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!");
1719 unsigned Srl_imm = 0;
1720 if (isInt32Immediate(N->getOperand(1), Srl_imm)) {
1721 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
1722 unsigned Width = 32 - Srl_imm;
1723 int LSB = Srl_imm - Shl_imm;
1726 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1727 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1728 CurDAG->getTargetConstant(LSB, MVT::i32),
1729 CurDAG->getTargetConstant(Width, MVT::i32),
1730 getAL(CurDAG), Reg0 };
1731 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1737 SDNode *ARMDAGToDAGISel::
1738 SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1739 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1742 if (SelectT2ShifterOperandReg(TrueVal, CPTmp0, CPTmp1)) {
1743 unsigned SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue();
1744 unsigned SOShOp = ARM_AM::getSORegShOp(SOVal);
1747 case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break;
1748 case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break;
1749 case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break;
1750 case ARM_AM::ror: Opc = ARM::t2MOVCCror; break;
1752 llvm_unreachable("Unknown so_reg opcode!");
1756 CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32);
1757 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1758 SDValue Ops[] = { FalseVal, CPTmp0, SOShImm, CC, CCR, InFlag };
1759 return CurDAG->SelectNodeTo(N, Opc, MVT::i32,Ops, 6);
1764 SDNode *ARMDAGToDAGISel::
1765 SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1766 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1770 if (SelectShifterOperandReg(TrueVal, CPTmp0, CPTmp1, CPTmp2)) {
1771 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1772 SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CPTmp2, CC, CCR, InFlag };
1773 return CurDAG->SelectNodeTo(N, ARM::MOVCCs, MVT::i32, Ops, 7);
1778 SDNode *ARMDAGToDAGISel::
1779 SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1780 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1781 ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
1782 if (!T || !TrueVal.getNode()->hasOneUse())
1786 unsigned TrueImm = T->getZExtValue();
1787 if (is_t2_so_imm(TrueImm)) {
1788 Opc = ARM::t2MOVCCi;
1789 } else if (TrueImm <= 0xffff) {
1790 Opc = ARM::t2MOVCCi16;
1791 } else if (is_t2_so_imm_not(TrueImm)) {
1793 Opc = ARM::t2MVNCCi;
1794 } else if (TrueVal.getNode()->hasOneUse() && Subtarget->hasV6T2Ops()) {
1796 Opc = ARM::t2MOVCCi32imm;
1800 SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
1801 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1802 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
1803 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1809 SDNode *ARMDAGToDAGISel::
1810 SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1811 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1812 ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
1817 unsigned TrueImm = T->getZExtValue();
1818 bool isSoImm = is_so_imm(TrueImm);
1821 } else if (Subtarget->hasV6T2Ops() && TrueImm <= 0xffff) {
1822 Opc = ARM::MOVCCi16;
1823 } else if (is_so_imm_not(TrueImm)) {
1826 } else if (TrueVal.getNode()->hasOneUse() &&
1827 (Subtarget->hasV6T2Ops() || ARM_AM::isSOImmTwoPartVal(TrueImm))) {
1829 Opc = ARM::MOVCCi32imm;
1833 SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
1834 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1835 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
1836 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1842 SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDNode *N) {
1843 EVT VT = N->getValueType(0);
1844 SDValue FalseVal = N->getOperand(0);
1845 SDValue TrueVal = N->getOperand(1);
1846 SDValue CC = N->getOperand(2);
1847 SDValue CCR = N->getOperand(3);
1848 SDValue InFlag = N->getOperand(4);
1849 assert(CC.getOpcode() == ISD::Constant);
1850 assert(CCR.getOpcode() == ISD::Register);
1851 ARMCC::CondCodes CCVal =
1852 (ARMCC::CondCodes)cast<ConstantSDNode>(CC)->getZExtValue();
1854 if (!Subtarget->isThumb1Only() && VT == MVT::i32) {
1855 // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1856 // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1857 // Pattern complexity = 18 cost = 1 size = 0
1861 if (Subtarget->isThumb()) {
1862 SDNode *Res = SelectT2CMOVShiftOp(N, FalseVal, TrueVal,
1863 CCVal, CCR, InFlag);
1865 Res = SelectT2CMOVShiftOp(N, TrueVal, FalseVal,
1866 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1870 SDNode *Res = SelectARMCMOVShiftOp(N, FalseVal, TrueVal,
1871 CCVal, CCR, InFlag);
1873 Res = SelectARMCMOVShiftOp(N, TrueVal, FalseVal,
1874 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1879 // Pattern: (ARMcmov:i32 GPR:i32:$false,
1880 // (imm:i32)<<P:Pred_so_imm>>:$true,
1882 // Emits: (MOVCCi:i32 GPR:i32:$false,
1883 // (so_imm:i32 (imm:i32):$true), (imm:i32):$cc)
1884 // Pattern complexity = 10 cost = 1 size = 0
1885 if (Subtarget->isThumb()) {
1886 SDNode *Res = SelectT2CMOVImmOp(N, FalseVal, TrueVal,
1887 CCVal, CCR, InFlag);
1889 Res = SelectT2CMOVImmOp(N, TrueVal, FalseVal,
1890 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1894 SDNode *Res = SelectARMCMOVImmOp(N, FalseVal, TrueVal,
1895 CCVal, CCR, InFlag);
1897 Res = SelectARMCMOVImmOp(N, TrueVal, FalseVal,
1898 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1904 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1905 // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1906 // Pattern complexity = 6 cost = 1 size = 0
1908 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1909 // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1910 // Pattern complexity = 6 cost = 11 size = 0
1912 // Also FCPYScc and FCPYDcc.
1913 SDValue Tmp2 = CurDAG->getTargetConstant(CCVal, MVT::i32);
1914 SDValue Ops[] = { FalseVal, TrueVal, Tmp2, CCR, InFlag };
1916 switch (VT.getSimpleVT().SimpleTy) {
1917 default: assert(false && "Illegal conditional move type!");
1920 Opc = Subtarget->isThumb()
1921 ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo)
1931 return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
1934 SDNode *ARMDAGToDAGISel::SelectConcatVector(SDNode *N) {
1935 // The only time a CONCAT_VECTORS operation can have legal types is when
1936 // two 64-bit vectors are concatenated to a 128-bit vector.
1937 EVT VT = N->getValueType(0);
1938 if (!VT.is128BitVector() || N->getNumOperands() != 2)
1939 llvm_unreachable("unexpected CONCAT_VECTORS");
1940 DebugLoc dl = N->getDebugLoc();
1941 SDValue V0 = N->getOperand(0);
1942 SDValue V1 = N->getOperand(1);
1943 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1944 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1945 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
1946 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
1949 SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
1950 DebugLoc dl = N->getDebugLoc();
1952 if (N->isMachineOpcode())
1953 return NULL; // Already selected.
1955 switch (N->getOpcode()) {
1957 case ISD::Constant: {
1958 unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
1960 if (Subtarget->hasThumb2())
1961 // Thumb2-aware targets have the MOVT instruction, so all immediates can
1962 // be done with MOV + MOVT, at worst.
1965 if (Subtarget->isThumb()) {
1966 UseCP = (Val > 255 && // MOV
1967 ~Val > 255 && // MOV + MVN
1968 !ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL
1970 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
1971 ARM_AM::getSOImmVal(~Val) == -1 && // MVN
1972 !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs.
1977 CurDAG->getTargetConstantPool(ConstantInt::get(
1978 Type::getInt32Ty(*CurDAG->getContext()), Val),
1979 TLI.getPointerTy());
1982 if (Subtarget->isThumb1Only()) {
1983 SDValue Pred = getAL(CurDAG);
1984 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
1985 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
1986 ResNode = CurDAG->getMachineNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other,
1991 CurDAG->getTargetConstant(0, MVT::i32),
1993 CurDAG->getRegister(0, MVT::i32),
1994 CurDAG->getEntryNode()
1996 ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
1999 ReplaceUses(SDValue(N, 0), SDValue(ResNode, 0));
2003 // Other cases are autogenerated.
2006 case ISD::FrameIndex: {
2007 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
2008 int FI = cast<FrameIndexSDNode>(N)->getIndex();
2009 SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
2010 if (Subtarget->isThumb1Only()) {
2011 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
2012 CurDAG->getTargetConstant(0, MVT::i32));
2014 unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
2015 ARM::t2ADDri : ARM::ADDri);
2016 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
2017 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2018 CurDAG->getRegister(0, MVT::i32) };
2019 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2023 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2027 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, true))
2031 if (Subtarget->isThumb1Only())
2033 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
2034 unsigned RHSV = C->getZExtValue();
2036 if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
2037 unsigned ShImm = Log2_32(RHSV-1);
2040 SDValue V = N->getOperand(0);
2041 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2042 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2043 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2044 if (Subtarget->isThumb()) {
2045 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2046 return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
2048 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2049 return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7);
2052 if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
2053 unsigned ShImm = Log2_32(RHSV+1);
2056 SDValue V = N->getOperand(0);
2057 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2058 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2059 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2060 if (Subtarget->isThumb()) {
2061 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2062 return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 6);
2064 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2065 return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7);
2071 // Check for unsigned bitfield extract
2072 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2075 // (and (or x, c2), c1) and top 16-bits of c1 and c2 match, lower 16-bits
2076 // of c1 are 0xffff, and lower 16-bit of c2 are 0. That is, the top 16-bits
2077 // are entirely contributed by c2 and lower 16-bits are entirely contributed
2078 // by x. That's equal to (or (and x, 0xffff), (and c1, 0xffff0000)).
2079 // Select it to: "movt x, ((c1 & 0xffff) >> 16)
2080 EVT VT = N->getValueType(0);
2083 unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2())
2085 : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0);
2088 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2089 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2092 if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) {
2093 SDValue N2 = N0.getOperand(1);
2094 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2097 unsigned N1CVal = N1C->getZExtValue();
2098 unsigned N2CVal = N2C->getZExtValue();
2099 if ((N1CVal & 0xffff0000U) == (N2CVal & 0xffff0000U) &&
2100 (N1CVal & 0xffffU) == 0xffffU &&
2101 (N2CVal & 0xffffU) == 0x0U) {
2102 SDValue Imm16 = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16,
2104 SDValue Ops[] = { N0.getOperand(0), Imm16,
2105 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2106 return CurDAG->getMachineNode(Opc, dl, VT, Ops, 4);
2111 case ARMISD::VMOVRRD:
2112 return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32,
2113 N->getOperand(0), getAL(CurDAG),
2114 CurDAG->getRegister(0, MVT::i32));
2115 case ISD::UMUL_LOHI: {
2116 if (Subtarget->isThumb1Only())
2118 if (Subtarget->isThumb()) {
2119 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2120 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2121 CurDAG->getRegister(0, MVT::i32) };
2122 return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32,Ops,4);
2124 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2125 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2126 CurDAG->getRegister(0, MVT::i32) };
2127 return CurDAG->getMachineNode(ARM::UMULL, dl, MVT::i32, MVT::i32, Ops, 5);
2130 case ISD::SMUL_LOHI: {
2131 if (Subtarget->isThumb1Only())
2133 if (Subtarget->isThumb()) {
2134 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2135 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2136 return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32,Ops,4);
2138 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2139 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2140 CurDAG->getRegister(0, MVT::i32) };
2141 return CurDAG->getMachineNode(ARM::SMULL, dl, MVT::i32, MVT::i32, Ops, 5);
2145 SDNode *ResNode = 0;
2146 if (Subtarget->isThumb() && Subtarget->hasThumb2())
2147 ResNode = SelectT2IndexedLoad(N);
2149 ResNode = SelectARMIndexedLoad(N);
2152 // Other cases are autogenerated.
2155 case ARMISD::BRCOND: {
2156 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2157 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2158 // Pattern complexity = 6 cost = 1 size = 0
2160 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2161 // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
2162 // Pattern complexity = 6 cost = 1 size = 0
2164 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2165 // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2166 // Pattern complexity = 6 cost = 1 size = 0
2168 unsigned Opc = Subtarget->isThumb() ?
2169 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
2170 SDValue Chain = N->getOperand(0);
2171 SDValue N1 = N->getOperand(1);
2172 SDValue N2 = N->getOperand(2);
2173 SDValue N3 = N->getOperand(3);
2174 SDValue InFlag = N->getOperand(4);
2175 assert(N1.getOpcode() == ISD::BasicBlock);
2176 assert(N2.getOpcode() == ISD::Constant);
2177 assert(N3.getOpcode() == ISD::Register);
2179 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
2180 cast<ConstantSDNode>(N2)->getZExtValue()),
2182 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
2183 SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,
2185 Chain = SDValue(ResNode, 0);
2186 if (N->getNumValues() == 2) {
2187 InFlag = SDValue(ResNode, 1);
2188 ReplaceUses(SDValue(N, 1), InFlag);
2190 ReplaceUses(SDValue(N, 0),
2191 SDValue(Chain.getNode(), Chain.getResNo()));
2195 return SelectCMOVOp(N);
2196 case ARMISD::CNEG: {
2197 EVT VT = N->getValueType(0);
2198 SDValue N0 = N->getOperand(0);
2199 SDValue N1 = N->getOperand(1);
2200 SDValue N2 = N->getOperand(2);
2201 SDValue N3 = N->getOperand(3);
2202 SDValue InFlag = N->getOperand(4);
2203 assert(N2.getOpcode() == ISD::Constant);
2204 assert(N3.getOpcode() == ISD::Register);
2206 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
2207 cast<ConstantSDNode>(N2)->getZExtValue()),
2209 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
2211 switch (VT.getSimpleVT().SimpleTy) {
2212 default: assert(false && "Illegal conditional move type!");
2221 return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
2224 case ARMISD::VZIP: {
2226 EVT VT = N->getValueType(0);
2227 switch (VT.getSimpleVT().SimpleTy) {
2228 default: return NULL;
2229 case MVT::v8i8: Opc = ARM::VZIPd8; break;
2230 case MVT::v4i16: Opc = ARM::VZIPd16; break;
2232 case MVT::v2i32: Opc = ARM::VZIPd32; break;
2233 case MVT::v16i8: Opc = ARM::VZIPq8; break;
2234 case MVT::v8i16: Opc = ARM::VZIPq16; break;
2236 case MVT::v4i32: Opc = ARM::VZIPq32; break;
2238 SDValue Pred = getAL(CurDAG);
2239 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2240 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2241 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2243 case ARMISD::VUZP: {
2245 EVT VT = N->getValueType(0);
2246 switch (VT.getSimpleVT().SimpleTy) {
2247 default: return NULL;
2248 case MVT::v8i8: Opc = ARM::VUZPd8; break;
2249 case MVT::v4i16: Opc = ARM::VUZPd16; break;
2251 case MVT::v2i32: Opc = ARM::VUZPd32; break;
2252 case MVT::v16i8: Opc = ARM::VUZPq8; break;
2253 case MVT::v8i16: Opc = ARM::VUZPq16; break;
2255 case MVT::v4i32: Opc = ARM::VUZPq32; break;
2257 SDValue Pred = getAL(CurDAG);
2258 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2259 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2260 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2262 case ARMISD::VTRN: {
2264 EVT VT = N->getValueType(0);
2265 switch (VT.getSimpleVT().SimpleTy) {
2266 default: return NULL;
2267 case MVT::v8i8: Opc = ARM::VTRNd8; break;
2268 case MVT::v4i16: Opc = ARM::VTRNd16; break;
2270 case MVT::v2i32: Opc = ARM::VTRNd32; break;
2271 case MVT::v16i8: Opc = ARM::VTRNq8; break;
2272 case MVT::v8i16: Opc = ARM::VTRNq16; break;
2274 case MVT::v4i32: Opc = ARM::VTRNq32; break;
2276 SDValue Pred = getAL(CurDAG);
2277 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2278 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2279 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2281 case ARMISD::BUILD_VECTOR: {
2282 EVT VecVT = N->getValueType(0);
2283 EVT EltVT = VecVT.getVectorElementType();
2284 unsigned NumElts = VecVT.getVectorNumElements();
2285 if (EltVT == MVT::f64) {
2286 assert(NumElts == 2 && "unexpected type for BUILD_VECTOR");
2287 return PairDRegs(VecVT, N->getOperand(0), N->getOperand(1));
2289 assert(EltVT == MVT::f32 && "unexpected type for BUILD_VECTOR");
2291 return PairSRegs(VecVT, N->getOperand(0), N->getOperand(1));
2292 assert(NumElts == 4 && "unexpected type for BUILD_VECTOR");
2293 return QuadSRegs(VecVT, N->getOperand(0), N->getOperand(1),
2294 N->getOperand(2), N->getOperand(3));
2297 case ISD::INTRINSIC_VOID:
2298 case ISD::INTRINSIC_W_CHAIN: {
2299 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
2304 case Intrinsic::arm_neon_vld1: {
2305 unsigned DOpcodes[] = { ARM::VLD1d8, ARM::VLD1d16,
2306 ARM::VLD1d32, ARM::VLD1d64 };
2307 unsigned QOpcodes[] = { ARM::VLD1q8Pseudo, ARM::VLD1q16Pseudo,
2308 ARM::VLD1q32Pseudo, ARM::VLD1q64Pseudo };
2309 return SelectVLD(N, 1, DOpcodes, QOpcodes, 0);
2312 case Intrinsic::arm_neon_vld2: {
2313 unsigned DOpcodes[] = { ARM::VLD2d8Pseudo, ARM::VLD2d16Pseudo,
2314 ARM::VLD2d32Pseudo, ARM::VLD1q64Pseudo };
2315 unsigned QOpcodes[] = { ARM::VLD2q8Pseudo, ARM::VLD2q16Pseudo,
2316 ARM::VLD2q32Pseudo };
2317 return SelectVLD(N, 2, DOpcodes, QOpcodes, 0);
2320 case Intrinsic::arm_neon_vld3: {
2321 unsigned DOpcodes[] = { ARM::VLD3d8Pseudo, ARM::VLD3d16Pseudo,
2322 ARM::VLD3d32Pseudo, ARM::VLD1d64TPseudo };
2323 unsigned QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
2324 ARM::VLD3q16Pseudo_UPD,
2325 ARM::VLD3q32Pseudo_UPD };
2326 unsigned QOpcodes1[] = { ARM::VLD3q8oddPseudo_UPD,
2327 ARM::VLD3q16oddPseudo_UPD,
2328 ARM::VLD3q32oddPseudo_UPD };
2329 return SelectVLD(N, 3, DOpcodes, QOpcodes0, QOpcodes1);
2332 case Intrinsic::arm_neon_vld4: {
2333 unsigned DOpcodes[] = { ARM::VLD4d8Pseudo, ARM::VLD4d16Pseudo,
2334 ARM::VLD4d32Pseudo, ARM::VLD1d64QPseudo };
2335 unsigned QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
2336 ARM::VLD4q16Pseudo_UPD,
2337 ARM::VLD4q32Pseudo_UPD };
2338 unsigned QOpcodes1[] = { ARM::VLD4q8oddPseudo_UPD,
2339 ARM::VLD4q16oddPseudo_UPD,
2340 ARM::VLD4q32oddPseudo_UPD };
2341 return SelectVLD(N, 4, DOpcodes, QOpcodes0, QOpcodes1);
2344 case Intrinsic::arm_neon_vld2lane: {
2345 unsigned DOpcodes[] = { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd16Pseudo,
2346 ARM::VLD2LNd32Pseudo };
2347 unsigned QOpcodes[] = { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq32Pseudo };
2348 return SelectVLDSTLane(N, true, 2, DOpcodes, QOpcodes);
2351 case Intrinsic::arm_neon_vld3lane: {
2352 unsigned DOpcodes[] = { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd16Pseudo,
2353 ARM::VLD3LNd32Pseudo };
2354 unsigned QOpcodes[] = { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq32Pseudo };
2355 return SelectVLDSTLane(N, true, 3, DOpcodes, QOpcodes);
2358 case Intrinsic::arm_neon_vld4lane: {
2359 unsigned DOpcodes[] = { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd16Pseudo,
2360 ARM::VLD4LNd32Pseudo };
2361 unsigned QOpcodes[] = { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq32Pseudo };
2362 return SelectVLDSTLane(N, true, 4, DOpcodes, QOpcodes);
2365 case Intrinsic::arm_neon_vst1: {
2366 unsigned DOpcodes[] = { ARM::VST1d8, ARM::VST1d16,
2367 ARM::VST1d32, ARM::VST1d64 };
2368 unsigned QOpcodes[] = { ARM::VST1q8Pseudo, ARM::VST1q16Pseudo,
2369 ARM::VST1q32Pseudo, ARM::VST1q64Pseudo };
2370 return SelectVST(N, 1, DOpcodes, QOpcodes, 0);
2373 case Intrinsic::arm_neon_vst2: {
2374 unsigned DOpcodes[] = { ARM::VST2d8Pseudo, ARM::VST2d16Pseudo,
2375 ARM::VST2d32Pseudo, ARM::VST1q64Pseudo };
2376 unsigned QOpcodes[] = { ARM::VST2q8Pseudo, ARM::VST2q16Pseudo,
2377 ARM::VST2q32Pseudo };
2378 return SelectVST(N, 2, DOpcodes, QOpcodes, 0);
2381 case Intrinsic::arm_neon_vst3: {
2382 unsigned DOpcodes[] = { ARM::VST3d8Pseudo, ARM::VST3d16Pseudo,
2383 ARM::VST3d32Pseudo, ARM::VST1d64TPseudo };
2384 unsigned QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
2385 ARM::VST3q16Pseudo_UPD,
2386 ARM::VST3q32Pseudo_UPD };
2387 unsigned QOpcodes1[] = { ARM::VST3q8oddPseudo_UPD,
2388 ARM::VST3q16oddPseudo_UPD,
2389 ARM::VST3q32oddPseudo_UPD };
2390 return SelectVST(N, 3, DOpcodes, QOpcodes0, QOpcodes1);
2393 case Intrinsic::arm_neon_vst4: {
2394 unsigned DOpcodes[] = { ARM::VST4d8Pseudo, ARM::VST4d16Pseudo,
2395 ARM::VST4d32Pseudo, ARM::VST1d64QPseudo };
2396 unsigned QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
2397 ARM::VST4q16Pseudo_UPD,
2398 ARM::VST4q32Pseudo_UPD };
2399 unsigned QOpcodes1[] = { ARM::VST4q8oddPseudo_UPD,
2400 ARM::VST4q16oddPseudo_UPD,
2401 ARM::VST4q32oddPseudo_UPD };
2402 return SelectVST(N, 4, DOpcodes, QOpcodes0, QOpcodes1);
2405 case Intrinsic::arm_neon_vst2lane: {
2406 unsigned DOpcodes[] = { ARM::VST2LNd8Pseudo, ARM::VST2LNd16Pseudo,
2407 ARM::VST2LNd32Pseudo };
2408 unsigned QOpcodes[] = { ARM::VST2LNq16Pseudo, ARM::VST2LNq32Pseudo };
2409 return SelectVLDSTLane(N, false, 2, DOpcodes, QOpcodes);
2412 case Intrinsic::arm_neon_vst3lane: {
2413 unsigned DOpcodes[] = { ARM::VST3LNd8Pseudo, ARM::VST3LNd16Pseudo,
2414 ARM::VST3LNd32Pseudo };
2415 unsigned QOpcodes[] = { ARM::VST3LNq16Pseudo, ARM::VST3LNq32Pseudo };
2416 return SelectVLDSTLane(N, false, 3, DOpcodes, QOpcodes);
2419 case Intrinsic::arm_neon_vst4lane: {
2420 unsigned DOpcodes[] = { ARM::VST4LNd8Pseudo, ARM::VST4LNd16Pseudo,
2421 ARM::VST4LNd32Pseudo };
2422 unsigned QOpcodes[] = { ARM::VST4LNq16Pseudo, ARM::VST4LNq32Pseudo };
2423 return SelectVLDSTLane(N, false, 4, DOpcodes, QOpcodes);
2429 case ISD::INTRINSIC_WO_CHAIN: {
2430 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
2435 case Intrinsic::arm_neon_vtbl2:
2436 return SelectVTBL(N, false, 2, ARM::VTBL2Pseudo);
2437 case Intrinsic::arm_neon_vtbl3:
2438 return SelectVTBL(N, false, 3, ARM::VTBL3Pseudo);
2439 case Intrinsic::arm_neon_vtbl4:
2440 return SelectVTBL(N, false, 4, ARM::VTBL4Pseudo);
2442 case Intrinsic::arm_neon_vtbx2:
2443 return SelectVTBL(N, true, 2, ARM::VTBX2Pseudo);
2444 case Intrinsic::arm_neon_vtbx3:
2445 return SelectVTBL(N, true, 3, ARM::VTBX3Pseudo);
2446 case Intrinsic::arm_neon_vtbx4:
2447 return SelectVTBL(N, true, 4, ARM::VTBX4Pseudo);
2452 case ISD::CONCAT_VECTORS:
2453 return SelectConcatVector(N);
2456 return SelectCode(N);
2459 bool ARMDAGToDAGISel::
2460 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
2461 std::vector<SDValue> &OutOps) {
2462 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
2463 // Require the address to be in a register. That is safe for all ARM
2464 // variants and it is hard to do anything much smarter without knowing
2465 // how the operand is used.
2466 OutOps.push_back(Op);
2470 /// createARMISelDag - This pass converts a legalized DAG into a
2471 /// ARM-specific DAG, ready for instruction scheduling.
2473 FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
2474 CodeGenOpt::Level OptLevel) {
2475 return new ARMDAGToDAGISel(TM, OptLevel);