1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMISelLowering.h"
18 #include "ARMTargetMachine.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/Constants.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/Intrinsics.h"
24 #include "llvm/LLVMContext.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/SelectionDAGISel.h"
30 #include "llvm/Target/TargetLowering.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Support/Compiler.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
39 static const unsigned arm_dsubreg_0 = 5;
40 static const unsigned arm_dsubreg_1 = 6;
42 //===--------------------------------------------------------------------===//
43 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
44 /// instructions for SelectionDAG operations.
47 class ARMDAGToDAGISel : public SelectionDAGISel {
48 ARMBaseTargetMachine &TM;
50 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
51 /// make the right decision when generating code for different targets.
52 const ARMSubtarget *Subtarget;
55 explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm)
56 : SelectionDAGISel(tm), TM(tm),
57 Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
60 virtual const char *getPassName() const {
61 return "ARM Instruction Selection";
64 /// getI32Imm - Return a target constant with the specified value, of type i32.
65 inline SDValue getI32Imm(unsigned Imm) {
66 return CurDAG->getTargetConstant(Imm, MVT::i32);
69 SDNode *Select(SDValue Op);
70 virtual void InstructionSelect();
71 bool SelectShifterOperandReg(SDValue Op, SDValue N, SDValue &A,
72 SDValue &B, SDValue &C);
73 bool SelectAddrMode2(SDValue Op, SDValue N, SDValue &Base,
74 SDValue &Offset, SDValue &Opc);
75 bool SelectAddrMode2Offset(SDValue Op, SDValue N,
76 SDValue &Offset, SDValue &Opc);
77 bool SelectAddrMode3(SDValue Op, SDValue N, SDValue &Base,
78 SDValue &Offset, SDValue &Opc);
79 bool SelectAddrMode3Offset(SDValue Op, SDValue N,
80 SDValue &Offset, SDValue &Opc);
81 bool SelectAddrMode5(SDValue Op, SDValue N, SDValue &Base,
83 bool SelectAddrMode6(SDValue Op, SDValue N, SDValue &Addr, SDValue &Update,
86 bool SelectAddrModePC(SDValue Op, SDValue N, SDValue &Offset,
89 bool SelectThumbAddrModeRR(SDValue Op, SDValue N, SDValue &Base,
91 bool SelectThumbAddrModeRI5(SDValue Op, SDValue N, unsigned Scale,
92 SDValue &Base, SDValue &OffImm,
94 bool SelectThumbAddrModeS1(SDValue Op, SDValue N, SDValue &Base,
95 SDValue &OffImm, SDValue &Offset);
96 bool SelectThumbAddrModeS2(SDValue Op, SDValue N, SDValue &Base,
97 SDValue &OffImm, SDValue &Offset);
98 bool SelectThumbAddrModeS4(SDValue Op, SDValue N, SDValue &Base,
99 SDValue &OffImm, SDValue &Offset);
100 bool SelectThumbAddrModeSP(SDValue Op, SDValue N, SDValue &Base,
103 bool SelectT2ShifterOperandReg(SDValue Op, SDValue N,
104 SDValue &BaseReg, SDValue &Opc);
105 bool SelectT2AddrModeImm12(SDValue Op, SDValue N, SDValue &Base,
107 bool SelectT2AddrModeImm8(SDValue Op, SDValue N, SDValue &Base,
109 bool SelectT2AddrModeImm8Offset(SDValue Op, SDValue N,
111 bool SelectT2AddrModeImm8s4(SDValue Op, SDValue N, SDValue &Base,
113 bool SelectT2AddrModeSoReg(SDValue Op, SDValue N, SDValue &Base,
114 SDValue &OffReg, SDValue &ShImm);
116 // Include the pieces autogenerated from the target description.
117 #include "ARMGenDAGISel.inc"
120 /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
122 SDNode *SelectARMIndexedLoad(SDValue Op);
123 SDNode *SelectT2IndexedLoad(SDValue Op);
126 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
127 /// inline asm expressions.
128 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
130 std::vector<SDValue> &OutOps);
134 void ARMDAGToDAGISel::InstructionSelect() {
138 CurDAG->RemoveDeadNodes();
141 bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue Op,
146 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
148 // Don't match base register only case. That is matched to a separate
149 // lower complexity pattern with explicit register operand.
150 if (ShOpcVal == ARM_AM::no_shift) return false;
152 BaseReg = N.getOperand(0);
153 unsigned ShImmVal = 0;
154 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
155 ShReg = CurDAG->getRegister(0, MVT::i32);
156 ShImmVal = RHS->getZExtValue() & 31;
158 ShReg = N.getOperand(1);
160 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
165 bool ARMDAGToDAGISel::SelectAddrMode2(SDValue Op, SDValue N,
166 SDValue &Base, SDValue &Offset,
168 if (N.getOpcode() == ISD::MUL) {
169 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
170 // X * [3,5,9] -> X + X * [2,4,8] etc.
171 int RHSC = (int)RHS->getZExtValue();
174 ARM_AM::AddrOpc AddSub = ARM_AM::add;
176 AddSub = ARM_AM::sub;
179 if (isPowerOf2_32(RHSC)) {
180 unsigned ShAmt = Log2_32(RHSC);
181 Base = Offset = N.getOperand(0);
182 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
191 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
193 if (N.getOpcode() == ISD::FrameIndex) {
194 int FI = cast<FrameIndexSDNode>(N)->getIndex();
195 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
196 } else if (N.getOpcode() == ARMISD::Wrapper) {
197 Base = N.getOperand(0);
199 Offset = CurDAG->getRegister(0, MVT::i32);
200 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
206 // Match simple R +/- imm12 operands.
207 if (N.getOpcode() == ISD::ADD)
208 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
209 int RHSC = (int)RHS->getZExtValue();
210 if ((RHSC >= 0 && RHSC < 0x1000) ||
211 (RHSC < 0 && RHSC > -0x1000)) { // 12 bits.
212 Base = N.getOperand(0);
213 if (Base.getOpcode() == ISD::FrameIndex) {
214 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
215 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
217 Offset = CurDAG->getRegister(0, MVT::i32);
219 ARM_AM::AddrOpc AddSub = ARM_AM::add;
221 AddSub = ARM_AM::sub;
224 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
231 // Otherwise this is R +/- [possibly shifted] R
232 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
233 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
236 Base = N.getOperand(0);
237 Offset = N.getOperand(1);
239 if (ShOpcVal != ARM_AM::no_shift) {
240 // Check to see if the RHS of the shift is a constant, if not, we can't fold
242 if (ConstantSDNode *Sh =
243 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
244 ShAmt = Sh->getZExtValue();
245 Offset = N.getOperand(1).getOperand(0);
247 ShOpcVal = ARM_AM::no_shift;
251 // Try matching (R shl C) + (R).
252 if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift) {
253 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
254 if (ShOpcVal != ARM_AM::no_shift) {
255 // Check to see if the RHS of the shift is a constant, if not, we can't
257 if (ConstantSDNode *Sh =
258 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
259 ShAmt = Sh->getZExtValue();
260 Offset = N.getOperand(0).getOperand(0);
261 Base = N.getOperand(1);
263 ShOpcVal = ARM_AM::no_shift;
268 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
273 bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDValue Op, SDValue N,
274 SDValue &Offset, SDValue &Opc) {
275 unsigned Opcode = Op.getOpcode();
276 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
277 ? cast<LoadSDNode>(Op)->getAddressingMode()
278 : cast<StoreSDNode>(Op)->getAddressingMode();
279 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
280 ? ARM_AM::add : ARM_AM::sub;
281 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
282 int Val = (int)C->getZExtValue();
283 if (Val >= 0 && Val < 0x1000) { // 12 bits.
284 Offset = CurDAG->getRegister(0, MVT::i32);
285 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
293 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
295 if (ShOpcVal != ARM_AM::no_shift) {
296 // Check to see if the RHS of the shift is a constant, if not, we can't fold
298 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
299 ShAmt = Sh->getZExtValue();
300 Offset = N.getOperand(0);
302 ShOpcVal = ARM_AM::no_shift;
306 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
312 bool ARMDAGToDAGISel::SelectAddrMode3(SDValue Op, SDValue N,
313 SDValue &Base, SDValue &Offset,
315 if (N.getOpcode() == ISD::SUB) {
316 // X - C is canonicalize to X + -C, no need to handle it here.
317 Base = N.getOperand(0);
318 Offset = N.getOperand(1);
319 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
323 if (N.getOpcode() != ISD::ADD) {
325 if (N.getOpcode() == ISD::FrameIndex) {
326 int FI = cast<FrameIndexSDNode>(N)->getIndex();
327 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
329 Offset = CurDAG->getRegister(0, MVT::i32);
330 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
334 // If the RHS is +/- imm8, fold into addr mode.
335 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
336 int RHSC = (int)RHS->getZExtValue();
337 if ((RHSC >= 0 && RHSC < 256) ||
338 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
339 Base = N.getOperand(0);
340 if (Base.getOpcode() == ISD::FrameIndex) {
341 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
342 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
344 Offset = CurDAG->getRegister(0, MVT::i32);
346 ARM_AM::AddrOpc AddSub = ARM_AM::add;
348 AddSub = ARM_AM::sub;
351 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
356 Base = N.getOperand(0);
357 Offset = N.getOperand(1);
358 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
362 bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDValue Op, SDValue N,
363 SDValue &Offset, SDValue &Opc) {
364 unsigned Opcode = Op.getOpcode();
365 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
366 ? cast<LoadSDNode>(Op)->getAddressingMode()
367 : cast<StoreSDNode>(Op)->getAddressingMode();
368 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
369 ? ARM_AM::add : ARM_AM::sub;
370 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
371 int Val = (int)C->getZExtValue();
372 if (Val >= 0 && Val < 256) {
373 Offset = CurDAG->getRegister(0, MVT::i32);
374 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
380 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
385 bool ARMDAGToDAGISel::SelectAddrMode5(SDValue Op, SDValue N,
386 SDValue &Base, SDValue &Offset) {
387 if (N.getOpcode() != ISD::ADD) {
389 if (N.getOpcode() == ISD::FrameIndex) {
390 int FI = cast<FrameIndexSDNode>(N)->getIndex();
391 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
392 } else if (N.getOpcode() == ARMISD::Wrapper) {
393 Base = N.getOperand(0);
395 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
400 // If the RHS is +/- imm8, fold into addr mode.
401 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
402 int RHSC = (int)RHS->getZExtValue();
403 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied by 4.
405 if ((RHSC >= 0 && RHSC < 256) ||
406 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
407 Base = N.getOperand(0);
408 if (Base.getOpcode() == ISD::FrameIndex) {
409 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
410 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
413 ARM_AM::AddrOpc AddSub = ARM_AM::add;
415 AddSub = ARM_AM::sub;
418 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
426 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
431 bool ARMDAGToDAGISel::SelectAddrMode6(SDValue Op, SDValue N,
432 SDValue &Addr, SDValue &Update,
435 // The optional writeback is handled in ARMLoadStoreOpt.
436 Update = CurDAG->getRegister(0, MVT::i32);
437 Opc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(false), MVT::i32);
441 bool ARMDAGToDAGISel::SelectAddrModePC(SDValue Op, SDValue N,
442 SDValue &Offset, SDValue &Label) {
443 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
444 Offset = N.getOperand(0);
445 SDValue N1 = N.getOperand(1);
446 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
453 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue Op, SDValue N,
454 SDValue &Base, SDValue &Offset){
455 // FIXME dl should come from the parent load or store, not the address
456 DebugLoc dl = Op.getDebugLoc();
457 if (N.getOpcode() != ISD::ADD) {
458 ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
459 if (!NC || NC->getZExtValue() != 0)
466 Base = N.getOperand(0);
467 Offset = N.getOperand(1);
472 ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDValue Op, SDValue N,
473 unsigned Scale, SDValue &Base,
474 SDValue &OffImm, SDValue &Offset) {
476 SDValue TmpBase, TmpOffImm;
477 if (SelectThumbAddrModeSP(Op, N, TmpBase, TmpOffImm))
478 return false; // We want to select tLDRspi / tSTRspi instead.
479 if (N.getOpcode() == ARMISD::Wrapper &&
480 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
481 return false; // We want to select tLDRpci instead.
484 if (N.getOpcode() != ISD::ADD) {
485 Base = (N.getOpcode() == ARMISD::Wrapper) ? N.getOperand(0) : N;
486 Offset = CurDAG->getRegister(0, MVT::i32);
487 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
491 // Thumb does not have [sp, r] address mode.
492 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
493 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
494 if ((LHSR && LHSR->getReg() == ARM::SP) ||
495 (RHSR && RHSR->getReg() == ARM::SP)) {
497 Offset = CurDAG->getRegister(0, MVT::i32);
498 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
502 // If the RHS is + imm5 * scale, fold into addr mode.
503 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
504 int RHSC = (int)RHS->getZExtValue();
505 if ((RHSC & (Scale-1)) == 0) { // The constant is implicitly multiplied.
507 if (RHSC >= 0 && RHSC < 32) {
508 Base = N.getOperand(0);
509 Offset = CurDAG->getRegister(0, MVT::i32);
510 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
516 Base = N.getOperand(0);
517 Offset = N.getOperand(1);
518 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
522 bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDValue Op, SDValue N,
523 SDValue &Base, SDValue &OffImm,
525 return SelectThumbAddrModeRI5(Op, N, 1, Base, OffImm, Offset);
528 bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDValue Op, SDValue N,
529 SDValue &Base, SDValue &OffImm,
531 return SelectThumbAddrModeRI5(Op, N, 2, Base, OffImm, Offset);
534 bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDValue Op, SDValue N,
535 SDValue &Base, SDValue &OffImm,
537 return SelectThumbAddrModeRI5(Op, N, 4, Base, OffImm, Offset);
540 bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue Op, SDValue N,
541 SDValue &Base, SDValue &OffImm) {
542 if (N.getOpcode() == ISD::FrameIndex) {
543 int FI = cast<FrameIndexSDNode>(N)->getIndex();
544 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
545 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
549 if (N.getOpcode() != ISD::ADD)
552 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
553 if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
554 (LHSR && LHSR->getReg() == ARM::SP)) {
555 // If the RHS is + imm8 * scale, fold into addr mode.
556 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
557 int RHSC = (int)RHS->getZExtValue();
558 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied.
560 if (RHSC >= 0 && RHSC < 256) {
561 Base = N.getOperand(0);
562 if (Base.getOpcode() == ISD::FrameIndex) {
563 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
564 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
566 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
576 bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue Op, SDValue N,
579 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
581 // Don't match base register only case. That is matched to a separate
582 // lower complexity pattern with explicit register operand.
583 if (ShOpcVal == ARM_AM::no_shift) return false;
585 BaseReg = N.getOperand(0);
586 unsigned ShImmVal = 0;
587 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
588 ShImmVal = RHS->getZExtValue() & 31;
589 Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
596 bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue Op, SDValue N,
597 SDValue &Base, SDValue &OffImm) {
598 // Match simple R + imm12 operands.
599 if (N.getOpcode() != ISD::ADD)
602 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
603 int RHSC = (int)RHS->getZExtValue();
604 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits.
605 Base = N.getOperand(0);
606 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
614 bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue Op, SDValue N,
615 SDValue &Base, SDValue &OffImm) {
616 if ((N.getOpcode() == ISD::ADD) || (N.getOpcode() == ISD::SUB)) {
617 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
618 int RHSC = (int)RHS->getSExtValue();
619 if (N.getOpcode() == ISD::SUB)
622 if ((RHSC >= -255) && (RHSC <= 255)) { // sign + 8 bits.
623 Base = N.getOperand(0);
624 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
627 } else if (N.getOpcode() == ISD::SUB) {
629 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
637 bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDValue Op, SDValue N,
639 unsigned Opcode = Op.getOpcode();
640 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
641 ? cast<LoadSDNode>(Op)->getAddressingMode()
642 : cast<StoreSDNode>(Op)->getAddressingMode();
643 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N)) {
644 int RHSC = (int)RHS->getZExtValue();
645 if (RHSC >= 0 && RHSC < 0x100) { // 8 bits.
646 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
647 ? CurDAG->getTargetConstant(RHSC, MVT::i32)
648 : CurDAG->getTargetConstant(-RHSC, MVT::i32);
656 bool ARMDAGToDAGISel::SelectT2AddrModeImm8s4(SDValue Op, SDValue N,
657 SDValue &Base, SDValue &OffImm) {
658 if (N.getOpcode() == ISD::ADD) {
659 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
660 int RHSC = (int)RHS->getZExtValue();
661 if (((RHSC & 0x3) == 0) &&
662 ((RHSC >= 0 && RHSC < 0x400) || (RHSC < 0 && RHSC > -0x400))) { // 8 bits.
663 Base = N.getOperand(0);
664 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
668 } else if (N.getOpcode() == ISD::SUB) {
669 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
670 int RHSC = (int)RHS->getZExtValue();
671 if (((RHSC & 0x3) == 0) && (RHSC >= 0 && RHSC < 0x400)) { // 8 bits.
672 Base = N.getOperand(0);
673 OffImm = CurDAG->getTargetConstant(-RHSC, MVT::i32);
682 bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue Op, SDValue N,
684 SDValue &OffReg, SDValue &ShImm) {
686 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
688 if (N.getOpcode() == ISD::FrameIndex) {
689 int FI = cast<FrameIndexSDNode>(N)->getIndex();
690 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
691 } else if (N.getOpcode() == ARMISD::Wrapper) {
692 Base = N.getOperand(0);
693 if (Base.getOpcode() == ISD::TargetConstantPool)
694 return false; // We want to select t2LDRpci instead.
696 OffReg = CurDAG->getRegister(0, MVT::i32);
697 ShImm = CurDAG->getTargetConstant(0, MVT::i32);
701 // Thumb2 does not support (R - R) or (R - (R << [1,2,3])).
702 if (N.getOpcode() != ISD::ADD)
705 // Look for (R + R) or (R + (R << [1,2,3])).
707 Base = N.getOperand(0);
708 OffReg = N.getOperand(1);
710 // Swap if it is ((R << c) + R).
711 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg);
712 if (ShOpcVal != ARM_AM::lsl) {
713 ShOpcVal = ARM_AM::getShiftOpcForNode(Base);
714 if (ShOpcVal == ARM_AM::lsl)
715 std::swap(Base, OffReg);
718 if (ShOpcVal == ARM_AM::lsl) {
719 // Check to see if the RHS of the shift is a constant, if not, we can't fold
721 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
722 ShAmt = Sh->getZExtValue();
725 ShOpcVal = ARM_AM::no_shift;
727 OffReg = OffReg.getOperand(0);
729 ShOpcVal = ARM_AM::no_shift;
731 } else if (SelectT2AddrModeImm12(Op, N, Base, ShImm) ||
732 SelectT2AddrModeImm8 (Op, N, Base, ShImm)) {
733 // Don't match if it's possible to match to one of the r +/- imm cases.
737 ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
742 //===--------------------------------------------------------------------===//
744 /// getAL - Returns a ARMCC::AL immediate node.
745 static inline SDValue getAL(SelectionDAG *CurDAG) {
746 return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
749 SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDValue Op) {
750 LoadSDNode *LD = cast<LoadSDNode>(Op);
751 ISD::MemIndexedMode AM = LD->getAddressingMode();
752 if (AM == ISD::UNINDEXED)
755 MVT LoadedVT = LD->getMemoryVT();
756 SDValue Offset, AMOpc;
757 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
760 if (LoadedVT == MVT::i32 &&
761 SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
762 Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST;
764 } else if (LoadedVT == MVT::i16 &&
765 SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
767 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
768 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
769 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
770 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
771 if (LD->getExtensionType() == ISD::SEXTLOAD) {
772 if (SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
774 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
777 if (SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
779 Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST;
785 SDValue Chain = LD->getChain();
786 SDValue Base = LD->getBasePtr();
787 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
788 CurDAG->getRegister(0, MVT::i32), Chain };
789 return CurDAG->getTargetNode(Opcode, Op.getDebugLoc(), MVT::i32, MVT::i32,
796 SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDValue Op) {
797 LoadSDNode *LD = cast<LoadSDNode>(Op);
798 ISD::MemIndexedMode AM = LD->getAddressingMode();
799 if (AM == ISD::UNINDEXED)
802 MVT LoadedVT = LD->getMemoryVT();
803 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
805 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
808 if (SelectT2AddrModeImm8Offset(Op, LD->getOffset(), Offset)) {
809 switch (LoadedVT.getSimpleVT()) {
811 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
815 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
817 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
822 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
824 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
833 SDValue Chain = LD->getChain();
834 SDValue Base = LD->getBasePtr();
835 SDValue Ops[]= { Base, Offset, getAL(CurDAG),
836 CurDAG->getRegister(0, MVT::i32), Chain };
837 return CurDAG->getTargetNode(Opcode, Op.getDebugLoc(), MVT::i32, MVT::i32,
845 SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
846 SDNode *N = Op.getNode();
847 DebugLoc dl = N->getDebugLoc();
849 if (N->isMachineOpcode())
850 return NULL; // Already selected.
852 switch (N->getOpcode()) {
854 case ISD::Constant: {
855 unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
857 if (Subtarget->isThumb()) {
858 if (Subtarget->hasThumb2())
859 // Thumb2 has the MOVT instruction, so all immediates can
860 // be done with MOV + MOVT, at worst.
863 UseCP = (Val > 255 && // MOV
864 ~Val > 255 && // MOV + MVN
865 !ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL
867 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
868 ARM_AM::getSOImmVal(~Val) == -1 && // MVN
869 !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs.
872 CurDAG->getTargetConstantPool(
873 CurDAG->getContext()->getConstantInt(Type::Int32Ty, Val),
877 if (Subtarget->isThumb1Only()) {
878 SDValue Pred = CurDAG->getTargetConstant(0xEULL, MVT::i32);
879 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
880 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
881 ResNode = CurDAG->getTargetNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other,
886 CurDAG->getRegister(0, MVT::i32),
887 CurDAG->getTargetConstant(0, MVT::i32),
889 CurDAG->getRegister(0, MVT::i32),
890 CurDAG->getEntryNode()
892 ResNode=CurDAG->getTargetNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
895 ReplaceUses(Op, SDValue(ResNode, 0));
899 // Other cases are autogenerated.
902 case ISD::FrameIndex: {
903 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
904 int FI = cast<FrameIndexSDNode>(N)->getIndex();
905 SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
906 if (Subtarget->isThumb1Only()) {
907 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
908 CurDAG->getTargetConstant(0, MVT::i32));
910 unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
911 ARM::t2ADDri : ARM::ADDri);
912 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
913 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
914 CurDAG->getRegister(0, MVT::i32) };
915 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
919 if (!Subtarget->isThumb1Only())
921 // Select add sp, c to tADDhirr.
922 SDValue N0 = Op.getOperand(0);
923 SDValue N1 = Op.getOperand(1);
924 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(Op.getOperand(0));
925 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(Op.getOperand(1));
926 if (LHSR && LHSR->getReg() == ARM::SP) {
928 std::swap(LHSR, RHSR);
930 if (RHSR && RHSR->getReg() == ARM::SP) {
931 SDValue Val = SDValue(CurDAG->getTargetNode(ARM::tMOVlor2hir, dl,
932 Op.getValueType(), N0, N0),0);
933 return CurDAG->SelectNodeTo(N, ARM::tADDhirr, Op.getValueType(), Val, N1);
938 if (Subtarget->isThumb1Only())
940 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
941 unsigned RHSV = C->getZExtValue();
943 if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
944 SDValue V = Op.getOperand(0);
945 unsigned ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, Log2_32(RHSV-1));
946 SDValue Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
947 CurDAG->getTargetConstant(ShImm, MVT::i32),
948 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
949 CurDAG->getRegister(0, MVT::i32) };
950 return CurDAG->SelectNodeTo(N, (Subtarget->isThumb() &&
951 Subtarget->hasThumb2()) ?
952 ARM::t2ADDrs : ARM::ADDrs, MVT::i32, Ops, 7);
954 if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
955 SDValue V = Op.getOperand(0);
956 unsigned ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, Log2_32(RHSV+1));
957 SDValue Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
958 CurDAG->getTargetConstant(ShImm, MVT::i32),
959 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
960 CurDAG->getRegister(0, MVT::i32) };
961 return CurDAG->SelectNodeTo(N, (Subtarget->isThumb() &&
962 Subtarget->hasThumb2()) ?
963 ARM::t2RSBrs : ARM::RSBrs, MVT::i32, Ops, 7);
968 return CurDAG->getTargetNode(ARM::FMRRD, dl, MVT::i32, MVT::i32,
969 Op.getOperand(0), getAL(CurDAG),
970 CurDAG->getRegister(0, MVT::i32));
971 case ISD::UMUL_LOHI: {
972 if (Subtarget->isThumb1Only())
974 if (Subtarget->isThumb()) {
975 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
976 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
977 CurDAG->getRegister(0, MVT::i32) };
978 return CurDAG->getTargetNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32, Ops,4);
980 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
981 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
982 CurDAG->getRegister(0, MVT::i32) };
983 return CurDAG->getTargetNode(ARM::UMULL, dl, MVT::i32, MVT::i32, Ops, 5);
986 case ISD::SMUL_LOHI: {
987 if (Subtarget->isThumb1Only())
989 if (Subtarget->isThumb()) {
990 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
991 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
992 return CurDAG->getTargetNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32, Ops,4);
994 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
995 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
996 CurDAG->getRegister(0, MVT::i32) };
997 return CurDAG->getTargetNode(ARM::SMULL, dl, MVT::i32, MVT::i32, Ops, 5);
1001 SDNode *ResNode = 0;
1002 if (Subtarget->isThumb() && Subtarget->hasThumb2())
1003 ResNode = SelectT2IndexedLoad(Op);
1005 ResNode = SelectARMIndexedLoad(Op);
1008 // Other cases are autogenerated.
1011 case ARMISD::BRCOND: {
1012 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1013 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
1014 // Pattern complexity = 6 cost = 1 size = 0
1016 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1017 // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
1018 // Pattern complexity = 6 cost = 1 size = 0
1020 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1021 // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
1022 // Pattern complexity = 6 cost = 1 size = 0
1024 unsigned Opc = Subtarget->isThumb() ?
1025 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
1026 SDValue Chain = Op.getOperand(0);
1027 SDValue N1 = Op.getOperand(1);
1028 SDValue N2 = Op.getOperand(2);
1029 SDValue N3 = Op.getOperand(3);
1030 SDValue InFlag = Op.getOperand(4);
1031 assert(N1.getOpcode() == ISD::BasicBlock);
1032 assert(N2.getOpcode() == ISD::Constant);
1033 assert(N3.getOpcode() == ISD::Register);
1035 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1036 cast<ConstantSDNode>(N2)->getZExtValue()),
1038 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
1039 SDNode *ResNode = CurDAG->getTargetNode(Opc, dl, MVT::Other,
1041 Chain = SDValue(ResNode, 0);
1042 if (Op.getNode()->getNumValues() == 2) {
1043 InFlag = SDValue(ResNode, 1);
1044 ReplaceUses(SDValue(Op.getNode(), 1), InFlag);
1046 ReplaceUses(SDValue(Op.getNode(), 0), SDValue(Chain.getNode(), Chain.getResNo()));
1049 case ARMISD::CMOV: {
1050 MVT VT = Op.getValueType();
1051 SDValue N0 = Op.getOperand(0);
1052 SDValue N1 = Op.getOperand(1);
1053 SDValue N2 = Op.getOperand(2);
1054 SDValue N3 = Op.getOperand(3);
1055 SDValue InFlag = Op.getOperand(4);
1056 assert(N2.getOpcode() == ISD::Constant);
1057 assert(N3.getOpcode() == ISD::Register);
1059 if (!Subtarget->isThumb1Only() && VT == MVT::i32) {
1060 // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1061 // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1062 // Pattern complexity = 18 cost = 1 size = 0
1066 if (Subtarget->isThumb()) {
1067 if (SelectT2ShifterOperandReg(Op, N1, CPTmp0, CPTmp1)) {
1068 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1069 cast<ConstantSDNode>(N2)->getZExtValue()),
1071 SDValue Ops[] = { N0, CPTmp0, CPTmp1, Tmp2, N3, InFlag };
1072 return CurDAG->SelectNodeTo(Op.getNode(),
1073 ARM::t2MOVCCs, MVT::i32,Ops, 6);
1076 if (SelectShifterOperandReg(Op, N1, CPTmp0, CPTmp1, CPTmp2)) {
1077 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1078 cast<ConstantSDNode>(N2)->getZExtValue()),
1080 SDValue Ops[] = { N0, CPTmp0, CPTmp1, CPTmp2, Tmp2, N3, InFlag };
1081 return CurDAG->SelectNodeTo(Op.getNode(),
1082 ARM::MOVCCs, MVT::i32, Ops, 7);
1086 // Pattern: (ARMcmov:i32 GPR:i32:$false,
1087 // (imm:i32)<<P:Predicate_so_imm>>:$true,
1089 // Emits: (MOVCCi:i32 GPR:i32:$false,
1090 // (so_imm:i32 (imm:i32):$true), (imm:i32):$cc)
1091 // Pattern complexity = 10 cost = 1 size = 0
1092 if (N3.getOpcode() == ISD::Constant) {
1093 if (Subtarget->isThumb()) {
1094 if (Predicate_t2_so_imm(N3.getNode())) {
1095 SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
1096 cast<ConstantSDNode>(N1)->getZExtValue()),
1098 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1099 cast<ConstantSDNode>(N2)->getZExtValue()),
1101 SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
1102 return CurDAG->SelectNodeTo(Op.getNode(),
1103 ARM::t2MOVCCi, MVT::i32, Ops, 5);
1106 if (Predicate_so_imm(N3.getNode())) {
1107 SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
1108 cast<ConstantSDNode>(N1)->getZExtValue()),
1110 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1111 cast<ConstantSDNode>(N2)->getZExtValue()),
1113 SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
1114 return CurDAG->SelectNodeTo(Op.getNode(),
1115 ARM::MOVCCi, MVT::i32, Ops, 5);
1121 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1122 // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1123 // Pattern complexity = 6 cost = 1 size = 0
1125 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1126 // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1127 // Pattern complexity = 6 cost = 11 size = 0
1129 // Also FCPYScc and FCPYDcc.
1130 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1131 cast<ConstantSDNode>(N2)->getZExtValue()),
1133 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
1135 switch (VT.getSimpleVT()) {
1136 default: assert(false && "Illegal conditional move type!");
1139 Opc = Subtarget->isThumb()
1140 ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr)
1150 return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
1152 case ARMISD::CNEG: {
1153 MVT VT = Op.getValueType();
1154 SDValue N0 = Op.getOperand(0);
1155 SDValue N1 = Op.getOperand(1);
1156 SDValue N2 = Op.getOperand(2);
1157 SDValue N3 = Op.getOperand(3);
1158 SDValue InFlag = Op.getOperand(4);
1159 assert(N2.getOpcode() == ISD::Constant);
1160 assert(N3.getOpcode() == ISD::Register);
1162 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1163 cast<ConstantSDNode>(N2)->getZExtValue()),
1165 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
1167 switch (VT.getSimpleVT()) {
1168 default: assert(false && "Illegal conditional move type!");
1177 return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
1180 case ISD::DECLARE: {
1181 SDValue Chain = Op.getOperand(0);
1182 SDValue N1 = Op.getOperand(1);
1183 SDValue N2 = Op.getOperand(2);
1184 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N1);
1185 // FIXME: handle VLAs.
1187 ReplaceUses(Op.getValue(0), Chain);
1190 if (N2.getOpcode() == ARMISD::PIC_ADD && isa<LoadSDNode>(N2.getOperand(0)))
1191 N2 = N2.getOperand(0);
1192 LoadSDNode *Ld = dyn_cast<LoadSDNode>(N2);
1194 ReplaceUses(Op.getValue(0), Chain);
1197 SDValue BasePtr = Ld->getBasePtr();
1198 assert(BasePtr.getOpcode() == ARMISD::Wrapper &&
1199 isa<ConstantPoolSDNode>(BasePtr.getOperand(0)) &&
1200 "llvm.dbg.variable should be a constantpool node");
1201 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(BasePtr.getOperand(0));
1202 GlobalValue *GV = 0;
1203 if (CP->isMachineConstantPoolEntry()) {
1204 ARMConstantPoolValue *ACPV = (ARMConstantPoolValue*)CP->getMachineCPVal();
1207 GV = dyn_cast<GlobalValue>(CP->getConstVal());
1209 ReplaceUses(Op.getValue(0), Chain);
1213 SDValue Tmp1 = CurDAG->getTargetFrameIndex(FINode->getIndex(),
1214 TLI.getPointerTy());
1215 SDValue Tmp2 = CurDAG->getTargetGlobalAddress(GV, TLI.getPointerTy());
1216 SDValue Ops[] = { Tmp1, Tmp2, Chain };
1217 return CurDAG->getTargetNode(TargetInstrInfo::DECLARE, dl,
1218 MVT::Other, Ops, 3);
1221 case ISD::CONCAT_VECTORS: {
1222 MVT VT = Op.getValueType();
1223 assert(VT.is128BitVector() && Op.getNumOperands() == 2 &&
1224 "unexpected CONCAT_VECTORS");
1225 SDValue N0 = Op.getOperand(0);
1226 SDValue N1 = Op.getOperand(1);
1228 CurDAG->getTargetNode(TargetInstrInfo::IMPLICIT_DEF, dl, VT);
1229 if (N0.getOpcode() != ISD::UNDEF)
1230 Result = CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, VT,
1231 SDValue(Result, 0), N0,
1232 CurDAG->getTargetConstant(arm_dsubreg_0,
1234 if (N1.getOpcode() != ISD::UNDEF)
1235 Result = CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, VT,
1236 SDValue(Result, 0), N1,
1237 CurDAG->getTargetConstant(arm_dsubreg_1,
1242 case ISD::VECTOR_SHUFFLE: {
1243 MVT VT = Op.getValueType();
1245 // Match 128-bit splat to VDUPLANEQ. (This could be done with a Pat in
1246 // ARMInstrNEON.td but it is awkward because the shuffle mask needs to be
1247 // transformed first into a lane number and then to both a subregister
1248 // index and an adjusted lane number.) If the source operand is a
1249 // SCALAR_TO_VECTOR, leave it so it will be matched later as a VDUP.
1250 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1251 if (VT.is128BitVector() && SVOp->isSplat() &&
1252 Op.getOperand(0).getOpcode() != ISD::SCALAR_TO_VECTOR &&
1253 Op.getOperand(1).getOpcode() == ISD::UNDEF) {
1254 unsigned LaneVal = SVOp->getSplatIndex();
1258 switch (VT.getVectorElementType().getSimpleVT()) {
1259 default: assert(false && "unhandled VDUP splat type");
1260 case MVT::i8: Opc = ARM::VDUPLN8q; HalfVT = MVT::v8i8; break;
1261 case MVT::i16: Opc = ARM::VDUPLN16q; HalfVT = MVT::v4i16; break;
1262 case MVT::i32: Opc = ARM::VDUPLN32q; HalfVT = MVT::v2i32; break;
1263 case MVT::f32: Opc = ARM::VDUPLNfq; HalfVT = MVT::v2f32; break;
1266 // The source operand needs to be changed to a subreg of the original
1267 // 128-bit operand, and the lane number needs to be adjusted accordingly.
1268 unsigned NumElts = VT.getVectorNumElements() / 2;
1269 unsigned SRVal = (LaneVal < NumElts ? arm_dsubreg_0 : arm_dsubreg_1);
1270 SDValue SR = CurDAG->getTargetConstant(SRVal, MVT::i32);
1271 SDValue NewLane = CurDAG->getTargetConstant(LaneVal % NumElts, MVT::i32);
1272 SDNode *SubReg = CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG,
1273 dl, HalfVT, N->getOperand(0), SR);
1274 return CurDAG->SelectNodeTo(N, Opc, VT, SDValue(SubReg, 0), NewLane);
1281 return SelectCode(Op);
1284 bool ARMDAGToDAGISel::
1285 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
1286 std::vector<SDValue> &OutOps) {
1287 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
1289 SDValue Base, Offset, Opc;
1290 if (!SelectAddrMode2(Op, Op, Base, Offset, Opc))
1293 OutOps.push_back(Base);
1294 OutOps.push_back(Offset);
1295 OutOps.push_back(Opc);
1299 /// createARMISelDag - This pass converts a legalized DAG into a
1300 /// ARM-specific DAG, ready for instruction scheduling.
1302 FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM) {
1303 return new ARMDAGToDAGISel(TM);