1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMTargetMachine.h"
17 #include "MCTargetDesc/ARMAddressingModes.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/IR/CallingConv.h"
25 #include "llvm/IR/Constants.h"
26 #include "llvm/IR/DerivedTypes.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/Intrinsics.h"
29 #include "llvm/IR/LLVMContext.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/Compiler.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Target/TargetLowering.h"
35 #include "llvm/Target/TargetOptions.h"
39 #define DEBUG_TYPE "arm-isel"
42 DisableShifterOp("disable-shifter-op", cl::Hidden,
43 cl::desc("Disable isel of shifter-op"),
47 CheckVMLxHazard("check-vmlx-hazard", cl::Hidden,
48 cl::desc("Check fp vmla / vmls hazard at isel time"),
51 //===--------------------------------------------------------------------===//
52 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
53 /// instructions for SelectionDAG operations.
58 AM2_BASE, // Simple AM2 (+-imm12)
59 AM2_SHOP // Shifter-op AM2
62 class ARMDAGToDAGISel : public SelectionDAGISel {
63 ARMBaseTargetMachine &TM;
65 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
66 /// make the right decision when generating code for different targets.
67 const ARMSubtarget *Subtarget;
70 explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm,
71 CodeGenOpt::Level OptLevel)
72 : SelectionDAGISel(tm, OptLevel), TM(tm),
73 Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
76 const char *getPassName() const override {
77 return "ARM Instruction Selection";
80 void PreprocessISelDAG() override;
82 /// getI32Imm - Return a target constant of type i32 with the specified
84 inline SDValue getI32Imm(unsigned Imm) {
85 return CurDAG->getTargetConstant(Imm, MVT::i32);
88 SDNode *Select(SDNode *N) override;
91 bool hasNoVMLxHazardUse(SDNode *N) const;
92 bool isShifterOpProfitable(const SDValue &Shift,
93 ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
94 bool SelectRegShifterOperand(SDValue N, SDValue &A,
95 SDValue &B, SDValue &C,
96 bool CheckProfitability = true);
97 bool SelectImmShifterOperand(SDValue N, SDValue &A,
98 SDValue &B, bool CheckProfitability = true);
99 bool SelectShiftRegShifterOperand(SDValue N, SDValue &A,
100 SDValue &B, SDValue &C) {
101 // Don't apply the profitability check
102 return SelectRegShifterOperand(N, A, B, C, false);
104 bool SelectShiftImmShifterOperand(SDValue N, SDValue &A,
106 // Don't apply the profitability check
107 return SelectImmShifterOperand(N, A, B, false);
110 bool SelectAddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
111 bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc);
113 AddrMode2Type SelectAddrMode2Worker(SDValue N, SDValue &Base,
114 SDValue &Offset, SDValue &Opc);
115 bool SelectAddrMode2Base(SDValue N, SDValue &Base, SDValue &Offset,
117 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_BASE;
120 bool SelectAddrMode2ShOp(SDValue N, SDValue &Base, SDValue &Offset,
122 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_SHOP;
125 bool SelectAddrMode2(SDValue N, SDValue &Base, SDValue &Offset,
127 SelectAddrMode2Worker(N, Base, Offset, Opc);
128 // return SelectAddrMode2ShOp(N, Base, Offset, Opc);
129 // This always matches one way or another.
133 bool SelectCMOVPred(SDValue N, SDValue &Pred, SDValue &Reg) {
134 const ConstantSDNode *CN = cast<ConstantSDNode>(N);
135 Pred = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
136 Reg = CurDAG->getRegister(ARM::CPSR, MVT::i32);
140 bool SelectAddrMode2OffsetReg(SDNode *Op, SDValue N,
141 SDValue &Offset, SDValue &Opc);
142 bool SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
143 SDValue &Offset, SDValue &Opc);
144 bool SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N,
145 SDValue &Offset, SDValue &Opc);
146 bool SelectAddrOffsetNone(SDValue N, SDValue &Base);
147 bool SelectAddrMode3(SDValue N, SDValue &Base,
148 SDValue &Offset, SDValue &Opc);
149 bool SelectAddrMode3Offset(SDNode *Op, SDValue N,
150 SDValue &Offset, SDValue &Opc);
151 bool SelectAddrMode5(SDValue N, SDValue &Base,
153 bool SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,SDValue &Align);
154 bool SelectAddrMode6Offset(SDNode *Op, SDValue N, SDValue &Offset);
156 bool SelectAddrModePC(SDValue N, SDValue &Offset, SDValue &Label);
158 // Thumb Addressing Modes:
159 bool SelectThumbAddrModeRR(SDValue N, SDValue &Base, SDValue &Offset);
160 bool SelectThumbAddrModeRI(SDValue N, SDValue &Base, SDValue &Offset,
162 bool SelectThumbAddrModeRI5S1(SDValue N, SDValue &Base, SDValue &Offset);
163 bool SelectThumbAddrModeRI5S2(SDValue N, SDValue &Base, SDValue &Offset);
164 bool SelectThumbAddrModeRI5S4(SDValue N, SDValue &Base, SDValue &Offset);
165 bool SelectThumbAddrModeImm5S(SDValue N, unsigned Scale, SDValue &Base,
167 bool SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
169 bool SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
171 bool SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
173 bool SelectThumbAddrModeSP(SDValue N, SDValue &Base, SDValue &OffImm);
175 // Thumb 2 Addressing Modes:
176 bool SelectT2ShifterOperandReg(SDValue N,
177 SDValue &BaseReg, SDValue &Opc);
178 bool SelectT2AddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
179 bool SelectT2AddrModeImm8(SDValue N, SDValue &Base,
181 bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
183 bool SelectT2AddrModeSoReg(SDValue N, SDValue &Base,
184 SDValue &OffReg, SDValue &ShImm);
185 bool SelectT2AddrModeExclusive(SDValue N, SDValue &Base, SDValue &OffImm);
187 inline bool is_so_imm(unsigned Imm) const {
188 return ARM_AM::getSOImmVal(Imm) != -1;
191 inline bool is_so_imm_not(unsigned Imm) const {
192 return ARM_AM::getSOImmVal(~Imm) != -1;
195 inline bool is_t2_so_imm(unsigned Imm) const {
196 return ARM_AM::getT2SOImmVal(Imm) != -1;
199 inline bool is_t2_so_imm_not(unsigned Imm) const {
200 return ARM_AM::getT2SOImmVal(~Imm) != -1;
203 // Include the pieces autogenerated from the target description.
204 #include "ARMGenDAGISel.inc"
207 /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
209 SDNode *SelectARMIndexedLoad(SDNode *N);
210 SDNode *SelectT2IndexedLoad(SDNode *N);
212 /// SelectVLD - Select NEON load intrinsics. NumVecs should be
213 /// 1, 2, 3 or 4. The opcode arrays specify the instructions used for
214 /// loads of D registers and even subregs and odd subregs of Q registers.
215 /// For NumVecs <= 2, QOpcodes1 is not used.
216 SDNode *SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
217 const uint16_t *DOpcodes,
218 const uint16_t *QOpcodes0, const uint16_t *QOpcodes1);
220 /// SelectVST - Select NEON store intrinsics. NumVecs should
221 /// be 1, 2, 3 or 4. The opcode arrays specify the instructions used for
222 /// stores of D registers and even subregs and odd subregs of Q registers.
223 /// For NumVecs <= 2, QOpcodes1 is not used.
224 SDNode *SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
225 const uint16_t *DOpcodes,
226 const uint16_t *QOpcodes0, const uint16_t *QOpcodes1);
228 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should
229 /// be 2, 3 or 4. The opcode arrays specify the instructions used for
230 /// load/store of D registers and Q registers.
231 SDNode *SelectVLDSTLane(SDNode *N, bool IsLoad,
232 bool isUpdating, unsigned NumVecs,
233 const uint16_t *DOpcodes, const uint16_t *QOpcodes);
235 /// SelectVLDDup - Select NEON load-duplicate intrinsics. NumVecs
236 /// should be 2, 3 or 4. The opcode array specifies the instructions used
237 /// for loading D registers. (Q registers are not supported.)
238 SDNode *SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs,
239 const uint16_t *Opcodes);
241 /// SelectVTBL - Select NEON VTBL and VTBX intrinsics. NumVecs should be 2,
242 /// 3 or 4. These are custom-selected so that a REG_SEQUENCE can be
243 /// generated to force the table registers to be consecutive.
244 SDNode *SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc);
246 /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM.
247 SDNode *SelectV6T2BitfieldExtractOp(SDNode *N, bool isSigned);
249 // Select special operations if node forms integer ABS pattern
250 SDNode *SelectABSOp(SDNode *N);
252 SDNode *SelectInlineAsm(SDNode *N);
254 SDNode *SelectConcatVector(SDNode *N);
256 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
257 /// inline asm expressions.
258 bool SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
259 std::vector<SDValue> &OutOps) override;
261 // Form pairs of consecutive R, S, D, or Q registers.
262 SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
263 SDNode *createSRegPairNode(EVT VT, SDValue V0, SDValue V1);
264 SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
265 SDNode *createQRegPairNode(EVT VT, SDValue V0, SDValue V1);
267 // Form sequences of 4 consecutive S, D, or Q registers.
268 SDNode *createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
269 SDNode *createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
270 SDNode *createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
272 // Get the alignment operand for a NEON VLD or VST instruction.
273 SDValue GetVLDSTAlign(SDValue Align, unsigned NumVecs, bool is64BitVector);
277 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
278 /// operand. If so Imm will receive the 32-bit value.
279 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
280 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
281 Imm = cast<ConstantSDNode>(N)->getZExtValue();
287 // isInt32Immediate - This method tests to see if a constant operand.
288 // If so Imm will receive the 32 bit value.
289 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
290 return isInt32Immediate(N.getNode(), Imm);
293 // isOpcWithIntImmediate - This method tests to see if the node is a specific
294 // opcode and that it has a immediate integer right operand.
295 // If so Imm will receive the 32 bit value.
296 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
297 return N->getOpcode() == Opc &&
298 isInt32Immediate(N->getOperand(1).getNode(), Imm);
301 /// \brief Check whether a particular node is a constant value representable as
302 /// (N * Scale) where (N in [\p RangeMin, \p RangeMax).
304 /// \param ScaledConstant [out] - On success, the pre-scaled constant value.
305 static bool isScaledConstantInRange(SDValue Node, int Scale,
306 int RangeMin, int RangeMax,
307 int &ScaledConstant) {
308 assert(Scale > 0 && "Invalid scale!");
310 // Check that this is a constant.
311 const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Node);
315 ScaledConstant = (int) C->getZExtValue();
316 if ((ScaledConstant % Scale) != 0)
319 ScaledConstant /= Scale;
320 return ScaledConstant >= RangeMin && ScaledConstant < RangeMax;
323 void ARMDAGToDAGISel::PreprocessISelDAG() {
324 if (!Subtarget->hasV6T2Ops())
327 bool isThumb2 = Subtarget->isThumb();
328 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
329 E = CurDAG->allnodes_end(); I != E; ) {
330 SDNode *N = I++; // Preincrement iterator to avoid invalidation issues.
332 if (N->getOpcode() != ISD::ADD)
335 // Look for (add X1, (and (srl X2, c1), c2)) where c2 is constant with
336 // leading zeros, followed by consecutive set bits, followed by 1 or 2
337 // trailing zeros, e.g. 1020.
338 // Transform the expression to
339 // (add X1, (shl (and (srl X2, c1), (c2>>tz)), tz)) where tz is the number
340 // of trailing zeros of c2. The left shift would be folded as an shifter
341 // operand of 'add' and the 'and' and 'srl' would become a bits extraction
344 SDValue N0 = N->getOperand(0);
345 SDValue N1 = N->getOperand(1);
346 unsigned And_imm = 0;
347 if (!isOpcWithIntImmediate(N1.getNode(), ISD::AND, And_imm)) {
348 if (isOpcWithIntImmediate(N0.getNode(), ISD::AND, And_imm))
354 // Check if the AND mask is an immediate of the form: 000.....1111111100
355 unsigned TZ = countTrailingZeros(And_imm);
356 if (TZ != 1 && TZ != 2)
357 // Be conservative here. Shifter operands aren't always free. e.g. On
358 // Swift, left shifter operand of 1 / 2 for free but others are not.
360 // ubfx r3, r1, #16, #8
361 // ldr.w r3, [r0, r3, lsl #2]
364 // and.w r2, r9, r1, lsr #14
368 if (And_imm & (And_imm + 1))
371 // Look for (and (srl X, c1), c2).
372 SDValue Srl = N1.getOperand(0);
373 unsigned Srl_imm = 0;
374 if (!isOpcWithIntImmediate(Srl.getNode(), ISD::SRL, Srl_imm) ||
378 // Make sure first operand is not a shifter operand which would prevent
379 // folding of the left shift.
384 if (SelectT2ShifterOperandReg(N0, CPTmp0, CPTmp1))
387 if (SelectImmShifterOperand(N0, CPTmp0, CPTmp1) ||
388 SelectRegShifterOperand(N0, CPTmp0, CPTmp1, CPTmp2))
392 // Now make the transformation.
393 Srl = CurDAG->getNode(ISD::SRL, SDLoc(Srl), MVT::i32,
395 CurDAG->getConstant(Srl_imm+TZ, MVT::i32));
396 N1 = CurDAG->getNode(ISD::AND, SDLoc(N1), MVT::i32,
397 Srl, CurDAG->getConstant(And_imm, MVT::i32));
398 N1 = CurDAG->getNode(ISD::SHL, SDLoc(N1), MVT::i32,
399 N1, CurDAG->getConstant(TZ, MVT::i32));
400 CurDAG->UpdateNodeOperands(N, N0, N1);
404 /// hasNoVMLxHazardUse - Return true if it's desirable to select a FP MLA / MLS
405 /// node. VFP / NEON fp VMLA / VMLS instructions have special RAW hazards (at
406 /// least on current ARM implementations) which should be avoidded.
407 bool ARMDAGToDAGISel::hasNoVMLxHazardUse(SDNode *N) const {
408 if (OptLevel == CodeGenOpt::None)
411 if (!CheckVMLxHazard)
414 if (!Subtarget->isCortexA7() && !Subtarget->isCortexA8() &&
415 !Subtarget->isCortexA9() && !Subtarget->isSwift())
421 SDNode *Use = *N->use_begin();
422 if (Use->getOpcode() == ISD::CopyToReg)
424 if (Use->isMachineOpcode()) {
425 const ARMBaseInstrInfo *TII =
426 static_cast<const ARMBaseInstrInfo*>(TM.getInstrInfo());
428 const MCInstrDesc &MCID = TII->get(Use->getMachineOpcode());
431 unsigned Opcode = MCID.getOpcode();
432 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
434 // vmlx feeding into another vmlx. We actually want to unfold
435 // the use later in the MLxExpansion pass. e.g.
437 // vmla (stall 8 cycles)
442 // This adds up to about 18 - 19 cycles.
445 // vmul (stall 4 cycles)
446 // vadd adds up to about 14 cycles.
447 return TII->isFpMLxInstruction(Opcode);
453 bool ARMDAGToDAGISel::isShifterOpProfitable(const SDValue &Shift,
454 ARM_AM::ShiftOpc ShOpcVal,
456 if (!Subtarget->isLikeA9() && !Subtarget->isSwift())
458 if (Shift.hasOneUse())
461 return ShOpcVal == ARM_AM::lsl &&
462 (ShAmt == 2 || (Subtarget->isSwift() && ShAmt == 1));
465 bool ARMDAGToDAGISel::SelectImmShifterOperand(SDValue N,
468 bool CheckProfitability) {
469 if (DisableShifterOp)
472 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
474 // Don't match base register only case. That is matched to a separate
475 // lower complexity pattern with explicit register operand.
476 if (ShOpcVal == ARM_AM::no_shift) return false;
478 BaseReg = N.getOperand(0);
479 unsigned ShImmVal = 0;
480 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
481 if (!RHS) return false;
482 ShImmVal = RHS->getZExtValue() & 31;
483 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
488 bool ARMDAGToDAGISel::SelectRegShifterOperand(SDValue N,
492 bool CheckProfitability) {
493 if (DisableShifterOp)
496 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
498 // Don't match base register only case. That is matched to a separate
499 // lower complexity pattern with explicit register operand.
500 if (ShOpcVal == ARM_AM::no_shift) return false;
502 BaseReg = N.getOperand(0);
503 unsigned ShImmVal = 0;
504 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
505 if (RHS) return false;
507 ShReg = N.getOperand(1);
508 if (CheckProfitability && !isShifterOpProfitable(N, ShOpcVal, ShImmVal))
510 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
516 bool ARMDAGToDAGISel::SelectAddrModeImm12(SDValue N,
519 // Match simple R + imm12 operands.
522 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
523 !CurDAG->isBaseWithConstantOffset(N)) {
524 if (N.getOpcode() == ISD::FrameIndex) {
525 // Match frame index.
526 int FI = cast<FrameIndexSDNode>(N)->getIndex();
527 Base = CurDAG->getTargetFrameIndex(FI,
528 getTargetLowering()->getPointerTy());
529 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
533 if (N.getOpcode() == ARMISD::Wrapper &&
534 N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress) {
535 Base = N.getOperand(0);
538 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
542 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
543 int RHSC = (int)RHS->getZExtValue();
544 if (N.getOpcode() == ISD::SUB)
547 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
548 Base = N.getOperand(0);
549 if (Base.getOpcode() == ISD::FrameIndex) {
550 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
551 Base = CurDAG->getTargetFrameIndex(FI,
552 getTargetLowering()->getPointerTy());
554 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
561 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
567 bool ARMDAGToDAGISel::SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset,
569 if (N.getOpcode() == ISD::MUL &&
570 ((!Subtarget->isLikeA9() && !Subtarget->isSwift()) || N.hasOneUse())) {
571 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
572 // X * [3,5,9] -> X + X * [2,4,8] etc.
573 int RHSC = (int)RHS->getZExtValue();
576 ARM_AM::AddrOpc AddSub = ARM_AM::add;
578 AddSub = ARM_AM::sub;
581 if (isPowerOf2_32(RHSC)) {
582 unsigned ShAmt = Log2_32(RHSC);
583 Base = Offset = N.getOperand(0);
584 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
593 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
594 // ISD::OR that is equivalent to an ISD::ADD.
595 !CurDAG->isBaseWithConstantOffset(N))
598 // Leave simple R +/- imm12 operands for LDRi12
599 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR) {
601 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
602 -0x1000+1, 0x1000, RHSC)) // 12 bits.
606 // Otherwise this is R +/- [possibly shifted] R.
607 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::SUB ? ARM_AM::sub:ARM_AM::add;
608 ARM_AM::ShiftOpc ShOpcVal =
609 ARM_AM::getShiftOpcForNode(N.getOperand(1).getOpcode());
612 Base = N.getOperand(0);
613 Offset = N.getOperand(1);
615 if (ShOpcVal != ARM_AM::no_shift) {
616 // Check to see if the RHS of the shift is a constant, if not, we can't fold
618 if (ConstantSDNode *Sh =
619 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
620 ShAmt = Sh->getZExtValue();
621 if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
622 Offset = N.getOperand(1).getOperand(0);
625 ShOpcVal = ARM_AM::no_shift;
628 ShOpcVal = ARM_AM::no_shift;
632 // Try matching (R shl C) + (R).
633 if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
634 !(Subtarget->isLikeA9() || Subtarget->isSwift() ||
635 N.getOperand(0).hasOneUse())) {
636 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0).getOpcode());
637 if (ShOpcVal != ARM_AM::no_shift) {
638 // Check to see if the RHS of the shift is a constant, if not, we can't
640 if (ConstantSDNode *Sh =
641 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
642 ShAmt = Sh->getZExtValue();
643 if (isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt)) {
644 Offset = N.getOperand(0).getOperand(0);
645 Base = N.getOperand(1);
648 ShOpcVal = ARM_AM::no_shift;
651 ShOpcVal = ARM_AM::no_shift;
656 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
664 AddrMode2Type ARMDAGToDAGISel::SelectAddrMode2Worker(SDValue N,
668 if (N.getOpcode() == ISD::MUL &&
669 (!(Subtarget->isLikeA9() || Subtarget->isSwift()) || N.hasOneUse())) {
670 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
671 // X * [3,5,9] -> X + X * [2,4,8] etc.
672 int RHSC = (int)RHS->getZExtValue();
675 ARM_AM::AddrOpc AddSub = ARM_AM::add;
677 AddSub = ARM_AM::sub;
680 if (isPowerOf2_32(RHSC)) {
681 unsigned ShAmt = Log2_32(RHSC);
682 Base = Offset = N.getOperand(0);
683 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
692 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
693 // ISD::OR that is equivalent to an ADD.
694 !CurDAG->isBaseWithConstantOffset(N)) {
696 if (N.getOpcode() == ISD::FrameIndex) {
697 int FI = cast<FrameIndexSDNode>(N)->getIndex();
698 Base = CurDAG->getTargetFrameIndex(FI,
699 getTargetLowering()->getPointerTy());
700 } else if (N.getOpcode() == ARMISD::Wrapper &&
701 N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress) {
702 Base = N.getOperand(0);
704 Offset = CurDAG->getRegister(0, MVT::i32);
705 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
711 // Match simple R +/- imm12 operands.
712 if (N.getOpcode() != ISD::SUB) {
714 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
715 -0x1000+1, 0x1000, RHSC)) { // 12 bits.
716 Base = N.getOperand(0);
717 if (Base.getOpcode() == ISD::FrameIndex) {
718 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
719 Base = CurDAG->getTargetFrameIndex(FI,
720 getTargetLowering()->getPointerTy());
722 Offset = CurDAG->getRegister(0, MVT::i32);
724 ARM_AM::AddrOpc AddSub = ARM_AM::add;
726 AddSub = ARM_AM::sub;
729 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
736 if ((Subtarget->isLikeA9() || Subtarget->isSwift()) && !N.hasOneUse()) {
737 // Compute R +/- (R << N) and reuse it.
739 Offset = CurDAG->getRegister(0, MVT::i32);
740 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
746 // Otherwise this is R +/- [possibly shifted] R.
747 ARM_AM::AddrOpc AddSub = N.getOpcode() != ISD::SUB ? ARM_AM::add:ARM_AM::sub;
748 ARM_AM::ShiftOpc ShOpcVal =
749 ARM_AM::getShiftOpcForNode(N.getOperand(1).getOpcode());
752 Base = N.getOperand(0);
753 Offset = N.getOperand(1);
755 if (ShOpcVal != ARM_AM::no_shift) {
756 // Check to see if the RHS of the shift is a constant, if not, we can't fold
758 if (ConstantSDNode *Sh =
759 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
760 ShAmt = Sh->getZExtValue();
761 if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
762 Offset = N.getOperand(1).getOperand(0);
765 ShOpcVal = ARM_AM::no_shift;
768 ShOpcVal = ARM_AM::no_shift;
772 // Try matching (R shl C) + (R).
773 if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
774 !(Subtarget->isLikeA9() || Subtarget->isSwift() ||
775 N.getOperand(0).hasOneUse())) {
776 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0).getOpcode());
777 if (ShOpcVal != ARM_AM::no_shift) {
778 // Check to see if the RHS of the shift is a constant, if not, we can't
780 if (ConstantSDNode *Sh =
781 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
782 ShAmt = Sh->getZExtValue();
783 if (isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt)) {
784 Offset = N.getOperand(0).getOperand(0);
785 Base = N.getOperand(1);
788 ShOpcVal = ARM_AM::no_shift;
791 ShOpcVal = ARM_AM::no_shift;
796 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
801 bool ARMDAGToDAGISel::SelectAddrMode2OffsetReg(SDNode *Op, SDValue N,
802 SDValue &Offset, SDValue &Opc) {
803 unsigned Opcode = Op->getOpcode();
804 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
805 ? cast<LoadSDNode>(Op)->getAddressingMode()
806 : cast<StoreSDNode>(Op)->getAddressingMode();
807 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
808 ? ARM_AM::add : ARM_AM::sub;
810 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val))
814 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
816 if (ShOpcVal != ARM_AM::no_shift) {
817 // Check to see if the RHS of the shift is a constant, if not, we can't fold
819 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
820 ShAmt = Sh->getZExtValue();
821 if (isShifterOpProfitable(N, ShOpcVal, ShAmt))
822 Offset = N.getOperand(0);
825 ShOpcVal = ARM_AM::no_shift;
828 ShOpcVal = ARM_AM::no_shift;
832 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
837 bool ARMDAGToDAGISel::SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N,
838 SDValue &Offset, SDValue &Opc) {
839 unsigned Opcode = Op->getOpcode();
840 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
841 ? cast<LoadSDNode>(Op)->getAddressingMode()
842 : cast<StoreSDNode>(Op)->getAddressingMode();
843 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
844 ? ARM_AM::add : ARM_AM::sub;
846 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits.
847 if (AddSub == ARM_AM::sub) Val *= -1;
848 Offset = CurDAG->getRegister(0, MVT::i32);
849 Opc = CurDAG->getTargetConstant(Val, MVT::i32);
857 bool ARMDAGToDAGISel::SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
858 SDValue &Offset, SDValue &Opc) {
859 unsigned Opcode = Op->getOpcode();
860 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
861 ? cast<LoadSDNode>(Op)->getAddressingMode()
862 : cast<StoreSDNode>(Op)->getAddressingMode();
863 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
864 ? ARM_AM::add : ARM_AM::sub;
866 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits.
867 Offset = CurDAG->getRegister(0, MVT::i32);
868 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
877 bool ARMDAGToDAGISel::SelectAddrOffsetNone(SDValue N, SDValue &Base) {
882 bool ARMDAGToDAGISel::SelectAddrMode3(SDValue N,
883 SDValue &Base, SDValue &Offset,
885 if (N.getOpcode() == ISD::SUB) {
886 // X - C is canonicalize to X + -C, no need to handle it here.
887 Base = N.getOperand(0);
888 Offset = N.getOperand(1);
889 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
893 if (!CurDAG->isBaseWithConstantOffset(N)) {
895 if (N.getOpcode() == ISD::FrameIndex) {
896 int FI = cast<FrameIndexSDNode>(N)->getIndex();
897 Base = CurDAG->getTargetFrameIndex(FI,
898 getTargetLowering()->getPointerTy());
900 Offset = CurDAG->getRegister(0, MVT::i32);
901 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
905 // If the RHS is +/- imm8, fold into addr mode.
907 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
908 -256 + 1, 256, RHSC)) { // 8 bits.
909 Base = N.getOperand(0);
910 if (Base.getOpcode() == ISD::FrameIndex) {
911 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
912 Base = CurDAG->getTargetFrameIndex(FI,
913 getTargetLowering()->getPointerTy());
915 Offset = CurDAG->getRegister(0, MVT::i32);
917 ARM_AM::AddrOpc AddSub = ARM_AM::add;
919 AddSub = ARM_AM::sub;
922 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
926 Base = N.getOperand(0);
927 Offset = N.getOperand(1);
928 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
932 bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N,
933 SDValue &Offset, SDValue &Opc) {
934 unsigned Opcode = Op->getOpcode();
935 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
936 ? cast<LoadSDNode>(Op)->getAddressingMode()
937 : cast<StoreSDNode>(Op)->getAddressingMode();
938 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
939 ? ARM_AM::add : ARM_AM::sub;
941 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 256, Val)) { // 12 bits.
942 Offset = CurDAG->getRegister(0, MVT::i32);
943 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
948 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
952 bool ARMDAGToDAGISel::SelectAddrMode5(SDValue N,
953 SDValue &Base, SDValue &Offset) {
954 if (!CurDAG->isBaseWithConstantOffset(N)) {
956 if (N.getOpcode() == ISD::FrameIndex) {
957 int FI = cast<FrameIndexSDNode>(N)->getIndex();
958 Base = CurDAG->getTargetFrameIndex(FI,
959 getTargetLowering()->getPointerTy());
960 } else if (N.getOpcode() == ARMISD::Wrapper &&
961 N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress) {
962 Base = N.getOperand(0);
964 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
969 // If the RHS is +/- imm8, fold into addr mode.
971 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/4,
972 -256 + 1, 256, RHSC)) {
973 Base = N.getOperand(0);
974 if (Base.getOpcode() == ISD::FrameIndex) {
975 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
976 Base = CurDAG->getTargetFrameIndex(FI,
977 getTargetLowering()->getPointerTy());
980 ARM_AM::AddrOpc AddSub = ARM_AM::add;
982 AddSub = ARM_AM::sub;
985 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
991 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
996 bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,
1000 unsigned Alignment = 0;
1001 if (LSBaseSDNode *LSN = dyn_cast<LSBaseSDNode>(Parent)) {
1002 // This case occurs only for VLD1-lane/dup and VST1-lane instructions.
1003 // The maximum alignment is equal to the memory size being referenced.
1004 unsigned LSNAlign = LSN->getAlignment();
1005 unsigned MemSize = LSN->getMemoryVT().getSizeInBits() / 8;
1006 if (LSNAlign >= MemSize && MemSize > 1)
1007 Alignment = MemSize;
1009 // All other uses of addrmode6 are for intrinsics. For now just record
1010 // the raw alignment value; it will be refined later based on the legal
1011 // alignment operands for the intrinsic.
1012 Alignment = cast<MemIntrinsicSDNode>(Parent)->getAlignment();
1015 Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
1019 bool ARMDAGToDAGISel::SelectAddrMode6Offset(SDNode *Op, SDValue N,
1021 LSBaseSDNode *LdSt = cast<LSBaseSDNode>(Op);
1022 ISD::MemIndexedMode AM = LdSt->getAddressingMode();
1023 if (AM != ISD::POST_INC)
1026 if (ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N)) {
1027 if (NC->getZExtValue() * 8 == LdSt->getMemoryVT().getSizeInBits())
1028 Offset = CurDAG->getRegister(0, MVT::i32);
1033 bool ARMDAGToDAGISel::SelectAddrModePC(SDValue N,
1034 SDValue &Offset, SDValue &Label) {
1035 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
1036 Offset = N.getOperand(0);
1037 SDValue N1 = N.getOperand(1);
1038 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
1047 //===----------------------------------------------------------------------===//
1048 // Thumb Addressing Modes
1049 //===----------------------------------------------------------------------===//
1051 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue N,
1052 SDValue &Base, SDValue &Offset){
1053 if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N)) {
1054 ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
1055 if (!NC || !NC->isNullValue())
1062 Base = N.getOperand(0);
1063 Offset = N.getOperand(1);
1068 ARMDAGToDAGISel::SelectThumbAddrModeRI(SDValue N, SDValue &Base,
1069 SDValue &Offset, unsigned Scale) {
1071 SDValue TmpBase, TmpOffImm;
1072 if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
1073 return false; // We want to select tLDRspi / tSTRspi instead.
1075 if (N.getOpcode() == ARMISD::Wrapper &&
1076 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
1077 return false; // We want to select tLDRpci instead.
1080 if (!CurDAG->isBaseWithConstantOffset(N))
1083 // Thumb does not have [sp, r] address mode.
1084 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1085 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
1086 if ((LHSR && LHSR->getReg() == ARM::SP) ||
1087 (RHSR && RHSR->getReg() == ARM::SP))
1090 // FIXME: Why do we explicitly check for a match here and then return false?
1091 // Presumably to allow something else to match, but shouldn't this be
1094 if (isScaledConstantInRange(N.getOperand(1), Scale, 0, 32, RHSC))
1097 Base = N.getOperand(0);
1098 Offset = N.getOperand(1);
1103 ARMDAGToDAGISel::SelectThumbAddrModeRI5S1(SDValue N,
1106 return SelectThumbAddrModeRI(N, Base, Offset, 1);
1110 ARMDAGToDAGISel::SelectThumbAddrModeRI5S2(SDValue N,
1113 return SelectThumbAddrModeRI(N, Base, Offset, 2);
1117 ARMDAGToDAGISel::SelectThumbAddrModeRI5S4(SDValue N,
1120 return SelectThumbAddrModeRI(N, Base, Offset, 4);
1124 ARMDAGToDAGISel::SelectThumbAddrModeImm5S(SDValue N, unsigned Scale,
1125 SDValue &Base, SDValue &OffImm) {
1127 SDValue TmpBase, TmpOffImm;
1128 if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
1129 return false; // We want to select tLDRspi / tSTRspi instead.
1131 if (N.getOpcode() == ARMISD::Wrapper &&
1132 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
1133 return false; // We want to select tLDRpci instead.
1136 if (!CurDAG->isBaseWithConstantOffset(N)) {
1137 if (N.getOpcode() == ARMISD::Wrapper &&
1138 N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress) {
1139 Base = N.getOperand(0);
1144 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1148 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1149 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
1150 if ((LHSR && LHSR->getReg() == ARM::SP) ||
1151 (RHSR && RHSR->getReg() == ARM::SP)) {
1152 ConstantSDNode *LHS = dyn_cast<ConstantSDNode>(N.getOperand(0));
1153 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
1154 unsigned LHSC = LHS ? LHS->getZExtValue() : 0;
1155 unsigned RHSC = RHS ? RHS->getZExtValue() : 0;
1157 // Thumb does not have [sp, #imm5] address mode for non-zero imm5.
1158 if (LHSC != 0 || RHSC != 0) return false;
1161 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1165 // If the RHS is + imm5 * scale, fold into addr mode.
1167 if (isScaledConstantInRange(N.getOperand(1), Scale, 0, 32, RHSC)) {
1168 Base = N.getOperand(0);
1169 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1173 Base = N.getOperand(0);
1174 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1179 ARMDAGToDAGISel::SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
1181 return SelectThumbAddrModeImm5S(N, 4, Base, OffImm);
1185 ARMDAGToDAGISel::SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
1187 return SelectThumbAddrModeImm5S(N, 2, Base, OffImm);
1191 ARMDAGToDAGISel::SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
1193 return SelectThumbAddrModeImm5S(N, 1, Base, OffImm);
1196 bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue N,
1197 SDValue &Base, SDValue &OffImm) {
1198 if (N.getOpcode() == ISD::FrameIndex) {
1199 int FI = cast<FrameIndexSDNode>(N)->getIndex();
1200 Base = CurDAG->getTargetFrameIndex(FI,
1201 getTargetLowering()->getPointerTy());
1202 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1206 if (!CurDAG->isBaseWithConstantOffset(N))
1209 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1210 if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
1211 (LHSR && LHSR->getReg() == ARM::SP)) {
1212 // If the RHS is + imm8 * scale, fold into addr mode.
1214 if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/4, 0, 256, RHSC)) {
1215 Base = N.getOperand(0);
1216 if (Base.getOpcode() == ISD::FrameIndex) {
1217 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1218 Base = CurDAG->getTargetFrameIndex(FI,
1219 getTargetLowering()->getPointerTy());
1221 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1230 //===----------------------------------------------------------------------===//
1231 // Thumb 2 Addressing Modes
1232 //===----------------------------------------------------------------------===//
1235 bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue N, SDValue &BaseReg,
1237 if (DisableShifterOp)
1240 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
1242 // Don't match base register only case. That is matched to a separate
1243 // lower complexity pattern with explicit register operand.
1244 if (ShOpcVal == ARM_AM::no_shift) return false;
1246 BaseReg = N.getOperand(0);
1247 unsigned ShImmVal = 0;
1248 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1249 ShImmVal = RHS->getZExtValue() & 31;
1250 Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
1257 bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue N,
1258 SDValue &Base, SDValue &OffImm) {
1259 // Match simple R + imm12 operands.
1262 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1263 !CurDAG->isBaseWithConstantOffset(N)) {
1264 if (N.getOpcode() == ISD::FrameIndex) {
1265 // Match frame index.
1266 int FI = cast<FrameIndexSDNode>(N)->getIndex();
1267 Base = CurDAG->getTargetFrameIndex(FI,
1268 getTargetLowering()->getPointerTy());
1269 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1273 if (N.getOpcode() == ARMISD::Wrapper &&
1274 N.getOperand(0).getOpcode() != ISD::TargetGlobalAddress) {
1275 Base = N.getOperand(0);
1276 if (Base.getOpcode() == ISD::TargetConstantPool)
1277 return false; // We want to select t2LDRpci instead.
1280 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1284 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1285 if (SelectT2AddrModeImm8(N, Base, OffImm))
1286 // Let t2LDRi8 handle (R - imm8).
1289 int RHSC = (int)RHS->getZExtValue();
1290 if (N.getOpcode() == ISD::SUB)
1293 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
1294 Base = N.getOperand(0);
1295 if (Base.getOpcode() == ISD::FrameIndex) {
1296 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1297 Base = CurDAG->getTargetFrameIndex(FI,
1298 getTargetLowering()->getPointerTy());
1300 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1307 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1311 bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue N,
1312 SDValue &Base, SDValue &OffImm) {
1313 // Match simple R - imm8 operands.
1314 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1315 !CurDAG->isBaseWithConstantOffset(N))
1318 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1319 int RHSC = (int)RHS->getSExtValue();
1320 if (N.getOpcode() == ISD::SUB)
1323 if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative)
1324 Base = N.getOperand(0);
1325 if (Base.getOpcode() == ISD::FrameIndex) {
1326 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1327 Base = CurDAG->getTargetFrameIndex(FI,
1328 getTargetLowering()->getPointerTy());
1330 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1338 bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
1340 unsigned Opcode = Op->getOpcode();
1341 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
1342 ? cast<LoadSDNode>(Op)->getAddressingMode()
1343 : cast<StoreSDNode>(Op)->getAddressingMode();
1345 if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x100, RHSC)) { // 8 bits.
1346 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
1347 ? CurDAG->getTargetConstant(RHSC, MVT::i32)
1348 : CurDAG->getTargetConstant(-RHSC, MVT::i32);
1355 bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue N,
1357 SDValue &OffReg, SDValue &ShImm) {
1358 // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.
1359 if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N))
1362 // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8.
1363 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1364 int RHSC = (int)RHS->getZExtValue();
1365 if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned)
1367 else if (RHSC < 0 && RHSC >= -255) // 8 bits
1371 // Look for (R + R) or (R + (R << [1,2,3])).
1373 Base = N.getOperand(0);
1374 OffReg = N.getOperand(1);
1376 // Swap if it is ((R << c) + R).
1377 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode());
1378 if (ShOpcVal != ARM_AM::lsl) {
1379 ShOpcVal = ARM_AM::getShiftOpcForNode(Base.getOpcode());
1380 if (ShOpcVal == ARM_AM::lsl)
1381 std::swap(Base, OffReg);
1384 if (ShOpcVal == ARM_AM::lsl) {
1385 // Check to see if the RHS of the shift is a constant, if not, we can't fold
1387 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
1388 ShAmt = Sh->getZExtValue();
1389 if (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt))
1390 OffReg = OffReg.getOperand(0);
1393 ShOpcVal = ARM_AM::no_shift;
1396 ShOpcVal = ARM_AM::no_shift;
1400 ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
1405 bool ARMDAGToDAGISel::SelectT2AddrModeExclusive(SDValue N, SDValue &Base,
1407 // This *must* succeed since it's used for the irreplaceable ldrex and strex
1410 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1412 if (N.getOpcode() != ISD::ADD || !CurDAG->isBaseWithConstantOffset(N))
1415 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
1419 uint32_t RHSC = (int)RHS->getZExtValue();
1420 if (RHSC > 1020 || RHSC % 4 != 0)
1423 Base = N.getOperand(0);
1424 if (Base.getOpcode() == ISD::FrameIndex) {
1425 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1426 Base = CurDAG->getTargetFrameIndex(FI, getTargetLowering()->getPointerTy());
1429 OffImm = CurDAG->getTargetConstant(RHSC / 4, MVT::i32);
1433 //===--------------------------------------------------------------------===//
1435 /// getAL - Returns a ARMCC::AL immediate node.
1436 static inline SDValue getAL(SelectionDAG *CurDAG) {
1437 return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
1440 SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDNode *N) {
1441 LoadSDNode *LD = cast<LoadSDNode>(N);
1442 ISD::MemIndexedMode AM = LD->getAddressingMode();
1443 if (AM == ISD::UNINDEXED)
1446 EVT LoadedVT = LD->getMemoryVT();
1447 SDValue Offset, AMOpc;
1448 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1449 unsigned Opcode = 0;
1451 if (LoadedVT == MVT::i32 && isPre &&
1452 SelectAddrMode2OffsetImmPre(N, LD->getOffset(), Offset, AMOpc)) {
1453 Opcode = ARM::LDR_PRE_IMM;
1455 } else if (LoadedVT == MVT::i32 && !isPre &&
1456 SelectAddrMode2OffsetImm(N, LD->getOffset(), Offset, AMOpc)) {
1457 Opcode = ARM::LDR_POST_IMM;
1459 } else if (LoadedVT == MVT::i32 &&
1460 SelectAddrMode2OffsetReg(N, LD->getOffset(), Offset, AMOpc)) {
1461 Opcode = isPre ? ARM::LDR_PRE_REG : ARM::LDR_POST_REG;
1464 } else if (LoadedVT == MVT::i16 &&
1465 SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1467 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
1468 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
1469 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
1470 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
1471 if (LD->getExtensionType() == ISD::SEXTLOAD) {
1472 if (SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1474 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
1478 SelectAddrMode2OffsetImmPre(N, LD->getOffset(), Offset, AMOpc)) {
1480 Opcode = ARM::LDRB_PRE_IMM;
1481 } else if (!isPre &&
1482 SelectAddrMode2OffsetImm(N, LD->getOffset(), Offset, AMOpc)) {
1484 Opcode = ARM::LDRB_POST_IMM;
1485 } else if (SelectAddrMode2OffsetReg(N, LD->getOffset(), Offset, AMOpc)) {
1487 Opcode = isPre ? ARM::LDRB_PRE_REG : ARM::LDRB_POST_REG;
1493 if (Opcode == ARM::LDR_PRE_IMM || Opcode == ARM::LDRB_PRE_IMM) {
1494 SDValue Chain = LD->getChain();
1495 SDValue Base = LD->getBasePtr();
1496 SDValue Ops[]= { Base, AMOpc, getAL(CurDAG),
1497 CurDAG->getRegister(0, MVT::i32), Chain };
1498 return CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i32,
1499 MVT::i32, MVT::Other, Ops);
1501 SDValue Chain = LD->getChain();
1502 SDValue Base = LD->getBasePtr();
1503 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
1504 CurDAG->getRegister(0, MVT::i32), Chain };
1505 return CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i32,
1506 MVT::i32, MVT::Other, Ops);
1513 SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDNode *N) {
1514 LoadSDNode *LD = cast<LoadSDNode>(N);
1515 ISD::MemIndexedMode AM = LD->getAddressingMode();
1516 if (AM == ISD::UNINDEXED)
1519 EVT LoadedVT = LD->getMemoryVT();
1520 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
1522 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1523 unsigned Opcode = 0;
1525 if (SelectT2AddrModeImm8Offset(N, LD->getOffset(), Offset)) {
1526 switch (LoadedVT.getSimpleVT().SimpleTy) {
1528 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
1532 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
1534 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
1539 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
1541 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
1550 SDValue Chain = LD->getChain();
1551 SDValue Base = LD->getBasePtr();
1552 SDValue Ops[]= { Base, Offset, getAL(CurDAG),
1553 CurDAG->getRegister(0, MVT::i32), Chain };
1554 return CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i32, MVT::i32,
1561 /// \brief Form a GPRPair pseudo register from a pair of GPR regs.
1562 SDNode *ARMDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) {
1563 SDLoc dl(V0.getNode());
1565 CurDAG->getTargetConstant(ARM::GPRPairRegClassID, MVT::i32);
1566 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::gsub_0, MVT::i32);
1567 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::gsub_1, MVT::i32);
1568 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1569 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1572 /// \brief Form a D register from a pair of S registers.
1573 SDNode *ARMDAGToDAGISel::createSRegPairNode(EVT VT, SDValue V0, SDValue V1) {
1574 SDLoc dl(V0.getNode());
1576 CurDAG->getTargetConstant(ARM::DPR_VFP2RegClassID, MVT::i32);
1577 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1578 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1579 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1580 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1583 /// \brief Form a quad register from a pair of D registers.
1584 SDNode *ARMDAGToDAGISel::createDRegPairNode(EVT VT, SDValue V0, SDValue V1) {
1585 SDLoc dl(V0.getNode());
1586 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, MVT::i32);
1587 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1588 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1589 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1590 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1593 /// \brief Form 4 consecutive D registers from a pair of Q registers.
1594 SDNode *ARMDAGToDAGISel::createQRegPairNode(EVT VT, SDValue V0, SDValue V1) {
1595 SDLoc dl(V0.getNode());
1596 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32);
1597 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1598 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1599 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1600 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1603 /// \brief Form 4 consecutive S registers.
1604 SDNode *ARMDAGToDAGISel::createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1,
1605 SDValue V2, SDValue V3) {
1606 SDLoc dl(V0.getNode());
1608 CurDAG->getTargetConstant(ARM::QPR_VFP2RegClassID, MVT::i32);
1609 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1610 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1611 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, MVT::i32);
1612 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::ssub_3, MVT::i32);
1613 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1614 V2, SubReg2, V3, SubReg3 };
1615 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1618 /// \brief Form 4 consecutive D registers.
1619 SDNode *ARMDAGToDAGISel::createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1,
1620 SDValue V2, SDValue V3) {
1621 SDLoc dl(V0.getNode());
1622 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32);
1623 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1624 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1625 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, MVT::i32);
1626 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, MVT::i32);
1627 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1628 V2, SubReg2, V3, SubReg3 };
1629 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1632 /// \brief Form 4 consecutive Q registers.
1633 SDNode *ARMDAGToDAGISel::createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1,
1634 SDValue V2, SDValue V3) {
1635 SDLoc dl(V0.getNode());
1636 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, MVT::i32);
1637 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1638 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1639 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, MVT::i32);
1640 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, MVT::i32);
1641 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1642 V2, SubReg2, V3, SubReg3 };
1643 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops);
1646 /// GetVLDSTAlign - Get the alignment (in bytes) for the alignment operand
1647 /// of a NEON VLD or VST instruction. The supported values depend on the
1648 /// number of registers being loaded.
1649 SDValue ARMDAGToDAGISel::GetVLDSTAlign(SDValue Align, unsigned NumVecs,
1650 bool is64BitVector) {
1651 unsigned NumRegs = NumVecs;
1652 if (!is64BitVector && NumVecs < 3)
1655 unsigned Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1656 if (Alignment >= 32 && NumRegs == 4)
1658 else if (Alignment >= 16 && (NumRegs == 2 || NumRegs == 4))
1660 else if (Alignment >= 8)
1665 return CurDAG->getTargetConstant(Alignment, MVT::i32);
1668 static bool isVLDfixed(unsigned Opc)
1671 default: return false;
1672 case ARM::VLD1d8wb_fixed : return true;
1673 case ARM::VLD1d16wb_fixed : return true;
1674 case ARM::VLD1d64Qwb_fixed : return true;
1675 case ARM::VLD1d32wb_fixed : return true;
1676 case ARM::VLD1d64wb_fixed : return true;
1677 case ARM::VLD1d64TPseudoWB_fixed : return true;
1678 case ARM::VLD1d64QPseudoWB_fixed : return true;
1679 case ARM::VLD1q8wb_fixed : return true;
1680 case ARM::VLD1q16wb_fixed : return true;
1681 case ARM::VLD1q32wb_fixed : return true;
1682 case ARM::VLD1q64wb_fixed : return true;
1683 case ARM::VLD2d8wb_fixed : return true;
1684 case ARM::VLD2d16wb_fixed : return true;
1685 case ARM::VLD2d32wb_fixed : return true;
1686 case ARM::VLD2q8PseudoWB_fixed : return true;
1687 case ARM::VLD2q16PseudoWB_fixed : return true;
1688 case ARM::VLD2q32PseudoWB_fixed : return true;
1689 case ARM::VLD2DUPd8wb_fixed : return true;
1690 case ARM::VLD2DUPd16wb_fixed : return true;
1691 case ARM::VLD2DUPd32wb_fixed : return true;
1695 static bool isVSTfixed(unsigned Opc)
1698 default: return false;
1699 case ARM::VST1d8wb_fixed : return true;
1700 case ARM::VST1d16wb_fixed : return true;
1701 case ARM::VST1d32wb_fixed : return true;
1702 case ARM::VST1d64wb_fixed : return true;
1703 case ARM::VST1q8wb_fixed : return true;
1704 case ARM::VST1q16wb_fixed : return true;
1705 case ARM::VST1q32wb_fixed : return true;
1706 case ARM::VST1q64wb_fixed : return true;
1707 case ARM::VST1d64TPseudoWB_fixed : return true;
1708 case ARM::VST1d64QPseudoWB_fixed : return true;
1709 case ARM::VST2d8wb_fixed : return true;
1710 case ARM::VST2d16wb_fixed : return true;
1711 case ARM::VST2d32wb_fixed : return true;
1712 case ARM::VST2q8PseudoWB_fixed : return true;
1713 case ARM::VST2q16PseudoWB_fixed : return true;
1714 case ARM::VST2q32PseudoWB_fixed : return true;
1718 // Get the register stride update opcode of a VLD/VST instruction that
1719 // is otherwise equivalent to the given fixed stride updating instruction.
1720 static unsigned getVLDSTRegisterUpdateOpcode(unsigned Opc) {
1721 assert((isVLDfixed(Opc) || isVSTfixed(Opc))
1722 && "Incorrect fixed stride updating instruction.");
1725 case ARM::VLD1d8wb_fixed: return ARM::VLD1d8wb_register;
1726 case ARM::VLD1d16wb_fixed: return ARM::VLD1d16wb_register;
1727 case ARM::VLD1d32wb_fixed: return ARM::VLD1d32wb_register;
1728 case ARM::VLD1d64wb_fixed: return ARM::VLD1d64wb_register;
1729 case ARM::VLD1q8wb_fixed: return ARM::VLD1q8wb_register;
1730 case ARM::VLD1q16wb_fixed: return ARM::VLD1q16wb_register;
1731 case ARM::VLD1q32wb_fixed: return ARM::VLD1q32wb_register;
1732 case ARM::VLD1q64wb_fixed: return ARM::VLD1q64wb_register;
1733 case ARM::VLD1d64Twb_fixed: return ARM::VLD1d64Twb_register;
1734 case ARM::VLD1d64Qwb_fixed: return ARM::VLD1d64Qwb_register;
1735 case ARM::VLD1d64TPseudoWB_fixed: return ARM::VLD1d64TPseudoWB_register;
1736 case ARM::VLD1d64QPseudoWB_fixed: return ARM::VLD1d64QPseudoWB_register;
1738 case ARM::VST1d8wb_fixed: return ARM::VST1d8wb_register;
1739 case ARM::VST1d16wb_fixed: return ARM::VST1d16wb_register;
1740 case ARM::VST1d32wb_fixed: return ARM::VST1d32wb_register;
1741 case ARM::VST1d64wb_fixed: return ARM::VST1d64wb_register;
1742 case ARM::VST1q8wb_fixed: return ARM::VST1q8wb_register;
1743 case ARM::VST1q16wb_fixed: return ARM::VST1q16wb_register;
1744 case ARM::VST1q32wb_fixed: return ARM::VST1q32wb_register;
1745 case ARM::VST1q64wb_fixed: return ARM::VST1q64wb_register;
1746 case ARM::VST1d64TPseudoWB_fixed: return ARM::VST1d64TPseudoWB_register;
1747 case ARM::VST1d64QPseudoWB_fixed: return ARM::VST1d64QPseudoWB_register;
1749 case ARM::VLD2d8wb_fixed: return ARM::VLD2d8wb_register;
1750 case ARM::VLD2d16wb_fixed: return ARM::VLD2d16wb_register;
1751 case ARM::VLD2d32wb_fixed: return ARM::VLD2d32wb_register;
1752 case ARM::VLD2q8PseudoWB_fixed: return ARM::VLD2q8PseudoWB_register;
1753 case ARM::VLD2q16PseudoWB_fixed: return ARM::VLD2q16PseudoWB_register;
1754 case ARM::VLD2q32PseudoWB_fixed: return ARM::VLD2q32PseudoWB_register;
1756 case ARM::VST2d8wb_fixed: return ARM::VST2d8wb_register;
1757 case ARM::VST2d16wb_fixed: return ARM::VST2d16wb_register;
1758 case ARM::VST2d32wb_fixed: return ARM::VST2d32wb_register;
1759 case ARM::VST2q8PseudoWB_fixed: return ARM::VST2q8PseudoWB_register;
1760 case ARM::VST2q16PseudoWB_fixed: return ARM::VST2q16PseudoWB_register;
1761 case ARM::VST2q32PseudoWB_fixed: return ARM::VST2q32PseudoWB_register;
1763 case ARM::VLD2DUPd8wb_fixed: return ARM::VLD2DUPd8wb_register;
1764 case ARM::VLD2DUPd16wb_fixed: return ARM::VLD2DUPd16wb_register;
1765 case ARM::VLD2DUPd32wb_fixed: return ARM::VLD2DUPd32wb_register;
1767 return Opc; // If not one we handle, return it unchanged.
1770 SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
1771 const uint16_t *DOpcodes,
1772 const uint16_t *QOpcodes0,
1773 const uint16_t *QOpcodes1) {
1774 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range");
1777 SDValue MemAddr, Align;
1778 unsigned AddrOpIdx = isUpdating ? 1 : 2;
1779 if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1782 SDValue Chain = N->getOperand(0);
1783 EVT VT = N->getValueType(0);
1784 bool is64BitVector = VT.is64BitVector();
1785 Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1787 unsigned OpcodeIndex;
1788 switch (VT.getSimpleVT().SimpleTy) {
1789 default: llvm_unreachable("unhandled vld type");
1790 // Double-register operations:
1791 case MVT::v8i8: OpcodeIndex = 0; break;
1792 case MVT::v4i16: OpcodeIndex = 1; break;
1794 case MVT::v2i32: OpcodeIndex = 2; break;
1795 case MVT::v1i64: OpcodeIndex = 3; break;
1796 // Quad-register operations:
1797 case MVT::v16i8: OpcodeIndex = 0; break;
1798 case MVT::v8i16: OpcodeIndex = 1; break;
1800 case MVT::v4i32: OpcodeIndex = 2; break;
1801 case MVT::v2i64: OpcodeIndex = 3;
1802 assert(NumVecs == 1 && "v2i64 type only supported for VLD1");
1810 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1813 ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts);
1815 std::vector<EVT> ResTys;
1816 ResTys.push_back(ResTy);
1818 ResTys.push_back(MVT::i32);
1819 ResTys.push_back(MVT::Other);
1821 SDValue Pred = getAL(CurDAG);
1822 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1824 SmallVector<SDValue, 7> Ops;
1826 // Double registers and VLD1/VLD2 quad registers are directly supported.
1827 if (is64BitVector || NumVecs <= 2) {
1828 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1829 QOpcodes0[OpcodeIndex]);
1830 Ops.push_back(MemAddr);
1831 Ops.push_back(Align);
1833 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1834 // FIXME: VLD1/VLD2 fixed increment doesn't need Reg0. Remove the reg0
1835 // case entirely when the rest are updated to that form, too.
1836 if ((NumVecs <= 2) && !isa<ConstantSDNode>(Inc.getNode()))
1837 Opc = getVLDSTRegisterUpdateOpcode(Opc);
1838 // FIXME: We use a VLD1 for v1i64 even if the pseudo says vld2/3/4, so
1839 // check for that explicitly too. Horribly hacky, but temporary.
1840 if ((NumVecs > 2 && !isVLDfixed(Opc)) ||
1841 !isa<ConstantSDNode>(Inc.getNode()))
1842 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1844 Ops.push_back(Pred);
1845 Ops.push_back(Reg0);
1846 Ops.push_back(Chain);
1847 VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
1850 // Otherwise, quad registers are loaded with two separate instructions,
1851 // where one loads the even registers and the other loads the odd registers.
1852 EVT AddrTy = MemAddr.getValueType();
1854 // Load the even subregs. This is always an updating load, so that it
1855 // provides the address to the second load for the odd subregs.
1857 SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy), 0);
1858 const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain };
1859 SDNode *VLdA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl,
1860 ResTy, AddrTy, MVT::Other, OpsA);
1861 Chain = SDValue(VLdA, 2);
1863 // Load the odd subregs.
1864 Ops.push_back(SDValue(VLdA, 1));
1865 Ops.push_back(Align);
1867 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1868 assert(isa<ConstantSDNode>(Inc.getNode()) &&
1869 "only constant post-increment update allowed for VLD3/4");
1871 Ops.push_back(Reg0);
1873 Ops.push_back(SDValue(VLdA, 0));
1874 Ops.push_back(Pred);
1875 Ops.push_back(Reg0);
1876 Ops.push_back(Chain);
1877 VLd = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys, Ops);
1880 // Transfer memoperands.
1881 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1882 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1883 cast<MachineSDNode>(VLd)->setMemRefs(MemOp, MemOp + 1);
1888 // Extract out the subregisters.
1889 SDValue SuperReg = SDValue(VLd, 0);
1890 assert(ARM::dsub_7 == ARM::dsub_0+7 &&
1891 ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1892 unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0);
1893 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1894 ReplaceUses(SDValue(N, Vec),
1895 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
1896 ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1));
1898 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLd, 2));
1902 SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
1903 const uint16_t *DOpcodes,
1904 const uint16_t *QOpcodes0,
1905 const uint16_t *QOpcodes1) {
1906 assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range");
1909 SDValue MemAddr, Align;
1910 unsigned AddrOpIdx = isUpdating ? 1 : 2;
1911 unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
1912 if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1915 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1916 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1918 SDValue Chain = N->getOperand(0);
1919 EVT VT = N->getOperand(Vec0Idx).getValueType();
1920 bool is64BitVector = VT.is64BitVector();
1921 Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1923 unsigned OpcodeIndex;
1924 switch (VT.getSimpleVT().SimpleTy) {
1925 default: llvm_unreachable("unhandled vst type");
1926 // Double-register operations:
1927 case MVT::v8i8: OpcodeIndex = 0; break;
1928 case MVT::v4i16: OpcodeIndex = 1; break;
1930 case MVT::v2i32: OpcodeIndex = 2; break;
1931 case MVT::v1i64: OpcodeIndex = 3; break;
1932 // Quad-register operations:
1933 case MVT::v16i8: OpcodeIndex = 0; break;
1934 case MVT::v8i16: OpcodeIndex = 1; break;
1936 case MVT::v4i32: OpcodeIndex = 2; break;
1937 case MVT::v2i64: OpcodeIndex = 3;
1938 assert(NumVecs == 1 && "v2i64 type only supported for VST1");
1942 std::vector<EVT> ResTys;
1944 ResTys.push_back(MVT::i32);
1945 ResTys.push_back(MVT::Other);
1947 SDValue Pred = getAL(CurDAG);
1948 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1949 SmallVector<SDValue, 7> Ops;
1951 // Double registers and VST1/VST2 quad registers are directly supported.
1952 if (is64BitVector || NumVecs <= 2) {
1955 SrcReg = N->getOperand(Vec0Idx);
1956 } else if (is64BitVector) {
1957 // Form a REG_SEQUENCE to force register allocation.
1958 SDValue V0 = N->getOperand(Vec0Idx + 0);
1959 SDValue V1 = N->getOperand(Vec0Idx + 1);
1961 SrcReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0);
1963 SDValue V2 = N->getOperand(Vec0Idx + 2);
1964 // If it's a vst3, form a quad D-register and leave the last part as
1966 SDValue V3 = (NumVecs == 3)
1967 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1968 : N->getOperand(Vec0Idx + 3);
1969 SrcReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);
1972 // Form a QQ register.
1973 SDValue Q0 = N->getOperand(Vec0Idx);
1974 SDValue Q1 = N->getOperand(Vec0Idx + 1);
1975 SrcReg = SDValue(createQRegPairNode(MVT::v4i64, Q0, Q1), 0);
1978 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1979 QOpcodes0[OpcodeIndex]);
1980 Ops.push_back(MemAddr);
1981 Ops.push_back(Align);
1983 SDValue Inc = N->getOperand(AddrOpIdx + 1);
1984 // FIXME: VST1/VST2 fixed increment doesn't need Reg0. Remove the reg0
1985 // case entirely when the rest are updated to that form, too.
1986 if (NumVecs <= 2 && !isa<ConstantSDNode>(Inc.getNode()))
1987 Opc = getVLDSTRegisterUpdateOpcode(Opc);
1988 // FIXME: We use a VST1 for v1i64 even if the pseudo says vld2/3/4, so
1989 // check for that explicitly too. Horribly hacky, but temporary.
1990 if (!isa<ConstantSDNode>(Inc.getNode()))
1992 else if (NumVecs > 2 && !isVSTfixed(Opc))
1993 Ops.push_back(Reg0);
1995 Ops.push_back(SrcReg);
1996 Ops.push_back(Pred);
1997 Ops.push_back(Reg0);
1998 Ops.push_back(Chain);
1999 SDNode *VSt = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
2001 // Transfer memoperands.
2002 cast<MachineSDNode>(VSt)->setMemRefs(MemOp, MemOp + 1);
2007 // Otherwise, quad registers are stored with two separate instructions,
2008 // where one stores the even registers and the other stores the odd registers.
2010 // Form the QQQQ REG_SEQUENCE.
2011 SDValue V0 = N->getOperand(Vec0Idx + 0);
2012 SDValue V1 = N->getOperand(Vec0Idx + 1);
2013 SDValue V2 = N->getOperand(Vec0Idx + 2);
2014 SDValue V3 = (NumVecs == 3)
2015 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
2016 : N->getOperand(Vec0Idx + 3);
2017 SDValue RegSeq = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0);
2019 // Store the even D registers. This is always an updating store, so that it
2020 // provides the address to the second store for the odd subregs.
2021 const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain };
2022 SDNode *VStA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl,
2023 MemAddr.getValueType(),
2025 cast<MachineSDNode>(VStA)->setMemRefs(MemOp, MemOp + 1);
2026 Chain = SDValue(VStA, 1);
2028 // Store the odd D registers.
2029 Ops.push_back(SDValue(VStA, 0));
2030 Ops.push_back(Align);
2032 SDValue Inc = N->getOperand(AddrOpIdx + 1);
2033 assert(isa<ConstantSDNode>(Inc.getNode()) &&
2034 "only constant post-increment update allowed for VST3/4");
2036 Ops.push_back(Reg0);
2038 Ops.push_back(RegSeq);
2039 Ops.push_back(Pred);
2040 Ops.push_back(Reg0);
2041 Ops.push_back(Chain);
2042 SDNode *VStB = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys,
2044 cast<MachineSDNode>(VStB)->setMemRefs(MemOp, MemOp + 1);
2048 SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
2049 bool isUpdating, unsigned NumVecs,
2050 const uint16_t *DOpcodes,
2051 const uint16_t *QOpcodes) {
2052 assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
2055 SDValue MemAddr, Align;
2056 unsigned AddrOpIdx = isUpdating ? 1 : 2;
2057 unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
2058 if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
2061 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2062 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
2064 SDValue Chain = N->getOperand(0);
2066 cast<ConstantSDNode>(N->getOperand(Vec0Idx + NumVecs))->getZExtValue();
2067 EVT VT = N->getOperand(Vec0Idx).getValueType();
2068 bool is64BitVector = VT.is64BitVector();
2070 unsigned Alignment = 0;
2072 Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
2073 unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
2074 if (Alignment > NumBytes)
2075 Alignment = NumBytes;
2076 if (Alignment < 8 && Alignment < NumBytes)
2078 // Alignment must be a power of two; make sure of that.
2079 Alignment = (Alignment & -Alignment);
2083 Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
2085 unsigned OpcodeIndex;
2086 switch (VT.getSimpleVT().SimpleTy) {
2087 default: llvm_unreachable("unhandled vld/vst lane type");
2088 // Double-register operations:
2089 case MVT::v8i8: OpcodeIndex = 0; break;
2090 case MVT::v4i16: OpcodeIndex = 1; break;
2092 case MVT::v2i32: OpcodeIndex = 2; break;
2093 // Quad-register operations:
2094 case MVT::v8i16: OpcodeIndex = 0; break;
2096 case MVT::v4i32: OpcodeIndex = 1; break;
2099 std::vector<EVT> ResTys;
2101 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
2104 ResTys.push_back(EVT::getVectorVT(*CurDAG->getContext(),
2105 MVT::i64, ResTyElts));
2108 ResTys.push_back(MVT::i32);
2109 ResTys.push_back(MVT::Other);
2111 SDValue Pred = getAL(CurDAG);
2112 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2114 SmallVector<SDValue, 8> Ops;
2115 Ops.push_back(MemAddr);
2116 Ops.push_back(Align);
2118 SDValue Inc = N->getOperand(AddrOpIdx + 1);
2119 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
2123 SDValue V0 = N->getOperand(Vec0Idx + 0);
2124 SDValue V1 = N->getOperand(Vec0Idx + 1);
2127 SuperReg = SDValue(createDRegPairNode(MVT::v2i64, V0, V1), 0);
2129 SuperReg = SDValue(createQRegPairNode(MVT::v4i64, V0, V1), 0);
2131 SDValue V2 = N->getOperand(Vec0Idx + 2);
2132 SDValue V3 = (NumVecs == 3)
2133 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
2134 : N->getOperand(Vec0Idx + 3);
2136 SuperReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);
2138 SuperReg = SDValue(createQuadQRegsNode(MVT::v8i64, V0, V1, V2, V3), 0);
2140 Ops.push_back(SuperReg);
2141 Ops.push_back(getI32Imm(Lane));
2142 Ops.push_back(Pred);
2143 Ops.push_back(Reg0);
2144 Ops.push_back(Chain);
2146 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
2147 QOpcodes[OpcodeIndex]);
2148 SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
2149 cast<MachineSDNode>(VLdLn)->setMemRefs(MemOp, MemOp + 1);
2153 // Extract the subregisters.
2154 SuperReg = SDValue(VLdLn, 0);
2155 assert(ARM::dsub_7 == ARM::dsub_0+7 &&
2156 ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
2157 unsigned Sub0 = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;
2158 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
2159 ReplaceUses(SDValue(N, Vec),
2160 CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
2161 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, 1));
2163 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdLn, 2));
2167 SDNode *ARMDAGToDAGISel::SelectVLDDup(SDNode *N, bool isUpdating,
2169 const uint16_t *Opcodes) {
2170 assert(NumVecs >=2 && NumVecs <= 4 && "VLDDup NumVecs out-of-range");
2173 SDValue MemAddr, Align;
2174 if (!SelectAddrMode6(N, N->getOperand(1), MemAddr, Align))
2177 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2178 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
2180 SDValue Chain = N->getOperand(0);
2181 EVT VT = N->getValueType(0);
2183 unsigned Alignment = 0;
2185 Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
2186 unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
2187 if (Alignment > NumBytes)
2188 Alignment = NumBytes;
2189 if (Alignment < 8 && Alignment < NumBytes)
2191 // Alignment must be a power of two; make sure of that.
2192 Alignment = (Alignment & -Alignment);
2196 Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
2198 unsigned OpcodeIndex;
2199 switch (VT.getSimpleVT().SimpleTy) {
2200 default: llvm_unreachable("unhandled vld-dup type");
2201 case MVT::v8i8: OpcodeIndex = 0; break;
2202 case MVT::v4i16: OpcodeIndex = 1; break;
2204 case MVT::v2i32: OpcodeIndex = 2; break;
2207 SDValue Pred = getAL(CurDAG);
2208 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2210 unsigned Opc = Opcodes[OpcodeIndex];
2211 SmallVector<SDValue, 6> Ops;
2212 Ops.push_back(MemAddr);
2213 Ops.push_back(Align);
2215 // fixed-stride update instructions don't have an explicit writeback
2216 // operand. It's implicit in the opcode itself.
2217 SDValue Inc = N->getOperand(2);
2218 if (!isa<ConstantSDNode>(Inc.getNode()))
2220 // FIXME: VLD3 and VLD4 haven't been updated to that form yet.
2221 else if (NumVecs > 2)
2222 Ops.push_back(Reg0);
2224 Ops.push_back(Pred);
2225 Ops.push_back(Reg0);
2226 Ops.push_back(Chain);
2228 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
2229 std::vector<EVT> ResTys;
2230 ResTys.push_back(EVT::getVectorVT(*CurDAG->getContext(), MVT::i64,ResTyElts));
2232 ResTys.push_back(MVT::i32);
2233 ResTys.push_back(MVT::Other);
2234 SDNode *VLdDup = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
2235 cast<MachineSDNode>(VLdDup)->setMemRefs(MemOp, MemOp + 1);
2236 SuperReg = SDValue(VLdDup, 0);
2238 // Extract the subregisters.
2239 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2240 unsigned SubIdx = ARM::dsub_0;
2241 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
2242 ReplaceUses(SDValue(N, Vec),
2243 CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, SuperReg));
2244 ReplaceUses(SDValue(N, NumVecs), SDValue(VLdDup, 1));
2246 ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdDup, 2));
2250 SDNode *ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs,
2252 assert(NumVecs >= 2 && NumVecs <= 4 && "VTBL NumVecs out-of-range");
2254 EVT VT = N->getValueType(0);
2255 unsigned FirstTblReg = IsExt ? 2 : 1;
2257 // Form a REG_SEQUENCE to force register allocation.
2259 SDValue V0 = N->getOperand(FirstTblReg + 0);
2260 SDValue V1 = N->getOperand(FirstTblReg + 1);
2262 RegSeq = SDValue(createDRegPairNode(MVT::v16i8, V0, V1), 0);
2264 SDValue V2 = N->getOperand(FirstTblReg + 2);
2265 // If it's a vtbl3, form a quad D-register and leave the last part as
2267 SDValue V3 = (NumVecs == 3)
2268 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
2269 : N->getOperand(FirstTblReg + 3);
2270 RegSeq = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0);
2273 SmallVector<SDValue, 6> Ops;
2275 Ops.push_back(N->getOperand(1));
2276 Ops.push_back(RegSeq);
2277 Ops.push_back(N->getOperand(FirstTblReg + NumVecs));
2278 Ops.push_back(getAL(CurDAG)); // predicate
2279 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // predicate register
2280 return CurDAG->getMachineNode(Opc, dl, VT, Ops);
2283 SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N,
2285 if (!Subtarget->hasV6T2Ops())
2288 unsigned Opc = isSigned
2289 ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX)
2290 : (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX);
2292 // For unsigned extracts, check for a shift right and mask
2293 unsigned And_imm = 0;
2294 if (N->getOpcode() == ISD::AND) {
2295 if (isOpcWithIntImmediate(N, ISD::AND, And_imm)) {
2297 // The immediate is a mask of the low bits iff imm & (imm+1) == 0
2298 if (And_imm & (And_imm + 1))
2301 unsigned Srl_imm = 0;
2302 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL,
2304 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
2306 // Note: The width operand is encoded as width-1.
2307 unsigned Width = CountTrailingOnes_32(And_imm) - 1;
2308 unsigned LSB = Srl_imm;
2310 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2312 if ((LSB + Width + 1) == N->getValueType(0).getSizeInBits()) {
2313 // It's cheaper to use a right shift to extract the top bits.
2314 if (Subtarget->isThumb()) {
2315 Opc = isSigned ? ARM::t2ASRri : ARM::t2LSRri;
2316 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2317 CurDAG->getTargetConstant(LSB, MVT::i32),
2318 getAL(CurDAG), Reg0, Reg0 };
2319 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2322 // ARM models shift instructions as MOVsi with shifter operand.
2323 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(ISD::SRL);
2325 CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, LSB),
2327 SDValue Ops[] = { N->getOperand(0).getOperand(0), ShOpc,
2328 getAL(CurDAG), Reg0, Reg0 };
2329 return CurDAG->SelectNodeTo(N, ARM::MOVsi, MVT::i32, Ops, 5);
2332 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2333 CurDAG->getTargetConstant(LSB, MVT::i32),
2334 CurDAG->getTargetConstant(Width, MVT::i32),
2335 getAL(CurDAG), Reg0 };
2336 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2342 // Otherwise, we're looking for a shift of a shift
2343 unsigned Shl_imm = 0;
2344 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, Shl_imm)) {
2345 assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!");
2346 unsigned Srl_imm = 0;
2347 if (isInt32Immediate(N->getOperand(1), Srl_imm)) {
2348 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
2349 // Note: The width operand is encoded as width-1.
2350 unsigned Width = 32 - Srl_imm - 1;
2351 int LSB = Srl_imm - Shl_imm;
2354 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2355 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2356 CurDAG->getTargetConstant(LSB, MVT::i32),
2357 CurDAG->getTargetConstant(Width, MVT::i32),
2358 getAL(CurDAG), Reg0 };
2359 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2365 /// Target-specific DAG combining for ISD::XOR.
2366 /// Target-independent combining lowers SELECT_CC nodes of the form
2367 /// select_cc setg[ge] X, 0, X, -X
2368 /// select_cc setgt X, -1, X, -X
2369 /// select_cc setl[te] X, 0, -X, X
2370 /// select_cc setlt X, 1, -X, X
2371 /// which represent Integer ABS into:
2372 /// Y = sra (X, size(X)-1); xor (add (X, Y), Y)
2373 /// ARM instruction selection detects the latter and matches it to
2374 /// ARM::ABS or ARM::t2ABS machine node.
2375 SDNode *ARMDAGToDAGISel::SelectABSOp(SDNode *N){
2376 SDValue XORSrc0 = N->getOperand(0);
2377 SDValue XORSrc1 = N->getOperand(1);
2378 EVT VT = N->getValueType(0);
2380 if (Subtarget->isThumb1Only())
2383 if (XORSrc0.getOpcode() != ISD::ADD || XORSrc1.getOpcode() != ISD::SRA)
2386 SDValue ADDSrc0 = XORSrc0.getOperand(0);
2387 SDValue ADDSrc1 = XORSrc0.getOperand(1);
2388 SDValue SRASrc0 = XORSrc1.getOperand(0);
2389 SDValue SRASrc1 = XORSrc1.getOperand(1);
2390 ConstantSDNode *SRAConstant = dyn_cast<ConstantSDNode>(SRASrc1);
2391 EVT XType = SRASrc0.getValueType();
2392 unsigned Size = XType.getSizeInBits() - 1;
2394 if (ADDSrc1 == XORSrc1 && ADDSrc0 == SRASrc0 &&
2395 XType.isInteger() && SRAConstant != nullptr &&
2396 Size == SRAConstant->getZExtValue()) {
2397 unsigned Opcode = Subtarget->isThumb2() ? ARM::t2ABS : ARM::ABS;
2398 return CurDAG->SelectNodeTo(N, Opcode, VT, ADDSrc0);
2404 SDNode *ARMDAGToDAGISel::SelectConcatVector(SDNode *N) {
2405 // The only time a CONCAT_VECTORS operation can have legal types is when
2406 // two 64-bit vectors are concatenated to a 128-bit vector.
2407 EVT VT = N->getValueType(0);
2408 if (!VT.is128BitVector() || N->getNumOperands() != 2)
2409 llvm_unreachable("unexpected CONCAT_VECTORS");
2410 return createDRegPairNode(VT, N->getOperand(0), N->getOperand(1));
2413 SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
2416 if (N->isMachineOpcode()) {
2418 return nullptr; // Already selected.
2421 switch (N->getOpcode()) {
2423 case ISD::INLINEASM: {
2424 SDNode *ResNode = SelectInlineAsm(N);
2430 // Select special operations if XOR node forms integer ABS pattern
2431 SDNode *ResNode = SelectABSOp(N);
2434 // Other cases are autogenerated.
2437 case ISD::Constant: {
2438 unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
2440 if (Subtarget->useMovt())
2441 // Thumb2-aware targets have the MOVT instruction, so all immediates can
2442 // be done with MOV + MOVT, at worst.
2445 if (Subtarget->isThumb()) {
2446 UseCP = (Val > 255 && // MOV
2447 ~Val > 255 && // MOV + MVN
2448 !ARM_AM::isThumbImmShiftedVal(Val) && // MOV + LSL
2449 !(Subtarget->hasV6T2Ops() && Val <= 0xffff)); // MOVW
2451 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
2452 ARM_AM::getSOImmVal(~Val) == -1 && // MVN
2453 !ARM_AM::isSOImmTwoPartVal(Val) && // two instrs.
2454 !(Subtarget->hasV6T2Ops() && Val <= 0xffff)); // MOVW
2459 CurDAG->getTargetConstantPool(ConstantInt::get(
2460 Type::getInt32Ty(*CurDAG->getContext()), Val),
2461 getTargetLowering()->getPointerTy());
2464 if (Subtarget->isThumb()) {
2465 SDValue Pred = getAL(CurDAG);
2466 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2467 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
2468 ResNode = CurDAG->getMachineNode(ARM::tLDRpci, dl, MVT::i32, MVT::Other,
2473 CurDAG->getTargetConstant(0, MVT::i32),
2475 CurDAG->getRegister(0, MVT::i32),
2476 CurDAG->getEntryNode()
2478 ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
2481 ReplaceUses(SDValue(N, 0), SDValue(ResNode, 0));
2485 // Other cases are autogenerated.
2488 case ISD::FrameIndex: {
2489 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
2490 int FI = cast<FrameIndexSDNode>(N)->getIndex();
2491 SDValue TFI = CurDAG->getTargetFrameIndex(FI,
2492 getTargetLowering()->getPointerTy());
2493 if (Subtarget->isThumb1Only()) {
2494 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
2495 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2496 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, Ops, 4);
2498 unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
2499 ARM::t2ADDri : ARM::ADDri);
2500 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
2501 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2502 CurDAG->getRegister(0, MVT::i32) };
2503 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2507 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2511 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, true))
2515 if (Subtarget->isThumb1Only())
2517 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
2518 unsigned RHSV = C->getZExtValue();
2520 if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
2521 unsigned ShImm = Log2_32(RHSV-1);
2524 SDValue V = N->getOperand(0);
2525 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2526 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2527 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2528 if (Subtarget->isThumb()) {
2529 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2530 return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
2532 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2533 return CurDAG->SelectNodeTo(N, ARM::ADDrsi, MVT::i32, Ops, 7);
2536 if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
2537 unsigned ShImm = Log2_32(RHSV+1);
2540 SDValue V = N->getOperand(0);
2541 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2542 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2543 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2544 if (Subtarget->isThumb()) {
2545 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2546 return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 6);
2548 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2549 return CurDAG->SelectNodeTo(N, ARM::RSBrsi, MVT::i32, Ops, 7);
2555 // Check for unsigned bitfield extract
2556 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2559 // (and (or x, c2), c1) and top 16-bits of c1 and c2 match, lower 16-bits
2560 // of c1 are 0xffff, and lower 16-bit of c2 are 0. That is, the top 16-bits
2561 // are entirely contributed by c2 and lower 16-bits are entirely contributed
2562 // by x. That's equal to (or (and x, 0xffff), (and c1, 0xffff0000)).
2563 // Select it to: "movt x, ((c1 & 0xffff) >> 16)
2564 EVT VT = N->getValueType(0);
2567 unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2())
2569 : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0);
2572 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2573 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2576 if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) {
2577 SDValue N2 = N0.getOperand(1);
2578 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2581 unsigned N1CVal = N1C->getZExtValue();
2582 unsigned N2CVal = N2C->getZExtValue();
2583 if ((N1CVal & 0xffff0000U) == (N2CVal & 0xffff0000U) &&
2584 (N1CVal & 0xffffU) == 0xffffU &&
2585 (N2CVal & 0xffffU) == 0x0U) {
2586 SDValue Imm16 = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16,
2588 SDValue Ops[] = { N0.getOperand(0), Imm16,
2589 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2590 return CurDAG->getMachineNode(Opc, dl, VT, Ops);
2595 case ARMISD::VMOVRRD:
2596 return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32,
2597 N->getOperand(0), getAL(CurDAG),
2598 CurDAG->getRegister(0, MVT::i32));
2599 case ISD::UMUL_LOHI: {
2600 if (Subtarget->isThumb1Only())
2602 if (Subtarget->isThumb()) {
2603 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2604 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2605 return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32, Ops);
2607 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2608 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2609 CurDAG->getRegister(0, MVT::i32) };
2610 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2611 ARM::UMULL : ARM::UMULLv5,
2612 dl, MVT::i32, MVT::i32, Ops);
2615 case ISD::SMUL_LOHI: {
2616 if (Subtarget->isThumb1Only())
2618 if (Subtarget->isThumb()) {
2619 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2620 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2621 return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32, Ops);
2623 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2624 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2625 CurDAG->getRegister(0, MVT::i32) };
2626 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2627 ARM::SMULL : ARM::SMULLv5,
2628 dl, MVT::i32, MVT::i32, Ops);
2631 case ARMISD::UMLAL:{
2632 if (Subtarget->isThumb()) {
2633 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
2634 N->getOperand(3), getAL(CurDAG),
2635 CurDAG->getRegister(0, MVT::i32)};
2636 return CurDAG->getMachineNode(ARM::t2UMLAL, dl, MVT::i32, MVT::i32, Ops);
2638 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
2639 N->getOperand(3), getAL(CurDAG),
2640 CurDAG->getRegister(0, MVT::i32),
2641 CurDAG->getRegister(0, MVT::i32) };
2642 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2643 ARM::UMLAL : ARM::UMLALv5,
2644 dl, MVT::i32, MVT::i32, Ops);
2647 case ARMISD::SMLAL:{
2648 if (Subtarget->isThumb()) {
2649 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
2650 N->getOperand(3), getAL(CurDAG),
2651 CurDAG->getRegister(0, MVT::i32)};
2652 return CurDAG->getMachineNode(ARM::t2SMLAL, dl, MVT::i32, MVT::i32, Ops);
2654 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
2655 N->getOperand(3), getAL(CurDAG),
2656 CurDAG->getRegister(0, MVT::i32),
2657 CurDAG->getRegister(0, MVT::i32) };
2658 return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2659 ARM::SMLAL : ARM::SMLALv5,
2660 dl, MVT::i32, MVT::i32, Ops);
2664 SDNode *ResNode = nullptr;
2665 if (Subtarget->isThumb() && Subtarget->hasThumb2())
2666 ResNode = SelectT2IndexedLoad(N);
2668 ResNode = SelectARMIndexedLoad(N);
2671 // Other cases are autogenerated.
2674 case ARMISD::BRCOND: {
2675 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2676 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2677 // Pattern complexity = 6 cost = 1 size = 0
2679 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2680 // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
2681 // Pattern complexity = 6 cost = 1 size = 0
2683 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2684 // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2685 // Pattern complexity = 6 cost = 1 size = 0
2687 unsigned Opc = Subtarget->isThumb() ?
2688 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
2689 SDValue Chain = N->getOperand(0);
2690 SDValue N1 = N->getOperand(1);
2691 SDValue N2 = N->getOperand(2);
2692 SDValue N3 = N->getOperand(3);
2693 SDValue InFlag = N->getOperand(4);
2694 assert(N1.getOpcode() == ISD::BasicBlock);
2695 assert(N2.getOpcode() == ISD::Constant);
2696 assert(N3.getOpcode() == ISD::Register);
2698 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
2699 cast<ConstantSDNode>(N2)->getZExtValue()),
2701 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
2702 SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,
2704 Chain = SDValue(ResNode, 0);
2705 if (N->getNumValues() == 2) {
2706 InFlag = SDValue(ResNode, 1);
2707 ReplaceUses(SDValue(N, 1), InFlag);
2709 ReplaceUses(SDValue(N, 0),
2710 SDValue(Chain.getNode(), Chain.getResNo()));
2713 case ARMISD::VZIP: {
2715 EVT VT = N->getValueType(0);
2716 switch (VT.getSimpleVT().SimpleTy) {
2717 default: return nullptr;
2718 case MVT::v8i8: Opc = ARM::VZIPd8; break;
2719 case MVT::v4i16: Opc = ARM::VZIPd16; break;
2721 // vzip.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.
2722 case MVT::v2i32: Opc = ARM::VTRNd32; break;
2723 case MVT::v16i8: Opc = ARM::VZIPq8; break;
2724 case MVT::v8i16: Opc = ARM::VZIPq16; break;
2726 case MVT::v4i32: Opc = ARM::VZIPq32; break;
2728 SDValue Pred = getAL(CurDAG);
2729 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2730 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2731 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops);
2733 case ARMISD::VUZP: {
2735 EVT VT = N->getValueType(0);
2736 switch (VT.getSimpleVT().SimpleTy) {
2737 default: return nullptr;
2738 case MVT::v8i8: Opc = ARM::VUZPd8; break;
2739 case MVT::v4i16: Opc = ARM::VUZPd16; break;
2741 // vuzp.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.
2742 case MVT::v2i32: Opc = ARM::VTRNd32; break;
2743 case MVT::v16i8: Opc = ARM::VUZPq8; break;
2744 case MVT::v8i16: Opc = ARM::VUZPq16; break;
2746 case MVT::v4i32: Opc = ARM::VUZPq32; break;
2748 SDValue Pred = getAL(CurDAG);
2749 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2750 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2751 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops);
2753 case ARMISD::VTRN: {
2755 EVT VT = N->getValueType(0);
2756 switch (VT.getSimpleVT().SimpleTy) {
2757 default: return nullptr;
2758 case MVT::v8i8: Opc = ARM::VTRNd8; break;
2759 case MVT::v4i16: Opc = ARM::VTRNd16; break;
2761 case MVT::v2i32: Opc = ARM::VTRNd32; break;
2762 case MVT::v16i8: Opc = ARM::VTRNq8; break;
2763 case MVT::v8i16: Opc = ARM::VTRNq16; break;
2765 case MVT::v4i32: Opc = ARM::VTRNq32; break;
2767 SDValue Pred = getAL(CurDAG);
2768 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2769 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2770 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops);
2772 case ARMISD::BUILD_VECTOR: {
2773 EVT VecVT = N->getValueType(0);
2774 EVT EltVT = VecVT.getVectorElementType();
2775 unsigned NumElts = VecVT.getVectorNumElements();
2776 if (EltVT == MVT::f64) {
2777 assert(NumElts == 2 && "unexpected type for BUILD_VECTOR");
2778 return createDRegPairNode(VecVT, N->getOperand(0), N->getOperand(1));
2780 assert(EltVT == MVT::f32 && "unexpected type for BUILD_VECTOR");
2782 return createSRegPairNode(VecVT, N->getOperand(0), N->getOperand(1));
2783 assert(NumElts == 4 && "unexpected type for BUILD_VECTOR");
2784 return createQuadSRegsNode(VecVT, N->getOperand(0), N->getOperand(1),
2785 N->getOperand(2), N->getOperand(3));
2788 case ARMISD::VLD2DUP: {
2789 static const uint16_t Opcodes[] = { ARM::VLD2DUPd8, ARM::VLD2DUPd16,
2791 return SelectVLDDup(N, false, 2, Opcodes);
2794 case ARMISD::VLD3DUP: {
2795 static const uint16_t Opcodes[] = { ARM::VLD3DUPd8Pseudo,
2796 ARM::VLD3DUPd16Pseudo,
2797 ARM::VLD3DUPd32Pseudo };
2798 return SelectVLDDup(N, false, 3, Opcodes);
2801 case ARMISD::VLD4DUP: {
2802 static const uint16_t Opcodes[] = { ARM::VLD4DUPd8Pseudo,
2803 ARM::VLD4DUPd16Pseudo,
2804 ARM::VLD4DUPd32Pseudo };
2805 return SelectVLDDup(N, false, 4, Opcodes);
2808 case ARMISD::VLD2DUP_UPD: {
2809 static const uint16_t Opcodes[] = { ARM::VLD2DUPd8wb_fixed,
2810 ARM::VLD2DUPd16wb_fixed,
2811 ARM::VLD2DUPd32wb_fixed };
2812 return SelectVLDDup(N, true, 2, Opcodes);
2815 case ARMISD::VLD3DUP_UPD: {
2816 static const uint16_t Opcodes[] = { ARM::VLD3DUPd8Pseudo_UPD,
2817 ARM::VLD3DUPd16Pseudo_UPD,
2818 ARM::VLD3DUPd32Pseudo_UPD };
2819 return SelectVLDDup(N, true, 3, Opcodes);
2822 case ARMISD::VLD4DUP_UPD: {
2823 static const uint16_t Opcodes[] = { ARM::VLD4DUPd8Pseudo_UPD,
2824 ARM::VLD4DUPd16Pseudo_UPD,
2825 ARM::VLD4DUPd32Pseudo_UPD };
2826 return SelectVLDDup(N, true, 4, Opcodes);
2829 case ARMISD::VLD1_UPD: {
2830 static const uint16_t DOpcodes[] = { ARM::VLD1d8wb_fixed,
2831 ARM::VLD1d16wb_fixed,
2832 ARM::VLD1d32wb_fixed,
2833 ARM::VLD1d64wb_fixed };
2834 static const uint16_t QOpcodes[] = { ARM::VLD1q8wb_fixed,
2835 ARM::VLD1q16wb_fixed,
2836 ARM::VLD1q32wb_fixed,
2837 ARM::VLD1q64wb_fixed };
2838 return SelectVLD(N, true, 1, DOpcodes, QOpcodes, nullptr);
2841 case ARMISD::VLD2_UPD: {
2842 static const uint16_t DOpcodes[] = { ARM::VLD2d8wb_fixed,
2843 ARM::VLD2d16wb_fixed,
2844 ARM::VLD2d32wb_fixed,
2845 ARM::VLD1q64wb_fixed};
2846 static const uint16_t QOpcodes[] = { ARM::VLD2q8PseudoWB_fixed,
2847 ARM::VLD2q16PseudoWB_fixed,
2848 ARM::VLD2q32PseudoWB_fixed };
2849 return SelectVLD(N, true, 2, DOpcodes, QOpcodes, nullptr);
2852 case ARMISD::VLD3_UPD: {
2853 static const uint16_t DOpcodes[] = { ARM::VLD3d8Pseudo_UPD,
2854 ARM::VLD3d16Pseudo_UPD,
2855 ARM::VLD3d32Pseudo_UPD,
2856 ARM::VLD1d64TPseudoWB_fixed};
2857 static const uint16_t QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
2858 ARM::VLD3q16Pseudo_UPD,
2859 ARM::VLD3q32Pseudo_UPD };
2860 static const uint16_t QOpcodes1[] = { ARM::VLD3q8oddPseudo_UPD,
2861 ARM::VLD3q16oddPseudo_UPD,
2862 ARM::VLD3q32oddPseudo_UPD };
2863 return SelectVLD(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
2866 case ARMISD::VLD4_UPD: {
2867 static const uint16_t DOpcodes[] = { ARM::VLD4d8Pseudo_UPD,
2868 ARM::VLD4d16Pseudo_UPD,
2869 ARM::VLD4d32Pseudo_UPD,
2870 ARM::VLD1d64QPseudoWB_fixed};
2871 static const uint16_t QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
2872 ARM::VLD4q16Pseudo_UPD,
2873 ARM::VLD4q32Pseudo_UPD };
2874 static const uint16_t QOpcodes1[] = { ARM::VLD4q8oddPseudo_UPD,
2875 ARM::VLD4q16oddPseudo_UPD,
2876 ARM::VLD4q32oddPseudo_UPD };
2877 return SelectVLD(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
2880 case ARMISD::VLD2LN_UPD: {
2881 static const uint16_t DOpcodes[] = { ARM::VLD2LNd8Pseudo_UPD,
2882 ARM::VLD2LNd16Pseudo_UPD,
2883 ARM::VLD2LNd32Pseudo_UPD };
2884 static const uint16_t QOpcodes[] = { ARM::VLD2LNq16Pseudo_UPD,
2885 ARM::VLD2LNq32Pseudo_UPD };
2886 return SelectVLDSTLane(N, true, true, 2, DOpcodes, QOpcodes);
2889 case ARMISD::VLD3LN_UPD: {
2890 static const uint16_t DOpcodes[] = { ARM::VLD3LNd8Pseudo_UPD,
2891 ARM::VLD3LNd16Pseudo_UPD,
2892 ARM::VLD3LNd32Pseudo_UPD };
2893 static const uint16_t QOpcodes[] = { ARM::VLD3LNq16Pseudo_UPD,
2894 ARM::VLD3LNq32Pseudo_UPD };
2895 return SelectVLDSTLane(N, true, true, 3, DOpcodes, QOpcodes);
2898 case ARMISD::VLD4LN_UPD: {
2899 static const uint16_t DOpcodes[] = { ARM::VLD4LNd8Pseudo_UPD,
2900 ARM::VLD4LNd16Pseudo_UPD,
2901 ARM::VLD4LNd32Pseudo_UPD };
2902 static const uint16_t QOpcodes[] = { ARM::VLD4LNq16Pseudo_UPD,
2903 ARM::VLD4LNq32Pseudo_UPD };
2904 return SelectVLDSTLane(N, true, true, 4, DOpcodes, QOpcodes);
2907 case ARMISD::VST1_UPD: {
2908 static const uint16_t DOpcodes[] = { ARM::VST1d8wb_fixed,
2909 ARM::VST1d16wb_fixed,
2910 ARM::VST1d32wb_fixed,
2911 ARM::VST1d64wb_fixed };
2912 static const uint16_t QOpcodes[] = { ARM::VST1q8wb_fixed,
2913 ARM::VST1q16wb_fixed,
2914 ARM::VST1q32wb_fixed,
2915 ARM::VST1q64wb_fixed };
2916 return SelectVST(N, true, 1, DOpcodes, QOpcodes, nullptr);
2919 case ARMISD::VST2_UPD: {
2920 static const uint16_t DOpcodes[] = { ARM::VST2d8wb_fixed,
2921 ARM::VST2d16wb_fixed,
2922 ARM::VST2d32wb_fixed,
2923 ARM::VST1q64wb_fixed};
2924 static const uint16_t QOpcodes[] = { ARM::VST2q8PseudoWB_fixed,
2925 ARM::VST2q16PseudoWB_fixed,
2926 ARM::VST2q32PseudoWB_fixed };
2927 return SelectVST(N, true, 2, DOpcodes, QOpcodes, nullptr);
2930 case ARMISD::VST3_UPD: {
2931 static const uint16_t DOpcodes[] = { ARM::VST3d8Pseudo_UPD,
2932 ARM::VST3d16Pseudo_UPD,
2933 ARM::VST3d32Pseudo_UPD,
2934 ARM::VST1d64TPseudoWB_fixed};
2935 static const uint16_t QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
2936 ARM::VST3q16Pseudo_UPD,
2937 ARM::VST3q32Pseudo_UPD };
2938 static const uint16_t QOpcodes1[] = { ARM::VST3q8oddPseudo_UPD,
2939 ARM::VST3q16oddPseudo_UPD,
2940 ARM::VST3q32oddPseudo_UPD };
2941 return SelectVST(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
2944 case ARMISD::VST4_UPD: {
2945 static const uint16_t DOpcodes[] = { ARM::VST4d8Pseudo_UPD,
2946 ARM::VST4d16Pseudo_UPD,
2947 ARM::VST4d32Pseudo_UPD,
2948 ARM::VST1d64QPseudoWB_fixed};
2949 static const uint16_t QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
2950 ARM::VST4q16Pseudo_UPD,
2951 ARM::VST4q32Pseudo_UPD };
2952 static const uint16_t QOpcodes1[] = { ARM::VST4q8oddPseudo_UPD,
2953 ARM::VST4q16oddPseudo_UPD,
2954 ARM::VST4q32oddPseudo_UPD };
2955 return SelectVST(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
2958 case ARMISD::VST2LN_UPD: {
2959 static const uint16_t DOpcodes[] = { ARM::VST2LNd8Pseudo_UPD,
2960 ARM::VST2LNd16Pseudo_UPD,
2961 ARM::VST2LNd32Pseudo_UPD };
2962 static const uint16_t QOpcodes[] = { ARM::VST2LNq16Pseudo_UPD,
2963 ARM::VST2LNq32Pseudo_UPD };
2964 return SelectVLDSTLane(N, false, true, 2, DOpcodes, QOpcodes);
2967 case ARMISD::VST3LN_UPD: {
2968 static const uint16_t DOpcodes[] = { ARM::VST3LNd8Pseudo_UPD,
2969 ARM::VST3LNd16Pseudo_UPD,
2970 ARM::VST3LNd32Pseudo_UPD };
2971 static const uint16_t QOpcodes[] = { ARM::VST3LNq16Pseudo_UPD,
2972 ARM::VST3LNq32Pseudo_UPD };
2973 return SelectVLDSTLane(N, false, true, 3, DOpcodes, QOpcodes);
2976 case ARMISD::VST4LN_UPD: {
2977 static const uint16_t DOpcodes[] = { ARM::VST4LNd8Pseudo_UPD,
2978 ARM::VST4LNd16Pseudo_UPD,
2979 ARM::VST4LNd32Pseudo_UPD };
2980 static const uint16_t QOpcodes[] = { ARM::VST4LNq16Pseudo_UPD,
2981 ARM::VST4LNq32Pseudo_UPD };
2982 return SelectVLDSTLane(N, false, true, 4, DOpcodes, QOpcodes);
2985 case ISD::INTRINSIC_VOID:
2986 case ISD::INTRINSIC_W_CHAIN: {
2987 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
2992 case Intrinsic::arm_ldaexd:
2993 case Intrinsic::arm_ldrexd: {
2995 SDValue Chain = N->getOperand(0);
2996 SDValue MemAddr = N->getOperand(2);
2997 bool isThumb = Subtarget->isThumb() && Subtarget->hasThumb2();
2999 bool IsAcquire = IntNo == Intrinsic::arm_ldaexd;
3000 unsigned NewOpc = isThumb ? (IsAcquire ? ARM::t2LDAEXD : ARM::t2LDREXD)
3001 : (IsAcquire ? ARM::LDAEXD : ARM::LDREXD);
3003 // arm_ldrexd returns a i64 value in {i32, i32}
3004 std::vector<EVT> ResTys;
3006 ResTys.push_back(MVT::i32);
3007 ResTys.push_back(MVT::i32);
3009 ResTys.push_back(MVT::Untyped);
3010 ResTys.push_back(MVT::Other);
3012 // Place arguments in the right order.
3013 SmallVector<SDValue, 7> Ops;
3014 Ops.push_back(MemAddr);
3015 Ops.push_back(getAL(CurDAG));
3016 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
3017 Ops.push_back(Chain);
3018 SDNode *Ld = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops);
3019 // Transfer memoperands.
3020 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
3021 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
3022 cast<MachineSDNode>(Ld)->setMemRefs(MemOp, MemOp + 1);
3025 SDValue OutChain = isThumb ? SDValue(Ld, 2) : SDValue(Ld, 1);
3026 if (!SDValue(N, 0).use_empty()) {
3029 Result = SDValue(Ld, 0);
3031 SDValue SubRegIdx = CurDAG->getTargetConstant(ARM::gsub_0, MVT::i32);
3032 SDNode *ResNode = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
3033 dl, MVT::i32, SDValue(Ld, 0), SubRegIdx);
3034 Result = SDValue(ResNode,0);
3036 ReplaceUses(SDValue(N, 0), Result);
3038 if (!SDValue(N, 1).use_empty()) {
3041 Result = SDValue(Ld, 1);
3043 SDValue SubRegIdx = CurDAG->getTargetConstant(ARM::gsub_1, MVT::i32);
3044 SDNode *ResNode = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
3045 dl, MVT::i32, SDValue(Ld, 0), SubRegIdx);
3046 Result = SDValue(ResNode,0);
3048 ReplaceUses(SDValue(N, 1), Result);
3050 ReplaceUses(SDValue(N, 2), OutChain);
3053 case Intrinsic::arm_stlexd:
3054 case Intrinsic::arm_strexd: {
3056 SDValue Chain = N->getOperand(0);
3057 SDValue Val0 = N->getOperand(2);
3058 SDValue Val1 = N->getOperand(3);
3059 SDValue MemAddr = N->getOperand(4);
3061 // Store exclusive double return a i32 value which is the return status
3062 // of the issued store.
3063 EVT ResTys[] = { MVT::i32, MVT::Other };
3065 bool isThumb = Subtarget->isThumb() && Subtarget->hasThumb2();
3066 // Place arguments in the right order.
3067 SmallVector<SDValue, 7> Ops;
3069 Ops.push_back(Val0);
3070 Ops.push_back(Val1);
3072 // arm_strexd uses GPRPair.
3073 Ops.push_back(SDValue(createGPRPairNode(MVT::Untyped, Val0, Val1), 0));
3074 Ops.push_back(MemAddr);
3075 Ops.push_back(getAL(CurDAG));
3076 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
3077 Ops.push_back(Chain);
3079 bool IsRelease = IntNo == Intrinsic::arm_stlexd;
3080 unsigned NewOpc = isThumb ? (IsRelease ? ARM::t2STLEXD : ARM::t2STREXD)
3081 : (IsRelease ? ARM::STLEXD : ARM::STREXD);
3083 SDNode *St = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops);
3084 // Transfer memoperands.
3085 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
3086 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
3087 cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1);
3092 case Intrinsic::arm_neon_vld1: {
3093 static const uint16_t DOpcodes[] = { ARM::VLD1d8, ARM::VLD1d16,
3094 ARM::VLD1d32, ARM::VLD1d64 };
3095 static const uint16_t QOpcodes[] = { ARM::VLD1q8, ARM::VLD1q16,
3096 ARM::VLD1q32, ARM::VLD1q64};
3097 return SelectVLD(N, false, 1, DOpcodes, QOpcodes, nullptr);
3100 case Intrinsic::arm_neon_vld2: {
3101 static const uint16_t DOpcodes[] = { ARM::VLD2d8, ARM::VLD2d16,
3102 ARM::VLD2d32, ARM::VLD1q64 };
3103 static const uint16_t QOpcodes[] = { ARM::VLD2q8Pseudo, ARM::VLD2q16Pseudo,
3104 ARM::VLD2q32Pseudo };
3105 return SelectVLD(N, false, 2, DOpcodes, QOpcodes, nullptr);
3108 case Intrinsic::arm_neon_vld3: {
3109 static const uint16_t DOpcodes[] = { ARM::VLD3d8Pseudo,
3112 ARM::VLD1d64TPseudo };
3113 static const uint16_t QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
3114 ARM::VLD3q16Pseudo_UPD,
3115 ARM::VLD3q32Pseudo_UPD };
3116 static const uint16_t QOpcodes1[] = { ARM::VLD3q8oddPseudo,
3117 ARM::VLD3q16oddPseudo,
3118 ARM::VLD3q32oddPseudo };
3119 return SelectVLD(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
3122 case Intrinsic::arm_neon_vld4: {
3123 static const uint16_t DOpcodes[] = { ARM::VLD4d8Pseudo,
3126 ARM::VLD1d64QPseudo };
3127 static const uint16_t QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
3128 ARM::VLD4q16Pseudo_UPD,
3129 ARM::VLD4q32Pseudo_UPD };
3130 static const uint16_t QOpcodes1[] = { ARM::VLD4q8oddPseudo,
3131 ARM::VLD4q16oddPseudo,
3132 ARM::VLD4q32oddPseudo };
3133 return SelectVLD(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
3136 case Intrinsic::arm_neon_vld2lane: {
3137 static const uint16_t DOpcodes[] = { ARM::VLD2LNd8Pseudo,
3138 ARM::VLD2LNd16Pseudo,
3139 ARM::VLD2LNd32Pseudo };
3140 static const uint16_t QOpcodes[] = { ARM::VLD2LNq16Pseudo,
3141 ARM::VLD2LNq32Pseudo };
3142 return SelectVLDSTLane(N, true, false, 2, DOpcodes, QOpcodes);
3145 case Intrinsic::arm_neon_vld3lane: {
3146 static const uint16_t DOpcodes[] = { ARM::VLD3LNd8Pseudo,
3147 ARM::VLD3LNd16Pseudo,
3148 ARM::VLD3LNd32Pseudo };
3149 static const uint16_t QOpcodes[] = { ARM::VLD3LNq16Pseudo,
3150 ARM::VLD3LNq32Pseudo };
3151 return SelectVLDSTLane(N, true, false, 3, DOpcodes, QOpcodes);
3154 case Intrinsic::arm_neon_vld4lane: {
3155 static const uint16_t DOpcodes[] = { ARM::VLD4LNd8Pseudo,
3156 ARM::VLD4LNd16Pseudo,
3157 ARM::VLD4LNd32Pseudo };
3158 static const uint16_t QOpcodes[] = { ARM::VLD4LNq16Pseudo,
3159 ARM::VLD4LNq32Pseudo };
3160 return SelectVLDSTLane(N, true, false, 4, DOpcodes, QOpcodes);
3163 case Intrinsic::arm_neon_vst1: {
3164 static const uint16_t DOpcodes[] = { ARM::VST1d8, ARM::VST1d16,
3165 ARM::VST1d32, ARM::VST1d64 };
3166 static const uint16_t QOpcodes[] = { ARM::VST1q8, ARM::VST1q16,
3167 ARM::VST1q32, ARM::VST1q64 };
3168 return SelectVST(N, false, 1, DOpcodes, QOpcodes, nullptr);
3171 case Intrinsic::arm_neon_vst2: {
3172 static const uint16_t DOpcodes[] = { ARM::VST2d8, ARM::VST2d16,
3173 ARM::VST2d32, ARM::VST1q64 };
3174 static uint16_t QOpcodes[] = { ARM::VST2q8Pseudo, ARM::VST2q16Pseudo,
3175 ARM::VST2q32Pseudo };
3176 return SelectVST(N, false, 2, DOpcodes, QOpcodes, nullptr);
3179 case Intrinsic::arm_neon_vst3: {
3180 static const uint16_t DOpcodes[] = { ARM::VST3d8Pseudo,
3183 ARM::VST1d64TPseudo };
3184 static const uint16_t QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
3185 ARM::VST3q16Pseudo_UPD,
3186 ARM::VST3q32Pseudo_UPD };
3187 static const uint16_t QOpcodes1[] = { ARM::VST3q8oddPseudo,
3188 ARM::VST3q16oddPseudo,
3189 ARM::VST3q32oddPseudo };
3190 return SelectVST(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
3193 case Intrinsic::arm_neon_vst4: {
3194 static const uint16_t DOpcodes[] = { ARM::VST4d8Pseudo,
3197 ARM::VST1d64QPseudo };
3198 static const uint16_t QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
3199 ARM::VST4q16Pseudo_UPD,
3200 ARM::VST4q32Pseudo_UPD };
3201 static const uint16_t QOpcodes1[] = { ARM::VST4q8oddPseudo,
3202 ARM::VST4q16oddPseudo,
3203 ARM::VST4q32oddPseudo };
3204 return SelectVST(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
3207 case Intrinsic::arm_neon_vst2lane: {
3208 static const uint16_t DOpcodes[] = { ARM::VST2LNd8Pseudo,
3209 ARM::VST2LNd16Pseudo,
3210 ARM::VST2LNd32Pseudo };
3211 static const uint16_t QOpcodes[] = { ARM::VST2LNq16Pseudo,
3212 ARM::VST2LNq32Pseudo };
3213 return SelectVLDSTLane(N, false, false, 2, DOpcodes, QOpcodes);
3216 case Intrinsic::arm_neon_vst3lane: {
3217 static const uint16_t DOpcodes[] = { ARM::VST3LNd8Pseudo,
3218 ARM::VST3LNd16Pseudo,
3219 ARM::VST3LNd32Pseudo };
3220 static const uint16_t QOpcodes[] = { ARM::VST3LNq16Pseudo,
3221 ARM::VST3LNq32Pseudo };
3222 return SelectVLDSTLane(N, false, false, 3, DOpcodes, QOpcodes);
3225 case Intrinsic::arm_neon_vst4lane: {
3226 static const uint16_t DOpcodes[] = { ARM::VST4LNd8Pseudo,
3227 ARM::VST4LNd16Pseudo,
3228 ARM::VST4LNd32Pseudo };
3229 static const uint16_t QOpcodes[] = { ARM::VST4LNq16Pseudo,
3230 ARM::VST4LNq32Pseudo };
3231 return SelectVLDSTLane(N, false, false, 4, DOpcodes, QOpcodes);
3237 case ISD::INTRINSIC_WO_CHAIN: {
3238 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
3243 case Intrinsic::arm_neon_vtbl2:
3244 return SelectVTBL(N, false, 2, ARM::VTBL2);
3245 case Intrinsic::arm_neon_vtbl3:
3246 return SelectVTBL(N, false, 3, ARM::VTBL3Pseudo);
3247 case Intrinsic::arm_neon_vtbl4:
3248 return SelectVTBL(N, false, 4, ARM::VTBL4Pseudo);
3250 case Intrinsic::arm_neon_vtbx2:
3251 return SelectVTBL(N, true, 2, ARM::VTBX2);
3252 case Intrinsic::arm_neon_vtbx3:
3253 return SelectVTBL(N, true, 3, ARM::VTBX3Pseudo);
3254 case Intrinsic::arm_neon_vtbx4:
3255 return SelectVTBL(N, true, 4, ARM::VTBX4Pseudo);
3260 case ARMISD::VTBL1: {
3262 EVT VT = N->getValueType(0);
3263 SmallVector<SDValue, 6> Ops;
3265 Ops.push_back(N->getOperand(0));
3266 Ops.push_back(N->getOperand(1));
3267 Ops.push_back(getAL(CurDAG)); // Predicate
3268 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register
3269 return CurDAG->getMachineNode(ARM::VTBL1, dl, VT, Ops);
3271 case ARMISD::VTBL2: {
3273 EVT VT = N->getValueType(0);
3275 // Form a REG_SEQUENCE to force register allocation.
3276 SDValue V0 = N->getOperand(0);
3277 SDValue V1 = N->getOperand(1);
3278 SDValue RegSeq = SDValue(createDRegPairNode(MVT::v16i8, V0, V1), 0);
3280 SmallVector<SDValue, 6> Ops;
3281 Ops.push_back(RegSeq);
3282 Ops.push_back(N->getOperand(2));
3283 Ops.push_back(getAL(CurDAG)); // Predicate
3284 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register
3285 return CurDAG->getMachineNode(ARM::VTBL2, dl, VT, Ops);
3288 case ISD::CONCAT_VECTORS:
3289 return SelectConcatVector(N);
3292 return SelectCode(N);
3295 SDNode *ARMDAGToDAGISel::SelectInlineAsm(SDNode *N){
3296 std::vector<SDValue> AsmNodeOperands;
3297 unsigned Flag, Kind;
3298 bool Changed = false;
3299 unsigned NumOps = N->getNumOperands();
3301 // Normally, i64 data is bounded to two arbitrary GRPs for "%r" constraint.
3302 // However, some instrstions (e.g. ldrexd/strexd in ARM mode) require
3303 // (even/even+1) GPRs and use %n and %Hn to refer to the individual regs
3304 // respectively. Since there is no constraint to explicitly specify a
3305 // reg pair, we use GPRPair reg class for "%r" for 64-bit data. For Thumb,
3306 // the 64-bit data may be referred by H, Q, R modifiers, so we still pack
3307 // them into a GPRPair.
3310 SDValue Glue = N->getGluedNode() ? N->getOperand(NumOps-1)
3311 : SDValue(nullptr,0);
3313 SmallVector<bool, 8> OpChanged;
3314 // Glue node will be appended late.
3315 for(unsigned i = 0, e = N->getGluedNode() ? NumOps - 1 : NumOps; i < e; ++i) {
3316 SDValue op = N->getOperand(i);
3317 AsmNodeOperands.push_back(op);
3319 if (i < InlineAsm::Op_FirstOperand)
3322 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(i))) {
3323 Flag = C->getZExtValue();
3324 Kind = InlineAsm::getKind(Flag);
3329 // Immediate operands to inline asm in the SelectionDAG are modeled with
3330 // two operands. The first is a constant of value InlineAsm::Kind_Imm, and
3331 // the second is a constant with the value of the immediate. If we get here
3332 // and we have a Kind_Imm, skip the next operand, and continue.
3333 if (Kind == InlineAsm::Kind_Imm) {
3334 SDValue op = N->getOperand(++i);
3335 AsmNodeOperands.push_back(op);
3339 unsigned NumRegs = InlineAsm::getNumOperandRegisters(Flag);
3341 OpChanged.push_back(false);
3343 unsigned DefIdx = 0;
3344 bool IsTiedToChangedOp = false;
3345 // If it's a use that is tied with a previous def, it has no
3346 // reg class constraint.
3347 if (Changed && InlineAsm::isUseOperandTiedToDef(Flag, DefIdx))
3348 IsTiedToChangedOp = OpChanged[DefIdx];
3350 if (Kind != InlineAsm::Kind_RegUse && Kind != InlineAsm::Kind_RegDef
3351 && Kind != InlineAsm::Kind_RegDefEarlyClobber)
3355 bool HasRC = InlineAsm::hasRegClassConstraint(Flag, RC);
3356 if ((!IsTiedToChangedOp && (!HasRC || RC != ARM::GPRRegClassID))
3360 assert((i+2 < NumOps) && "Invalid number of operands in inline asm");
3361 SDValue V0 = N->getOperand(i+1);
3362 SDValue V1 = N->getOperand(i+2);
3363 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg();
3364 unsigned Reg1 = cast<RegisterSDNode>(V1)->getReg();
3366 MachineRegisterInfo &MRI = MF->getRegInfo();
3368 if (Kind == InlineAsm::Kind_RegDef ||
3369 Kind == InlineAsm::Kind_RegDefEarlyClobber) {
3370 // Replace the two GPRs with 1 GPRPair and copy values from GPRPair to
3371 // the original GPRs.
3373 unsigned GPVR = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
3374 PairedReg = CurDAG->getRegister(GPVR, MVT::Untyped);
3375 SDValue Chain = SDValue(N,0);
3377 SDNode *GU = N->getGluedUser();
3378 SDValue RegCopy = CurDAG->getCopyFromReg(Chain, dl, GPVR, MVT::Untyped,
3381 // Extract values from a GPRPair reg and copy to the original GPR reg.
3382 SDValue Sub0 = CurDAG->getTargetExtractSubreg(ARM::gsub_0, dl, MVT::i32,
3384 SDValue Sub1 = CurDAG->getTargetExtractSubreg(ARM::gsub_1, dl, MVT::i32,
3386 SDValue T0 = CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0,
3387 RegCopy.getValue(1));
3388 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1));
3390 // Update the original glue user.
3391 std::vector<SDValue> Ops(GU->op_begin(), GU->op_end()-1);
3392 Ops.push_back(T1.getValue(1));
3393 CurDAG->UpdateNodeOperands(GU, &Ops[0], Ops.size());
3397 // For Kind == InlineAsm::Kind_RegUse, we first copy two GPRs into a
3398 // GPRPair and then pass the GPRPair to the inline asm.
3399 SDValue Chain = AsmNodeOperands[InlineAsm::Op_InputChain];
3401 // As REG_SEQ doesn't take RegisterSDNode, we copy them first.
3402 SDValue T0 = CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32,
3404 SDValue T1 = CurDAG->getCopyFromReg(Chain, dl, Reg1, MVT::i32,
3406 SDValue Pair = SDValue(createGPRPairNode(MVT::Untyped, T0, T1), 0);
3408 // Copy REG_SEQ into a GPRPair-typed VR and replace the original two
3409 // i32 VRs of inline asm with it.
3410 unsigned GPVR = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
3411 PairedReg = CurDAG->getRegister(GPVR, MVT::Untyped);
3412 Chain = CurDAG->getCopyToReg(T1, dl, GPVR, Pair, T1.getValue(1));
3414 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain;
3415 Glue = Chain.getValue(1);
3420 if(PairedReg.getNode()) {
3421 OpChanged[OpChanged.size() -1 ] = true;
3422 Flag = InlineAsm::getFlagWord(Kind, 1 /* RegNum*/);
3423 if (IsTiedToChangedOp)
3424 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, DefIdx);
3426 Flag = InlineAsm::getFlagWordForRegClass(Flag, ARM::GPRPairRegClassID);
3427 // Replace the current flag.
3428 AsmNodeOperands[AsmNodeOperands.size() -1] = CurDAG->getTargetConstant(
3430 // Add the new register node and skip the original two GPRs.
3431 AsmNodeOperands.push_back(PairedReg);
3432 // Skip the next two GPRs.
3438 AsmNodeOperands.push_back(Glue);
3442 SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N),
3443 CurDAG->getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
3445 return New.getNode();
3449 bool ARMDAGToDAGISel::
3450 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
3451 std::vector<SDValue> &OutOps) {
3452 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
3453 // Require the address to be in a register. That is safe for all ARM
3454 // variants and it is hard to do anything much smarter without knowing
3455 // how the operand is used.
3456 OutOps.push_back(Op);
3460 /// createARMISelDag - This pass converts a legalized DAG into a
3461 /// ARM-specific DAG, ready for instruction scheduling.
3463 FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
3464 CodeGenOpt::Level OptLevel) {
3465 return new ARMDAGToDAGISel(TM, OptLevel);