1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
15 #include "ARMTargetMachine.h"
16 #include "llvm/CallingConv.h"
17 #include "llvm/DerivedTypes.h"
18 #include "llvm/Function.h"
19 #include "llvm/Intrinsics.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/CodeGen/SelectionDAGISel.h"
25 #include "llvm/CodeGen/SSARegMap.h"
26 #include "llvm/Target/TargetLowering.h"
27 #include "llvm/Support/Debug.h"
33 class ARMTargetLowering : public TargetLowering {
35 ARMTargetLowering(TargetMachine &TM);
36 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
37 virtual const char *getTargetNodeName(unsigned Opcode) const;
42 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
43 : TargetLowering(TM) {
44 setOperationAction(ISD::RET, MVT::Other, Custom);
50 // Start the numbering where the builting ops and target ops leave off.
51 FIRST_NUMBER = ISD::BUILTIN_OP_END+ARM::INSTRUCTION_LIST_END,
52 /// CALL - A direct function call.
58 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
61 case ARMISD::CALL: return "ARMISD::CALL";
65 // This transforms a ISD::CALL node into a
66 // callseq_star <- ARMISD:CALL <- callseq_end
68 static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
69 SDOperand Chain = Op.getOperand(0);
70 unsigned CallConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
71 assert(CallConv == CallingConv::C && "unknown calling convention");
72 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
73 assert(isVarArg == false && "VarArg not supported");
74 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
75 assert(isTailCall == false && "tail call not supported");
76 SDOperand Callee = Op.getOperand(4);
77 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
80 // Count how many bytes are to be pushed on the stack. Initially
81 // only the link register.
82 unsigned NumBytes = 4;
84 // Adjust the stack pointer for the new arguments...
85 // These operations are automatically eliminated by the prolog/epilog pass
86 Chain = DAG.getCALLSEQ_START(Chain,
87 DAG.getConstant(NumBytes, MVT::i32));
89 std::vector<MVT::ValueType> NodeTys;
90 NodeTys.push_back(MVT::Other); // Returns a chain
91 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
93 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
94 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
95 // node so that legalize doesn't hack it.
96 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
97 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType());
99 // If this is a direct call, pass the chain and the callee.
101 std::vector<SDOperand> Ops;
102 Ops.push_back(Chain);
103 Ops.push_back(Callee);
105 unsigned CallOpc = ARMISD::CALL;
106 Chain = DAG.getNode(CallOpc, NodeTys, Ops);
108 assert(Op.Val->getValueType(0) == MVT::Other);
110 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
111 DAG.getConstant(NumBytes, MVT::i32));
116 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
118 SDOperand Chain = Op.getOperand(0);
119 switch(Op.getNumOperands()) {
121 assert(0 && "Do not know how to return this many arguments!");
124 SDOperand LR = DAG.getRegister(ARM::R14, MVT::i32);
125 return DAG.getNode(ISD::BRIND, MVT::Other, Chain, LR);
128 Copy = DAG.getCopyToReg(Chain, ARM::R0, Op.getOperand(1), SDOperand());
129 if (DAG.getMachineFunction().liveout_empty())
130 DAG.getMachineFunction().addLiveOut(ARM::R0);
134 SDOperand LR = DAG.getRegister(ARM::R14, MVT::i32);
136 //bug: the copy and branch should be linked with a flag so that the
137 //scheduller can't move an instruction that destroys R0 in between them
138 //return DAG.getNode(ISD::BRIND, MVT::Other, Copy, LR, Copy.getValue(1));
140 return DAG.getNode(ISD::BRIND, MVT::Other, Copy, LR);
143 static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG,
145 MachineFunction &MF = DAG.getMachineFunction();
146 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
147 assert (ObjectVT == MVT::i32);
148 SDOperand Root = Op.getOperand(0);
149 SSARegMap *RegMap = MF.getSSARegMap();
151 unsigned num_regs = 4;
152 static const unsigned REGS[] = {
153 ARM::R0, ARM::R1, ARM::R2, ARM::R3
156 if(ArgNo < num_regs) {
157 unsigned VReg = RegMap->createVirtualRegister(&ARM::IntRegsRegClass);
158 MF.addLiveIn(REGS[ArgNo], VReg);
159 return DAG.getCopyFromReg(Root, VReg, MVT::i32);
161 // If the argument is actually used, emit a load from the right stack
163 if (!Op.Val->hasNUsesOfValue(0, ArgNo)) {
164 unsigned ArgOffset = (ArgNo - num_regs) * 4;
166 MachineFrameInfo *MFI = MF.getFrameInfo();
167 unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8;
168 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
169 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
170 return DAG.getLoad(ObjectVT, Root, FIN,
171 DAG.getSrcValue(NULL));
173 // Don't emit a dead load.
174 return DAG.getNode(ISD::UNDEF, ObjectVT);
179 static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
180 std::vector<SDOperand> ArgValues;
181 SDOperand Root = Op.getOperand(0);
183 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
184 SDOperand ArgVal = LowerFORMAL_ARGUMENT(Op, DAG, ArgNo);
186 ArgValues.push_back(ArgVal);
189 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
192 ArgValues.push_back(Root);
194 // Return the new list of results.
195 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
196 Op.Val->value_end());
197 return DAG.getNode(ISD::MERGE_VALUES, RetVT, ArgValues);
200 SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
201 switch (Op.getOpcode()) {
203 assert(0 && "Should not custom lower this!");
205 case ISD::FORMAL_ARGUMENTS:
206 return LowerFORMAL_ARGUMENTS(Op, DAG);
208 return LowerCALL(Op, DAG);
210 return LowerRET(Op, DAG);
214 //===----------------------------------------------------------------------===//
215 // Instruction Selector Implementation
216 //===----------------------------------------------------------------------===//
218 //===--------------------------------------------------------------------===//
219 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
220 /// instructions for SelectionDAG operations.
223 class ARMDAGToDAGISel : public SelectionDAGISel {
224 ARMTargetLowering Lowering;
227 ARMDAGToDAGISel(TargetMachine &TM)
228 : SelectionDAGISel(Lowering), Lowering(TM) {
231 void Select(SDOperand &Result, SDOperand Op);
232 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
233 bool SelectAddrRegImm(SDOperand N, SDOperand &Offset, SDOperand &Base);
235 // Include the pieces autogenerated from the target description.
236 #include "ARMGenDAGISel.inc"
239 void ARMDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
242 DAG.setRoot(SelectRoot(DAG.getRoot()));
243 assert(InFlightSet.empty() && "ISel InFlightSet has not been emptied!");
247 DAG.RemoveDeadNodes();
249 ScheduleAndEmitDAG(DAG);
252 //register plus/minus 12 bit offset
253 bool ARMDAGToDAGISel::SelectAddrRegImm(SDOperand N, SDOperand &Offset,
255 Offset = CurDAG->getTargetConstant(0, MVT::i32);
256 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
257 Base = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType());
261 return true; //any address fits in a register
264 void ARMDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
267 switch (N->getOpcode()) {
269 SelectCode(Result, Op);
274 } // end anonymous namespace
276 /// createARMISelDag - This pass converts a legalized DAG into a
277 /// ARM-specific DAG, ready for instruction scheduling.
279 FunctionPass *llvm::createARMISelDag(TargetMachine &TM) {
280 return new ARMDAGToDAGISel(TM);