1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMISelLowering.h"
17 #include "ARMTargetMachine.h"
18 #include "llvm/CallingConv.h"
19 #include "llvm/Constants.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/LLVMContext.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CodeGen/SelectionDAGISel.h"
29 #include "llvm/Target/TargetLowering.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Support/Compiler.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
38 //===--------------------------------------------------------------------===//
39 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
40 /// instructions for SelectionDAG operations.
43 class ARMDAGToDAGISel : public SelectionDAGISel {
44 ARMBaseTargetMachine &TM;
46 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
47 /// make the right decision when generating code for different targets.
48 const ARMSubtarget *Subtarget;
51 explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm,
52 CodeGenOpt::Level OptLevel)
53 : SelectionDAGISel(tm, OptLevel), TM(tm),
54 Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
57 virtual const char *getPassName() const {
58 return "ARM Instruction Selection";
61 /// getI32Imm - Return a target constant of type i32 with the specified
63 inline SDValue getI32Imm(unsigned Imm) {
64 return CurDAG->getTargetConstant(Imm, MVT::i32);
67 SDNode *Select(SDNode *N);
69 bool SelectShifterOperandReg(SDNode *Op, SDValue N, SDValue &A,
70 SDValue &B, SDValue &C);
71 bool SelectAddrMode2(SDNode *Op, SDValue N, SDValue &Base,
72 SDValue &Offset, SDValue &Opc);
73 bool SelectAddrMode2Offset(SDNode *Op, SDValue N,
74 SDValue &Offset, SDValue &Opc);
75 bool SelectAddrMode3(SDNode *Op, SDValue N, SDValue &Base,
76 SDValue &Offset, SDValue &Opc);
77 bool SelectAddrMode3Offset(SDNode *Op, SDValue N,
78 SDValue &Offset, SDValue &Opc);
79 bool SelectAddrMode4(SDNode *Op, SDValue N, SDValue &Addr,
81 bool SelectAddrMode5(SDNode *Op, SDValue N, SDValue &Base,
83 bool SelectAddrMode6(SDNode *Op, SDValue N, SDValue &Addr, SDValue &Update,
84 SDValue &Opc, SDValue &Align);
86 bool SelectAddrModePC(SDNode *Op, SDValue N, SDValue &Offset,
89 bool SelectThumbAddrModeRR(SDNode *Op, SDValue N, SDValue &Base,
91 bool SelectThumbAddrModeRI5(SDNode *Op, SDValue N, unsigned Scale,
92 SDValue &Base, SDValue &OffImm,
94 bool SelectThumbAddrModeS1(SDNode *Op, SDValue N, SDValue &Base,
95 SDValue &OffImm, SDValue &Offset);
96 bool SelectThumbAddrModeS2(SDNode *Op, SDValue N, SDValue &Base,
97 SDValue &OffImm, SDValue &Offset);
98 bool SelectThumbAddrModeS4(SDNode *Op, SDValue N, SDValue &Base,
99 SDValue &OffImm, SDValue &Offset);
100 bool SelectThumbAddrModeSP(SDNode *Op, SDValue N, SDValue &Base,
103 bool SelectT2ShifterOperandReg(SDNode *Op, SDValue N,
104 SDValue &BaseReg, SDValue &Opc);
105 bool SelectT2AddrModeImm12(SDNode *Op, SDValue N, SDValue &Base,
107 bool SelectT2AddrModeImm8(SDNode *Op, SDValue N, SDValue &Base,
109 bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
111 bool SelectT2AddrModeImm8s4(SDNode *Op, SDValue N, SDValue &Base,
113 bool SelectT2AddrModeSoReg(SDNode *Op, SDValue N, SDValue &Base,
114 SDValue &OffReg, SDValue &ShImm);
116 // Include the pieces autogenerated from the target description.
117 #include "ARMGenDAGISel.inc"
120 /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
122 SDNode *SelectARMIndexedLoad(SDNode *N);
123 SDNode *SelectT2IndexedLoad(SDNode *N);
125 /// SelectDYN_ALLOC - Select dynamic alloc for Thumb.
126 SDNode *SelectDYN_ALLOC(SDNode *N);
128 /// SelectVLD - Select NEON load intrinsics. NumVecs should
129 /// be 2, 3 or 4. The opcode arrays specify the instructions used for
130 /// loads of D registers and even subregs and odd subregs of Q registers.
131 /// For NumVecs == 2, QOpcodes1 is not used.
132 SDNode *SelectVLD(SDNode *N, unsigned NumVecs, unsigned *DOpcodes,
133 unsigned *QOpcodes0, unsigned *QOpcodes1);
135 /// SelectVST - Select NEON store intrinsics. NumVecs should
136 /// be 2, 3 or 4. The opcode arrays specify the instructions used for
137 /// stores of D registers and even subregs and odd subregs of Q registers.
138 /// For NumVecs == 2, QOpcodes1 is not used.
139 SDNode *SelectVST(SDNode *N, unsigned NumVecs, unsigned *DOpcodes,
140 unsigned *QOpcodes0, unsigned *QOpcodes1);
142 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should
143 /// be 2, 3 or 4. The opcode arrays specify the instructions used for
144 /// load/store of D registers and even subregs and odd subregs of Q registers.
145 SDNode *SelectVLDSTLane(SDNode *N, bool IsLoad, unsigned NumVecs,
146 unsigned *DOpcodes, unsigned *QOpcodes0,
147 unsigned *QOpcodes1);
149 /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM.
150 SDNode *SelectV6T2BitfieldExtractOp(SDNode *N, unsigned Opc);
152 /// SelectCMOVOp - Select CMOV instructions for ARM.
153 SDNode *SelectCMOVOp(SDNode *N);
154 SDNode *SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
155 ARMCC::CondCodes CCVal, SDValue CCR,
157 SDNode *SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
158 ARMCC::CondCodes CCVal, SDValue CCR,
160 SDNode *SelectT2CMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
161 ARMCC::CondCodes CCVal, SDValue CCR,
163 SDNode *SelectARMCMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
164 ARMCC::CondCodes CCVal, SDValue CCR,
167 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
168 /// inline asm expressions.
169 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
171 std::vector<SDValue> &OutOps);
173 /// PairDRegs - Insert a pair of double registers into an implicit def to
174 /// form a quad register.
175 SDNode *PairDRegs(EVT VT, SDValue V0, SDValue V1);
179 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
180 /// operand. If so Imm will receive the 32-bit value.
181 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
182 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
183 Imm = cast<ConstantSDNode>(N)->getZExtValue();
189 // isInt32Immediate - This method tests to see if a constant operand.
190 // If so Imm will receive the 32 bit value.
191 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
192 return isInt32Immediate(N.getNode(), Imm);
195 // isOpcWithIntImmediate - This method tests to see if the node is a specific
196 // opcode and that it has a immediate integer right operand.
197 // If so Imm will receive the 32 bit value.
198 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
199 return N->getOpcode() == Opc &&
200 isInt32Immediate(N->getOperand(1).getNode(), Imm);
204 bool ARMDAGToDAGISel::SelectShifterOperandReg(SDNode *Op,
209 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
211 // Don't match base register only case. That is matched to a separate
212 // lower complexity pattern with explicit register operand.
213 if (ShOpcVal == ARM_AM::no_shift) return false;
215 BaseReg = N.getOperand(0);
216 unsigned ShImmVal = 0;
217 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
218 ShReg = CurDAG->getRegister(0, MVT::i32);
219 ShImmVal = RHS->getZExtValue() & 31;
221 ShReg = N.getOperand(1);
223 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
228 bool ARMDAGToDAGISel::SelectAddrMode2(SDNode *Op, SDValue N,
229 SDValue &Base, SDValue &Offset,
231 if (N.getOpcode() == ISD::MUL) {
232 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
233 // X * [3,5,9] -> X + X * [2,4,8] etc.
234 int RHSC = (int)RHS->getZExtValue();
237 ARM_AM::AddrOpc AddSub = ARM_AM::add;
239 AddSub = ARM_AM::sub;
242 if (isPowerOf2_32(RHSC)) {
243 unsigned ShAmt = Log2_32(RHSC);
244 Base = Offset = N.getOperand(0);
245 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
254 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
256 if (N.getOpcode() == ISD::FrameIndex) {
257 int FI = cast<FrameIndexSDNode>(N)->getIndex();
258 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
259 } else if (N.getOpcode() == ARMISD::Wrapper &&
260 !(Subtarget->useMovt() &&
261 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
262 Base = N.getOperand(0);
264 Offset = CurDAG->getRegister(0, MVT::i32);
265 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
271 // Match simple R +/- imm12 operands.
272 if (N.getOpcode() == ISD::ADD)
273 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
274 int RHSC = (int)RHS->getZExtValue();
275 if ((RHSC >= 0 && RHSC < 0x1000) ||
276 (RHSC < 0 && RHSC > -0x1000)) { // 12 bits.
277 Base = N.getOperand(0);
278 if (Base.getOpcode() == ISD::FrameIndex) {
279 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
280 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
282 Offset = CurDAG->getRegister(0, MVT::i32);
284 ARM_AM::AddrOpc AddSub = ARM_AM::add;
286 AddSub = ARM_AM::sub;
289 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
296 // Otherwise this is R +/- [possibly shifted] R.
297 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
298 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
301 Base = N.getOperand(0);
302 Offset = N.getOperand(1);
304 if (ShOpcVal != ARM_AM::no_shift) {
305 // Check to see if the RHS of the shift is a constant, if not, we can't fold
307 if (ConstantSDNode *Sh =
308 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
309 ShAmt = Sh->getZExtValue();
310 Offset = N.getOperand(1).getOperand(0);
312 ShOpcVal = ARM_AM::no_shift;
316 // Try matching (R shl C) + (R).
317 if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift) {
318 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
319 if (ShOpcVal != ARM_AM::no_shift) {
320 // Check to see if the RHS of the shift is a constant, if not, we can't
322 if (ConstantSDNode *Sh =
323 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
324 ShAmt = Sh->getZExtValue();
325 Offset = N.getOperand(0).getOperand(0);
326 Base = N.getOperand(1);
328 ShOpcVal = ARM_AM::no_shift;
333 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
338 bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDNode *Op, SDValue N,
339 SDValue &Offset, SDValue &Opc) {
340 unsigned Opcode = Op->getOpcode();
341 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
342 ? cast<LoadSDNode>(Op)->getAddressingMode()
343 : cast<StoreSDNode>(Op)->getAddressingMode();
344 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
345 ? ARM_AM::add : ARM_AM::sub;
346 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
347 int Val = (int)C->getZExtValue();
348 if (Val >= 0 && Val < 0x1000) { // 12 bits.
349 Offset = CurDAG->getRegister(0, MVT::i32);
350 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
358 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
360 if (ShOpcVal != ARM_AM::no_shift) {
361 // Check to see if the RHS of the shift is a constant, if not, we can't fold
363 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
364 ShAmt = Sh->getZExtValue();
365 Offset = N.getOperand(0);
367 ShOpcVal = ARM_AM::no_shift;
371 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
377 bool ARMDAGToDAGISel::SelectAddrMode3(SDNode *Op, SDValue N,
378 SDValue &Base, SDValue &Offset,
380 if (N.getOpcode() == ISD::SUB) {
381 // X - C is canonicalize to X + -C, no need to handle it here.
382 Base = N.getOperand(0);
383 Offset = N.getOperand(1);
384 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
388 if (N.getOpcode() != ISD::ADD) {
390 if (N.getOpcode() == ISD::FrameIndex) {
391 int FI = cast<FrameIndexSDNode>(N)->getIndex();
392 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
394 Offset = CurDAG->getRegister(0, MVT::i32);
395 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
399 // If the RHS is +/- imm8, fold into addr mode.
400 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
401 int RHSC = (int)RHS->getZExtValue();
402 if ((RHSC >= 0 && RHSC < 256) ||
403 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
404 Base = N.getOperand(0);
405 if (Base.getOpcode() == ISD::FrameIndex) {
406 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
407 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
409 Offset = CurDAG->getRegister(0, MVT::i32);
411 ARM_AM::AddrOpc AddSub = ARM_AM::add;
413 AddSub = ARM_AM::sub;
416 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
421 Base = N.getOperand(0);
422 Offset = N.getOperand(1);
423 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
427 bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N,
428 SDValue &Offset, SDValue &Opc) {
429 unsigned Opcode = Op->getOpcode();
430 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
431 ? cast<LoadSDNode>(Op)->getAddressingMode()
432 : cast<StoreSDNode>(Op)->getAddressingMode();
433 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
434 ? ARM_AM::add : ARM_AM::sub;
435 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
436 int Val = (int)C->getZExtValue();
437 if (Val >= 0 && Val < 256) {
438 Offset = CurDAG->getRegister(0, MVT::i32);
439 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
445 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
449 bool ARMDAGToDAGISel::SelectAddrMode4(SDNode *Op, SDValue N,
450 SDValue &Addr, SDValue &Mode) {
452 Mode = CurDAG->getTargetConstant(0, MVT::i32);
456 bool ARMDAGToDAGISel::SelectAddrMode5(SDNode *Op, SDValue N,
457 SDValue &Base, SDValue &Offset) {
458 if (N.getOpcode() != ISD::ADD) {
460 if (N.getOpcode() == ISD::FrameIndex) {
461 int FI = cast<FrameIndexSDNode>(N)->getIndex();
462 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
463 } else if (N.getOpcode() == ARMISD::Wrapper &&
464 !(Subtarget->useMovt() &&
465 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
466 Base = N.getOperand(0);
468 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
473 // If the RHS is +/- imm8, fold into addr mode.
474 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
475 int RHSC = (int)RHS->getZExtValue();
476 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied by 4.
478 if ((RHSC >= 0 && RHSC < 256) ||
479 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
480 Base = N.getOperand(0);
481 if (Base.getOpcode() == ISD::FrameIndex) {
482 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
483 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
486 ARM_AM::AddrOpc AddSub = ARM_AM::add;
488 AddSub = ARM_AM::sub;
491 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
499 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
504 bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Op, SDValue N,
505 SDValue &Addr, SDValue &Update,
506 SDValue &Opc, SDValue &Align) {
508 // Default to no writeback.
509 Update = CurDAG->getRegister(0, MVT::i32);
510 Opc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(false), MVT::i32);
511 // Default to no alignment.
512 Align = CurDAG->getTargetConstant(0, MVT::i32);
516 bool ARMDAGToDAGISel::SelectAddrModePC(SDNode *Op, SDValue N,
517 SDValue &Offset, SDValue &Label) {
518 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
519 Offset = N.getOperand(0);
520 SDValue N1 = N.getOperand(1);
521 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
528 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDNode *Op, SDValue N,
529 SDValue &Base, SDValue &Offset){
530 // FIXME dl should come from the parent load or store, not the address
531 DebugLoc dl = Op->getDebugLoc();
532 if (N.getOpcode() != ISD::ADD) {
533 ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
534 if (!NC || NC->getZExtValue() != 0)
541 Base = N.getOperand(0);
542 Offset = N.getOperand(1);
547 ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDNode *Op, SDValue N,
548 unsigned Scale, SDValue &Base,
549 SDValue &OffImm, SDValue &Offset) {
551 SDValue TmpBase, TmpOffImm;
552 if (SelectThumbAddrModeSP(Op, N, TmpBase, TmpOffImm))
553 return false; // We want to select tLDRspi / tSTRspi instead.
554 if (N.getOpcode() == ARMISD::Wrapper &&
555 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
556 return false; // We want to select tLDRpci instead.
559 if (N.getOpcode() != ISD::ADD) {
560 if (N.getOpcode() == ARMISD::Wrapper &&
561 !(Subtarget->useMovt() &&
562 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
563 Base = N.getOperand(0);
567 Offset = CurDAG->getRegister(0, MVT::i32);
568 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
572 // Thumb does not have [sp, r] address mode.
573 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
574 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
575 if ((LHSR && LHSR->getReg() == ARM::SP) ||
576 (RHSR && RHSR->getReg() == ARM::SP)) {
578 Offset = CurDAG->getRegister(0, MVT::i32);
579 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
583 // If the RHS is + imm5 * scale, fold into addr mode.
584 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
585 int RHSC = (int)RHS->getZExtValue();
586 if ((RHSC & (Scale-1)) == 0) { // The constant is implicitly multiplied.
588 if (RHSC >= 0 && RHSC < 32) {
589 Base = N.getOperand(0);
590 Offset = CurDAG->getRegister(0, MVT::i32);
591 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
597 Base = N.getOperand(0);
598 Offset = N.getOperand(1);
599 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
603 bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDNode *Op, SDValue N,
604 SDValue &Base, SDValue &OffImm,
606 return SelectThumbAddrModeRI5(Op, N, 1, Base, OffImm, Offset);
609 bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDNode *Op, SDValue N,
610 SDValue &Base, SDValue &OffImm,
612 return SelectThumbAddrModeRI5(Op, N, 2, Base, OffImm, Offset);
615 bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDNode *Op, SDValue N,
616 SDValue &Base, SDValue &OffImm,
618 return SelectThumbAddrModeRI5(Op, N, 4, Base, OffImm, Offset);
621 bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDNode *Op, SDValue N,
622 SDValue &Base, SDValue &OffImm) {
623 if (N.getOpcode() == ISD::FrameIndex) {
624 int FI = cast<FrameIndexSDNode>(N)->getIndex();
625 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
626 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
630 if (N.getOpcode() != ISD::ADD)
633 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
634 if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
635 (LHSR && LHSR->getReg() == ARM::SP)) {
636 // If the RHS is + imm8 * scale, fold into addr mode.
637 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
638 int RHSC = (int)RHS->getZExtValue();
639 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied.
641 if (RHSC >= 0 && RHSC < 256) {
642 Base = N.getOperand(0);
643 if (Base.getOpcode() == ISD::FrameIndex) {
644 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
645 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
647 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
657 bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDNode *Op, SDValue N,
660 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
662 // Don't match base register only case. That is matched to a separate
663 // lower complexity pattern with explicit register operand.
664 if (ShOpcVal == ARM_AM::no_shift) return false;
666 BaseReg = N.getOperand(0);
667 unsigned ShImmVal = 0;
668 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
669 ShImmVal = RHS->getZExtValue() & 31;
670 Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
677 bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDNode *Op, SDValue N,
678 SDValue &Base, SDValue &OffImm) {
679 // Match simple R + imm12 operands.
682 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
683 if (N.getOpcode() == ISD::FrameIndex) {
684 // Match frame index...
685 int FI = cast<FrameIndexSDNode>(N)->getIndex();
686 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
687 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
689 } else if (N.getOpcode() == ARMISD::Wrapper &&
690 !(Subtarget->useMovt() &&
691 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
692 Base = N.getOperand(0);
693 if (Base.getOpcode() == ISD::TargetConstantPool)
694 return false; // We want to select t2LDRpci instead.
697 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
701 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
702 if (SelectT2AddrModeImm8(Op, N, Base, OffImm))
703 // Let t2LDRi8 handle (R - imm8).
706 int RHSC = (int)RHS->getZExtValue();
707 if (N.getOpcode() == ISD::SUB)
710 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
711 Base = N.getOperand(0);
712 if (Base.getOpcode() == ISD::FrameIndex) {
713 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
714 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
716 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
723 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
727 bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDNode *Op, SDValue N,
728 SDValue &Base, SDValue &OffImm) {
729 // Match simple R - imm8 operands.
730 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::SUB) {
731 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
732 int RHSC = (int)RHS->getSExtValue();
733 if (N.getOpcode() == ISD::SUB)
736 if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative)
737 Base = N.getOperand(0);
738 if (Base.getOpcode() == ISD::FrameIndex) {
739 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
740 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
742 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
751 bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
753 unsigned Opcode = Op->getOpcode();
754 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
755 ? cast<LoadSDNode>(Op)->getAddressingMode()
756 : cast<StoreSDNode>(Op)->getAddressingMode();
757 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N)) {
758 int RHSC = (int)RHS->getZExtValue();
759 if (RHSC >= 0 && RHSC < 0x100) { // 8 bits.
760 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
761 ? CurDAG->getTargetConstant(RHSC, MVT::i32)
762 : CurDAG->getTargetConstant(-RHSC, MVT::i32);
770 bool ARMDAGToDAGISel::SelectT2AddrModeImm8s4(SDNode *Op, SDValue N,
771 SDValue &Base, SDValue &OffImm) {
772 if (N.getOpcode() == ISD::ADD) {
773 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
774 int RHSC = (int)RHS->getZExtValue();
775 if (((RHSC & 0x3) == 0) &&
776 ((RHSC >= 0 && RHSC < 0x400) || (RHSC < 0 && RHSC > -0x400))) { // 8 bits.
777 Base = N.getOperand(0);
778 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
782 } else if (N.getOpcode() == ISD::SUB) {
783 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
784 int RHSC = (int)RHS->getZExtValue();
785 if (((RHSC & 0x3) == 0) && (RHSC >= 0 && RHSC < 0x400)) { // 8 bits.
786 Base = N.getOperand(0);
787 OffImm = CurDAG->getTargetConstant(-RHSC, MVT::i32);
796 bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDNode *Op, SDValue N,
798 SDValue &OffReg, SDValue &ShImm) {
799 // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.
800 if (N.getOpcode() != ISD::ADD)
803 // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8.
804 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
805 int RHSC = (int)RHS->getZExtValue();
806 if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned)
808 else if (RHSC < 0 && RHSC >= -255) // 8 bits
812 // Look for (R + R) or (R + (R << [1,2,3])).
814 Base = N.getOperand(0);
815 OffReg = N.getOperand(1);
817 // Swap if it is ((R << c) + R).
818 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg);
819 if (ShOpcVal != ARM_AM::lsl) {
820 ShOpcVal = ARM_AM::getShiftOpcForNode(Base);
821 if (ShOpcVal == ARM_AM::lsl)
822 std::swap(Base, OffReg);
825 if (ShOpcVal == ARM_AM::lsl) {
826 // Check to see if the RHS of the shift is a constant, if not, we can't fold
828 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
829 ShAmt = Sh->getZExtValue();
832 ShOpcVal = ARM_AM::no_shift;
834 OffReg = OffReg.getOperand(0);
836 ShOpcVal = ARM_AM::no_shift;
840 ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
845 //===--------------------------------------------------------------------===//
847 /// getAL - Returns a ARMCC::AL immediate node.
848 static inline SDValue getAL(SelectionDAG *CurDAG) {
849 return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
852 SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDNode *N) {
853 LoadSDNode *LD = cast<LoadSDNode>(N);
854 ISD::MemIndexedMode AM = LD->getAddressingMode();
855 if (AM == ISD::UNINDEXED)
858 EVT LoadedVT = LD->getMemoryVT();
859 SDValue Offset, AMOpc;
860 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
863 if (LoadedVT == MVT::i32 &&
864 SelectAddrMode2Offset(N, LD->getOffset(), Offset, AMOpc)) {
865 Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST;
867 } else if (LoadedVT == MVT::i16 &&
868 SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
870 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
871 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
872 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
873 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
874 if (LD->getExtensionType() == ISD::SEXTLOAD) {
875 if (SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
877 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
880 if (SelectAddrMode2Offset(N, LD->getOffset(), Offset, AMOpc)) {
882 Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST;
888 SDValue Chain = LD->getChain();
889 SDValue Base = LD->getBasePtr();
890 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
891 CurDAG->getRegister(0, MVT::i32), Chain };
892 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32,
899 SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDNode *N) {
900 LoadSDNode *LD = cast<LoadSDNode>(N);
901 ISD::MemIndexedMode AM = LD->getAddressingMode();
902 if (AM == ISD::UNINDEXED)
905 EVT LoadedVT = LD->getMemoryVT();
906 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
908 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
911 if (SelectT2AddrModeImm8Offset(N, LD->getOffset(), Offset)) {
912 switch (LoadedVT.getSimpleVT().SimpleTy) {
914 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
918 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
920 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
925 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
927 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
936 SDValue Chain = LD->getChain();
937 SDValue Base = LD->getBasePtr();
938 SDValue Ops[]= { Base, Offset, getAL(CurDAG),
939 CurDAG->getRegister(0, MVT::i32), Chain };
940 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32,
947 SDNode *ARMDAGToDAGISel::SelectDYN_ALLOC(SDNode *N) {
948 DebugLoc dl = N->getDebugLoc();
949 EVT VT = N->getValueType(0);
950 SDValue Chain = N->getOperand(0);
951 SDValue Size = N->getOperand(1);
952 SDValue Align = N->getOperand(2);
953 SDValue SP = CurDAG->getRegister(ARM::SP, MVT::i32);
954 int32_t AlignVal = cast<ConstantSDNode>(Align)->getSExtValue();
956 // We need to align the stack. Use Thumb1 tAND which is the only thumb
957 // instruction that can read and write SP. This matches to a pseudo
958 // instruction that has a chain to ensure the result is written back to
959 // the stack pointer.
960 SP = SDValue(CurDAG->getMachineNode(ARM::tANDsp, dl, VT, SP, Align), 0);
962 bool isC = isa<ConstantSDNode>(Size);
963 uint32_t C = isC ? cast<ConstantSDNode>(Size)->getZExtValue() : ~0UL;
964 // Handle the most common case for both Thumb1 and Thumb2:
965 // tSUBspi - immediate is between 0 ... 508 inclusive.
966 if (C <= 508 && ((C & 3) == 0))
967 // FIXME: tSUBspi encode scale 4 implicitly.
968 return CurDAG->SelectNodeTo(N, ARM::tSUBspi_, VT, MVT::Other, SP,
969 CurDAG->getTargetConstant(C/4, MVT::i32),
972 if (Subtarget->isThumb1Only()) {
973 // Use tADDspr since Thumb1 does not have a sub r, sp, r. ARMISelLowering
974 // should have negated the size operand already. FIXME: We can't insert
975 // new target independent node at this stage so we are forced to negate
976 // it earlier. Is there a better solution?
977 return CurDAG->SelectNodeTo(N, ARM::tADDspr_, VT, MVT::Other, SP, Size,
979 } else if (Subtarget->isThumb2()) {
980 if (isC && Predicate_t2_so_imm(Size.getNode())) {
982 SDValue Ops[] = { SP, CurDAG->getTargetConstant(C, MVT::i32), Chain };
983 return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPi_, VT, MVT::Other, Ops, 3);
984 } else if (isC && Predicate_imm0_4095(Size.getNode())) {
986 SDValue Ops[] = { SP, CurDAG->getTargetConstant(C, MVT::i32), Chain };
987 return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPi12_, VT, MVT::Other, Ops, 3);
990 SDValue Ops[] = { SP, Size,
991 getI32Imm(ARM_AM::getSORegOpc(ARM_AM::lsl,0)), Chain };
992 return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPs_, VT, MVT::Other, Ops, 4);
996 // FIXME: Add ADD / SUB sp instructions for ARM.
1000 /// PairDRegs - Insert a pair of double registers into an implicit def to
1001 /// form a quad register.
1002 SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) {
1003 DebugLoc dl = V0.getNode()->getDebugLoc();
1005 SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0);
1006 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::DSUBREG_0, MVT::i32);
1007 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::DSUBREG_1, MVT::i32);
1008 SDNode *Pair = CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
1009 VT, Undef, V0, SubReg0);
1010 return CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, dl,
1011 VT, SDValue(Pair, 0), V1, SubReg1);
1014 /// GetNEONSubregVT - Given a type for a 128-bit NEON vector, return the type
1015 /// for a 64-bit subregister of the vector.
1016 static EVT GetNEONSubregVT(EVT VT) {
1017 switch (VT.getSimpleVT().SimpleTy) {
1018 default: llvm_unreachable("unhandled NEON type");
1019 case MVT::v16i8: return MVT::v8i8;
1020 case MVT::v8i16: return MVT::v4i16;
1021 case MVT::v4f32: return MVT::v2f32;
1022 case MVT::v4i32: return MVT::v2i32;
1023 case MVT::v2i64: return MVT::v1i64;
1027 SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, unsigned NumVecs,
1028 unsigned *DOpcodes, unsigned *QOpcodes0,
1029 unsigned *QOpcodes1) {
1030 assert(NumVecs >=2 && NumVecs <= 4 && "VLD NumVecs out-of-range");
1031 DebugLoc dl = N->getDebugLoc();
1033 SDValue MemAddr, MemUpdate, MemOpc, Align;
1034 if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, MemUpdate, MemOpc, Align))
1037 SDValue Chain = N->getOperand(0);
1038 EVT VT = N->getValueType(0);
1039 bool is64BitVector = VT.is64BitVector();
1041 unsigned OpcodeIndex;
1042 switch (VT.getSimpleVT().SimpleTy) {
1043 default: llvm_unreachable("unhandled vld type");
1044 // Double-register operations:
1045 case MVT::v8i8: OpcodeIndex = 0; break;
1046 case MVT::v4i16: OpcodeIndex = 1; break;
1048 case MVT::v2i32: OpcodeIndex = 2; break;
1049 case MVT::v1i64: OpcodeIndex = 3; break;
1050 // Quad-register operations:
1051 case MVT::v16i8: OpcodeIndex = 0; break;
1052 case MVT::v8i16: OpcodeIndex = 1; break;
1054 case MVT::v4i32: OpcodeIndex = 2; break;
1057 SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32);
1058 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
1059 if (is64BitVector) {
1060 unsigned Opc = DOpcodes[OpcodeIndex];
1061 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Align,
1062 Pred, PredReg, Chain };
1063 std::vector<EVT> ResTys(NumVecs, VT);
1064 ResTys.push_back(MVT::Other);
1065 return CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 7);
1068 EVT RegVT = GetNEONSubregVT(VT);
1070 // Quad registers are directly supported for VLD2,
1071 // loading 2 pairs of D regs.
1072 unsigned Opc = QOpcodes0[OpcodeIndex];
1073 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Align,
1074 Pred, PredReg, Chain };
1075 std::vector<EVT> ResTys(4, VT);
1076 ResTys.push_back(MVT::Other);
1077 SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 7);
1078 Chain = SDValue(VLd, 4);
1080 // Combine the even and odd subregs to produce the result.
1081 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1082 SDNode *Q = PairDRegs(VT, SDValue(VLd, 2*Vec), SDValue(VLd, 2*Vec+1));
1083 ReplaceUses(SDValue(N, Vec), SDValue(Q, 0));
1086 // Otherwise, quad registers are loaded with two separate instructions,
1087 // where one loads the even registers and the other loads the odd registers.
1089 // Enable writeback to the address register.
1090 MemOpc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(true), MVT::i32);
1092 std::vector<EVT> ResTys(NumVecs, RegVT);
1093 ResTys.push_back(MemAddr.getValueType());
1094 ResTys.push_back(MVT::Other);
1096 // Load the even subregs.
1097 unsigned Opc = QOpcodes0[OpcodeIndex];
1098 const SDValue OpsA[] = { MemAddr, MemUpdate, MemOpc, Align,
1099 Pred, PredReg, Chain };
1100 SDNode *VLdA = CurDAG->getMachineNode(Opc, dl, ResTys, OpsA, 7);
1101 Chain = SDValue(VLdA, NumVecs+1);
1103 // Load the odd subregs.
1104 Opc = QOpcodes1[OpcodeIndex];
1105 const SDValue OpsB[] = { SDValue(VLdA, NumVecs), MemUpdate, MemOpc,
1106 Align, Pred, PredReg, Chain };
1107 SDNode *VLdB = CurDAG->getMachineNode(Opc, dl, ResTys, OpsB, 7);
1108 Chain = SDValue(VLdB, NumVecs+1);
1110 // Combine the even and odd subregs to produce the result.
1111 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1112 SDNode *Q = PairDRegs(VT, SDValue(VLdA, Vec), SDValue(VLdB, Vec));
1113 ReplaceUses(SDValue(N, Vec), SDValue(Q, 0));
1116 ReplaceUses(SDValue(N, NumVecs), Chain);
1120 SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, unsigned NumVecs,
1121 unsigned *DOpcodes, unsigned *QOpcodes0,
1122 unsigned *QOpcodes1) {
1123 assert(NumVecs >=2 && NumVecs <= 4 && "VST NumVecs out-of-range");
1124 DebugLoc dl = N->getDebugLoc();
1126 SDValue MemAddr, MemUpdate, MemOpc, Align;
1127 if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, MemUpdate, MemOpc, Align))
1130 SDValue Chain = N->getOperand(0);
1131 EVT VT = N->getOperand(3).getValueType();
1132 bool is64BitVector = VT.is64BitVector();
1134 unsigned OpcodeIndex;
1135 switch (VT.getSimpleVT().SimpleTy) {
1136 default: llvm_unreachable("unhandled vst type");
1137 // Double-register operations:
1138 case MVT::v8i8: OpcodeIndex = 0; break;
1139 case MVT::v4i16: OpcodeIndex = 1; break;
1141 case MVT::v2i32: OpcodeIndex = 2; break;
1142 case MVT::v1i64: OpcodeIndex = 3; break;
1143 // Quad-register operations:
1144 case MVT::v16i8: OpcodeIndex = 0; break;
1145 case MVT::v8i16: OpcodeIndex = 1; break;
1147 case MVT::v4i32: OpcodeIndex = 2; break;
1150 SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32);
1151 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
1153 SmallVector<SDValue, 8> Ops;
1154 Ops.push_back(MemAddr);
1155 Ops.push_back(MemUpdate);
1156 Ops.push_back(MemOpc);
1157 Ops.push_back(Align);
1159 if (is64BitVector) {
1160 unsigned Opc = DOpcodes[OpcodeIndex];
1161 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1162 Ops.push_back(N->getOperand(Vec+3));
1163 Ops.push_back(Pred);
1164 Ops.push_back(PredReg);
1165 Ops.push_back(Chain);
1166 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), NumVecs+7);
1169 EVT RegVT = GetNEONSubregVT(VT);
1171 // Quad registers are directly supported for VST2,
1172 // storing 2 pairs of D regs.
1173 unsigned Opc = QOpcodes0[OpcodeIndex];
1174 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1175 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
1176 N->getOperand(Vec+3)));
1177 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
1178 N->getOperand(Vec+3)));
1180 Ops.push_back(Pred);
1181 Ops.push_back(PredReg);
1182 Ops.push_back(Chain);
1183 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 11);
1186 // Otherwise, quad registers are stored with two separate instructions,
1187 // where one stores the even registers and the other stores the odd registers.
1189 // Enable writeback to the address register.
1190 MemOpc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(true), MVT::i32);
1192 // Store the even subregs.
1193 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1194 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
1195 N->getOperand(Vec+3)));
1196 Ops.push_back(Pred);
1197 Ops.push_back(PredReg);
1198 Ops.push_back(Chain);
1199 unsigned Opc = QOpcodes0[OpcodeIndex];
1200 SDNode *VStA = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
1201 MVT::Other, Ops.data(), NumVecs+7);
1202 Chain = SDValue(VStA, 1);
1204 // Store the odd subregs.
1205 Ops[0] = SDValue(VStA, 0); // MemAddr
1206 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1207 Ops[Vec+4] = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
1208 N->getOperand(Vec+3));
1209 Ops[NumVecs+4] = Pred;
1210 Ops[NumVecs+5] = PredReg;
1211 Ops[NumVecs+6] = Chain;
1212 Opc = QOpcodes1[OpcodeIndex];
1213 SDNode *VStB = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
1214 MVT::Other, Ops.data(), NumVecs+7);
1215 Chain = SDValue(VStB, 1);
1216 ReplaceUses(SDValue(N, 0), Chain);
1220 SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
1221 unsigned NumVecs, unsigned *DOpcodes,
1222 unsigned *QOpcodes0,
1223 unsigned *QOpcodes1) {
1224 assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
1225 DebugLoc dl = N->getDebugLoc();
1227 SDValue MemAddr, MemUpdate, MemOpc, Align;
1228 if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, MemUpdate, MemOpc, Align))
1231 SDValue Chain = N->getOperand(0);
1233 cast<ConstantSDNode>(N->getOperand(NumVecs+3))->getZExtValue();
1234 EVT VT = IsLoad ? N->getValueType(0) : N->getOperand(3).getValueType();
1235 bool is64BitVector = VT.is64BitVector();
1237 // Quad registers are handled by load/store of subregs. Find the subreg info.
1238 unsigned NumElts = 0;
1241 if (!is64BitVector) {
1242 RegVT = GetNEONSubregVT(VT);
1243 NumElts = RegVT.getVectorNumElements();
1244 SubregIdx = (Lane < NumElts) ? ARM::DSUBREG_0 : ARM::DSUBREG_1;
1247 unsigned OpcodeIndex;
1248 switch (VT.getSimpleVT().SimpleTy) {
1249 default: llvm_unreachable("unhandled vld/vst lane type");
1250 // Double-register operations:
1251 case MVT::v8i8: OpcodeIndex = 0; break;
1252 case MVT::v4i16: OpcodeIndex = 1; break;
1254 case MVT::v2i32: OpcodeIndex = 2; break;
1255 // Quad-register operations:
1256 case MVT::v8i16: OpcodeIndex = 0; break;
1258 case MVT::v4i32: OpcodeIndex = 1; break;
1261 SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32);
1262 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
1264 SmallVector<SDValue, 9> Ops;
1265 Ops.push_back(MemAddr);
1266 Ops.push_back(MemUpdate);
1267 Ops.push_back(MemOpc);
1268 Ops.push_back(Align);
1271 if (is64BitVector) {
1272 Opc = DOpcodes[OpcodeIndex];
1273 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1274 Ops.push_back(N->getOperand(Vec+3));
1276 // Check if this is loading the even or odd subreg of a Q register.
1277 if (Lane < NumElts) {
1278 Opc = QOpcodes0[OpcodeIndex];
1281 Opc = QOpcodes1[OpcodeIndex];
1283 // Extract the subregs of the input vector.
1284 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1285 Ops.push_back(CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
1286 N->getOperand(Vec+3)));
1288 Ops.push_back(getI32Imm(Lane));
1289 Ops.push_back(Pred);
1290 Ops.push_back(PredReg);
1291 Ops.push_back(Chain);
1294 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), NumVecs+8);
1296 std::vector<EVT> ResTys(NumVecs, RegVT);
1297 ResTys.push_back(MVT::Other);
1299 CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), NumVecs+8);
1300 // For a 64-bit vector load to D registers, nothing more needs to be done.
1304 // For 128-bit vectors, take the 64-bit results of the load and insert them
1305 // as subregs into the result.
1306 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1307 SDValue QuadVec = CurDAG->getTargetInsertSubreg(SubregIdx, dl, VT,
1308 N->getOperand(Vec+3),
1309 SDValue(VLdLn, Vec));
1310 ReplaceUses(SDValue(N, Vec), QuadVec);
1313 Chain = SDValue(VLdLn, NumVecs);
1314 ReplaceUses(SDValue(N, NumVecs), Chain);
1318 SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N,
1320 if (!Subtarget->hasV6T2Ops())
1323 unsigned Shl_imm = 0;
1324 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, Shl_imm)) {
1325 assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!");
1326 unsigned Srl_imm = 0;
1327 if (isInt32Immediate(N->getOperand(1), Srl_imm)) {
1328 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
1329 unsigned Width = 32 - Srl_imm;
1330 int LSB = Srl_imm - Shl_imm;
1333 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1334 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1335 CurDAG->getTargetConstant(LSB, MVT::i32),
1336 CurDAG->getTargetConstant(Width, MVT::i32),
1337 getAL(CurDAG), Reg0 };
1338 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1344 SDNode *ARMDAGToDAGISel::
1345 SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1346 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1349 if (SelectT2ShifterOperandReg(N, TrueVal, CPTmp0, CPTmp1)) {
1350 unsigned SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue();
1351 unsigned SOShOp = ARM_AM::getSORegShOp(SOVal);
1354 case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break;
1355 case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break;
1356 case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break;
1357 case ARM_AM::ror: Opc = ARM::t2MOVCCror; break;
1359 llvm_unreachable("Unknown so_reg opcode!");
1363 CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32);
1364 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1365 SDValue Ops[] = { FalseVal, CPTmp0, SOShImm, CC, CCR, InFlag };
1366 return CurDAG->SelectNodeTo(N, Opc, MVT::i32,Ops, 6);
1371 SDNode *ARMDAGToDAGISel::
1372 SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1373 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1377 if (SelectShifterOperandReg(N, TrueVal, CPTmp0, CPTmp1, CPTmp2)) {
1378 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1379 SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CPTmp2, CC, CCR, InFlag };
1380 return CurDAG->SelectNodeTo(N, ARM::MOVCCs, MVT::i32, Ops, 7);
1385 SDNode *ARMDAGToDAGISel::
1386 SelectT2CMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1387 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1388 ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
1392 if (Predicate_t2_so_imm(TrueVal.getNode())) {
1393 SDValue True = CurDAG->getTargetConstant(T->getZExtValue(), MVT::i32);
1394 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1395 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
1396 return CurDAG->SelectNodeTo(N,
1397 ARM::t2MOVCCi, MVT::i32, Ops, 5);
1402 SDNode *ARMDAGToDAGISel::
1403 SelectARMCMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1404 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1405 ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
1409 if (Predicate_so_imm(TrueVal.getNode())) {
1410 SDValue True = CurDAG->getTargetConstant(T->getZExtValue(), MVT::i32);
1411 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1412 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
1413 return CurDAG->SelectNodeTo(N,
1414 ARM::MOVCCi, MVT::i32, Ops, 5);
1419 SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDNode *N) {
1420 EVT VT = N->getValueType(0);
1421 SDValue FalseVal = N->getOperand(0);
1422 SDValue TrueVal = N->getOperand(1);
1423 SDValue CC = N->getOperand(2);
1424 SDValue CCR = N->getOperand(3);
1425 SDValue InFlag = N->getOperand(4);
1426 assert(CC.getOpcode() == ISD::Constant);
1427 assert(CCR.getOpcode() == ISD::Register);
1428 ARMCC::CondCodes CCVal =
1429 (ARMCC::CondCodes)cast<ConstantSDNode>(CC)->getZExtValue();
1431 if (!Subtarget->isThumb1Only() && VT == MVT::i32) {
1432 // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1433 // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1434 // Pattern complexity = 18 cost = 1 size = 0
1438 if (Subtarget->isThumb()) {
1439 SDNode *Res = SelectT2CMOVShiftOp(N, FalseVal, TrueVal,
1440 CCVal, CCR, InFlag);
1442 Res = SelectT2CMOVShiftOp(N, TrueVal, FalseVal,
1443 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1447 SDNode *Res = SelectARMCMOVShiftOp(N, FalseVal, TrueVal,
1448 CCVal, CCR, InFlag);
1450 Res = SelectARMCMOVShiftOp(N, TrueVal, FalseVal,
1451 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1456 // Pattern: (ARMcmov:i32 GPR:i32:$false,
1457 // (imm:i32)<<P:Predicate_so_imm>>:$true,
1459 // Emits: (MOVCCi:i32 GPR:i32:$false,
1460 // (so_imm:i32 (imm:i32):$true), (imm:i32):$cc)
1461 // Pattern complexity = 10 cost = 1 size = 0
1462 if (Subtarget->isThumb()) {
1463 SDNode *Res = SelectT2CMOVSoImmOp(N, FalseVal, TrueVal,
1464 CCVal, CCR, InFlag);
1466 Res = SelectT2CMOVSoImmOp(N, TrueVal, FalseVal,
1467 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1471 SDNode *Res = SelectARMCMOVSoImmOp(N, FalseVal, TrueVal,
1472 CCVal, CCR, InFlag);
1474 Res = SelectARMCMOVSoImmOp(N, TrueVal, FalseVal,
1475 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1481 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1482 // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1483 // Pattern complexity = 6 cost = 1 size = 0
1485 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1486 // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1487 // Pattern complexity = 6 cost = 11 size = 0
1489 // Also FCPYScc and FCPYDcc.
1490 SDValue Tmp2 = CurDAG->getTargetConstant(CCVal, MVT::i32);
1491 SDValue Ops[] = { FalseVal, TrueVal, Tmp2, CCR, InFlag };
1493 switch (VT.getSimpleVT().SimpleTy) {
1494 default: assert(false && "Illegal conditional move type!");
1497 Opc = Subtarget->isThumb()
1498 ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo)
1508 return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
1511 SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
1512 DebugLoc dl = N->getDebugLoc();
1514 if (N->isMachineOpcode())
1515 return NULL; // Already selected.
1517 switch (N->getOpcode()) {
1519 case ISD::Constant: {
1520 unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
1522 if (Subtarget->hasThumb2())
1523 // Thumb2-aware targets have the MOVT instruction, so all immediates can
1524 // be done with MOV + MOVT, at worst.
1527 if (Subtarget->isThumb()) {
1528 UseCP = (Val > 255 && // MOV
1529 ~Val > 255 && // MOV + MVN
1530 !ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL
1532 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
1533 ARM_AM::getSOImmVal(~Val) == -1 && // MVN
1534 !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs.
1539 CurDAG->getTargetConstantPool(ConstantInt::get(
1540 Type::getInt32Ty(*CurDAG->getContext()), Val),
1541 TLI.getPointerTy());
1544 if (Subtarget->isThumb1Only()) {
1545 SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32);
1546 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
1547 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
1548 ResNode = CurDAG->getMachineNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other,
1553 CurDAG->getRegister(0, MVT::i32),
1554 CurDAG->getTargetConstant(0, MVT::i32),
1556 CurDAG->getRegister(0, MVT::i32),
1557 CurDAG->getEntryNode()
1559 ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
1562 ReplaceUses(SDValue(N, 0), SDValue(ResNode, 0));
1566 // Other cases are autogenerated.
1569 case ISD::FrameIndex: {
1570 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
1571 int FI = cast<FrameIndexSDNode>(N)->getIndex();
1572 SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1573 if (Subtarget->isThumb1Only()) {
1574 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
1575 CurDAG->getTargetConstant(0, MVT::i32));
1577 unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
1578 ARM::t2ADDri : ARM::ADDri);
1579 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
1580 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1581 CurDAG->getRegister(0, MVT::i32) };
1582 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1585 case ARMISD::DYN_ALLOC:
1586 return SelectDYN_ALLOC(N);
1588 if (SDNode *I = SelectV6T2BitfieldExtractOp(N,
1589 Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX))
1593 if (SDNode *I = SelectV6T2BitfieldExtractOp(N,
1594 Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX))
1598 if (Subtarget->isThumb1Only())
1600 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1601 unsigned RHSV = C->getZExtValue();
1603 if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
1604 unsigned ShImm = Log2_32(RHSV-1);
1607 SDValue V = N->getOperand(0);
1608 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
1609 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
1610 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1611 if (Subtarget->isThumb()) {
1612 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1613 return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
1615 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1616 return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7);
1619 if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
1620 unsigned ShImm = Log2_32(RHSV+1);
1623 SDValue V = N->getOperand(0);
1624 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
1625 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
1626 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1627 if (Subtarget->isThumb()) {
1628 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0 };
1629 return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 5);
1631 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1632 return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7);
1638 // (and (or x, c2), c1) and top 16-bits of c1 and c2 match, lower 16-bits
1639 // of c1 are 0xffff, and lower 16-bit of c2 are 0. That is, the top 16-bits
1640 // are entirely contributed by c2 and lower 16-bits are entirely contributed
1641 // by x. That's equal to (or (and x, 0xffff), (and c1, 0xffff0000)).
1642 // Select it to: "movt x, ((c1 & 0xffff) >> 16)
1643 EVT VT = N->getValueType(0);
1646 unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2())
1648 : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0);
1651 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
1652 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1655 if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) {
1656 SDValue N2 = N0.getOperand(1);
1657 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1660 unsigned N1CVal = N1C->getZExtValue();
1661 unsigned N2CVal = N2C->getZExtValue();
1662 if ((N1CVal & 0xffff0000U) == (N2CVal & 0xffff0000U) &&
1663 (N1CVal & 0xffffU) == 0xffffU &&
1664 (N2CVal & 0xffffU) == 0x0U) {
1665 SDValue Imm16 = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16,
1667 SDValue Ops[] = { N0.getOperand(0), Imm16,
1668 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
1669 return CurDAG->getMachineNode(Opc, dl, VT, Ops, 4);
1674 case ARMISD::VMOVRRD:
1675 return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32,
1676 N->getOperand(0), getAL(CurDAG),
1677 CurDAG->getRegister(0, MVT::i32));
1678 case ISD::UMUL_LOHI: {
1679 if (Subtarget->isThumb1Only())
1681 if (Subtarget->isThumb()) {
1682 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
1683 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1684 CurDAG->getRegister(0, MVT::i32) };
1685 return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32, Ops,4);
1687 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
1688 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1689 CurDAG->getRegister(0, MVT::i32) };
1690 return CurDAG->getMachineNode(ARM::UMULL, dl, MVT::i32, MVT::i32, Ops, 5);
1693 case ISD::SMUL_LOHI: {
1694 if (Subtarget->isThumb1Only())
1696 if (Subtarget->isThumb()) {
1697 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
1698 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
1699 return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32, Ops,4);
1701 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
1702 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1703 CurDAG->getRegister(0, MVT::i32) };
1704 return CurDAG->getMachineNode(ARM::SMULL, dl, MVT::i32, MVT::i32, Ops, 5);
1708 SDNode *ResNode = 0;
1709 if (Subtarget->isThumb() && Subtarget->hasThumb2())
1710 ResNode = SelectT2IndexedLoad(N);
1712 ResNode = SelectARMIndexedLoad(N);
1715 // Other cases are autogenerated.
1718 case ARMISD::BRCOND: {
1719 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1720 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
1721 // Pattern complexity = 6 cost = 1 size = 0
1723 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1724 // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
1725 // Pattern complexity = 6 cost = 1 size = 0
1727 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1728 // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
1729 // Pattern complexity = 6 cost = 1 size = 0
1731 unsigned Opc = Subtarget->isThumb() ?
1732 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
1733 SDValue Chain = N->getOperand(0);
1734 SDValue N1 = N->getOperand(1);
1735 SDValue N2 = N->getOperand(2);
1736 SDValue N3 = N->getOperand(3);
1737 SDValue InFlag = N->getOperand(4);
1738 assert(N1.getOpcode() == ISD::BasicBlock);
1739 assert(N2.getOpcode() == ISD::Constant);
1740 assert(N3.getOpcode() == ISD::Register);
1742 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1743 cast<ConstantSDNode>(N2)->getZExtValue()),
1745 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
1746 SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,
1748 Chain = SDValue(ResNode, 0);
1749 if (N->getNumValues() == 2) {
1750 InFlag = SDValue(ResNode, 1);
1751 ReplaceUses(SDValue(N, 1), InFlag);
1753 ReplaceUses(SDValue(N, 0),
1754 SDValue(Chain.getNode(), Chain.getResNo()));
1758 return SelectCMOVOp(N);
1759 case ARMISD::CNEG: {
1760 EVT VT = N->getValueType(0);
1761 SDValue N0 = N->getOperand(0);
1762 SDValue N1 = N->getOperand(1);
1763 SDValue N2 = N->getOperand(2);
1764 SDValue N3 = N->getOperand(3);
1765 SDValue InFlag = N->getOperand(4);
1766 assert(N2.getOpcode() == ISD::Constant);
1767 assert(N3.getOpcode() == ISD::Register);
1769 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1770 cast<ConstantSDNode>(N2)->getZExtValue()),
1772 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
1774 switch (VT.getSimpleVT().SimpleTy) {
1775 default: assert(false && "Illegal conditional move type!");
1784 return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
1787 case ARMISD::VZIP: {
1789 EVT VT = N->getValueType(0);
1790 switch (VT.getSimpleVT().SimpleTy) {
1791 default: return NULL;
1792 case MVT::v8i8: Opc = ARM::VZIPd8; break;
1793 case MVT::v4i16: Opc = ARM::VZIPd16; break;
1795 case MVT::v2i32: Opc = ARM::VZIPd32; break;
1796 case MVT::v16i8: Opc = ARM::VZIPq8; break;
1797 case MVT::v8i16: Opc = ARM::VZIPq16; break;
1799 case MVT::v4i32: Opc = ARM::VZIPq32; break;
1801 SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32);
1802 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
1803 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
1804 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
1806 case ARMISD::VUZP: {
1808 EVT VT = N->getValueType(0);
1809 switch (VT.getSimpleVT().SimpleTy) {
1810 default: return NULL;
1811 case MVT::v8i8: Opc = ARM::VUZPd8; break;
1812 case MVT::v4i16: Opc = ARM::VUZPd16; break;
1814 case MVT::v2i32: Opc = ARM::VUZPd32; break;
1815 case MVT::v16i8: Opc = ARM::VUZPq8; break;
1816 case MVT::v8i16: Opc = ARM::VUZPq16; break;
1818 case MVT::v4i32: Opc = ARM::VUZPq32; break;
1820 SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32);
1821 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
1822 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
1823 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
1825 case ARMISD::VTRN: {
1827 EVT VT = N->getValueType(0);
1828 switch (VT.getSimpleVT().SimpleTy) {
1829 default: return NULL;
1830 case MVT::v8i8: Opc = ARM::VTRNd8; break;
1831 case MVT::v4i16: Opc = ARM::VTRNd16; break;
1833 case MVT::v2i32: Opc = ARM::VTRNd32; break;
1834 case MVT::v16i8: Opc = ARM::VTRNq8; break;
1835 case MVT::v8i16: Opc = ARM::VTRNq16; break;
1837 case MVT::v4i32: Opc = ARM::VTRNq32; break;
1839 SDValue Pred = CurDAG->getTargetConstant(14, MVT::i32);
1840 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
1841 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
1842 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
1845 case ISD::INTRINSIC_VOID:
1846 case ISD::INTRINSIC_W_CHAIN: {
1847 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
1852 case Intrinsic::arm_neon_vld2: {
1853 unsigned DOpcodes[] = { ARM::VLD2d8, ARM::VLD2d16,
1854 ARM::VLD2d32, ARM::VLD2d64 };
1855 unsigned QOpcodes[] = { ARM::VLD2q8, ARM::VLD2q16, ARM::VLD2q32 };
1856 return SelectVLD(N, 2, DOpcodes, QOpcodes, 0);
1859 case Intrinsic::arm_neon_vld3: {
1860 unsigned DOpcodes[] = { ARM::VLD3d8, ARM::VLD3d16,
1861 ARM::VLD3d32, ARM::VLD3d64 };
1862 unsigned QOpcodes0[] = { ARM::VLD3q8_UPD,
1865 unsigned QOpcodes1[] = { ARM::VLD3q8odd_UPD,
1866 ARM::VLD3q16odd_UPD,
1867 ARM::VLD3q32odd_UPD };
1868 return SelectVLD(N, 3, DOpcodes, QOpcodes0, QOpcodes1);
1871 case Intrinsic::arm_neon_vld4: {
1872 unsigned DOpcodes[] = { ARM::VLD4d8, ARM::VLD4d16,
1873 ARM::VLD4d32, ARM::VLD4d64 };
1874 unsigned QOpcodes0[] = { ARM::VLD4q8_UPD,
1877 unsigned QOpcodes1[] = { ARM::VLD4q8odd_UPD,
1878 ARM::VLD4q16odd_UPD,
1879 ARM::VLD4q32odd_UPD };
1880 return SelectVLD(N, 4, DOpcodes, QOpcodes0, QOpcodes1);
1883 case Intrinsic::arm_neon_vld2lane: {
1884 unsigned DOpcodes[] = { ARM::VLD2LNd8, ARM::VLD2LNd16, ARM::VLD2LNd32 };
1885 unsigned QOpcodes0[] = { ARM::VLD2LNq16, ARM::VLD2LNq32 };
1886 unsigned QOpcodes1[] = { ARM::VLD2LNq16odd, ARM::VLD2LNq32odd };
1887 return SelectVLDSTLane(N, true, 2, DOpcodes, QOpcodes0, QOpcodes1);
1890 case Intrinsic::arm_neon_vld3lane: {
1891 unsigned DOpcodes[] = { ARM::VLD3LNd8, ARM::VLD3LNd16, ARM::VLD3LNd32 };
1892 unsigned QOpcodes0[] = { ARM::VLD3LNq16, ARM::VLD3LNq32 };
1893 unsigned QOpcodes1[] = { ARM::VLD3LNq16odd, ARM::VLD3LNq32odd };
1894 return SelectVLDSTLane(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
1897 case Intrinsic::arm_neon_vld4lane: {
1898 unsigned DOpcodes[] = { ARM::VLD4LNd8, ARM::VLD4LNd16, ARM::VLD4LNd32 };
1899 unsigned QOpcodes0[] = { ARM::VLD4LNq16, ARM::VLD4LNq32 };
1900 unsigned QOpcodes1[] = { ARM::VLD4LNq16odd, ARM::VLD4LNq32odd };
1901 return SelectVLDSTLane(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
1904 case Intrinsic::arm_neon_vst2: {
1905 unsigned DOpcodes[] = { ARM::VST2d8, ARM::VST2d16,
1906 ARM::VST2d32, ARM::VST2d64 };
1907 unsigned QOpcodes[] = { ARM::VST2q8, ARM::VST2q16, ARM::VST2q32 };
1908 return SelectVST(N, 2, DOpcodes, QOpcodes, 0);
1911 case Intrinsic::arm_neon_vst3: {
1912 unsigned DOpcodes[] = { ARM::VST3d8, ARM::VST3d16,
1913 ARM::VST3d32, ARM::VST3d64 };
1914 unsigned QOpcodes0[] = { ARM::VST3q8_UPD,
1917 unsigned QOpcodes1[] = { ARM::VST3q8odd_UPD,
1918 ARM::VST3q16odd_UPD,
1919 ARM::VST3q32odd_UPD };
1920 return SelectVST(N, 3, DOpcodes, QOpcodes0, QOpcodes1);
1923 case Intrinsic::arm_neon_vst4: {
1924 unsigned DOpcodes[] = { ARM::VST4d8, ARM::VST4d16,
1925 ARM::VST4d32, ARM::VST4d64 };
1926 unsigned QOpcodes0[] = { ARM::VST4q8_UPD,
1929 unsigned QOpcodes1[] = { ARM::VST4q8odd_UPD,
1930 ARM::VST4q16odd_UPD,
1931 ARM::VST4q32odd_UPD };
1932 return SelectVST(N, 4, DOpcodes, QOpcodes0, QOpcodes1);
1935 case Intrinsic::arm_neon_vst2lane: {
1936 unsigned DOpcodes[] = { ARM::VST2LNd8, ARM::VST2LNd16, ARM::VST2LNd32 };
1937 unsigned QOpcodes0[] = { ARM::VST2LNq16, ARM::VST2LNq32 };
1938 unsigned QOpcodes1[] = { ARM::VST2LNq16odd, ARM::VST2LNq32odd };
1939 return SelectVLDSTLane(N, false, 2, DOpcodes, QOpcodes0, QOpcodes1);
1942 case Intrinsic::arm_neon_vst3lane: {
1943 unsigned DOpcodes[] = { ARM::VST3LNd8, ARM::VST3LNd16, ARM::VST3LNd32 };
1944 unsigned QOpcodes0[] = { ARM::VST3LNq16, ARM::VST3LNq32 };
1945 unsigned QOpcodes1[] = { ARM::VST3LNq16odd, ARM::VST3LNq32odd };
1946 return SelectVLDSTLane(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
1949 case Intrinsic::arm_neon_vst4lane: {
1950 unsigned DOpcodes[] = { ARM::VST4LNd8, ARM::VST4LNd16, ARM::VST4LNd32 };
1951 unsigned QOpcodes0[] = { ARM::VST4LNq16, ARM::VST4LNq32 };
1952 unsigned QOpcodes1[] = { ARM::VST4LNq16odd, ARM::VST4LNq32odd };
1953 return SelectVLDSTLane(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
1959 return SelectCode(N);
1962 bool ARMDAGToDAGISel::
1963 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
1964 std::vector<SDValue> &OutOps) {
1965 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
1966 // Require the address to be in a register. That is safe for all ARM
1967 // variants and it is hard to do anything much smarter without knowing
1968 // how the operand is used.
1969 OutOps.push_back(Op);
1973 /// createARMISelDag - This pass converts a legalized DAG into a
1974 /// ARM-specific DAG, ready for instruction scheduling.
1976 FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
1977 CodeGenOpt::Level OptLevel) {
1978 return new ARMDAGToDAGISel(TM, OptLevel);