1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMISelLowering.h"
17 #include "ARMTargetMachine.h"
18 #include "llvm/CallingConv.h"
19 #include "llvm/Constants.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/LLVMContext.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CodeGen/SelectionDAGISel.h"
29 #include "llvm/Target/TargetLowering.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Support/Compiler.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
38 //===--------------------------------------------------------------------===//
39 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
40 /// instructions for SelectionDAG operations.
43 class ARMDAGToDAGISel : public SelectionDAGISel {
44 ARMBaseTargetMachine &TM;
46 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
47 /// make the right decision when generating code for different targets.
48 const ARMSubtarget *Subtarget;
51 explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm,
52 CodeGenOpt::Level OptLevel)
53 : SelectionDAGISel(tm, OptLevel), TM(tm),
54 Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
57 virtual const char *getPassName() const {
58 return "ARM Instruction Selection";
61 /// getI32Imm - Return a target constant of type i32 with the specified
63 inline SDValue getI32Imm(unsigned Imm) {
64 return CurDAG->getTargetConstant(Imm, MVT::i32);
67 SDNode *Select(SDValue Op);
68 virtual void InstructionSelect();
69 bool SelectShifterOperandReg(SDValue Op, SDValue N, SDValue &A,
70 SDValue &B, SDValue &C);
71 bool SelectAddrMode2(SDValue Op, SDValue N, SDValue &Base,
72 SDValue &Offset, SDValue &Opc);
73 bool SelectAddrMode2Offset(SDValue Op, SDValue N,
74 SDValue &Offset, SDValue &Opc);
75 bool SelectAddrMode3(SDValue Op, SDValue N, SDValue &Base,
76 SDValue &Offset, SDValue &Opc);
77 bool SelectAddrMode3Offset(SDValue Op, SDValue N,
78 SDValue &Offset, SDValue &Opc);
79 bool SelectAddrMode4(SDValue Op, SDValue N, SDValue &Addr,
81 bool SelectAddrMode5(SDValue Op, SDValue N, SDValue &Base,
83 bool SelectAddrMode6(SDValue Op, SDValue N, SDValue &Addr, SDValue &Update,
84 SDValue &Opc, SDValue &Align);
86 bool SelectAddrModePC(SDValue Op, SDValue N, SDValue &Offset,
89 bool SelectThumbAddrModeRR(SDValue Op, SDValue N, SDValue &Base,
91 bool SelectThumbAddrModeRI5(SDValue Op, SDValue N, unsigned Scale,
92 SDValue &Base, SDValue &OffImm,
94 bool SelectThumbAddrModeS1(SDValue Op, SDValue N, SDValue &Base,
95 SDValue &OffImm, SDValue &Offset);
96 bool SelectThumbAddrModeS2(SDValue Op, SDValue N, SDValue &Base,
97 SDValue &OffImm, SDValue &Offset);
98 bool SelectThumbAddrModeS4(SDValue Op, SDValue N, SDValue &Base,
99 SDValue &OffImm, SDValue &Offset);
100 bool SelectThumbAddrModeSP(SDValue Op, SDValue N, SDValue &Base,
103 bool SelectT2ShifterOperandReg(SDValue Op, SDValue N,
104 SDValue &BaseReg, SDValue &Opc);
105 bool SelectT2AddrModeImm12(SDValue Op, SDValue N, SDValue &Base,
107 bool SelectT2AddrModeImm8(SDValue Op, SDValue N, SDValue &Base,
109 bool SelectT2AddrModeImm8Offset(SDValue Op, SDValue N,
111 bool SelectT2AddrModeImm8s4(SDValue Op, SDValue N, SDValue &Base,
113 bool SelectT2AddrModeSoReg(SDValue Op, SDValue N, SDValue &Base,
114 SDValue &OffReg, SDValue &ShImm);
116 // Include the pieces autogenerated from the target description.
117 #include "ARMGenDAGISel.inc"
120 /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
122 SDNode *SelectARMIndexedLoad(SDValue Op);
123 SDNode *SelectT2IndexedLoad(SDValue Op);
125 /// SelectDYN_ALLOC - Select dynamic alloc for Thumb.
126 SDNode *SelectDYN_ALLOC(SDValue Op);
128 /// SelectVLD - Select NEON load intrinsics. NumVecs should
129 /// be 2, 3 or 4. The opcode arrays specify the instructions used for
130 /// loads of D registers and even subregs and odd subregs of Q registers.
131 /// For NumVecs == 2, QOpcodes1 is not used.
132 SDNode *SelectVLD(SDValue Op, unsigned NumVecs, unsigned *DOpcodes,
133 unsigned *QOpcodes0, unsigned *QOpcodes1);
135 /// SelectVST - Select NEON store intrinsics. NumVecs should
136 /// be 2, 3 or 4. The opcode arrays specify the instructions used for
137 /// stores of D registers and even subregs and odd subregs of Q registers.
138 /// For NumVecs == 2, QOpcodes1 is not used.
139 SDNode *SelectVST(SDValue Op, unsigned NumVecs, unsigned *DOpcodes,
140 unsigned *QOpcodes0, unsigned *QOpcodes1);
142 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should
143 /// be 2, 3 or 4. The opcode arrays specify the instructions used for
144 /// load/store of D registers and even subregs and odd subregs of Q registers.
145 SDNode *SelectVLDSTLane(SDValue Op, bool IsLoad, unsigned NumVecs,
146 unsigned *DOpcodes, unsigned *QOpcodes0,
147 unsigned *QOpcodes1);
149 /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM.
150 SDNode *SelectV6T2BitfieldExtractOp(SDValue Op, unsigned Opc);
152 /// SelectCMOVOp - Select CMOV instructions for ARM.
153 SDNode *SelectCMOVOp(SDValue Op);
154 SDNode *SelectT2CMOVShiftOp(SDValue Op, SDValue FalseVal, SDValue TrueVal,
155 ARMCC::CondCodes CCVal, SDValue CCR,
157 SDNode *SelectARMCMOVShiftOp(SDValue Op, SDValue FalseVal, SDValue TrueVal,
158 ARMCC::CondCodes CCVal, SDValue CCR,
160 SDNode *SelectT2CMOVSoImmOp(SDValue Op, SDValue FalseVal, SDValue TrueVal,
161 ARMCC::CondCodes CCVal, SDValue CCR,
163 SDNode *SelectARMCMOVSoImmOp(SDValue Op, SDValue FalseVal, SDValue TrueVal,
164 ARMCC::CondCodes CCVal, SDValue CCR,
167 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
168 /// inline asm expressions.
169 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
171 std::vector<SDValue> &OutOps);
173 /// PairDRegs - Insert a pair of double registers into an implicit def to
174 /// form a quad register.
175 SDNode *PairDRegs(EVT VT, SDValue V0, SDValue V1);
179 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
180 /// operand. If so Imm will receive the 32-bit value.
181 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
182 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
183 Imm = cast<ConstantSDNode>(N)->getZExtValue();
189 // isInt32Immediate - This method tests to see if a constant operand.
190 // If so Imm will receive the 32 bit value.
191 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
192 return isInt32Immediate(N.getNode(), Imm);
195 // isOpcWithIntImmediate - This method tests to see if the node is a specific
196 // opcode and that it has a immediate integer right operand.
197 // If so Imm will receive the 32 bit value.
198 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
199 return N->getOpcode() == Opc &&
200 isInt32Immediate(N->getOperand(1).getNode(), Imm);
204 void ARMDAGToDAGISel::InstructionSelect() {
206 CurDAG->RemoveDeadNodes();
209 bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue Op,
214 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
216 // Don't match base register only case. That is matched to a separate
217 // lower complexity pattern with explicit register operand.
218 if (ShOpcVal == ARM_AM::no_shift) return false;
220 BaseReg = N.getOperand(0);
221 unsigned ShImmVal = 0;
222 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
223 ShReg = CurDAG->getRegister(0, MVT::i32);
224 ShImmVal = RHS->getZExtValue() & 31;
226 ShReg = N.getOperand(1);
228 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
233 bool ARMDAGToDAGISel::SelectAddrMode2(SDValue Op, SDValue N,
234 SDValue &Base, SDValue &Offset,
236 if (N.getOpcode() == ISD::MUL) {
237 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
238 // X * [3,5,9] -> X + X * [2,4,8] etc.
239 int RHSC = (int)RHS->getZExtValue();
242 ARM_AM::AddrOpc AddSub = ARM_AM::add;
244 AddSub = ARM_AM::sub;
247 if (isPowerOf2_32(RHSC)) {
248 unsigned ShAmt = Log2_32(RHSC);
249 Base = Offset = N.getOperand(0);
250 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
259 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
261 if (N.getOpcode() == ISD::FrameIndex) {
262 int FI = cast<FrameIndexSDNode>(N)->getIndex();
263 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
264 } else if (N.getOpcode() == ARMISD::Wrapper) {
265 Base = N.getOperand(0);
267 Offset = CurDAG->getRegister(0, MVT::i32);
268 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
274 // Match simple R +/- imm12 operands.
275 if (N.getOpcode() == ISD::ADD)
276 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
277 int RHSC = (int)RHS->getZExtValue();
278 if ((RHSC >= 0 && RHSC < 0x1000) ||
279 (RHSC < 0 && RHSC > -0x1000)) { // 12 bits.
280 Base = N.getOperand(0);
281 if (Base.getOpcode() == ISD::FrameIndex) {
282 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
283 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
285 Offset = CurDAG->getRegister(0, MVT::i32);
287 ARM_AM::AddrOpc AddSub = ARM_AM::add;
289 AddSub = ARM_AM::sub;
292 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
299 // Otherwise this is R +/- [possibly shifted] R.
300 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
301 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
304 Base = N.getOperand(0);
305 Offset = N.getOperand(1);
307 if (ShOpcVal != ARM_AM::no_shift) {
308 // Check to see if the RHS of the shift is a constant, if not, we can't fold
310 if (ConstantSDNode *Sh =
311 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
312 ShAmt = Sh->getZExtValue();
313 Offset = N.getOperand(1).getOperand(0);
315 ShOpcVal = ARM_AM::no_shift;
319 // Try matching (R shl C) + (R).
320 if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift) {
321 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
322 if (ShOpcVal != ARM_AM::no_shift) {
323 // Check to see if the RHS of the shift is a constant, if not, we can't
325 if (ConstantSDNode *Sh =
326 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
327 ShAmt = Sh->getZExtValue();
328 Offset = N.getOperand(0).getOperand(0);
329 Base = N.getOperand(1);
331 ShOpcVal = ARM_AM::no_shift;
336 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
341 bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDValue Op, SDValue N,
342 SDValue &Offset, SDValue &Opc) {
343 unsigned Opcode = Op.getOpcode();
344 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
345 ? cast<LoadSDNode>(Op)->getAddressingMode()
346 : cast<StoreSDNode>(Op)->getAddressingMode();
347 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
348 ? ARM_AM::add : ARM_AM::sub;
349 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
350 int Val = (int)C->getZExtValue();
351 if (Val >= 0 && Val < 0x1000) { // 12 bits.
352 Offset = CurDAG->getRegister(0, MVT::i32);
353 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
361 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
363 if (ShOpcVal != ARM_AM::no_shift) {
364 // Check to see if the RHS of the shift is a constant, if not, we can't fold
366 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
367 ShAmt = Sh->getZExtValue();
368 Offset = N.getOperand(0);
370 ShOpcVal = ARM_AM::no_shift;
374 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
380 bool ARMDAGToDAGISel::SelectAddrMode3(SDValue Op, SDValue N,
381 SDValue &Base, SDValue &Offset,
383 if (N.getOpcode() == ISD::SUB) {
384 // X - C is canonicalize to X + -C, no need to handle it here.
385 Base = N.getOperand(0);
386 Offset = N.getOperand(1);
387 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
391 if (N.getOpcode() != ISD::ADD) {
393 if (N.getOpcode() == ISD::FrameIndex) {
394 int FI = cast<FrameIndexSDNode>(N)->getIndex();
395 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
397 Offset = CurDAG->getRegister(0, MVT::i32);
398 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
402 // If the RHS is +/- imm8, fold into addr mode.
403 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
404 int RHSC = (int)RHS->getZExtValue();
405 if ((RHSC >= 0 && RHSC < 256) ||
406 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
407 Base = N.getOperand(0);
408 if (Base.getOpcode() == ISD::FrameIndex) {
409 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
410 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
412 Offset = CurDAG->getRegister(0, MVT::i32);
414 ARM_AM::AddrOpc AddSub = ARM_AM::add;
416 AddSub = ARM_AM::sub;
419 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
424 Base = N.getOperand(0);
425 Offset = N.getOperand(1);
426 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
430 bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDValue Op, SDValue N,
431 SDValue &Offset, SDValue &Opc) {
432 unsigned Opcode = Op.getOpcode();
433 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
434 ? cast<LoadSDNode>(Op)->getAddressingMode()
435 : cast<StoreSDNode>(Op)->getAddressingMode();
436 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
437 ? ARM_AM::add : ARM_AM::sub;
438 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
439 int Val = (int)C->getZExtValue();
440 if (Val >= 0 && Val < 256) {
441 Offset = CurDAG->getRegister(0, MVT::i32);
442 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
448 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
452 bool ARMDAGToDAGISel::SelectAddrMode4(SDValue Op, SDValue N,
453 SDValue &Addr, SDValue &Mode) {
455 Mode = CurDAG->getTargetConstant(0, MVT::i32);
459 bool ARMDAGToDAGISel::SelectAddrMode5(SDValue Op, SDValue N,
460 SDValue &Base, SDValue &Offset) {
461 if (N.getOpcode() != ISD::ADD) {
463 if (N.getOpcode() == ISD::FrameIndex) {
464 int FI = cast<FrameIndexSDNode>(N)->getIndex();
465 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
466 } else if (N.getOpcode() == ARMISD::Wrapper) {
467 Base = N.getOperand(0);
469 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
474 // If the RHS is +/- imm8, fold into addr mode.
475 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
476 int RHSC = (int)RHS->getZExtValue();
477 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied by 4.
479 if ((RHSC >= 0 && RHSC < 256) ||
480 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
481 Base = N.getOperand(0);
482 if (Base.getOpcode() == ISD::FrameIndex) {
483 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
484 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
487 ARM_AM::AddrOpc AddSub = ARM_AM::add;
489 AddSub = ARM_AM::sub;
492 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
500 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
505 bool ARMDAGToDAGISel::SelectAddrMode6(SDValue Op, SDValue N,
506 SDValue &Addr, SDValue &Update,
507 SDValue &Opc, SDValue &Align) {
509 // Default to no writeback.
510 Update = CurDAG->getRegister(0, MVT::i32);
511 Opc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(false), MVT::i32);
512 // Default to no alignment.
513 Align = CurDAG->getTargetConstant(0, MVT::i32);
517 bool ARMDAGToDAGISel::SelectAddrModePC(SDValue Op, SDValue N,
518 SDValue &Offset, SDValue &Label) {
519 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
520 Offset = N.getOperand(0);
521 SDValue N1 = N.getOperand(1);
522 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
529 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue Op, SDValue N,
530 SDValue &Base, SDValue &Offset){
531 // FIXME dl should come from the parent load or store, not the address
532 DebugLoc dl = Op.getDebugLoc();
533 if (N.getOpcode() != ISD::ADD) {
534 ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
535 if (!NC || NC->getZExtValue() != 0)
542 Base = N.getOperand(0);
543 Offset = N.getOperand(1);
548 ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDValue Op, SDValue N,
549 unsigned Scale, SDValue &Base,
550 SDValue &OffImm, SDValue &Offset) {
552 SDValue TmpBase, TmpOffImm;
553 if (SelectThumbAddrModeSP(Op, N, TmpBase, TmpOffImm))
554 return false; // We want to select tLDRspi / tSTRspi instead.
555 if (N.getOpcode() == ARMISD::Wrapper &&
556 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
557 return false; // We want to select tLDRpci instead.
560 if (N.getOpcode() != ISD::ADD) {
561 Base = (N.getOpcode() == ARMISD::Wrapper) ? N.getOperand(0) : N;
562 Offset = CurDAG->getRegister(0, MVT::i32);
563 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
567 // Thumb does not have [sp, r] address mode.
568 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
569 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
570 if ((LHSR && LHSR->getReg() == ARM::SP) ||
571 (RHSR && RHSR->getReg() == ARM::SP)) {
573 Offset = CurDAG->getRegister(0, MVT::i32);
574 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
578 // If the RHS is + imm5 * scale, fold into addr mode.
579 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
580 int RHSC = (int)RHS->getZExtValue();
581 if ((RHSC & (Scale-1)) == 0) { // The constant is implicitly multiplied.
583 if (RHSC >= 0 && RHSC < 32) {
584 Base = N.getOperand(0);
585 Offset = CurDAG->getRegister(0, MVT::i32);
586 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
592 Base = N.getOperand(0);
593 Offset = N.getOperand(1);
594 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
598 bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDValue Op, SDValue N,
599 SDValue &Base, SDValue &OffImm,
601 return SelectThumbAddrModeRI5(Op, N, 1, Base, OffImm, Offset);
604 bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDValue Op, SDValue N,
605 SDValue &Base, SDValue &OffImm,
607 return SelectThumbAddrModeRI5(Op, N, 2, Base, OffImm, Offset);
610 bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDValue Op, SDValue N,
611 SDValue &Base, SDValue &OffImm,
613 return SelectThumbAddrModeRI5(Op, N, 4, Base, OffImm, Offset);
616 bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue Op, SDValue N,
617 SDValue &Base, SDValue &OffImm) {
618 if (N.getOpcode() == ISD::FrameIndex) {
619 int FI = cast<FrameIndexSDNode>(N)->getIndex();
620 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
621 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
625 if (N.getOpcode() != ISD::ADD)
628 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
629 if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
630 (LHSR && LHSR->getReg() == ARM::SP)) {
631 // If the RHS is + imm8 * scale, fold into addr mode.
632 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
633 int RHSC = (int)RHS->getZExtValue();
634 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied.
636 if (RHSC >= 0 && RHSC < 256) {
637 Base = N.getOperand(0);
638 if (Base.getOpcode() == ISD::FrameIndex) {
639 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
640 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
642 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
652 bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue Op, SDValue N,
655 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
657 // Don't match base register only case. That is matched to a separate
658 // lower complexity pattern with explicit register operand.
659 if (ShOpcVal == ARM_AM::no_shift) return false;
661 BaseReg = N.getOperand(0);
662 unsigned ShImmVal = 0;
663 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
664 ShImmVal = RHS->getZExtValue() & 31;
665 Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
672 bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue Op, SDValue N,
673 SDValue &Base, SDValue &OffImm) {
674 // Match simple R + imm12 operands.
677 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
678 if (N.getOpcode() == ISD::FrameIndex) {
679 // Match frame index...
680 int FI = cast<FrameIndexSDNode>(N)->getIndex();
681 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
682 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
684 } else if (N.getOpcode() == ARMISD::Wrapper) {
685 Base = N.getOperand(0);
686 if (Base.getOpcode() == ISD::TargetConstantPool)
687 return false; // We want to select t2LDRpci instead.
690 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
694 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
695 if (SelectT2AddrModeImm8(Op, N, Base, OffImm))
696 // Let t2LDRi8 handle (R - imm8).
699 int RHSC = (int)RHS->getZExtValue();
700 if (N.getOpcode() == ISD::SUB)
703 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
704 Base = N.getOperand(0);
705 if (Base.getOpcode() == ISD::FrameIndex) {
706 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
707 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
709 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
716 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
720 bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue Op, SDValue N,
721 SDValue &Base, SDValue &OffImm) {
722 // Match simple R - imm8 operands.
723 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::SUB) {
724 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
725 int RHSC = (int)RHS->getSExtValue();
726 if (N.getOpcode() == ISD::SUB)
729 if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative)
730 Base = N.getOperand(0);
731 if (Base.getOpcode() == ISD::FrameIndex) {
732 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
733 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
735 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
744 bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDValue Op, SDValue N,
746 unsigned Opcode = Op.getOpcode();
747 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
748 ? cast<LoadSDNode>(Op)->getAddressingMode()
749 : cast<StoreSDNode>(Op)->getAddressingMode();
750 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N)) {
751 int RHSC = (int)RHS->getZExtValue();
752 if (RHSC >= 0 && RHSC < 0x100) { // 8 bits.
753 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
754 ? CurDAG->getTargetConstant(RHSC, MVT::i32)
755 : CurDAG->getTargetConstant(-RHSC, MVT::i32);
763 bool ARMDAGToDAGISel::SelectT2AddrModeImm8s4(SDValue Op, SDValue N,
764 SDValue &Base, SDValue &OffImm) {
765 if (N.getOpcode() == ISD::ADD) {
766 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
767 int RHSC = (int)RHS->getZExtValue();
768 if (((RHSC & 0x3) == 0) &&
769 ((RHSC >= 0 && RHSC < 0x400) || (RHSC < 0 && RHSC > -0x400))) { // 8 bits.
770 Base = N.getOperand(0);
771 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
775 } else if (N.getOpcode() == ISD::SUB) {
776 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
777 int RHSC = (int)RHS->getZExtValue();
778 if (((RHSC & 0x3) == 0) && (RHSC >= 0 && RHSC < 0x400)) { // 8 bits.
779 Base = N.getOperand(0);
780 OffImm = CurDAG->getTargetConstant(-RHSC, MVT::i32);
789 bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue Op, SDValue N,
791 SDValue &OffReg, SDValue &ShImm) {
792 // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.
793 if (N.getOpcode() != ISD::ADD)
796 // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8.
797 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
798 int RHSC = (int)RHS->getZExtValue();
799 if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned)
801 else if (RHSC < 0 && RHSC >= -255) // 8 bits
805 // Look for (R + R) or (R + (R << [1,2,3])).
807 Base = N.getOperand(0);
808 OffReg = N.getOperand(1);
810 // Swap if it is ((R << c) + R).
811 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg);
812 if (ShOpcVal != ARM_AM::lsl) {
813 ShOpcVal = ARM_AM::getShiftOpcForNode(Base);
814 if (ShOpcVal == ARM_AM::lsl)
815 std::swap(Base, OffReg);
818 if (ShOpcVal == ARM_AM::lsl) {
819 // Check to see if the RHS of the shift is a constant, if not, we can't fold
821 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
822 ShAmt = Sh->getZExtValue();
825 ShOpcVal = ARM_AM::no_shift;
827 OffReg = OffReg.getOperand(0);
829 ShOpcVal = ARM_AM::no_shift;
833 ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
838 //===--------------------------------------------------------------------===//
840 /// getAL - Returns a ARMCC::AL immediate node.
841 static inline SDValue getAL(SelectionDAG *CurDAG) {
842 return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
845 SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDValue Op) {
846 LoadSDNode *LD = cast<LoadSDNode>(Op);
847 ISD::MemIndexedMode AM = LD->getAddressingMode();
848 if (AM == ISD::UNINDEXED)
851 EVT LoadedVT = LD->getMemoryVT();
852 SDValue Offset, AMOpc;
853 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
856 if (LoadedVT == MVT::i32 &&
857 SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
858 Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST;
860 } else if (LoadedVT == MVT::i16 &&
861 SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
863 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
864 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
865 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
866 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
867 if (LD->getExtensionType() == ISD::SEXTLOAD) {
868 if (SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
870 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
873 if (SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
875 Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST;
881 SDValue Chain = LD->getChain();
882 SDValue Base = LD->getBasePtr();
883 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
884 CurDAG->getRegister(0, MVT::i32), Chain };
885 return CurDAG->getMachineNode(Opcode, Op.getDebugLoc(), MVT::i32, MVT::i32,
892 SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDValue Op) {
893 LoadSDNode *LD = cast<LoadSDNode>(Op);
894 ISD::MemIndexedMode AM = LD->getAddressingMode();
895 if (AM == ISD::UNINDEXED)
898 EVT LoadedVT = LD->getMemoryVT();
899 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
901 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
904 if (SelectT2AddrModeImm8Offset(Op, LD->getOffset(), Offset)) {
905 switch (LoadedVT.getSimpleVT().SimpleTy) {
907 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
911 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
913 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
918 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
920 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
929 SDValue Chain = LD->getChain();
930 SDValue Base = LD->getBasePtr();
931 SDValue Ops[]= { Base, Offset, getAL(CurDAG),
932 CurDAG->getRegister(0, MVT::i32), Chain };
933 return CurDAG->getMachineNode(Opcode, Op.getDebugLoc(), MVT::i32, MVT::i32,
940 SDNode *ARMDAGToDAGISel::SelectDYN_ALLOC(SDValue Op) {
941 SDNode *N = Op.getNode();
942 DebugLoc dl = N->getDebugLoc();
943 EVT VT = Op.getValueType();
944 SDValue Chain = Op.getOperand(0);
945 SDValue Size = Op.getOperand(1);
946 SDValue Align = Op.getOperand(2);
947 SDValue SP = CurDAG->getRegister(ARM::SP, MVT::i32);
948 int32_t AlignVal = cast<ConstantSDNode>(Align)->getSExtValue();
950 // We need to align the stack. Use Thumb1 tAND which is the only thumb
951 // instruction that can read and write SP. This matches to a pseudo
952 // instruction that has a chain to ensure the result is written back to
953 // the stack pointer.
954 SP = SDValue(CurDAG->getMachineNode(ARM::tANDsp, dl, VT, SP, Align), 0);
956 bool isC = isa<ConstantSDNode>(Size);
957 uint32_t C = isC ? cast<ConstantSDNode>(Size)->getZExtValue() : ~0UL;
958 // Handle the most common case for both Thumb1 and Thumb2:
959 // tSUBspi - immediate is between 0 ... 508 inclusive.
960 if (C <= 508 && ((C & 3) == 0))
961 // FIXME: tSUBspi encode scale 4 implicitly.
962 return CurDAG->SelectNodeTo(N, ARM::tSUBspi_, VT, MVT::Other, SP,
963 CurDAG->getTargetConstant(C/4, MVT::i32),
966 if (Subtarget->isThumb1Only()) {
967 // Use tADDspr since Thumb1 does not have a sub r, sp, r. ARMISelLowering
968 // should have negated the size operand already. FIXME: We can't insert
969 // new target independent node at this stage so we are forced to negate
970 // it earlier. Is there a better solution?
971 return CurDAG->SelectNodeTo(N, ARM::tADDspr_, VT, MVT::Other, SP, Size,
973 } else if (Subtarget->isThumb2()) {
974 if (isC && Predicate_t2_so_imm(Size.getNode())) {
976 SDValue Ops[] = { SP, CurDAG->getTargetConstant(C, MVT::i32), Chain };
977 return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPi_, VT, MVT::Other, Ops, 3);
978 } else if (isC && Predicate_imm0_4095(Size.getNode())) {
980 SDValue Ops[] = { SP, CurDAG->getTargetConstant(C, MVT::i32), Chain };
981 return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPi12_, VT, MVT::Other, Ops, 3);
984 SDValue Ops[] = { SP, Size,
985 getI32Imm(ARM_AM::getSORegOpc(ARM_AM::lsl,0)), Chain };
986 return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPs_, VT, MVT::Other, Ops, 4);
990 // FIXME: Add ADD / SUB sp instructions for ARM.
994 /// PairDRegs - Insert a pair of double registers into an implicit def to
995 /// form a quad register.
996 SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) {
997 DebugLoc dl = V0.getNode()->getDebugLoc();
999 SDValue(CurDAG->getMachineNode(TargetInstrInfo::IMPLICIT_DEF, dl, VT), 0);
1000 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::DSUBREG_0, MVT::i32);
1001 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::DSUBREG_1, MVT::i32);
1002 SDNode *Pair = CurDAG->getMachineNode(TargetInstrInfo::INSERT_SUBREG, dl,
1003 VT, Undef, V0, SubReg0);
1004 return CurDAG->getMachineNode(TargetInstrInfo::INSERT_SUBREG, dl,
1005 VT, SDValue(Pair, 0), V1, SubReg1);
1008 /// GetNEONSubregVT - Given a type for a 128-bit NEON vector, return the type
1009 /// for a 64-bit subregister of the vector.
1010 static EVT GetNEONSubregVT(EVT VT) {
1011 switch (VT.getSimpleVT().SimpleTy) {
1012 default: llvm_unreachable("unhandled NEON type");
1013 case MVT::v16i8: return MVT::v8i8;
1014 case MVT::v8i16: return MVT::v4i16;
1015 case MVT::v4f32: return MVT::v2f32;
1016 case MVT::v4i32: return MVT::v2i32;
1017 case MVT::v2i64: return MVT::v1i64;
1021 SDNode *ARMDAGToDAGISel::SelectVLD(SDValue Op, unsigned NumVecs,
1022 unsigned *DOpcodes, unsigned *QOpcodes0,
1023 unsigned *QOpcodes1) {
1024 assert(NumVecs >=2 && NumVecs <= 4 && "VLD NumVecs out-of-range");
1025 SDNode *N = Op.getNode();
1026 DebugLoc dl = N->getDebugLoc();
1028 SDValue MemAddr, MemUpdate, MemOpc, Align;
1029 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc, Align))
1032 SDValue Chain = N->getOperand(0);
1033 EVT VT = N->getValueType(0);
1034 bool is64BitVector = VT.is64BitVector();
1036 unsigned OpcodeIndex;
1037 switch (VT.getSimpleVT().SimpleTy) {
1038 default: llvm_unreachable("unhandled vld type");
1039 // Double-register operations:
1040 case MVT::v8i8: OpcodeIndex = 0; break;
1041 case MVT::v4i16: OpcodeIndex = 1; break;
1043 case MVT::v2i32: OpcodeIndex = 2; break;
1044 case MVT::v1i64: OpcodeIndex = 3; break;
1045 // Quad-register operations:
1046 case MVT::v16i8: OpcodeIndex = 0; break;
1047 case MVT::v8i16: OpcodeIndex = 1; break;
1049 case MVT::v4i32: OpcodeIndex = 2; break;
1052 if (is64BitVector) {
1053 unsigned Opc = DOpcodes[OpcodeIndex];
1054 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Align, Chain };
1055 std::vector<EVT> ResTys(NumVecs, VT);
1056 ResTys.push_back(MVT::Other);
1057 return CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 5);
1060 EVT RegVT = GetNEONSubregVT(VT);
1062 // Quad registers are directly supported for VLD2,
1063 // loading 2 pairs of D regs.
1064 unsigned Opc = QOpcodes0[OpcodeIndex];
1065 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Align, Chain };
1066 std::vector<EVT> ResTys(4, VT);
1067 ResTys.push_back(MVT::Other);
1068 SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 5);
1069 Chain = SDValue(VLd, 4);
1071 // Combine the even and odd subregs to produce the result.
1072 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1073 SDNode *Q = PairDRegs(VT, SDValue(VLd, 2*Vec), SDValue(VLd, 2*Vec+1));
1074 ReplaceUses(SDValue(N, Vec), SDValue(Q, 0));
1077 // Otherwise, quad registers are loaded with two separate instructions,
1078 // where one loads the even registers and the other loads the odd registers.
1080 // Enable writeback to the address register.
1081 MemOpc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(true), MVT::i32);
1083 std::vector<EVT> ResTys(NumVecs, RegVT);
1084 ResTys.push_back(MemAddr.getValueType());
1085 ResTys.push_back(MVT::Other);
1087 // Load the even subregs.
1088 unsigned Opc = QOpcodes0[OpcodeIndex];
1089 const SDValue OpsA[] = { MemAddr, MemUpdate, MemOpc, Align, Chain };
1090 SDNode *VLdA = CurDAG->getMachineNode(Opc, dl, ResTys, OpsA, 5);
1091 Chain = SDValue(VLdA, NumVecs+1);
1093 // Load the odd subregs.
1094 Opc = QOpcodes1[OpcodeIndex];
1095 const SDValue OpsB[] = { SDValue(VLdA, NumVecs), MemUpdate, MemOpc,
1097 SDNode *VLdB = CurDAG->getMachineNode(Opc, dl, ResTys, OpsB, 5);
1098 Chain = SDValue(VLdB, NumVecs+1);
1100 // Combine the even and odd subregs to produce the result.
1101 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1102 SDNode *Q = PairDRegs(VT, SDValue(VLdA, Vec), SDValue(VLdB, Vec));
1103 ReplaceUses(SDValue(N, Vec), SDValue(Q, 0));
1106 ReplaceUses(SDValue(N, NumVecs), Chain);
1110 SDNode *ARMDAGToDAGISel::SelectVST(SDValue Op, unsigned NumVecs,
1111 unsigned *DOpcodes, unsigned *QOpcodes0,
1112 unsigned *QOpcodes1) {
1113 assert(NumVecs >=2 && NumVecs <= 4 && "VST NumVecs out-of-range");
1114 SDNode *N = Op.getNode();
1115 DebugLoc dl = N->getDebugLoc();
1117 SDValue MemAddr, MemUpdate, MemOpc, Align;
1118 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc, Align))
1121 SDValue Chain = N->getOperand(0);
1122 EVT VT = N->getOperand(3).getValueType();
1123 bool is64BitVector = VT.is64BitVector();
1125 unsigned OpcodeIndex;
1126 switch (VT.getSimpleVT().SimpleTy) {
1127 default: llvm_unreachable("unhandled vst type");
1128 // Double-register operations:
1129 case MVT::v8i8: OpcodeIndex = 0; break;
1130 case MVT::v4i16: OpcodeIndex = 1; break;
1132 case MVT::v2i32: OpcodeIndex = 2; break;
1133 case MVT::v1i64: OpcodeIndex = 3; break;
1134 // Quad-register operations:
1135 case MVT::v16i8: OpcodeIndex = 0; break;
1136 case MVT::v8i16: OpcodeIndex = 1; break;
1138 case MVT::v4i32: OpcodeIndex = 2; break;
1141 SmallVector<SDValue, 8> Ops;
1142 Ops.push_back(MemAddr);
1143 Ops.push_back(MemUpdate);
1144 Ops.push_back(MemOpc);
1145 Ops.push_back(Align);
1147 if (is64BitVector) {
1148 unsigned Opc = DOpcodes[OpcodeIndex];
1149 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1150 Ops.push_back(N->getOperand(Vec+3));
1151 Ops.push_back(Chain);
1152 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), NumVecs+5);
1155 EVT RegVT = GetNEONSubregVT(VT);
1157 // Quad registers are directly supported for VST2,
1158 // storing 2 pairs of D regs.
1159 unsigned Opc = QOpcodes0[OpcodeIndex];
1160 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1161 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
1162 N->getOperand(Vec+3)));
1163 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
1164 N->getOperand(Vec+3)));
1166 Ops.push_back(Chain);
1167 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 9);
1170 // Otherwise, quad registers are stored with two separate instructions,
1171 // where one stores the even registers and the other stores the odd registers.
1173 // Enable writeback to the address register.
1174 MemOpc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(true), MVT::i32);
1176 // Store the even subregs.
1177 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1178 Ops.push_back(CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
1179 N->getOperand(Vec+3)));
1180 Ops.push_back(Chain);
1181 unsigned Opc = QOpcodes0[OpcodeIndex];
1182 SDNode *VStA = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
1183 MVT::Other, Ops.data(), NumVecs+5);
1184 Chain = SDValue(VStA, 1);
1186 // Store the odd subregs.
1187 Ops[0] = SDValue(VStA, 0); // MemAddr
1188 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1189 Ops[Vec+4] = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
1190 N->getOperand(Vec+3));
1191 Ops[NumVecs+4] = Chain;
1192 Opc = QOpcodes1[OpcodeIndex];
1193 SDNode *VStB = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
1194 MVT::Other, Ops.data(), NumVecs+5);
1195 Chain = SDValue(VStB, 1);
1196 ReplaceUses(SDValue(N, 0), Chain);
1200 SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDValue Op, bool IsLoad,
1201 unsigned NumVecs, unsigned *DOpcodes,
1202 unsigned *QOpcodes0,
1203 unsigned *QOpcodes1) {
1204 assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
1205 SDNode *N = Op.getNode();
1206 DebugLoc dl = N->getDebugLoc();
1208 SDValue MemAddr, MemUpdate, MemOpc, Align;
1209 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc, Align))
1212 SDValue Chain = N->getOperand(0);
1214 cast<ConstantSDNode>(N->getOperand(NumVecs+3))->getZExtValue();
1215 EVT VT = IsLoad ? N->getValueType(0) : N->getOperand(3).getValueType();
1216 bool is64BitVector = VT.is64BitVector();
1218 // Quad registers are handled by load/store of subregs. Find the subreg info.
1219 unsigned NumElts = 0;
1222 if (!is64BitVector) {
1223 RegVT = GetNEONSubregVT(VT);
1224 NumElts = RegVT.getVectorNumElements();
1225 SubregIdx = (Lane < NumElts) ? ARM::DSUBREG_0 : ARM::DSUBREG_1;
1228 unsigned OpcodeIndex;
1229 switch (VT.getSimpleVT().SimpleTy) {
1230 default: llvm_unreachable("unhandled vld/vst lane type");
1231 // Double-register operations:
1232 case MVT::v8i8: OpcodeIndex = 0; break;
1233 case MVT::v4i16: OpcodeIndex = 1; break;
1235 case MVT::v2i32: OpcodeIndex = 2; break;
1236 // Quad-register operations:
1237 case MVT::v8i16: OpcodeIndex = 0; break;
1239 case MVT::v4i32: OpcodeIndex = 1; break;
1242 SmallVector<SDValue, 9> Ops;
1243 Ops.push_back(MemAddr);
1244 Ops.push_back(MemUpdate);
1245 Ops.push_back(MemOpc);
1246 Ops.push_back(Align);
1249 if (is64BitVector) {
1250 Opc = DOpcodes[OpcodeIndex];
1251 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1252 Ops.push_back(N->getOperand(Vec+3));
1254 // Check if this is loading the even or odd subreg of a Q register.
1255 if (Lane < NumElts) {
1256 Opc = QOpcodes0[OpcodeIndex];
1259 Opc = QOpcodes1[OpcodeIndex];
1261 // Extract the subregs of the input vector.
1262 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1263 Ops.push_back(CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
1264 N->getOperand(Vec+3)));
1266 Ops.push_back(getI32Imm(Lane));
1267 Ops.push_back(Chain);
1270 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), NumVecs+5);
1272 std::vector<EVT> ResTys(NumVecs, RegVT);
1273 ResTys.push_back(MVT::Other);
1275 CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), NumVecs+5);
1276 // For a 64-bit vector load to D registers, nothing more needs to be done.
1280 // For 128-bit vectors, take the 64-bit results of the load and insert them
1281 // as subregs into the result.
1282 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1283 SDValue QuadVec = CurDAG->getTargetInsertSubreg(SubregIdx, dl, VT,
1284 N->getOperand(Vec+3),
1285 SDValue(VLdLn, Vec));
1286 ReplaceUses(SDValue(N, Vec), QuadVec);
1289 Chain = SDValue(VLdLn, NumVecs);
1290 ReplaceUses(SDValue(N, NumVecs), Chain);
1294 SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDValue Op,
1296 if (!Subtarget->hasV6T2Ops())
1299 unsigned Shl_imm = 0;
1300 if (isOpcWithIntImmediate(Op.getOperand(0).getNode(), ISD::SHL, Shl_imm)){
1301 assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!");
1302 unsigned Srl_imm = 0;
1303 if (isInt32Immediate(Op.getOperand(1), Srl_imm)) {
1304 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
1305 unsigned Width = 32 - Srl_imm;
1306 int LSB = Srl_imm - Shl_imm;
1309 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1310 SDValue Ops[] = { Op.getOperand(0).getOperand(0),
1311 CurDAG->getTargetConstant(LSB, MVT::i32),
1312 CurDAG->getTargetConstant(Width, MVT::i32),
1313 getAL(CurDAG), Reg0 };
1314 return CurDAG->SelectNodeTo(Op.getNode(), Opc, MVT::i32, Ops, 5);
1320 SDNode *ARMDAGToDAGISel::
1321 SelectT2CMOVShiftOp(SDValue Op, SDValue FalseVal, SDValue TrueVal,
1322 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1325 if (SelectT2ShifterOperandReg(Op, TrueVal, CPTmp0, CPTmp1)) {
1326 unsigned SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue();
1327 unsigned SOShOp = ARM_AM::getSORegShOp(SOVal);
1330 case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break;
1331 case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break;
1332 case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break;
1333 case ARM_AM::ror: Opc = ARM::t2MOVCCror; break;
1335 llvm_unreachable("Unknown so_reg opcode!");
1339 CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32);
1340 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1341 SDValue Ops[] = { FalseVal, CPTmp0, SOShImm, CC, CCR, InFlag };
1342 return CurDAG->SelectNodeTo(Op.getNode(), Opc, MVT::i32,Ops, 6);
1347 SDNode *ARMDAGToDAGISel::
1348 SelectARMCMOVShiftOp(SDValue Op, SDValue FalseVal, SDValue TrueVal,
1349 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1353 if (SelectShifterOperandReg(Op, TrueVal, CPTmp0, CPTmp1, CPTmp2)) {
1354 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1355 SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CPTmp2, CC, CCR, InFlag };
1356 return CurDAG->SelectNodeTo(Op.getNode(), ARM::MOVCCs, MVT::i32, Ops, 7);
1361 SDNode *ARMDAGToDAGISel::
1362 SelectT2CMOVSoImmOp(SDValue Op, SDValue FalseVal, SDValue TrueVal,
1363 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1364 ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
1368 if (Predicate_t2_so_imm(TrueVal.getNode())) {
1369 SDValue True = CurDAG->getTargetConstant(T->getZExtValue(), MVT::i32);
1370 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1371 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
1372 return CurDAG->SelectNodeTo(Op.getNode(),
1373 ARM::t2MOVCCi, MVT::i32, Ops, 5);
1378 SDNode *ARMDAGToDAGISel::
1379 SelectARMCMOVSoImmOp(SDValue Op, SDValue FalseVal, SDValue TrueVal,
1380 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1381 ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
1385 if (Predicate_so_imm(TrueVal.getNode())) {
1386 SDValue True = CurDAG->getTargetConstant(T->getZExtValue(), MVT::i32);
1387 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1388 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
1389 return CurDAG->SelectNodeTo(Op.getNode(),
1390 ARM::MOVCCi, MVT::i32, Ops, 5);
1395 SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDValue Op) {
1396 EVT VT = Op.getValueType();
1397 SDValue FalseVal = Op.getOperand(0);
1398 SDValue TrueVal = Op.getOperand(1);
1399 SDValue CC = Op.getOperand(2);
1400 SDValue CCR = Op.getOperand(3);
1401 SDValue InFlag = Op.getOperand(4);
1402 assert(CC.getOpcode() == ISD::Constant);
1403 assert(CCR.getOpcode() == ISD::Register);
1404 ARMCC::CondCodes CCVal =
1405 (ARMCC::CondCodes)cast<ConstantSDNode>(CC)->getZExtValue();
1407 if (!Subtarget->isThumb1Only() && VT == MVT::i32) {
1408 // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1409 // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1410 // Pattern complexity = 18 cost = 1 size = 0
1414 if (Subtarget->isThumb()) {
1415 SDNode *Res = SelectT2CMOVShiftOp(Op, FalseVal, TrueVal,
1416 CCVal, CCR, InFlag);
1418 Res = SelectT2CMOVShiftOp(Op, TrueVal, FalseVal,
1419 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1423 SDNode *Res = SelectARMCMOVShiftOp(Op, FalseVal, TrueVal,
1424 CCVal, CCR, InFlag);
1426 Res = SelectARMCMOVShiftOp(Op, TrueVal, FalseVal,
1427 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1432 // Pattern: (ARMcmov:i32 GPR:i32:$false,
1433 // (imm:i32)<<P:Predicate_so_imm>>:$true,
1435 // Emits: (MOVCCi:i32 GPR:i32:$false,
1436 // (so_imm:i32 (imm:i32):$true), (imm:i32):$cc)
1437 // Pattern complexity = 10 cost = 1 size = 0
1438 if (Subtarget->isThumb()) {
1439 SDNode *Res = SelectT2CMOVSoImmOp(Op, FalseVal, TrueVal,
1440 CCVal, CCR, InFlag);
1442 Res = SelectT2CMOVSoImmOp(Op, TrueVal, FalseVal,
1443 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1447 SDNode *Res = SelectARMCMOVSoImmOp(Op, FalseVal, TrueVal,
1448 CCVal, CCR, InFlag);
1450 Res = SelectARMCMOVSoImmOp(Op, TrueVal, FalseVal,
1451 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1457 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1458 // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1459 // Pattern complexity = 6 cost = 1 size = 0
1461 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1462 // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1463 // Pattern complexity = 6 cost = 11 size = 0
1465 // Also FCPYScc and FCPYDcc.
1466 SDValue Tmp2 = CurDAG->getTargetConstant(CCVal, MVT::i32);
1467 SDValue Ops[] = { FalseVal, TrueVal, Tmp2, CCR, InFlag };
1469 switch (VT.getSimpleVT().SimpleTy) {
1470 default: assert(false && "Illegal conditional move type!");
1473 Opc = Subtarget->isThumb()
1474 ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo)
1484 return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
1487 SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
1488 SDNode *N = Op.getNode();
1489 DebugLoc dl = N->getDebugLoc();
1491 if (N->isMachineOpcode())
1492 return NULL; // Already selected.
1494 switch (N->getOpcode()) {
1496 case ISD::Constant: {
1497 unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
1499 if (Subtarget->hasThumb2())
1500 // Thumb2-aware targets have the MOVT instruction, so all immediates can
1501 // be done with MOV + MOVT, at worst.
1504 if (Subtarget->isThumb()) {
1505 UseCP = (Val > 255 && // MOV
1506 ~Val > 255 && // MOV + MVN
1507 !ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL
1509 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
1510 ARM_AM::getSOImmVal(~Val) == -1 && // MVN
1511 !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs.
1516 CurDAG->getTargetConstantPool(ConstantInt::get(
1517 Type::getInt32Ty(*CurDAG->getContext()), Val),
1518 TLI.getPointerTy());
1521 if (Subtarget->isThumb1Only()) {
1522 SDValue Pred = CurDAG->getTargetConstant(0xEULL, MVT::i32);
1523 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
1524 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
1525 ResNode = CurDAG->getMachineNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other,
1530 CurDAG->getRegister(0, MVT::i32),
1531 CurDAG->getTargetConstant(0, MVT::i32),
1533 CurDAG->getRegister(0, MVT::i32),
1534 CurDAG->getEntryNode()
1536 ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
1539 ReplaceUses(Op, SDValue(ResNode, 0));
1543 // Other cases are autogenerated.
1546 case ISD::FrameIndex: {
1547 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
1548 int FI = cast<FrameIndexSDNode>(N)->getIndex();
1549 SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1550 if (Subtarget->isThumb1Only()) {
1551 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
1552 CurDAG->getTargetConstant(0, MVT::i32));
1554 unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
1555 ARM::t2ADDri : ARM::ADDri);
1556 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
1557 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1558 CurDAG->getRegister(0, MVT::i32) };
1559 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1562 case ARMISD::DYN_ALLOC:
1563 return SelectDYN_ALLOC(Op);
1565 if (SDNode *I = SelectV6T2BitfieldExtractOp(Op,
1566 Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX))
1570 if (SDNode *I = SelectV6T2BitfieldExtractOp(Op,
1571 Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX))
1575 if (Subtarget->isThumb1Only())
1577 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1578 unsigned RHSV = C->getZExtValue();
1580 if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
1581 unsigned ShImm = Log2_32(RHSV-1);
1584 SDValue V = Op.getOperand(0);
1585 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
1586 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
1587 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1588 if (Subtarget->isThumb()) {
1589 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1590 return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
1592 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1593 return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7);
1596 if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
1597 unsigned ShImm = Log2_32(RHSV+1);
1600 SDValue V = Op.getOperand(0);
1601 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
1602 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
1603 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1604 if (Subtarget->isThumb()) {
1605 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0 };
1606 return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 5);
1608 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1609 return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7);
1615 // (and (or x, c2), c1) and top 16-bits of c1 and c2 match, lower 16-bits
1616 // of c1 are 0xffff, and lower 16-bit of c2 are 0. That is, the top 16-bits
1617 // are entirely contributed by c2 and lower 16-bits are entirely contributed
1618 // by x. That's equal to (or (and x, 0xffff), (and c1, 0xffff0000)).
1619 // Select it to: "movt x, ((c1 & 0xffff) >> 16)
1620 EVT VT = Op.getValueType();
1623 unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2())
1625 : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0);
1628 SDValue N0 = Op.getOperand(0), N1 = Op.getOperand(1);
1629 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1632 if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) {
1633 SDValue N2 = N0.getOperand(1);
1634 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1637 unsigned N1CVal = N1C->getZExtValue();
1638 unsigned N2CVal = N2C->getZExtValue();
1639 if ((N1CVal & 0xffff0000U) == (N2CVal & 0xffff0000U) &&
1640 (N1CVal & 0xffffU) == 0xffffU &&
1641 (N2CVal & 0xffffU) == 0x0U) {
1642 SDValue Imm16 = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16,
1644 SDValue Ops[] = { N0.getOperand(0), Imm16,
1645 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
1646 return CurDAG->getMachineNode(Opc, dl, VT, Ops, 4);
1651 case ARMISD::VMOVRRD:
1652 return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32,
1653 Op.getOperand(0), getAL(CurDAG),
1654 CurDAG->getRegister(0, MVT::i32));
1655 case ISD::UMUL_LOHI: {
1656 if (Subtarget->isThumb1Only())
1658 if (Subtarget->isThumb()) {
1659 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
1660 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1661 CurDAG->getRegister(0, MVT::i32) };
1662 return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32, Ops,4);
1664 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
1665 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1666 CurDAG->getRegister(0, MVT::i32) };
1667 return CurDAG->getMachineNode(ARM::UMULL, dl, MVT::i32, MVT::i32, Ops, 5);
1670 case ISD::SMUL_LOHI: {
1671 if (Subtarget->isThumb1Only())
1673 if (Subtarget->isThumb()) {
1674 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
1675 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
1676 return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32, Ops,4);
1678 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
1679 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1680 CurDAG->getRegister(0, MVT::i32) };
1681 return CurDAG->getMachineNode(ARM::SMULL, dl, MVT::i32, MVT::i32, Ops, 5);
1685 SDNode *ResNode = 0;
1686 if (Subtarget->isThumb() && Subtarget->hasThumb2())
1687 ResNode = SelectT2IndexedLoad(Op);
1689 ResNode = SelectARMIndexedLoad(Op);
1692 // Other cases are autogenerated.
1695 case ARMISD::BRCOND: {
1696 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1697 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
1698 // Pattern complexity = 6 cost = 1 size = 0
1700 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1701 // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
1702 // Pattern complexity = 6 cost = 1 size = 0
1704 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1705 // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
1706 // Pattern complexity = 6 cost = 1 size = 0
1708 unsigned Opc = Subtarget->isThumb() ?
1709 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
1710 SDValue Chain = Op.getOperand(0);
1711 SDValue N1 = Op.getOperand(1);
1712 SDValue N2 = Op.getOperand(2);
1713 SDValue N3 = Op.getOperand(3);
1714 SDValue InFlag = Op.getOperand(4);
1715 assert(N1.getOpcode() == ISD::BasicBlock);
1716 assert(N2.getOpcode() == ISD::Constant);
1717 assert(N3.getOpcode() == ISD::Register);
1719 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1720 cast<ConstantSDNode>(N2)->getZExtValue()),
1722 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
1723 SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,
1725 Chain = SDValue(ResNode, 0);
1726 if (Op.getNode()->getNumValues() == 2) {
1727 InFlag = SDValue(ResNode, 1);
1728 ReplaceUses(SDValue(Op.getNode(), 1), InFlag);
1730 ReplaceUses(SDValue(Op.getNode(), 0),
1731 SDValue(Chain.getNode(), Chain.getResNo()));
1735 return SelectCMOVOp(Op);
1736 case ARMISD::CNEG: {
1737 EVT VT = Op.getValueType();
1738 SDValue N0 = Op.getOperand(0);
1739 SDValue N1 = Op.getOperand(1);
1740 SDValue N2 = Op.getOperand(2);
1741 SDValue N3 = Op.getOperand(3);
1742 SDValue InFlag = Op.getOperand(4);
1743 assert(N2.getOpcode() == ISD::Constant);
1744 assert(N3.getOpcode() == ISD::Register);
1746 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1747 cast<ConstantSDNode>(N2)->getZExtValue()),
1749 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
1751 switch (VT.getSimpleVT().SimpleTy) {
1752 default: assert(false && "Illegal conditional move type!");
1761 return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
1764 case ARMISD::VZIP: {
1766 EVT VT = N->getValueType(0);
1767 switch (VT.getSimpleVT().SimpleTy) {
1768 default: return NULL;
1769 case MVT::v8i8: Opc = ARM::VZIPd8; break;
1770 case MVT::v4i16: Opc = ARM::VZIPd16; break;
1772 case MVT::v2i32: Opc = ARM::VZIPd32; break;
1773 case MVT::v16i8: Opc = ARM::VZIPq8; break;
1774 case MVT::v8i16: Opc = ARM::VZIPq16; break;
1776 case MVT::v4i32: Opc = ARM::VZIPq32; break;
1778 return CurDAG->getMachineNode(Opc, dl, VT, VT,
1779 N->getOperand(0), N->getOperand(1));
1781 case ARMISD::VUZP: {
1783 EVT VT = N->getValueType(0);
1784 switch (VT.getSimpleVT().SimpleTy) {
1785 default: return NULL;
1786 case MVT::v8i8: Opc = ARM::VUZPd8; break;
1787 case MVT::v4i16: Opc = ARM::VUZPd16; break;
1789 case MVT::v2i32: Opc = ARM::VUZPd32; break;
1790 case MVT::v16i8: Opc = ARM::VUZPq8; break;
1791 case MVT::v8i16: Opc = ARM::VUZPq16; break;
1793 case MVT::v4i32: Opc = ARM::VUZPq32; break;
1795 return CurDAG->getMachineNode(Opc, dl, VT, VT,
1796 N->getOperand(0), N->getOperand(1));
1798 case ARMISD::VTRN: {
1800 EVT VT = N->getValueType(0);
1801 switch (VT.getSimpleVT().SimpleTy) {
1802 default: return NULL;
1803 case MVT::v8i8: Opc = ARM::VTRNd8; break;
1804 case MVT::v4i16: Opc = ARM::VTRNd16; break;
1806 case MVT::v2i32: Opc = ARM::VTRNd32; break;
1807 case MVT::v16i8: Opc = ARM::VTRNq8; break;
1808 case MVT::v8i16: Opc = ARM::VTRNq16; break;
1810 case MVT::v4i32: Opc = ARM::VTRNq32; break;
1812 return CurDAG->getMachineNode(Opc, dl, VT, VT,
1813 N->getOperand(0), N->getOperand(1));
1816 case ISD::INTRINSIC_VOID:
1817 case ISD::INTRINSIC_W_CHAIN: {
1818 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
1823 case Intrinsic::arm_neon_vld2: {
1824 unsigned DOpcodes[] = { ARM::VLD2d8, ARM::VLD2d16,
1825 ARM::VLD2d32, ARM::VLD2d64 };
1826 unsigned QOpcodes[] = { ARM::VLD2q8, ARM::VLD2q16, ARM::VLD2q32 };
1827 return SelectVLD(Op, 2, DOpcodes, QOpcodes, 0);
1830 case Intrinsic::arm_neon_vld3: {
1831 unsigned DOpcodes[] = { ARM::VLD3d8, ARM::VLD3d16,
1832 ARM::VLD3d32, ARM::VLD3d64 };
1833 unsigned QOpcodes0[] = { ARM::VLD3q8a, ARM::VLD3q16a, ARM::VLD3q32a };
1834 unsigned QOpcodes1[] = { ARM::VLD3q8b, ARM::VLD3q16b, ARM::VLD3q32b };
1835 return SelectVLD(Op, 3, DOpcodes, QOpcodes0, QOpcodes1);
1838 case Intrinsic::arm_neon_vld4: {
1839 unsigned DOpcodes[] = { ARM::VLD4d8, ARM::VLD4d16,
1840 ARM::VLD4d32, ARM::VLD4d64 };
1841 unsigned QOpcodes0[] = { ARM::VLD4q8a, ARM::VLD4q16a, ARM::VLD4q32a };
1842 unsigned QOpcodes1[] = { ARM::VLD4q8b, ARM::VLD4q16b, ARM::VLD4q32b };
1843 return SelectVLD(Op, 4, DOpcodes, QOpcodes0, QOpcodes1);
1846 case Intrinsic::arm_neon_vld2lane: {
1847 unsigned DOpcodes[] = { ARM::VLD2LNd8, ARM::VLD2LNd16, ARM::VLD2LNd32 };
1848 unsigned QOpcodes0[] = { ARM::VLD2LNq16a, ARM::VLD2LNq32a };
1849 unsigned QOpcodes1[] = { ARM::VLD2LNq16b, ARM::VLD2LNq32b };
1850 return SelectVLDSTLane(Op, true, 2, DOpcodes, QOpcodes0, QOpcodes1);
1853 case Intrinsic::arm_neon_vld3lane: {
1854 unsigned DOpcodes[] = { ARM::VLD3LNd8, ARM::VLD3LNd16, ARM::VLD3LNd32 };
1855 unsigned QOpcodes0[] = { ARM::VLD3LNq16a, ARM::VLD3LNq32a };
1856 unsigned QOpcodes1[] = { ARM::VLD3LNq16b, ARM::VLD3LNq32b };
1857 return SelectVLDSTLane(Op, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
1860 case Intrinsic::arm_neon_vld4lane: {
1861 unsigned DOpcodes[] = { ARM::VLD4LNd8, ARM::VLD4LNd16, ARM::VLD4LNd32 };
1862 unsigned QOpcodes0[] = { ARM::VLD4LNq16a, ARM::VLD4LNq32a };
1863 unsigned QOpcodes1[] = { ARM::VLD4LNq16b, ARM::VLD4LNq32b };
1864 return SelectVLDSTLane(Op, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
1867 case Intrinsic::arm_neon_vst2: {
1868 unsigned DOpcodes[] = { ARM::VST2d8, ARM::VST2d16,
1869 ARM::VST2d32, ARM::VST2d64 };
1870 unsigned QOpcodes[] = { ARM::VST2q8, ARM::VST2q16, ARM::VST2q32 };
1871 return SelectVST(Op, 2, DOpcodes, QOpcodes, 0);
1874 case Intrinsic::arm_neon_vst3: {
1875 unsigned DOpcodes[] = { ARM::VST3d8, ARM::VST3d16,
1876 ARM::VST3d32, ARM::VST3d64 };
1877 unsigned QOpcodes0[] = { ARM::VST3q8a, ARM::VST3q16a, ARM::VST3q32a };
1878 unsigned QOpcodes1[] = { ARM::VST3q8b, ARM::VST3q16b, ARM::VST3q32b };
1879 return SelectVST(Op, 3, DOpcodes, QOpcodes0, QOpcodes1);
1882 case Intrinsic::arm_neon_vst4: {
1883 unsigned DOpcodes[] = { ARM::VST4d8, ARM::VST4d16,
1884 ARM::VST4d32, ARM::VST4d64 };
1885 unsigned QOpcodes0[] = { ARM::VST4q8a, ARM::VST4q16a, ARM::VST4q32a };
1886 unsigned QOpcodes1[] = { ARM::VST4q8b, ARM::VST4q16b, ARM::VST4q32b };
1887 return SelectVST(Op, 4, DOpcodes, QOpcodes0, QOpcodes1);
1890 case Intrinsic::arm_neon_vst2lane: {
1891 unsigned DOpcodes[] = { ARM::VST2LNd8, ARM::VST2LNd16, ARM::VST2LNd32 };
1892 unsigned QOpcodes0[] = { ARM::VST2LNq16a, ARM::VST2LNq32a };
1893 unsigned QOpcodes1[] = { ARM::VST2LNq16b, ARM::VST2LNq32b };
1894 return SelectVLDSTLane(Op, false, 2, DOpcodes, QOpcodes0, QOpcodes1);
1897 case Intrinsic::arm_neon_vst3lane: {
1898 unsigned DOpcodes[] = { ARM::VST3LNd8, ARM::VST3LNd16, ARM::VST3LNd32 };
1899 unsigned QOpcodes0[] = { ARM::VST3LNq16a, ARM::VST3LNq32a };
1900 unsigned QOpcodes1[] = { ARM::VST3LNq16b, ARM::VST3LNq32b };
1901 return SelectVLDSTLane(Op, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
1904 case Intrinsic::arm_neon_vst4lane: {
1905 unsigned DOpcodes[] = { ARM::VST4LNd8, ARM::VST4LNd16, ARM::VST4LNd32 };
1906 unsigned QOpcodes0[] = { ARM::VST4LNq16a, ARM::VST4LNq32a };
1907 unsigned QOpcodes1[] = { ARM::VST4LNq16b, ARM::VST4LNq32b };
1908 return SelectVLDSTLane(Op, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
1914 return SelectCode(Op);
1917 bool ARMDAGToDAGISel::
1918 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
1919 std::vector<SDValue> &OutOps) {
1920 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
1921 // Require the address to be in a register. That is safe for all ARM
1922 // variants and it is hard to do anything much smarter without knowing
1923 // how the operand is used.
1924 OutOps.push_back(Op);
1928 /// createARMISelDag - This pass converts a legalized DAG into a
1929 /// ARM-specific DAG, ready for instruction scheduling.
1931 FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
1932 CodeGenOpt::Level OptLevel) {
1933 return new ARMDAGToDAGISel(TM, OptLevel);