1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "arm-isel"
16 #include "ARMAddressingModes.h"
17 #include "ARMTargetMachine.h"
18 #include "llvm/CallingConv.h"
19 #include "llvm/Constants.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/LLVMContext.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CodeGen/SelectionDAGISel.h"
29 #include "llvm/Target/TargetLowering.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Compiler.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
40 DisableShifterOp("disable-shifter-op", cl::Hidden,
41 cl::desc("Disable isel of shifter-op"),
44 //===--------------------------------------------------------------------===//
45 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
46 /// instructions for SelectionDAG operations.
51 AM2_BASE, // Simple AM2 (+-imm12)
52 AM2_SHOP // Shifter-op AM2
55 class ARMDAGToDAGISel : public SelectionDAGISel {
56 ARMBaseTargetMachine &TM;
58 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
59 /// make the right decision when generating code for different targets.
60 const ARMSubtarget *Subtarget;
63 explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm,
64 CodeGenOpt::Level OptLevel)
65 : SelectionDAGISel(tm, OptLevel), TM(tm),
66 Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
69 virtual const char *getPassName() const {
70 return "ARM Instruction Selection";
73 /// getI32Imm - Return a target constant of type i32 with the specified
75 inline SDValue getI32Imm(unsigned Imm) {
76 return CurDAG->getTargetConstant(Imm, MVT::i32);
79 SDNode *Select(SDNode *N);
81 bool isShifterOpProfitable(const SDValue &Shift,
82 ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
83 bool SelectShifterOperandReg(SDValue N, SDValue &A,
84 SDValue &B, SDValue &C);
85 bool SelectShiftShifterOperandReg(SDValue N, SDValue &A,
86 SDValue &B, SDValue &C);
87 bool SelectAddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
88 bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc);
90 AddrMode2Type SelectAddrMode2Worker(SDValue N, SDValue &Base,
91 SDValue &Offset, SDValue &Opc);
92 bool SelectAddrMode2Base(SDValue N, SDValue &Base, SDValue &Offset,
94 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_BASE;
97 bool SelectAddrMode2ShOp(SDValue N, SDValue &Base, SDValue &Offset,
99 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_SHOP;
102 bool SelectAddrMode2(SDValue N, SDValue &Base, SDValue &Offset,
104 SelectAddrMode2Worker(N, Base, Offset, Opc);
105 // return SelectAddrMode2ShOp(N, Base, Offset, Opc);
106 // This always matches one way or another.
110 bool SelectAddrMode2Offset(SDNode *Op, SDValue N,
111 SDValue &Offset, SDValue &Opc);
112 bool SelectAddrMode3(SDValue N, SDValue &Base,
113 SDValue &Offset, SDValue &Opc);
114 bool SelectAddrMode3Offset(SDNode *Op, SDValue N,
115 SDValue &Offset, SDValue &Opc);
116 bool SelectAddrMode5(SDValue N, SDValue &Base,
118 bool SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,SDValue &Align);
120 bool SelectAddrModePC(SDValue N, SDValue &Offset,
123 bool SelectThumbAddrModeRR(SDValue N, SDValue &Base, SDValue &Offset);
124 bool SelectThumbAddrModeRI5(SDValue N, unsigned Scale,
125 SDValue &Base, SDValue &OffImm,
127 bool SelectThumbAddrModeS1(SDValue N, SDValue &Base,
128 SDValue &OffImm, SDValue &Offset);
129 bool SelectThumbAddrModeS2(SDValue N, SDValue &Base,
130 SDValue &OffImm, SDValue &Offset);
131 bool SelectThumbAddrModeS4(SDValue N, SDValue &Base,
132 SDValue &OffImm, SDValue &Offset);
133 bool SelectThumbAddrModeSP(SDValue N, SDValue &Base, SDValue &OffImm);
135 bool SelectT2ShifterOperandReg(SDValue N,
136 SDValue &BaseReg, SDValue &Opc);
137 bool SelectT2AddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
138 bool SelectT2AddrModeImm8(SDValue N, SDValue &Base,
140 bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
142 bool SelectT2AddrModeSoReg(SDValue N, SDValue &Base,
143 SDValue &OffReg, SDValue &ShImm);
145 inline bool is_so_imm(unsigned Imm) const {
146 return ARM_AM::getSOImmVal(Imm) != -1;
149 inline bool is_so_imm_not(unsigned Imm) const {
150 return ARM_AM::getSOImmVal(~Imm) != -1;
153 inline bool is_t2_so_imm(unsigned Imm) const {
154 return ARM_AM::getT2SOImmVal(Imm) != -1;
157 inline bool is_t2_so_imm_not(unsigned Imm) const {
158 return ARM_AM::getT2SOImmVal(~Imm) != -1;
161 inline bool Pred_so_imm(SDNode *inN) const {
162 ConstantSDNode *N = cast<ConstantSDNode>(inN);
163 return is_so_imm(N->getZExtValue());
166 inline bool Pred_t2_so_imm(SDNode *inN) const {
167 ConstantSDNode *N = cast<ConstantSDNode>(inN);
168 return is_t2_so_imm(N->getZExtValue());
171 // Include the pieces autogenerated from the target description.
172 #include "ARMGenDAGISel.inc"
175 /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
177 SDNode *SelectARMIndexedLoad(SDNode *N);
178 SDNode *SelectT2IndexedLoad(SDNode *N);
180 /// SelectVLD - Select NEON load intrinsics. NumVecs should be
181 /// 1, 2, 3 or 4. The opcode arrays specify the instructions used for
182 /// loads of D registers and even subregs and odd subregs of Q registers.
183 /// For NumVecs <= 2, QOpcodes1 is not used.
184 SDNode *SelectVLD(SDNode *N, unsigned NumVecs, unsigned *DOpcodes,
185 unsigned *QOpcodes0, unsigned *QOpcodes1);
187 /// SelectVST - Select NEON store intrinsics. NumVecs should
188 /// be 1, 2, 3 or 4. The opcode arrays specify the instructions used for
189 /// stores of D registers and even subregs and odd subregs of Q registers.
190 /// For NumVecs <= 2, QOpcodes1 is not used.
191 SDNode *SelectVST(SDNode *N, unsigned NumVecs, unsigned *DOpcodes,
192 unsigned *QOpcodes0, unsigned *QOpcodes1);
194 /// SelectVLDSTLane - Select NEON load/store lane intrinsics. NumVecs should
195 /// be 2, 3 or 4. The opcode arrays specify the instructions used for
196 /// load/store of D registers and Q registers.
197 SDNode *SelectVLDSTLane(SDNode *N, bool IsLoad, unsigned NumVecs,
198 unsigned *DOpcodes, unsigned *QOpcodes);
200 /// SelectVLDDup - Select NEON load-duplicate intrinsics. NumVecs
201 /// should be 2, 3 or 4. The opcode array specifies the instructions used
202 /// for loading D registers. (Q registers are not supported.)
203 SDNode *SelectVLDDup(SDNode *N, unsigned NumVecs, unsigned *Opcodes);
205 /// SelectVTBL - Select NEON VTBL and VTBX intrinsics. NumVecs should be 2,
206 /// 3 or 4. These are custom-selected so that a REG_SEQUENCE can be
207 /// generated to force the table registers to be consecutive.
208 SDNode *SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc);
210 /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM.
211 SDNode *SelectV6T2BitfieldExtractOp(SDNode *N, bool isSigned);
213 /// SelectCMOVOp - Select CMOV instructions for ARM.
214 SDNode *SelectCMOVOp(SDNode *N);
215 SDNode *SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
216 ARMCC::CondCodes CCVal, SDValue CCR,
218 SDNode *SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
219 ARMCC::CondCodes CCVal, SDValue CCR,
221 SDNode *SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
222 ARMCC::CondCodes CCVal, SDValue CCR,
224 SDNode *SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
225 ARMCC::CondCodes CCVal, SDValue CCR,
228 SDNode *SelectConcatVector(SDNode *N);
230 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
231 /// inline asm expressions.
232 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
234 std::vector<SDValue> &OutOps);
236 // Form pairs of consecutive S, D, or Q registers.
237 SDNode *PairSRegs(EVT VT, SDValue V0, SDValue V1);
238 SDNode *PairDRegs(EVT VT, SDValue V0, SDValue V1);
239 SDNode *PairQRegs(EVT VT, SDValue V0, SDValue V1);
241 // Form sequences of 4 consecutive S, D, or Q registers.
242 SDNode *QuadSRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
243 SDNode *QuadDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
244 SDNode *QuadQRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
246 // Get the alignment operand for a NEON VLD or VST instruction.
247 SDValue GetVLDSTAlign(SDValue Align, unsigned NumVecs, bool is64BitVector);
251 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
252 /// operand. If so Imm will receive the 32-bit value.
253 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
254 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
255 Imm = cast<ConstantSDNode>(N)->getZExtValue();
261 // isInt32Immediate - This method tests to see if a constant operand.
262 // If so Imm will receive the 32 bit value.
263 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
264 return isInt32Immediate(N.getNode(), Imm);
267 // isOpcWithIntImmediate - This method tests to see if the node is a specific
268 // opcode and that it has a immediate integer right operand.
269 // If so Imm will receive the 32 bit value.
270 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
271 return N->getOpcode() == Opc &&
272 isInt32Immediate(N->getOperand(1).getNode(), Imm);
276 bool ARMDAGToDAGISel::isShifterOpProfitable(const SDValue &Shift,
277 ARM_AM::ShiftOpc ShOpcVal,
279 if (!Subtarget->isCortexA9())
281 if (Shift.hasOneUse())
284 return ShOpcVal == ARM_AM::lsl && ShAmt == 2;
287 bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue N,
291 if (DisableShifterOp)
294 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
296 // Don't match base register only case. That is matched to a separate
297 // lower complexity pattern with explicit register operand.
298 if (ShOpcVal == ARM_AM::no_shift) return false;
300 BaseReg = N.getOperand(0);
301 unsigned ShImmVal = 0;
302 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
303 ShReg = CurDAG->getRegister(0, MVT::i32);
304 ShImmVal = RHS->getZExtValue() & 31;
306 ShReg = N.getOperand(1);
307 if (!isShifterOpProfitable(N, ShOpcVal, ShImmVal))
310 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
315 bool ARMDAGToDAGISel::SelectShiftShifterOperandReg(SDValue N,
319 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
321 // Don't match base register only case. That is matched to a separate
322 // lower complexity pattern with explicit register operand.
323 if (ShOpcVal == ARM_AM::no_shift) return false;
325 BaseReg = N.getOperand(0);
326 unsigned ShImmVal = 0;
327 // Do not check isShifterOpProfitable. This must return true.
328 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
329 ShReg = CurDAG->getRegister(0, MVT::i32);
330 ShImmVal = RHS->getZExtValue() & 31;
332 ShReg = N.getOperand(1);
334 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
339 bool ARMDAGToDAGISel::SelectAddrModeImm12(SDValue N,
342 // Match simple R + imm12 operands.
345 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
346 if (N.getOpcode() == ISD::FrameIndex) {
347 // Match frame index...
348 int FI = cast<FrameIndexSDNode>(N)->getIndex();
349 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
350 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
352 } else if (N.getOpcode() == ARMISD::Wrapper &&
353 !(Subtarget->useMovt() &&
354 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
355 Base = N.getOperand(0);
358 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
362 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
363 int RHSC = (int)RHS->getZExtValue();
364 if (N.getOpcode() == ISD::SUB)
367 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
368 Base = N.getOperand(0);
369 if (Base.getOpcode() == ISD::FrameIndex) {
370 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
371 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
373 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
380 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
386 bool ARMDAGToDAGISel::SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset,
388 if (N.getOpcode() == ISD::MUL &&
389 (!Subtarget->isCortexA9() || N.hasOneUse())) {
390 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
391 // X * [3,5,9] -> X + X * [2,4,8] etc.
392 int RHSC = (int)RHS->getZExtValue();
395 ARM_AM::AddrOpc AddSub = ARM_AM::add;
397 AddSub = ARM_AM::sub;
400 if (isPowerOf2_32(RHSC)) {
401 unsigned ShAmt = Log2_32(RHSC);
402 Base = Offset = N.getOperand(0);
403 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
412 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB)
415 // Leave simple R +/- imm12 operands for LDRi12
416 if (N.getOpcode() == ISD::ADD) {
417 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
418 int RHSC = (int)RHS->getZExtValue();
419 if ((RHSC >= 0 && RHSC < 0x1000) ||
420 (RHSC < 0 && RHSC > -0x1000)) // 12 bits.
425 if (Subtarget->isCortexA9() && !N.hasOneUse())
426 // Compute R +/- (R << N) and reuse it.
429 // Otherwise this is R +/- [possibly shifted] R.
430 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
431 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
434 Base = N.getOperand(0);
435 Offset = N.getOperand(1);
437 if (ShOpcVal != ARM_AM::no_shift) {
438 // Check to see if the RHS of the shift is a constant, if not, we can't fold
440 if (ConstantSDNode *Sh =
441 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
442 ShAmt = Sh->getZExtValue();
443 if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
444 Offset = N.getOperand(1).getOperand(0);
447 ShOpcVal = ARM_AM::no_shift;
450 ShOpcVal = ARM_AM::no_shift;
454 // Try matching (R shl C) + (R).
455 if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift &&
456 !(Subtarget->isCortexA9() || N.getOperand(0).hasOneUse())) {
457 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
458 if (ShOpcVal != ARM_AM::no_shift) {
459 // Check to see if the RHS of the shift is a constant, if not, we can't
461 if (ConstantSDNode *Sh =
462 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
463 ShAmt = Sh->getZExtValue();
464 if (!Subtarget->isCortexA9() ||
466 isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt))) {
467 Offset = N.getOperand(0).getOperand(0);
468 Base = N.getOperand(1);
471 ShOpcVal = ARM_AM::no_shift;
474 ShOpcVal = ARM_AM::no_shift;
479 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
489 AddrMode2Type ARMDAGToDAGISel::SelectAddrMode2Worker(SDValue N,
493 if (N.getOpcode() == ISD::MUL &&
494 (!Subtarget->isCortexA9() || N.hasOneUse())) {
495 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
496 // X * [3,5,9] -> X + X * [2,4,8] etc.
497 int RHSC = (int)RHS->getZExtValue();
500 ARM_AM::AddrOpc AddSub = ARM_AM::add;
502 AddSub = ARM_AM::sub;
505 if (isPowerOf2_32(RHSC)) {
506 unsigned ShAmt = Log2_32(RHSC);
507 Base = Offset = N.getOperand(0);
508 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
517 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
519 if (N.getOpcode() == ISD::FrameIndex) {
520 int FI = cast<FrameIndexSDNode>(N)->getIndex();
521 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
522 } else if (N.getOpcode() == ARMISD::Wrapper &&
523 !(Subtarget->useMovt() &&
524 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
525 Base = N.getOperand(0);
527 Offset = CurDAG->getRegister(0, MVT::i32);
528 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
534 // Match simple R +/- imm12 operands.
535 if (N.getOpcode() == ISD::ADD) {
536 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
537 int RHSC = (int)RHS->getZExtValue();
538 if ((RHSC >= 0 && RHSC < 0x1000) ||
539 (RHSC < 0 && RHSC > -0x1000)) { // 12 bits.
540 Base = N.getOperand(0);
541 if (Base.getOpcode() == ISD::FrameIndex) {
542 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
543 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
545 Offset = CurDAG->getRegister(0, MVT::i32);
547 ARM_AM::AddrOpc AddSub = ARM_AM::add;
549 AddSub = ARM_AM::sub;
552 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
560 if (Subtarget->isCortexA9() && !N.hasOneUse()) {
561 // Compute R +/- (R << N) and reuse it.
563 Offset = CurDAG->getRegister(0, MVT::i32);
564 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
570 // Otherwise this is R +/- [possibly shifted] R.
571 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
572 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
575 Base = N.getOperand(0);
576 Offset = N.getOperand(1);
578 if (ShOpcVal != ARM_AM::no_shift) {
579 // Check to see if the RHS of the shift is a constant, if not, we can't fold
581 if (ConstantSDNode *Sh =
582 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
583 ShAmt = Sh->getZExtValue();
584 if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
585 Offset = N.getOperand(1).getOperand(0);
588 ShOpcVal = ARM_AM::no_shift;
591 ShOpcVal = ARM_AM::no_shift;
595 // Try matching (R shl C) + (R).
596 if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift &&
597 !(Subtarget->isCortexA9() || N.getOperand(0).hasOneUse())) {
598 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
599 if (ShOpcVal != ARM_AM::no_shift) {
600 // Check to see if the RHS of the shift is a constant, if not, we can't
602 if (ConstantSDNode *Sh =
603 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
604 ShAmt = Sh->getZExtValue();
605 if (!Subtarget->isCortexA9() ||
607 isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt))) {
608 Offset = N.getOperand(0).getOperand(0);
609 Base = N.getOperand(1);
612 ShOpcVal = ARM_AM::no_shift;
615 ShOpcVal = ARM_AM::no_shift;
620 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
625 bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDNode *Op, SDValue N,
626 SDValue &Offset, SDValue &Opc) {
627 unsigned Opcode = Op->getOpcode();
628 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
629 ? cast<LoadSDNode>(Op)->getAddressingMode()
630 : cast<StoreSDNode>(Op)->getAddressingMode();
631 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
632 ? ARM_AM::add : ARM_AM::sub;
633 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
634 int Val = (int)C->getZExtValue();
635 if (Val >= 0 && Val < 0x1000) { // 12 bits.
636 Offset = CurDAG->getRegister(0, MVT::i32);
637 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
645 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
647 if (ShOpcVal != ARM_AM::no_shift) {
648 // Check to see if the RHS of the shift is a constant, if not, we can't fold
650 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
651 ShAmt = Sh->getZExtValue();
652 if (isShifterOpProfitable(N, ShOpcVal, ShAmt))
653 Offset = N.getOperand(0);
656 ShOpcVal = ARM_AM::no_shift;
659 ShOpcVal = ARM_AM::no_shift;
663 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
669 bool ARMDAGToDAGISel::SelectAddrMode3(SDValue N,
670 SDValue &Base, SDValue &Offset,
672 if (N.getOpcode() == ISD::SUB) {
673 // X - C is canonicalize to X + -C, no need to handle it here.
674 Base = N.getOperand(0);
675 Offset = N.getOperand(1);
676 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
680 if (N.getOpcode() != ISD::ADD) {
682 if (N.getOpcode() == ISD::FrameIndex) {
683 int FI = cast<FrameIndexSDNode>(N)->getIndex();
684 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
686 Offset = CurDAG->getRegister(0, MVT::i32);
687 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
691 // If the RHS is +/- imm8, fold into addr mode.
692 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
693 int RHSC = (int)RHS->getZExtValue();
694 if ((RHSC >= 0 && RHSC < 256) ||
695 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
696 Base = N.getOperand(0);
697 if (Base.getOpcode() == ISD::FrameIndex) {
698 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
699 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
701 Offset = CurDAG->getRegister(0, MVT::i32);
703 ARM_AM::AddrOpc AddSub = ARM_AM::add;
705 AddSub = ARM_AM::sub;
708 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
713 Base = N.getOperand(0);
714 Offset = N.getOperand(1);
715 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
719 bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N,
720 SDValue &Offset, SDValue &Opc) {
721 unsigned Opcode = Op->getOpcode();
722 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
723 ? cast<LoadSDNode>(Op)->getAddressingMode()
724 : cast<StoreSDNode>(Op)->getAddressingMode();
725 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
726 ? ARM_AM::add : ARM_AM::sub;
727 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
728 int Val = (int)C->getZExtValue();
729 if (Val >= 0 && Val < 256) {
730 Offset = CurDAG->getRegister(0, MVT::i32);
731 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
737 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
741 bool ARMDAGToDAGISel::SelectAddrMode5(SDValue N,
742 SDValue &Base, SDValue &Offset) {
743 if (N.getOpcode() != ISD::ADD) {
745 if (N.getOpcode() == ISD::FrameIndex) {
746 int FI = cast<FrameIndexSDNode>(N)->getIndex();
747 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
748 } else if (N.getOpcode() == ARMISD::Wrapper &&
749 !(Subtarget->useMovt() &&
750 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
751 Base = N.getOperand(0);
753 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
758 // If the RHS is +/- imm8, fold into addr mode.
759 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
760 int RHSC = (int)RHS->getZExtValue();
761 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied by 4.
763 if ((RHSC >= 0 && RHSC < 256) ||
764 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
765 Base = N.getOperand(0);
766 if (Base.getOpcode() == ISD::FrameIndex) {
767 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
768 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
771 ARM_AM::AddrOpc AddSub = ARM_AM::add;
773 AddSub = ARM_AM::sub;
776 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
784 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
789 bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,
793 unsigned Alignment = 0;
794 if (LSBaseSDNode *LSN = dyn_cast<LSBaseSDNode>(Parent)) {
795 // This case occurs only for VLD1-lane/dup and VST1-lane instructions.
796 // The maximum alignment is equal to the memory size being referenced.
797 unsigned LSNAlign = LSN->getAlignment();
798 unsigned MemSize = LSN->getMemoryVT().getSizeInBits() / 8;
799 if (LSNAlign > MemSize && MemSize > 1)
802 // All other uses of addrmode6 are for intrinsics. For now just record
803 // the raw alignment value; it will be refined later based on the legal
804 // alignment operands for the intrinsic.
805 Alignment = cast<MemIntrinsicSDNode>(Parent)->getAlignment();
808 Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
812 bool ARMDAGToDAGISel::SelectAddrModePC(SDValue N,
813 SDValue &Offset, SDValue &Label) {
814 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
815 Offset = N.getOperand(0);
816 SDValue N1 = N.getOperand(1);
817 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
824 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue N,
825 SDValue &Base, SDValue &Offset){
826 // FIXME dl should come from the parent load or store, not the address
827 if (N.getOpcode() != ISD::ADD) {
828 ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
829 if (!NC || !NC->isNullValue())
836 Base = N.getOperand(0);
837 Offset = N.getOperand(1);
842 ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDValue N,
843 unsigned Scale, SDValue &Base,
844 SDValue &OffImm, SDValue &Offset) {
846 SDValue TmpBase, TmpOffImm;
847 if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
848 return false; // We want to select tLDRspi / tSTRspi instead.
849 if (N.getOpcode() == ARMISD::Wrapper &&
850 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
851 return false; // We want to select tLDRpci instead.
854 if (N.getOpcode() != ISD::ADD) {
855 if (N.getOpcode() == ARMISD::Wrapper &&
856 !(Subtarget->useMovt() &&
857 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
858 Base = N.getOperand(0);
862 Offset = CurDAG->getRegister(0, MVT::i32);
863 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
867 // Thumb does not have [sp, r] address mode.
868 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
869 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
870 if ((LHSR && LHSR->getReg() == ARM::SP) ||
871 (RHSR && RHSR->getReg() == ARM::SP)) {
873 Offset = CurDAG->getRegister(0, MVT::i32);
874 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
878 // If the RHS is + imm5 * scale, fold into addr mode.
879 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
880 int RHSC = (int)RHS->getZExtValue();
881 if ((RHSC & (Scale-1)) == 0) { // The constant is implicitly multiplied.
883 if (RHSC >= 0 && RHSC < 32) {
884 Base = N.getOperand(0);
885 Offset = CurDAG->getRegister(0, MVT::i32);
886 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
892 Base = N.getOperand(0);
893 Offset = N.getOperand(1);
894 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
898 bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDValue N,
899 SDValue &Base, SDValue &OffImm,
901 return SelectThumbAddrModeRI5(N, 1, Base, OffImm, Offset);
904 bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDValue N,
905 SDValue &Base, SDValue &OffImm,
907 return SelectThumbAddrModeRI5(N, 2, Base, OffImm, Offset);
910 bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDValue N,
911 SDValue &Base, SDValue &OffImm,
913 return SelectThumbAddrModeRI5(N, 4, Base, OffImm, Offset);
916 bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue N,
917 SDValue &Base, SDValue &OffImm) {
918 if (N.getOpcode() == ISD::FrameIndex) {
919 int FI = cast<FrameIndexSDNode>(N)->getIndex();
920 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
921 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
925 if (N.getOpcode() != ISD::ADD)
928 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
929 if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
930 (LHSR && LHSR->getReg() == ARM::SP)) {
931 // If the RHS is + imm8 * scale, fold into addr mode.
932 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
933 int RHSC = (int)RHS->getZExtValue();
934 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied.
936 if (RHSC >= 0 && RHSC < 256) {
937 Base = N.getOperand(0);
938 if (Base.getOpcode() == ISD::FrameIndex) {
939 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
940 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
942 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
952 bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue N, SDValue &BaseReg,
954 if (DisableShifterOp)
957 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
959 // Don't match base register only case. That is matched to a separate
960 // lower complexity pattern with explicit register operand.
961 if (ShOpcVal == ARM_AM::no_shift) return false;
963 BaseReg = N.getOperand(0);
964 unsigned ShImmVal = 0;
965 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
966 ShImmVal = RHS->getZExtValue() & 31;
967 Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
974 bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue N,
975 SDValue &Base, SDValue &OffImm) {
976 // Match simple R + imm12 operands.
979 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
980 if (N.getOpcode() == ISD::FrameIndex) {
981 // Match frame index...
982 int FI = cast<FrameIndexSDNode>(N)->getIndex();
983 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
984 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
986 } else if (N.getOpcode() == ARMISD::Wrapper &&
987 !(Subtarget->useMovt() &&
988 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
989 Base = N.getOperand(0);
990 if (Base.getOpcode() == ISD::TargetConstantPool)
991 return false; // We want to select t2LDRpci instead.
994 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
998 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
999 if (SelectT2AddrModeImm8(N, Base, OffImm))
1000 // Let t2LDRi8 handle (R - imm8).
1003 int RHSC = (int)RHS->getZExtValue();
1004 if (N.getOpcode() == ISD::SUB)
1007 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
1008 Base = N.getOperand(0);
1009 if (Base.getOpcode() == ISD::FrameIndex) {
1010 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1011 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1013 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1020 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1024 bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue N,
1025 SDValue &Base, SDValue &OffImm) {
1026 // Match simple R - imm8 operands.
1027 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::SUB) {
1028 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1029 int RHSC = (int)RHS->getSExtValue();
1030 if (N.getOpcode() == ISD::SUB)
1033 if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative)
1034 Base = N.getOperand(0);
1035 if (Base.getOpcode() == ISD::FrameIndex) {
1036 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1037 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1039 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1048 bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
1050 unsigned Opcode = Op->getOpcode();
1051 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
1052 ? cast<LoadSDNode>(Op)->getAddressingMode()
1053 : cast<StoreSDNode>(Op)->getAddressingMode();
1054 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N)) {
1055 int RHSC = (int)RHS->getZExtValue();
1056 if (RHSC >= 0 && RHSC < 0x100) { // 8 bits.
1057 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
1058 ? CurDAG->getTargetConstant(RHSC, MVT::i32)
1059 : CurDAG->getTargetConstant(-RHSC, MVT::i32);
1067 bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue N,
1069 SDValue &OffReg, SDValue &ShImm) {
1070 // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.
1071 if (N.getOpcode() != ISD::ADD)
1074 // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8.
1075 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1076 int RHSC = (int)RHS->getZExtValue();
1077 if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned)
1079 else if (RHSC < 0 && RHSC >= -255) // 8 bits
1083 if (Subtarget->isCortexA9() && !N.hasOneUse()) {
1084 // Compute R + (R << [1,2,3]) and reuse it.
1089 // Look for (R + R) or (R + (R << [1,2,3])).
1091 Base = N.getOperand(0);
1092 OffReg = N.getOperand(1);
1094 // Swap if it is ((R << c) + R).
1095 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg);
1096 if (ShOpcVal != ARM_AM::lsl) {
1097 ShOpcVal = ARM_AM::getShiftOpcForNode(Base);
1098 if (ShOpcVal == ARM_AM::lsl)
1099 std::swap(Base, OffReg);
1102 if (ShOpcVal == ARM_AM::lsl) {
1103 // Check to see if the RHS of the shift is a constant, if not, we can't fold
1105 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
1106 ShAmt = Sh->getZExtValue();
1107 if (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt))
1108 OffReg = OffReg.getOperand(0);
1111 ShOpcVal = ARM_AM::no_shift;
1114 ShOpcVal = ARM_AM::no_shift;
1118 ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
1123 //===--------------------------------------------------------------------===//
1125 /// getAL - Returns a ARMCC::AL immediate node.
1126 static inline SDValue getAL(SelectionDAG *CurDAG) {
1127 return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
1130 SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDNode *N) {
1131 LoadSDNode *LD = cast<LoadSDNode>(N);
1132 ISD::MemIndexedMode AM = LD->getAddressingMode();
1133 if (AM == ISD::UNINDEXED)
1136 EVT LoadedVT = LD->getMemoryVT();
1137 SDValue Offset, AMOpc;
1138 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1139 unsigned Opcode = 0;
1141 if (LoadedVT == MVT::i32 &&
1142 SelectAddrMode2Offset(N, LD->getOffset(), Offset, AMOpc)) {
1143 Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST;
1145 } else if (LoadedVT == MVT::i16 &&
1146 SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1148 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
1149 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
1150 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
1151 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
1152 if (LD->getExtensionType() == ISD::SEXTLOAD) {
1153 if (SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1155 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
1158 if (SelectAddrMode2Offset(N, LD->getOffset(), Offset, AMOpc)) {
1160 Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST;
1166 SDValue Chain = LD->getChain();
1167 SDValue Base = LD->getBasePtr();
1168 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
1169 CurDAG->getRegister(0, MVT::i32), Chain };
1170 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32,
1171 MVT::Other, Ops, 6);
1177 SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDNode *N) {
1178 LoadSDNode *LD = cast<LoadSDNode>(N);
1179 ISD::MemIndexedMode AM = LD->getAddressingMode();
1180 if (AM == ISD::UNINDEXED)
1183 EVT LoadedVT = LD->getMemoryVT();
1184 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
1186 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1187 unsigned Opcode = 0;
1189 if (SelectT2AddrModeImm8Offset(N, LD->getOffset(), Offset)) {
1190 switch (LoadedVT.getSimpleVT().SimpleTy) {
1192 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
1196 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
1198 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
1203 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
1205 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
1214 SDValue Chain = LD->getChain();
1215 SDValue Base = LD->getBasePtr();
1216 SDValue Ops[]= { Base, Offset, getAL(CurDAG),
1217 CurDAG->getRegister(0, MVT::i32), Chain };
1218 return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32,
1219 MVT::Other, Ops, 5);
1225 /// PairSRegs - Form a D register from a pair of S registers.
1227 SDNode *ARMDAGToDAGISel::PairSRegs(EVT VT, SDValue V0, SDValue V1) {
1228 DebugLoc dl = V0.getNode()->getDebugLoc();
1229 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1230 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1231 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
1232 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
1235 /// PairDRegs - Form a quad register from a pair of D registers.
1237 SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) {
1238 DebugLoc dl = V0.getNode()->getDebugLoc();
1239 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1240 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1241 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
1242 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
1245 /// PairQRegs - Form 4 consecutive D registers from a pair of Q registers.
1247 SDNode *ARMDAGToDAGISel::PairQRegs(EVT VT, SDValue V0, SDValue V1) {
1248 DebugLoc dl = V0.getNode()->getDebugLoc();
1249 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1250 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1251 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
1252 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
1255 /// QuadSRegs - Form 4 consecutive S registers.
1257 SDNode *ARMDAGToDAGISel::QuadSRegs(EVT VT, SDValue V0, SDValue V1,
1258 SDValue V2, SDValue V3) {
1259 DebugLoc dl = V0.getNode()->getDebugLoc();
1260 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1261 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1262 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, MVT::i32);
1263 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::ssub_3, MVT::i32);
1264 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 };
1265 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
1268 /// QuadDRegs - Form 4 consecutive D registers.
1270 SDNode *ARMDAGToDAGISel::QuadDRegs(EVT VT, SDValue V0, SDValue V1,
1271 SDValue V2, SDValue V3) {
1272 DebugLoc dl = V0.getNode()->getDebugLoc();
1273 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1274 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1275 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, MVT::i32);
1276 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, MVT::i32);
1277 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 };
1278 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
1281 /// QuadQRegs - Form 4 consecutive Q registers.
1283 SDNode *ARMDAGToDAGISel::QuadQRegs(EVT VT, SDValue V0, SDValue V1,
1284 SDValue V2, SDValue V3) {
1285 DebugLoc dl = V0.getNode()->getDebugLoc();
1286 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1287 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1288 SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, MVT::i32);
1289 SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, MVT::i32);
1290 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1, V2, SubReg2, V3, SubReg3 };
1291 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 8);
1294 /// GetVLDSTAlign - Get the alignment (in bytes) for the alignment operand
1295 /// of a NEON VLD or VST instruction. The supported values depend on the
1296 /// number of registers being loaded.
1297 SDValue ARMDAGToDAGISel::GetVLDSTAlign(SDValue Align, unsigned NumVecs,
1298 bool is64BitVector) {
1299 unsigned NumRegs = NumVecs;
1300 if (!is64BitVector && NumVecs < 3)
1303 unsigned Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1304 if (Alignment >= 32 && NumRegs == 4)
1306 else if (Alignment >= 16 && (NumRegs == 2 || NumRegs == 4))
1308 else if (Alignment >= 8)
1313 return CurDAG->getTargetConstant(Alignment, MVT::i32);
1316 SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, unsigned NumVecs,
1317 unsigned *DOpcodes, unsigned *QOpcodes0,
1318 unsigned *QOpcodes1) {
1319 assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range");
1320 DebugLoc dl = N->getDebugLoc();
1322 SDValue MemAddr, Align;
1323 if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, Align))
1326 SDValue Chain = N->getOperand(0);
1327 EVT VT = N->getValueType(0);
1328 bool is64BitVector = VT.is64BitVector();
1329 Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1331 unsigned OpcodeIndex;
1332 switch (VT.getSimpleVT().SimpleTy) {
1333 default: llvm_unreachable("unhandled vld type");
1334 // Double-register operations:
1335 case MVT::v8i8: OpcodeIndex = 0; break;
1336 case MVT::v4i16: OpcodeIndex = 1; break;
1338 case MVT::v2i32: OpcodeIndex = 2; break;
1339 case MVT::v1i64: OpcodeIndex = 3; break;
1340 // Quad-register operations:
1341 case MVT::v16i8: OpcodeIndex = 0; break;
1342 case MVT::v8i16: OpcodeIndex = 1; break;
1344 case MVT::v4i32: OpcodeIndex = 2; break;
1345 case MVT::v2i64: OpcodeIndex = 3;
1346 assert(NumVecs == 1 && "v2i64 type only supported for VLD1");
1354 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1357 ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts);
1360 SDValue Pred = getAL(CurDAG);
1361 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1363 if (is64BitVector) {
1364 unsigned Opc = DOpcodes[OpcodeIndex];
1365 const SDValue Ops[] = { MemAddr, Align, Pred, Reg0, Chain };
1366 SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTy, MVT::Other, Ops, 5);
1370 SuperReg = SDValue(VLd, 0);
1371 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1372 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1373 SDValue D = CurDAG->getTargetExtractSubreg(ARM::dsub_0+Vec,
1375 ReplaceUses(SDValue(N, Vec), D);
1377 ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1));
1382 // Quad registers are directly supported for VLD1 and VLD2,
1383 // loading pairs of D regs.
1384 unsigned Opc = QOpcodes0[OpcodeIndex];
1385 const SDValue Ops[] = { MemAddr, Align, Pred, Reg0, Chain };
1386 SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTy, MVT::Other, Ops, 5);
1390 SuperReg = SDValue(VLd, 0);
1391 Chain = SDValue(VLd, 1);
1394 // Otherwise, quad registers are loaded with two separate instructions,
1395 // where one loads the even registers and the other loads the odd registers.
1396 EVT AddrTy = MemAddr.getValueType();
1398 // Load the even subregs.
1399 unsigned Opc = QOpcodes0[OpcodeIndex];
1401 SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy), 0);
1402 const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain };
1404 CurDAG->getMachineNode(Opc, dl, ResTy, AddrTy, MVT::Other, OpsA, 7);
1405 Chain = SDValue(VLdA, 2);
1407 // Load the odd subregs.
1408 Opc = QOpcodes1[OpcodeIndex];
1409 const SDValue OpsB[] = { SDValue(VLdA, 1), Align, Reg0, SDValue(VLdA, 0),
1410 Pred, Reg0, Chain };
1412 CurDAG->getMachineNode(Opc, dl, ResTy, AddrTy, MVT::Other, OpsB, 7);
1413 SuperReg = SDValue(VLdB, 0);
1414 Chain = SDValue(VLdB, 2);
1417 // Extract out the Q registers.
1418 assert(ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1419 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1420 SDValue Q = CurDAG->getTargetExtractSubreg(ARM::qsub_0+Vec,
1422 ReplaceUses(SDValue(N, Vec), Q);
1424 ReplaceUses(SDValue(N, NumVecs), Chain);
1428 SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, unsigned NumVecs,
1429 unsigned *DOpcodes, unsigned *QOpcodes0,
1430 unsigned *QOpcodes1) {
1431 assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range");
1432 DebugLoc dl = N->getDebugLoc();
1434 SDValue MemAddr, Align;
1435 if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, Align))
1438 SDValue Chain = N->getOperand(0);
1439 EVT VT = N->getOperand(3).getValueType();
1440 bool is64BitVector = VT.is64BitVector();
1441 Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1443 unsigned OpcodeIndex;
1444 switch (VT.getSimpleVT().SimpleTy) {
1445 default: llvm_unreachable("unhandled vst type");
1446 // Double-register operations:
1447 case MVT::v8i8: OpcodeIndex = 0; break;
1448 case MVT::v4i16: OpcodeIndex = 1; break;
1450 case MVT::v2i32: OpcodeIndex = 2; break;
1451 case MVT::v1i64: OpcodeIndex = 3; break;
1452 // Quad-register operations:
1453 case MVT::v16i8: OpcodeIndex = 0; break;
1454 case MVT::v8i16: OpcodeIndex = 1; break;
1456 case MVT::v4i32: OpcodeIndex = 2; break;
1457 case MVT::v2i64: OpcodeIndex = 3;
1458 assert(NumVecs == 1 && "v2i64 type only supported for VST1");
1462 SDValue Pred = getAL(CurDAG);
1463 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1465 SmallVector<SDValue, 7> Ops;
1466 Ops.push_back(MemAddr);
1467 Ops.push_back(Align);
1469 if (is64BitVector) {
1471 Ops.push_back(N->getOperand(3));
1474 SDValue V0 = N->getOperand(0+3);
1475 SDValue V1 = N->getOperand(1+3);
1477 // Form a REG_SEQUENCE to force register allocation.
1479 RegSeq = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1481 SDValue V2 = N->getOperand(2+3);
1482 // If it's a vld3, form a quad D-register and leave the last part as
1484 SDValue V3 = (NumVecs == 3)
1485 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1486 : N->getOperand(3+3);
1487 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1489 Ops.push_back(RegSeq);
1491 Ops.push_back(Pred);
1492 Ops.push_back(Reg0); // predicate register
1493 Ops.push_back(Chain);
1494 unsigned Opc = DOpcodes[OpcodeIndex];
1495 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 6);
1499 // Quad registers are directly supported for VST1 and VST2.
1500 unsigned Opc = QOpcodes0[OpcodeIndex];
1502 Ops.push_back(N->getOperand(3));
1504 // Form a QQ register.
1505 SDValue Q0 = N->getOperand(3);
1506 SDValue Q1 = N->getOperand(4);
1507 Ops.push_back(SDValue(PairQRegs(MVT::v4i64, Q0, Q1), 0));
1509 Ops.push_back(Pred);
1510 Ops.push_back(Reg0); // predicate register
1511 Ops.push_back(Chain);
1512 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 6);
1515 // Otherwise, quad registers are stored with two separate instructions,
1516 // where one stores the even registers and the other stores the odd registers.
1518 // Form the QQQQ REG_SEQUENCE.
1519 SDValue V0 = N->getOperand(0+3);
1520 SDValue V1 = N->getOperand(1+3);
1521 SDValue V2 = N->getOperand(2+3);
1522 SDValue V3 = (NumVecs == 3)
1523 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1524 : N->getOperand(3+3);
1525 SDValue RegSeq = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);
1527 // Store the even D registers.
1528 Ops.push_back(Reg0); // post-access address offset
1529 Ops.push_back(RegSeq);
1530 Ops.push_back(Pred);
1531 Ops.push_back(Reg0); // predicate register
1532 Ops.push_back(Chain);
1533 unsigned Opc = QOpcodes0[OpcodeIndex];
1534 SDNode *VStA = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
1535 MVT::Other, Ops.data(), 7);
1536 Chain = SDValue(VStA, 1);
1538 // Store the odd D registers.
1539 Ops[0] = SDValue(VStA, 0); // MemAddr
1541 Opc = QOpcodes1[OpcodeIndex];
1542 SDNode *VStB = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
1543 MVT::Other, Ops.data(), 7);
1544 Chain = SDValue(VStB, 1);
1545 ReplaceUses(SDValue(N, 0), Chain);
1549 SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
1550 unsigned NumVecs, unsigned *DOpcodes,
1551 unsigned *QOpcodes) {
1552 assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
1553 DebugLoc dl = N->getDebugLoc();
1555 SDValue MemAddr, Align;
1556 if (!SelectAddrMode6(N, N->getOperand(2), MemAddr, Align))
1559 SDValue Chain = N->getOperand(0);
1561 cast<ConstantSDNode>(N->getOperand(NumVecs+3))->getZExtValue();
1562 EVT VT = IsLoad ? N->getValueType(0) : N->getOperand(3).getValueType();
1563 bool is64BitVector = VT.is64BitVector();
1565 unsigned Alignment = 0;
1567 Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1568 unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
1569 if (Alignment > NumBytes)
1570 Alignment = NumBytes;
1571 // Alignment must be a power of two; make sure of that.
1572 Alignment = (Alignment & -Alignment);
1576 Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
1578 unsigned OpcodeIndex;
1579 switch (VT.getSimpleVT().SimpleTy) {
1580 default: llvm_unreachable("unhandled vld/vst lane type");
1581 // Double-register operations:
1582 case MVT::v8i8: OpcodeIndex = 0; break;
1583 case MVT::v4i16: OpcodeIndex = 1; break;
1585 case MVT::v2i32: OpcodeIndex = 2; break;
1586 // Quad-register operations:
1587 case MVT::v8i16: OpcodeIndex = 0; break;
1589 case MVT::v4i32: OpcodeIndex = 1; break;
1592 SDValue Pred = getAL(CurDAG);
1593 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1595 SmallVector<SDValue, 7> Ops;
1596 Ops.push_back(MemAddr);
1597 Ops.push_back(Align);
1599 unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1600 QOpcodes[OpcodeIndex]);
1603 SDValue V0 = N->getOperand(0+3);
1604 SDValue V1 = N->getOperand(1+3);
1607 SuperReg = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1609 SuperReg = SDValue(PairQRegs(MVT::v4i64, V0, V1), 0);
1611 SDValue V2 = N->getOperand(2+3);
1612 SDValue V3 = (NumVecs == 3)
1613 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1614 : N->getOperand(3+3);
1616 SuperReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1618 SuperReg = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);
1620 Ops.push_back(SuperReg);
1621 Ops.push_back(getI32Imm(Lane));
1622 Ops.push_back(Pred);
1623 Ops.push_back(Reg0);
1624 Ops.push_back(Chain);
1627 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops.data(), 7);
1630 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1633 ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts);
1635 SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTy, MVT::Other,
1637 SuperReg = SDValue(VLdLn, 0);
1638 Chain = SDValue(VLdLn, 1);
1640 // Extract the subregisters.
1641 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1642 assert(ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1643 unsigned SubIdx = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;
1644 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1645 ReplaceUses(SDValue(N, Vec),
1646 CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, SuperReg));
1647 ReplaceUses(SDValue(N, NumVecs), Chain);
1651 SDNode *ARMDAGToDAGISel::SelectVLDDup(SDNode *N, unsigned NumVecs,
1652 unsigned *Opcodes) {
1653 assert(NumVecs >=2 && NumVecs <= 4 && "VLDDup NumVecs out-of-range");
1654 DebugLoc dl = N->getDebugLoc();
1656 SDValue MemAddr, Align;
1657 if (!SelectAddrMode6(N, N->getOperand(1), MemAddr, Align))
1660 SDValue Chain = N->getOperand(0);
1661 EVT VT = N->getValueType(0);
1663 unsigned Alignment = 0;
1665 Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1666 unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
1667 if (Alignment > NumBytes)
1668 Alignment = NumBytes;
1669 // Alignment must be a power of two; make sure of that.
1670 Alignment = (Alignment & -Alignment);
1674 Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
1676 unsigned OpcodeIndex;
1677 switch (VT.getSimpleVT().SimpleTy) {
1678 default: llvm_unreachable("unhandled vld-dup type");
1679 case MVT::v8i8: OpcodeIndex = 0; break;
1680 case MVT::v4i16: OpcodeIndex = 1; break;
1682 case MVT::v2i32: OpcodeIndex = 2; break;
1685 SDValue Pred = getAL(CurDAG);
1686 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1688 unsigned Opc = Opcodes[OpcodeIndex];
1689 const SDValue Ops[] = { MemAddr, Align, Pred, Reg0, Chain };
1691 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1692 EVT ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts);
1693 SDNode *VLdDup = CurDAG->getMachineNode(Opc, dl, ResTy, MVT::Other, Ops, 5);
1694 SuperReg = SDValue(VLdDup, 0);
1695 Chain = SDValue(VLdDup, 1);
1697 // Extract the subregisters.
1698 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
1699 unsigned SubIdx = ARM::dsub_0;
1700 for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1701 ReplaceUses(SDValue(N, Vec),
1702 CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, SuperReg));
1703 ReplaceUses(SDValue(N, NumVecs), Chain);
1707 SDNode *ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs,
1709 assert(NumVecs >= 2 && NumVecs <= 4 && "VTBL NumVecs out-of-range");
1710 DebugLoc dl = N->getDebugLoc();
1711 EVT VT = N->getValueType(0);
1712 unsigned FirstTblReg = IsExt ? 2 : 1;
1714 // Form a REG_SEQUENCE to force register allocation.
1716 SDValue V0 = N->getOperand(FirstTblReg + 0);
1717 SDValue V1 = N->getOperand(FirstTblReg + 1);
1719 RegSeq = SDValue(PairDRegs(MVT::v16i8, V0, V1), 0);
1721 SDValue V2 = N->getOperand(FirstTblReg + 2);
1722 // If it's a vtbl3, form a quad D-register and leave the last part as
1724 SDValue V3 = (NumVecs == 3)
1725 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1726 : N->getOperand(FirstTblReg + 3);
1727 RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1730 SmallVector<SDValue, 6> Ops;
1732 Ops.push_back(N->getOperand(1));
1733 Ops.push_back(RegSeq);
1734 Ops.push_back(N->getOperand(FirstTblReg + NumVecs));
1735 Ops.push_back(getAL(CurDAG)); // predicate
1736 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // predicate register
1737 return CurDAG->getMachineNode(Opc, dl, VT, Ops.data(), Ops.size());
1740 SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N,
1742 if (!Subtarget->hasV6T2Ops())
1745 unsigned Opc = isSigned ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX)
1746 : (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX);
1749 // For unsigned extracts, check for a shift right and mask
1750 unsigned And_imm = 0;
1751 if (N->getOpcode() == ISD::AND) {
1752 if (isOpcWithIntImmediate(N, ISD::AND, And_imm)) {
1754 // The immediate is a mask of the low bits iff imm & (imm+1) == 0
1755 if (And_imm & (And_imm + 1))
1758 unsigned Srl_imm = 0;
1759 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL,
1761 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
1763 unsigned Width = CountTrailingOnes_32(And_imm);
1764 unsigned LSB = Srl_imm;
1765 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1766 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1767 CurDAG->getTargetConstant(LSB, MVT::i32),
1768 CurDAG->getTargetConstant(Width, MVT::i32),
1769 getAL(CurDAG), Reg0 };
1770 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1776 // Otherwise, we're looking for a shift of a shift
1777 unsigned Shl_imm = 0;
1778 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, Shl_imm)) {
1779 assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!");
1780 unsigned Srl_imm = 0;
1781 if (isInt32Immediate(N->getOperand(1), Srl_imm)) {
1782 assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
1783 unsigned Width = 32 - Srl_imm;
1784 int LSB = Srl_imm - Shl_imm;
1787 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1788 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1789 CurDAG->getTargetConstant(LSB, MVT::i32),
1790 CurDAG->getTargetConstant(Width, MVT::i32),
1791 getAL(CurDAG), Reg0 };
1792 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1798 SDNode *ARMDAGToDAGISel::
1799 SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1800 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1803 if (SelectT2ShifterOperandReg(TrueVal, CPTmp0, CPTmp1)) {
1804 unsigned SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue();
1805 unsigned SOShOp = ARM_AM::getSORegShOp(SOVal);
1808 case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break;
1809 case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break;
1810 case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break;
1811 case ARM_AM::ror: Opc = ARM::t2MOVCCror; break;
1813 llvm_unreachable("Unknown so_reg opcode!");
1817 CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32);
1818 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1819 SDValue Ops[] = { FalseVal, CPTmp0, SOShImm, CC, CCR, InFlag };
1820 return CurDAG->SelectNodeTo(N, Opc, MVT::i32,Ops, 6);
1825 SDNode *ARMDAGToDAGISel::
1826 SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1827 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1831 if (SelectShifterOperandReg(TrueVal, CPTmp0, CPTmp1, CPTmp2)) {
1832 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1833 SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CPTmp2, CC, CCR, InFlag };
1834 return CurDAG->SelectNodeTo(N, ARM::MOVCCs, MVT::i32, Ops, 7);
1839 SDNode *ARMDAGToDAGISel::
1840 SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1841 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1842 ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
1847 unsigned TrueImm = T->getZExtValue();
1848 if (is_t2_so_imm(TrueImm)) {
1849 Opc = ARM::t2MOVCCi;
1850 } else if (TrueImm <= 0xffff) {
1851 Opc = ARM::t2MOVCCi16;
1852 } else if (is_t2_so_imm_not(TrueImm)) {
1854 Opc = ARM::t2MVNCCi;
1855 } else if (TrueVal.getNode()->hasOneUse() && Subtarget->hasV6T2Ops()) {
1857 Opc = ARM::t2MOVCCi32imm;
1861 SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
1862 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1863 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
1864 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1870 SDNode *ARMDAGToDAGISel::
1871 SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
1872 ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
1873 ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
1878 unsigned TrueImm = T->getZExtValue();
1879 bool isSoImm = is_so_imm(TrueImm);
1882 } else if (Subtarget->hasV6T2Ops() && TrueImm <= 0xffff) {
1883 Opc = ARM::MOVCCi16;
1884 } else if (is_so_imm_not(TrueImm)) {
1887 } else if (TrueVal.getNode()->hasOneUse() &&
1888 (Subtarget->hasV6T2Ops() || ARM_AM::isSOImmTwoPartVal(TrueImm))) {
1890 Opc = ARM::MOVCCi32imm;
1894 SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
1895 SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
1896 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
1897 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1903 SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDNode *N) {
1904 EVT VT = N->getValueType(0);
1905 SDValue FalseVal = N->getOperand(0);
1906 SDValue TrueVal = N->getOperand(1);
1907 SDValue CC = N->getOperand(2);
1908 SDValue CCR = N->getOperand(3);
1909 SDValue InFlag = N->getOperand(4);
1910 assert(CC.getOpcode() == ISD::Constant);
1911 assert(CCR.getOpcode() == ISD::Register);
1912 ARMCC::CondCodes CCVal =
1913 (ARMCC::CondCodes)cast<ConstantSDNode>(CC)->getZExtValue();
1915 if (!Subtarget->isThumb1Only() && VT == MVT::i32) {
1916 // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1917 // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1918 // Pattern complexity = 18 cost = 1 size = 0
1922 if (Subtarget->isThumb()) {
1923 SDNode *Res = SelectT2CMOVShiftOp(N, FalseVal, TrueVal,
1924 CCVal, CCR, InFlag);
1926 Res = SelectT2CMOVShiftOp(N, TrueVal, FalseVal,
1927 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1931 SDNode *Res = SelectARMCMOVShiftOp(N, FalseVal, TrueVal,
1932 CCVal, CCR, InFlag);
1934 Res = SelectARMCMOVShiftOp(N, TrueVal, FalseVal,
1935 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1940 // Pattern: (ARMcmov:i32 GPR:i32:$false,
1941 // (imm:i32)<<P:Pred_so_imm>>:$true,
1943 // Emits: (MOVCCi:i32 GPR:i32:$false,
1944 // (so_imm:i32 (imm:i32):$true), (imm:i32):$cc)
1945 // Pattern complexity = 10 cost = 1 size = 0
1946 if (Subtarget->isThumb()) {
1947 SDNode *Res = SelectT2CMOVImmOp(N, FalseVal, TrueVal,
1948 CCVal, CCR, InFlag);
1950 Res = SelectT2CMOVImmOp(N, TrueVal, FalseVal,
1951 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1955 SDNode *Res = SelectARMCMOVImmOp(N, FalseVal, TrueVal,
1956 CCVal, CCR, InFlag);
1958 Res = SelectARMCMOVImmOp(N, TrueVal, FalseVal,
1959 ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
1965 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1966 // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1967 // Pattern complexity = 6 cost = 1 size = 0
1969 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1970 // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1971 // Pattern complexity = 6 cost = 11 size = 0
1973 // Also FCPYScc and FCPYDcc.
1974 SDValue Tmp2 = CurDAG->getTargetConstant(CCVal, MVT::i32);
1975 SDValue Ops[] = { FalseVal, TrueVal, Tmp2, CCR, InFlag };
1977 switch (VT.getSimpleVT().SimpleTy) {
1978 default: assert(false && "Illegal conditional move type!");
1981 Opc = Subtarget->isThumb()
1982 ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo)
1992 return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
1995 SDNode *ARMDAGToDAGISel::SelectConcatVector(SDNode *N) {
1996 // The only time a CONCAT_VECTORS operation can have legal types is when
1997 // two 64-bit vectors are concatenated to a 128-bit vector.
1998 EVT VT = N->getValueType(0);
1999 if (!VT.is128BitVector() || N->getNumOperands() != 2)
2000 llvm_unreachable("unexpected CONCAT_VECTORS");
2001 DebugLoc dl = N->getDebugLoc();
2002 SDValue V0 = N->getOperand(0);
2003 SDValue V1 = N->getOperand(1);
2004 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
2005 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
2006 const SDValue Ops[] = { V0, SubReg0, V1, SubReg1 };
2007 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 4);
2010 SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
2011 DebugLoc dl = N->getDebugLoc();
2013 if (N->isMachineOpcode())
2014 return NULL; // Already selected.
2016 switch (N->getOpcode()) {
2018 case ISD::Constant: {
2019 unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
2021 if (Subtarget->hasThumb2())
2022 // Thumb2-aware targets have the MOVT instruction, so all immediates can
2023 // be done with MOV + MOVT, at worst.
2026 if (Subtarget->isThumb()) {
2027 UseCP = (Val > 255 && // MOV
2028 ~Val > 255 && // MOV + MVN
2029 !ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL
2031 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
2032 ARM_AM::getSOImmVal(~Val) == -1 && // MVN
2033 !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs.
2038 CurDAG->getTargetConstantPool(ConstantInt::get(
2039 Type::getInt32Ty(*CurDAG->getContext()), Val),
2040 TLI.getPointerTy());
2043 if (Subtarget->isThumb1Only()) {
2044 SDValue Pred = getAL(CurDAG);
2045 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2046 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
2047 ResNode = CurDAG->getMachineNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other,
2052 CurDAG->getTargetConstant(0, MVT::i32),
2054 CurDAG->getRegister(0, MVT::i32),
2055 CurDAG->getEntryNode()
2057 ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
2060 ReplaceUses(SDValue(N, 0), SDValue(ResNode, 0));
2064 // Other cases are autogenerated.
2067 case ISD::FrameIndex: {
2068 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
2069 int FI = cast<FrameIndexSDNode>(N)->getIndex();
2070 SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
2071 if (Subtarget->isThumb1Only()) {
2072 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
2073 CurDAG->getTargetConstant(0, MVT::i32));
2075 unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
2076 ARM::t2ADDri : ARM::ADDri);
2077 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
2078 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2079 CurDAG->getRegister(0, MVT::i32) };
2080 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2084 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2088 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, true))
2092 if (Subtarget->isThumb1Only())
2094 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
2095 unsigned RHSV = C->getZExtValue();
2097 if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
2098 unsigned ShImm = Log2_32(RHSV-1);
2101 SDValue V = N->getOperand(0);
2102 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2103 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2104 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2105 if (Subtarget->isThumb()) {
2106 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2107 return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
2109 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2110 return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7);
2113 if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
2114 unsigned ShImm = Log2_32(RHSV+1);
2117 SDValue V = N->getOperand(0);
2118 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2119 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2120 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2121 if (Subtarget->isThumb()) {
2122 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2123 return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 6);
2125 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2126 return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7);
2132 // Check for unsigned bitfield extract
2133 if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2136 // (and (or x, c2), c1) and top 16-bits of c1 and c2 match, lower 16-bits
2137 // of c1 are 0xffff, and lower 16-bit of c2 are 0. That is, the top 16-bits
2138 // are entirely contributed by c2 and lower 16-bits are entirely contributed
2139 // by x. That's equal to (or (and x, 0xffff), (and c1, 0xffff0000)).
2140 // Select it to: "movt x, ((c1 & 0xffff) >> 16)
2141 EVT VT = N->getValueType(0);
2144 unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2())
2146 : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0);
2149 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2150 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2153 if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) {
2154 SDValue N2 = N0.getOperand(1);
2155 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2158 unsigned N1CVal = N1C->getZExtValue();
2159 unsigned N2CVal = N2C->getZExtValue();
2160 if ((N1CVal & 0xffff0000U) == (N2CVal & 0xffff0000U) &&
2161 (N1CVal & 0xffffU) == 0xffffU &&
2162 (N2CVal & 0xffffU) == 0x0U) {
2163 SDValue Imm16 = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16,
2165 SDValue Ops[] = { N0.getOperand(0), Imm16,
2166 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2167 return CurDAG->getMachineNode(Opc, dl, VT, Ops, 4);
2172 case ARMISD::VMOVRRD:
2173 return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32,
2174 N->getOperand(0), getAL(CurDAG),
2175 CurDAG->getRegister(0, MVT::i32));
2176 case ISD::UMUL_LOHI: {
2177 if (Subtarget->isThumb1Only())
2179 if (Subtarget->isThumb()) {
2180 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2181 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2182 CurDAG->getRegister(0, MVT::i32) };
2183 return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32,Ops,4);
2185 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2186 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2187 CurDAG->getRegister(0, MVT::i32) };
2188 return CurDAG->getMachineNode(ARM::UMULL, dl, MVT::i32, MVT::i32, Ops, 5);
2191 case ISD::SMUL_LOHI: {
2192 if (Subtarget->isThumb1Only())
2194 if (Subtarget->isThumb()) {
2195 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2196 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2197 return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32,Ops,4);
2199 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2200 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2201 CurDAG->getRegister(0, MVT::i32) };
2202 return CurDAG->getMachineNode(ARM::SMULL, dl, MVT::i32, MVT::i32, Ops, 5);
2206 SDNode *ResNode = 0;
2207 if (Subtarget->isThumb() && Subtarget->hasThumb2())
2208 ResNode = SelectT2IndexedLoad(N);
2210 ResNode = SelectARMIndexedLoad(N);
2213 // Other cases are autogenerated.
2216 case ARMISD::BRCOND: {
2217 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2218 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2219 // Pattern complexity = 6 cost = 1 size = 0
2221 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2222 // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
2223 // Pattern complexity = 6 cost = 1 size = 0
2225 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2226 // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2227 // Pattern complexity = 6 cost = 1 size = 0
2229 unsigned Opc = Subtarget->isThumb() ?
2230 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
2231 SDValue Chain = N->getOperand(0);
2232 SDValue N1 = N->getOperand(1);
2233 SDValue N2 = N->getOperand(2);
2234 SDValue N3 = N->getOperand(3);
2235 SDValue InFlag = N->getOperand(4);
2236 assert(N1.getOpcode() == ISD::BasicBlock);
2237 assert(N2.getOpcode() == ISD::Constant);
2238 assert(N3.getOpcode() == ISD::Register);
2240 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
2241 cast<ConstantSDNode>(N2)->getZExtValue()),
2243 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
2244 SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,
2246 Chain = SDValue(ResNode, 0);
2247 if (N->getNumValues() == 2) {
2248 InFlag = SDValue(ResNode, 1);
2249 ReplaceUses(SDValue(N, 1), InFlag);
2251 ReplaceUses(SDValue(N, 0),
2252 SDValue(Chain.getNode(), Chain.getResNo()));
2256 return SelectCMOVOp(N);
2257 case ARMISD::CNEG: {
2258 EVT VT = N->getValueType(0);
2259 SDValue N0 = N->getOperand(0);
2260 SDValue N1 = N->getOperand(1);
2261 SDValue N2 = N->getOperand(2);
2262 SDValue N3 = N->getOperand(3);
2263 SDValue InFlag = N->getOperand(4);
2264 assert(N2.getOpcode() == ISD::Constant);
2265 assert(N3.getOpcode() == ISD::Register);
2267 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
2268 cast<ConstantSDNode>(N2)->getZExtValue()),
2270 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
2272 switch (VT.getSimpleVT().SimpleTy) {
2273 default: assert(false && "Illegal conditional move type!");
2282 return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
2285 case ARMISD::VZIP: {
2287 EVT VT = N->getValueType(0);
2288 switch (VT.getSimpleVT().SimpleTy) {
2289 default: return NULL;
2290 case MVT::v8i8: Opc = ARM::VZIPd8; break;
2291 case MVT::v4i16: Opc = ARM::VZIPd16; break;
2293 case MVT::v2i32: Opc = ARM::VZIPd32; break;
2294 case MVT::v16i8: Opc = ARM::VZIPq8; break;
2295 case MVT::v8i16: Opc = ARM::VZIPq16; break;
2297 case MVT::v4i32: Opc = ARM::VZIPq32; break;
2299 SDValue Pred = getAL(CurDAG);
2300 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2301 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2302 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2304 case ARMISD::VUZP: {
2306 EVT VT = N->getValueType(0);
2307 switch (VT.getSimpleVT().SimpleTy) {
2308 default: return NULL;
2309 case MVT::v8i8: Opc = ARM::VUZPd8; break;
2310 case MVT::v4i16: Opc = ARM::VUZPd16; break;
2312 case MVT::v2i32: Opc = ARM::VUZPd32; break;
2313 case MVT::v16i8: Opc = ARM::VUZPq8; break;
2314 case MVT::v8i16: Opc = ARM::VUZPq16; break;
2316 case MVT::v4i32: Opc = ARM::VUZPq32; break;
2318 SDValue Pred = getAL(CurDAG);
2319 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2320 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2321 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2323 case ARMISD::VTRN: {
2325 EVT VT = N->getValueType(0);
2326 switch (VT.getSimpleVT().SimpleTy) {
2327 default: return NULL;
2328 case MVT::v8i8: Opc = ARM::VTRNd8; break;
2329 case MVT::v4i16: Opc = ARM::VTRNd16; break;
2331 case MVT::v2i32: Opc = ARM::VTRNd32; break;
2332 case MVT::v16i8: Opc = ARM::VTRNq8; break;
2333 case MVT::v8i16: Opc = ARM::VTRNq16; break;
2335 case MVT::v4i32: Opc = ARM::VTRNq32; break;
2337 SDValue Pred = getAL(CurDAG);
2338 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2339 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2340 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2342 case ARMISD::BUILD_VECTOR: {
2343 EVT VecVT = N->getValueType(0);
2344 EVT EltVT = VecVT.getVectorElementType();
2345 unsigned NumElts = VecVT.getVectorNumElements();
2346 if (EltVT == MVT::f64) {
2347 assert(NumElts == 2 && "unexpected type for BUILD_VECTOR");
2348 return PairDRegs(VecVT, N->getOperand(0), N->getOperand(1));
2350 assert(EltVT == MVT::f32 && "unexpected type for BUILD_VECTOR");
2352 return PairSRegs(VecVT, N->getOperand(0), N->getOperand(1));
2353 assert(NumElts == 4 && "unexpected type for BUILD_VECTOR");
2354 return QuadSRegs(VecVT, N->getOperand(0), N->getOperand(1),
2355 N->getOperand(2), N->getOperand(3));
2358 case ARMISD::VLD2DUP: {
2359 unsigned Opcodes[] = { ARM::VLD2DUPd8Pseudo, ARM::VLD2DUPd16Pseudo,
2360 ARM::VLD2DUPd32Pseudo };
2361 return SelectVLDDup(N, 2, Opcodes);
2364 case ISD::INTRINSIC_VOID:
2365 case ISD::INTRINSIC_W_CHAIN: {
2366 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
2371 case Intrinsic::arm_neon_vld1: {
2372 unsigned DOpcodes[] = { ARM::VLD1d8, ARM::VLD1d16,
2373 ARM::VLD1d32, ARM::VLD1d64 };
2374 unsigned QOpcodes[] = { ARM::VLD1q8Pseudo, ARM::VLD1q16Pseudo,
2375 ARM::VLD1q32Pseudo, ARM::VLD1q64Pseudo };
2376 return SelectVLD(N, 1, DOpcodes, QOpcodes, 0);
2379 case Intrinsic::arm_neon_vld2: {
2380 unsigned DOpcodes[] = { ARM::VLD2d8Pseudo, ARM::VLD2d16Pseudo,
2381 ARM::VLD2d32Pseudo, ARM::VLD1q64Pseudo };
2382 unsigned QOpcodes[] = { ARM::VLD2q8Pseudo, ARM::VLD2q16Pseudo,
2383 ARM::VLD2q32Pseudo };
2384 return SelectVLD(N, 2, DOpcodes, QOpcodes, 0);
2387 case Intrinsic::arm_neon_vld3: {
2388 unsigned DOpcodes[] = { ARM::VLD3d8Pseudo, ARM::VLD3d16Pseudo,
2389 ARM::VLD3d32Pseudo, ARM::VLD1d64TPseudo };
2390 unsigned QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
2391 ARM::VLD3q16Pseudo_UPD,
2392 ARM::VLD3q32Pseudo_UPD };
2393 unsigned QOpcodes1[] = { ARM::VLD3q8oddPseudo_UPD,
2394 ARM::VLD3q16oddPseudo_UPD,
2395 ARM::VLD3q32oddPseudo_UPD };
2396 return SelectVLD(N, 3, DOpcodes, QOpcodes0, QOpcodes1);
2399 case Intrinsic::arm_neon_vld4: {
2400 unsigned DOpcodes[] = { ARM::VLD4d8Pseudo, ARM::VLD4d16Pseudo,
2401 ARM::VLD4d32Pseudo, ARM::VLD1d64QPseudo };
2402 unsigned QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
2403 ARM::VLD4q16Pseudo_UPD,
2404 ARM::VLD4q32Pseudo_UPD };
2405 unsigned QOpcodes1[] = { ARM::VLD4q8oddPseudo_UPD,
2406 ARM::VLD4q16oddPseudo_UPD,
2407 ARM::VLD4q32oddPseudo_UPD };
2408 return SelectVLD(N, 4, DOpcodes, QOpcodes0, QOpcodes1);
2411 case Intrinsic::arm_neon_vld2lane: {
2412 unsigned DOpcodes[] = { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd16Pseudo,
2413 ARM::VLD2LNd32Pseudo };
2414 unsigned QOpcodes[] = { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq32Pseudo };
2415 return SelectVLDSTLane(N, true, 2, DOpcodes, QOpcodes);
2418 case Intrinsic::arm_neon_vld3lane: {
2419 unsigned DOpcodes[] = { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd16Pseudo,
2420 ARM::VLD3LNd32Pseudo };
2421 unsigned QOpcodes[] = { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq32Pseudo };
2422 return SelectVLDSTLane(N, true, 3, DOpcodes, QOpcodes);
2425 case Intrinsic::arm_neon_vld4lane: {
2426 unsigned DOpcodes[] = { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd16Pseudo,
2427 ARM::VLD4LNd32Pseudo };
2428 unsigned QOpcodes[] = { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq32Pseudo };
2429 return SelectVLDSTLane(N, true, 4, DOpcodes, QOpcodes);
2432 case Intrinsic::arm_neon_vst1: {
2433 unsigned DOpcodes[] = { ARM::VST1d8, ARM::VST1d16,
2434 ARM::VST1d32, ARM::VST1d64 };
2435 unsigned QOpcodes[] = { ARM::VST1q8Pseudo, ARM::VST1q16Pseudo,
2436 ARM::VST1q32Pseudo, ARM::VST1q64Pseudo };
2437 return SelectVST(N, 1, DOpcodes, QOpcodes, 0);
2440 case Intrinsic::arm_neon_vst2: {
2441 unsigned DOpcodes[] = { ARM::VST2d8Pseudo, ARM::VST2d16Pseudo,
2442 ARM::VST2d32Pseudo, ARM::VST1q64Pseudo };
2443 unsigned QOpcodes[] = { ARM::VST2q8Pseudo, ARM::VST2q16Pseudo,
2444 ARM::VST2q32Pseudo };
2445 return SelectVST(N, 2, DOpcodes, QOpcodes, 0);
2448 case Intrinsic::arm_neon_vst3: {
2449 unsigned DOpcodes[] = { ARM::VST3d8Pseudo, ARM::VST3d16Pseudo,
2450 ARM::VST3d32Pseudo, ARM::VST1d64TPseudo };
2451 unsigned QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
2452 ARM::VST3q16Pseudo_UPD,
2453 ARM::VST3q32Pseudo_UPD };
2454 unsigned QOpcodes1[] = { ARM::VST3q8oddPseudo_UPD,
2455 ARM::VST3q16oddPseudo_UPD,
2456 ARM::VST3q32oddPseudo_UPD };
2457 return SelectVST(N, 3, DOpcodes, QOpcodes0, QOpcodes1);
2460 case Intrinsic::arm_neon_vst4: {
2461 unsigned DOpcodes[] = { ARM::VST4d8Pseudo, ARM::VST4d16Pseudo,
2462 ARM::VST4d32Pseudo, ARM::VST1d64QPseudo };
2463 unsigned QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
2464 ARM::VST4q16Pseudo_UPD,
2465 ARM::VST4q32Pseudo_UPD };
2466 unsigned QOpcodes1[] = { ARM::VST4q8oddPseudo_UPD,
2467 ARM::VST4q16oddPseudo_UPD,
2468 ARM::VST4q32oddPseudo_UPD };
2469 return SelectVST(N, 4, DOpcodes, QOpcodes0, QOpcodes1);
2472 case Intrinsic::arm_neon_vst2lane: {
2473 unsigned DOpcodes[] = { ARM::VST2LNd8Pseudo, ARM::VST2LNd16Pseudo,
2474 ARM::VST2LNd32Pseudo };
2475 unsigned QOpcodes[] = { ARM::VST2LNq16Pseudo, ARM::VST2LNq32Pseudo };
2476 return SelectVLDSTLane(N, false, 2, DOpcodes, QOpcodes);
2479 case Intrinsic::arm_neon_vst3lane: {
2480 unsigned DOpcodes[] = { ARM::VST3LNd8Pseudo, ARM::VST3LNd16Pseudo,
2481 ARM::VST3LNd32Pseudo };
2482 unsigned QOpcodes[] = { ARM::VST3LNq16Pseudo, ARM::VST3LNq32Pseudo };
2483 return SelectVLDSTLane(N, false, 3, DOpcodes, QOpcodes);
2486 case Intrinsic::arm_neon_vst4lane: {
2487 unsigned DOpcodes[] = { ARM::VST4LNd8Pseudo, ARM::VST4LNd16Pseudo,
2488 ARM::VST4LNd32Pseudo };
2489 unsigned QOpcodes[] = { ARM::VST4LNq16Pseudo, ARM::VST4LNq32Pseudo };
2490 return SelectVLDSTLane(N, false, 4, DOpcodes, QOpcodes);
2496 case ISD::INTRINSIC_WO_CHAIN: {
2497 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
2502 case Intrinsic::arm_neon_vtbl2:
2503 return SelectVTBL(N, false, 2, ARM::VTBL2Pseudo);
2504 case Intrinsic::arm_neon_vtbl3:
2505 return SelectVTBL(N, false, 3, ARM::VTBL3Pseudo);
2506 case Intrinsic::arm_neon_vtbl4:
2507 return SelectVTBL(N, false, 4, ARM::VTBL4Pseudo);
2509 case Intrinsic::arm_neon_vtbx2:
2510 return SelectVTBL(N, true, 2, ARM::VTBX2Pseudo);
2511 case Intrinsic::arm_neon_vtbx3:
2512 return SelectVTBL(N, true, 3, ARM::VTBX3Pseudo);
2513 case Intrinsic::arm_neon_vtbx4:
2514 return SelectVTBL(N, true, 4, ARM::VTBX4Pseudo);
2519 case ISD::CONCAT_VECTORS:
2520 return SelectConcatVector(N);
2523 return SelectCode(N);
2526 bool ARMDAGToDAGISel::
2527 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
2528 std::vector<SDValue> &OutOps) {
2529 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
2530 // Require the address to be in a register. That is safe for all ARM
2531 // variants and it is hard to do anything much smarter without knowing
2532 // how the operand is used.
2533 OutOps.push_back(Op);
2537 /// createARMISelDag - This pass converts a legalized DAG into a
2538 /// ARM-specific DAG, ready for instruction scheduling.
2540 FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
2541 CodeGenOpt::Level OptLevel) {
2542 return new ARMDAGToDAGISel(TM, OptLevel);