1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
15 #include "ARMAddressingModes.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMISelLowering.h"
18 #include "ARMTargetMachine.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/Constants.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/Intrinsics.h"
24 #include "llvm/LLVMContext.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/SelectionDAGISel.h"
30 #include "llvm/Target/TargetLowering.h"
31 #include "llvm/Target/TargetOptions.h"
32 #include "llvm/Support/Compiler.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
39 //===--------------------------------------------------------------------===//
40 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
41 /// instructions for SelectionDAG operations.
44 class ARMDAGToDAGISel : public SelectionDAGISel {
45 ARMBaseTargetMachine &TM;
47 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
48 /// make the right decision when generating code for different targets.
49 const ARMSubtarget *Subtarget;
52 explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm,
53 CodeGenOpt::Level OptLevel)
54 : SelectionDAGISel(tm, OptLevel), TM(tm),
55 Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
58 virtual const char *getPassName() const {
59 return "ARM Instruction Selection";
62 /// getI32Imm - Return a target constant of type i32 with the specified
64 inline SDValue getI32Imm(unsigned Imm) {
65 return CurDAG->getTargetConstant(Imm, MVT::i32);
68 SDNode *Select(SDValue Op);
69 virtual void InstructionSelect();
70 bool SelectShifterOperandReg(SDValue Op, SDValue N, SDValue &A,
71 SDValue &B, SDValue &C);
72 bool SelectAddrMode2(SDValue Op, SDValue N, SDValue &Base,
73 SDValue &Offset, SDValue &Opc);
74 bool SelectAddrMode2Offset(SDValue Op, SDValue N,
75 SDValue &Offset, SDValue &Opc);
76 bool SelectAddrMode3(SDValue Op, SDValue N, SDValue &Base,
77 SDValue &Offset, SDValue &Opc);
78 bool SelectAddrMode3Offset(SDValue Op, SDValue N,
79 SDValue &Offset, SDValue &Opc);
80 bool SelectAddrMode4(SDValue Op, SDValue N, SDValue &Addr,
82 bool SelectAddrMode5(SDValue Op, SDValue N, SDValue &Base,
84 bool SelectAddrMode6(SDValue Op, SDValue N, SDValue &Addr, SDValue &Update,
87 bool SelectAddrModePC(SDValue Op, SDValue N, SDValue &Offset,
90 bool SelectThumbAddrModeRR(SDValue Op, SDValue N, SDValue &Base,
92 bool SelectThumbAddrModeRI5(SDValue Op, SDValue N, unsigned Scale,
93 SDValue &Base, SDValue &OffImm,
95 bool SelectThumbAddrModeS1(SDValue Op, SDValue N, SDValue &Base,
96 SDValue &OffImm, SDValue &Offset);
97 bool SelectThumbAddrModeS2(SDValue Op, SDValue N, SDValue &Base,
98 SDValue &OffImm, SDValue &Offset);
99 bool SelectThumbAddrModeS4(SDValue Op, SDValue N, SDValue &Base,
100 SDValue &OffImm, SDValue &Offset);
101 bool SelectThumbAddrModeSP(SDValue Op, SDValue N, SDValue &Base,
104 bool SelectT2ShifterOperandReg(SDValue Op, SDValue N,
105 SDValue &BaseReg, SDValue &Opc);
106 bool SelectT2AddrModeImm12(SDValue Op, SDValue N, SDValue &Base,
108 bool SelectT2AddrModeImm8(SDValue Op, SDValue N, SDValue &Base,
110 bool SelectT2AddrModeImm8Offset(SDValue Op, SDValue N,
112 bool SelectT2AddrModeImm8s4(SDValue Op, SDValue N, SDValue &Base,
114 bool SelectT2AddrModeSoReg(SDValue Op, SDValue N, SDValue &Base,
115 SDValue &OffReg, SDValue &ShImm);
117 // Include the pieces autogenerated from the target description.
118 #include "ARMGenDAGISel.inc"
121 /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
123 SDNode *SelectARMIndexedLoad(SDValue Op);
124 SDNode *SelectT2IndexedLoad(SDValue Op);
126 /// SelectDYN_ALLOC - Select dynamic alloc for Thumb.
127 SDNode *SelectDYN_ALLOC(SDValue Op);
129 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
130 /// inline asm expressions.
131 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
133 std::vector<SDValue> &OutOps);
135 /// PairDRegs - Insert a pair of double registers into an implicit def to
136 /// form a quad register.
137 SDNode *PairDRegs(EVT VT, SDValue V0, SDValue V1);
141 void ARMDAGToDAGISel::InstructionSelect() {
145 CurDAG->RemoveDeadNodes();
148 bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue Op,
153 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
155 // Don't match base register only case. That is matched to a separate
156 // lower complexity pattern with explicit register operand.
157 if (ShOpcVal == ARM_AM::no_shift) return false;
159 BaseReg = N.getOperand(0);
160 unsigned ShImmVal = 0;
161 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
162 ShReg = CurDAG->getRegister(0, MVT::i32);
163 ShImmVal = RHS->getZExtValue() & 31;
165 ShReg = N.getOperand(1);
167 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
172 bool ARMDAGToDAGISel::SelectAddrMode2(SDValue Op, SDValue N,
173 SDValue &Base, SDValue &Offset,
175 if (N.getOpcode() == ISD::MUL) {
176 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
177 // X * [3,5,9] -> X + X * [2,4,8] etc.
178 int RHSC = (int)RHS->getZExtValue();
181 ARM_AM::AddrOpc AddSub = ARM_AM::add;
183 AddSub = ARM_AM::sub;
186 if (isPowerOf2_32(RHSC)) {
187 unsigned ShAmt = Log2_32(RHSC);
188 Base = Offset = N.getOperand(0);
189 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
198 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
200 if (N.getOpcode() == ISD::FrameIndex) {
201 int FI = cast<FrameIndexSDNode>(N)->getIndex();
202 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
203 } else if (N.getOpcode() == ARMISD::Wrapper) {
204 Base = N.getOperand(0);
206 Offset = CurDAG->getRegister(0, MVT::i32);
207 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
213 // Match simple R +/- imm12 operands.
214 if (N.getOpcode() == ISD::ADD)
215 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
216 int RHSC = (int)RHS->getZExtValue();
217 if ((RHSC >= 0 && RHSC < 0x1000) ||
218 (RHSC < 0 && RHSC > -0x1000)) { // 12 bits.
219 Base = N.getOperand(0);
220 if (Base.getOpcode() == ISD::FrameIndex) {
221 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
222 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
224 Offset = CurDAG->getRegister(0, MVT::i32);
226 ARM_AM::AddrOpc AddSub = ARM_AM::add;
228 AddSub = ARM_AM::sub;
231 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
238 // Otherwise this is R +/- [possibly shifted] R
239 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
240 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
243 Base = N.getOperand(0);
244 Offset = N.getOperand(1);
246 if (ShOpcVal != ARM_AM::no_shift) {
247 // Check to see if the RHS of the shift is a constant, if not, we can't fold
249 if (ConstantSDNode *Sh =
250 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
251 ShAmt = Sh->getZExtValue();
252 Offset = N.getOperand(1).getOperand(0);
254 ShOpcVal = ARM_AM::no_shift;
258 // Try matching (R shl C) + (R).
259 if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift) {
260 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
261 if (ShOpcVal != ARM_AM::no_shift) {
262 // Check to see if the RHS of the shift is a constant, if not, we can't
264 if (ConstantSDNode *Sh =
265 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
266 ShAmt = Sh->getZExtValue();
267 Offset = N.getOperand(0).getOperand(0);
268 Base = N.getOperand(1);
270 ShOpcVal = ARM_AM::no_shift;
275 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
280 bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDValue Op, SDValue N,
281 SDValue &Offset, SDValue &Opc) {
282 unsigned Opcode = Op.getOpcode();
283 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
284 ? cast<LoadSDNode>(Op)->getAddressingMode()
285 : cast<StoreSDNode>(Op)->getAddressingMode();
286 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
287 ? ARM_AM::add : ARM_AM::sub;
288 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
289 int Val = (int)C->getZExtValue();
290 if (Val >= 0 && Val < 0x1000) { // 12 bits.
291 Offset = CurDAG->getRegister(0, MVT::i32);
292 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
300 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
302 if (ShOpcVal != ARM_AM::no_shift) {
303 // Check to see if the RHS of the shift is a constant, if not, we can't fold
305 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
306 ShAmt = Sh->getZExtValue();
307 Offset = N.getOperand(0);
309 ShOpcVal = ARM_AM::no_shift;
313 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
319 bool ARMDAGToDAGISel::SelectAddrMode3(SDValue Op, SDValue N,
320 SDValue &Base, SDValue &Offset,
322 if (N.getOpcode() == ISD::SUB) {
323 // X - C is canonicalize to X + -C, no need to handle it here.
324 Base = N.getOperand(0);
325 Offset = N.getOperand(1);
326 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
330 if (N.getOpcode() != ISD::ADD) {
332 if (N.getOpcode() == ISD::FrameIndex) {
333 int FI = cast<FrameIndexSDNode>(N)->getIndex();
334 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
336 Offset = CurDAG->getRegister(0, MVT::i32);
337 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
341 // If the RHS is +/- imm8, fold into addr mode.
342 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
343 int RHSC = (int)RHS->getZExtValue();
344 if ((RHSC >= 0 && RHSC < 256) ||
345 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
346 Base = N.getOperand(0);
347 if (Base.getOpcode() == ISD::FrameIndex) {
348 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
349 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
351 Offset = CurDAG->getRegister(0, MVT::i32);
353 ARM_AM::AddrOpc AddSub = ARM_AM::add;
355 AddSub = ARM_AM::sub;
358 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
363 Base = N.getOperand(0);
364 Offset = N.getOperand(1);
365 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
369 bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDValue Op, SDValue N,
370 SDValue &Offset, SDValue &Opc) {
371 unsigned Opcode = Op.getOpcode();
372 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
373 ? cast<LoadSDNode>(Op)->getAddressingMode()
374 : cast<StoreSDNode>(Op)->getAddressingMode();
375 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
376 ? ARM_AM::add : ARM_AM::sub;
377 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
378 int Val = (int)C->getZExtValue();
379 if (Val >= 0 && Val < 256) {
380 Offset = CurDAG->getRegister(0, MVT::i32);
381 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
387 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
391 bool ARMDAGToDAGISel::SelectAddrMode4(SDValue Op, SDValue N,
392 SDValue &Addr, SDValue &Mode) {
394 Mode = CurDAG->getTargetConstant(0, MVT::i32);
398 bool ARMDAGToDAGISel::SelectAddrMode5(SDValue Op, SDValue N,
399 SDValue &Base, SDValue &Offset) {
400 if (N.getOpcode() != ISD::ADD) {
402 if (N.getOpcode() == ISD::FrameIndex) {
403 int FI = cast<FrameIndexSDNode>(N)->getIndex();
404 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
405 } else if (N.getOpcode() == ARMISD::Wrapper) {
406 Base = N.getOperand(0);
408 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
413 // If the RHS is +/- imm8, fold into addr mode.
414 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
415 int RHSC = (int)RHS->getZExtValue();
416 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied by 4.
418 if ((RHSC >= 0 && RHSC < 256) ||
419 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
420 Base = N.getOperand(0);
421 if (Base.getOpcode() == ISD::FrameIndex) {
422 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
423 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
426 ARM_AM::AddrOpc AddSub = ARM_AM::add;
428 AddSub = ARM_AM::sub;
431 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
439 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
444 bool ARMDAGToDAGISel::SelectAddrMode6(SDValue Op, SDValue N,
445 SDValue &Addr, SDValue &Update,
448 // Default to no writeback.
449 Update = CurDAG->getRegister(0, MVT::i32);
450 Opc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(false), MVT::i32);
454 bool ARMDAGToDAGISel::SelectAddrModePC(SDValue Op, SDValue N,
455 SDValue &Offset, SDValue &Label) {
456 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
457 Offset = N.getOperand(0);
458 SDValue N1 = N.getOperand(1);
459 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
466 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue Op, SDValue N,
467 SDValue &Base, SDValue &Offset){
468 // FIXME dl should come from the parent load or store, not the address
469 DebugLoc dl = Op.getDebugLoc();
470 if (N.getOpcode() != ISD::ADD) {
471 ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
472 if (!NC || NC->getZExtValue() != 0)
479 Base = N.getOperand(0);
480 Offset = N.getOperand(1);
485 ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDValue Op, SDValue N,
486 unsigned Scale, SDValue &Base,
487 SDValue &OffImm, SDValue &Offset) {
489 SDValue TmpBase, TmpOffImm;
490 if (SelectThumbAddrModeSP(Op, N, TmpBase, TmpOffImm))
491 return false; // We want to select tLDRspi / tSTRspi instead.
492 if (N.getOpcode() == ARMISD::Wrapper &&
493 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
494 return false; // We want to select tLDRpci instead.
497 if (N.getOpcode() != ISD::ADD) {
498 Base = (N.getOpcode() == ARMISD::Wrapper) ? N.getOperand(0) : N;
499 Offset = CurDAG->getRegister(0, MVT::i32);
500 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
504 // Thumb does not have [sp, r] address mode.
505 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
506 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
507 if ((LHSR && LHSR->getReg() == ARM::SP) ||
508 (RHSR && RHSR->getReg() == ARM::SP)) {
510 Offset = CurDAG->getRegister(0, MVT::i32);
511 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
515 // If the RHS is + imm5 * scale, fold into addr mode.
516 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
517 int RHSC = (int)RHS->getZExtValue();
518 if ((RHSC & (Scale-1)) == 0) { // The constant is implicitly multiplied.
520 if (RHSC >= 0 && RHSC < 32) {
521 Base = N.getOperand(0);
522 Offset = CurDAG->getRegister(0, MVT::i32);
523 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
529 Base = N.getOperand(0);
530 Offset = N.getOperand(1);
531 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
535 bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDValue Op, SDValue N,
536 SDValue &Base, SDValue &OffImm,
538 return SelectThumbAddrModeRI5(Op, N, 1, Base, OffImm, Offset);
541 bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDValue Op, SDValue N,
542 SDValue &Base, SDValue &OffImm,
544 return SelectThumbAddrModeRI5(Op, N, 2, Base, OffImm, Offset);
547 bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDValue Op, SDValue N,
548 SDValue &Base, SDValue &OffImm,
550 return SelectThumbAddrModeRI5(Op, N, 4, Base, OffImm, Offset);
553 bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue Op, SDValue N,
554 SDValue &Base, SDValue &OffImm) {
555 if (N.getOpcode() == ISD::FrameIndex) {
556 int FI = cast<FrameIndexSDNode>(N)->getIndex();
557 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
558 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
562 if (N.getOpcode() != ISD::ADD)
565 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
566 if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
567 (LHSR && LHSR->getReg() == ARM::SP)) {
568 // If the RHS is + imm8 * scale, fold into addr mode.
569 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
570 int RHSC = (int)RHS->getZExtValue();
571 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied.
573 if (RHSC >= 0 && RHSC < 256) {
574 Base = N.getOperand(0);
575 if (Base.getOpcode() == ISD::FrameIndex) {
576 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
577 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
579 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
589 bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue Op, SDValue N,
592 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
594 // Don't match base register only case. That is matched to a separate
595 // lower complexity pattern with explicit register operand.
596 if (ShOpcVal == ARM_AM::no_shift) return false;
598 BaseReg = N.getOperand(0);
599 unsigned ShImmVal = 0;
600 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
601 ShImmVal = RHS->getZExtValue() & 31;
602 Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
609 bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue Op, SDValue N,
610 SDValue &Base, SDValue &OffImm) {
611 // Match simple R + imm12 operands.
614 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
615 if (N.getOpcode() == ISD::FrameIndex) {
616 // Match frame index...
617 int FI = cast<FrameIndexSDNode>(N)->getIndex();
618 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
619 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
621 } else if (N.getOpcode() == ARMISD::Wrapper) {
622 Base = N.getOperand(0);
623 if (Base.getOpcode() == ISD::TargetConstantPool)
624 return false; // We want to select t2LDRpci instead.
627 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
631 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
632 if (SelectT2AddrModeImm8(Op, N, Base, OffImm))
633 // Let t2LDRi8 handle (R - imm8).
636 int RHSC = (int)RHS->getZExtValue();
637 if (N.getOpcode() == ISD::SUB)
640 if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
641 Base = N.getOperand(0);
642 if (Base.getOpcode() == ISD::FrameIndex) {
643 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
644 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
646 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
653 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
657 bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue Op, SDValue N,
658 SDValue &Base, SDValue &OffImm) {
659 // Match simple R - imm8 operands.
660 if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::SUB) {
661 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
662 int RHSC = (int)RHS->getSExtValue();
663 if (N.getOpcode() == ISD::SUB)
666 if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative)
667 Base = N.getOperand(0);
668 if (Base.getOpcode() == ISD::FrameIndex) {
669 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
670 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
672 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
681 bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDValue Op, SDValue N,
683 unsigned Opcode = Op.getOpcode();
684 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
685 ? cast<LoadSDNode>(Op)->getAddressingMode()
686 : cast<StoreSDNode>(Op)->getAddressingMode();
687 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N)) {
688 int RHSC = (int)RHS->getZExtValue();
689 if (RHSC >= 0 && RHSC < 0x100) { // 8 bits.
690 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
691 ? CurDAG->getTargetConstant(RHSC, MVT::i32)
692 : CurDAG->getTargetConstant(-RHSC, MVT::i32);
700 bool ARMDAGToDAGISel::SelectT2AddrModeImm8s4(SDValue Op, SDValue N,
701 SDValue &Base, SDValue &OffImm) {
702 if (N.getOpcode() == ISD::ADD) {
703 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
704 int RHSC = (int)RHS->getZExtValue();
705 if (((RHSC & 0x3) == 0) &&
706 ((RHSC >= 0 && RHSC < 0x400) || (RHSC < 0 && RHSC > -0x400))) { // 8 bits.
707 Base = N.getOperand(0);
708 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
712 } else if (N.getOpcode() == ISD::SUB) {
713 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
714 int RHSC = (int)RHS->getZExtValue();
715 if (((RHSC & 0x3) == 0) && (RHSC >= 0 && RHSC < 0x400)) { // 8 bits.
716 Base = N.getOperand(0);
717 OffImm = CurDAG->getTargetConstant(-RHSC, MVT::i32);
726 bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue Op, SDValue N,
728 SDValue &OffReg, SDValue &ShImm) {
729 // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.
730 if (N.getOpcode() != ISD::ADD)
733 // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8.
734 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
735 int RHSC = (int)RHS->getZExtValue();
736 if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned)
738 else if (RHSC < 0 && RHSC >= -255) // 8 bits
742 // Look for (R + R) or (R + (R << [1,2,3])).
744 Base = N.getOperand(0);
745 OffReg = N.getOperand(1);
747 // Swap if it is ((R << c) + R).
748 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg);
749 if (ShOpcVal != ARM_AM::lsl) {
750 ShOpcVal = ARM_AM::getShiftOpcForNode(Base);
751 if (ShOpcVal == ARM_AM::lsl)
752 std::swap(Base, OffReg);
755 if (ShOpcVal == ARM_AM::lsl) {
756 // Check to see if the RHS of the shift is a constant, if not, we can't fold
758 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
759 ShAmt = Sh->getZExtValue();
762 ShOpcVal = ARM_AM::no_shift;
764 OffReg = OffReg.getOperand(0);
766 ShOpcVal = ARM_AM::no_shift;
770 ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
775 //===--------------------------------------------------------------------===//
777 /// getAL - Returns a ARMCC::AL immediate node.
778 static inline SDValue getAL(SelectionDAG *CurDAG) {
779 return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
782 SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDValue Op) {
783 LoadSDNode *LD = cast<LoadSDNode>(Op);
784 ISD::MemIndexedMode AM = LD->getAddressingMode();
785 if (AM == ISD::UNINDEXED)
788 EVT LoadedVT = LD->getMemoryVT();
789 SDValue Offset, AMOpc;
790 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
793 if (LoadedVT == MVT::i32 &&
794 SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
795 Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST;
797 } else if (LoadedVT == MVT::i16 &&
798 SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
800 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
801 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
802 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
803 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
804 if (LD->getExtensionType() == ISD::SEXTLOAD) {
805 if (SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
807 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
810 if (SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
812 Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST;
818 SDValue Chain = LD->getChain();
819 SDValue Base = LD->getBasePtr();
820 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
821 CurDAG->getRegister(0, MVT::i32), Chain };
822 return CurDAG->getMachineNode(Opcode, Op.getDebugLoc(), MVT::i32, MVT::i32,
829 SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDValue Op) {
830 LoadSDNode *LD = cast<LoadSDNode>(Op);
831 ISD::MemIndexedMode AM = LD->getAddressingMode();
832 if (AM == ISD::UNINDEXED)
835 EVT LoadedVT = LD->getMemoryVT();
836 bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
838 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
841 if (SelectT2AddrModeImm8Offset(Op, LD->getOffset(), Offset)) {
842 switch (LoadedVT.getSimpleVT().SimpleTy) {
844 Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
848 Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
850 Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
855 Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
857 Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
866 SDValue Chain = LD->getChain();
867 SDValue Base = LD->getBasePtr();
868 SDValue Ops[]= { Base, Offset, getAL(CurDAG),
869 CurDAG->getRegister(0, MVT::i32), Chain };
870 return CurDAG->getMachineNode(Opcode, Op.getDebugLoc(), MVT::i32, MVT::i32,
877 SDNode *ARMDAGToDAGISel::SelectDYN_ALLOC(SDValue Op) {
878 SDNode *N = Op.getNode();
879 DebugLoc dl = N->getDebugLoc();
880 EVT VT = Op.getValueType();
881 SDValue Chain = Op.getOperand(0);
882 SDValue Size = Op.getOperand(1);
883 SDValue Align = Op.getOperand(2);
884 SDValue SP = CurDAG->getRegister(ARM::SP, MVT::i32);
885 int32_t AlignVal = cast<ConstantSDNode>(Align)->getSExtValue();
887 // We need to align the stack. Use Thumb1 tAND which is the only thumb
888 // instruction that can read and write SP. This matches to a pseudo
889 // instruction that has a chain to ensure the result is written back to
890 // the stack pointer.
891 SP = SDValue(CurDAG->getMachineNode(ARM::tANDsp, dl, VT, SP, Align), 0);
893 bool isC = isa<ConstantSDNode>(Size);
894 uint32_t C = isC ? cast<ConstantSDNode>(Size)->getZExtValue() : ~0UL;
895 // Handle the most common case for both Thumb1 and Thumb2:
896 // tSUBspi - immediate is between 0 ... 508 inclusive.
897 if (C <= 508 && ((C & 3) == 0))
898 // FIXME: tSUBspi encode scale 4 implicitly.
899 return CurDAG->SelectNodeTo(N, ARM::tSUBspi_, VT, MVT::Other, SP,
900 CurDAG->getTargetConstant(C/4, MVT::i32),
903 if (Subtarget->isThumb1Only()) {
904 // Use tADDspr since Thumb1 does not have a sub r, sp, r. ARMISelLowering
905 // should have negated the size operand already. FIXME: We can't insert
906 // new target independent node at this stage so we are forced to negate
907 // it earlier. Is there a better solution?
908 return CurDAG->SelectNodeTo(N, ARM::tADDspr_, VT, MVT::Other, SP, Size,
910 } else if (Subtarget->isThumb2()) {
911 if (isC && Predicate_t2_so_imm(Size.getNode())) {
913 SDValue Ops[] = { SP, CurDAG->getTargetConstant(C, MVT::i32), Chain };
914 return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPi_, VT, MVT::Other, Ops, 3);
915 } else if (isC && Predicate_imm0_4095(Size.getNode())) {
917 SDValue Ops[] = { SP, CurDAG->getTargetConstant(C, MVT::i32), Chain };
918 return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPi12_, VT, MVT::Other, Ops, 3);
921 SDValue Ops[] = { SP, Size,
922 getI32Imm(ARM_AM::getSORegOpc(ARM_AM::lsl,0)), Chain };
923 return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPs_, VT, MVT::Other, Ops, 4);
927 // FIXME: Add ADD / SUB sp instructions for ARM.
931 /// PairDRegs - Insert a pair of double registers into an implicit def to
932 /// form a quad register.
933 SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) {
934 DebugLoc dl = V0.getNode()->getDebugLoc();
936 SDValue(CurDAG->getMachineNode(TargetInstrInfo::IMPLICIT_DEF, dl, VT), 0);
937 SDValue SubReg0 = CurDAG->getTargetConstant(ARM::DSUBREG_0, MVT::i32);
938 SDValue SubReg1 = CurDAG->getTargetConstant(ARM::DSUBREG_1, MVT::i32);
939 SDNode *Pair = CurDAG->getMachineNode(TargetInstrInfo::INSERT_SUBREG, dl,
940 VT, Undef, V0, SubReg0);
941 return CurDAG->getMachineNode(TargetInstrInfo::INSERT_SUBREG, dl,
942 VT, SDValue(Pair, 0), V1, SubReg1);
945 SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
946 SDNode *N = Op.getNode();
947 DebugLoc dl = N->getDebugLoc();
949 if (N->isMachineOpcode())
950 return NULL; // Already selected.
952 switch (N->getOpcode()) {
954 case ISD::Constant: {
955 unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
957 if (Subtarget->hasThumb2())
958 // Thumb2-aware targets have the MOVT instruction, so all immediates can
959 // be done with MOV + MOVT, at worst.
962 if (Subtarget->isThumb()) {
963 UseCP = (Val > 255 && // MOV
964 ~Val > 255 && // MOV + MVN
965 !ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL
967 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
968 ARM_AM::getSOImmVal(~Val) == -1 && // MVN
969 !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs.
974 CurDAG->getTargetConstantPool(ConstantInt::get(
975 Type::getInt32Ty(*CurDAG->getContext()), Val),
979 if (Subtarget->isThumb1Only()) {
980 SDValue Pred = CurDAG->getTargetConstant(0xEULL, MVT::i32);
981 SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
982 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
983 ResNode = CurDAG->getMachineNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other,
988 CurDAG->getRegister(0, MVT::i32),
989 CurDAG->getTargetConstant(0, MVT::i32),
991 CurDAG->getRegister(0, MVT::i32),
992 CurDAG->getEntryNode()
994 ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
997 ReplaceUses(Op, SDValue(ResNode, 0));
1001 // Other cases are autogenerated.
1004 case ISD::FrameIndex: {
1005 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
1006 int FI = cast<FrameIndexSDNode>(N)->getIndex();
1007 SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1008 if (Subtarget->isThumb1Only()) {
1009 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
1010 CurDAG->getTargetConstant(0, MVT::i32));
1012 unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
1013 ARM::t2ADDri : ARM::ADDri);
1014 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
1015 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1016 CurDAG->getRegister(0, MVT::i32) };
1017 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
1020 case ARMISD::DYN_ALLOC:
1021 return SelectDYN_ALLOC(Op);
1023 if (Subtarget->isThumb1Only())
1025 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1026 unsigned RHSV = C->getZExtValue();
1028 if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
1029 unsigned ShImm = Log2_32(RHSV-1);
1032 SDValue V = Op.getOperand(0);
1033 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
1034 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
1035 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1036 if (Subtarget->isThumb()) {
1037 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1038 return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
1040 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1041 return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7);
1044 if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
1045 unsigned ShImm = Log2_32(RHSV+1);
1048 SDValue V = Op.getOperand(0);
1049 ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
1050 SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
1051 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1052 if (Subtarget->isThumb()) {
1053 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0 };
1054 return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 5);
1056 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
1057 return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7);
1063 return CurDAG->getMachineNode(ARM::FMRRD, dl, MVT::i32, MVT::i32,
1064 Op.getOperand(0), getAL(CurDAG),
1065 CurDAG->getRegister(0, MVT::i32));
1066 case ISD::UMUL_LOHI: {
1067 if (Subtarget->isThumb1Only())
1069 if (Subtarget->isThumb()) {
1070 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
1071 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1072 CurDAG->getRegister(0, MVT::i32) };
1073 return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32, Ops,4);
1075 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
1076 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1077 CurDAG->getRegister(0, MVT::i32) };
1078 return CurDAG->getMachineNode(ARM::UMULL, dl, MVT::i32, MVT::i32, Ops, 5);
1081 case ISD::SMUL_LOHI: {
1082 if (Subtarget->isThumb1Only())
1084 if (Subtarget->isThumb()) {
1085 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
1086 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
1087 return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32, Ops,4);
1089 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1),
1090 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
1091 CurDAG->getRegister(0, MVT::i32) };
1092 return CurDAG->getMachineNode(ARM::SMULL, dl, MVT::i32, MVT::i32, Ops, 5);
1096 SDNode *ResNode = 0;
1097 if (Subtarget->isThumb() && Subtarget->hasThumb2())
1098 ResNode = SelectT2IndexedLoad(Op);
1100 ResNode = SelectARMIndexedLoad(Op);
1103 // Other cases are autogenerated.
1106 case ARMISD::BRCOND: {
1107 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1108 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
1109 // Pattern complexity = 6 cost = 1 size = 0
1111 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1112 // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
1113 // Pattern complexity = 6 cost = 1 size = 0
1115 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
1116 // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
1117 // Pattern complexity = 6 cost = 1 size = 0
1119 unsigned Opc = Subtarget->isThumb() ?
1120 ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
1121 SDValue Chain = Op.getOperand(0);
1122 SDValue N1 = Op.getOperand(1);
1123 SDValue N2 = Op.getOperand(2);
1124 SDValue N3 = Op.getOperand(3);
1125 SDValue InFlag = Op.getOperand(4);
1126 assert(N1.getOpcode() == ISD::BasicBlock);
1127 assert(N2.getOpcode() == ISD::Constant);
1128 assert(N3.getOpcode() == ISD::Register);
1130 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1131 cast<ConstantSDNode>(N2)->getZExtValue()),
1133 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
1134 SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,
1136 Chain = SDValue(ResNode, 0);
1137 if (Op.getNode()->getNumValues() == 2) {
1138 InFlag = SDValue(ResNode, 1);
1139 ReplaceUses(SDValue(Op.getNode(), 1), InFlag);
1141 ReplaceUses(SDValue(Op.getNode(), 0), SDValue(Chain.getNode(), Chain.getResNo()));
1144 case ARMISD::CMOV: {
1145 EVT VT = Op.getValueType();
1146 SDValue N0 = Op.getOperand(0);
1147 SDValue N1 = Op.getOperand(1);
1148 SDValue N2 = Op.getOperand(2);
1149 SDValue N3 = Op.getOperand(3);
1150 SDValue InFlag = Op.getOperand(4);
1151 assert(N2.getOpcode() == ISD::Constant);
1152 assert(N3.getOpcode() == ISD::Register);
1154 if (!Subtarget->isThumb1Only() && VT == MVT::i32) {
1155 // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1156 // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
1157 // Pattern complexity = 18 cost = 1 size = 0
1161 if (Subtarget->isThumb()) {
1162 if (SelectT2ShifterOperandReg(Op, N1, CPTmp0, CPTmp1)) {
1163 unsigned SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue();
1164 unsigned SOShOp = ARM_AM::getSORegShOp(SOVal);
1167 case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break;
1168 case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break;
1169 case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break;
1170 case ARM_AM::ror: Opc = ARM::t2MOVCCror; break;
1172 llvm_unreachable("Unknown so_reg opcode!");
1176 CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32);
1177 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1178 cast<ConstantSDNode>(N2)->getZExtValue()),
1180 SDValue Ops[] = { N0, CPTmp0, SOShImm, Tmp2, N3, InFlag };
1181 return CurDAG->SelectNodeTo(Op.getNode(), Opc, MVT::i32,Ops, 6);
1184 if (SelectShifterOperandReg(Op, N1, CPTmp0, CPTmp1, CPTmp2)) {
1185 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1186 cast<ConstantSDNode>(N2)->getZExtValue()),
1188 SDValue Ops[] = { N0, CPTmp0, CPTmp1, CPTmp2, Tmp2, N3, InFlag };
1189 return CurDAG->SelectNodeTo(Op.getNode(),
1190 ARM::MOVCCs, MVT::i32, Ops, 7);
1194 // Pattern: (ARMcmov:i32 GPR:i32:$false,
1195 // (imm:i32)<<P:Predicate_so_imm>>:$true,
1197 // Emits: (MOVCCi:i32 GPR:i32:$false,
1198 // (so_imm:i32 (imm:i32):$true), (imm:i32):$cc)
1199 // Pattern complexity = 10 cost = 1 size = 0
1200 if (N3.getOpcode() == ISD::Constant) {
1201 if (Subtarget->isThumb()) {
1202 if (Predicate_t2_so_imm(N3.getNode())) {
1203 SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
1204 cast<ConstantSDNode>(N1)->getZExtValue()),
1206 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1207 cast<ConstantSDNode>(N2)->getZExtValue()),
1209 SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
1210 return CurDAG->SelectNodeTo(Op.getNode(),
1211 ARM::t2MOVCCi, MVT::i32, Ops, 5);
1214 if (Predicate_so_imm(N3.getNode())) {
1215 SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
1216 cast<ConstantSDNode>(N1)->getZExtValue()),
1218 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1219 cast<ConstantSDNode>(N2)->getZExtValue()),
1221 SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
1222 return CurDAG->SelectNodeTo(Op.getNode(),
1223 ARM::MOVCCi, MVT::i32, Ops, 5);
1229 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1230 // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1231 // Pattern complexity = 6 cost = 1 size = 0
1233 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1234 // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
1235 // Pattern complexity = 6 cost = 11 size = 0
1237 // Also FCPYScc and FCPYDcc.
1238 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1239 cast<ConstantSDNode>(N2)->getZExtValue()),
1241 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
1243 switch (VT.getSimpleVT().SimpleTy) {
1244 default: assert(false && "Illegal conditional move type!");
1247 Opc = Subtarget->isThumb()
1248 ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo)
1258 return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
1260 case ARMISD::CNEG: {
1261 EVT VT = Op.getValueType();
1262 SDValue N0 = Op.getOperand(0);
1263 SDValue N1 = Op.getOperand(1);
1264 SDValue N2 = Op.getOperand(2);
1265 SDValue N3 = Op.getOperand(3);
1266 SDValue InFlag = Op.getOperand(4);
1267 assert(N2.getOpcode() == ISD::Constant);
1268 assert(N3.getOpcode() == ISD::Register);
1270 SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
1271 cast<ConstantSDNode>(N2)->getZExtValue()),
1273 SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag };
1275 switch (VT.getSimpleVT().SimpleTy) {
1276 default: assert(false && "Illegal conditional move type!");
1285 return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
1288 case ARMISD::VZIP: {
1290 EVT VT = N->getValueType(0);
1291 switch (VT.getSimpleVT().SimpleTy) {
1292 default: return NULL;
1293 case MVT::v8i8: Opc = ARM::VZIPd8; break;
1294 case MVT::v4i16: Opc = ARM::VZIPd16; break;
1296 case MVT::v2i32: Opc = ARM::VZIPd32; break;
1297 case MVT::v16i8: Opc = ARM::VZIPq8; break;
1298 case MVT::v8i16: Opc = ARM::VZIPq16; break;
1300 case MVT::v4i32: Opc = ARM::VZIPq32; break;
1302 return CurDAG->getMachineNode(Opc, dl, VT, VT,
1303 N->getOperand(0), N->getOperand(1));
1305 case ARMISD::VUZP: {
1307 EVT VT = N->getValueType(0);
1308 switch (VT.getSimpleVT().SimpleTy) {
1309 default: return NULL;
1310 case MVT::v8i8: Opc = ARM::VUZPd8; break;
1311 case MVT::v4i16: Opc = ARM::VUZPd16; break;
1313 case MVT::v2i32: Opc = ARM::VUZPd32; break;
1314 case MVT::v16i8: Opc = ARM::VUZPq8; break;
1315 case MVT::v8i16: Opc = ARM::VUZPq16; break;
1317 case MVT::v4i32: Opc = ARM::VUZPq32; break;
1319 return CurDAG->getMachineNode(Opc, dl, VT, VT,
1320 N->getOperand(0), N->getOperand(1));
1322 case ARMISD::VTRN: {
1324 EVT VT = N->getValueType(0);
1325 switch (VT.getSimpleVT().SimpleTy) {
1326 default: return NULL;
1327 case MVT::v8i8: Opc = ARM::VTRNd8; break;
1328 case MVT::v4i16: Opc = ARM::VTRNd16; break;
1330 case MVT::v2i32: Opc = ARM::VTRNd32; break;
1331 case MVT::v16i8: Opc = ARM::VTRNq8; break;
1332 case MVT::v8i16: Opc = ARM::VTRNq16; break;
1334 case MVT::v4i32: Opc = ARM::VTRNq32; break;
1336 return CurDAG->getMachineNode(Opc, dl, VT, VT,
1337 N->getOperand(0), N->getOperand(1));
1340 case ISD::INTRINSIC_VOID:
1341 case ISD::INTRINSIC_W_CHAIN: {
1342 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
1343 EVT VT = N->getValueType(0);
1350 case Intrinsic::arm_neon_vld2: {
1351 SDValue MemAddr, MemUpdate, MemOpc;
1352 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1354 if (VT.is64BitVector()) {
1355 switch (VT.getSimpleVT().SimpleTy) {
1356 default: llvm_unreachable("unhandled vld2 type");
1357 case MVT::v8i8: Opc = ARM::VLD2d8; break;
1358 case MVT::v4i16: Opc = ARM::VLD2d16; break;
1360 case MVT::v2i32: Opc = ARM::VLD2d32; break;
1361 case MVT::v1i64: Opc = ARM::VLD2d64; break;
1363 SDValue Chain = N->getOperand(0);
1364 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
1365 return CurDAG->getMachineNode(Opc, dl, VT, VT, MVT::Other, Ops, 4);
1367 // Quad registers are loaded as pairs of double registers.
1369 switch (VT.getSimpleVT().SimpleTy) {
1370 default: llvm_unreachable("unhandled vld2 type");
1371 case MVT::v16i8: Opc = ARM::VLD2q8; RegVT = MVT::v8i8; break;
1372 case MVT::v8i16: Opc = ARM::VLD2q16; RegVT = MVT::v4i16; break;
1373 case MVT::v4f32: Opc = ARM::VLD2q32; RegVT = MVT::v2f32; break;
1374 case MVT::v4i32: Opc = ARM::VLD2q32; RegVT = MVT::v2i32; break;
1376 SDValue Chain = N->getOperand(0);
1377 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
1378 std::vector<EVT> ResTys(4, RegVT);
1379 ResTys.push_back(MVT::Other);
1380 SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 4);
1381 SDNode *Q0 = PairDRegs(VT, SDValue(VLd, 0), SDValue(VLd, 1));
1382 SDNode *Q1 = PairDRegs(VT, SDValue(VLd, 2), SDValue(VLd, 3));
1383 ReplaceUses(SDValue(N, 0), SDValue(Q0, 0));
1384 ReplaceUses(SDValue(N, 1), SDValue(Q1, 0));
1385 ReplaceUses(SDValue(N, 2), SDValue(VLd, 4));
1389 case Intrinsic::arm_neon_vld3: {
1390 SDValue MemAddr, MemUpdate, MemOpc;
1391 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1393 if (VT.is64BitVector()) {
1394 switch (VT.getSimpleVT().SimpleTy) {
1395 default: llvm_unreachable("unhandled vld3 type");
1396 case MVT::v8i8: Opc = ARM::VLD3d8; break;
1397 case MVT::v4i16: Opc = ARM::VLD3d16; break;
1399 case MVT::v2i32: Opc = ARM::VLD3d32; break;
1400 case MVT::v1i64: Opc = ARM::VLD3d64; break;
1402 SDValue Chain = N->getOperand(0);
1403 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
1404 return CurDAG->getMachineNode(Opc, dl, VT, VT, VT, MVT::Other, Ops, 4);
1406 // Quad registers are loaded with two separate instructions, where one
1407 // loads the even registers and the other loads the odd registers.
1410 switch (VT.getSimpleVT().SimpleTy) {
1411 default: llvm_unreachable("unhandled vld3 type");
1413 Opc = ARM::VLD3q8a; Opc2 = ARM::VLD3q8b; RegVT = MVT::v8i8; break;
1415 Opc = ARM::VLD3q16a; Opc2 = ARM::VLD3q16b; RegVT = MVT::v4i16; break;
1417 Opc = ARM::VLD3q32a; Opc2 = ARM::VLD3q32b; RegVT = MVT::v2f32; break;
1419 Opc = ARM::VLD3q32a; Opc2 = ARM::VLD3q32b; RegVT = MVT::v2i32; break;
1421 SDValue Chain = N->getOperand(0);
1422 // Enable writeback to the address register.
1423 MemOpc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(true), MVT::i32);
1425 std::vector<EVT> ResTys(3, RegVT);
1426 ResTys.push_back(MemAddr.getValueType());
1427 ResTys.push_back(MVT::Other);
1429 const SDValue OpsA[] = { MemAddr, MemUpdate, MemOpc, Chain };
1430 SDNode *VLdA = CurDAG->getMachineNode(Opc, dl, ResTys, OpsA, 4);
1431 Chain = SDValue(VLdA, 4);
1433 const SDValue OpsB[] = { SDValue(VLdA, 3), MemUpdate, MemOpc, Chain };
1434 SDNode *VLdB = CurDAG->getMachineNode(Opc2, dl, ResTys, OpsB, 4);
1435 Chain = SDValue(VLdB, 4);
1437 SDNode *Q0 = PairDRegs(VT, SDValue(VLdA, 0), SDValue(VLdB, 0));
1438 SDNode *Q1 = PairDRegs(VT, SDValue(VLdA, 1), SDValue(VLdB, 1));
1439 SDNode *Q2 = PairDRegs(VT, SDValue(VLdA, 2), SDValue(VLdB, 2));
1440 ReplaceUses(SDValue(N, 0), SDValue(Q0, 0));
1441 ReplaceUses(SDValue(N, 1), SDValue(Q1, 0));
1442 ReplaceUses(SDValue(N, 2), SDValue(Q2, 0));
1443 ReplaceUses(SDValue(N, 3), Chain);
1447 case Intrinsic::arm_neon_vld4: {
1448 SDValue MemAddr, MemUpdate, MemOpc;
1449 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1451 if (VT.is64BitVector()) {
1452 switch (VT.getSimpleVT().SimpleTy) {
1453 default: llvm_unreachable("unhandled vld4 type");
1454 case MVT::v8i8: Opc = ARM::VLD4d8; break;
1455 case MVT::v4i16: Opc = ARM::VLD4d16; break;
1457 case MVT::v2i32: Opc = ARM::VLD4d32; break;
1458 case MVT::v1i64: Opc = ARM::VLD4d64; break;
1460 SDValue Chain = N->getOperand(0);
1461 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
1462 std::vector<EVT> ResTys(4, VT);
1463 ResTys.push_back(MVT::Other);
1464 return CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 4);
1466 // Quad registers are loaded with two separate instructions, where one
1467 // loads the even registers and the other loads the odd registers.
1470 switch (VT.getSimpleVT().SimpleTy) {
1471 default: llvm_unreachable("unhandled vld4 type");
1473 Opc = ARM::VLD4q8a; Opc2 = ARM::VLD4q8b; RegVT = MVT::v8i8; break;
1475 Opc = ARM::VLD4q16a; Opc2 = ARM::VLD4q16b; RegVT = MVT::v4i16; break;
1477 Opc = ARM::VLD4q32a; Opc2 = ARM::VLD4q32b; RegVT = MVT::v2f32; break;
1479 Opc = ARM::VLD4q32a; Opc2 = ARM::VLD4q32b; RegVT = MVT::v2i32; break;
1481 SDValue Chain = N->getOperand(0);
1482 // Enable writeback to the address register.
1483 MemOpc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(true), MVT::i32);
1485 std::vector<EVT> ResTys(4, RegVT);
1486 ResTys.push_back(MemAddr.getValueType());
1487 ResTys.push_back(MVT::Other);
1489 const SDValue OpsA[] = { MemAddr, MemUpdate, MemOpc, Chain };
1490 SDNode *VLdA = CurDAG->getMachineNode(Opc, dl, ResTys, OpsA, 4);
1491 Chain = SDValue(VLdA, 5);
1493 const SDValue OpsB[] = { SDValue(VLdA, 4), MemUpdate, MemOpc, Chain };
1494 SDNode *VLdB = CurDAG->getMachineNode(Opc2, dl, ResTys, OpsB, 4);
1495 Chain = SDValue(VLdB, 5);
1497 SDNode *Q0 = PairDRegs(VT, SDValue(VLdA, 0), SDValue(VLdB, 0));
1498 SDNode *Q1 = PairDRegs(VT, SDValue(VLdA, 1), SDValue(VLdB, 1));
1499 SDNode *Q2 = PairDRegs(VT, SDValue(VLdA, 2), SDValue(VLdB, 2));
1500 SDNode *Q3 = PairDRegs(VT, SDValue(VLdA, 3), SDValue(VLdB, 3));
1501 ReplaceUses(SDValue(N, 0), SDValue(Q0, 0));
1502 ReplaceUses(SDValue(N, 1), SDValue(Q1, 0));
1503 ReplaceUses(SDValue(N, 2), SDValue(Q2, 0));
1504 ReplaceUses(SDValue(N, 3), SDValue(Q3, 0));
1505 ReplaceUses(SDValue(N, 4), Chain);
1509 case Intrinsic::arm_neon_vld2lane: {
1510 SDValue MemAddr, MemUpdate, MemOpc;
1511 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1513 if (VT.is64BitVector()) {
1514 switch (VT.getSimpleVT().SimpleTy) {
1515 default: llvm_unreachable("unhandled vld2lane type");
1516 case MVT::v8i8: Opc = ARM::VLD2LNd8; break;
1517 case MVT::v4i16: Opc = ARM::VLD2LNd16; break;
1519 case MVT::v2i32: Opc = ARM::VLD2LNd32; break;
1521 SDValue Chain = N->getOperand(0);
1522 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1523 N->getOperand(3), N->getOperand(4),
1524 N->getOperand(5), Chain };
1525 return CurDAG->getMachineNode(Opc, dl, VT, VT, MVT::Other, Ops, 7);
1527 // Quad registers are handled by extracting subregs, doing the load,
1528 // and then inserting the results as subregs.
1531 switch (VT.getSimpleVT().SimpleTy) {
1532 default: llvm_unreachable("unhandled vld2lane type");
1534 Opc = ARM::VLD2LNq16a;
1535 Opc2 = ARM::VLD2LNq16b;
1539 Opc = ARM::VLD2LNq32a;
1540 Opc2 = ARM::VLD2LNq32b;
1544 Opc = ARM::VLD2LNq32a;
1545 Opc2 = ARM::VLD2LNq32b;
1549 SDValue Chain = N->getOperand(0);
1550 unsigned Lane = cast<ConstantSDNode>(N->getOperand(5))->getZExtValue();
1551 unsigned NumElts = RegVT.getVectorNumElements();
1552 int SubregIdx = (Lane < NumElts) ? ARM::DSUBREG_0 : ARM::DSUBREG_1;
1554 SDValue D0 = CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
1556 SDValue D1 = CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
1558 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, D0, D1,
1559 getI32Imm(Lane % NumElts), Chain };
1560 SDNode *VLdLn = CurDAG->getMachineNode((Lane < NumElts) ? Opc : Opc2,
1561 dl, RegVT, RegVT, MVT::Other,
1563 SDValue Q0 = CurDAG->getTargetInsertSubreg(SubregIdx, dl, VT,
1566 SDValue Q1 = CurDAG->getTargetInsertSubreg(SubregIdx, dl, VT,
1569 Chain = SDValue(VLdLn, 2);
1570 ReplaceUses(SDValue(N, 0), Q0);
1571 ReplaceUses(SDValue(N, 1), Q1);
1572 ReplaceUses(SDValue(N, 2), Chain);
1576 case Intrinsic::arm_neon_vld3lane: {
1577 SDValue MemAddr, MemUpdate, MemOpc;
1578 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1580 if (VT.is64BitVector()) {
1581 switch (VT.getSimpleVT().SimpleTy) {
1582 default: llvm_unreachable("unhandled vld3lane type");
1583 case MVT::v8i8: Opc = ARM::VLD3LNd8; break;
1584 case MVT::v4i16: Opc = ARM::VLD3LNd16; break;
1586 case MVT::v2i32: Opc = ARM::VLD3LNd32; break;
1588 SDValue Chain = N->getOperand(0);
1589 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1590 N->getOperand(3), N->getOperand(4),
1591 N->getOperand(5), N->getOperand(6), Chain };
1592 return CurDAG->getMachineNode(Opc, dl, VT, VT, VT, MVT::Other, Ops, 8);
1594 // Quad registers are handled by extracting subregs, doing the load,
1595 // and then inserting the results as subregs.
1598 switch (VT.getSimpleVT().SimpleTy) {
1599 default: llvm_unreachable("unhandled vld3lane type");
1601 Opc = ARM::VLD3LNq16a;
1602 Opc2 = ARM::VLD3LNq16b;
1606 Opc = ARM::VLD3LNq32a;
1607 Opc2 = ARM::VLD3LNq32b;
1611 Opc = ARM::VLD3LNq32a;
1612 Opc2 = ARM::VLD3LNq32b;
1616 SDValue Chain = N->getOperand(0);
1617 unsigned Lane = cast<ConstantSDNode>(N->getOperand(6))->getZExtValue();
1618 unsigned NumElts = RegVT.getVectorNumElements();
1619 int SubregIdx = (Lane < NumElts) ? ARM::DSUBREG_0 : ARM::DSUBREG_1;
1621 SDValue D0 = CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
1623 SDValue D1 = CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
1625 SDValue D2 = CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
1627 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, D0, D1, D2,
1628 getI32Imm(Lane % NumElts), Chain };
1629 SDNode *VLdLn = CurDAG->getMachineNode((Lane < NumElts) ? Opc : Opc2,
1630 dl, RegVT, RegVT, RegVT,
1631 MVT::Other, Ops, 8);
1632 SDValue Q0 = CurDAG->getTargetInsertSubreg(SubregIdx, dl, VT,
1635 SDValue Q1 = CurDAG->getTargetInsertSubreg(SubregIdx, dl, VT,
1638 SDValue Q2 = CurDAG->getTargetInsertSubreg(SubregIdx, dl, VT,
1641 Chain = SDValue(VLdLn, 3);
1642 ReplaceUses(SDValue(N, 0), Q0);
1643 ReplaceUses(SDValue(N, 1), Q1);
1644 ReplaceUses(SDValue(N, 2), Q2);
1645 ReplaceUses(SDValue(N, 3), Chain);
1649 case Intrinsic::arm_neon_vld4lane: {
1650 SDValue MemAddr, MemUpdate, MemOpc;
1651 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1653 if (VT.is64BitVector()) {
1654 switch (VT.getSimpleVT().SimpleTy) {
1655 default: llvm_unreachable("unhandled vld4lane type");
1656 case MVT::v8i8: Opc = ARM::VLD4LNd8; break;
1657 case MVT::v4i16: Opc = ARM::VLD4LNd16; break;
1659 case MVT::v2i32: Opc = ARM::VLD4LNd32; break;
1661 SDValue Chain = N->getOperand(0);
1662 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1663 N->getOperand(3), N->getOperand(4),
1664 N->getOperand(5), N->getOperand(6),
1665 N->getOperand(7), Chain };
1666 std::vector<EVT> ResTys(4, VT);
1667 ResTys.push_back(MVT::Other);
1668 return CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 9);
1670 // Quad registers are handled by extracting subregs, doing the load,
1671 // and then inserting the results as subregs.
1674 switch (VT.getSimpleVT().SimpleTy) {
1675 default: llvm_unreachable("unhandled vld4lane type");
1677 Opc = ARM::VLD4LNq16a;
1678 Opc2 = ARM::VLD4LNq16b;
1682 Opc = ARM::VLD4LNq32a;
1683 Opc2 = ARM::VLD4LNq32b;
1687 Opc = ARM::VLD4LNq32a;
1688 Opc2 = ARM::VLD4LNq32b;
1692 SDValue Chain = N->getOperand(0);
1693 unsigned Lane = cast<ConstantSDNode>(N->getOperand(7))->getZExtValue();
1694 unsigned NumElts = RegVT.getVectorNumElements();
1695 int SubregIdx = (Lane < NumElts) ? ARM::DSUBREG_0 : ARM::DSUBREG_1;
1697 SDValue D0 = CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
1699 SDValue D1 = CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
1701 SDValue D2 = CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
1703 SDValue D3 = CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
1705 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, D0, D1, D2, D3,
1706 getI32Imm(Lane % NumElts), Chain };
1707 std::vector<EVT> ResTys(4, RegVT);
1708 ResTys.push_back(MVT::Other);
1709 SDNode *VLdLn = CurDAG->getMachineNode((Lane < NumElts) ? Opc : Opc2,
1710 dl, ResTys, Ops, 9);
1711 SDValue Q0 = CurDAG->getTargetInsertSubreg(SubregIdx, dl, VT,
1714 SDValue Q1 = CurDAG->getTargetInsertSubreg(SubregIdx, dl, VT,
1717 SDValue Q2 = CurDAG->getTargetInsertSubreg(SubregIdx, dl, VT,
1720 SDValue Q3 = CurDAG->getTargetInsertSubreg(SubregIdx, dl, VT,
1723 Chain = SDValue(VLdLn, 4);
1724 ReplaceUses(SDValue(N, 0), Q0);
1725 ReplaceUses(SDValue(N, 1), Q1);
1726 ReplaceUses(SDValue(N, 2), Q2);
1727 ReplaceUses(SDValue(N, 3), Q3);
1728 ReplaceUses(SDValue(N, 4), Chain);
1732 case Intrinsic::arm_neon_vst2: {
1733 SDValue MemAddr, MemUpdate, MemOpc;
1734 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1736 VT = N->getOperand(3).getValueType();
1737 if (VT.is64BitVector()) {
1738 switch (VT.getSimpleVT().SimpleTy) {
1739 default: llvm_unreachable("unhandled vst2 type");
1740 case MVT::v8i8: Opc = ARM::VST2d8; break;
1741 case MVT::v4i16: Opc = ARM::VST2d16; break;
1743 case MVT::v2i32: Opc = ARM::VST2d32; break;
1744 case MVT::v1i64: Opc = ARM::VST2d64; break;
1746 SDValue Chain = N->getOperand(0);
1747 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1748 N->getOperand(3), N->getOperand(4), Chain };
1749 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 6);
1751 // Quad registers are stored as pairs of double registers.
1753 switch (VT.getSimpleVT().SimpleTy) {
1754 default: llvm_unreachable("unhandled vst2 type");
1755 case MVT::v16i8: Opc = ARM::VST2q8; RegVT = MVT::v8i8; break;
1756 case MVT::v8i16: Opc = ARM::VST2q16; RegVT = MVT::v4i16; break;
1757 case MVT::v4f32: Opc = ARM::VST2q32; RegVT = MVT::v2f32; break;
1758 case MVT::v4i32: Opc = ARM::VST2q32; RegVT = MVT::v2i32; break;
1760 SDValue Chain = N->getOperand(0);
1761 SDValue D0 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
1763 SDValue D1 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
1765 SDValue D2 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
1767 SDValue D3 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
1769 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1770 D0, D1, D2, D3, Chain };
1771 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 8);
1774 case Intrinsic::arm_neon_vst3: {
1775 SDValue MemAddr, MemUpdate, MemOpc;
1776 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1778 VT = N->getOperand(3).getValueType();
1779 if (VT.is64BitVector()) {
1780 switch (VT.getSimpleVT().SimpleTy) {
1781 default: llvm_unreachable("unhandled vst3 type");
1782 case MVT::v8i8: Opc = ARM::VST3d8; break;
1783 case MVT::v4i16: Opc = ARM::VST3d16; break;
1785 case MVT::v2i32: Opc = ARM::VST3d32; break;
1786 case MVT::v1i64: Opc = ARM::VST3d64; break;
1788 SDValue Chain = N->getOperand(0);
1789 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1790 N->getOperand(3), N->getOperand(4),
1791 N->getOperand(5), Chain };
1792 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 7);
1794 // Quad registers are stored with two separate instructions, where one
1795 // stores the even registers and the other stores the odd registers.
1798 switch (VT.getSimpleVT().SimpleTy) {
1799 default: llvm_unreachable("unhandled vst3 type");
1801 Opc = ARM::VST3q8a; Opc2 = ARM::VST3q8b; RegVT = MVT::v8i8; break;
1803 Opc = ARM::VST3q16a; Opc2 = ARM::VST3q16b; RegVT = MVT::v4i16; break;
1805 Opc = ARM::VST3q32a; Opc2 = ARM::VST3q32b; RegVT = MVT::v2f32; break;
1807 Opc = ARM::VST3q32a; Opc2 = ARM::VST3q32b; RegVT = MVT::v2i32; break;
1809 SDValue Chain = N->getOperand(0);
1810 // Enable writeback to the address register.
1811 MemOpc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(true), MVT::i32);
1813 SDValue D0 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
1815 SDValue D2 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
1817 SDValue D4 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
1819 const SDValue OpsA[] = { MemAddr, MemUpdate, MemOpc, D0, D2, D4, Chain };
1820 SDNode *VStA = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
1821 MVT::Other, OpsA, 7);
1822 Chain = SDValue(VStA, 1);
1824 SDValue D1 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
1826 SDValue D3 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
1828 SDValue D5 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
1830 MemAddr = SDValue(VStA, 0);
1831 const SDValue OpsB[] = { MemAddr, MemUpdate, MemOpc, D1, D3, D5, Chain };
1832 SDNode *VStB = CurDAG->getMachineNode(Opc2, dl, MemAddr.getValueType(),
1833 MVT::Other, OpsB, 7);
1834 Chain = SDValue(VStB, 1);
1835 ReplaceUses(SDValue(N, 0), Chain);
1839 case Intrinsic::arm_neon_vst4: {
1840 SDValue MemAddr, MemUpdate, MemOpc;
1841 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1843 VT = N->getOperand(3).getValueType();
1844 if (VT.is64BitVector()) {
1845 switch (VT.getSimpleVT().SimpleTy) {
1846 default: llvm_unreachable("unhandled vst4 type");
1847 case MVT::v8i8: Opc = ARM::VST4d8; break;
1848 case MVT::v4i16: Opc = ARM::VST4d16; break;
1850 case MVT::v2i32: Opc = ARM::VST4d32; break;
1851 case MVT::v1i64: Opc = ARM::VST4d64; break;
1853 SDValue Chain = N->getOperand(0);
1854 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1855 N->getOperand(3), N->getOperand(4),
1856 N->getOperand(5), N->getOperand(6), Chain };
1857 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 8);
1859 // Quad registers are stored with two separate instructions, where one
1860 // stores the even registers and the other stores the odd registers.
1863 switch (VT.getSimpleVT().SimpleTy) {
1864 default: llvm_unreachable("unhandled vst4 type");
1866 Opc = ARM::VST4q8a; Opc2 = ARM::VST4q8b; RegVT = MVT::v8i8; break;
1868 Opc = ARM::VST4q16a; Opc2 = ARM::VST4q16b; RegVT = MVT::v4i16; break;
1870 Opc = ARM::VST4q32a; Opc2 = ARM::VST4q32b; RegVT = MVT::v2f32; break;
1872 Opc = ARM::VST4q32a; Opc2 = ARM::VST4q32b; RegVT = MVT::v2i32; break;
1874 SDValue Chain = N->getOperand(0);
1875 // Enable writeback to the address register.
1876 MemOpc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(true), MVT::i32);
1878 SDValue D0 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
1880 SDValue D2 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
1882 SDValue D4 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
1884 SDValue D6 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_0, dl, RegVT,
1886 const SDValue OpsA[] = { MemAddr, MemUpdate, MemOpc,
1887 D0, D2, D4, D6, Chain };
1888 SDNode *VStA = CurDAG->getMachineNode(Opc, dl, MemAddr.getValueType(),
1889 MVT::Other, OpsA, 8);
1890 Chain = SDValue(VStA, 1);
1892 SDValue D1 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
1894 SDValue D3 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
1896 SDValue D5 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
1898 SDValue D7 = CurDAG->getTargetExtractSubreg(ARM::DSUBREG_1, dl, RegVT,
1900 MemAddr = SDValue(VStA, 0);
1901 const SDValue OpsB[] = { MemAddr, MemUpdate, MemOpc,
1902 D1, D3, D5, D7, Chain };
1903 SDNode *VStB = CurDAG->getMachineNode(Opc2, dl, MemAddr.getValueType(),
1904 MVT::Other, OpsB, 8);
1905 Chain = SDValue(VStB, 1);
1906 ReplaceUses(SDValue(N, 0), Chain);
1910 case Intrinsic::arm_neon_vst2lane: {
1911 SDValue MemAddr, MemUpdate, MemOpc;
1912 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1914 VT = N->getOperand(3).getValueType();
1915 if (VT.is64BitVector()) {
1916 switch (VT.getSimpleVT().SimpleTy) {
1917 default: llvm_unreachable("unhandled vst2lane type");
1918 case MVT::v8i8: Opc = ARM::VST2LNd8; break;
1919 case MVT::v4i16: Opc = ARM::VST2LNd16; break;
1921 case MVT::v2i32: Opc = ARM::VST2LNd32; break;
1923 SDValue Chain = N->getOperand(0);
1924 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1925 N->getOperand(3), N->getOperand(4),
1926 N->getOperand(5), Chain };
1927 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 7);
1929 // Quad registers are handled by extracting subregs and then doing
1933 switch (VT.getSimpleVT().SimpleTy) {
1934 default: llvm_unreachable("unhandled vst2lane type");
1936 Opc = ARM::VST2LNq16a;
1937 Opc2 = ARM::VST2LNq16b;
1941 Opc = ARM::VST2LNq32a;
1942 Opc2 = ARM::VST2LNq32b;
1946 Opc = ARM::VST2LNq32a;
1947 Opc2 = ARM::VST2LNq32b;
1951 SDValue Chain = N->getOperand(0);
1952 unsigned Lane = cast<ConstantSDNode>(N->getOperand(5))->getZExtValue();
1953 unsigned NumElts = RegVT.getVectorNumElements();
1954 int SubregIdx = (Lane < NumElts) ? ARM::DSUBREG_0 : ARM::DSUBREG_1;
1956 SDValue D0 = CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
1958 SDValue D1 = CurDAG->getTargetExtractSubreg(SubregIdx, dl, RegVT,
1960 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, D0, D1,
1961 getI32Imm(Lane % NumElts), Chain };
1962 return CurDAG->getMachineNode((Lane < NumElts) ? Opc : Opc2,
1963 dl, MVT::Other, Ops, 7);
1966 case Intrinsic::arm_neon_vst3lane: {
1967 SDValue MemAddr, MemUpdate, MemOpc;
1968 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1970 switch (N->getOperand(3).getValueType().getSimpleVT().SimpleTy) {
1971 default: llvm_unreachable("unhandled vst3lane type");
1972 case MVT::v8i8: Opc = ARM::VST3LNd8; break;
1973 case MVT::v4i16: Opc = ARM::VST3LNd16; break;
1975 case MVT::v2i32: Opc = ARM::VST3LNd32; break;
1977 SDValue Chain = N->getOperand(0);
1978 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1979 N->getOperand(3), N->getOperand(4),
1980 N->getOperand(5), N->getOperand(6), Chain };
1981 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 8);
1984 case Intrinsic::arm_neon_vst4lane: {
1985 SDValue MemAddr, MemUpdate, MemOpc;
1986 if (!SelectAddrMode6(Op, N->getOperand(2), MemAddr, MemUpdate, MemOpc))
1988 switch (N->getOperand(3).getValueType().getSimpleVT().SimpleTy) {
1989 default: llvm_unreachable("unhandled vst4lane type");
1990 case MVT::v8i8: Opc = ARM::VST4LNd8; break;
1991 case MVT::v4i16: Opc = ARM::VST4LNd16; break;
1993 case MVT::v2i32: Opc = ARM::VST4LNd32; break;
1995 SDValue Chain = N->getOperand(0);
1996 const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
1997 N->getOperand(3), N->getOperand(4),
1998 N->getOperand(5), N->getOperand(6),
1999 N->getOperand(7), Chain };
2000 return CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 9);
2006 return SelectCode(Op);
2009 bool ARMDAGToDAGISel::
2010 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
2011 std::vector<SDValue> &OutOps) {
2012 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
2014 SDValue Base, Offset, Opc;
2015 if (!SelectAddrMode2(Op, Op, Base, Offset, Opc))
2018 OutOps.push_back(Base);
2019 OutOps.push_back(Offset);
2020 OutOps.push_back(Opc);
2024 /// createARMISelDag - This pass converts a legalized DAG into a
2025 /// ARM-specific DAG, ready for instruction scheduling.
2027 FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
2028 CodeGenOpt::Level OptLevel) {
2029 return new ARMDAGToDAGISel(TM, OptLevel);