1 //===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM target.
12 //===----------------------------------------------------------------------===//
15 #include "ARMISelLowering.h"
16 #include "ARMTargetMachine.h"
17 #include "ARMAddressingModes.h"
18 #include "llvm/CallingConv.h"
19 #include "llvm/Constants.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/SelectionDAGISel.h"
28 #include "llvm/Target/TargetLowering.h"
29 #include "llvm/Target/TargetOptions.h"
30 #include "llvm/Support/Compiler.h"
31 #include "llvm/Support/Debug.h"
34 //===--------------------------------------------------------------------===//
35 /// ARMDAGToDAGISel - ARM specific code to select ARM machine
36 /// instructions for SelectionDAG operations.
39 class ARMDAGToDAGISel : public SelectionDAGISel {
40 ARMTargetLowering Lowering;
42 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
43 /// make the right decision when generating code for different targets.
44 const ARMSubtarget *Subtarget;
47 explicit ARMDAGToDAGISel(ARMTargetMachine &TM)
48 : SelectionDAGISel(Lowering), Lowering(TM),
49 Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
52 virtual const char *getPassName() const {
53 return "ARM Instruction Selection";
56 SDNode *Select(SDOperand Op);
57 virtual void InstructionSelect(SelectionDAG &DAG);
58 bool SelectAddrMode2(SDOperand Op, SDOperand N, SDOperand &Base,
59 SDOperand &Offset, SDOperand &Opc);
60 bool SelectAddrMode2Offset(SDOperand Op, SDOperand N,
61 SDOperand &Offset, SDOperand &Opc);
62 bool SelectAddrMode3(SDOperand Op, SDOperand N, SDOperand &Base,
63 SDOperand &Offset, SDOperand &Opc);
64 bool SelectAddrMode3Offset(SDOperand Op, SDOperand N,
65 SDOperand &Offset, SDOperand &Opc);
66 bool SelectAddrMode5(SDOperand Op, SDOperand N, SDOperand &Base,
69 bool SelectAddrModePC(SDOperand Op, SDOperand N, SDOperand &Offset,
72 bool SelectThumbAddrModeRR(SDOperand Op, SDOperand N, SDOperand &Base,
74 bool SelectThumbAddrModeRI5(SDOperand Op, SDOperand N, unsigned Scale,
75 SDOperand &Base, SDOperand &OffImm,
77 bool SelectThumbAddrModeS1(SDOperand Op, SDOperand N, SDOperand &Base,
78 SDOperand &OffImm, SDOperand &Offset);
79 bool SelectThumbAddrModeS2(SDOperand Op, SDOperand N, SDOperand &Base,
80 SDOperand &OffImm, SDOperand &Offset);
81 bool SelectThumbAddrModeS4(SDOperand Op, SDOperand N, SDOperand &Base,
82 SDOperand &OffImm, SDOperand &Offset);
83 bool SelectThumbAddrModeSP(SDOperand Op, SDOperand N, SDOperand &Base,
86 bool SelectShifterOperandReg(SDOperand Op, SDOperand N, SDOperand &A,
87 SDOperand &B, SDOperand &C);
89 // Include the pieces autogenerated from the target description.
90 #include "ARMGenDAGISel.inc"
94 void ARMDAGToDAGISel::InstructionSelect(SelectionDAG &DAG) {
97 DAG.setRoot(SelectRoot(DAG.getRoot()));
98 DAG.RemoveDeadNodes();
101 bool ARMDAGToDAGISel::SelectAddrMode2(SDOperand Op, SDOperand N,
102 SDOperand &Base, SDOperand &Offset,
104 if (N.getOpcode() == ISD::MUL) {
105 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
106 // X * [3,5,9] -> X + X * [2,4,8] etc.
107 int RHSC = (int)RHS->getValue();
110 ARM_AM::AddrOpc AddSub = ARM_AM::add;
112 AddSub = ARM_AM::sub;
115 if (isPowerOf2_32(RHSC)) {
116 unsigned ShAmt = Log2_32(RHSC);
117 Base = Offset = N.getOperand(0);
118 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
127 if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB) {
129 if (N.getOpcode() == ISD::FrameIndex) {
130 int FI = cast<FrameIndexSDNode>(N)->getIndex();
131 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
132 } else if (N.getOpcode() == ARMISD::Wrapper) {
133 Base = N.getOperand(0);
135 Offset = CurDAG->getRegister(0, MVT::i32);
136 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
142 // Match simple R +/- imm12 operands.
143 if (N.getOpcode() == ISD::ADD)
144 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
145 int RHSC = (int)RHS->getValue();
146 if ((RHSC >= 0 && RHSC < 0x1000) ||
147 (RHSC < 0 && RHSC > -0x1000)) { // 12 bits.
148 Base = N.getOperand(0);
149 if (Base.getOpcode() == ISD::FrameIndex) {
150 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
151 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
153 Offset = CurDAG->getRegister(0, MVT::i32);
155 ARM_AM::AddrOpc AddSub = ARM_AM::add;
157 AddSub = ARM_AM::sub;
160 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
167 // Otherwise this is R +/- [possibly shifted] R
168 ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::ADD ? ARM_AM::add:ARM_AM::sub;
169 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(1));
172 Base = N.getOperand(0);
173 Offset = N.getOperand(1);
175 if (ShOpcVal != ARM_AM::no_shift) {
176 // Check to see if the RHS of the shift is a constant, if not, we can't fold
178 if (ConstantSDNode *Sh =
179 dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
180 ShAmt = Sh->getValue();
181 Offset = N.getOperand(1).getOperand(0);
183 ShOpcVal = ARM_AM::no_shift;
187 // Try matching (R shl C) + (R).
188 if (N.getOpcode() == ISD::ADD && ShOpcVal == ARM_AM::no_shift) {
189 ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0));
190 if (ShOpcVal != ARM_AM::no_shift) {
191 // Check to see if the RHS of the shift is a constant, if not, we can't
193 if (ConstantSDNode *Sh =
194 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
195 ShAmt = Sh->getValue();
196 Offset = N.getOperand(0).getOperand(0);
197 Base = N.getOperand(1);
199 ShOpcVal = ARM_AM::no_shift;
204 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
209 bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDOperand Op, SDOperand N,
210 SDOperand &Offset, SDOperand &Opc) {
211 unsigned Opcode = Op.getOpcode();
212 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
213 ? cast<LoadSDNode>(Op)->getAddressingMode()
214 : cast<StoreSDNode>(Op)->getAddressingMode();
215 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
216 ? ARM_AM::add : ARM_AM::sub;
217 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
218 int Val = (int)C->getValue();
219 if (Val >= 0 && Val < 0x1000) { // 12 bits.
220 Offset = CurDAG->getRegister(0, MVT::i32);
221 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
229 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
231 if (ShOpcVal != ARM_AM::no_shift) {
232 // Check to see if the RHS of the shift is a constant, if not, we can't fold
234 if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
235 ShAmt = Sh->getValue();
236 Offset = N.getOperand(0);
238 ShOpcVal = ARM_AM::no_shift;
242 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
248 bool ARMDAGToDAGISel::SelectAddrMode3(SDOperand Op, SDOperand N,
249 SDOperand &Base, SDOperand &Offset,
251 if (N.getOpcode() == ISD::SUB) {
252 // X - C is canonicalize to X + -C, no need to handle it here.
253 Base = N.getOperand(0);
254 Offset = N.getOperand(1);
255 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
259 if (N.getOpcode() != ISD::ADD) {
261 if (N.getOpcode() == ISD::FrameIndex) {
262 int FI = cast<FrameIndexSDNode>(N)->getIndex();
263 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
265 Offset = CurDAG->getRegister(0, MVT::i32);
266 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
270 // If the RHS is +/- imm8, fold into addr mode.
271 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
272 int RHSC = (int)RHS->getValue();
273 if ((RHSC >= 0 && RHSC < 256) ||
274 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
275 Base = N.getOperand(0);
276 if (Base.getOpcode() == ISD::FrameIndex) {
277 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
278 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
280 Offset = CurDAG->getRegister(0, MVT::i32);
282 ARM_AM::AddrOpc AddSub = ARM_AM::add;
284 AddSub = ARM_AM::sub;
287 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
292 Base = N.getOperand(0);
293 Offset = N.getOperand(1);
294 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
298 bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDOperand Op, SDOperand N,
299 SDOperand &Offset, SDOperand &Opc) {
300 unsigned Opcode = Op.getOpcode();
301 ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
302 ? cast<LoadSDNode>(Op)->getAddressingMode()
303 : cast<StoreSDNode>(Op)->getAddressingMode();
304 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
305 ? ARM_AM::add : ARM_AM::sub;
306 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) {
307 int Val = (int)C->getValue();
308 if (Val >= 0 && Val < 256) {
309 Offset = CurDAG->getRegister(0, MVT::i32);
310 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
316 Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
321 bool ARMDAGToDAGISel::SelectAddrMode5(SDOperand Op, SDOperand N,
322 SDOperand &Base, SDOperand &Offset) {
323 if (N.getOpcode() != ISD::ADD) {
325 if (N.getOpcode() == ISD::FrameIndex) {
326 int FI = cast<FrameIndexSDNode>(N)->getIndex();
327 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
328 } else if (N.getOpcode() == ARMISD::Wrapper) {
329 Base = N.getOperand(0);
331 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
336 // If the RHS is +/- imm8, fold into addr mode.
337 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
338 int RHSC = (int)RHS->getValue();
339 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied by 4.
341 if ((RHSC >= 0 && RHSC < 256) ||
342 (RHSC < 0 && RHSC > -256)) { // note -256 itself isn't allowed.
343 Base = N.getOperand(0);
344 if (Base.getOpcode() == ISD::FrameIndex) {
345 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
346 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
349 ARM_AM::AddrOpc AddSub = ARM_AM::add;
351 AddSub = ARM_AM::sub;
354 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
362 Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
367 bool ARMDAGToDAGISel::SelectAddrModePC(SDOperand Op, SDOperand N,
368 SDOperand &Offset, SDOperand &Label) {
369 if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
370 Offset = N.getOperand(0);
371 SDOperand N1 = N.getOperand(1);
372 Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getValue(),
379 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDOperand Op, SDOperand N,
380 SDOperand &Base, SDOperand &Offset){
381 if (N.getOpcode() != ISD::ADD) {
383 // We must materialize a zero in a reg! Returning an constant here won't
384 // work since its node is -1 so it won't get added to the selection queue.
385 // Explicitly issue a tMOVri8 node!
386 Offset = SDOperand(CurDAG->getTargetNode(ARM::tMOVi8, MVT::i32,
387 CurDAG->getTargetConstant(0, MVT::i32)), 0);
391 Base = N.getOperand(0);
392 Offset = N.getOperand(1);
397 ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDOperand Op, SDOperand N,
398 unsigned Scale, SDOperand &Base,
399 SDOperand &OffImm, SDOperand &Offset) {
401 SDOperand TmpBase, TmpOffImm;
402 if (SelectThumbAddrModeSP(Op, N, TmpBase, TmpOffImm))
403 return false; // We want to select tLDRspi / tSTRspi instead.
404 if (N.getOpcode() == ARMISD::Wrapper &&
405 N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
406 return false; // We want to select tLDRpci instead.
409 if (N.getOpcode() != ISD::ADD) {
410 Base = (N.getOpcode() == ARMISD::Wrapper) ? N.getOperand(0) : N;
411 Offset = CurDAG->getRegister(0, MVT::i32);
412 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
416 // Thumb does not have [sp, r] address mode.
417 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
418 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
419 if ((LHSR && LHSR->getReg() == ARM::SP) ||
420 (RHSR && RHSR->getReg() == ARM::SP)) {
422 Offset = CurDAG->getRegister(0, MVT::i32);
423 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
427 // If the RHS is + imm5 * scale, fold into addr mode.
428 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
429 int RHSC = (int)RHS->getValue();
430 if ((RHSC & (Scale-1)) == 0) { // The constant is implicitly multiplied.
432 if (RHSC >= 0 && RHSC < 32) {
433 Base = N.getOperand(0);
434 Offset = CurDAG->getRegister(0, MVT::i32);
435 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
441 Base = N.getOperand(0);
442 Offset = N.getOperand(1);
443 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
447 bool ARMDAGToDAGISel::SelectThumbAddrModeS1(SDOperand Op, SDOperand N,
448 SDOperand &Base, SDOperand &OffImm,
450 return SelectThumbAddrModeRI5(Op, N, 1, Base, OffImm, Offset);
453 bool ARMDAGToDAGISel::SelectThumbAddrModeS2(SDOperand Op, SDOperand N,
454 SDOperand &Base, SDOperand &OffImm,
456 return SelectThumbAddrModeRI5(Op, N, 2, Base, OffImm, Offset);
459 bool ARMDAGToDAGISel::SelectThumbAddrModeS4(SDOperand Op, SDOperand N,
460 SDOperand &Base, SDOperand &OffImm,
462 return SelectThumbAddrModeRI5(Op, N, 4, Base, OffImm, Offset);
465 bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDOperand Op, SDOperand N,
466 SDOperand &Base, SDOperand &OffImm) {
467 if (N.getOpcode() == ISD::FrameIndex) {
468 int FI = cast<FrameIndexSDNode>(N)->getIndex();
469 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
470 OffImm = CurDAG->getTargetConstant(0, MVT::i32);
474 if (N.getOpcode() != ISD::ADD)
477 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
478 if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
479 (LHSR && LHSR->getReg() == ARM::SP)) {
480 // If the RHS is + imm8 * scale, fold into addr mode.
481 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
482 int RHSC = (int)RHS->getValue();
483 if ((RHSC & 3) == 0) { // The constant is implicitly multiplied.
485 if (RHSC >= 0 && RHSC < 256) {
486 Base = N.getOperand(0);
487 if (Base.getOpcode() == ISD::FrameIndex) {
488 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
489 Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
491 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
501 bool ARMDAGToDAGISel::SelectShifterOperandReg(SDOperand Op,
506 ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N);
508 // Don't match base register only case. That is matched to a separate
509 // lower complexity pattern with explicit register operand.
510 if (ShOpcVal == ARM_AM::no_shift) return false;
512 BaseReg = N.getOperand(0);
513 unsigned ShImmVal = 0;
514 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
515 ShReg = CurDAG->getRegister(0, MVT::i32);
516 ShImmVal = RHS->getValue() & 31;
518 ShReg = N.getOperand(1);
520 Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
525 /// getAL - Returns a ARMCC::AL immediate node.
526 static inline SDOperand getAL(SelectionDAG *CurDAG) {
527 return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
531 SDNode *ARMDAGToDAGISel::Select(SDOperand Op) {
534 if (N->isMachineOpcode())
535 return NULL; // Already selected.
537 switch (N->getOpcode()) {
539 case ISD::Constant: {
540 unsigned Val = cast<ConstantSDNode>(N)->getValue();
542 if (Subtarget->isThumb())
543 UseCP = (Val > 255 && // MOV
544 ~Val > 255 && // MOV + MVN
545 !ARM_AM::isThumbImmShiftedVal(Val)); // MOV + LSL
547 UseCP = (ARM_AM::getSOImmVal(Val) == -1 && // MOV
548 ARM_AM::getSOImmVal(~Val) == -1 && // MVN
549 !ARM_AM::isSOImmTwoPartVal(Val)); // two instrs.
552 CurDAG->getTargetConstantPool(ConstantInt::get(Type::Int32Ty, Val),
556 if (Subtarget->isThumb())
557 ResNode = CurDAG->getTargetNode(ARM::tLDRcp, MVT::i32, MVT::Other,
558 CPIdx, CurDAG->getEntryNode());
562 CurDAG->getRegister(0, MVT::i32),
563 CurDAG->getTargetConstant(0, MVT::i32),
565 CurDAG->getRegister(0, MVT::i32),
566 CurDAG->getEntryNode()
568 ResNode=CurDAG->getTargetNode(ARM::LDRcp, MVT::i32, MVT::Other, Ops, 6);
570 ReplaceUses(Op, SDOperand(ResNode, 0));
574 // Other cases are autogenerated.
577 case ISD::FrameIndex: {
578 // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
579 int FI = cast<FrameIndexSDNode>(N)->getIndex();
580 SDOperand TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
581 if (Subtarget->isThumb())
582 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI,
583 CurDAG->getTargetConstant(0, MVT::i32));
585 SDOperand Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
586 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
587 CurDAG->getRegister(0, MVT::i32) };
588 return CurDAG->SelectNodeTo(N, ARM::ADDri, MVT::i32, Ops, 5);
592 // Select add sp, c to tADDhirr.
593 SDOperand N0 = Op.getOperand(0);
594 SDOperand N1 = Op.getOperand(1);
595 RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(Op.getOperand(0));
596 RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(Op.getOperand(1));
597 if (LHSR && LHSR->getReg() == ARM::SP) {
599 std::swap(LHSR, RHSR);
601 if (RHSR && RHSR->getReg() == ARM::SP) {
604 return CurDAG->SelectNodeTo(N, ARM::tADDhirr, Op.getValueType(), N0, N1);
609 if (Subtarget->isThumb())
611 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
612 unsigned RHSV = C->getValue();
614 if (isPowerOf2_32(RHSV-1)) { // 2^n+1?
615 SDOperand V = Op.getOperand(0);
617 unsigned ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, Log2_32(RHSV-1));
618 SDOperand Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
619 CurDAG->getTargetConstant(ShImm, MVT::i32),
620 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
621 CurDAG->getRegister(0, MVT::i32) };
622 return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7);
624 if (isPowerOf2_32(RHSV+1)) { // 2^n-1?
625 SDOperand V = Op.getOperand(0);
627 unsigned ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, Log2_32(RHSV+1));
628 SDOperand Ops[] = { V, V, CurDAG->getRegister(0, MVT::i32),
629 CurDAG->getTargetConstant(ShImm, MVT::i32),
630 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
631 CurDAG->getRegister(0, MVT::i32) };
632 return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7);
637 AddToISelQueue(Op.getOperand(0));
638 return CurDAG->getTargetNode(ARM::FMRRD, MVT::i32, MVT::i32,
639 Op.getOperand(0), getAL(CurDAG),
640 CurDAG->getRegister(0, MVT::i32));
641 case ISD::UMUL_LOHI: {
642 AddToISelQueue(Op.getOperand(0));
643 AddToISelQueue(Op.getOperand(1));
644 SDOperand Ops[] = { Op.getOperand(0), Op.getOperand(1),
645 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
646 CurDAG->getRegister(0, MVT::i32) };
647 return CurDAG->getTargetNode(ARM::UMULL, MVT::i32, MVT::i32, Ops, 5);
649 case ISD::SMUL_LOHI: {
650 AddToISelQueue(Op.getOperand(0));
651 AddToISelQueue(Op.getOperand(1));
652 SDOperand Ops[] = { Op.getOperand(0), Op.getOperand(1),
653 getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
654 CurDAG->getRegister(0, MVT::i32) };
655 return CurDAG->getTargetNode(ARM::SMULL, MVT::i32, MVT::i32, Ops, 5);
658 LoadSDNode *LD = cast<LoadSDNode>(Op);
659 ISD::MemIndexedMode AM = LD->getAddressingMode();
660 MVT LoadedVT = LD->getMemoryVT();
661 if (AM != ISD::UNINDEXED) {
662 SDOperand Offset, AMOpc;
663 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
666 if (LoadedVT == MVT::i32 &&
667 SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
668 Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST;
670 } else if (LoadedVT == MVT::i16 &&
671 SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
673 Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
674 ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
675 : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
676 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
677 if (LD->getExtensionType() == ISD::SEXTLOAD) {
678 if (SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) {
680 Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
683 if (SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) {
685 Opcode = isPre ? ARM::LDRB_PRE : ARM::LDRB_POST;
691 SDOperand Chain = LD->getChain();
692 SDOperand Base = LD->getBasePtr();
693 AddToISelQueue(Chain);
694 AddToISelQueue(Base);
695 AddToISelQueue(Offset);
696 SDOperand Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
697 CurDAG->getRegister(0, MVT::i32), Chain };
698 return CurDAG->getTargetNode(Opcode, MVT::i32, MVT::i32,
702 // Other cases are autogenerated.
705 case ARMISD::BRCOND: {
706 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
707 // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
708 // Pattern complexity = 6 cost = 1 size = 0
710 // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
711 // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
712 // Pattern complexity = 6 cost = 1 size = 0
714 unsigned Opc = Subtarget->isThumb() ? ARM::tBcc : ARM::Bcc;
715 SDOperand Chain = Op.getOperand(0);
716 SDOperand N1 = Op.getOperand(1);
717 SDOperand N2 = Op.getOperand(2);
718 SDOperand N3 = Op.getOperand(3);
719 SDOperand InFlag = Op.getOperand(4);
720 assert(N1.getOpcode() == ISD::BasicBlock);
721 assert(N2.getOpcode() == ISD::Constant);
722 assert(N3.getOpcode() == ISD::Register);
724 AddToISelQueue(Chain);
726 AddToISelQueue(InFlag);
727 SDOperand Tmp2 = CurDAG->getTargetConstant(((unsigned)
728 cast<ConstantSDNode>(N2)->getValue()), MVT::i32);
729 SDOperand Ops[] = { N1, Tmp2, N3, Chain, InFlag };
730 SDNode *ResNode = CurDAG->getTargetNode(Opc, MVT::Other, MVT::Flag, Ops, 5);
731 Chain = SDOperand(ResNode, 0);
732 if (Op.Val->getNumValues() == 2) {
733 InFlag = SDOperand(ResNode, 1);
734 ReplaceUses(SDOperand(Op.Val, 1), InFlag);
736 ReplaceUses(SDOperand(Op.Val, 0), SDOperand(Chain.Val, Chain.ResNo));
740 bool isThumb = Subtarget->isThumb();
741 MVT VT = Op.getValueType();
742 SDOperand N0 = Op.getOperand(0);
743 SDOperand N1 = Op.getOperand(1);
744 SDOperand N2 = Op.getOperand(2);
745 SDOperand N3 = Op.getOperand(3);
746 SDOperand InFlag = Op.getOperand(4);
747 assert(N2.getOpcode() == ISD::Constant);
748 assert(N3.getOpcode() == ISD::Register);
750 // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
751 // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
752 // Pattern complexity = 18 cost = 1 size = 0
756 if (!isThumb && VT == MVT::i32 &&
757 SelectShifterOperandReg(Op, N1, CPTmp0, CPTmp1, CPTmp2)) {
759 AddToISelQueue(CPTmp0);
760 AddToISelQueue(CPTmp1);
761 AddToISelQueue(CPTmp2);
762 AddToISelQueue(InFlag);
763 SDOperand Tmp2 = CurDAG->getTargetConstant(((unsigned)
764 cast<ConstantSDNode>(N2)->getValue()), MVT::i32);
765 SDOperand Ops[] = { N0, CPTmp0, CPTmp1, CPTmp2, Tmp2, N3, InFlag };
766 return CurDAG->SelectNodeTo(Op.Val, ARM::MOVCCs, MVT::i32, Ops, 7);
769 // Pattern: (ARMcmov:i32 GPR:i32:$false,
770 // (imm:i32)<<P:Predicate_so_imm>><<X:so_imm_XFORM>>:$true,
772 // Emits: (MOVCCi:i32 GPR:i32:$false,
773 // (so_imm_XFORM:i32 (imm:i32):$true), (imm:i32):$cc)
774 // Pattern complexity = 10 cost = 1 size = 0
775 if (VT == MVT::i32 &&
776 N3.getOpcode() == ISD::Constant &&
777 Predicate_so_imm(N3.Val)) {
779 AddToISelQueue(InFlag);
780 SDOperand Tmp1 = CurDAG->getTargetConstant(((unsigned)
781 cast<ConstantSDNode>(N1)->getValue()), MVT::i32);
782 Tmp1 = Transform_so_imm_XFORM(Tmp1.Val);
783 SDOperand Tmp2 = CurDAG->getTargetConstant(((unsigned)
784 cast<ConstantSDNode>(N2)->getValue()), MVT::i32);
785 SDOperand Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
786 return CurDAG->SelectNodeTo(Op.Val, ARM::MOVCCi, MVT::i32, Ops, 5);
789 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
790 // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
791 // Pattern complexity = 6 cost = 1 size = 0
793 // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
794 // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
795 // Pattern complexity = 6 cost = 11 size = 0
797 // Also FCPYScc and FCPYDcc.
800 AddToISelQueue(InFlag);
801 SDOperand Tmp2 = CurDAG->getTargetConstant(((unsigned)
802 cast<ConstantSDNode>(N2)->getValue()), MVT::i32);
803 SDOperand Ops[] = { N0, N1, Tmp2, N3, InFlag };
805 switch (VT.getSimpleVT()) {
806 default: assert(false && "Illegal conditional move type!");
809 Opc = isThumb ? ARM::tMOVCCr : ARM::MOVCCr;
818 return CurDAG->SelectNodeTo(Op.Val, Opc, VT, Ops, 5);
821 MVT VT = Op.getValueType();
822 SDOperand N0 = Op.getOperand(0);
823 SDOperand N1 = Op.getOperand(1);
824 SDOperand N2 = Op.getOperand(2);
825 SDOperand N3 = Op.getOperand(3);
826 SDOperand InFlag = Op.getOperand(4);
827 assert(N2.getOpcode() == ISD::Constant);
828 assert(N3.getOpcode() == ISD::Register);
832 AddToISelQueue(InFlag);
833 SDOperand Tmp2 = CurDAG->getTargetConstant(((unsigned)
834 cast<ConstantSDNode>(N2)->getValue()), MVT::i32);
835 SDOperand Ops[] = { N0, N1, Tmp2, N3, InFlag };
837 switch (VT.getSimpleVT()) {
838 default: assert(false && "Illegal conditional move type!");
847 return CurDAG->SelectNodeTo(Op.Val, Opc, VT, Ops, 5);
850 return SelectCode(Op);
853 /// createARMISelDag - This pass converts a legalized DAG into a
854 /// ARM-specific DAG, ready for instruction scheduling.
856 FunctionPass *llvm::createARMISelDag(ARMTargetMachine &TM) {
857 return new ARMDAGToDAGISel(TM);