1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "arm-isel"
17 #include "ARMCallingConv.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMISelLowering.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMPerfectShuffle.h"
22 #include "ARMRegisterInfo.h"
23 #include "ARMSubtarget.h"
24 #include "ARMTargetMachine.h"
25 #include "ARMTargetObjectFile.h"
26 #include "MCTargetDesc/ARMAddressingModes.h"
27 #include "llvm/CallingConv.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Function.h"
30 #include "llvm/GlobalValue.h"
31 #include "llvm/Instruction.h"
32 #include "llvm/Instructions.h"
33 #include "llvm/Intrinsics.h"
34 #include "llvm/Type.h"
35 #include "llvm/CodeGen/CallingConvLower.h"
36 #include "llvm/CodeGen/IntrinsicLowering.h"
37 #include "llvm/CodeGen/MachineBasicBlock.h"
38 #include "llvm/CodeGen/MachineFrameInfo.h"
39 #include "llvm/CodeGen/MachineFunction.h"
40 #include "llvm/CodeGen/MachineInstrBuilder.h"
41 #include "llvm/CodeGen/MachineModuleInfo.h"
42 #include "llvm/CodeGen/MachineRegisterInfo.h"
43 #include "llvm/CodeGen/PseudoSourceValue.h"
44 #include "llvm/CodeGen/SelectionDAG.h"
45 #include "llvm/MC/MCSectionMachO.h"
46 #include "llvm/Target/TargetOptions.h"
47 #include "llvm/ADT/VectorExtras.h"
48 #include "llvm/ADT/StringExtras.h"
49 #include "llvm/ADT/Statistic.h"
50 #include "llvm/Support/CommandLine.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/MathExtras.h"
53 #include "llvm/Support/raw_ostream.h"
57 STATISTIC(NumTailCalls, "Number of tail calls");
58 STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt");
60 // This option should go away when tail calls fully work.
62 EnableARMTailCalls("arm-tail-calls", cl::Hidden,
63 cl::desc("Generate tail calls (TEMPORARY OPTION)."),
67 EnableARMLongCalls("arm-long-calls", cl::Hidden,
68 cl::desc("Generate calls via indirect call instructions"),
72 ARMInterworking("arm-interworking", cl::Hidden,
73 cl::desc("Enable / disable ARM interworking (for debugging only)"),
77 class ARMCCState : public CCState {
79 ARMCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
80 const TargetMachine &TM, SmallVector<CCValAssign, 16> &locs,
81 LLVMContext &C, ParmContext PC)
82 : CCState(CC, isVarArg, MF, TM, locs, C) {
83 assert(((PC == Call) || (PC == Prologue)) &&
84 "ARMCCState users must specify whether their context is call"
85 "or prologue generation.");
91 // The APCS parameter registers.
92 static const unsigned GPRArgRegs[] = {
93 ARM::R0, ARM::R1, ARM::R2, ARM::R3
96 void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
97 EVT PromotedBitwiseVT) {
98 if (VT != PromotedLdStVT) {
99 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
100 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
101 PromotedLdStVT.getSimpleVT());
103 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
104 AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
105 PromotedLdStVT.getSimpleVT());
108 EVT ElemTy = VT.getVectorElementType();
109 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
110 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom);
111 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
112 if (ElemTy != MVT::i32) {
113 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
114 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand);
115 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand);
116 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand);
118 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
119 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
120 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
121 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Legal);
122 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
123 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
124 if (VT.isInteger()) {
125 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
126 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
127 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
128 setLoadExtAction(ISD::SEXTLOAD, VT.getSimpleVT(), Expand);
129 setLoadExtAction(ISD::ZEXTLOAD, VT.getSimpleVT(), Expand);
130 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
131 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
132 setTruncStoreAction(VT.getSimpleVT(),
133 (MVT::SimpleValueType)InnerVT, Expand);
135 setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand);
137 // Promote all bit-wise operations.
138 if (VT.isInteger() && VT != PromotedBitwiseVT) {
139 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
140 AddPromotedToType (ISD::AND, VT.getSimpleVT(),
141 PromotedBitwiseVT.getSimpleVT());
142 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
143 AddPromotedToType (ISD::OR, VT.getSimpleVT(),
144 PromotedBitwiseVT.getSimpleVT());
145 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
146 AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
147 PromotedBitwiseVT.getSimpleVT());
150 // Neon does not support vector divide/remainder operations.
151 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
152 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
153 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand);
154 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
155 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
156 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
159 void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
160 addRegisterClass(VT, ARM::DPRRegisterClass);
161 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
164 void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
165 addRegisterClass(VT, ARM::QPRRegisterClass);
166 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
169 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
170 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
171 return new TargetLoweringObjectFileMachO();
173 return new ARMElfTargetObjectFile();
176 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
177 : TargetLowering(TM, createTLOF(TM)) {
178 Subtarget = &TM.getSubtarget<ARMSubtarget>();
179 RegInfo = TM.getRegisterInfo();
180 Itins = TM.getInstrItineraryData();
182 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
184 if (Subtarget->isTargetDarwin()) {
185 // Uses VFP for Thumb libfuncs if available.
186 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
187 // Single-precision floating-point arithmetic.
188 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
189 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
190 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
191 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
193 // Double-precision floating-point arithmetic.
194 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
195 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
196 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
197 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
199 // Single-precision comparisons.
200 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
201 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
202 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
203 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
204 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
205 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
206 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
207 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
209 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
210 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
211 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
212 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
213 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
214 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
215 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
216 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
218 // Double-precision comparisons.
219 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
220 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
221 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
222 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
223 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
224 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
225 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
226 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
228 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
229 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
230 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
231 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
232 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
233 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
234 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
235 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
237 // Floating-point to integer conversions.
238 // i64 conversions are done via library routines even when generating VFP
239 // instructions, so use the same ones.
240 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
241 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
242 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
243 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
245 // Conversions between floating types.
246 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
247 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
249 // Integer to floating-point conversions.
250 // i64 conversions are done via library routines even when generating VFP
251 // instructions, so use the same ones.
252 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
253 // e.g., __floatunsidf vs. __floatunssidfvfp.
254 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
255 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
256 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
257 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
261 // These libcalls are not available in 32-bit.
262 setLibcallName(RTLIB::SHL_I128, 0);
263 setLibcallName(RTLIB::SRL_I128, 0);
264 setLibcallName(RTLIB::SRA_I128, 0);
266 if (Subtarget->isAAPCS_ABI()) {
267 // Double-precision floating-point arithmetic helper functions
268 // RTABI chapter 4.1.2, Table 2
269 setLibcallName(RTLIB::ADD_F64, "__aeabi_dadd");
270 setLibcallName(RTLIB::DIV_F64, "__aeabi_ddiv");
271 setLibcallName(RTLIB::MUL_F64, "__aeabi_dmul");
272 setLibcallName(RTLIB::SUB_F64, "__aeabi_dsub");
273 setLibcallCallingConv(RTLIB::ADD_F64, CallingConv::ARM_AAPCS);
274 setLibcallCallingConv(RTLIB::DIV_F64, CallingConv::ARM_AAPCS);
275 setLibcallCallingConv(RTLIB::MUL_F64, CallingConv::ARM_AAPCS);
276 setLibcallCallingConv(RTLIB::SUB_F64, CallingConv::ARM_AAPCS);
278 // Double-precision floating-point comparison helper functions
279 // RTABI chapter 4.1.2, Table 3
280 setLibcallName(RTLIB::OEQ_F64, "__aeabi_dcmpeq");
281 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
282 setLibcallName(RTLIB::UNE_F64, "__aeabi_dcmpeq");
283 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETEQ);
284 setLibcallName(RTLIB::OLT_F64, "__aeabi_dcmplt");
285 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
286 setLibcallName(RTLIB::OLE_F64, "__aeabi_dcmple");
287 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
288 setLibcallName(RTLIB::OGE_F64, "__aeabi_dcmpge");
289 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
290 setLibcallName(RTLIB::OGT_F64, "__aeabi_dcmpgt");
291 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
292 setLibcallName(RTLIB::UO_F64, "__aeabi_dcmpun");
293 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
294 setLibcallName(RTLIB::O_F64, "__aeabi_dcmpun");
295 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
296 setLibcallCallingConv(RTLIB::OEQ_F64, CallingConv::ARM_AAPCS);
297 setLibcallCallingConv(RTLIB::UNE_F64, CallingConv::ARM_AAPCS);
298 setLibcallCallingConv(RTLIB::OLT_F64, CallingConv::ARM_AAPCS);
299 setLibcallCallingConv(RTLIB::OLE_F64, CallingConv::ARM_AAPCS);
300 setLibcallCallingConv(RTLIB::OGE_F64, CallingConv::ARM_AAPCS);
301 setLibcallCallingConv(RTLIB::OGT_F64, CallingConv::ARM_AAPCS);
302 setLibcallCallingConv(RTLIB::UO_F64, CallingConv::ARM_AAPCS);
303 setLibcallCallingConv(RTLIB::O_F64, CallingConv::ARM_AAPCS);
305 // Single-precision floating-point arithmetic helper functions
306 // RTABI chapter 4.1.2, Table 4
307 setLibcallName(RTLIB::ADD_F32, "__aeabi_fadd");
308 setLibcallName(RTLIB::DIV_F32, "__aeabi_fdiv");
309 setLibcallName(RTLIB::MUL_F32, "__aeabi_fmul");
310 setLibcallName(RTLIB::SUB_F32, "__aeabi_fsub");
311 setLibcallCallingConv(RTLIB::ADD_F32, CallingConv::ARM_AAPCS);
312 setLibcallCallingConv(RTLIB::DIV_F32, CallingConv::ARM_AAPCS);
313 setLibcallCallingConv(RTLIB::MUL_F32, CallingConv::ARM_AAPCS);
314 setLibcallCallingConv(RTLIB::SUB_F32, CallingConv::ARM_AAPCS);
316 // Single-precision floating-point comparison helper functions
317 // RTABI chapter 4.1.2, Table 5
318 setLibcallName(RTLIB::OEQ_F32, "__aeabi_fcmpeq");
319 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
320 setLibcallName(RTLIB::UNE_F32, "__aeabi_fcmpeq");
321 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETEQ);
322 setLibcallName(RTLIB::OLT_F32, "__aeabi_fcmplt");
323 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
324 setLibcallName(RTLIB::OLE_F32, "__aeabi_fcmple");
325 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
326 setLibcallName(RTLIB::OGE_F32, "__aeabi_fcmpge");
327 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
328 setLibcallName(RTLIB::OGT_F32, "__aeabi_fcmpgt");
329 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
330 setLibcallName(RTLIB::UO_F32, "__aeabi_fcmpun");
331 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
332 setLibcallName(RTLIB::O_F32, "__aeabi_fcmpun");
333 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
334 setLibcallCallingConv(RTLIB::OEQ_F32, CallingConv::ARM_AAPCS);
335 setLibcallCallingConv(RTLIB::UNE_F32, CallingConv::ARM_AAPCS);
336 setLibcallCallingConv(RTLIB::OLT_F32, CallingConv::ARM_AAPCS);
337 setLibcallCallingConv(RTLIB::OLE_F32, CallingConv::ARM_AAPCS);
338 setLibcallCallingConv(RTLIB::OGE_F32, CallingConv::ARM_AAPCS);
339 setLibcallCallingConv(RTLIB::OGT_F32, CallingConv::ARM_AAPCS);
340 setLibcallCallingConv(RTLIB::UO_F32, CallingConv::ARM_AAPCS);
341 setLibcallCallingConv(RTLIB::O_F32, CallingConv::ARM_AAPCS);
343 // Floating-point to integer conversions.
344 // RTABI chapter 4.1.2, Table 6
345 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz");
346 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz");
347 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz");
348 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz");
349 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz");
350 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz");
351 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz");
352 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz");
353 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I32, CallingConv::ARM_AAPCS);
354 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I32, CallingConv::ARM_AAPCS);
355 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I64, CallingConv::ARM_AAPCS);
356 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::ARM_AAPCS);
357 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I32, CallingConv::ARM_AAPCS);
358 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I32, CallingConv::ARM_AAPCS);
359 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I64, CallingConv::ARM_AAPCS);
360 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::ARM_AAPCS);
362 // Conversions between floating types.
363 // RTABI chapter 4.1.2, Table 7
364 setLibcallName(RTLIB::FPROUND_F64_F32, "__aeabi_d2f");
365 setLibcallName(RTLIB::FPEXT_F32_F64, "__aeabi_f2d");
366 setLibcallCallingConv(RTLIB::FPROUND_F64_F32, CallingConv::ARM_AAPCS);
367 setLibcallCallingConv(RTLIB::FPEXT_F32_F64, CallingConv::ARM_AAPCS);
369 // Integer to floating-point conversions.
370 // RTABI chapter 4.1.2, Table 8
371 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d");
372 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d");
373 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d");
374 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d");
375 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f");
376 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f");
377 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f");
378 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f");
379 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
380 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
381 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
382 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
383 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
384 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
385 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
386 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
388 // Long long helper functions
389 // RTABI chapter 4.2, Table 9
390 setLibcallName(RTLIB::MUL_I64, "__aeabi_lmul");
391 setLibcallName(RTLIB::SDIV_I64, "__aeabi_ldivmod");
392 setLibcallName(RTLIB::UDIV_I64, "__aeabi_uldivmod");
393 setLibcallName(RTLIB::SHL_I64, "__aeabi_llsl");
394 setLibcallName(RTLIB::SRL_I64, "__aeabi_llsr");
395 setLibcallName(RTLIB::SRA_I64, "__aeabi_lasr");
396 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::ARM_AAPCS);
397 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::ARM_AAPCS);
398 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::ARM_AAPCS);
399 setLibcallCallingConv(RTLIB::SHL_I64, CallingConv::ARM_AAPCS);
400 setLibcallCallingConv(RTLIB::SRL_I64, CallingConv::ARM_AAPCS);
401 setLibcallCallingConv(RTLIB::SRA_I64, CallingConv::ARM_AAPCS);
403 // Integer division functions
404 // RTABI chapter 4.3.1
405 setLibcallName(RTLIB::SDIV_I8, "__aeabi_idiv");
406 setLibcallName(RTLIB::SDIV_I16, "__aeabi_idiv");
407 setLibcallName(RTLIB::SDIV_I32, "__aeabi_idiv");
408 setLibcallName(RTLIB::UDIV_I8, "__aeabi_uidiv");
409 setLibcallName(RTLIB::UDIV_I16, "__aeabi_uidiv");
410 setLibcallName(RTLIB::UDIV_I32, "__aeabi_uidiv");
411 setLibcallCallingConv(RTLIB::SDIV_I8, CallingConv::ARM_AAPCS);
412 setLibcallCallingConv(RTLIB::SDIV_I16, CallingConv::ARM_AAPCS);
413 setLibcallCallingConv(RTLIB::SDIV_I32, CallingConv::ARM_AAPCS);
414 setLibcallCallingConv(RTLIB::UDIV_I8, CallingConv::ARM_AAPCS);
415 setLibcallCallingConv(RTLIB::UDIV_I16, CallingConv::ARM_AAPCS);
416 setLibcallCallingConv(RTLIB::UDIV_I32, CallingConv::ARM_AAPCS);
419 // RTABI chapter 4.3.4
420 setLibcallName(RTLIB::MEMCPY, "__aeabi_memcpy");
421 setLibcallName(RTLIB::MEMMOVE, "__aeabi_memmove");
422 setLibcallName(RTLIB::MEMSET, "__aeabi_memset");
425 // Use divmod compiler-rt calls for iOS 5.0 and later.
426 if (Subtarget->getTargetTriple().getOS() == Triple::IOS &&
427 !Subtarget->getTargetTriple().isOSVersionLT(5, 0)) {
428 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
429 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
432 if (Subtarget->isThumb1Only())
433 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
435 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
436 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
437 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
438 if (!Subtarget->isFPOnlySP())
439 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
441 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
444 if (Subtarget->hasNEON()) {
445 addDRTypeForNEON(MVT::v2f32);
446 addDRTypeForNEON(MVT::v8i8);
447 addDRTypeForNEON(MVT::v4i16);
448 addDRTypeForNEON(MVT::v2i32);
449 addDRTypeForNEON(MVT::v1i64);
451 addQRTypeForNEON(MVT::v4f32);
452 addQRTypeForNEON(MVT::v2f64);
453 addQRTypeForNEON(MVT::v16i8);
454 addQRTypeForNEON(MVT::v8i16);
455 addQRTypeForNEON(MVT::v4i32);
456 addQRTypeForNEON(MVT::v2i64);
458 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
459 // neither Neon nor VFP support any arithmetic operations on it.
460 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
461 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
462 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
463 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
464 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
465 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
466 setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
467 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
468 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
469 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
470 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
471 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
472 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
473 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
474 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
475 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
476 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
477 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
478 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
479 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
480 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
481 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
482 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
483 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
485 setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand);
487 // Neon does not support some operations on v1i64 and v2i64 types.
488 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
489 // Custom handling for some quad-vector types to detect VMULL.
490 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
491 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
492 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
493 // Custom handling for some vector types to avoid expensive expansions
494 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
495 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
496 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
497 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
498 setOperationAction(ISD::SETCC, MVT::v1i64, Expand);
499 setOperationAction(ISD::SETCC, MVT::v2i64, Expand);
500 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
501 // a destination type that is wider than the source.
502 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
503 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
505 setTargetDAGCombine(ISD::INTRINSIC_VOID);
506 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
507 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
508 setTargetDAGCombine(ISD::SHL);
509 setTargetDAGCombine(ISD::SRL);
510 setTargetDAGCombine(ISD::SRA);
511 setTargetDAGCombine(ISD::SIGN_EXTEND);
512 setTargetDAGCombine(ISD::ZERO_EXTEND);
513 setTargetDAGCombine(ISD::ANY_EXTEND);
514 setTargetDAGCombine(ISD::SELECT_CC);
515 setTargetDAGCombine(ISD::BUILD_VECTOR);
516 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
517 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
518 setTargetDAGCombine(ISD::STORE);
519 setTargetDAGCombine(ISD::FP_TO_SINT);
520 setTargetDAGCombine(ISD::FP_TO_UINT);
521 setTargetDAGCombine(ISD::FDIV);
524 computeRegisterProperties();
526 // ARM does not have f32 extending load.
527 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
529 // ARM does not have i1 sign extending load.
530 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
532 // ARM supports all 4 flavors of integer indexed load / store.
533 if (!Subtarget->isThumb1Only()) {
534 for (unsigned im = (unsigned)ISD::PRE_INC;
535 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
536 setIndexedLoadAction(im, MVT::i1, Legal);
537 setIndexedLoadAction(im, MVT::i8, Legal);
538 setIndexedLoadAction(im, MVT::i16, Legal);
539 setIndexedLoadAction(im, MVT::i32, Legal);
540 setIndexedStoreAction(im, MVT::i1, Legal);
541 setIndexedStoreAction(im, MVT::i8, Legal);
542 setIndexedStoreAction(im, MVT::i16, Legal);
543 setIndexedStoreAction(im, MVT::i32, Legal);
547 // i64 operation support.
548 setOperationAction(ISD::MUL, MVT::i64, Expand);
549 setOperationAction(ISD::MULHU, MVT::i32, Expand);
550 if (Subtarget->isThumb1Only()) {
551 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
552 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
554 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
555 || (Subtarget->isThumb2() && !Subtarget->hasThumb2DSP()))
556 setOperationAction(ISD::MULHS, MVT::i32, Expand);
558 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
559 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
560 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
561 setOperationAction(ISD::SRL, MVT::i64, Custom);
562 setOperationAction(ISD::SRA, MVT::i64, Custom);
564 if (!Subtarget->isThumb1Only()) {
565 // FIXME: We should do this for Thumb1 as well.
566 setOperationAction(ISD::ADDC, MVT::i32, Custom);
567 setOperationAction(ISD::ADDE, MVT::i32, Custom);
568 setOperationAction(ISD::SUBC, MVT::i32, Custom);
569 setOperationAction(ISD::SUBE, MVT::i32, Custom);
572 // ARM does not have ROTL.
573 setOperationAction(ISD::ROTL, MVT::i32, Expand);
574 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
575 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
576 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
577 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
579 // Only ARMv6 has BSWAP.
580 if (!Subtarget->hasV6Ops())
581 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
583 // These are expanded into libcalls.
584 if (!Subtarget->hasDivide() || !Subtarget->isThumb2()) {
585 // v7M has a hardware divider
586 setOperationAction(ISD::SDIV, MVT::i32, Expand);
587 setOperationAction(ISD::UDIV, MVT::i32, Expand);
589 setOperationAction(ISD::SREM, MVT::i32, Expand);
590 setOperationAction(ISD::UREM, MVT::i32, Expand);
591 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
592 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
594 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
595 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
596 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
597 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
598 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
600 setOperationAction(ISD::TRAP, MVT::Other, Legal);
602 // Use the default implementation.
603 setOperationAction(ISD::VASTART, MVT::Other, Custom);
604 setOperationAction(ISD::VAARG, MVT::Other, Expand);
605 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
606 setOperationAction(ISD::VAEND, MVT::Other, Expand);
607 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
608 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
609 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
610 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
611 setExceptionPointerRegister(ARM::R0);
612 setExceptionSelectorRegister(ARM::R1);
614 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
615 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
616 // the default expansion.
617 // FIXME: This should be checking for v6k, not just v6.
618 if (Subtarget->hasDataBarrier() ||
619 (Subtarget->hasV6Ops() && !Subtarget->isThumb())) {
620 // membarrier needs custom lowering; the rest are legal and handled
622 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
623 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
624 // Custom lowering for 64-bit ops
625 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
626 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
627 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
628 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
629 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
630 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
631 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
632 // Automatically insert fences (dmb ist) around ATOMIC_SWAP etc.
633 setInsertFencesForAtomic(true);
635 // Set them all for expansion, which will force libcalls.
636 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
637 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
638 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
639 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
640 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
641 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
642 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
643 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
644 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
645 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
646 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
647 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
648 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
649 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
650 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the
651 // Unordered/Monotonic case.
652 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
653 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
654 // Since the libcalls include locking, fold in the fences
655 setShouldFoldAtomicFences(true);
658 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
660 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
661 if (!Subtarget->hasV6Ops()) {
662 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
663 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
665 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
667 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
668 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
669 // iff target supports vfp2.
670 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
671 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
674 // We want to custom lower some of our intrinsics.
675 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
676 if (Subtarget->isTargetDarwin()) {
677 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
678 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
679 setOperationAction(ISD::EH_SJLJ_DISPATCHSETUP, MVT::Other, Custom);
680 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
683 setOperationAction(ISD::SETCC, MVT::i32, Expand);
684 setOperationAction(ISD::SETCC, MVT::f32, Expand);
685 setOperationAction(ISD::SETCC, MVT::f64, Expand);
686 setOperationAction(ISD::SELECT, MVT::i32, Custom);
687 setOperationAction(ISD::SELECT, MVT::f32, Custom);
688 setOperationAction(ISD::SELECT, MVT::f64, Custom);
689 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
690 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
691 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
693 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
694 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
695 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
696 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
697 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
699 // We don't support sin/cos/fmod/copysign/pow
700 setOperationAction(ISD::FSIN, MVT::f64, Expand);
701 setOperationAction(ISD::FSIN, MVT::f32, Expand);
702 setOperationAction(ISD::FCOS, MVT::f32, Expand);
703 setOperationAction(ISD::FCOS, MVT::f64, Expand);
704 setOperationAction(ISD::FREM, MVT::f64, Expand);
705 setOperationAction(ISD::FREM, MVT::f32, Expand);
706 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
707 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
708 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
710 setOperationAction(ISD::FPOW, MVT::f64, Expand);
711 setOperationAction(ISD::FPOW, MVT::f32, Expand);
713 setOperationAction(ISD::FMA, MVT::f64, Expand);
714 setOperationAction(ISD::FMA, MVT::f32, Expand);
716 // Various VFP goodness
717 if (!UseSoftFloat && !Subtarget->isThumb1Only()) {
718 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
719 if (Subtarget->hasVFP2()) {
720 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
721 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
722 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
723 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
725 // Special handling for half-precision FP.
726 if (!Subtarget->hasFP16()) {
727 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
728 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand);
732 // We have target-specific dag combine patterns for the following nodes:
733 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
734 setTargetDAGCombine(ISD::ADD);
735 setTargetDAGCombine(ISD::SUB);
736 setTargetDAGCombine(ISD::MUL);
738 if (Subtarget->hasV6T2Ops() || Subtarget->hasNEON())
739 setTargetDAGCombine(ISD::OR);
740 if (Subtarget->hasNEON())
741 setTargetDAGCombine(ISD::AND);
743 setStackPointerRegisterToSaveRestore(ARM::SP);
745 if (UseSoftFloat || Subtarget->isThumb1Only() || !Subtarget->hasVFP2())
746 setSchedulingPreference(Sched::RegPressure);
748 setSchedulingPreference(Sched::Hybrid);
750 //// temporary - rewrite interface to use type
751 maxStoresPerMemcpy = maxStoresPerMemcpyOptSize = 1;
753 // On ARM arguments smaller than 4 bytes are extended, so all arguments
754 // are at least 4 bytes aligned.
755 setMinStackArgumentAlignment(4);
757 benefitFromCodePlacementOpt = true;
759 setMinFunctionAlignment(Subtarget->isThumb() ? 1 : 2);
762 // FIXME: It might make sense to define the representative register class as the
763 // nearest super-register that has a non-null superset. For example, DPR_VFP2 is
764 // a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
765 // SPR's representative would be DPR_VFP2. This should work well if register
766 // pressure tracking were modified such that a register use would increment the
767 // pressure of the register class's representative and all of it's super
768 // classes' representatives transitively. We have not implemented this because
769 // of the difficulty prior to coalescing of modeling operand register classes
770 // due to the common occurrence of cross class copies and subregister insertions
772 std::pair<const TargetRegisterClass*, uint8_t>
773 ARMTargetLowering::findRepresentativeClass(EVT VT) const{
774 const TargetRegisterClass *RRC = 0;
776 switch (VT.getSimpleVT().SimpleTy) {
778 return TargetLowering::findRepresentativeClass(VT);
779 // Use DPR as representative register class for all floating point
780 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
781 // the cost is 1 for both f32 and f64.
782 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
783 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
784 RRC = ARM::DPRRegisterClass;
785 // When NEON is used for SP, only half of the register file is available
786 // because operations that define both SP and DP results will be constrained
787 // to the VFP2 class (D0-D15). We currently model this constraint prior to
788 // coalescing by double-counting the SP regs. See the FIXME above.
789 if (Subtarget->useNEONForSinglePrecisionFP())
792 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
793 case MVT::v4f32: case MVT::v2f64:
794 RRC = ARM::DPRRegisterClass;
798 RRC = ARM::DPRRegisterClass;
802 RRC = ARM::DPRRegisterClass;
806 return std::make_pair(RRC, Cost);
809 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
812 case ARMISD::Wrapper: return "ARMISD::Wrapper";
813 case ARMISD::WrapperDYN: return "ARMISD::WrapperDYN";
814 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
815 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
816 case ARMISD::CALL: return "ARMISD::CALL";
817 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
818 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
819 case ARMISD::tCALL: return "ARMISD::tCALL";
820 case ARMISD::BRCOND: return "ARMISD::BRCOND";
821 case ARMISD::BR_JT: return "ARMISD::BR_JT";
822 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
823 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
824 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
825 case ARMISD::CMP: return "ARMISD::CMP";
826 case ARMISD::CMPZ: return "ARMISD::CMPZ";
827 case ARMISD::CMPFP: return "ARMISD::CMPFP";
828 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
829 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
830 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
831 case ARMISD::CMOV: return "ARMISD::CMOV";
833 case ARMISD::RBIT: return "ARMISD::RBIT";
835 case ARMISD::FTOSI: return "ARMISD::FTOSI";
836 case ARMISD::FTOUI: return "ARMISD::FTOUI";
837 case ARMISD::SITOF: return "ARMISD::SITOF";
838 case ARMISD::UITOF: return "ARMISD::UITOF";
840 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
841 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
842 case ARMISD::RRX: return "ARMISD::RRX";
844 case ARMISD::ADDC: return "ARMISD::ADDC";
845 case ARMISD::ADDE: return "ARMISD::ADDE";
846 case ARMISD::SUBC: return "ARMISD::SUBC";
847 case ARMISD::SUBE: return "ARMISD::SUBE";
849 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
850 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
852 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
853 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
854 case ARMISD::EH_SJLJ_DISPATCHSETUP:return "ARMISD::EH_SJLJ_DISPATCHSETUP";
856 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
858 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
860 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
862 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER";
863 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
865 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
867 case ARMISD::VCEQ: return "ARMISD::VCEQ";
868 case ARMISD::VCEQZ: return "ARMISD::VCEQZ";
869 case ARMISD::VCGE: return "ARMISD::VCGE";
870 case ARMISD::VCGEZ: return "ARMISD::VCGEZ";
871 case ARMISD::VCLEZ: return "ARMISD::VCLEZ";
872 case ARMISD::VCGEU: return "ARMISD::VCGEU";
873 case ARMISD::VCGT: return "ARMISD::VCGT";
874 case ARMISD::VCGTZ: return "ARMISD::VCGTZ";
875 case ARMISD::VCLTZ: return "ARMISD::VCLTZ";
876 case ARMISD::VCGTU: return "ARMISD::VCGTU";
877 case ARMISD::VTST: return "ARMISD::VTST";
879 case ARMISD::VSHL: return "ARMISD::VSHL";
880 case ARMISD::VSHRs: return "ARMISD::VSHRs";
881 case ARMISD::VSHRu: return "ARMISD::VSHRu";
882 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
883 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
884 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
885 case ARMISD::VSHRN: return "ARMISD::VSHRN";
886 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
887 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
888 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
889 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
890 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
891 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
892 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
893 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
894 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
895 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
896 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
897 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
898 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
899 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
900 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
901 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
902 case ARMISD::VDUP: return "ARMISD::VDUP";
903 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
904 case ARMISD::VEXT: return "ARMISD::VEXT";
905 case ARMISD::VREV64: return "ARMISD::VREV64";
906 case ARMISD::VREV32: return "ARMISD::VREV32";
907 case ARMISD::VREV16: return "ARMISD::VREV16";
908 case ARMISD::VZIP: return "ARMISD::VZIP";
909 case ARMISD::VUZP: return "ARMISD::VUZP";
910 case ARMISD::VTRN: return "ARMISD::VTRN";
911 case ARMISD::VTBL1: return "ARMISD::VTBL1";
912 case ARMISD::VTBL2: return "ARMISD::VTBL2";
913 case ARMISD::VMULLs: return "ARMISD::VMULLs";
914 case ARMISD::VMULLu: return "ARMISD::VMULLu";
915 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
916 case ARMISD::FMAX: return "ARMISD::FMAX";
917 case ARMISD::FMIN: return "ARMISD::FMIN";
918 case ARMISD::BFI: return "ARMISD::BFI";
919 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
920 case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
921 case ARMISD::VBSL: return "ARMISD::VBSL";
922 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
923 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
924 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
925 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD";
926 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD";
927 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD";
928 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD";
929 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD";
930 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD";
931 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD";
932 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD";
933 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD";
934 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD";
935 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD";
936 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD";
937 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD";
938 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD";
939 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD";
940 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD";
941 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD";
945 EVT ARMTargetLowering::getSetCCResultType(EVT VT) const {
946 if (!VT.isVector()) return getPointerTy();
947 return VT.changeVectorElementTypeToInteger();
950 /// getRegClassFor - Return the register class that should be used for the
951 /// specified value type.
952 TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const {
953 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
954 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
955 // load / store 4 to 8 consecutive D registers.
956 if (Subtarget->hasNEON()) {
957 if (VT == MVT::v4i64)
958 return ARM::QQPRRegisterClass;
959 else if (VT == MVT::v8i64)
960 return ARM::QQQQPRRegisterClass;
962 return TargetLowering::getRegClassFor(VT);
965 // Create a fast isel object.
967 ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
968 return ARM::createFastISel(funcInfo);
971 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
972 /// be used for loads / stores from the global.
973 unsigned ARMTargetLowering::getMaximalGlobalOffset() const {
974 return (Subtarget->isThumb1Only() ? 127 : 4095);
977 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
978 unsigned NumVals = N->getNumValues();
980 return Sched::RegPressure;
982 for (unsigned i = 0; i != NumVals; ++i) {
983 EVT VT = N->getValueType(i);
984 if (VT == MVT::Glue || VT == MVT::Other)
986 if (VT.isFloatingPoint() || VT.isVector())
987 return Sched::Latency;
990 if (!N->isMachineOpcode())
991 return Sched::RegPressure;
993 // Load are scheduled for latency even if there instruction itinerary
995 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
996 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
998 if (MCID.getNumDefs() == 0)
999 return Sched::RegPressure;
1000 if (!Itins->isEmpty() &&
1001 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
1002 return Sched::Latency;
1004 return Sched::RegPressure;
1007 //===----------------------------------------------------------------------===//
1009 //===----------------------------------------------------------------------===//
1011 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
1012 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
1014 default: llvm_unreachable("Unknown condition code!");
1015 case ISD::SETNE: return ARMCC::NE;
1016 case ISD::SETEQ: return ARMCC::EQ;
1017 case ISD::SETGT: return ARMCC::GT;
1018 case ISD::SETGE: return ARMCC::GE;
1019 case ISD::SETLT: return ARMCC::LT;
1020 case ISD::SETLE: return ARMCC::LE;
1021 case ISD::SETUGT: return ARMCC::HI;
1022 case ISD::SETUGE: return ARMCC::HS;
1023 case ISD::SETULT: return ARMCC::LO;
1024 case ISD::SETULE: return ARMCC::LS;
1028 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
1029 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
1030 ARMCC::CondCodes &CondCode2) {
1031 CondCode2 = ARMCC::AL;
1033 default: llvm_unreachable("Unknown FP condition!");
1035 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
1037 case ISD::SETOGT: CondCode = ARMCC::GT; break;
1039 case ISD::SETOGE: CondCode = ARMCC::GE; break;
1040 case ISD::SETOLT: CondCode = ARMCC::MI; break;
1041 case ISD::SETOLE: CondCode = ARMCC::LS; break;
1042 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
1043 case ISD::SETO: CondCode = ARMCC::VC; break;
1044 case ISD::SETUO: CondCode = ARMCC::VS; break;
1045 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
1046 case ISD::SETUGT: CondCode = ARMCC::HI; break;
1047 case ISD::SETUGE: CondCode = ARMCC::PL; break;
1049 case ISD::SETULT: CondCode = ARMCC::LT; break;
1051 case ISD::SETULE: CondCode = ARMCC::LE; break;
1053 case ISD::SETUNE: CondCode = ARMCC::NE; break;
1057 //===----------------------------------------------------------------------===//
1058 // Calling Convention Implementation
1059 //===----------------------------------------------------------------------===//
1061 #include "ARMGenCallingConv.inc"
1063 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1064 /// given CallingConvention value.
1065 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
1067 bool isVarArg) const {
1070 llvm_unreachable("Unsupported calling convention");
1071 case CallingConv::Fast:
1072 if (Subtarget->hasVFP2() && !isVarArg) {
1073 if (!Subtarget->isAAPCS_ABI())
1074 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1075 // For AAPCS ABI targets, just use VFP variant of the calling convention.
1076 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1079 case CallingConv::C: {
1080 // Use target triple & subtarget features to do actual dispatch.
1081 if (!Subtarget->isAAPCS_ABI())
1082 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1083 else if (Subtarget->hasVFP2() &&
1084 FloatABIType == FloatABI::Hard && !isVarArg)
1085 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1086 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1088 case CallingConv::ARM_AAPCS_VFP:
1089 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1090 case CallingConv::ARM_AAPCS:
1091 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1092 case CallingConv::ARM_APCS:
1093 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1097 /// LowerCallResult - Lower the result values of a call into the
1098 /// appropriate copies out of appropriate physical registers.
1100 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1101 CallingConv::ID CallConv, bool isVarArg,
1102 const SmallVectorImpl<ISD::InputArg> &Ins,
1103 DebugLoc dl, SelectionDAG &DAG,
1104 SmallVectorImpl<SDValue> &InVals) const {
1106 // Assign locations to each value returned by this call.
1107 SmallVector<CCValAssign, 16> RVLocs;
1108 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1109 getTargetMachine(), RVLocs, *DAG.getContext(), Call);
1110 CCInfo.AnalyzeCallResult(Ins,
1111 CCAssignFnForNode(CallConv, /* Return*/ true,
1114 // Copy all of the result registers out of their specified physreg.
1115 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1116 CCValAssign VA = RVLocs[i];
1119 if (VA.needsCustom()) {
1120 // Handle f64 or half of a v2f64.
1121 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1123 Chain = Lo.getValue(1);
1124 InFlag = Lo.getValue(2);
1125 VA = RVLocs[++i]; // skip ahead to next loc
1126 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1128 Chain = Hi.getValue(1);
1129 InFlag = Hi.getValue(2);
1130 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1132 if (VA.getLocVT() == MVT::v2f64) {
1133 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1134 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1135 DAG.getConstant(0, MVT::i32));
1137 VA = RVLocs[++i]; // skip ahead to next loc
1138 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1139 Chain = Lo.getValue(1);
1140 InFlag = Lo.getValue(2);
1141 VA = RVLocs[++i]; // skip ahead to next loc
1142 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1143 Chain = Hi.getValue(1);
1144 InFlag = Hi.getValue(2);
1145 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1146 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1147 DAG.getConstant(1, MVT::i32));
1150 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1152 Chain = Val.getValue(1);
1153 InFlag = Val.getValue(2);
1156 switch (VA.getLocInfo()) {
1157 default: llvm_unreachable("Unknown loc info!");
1158 case CCValAssign::Full: break;
1159 case CCValAssign::BCvt:
1160 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1164 InVals.push_back(Val);
1170 /// LowerMemOpCallTo - Store the argument to the stack.
1172 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
1173 SDValue StackPtr, SDValue Arg,
1174 DebugLoc dl, SelectionDAG &DAG,
1175 const CCValAssign &VA,
1176 ISD::ArgFlagsTy Flags) const {
1177 unsigned LocMemOffset = VA.getLocMemOffset();
1178 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1179 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1180 return DAG.getStore(Chain, dl, Arg, PtrOff,
1181 MachinePointerInfo::getStack(LocMemOffset),
1185 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
1186 SDValue Chain, SDValue &Arg,
1187 RegsToPassVector &RegsToPass,
1188 CCValAssign &VA, CCValAssign &NextVA,
1190 SmallVector<SDValue, 8> &MemOpChains,
1191 ISD::ArgFlagsTy Flags) const {
1193 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1194 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1195 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
1197 if (NextVA.isRegLoc())
1198 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
1200 assert(NextVA.isMemLoc());
1201 if (StackPtr.getNode() == 0)
1202 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1204 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
1210 /// LowerCall - Lowering a call into a callseq_start <-
1211 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1214 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1215 CallingConv::ID CallConv, bool isVarArg,
1217 const SmallVectorImpl<ISD::OutputArg> &Outs,
1218 const SmallVectorImpl<SDValue> &OutVals,
1219 const SmallVectorImpl<ISD::InputArg> &Ins,
1220 DebugLoc dl, SelectionDAG &DAG,
1221 SmallVectorImpl<SDValue> &InVals) const {
1222 MachineFunction &MF = DAG.getMachineFunction();
1223 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1224 bool IsSibCall = false;
1225 // Disable tail calls if they're not supported.
1226 if (!EnableARMTailCalls && !Subtarget->supportsTailCall())
1229 // Check if it's really possible to do a tail call.
1230 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1231 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1232 Outs, OutVals, Ins, DAG);
1233 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1234 // detected sibcalls.
1241 // Analyze operands of the call, assigning locations to each operand.
1242 SmallVector<CCValAssign, 16> ArgLocs;
1243 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1244 getTargetMachine(), ArgLocs, *DAG.getContext(), Call);
1245 CCInfo.AnalyzeCallOperands(Outs,
1246 CCAssignFnForNode(CallConv, /* Return*/ false,
1249 // Get a count of how many bytes are to be pushed on the stack.
1250 unsigned NumBytes = CCInfo.getNextStackOffset();
1252 // For tail calls, memory operands are available in our caller's stack.
1256 // Adjust the stack pointer for the new arguments...
1257 // These operations are automatically eliminated by the prolog/epilog pass
1259 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1261 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1263 RegsToPassVector RegsToPass;
1264 SmallVector<SDValue, 8> MemOpChains;
1266 // Walk the register/memloc assignments, inserting copies/loads. In the case
1267 // of tail call optimization, arguments are handled later.
1268 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1270 ++i, ++realArgIdx) {
1271 CCValAssign &VA = ArgLocs[i];
1272 SDValue Arg = OutVals[realArgIdx];
1273 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1274 bool isByVal = Flags.isByVal();
1276 // Promote the value if needed.
1277 switch (VA.getLocInfo()) {
1278 default: llvm_unreachable("Unknown loc info!");
1279 case CCValAssign::Full: break;
1280 case CCValAssign::SExt:
1281 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1283 case CCValAssign::ZExt:
1284 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1286 case CCValAssign::AExt:
1287 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1289 case CCValAssign::BCvt:
1290 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1294 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1295 if (VA.needsCustom()) {
1296 if (VA.getLocVT() == MVT::v2f64) {
1297 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1298 DAG.getConstant(0, MVT::i32));
1299 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1300 DAG.getConstant(1, MVT::i32));
1302 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1303 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1305 VA = ArgLocs[++i]; // skip ahead to next loc
1306 if (VA.isRegLoc()) {
1307 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1308 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1310 assert(VA.isMemLoc());
1312 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1313 dl, DAG, VA, Flags));
1316 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1317 StackPtr, MemOpChains, Flags);
1319 } else if (VA.isRegLoc()) {
1320 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1321 } else if (isByVal) {
1322 assert(VA.isMemLoc());
1323 unsigned offset = 0;
1325 // True if this byval aggregate will be split between registers
1327 if (CCInfo.isFirstByValRegValid()) {
1328 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1330 for (i = 0, j = CCInfo.getFirstByValReg(); j < ARM::R4; i++, j++) {
1331 SDValue Const = DAG.getConstant(4*i, MVT::i32);
1332 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
1333 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
1334 MachinePointerInfo(),
1336 MemOpChains.push_back(Load.getValue(1));
1337 RegsToPass.push_back(std::make_pair(j, Load));
1339 offset = ARM::R4 - CCInfo.getFirstByValReg();
1340 CCInfo.clearFirstByValReg();
1343 unsigned LocMemOffset = VA.getLocMemOffset();
1344 SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset);
1345 SDValue Dst = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr,
1347 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset);
1348 SDValue Src = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg, SrcOffset);
1349 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset,
1351 // TODO: Disable AlwaysInline when it becomes possible
1352 // to emit a nested call sequence.
1353 MemOpChains.push_back(DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode,
1354 Flags.getByValAlign(),
1355 /*isVolatile=*/false,
1356 /*AlwaysInline=*/true,
1357 MachinePointerInfo(0),
1358 MachinePointerInfo(0)));
1360 } else if (!IsSibCall) {
1361 assert(VA.isMemLoc());
1363 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1364 dl, DAG, VA, Flags));
1368 if (!MemOpChains.empty())
1369 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1370 &MemOpChains[0], MemOpChains.size());
1372 // Build a sequence of copy-to-reg nodes chained together with token chain
1373 // and flag operands which copy the outgoing args into the appropriate regs.
1375 // Tail call byval lowering might overwrite argument registers so in case of
1376 // tail call optimization the copies to registers are lowered later.
1378 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1379 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1380 RegsToPass[i].second, InFlag);
1381 InFlag = Chain.getValue(1);
1384 // For tail calls lower the arguments to the 'real' stack slot.
1386 // Force all the incoming stack arguments to be loaded from the stack
1387 // before any new outgoing arguments are stored to the stack, because the
1388 // outgoing stack slots may alias the incoming argument stack slots, and
1389 // the alias isn't otherwise explicit. This is slightly more conservative
1390 // than necessary, because it means that each store effectively depends
1391 // on every argument instead of just those arguments it would clobber.
1393 // Do not flag preceding copytoreg stuff together with the following stuff.
1395 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1396 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1397 RegsToPass[i].second, InFlag);
1398 InFlag = Chain.getValue(1);
1403 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1404 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1405 // node so that legalize doesn't hack it.
1406 bool isDirect = false;
1407 bool isARMFunc = false;
1408 bool isLocalARMFunc = false;
1409 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1411 if (EnableARMLongCalls) {
1412 assert (getTargetMachine().getRelocationModel() == Reloc::Static
1413 && "long-calls with non-static relocation model!");
1414 // Handle a global address or an external symbol. If it's not one of
1415 // those, the target's already in a register, so we don't need to do
1417 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1418 const GlobalValue *GV = G->getGlobal();
1419 // Create a constant pool entry for the callee address
1420 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1421 ARMConstantPoolValue *CPV =
1422 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0);
1424 // Get the address of the callee into a register
1425 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1426 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1427 Callee = DAG.getLoad(getPointerTy(), dl,
1428 DAG.getEntryNode(), CPAddr,
1429 MachinePointerInfo::getConstantPool(),
1431 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1432 const char *Sym = S->getSymbol();
1434 // Create a constant pool entry for the callee address
1435 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1436 ARMConstantPoolValue *CPV =
1437 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
1438 ARMPCLabelIndex, 0);
1439 // Get the address of the callee into a register
1440 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1441 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1442 Callee = DAG.getLoad(getPointerTy(), dl,
1443 DAG.getEntryNode(), CPAddr,
1444 MachinePointerInfo::getConstantPool(),
1447 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1448 const GlobalValue *GV = G->getGlobal();
1450 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1451 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
1452 getTargetMachine().getRelocationModel() != Reloc::Static;
1453 isARMFunc = !Subtarget->isThumb() || isStub;
1454 // ARM call to a local ARM function is predicable.
1455 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
1456 // tBX takes a register source operand.
1457 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1458 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1459 ARMConstantPoolValue *CPV =
1460 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 4);
1461 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1462 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1463 Callee = DAG.getLoad(getPointerTy(), dl,
1464 DAG.getEntryNode(), CPAddr,
1465 MachinePointerInfo::getConstantPool(),
1467 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1468 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1469 getPointerTy(), Callee, PICLabel);
1471 // On ELF targets for PIC code, direct calls should go through the PLT
1472 unsigned OpFlags = 0;
1473 if (Subtarget->isTargetELF() &&
1474 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1475 OpFlags = ARMII::MO_PLT;
1476 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
1478 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1480 bool isStub = Subtarget->isTargetDarwin() &&
1481 getTargetMachine().getRelocationModel() != Reloc::Static;
1482 isARMFunc = !Subtarget->isThumb() || isStub;
1483 // tBX takes a register source operand.
1484 const char *Sym = S->getSymbol();
1485 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1486 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1487 ARMConstantPoolValue *CPV =
1488 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
1489 ARMPCLabelIndex, 4);
1490 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1491 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1492 Callee = DAG.getLoad(getPointerTy(), dl,
1493 DAG.getEntryNode(), CPAddr,
1494 MachinePointerInfo::getConstantPool(),
1496 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1497 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1498 getPointerTy(), Callee, PICLabel);
1500 unsigned OpFlags = 0;
1501 // On ELF targets for PIC code, direct calls should go through the PLT
1502 if (Subtarget->isTargetELF() &&
1503 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1504 OpFlags = ARMII::MO_PLT;
1505 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags);
1509 // FIXME: handle tail calls differently.
1511 if (Subtarget->isThumb()) {
1512 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1513 CallOpc = ARMISD::CALL_NOLINK;
1515 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1517 CallOpc = (isDirect || Subtarget->hasV5TOps())
1518 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
1519 : ARMISD::CALL_NOLINK;
1522 std::vector<SDValue> Ops;
1523 Ops.push_back(Chain);
1524 Ops.push_back(Callee);
1526 // Add argument registers to the end of the list so that they are known live
1528 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1529 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1530 RegsToPass[i].second.getValueType()));
1532 if (InFlag.getNode())
1533 Ops.push_back(InFlag);
1535 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1537 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
1539 // Returns a chain and a flag for retval copy to use.
1540 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
1541 InFlag = Chain.getValue(1);
1543 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1544 DAG.getIntPtrConstant(0, true), InFlag);
1546 InFlag = Chain.getValue(1);
1548 // Handle result values, copying them out of physregs into vregs that we
1550 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1554 /// HandleByVal - Every parameter *after* a byval parameter is passed
1555 /// on the stack. Remember the next parameter register to allocate,
1556 /// and then confiscate the rest of the parameter registers to insure
1559 llvm::ARMTargetLowering::HandleByVal(CCState *State, unsigned &size) const {
1560 unsigned reg = State->AllocateReg(GPRArgRegs, 4);
1561 assert((State->getCallOrPrologue() == Prologue ||
1562 State->getCallOrPrologue() == Call) &&
1563 "unhandled ParmContext");
1564 if ((!State->isFirstByValRegValid()) &&
1565 (ARM::R0 <= reg) && (reg <= ARM::R3)) {
1566 State->setFirstByValReg(reg);
1567 // At a call site, a byval parameter that is split between
1568 // registers and memory needs its size truncated here. In a
1569 // function prologue, such byval parameters are reassembled in
1570 // memory, and are not truncated.
1571 if (State->getCallOrPrologue() == Call) {
1572 unsigned excess = 4 * (ARM::R4 - reg);
1573 assert(size >= excess && "expected larger existing stack allocation");
1577 // Confiscate any remaining parameter registers to preclude their
1578 // assignment to subsequent parameters.
1579 while (State->AllocateReg(GPRArgRegs, 4))
1583 /// MatchingStackOffset - Return true if the given stack call argument is
1584 /// already available in the same position (relatively) of the caller's
1585 /// incoming argument stack.
1587 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1588 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1589 const ARMInstrInfo *TII) {
1590 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
1592 if (Arg.getOpcode() == ISD::CopyFromReg) {
1593 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
1594 if (!TargetRegisterInfo::isVirtualRegister(VR))
1596 MachineInstr *Def = MRI->getVRegDef(VR);
1599 if (!Flags.isByVal()) {
1600 if (!TII->isLoadFromStackSlot(Def, FI))
1605 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
1606 if (Flags.isByVal())
1607 // ByVal argument is passed in as a pointer but it's now being
1608 // dereferenced. e.g.
1609 // define @foo(%struct.X* %A) {
1610 // tail call @bar(%struct.X* byval %A)
1613 SDValue Ptr = Ld->getBasePtr();
1614 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
1617 FI = FINode->getIndex();
1621 assert(FI != INT_MAX);
1622 if (!MFI->isFixedObjectIndex(FI))
1624 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
1627 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1628 /// for tail call optimization. Targets which want to do tail call
1629 /// optimization should implement this function.
1631 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1632 CallingConv::ID CalleeCC,
1634 bool isCalleeStructRet,
1635 bool isCallerStructRet,
1636 const SmallVectorImpl<ISD::OutputArg> &Outs,
1637 const SmallVectorImpl<SDValue> &OutVals,
1638 const SmallVectorImpl<ISD::InputArg> &Ins,
1639 SelectionDAG& DAG) const {
1640 const Function *CallerF = DAG.getMachineFunction().getFunction();
1641 CallingConv::ID CallerCC = CallerF->getCallingConv();
1642 bool CCMatch = CallerCC == CalleeCC;
1644 // Look for obvious safe cases to perform tail call optimization that do not
1645 // require ABI changes. This is what gcc calls sibcall.
1647 // Do not sibcall optimize vararg calls unless the call site is not passing
1649 if (isVarArg && !Outs.empty())
1652 // Also avoid sibcall optimization if either caller or callee uses struct
1653 // return semantics.
1654 if (isCalleeStructRet || isCallerStructRet)
1657 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
1658 // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
1659 // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
1660 // support in the assembler and linker to be used. This would need to be
1661 // fixed to fully support tail calls in Thumb1.
1663 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
1664 // LR. This means if we need to reload LR, it takes an extra instructions,
1665 // which outweighs the value of the tail call; but here we don't know yet
1666 // whether LR is going to be used. Probably the right approach is to
1667 // generate the tail call here and turn it back into CALL/RET in
1668 // emitEpilogue if LR is used.
1670 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
1671 // but we need to make sure there are enough registers; the only valid
1672 // registers are the 4 used for parameters. We don't currently do this
1674 if (Subtarget->isThumb1Only())
1677 // If the calling conventions do not match, then we'd better make sure the
1678 // results are returned in the same way as what the caller expects.
1680 SmallVector<CCValAssign, 16> RVLocs1;
1681 ARMCCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
1682 getTargetMachine(), RVLocs1, *DAG.getContext(), Call);
1683 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
1685 SmallVector<CCValAssign, 16> RVLocs2;
1686 ARMCCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
1687 getTargetMachine(), RVLocs2, *DAG.getContext(), Call);
1688 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
1690 if (RVLocs1.size() != RVLocs2.size())
1692 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
1693 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
1695 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
1697 if (RVLocs1[i].isRegLoc()) {
1698 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
1701 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
1707 // If the callee takes no arguments then go on to check the results of the
1709 if (!Outs.empty()) {
1710 // Check if stack adjustment is needed. For now, do not do this if any
1711 // argument is passed on the stack.
1712 SmallVector<CCValAssign, 16> ArgLocs;
1713 ARMCCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
1714 getTargetMachine(), ArgLocs, *DAG.getContext(), Call);
1715 CCInfo.AnalyzeCallOperands(Outs,
1716 CCAssignFnForNode(CalleeCC, false, isVarArg));
1717 if (CCInfo.getNextStackOffset()) {
1718 MachineFunction &MF = DAG.getMachineFunction();
1720 // Check if the arguments are already laid out in the right way as
1721 // the caller's fixed stack objects.
1722 MachineFrameInfo *MFI = MF.getFrameInfo();
1723 const MachineRegisterInfo *MRI = &MF.getRegInfo();
1724 const ARMInstrInfo *TII =
1725 ((ARMTargetMachine&)getTargetMachine()).getInstrInfo();
1726 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1728 ++i, ++realArgIdx) {
1729 CCValAssign &VA = ArgLocs[i];
1730 EVT RegVT = VA.getLocVT();
1731 SDValue Arg = OutVals[realArgIdx];
1732 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1733 if (VA.getLocInfo() == CCValAssign::Indirect)
1735 if (VA.needsCustom()) {
1736 // f64 and vector types are split into multiple registers or
1737 // register/stack-slot combinations. The types will not match
1738 // the registers; give up on memory f64 refs until we figure
1739 // out what to do about this.
1742 if (!ArgLocs[++i].isRegLoc())
1744 if (RegVT == MVT::v2f64) {
1745 if (!ArgLocs[++i].isRegLoc())
1747 if (!ArgLocs[++i].isRegLoc())
1750 } else if (!VA.isRegLoc()) {
1751 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
1763 ARMTargetLowering::LowerReturn(SDValue Chain,
1764 CallingConv::ID CallConv, bool isVarArg,
1765 const SmallVectorImpl<ISD::OutputArg> &Outs,
1766 const SmallVectorImpl<SDValue> &OutVals,
1767 DebugLoc dl, SelectionDAG &DAG) const {
1769 // CCValAssign - represent the assignment of the return value to a location.
1770 SmallVector<CCValAssign, 16> RVLocs;
1772 // CCState - Info about the registers and stack slots.
1773 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1774 getTargetMachine(), RVLocs, *DAG.getContext(), Call);
1776 // Analyze outgoing return values.
1777 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1780 // If this is the first return lowered for this function, add
1781 // the regs to the liveout set for the function.
1782 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1783 for (unsigned i = 0; i != RVLocs.size(); ++i)
1784 if (RVLocs[i].isRegLoc())
1785 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1790 // Copy the result values into the output registers.
1791 for (unsigned i = 0, realRVLocIdx = 0;
1793 ++i, ++realRVLocIdx) {
1794 CCValAssign &VA = RVLocs[i];
1795 assert(VA.isRegLoc() && "Can only return in registers!");
1797 SDValue Arg = OutVals[realRVLocIdx];
1799 switch (VA.getLocInfo()) {
1800 default: llvm_unreachable("Unknown loc info!");
1801 case CCValAssign::Full: break;
1802 case CCValAssign::BCvt:
1803 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1807 if (VA.needsCustom()) {
1808 if (VA.getLocVT() == MVT::v2f64) {
1809 // Extract the first half and return it in two registers.
1810 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1811 DAG.getConstant(0, MVT::i32));
1812 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
1813 DAG.getVTList(MVT::i32, MVT::i32), Half);
1815 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1816 Flag = Chain.getValue(1);
1817 VA = RVLocs[++i]; // skip ahead to next loc
1818 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1819 HalfGPRs.getValue(1), Flag);
1820 Flag = Chain.getValue(1);
1821 VA = RVLocs[++i]; // skip ahead to next loc
1823 // Extract the 2nd half and fall through to handle it as an f64 value.
1824 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1825 DAG.getConstant(1, MVT::i32));
1827 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1829 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1830 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1831 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1832 Flag = Chain.getValue(1);
1833 VA = RVLocs[++i]; // skip ahead to next loc
1834 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1837 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1839 // Guarantee that all emitted copies are
1840 // stuck together, avoiding something bad.
1841 Flag = Chain.getValue(1);
1846 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1848 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1853 bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N) const {
1854 if (N->getNumValues() != 1)
1856 if (!N->hasNUsesOfValue(1, 0))
1859 unsigned NumCopies = 0;
1861 SDNode *Use = *N->use_begin();
1862 if (Use->getOpcode() == ISD::CopyToReg) {
1863 Copies[NumCopies++] = Use;
1864 } else if (Use->getOpcode() == ARMISD::VMOVRRD) {
1865 // f64 returned in a pair of GPRs.
1866 for (SDNode::use_iterator UI = Use->use_begin(), UE = Use->use_end();
1868 if (UI->getOpcode() != ISD::CopyToReg)
1870 Copies[UI.getUse().getResNo()] = *UI;
1873 } else if (Use->getOpcode() == ISD::BITCAST) {
1874 // f32 returned in a single GPR.
1875 if (!Use->hasNUsesOfValue(1, 0))
1877 Use = *Use->use_begin();
1878 if (Use->getOpcode() != ISD::CopyToReg || !Use->hasNUsesOfValue(1, 0))
1880 Copies[NumCopies++] = Use;
1885 if (NumCopies != 1 && NumCopies != 2)
1888 bool HasRet = false;
1889 for (unsigned i = 0; i < NumCopies; ++i) {
1890 SDNode *Copy = Copies[i];
1891 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1893 if (UI->getOpcode() == ISD::CopyToReg) {
1895 if (Use == Copies[0] || Use == Copies[1])
1899 if (UI->getOpcode() != ARMISD::RET_FLAG)
1908 bool ARMTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1909 if (!EnableARMTailCalls)
1912 if (!CI->isTailCall())
1915 return !Subtarget->isThumb1Only();
1918 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1919 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1920 // one of the above mentioned nodes. It has to be wrapped because otherwise
1921 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1922 // be used to form addressing mode. These wrapped nodes will be selected
1924 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1925 EVT PtrVT = Op.getValueType();
1926 // FIXME there is no actual debug info here
1927 DebugLoc dl = Op.getDebugLoc();
1928 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1930 if (CP->isMachineConstantPoolEntry())
1931 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1932 CP->getAlignment());
1934 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1935 CP->getAlignment());
1936 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1939 unsigned ARMTargetLowering::getJumpTableEncoding() const {
1940 return MachineJumpTableInfo::EK_Inline;
1943 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
1944 SelectionDAG &DAG) const {
1945 MachineFunction &MF = DAG.getMachineFunction();
1946 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1947 unsigned ARMPCLabelIndex = 0;
1948 DebugLoc DL = Op.getDebugLoc();
1949 EVT PtrVT = getPointerTy();
1950 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1951 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1953 if (RelocM == Reloc::Static) {
1954 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
1956 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1957 ARMPCLabelIndex = AFI->createPICLabelUId();
1958 ARMConstantPoolValue *CPV =
1959 ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex,
1960 ARMCP::CPBlockAddress, PCAdj);
1961 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1963 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
1964 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
1965 MachinePointerInfo::getConstantPool(),
1967 if (RelocM == Reloc::Static)
1969 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1970 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
1973 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
1975 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1976 SelectionDAG &DAG) const {
1977 DebugLoc dl = GA->getDebugLoc();
1978 EVT PtrVT = getPointerTy();
1979 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1980 MachineFunction &MF = DAG.getMachineFunction();
1981 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1982 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1983 ARMConstantPoolValue *CPV =
1984 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
1985 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
1986 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1987 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
1988 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
1989 MachinePointerInfo::getConstantPool(),
1991 SDValue Chain = Argument.getValue(1);
1993 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1994 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
1996 // call __tls_get_addr.
1999 Entry.Node = Argument;
2000 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
2001 Args.push_back(Entry);
2002 // FIXME: is there useful debug info available here?
2003 std::pair<SDValue, SDValue> CallResult =
2004 LowerCallTo(Chain, (Type *) Type::getInt32Ty(*DAG.getContext()),
2005 false, false, false, false,
2006 0, CallingConv::C, false, /*isReturnValueUsed=*/true,
2007 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
2008 return CallResult.first;
2011 // Lower ISD::GlobalTLSAddress using the "initial exec" or
2012 // "local exec" model.
2014 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
2015 SelectionDAG &DAG) const {
2016 const GlobalValue *GV = GA->getGlobal();
2017 DebugLoc dl = GA->getDebugLoc();
2019 SDValue Chain = DAG.getEntryNode();
2020 EVT PtrVT = getPointerTy();
2021 // Get the Thread Pointer
2022 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2024 if (GV->isDeclaration()) {
2025 MachineFunction &MF = DAG.getMachineFunction();
2026 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2027 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2028 // Initial exec model.
2029 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2030 ARMConstantPoolValue *CPV =
2031 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2032 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF,
2034 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2035 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2036 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2037 MachinePointerInfo::getConstantPool(),
2039 Chain = Offset.getValue(1);
2041 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2042 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
2044 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2045 MachinePointerInfo::getConstantPool(),
2049 ARMConstantPoolValue *CPV =
2050 ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF);
2051 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2052 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2053 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2054 MachinePointerInfo::getConstantPool(),
2058 // The address of the thread local variable is the add of the thread
2059 // pointer with the offset of the variable.
2060 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
2064 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
2065 // TODO: implement the "local dynamic" model
2066 assert(Subtarget->isTargetELF() &&
2067 "TLS not implemented for non-ELF targets");
2068 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2069 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
2070 // otherwise use the "Local Exec" TLS Model
2071 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
2072 return LowerToTLSGeneralDynamicModel(GA, DAG);
2074 return LowerToTLSExecModels(GA, DAG);
2077 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
2078 SelectionDAG &DAG) const {
2079 EVT PtrVT = getPointerTy();
2080 DebugLoc dl = Op.getDebugLoc();
2081 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2082 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2083 if (RelocM == Reloc::PIC_) {
2084 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
2085 ARMConstantPoolValue *CPV =
2086 ARMConstantPoolConstant::Create(GV,
2087 UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
2088 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2089 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2090 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
2092 MachinePointerInfo::getConstantPool(),
2094 SDValue Chain = Result.getValue(1);
2095 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
2096 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
2098 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
2099 MachinePointerInfo::getGOT(), false, false, 0);
2103 // If we have T2 ops, we can materialize the address directly via movt/movw
2104 // pair. This is always cheaper.
2105 if (Subtarget->useMovt()) {
2107 // FIXME: Once remat is capable of dealing with instructions with register
2108 // operands, expand this into two nodes.
2109 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2110 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2112 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
2113 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2114 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2115 MachinePointerInfo::getConstantPool(),
2120 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
2121 SelectionDAG &DAG) const {
2122 EVT PtrVT = getPointerTy();
2123 DebugLoc dl = Op.getDebugLoc();
2124 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2125 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2126 MachineFunction &MF = DAG.getMachineFunction();
2127 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2129 // FIXME: Enable this for static codegen when tool issues are fixed.
2130 if (Subtarget->useMovt() && RelocM != Reloc::Static) {
2132 // FIXME: Once remat is capable of dealing with instructions with register
2133 // operands, expand this into two nodes.
2134 if (RelocM == Reloc::Static)
2135 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2136 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2138 unsigned Wrapper = (RelocM == Reloc::PIC_)
2139 ? ARMISD::WrapperPIC : ARMISD::WrapperDYN;
2140 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT,
2141 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2142 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
2143 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
2144 MachinePointerInfo::getGOT(), false, false, 0);
2148 unsigned ARMPCLabelIndex = 0;
2150 if (RelocM == Reloc::Static) {
2151 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
2153 ARMPCLabelIndex = AFI->createPICLabelUId();
2154 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8);
2155 ARMConstantPoolValue *CPV =
2156 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue,
2158 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2160 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2162 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2163 MachinePointerInfo::getConstantPool(),
2165 SDValue Chain = Result.getValue(1);
2167 if (RelocM == Reloc::PIC_) {
2168 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2169 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2172 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
2173 Result = DAG.getLoad(PtrVT, dl, Chain, Result, MachinePointerInfo::getGOT(),
2179 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
2180 SelectionDAG &DAG) const {
2181 assert(Subtarget->isTargetELF() &&
2182 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
2183 MachineFunction &MF = DAG.getMachineFunction();
2184 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2185 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2186 EVT PtrVT = getPointerTy();
2187 DebugLoc dl = Op.getDebugLoc();
2188 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2189 ARMConstantPoolValue *CPV =
2190 ARMConstantPoolSymbol::Create(*DAG.getContext(), "_GLOBAL_OFFSET_TABLE_",
2191 ARMPCLabelIndex, PCAdj);
2192 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2193 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2194 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2195 MachinePointerInfo::getConstantPool(),
2197 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2198 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2202 ARMTargetLowering::LowerEH_SJLJ_DISPATCHSETUP(SDValue Op, SelectionDAG &DAG)
2204 DebugLoc dl = Op.getDebugLoc();
2205 return DAG.getNode(ARMISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other,
2206 Op.getOperand(0), Op.getOperand(1));
2210 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
2211 DebugLoc dl = Op.getDebugLoc();
2212 SDValue Val = DAG.getConstant(0, MVT::i32);
2213 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl,
2214 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
2215 Op.getOperand(1), Val);
2219 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
2220 DebugLoc dl = Op.getDebugLoc();
2221 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
2222 Op.getOperand(1), DAG.getConstant(0, MVT::i32));
2226 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
2227 const ARMSubtarget *Subtarget) const {
2228 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2229 DebugLoc dl = Op.getDebugLoc();
2231 default: return SDValue(); // Don't custom lower most intrinsics.
2232 case Intrinsic::arm_thread_pointer: {
2233 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2234 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2236 case Intrinsic::eh_sjlj_lsda: {
2237 MachineFunction &MF = DAG.getMachineFunction();
2238 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2239 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2240 EVT PtrVT = getPointerTy();
2241 DebugLoc dl = Op.getDebugLoc();
2242 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2244 unsigned PCAdj = (RelocM != Reloc::PIC_)
2245 ? 0 : (Subtarget->isThumb() ? 4 : 8);
2246 ARMConstantPoolValue *CPV =
2247 ARMConstantPoolConstant::Create(MF.getFunction(), ARMPCLabelIndex,
2248 ARMCP::CPLSDA, PCAdj);
2249 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2250 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2252 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2253 MachinePointerInfo::getConstantPool(),
2256 if (RelocM == Reloc::PIC_) {
2257 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2258 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2262 case Intrinsic::arm_neon_vmulls:
2263 case Intrinsic::arm_neon_vmullu: {
2264 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
2265 ? ARMISD::VMULLs : ARMISD::VMULLu;
2266 return DAG.getNode(NewOpc, Op.getDebugLoc(), Op.getValueType(),
2267 Op.getOperand(1), Op.getOperand(2));
2272 static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG,
2273 const ARMSubtarget *Subtarget) {
2274 DebugLoc dl = Op.getDebugLoc();
2275 if (!Subtarget->hasDataBarrier()) {
2276 // Some ARMv6 cpus can support data barriers with an mcr instruction.
2277 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
2279 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&
2280 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!");
2281 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2282 DAG.getConstant(0, MVT::i32));
2285 SDValue Op5 = Op.getOperand(5);
2286 bool isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue() != 0;
2287 unsigned isLL = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
2288 unsigned isLS = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
2289 bool isOnlyStoreBarrier = (isLL == 0 && isLS == 0);
2291 ARM_MB::MemBOpt DMBOpt;
2292 if (isDeviceBarrier)
2293 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ST : ARM_MB::SY;
2295 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ISHST : ARM_MB::ISH;
2296 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
2297 DAG.getConstant(DMBOpt, MVT::i32));
2301 static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
2302 const ARMSubtarget *Subtarget) {
2303 // FIXME: handle "fence singlethread" more efficiently.
2304 DebugLoc dl = Op.getDebugLoc();
2305 if (!Subtarget->hasDataBarrier()) {
2306 // Some ARMv6 cpus can support data barriers with an mcr instruction.
2307 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
2309 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&
2310 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!");
2311 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2312 DAG.getConstant(0, MVT::i32));
2315 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
2316 DAG.getConstant(ARM_MB::ISH, MVT::i32));
2319 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
2320 const ARMSubtarget *Subtarget) {
2321 // ARM pre v5TE and Thumb1 does not have preload instructions.
2322 if (!(Subtarget->isThumb2() ||
2323 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
2324 // Just preserve the chain.
2325 return Op.getOperand(0);
2327 DebugLoc dl = Op.getDebugLoc();
2328 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
2330 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
2331 // ARMv7 with MP extension has PLDW.
2332 return Op.getOperand(0);
2334 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
2335 if (Subtarget->isThumb()) {
2337 isRead = ~isRead & 1;
2338 isData = ~isData & 1;
2341 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
2342 Op.getOperand(1), DAG.getConstant(isRead, MVT::i32),
2343 DAG.getConstant(isData, MVT::i32));
2346 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
2347 MachineFunction &MF = DAG.getMachineFunction();
2348 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
2350 // vastart just stores the address of the VarArgsFrameIndex slot into the
2351 // memory location argument.
2352 DebugLoc dl = Op.getDebugLoc();
2353 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2354 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2355 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2356 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2357 MachinePointerInfo(SV), false, false, 0);
2361 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
2362 SDValue &Root, SelectionDAG &DAG,
2363 DebugLoc dl) const {
2364 MachineFunction &MF = DAG.getMachineFunction();
2365 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2367 TargetRegisterClass *RC;
2368 if (AFI->isThumb1OnlyFunction())
2369 RC = ARM::tGPRRegisterClass;
2371 RC = ARM::GPRRegisterClass;
2373 // Transform the arguments stored in physical registers into virtual ones.
2374 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2375 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2378 if (NextVA.isMemLoc()) {
2379 MachineFrameInfo *MFI = MF.getFrameInfo();
2380 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
2382 // Create load node to retrieve arguments from the stack.
2383 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2384 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
2385 MachinePointerInfo::getFixedStack(FI),
2388 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2389 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2392 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
2396 ARMTargetLowering::computeRegArea(CCState &CCInfo, MachineFunction &MF,
2397 unsigned &VARegSize, unsigned &VARegSaveSize)
2400 if (CCInfo.isFirstByValRegValid())
2401 NumGPRs = ARM::R4 - CCInfo.getFirstByValReg();
2403 unsigned int firstUnalloced;
2404 firstUnalloced = CCInfo.getFirstUnallocated(GPRArgRegs,
2405 sizeof(GPRArgRegs) /
2406 sizeof(GPRArgRegs[0]));
2407 NumGPRs = (firstUnalloced <= 3) ? (4 - firstUnalloced) : 0;
2410 unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment();
2411 VARegSize = NumGPRs * 4;
2412 VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
2415 // The remaining GPRs hold either the beginning of variable-argument
2416 // data, or the beginning of an aggregate passed by value (usuall
2417 // byval). Either way, we allocate stack slots adjacent to the data
2418 // provided by our caller, and store the unallocated registers there.
2419 // If this is a variadic function, the va_list pointer will begin with
2420 // these values; otherwise, this reassembles a (byval) structure that
2421 // was split between registers and memory.
2423 ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
2424 DebugLoc dl, SDValue &Chain,
2425 unsigned ArgOffset) const {
2426 MachineFunction &MF = DAG.getMachineFunction();
2427 MachineFrameInfo *MFI = MF.getFrameInfo();
2428 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2429 unsigned firstRegToSaveIndex;
2430 if (CCInfo.isFirstByValRegValid())
2431 firstRegToSaveIndex = CCInfo.getFirstByValReg() - ARM::R0;
2433 firstRegToSaveIndex = CCInfo.getFirstUnallocated
2434 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
2437 unsigned VARegSize, VARegSaveSize;
2438 computeRegArea(CCInfo, MF, VARegSize, VARegSaveSize);
2439 if (VARegSaveSize) {
2440 // If this function is vararg, store any remaining integer argument regs
2441 // to their spots on the stack so that they may be loaded by deferencing
2442 // the result of va_next.
2443 AFI->setVarArgsRegSaveSize(VARegSaveSize);
2444 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(VARegSaveSize,
2445 ArgOffset + VARegSaveSize
2448 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(),
2451 SmallVector<SDValue, 4> MemOps;
2452 for (; firstRegToSaveIndex < 4; ++firstRegToSaveIndex) {
2453 TargetRegisterClass *RC;
2454 if (AFI->isThumb1OnlyFunction())
2455 RC = ARM::tGPRRegisterClass;
2457 RC = ARM::GPRRegisterClass;
2459 unsigned VReg = MF.addLiveIn(GPRArgRegs[firstRegToSaveIndex], RC);
2460 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2462 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2463 MachinePointerInfo::getFixedStack(AFI->getVarArgsFrameIndex()),
2465 MemOps.push_back(Store);
2466 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
2467 DAG.getConstant(4, getPointerTy()));
2469 if (!MemOps.empty())
2470 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2471 &MemOps[0], MemOps.size());
2473 // This will point to the next argument passed via stack.
2474 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset, true));
2478 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
2479 CallingConv::ID CallConv, bool isVarArg,
2480 const SmallVectorImpl<ISD::InputArg>
2482 DebugLoc dl, SelectionDAG &DAG,
2483 SmallVectorImpl<SDValue> &InVals)
2485 MachineFunction &MF = DAG.getMachineFunction();
2486 MachineFrameInfo *MFI = MF.getFrameInfo();
2488 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2490 // Assign locations to all of the incoming arguments.
2491 SmallVector<CCValAssign, 16> ArgLocs;
2492 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2493 getTargetMachine(), ArgLocs, *DAG.getContext(), Prologue);
2494 CCInfo.AnalyzeFormalArguments(Ins,
2495 CCAssignFnForNode(CallConv, /* Return*/ false,
2498 SmallVector<SDValue, 16> ArgValues;
2499 int lastInsIndex = -1;
2502 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2503 CCValAssign &VA = ArgLocs[i];
2505 // Arguments stored in registers.
2506 if (VA.isRegLoc()) {
2507 EVT RegVT = VA.getLocVT();
2509 if (VA.needsCustom()) {
2510 // f64 and vector types are split up into multiple registers or
2511 // combinations of registers and stack slots.
2512 if (VA.getLocVT() == MVT::v2f64) {
2513 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
2515 VA = ArgLocs[++i]; // skip ahead to next loc
2517 if (VA.isMemLoc()) {
2518 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
2519 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2520 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
2521 MachinePointerInfo::getFixedStack(FI),
2524 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
2527 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2528 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2529 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
2530 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2531 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
2533 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
2536 TargetRegisterClass *RC;
2538 if (RegVT == MVT::f32)
2539 RC = ARM::SPRRegisterClass;
2540 else if (RegVT == MVT::f64)
2541 RC = ARM::DPRRegisterClass;
2542 else if (RegVT == MVT::v2f64)
2543 RC = ARM::QPRRegisterClass;
2544 else if (RegVT == MVT::i32)
2545 RC = (AFI->isThumb1OnlyFunction() ?
2546 ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
2548 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2550 // Transform the arguments in physical registers into virtual ones.
2551 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2552 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2555 // If this is an 8 or 16-bit value, it is really passed promoted
2556 // to 32 bits. Insert an assert[sz]ext to capture this, then
2557 // truncate to the right size.
2558 switch (VA.getLocInfo()) {
2559 default: llvm_unreachable("Unknown loc info!");
2560 case CCValAssign::Full: break;
2561 case CCValAssign::BCvt:
2562 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2564 case CCValAssign::SExt:
2565 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2566 DAG.getValueType(VA.getValVT()));
2567 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2569 case CCValAssign::ZExt:
2570 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2571 DAG.getValueType(VA.getValVT()));
2572 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2576 InVals.push_back(ArgValue);
2578 } else { // VA.isRegLoc()
2581 assert(VA.isMemLoc());
2582 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
2584 int index = ArgLocs[i].getValNo();
2586 // Some Ins[] entries become multiple ArgLoc[] entries.
2587 // Process them only once.
2588 if (index != lastInsIndex)
2590 ISD::ArgFlagsTy Flags = Ins[index].Flags;
2591 // FIXME: For now, all byval parameter objects are marked mutable.
2592 // This can be changed with more analysis.
2593 // In case of tail call optimization mark all arguments mutable.
2594 // Since they could be overwritten by lowering of arguments in case of
2596 if (Flags.isByVal()) {
2597 unsigned VARegSize, VARegSaveSize;
2598 computeRegArea(CCInfo, MF, VARegSize, VARegSaveSize);
2599 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, 0);
2600 unsigned Bytes = Flags.getByValSize() - VARegSize;
2601 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2602 int FI = MFI->CreateFixedObject(Bytes,
2603 VA.getLocMemOffset(), false);
2604 InVals.push_back(DAG.getFrameIndex(FI, getPointerTy()));
2606 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
2607 VA.getLocMemOffset(), true);
2609 // Create load nodes to retrieve arguments from the stack.
2610 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2611 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2612 MachinePointerInfo::getFixedStack(FI),
2615 lastInsIndex = index;
2622 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, CCInfo.getNextStackOffset());
2627 /// isFloatingPointZero - Return true if this is +0.0.
2628 static bool isFloatingPointZero(SDValue Op) {
2629 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
2630 return CFP->getValueAPF().isPosZero();
2631 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
2632 // Maybe this has already been legalized into the constant pool?
2633 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
2634 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
2635 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
2636 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
2637 return CFP->getValueAPF().isPosZero();
2643 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
2644 /// the given operands.
2646 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2647 SDValue &ARMcc, SelectionDAG &DAG,
2648 DebugLoc dl) const {
2649 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
2650 unsigned C = RHSC->getZExtValue();
2651 if (!isLegalICmpImmediate(C)) {
2652 // Constant does not fit, try adjusting it by one?
2657 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
2658 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
2659 RHS = DAG.getConstant(C-1, MVT::i32);
2664 if (C != 0 && isLegalICmpImmediate(C-1)) {
2665 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
2666 RHS = DAG.getConstant(C-1, MVT::i32);
2671 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
2672 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
2673 RHS = DAG.getConstant(C+1, MVT::i32);
2678 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
2679 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2680 RHS = DAG.getConstant(C+1, MVT::i32);
2687 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2688 ARMISD::NodeType CompareType;
2691 CompareType = ARMISD::CMP;
2696 CompareType = ARMISD::CMPZ;
2699 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2700 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
2703 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
2705 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
2706 DebugLoc dl) const {
2708 if (!isFloatingPointZero(RHS))
2709 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS);
2711 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS);
2712 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
2715 /// duplicateCmp - Glue values can have only one use, so this function
2716 /// duplicates a comparison node.
2718 ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
2719 unsigned Opc = Cmp.getOpcode();
2720 DebugLoc DL = Cmp.getDebugLoc();
2721 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
2722 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
2724 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation");
2725 Cmp = Cmp.getOperand(0);
2726 Opc = Cmp.getOpcode();
2727 if (Opc == ARMISD::CMPFP)
2728 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
2730 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT");
2731 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0));
2733 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
2736 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2737 SDValue Cond = Op.getOperand(0);
2738 SDValue SelectTrue = Op.getOperand(1);
2739 SDValue SelectFalse = Op.getOperand(2);
2740 DebugLoc dl = Op.getDebugLoc();
2744 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
2745 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
2747 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
2748 const ConstantSDNode *CMOVTrue =
2749 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
2750 const ConstantSDNode *CMOVFalse =
2751 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
2753 if (CMOVTrue && CMOVFalse) {
2754 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
2755 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
2759 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
2761 False = SelectFalse;
2762 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
2767 if (True.getNode() && False.getNode()) {
2768 EVT VT = Op.getValueType();
2769 SDValue ARMcc = Cond.getOperand(2);
2770 SDValue CCR = Cond.getOperand(3);
2771 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
2772 assert(True.getValueType() == VT);
2773 return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp);
2778 return DAG.getSelectCC(dl, Cond,
2779 DAG.getConstant(0, Cond.getValueType()),
2780 SelectTrue, SelectFalse, ISD::SETNE);
2783 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
2784 EVT VT = Op.getValueType();
2785 SDValue LHS = Op.getOperand(0);
2786 SDValue RHS = Op.getOperand(1);
2787 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2788 SDValue TrueVal = Op.getOperand(2);
2789 SDValue FalseVal = Op.getOperand(3);
2790 DebugLoc dl = Op.getDebugLoc();
2792 if (LHS.getValueType() == MVT::i32) {
2794 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2795 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2796 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,Cmp);
2799 ARMCC::CondCodes CondCode, CondCode2;
2800 FPCCToARMCC(CC, CondCode, CondCode2);
2802 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2803 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2804 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2805 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
2807 if (CondCode2 != ARMCC::AL) {
2808 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32);
2809 // FIXME: Needs another CMP because flag can have but one use.
2810 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
2811 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
2812 Result, TrueVal, ARMcc2, CCR, Cmp2);
2817 /// canChangeToInt - Given the fp compare operand, return true if it is suitable
2818 /// to morph to an integer compare sequence.
2819 static bool canChangeToInt(SDValue Op, bool &SeenZero,
2820 const ARMSubtarget *Subtarget) {
2821 SDNode *N = Op.getNode();
2822 if (!N->hasOneUse())
2823 // Otherwise it requires moving the value from fp to integer registers.
2825 if (!N->getNumValues())
2827 EVT VT = Op.getValueType();
2828 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
2829 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
2830 // vmrs are very slow, e.g. cortex-a8.
2833 if (isFloatingPointZero(Op)) {
2837 return ISD::isNormalLoad(N);
2840 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
2841 if (isFloatingPointZero(Op))
2842 return DAG.getConstant(0, MVT::i32);
2844 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
2845 return DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2846 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(),
2847 Ld->isVolatile(), Ld->isNonTemporal(),
2848 Ld->getAlignment());
2850 llvm_unreachable("Unknown VFP cmp argument!");
2853 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
2854 SDValue &RetVal1, SDValue &RetVal2) {
2855 if (isFloatingPointZero(Op)) {
2856 RetVal1 = DAG.getConstant(0, MVT::i32);
2857 RetVal2 = DAG.getConstant(0, MVT::i32);
2861 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
2862 SDValue Ptr = Ld->getBasePtr();
2863 RetVal1 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2864 Ld->getChain(), Ptr,
2865 Ld->getPointerInfo(),
2866 Ld->isVolatile(), Ld->isNonTemporal(),
2867 Ld->getAlignment());
2869 EVT PtrType = Ptr.getValueType();
2870 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
2871 SDValue NewPtr = DAG.getNode(ISD::ADD, Op.getDebugLoc(),
2872 PtrType, Ptr, DAG.getConstant(4, PtrType));
2873 RetVal2 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2874 Ld->getChain(), NewPtr,
2875 Ld->getPointerInfo().getWithOffset(4),
2876 Ld->isVolatile(), Ld->isNonTemporal(),
2881 llvm_unreachable("Unknown VFP cmp argument!");
2884 /// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
2885 /// f32 and even f64 comparisons to integer ones.
2887 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
2888 SDValue Chain = Op.getOperand(0);
2889 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2890 SDValue LHS = Op.getOperand(2);
2891 SDValue RHS = Op.getOperand(3);
2892 SDValue Dest = Op.getOperand(4);
2893 DebugLoc dl = Op.getDebugLoc();
2895 bool SeenZero = false;
2896 if (canChangeToInt(LHS, SeenZero, Subtarget) &&
2897 canChangeToInt(RHS, SeenZero, Subtarget) &&
2898 // If one of the operand is zero, it's safe to ignore the NaN case since
2899 // we only care about equality comparisons.
2900 (SeenZero || (DAG.isKnownNeverNaN(LHS) && DAG.isKnownNeverNaN(RHS)))) {
2901 // If unsafe fp math optimization is enabled and there are no other uses of
2902 // the CMP operands, and the condition code is EQ or NE, we can optimize it
2903 // to an integer comparison.
2904 if (CC == ISD::SETOEQ)
2906 else if (CC == ISD::SETUNE)
2910 if (LHS.getValueType() == MVT::f32) {
2911 LHS = bitcastf32Toi32(LHS, DAG);
2912 RHS = bitcastf32Toi32(RHS, DAG);
2913 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2914 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2915 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2916 Chain, Dest, ARMcc, CCR, Cmp);
2921 expandf64Toi32(LHS, DAG, LHS1, LHS2);
2922 expandf64Toi32(RHS, DAG, RHS1, RHS2);
2923 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2924 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2925 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
2926 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
2927 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7);
2933 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2934 SDValue Chain = Op.getOperand(0);
2935 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2936 SDValue LHS = Op.getOperand(2);
2937 SDValue RHS = Op.getOperand(3);
2938 SDValue Dest = Op.getOperand(4);
2939 DebugLoc dl = Op.getDebugLoc();
2941 if (LHS.getValueType() == MVT::i32) {
2943 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2944 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2945 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2946 Chain, Dest, ARMcc, CCR, Cmp);
2949 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
2952 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
2953 CC == ISD::SETNE || CC == ISD::SETUNE)) {
2954 SDValue Result = OptimizeVFPBrcond(Op, DAG);
2955 if (Result.getNode())
2959 ARMCC::CondCodes CondCode, CondCode2;
2960 FPCCToARMCC(CC, CondCode, CondCode2);
2962 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2963 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2964 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2965 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
2966 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
2967 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2968 if (CondCode2 != ARMCC::AL) {
2969 ARMcc = DAG.getConstant(CondCode2, MVT::i32);
2970 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
2971 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2976 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
2977 SDValue Chain = Op.getOperand(0);
2978 SDValue Table = Op.getOperand(1);
2979 SDValue Index = Op.getOperand(2);
2980 DebugLoc dl = Op.getDebugLoc();
2982 EVT PTy = getPointerTy();
2983 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
2984 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
2985 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
2986 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
2987 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
2988 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
2989 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2990 if (Subtarget->isThumb2()) {
2991 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
2992 // which does another jump to the destination. This also makes it easier
2993 // to translate it to TBB / TBH later.
2994 // FIXME: This might not work if the function is extremely large.
2995 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
2996 Addr, Op.getOperand(2), JTI, UId);
2998 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2999 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
3000 MachinePointerInfo::getJumpTable(),
3002 Chain = Addr.getValue(1);
3003 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
3004 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
3006 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
3007 MachinePointerInfo::getJumpTable(), false, false, 0);
3008 Chain = Addr.getValue(1);
3009 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
3013 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
3014 DebugLoc dl = Op.getDebugLoc();
3017 switch (Op.getOpcode()) {
3019 assert(0 && "Invalid opcode!");
3020 case ISD::FP_TO_SINT:
3021 Opc = ARMISD::FTOSI;
3023 case ISD::FP_TO_UINT:
3024 Opc = ARMISD::FTOUI;
3027 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
3028 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3031 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
3032 EVT VT = Op.getValueType();
3033 DebugLoc dl = Op.getDebugLoc();
3035 assert(Op.getOperand(0).getValueType() == MVT::v4i16 &&
3036 "Invalid type for custom lowering!");
3037 if (VT != MVT::v4f32)
3038 return DAG.UnrollVectorOp(Op.getNode());
3042 switch (Op.getOpcode()) {
3044 assert(0 && "Invalid opcode!");
3045 case ISD::SINT_TO_FP:
3046 CastOpc = ISD::SIGN_EXTEND;
3047 Opc = ISD::SINT_TO_FP;
3049 case ISD::UINT_TO_FP:
3050 CastOpc = ISD::ZERO_EXTEND;
3051 Opc = ISD::UINT_TO_FP;
3055 Op = DAG.getNode(CastOpc, dl, MVT::v4i32, Op.getOperand(0));
3056 return DAG.getNode(Opc, dl, VT, Op);
3059 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
3060 EVT VT = Op.getValueType();
3062 return LowerVectorINT_TO_FP(Op, DAG);
3064 DebugLoc dl = Op.getDebugLoc();
3067 switch (Op.getOpcode()) {
3069 assert(0 && "Invalid opcode!");
3070 case ISD::SINT_TO_FP:
3071 Opc = ARMISD::SITOF;
3073 case ISD::UINT_TO_FP:
3074 Opc = ARMISD::UITOF;
3078 Op = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0));
3079 return DAG.getNode(Opc, dl, VT, Op);
3082 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
3083 // Implement fcopysign with a fabs and a conditional fneg.
3084 SDValue Tmp0 = Op.getOperand(0);
3085 SDValue Tmp1 = Op.getOperand(1);
3086 DebugLoc dl = Op.getDebugLoc();
3087 EVT VT = Op.getValueType();
3088 EVT SrcVT = Tmp1.getValueType();
3089 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
3090 Tmp0.getOpcode() == ARMISD::VMOVDRR;
3091 bool UseNEON = !InGPR && Subtarget->hasNEON();
3094 // Use VBSL to copy the sign bit.
3095 unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80);
3096 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
3097 DAG.getTargetConstant(EncodedVal, MVT::i32));
3098 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
3100 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT,
3101 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
3102 DAG.getConstant(32, MVT::i32));
3103 else /*if (VT == MVT::f32)*/
3104 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
3105 if (SrcVT == MVT::f32) {
3106 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
3108 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT,
3109 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
3110 DAG.getConstant(32, MVT::i32));
3111 } else if (VT == MVT::f32)
3112 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64,
3113 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
3114 DAG.getConstant(32, MVT::i32));
3115 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
3116 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
3118 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff),
3120 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
3121 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
3122 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
3124 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
3125 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
3126 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
3127 if (VT == MVT::f32) {
3128 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
3129 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
3130 DAG.getConstant(0, MVT::i32));
3132 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
3138 // Bitcast operand 1 to i32.
3139 if (SrcVT == MVT::f64)
3140 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
3141 &Tmp1, 1).getValue(1);
3142 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
3144 // Or in the signbit with integer operations.
3145 SDValue Mask1 = DAG.getConstant(0x80000000, MVT::i32);
3146 SDValue Mask2 = DAG.getConstant(0x7fffffff, MVT::i32);
3147 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
3148 if (VT == MVT::f32) {
3149 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
3150 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
3151 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3152 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
3155 // f64: Or the high part with signbit and then combine two parts.
3156 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
3158 SDValue Lo = Tmp0.getValue(0);
3159 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
3160 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
3161 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
3164 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
3165 MachineFunction &MF = DAG.getMachineFunction();
3166 MachineFrameInfo *MFI = MF.getFrameInfo();
3167 MFI->setReturnAddressIsTaken(true);
3169 EVT VT = Op.getValueType();
3170 DebugLoc dl = Op.getDebugLoc();
3171 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3173 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
3174 SDValue Offset = DAG.getConstant(4, MVT::i32);
3175 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
3176 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
3177 MachinePointerInfo(), false, false, 0);
3180 // Return LR, which contains the return address. Mark it an implicit live-in.
3181 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
3182 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
3185 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
3186 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3187 MFI->setFrameAddressIsTaken(true);
3189 EVT VT = Op.getValueType();
3190 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
3191 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3192 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
3193 ? ARM::R7 : ARM::R11;
3194 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
3196 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
3197 MachinePointerInfo(),
3202 /// ExpandBITCAST - If the target supports VFP, this function is called to
3203 /// expand a bit convert where either the source or destination type is i64 to
3204 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
3205 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
3206 /// vectors), since the legalizer won't know what to do with that.
3207 static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) {
3208 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3209 DebugLoc dl = N->getDebugLoc();
3210 SDValue Op = N->getOperand(0);
3212 // This function is only supposed to be called for i64 types, either as the
3213 // source or destination of the bit convert.
3214 EVT SrcVT = Op.getValueType();
3215 EVT DstVT = N->getValueType(0);
3216 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
3217 "ExpandBITCAST called for non-i64 type");
3219 // Turn i64->f64 into VMOVDRR.
3220 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
3221 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
3222 DAG.getConstant(0, MVT::i32));
3223 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
3224 DAG.getConstant(1, MVT::i32));
3225 return DAG.getNode(ISD::BITCAST, dl, DstVT,
3226 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
3229 // Turn f64->i64 into VMOVRRD.
3230 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
3231 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
3232 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
3233 // Merge the pieces into a single i64 value.
3234 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
3240 /// getZeroVector - Returns a vector of specified type with all zero elements.
3241 /// Zero vectors are used to represent vector negation and in those cases
3242 /// will be implemented with the NEON VNEG instruction. However, VNEG does
3243 /// not support i64 elements, so sometimes the zero vectors will need to be
3244 /// explicitly constructed. Regardless, use a canonical VMOV to create the
3246 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3247 assert(VT.isVector() && "Expected a vector type");
3248 // The canonical modified immediate encoding of a zero vector is....0!
3249 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32);
3250 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
3251 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
3252 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3255 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
3256 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
3257 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
3258 SelectionDAG &DAG) const {
3259 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3260 EVT VT = Op.getValueType();
3261 unsigned VTBits = VT.getSizeInBits();
3262 DebugLoc dl = Op.getDebugLoc();
3263 SDValue ShOpLo = Op.getOperand(0);
3264 SDValue ShOpHi = Op.getOperand(1);
3265 SDValue ShAmt = Op.getOperand(2);
3267 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
3269 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
3271 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
3272 DAG.getConstant(VTBits, MVT::i32), ShAmt);
3273 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
3274 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
3275 DAG.getConstant(VTBits, MVT::i32));
3276 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
3277 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3278 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
3280 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3281 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
3283 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
3284 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
3287 SDValue Ops[2] = { Lo, Hi };
3288 return DAG.getMergeValues(Ops, 2, dl);
3291 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
3292 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
3293 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
3294 SelectionDAG &DAG) const {
3295 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3296 EVT VT = Op.getValueType();
3297 unsigned VTBits = VT.getSizeInBits();
3298 DebugLoc dl = Op.getDebugLoc();
3299 SDValue ShOpLo = Op.getOperand(0);
3300 SDValue ShOpHi = Op.getOperand(1);
3301 SDValue ShAmt = Op.getOperand(2);
3304 assert(Op.getOpcode() == ISD::SHL_PARTS);
3305 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
3306 DAG.getConstant(VTBits, MVT::i32), ShAmt);
3307 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
3308 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
3309 DAG.getConstant(VTBits, MVT::i32));
3310 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
3311 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
3313 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3314 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3315 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
3317 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
3318 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
3321 SDValue Ops[2] = { Lo, Hi };
3322 return DAG.getMergeValues(Ops, 2, dl);
3325 SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
3326 SelectionDAG &DAG) const {
3327 // The rounding mode is in bits 23:22 of the FPSCR.
3328 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
3329 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
3330 // so that the shift + and get folded into a bitfield extract.
3331 DebugLoc dl = Op.getDebugLoc();
3332 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
3333 DAG.getConstant(Intrinsic::arm_get_fpscr,
3335 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
3336 DAG.getConstant(1U << 22, MVT::i32));
3337 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
3338 DAG.getConstant(22, MVT::i32));
3339 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
3340 DAG.getConstant(3, MVT::i32));
3343 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
3344 const ARMSubtarget *ST) {
3345 EVT VT = N->getValueType(0);
3346 DebugLoc dl = N->getDebugLoc();
3348 if (!ST->hasV6T2Ops())
3351 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
3352 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
3355 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
3356 const ARMSubtarget *ST) {
3357 EVT VT = N->getValueType(0);
3358 DebugLoc dl = N->getDebugLoc();
3363 // Lower vector shifts on NEON to use VSHL.
3364 assert(ST->hasNEON() && "unexpected vector shift");
3366 // Left shifts translate directly to the vshiftu intrinsic.
3367 if (N->getOpcode() == ISD::SHL)
3368 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
3369 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
3370 N->getOperand(0), N->getOperand(1));
3372 assert((N->getOpcode() == ISD::SRA ||
3373 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
3375 // NEON uses the same intrinsics for both left and right shifts. For
3376 // right shifts, the shift amounts are negative, so negate the vector of
3378 EVT ShiftVT = N->getOperand(1).getValueType();
3379 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
3380 getZeroVector(ShiftVT, DAG, dl),
3382 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
3383 Intrinsic::arm_neon_vshifts :
3384 Intrinsic::arm_neon_vshiftu);
3385 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
3386 DAG.getConstant(vshiftInt, MVT::i32),
3387 N->getOperand(0), NegatedCount);
3390 static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
3391 const ARMSubtarget *ST) {
3392 EVT VT = N->getValueType(0);
3393 DebugLoc dl = N->getDebugLoc();
3395 // We can get here for a node like i32 = ISD::SHL i32, i64
3399 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
3400 "Unknown shift to lower!");
3402 // We only lower SRA, SRL of 1 here, all others use generic lowering.
3403 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
3404 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
3407 // If we are in thumb mode, we don't have RRX.
3408 if (ST->isThumb1Only()) return SDValue();
3410 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
3411 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
3412 DAG.getConstant(0, MVT::i32));
3413 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
3414 DAG.getConstant(1, MVT::i32));
3416 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
3417 // captures the result into a carry flag.
3418 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
3419 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), &Hi, 1);
3421 // The low part is an ARMISD::RRX operand, which shifts the carry in.
3422 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
3424 // Merge the pieces into a single i64 value.
3425 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
3428 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
3429 SDValue TmpOp0, TmpOp1;
3430 bool Invert = false;
3434 SDValue Op0 = Op.getOperand(0);
3435 SDValue Op1 = Op.getOperand(1);
3436 SDValue CC = Op.getOperand(2);
3437 EVT VT = Op.getValueType();
3438 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
3439 DebugLoc dl = Op.getDebugLoc();
3441 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
3442 switch (SetCCOpcode) {
3443 default: llvm_unreachable("Illegal FP comparison"); break;
3445 case ISD::SETNE: Invert = true; // Fallthrough
3447 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3449 case ISD::SETLT: Swap = true; // Fallthrough
3451 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3453 case ISD::SETLE: Swap = true; // Fallthrough
3455 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3456 case ISD::SETUGE: Swap = true; // Fallthrough
3457 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
3458 case ISD::SETUGT: Swap = true; // Fallthrough
3459 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
3460 case ISD::SETUEQ: Invert = true; // Fallthrough
3462 // Expand this to (OLT | OGT).
3466 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3467 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
3469 case ISD::SETUO: Invert = true; // Fallthrough
3471 // Expand this to (OLT | OGE).
3475 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3476 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
3480 // Integer comparisons.
3481 switch (SetCCOpcode) {
3482 default: llvm_unreachable("Illegal integer comparison"); break;
3483 case ISD::SETNE: Invert = true;
3484 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3485 case ISD::SETLT: Swap = true;
3486 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3487 case ISD::SETLE: Swap = true;
3488 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3489 case ISD::SETULT: Swap = true;
3490 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
3491 case ISD::SETULE: Swap = true;
3492 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
3495 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
3496 if (Opc == ARMISD::VCEQ) {
3499 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
3501 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
3504 // Ignore bitconvert.
3505 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST)
3506 AndOp = AndOp.getOperand(0);
3508 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
3510 Op0 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(0));
3511 Op1 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(1));
3518 std::swap(Op0, Op1);
3520 // If one of the operands is a constant vector zero, attempt to fold the
3521 // comparison to a specialized compare-against-zero form.
3523 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
3525 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) {
3526 if (Opc == ARMISD::VCGE)
3527 Opc = ARMISD::VCLEZ;
3528 else if (Opc == ARMISD::VCGT)
3529 Opc = ARMISD::VCLTZ;
3534 if (SingleOp.getNode()) {
3537 Result = DAG.getNode(ARMISD::VCEQZ, dl, VT, SingleOp); break;
3539 Result = DAG.getNode(ARMISD::VCGEZ, dl, VT, SingleOp); break;
3541 Result = DAG.getNode(ARMISD::VCLEZ, dl, VT, SingleOp); break;
3543 Result = DAG.getNode(ARMISD::VCGTZ, dl, VT, SingleOp); break;
3545 Result = DAG.getNode(ARMISD::VCLTZ, dl, VT, SingleOp); break;
3547 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3550 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3554 Result = DAG.getNOT(dl, Result, VT);
3559 /// isNEONModifiedImm - Check if the specified splat value corresponds to a
3560 /// valid vector constant for a NEON instruction with a "modified immediate"
3561 /// operand (e.g., VMOV). If so, return the encoded value.
3562 static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
3563 unsigned SplatBitSize, SelectionDAG &DAG,
3564 EVT &VT, bool is128Bits, NEONModImmType type) {
3565 unsigned OpCmode, Imm;
3567 // SplatBitSize is set to the smallest size that splats the vector, so a
3568 // zero vector will always have SplatBitSize == 8. However, NEON modified
3569 // immediate instructions others than VMOV do not support the 8-bit encoding
3570 // of a zero vector, and the default encoding of zero is supposed to be the
3575 switch (SplatBitSize) {
3577 if (type != VMOVModImm)
3579 // Any 1-byte value is OK. Op=0, Cmode=1110.
3580 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
3583 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
3587 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
3588 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
3589 if ((SplatBits & ~0xff) == 0) {
3590 // Value = 0x00nn: Op=x, Cmode=100x.
3595 if ((SplatBits & ~0xff00) == 0) {
3596 // Value = 0xnn00: Op=x, Cmode=101x.
3598 Imm = SplatBits >> 8;
3604 // NEON's 32-bit VMOV supports splat values where:
3605 // * only one byte is nonzero, or
3606 // * the least significant byte is 0xff and the second byte is nonzero, or
3607 // * the least significant 2 bytes are 0xff and the third is nonzero.
3608 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
3609 if ((SplatBits & ~0xff) == 0) {
3610 // Value = 0x000000nn: Op=x, Cmode=000x.
3615 if ((SplatBits & ~0xff00) == 0) {
3616 // Value = 0x0000nn00: Op=x, Cmode=001x.
3618 Imm = SplatBits >> 8;
3621 if ((SplatBits & ~0xff0000) == 0) {
3622 // Value = 0x00nn0000: Op=x, Cmode=010x.
3624 Imm = SplatBits >> 16;
3627 if ((SplatBits & ~0xff000000) == 0) {
3628 // Value = 0xnn000000: Op=x, Cmode=011x.
3630 Imm = SplatBits >> 24;
3634 // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC
3635 if (type == OtherModImm) return SDValue();
3637 if ((SplatBits & ~0xffff) == 0 &&
3638 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
3639 // Value = 0x0000nnff: Op=x, Cmode=1100.
3641 Imm = SplatBits >> 8;
3646 if ((SplatBits & ~0xffffff) == 0 &&
3647 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
3648 // Value = 0x00nnffff: Op=x, Cmode=1101.
3650 Imm = SplatBits >> 16;
3651 SplatBits |= 0xffff;
3655 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
3656 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
3657 // VMOV.I32. A (very) minor optimization would be to replicate the value
3658 // and fall through here to test for a valid 64-bit splat. But, then the
3659 // caller would also need to check and handle the change in size.
3663 if (type != VMOVModImm)
3665 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
3666 uint64_t BitMask = 0xff;
3668 unsigned ImmMask = 1;
3670 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
3671 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
3674 } else if ((SplatBits & BitMask) != 0) {
3680 // Op=1, Cmode=1110.
3683 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
3688 llvm_unreachable("unexpected size for isNEONModifiedImm");
3692 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
3693 return DAG.getTargetConstant(EncodedVal, MVT::i32);
3696 static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT,
3697 bool &ReverseVEXT, unsigned &Imm) {
3698 unsigned NumElts = VT.getVectorNumElements();
3699 ReverseVEXT = false;
3701 // Assume that the first shuffle index is not UNDEF. Fail if it is.
3707 // If this is a VEXT shuffle, the immediate value is the index of the first
3708 // element. The other shuffle indices must be the successive elements after
3710 unsigned ExpectedElt = Imm;
3711 for (unsigned i = 1; i < NumElts; ++i) {
3712 // Increment the expected index. If it wraps around, it may still be
3713 // a VEXT but the source vectors must be swapped.
3715 if (ExpectedElt == NumElts * 2) {
3720 if (M[i] < 0) continue; // ignore UNDEF indices
3721 if (ExpectedElt != static_cast<unsigned>(M[i]))
3725 // Adjust the index value if the source operands will be swapped.
3732 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
3733 /// instruction with the specified blocksize. (The order of the elements
3734 /// within each block of the vector is reversed.)
3735 static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT,
3736 unsigned BlockSize) {
3737 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
3738 "Only possible block sizes for VREV are: 16, 32, 64");
3740 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3744 unsigned NumElts = VT.getVectorNumElements();
3745 unsigned BlockElts = M[0] + 1;
3746 // If the first shuffle index is UNDEF, be optimistic.
3748 BlockElts = BlockSize / EltSz;
3750 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
3753 for (unsigned i = 0; i < NumElts; ++i) {
3754 if (M[i] < 0) continue; // ignore UNDEF indices
3755 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
3762 static bool isVTBLMask(const SmallVectorImpl<int> &M, EVT VT) {
3763 // We can handle <8 x i8> vector shuffles. If the index in the mask is out of
3764 // range, then 0 is placed into the resulting vector. So pretty much any mask
3765 // of 8 elements can work here.
3766 return VT == MVT::v8i8 && M.size() == 8;
3769 static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT,
3770 unsigned &WhichResult) {
3771 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3775 unsigned NumElts = VT.getVectorNumElements();
3776 WhichResult = (M[0] == 0 ? 0 : 1);
3777 for (unsigned i = 0; i < NumElts; i += 2) {
3778 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3779 (M[i+1] >= 0 && (unsigned) M[i+1] != i + NumElts + WhichResult))
3785 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
3786 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3787 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
3788 static bool isVTRN_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3789 unsigned &WhichResult) {
3790 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3794 unsigned NumElts = VT.getVectorNumElements();
3795 WhichResult = (M[0] == 0 ? 0 : 1);
3796 for (unsigned i = 0; i < NumElts; i += 2) {
3797 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3798 (M[i+1] >= 0 && (unsigned) M[i+1] != i + WhichResult))
3804 static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT,
3805 unsigned &WhichResult) {
3806 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3810 unsigned NumElts = VT.getVectorNumElements();
3811 WhichResult = (M[0] == 0 ? 0 : 1);
3812 for (unsigned i = 0; i != NumElts; ++i) {
3813 if (M[i] < 0) continue; // ignore UNDEF indices
3814 if ((unsigned) M[i] != 2 * i + WhichResult)
3818 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3819 if (VT.is64BitVector() && EltSz == 32)
3825 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
3826 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3827 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
3828 static bool isVUZP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3829 unsigned &WhichResult) {
3830 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3834 unsigned Half = VT.getVectorNumElements() / 2;
3835 WhichResult = (M[0] == 0 ? 0 : 1);
3836 for (unsigned j = 0; j != 2; ++j) {
3837 unsigned Idx = WhichResult;
3838 for (unsigned i = 0; i != Half; ++i) {
3839 int MIdx = M[i + j * Half];
3840 if (MIdx >= 0 && (unsigned) MIdx != Idx)
3846 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3847 if (VT.is64BitVector() && EltSz == 32)
3853 static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT,
3854 unsigned &WhichResult) {
3855 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3859 unsigned NumElts = VT.getVectorNumElements();
3860 WhichResult = (M[0] == 0 ? 0 : 1);
3861 unsigned Idx = WhichResult * NumElts / 2;
3862 for (unsigned i = 0; i != NumElts; i += 2) {
3863 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3864 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts))
3869 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3870 if (VT.is64BitVector() && EltSz == 32)
3876 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
3877 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3878 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
3879 static bool isVZIP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3880 unsigned &WhichResult) {
3881 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3885 unsigned NumElts = VT.getVectorNumElements();
3886 WhichResult = (M[0] == 0 ? 0 : 1);
3887 unsigned Idx = WhichResult * NumElts / 2;
3888 for (unsigned i = 0; i != NumElts; i += 2) {
3889 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3890 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx))
3895 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3896 if (VT.is64BitVector() && EltSz == 32)
3902 // If N is an integer constant that can be moved into a register in one
3903 // instruction, return an SDValue of such a constant (will become a MOV
3904 // instruction). Otherwise return null.
3905 static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG,
3906 const ARMSubtarget *ST, DebugLoc dl) {
3908 if (!isa<ConstantSDNode>(N))
3910 Val = cast<ConstantSDNode>(N)->getZExtValue();
3912 if (ST->isThumb1Only()) {
3913 if (Val <= 255 || ~Val <= 255)
3914 return DAG.getConstant(Val, MVT::i32);
3916 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1)
3917 return DAG.getConstant(Val, MVT::i32);
3922 // If this is a case we can't handle, return null and let the default
3923 // expansion code take care of it.
3924 SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
3925 const ARMSubtarget *ST) const {
3926 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
3927 DebugLoc dl = Op.getDebugLoc();
3928 EVT VT = Op.getValueType();
3930 APInt SplatBits, SplatUndef;
3931 unsigned SplatBitSize;
3933 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
3934 if (SplatBitSize <= 64) {
3935 // Check if an immediate VMOV works.
3937 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
3938 SplatUndef.getZExtValue(), SplatBitSize,
3939 DAG, VmovVT, VT.is128BitVector(),
3941 if (Val.getNode()) {
3942 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
3943 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3946 // Try an immediate VMVN.
3947 uint64_t NegatedImm = (SplatBits.getZExtValue() ^
3948 ((1LL << SplatBitSize) - 1));
3949 Val = isNEONModifiedImm(NegatedImm,
3950 SplatUndef.getZExtValue(), SplatBitSize,
3951 DAG, VmovVT, VT.is128BitVector(),
3953 if (Val.getNode()) {
3954 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
3955 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3960 // Scan through the operands to see if only one value is used.
3961 unsigned NumElts = VT.getVectorNumElements();
3962 bool isOnlyLowElement = true;
3963 bool usesOnlyOneValue = true;
3964 bool isConstant = true;
3966 for (unsigned i = 0; i < NumElts; ++i) {
3967 SDValue V = Op.getOperand(i);
3968 if (V.getOpcode() == ISD::UNDEF)
3971 isOnlyLowElement = false;
3972 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
3975 if (!Value.getNode())
3977 else if (V != Value)
3978 usesOnlyOneValue = false;
3981 if (!Value.getNode())
3982 return DAG.getUNDEF(VT);
3984 if (isOnlyLowElement)
3985 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
3987 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3989 // Use VDUP for non-constant splats. For f32 constant splats, reduce to
3990 // i32 and try again.
3991 if (usesOnlyOneValue && EltSize <= 32) {
3993 return DAG.getNode(ARMISD::VDUP, dl, VT, Value);
3994 if (VT.getVectorElementType().isFloatingPoint()) {
3995 SmallVector<SDValue, 8> Ops;
3996 for (unsigned i = 0; i < NumElts; ++i)
3997 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32,
3999 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
4000 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], NumElts);
4001 Val = LowerBUILD_VECTOR(Val, DAG, ST);
4003 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
4005 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
4007 return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
4010 // If all elements are constants and the case above didn't get hit, fall back
4011 // to the default expansion, which will generate a load from the constant
4016 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
4018 SDValue shuffle = ReconstructShuffle(Op, DAG);
4019 if (shuffle != SDValue())
4023 // Vectors with 32- or 64-bit elements can be built by directly assigning
4024 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
4025 // will be legalized.
4026 if (EltSize >= 32) {
4027 // Do the expansion with floating-point types, since that is what the VFP
4028 // registers are defined to use, and since i64 is not legal.
4029 EVT EltVT = EVT::getFloatingPointVT(EltSize);
4030 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
4031 SmallVector<SDValue, 8> Ops;
4032 for (unsigned i = 0; i < NumElts; ++i)
4033 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i)));
4034 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
4035 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
4041 // Gather data to see if the operation can be modelled as a
4042 // shuffle in combination with VEXTs.
4043 SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
4044 SelectionDAG &DAG) const {
4045 DebugLoc dl = Op.getDebugLoc();
4046 EVT VT = Op.getValueType();
4047 unsigned NumElts = VT.getVectorNumElements();
4049 SmallVector<SDValue, 2> SourceVecs;
4050 SmallVector<unsigned, 2> MinElts;
4051 SmallVector<unsigned, 2> MaxElts;
4053 for (unsigned i = 0; i < NumElts; ++i) {
4054 SDValue V = Op.getOperand(i);
4055 if (V.getOpcode() == ISD::UNDEF)
4057 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
4058 // A shuffle can only come from building a vector from various
4059 // elements of other vectors.
4063 // Record this extraction against the appropriate vector if possible...
4064 SDValue SourceVec = V.getOperand(0);
4065 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
4066 bool FoundSource = false;
4067 for (unsigned j = 0; j < SourceVecs.size(); ++j) {
4068 if (SourceVecs[j] == SourceVec) {
4069 if (MinElts[j] > EltNo)
4071 if (MaxElts[j] < EltNo)
4078 // Or record a new source if not...
4080 SourceVecs.push_back(SourceVec);
4081 MinElts.push_back(EltNo);
4082 MaxElts.push_back(EltNo);
4086 // Currently only do something sane when at most two source vectors
4088 if (SourceVecs.size() > 2)
4091 SDValue ShuffleSrcs[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT) };
4092 int VEXTOffsets[2] = {0, 0};
4094 // This loop extracts the usage patterns of the source vectors
4095 // and prepares appropriate SDValues for a shuffle if possible.
4096 for (unsigned i = 0; i < SourceVecs.size(); ++i) {
4097 if (SourceVecs[i].getValueType() == VT) {
4098 // No VEXT necessary
4099 ShuffleSrcs[i] = SourceVecs[i];
4102 } else if (SourceVecs[i].getValueType().getVectorNumElements() < NumElts) {
4103 // It probably isn't worth padding out a smaller vector just to
4104 // break it down again in a shuffle.
4108 // Since only 64-bit and 128-bit vectors are legal on ARM and
4109 // we've eliminated the other cases...
4110 assert(SourceVecs[i].getValueType().getVectorNumElements() == 2*NumElts &&
4111 "unexpected vector sizes in ReconstructShuffle");
4113 if (MaxElts[i] - MinElts[i] >= NumElts) {
4114 // Span too large for a VEXT to cope
4118 if (MinElts[i] >= NumElts) {
4119 // The extraction can just take the second half
4120 VEXTOffsets[i] = NumElts;
4121 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4123 DAG.getIntPtrConstant(NumElts));
4124 } else if (MaxElts[i] < NumElts) {
4125 // The extraction can just take the first half
4127 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4129 DAG.getIntPtrConstant(0));
4131 // An actual VEXT is needed
4132 VEXTOffsets[i] = MinElts[i];
4133 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4135 DAG.getIntPtrConstant(0));
4136 SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4138 DAG.getIntPtrConstant(NumElts));
4139 ShuffleSrcs[i] = DAG.getNode(ARMISD::VEXT, dl, VT, VEXTSrc1, VEXTSrc2,
4140 DAG.getConstant(VEXTOffsets[i], MVT::i32));
4144 SmallVector<int, 8> Mask;
4146 for (unsigned i = 0; i < NumElts; ++i) {
4147 SDValue Entry = Op.getOperand(i);
4148 if (Entry.getOpcode() == ISD::UNDEF) {
4153 SDValue ExtractVec = Entry.getOperand(0);
4154 int ExtractElt = cast<ConstantSDNode>(Op.getOperand(i)
4155 .getOperand(1))->getSExtValue();
4156 if (ExtractVec == SourceVecs[0]) {
4157 Mask.push_back(ExtractElt - VEXTOffsets[0]);
4159 Mask.push_back(ExtractElt + NumElts - VEXTOffsets[1]);
4163 // Final check before we try to produce nonsense...
4164 if (isShuffleMaskLegal(Mask, VT))
4165 return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1],
4171 /// isShuffleMaskLegal - Targets can use this to indicate that they only
4172 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
4173 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
4174 /// are assumed to be legal.
4176 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
4178 if (VT.getVectorNumElements() == 4 &&
4179 (VT.is128BitVector() || VT.is64BitVector())) {
4180 unsigned PFIndexes[4];
4181 for (unsigned i = 0; i != 4; ++i) {
4185 PFIndexes[i] = M[i];
4188 // Compute the index in the perfect shuffle table.
4189 unsigned PFTableIndex =
4190 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
4191 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4192 unsigned Cost = (PFEntry >> 30);
4199 unsigned Imm, WhichResult;
4201 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4202 return (EltSize >= 32 ||
4203 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
4204 isVREVMask(M, VT, 64) ||
4205 isVREVMask(M, VT, 32) ||
4206 isVREVMask(M, VT, 16) ||
4207 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
4208 isVTBLMask(M, VT) ||
4209 isVTRNMask(M, VT, WhichResult) ||
4210 isVUZPMask(M, VT, WhichResult) ||
4211 isVZIPMask(M, VT, WhichResult) ||
4212 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
4213 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
4214 isVZIP_v_undef_Mask(M, VT, WhichResult));
4217 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
4218 /// the specified operations to build the shuffle.
4219 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
4220 SDValue RHS, SelectionDAG &DAG,
4222 unsigned OpNum = (PFEntry >> 26) & 0x0F;
4223 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
4224 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
4227 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
4236 OP_VUZPL, // VUZP, left result
4237 OP_VUZPR, // VUZP, right result
4238 OP_VZIPL, // VZIP, left result
4239 OP_VZIPR, // VZIP, right result
4240 OP_VTRNL, // VTRN, left result
4241 OP_VTRNR // VTRN, right result
4244 if (OpNum == OP_COPY) {
4245 if (LHSID == (1*9+2)*9+3) return LHS;
4246 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
4250 SDValue OpLHS, OpRHS;
4251 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
4252 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
4253 EVT VT = OpLHS.getValueType();
4256 default: llvm_unreachable("Unknown shuffle opcode!");
4258 // VREV divides the vector in half and swaps within the half.
4259 if (VT.getVectorElementType() == MVT::i32 ||
4260 VT.getVectorElementType() == MVT::f32)
4261 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
4262 // vrev <4 x i16> -> VREV32
4263 if (VT.getVectorElementType() == MVT::i16)
4264 return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS);
4265 // vrev <4 x i8> -> VREV16
4266 assert(VT.getVectorElementType() == MVT::i8);
4267 return DAG.getNode(ARMISD::VREV16, dl, VT, OpLHS);
4272 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
4273 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
4277 return DAG.getNode(ARMISD::VEXT, dl, VT,
4279 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
4282 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4283 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
4286 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4287 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
4290 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4291 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
4295 static SDValue LowerVECTOR_SHUFFLEv8i8(SDValue Op,
4296 SmallVectorImpl<int> &ShuffleMask,
4297 SelectionDAG &DAG) {
4298 // Check to see if we can use the VTBL instruction.
4299 SDValue V1 = Op.getOperand(0);
4300 SDValue V2 = Op.getOperand(1);
4301 DebugLoc DL = Op.getDebugLoc();
4303 SmallVector<SDValue, 8> VTBLMask;
4304 for (SmallVectorImpl<int>::iterator
4305 I = ShuffleMask.begin(), E = ShuffleMask.end(); I != E; ++I)
4306 VTBLMask.push_back(DAG.getConstant(*I, MVT::i32));
4308 if (V2.getNode()->getOpcode() == ISD::UNDEF)
4309 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1,
4310 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
4313 return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2,
4314 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
4318 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
4319 SDValue V1 = Op.getOperand(0);
4320 SDValue V2 = Op.getOperand(1);
4321 DebugLoc dl = Op.getDebugLoc();
4322 EVT VT = Op.getValueType();
4323 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
4324 SmallVector<int, 8> ShuffleMask;
4326 // Convert shuffles that are directly supported on NEON to target-specific
4327 // DAG nodes, instead of keeping them as shuffles and matching them again
4328 // during code selection. This is more efficient and avoids the possibility
4329 // of inconsistencies between legalization and selection.
4330 // FIXME: floating-point vectors should be canonicalized to integer vectors
4331 // of the same time so that they get CSEd properly.
4332 SVN->getMask(ShuffleMask);
4334 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4335 if (EltSize <= 32) {
4336 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
4337 int Lane = SVN->getSplatIndex();
4338 // If this is undef splat, generate it via "just" vdup, if possible.
4339 if (Lane == -1) Lane = 0;
4341 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4342 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
4344 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
4345 DAG.getConstant(Lane, MVT::i32));
4350 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
4353 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
4354 DAG.getConstant(Imm, MVT::i32));
4357 if (isVREVMask(ShuffleMask, VT, 64))
4358 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
4359 if (isVREVMask(ShuffleMask, VT, 32))
4360 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
4361 if (isVREVMask(ShuffleMask, VT, 16))
4362 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
4364 // Check for Neon shuffles that modify both input vectors in place.
4365 // If both results are used, i.e., if there are two shuffles with the same
4366 // source operands and with masks corresponding to both results of one of
4367 // these operations, DAG memoization will ensure that a single node is
4368 // used for both shuffles.
4369 unsigned WhichResult;
4370 if (isVTRNMask(ShuffleMask, VT, WhichResult))
4371 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4372 V1, V2).getValue(WhichResult);
4373 if (isVUZPMask(ShuffleMask, VT, WhichResult))
4374 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4375 V1, V2).getValue(WhichResult);
4376 if (isVZIPMask(ShuffleMask, VT, WhichResult))
4377 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4378 V1, V2).getValue(WhichResult);
4380 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
4381 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4382 V1, V1).getValue(WhichResult);
4383 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
4384 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4385 V1, V1).getValue(WhichResult);
4386 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
4387 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4388 V1, V1).getValue(WhichResult);
4391 // If the shuffle is not directly supported and it has 4 elements, use
4392 // the PerfectShuffle-generated table to synthesize it from other shuffles.
4393 unsigned NumElts = VT.getVectorNumElements();
4395 unsigned PFIndexes[4];
4396 for (unsigned i = 0; i != 4; ++i) {
4397 if (ShuffleMask[i] < 0)
4400 PFIndexes[i] = ShuffleMask[i];
4403 // Compute the index in the perfect shuffle table.
4404 unsigned PFTableIndex =
4405 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
4406 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4407 unsigned Cost = (PFEntry >> 30);
4410 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
4413 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
4414 if (EltSize >= 32) {
4415 // Do the expansion with floating-point types, since that is what the VFP
4416 // registers are defined to use, and since i64 is not legal.
4417 EVT EltVT = EVT::getFloatingPointVT(EltSize);
4418 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
4419 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1);
4420 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2);
4421 SmallVector<SDValue, 8> Ops;
4422 for (unsigned i = 0; i < NumElts; ++i) {
4423 if (ShuffleMask[i] < 0)
4424 Ops.push_back(DAG.getUNDEF(EltVT));
4426 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
4427 ShuffleMask[i] < (int)NumElts ? V1 : V2,
4428 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
4431 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
4432 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
4435 if (VT == MVT::v8i8) {
4436 SDValue NewOp = LowerVECTOR_SHUFFLEv8i8(Op, ShuffleMask, DAG);
4437 if (NewOp.getNode())
4444 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4445 // EXTRACT_VECTOR_ELT is legal only for immediate indexes.
4446 SDValue Lane = Op.getOperand(1);
4447 if (!isa<ConstantSDNode>(Lane))
4450 SDValue Vec = Op.getOperand(0);
4451 if (Op.getValueType() == MVT::i32 &&
4452 Vec.getValueType().getVectorElementType().getSizeInBits() < 32) {
4453 DebugLoc dl = Op.getDebugLoc();
4454 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
4460 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
4461 // The only time a CONCAT_VECTORS operation can have legal types is when
4462 // two 64-bit vectors are concatenated to a 128-bit vector.
4463 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
4464 "unexpected CONCAT_VECTORS");
4465 DebugLoc dl = Op.getDebugLoc();
4466 SDValue Val = DAG.getUNDEF(MVT::v2f64);
4467 SDValue Op0 = Op.getOperand(0);
4468 SDValue Op1 = Op.getOperand(1);
4469 if (Op0.getOpcode() != ISD::UNDEF)
4470 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
4471 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0),
4472 DAG.getIntPtrConstant(0));
4473 if (Op1.getOpcode() != ISD::UNDEF)
4474 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
4475 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1),
4476 DAG.getIntPtrConstant(1));
4477 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val);
4480 /// isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each
4481 /// element has been zero/sign-extended, depending on the isSigned parameter,
4482 /// from an integer type half its size.
4483 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
4485 // A v2i64 BUILD_VECTOR will have been legalized to a BITCAST from v4i32.
4486 EVT VT = N->getValueType(0);
4487 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) {
4488 SDNode *BVN = N->getOperand(0).getNode();
4489 if (BVN->getValueType(0) != MVT::v4i32 ||
4490 BVN->getOpcode() != ISD::BUILD_VECTOR)
4492 unsigned LoElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
4493 unsigned HiElt = 1 - LoElt;
4494 ConstantSDNode *Lo0 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt));
4495 ConstantSDNode *Hi0 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt));
4496 ConstantSDNode *Lo1 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt+2));
4497 ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2));
4498 if (!Lo0 || !Hi0 || !Lo1 || !Hi1)
4501 if (Hi0->getSExtValue() == Lo0->getSExtValue() >> 32 &&
4502 Hi1->getSExtValue() == Lo1->getSExtValue() >> 32)
4505 if (Hi0->isNullValue() && Hi1->isNullValue())
4511 if (N->getOpcode() != ISD::BUILD_VECTOR)
4514 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
4515 SDNode *Elt = N->getOperand(i).getNode();
4516 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
4517 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4518 unsigned HalfSize = EltSize / 2;
4520 int64_t SExtVal = C->getSExtValue();
4521 if ((SExtVal >> HalfSize) != (SExtVal >> EltSize))
4524 if ((C->getZExtValue() >> HalfSize) != 0)
4535 /// isSignExtended - Check if a node is a vector value that is sign-extended
4536 /// or a constant BUILD_VECTOR with sign-extended elements.
4537 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
4538 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N))
4540 if (isExtendedBUILD_VECTOR(N, DAG, true))
4545 /// isZeroExtended - Check if a node is a vector value that is zero-extended
4546 /// or a constant BUILD_VECTOR with zero-extended elements.
4547 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
4548 if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N))
4550 if (isExtendedBUILD_VECTOR(N, DAG, false))
4555 /// SkipExtension - For a node that is a SIGN_EXTEND, ZERO_EXTEND, extending
4556 /// load, or BUILD_VECTOR with extended elements, return the unextended value.
4557 static SDValue SkipExtension(SDNode *N, SelectionDAG &DAG) {
4558 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
4559 return N->getOperand(0);
4560 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
4561 return DAG.getLoad(LD->getMemoryVT(), N->getDebugLoc(), LD->getChain(),
4562 LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(),
4563 LD->isNonTemporal(), LD->getAlignment());
4564 // Otherwise, the value must be a BUILD_VECTOR. For v2i64, it will
4565 // have been legalized as a BITCAST from v4i32.
4566 if (N->getOpcode() == ISD::BITCAST) {
4567 SDNode *BVN = N->getOperand(0).getNode();
4568 assert(BVN->getOpcode() == ISD::BUILD_VECTOR &&
4569 BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR");
4570 unsigned LowElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
4571 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), MVT::v2i32,
4572 BVN->getOperand(LowElt), BVN->getOperand(LowElt+2));
4574 // Construct a new BUILD_VECTOR with elements truncated to half the size.
4575 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
4576 EVT VT = N->getValueType(0);
4577 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
4578 unsigned NumElts = VT.getVectorNumElements();
4579 MVT TruncVT = MVT::getIntegerVT(EltSize);
4580 SmallVector<SDValue, 8> Ops;
4581 for (unsigned i = 0; i != NumElts; ++i) {
4582 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
4583 const APInt &CInt = C->getAPIntValue();
4584 Ops.push_back(DAG.getConstant(CInt.trunc(EltSize), TruncVT));
4586 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
4587 MVT::getVectorVT(TruncVT, NumElts), Ops.data(), NumElts);
4590 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
4591 unsigned Opcode = N->getOpcode();
4592 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
4593 SDNode *N0 = N->getOperand(0).getNode();
4594 SDNode *N1 = N->getOperand(1).getNode();
4595 return N0->hasOneUse() && N1->hasOneUse() &&
4596 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
4601 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
4602 unsigned Opcode = N->getOpcode();
4603 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
4604 SDNode *N0 = N->getOperand(0).getNode();
4605 SDNode *N1 = N->getOperand(1).getNode();
4606 return N0->hasOneUse() && N1->hasOneUse() &&
4607 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
4612 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
4613 // Multiplications are only custom-lowered for 128-bit vectors so that
4614 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
4615 EVT VT = Op.getValueType();
4616 assert(VT.is128BitVector() && "unexpected type for custom-lowering ISD::MUL");
4617 SDNode *N0 = Op.getOperand(0).getNode();
4618 SDNode *N1 = Op.getOperand(1).getNode();
4619 unsigned NewOpc = 0;
4621 bool isN0SExt = isSignExtended(N0, DAG);
4622 bool isN1SExt = isSignExtended(N1, DAG);
4623 if (isN0SExt && isN1SExt)
4624 NewOpc = ARMISD::VMULLs;
4626 bool isN0ZExt = isZeroExtended(N0, DAG);
4627 bool isN1ZExt = isZeroExtended(N1, DAG);
4628 if (isN0ZExt && isN1ZExt)
4629 NewOpc = ARMISD::VMULLu;
4630 else if (isN1SExt || isN1ZExt) {
4631 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
4632 // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
4633 if (isN1SExt && isAddSubSExt(N0, DAG)) {
4634 NewOpc = ARMISD::VMULLs;
4636 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
4637 NewOpc = ARMISD::VMULLu;
4639 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
4641 NewOpc = ARMISD::VMULLu;
4647 if (VT == MVT::v2i64)
4648 // Fall through to expand this. It is not legal.
4651 // Other vector multiplications are legal.
4656 // Legalize to a VMULL instruction.
4657 DebugLoc DL = Op.getDebugLoc();
4659 SDValue Op1 = SkipExtension(N1, DAG);
4661 Op0 = SkipExtension(N0, DAG);
4662 assert(Op0.getValueType().is64BitVector() &&
4663 Op1.getValueType().is64BitVector() &&
4664 "unexpected types for extended operands to VMULL");
4665 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
4668 // Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during
4669 // isel lowering to take advantage of no-stall back to back vmul + vmla.
4676 SDValue N00 = SkipExtension(N0->getOperand(0).getNode(), DAG);
4677 SDValue N01 = SkipExtension(N0->getOperand(1).getNode(), DAG);
4678 EVT Op1VT = Op1.getValueType();
4679 return DAG.getNode(N0->getOpcode(), DL, VT,
4680 DAG.getNode(NewOpc, DL, VT,
4681 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
4682 DAG.getNode(NewOpc, DL, VT,
4683 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
4687 LowerSDIV_v4i8(SDValue X, SDValue Y, DebugLoc dl, SelectionDAG &DAG) {
4689 // float4 xf = vcvt_f32_s32(vmovl_s16(a.lo));
4690 // float4 yf = vcvt_f32_s32(vmovl_s16(b.lo));
4691 X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X);
4692 Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y);
4693 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X);
4694 Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y);
4695 // Get reciprocal estimate.
4696 // float4 recip = vrecpeq_f32(yf);
4697 Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4698 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), Y);
4699 // Because char has a smaller range than uchar, we can actually get away
4700 // without any newton steps. This requires that we use a weird bias
4701 // of 0xb000, however (again, this has been exhaustively tested).
4702 // float4 result = as_float4(as_int4(xf*recip) + 0xb000);
4703 X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y);
4704 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X);
4705 Y = DAG.getConstant(0xb000, MVT::i32);
4706 Y = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Y, Y, Y, Y);
4707 X = DAG.getNode(ISD::ADD, dl, MVT::v4i32, X, Y);
4708 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X);
4709 // Convert back to short.
4710 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X);
4711 X = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, X);
4716 LowerSDIV_v4i16(SDValue N0, SDValue N1, DebugLoc dl, SelectionDAG &DAG) {
4718 // Convert to float.
4719 // float4 yf = vcvt_f32_s32(vmovl_s16(y));
4720 // float4 xf = vcvt_f32_s32(vmovl_s16(x));
4721 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0);
4722 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1);
4723 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
4724 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
4726 // Use reciprocal estimate and one refinement step.
4727 // float4 recip = vrecpeq_f32(yf);
4728 // recip *= vrecpsq_f32(yf, recip);
4729 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4730 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1);
4731 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4732 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
4734 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
4735 // Because short has a smaller range than ushort, we can actually get away
4736 // with only a single newton step. This requires that we use a weird bias
4737 // of 89, however (again, this has been exhaustively tested).
4738 // float4 result = as_float4(as_int4(xf*recip) + 0x89);
4739 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
4740 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
4741 N1 = DAG.getConstant(0x89, MVT::i32);
4742 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
4743 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
4744 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
4745 // Convert back to integer and return.
4746 // return vmovn_s32(vcvt_s32_f32(result));
4747 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
4748 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
4752 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
4753 EVT VT = Op.getValueType();
4754 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
4755 "unexpected type for custom-lowering ISD::SDIV");
4757 DebugLoc dl = Op.getDebugLoc();
4758 SDValue N0 = Op.getOperand(0);
4759 SDValue N1 = Op.getOperand(1);
4762 if (VT == MVT::v8i8) {
4763 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0);
4764 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1);
4766 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4767 DAG.getIntPtrConstant(4));
4768 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4769 DAG.getIntPtrConstant(4));
4770 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4771 DAG.getIntPtrConstant(0));
4772 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4773 DAG.getIntPtrConstant(0));
4775 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16
4776 N2 = LowerSDIV_v4i8(N2, N3, dl, DAG); // v4i16
4778 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
4779 N0 = LowerCONCAT_VECTORS(N0, DAG);
4781 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0);
4784 return LowerSDIV_v4i16(N0, N1, dl, DAG);
4787 static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG) {
4788 EVT VT = Op.getValueType();
4789 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
4790 "unexpected type for custom-lowering ISD::UDIV");
4792 DebugLoc dl = Op.getDebugLoc();
4793 SDValue N0 = Op.getOperand(0);
4794 SDValue N1 = Op.getOperand(1);
4797 if (VT == MVT::v8i8) {
4798 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0);
4799 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1);
4801 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4802 DAG.getIntPtrConstant(4));
4803 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4804 DAG.getIntPtrConstant(4));
4805 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4806 DAG.getIntPtrConstant(0));
4807 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4808 DAG.getIntPtrConstant(0));
4810 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16
4811 N2 = LowerSDIV_v4i16(N2, N3, dl, DAG); // v4i16
4813 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
4814 N0 = LowerCONCAT_VECTORS(N0, DAG);
4816 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8,
4817 DAG.getConstant(Intrinsic::arm_neon_vqmovnsu, MVT::i32),
4822 // v4i16 sdiv ... Convert to float.
4823 // float4 yf = vcvt_f32_s32(vmovl_u16(y));
4824 // float4 xf = vcvt_f32_s32(vmovl_u16(x));
4825 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0);
4826 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1);
4827 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
4828 SDValue BN1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
4830 // Use reciprocal estimate and two refinement steps.
4831 // float4 recip = vrecpeq_f32(yf);
4832 // recip *= vrecpsq_f32(yf, recip);
4833 // recip *= vrecpsq_f32(yf, recip);
4834 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4835 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), BN1);
4836 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4837 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
4839 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
4840 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4841 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
4843 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
4844 // Simply multiplying by the reciprocal estimate can leave us a few ulps
4845 // too low, so we add 2 ulps (exhaustive testing shows that this is enough,
4846 // and that it will never cause us to return an answer too large).
4847 // float4 result = as_float4(as_int4(xf*recip) + 2);
4848 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
4849 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
4850 N1 = DAG.getConstant(2, MVT::i32);
4851 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
4852 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
4853 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
4854 // Convert back to integer and return.
4855 // return vmovn_u32(vcvt_s32_f32(result));
4856 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
4857 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
4861 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
4862 EVT VT = Op.getNode()->getValueType(0);
4863 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
4866 bool ExtraOp = false;
4867 switch (Op.getOpcode()) {
4868 default: assert(0 && "Invalid code");
4869 case ISD::ADDC: Opc = ARMISD::ADDC; break;
4870 case ISD::ADDE: Opc = ARMISD::ADDE; ExtraOp = true; break;
4871 case ISD::SUBC: Opc = ARMISD::SUBC; break;
4872 case ISD::SUBE: Opc = ARMISD::SUBE; ExtraOp = true; break;
4876 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
4878 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
4879 Op.getOperand(1), Op.getOperand(2));
4882 static SDValue LowerAtomicLoadStore(SDValue Op, SelectionDAG &DAG) {
4883 // Monotonic load/store is legal for all targets
4884 if (cast<AtomicSDNode>(Op)->getOrdering() <= Monotonic)
4887 // Aquire/Release load/store is not legal for targets without a
4888 // dmb or equivalent available.
4894 ReplaceATOMIC_OP_64(SDNode *Node, SmallVectorImpl<SDValue>& Results,
4895 SelectionDAG &DAG, unsigned NewOp) {
4896 EVT T = Node->getValueType(0);
4897 DebugLoc dl = Node->getDebugLoc();
4898 assert (T == MVT::i64 && "Only know how to expand i64 atomics");
4900 SmallVector<SDValue, 6> Ops;
4901 Ops.push_back(Node->getOperand(0)); // Chain
4902 Ops.push_back(Node->getOperand(1)); // Ptr
4904 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
4905 Node->getOperand(2), DAG.getIntPtrConstant(0)));
4906 // High part of Val1
4907 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
4908 Node->getOperand(2), DAG.getIntPtrConstant(1)));
4909 if (NewOp == ARMISD::ATOMCMPXCHG64_DAG) {
4910 // High part of Val1
4911 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
4912 Node->getOperand(3), DAG.getIntPtrConstant(0)));
4913 // High part of Val2
4914 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
4915 Node->getOperand(3), DAG.getIntPtrConstant(1)));
4917 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
4919 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops.data(), Ops.size(), MVT::i64,
4920 cast<MemSDNode>(Node)->getMemOperand());
4921 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1) };
4922 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
4923 Results.push_back(Result.getValue(2));
4926 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
4927 switch (Op.getOpcode()) {
4928 default: llvm_unreachable("Don't know how to custom lower this!");
4929 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
4930 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
4931 case ISD::GlobalAddress:
4932 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
4933 LowerGlobalAddressELF(Op, DAG);
4934 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
4935 case ISD::SELECT: return LowerSELECT(Op, DAG);
4936 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
4937 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
4938 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
4939 case ISD::VASTART: return LowerVASTART(Op, DAG);
4940 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget);
4941 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG, Subtarget);
4942 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget);
4943 case ISD::SINT_TO_FP:
4944 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
4945 case ISD::FP_TO_SINT:
4946 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
4947 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
4948 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
4949 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
4950 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
4951 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
4952 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
4953 case ISD::EH_SJLJ_DISPATCHSETUP: return LowerEH_SJLJ_DISPATCHSETUP(Op, DAG);
4954 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
4956 case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG);
4959 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
4960 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
4961 case ISD::SRL_PARTS:
4962 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
4963 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
4964 case ISD::SETCC: return LowerVSETCC(Op, DAG);
4965 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
4966 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
4967 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
4968 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
4969 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
4970 case ISD::MUL: return LowerMUL(Op, DAG);
4971 case ISD::SDIV: return LowerSDIV(Op, DAG);
4972 case ISD::UDIV: return LowerUDIV(Op, DAG);
4976 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
4977 case ISD::ATOMIC_LOAD:
4978 case ISD::ATOMIC_STORE: return LowerAtomicLoadStore(Op, DAG);
4983 /// ReplaceNodeResults - Replace the results of node with an illegal result
4984 /// type with new values built out of custom code.
4985 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
4986 SmallVectorImpl<SDValue>&Results,
4987 SelectionDAG &DAG) const {
4989 switch (N->getOpcode()) {
4991 llvm_unreachable("Don't know how to custom expand this!");
4994 Res = ExpandBITCAST(N, DAG);
4998 Res = Expand64BitShift(N, DAG, Subtarget);
5000 case ISD::ATOMIC_LOAD_ADD:
5001 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMADD64_DAG);
5003 case ISD::ATOMIC_LOAD_AND:
5004 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMAND64_DAG);
5006 case ISD::ATOMIC_LOAD_NAND:
5007 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMNAND64_DAG);
5009 case ISD::ATOMIC_LOAD_OR:
5010 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMOR64_DAG);
5012 case ISD::ATOMIC_LOAD_SUB:
5013 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMSUB64_DAG);
5015 case ISD::ATOMIC_LOAD_XOR:
5016 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMXOR64_DAG);
5018 case ISD::ATOMIC_SWAP:
5019 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMSWAP64_DAG);
5021 case ISD::ATOMIC_CMP_SWAP:
5022 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMCMPXCHG64_DAG);
5026 Results.push_back(Res);
5029 //===----------------------------------------------------------------------===//
5030 // ARM Scheduler Hooks
5031 //===----------------------------------------------------------------------===//
5034 ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
5035 MachineBasicBlock *BB,
5036 unsigned Size) const {
5037 unsigned dest = MI->getOperand(0).getReg();
5038 unsigned ptr = MI->getOperand(1).getReg();
5039 unsigned oldval = MI->getOperand(2).getReg();
5040 unsigned newval = MI->getOperand(3).getReg();
5041 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5042 DebugLoc dl = MI->getDebugLoc();
5043 bool isThumb2 = Subtarget->isThumb2();
5045 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
5047 MRI.createVirtualRegister(isThumb2 ? ARM::rGPRRegisterClass
5048 : ARM::GPRRegisterClass);
5051 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass);
5052 MRI.constrainRegClass(oldval, ARM::rGPRRegisterClass);
5053 MRI.constrainRegClass(newval, ARM::rGPRRegisterClass);
5056 unsigned ldrOpc, strOpc;
5058 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
5060 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
5061 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
5064 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
5065 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
5068 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
5069 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
5073 MachineFunction *MF = BB->getParent();
5074 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5075 MachineFunction::iterator It = BB;
5076 ++It; // insert the new blocks after the current block
5078 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
5079 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
5080 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5081 MF->insert(It, loop1MBB);
5082 MF->insert(It, loop2MBB);
5083 MF->insert(It, exitMBB);
5085 // Transfer the remainder of BB and its successor edges to exitMBB.
5086 exitMBB->splice(exitMBB->begin(), BB,
5087 llvm::next(MachineBasicBlock::iterator(MI)),
5089 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5093 // fallthrough --> loop1MBB
5094 BB->addSuccessor(loop1MBB);
5097 // ldrex dest, [ptr]
5101 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
5102 if (ldrOpc == ARM::t2LDREX)
5104 AddDefaultPred(MIB);
5105 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
5106 .addReg(dest).addReg(oldval));
5107 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5108 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5109 BB->addSuccessor(loop2MBB);
5110 BB->addSuccessor(exitMBB);
5113 // strex scratch, newval, [ptr]
5117 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval).addReg(ptr);
5118 if (strOpc == ARM::t2STREX)
5120 AddDefaultPred(MIB);
5121 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5122 .addReg(scratch).addImm(0));
5123 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5124 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5125 BB->addSuccessor(loop1MBB);
5126 BB->addSuccessor(exitMBB);
5132 MI->eraseFromParent(); // The instruction is gone now.
5138 ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
5139 unsigned Size, unsigned BinOpcode) const {
5140 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
5141 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5143 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5144 MachineFunction *MF = BB->getParent();
5145 MachineFunction::iterator It = BB;
5148 unsigned dest = MI->getOperand(0).getReg();
5149 unsigned ptr = MI->getOperand(1).getReg();
5150 unsigned incr = MI->getOperand(2).getReg();
5151 DebugLoc dl = MI->getDebugLoc();
5152 bool isThumb2 = Subtarget->isThumb2();
5154 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
5156 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass);
5157 MRI.constrainRegClass(ptr, ARM::rGPRRegisterClass);
5160 unsigned ldrOpc, strOpc;
5162 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
5164 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
5165 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
5168 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
5169 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
5172 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
5173 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
5177 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5178 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5179 MF->insert(It, loopMBB);
5180 MF->insert(It, exitMBB);
5182 // Transfer the remainder of BB and its successor edges to exitMBB.
5183 exitMBB->splice(exitMBB->begin(), BB,
5184 llvm::next(MachineBasicBlock::iterator(MI)),
5186 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5188 TargetRegisterClass *TRC =
5189 isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
5190 unsigned scratch = MRI.createVirtualRegister(TRC);
5191 unsigned scratch2 = (!BinOpcode) ? incr : MRI.createVirtualRegister(TRC);
5195 // fallthrough --> loopMBB
5196 BB->addSuccessor(loopMBB);
5200 // <binop> scratch2, dest, incr
5201 // strex scratch, scratch2, ptr
5204 // fallthrough --> exitMBB
5206 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
5207 if (ldrOpc == ARM::t2LDREX)
5209 AddDefaultPred(MIB);
5211 // operand order needs to go the other way for NAND
5212 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr)
5213 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
5214 addReg(incr).addReg(dest)).addReg(0);
5216 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
5217 addReg(dest).addReg(incr)).addReg(0);
5220 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2).addReg(ptr);
5221 if (strOpc == ARM::t2STREX)
5223 AddDefaultPred(MIB);
5224 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5225 .addReg(scratch).addImm(0));
5226 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5227 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5229 BB->addSuccessor(loopMBB);
5230 BB->addSuccessor(exitMBB);
5236 MI->eraseFromParent(); // The instruction is gone now.
5242 ARMTargetLowering::EmitAtomicBinaryMinMax(MachineInstr *MI,
5243 MachineBasicBlock *BB,
5246 ARMCC::CondCodes Cond) const {
5247 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5249 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5250 MachineFunction *MF = BB->getParent();
5251 MachineFunction::iterator It = BB;
5254 unsigned dest = MI->getOperand(0).getReg();
5255 unsigned ptr = MI->getOperand(1).getReg();
5256 unsigned incr = MI->getOperand(2).getReg();
5257 unsigned oldval = dest;
5258 DebugLoc dl = MI->getDebugLoc();
5259 bool isThumb2 = Subtarget->isThumb2();
5261 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
5263 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass);
5264 MRI.constrainRegClass(ptr, ARM::rGPRRegisterClass);
5267 unsigned ldrOpc, strOpc, extendOpc;
5269 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
5271 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
5272 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
5273 extendOpc = isThumb2 ? ARM::t2SXTB : ARM::SXTB;
5276 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
5277 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
5278 extendOpc = isThumb2 ? ARM::t2SXTH : ARM::SXTH;
5281 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
5282 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
5287 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5288 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5289 MF->insert(It, loopMBB);
5290 MF->insert(It, exitMBB);
5292 // Transfer the remainder of BB and its successor edges to exitMBB.
5293 exitMBB->splice(exitMBB->begin(), BB,
5294 llvm::next(MachineBasicBlock::iterator(MI)),
5296 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5298 TargetRegisterClass *TRC =
5299 isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
5300 unsigned scratch = MRI.createVirtualRegister(TRC);
5301 unsigned scratch2 = MRI.createVirtualRegister(TRC);
5305 // fallthrough --> loopMBB
5306 BB->addSuccessor(loopMBB);
5310 // (sign extend dest, if required)
5312 // cmov.cond scratch2, dest, incr
5313 // strex scratch, scratch2, ptr
5316 // fallthrough --> exitMBB
5318 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
5319 if (ldrOpc == ARM::t2LDREX)
5321 AddDefaultPred(MIB);
5323 // Sign extend the value, if necessary.
5324 if (signExtend && extendOpc) {
5325 oldval = MRI.createVirtualRegister(ARM::GPRRegisterClass);
5326 AddDefaultPred(BuildMI(BB, dl, TII->get(extendOpc), oldval)
5331 // Build compare and cmov instructions.
5332 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
5333 .addReg(oldval).addReg(incr));
5334 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr), scratch2)
5335 .addReg(oldval).addReg(incr).addImm(Cond).addReg(ARM::CPSR);
5337 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2).addReg(ptr);
5338 if (strOpc == ARM::t2STREX)
5340 AddDefaultPred(MIB);
5341 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5342 .addReg(scratch).addImm(0));
5343 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5344 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5346 BB->addSuccessor(loopMBB);
5347 BB->addSuccessor(exitMBB);
5353 MI->eraseFromParent(); // The instruction is gone now.
5359 ARMTargetLowering::EmitAtomicBinary64(MachineInstr *MI, MachineBasicBlock *BB,
5360 unsigned Op1, unsigned Op2,
5361 bool NeedsCarry, bool IsCmpxchg) const {
5362 // This also handles ATOMIC_SWAP, indicated by Op1==0.
5363 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5365 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5366 MachineFunction *MF = BB->getParent();
5367 MachineFunction::iterator It = BB;
5370 unsigned destlo = MI->getOperand(0).getReg();
5371 unsigned desthi = MI->getOperand(1).getReg();
5372 unsigned ptr = MI->getOperand(2).getReg();
5373 unsigned vallo = MI->getOperand(3).getReg();
5374 unsigned valhi = MI->getOperand(4).getReg();
5375 DebugLoc dl = MI->getDebugLoc();
5376 bool isThumb2 = Subtarget->isThumb2();
5378 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
5380 MRI.constrainRegClass(destlo, ARM::rGPRRegisterClass);
5381 MRI.constrainRegClass(desthi, ARM::rGPRRegisterClass);
5382 MRI.constrainRegClass(ptr, ARM::rGPRRegisterClass);
5385 unsigned ldrOpc = isThumb2 ? ARM::t2LDREXD : ARM::LDREXD;
5386 unsigned strOpc = isThumb2 ? ARM::t2STREXD : ARM::STREXD;
5388 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5389 MachineBasicBlock *contBB = 0, *cont2BB = 0;
5391 contBB = MF->CreateMachineBasicBlock(LLVM_BB);
5392 cont2BB = MF->CreateMachineBasicBlock(LLVM_BB);
5394 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5395 MF->insert(It, loopMBB);
5397 MF->insert(It, contBB);
5398 MF->insert(It, cont2BB);
5400 MF->insert(It, exitMBB);
5402 // Transfer the remainder of BB and its successor edges to exitMBB.
5403 exitMBB->splice(exitMBB->begin(), BB,
5404 llvm::next(MachineBasicBlock::iterator(MI)),
5406 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5408 TargetRegisterClass *TRC =
5409 isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
5410 unsigned storesuccess = MRI.createVirtualRegister(TRC);
5414 // fallthrough --> loopMBB
5415 BB->addSuccessor(loopMBB);
5418 // ldrexd r2, r3, ptr
5419 // <binopa> r0, r2, incr
5420 // <binopb> r1, r3, incr
5421 // strexd storesuccess, r0, r1, ptr
5422 // cmp storesuccess, #0
5424 // fallthrough --> exitMBB
5426 // Note that the registers are explicitly specified because there is not any
5427 // way to force the register allocator to allocate a register pair.
5429 // FIXME: The hardcoded registers are not necessary for Thumb2, but we
5430 // need to properly enforce the restriction that the two output registers
5431 // for ldrexd must be different.
5434 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc))
5435 .addReg(ARM::R2, RegState::Define)
5436 .addReg(ARM::R3, RegState::Define).addReg(ptr));
5437 // Copy r2/r3 into dest. (This copy will normally be coalesced.)
5438 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), destlo).addReg(ARM::R2);
5439 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), desthi).addReg(ARM::R3);
5443 for (unsigned i = 0; i < 2; i++) {
5444 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr :
5446 .addReg(i == 0 ? destlo : desthi)
5447 .addReg(i == 0 ? vallo : valhi));
5448 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5449 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5450 BB->addSuccessor(exitMBB);
5451 BB->addSuccessor(i == 0 ? contBB : cont2BB);
5452 BB = (i == 0 ? contBB : cont2BB);
5455 // Copy to physregs for strexd
5456 unsigned setlo = MI->getOperand(5).getReg();
5457 unsigned sethi = MI->getOperand(6).getReg();
5458 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R0).addReg(setlo);
5459 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R1).addReg(sethi);
5461 // Perform binary operation
5462 AddDefaultPred(BuildMI(BB, dl, TII->get(Op1), ARM::R0)
5463 .addReg(destlo).addReg(vallo))
5464 .addReg(NeedsCarry ? ARM::CPSR : 0, getDefRegState(NeedsCarry));
5465 AddDefaultPred(BuildMI(BB, dl, TII->get(Op2), ARM::R1)
5466 .addReg(desthi).addReg(valhi)).addReg(0);
5468 // Copy to physregs for strexd
5469 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R0).addReg(vallo);
5470 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R1).addReg(valhi);
5474 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), storesuccess)
5475 .addReg(ARM::R0).addReg(ARM::R1).addReg(ptr));
5477 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5478 .addReg(storesuccess).addImm(0));
5479 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5480 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5482 BB->addSuccessor(loopMBB);
5483 BB->addSuccessor(exitMBB);
5489 MI->eraseFromParent(); // The instruction is gone now.
5494 /// EmitBasePointerRecalculation - For functions using a base pointer, we
5495 /// rematerialize it (via the frame pointer).
5496 void ARMTargetLowering::
5497 EmitBasePointerRecalculation(MachineInstr *MI, MachineBasicBlock *MBB,
5498 MachineBasicBlock *DispatchBB) const {
5499 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5500 const ARMBaseInstrInfo *AII = static_cast<const ARMBaseInstrInfo*>(TII);
5501 MachineFunction &MF = *MI->getParent()->getParent();
5502 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
5503 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
5505 if (!RI.hasBasePointer(MF)) return;
5507 MachineBasicBlock::iterator MBBI = MI;
5509 int32_t NumBytes = AFI->getFramePtrSpillOffset();
5510 unsigned FramePtr = RI.getFrameRegister(MF);
5511 assert(MF.getTarget().getFrameLowering()->hasFP(MF) &&
5512 "Base pointer without frame pointer?");
5514 if (AFI->isThumb2Function())
5515 llvm::emitT2RegPlusImmediate(*MBB, MBBI, MI->getDebugLoc(), ARM::R6,
5516 FramePtr, -NumBytes, ARMCC::AL, 0, *AII);
5517 else if (AFI->isThumbFunction())
5518 llvm::emitThumbRegPlusImmediate(*MBB, MBBI, MI->getDebugLoc(), ARM::R6,
5519 FramePtr, -NumBytes, *AII, RI);
5521 llvm::emitARMRegPlusImmediate(*MBB, MBBI, MI->getDebugLoc(), ARM::R6,
5522 FramePtr, -NumBytes, ARMCC::AL, 0, *AII);
5524 if (!RI.needsStackRealignment(MF)) return;
5526 // If there's dynamic realignment, adjust for it.
5527 MachineFrameInfo *MFI = MF.getFrameInfo();
5528 unsigned MaxAlign = MFI->getMaxAlignment();
5529 assert(!AFI->isThumb1OnlyFunction());
5531 // Emit bic r6, r6, MaxAlign
5532 unsigned bicOpc = AFI->isThumbFunction() ? ARM::t2BICri : ARM::BICri;
5535 BuildMI(*MBB, MBBI, MI->getDebugLoc(), TII->get(bicOpc), ARM::R6)
5536 .addReg(ARM::R6, RegState::Kill)
5537 .addImm(MaxAlign - 1)));
5540 /// SetupEntryBlockForSjLj - Insert code into the entry block that creates and
5541 /// registers the function context.
5542 void ARMTargetLowering::
5543 SetupEntryBlockForSjLj(MachineInstr *MI, MachineBasicBlock *MBB,
5544 MachineBasicBlock *DispatchBB, int FI) const {
5545 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5546 DebugLoc dl = MI->getDebugLoc();
5547 MachineFunction *MF = MBB->getParent();
5548 MachineRegisterInfo *MRI = &MF->getRegInfo();
5549 MachineConstantPool *MCP = MF->getConstantPool();
5550 ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>();
5551 const Function *F = MF->getFunction();
5553 bool isThumb = Subtarget->isThumb();
5554 bool isThumb2 = Subtarget->isThumb2();
5556 unsigned PCLabelId = AFI->createPICLabelUId();
5557 unsigned PCAdj = (isThumb || isThumb2) ? 4 : 8;
5558 ARMConstantPoolValue *CPV =
5559 ARMConstantPoolMBB::Create(F->getContext(), DispatchBB, PCLabelId, PCAdj);
5560 unsigned CPI = MCP->getConstantPoolIndex(CPV, 4);
5562 const TargetRegisterClass *TRC =
5563 isThumb ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
5565 // Grab constant pool and fixed stack memory operands.
5566 MachineMemOperand *CPMMO =
5567 MF->getMachineMemOperand(MachinePointerInfo::getConstantPool(),
5568 MachineMemOperand::MOLoad, 4, 4);
5570 MachineMemOperand *FIMMOSt =
5571 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
5572 MachineMemOperand::MOStore, 4, 4);
5574 EmitBasePointerRecalculation(MI, MBB, DispatchBB);
5576 // Load the address of the dispatch MBB into the jump buffer.
5578 // Incoming value: jbuf
5579 // ldr.n r5, LCPI1_1
5582 // str r5, [$jbuf, #+4] ; &jbuf[1]
5583 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
5584 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2LDRpci), NewVReg1)
5585 .addConstantPoolIndex(CPI)
5586 .addMemOperand(CPMMO));
5587 // Set the low bit because of thumb mode.
5588 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
5590 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2ORRri), NewVReg2)
5591 .addReg(NewVReg1, RegState::Kill)
5593 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
5594 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg3)
5595 .addReg(NewVReg2, RegState::Kill)
5597 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2STRi12))
5598 .addReg(NewVReg3, RegState::Kill)
5600 .addImm(36) // &jbuf[1] :: pc
5601 .addMemOperand(FIMMOSt));
5602 } else if (isThumb) {
5603 // Incoming value: jbuf
5604 // ldr.n r1, LCPI1_4
5608 // add r2, $jbuf, #+4 ; &jbuf[1]
5610 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
5611 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tLDRpci), NewVReg1)
5612 .addConstantPoolIndex(CPI)
5613 .addMemOperand(CPMMO));
5614 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
5615 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg2)
5616 .addReg(NewVReg1, RegState::Kill)
5618 // Set the low bit because of thumb mode.
5619 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
5620 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tMOVi8), NewVReg3)
5621 .addReg(ARM::CPSR, RegState::Define)
5623 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
5624 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tORR), NewVReg4)
5625 .addReg(ARM::CPSR, RegState::Define)
5626 .addReg(NewVReg2, RegState::Kill)
5627 .addReg(NewVReg3, RegState::Kill));
5628 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
5629 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tADDrSPi), NewVReg5)
5631 .addImm(36)); // &jbuf[1] :: pc
5632 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tSTRi))
5633 .addReg(NewVReg4, RegState::Kill)
5634 .addReg(NewVReg5, RegState::Kill)
5636 .addMemOperand(FIMMOSt));
5638 // Incoming value: jbuf
5641 // str r1, [$jbuf, #+4] ; &jbuf[1]
5642 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
5643 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::LDRi12), NewVReg1)
5644 .addConstantPoolIndex(CPI)
5646 .addMemOperand(CPMMO));
5647 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
5648 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::PICADD), NewVReg2)
5649 .addReg(NewVReg1, RegState::Kill)
5650 .addImm(PCLabelId));
5651 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::STRi12))
5652 .addReg(NewVReg2, RegState::Kill)
5654 .addImm(36) // &jbuf[1] :: pc
5655 .addMemOperand(FIMMOSt));
5659 MachineBasicBlock *ARMTargetLowering::
5660 EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const {
5661 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5662 DebugLoc dl = MI->getDebugLoc();
5663 MachineFunction *MF = MBB->getParent();
5664 MachineRegisterInfo *MRI = &MF->getRegInfo();
5665 ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>();
5666 MachineFrameInfo *MFI = MF->getFrameInfo();
5667 int FI = MFI->getFunctionContextIndex();
5669 const TargetRegisterClass *TRC =
5670 Subtarget->isThumb() ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
5672 // Get a mapping of the call site numbers to all of the landing pads they're
5674 DenseMap<unsigned, SmallVector<MachineBasicBlock*, 2> > CallSiteNumToLPad;
5675 unsigned MaxCSNum = 0;
5676 MachineModuleInfo &MMI = MF->getMMI();
5677 for (MachineFunction::iterator BB = MF->begin(), E = MF->end(); BB != E; ++BB) {
5678 if (!BB->isLandingPad()) continue;
5680 // FIXME: We should assert that the EH_LABEL is the first MI in the landing
5682 for (MachineBasicBlock::iterator
5683 II = BB->begin(), IE = BB->end(); II != IE; ++II) {
5684 if (!II->isEHLabel()) continue;
5686 MCSymbol *Sym = II->getOperand(0).getMCSymbol();
5687 if (!MMI.hasCallSiteLandingPad(Sym)) continue;
5689 SmallVectorImpl<unsigned> &CallSiteIdxs = MMI.getCallSiteLandingPad(Sym);
5690 for (SmallVectorImpl<unsigned>::iterator
5691 CSI = CallSiteIdxs.begin(), CSE = CallSiteIdxs.end();
5692 CSI != CSE; ++CSI) {
5693 CallSiteNumToLPad[*CSI].push_back(BB);
5694 MaxCSNum = std::max(MaxCSNum, *CSI);
5700 // Get an ordered list of the machine basic blocks for the jump table.
5701 std::vector<MachineBasicBlock*> LPadList;
5702 SmallPtrSet<MachineBasicBlock*, 64> InvokeBBs;
5703 LPadList.reserve(CallSiteNumToLPad.size());
5704 for (unsigned I = 1; I <= MaxCSNum; ++I) {
5705 SmallVectorImpl<MachineBasicBlock*> &MBBList = CallSiteNumToLPad[I];
5706 for (SmallVectorImpl<MachineBasicBlock*>::iterator
5707 II = MBBList.begin(), IE = MBBList.end(); II != IE; ++II) {
5708 LPadList.push_back(*II);
5709 InvokeBBs.insert((*II)->pred_begin(), (*II)->pred_end());
5713 assert(!LPadList.empty() &&
5714 "No landing pad destinations for the dispatch jump table!");
5716 // Create the jump table and associated information.
5717 MachineJumpTableInfo *JTI =
5718 MF->getOrCreateJumpTableInfo(MachineJumpTableInfo::EK_Inline);
5719 unsigned MJTI = JTI->createJumpTableIndex(LPadList);
5720 unsigned UId = AFI->createJumpTableUId();
5722 // Create the MBBs for the dispatch code.
5724 // Shove the dispatch's address into the return slot in the function context.
5725 MachineBasicBlock *DispatchBB = MF->CreateMachineBasicBlock();
5726 DispatchBB->setIsLandingPad();
5728 MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock();
5729 BuildMI(TrapBB, dl, TII->get(Subtarget->isThumb() ? ARM::tTRAP : ARM::TRAP));
5730 DispatchBB->addSuccessor(TrapBB);
5732 MachineBasicBlock *DispContBB = MF->CreateMachineBasicBlock();
5733 DispatchBB->addSuccessor(DispContBB);
5735 // Insert and renumber MBBs.
5736 MachineBasicBlock *Last = &MF->back();
5737 MF->insert(MF->end(), DispatchBB);
5738 MF->insert(MF->end(), DispContBB);
5739 MF->insert(MF->end(), TrapBB);
5740 MF->RenumberBlocks(Last);
5742 // Insert code into the entry block that creates and registers the function
5744 SetupEntryBlockForSjLj(MI, MBB, DispatchBB, FI);
5746 MachineMemOperand *FIMMOLd =
5747 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
5748 MachineMemOperand::MOLoad |
5749 MachineMemOperand::MOVolatile, 4, 4);
5751 if (Subtarget->isThumb2()) {
5752 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
5753 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2LDRi12), NewVReg1)
5756 .addMemOperand(FIMMOLd));
5757 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPri))
5759 .addImm(LPadList.size()));
5760 BuildMI(DispatchBB, dl, TII->get(ARM::t2Bcc))
5765 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
5766 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::t2LEApcrelJT),NewVReg2)
5767 .addJumpTableIndex(MJTI)
5770 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
5773 BuildMI(DispContBB, dl, TII->get(ARM::t2ADDrs), NewVReg3)
5774 .addReg(NewVReg2, RegState::Kill)
5776 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))));
5778 BuildMI(DispContBB, dl, TII->get(ARM::t2BR_JT))
5779 .addReg(NewVReg3, RegState::Kill)
5781 .addJumpTableIndex(MJTI)
5783 } else if (Subtarget->isThumb()) {
5784 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
5785 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRspi), NewVReg1)
5788 .addMemOperand(FIMMOLd));
5790 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPi8))
5792 .addImm(LPadList.size()));
5793 BuildMI(DispatchBB, dl, TII->get(ARM::tBcc))
5798 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
5799 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLSLri), NewVReg2)
5800 .addReg(ARM::CPSR, RegState::Define)
5804 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
5805 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLEApcrelJT), NewVReg3)
5806 .addJumpTableIndex(MJTI)
5809 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
5810 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg4)
5811 .addReg(ARM::CPSR, RegState::Define)
5812 .addReg(NewVReg2, RegState::Kill)
5815 MachineMemOperand *JTMMOLd =
5816 MF->getMachineMemOperand(MachinePointerInfo::getJumpTable(),
5817 MachineMemOperand::MOLoad, 4, 4);
5819 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
5820 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLDRi), NewVReg5)
5821 .addReg(NewVReg4, RegState::Kill)
5823 .addMemOperand(JTMMOLd));
5825 unsigned NewVReg6 = MRI->createVirtualRegister(TRC);
5826 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg6)
5827 .addReg(ARM::CPSR, RegState::Define)
5828 .addReg(NewVReg5, RegState::Kill)
5831 BuildMI(DispContBB, dl, TII->get(ARM::tBR_JTr))
5832 .addReg(NewVReg6, RegState::Kill)
5833 .addJumpTableIndex(MJTI)
5836 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
5837 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRi12), NewVReg1)
5840 .addMemOperand(FIMMOLd));
5841 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPri))
5843 .addImm(LPadList.size()));
5844 BuildMI(DispatchBB, dl, TII->get(ARM::Bcc))
5849 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
5851 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::MOVsi), NewVReg2)
5853 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))));
5854 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
5855 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::LEApcrelJT), NewVReg3)
5856 .addJumpTableIndex(MJTI)
5859 MachineMemOperand *JTMMOLd =
5860 MF->getMachineMemOperand(MachinePointerInfo::getJumpTable(),
5861 MachineMemOperand::MOLoad, 4, 4);
5862 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
5864 BuildMI(DispContBB, dl, TII->get(ARM::LDRrs), NewVReg4)
5865 .addReg(NewVReg2, RegState::Kill)
5868 .addMemOperand(JTMMOLd));
5870 BuildMI(DispContBB, dl, TII->get(ARM::BR_JTadd))
5871 .addReg(NewVReg4, RegState::Kill)
5873 .addJumpTableIndex(MJTI)
5877 // Add the jump table entries as successors to the MBB.
5878 MachineBasicBlock *PrevMBB = 0;
5879 for (std::vector<MachineBasicBlock*>::iterator
5880 I = LPadList.begin(), E = LPadList.end(); I != E; ++I) {
5881 MachineBasicBlock *CurMBB = *I;
5882 if (PrevMBB != CurMBB)
5883 DispContBB->addSuccessor(CurMBB);
5887 // Remove the landing pad successor from the invoke block and replace it with
5888 // the new dispatch block.
5889 for (SmallPtrSet<MachineBasicBlock*, 64>::iterator
5890 I = InvokeBBs.begin(), E = InvokeBBs.end(); I != E; ++I) {
5891 MachineBasicBlock *BB = *I;
5892 for (MachineBasicBlock::succ_iterator
5893 SI = BB->succ_begin(), SE = BB->succ_end(); SI != SE; ++SI) {
5894 MachineBasicBlock *SMBB = *SI;
5895 if (SMBB->isLandingPad()) {
5896 BB->removeSuccessor(SMBB);
5897 SMBB->setIsLandingPad(false);
5901 BB->addSuccessor(DispatchBB);
5904 // The instruction is gone now.
5905 MI->eraseFromParent();
5911 MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
5912 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
5913 E = MBB->succ_end(); I != E; ++I)
5916 llvm_unreachable("Expecting a BB with two successors!");
5920 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
5921 MachineBasicBlock *BB) const {
5922 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5923 DebugLoc dl = MI->getDebugLoc();
5924 bool isThumb2 = Subtarget->isThumb2();
5925 switch (MI->getOpcode()) {
5928 llvm_unreachable("Unexpected instr type to insert");
5930 // The Thumb2 pre-indexed stores have the same MI operands, they just
5931 // define them differently in the .td files from the isel patterns, so
5932 // they need pseudos.
5933 case ARM::t2STR_preidx:
5934 MI->setDesc(TII->get(ARM::t2STR_PRE));
5936 case ARM::t2STRB_preidx:
5937 MI->setDesc(TII->get(ARM::t2STRB_PRE));
5939 case ARM::t2STRH_preidx:
5940 MI->setDesc(TII->get(ARM::t2STRH_PRE));
5943 case ARM::STRi_preidx:
5944 case ARM::STRBi_preidx: {
5945 unsigned NewOpc = MI->getOpcode() == ARM::STRi_preidx ?
5946 ARM::STR_PRE_IMM : ARM::STRB_PRE_IMM;
5947 // Decode the offset.
5948 unsigned Offset = MI->getOperand(4).getImm();
5949 bool isSub = ARM_AM::getAM2Op(Offset) == ARM_AM::sub;
5950 Offset = ARM_AM::getAM2Offset(Offset);
5954 MachineMemOperand *MMO = *MI->memoperands_begin();
5955 BuildMI(*BB, MI, dl, TII->get(NewOpc))
5956 .addOperand(MI->getOperand(0)) // Rn_wb
5957 .addOperand(MI->getOperand(1)) // Rt
5958 .addOperand(MI->getOperand(2)) // Rn
5959 .addImm(Offset) // offset (skip GPR==zero_reg)
5960 .addOperand(MI->getOperand(5)) // pred
5961 .addOperand(MI->getOperand(6))
5962 .addMemOperand(MMO);
5963 MI->eraseFromParent();
5966 case ARM::STRr_preidx:
5967 case ARM::STRBr_preidx:
5968 case ARM::STRH_preidx: {
5970 switch (MI->getOpcode()) {
5971 default: llvm_unreachable("unexpected opcode!");
5972 case ARM::STRr_preidx: NewOpc = ARM::STR_PRE_REG; break;
5973 case ARM::STRBr_preidx: NewOpc = ARM::STRB_PRE_REG; break;
5974 case ARM::STRH_preidx: NewOpc = ARM::STRH_PRE; break;
5976 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc));
5977 for (unsigned i = 0; i < MI->getNumOperands(); ++i)
5978 MIB.addOperand(MI->getOperand(i));
5979 MI->eraseFromParent();
5982 case ARM::ATOMIC_LOAD_ADD_I8:
5983 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
5984 case ARM::ATOMIC_LOAD_ADD_I16:
5985 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
5986 case ARM::ATOMIC_LOAD_ADD_I32:
5987 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
5989 case ARM::ATOMIC_LOAD_AND_I8:
5990 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
5991 case ARM::ATOMIC_LOAD_AND_I16:
5992 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
5993 case ARM::ATOMIC_LOAD_AND_I32:
5994 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
5996 case ARM::ATOMIC_LOAD_OR_I8:
5997 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
5998 case ARM::ATOMIC_LOAD_OR_I16:
5999 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
6000 case ARM::ATOMIC_LOAD_OR_I32:
6001 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
6003 case ARM::ATOMIC_LOAD_XOR_I8:
6004 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
6005 case ARM::ATOMIC_LOAD_XOR_I16:
6006 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
6007 case ARM::ATOMIC_LOAD_XOR_I32:
6008 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
6010 case ARM::ATOMIC_LOAD_NAND_I8:
6011 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
6012 case ARM::ATOMIC_LOAD_NAND_I16:
6013 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
6014 case ARM::ATOMIC_LOAD_NAND_I32:
6015 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
6017 case ARM::ATOMIC_LOAD_SUB_I8:
6018 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
6019 case ARM::ATOMIC_LOAD_SUB_I16:
6020 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
6021 case ARM::ATOMIC_LOAD_SUB_I32:
6022 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
6024 case ARM::ATOMIC_LOAD_MIN_I8:
6025 return EmitAtomicBinaryMinMax(MI, BB, 1, true, ARMCC::LT);
6026 case ARM::ATOMIC_LOAD_MIN_I16:
6027 return EmitAtomicBinaryMinMax(MI, BB, 2, true, ARMCC::LT);
6028 case ARM::ATOMIC_LOAD_MIN_I32:
6029 return EmitAtomicBinaryMinMax(MI, BB, 4, true, ARMCC::LT);
6031 case ARM::ATOMIC_LOAD_MAX_I8:
6032 return EmitAtomicBinaryMinMax(MI, BB, 1, true, ARMCC::GT);
6033 case ARM::ATOMIC_LOAD_MAX_I16:
6034 return EmitAtomicBinaryMinMax(MI, BB, 2, true, ARMCC::GT);
6035 case ARM::ATOMIC_LOAD_MAX_I32:
6036 return EmitAtomicBinaryMinMax(MI, BB, 4, true, ARMCC::GT);
6038 case ARM::ATOMIC_LOAD_UMIN_I8:
6039 return EmitAtomicBinaryMinMax(MI, BB, 1, false, ARMCC::LO);
6040 case ARM::ATOMIC_LOAD_UMIN_I16:
6041 return EmitAtomicBinaryMinMax(MI, BB, 2, false, ARMCC::LO);
6042 case ARM::ATOMIC_LOAD_UMIN_I32:
6043 return EmitAtomicBinaryMinMax(MI, BB, 4, false, ARMCC::LO);
6045 case ARM::ATOMIC_LOAD_UMAX_I8:
6046 return EmitAtomicBinaryMinMax(MI, BB, 1, false, ARMCC::HI);
6047 case ARM::ATOMIC_LOAD_UMAX_I16:
6048 return EmitAtomicBinaryMinMax(MI, BB, 2, false, ARMCC::HI);
6049 case ARM::ATOMIC_LOAD_UMAX_I32:
6050 return EmitAtomicBinaryMinMax(MI, BB, 4, false, ARMCC::HI);
6052 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0);
6053 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0);
6054 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0);
6056 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1);
6057 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
6058 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
6061 case ARM::ATOMADD6432:
6062 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr,
6063 isThumb2 ? ARM::t2ADCrr : ARM::ADCrr,
6064 /*NeedsCarry*/ true);
6065 case ARM::ATOMSUB6432:
6066 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr,
6067 isThumb2 ? ARM::t2SBCrr : ARM::SBCrr,
6068 /*NeedsCarry*/ true);
6069 case ARM::ATOMOR6432:
6070 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr,
6071 isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
6072 case ARM::ATOMXOR6432:
6073 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2EORrr : ARM::EORrr,
6074 isThumb2 ? ARM::t2EORrr : ARM::EORrr);
6075 case ARM::ATOMAND6432:
6076 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr,
6077 isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
6078 case ARM::ATOMSWAP6432:
6079 return EmitAtomicBinary64(MI, BB, 0, 0, false);
6080 case ARM::ATOMCMPXCHG6432:
6081 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr,
6082 isThumb2 ? ARM::t2SBCrr : ARM::SBCrr,
6083 /*NeedsCarry*/ false, /*IsCmpxchg*/true);
6085 case ARM::tMOVCCr_pseudo: {
6086 // To "insert" a SELECT_CC instruction, we actually have to insert the
6087 // diamond control-flow pattern. The incoming instruction knows the
6088 // destination vreg to set, the condition code register to branch on, the
6089 // true/false values to select between, and a branch opcode to use.
6090 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6091 MachineFunction::iterator It = BB;
6097 // cmpTY ccX, r1, r2
6099 // fallthrough --> copy0MBB
6100 MachineBasicBlock *thisMBB = BB;
6101 MachineFunction *F = BB->getParent();
6102 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
6103 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
6104 F->insert(It, copy0MBB);
6105 F->insert(It, sinkMBB);
6107 // Transfer the remainder of BB and its successor edges to sinkMBB.
6108 sinkMBB->splice(sinkMBB->begin(), BB,
6109 llvm::next(MachineBasicBlock::iterator(MI)),
6111 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
6113 BB->addSuccessor(copy0MBB);
6114 BB->addSuccessor(sinkMBB);
6116 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
6117 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
6120 // %FalseValue = ...
6121 // # fallthrough to sinkMBB
6124 // Update machine-CFG edges
6125 BB->addSuccessor(sinkMBB);
6128 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
6131 BuildMI(*BB, BB->begin(), dl,
6132 TII->get(ARM::PHI), MI->getOperand(0).getReg())
6133 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
6134 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
6136 MI->eraseFromParent(); // The pseudo instruction is gone now.
6141 case ARM::BCCZi64: {
6142 // If there is an unconditional branch to the other successor, remove it.
6143 BB->erase(llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
6145 // Compare both parts that make up the double comparison separately for
6147 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
6149 unsigned LHS1 = MI->getOperand(1).getReg();
6150 unsigned LHS2 = MI->getOperand(2).getReg();
6152 AddDefaultPred(BuildMI(BB, dl,
6153 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
6154 .addReg(LHS1).addImm(0));
6155 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
6156 .addReg(LHS2).addImm(0)
6157 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
6159 unsigned RHS1 = MI->getOperand(3).getReg();
6160 unsigned RHS2 = MI->getOperand(4).getReg();
6161 AddDefaultPred(BuildMI(BB, dl,
6162 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
6163 .addReg(LHS1).addReg(RHS1));
6164 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
6165 .addReg(LHS2).addReg(RHS2)
6166 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
6169 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB();
6170 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
6171 if (MI->getOperand(0).getImm() == ARMCC::NE)
6172 std::swap(destMBB, exitMBB);
6174 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
6175 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
6177 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2B)).addMBB(exitMBB));
6179 BuildMI(BB, dl, TII->get(ARM::B)) .addMBB(exitMBB);
6181 MI->eraseFromParent(); // The pseudo instruction is gone now.
6187 // To insert an ABS instruction, we have to insert the
6188 // diamond control-flow pattern. The incoming instruction knows the
6189 // source vreg to test against 0, the destination vreg to set,
6190 // the condition code register to branch on, the
6191 // true/false values to select between, and a branch opcode to use.
6196 // BCC (branch to SinkBB if V0 >= 0)
6197 // RSBBB: V3 = RSBri V2, 0 (compute ABS if V2 < 0)
6198 // SinkBB: V1 = PHI(V2, V3)
6199 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6200 MachineFunction::iterator BBI = BB;
6202 MachineFunction *Fn = BB->getParent();
6203 MachineBasicBlock *RSBBB = Fn->CreateMachineBasicBlock(LLVM_BB);
6204 MachineBasicBlock *SinkBB = Fn->CreateMachineBasicBlock(LLVM_BB);
6205 Fn->insert(BBI, RSBBB);
6206 Fn->insert(BBI, SinkBB);
6208 unsigned int ABSSrcReg = MI->getOperand(1).getReg();
6209 unsigned int ABSDstReg = MI->getOperand(0).getReg();
6210 bool isThumb2 = Subtarget->isThumb2();
6211 MachineRegisterInfo &MRI = Fn->getRegInfo();
6212 // In Thumb mode S must not be specified if source register is the SP or
6213 // PC and if destination register is the SP, so restrict register class
6214 unsigned NewMovDstReg = MRI.createVirtualRegister(
6215 isThumb2 ? ARM::rGPRRegisterClass : ARM::GPRRegisterClass);
6216 unsigned NewRsbDstReg = MRI.createVirtualRegister(
6217 isThumb2 ? ARM::rGPRRegisterClass : ARM::GPRRegisterClass);
6219 // Transfer the remainder of BB and its successor edges to sinkMBB.
6220 SinkBB->splice(SinkBB->begin(), BB,
6221 llvm::next(MachineBasicBlock::iterator(MI)),
6223 SinkBB->transferSuccessorsAndUpdatePHIs(BB);
6225 BB->addSuccessor(RSBBB);
6226 BB->addSuccessor(SinkBB);
6228 // fall through to SinkMBB
6229 RSBBB->addSuccessor(SinkBB);
6231 // insert a movs at the end of BB
6232 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2MOVr : ARM::MOVr),
6234 .addReg(ABSSrcReg, RegState::Kill)
6235 .addImm((unsigned)ARMCC::AL).addReg(0)
6236 .addReg(ARM::CPSR, RegState::Define);
6238 // insert a bcc with opposite CC to ARMCC::MI at the end of BB
6240 TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)).addMBB(SinkBB)
6241 .addImm(ARMCC::getOppositeCondition(ARMCC::MI)).addReg(ARM::CPSR);
6243 // insert rsbri in RSBBB
6244 // Note: BCC and rsbri will be converted into predicated rsbmi
6245 // by if-conversion pass
6246 BuildMI(*RSBBB, RSBBB->begin(), dl,
6247 TII->get(isThumb2 ? ARM::t2RSBri : ARM::RSBri), NewRsbDstReg)
6248 .addReg(NewMovDstReg, RegState::Kill)
6249 .addImm(0).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
6251 // insert PHI in SinkBB,
6252 // reuse ABSDstReg to not change uses of ABS instruction
6253 BuildMI(*SinkBB, SinkBB->begin(), dl,
6254 TII->get(ARM::PHI), ABSDstReg)
6255 .addReg(NewRsbDstReg).addMBB(RSBBB)
6256 .addReg(NewMovDstReg).addMBB(BB);
6258 // remove ABS instruction
6259 MI->eraseFromParent();
6261 // return last added BB
6267 void ARMTargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
6268 SDNode *Node) const {
6269 const MCInstrDesc &MCID = MI->getDesc();
6270 if (!MCID.hasPostISelHook()) {
6271 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
6272 "Pseudo flag-setting opcodes must be marked with 'hasPostISelHook'");
6276 // Adjust potentially 's' setting instructions after isel, i.e. ADC, SBC, RSB,
6277 // RSC. Coming out of isel, they have an implicit CPSR def, but the optional
6278 // operand is still set to noreg. If needed, set the optional operand's
6279 // register to CPSR, and remove the redundant implicit def.
6281 // e.g. ADCS (...opt:%noreg, CPSR<imp-def>) -> ADC (... opt:CPSR<def>).
6283 // Rename pseudo opcodes.
6284 unsigned NewOpc = convertAddSubFlagsOpcode(MI->getOpcode());
6286 const ARMBaseInstrInfo *TII =
6287 static_cast<const ARMBaseInstrInfo*>(getTargetMachine().getInstrInfo());
6288 MI->setDesc(TII->get(NewOpc));
6290 unsigned ccOutIdx = MCID.getNumOperands() - 1;
6292 // Any ARM instruction that sets the 's' bit should specify an optional
6293 // "cc_out" operand in the last operand position.
6294 if (!MCID.hasOptionalDef() || !MCID.OpInfo[ccOutIdx].isOptionalDef()) {
6295 assert(!NewOpc && "Optional cc_out operand required");
6298 // Look for an implicit def of CPSR added by MachineInstr ctor. Remove it
6299 // since we already have an optional CPSR def.
6300 bool definesCPSR = false;
6301 bool deadCPSR = false;
6302 for (unsigned i = MCID.getNumOperands(), e = MI->getNumOperands();
6304 const MachineOperand &MO = MI->getOperand(i);
6305 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) {
6309 MI->RemoveOperand(i);
6314 assert(!NewOpc && "Optional cc_out operand required");
6317 assert(deadCPSR == !Node->hasAnyUseOfValue(1) && "inconsistent dead flag");
6319 assert(!MI->getOperand(ccOutIdx).getReg() &&
6320 "expect uninitialized optional cc_out operand");
6324 // If this instruction was defined with an optional CPSR def and its dag node
6325 // had a live implicit CPSR def, then activate the optional CPSR def.
6326 MachineOperand &MO = MI->getOperand(ccOutIdx);
6327 MO.setReg(ARM::CPSR);
6331 //===----------------------------------------------------------------------===//
6332 // ARM Optimization Hooks
6333 //===----------------------------------------------------------------------===//
6336 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
6337 TargetLowering::DAGCombinerInfo &DCI) {
6338 SelectionDAG &DAG = DCI.DAG;
6339 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6340 EVT VT = N->getValueType(0);
6341 unsigned Opc = N->getOpcode();
6342 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
6343 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
6344 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
6345 ISD::CondCode CC = ISD::SETCC_INVALID;
6348 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
6350 SDValue CCOp = Slct.getOperand(0);
6351 if (CCOp.getOpcode() == ISD::SETCC)
6352 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
6355 bool DoXform = false;
6357 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
6360 if (LHS.getOpcode() == ISD::Constant &&
6361 cast<ConstantSDNode>(LHS)->isNullValue()) {
6363 } else if (CC != ISD::SETCC_INVALID &&
6364 RHS.getOpcode() == ISD::Constant &&
6365 cast<ConstantSDNode>(RHS)->isNullValue()) {
6366 std::swap(LHS, RHS);
6367 SDValue Op0 = Slct.getOperand(0);
6368 EVT OpVT = isSlctCC ? Op0.getValueType() :
6369 Op0.getOperand(0).getValueType();
6370 bool isInt = OpVT.isInteger();
6371 CC = ISD::getSetCCInverse(CC, isInt);
6373 if (!TLI.isCondCodeLegal(CC, OpVT))
6374 return SDValue(); // Inverse operator isn't legal.
6381 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
6383 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
6384 Slct.getOperand(0), Slct.getOperand(1), CC);
6385 SDValue CCOp = Slct.getOperand(0);
6387 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
6388 CCOp.getOperand(0), CCOp.getOperand(1), CC);
6389 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
6390 CCOp, OtherOp, Result);
6395 // AddCombineToVPADDL- For pair-wise add on neon, use the vpaddl instruction
6396 // (only after legalization).
6397 static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1,
6398 TargetLowering::DAGCombinerInfo &DCI,
6399 const ARMSubtarget *Subtarget) {
6401 // Only perform optimization if after legalize, and if NEON is available. We
6402 // also expected both operands to be BUILD_VECTORs.
6403 if (DCI.isBeforeLegalize() || !Subtarget->hasNEON()
6404 || N0.getOpcode() != ISD::BUILD_VECTOR
6405 || N1.getOpcode() != ISD::BUILD_VECTOR)
6408 // Check output type since VPADDL operand elements can only be 8, 16, or 32.
6409 EVT VT = N->getValueType(0);
6410 if (!VT.isInteger() || VT.getVectorElementType() == MVT::i64)
6413 // Check that the vector operands are of the right form.
6414 // N0 and N1 are BUILD_VECTOR nodes with N number of EXTRACT_VECTOR
6415 // operands, where N is the size of the formed vector.
6416 // Each EXTRACT_VECTOR should have the same input vector and odd or even
6417 // index such that we have a pair wise add pattern.
6419 // Grab the vector that all EXTRACT_VECTOR nodes should be referencing.
6420 if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
6422 SDValue Vec = N0->getOperand(0)->getOperand(0);
6423 SDNode *V = Vec.getNode();
6424 unsigned nextIndex = 0;
6426 // For each operands to the ADD which are BUILD_VECTORs,
6427 // check to see if each of their operands are an EXTRACT_VECTOR with
6428 // the same vector and appropriate index.
6429 for (unsigned i = 0, e = N0->getNumOperands(); i != e; ++i) {
6430 if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT
6431 && N1->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
6433 SDValue ExtVec0 = N0->getOperand(i);
6434 SDValue ExtVec1 = N1->getOperand(i);
6436 // First operand is the vector, verify its the same.
6437 if (V != ExtVec0->getOperand(0).getNode() ||
6438 V != ExtVec1->getOperand(0).getNode())
6441 // Second is the constant, verify its correct.
6442 ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(ExtVec0->getOperand(1));
6443 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(ExtVec1->getOperand(1));
6445 // For the constant, we want to see all the even or all the odd.
6446 if (!C0 || !C1 || C0->getZExtValue() != nextIndex
6447 || C1->getZExtValue() != nextIndex+1)
6456 // Create VPADDL node.
6457 SelectionDAG &DAG = DCI.DAG;
6458 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6460 // Build operand list.
6461 SmallVector<SDValue, 8> Ops;
6462 Ops.push_back(DAG.getConstant(Intrinsic::arm_neon_vpaddls,
6463 TLI.getPointerTy()));
6465 // Input is the vector.
6468 // Get widened type and narrowed type.
6470 unsigned numElem = VT.getVectorNumElements();
6471 switch (VT.getVectorElementType().getSimpleVT().SimpleTy) {
6472 case MVT::i8: widenType = MVT::getVectorVT(MVT::i16, numElem); break;
6473 case MVT::i16: widenType = MVT::getVectorVT(MVT::i32, numElem); break;
6474 case MVT::i32: widenType = MVT::getVectorVT(MVT::i64, numElem); break;
6476 assert(0 && "Invalid vector element type for padd optimization.");
6479 SDValue tmp = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(),
6480 widenType, &Ops[0], Ops.size());
6481 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, tmp);
6484 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
6485 /// operands N0 and N1. This is a helper for PerformADDCombine that is
6486 /// called with the default operands, and if that fails, with commuted
6488 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
6489 TargetLowering::DAGCombinerInfo &DCI,
6490 const ARMSubtarget *Subtarget){
6492 // Attempt to create vpaddl for this add.
6493 SDValue Result = AddCombineToVPADDL(N, N0, N1, DCI, Subtarget);
6494 if (Result.getNode())
6497 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
6498 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
6499 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
6500 if (Result.getNode()) return Result;
6505 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
6507 static SDValue PerformADDCombine(SDNode *N,
6508 TargetLowering::DAGCombinerInfo &DCI,
6509 const ARMSubtarget *Subtarget) {
6510 SDValue N0 = N->getOperand(0);
6511 SDValue N1 = N->getOperand(1);
6513 // First try with the default operand order.
6514 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget);
6515 if (Result.getNode())
6518 // If that didn't work, try again with the operands commuted.
6519 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget);
6522 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
6524 static SDValue PerformSUBCombine(SDNode *N,
6525 TargetLowering::DAGCombinerInfo &DCI) {
6526 SDValue N0 = N->getOperand(0);
6527 SDValue N1 = N->getOperand(1);
6529 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
6530 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
6531 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
6532 if (Result.getNode()) return Result;
6538 /// PerformVMULCombine
6539 /// Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the
6540 /// special multiplier accumulator forwarding.
6546 static SDValue PerformVMULCombine(SDNode *N,
6547 TargetLowering::DAGCombinerInfo &DCI,
6548 const ARMSubtarget *Subtarget) {
6549 if (!Subtarget->hasVMLxForwarding())
6552 SelectionDAG &DAG = DCI.DAG;
6553 SDValue N0 = N->getOperand(0);
6554 SDValue N1 = N->getOperand(1);
6555 unsigned Opcode = N0.getOpcode();
6556 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
6557 Opcode != ISD::FADD && Opcode != ISD::FSUB) {
6558 Opcode = N1.getOpcode();
6559 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
6560 Opcode != ISD::FADD && Opcode != ISD::FSUB)
6565 EVT VT = N->getValueType(0);
6566 DebugLoc DL = N->getDebugLoc();
6567 SDValue N00 = N0->getOperand(0);
6568 SDValue N01 = N0->getOperand(1);
6569 return DAG.getNode(Opcode, DL, VT,
6570 DAG.getNode(ISD::MUL, DL, VT, N00, N1),
6571 DAG.getNode(ISD::MUL, DL, VT, N01, N1));
6574 static SDValue PerformMULCombine(SDNode *N,
6575 TargetLowering::DAGCombinerInfo &DCI,
6576 const ARMSubtarget *Subtarget) {
6577 SelectionDAG &DAG = DCI.DAG;
6579 if (Subtarget->isThumb1Only())
6582 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
6585 EVT VT = N->getValueType(0);
6586 if (VT.is64BitVector() || VT.is128BitVector())
6587 return PerformVMULCombine(N, DCI, Subtarget);
6591 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
6595 uint64_t MulAmt = C->getZExtValue();
6596 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt);
6597 ShiftAmt = ShiftAmt & (32 - 1);
6598 SDValue V = N->getOperand(0);
6599 DebugLoc DL = N->getDebugLoc();
6602 MulAmt >>= ShiftAmt;
6603 if (isPowerOf2_32(MulAmt - 1)) {
6604 // (mul x, 2^N + 1) => (add (shl x, N), x)
6605 Res = DAG.getNode(ISD::ADD, DL, VT,
6606 V, DAG.getNode(ISD::SHL, DL, VT,
6607 V, DAG.getConstant(Log2_32(MulAmt-1),
6609 } else if (isPowerOf2_32(MulAmt + 1)) {
6610 // (mul x, 2^N - 1) => (sub (shl x, N), x)
6611 Res = DAG.getNode(ISD::SUB, DL, VT,
6612 DAG.getNode(ISD::SHL, DL, VT,
6613 V, DAG.getConstant(Log2_32(MulAmt+1),
6620 Res = DAG.getNode(ISD::SHL, DL, VT, Res,
6621 DAG.getConstant(ShiftAmt, MVT::i32));
6623 // Do not add new nodes to DAG combiner worklist.
6624 DCI.CombineTo(N, Res, false);
6628 static SDValue PerformANDCombine(SDNode *N,
6629 TargetLowering::DAGCombinerInfo &DCI) {
6631 // Attempt to use immediate-form VBIC
6632 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
6633 DebugLoc dl = N->getDebugLoc();
6634 EVT VT = N->getValueType(0);
6635 SelectionDAG &DAG = DCI.DAG;
6637 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
6640 APInt SplatBits, SplatUndef;
6641 unsigned SplatBitSize;
6644 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
6645 if (SplatBitSize <= 64) {
6647 SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(),
6648 SplatUndef.getZExtValue(), SplatBitSize,
6649 DAG, VbicVT, VT.is128BitVector(),
6651 if (Val.getNode()) {
6653 DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0));
6654 SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val);
6655 return DAG.getNode(ISD::BITCAST, dl, VT, Vbic);
6663 /// PerformORCombine - Target-specific dag combine xforms for ISD::OR
6664 static SDValue PerformORCombine(SDNode *N,
6665 TargetLowering::DAGCombinerInfo &DCI,
6666 const ARMSubtarget *Subtarget) {
6667 // Attempt to use immediate-form VORR
6668 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
6669 DebugLoc dl = N->getDebugLoc();
6670 EVT VT = N->getValueType(0);
6671 SelectionDAG &DAG = DCI.DAG;
6673 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
6676 APInt SplatBits, SplatUndef;
6677 unsigned SplatBitSize;
6679 if (BVN && Subtarget->hasNEON() &&
6680 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
6681 if (SplatBitSize <= 64) {
6683 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
6684 SplatUndef.getZExtValue(), SplatBitSize,
6685 DAG, VorrVT, VT.is128BitVector(),
6687 if (Val.getNode()) {
6689 DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0));
6690 SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val);
6691 return DAG.getNode(ISD::BITCAST, dl, VT, Vorr);
6696 SDValue N0 = N->getOperand(0);
6697 if (N0.getOpcode() != ISD::AND)
6699 SDValue N1 = N->getOperand(1);
6701 // (or (and B, A), (and C, ~A)) => (VBSL A, B, C) when A is a constant.
6702 if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() &&
6703 DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
6705 unsigned SplatBitSize;
6708 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1));
6710 if (BVN0 && BVN0->isConstantSplat(SplatBits0, SplatUndef, SplatBitSize,
6711 HasAnyUndefs) && !HasAnyUndefs) {
6712 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(1));
6714 if (BVN1 && BVN1->isConstantSplat(SplatBits1, SplatUndef, SplatBitSize,
6715 HasAnyUndefs) && !HasAnyUndefs &&
6716 SplatBits0 == ~SplatBits1) {
6717 // Canonicalize the vector type to make instruction selection simpler.
6718 EVT CanonicalVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
6719 SDValue Result = DAG.getNode(ARMISD::VBSL, dl, CanonicalVT,
6720 N0->getOperand(1), N0->getOperand(0),
6722 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
6727 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when
6730 // BFI is only available on V6T2+
6731 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops())
6734 DebugLoc DL = N->getDebugLoc();
6735 // 1) or (and A, mask), val => ARMbfi A, val, mask
6736 // iff (val & mask) == val
6738 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
6739 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2)
6740 // && mask == ~mask2
6741 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2)
6742 // && ~mask == mask2
6743 // (i.e., copy a bitfield value into another bitfield of the same width)
6748 SDValue N00 = N0.getOperand(0);
6750 // The value and the mask need to be constants so we can verify this is
6751 // actually a bitfield set. If the mask is 0xffff, we can do better
6752 // via a movt instruction, so don't use BFI in that case.
6753 SDValue MaskOp = N0.getOperand(1);
6754 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(MaskOp);
6757 unsigned Mask = MaskC->getZExtValue();
6761 // Case (1): or (and A, mask), val => ARMbfi A, val, mask
6762 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
6764 unsigned Val = N1C->getZExtValue();
6765 if ((Val & ~Mask) != Val)
6768 if (ARM::isBitFieldInvertedMask(Mask)) {
6769 Val >>= CountTrailingZeros_32(~Mask);
6771 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00,
6772 DAG.getConstant(Val, MVT::i32),
6773 DAG.getConstant(Mask, MVT::i32));
6775 // Do not add new nodes to DAG combiner worklist.
6776 DCI.CombineTo(N, Res, false);
6779 } else if (N1.getOpcode() == ISD::AND) {
6780 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
6781 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
6784 unsigned Mask2 = N11C->getZExtValue();
6786 // Mask and ~Mask2 (or reverse) must be equivalent for the BFI pattern
6788 if (ARM::isBitFieldInvertedMask(Mask) &&
6790 // The pack halfword instruction works better for masks that fit it,
6791 // so use that when it's available.
6792 if (Subtarget->hasT2ExtractPack() &&
6793 (Mask == 0xffff || Mask == 0xffff0000))
6796 unsigned amt = CountTrailingZeros_32(Mask2);
6797 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
6798 DAG.getConstant(amt, MVT::i32));
6799 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res,
6800 DAG.getConstant(Mask, MVT::i32));
6801 // Do not add new nodes to DAG combiner worklist.
6802 DCI.CombineTo(N, Res, false);
6804 } else if (ARM::isBitFieldInvertedMask(~Mask) &&
6806 // The pack halfword instruction works better for masks that fit it,
6807 // so use that when it's available.
6808 if (Subtarget->hasT2ExtractPack() &&
6809 (Mask2 == 0xffff || Mask2 == 0xffff0000))
6812 unsigned lsb = CountTrailingZeros_32(Mask);
6813 Res = DAG.getNode(ISD::SRL, DL, VT, N00,
6814 DAG.getConstant(lsb, MVT::i32));
6815 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
6816 DAG.getConstant(Mask2, MVT::i32));
6817 // Do not add new nodes to DAG combiner worklist.
6818 DCI.CombineTo(N, Res, false);
6823 if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) &&
6824 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) &&
6825 ARM::isBitFieldInvertedMask(~Mask)) {
6826 // Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask
6827 // where lsb(mask) == #shamt and masked bits of B are known zero.
6828 SDValue ShAmt = N00.getOperand(1);
6829 unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue();
6830 unsigned LSB = CountTrailingZeros_32(Mask);
6834 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0),
6835 DAG.getConstant(~Mask, MVT::i32));
6837 // Do not add new nodes to DAG combiner worklist.
6838 DCI.CombineTo(N, Res, false);
6844 /// PerformBFICombine - (bfi A, (and B, Mask1), Mask2) -> (bfi A, B, Mask2) iff
6845 /// the bits being cleared by the AND are not demanded by the BFI.
6846 static SDValue PerformBFICombine(SDNode *N,
6847 TargetLowering::DAGCombinerInfo &DCI) {
6848 SDValue N1 = N->getOperand(1);
6849 if (N1.getOpcode() == ISD::AND) {
6850 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
6853 unsigned InvMask = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
6854 unsigned LSB = CountTrailingZeros_32(~InvMask);
6855 unsigned Width = (32 - CountLeadingZeros_32(~InvMask)) - LSB;
6856 unsigned Mask = (1 << Width)-1;
6857 unsigned Mask2 = N11C->getZExtValue();
6858 if ((Mask & (~Mask2)) == 0)
6859 return DCI.DAG.getNode(ARMISD::BFI, N->getDebugLoc(), N->getValueType(0),
6860 N->getOperand(0), N1.getOperand(0),
6866 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
6867 /// ARMISD::VMOVRRD.
6868 static SDValue PerformVMOVRRDCombine(SDNode *N,
6869 TargetLowering::DAGCombinerInfo &DCI) {
6870 // vmovrrd(vmovdrr x, y) -> x,y
6871 SDValue InDouble = N->getOperand(0);
6872 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
6873 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
6875 // vmovrrd(load f64) -> (load i32), (load i32)
6876 SDNode *InNode = InDouble.getNode();
6877 if (ISD::isNormalLoad(InNode) && InNode->hasOneUse() &&
6878 InNode->getValueType(0) == MVT::f64 &&
6879 InNode->getOperand(1).getOpcode() == ISD::FrameIndex &&
6880 !cast<LoadSDNode>(InNode)->isVolatile()) {
6881 // TODO: Should this be done for non-FrameIndex operands?
6882 LoadSDNode *LD = cast<LoadSDNode>(InNode);
6884 SelectionDAG &DAG = DCI.DAG;
6885 DebugLoc DL = LD->getDebugLoc();
6886 SDValue BasePtr = LD->getBasePtr();
6887 SDValue NewLD1 = DAG.getLoad(MVT::i32, DL, LD->getChain(), BasePtr,
6888 LD->getPointerInfo(), LD->isVolatile(),
6889 LD->isNonTemporal(), LD->getAlignment());
6891 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
6892 DAG.getConstant(4, MVT::i32));
6893 SDValue NewLD2 = DAG.getLoad(MVT::i32, DL, NewLD1.getValue(1), OffsetPtr,
6894 LD->getPointerInfo(), LD->isVolatile(),
6895 LD->isNonTemporal(),
6896 std::min(4U, LD->getAlignment() / 2));
6898 DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), NewLD2.getValue(1));
6899 SDValue Result = DCI.CombineTo(N, NewLD1, NewLD2);
6900 DCI.RemoveFromWorklist(LD);
6908 /// PerformVMOVDRRCombine - Target-specific dag combine xforms for
6909 /// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands.
6910 static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) {
6911 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X)
6912 SDValue Op0 = N->getOperand(0);
6913 SDValue Op1 = N->getOperand(1);
6914 if (Op0.getOpcode() == ISD::BITCAST)
6915 Op0 = Op0.getOperand(0);
6916 if (Op1.getOpcode() == ISD::BITCAST)
6917 Op1 = Op1.getOperand(0);
6918 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
6919 Op0.getNode() == Op1.getNode() &&
6920 Op0.getResNo() == 0 && Op1.getResNo() == 1)
6921 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
6922 N->getValueType(0), Op0.getOperand(0));
6926 /// PerformSTORECombine - Target-specific dag combine xforms for
6928 static SDValue PerformSTORECombine(SDNode *N,
6929 TargetLowering::DAGCombinerInfo &DCI) {
6930 // Bitcast an i64 store extracted from a vector to f64.
6931 // Otherwise, the i64 value will be legalized to a pair of i32 values.
6932 StoreSDNode *St = cast<StoreSDNode>(N);
6933 SDValue StVal = St->getValue();
6934 if (!ISD::isNormalStore(St) || St->isVolatile())
6937 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR &&
6938 StVal.getNode()->hasOneUse() && !St->isVolatile()) {
6939 SelectionDAG &DAG = DCI.DAG;
6940 DebugLoc DL = St->getDebugLoc();
6941 SDValue BasePtr = St->getBasePtr();
6942 SDValue NewST1 = DAG.getStore(St->getChain(), DL,
6943 StVal.getNode()->getOperand(0), BasePtr,
6944 St->getPointerInfo(), St->isVolatile(),
6945 St->isNonTemporal(), St->getAlignment());
6947 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
6948 DAG.getConstant(4, MVT::i32));
6949 return DAG.getStore(NewST1.getValue(0), DL, StVal.getNode()->getOperand(1),
6950 OffsetPtr, St->getPointerInfo(), St->isVolatile(),
6951 St->isNonTemporal(),
6952 std::min(4U, St->getAlignment() / 2));
6955 if (StVal.getValueType() != MVT::i64 ||
6956 StVal.getNode()->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
6959 SelectionDAG &DAG = DCI.DAG;
6960 DebugLoc dl = StVal.getDebugLoc();
6961 SDValue IntVec = StVal.getOperand(0);
6962 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
6963 IntVec.getValueType().getVectorNumElements());
6964 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec);
6965 SDValue ExtElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
6966 Vec, StVal.getOperand(1));
6967 dl = N->getDebugLoc();
6968 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt);
6969 // Make the DAGCombiner fold the bitcasts.
6970 DCI.AddToWorklist(Vec.getNode());
6971 DCI.AddToWorklist(ExtElt.getNode());
6972 DCI.AddToWorklist(V.getNode());
6973 return DAG.getStore(St->getChain(), dl, V, St->getBasePtr(),
6974 St->getPointerInfo(), St->isVolatile(),
6975 St->isNonTemporal(), St->getAlignment(),
6979 /// hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node
6980 /// are normal, non-volatile loads. If so, it is profitable to bitcast an
6981 /// i64 vector to have f64 elements, since the value can then be loaded
6982 /// directly into a VFP register.
6983 static bool hasNormalLoadOperand(SDNode *N) {
6984 unsigned NumElts = N->getValueType(0).getVectorNumElements();
6985 for (unsigned i = 0; i < NumElts; ++i) {
6986 SDNode *Elt = N->getOperand(i).getNode();
6987 if (ISD::isNormalLoad(Elt) && !cast<LoadSDNode>(Elt)->isVolatile())
6993 /// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for
6994 /// ISD::BUILD_VECTOR.
6995 static SDValue PerformBUILD_VECTORCombine(SDNode *N,
6996 TargetLowering::DAGCombinerInfo &DCI){
6997 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X):
6998 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value
6999 // into a pair of GPRs, which is fine when the value is used as a scalar,
7000 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD.
7001 SelectionDAG &DAG = DCI.DAG;
7002 if (N->getNumOperands() == 2) {
7003 SDValue RV = PerformVMOVDRRCombine(N, DAG);
7008 // Load i64 elements as f64 values so that type legalization does not split
7009 // them up into i32 values.
7010 EVT VT = N->getValueType(0);
7011 if (VT.getVectorElementType() != MVT::i64 || !hasNormalLoadOperand(N))
7013 DebugLoc dl = N->getDebugLoc();
7014 SmallVector<SDValue, 8> Ops;
7015 unsigned NumElts = VT.getVectorNumElements();
7016 for (unsigned i = 0; i < NumElts; ++i) {
7017 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(i));
7019 // Make the DAGCombiner fold the bitcast.
7020 DCI.AddToWorklist(V.getNode());
7022 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, NumElts);
7023 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, FloatVT, Ops.data(), NumElts);
7024 return DAG.getNode(ISD::BITCAST, dl, VT, BV);
7027 /// PerformInsertEltCombine - Target-specific dag combine xforms for
7028 /// ISD::INSERT_VECTOR_ELT.
7029 static SDValue PerformInsertEltCombine(SDNode *N,
7030 TargetLowering::DAGCombinerInfo &DCI) {
7031 // Bitcast an i64 load inserted into a vector to f64.
7032 // Otherwise, the i64 value will be legalized to a pair of i32 values.
7033 EVT VT = N->getValueType(0);
7034 SDNode *Elt = N->getOperand(1).getNode();
7035 if (VT.getVectorElementType() != MVT::i64 ||
7036 !ISD::isNormalLoad(Elt) || cast<LoadSDNode>(Elt)->isVolatile())
7039 SelectionDAG &DAG = DCI.DAG;
7040 DebugLoc dl = N->getDebugLoc();
7041 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
7042 VT.getVectorNumElements());
7043 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, N->getOperand(0));
7044 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(1));
7045 // Make the DAGCombiner fold the bitcasts.
7046 DCI.AddToWorklist(Vec.getNode());
7047 DCI.AddToWorklist(V.getNode());
7048 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT,
7049 Vec, V, N->getOperand(2));
7050 return DAG.getNode(ISD::BITCAST, dl, VT, InsElt);
7053 /// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for
7054 /// ISD::VECTOR_SHUFFLE.
7055 static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) {
7056 // The LLVM shufflevector instruction does not require the shuffle mask
7057 // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does
7058 // have that requirement. When translating to ISD::VECTOR_SHUFFLE, if the
7059 // operands do not match the mask length, they are extended by concatenating
7060 // them with undef vectors. That is probably the right thing for other
7061 // targets, but for NEON it is better to concatenate two double-register
7062 // size vector operands into a single quad-register size vector. Do that
7063 // transformation here:
7064 // shuffle(concat(v1, undef), concat(v2, undef)) ->
7065 // shuffle(concat(v1, v2), undef)
7066 SDValue Op0 = N->getOperand(0);
7067 SDValue Op1 = N->getOperand(1);
7068 if (Op0.getOpcode() != ISD::CONCAT_VECTORS ||
7069 Op1.getOpcode() != ISD::CONCAT_VECTORS ||
7070 Op0.getNumOperands() != 2 ||
7071 Op1.getNumOperands() != 2)
7073 SDValue Concat0Op1 = Op0.getOperand(1);
7074 SDValue Concat1Op1 = Op1.getOperand(1);
7075 if (Concat0Op1.getOpcode() != ISD::UNDEF ||
7076 Concat1Op1.getOpcode() != ISD::UNDEF)
7078 // Skip the transformation if any of the types are illegal.
7079 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7080 EVT VT = N->getValueType(0);
7081 if (!TLI.isTypeLegal(VT) ||
7082 !TLI.isTypeLegal(Concat0Op1.getValueType()) ||
7083 !TLI.isTypeLegal(Concat1Op1.getValueType()))
7086 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT,
7087 Op0.getOperand(0), Op1.getOperand(0));
7088 // Translate the shuffle mask.
7089 SmallVector<int, 16> NewMask;
7090 unsigned NumElts = VT.getVectorNumElements();
7091 unsigned HalfElts = NumElts/2;
7092 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
7093 for (unsigned n = 0; n < NumElts; ++n) {
7094 int MaskElt = SVN->getMaskElt(n);
7096 if (MaskElt < (int)HalfElts)
7098 else if (MaskElt >= (int)NumElts && MaskElt < (int)(NumElts + HalfElts))
7099 NewElt = HalfElts + MaskElt - NumElts;
7100 NewMask.push_back(NewElt);
7102 return DAG.getVectorShuffle(VT, N->getDebugLoc(), NewConcat,
7103 DAG.getUNDEF(VT), NewMask.data());
7106 /// CombineBaseUpdate - Target-specific DAG combine function for VLDDUP and
7107 /// NEON load/store intrinsics to merge base address updates.
7108 static SDValue CombineBaseUpdate(SDNode *N,
7109 TargetLowering::DAGCombinerInfo &DCI) {
7110 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
7113 SelectionDAG &DAG = DCI.DAG;
7114 bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID ||
7115 N->getOpcode() == ISD::INTRINSIC_W_CHAIN);
7116 unsigned AddrOpIdx = (isIntrinsic ? 2 : 1);
7117 SDValue Addr = N->getOperand(AddrOpIdx);
7119 // Search for a use of the address operand that is an increment.
7120 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
7121 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
7123 if (User->getOpcode() != ISD::ADD ||
7124 UI.getUse().getResNo() != Addr.getResNo())
7127 // Check that the add is independent of the load/store. Otherwise, folding
7128 // it would create a cycle.
7129 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
7132 // Find the new opcode for the updating load/store.
7134 bool isLaneOp = false;
7135 unsigned NewOpc = 0;
7136 unsigned NumVecs = 0;
7138 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
7140 default: assert(0 && "unexpected intrinsic for Neon base update");
7141 case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD;
7143 case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD;
7145 case Intrinsic::arm_neon_vld3: NewOpc = ARMISD::VLD3_UPD;
7147 case Intrinsic::arm_neon_vld4: NewOpc = ARMISD::VLD4_UPD;
7149 case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD;
7150 NumVecs = 2; isLaneOp = true; break;
7151 case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD;
7152 NumVecs = 3; isLaneOp = true; break;
7153 case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD;
7154 NumVecs = 4; isLaneOp = true; break;
7155 case Intrinsic::arm_neon_vst1: NewOpc = ARMISD::VST1_UPD;
7156 NumVecs = 1; isLoad = false; break;
7157 case Intrinsic::arm_neon_vst2: NewOpc = ARMISD::VST2_UPD;
7158 NumVecs = 2; isLoad = false; break;
7159 case Intrinsic::arm_neon_vst3: NewOpc = ARMISD::VST3_UPD;
7160 NumVecs = 3; isLoad = false; break;
7161 case Intrinsic::arm_neon_vst4: NewOpc = ARMISD::VST4_UPD;
7162 NumVecs = 4; isLoad = false; break;
7163 case Intrinsic::arm_neon_vst2lane: NewOpc = ARMISD::VST2LN_UPD;
7164 NumVecs = 2; isLoad = false; isLaneOp = true; break;
7165 case Intrinsic::arm_neon_vst3lane: NewOpc = ARMISD::VST3LN_UPD;
7166 NumVecs = 3; isLoad = false; isLaneOp = true; break;
7167 case Intrinsic::arm_neon_vst4lane: NewOpc = ARMISD::VST4LN_UPD;
7168 NumVecs = 4; isLoad = false; isLaneOp = true; break;
7172 switch (N->getOpcode()) {
7173 default: assert(0 && "unexpected opcode for Neon base update");
7174 case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break;
7175 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break;
7176 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break;
7180 // Find the size of memory referenced by the load/store.
7183 VecTy = N->getValueType(0);
7185 VecTy = N->getOperand(AddrOpIdx+1).getValueType();
7186 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
7188 NumBytes /= VecTy.getVectorNumElements();
7190 // If the increment is a constant, it must match the memory ref size.
7191 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
7192 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
7193 uint64_t IncVal = CInc->getZExtValue();
7194 if (IncVal != NumBytes)
7196 } else if (NumBytes >= 3 * 16) {
7197 // VLD3/4 and VST3/4 for 128-bit vectors are implemented with two
7198 // separate instructions that make it harder to use a non-constant update.
7202 // Create the new updating load/store node.
7204 unsigned NumResultVecs = (isLoad ? NumVecs : 0);
7206 for (n = 0; n < NumResultVecs; ++n)
7208 Tys[n++] = MVT::i32;
7209 Tys[n] = MVT::Other;
7210 SDVTList SDTys = DAG.getVTList(Tys, NumResultVecs+2);
7211 SmallVector<SDValue, 8> Ops;
7212 Ops.push_back(N->getOperand(0)); // incoming chain
7213 Ops.push_back(N->getOperand(AddrOpIdx));
7215 for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands(); ++i) {
7216 Ops.push_back(N->getOperand(i));
7218 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
7219 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, N->getDebugLoc(), SDTys,
7220 Ops.data(), Ops.size(),
7221 MemInt->getMemoryVT(),
7222 MemInt->getMemOperand());
7225 std::vector<SDValue> NewResults;
7226 for (unsigned i = 0; i < NumResultVecs; ++i) {
7227 NewResults.push_back(SDValue(UpdN.getNode(), i));
7229 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs+1)); // chain
7230 DCI.CombineTo(N, NewResults);
7231 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
7238 /// CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a
7239 /// vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic
7240 /// are also VDUPLANEs. If so, combine them to a vldN-dup operation and
7242 static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
7243 SelectionDAG &DAG = DCI.DAG;
7244 EVT VT = N->getValueType(0);
7245 // vldN-dup instructions only support 64-bit vectors for N > 1.
7246 if (!VT.is64BitVector())
7249 // Check if the VDUPLANE operand is a vldN-dup intrinsic.
7250 SDNode *VLD = N->getOperand(0).getNode();
7251 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN)
7253 unsigned NumVecs = 0;
7254 unsigned NewOpc = 0;
7255 unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue();
7256 if (IntNo == Intrinsic::arm_neon_vld2lane) {
7258 NewOpc = ARMISD::VLD2DUP;
7259 } else if (IntNo == Intrinsic::arm_neon_vld3lane) {
7261 NewOpc = ARMISD::VLD3DUP;
7262 } else if (IntNo == Intrinsic::arm_neon_vld4lane) {
7264 NewOpc = ARMISD::VLD4DUP;
7269 // First check that all the vldN-lane uses are VDUPLANEs and that the lane
7270 // numbers match the load.
7271 unsigned VLDLaneNo =
7272 cast<ConstantSDNode>(VLD->getOperand(NumVecs+3))->getZExtValue();
7273 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
7275 // Ignore uses of the chain result.
7276 if (UI.getUse().getResNo() == NumVecs)
7279 if (User->getOpcode() != ARMISD::VDUPLANE ||
7280 VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue())
7284 // Create the vldN-dup node.
7287 for (n = 0; n < NumVecs; ++n)
7289 Tys[n] = MVT::Other;
7290 SDVTList SDTys = DAG.getVTList(Tys, NumVecs+1);
7291 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) };
7292 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD);
7293 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, VLD->getDebugLoc(), SDTys,
7294 Ops, 2, VLDMemInt->getMemoryVT(),
7295 VLDMemInt->getMemOperand());
7298 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
7300 unsigned ResNo = UI.getUse().getResNo();
7301 // Ignore uses of the chain result.
7302 if (ResNo == NumVecs)
7305 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo));
7308 // Now the vldN-lane intrinsic is dead except for its chain result.
7309 // Update uses of the chain.
7310 std::vector<SDValue> VLDDupResults;
7311 for (unsigned n = 0; n < NumVecs; ++n)
7312 VLDDupResults.push_back(SDValue(VLDDup.getNode(), n));
7313 VLDDupResults.push_back(SDValue(VLDDup.getNode(), NumVecs));
7314 DCI.CombineTo(VLD, VLDDupResults);
7319 /// PerformVDUPLANECombine - Target-specific dag combine xforms for
7320 /// ARMISD::VDUPLANE.
7321 static SDValue PerformVDUPLANECombine(SDNode *N,
7322 TargetLowering::DAGCombinerInfo &DCI) {
7323 SDValue Op = N->getOperand(0);
7325 // If the source is a vldN-lane (N > 1) intrinsic, and all the other uses
7326 // of that intrinsic are also VDUPLANEs, combine them to a vldN-dup operation.
7327 if (CombineVLDDUP(N, DCI))
7328 return SDValue(N, 0);
7330 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
7331 // redundant. Ignore bit_converts for now; element sizes are checked below.
7332 while (Op.getOpcode() == ISD::BITCAST)
7333 Op = Op.getOperand(0);
7334 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
7337 // Make sure the VMOV element size is not bigger than the VDUPLANE elements.
7338 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits();
7339 // The canonical VMOV for a zero vector uses a 32-bit element size.
7340 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7342 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
7344 EVT VT = N->getValueType(0);
7345 if (EltSize > VT.getVectorElementType().getSizeInBits())
7348 return DCI.DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
7351 // isConstVecPow2 - Return true if each vector element is a power of 2, all
7352 // elements are the same constant, C, and Log2(C) ranges from 1 to 32.
7353 static bool isConstVecPow2(SDValue ConstVec, bool isSigned, uint64_t &C)
7357 for (unsigned I = 0, E = ConstVec.getValueType().getVectorNumElements();
7359 ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(ConstVec.getOperand(I));
7364 APFloat APF = C->getValueAPF();
7365 if (APF.convertToInteger(&cN, 64, isSigned, APFloat::rmTowardZero, &isExact)
7366 != APFloat::opOK || !isExact)
7369 c0 = (I == 0) ? cN : c0;
7370 if (!isPowerOf2_64(cN) || c0 != cN || Log2_64(c0) < 1 || Log2_64(c0) > 32)
7377 /// PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD)
7378 /// can replace combinations of VMUL and VCVT (floating-point to integer)
7379 /// when the VMUL has a constant operand that is a power of 2.
7381 /// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
7382 /// vmul.f32 d16, d17, d16
7383 /// vcvt.s32.f32 d16, d16
7385 /// vcvt.s32.f32 d16, d16, #3
7386 static SDValue PerformVCVTCombine(SDNode *N,
7387 TargetLowering::DAGCombinerInfo &DCI,
7388 const ARMSubtarget *Subtarget) {
7389 SelectionDAG &DAG = DCI.DAG;
7390 SDValue Op = N->getOperand(0);
7392 if (!Subtarget->hasNEON() || !Op.getValueType().isVector() ||
7393 Op.getOpcode() != ISD::FMUL)
7397 SDValue N0 = Op->getOperand(0);
7398 SDValue ConstVec = Op->getOperand(1);
7399 bool isSigned = N->getOpcode() == ISD::FP_TO_SINT;
7401 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
7402 !isConstVecPow2(ConstVec, isSigned, C))
7405 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfp2fxs :
7406 Intrinsic::arm_neon_vcvtfp2fxu;
7407 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(),
7409 DAG.getConstant(IntrinsicOpcode, MVT::i32), N0,
7410 DAG.getConstant(Log2_64(C), MVT::i32));
7413 /// PerformVDIVCombine - VCVT (fixed-point to floating-point, Advanced SIMD)
7414 /// can replace combinations of VCVT (integer to floating-point) and VDIV
7415 /// when the VDIV has a constant operand that is a power of 2.
7417 /// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
7418 /// vcvt.f32.s32 d16, d16
7419 /// vdiv.f32 d16, d17, d16
7421 /// vcvt.f32.s32 d16, d16, #3
7422 static SDValue PerformVDIVCombine(SDNode *N,
7423 TargetLowering::DAGCombinerInfo &DCI,
7424 const ARMSubtarget *Subtarget) {
7425 SelectionDAG &DAG = DCI.DAG;
7426 SDValue Op = N->getOperand(0);
7427 unsigned OpOpcode = Op.getNode()->getOpcode();
7429 if (!Subtarget->hasNEON() || !N->getValueType(0).isVector() ||
7430 (OpOpcode != ISD::SINT_TO_FP && OpOpcode != ISD::UINT_TO_FP))
7434 SDValue ConstVec = N->getOperand(1);
7435 bool isSigned = OpOpcode == ISD::SINT_TO_FP;
7437 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
7438 !isConstVecPow2(ConstVec, isSigned, C))
7441 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfxs2fp :
7442 Intrinsic::arm_neon_vcvtfxu2fp;
7443 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(),
7445 DAG.getConstant(IntrinsicOpcode, MVT::i32),
7446 Op.getOperand(0), DAG.getConstant(Log2_64(C), MVT::i32));
7449 /// Getvshiftimm - Check if this is a valid build_vector for the immediate
7450 /// operand of a vector shift operation, where all the elements of the
7451 /// build_vector must have the same constant integer value.
7452 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
7453 // Ignore bit_converts.
7454 while (Op.getOpcode() == ISD::BITCAST)
7455 Op = Op.getOperand(0);
7456 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
7457 APInt SplatBits, SplatUndef;
7458 unsigned SplatBitSize;
7460 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
7461 HasAnyUndefs, ElementBits) ||
7462 SplatBitSize > ElementBits)
7464 Cnt = SplatBits.getSExtValue();
7468 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
7469 /// operand of a vector shift left operation. That value must be in the range:
7470 /// 0 <= Value < ElementBits for a left shift; or
7471 /// 0 <= Value <= ElementBits for a long left shift.
7472 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
7473 assert(VT.isVector() && "vector shift count is not a vector type");
7474 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
7475 if (! getVShiftImm(Op, ElementBits, Cnt))
7477 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
7480 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
7481 /// operand of a vector shift right operation. For a shift opcode, the value
7482 /// is positive, but for an intrinsic the value count must be negative. The
7483 /// absolute value must be in the range:
7484 /// 1 <= |Value| <= ElementBits for a right shift; or
7485 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
7486 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
7488 assert(VT.isVector() && "vector shift count is not a vector type");
7489 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
7490 if (! getVShiftImm(Op, ElementBits, Cnt))
7494 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
7497 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
7498 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
7499 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
7502 // Don't do anything for most intrinsics.
7505 // Vector shifts: check for immediate versions and lower them.
7506 // Note: This is done during DAG combining instead of DAG legalizing because
7507 // the build_vectors for 64-bit vector element shift counts are generally
7508 // not legal, and it is hard to see their values after they get legalized to
7509 // loads from a constant pool.
7510 case Intrinsic::arm_neon_vshifts:
7511 case Intrinsic::arm_neon_vshiftu:
7512 case Intrinsic::arm_neon_vshiftls:
7513 case Intrinsic::arm_neon_vshiftlu:
7514 case Intrinsic::arm_neon_vshiftn:
7515 case Intrinsic::arm_neon_vrshifts:
7516 case Intrinsic::arm_neon_vrshiftu:
7517 case Intrinsic::arm_neon_vrshiftn:
7518 case Intrinsic::arm_neon_vqshifts:
7519 case Intrinsic::arm_neon_vqshiftu:
7520 case Intrinsic::arm_neon_vqshiftsu:
7521 case Intrinsic::arm_neon_vqshiftns:
7522 case Intrinsic::arm_neon_vqshiftnu:
7523 case Intrinsic::arm_neon_vqshiftnsu:
7524 case Intrinsic::arm_neon_vqrshiftns:
7525 case Intrinsic::arm_neon_vqrshiftnu:
7526 case Intrinsic::arm_neon_vqrshiftnsu: {
7527 EVT VT = N->getOperand(1).getValueType();
7529 unsigned VShiftOpc = 0;
7532 case Intrinsic::arm_neon_vshifts:
7533 case Intrinsic::arm_neon_vshiftu:
7534 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
7535 VShiftOpc = ARMISD::VSHL;
7538 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
7539 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
7540 ARMISD::VSHRs : ARMISD::VSHRu);
7545 case Intrinsic::arm_neon_vshiftls:
7546 case Intrinsic::arm_neon_vshiftlu:
7547 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
7549 llvm_unreachable("invalid shift count for vshll intrinsic");
7551 case Intrinsic::arm_neon_vrshifts:
7552 case Intrinsic::arm_neon_vrshiftu:
7553 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
7557 case Intrinsic::arm_neon_vqshifts:
7558 case Intrinsic::arm_neon_vqshiftu:
7559 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
7563 case Intrinsic::arm_neon_vqshiftsu:
7564 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
7566 llvm_unreachable("invalid shift count for vqshlu intrinsic");
7568 case Intrinsic::arm_neon_vshiftn:
7569 case Intrinsic::arm_neon_vrshiftn:
7570 case Intrinsic::arm_neon_vqshiftns:
7571 case Intrinsic::arm_neon_vqshiftnu:
7572 case Intrinsic::arm_neon_vqshiftnsu:
7573 case Intrinsic::arm_neon_vqrshiftns:
7574 case Intrinsic::arm_neon_vqrshiftnu:
7575 case Intrinsic::arm_neon_vqrshiftnsu:
7576 // Narrowing shifts require an immediate right shift.
7577 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
7579 llvm_unreachable("invalid shift count for narrowing vector shift "
7583 llvm_unreachable("unhandled vector shift");
7587 case Intrinsic::arm_neon_vshifts:
7588 case Intrinsic::arm_neon_vshiftu:
7589 // Opcode already set above.
7591 case Intrinsic::arm_neon_vshiftls:
7592 case Intrinsic::arm_neon_vshiftlu:
7593 if (Cnt == VT.getVectorElementType().getSizeInBits())
7594 VShiftOpc = ARMISD::VSHLLi;
7596 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
7597 ARMISD::VSHLLs : ARMISD::VSHLLu);
7599 case Intrinsic::arm_neon_vshiftn:
7600 VShiftOpc = ARMISD::VSHRN; break;
7601 case Intrinsic::arm_neon_vrshifts:
7602 VShiftOpc = ARMISD::VRSHRs; break;
7603 case Intrinsic::arm_neon_vrshiftu:
7604 VShiftOpc = ARMISD::VRSHRu; break;
7605 case Intrinsic::arm_neon_vrshiftn:
7606 VShiftOpc = ARMISD::VRSHRN; break;
7607 case Intrinsic::arm_neon_vqshifts:
7608 VShiftOpc = ARMISD::VQSHLs; break;
7609 case Intrinsic::arm_neon_vqshiftu:
7610 VShiftOpc = ARMISD::VQSHLu; break;
7611 case Intrinsic::arm_neon_vqshiftsu:
7612 VShiftOpc = ARMISD::VQSHLsu; break;
7613 case Intrinsic::arm_neon_vqshiftns:
7614 VShiftOpc = ARMISD::VQSHRNs; break;
7615 case Intrinsic::arm_neon_vqshiftnu:
7616 VShiftOpc = ARMISD::VQSHRNu; break;
7617 case Intrinsic::arm_neon_vqshiftnsu:
7618 VShiftOpc = ARMISD::VQSHRNsu; break;
7619 case Intrinsic::arm_neon_vqrshiftns:
7620 VShiftOpc = ARMISD::VQRSHRNs; break;
7621 case Intrinsic::arm_neon_vqrshiftnu:
7622 VShiftOpc = ARMISD::VQRSHRNu; break;
7623 case Intrinsic::arm_neon_vqrshiftnsu:
7624 VShiftOpc = ARMISD::VQRSHRNsu; break;
7627 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
7628 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
7631 case Intrinsic::arm_neon_vshiftins: {
7632 EVT VT = N->getOperand(1).getValueType();
7634 unsigned VShiftOpc = 0;
7636 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
7637 VShiftOpc = ARMISD::VSLI;
7638 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
7639 VShiftOpc = ARMISD::VSRI;
7641 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
7644 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
7645 N->getOperand(1), N->getOperand(2),
7646 DAG.getConstant(Cnt, MVT::i32));
7649 case Intrinsic::arm_neon_vqrshifts:
7650 case Intrinsic::arm_neon_vqrshiftu:
7651 // No immediate versions of these to check for.
7658 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
7659 /// lowers them. As with the vector shift intrinsics, this is done during DAG
7660 /// combining instead of DAG legalizing because the build_vectors for 64-bit
7661 /// vector element shift counts are generally not legal, and it is hard to see
7662 /// their values after they get legalized to loads from a constant pool.
7663 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
7664 const ARMSubtarget *ST) {
7665 EVT VT = N->getValueType(0);
7667 // Nothing to be done for scalar shifts.
7668 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7669 if (!VT.isVector() || !TLI.isTypeLegal(VT))
7672 assert(ST->hasNEON() && "unexpected vector shift");
7675 switch (N->getOpcode()) {
7676 default: llvm_unreachable("unexpected shift opcode");
7679 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
7680 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
7681 DAG.getConstant(Cnt, MVT::i32));
7686 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
7687 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
7688 ARMISD::VSHRs : ARMISD::VSHRu);
7689 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
7690 DAG.getConstant(Cnt, MVT::i32));
7696 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
7697 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
7698 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
7699 const ARMSubtarget *ST) {
7700 SDValue N0 = N->getOperand(0);
7702 // Check for sign- and zero-extensions of vector extract operations of 8-
7703 // and 16-bit vector elements. NEON supports these directly. They are
7704 // handled during DAG combining because type legalization will promote them
7705 // to 32-bit types and it is messy to recognize the operations after that.
7706 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
7707 SDValue Vec = N0.getOperand(0);
7708 SDValue Lane = N0.getOperand(1);
7709 EVT VT = N->getValueType(0);
7710 EVT EltVT = N0.getValueType();
7711 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7713 if (VT == MVT::i32 &&
7714 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
7715 TLI.isTypeLegal(Vec.getValueType()) &&
7716 isa<ConstantSDNode>(Lane)) {
7719 switch (N->getOpcode()) {
7720 default: llvm_unreachable("unexpected opcode");
7721 case ISD::SIGN_EXTEND:
7722 Opc = ARMISD::VGETLANEs;
7724 case ISD::ZERO_EXTEND:
7725 case ISD::ANY_EXTEND:
7726 Opc = ARMISD::VGETLANEu;
7729 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
7736 /// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
7737 /// to match f32 max/min patterns to use NEON vmax/vmin instructions.
7738 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
7739 const ARMSubtarget *ST) {
7740 // If the target supports NEON, try to use vmax/vmin instructions for f32
7741 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set,
7742 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
7743 // a NaN; only do the transformation when it matches that behavior.
7745 // For now only do this when using NEON for FP operations; if using VFP, it
7746 // is not obvious that the benefit outweighs the cost of switching to the
7748 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
7749 N->getValueType(0) != MVT::f32)
7752 SDValue CondLHS = N->getOperand(0);
7753 SDValue CondRHS = N->getOperand(1);
7754 SDValue LHS = N->getOperand(2);
7755 SDValue RHS = N->getOperand(3);
7756 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
7758 unsigned Opcode = 0;
7760 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
7761 IsReversed = false; // x CC y ? x : y
7762 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
7763 IsReversed = true ; // x CC y ? y : x
7777 // If LHS is NaN, an ordered comparison will be false and the result will
7778 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
7779 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
7780 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
7781 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
7783 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
7784 // will return -0, so vmin can only be used for unsafe math or if one of
7785 // the operands is known to be nonzero.
7786 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
7788 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
7790 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
7799 // If LHS is NaN, an ordered comparison will be false and the result will
7800 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
7801 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
7802 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
7803 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
7805 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
7806 // will return +0, so vmax can only be used for unsafe math or if one of
7807 // the operands is known to be nonzero.
7808 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
7810 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
7812 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
7818 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS);
7821 /// PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV.
7823 ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const {
7824 SDValue Cmp = N->getOperand(4);
7825 if (Cmp.getOpcode() != ARMISD::CMPZ)
7826 // Only looking at EQ and NE cases.
7829 EVT VT = N->getValueType(0);
7830 DebugLoc dl = N->getDebugLoc();
7831 SDValue LHS = Cmp.getOperand(0);
7832 SDValue RHS = Cmp.getOperand(1);
7833 SDValue FalseVal = N->getOperand(0);
7834 SDValue TrueVal = N->getOperand(1);
7835 SDValue ARMcc = N->getOperand(2);
7836 ARMCC::CondCodes CC =
7837 (ARMCC::CondCodes)cast<ConstantSDNode>(ARMcc)->getZExtValue();
7855 /// FIXME: Turn this into a target neutral optimization?
7857 if (CC == ARMCC::NE && FalseVal == RHS && FalseVal != LHS) {
7858 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, TrueVal, ARMcc,
7859 N->getOperand(3), Cmp);
7860 } else if (CC == ARMCC::EQ && TrueVal == RHS) {
7862 SDValue NewCmp = getARMCmp(LHS, RHS, ISD::SETNE, ARMcc, DAG, dl);
7863 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, FalseVal, ARMcc,
7864 N->getOperand(3), NewCmp);
7867 if (Res.getNode()) {
7868 APInt KnownZero, KnownOne;
7869 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
7870 DAG.ComputeMaskedBits(SDValue(N,0), Mask, KnownZero, KnownOne);
7871 // Capture demanded bits information that would be otherwise lost.
7872 if (KnownZero == 0xfffffffe)
7873 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
7874 DAG.getValueType(MVT::i1));
7875 else if (KnownZero == 0xffffff00)
7876 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
7877 DAG.getValueType(MVT::i8));
7878 else if (KnownZero == 0xffff0000)
7879 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
7880 DAG.getValueType(MVT::i16));
7886 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
7887 DAGCombinerInfo &DCI) const {
7888 switch (N->getOpcode()) {
7890 case ISD::ADD: return PerformADDCombine(N, DCI, Subtarget);
7891 case ISD::SUB: return PerformSUBCombine(N, DCI);
7892 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
7893 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
7894 case ISD::AND: return PerformANDCombine(N, DCI);
7895 case ARMISD::BFI: return PerformBFICombine(N, DCI);
7896 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
7897 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
7898 case ISD::STORE: return PerformSTORECombine(N, DCI);
7899 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI);
7900 case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI);
7901 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
7902 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
7903 case ISD::FP_TO_SINT:
7904 case ISD::FP_TO_UINT: return PerformVCVTCombine(N, DCI, Subtarget);
7905 case ISD::FDIV: return PerformVDIVCombine(N, DCI, Subtarget);
7906 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
7909 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
7910 case ISD::SIGN_EXTEND:
7911 case ISD::ZERO_EXTEND:
7912 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
7913 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
7914 case ARMISD::CMOV: return PerformCMOVCombine(N, DCI.DAG);
7915 case ARMISD::VLD2DUP:
7916 case ARMISD::VLD3DUP:
7917 case ARMISD::VLD4DUP:
7918 return CombineBaseUpdate(N, DCI);
7919 case ISD::INTRINSIC_VOID:
7920 case ISD::INTRINSIC_W_CHAIN:
7921 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
7922 case Intrinsic::arm_neon_vld1:
7923 case Intrinsic::arm_neon_vld2:
7924 case Intrinsic::arm_neon_vld3:
7925 case Intrinsic::arm_neon_vld4:
7926 case Intrinsic::arm_neon_vld2lane:
7927 case Intrinsic::arm_neon_vld3lane:
7928 case Intrinsic::arm_neon_vld4lane:
7929 case Intrinsic::arm_neon_vst1:
7930 case Intrinsic::arm_neon_vst2:
7931 case Intrinsic::arm_neon_vst3:
7932 case Intrinsic::arm_neon_vst4:
7933 case Intrinsic::arm_neon_vst2lane:
7934 case Intrinsic::arm_neon_vst3lane:
7935 case Intrinsic::arm_neon_vst4lane:
7936 return CombineBaseUpdate(N, DCI);
7944 bool ARMTargetLowering::isDesirableToTransformToIntegerOp(unsigned Opc,
7946 return (VT == MVT::f32) && (Opc == ISD::LOAD || Opc == ISD::STORE);
7949 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
7950 if (!Subtarget->allowsUnalignedMem())
7953 switch (VT.getSimpleVT().SimpleTy) {
7960 // FIXME: VLD1 etc with standard alignment is legal.
7964 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
7969 switch (VT.getSimpleVT().SimpleTy) {
7970 default: return false;
7985 if ((V & (Scale - 1)) != 0)
7988 return V == (V & ((1LL << 5) - 1));
7991 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
7992 const ARMSubtarget *Subtarget) {
7999 switch (VT.getSimpleVT().SimpleTy) {
8000 default: return false;
8005 // + imm12 or - imm8
8007 return V == (V & ((1LL << 8) - 1));
8008 return V == (V & ((1LL << 12) - 1));
8011 // Same as ARM mode. FIXME: NEON?
8012 if (!Subtarget->hasVFP2())
8017 return V == (V & ((1LL << 8) - 1));
8021 /// isLegalAddressImmediate - Return true if the integer value can be used
8022 /// as the offset of the target addressing mode for load / store of the
8024 static bool isLegalAddressImmediate(int64_t V, EVT VT,
8025 const ARMSubtarget *Subtarget) {
8032 if (Subtarget->isThumb1Only())
8033 return isLegalT1AddressImmediate(V, VT);
8034 else if (Subtarget->isThumb2())
8035 return isLegalT2AddressImmediate(V, VT, Subtarget);
8040 switch (VT.getSimpleVT().SimpleTy) {
8041 default: return false;
8046 return V == (V & ((1LL << 12) - 1));
8049 return V == (V & ((1LL << 8) - 1));
8052 if (!Subtarget->hasVFP2()) // FIXME: NEON?
8057 return V == (V & ((1LL << 8) - 1));
8061 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
8063 int Scale = AM.Scale;
8067 switch (VT.getSimpleVT().SimpleTy) {
8068 default: return false;
8077 return Scale == 2 || Scale == 4 || Scale == 8;
8080 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
8084 // Note, we allow "void" uses (basically, uses that aren't loads or
8085 // stores), because arm allows folding a scale into many arithmetic
8086 // operations. This should be made more precise and revisited later.
8088 // Allow r << imm, but the imm has to be a multiple of two.
8089 if (Scale & 1) return false;
8090 return isPowerOf2_32(Scale);
8094 /// isLegalAddressingMode - Return true if the addressing mode represented
8095 /// by AM is legal for this target, for a load/store of the specified type.
8096 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
8098 EVT VT = getValueType(Ty, true);
8099 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
8102 // Can never fold addr of global into load/store.
8107 case 0: // no scale reg, must be "r+i" or "r", or "i".
8110 if (Subtarget->isThumb1Only())
8114 // ARM doesn't support any R+R*scale+imm addr modes.
8121 if (Subtarget->isThumb2())
8122 return isLegalT2ScaledAddressingMode(AM, VT);
8124 int Scale = AM.Scale;
8125 switch (VT.getSimpleVT().SimpleTy) {
8126 default: return false;
8130 if (Scale < 0) Scale = -Scale;
8134 return isPowerOf2_32(Scale & ~1);
8138 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
8143 // Note, we allow "void" uses (basically, uses that aren't loads or
8144 // stores), because arm allows folding a scale into many arithmetic
8145 // operations. This should be made more precise and revisited later.
8147 // Allow r << imm, but the imm has to be a multiple of two.
8148 if (Scale & 1) return false;
8149 return isPowerOf2_32(Scale);
8156 /// isLegalICmpImmediate - Return true if the specified immediate is legal
8157 /// icmp immediate, that is the target has icmp instructions which can compare
8158 /// a register against the immediate without having to materialize the
8159 /// immediate into a register.
8160 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
8161 if (!Subtarget->isThumb())
8162 return ARM_AM::getSOImmVal(Imm) != -1;
8163 if (Subtarget->isThumb2())
8164 return ARM_AM::getT2SOImmVal(Imm) != -1;
8165 return Imm >= 0 && Imm <= 255;
8168 /// isLegalAddImmediate - Return true if the specified immediate is legal
8169 /// add immediate, that is the target has add instructions which can add
8170 /// a register with the immediate without having to materialize the
8171 /// immediate into a register.
8172 bool ARMTargetLowering::isLegalAddImmediate(int64_t Imm) const {
8173 return ARM_AM::getSOImmVal(Imm) != -1;
8176 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
8177 bool isSEXTLoad, SDValue &Base,
8178 SDValue &Offset, bool &isInc,
8179 SelectionDAG &DAG) {
8180 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
8183 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
8185 Base = Ptr->getOperand(0);
8186 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
8187 int RHSC = (int)RHS->getZExtValue();
8188 if (RHSC < 0 && RHSC > -256) {
8189 assert(Ptr->getOpcode() == ISD::ADD);
8191 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
8195 isInc = (Ptr->getOpcode() == ISD::ADD);
8196 Offset = Ptr->getOperand(1);
8198 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
8200 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
8201 int RHSC = (int)RHS->getZExtValue();
8202 if (RHSC < 0 && RHSC > -0x1000) {
8203 assert(Ptr->getOpcode() == ISD::ADD);
8205 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
8206 Base = Ptr->getOperand(0);
8211 if (Ptr->getOpcode() == ISD::ADD) {
8213 ARM_AM::ShiftOpc ShOpcVal=
8214 ARM_AM::getShiftOpcForNode(Ptr->getOperand(0).getOpcode());
8215 if (ShOpcVal != ARM_AM::no_shift) {
8216 Base = Ptr->getOperand(1);
8217 Offset = Ptr->getOperand(0);
8219 Base = Ptr->getOperand(0);
8220 Offset = Ptr->getOperand(1);
8225 isInc = (Ptr->getOpcode() == ISD::ADD);
8226 Base = Ptr->getOperand(0);
8227 Offset = Ptr->getOperand(1);
8231 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
8235 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
8236 bool isSEXTLoad, SDValue &Base,
8237 SDValue &Offset, bool &isInc,
8238 SelectionDAG &DAG) {
8239 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
8242 Base = Ptr->getOperand(0);
8243 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
8244 int RHSC = (int)RHS->getZExtValue();
8245 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
8246 assert(Ptr->getOpcode() == ISD::ADD);
8248 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
8250 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
8251 isInc = Ptr->getOpcode() == ISD::ADD;
8252 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
8260 /// getPreIndexedAddressParts - returns true by value, base pointer and
8261 /// offset pointer and addressing mode by reference if the node's address
8262 /// can be legally represented as pre-indexed load / store address.
8264 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
8266 ISD::MemIndexedMode &AM,
8267 SelectionDAG &DAG) const {
8268 if (Subtarget->isThumb1Only())
8273 bool isSEXTLoad = false;
8274 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
8275 Ptr = LD->getBasePtr();
8276 VT = LD->getMemoryVT();
8277 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
8278 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
8279 Ptr = ST->getBasePtr();
8280 VT = ST->getMemoryVT();
8285 bool isLegal = false;
8286 if (Subtarget->isThumb2())
8287 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
8288 Offset, isInc, DAG);
8290 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
8291 Offset, isInc, DAG);
8295 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
8299 /// getPostIndexedAddressParts - returns true by value, base pointer and
8300 /// offset pointer and addressing mode by reference if this node can be
8301 /// combined with a load / store to form a post-indexed load / store.
8302 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
8305 ISD::MemIndexedMode &AM,
8306 SelectionDAG &DAG) const {
8307 if (Subtarget->isThumb1Only())
8312 bool isSEXTLoad = false;
8313 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
8314 VT = LD->getMemoryVT();
8315 Ptr = LD->getBasePtr();
8316 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
8317 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
8318 VT = ST->getMemoryVT();
8319 Ptr = ST->getBasePtr();
8324 bool isLegal = false;
8325 if (Subtarget->isThumb2())
8326 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
8329 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
8335 // Swap base ptr and offset to catch more post-index load / store when
8336 // it's legal. In Thumb2 mode, offset must be an immediate.
8337 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
8338 !Subtarget->isThumb2())
8339 std::swap(Base, Offset);
8341 // Post-indexed load / store update the base pointer.
8346 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
8350 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
8354 const SelectionDAG &DAG,
8355 unsigned Depth) const {
8356 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
8357 switch (Op.getOpcode()) {
8359 case ARMISD::CMOV: {
8360 // Bits are known zero/one if known on the LHS and RHS.
8361 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
8362 if (KnownZero == 0 && KnownOne == 0) return;
8364 APInt KnownZeroRHS, KnownOneRHS;
8365 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
8366 KnownZeroRHS, KnownOneRHS, Depth+1);
8367 KnownZero &= KnownZeroRHS;
8368 KnownOne &= KnownOneRHS;
8374 //===----------------------------------------------------------------------===//
8375 // ARM Inline Assembly Support
8376 //===----------------------------------------------------------------------===//
8378 bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const {
8379 // Looking for "rev" which is V6+.
8380 if (!Subtarget->hasV6Ops())
8383 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
8384 std::string AsmStr = IA->getAsmString();
8385 SmallVector<StringRef, 4> AsmPieces;
8386 SplitString(AsmStr, AsmPieces, ";\n");
8388 switch (AsmPieces.size()) {
8389 default: return false;
8391 AsmStr = AsmPieces[0];
8393 SplitString(AsmStr, AsmPieces, " \t,");
8396 if (AsmPieces.size() == 3 &&
8397 AsmPieces[0] == "rev" && AsmPieces[1] == "$0" && AsmPieces[2] == "$1" &&
8398 IA->getConstraintString().compare(0, 4, "=l,l") == 0) {
8399 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
8400 if (Ty && Ty->getBitWidth() == 32)
8401 return IntrinsicLowering::LowerToByteSwap(CI);
8409 /// getConstraintType - Given a constraint letter, return the type of
8410 /// constraint it is for this target.
8411 ARMTargetLowering::ConstraintType
8412 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
8413 if (Constraint.size() == 1) {
8414 switch (Constraint[0]) {
8416 case 'l': return C_RegisterClass;
8417 case 'w': return C_RegisterClass;
8418 case 'h': return C_RegisterClass;
8419 case 'x': return C_RegisterClass;
8420 case 't': return C_RegisterClass;
8421 case 'j': return C_Other; // Constant for movw.
8422 // An address with a single base register. Due to the way we
8423 // currently handle addresses it is the same as an 'r' memory constraint.
8424 case 'Q': return C_Memory;
8426 } else if (Constraint.size() == 2) {
8427 switch (Constraint[0]) {
8429 // All 'U+' constraints are addresses.
8430 case 'U': return C_Memory;
8433 return TargetLowering::getConstraintType(Constraint);
8436 /// Examine constraint type and operand type and determine a weight value.
8437 /// This object must already have been set up with the operand type
8438 /// and the current alternative constraint selected.
8439 TargetLowering::ConstraintWeight
8440 ARMTargetLowering::getSingleConstraintMatchWeight(
8441 AsmOperandInfo &info, const char *constraint) const {
8442 ConstraintWeight weight = CW_Invalid;
8443 Value *CallOperandVal = info.CallOperandVal;
8444 // If we don't have a value, we can't do a match,
8445 // but allow it at the lowest weight.
8446 if (CallOperandVal == NULL)
8448 Type *type = CallOperandVal->getType();
8449 // Look at the constraint type.
8450 switch (*constraint) {
8452 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
8455 if (type->isIntegerTy()) {
8456 if (Subtarget->isThumb())
8457 weight = CW_SpecificReg;
8459 weight = CW_Register;
8463 if (type->isFloatingPointTy())
8464 weight = CW_Register;
8470 typedef std::pair<unsigned, const TargetRegisterClass*> RCPair;
8472 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
8474 if (Constraint.size() == 1) {
8475 // GCC ARM Constraint Letters
8476 switch (Constraint[0]) {
8477 case 'l': // Low regs or general regs.
8478 if (Subtarget->isThumb())
8479 return RCPair(0U, ARM::tGPRRegisterClass);
8481 return RCPair(0U, ARM::GPRRegisterClass);
8482 case 'h': // High regs or no regs.
8483 if (Subtarget->isThumb())
8484 return RCPair(0U, ARM::hGPRRegisterClass);
8487 return RCPair(0U, ARM::GPRRegisterClass);
8490 return RCPair(0U, ARM::SPRRegisterClass);
8491 if (VT.getSizeInBits() == 64)
8492 return RCPair(0U, ARM::DPRRegisterClass);
8493 if (VT.getSizeInBits() == 128)
8494 return RCPair(0U, ARM::QPRRegisterClass);
8498 return RCPair(0U, ARM::SPR_8RegisterClass);
8499 if (VT.getSizeInBits() == 64)
8500 return RCPair(0U, ARM::DPR_8RegisterClass);
8501 if (VT.getSizeInBits() == 128)
8502 return RCPair(0U, ARM::QPR_8RegisterClass);
8506 return RCPair(0U, ARM::SPRRegisterClass);
8510 if (StringRef("{cc}").equals_lower(Constraint))
8511 return std::make_pair(unsigned(ARM::CPSR), ARM::CCRRegisterClass);
8513 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
8516 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
8517 /// vector. If it is invalid, don't add anything to Ops.
8518 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
8519 std::string &Constraint,
8520 std::vector<SDValue>&Ops,
8521 SelectionDAG &DAG) const {
8522 SDValue Result(0, 0);
8524 // Currently only support length 1 constraints.
8525 if (Constraint.length() != 1) return;
8527 char ConstraintLetter = Constraint[0];
8528 switch (ConstraintLetter) {
8531 case 'I': case 'J': case 'K': case 'L':
8532 case 'M': case 'N': case 'O':
8533 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
8537 int64_t CVal64 = C->getSExtValue();
8538 int CVal = (int) CVal64;
8539 // None of these constraints allow values larger than 32 bits. Check
8540 // that the value fits in an int.
8544 switch (ConstraintLetter) {
8546 // Constant suitable for movw, must be between 0 and
8548 if (Subtarget->hasV6T2Ops())
8549 if (CVal >= 0 && CVal <= 65535)
8553 if (Subtarget->isThumb1Only()) {
8554 // This must be a constant between 0 and 255, for ADD
8556 if (CVal >= 0 && CVal <= 255)
8558 } else if (Subtarget->isThumb2()) {
8559 // A constant that can be used as an immediate value in a
8560 // data-processing instruction.
8561 if (ARM_AM::getT2SOImmVal(CVal) != -1)
8564 // A constant that can be used as an immediate value in a
8565 // data-processing instruction.
8566 if (ARM_AM::getSOImmVal(CVal) != -1)
8572 if (Subtarget->isThumb()) { // FIXME thumb2
8573 // This must be a constant between -255 and -1, for negated ADD
8574 // immediates. This can be used in GCC with an "n" modifier that
8575 // prints the negated value, for use with SUB instructions. It is
8576 // not useful otherwise but is implemented for compatibility.
8577 if (CVal >= -255 && CVal <= -1)
8580 // This must be a constant between -4095 and 4095. It is not clear
8581 // what this constraint is intended for. Implemented for
8582 // compatibility with GCC.
8583 if (CVal >= -4095 && CVal <= 4095)
8589 if (Subtarget->isThumb1Only()) {
8590 // A 32-bit value where only one byte has a nonzero value. Exclude
8591 // zero to match GCC. This constraint is used by GCC internally for
8592 // constants that can be loaded with a move/shift combination.
8593 // It is not useful otherwise but is implemented for compatibility.
8594 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
8596 } else if (Subtarget->isThumb2()) {
8597 // A constant whose bitwise inverse can be used as an immediate
8598 // value in a data-processing instruction. This can be used in GCC
8599 // with a "B" modifier that prints the inverted value, for use with
8600 // BIC and MVN instructions. It is not useful otherwise but is
8601 // implemented for compatibility.
8602 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
8605 // A constant whose bitwise inverse can be used as an immediate
8606 // value in a data-processing instruction. This can be used in GCC
8607 // with a "B" modifier that prints the inverted value, for use with
8608 // BIC and MVN instructions. It is not useful otherwise but is
8609 // implemented for compatibility.
8610 if (ARM_AM::getSOImmVal(~CVal) != -1)
8616 if (Subtarget->isThumb1Only()) {
8617 // This must be a constant between -7 and 7,
8618 // for 3-operand ADD/SUB immediate instructions.
8619 if (CVal >= -7 && CVal < 7)
8621 } else if (Subtarget->isThumb2()) {
8622 // A constant whose negation can be used as an immediate value in a
8623 // data-processing instruction. This can be used in GCC with an "n"
8624 // modifier that prints the negated value, for use with SUB
8625 // instructions. It is not useful otherwise but is implemented for
8627 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
8630 // A constant whose negation can be used as an immediate value in a
8631 // data-processing instruction. This can be used in GCC with an "n"
8632 // modifier that prints the negated value, for use with SUB
8633 // instructions. It is not useful otherwise but is implemented for
8635 if (ARM_AM::getSOImmVal(-CVal) != -1)
8641 if (Subtarget->isThumb()) { // FIXME thumb2
8642 // This must be a multiple of 4 between 0 and 1020, for
8643 // ADD sp + immediate.
8644 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
8647 // A power of two or a constant between 0 and 32. This is used in
8648 // GCC for the shift amount on shifted register operands, but it is
8649 // useful in general for any shift amounts.
8650 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
8656 if (Subtarget->isThumb()) { // FIXME thumb2
8657 // This must be a constant between 0 and 31, for shift amounts.
8658 if (CVal >= 0 && CVal <= 31)
8664 if (Subtarget->isThumb()) { // FIXME thumb2
8665 // This must be a multiple of 4 between -508 and 508, for
8666 // ADD/SUB sp = sp + immediate.
8667 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
8672 Result = DAG.getTargetConstant(CVal, Op.getValueType());
8676 if (Result.getNode()) {
8677 Ops.push_back(Result);
8680 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
8684 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
8685 // The ARM target isn't yet aware of offsets.
8689 bool ARM::isBitFieldInvertedMask(unsigned v) {
8690 if (v == 0xffffffff)
8692 // there can be 1's on either or both "outsides", all the "inside"
8694 unsigned int lsb = 0, msb = 31;
8695 while (v & (1 << msb)) --msb;
8696 while (v & (1 << lsb)) ++lsb;
8697 for (unsigned int i = lsb; i <= msb; ++i) {
8704 /// isFPImmLegal - Returns true if the target can instruction select the
8705 /// specified FP immediate natively. If false, the legalizer will
8706 /// materialize the FP immediate as a load from a constant pool.
8707 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
8708 if (!Subtarget->hasVFP3())
8711 return ARM_AM::getFP32Imm(Imm) != -1;
8713 return ARM_AM::getFP64Imm(Imm) != -1;
8717 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
8718 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
8719 /// specified in the intrinsic calls.
8720 bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
8722 unsigned Intrinsic) const {
8723 switch (Intrinsic) {
8724 case Intrinsic::arm_neon_vld1:
8725 case Intrinsic::arm_neon_vld2:
8726 case Intrinsic::arm_neon_vld3:
8727 case Intrinsic::arm_neon_vld4:
8728 case Intrinsic::arm_neon_vld2lane:
8729 case Intrinsic::arm_neon_vld3lane:
8730 case Intrinsic::arm_neon_vld4lane: {
8731 Info.opc = ISD::INTRINSIC_W_CHAIN;
8732 // Conservatively set memVT to the entire set of vectors loaded.
8733 uint64_t NumElts = getTargetData()->getTypeAllocSize(I.getType()) / 8;
8734 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
8735 Info.ptrVal = I.getArgOperand(0);
8737 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
8738 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
8739 Info.vol = false; // volatile loads with NEON intrinsics not supported
8740 Info.readMem = true;
8741 Info.writeMem = false;
8744 case Intrinsic::arm_neon_vst1:
8745 case Intrinsic::arm_neon_vst2:
8746 case Intrinsic::arm_neon_vst3:
8747 case Intrinsic::arm_neon_vst4:
8748 case Intrinsic::arm_neon_vst2lane:
8749 case Intrinsic::arm_neon_vst3lane:
8750 case Intrinsic::arm_neon_vst4lane: {
8751 Info.opc = ISD::INTRINSIC_VOID;
8752 // Conservatively set memVT to the entire set of vectors stored.
8753 unsigned NumElts = 0;
8754 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
8755 Type *ArgTy = I.getArgOperand(ArgI)->getType();
8756 if (!ArgTy->isVectorTy())
8758 NumElts += getTargetData()->getTypeAllocSize(ArgTy) / 8;
8760 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
8761 Info.ptrVal = I.getArgOperand(0);
8763 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
8764 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
8765 Info.vol = false; // volatile stores with NEON intrinsics not supported
8766 Info.readMem = false;
8767 Info.writeMem = true;
8770 case Intrinsic::arm_strexd: {
8771 Info.opc = ISD::INTRINSIC_W_CHAIN;
8772 Info.memVT = MVT::i64;
8773 Info.ptrVal = I.getArgOperand(2);
8777 Info.readMem = false;
8778 Info.writeMem = true;
8781 case Intrinsic::arm_ldrexd: {
8782 Info.opc = ISD::INTRINSIC_W_CHAIN;
8783 Info.memVT = MVT::i64;
8784 Info.ptrVal = I.getArgOperand(0);
8788 Info.readMem = true;
8789 Info.writeMem = false;