1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "arm-isel"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMISelLowering.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMPerfectShuffle.h"
22 #include "ARMRegisterInfo.h"
23 #include "ARMSubtarget.h"
24 #include "ARMTargetMachine.h"
25 #include "ARMTargetObjectFile.h"
26 #include "llvm/CallingConv.h"
27 #include "llvm/Constants.h"
28 #include "llvm/Function.h"
29 #include "llvm/GlobalValue.h"
30 #include "llvm/Instruction.h"
31 #include "llvm/Intrinsics.h"
32 #include "llvm/Type.h"
33 #include "llvm/CodeGen/CallingConvLower.h"
34 #include "llvm/CodeGen/MachineBasicBlock.h"
35 #include "llvm/CodeGen/MachineFrameInfo.h"
36 #include "llvm/CodeGen/MachineFunction.h"
37 #include "llvm/CodeGen/MachineInstrBuilder.h"
38 #include "llvm/CodeGen/MachineRegisterInfo.h"
39 #include "llvm/CodeGen/PseudoSourceValue.h"
40 #include "llvm/CodeGen/SelectionDAG.h"
41 #include "llvm/MC/MCSectionMachO.h"
42 #include "llvm/Target/TargetOptions.h"
43 #include "llvm/ADT/VectorExtras.h"
44 #include "llvm/ADT/Statistic.h"
45 #include "llvm/Support/CommandLine.h"
46 #include "llvm/Support/ErrorHandling.h"
47 #include "llvm/Support/MathExtras.h"
48 #include "llvm/Support/raw_ostream.h"
52 STATISTIC(NumTailCalls, "Number of tail calls");
54 // This option should go away when tail calls fully work.
56 EnableARMTailCalls("arm-tail-calls", cl::Hidden,
57 cl::desc("Generate tail calls (TEMPORARY OPTION)."),
60 // This option should go away when Machine LICM is smart enough to hoist a
63 EnableARMVDUPsplat("arm-vdup-splat", cl::Hidden,
64 cl::desc("Generate VDUP for integer constant splats (TEMPORARY OPTION)."),
68 EnableARMLongCalls("arm-long-calls", cl::Hidden,
69 cl::desc("Generate calls via indirect call instructions"),
73 ARMInterworking("arm-interworking", cl::Hidden,
74 cl::desc("Enable / disable ARM interworking (for debugging only)"),
78 EnableARMCodePlacement("arm-code-placement", cl::Hidden,
79 cl::desc("Enable code placement pass for ARM"),
82 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
83 CCValAssign::LocInfo &LocInfo,
84 ISD::ArgFlagsTy &ArgFlags,
86 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
87 CCValAssign::LocInfo &LocInfo,
88 ISD::ArgFlagsTy &ArgFlags,
90 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
91 CCValAssign::LocInfo &LocInfo,
92 ISD::ArgFlagsTy &ArgFlags,
94 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
95 CCValAssign::LocInfo &LocInfo,
96 ISD::ArgFlagsTy &ArgFlags,
99 void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
100 EVT PromotedBitwiseVT) {
101 if (VT != PromotedLdStVT) {
102 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
103 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
104 PromotedLdStVT.getSimpleVT());
106 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
107 AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
108 PromotedLdStVT.getSimpleVT());
111 EVT ElemTy = VT.getVectorElementType();
112 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
113 setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
114 if (ElemTy == MVT::i8 || ElemTy == MVT::i16)
115 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
116 if (ElemTy != MVT::i32) {
117 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
118 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand);
119 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand);
120 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand);
122 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
123 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
124 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
125 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Expand);
126 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
127 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
128 if (VT.isInteger()) {
129 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
130 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
131 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
132 setLoadExtAction(ISD::SEXTLOAD, VT.getSimpleVT(), Expand);
133 setLoadExtAction(ISD::ZEXTLOAD, VT.getSimpleVT(), Expand);
135 setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand);
137 // Promote all bit-wise operations.
138 if (VT.isInteger() && VT != PromotedBitwiseVT) {
139 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
140 AddPromotedToType (ISD::AND, VT.getSimpleVT(),
141 PromotedBitwiseVT.getSimpleVT());
142 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
143 AddPromotedToType (ISD::OR, VT.getSimpleVT(),
144 PromotedBitwiseVT.getSimpleVT());
145 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
146 AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
147 PromotedBitwiseVT.getSimpleVT());
150 // Neon does not support vector divide/remainder operations.
151 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
152 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
153 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand);
154 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
155 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
156 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
159 void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
160 addRegisterClass(VT, ARM::DPRRegisterClass);
161 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
164 void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
165 addRegisterClass(VT, ARM::QPRRegisterClass);
166 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
169 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
170 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
171 return new TargetLoweringObjectFileMachO();
173 return new ARMElfTargetObjectFile();
176 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
177 : TargetLowering(TM, createTLOF(TM)) {
178 Subtarget = &TM.getSubtarget<ARMSubtarget>();
179 RegInfo = TM.getRegisterInfo();
181 if (Subtarget->isTargetDarwin()) {
182 // Uses VFP for Thumb libfuncs if available.
183 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
184 // Single-precision floating-point arithmetic.
185 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
186 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
187 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
188 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
190 // Double-precision floating-point arithmetic.
191 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
192 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
193 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
194 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
196 // Single-precision comparisons.
197 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
198 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
199 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
200 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
201 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
202 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
203 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
204 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
206 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
207 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
208 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
209 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
210 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
211 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
212 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
213 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
215 // Double-precision comparisons.
216 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
217 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
218 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
219 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
220 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
221 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
222 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
223 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
225 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
226 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
227 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
228 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
229 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
230 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
231 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
232 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
234 // Floating-point to integer conversions.
235 // i64 conversions are done via library routines even when generating VFP
236 // instructions, so use the same ones.
237 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
238 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
239 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
240 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
242 // Conversions between floating types.
243 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
244 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
246 // Integer to floating-point conversions.
247 // i64 conversions are done via library routines even when generating VFP
248 // instructions, so use the same ones.
249 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
250 // e.g., __floatunsidf vs. __floatunssidfvfp.
251 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
252 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
253 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
254 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
258 // These libcalls are not available in 32-bit.
259 setLibcallName(RTLIB::SHL_I128, 0);
260 setLibcallName(RTLIB::SRL_I128, 0);
261 setLibcallName(RTLIB::SRA_I128, 0);
263 // Libcalls should use the AAPCS base standard ABI, even if hard float
264 // is in effect, as per the ARM RTABI specification, section 4.1.2.
265 if (Subtarget->isAAPCS_ABI()) {
266 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
267 setLibcallCallingConv(static_cast<RTLIB::Libcall>(i),
268 CallingConv::ARM_AAPCS);
272 if (Subtarget->isThumb1Only())
273 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
275 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
276 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
277 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
278 if (!Subtarget->isFPOnlySP())
279 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
281 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
284 if (Subtarget->hasNEON()) {
285 addDRTypeForNEON(MVT::v2f32);
286 addDRTypeForNEON(MVT::v8i8);
287 addDRTypeForNEON(MVT::v4i16);
288 addDRTypeForNEON(MVT::v2i32);
289 addDRTypeForNEON(MVT::v1i64);
291 addQRTypeForNEON(MVT::v4f32);
292 addQRTypeForNEON(MVT::v2f64);
293 addQRTypeForNEON(MVT::v16i8);
294 addQRTypeForNEON(MVT::v8i16);
295 addQRTypeForNEON(MVT::v4i32);
296 addQRTypeForNEON(MVT::v2i64);
298 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
299 // neither Neon nor VFP support any arithmetic operations on it.
300 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
301 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
302 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
303 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
304 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
305 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
306 setOperationAction(ISD::VSETCC, MVT::v2f64, Expand);
307 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
308 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
309 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
310 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
311 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
312 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
313 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
314 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
315 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
316 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
317 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
318 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
319 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
320 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
321 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
322 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
323 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
325 setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand);
327 // Neon does not support some operations on v1i64 and v2i64 types.
328 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
329 // Custom handling for some quad-vector types to detect VMULL.
330 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
331 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
332 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
333 setOperationAction(ISD::VSETCC, MVT::v1i64, Expand);
334 setOperationAction(ISD::VSETCC, MVT::v2i64, Expand);
336 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
337 setTargetDAGCombine(ISD::SHL);
338 setTargetDAGCombine(ISD::SRL);
339 setTargetDAGCombine(ISD::SRA);
340 setTargetDAGCombine(ISD::SIGN_EXTEND);
341 setTargetDAGCombine(ISD::ZERO_EXTEND);
342 setTargetDAGCombine(ISD::ANY_EXTEND);
343 setTargetDAGCombine(ISD::SELECT_CC);
346 computeRegisterProperties();
348 // ARM does not have f32 extending load.
349 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
351 // ARM does not have i1 sign extending load.
352 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
354 // ARM supports all 4 flavors of integer indexed load / store.
355 if (!Subtarget->isThumb1Only()) {
356 for (unsigned im = (unsigned)ISD::PRE_INC;
357 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
358 setIndexedLoadAction(im, MVT::i1, Legal);
359 setIndexedLoadAction(im, MVT::i8, Legal);
360 setIndexedLoadAction(im, MVT::i16, Legal);
361 setIndexedLoadAction(im, MVT::i32, Legal);
362 setIndexedStoreAction(im, MVT::i1, Legal);
363 setIndexedStoreAction(im, MVT::i8, Legal);
364 setIndexedStoreAction(im, MVT::i16, Legal);
365 setIndexedStoreAction(im, MVT::i32, Legal);
369 // i64 operation support.
370 if (Subtarget->isThumb1Only()) {
371 setOperationAction(ISD::MUL, MVT::i64, Expand);
372 setOperationAction(ISD::MULHU, MVT::i32, Expand);
373 setOperationAction(ISD::MULHS, MVT::i32, Expand);
374 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
375 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
377 setOperationAction(ISD::MUL, MVT::i64, Expand);
378 setOperationAction(ISD::MULHU, MVT::i32, Expand);
379 if (!Subtarget->hasV6Ops())
380 setOperationAction(ISD::MULHS, MVT::i32, Expand);
382 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
383 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
384 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
385 setOperationAction(ISD::SRL, MVT::i64, Custom);
386 setOperationAction(ISD::SRA, MVT::i64, Custom);
388 // ARM does not have ROTL.
389 setOperationAction(ISD::ROTL, MVT::i32, Expand);
390 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
391 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
392 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
393 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
395 // Only ARMv6 has BSWAP.
396 if (!Subtarget->hasV6Ops())
397 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
399 // These are expanded into libcalls.
400 if (!Subtarget->hasDivide()) {
401 // v7M has a hardware divider
402 setOperationAction(ISD::SDIV, MVT::i32, Expand);
403 setOperationAction(ISD::UDIV, MVT::i32, Expand);
405 setOperationAction(ISD::SREM, MVT::i32, Expand);
406 setOperationAction(ISD::UREM, MVT::i32, Expand);
407 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
408 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
410 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
411 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
412 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
413 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
414 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
416 setOperationAction(ISD::TRAP, MVT::Other, Legal);
418 // Use the default implementation.
419 setOperationAction(ISD::VASTART, MVT::Other, Custom);
420 setOperationAction(ISD::VAARG, MVT::Other, Expand);
421 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
422 setOperationAction(ISD::VAEND, MVT::Other, Expand);
423 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
424 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
425 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
426 // FIXME: Shouldn't need this, since no register is used, but the legalizer
427 // doesn't yet know how to not do that for SjLj.
428 setExceptionSelectorRegister(ARM::R0);
429 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
430 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
431 // the default expansion.
432 if (Subtarget->hasDataBarrier() ||
433 (Subtarget->hasV6Ops() && !Subtarget->isThumb1Only())) {
434 // membarrier needs custom lowering; the rest are legal and handled
436 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
438 // Set them all for expansion, which will force libcalls.
439 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
440 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Expand);
441 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Expand);
442 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
443 setOperationAction(ISD::ATOMIC_SWAP, MVT::i8, Expand);
444 setOperationAction(ISD::ATOMIC_SWAP, MVT::i16, Expand);
445 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
446 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i8, Expand);
447 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i16, Expand);
448 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
449 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Expand);
450 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Expand);
451 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
452 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i8, Expand);
453 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i16, Expand);
454 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
455 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i8, Expand);
456 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i16, Expand);
457 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
458 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i8, Expand);
459 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i16, Expand);
460 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
461 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i8, Expand);
462 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i16, Expand);
463 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
464 // Since the libcalls include locking, fold in the fences
465 setShouldFoldAtomicFences(true);
467 // 64-bit versions are always libcalls (for now)
468 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Expand);
469 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Expand);
470 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Expand);
471 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Expand);
472 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Expand);
473 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Expand);
474 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Expand);
475 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Expand);
477 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
478 if (!Subtarget->hasV6Ops()) {
479 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
480 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
482 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
484 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
485 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
486 // iff target supports vfp2.
487 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
488 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
491 // We want to custom lower some of our intrinsics.
492 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
493 if (Subtarget->isTargetDarwin()) {
494 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
495 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
498 setOperationAction(ISD::SETCC, MVT::i32, Expand);
499 setOperationAction(ISD::SETCC, MVT::f32, Expand);
500 setOperationAction(ISD::SETCC, MVT::f64, Expand);
501 setOperationAction(ISD::SELECT, MVT::i32, Custom);
502 setOperationAction(ISD::SELECT, MVT::f32, Custom);
503 setOperationAction(ISD::SELECT, MVT::f64, Custom);
504 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
505 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
506 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
508 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
509 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
510 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
511 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
512 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
514 // We don't support sin/cos/fmod/copysign/pow
515 setOperationAction(ISD::FSIN, MVT::f64, Expand);
516 setOperationAction(ISD::FSIN, MVT::f32, Expand);
517 setOperationAction(ISD::FCOS, MVT::f32, Expand);
518 setOperationAction(ISD::FCOS, MVT::f64, Expand);
519 setOperationAction(ISD::FREM, MVT::f64, Expand);
520 setOperationAction(ISD::FREM, MVT::f32, Expand);
521 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
522 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
523 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
525 setOperationAction(ISD::FPOW, MVT::f64, Expand);
526 setOperationAction(ISD::FPOW, MVT::f32, Expand);
528 // Various VFP goodness
529 if (!UseSoftFloat && !Subtarget->isThumb1Only()) {
530 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
531 if (Subtarget->hasVFP2()) {
532 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
533 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
534 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
535 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
537 // Special handling for half-precision FP.
538 if (!Subtarget->hasFP16()) {
539 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
540 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand);
544 // We have target-specific dag combine patterns for the following nodes:
545 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
546 setTargetDAGCombine(ISD::ADD);
547 setTargetDAGCombine(ISD::SUB);
548 setTargetDAGCombine(ISD::MUL);
550 if (Subtarget->hasV6T2Ops())
551 setTargetDAGCombine(ISD::OR);
553 setStackPointerRegisterToSaveRestore(ARM::SP);
555 if (UseSoftFloat || Subtarget->isThumb1Only() || !Subtarget->hasVFP2())
556 setSchedulingPreference(Sched::RegPressure);
558 setSchedulingPreference(Sched::Hybrid);
560 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
562 // On ARM arguments smaller than 4 bytes are extended, so all arguments
563 // are at least 4 bytes aligned.
564 setMinStackArgumentAlignment(4);
566 if (EnableARMCodePlacement)
567 benefitFromCodePlacementOpt = true;
570 std::pair<const TargetRegisterClass*, uint8_t>
571 ARMTargetLowering::findRepresentativeClass(EVT VT) const{
572 const TargetRegisterClass *RRC = 0;
574 switch (VT.getSimpleVT().SimpleTy) {
576 return TargetLowering::findRepresentativeClass(VT);
577 // Use DPR as representative register class for all floating point
578 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
579 // the cost is 1 for both f32 and f64.
580 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
581 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
582 RRC = ARM::DPRRegisterClass;
584 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
585 case MVT::v4f32: case MVT::v2f64:
586 RRC = ARM::DPRRegisterClass;
590 RRC = ARM::DPRRegisterClass;
594 RRC = ARM::DPRRegisterClass;
598 return std::make_pair(RRC, Cost);
601 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
604 case ARMISD::Wrapper: return "ARMISD::Wrapper";
605 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
606 case ARMISD::CALL: return "ARMISD::CALL";
607 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
608 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
609 case ARMISD::tCALL: return "ARMISD::tCALL";
610 case ARMISD::BRCOND: return "ARMISD::BRCOND";
611 case ARMISD::BR_JT: return "ARMISD::BR_JT";
612 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
613 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
614 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
615 case ARMISD::AND: return "ARMISD::AND";
616 case ARMISD::CMP: return "ARMISD::CMP";
617 case ARMISD::CMPZ: return "ARMISD::CMPZ";
618 case ARMISD::CMPFP: return "ARMISD::CMPFP";
619 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
620 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
621 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
622 case ARMISD::CMOV: return "ARMISD::CMOV";
623 case ARMISD::CNEG: return "ARMISD::CNEG";
625 case ARMISD::RBIT: return "ARMISD::RBIT";
627 case ARMISD::FTOSI: return "ARMISD::FTOSI";
628 case ARMISD::FTOUI: return "ARMISD::FTOUI";
629 case ARMISD::SITOF: return "ARMISD::SITOF";
630 case ARMISD::UITOF: return "ARMISD::UITOF";
632 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
633 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
634 case ARMISD::RRX: return "ARMISD::RRX";
636 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
637 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
639 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
640 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
642 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
644 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
646 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
648 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER";
649 case ARMISD::SYNCBARRIER: return "ARMISD::SYNCBARRIER";
651 case ARMISD::VCEQ: return "ARMISD::VCEQ";
652 case ARMISD::VCGE: return "ARMISD::VCGE";
653 case ARMISD::VCGEU: return "ARMISD::VCGEU";
654 case ARMISD::VCGT: return "ARMISD::VCGT";
655 case ARMISD::VCGTU: return "ARMISD::VCGTU";
656 case ARMISD::VTST: return "ARMISD::VTST";
658 case ARMISD::VSHL: return "ARMISD::VSHL";
659 case ARMISD::VSHRs: return "ARMISD::VSHRs";
660 case ARMISD::VSHRu: return "ARMISD::VSHRu";
661 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
662 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
663 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
664 case ARMISD::VSHRN: return "ARMISD::VSHRN";
665 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
666 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
667 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
668 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
669 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
670 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
671 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
672 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
673 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
674 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
675 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
676 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
677 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
678 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
679 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
680 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
681 case ARMISD::VDUP: return "ARMISD::VDUP";
682 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
683 case ARMISD::VEXT: return "ARMISD::VEXT";
684 case ARMISD::VREV64: return "ARMISD::VREV64";
685 case ARMISD::VREV32: return "ARMISD::VREV32";
686 case ARMISD::VREV16: return "ARMISD::VREV16";
687 case ARMISD::VZIP: return "ARMISD::VZIP";
688 case ARMISD::VUZP: return "ARMISD::VUZP";
689 case ARMISD::VTRN: return "ARMISD::VTRN";
690 case ARMISD::VMULLs: return "ARMISD::VMULLs";
691 case ARMISD::VMULLu: return "ARMISD::VMULLu";
692 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
693 case ARMISD::FMAX: return "ARMISD::FMAX";
694 case ARMISD::FMIN: return "ARMISD::FMIN";
695 case ARMISD::BFI: return "ARMISD::BFI";
699 /// getRegClassFor - Return the register class that should be used for the
700 /// specified value type.
701 TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const {
702 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
703 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
704 // load / store 4 to 8 consecutive D registers.
705 if (Subtarget->hasNEON()) {
706 if (VT == MVT::v4i64)
707 return ARM::QQPRRegisterClass;
708 else if (VT == MVT::v8i64)
709 return ARM::QQQQPRRegisterClass;
711 return TargetLowering::getRegClassFor(VT);
714 // Create a fast isel object.
716 ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
717 return ARM::createFastISel(funcInfo);
720 /// getFunctionAlignment - Return the Log2 alignment of this function.
721 unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
722 return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 1 : 2;
725 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
726 /// be used for loads / stores from the global.
727 unsigned ARMTargetLowering::getMaximalGlobalOffset() const {
728 return (Subtarget->isThumb1Only() ? 127 : 4095);
731 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
732 unsigned NumVals = N->getNumValues();
734 return Sched::RegPressure;
736 for (unsigned i = 0; i != NumVals; ++i) {
737 EVT VT = N->getValueType(i);
738 if (VT.isFloatingPoint() || VT.isVector())
739 return Sched::Latency;
742 if (!N->isMachineOpcode())
743 return Sched::RegPressure;
745 // Load are scheduled for latency even if there instruction itinerary
747 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
748 const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
750 return Sched::Latency;
752 const InstrItineraryData &Itins = getTargetMachine().getInstrItineraryData();
753 if (!Itins.isEmpty() && Itins.getStageLatency(TID.getSchedClass()) > 2)
754 return Sched::Latency;
755 return Sched::RegPressure;
759 ARMTargetLowering::getRegPressureLimit(const TargetRegisterClass *RC,
760 MachineFunction &MF) const {
761 switch (RC->getID()) {
764 case ARM::tGPRRegClassID:
765 return RegInfo->hasFP(MF) ? 4 : 5;
766 case ARM::GPRRegClassID: {
767 unsigned FP = RegInfo->hasFP(MF) ? 1 : 0;
768 return 10 - FP - (Subtarget->isR9Reserved() ? 1 : 0);
770 case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
771 case ARM::DPRRegClassID:
776 //===----------------------------------------------------------------------===//
778 //===----------------------------------------------------------------------===//
780 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
781 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
783 default: llvm_unreachable("Unknown condition code!");
784 case ISD::SETNE: return ARMCC::NE;
785 case ISD::SETEQ: return ARMCC::EQ;
786 case ISD::SETGT: return ARMCC::GT;
787 case ISD::SETGE: return ARMCC::GE;
788 case ISD::SETLT: return ARMCC::LT;
789 case ISD::SETLE: return ARMCC::LE;
790 case ISD::SETUGT: return ARMCC::HI;
791 case ISD::SETUGE: return ARMCC::HS;
792 case ISD::SETULT: return ARMCC::LO;
793 case ISD::SETULE: return ARMCC::LS;
797 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
798 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
799 ARMCC::CondCodes &CondCode2) {
800 CondCode2 = ARMCC::AL;
802 default: llvm_unreachable("Unknown FP condition!");
804 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
806 case ISD::SETOGT: CondCode = ARMCC::GT; break;
808 case ISD::SETOGE: CondCode = ARMCC::GE; break;
809 case ISD::SETOLT: CondCode = ARMCC::MI; break;
810 case ISD::SETOLE: CondCode = ARMCC::LS; break;
811 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
812 case ISD::SETO: CondCode = ARMCC::VC; break;
813 case ISD::SETUO: CondCode = ARMCC::VS; break;
814 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
815 case ISD::SETUGT: CondCode = ARMCC::HI; break;
816 case ISD::SETUGE: CondCode = ARMCC::PL; break;
818 case ISD::SETULT: CondCode = ARMCC::LT; break;
820 case ISD::SETULE: CondCode = ARMCC::LE; break;
822 case ISD::SETUNE: CondCode = ARMCC::NE; break;
826 //===----------------------------------------------------------------------===//
827 // Calling Convention Implementation
828 //===----------------------------------------------------------------------===//
830 #include "ARMGenCallingConv.inc"
832 // APCS f64 is in register pairs, possibly split to stack
833 static bool f64AssignAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
834 CCValAssign::LocInfo &LocInfo,
835 CCState &State, bool CanFail) {
836 static const unsigned RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
838 // Try to get the first register.
839 if (unsigned Reg = State.AllocateReg(RegList, 4))
840 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
842 // For the 2nd half of a v2f64, do not fail.
846 // Put the whole thing on the stack.
847 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
848 State.AllocateStack(8, 4),
853 // Try to get the second register.
854 if (unsigned Reg = State.AllocateReg(RegList, 4))
855 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
857 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
858 State.AllocateStack(4, 4),
863 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
864 CCValAssign::LocInfo &LocInfo,
865 ISD::ArgFlagsTy &ArgFlags,
867 if (!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
869 if (LocVT == MVT::v2f64 &&
870 !f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
872 return true; // we handled it
875 // AAPCS f64 is in aligned register pairs
876 static bool f64AssignAAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
877 CCValAssign::LocInfo &LocInfo,
878 CCState &State, bool CanFail) {
879 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
880 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
881 static const unsigned ShadowRegList[] = { ARM::R0, ARM::R1 };
883 unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList, 2);
885 // For the 2nd half of a v2f64, do not just fail.
889 // Put the whole thing on the stack.
890 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
891 State.AllocateStack(8, 8),
897 for (i = 0; i < 2; ++i)
898 if (HiRegList[i] == Reg)
901 unsigned T = State.AllocateReg(LoRegList[i]);
903 assert(T == LoRegList[i] && "Could not allocate register");
905 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
906 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
911 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
912 CCValAssign::LocInfo &LocInfo,
913 ISD::ArgFlagsTy &ArgFlags,
915 if (!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
917 if (LocVT == MVT::v2f64 &&
918 !f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
920 return true; // we handled it
923 static bool f64RetAssign(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
924 CCValAssign::LocInfo &LocInfo, CCState &State) {
925 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
926 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
928 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
930 return false; // we didn't handle it
933 for (i = 0; i < 2; ++i)
934 if (HiRegList[i] == Reg)
937 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
938 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
943 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
944 CCValAssign::LocInfo &LocInfo,
945 ISD::ArgFlagsTy &ArgFlags,
947 if (!f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
949 if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
951 return true; // we handled it
954 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
955 CCValAssign::LocInfo &LocInfo,
956 ISD::ArgFlagsTy &ArgFlags,
958 return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags,
962 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
963 /// given CallingConvention value.
964 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
966 bool isVarArg) const {
969 llvm_unreachable("Unsupported calling convention");
971 case CallingConv::Fast:
972 // Use target triple & subtarget features to do actual dispatch.
973 if (Subtarget->isAAPCS_ABI()) {
974 if (Subtarget->hasVFP2() &&
975 FloatABIType == FloatABI::Hard && !isVarArg)
976 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
978 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
980 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
981 case CallingConv::ARM_AAPCS_VFP:
982 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
983 case CallingConv::ARM_AAPCS:
984 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
985 case CallingConv::ARM_APCS:
986 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
990 /// LowerCallResult - Lower the result values of a call into the
991 /// appropriate copies out of appropriate physical registers.
993 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
994 CallingConv::ID CallConv, bool isVarArg,
995 const SmallVectorImpl<ISD::InputArg> &Ins,
996 DebugLoc dl, SelectionDAG &DAG,
997 SmallVectorImpl<SDValue> &InVals) const {
999 // Assign locations to each value returned by this call.
1000 SmallVector<CCValAssign, 16> RVLocs;
1001 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1002 RVLocs, *DAG.getContext());
1003 CCInfo.AnalyzeCallResult(Ins,
1004 CCAssignFnForNode(CallConv, /* Return*/ true,
1007 // Copy all of the result registers out of their specified physreg.
1008 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1009 CCValAssign VA = RVLocs[i];
1012 if (VA.needsCustom()) {
1013 // Handle f64 or half of a v2f64.
1014 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1016 Chain = Lo.getValue(1);
1017 InFlag = Lo.getValue(2);
1018 VA = RVLocs[++i]; // skip ahead to next loc
1019 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1021 Chain = Hi.getValue(1);
1022 InFlag = Hi.getValue(2);
1023 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1025 if (VA.getLocVT() == MVT::v2f64) {
1026 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1027 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1028 DAG.getConstant(0, MVT::i32));
1030 VA = RVLocs[++i]; // skip ahead to next loc
1031 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1032 Chain = Lo.getValue(1);
1033 InFlag = Lo.getValue(2);
1034 VA = RVLocs[++i]; // skip ahead to next loc
1035 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1036 Chain = Hi.getValue(1);
1037 InFlag = Hi.getValue(2);
1038 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1039 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1040 DAG.getConstant(1, MVT::i32));
1043 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1045 Chain = Val.getValue(1);
1046 InFlag = Val.getValue(2);
1049 switch (VA.getLocInfo()) {
1050 default: llvm_unreachable("Unknown loc info!");
1051 case CCValAssign::Full: break;
1052 case CCValAssign::BCvt:
1053 Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val);
1057 InVals.push_back(Val);
1063 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1064 /// by "Src" to address "Dst" of size "Size". Alignment information is
1065 /// specified by the specific parameter attribute. The copy will be passed as
1066 /// a byval function parameter.
1067 /// Sometimes what we are copying is the end of a larger object, the part that
1068 /// does not fit in registers.
1070 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1071 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1073 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1074 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1075 /*isVolatile=*/false, /*AlwaysInline=*/false,
1079 /// LowerMemOpCallTo - Store the argument to the stack.
1081 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
1082 SDValue StackPtr, SDValue Arg,
1083 DebugLoc dl, SelectionDAG &DAG,
1084 const CCValAssign &VA,
1085 ISD::ArgFlagsTy Flags) const {
1086 unsigned LocMemOffset = VA.getLocMemOffset();
1087 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1088 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1089 if (Flags.isByVal()) {
1090 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1092 return DAG.getStore(Chain, dl, Arg, PtrOff,
1093 PseudoSourceValue::getStack(), LocMemOffset,
1097 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
1098 SDValue Chain, SDValue &Arg,
1099 RegsToPassVector &RegsToPass,
1100 CCValAssign &VA, CCValAssign &NextVA,
1102 SmallVector<SDValue, 8> &MemOpChains,
1103 ISD::ArgFlagsTy Flags) const {
1105 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1106 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1107 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
1109 if (NextVA.isRegLoc())
1110 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
1112 assert(NextVA.isMemLoc());
1113 if (StackPtr.getNode() == 0)
1114 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1116 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
1122 /// LowerCall - Lowering a call into a callseq_start <-
1123 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1126 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1127 CallingConv::ID CallConv, bool isVarArg,
1129 const SmallVectorImpl<ISD::OutputArg> &Outs,
1130 const SmallVectorImpl<SDValue> &OutVals,
1131 const SmallVectorImpl<ISD::InputArg> &Ins,
1132 DebugLoc dl, SelectionDAG &DAG,
1133 SmallVectorImpl<SDValue> &InVals) const {
1134 MachineFunction &MF = DAG.getMachineFunction();
1135 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1136 bool IsSibCall = false;
1137 // Temporarily disable tail calls so things don't break.
1138 if (!EnableARMTailCalls)
1141 // Check if it's really possible to do a tail call.
1142 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1143 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1144 Outs, OutVals, Ins, DAG);
1145 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1146 // detected sibcalls.
1153 // Analyze operands of the call, assigning locations to each operand.
1154 SmallVector<CCValAssign, 16> ArgLocs;
1155 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1157 CCInfo.AnalyzeCallOperands(Outs,
1158 CCAssignFnForNode(CallConv, /* Return*/ false,
1161 // Get a count of how many bytes are to be pushed on the stack.
1162 unsigned NumBytes = CCInfo.getNextStackOffset();
1164 // For tail calls, memory operands are available in our caller's stack.
1168 // Adjust the stack pointer for the new arguments...
1169 // These operations are automatically eliminated by the prolog/epilog pass
1171 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1173 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1175 RegsToPassVector RegsToPass;
1176 SmallVector<SDValue, 8> MemOpChains;
1178 // Walk the register/memloc assignments, inserting copies/loads. In the case
1179 // of tail call optimization, arguments are handled later.
1180 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1182 ++i, ++realArgIdx) {
1183 CCValAssign &VA = ArgLocs[i];
1184 SDValue Arg = OutVals[realArgIdx];
1185 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1187 // Promote the value if needed.
1188 switch (VA.getLocInfo()) {
1189 default: llvm_unreachable("Unknown loc info!");
1190 case CCValAssign::Full: break;
1191 case CCValAssign::SExt:
1192 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1194 case CCValAssign::ZExt:
1195 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1197 case CCValAssign::AExt:
1198 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1200 case CCValAssign::BCvt:
1201 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1205 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1206 if (VA.needsCustom()) {
1207 if (VA.getLocVT() == MVT::v2f64) {
1208 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1209 DAG.getConstant(0, MVT::i32));
1210 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1211 DAG.getConstant(1, MVT::i32));
1213 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1214 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1216 VA = ArgLocs[++i]; // skip ahead to next loc
1217 if (VA.isRegLoc()) {
1218 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1219 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1221 assert(VA.isMemLoc());
1223 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1224 dl, DAG, VA, Flags));
1227 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1228 StackPtr, MemOpChains, Flags);
1230 } else if (VA.isRegLoc()) {
1231 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1232 } else if (!IsSibCall) {
1233 assert(VA.isMemLoc());
1235 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1236 dl, DAG, VA, Flags));
1240 if (!MemOpChains.empty())
1241 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1242 &MemOpChains[0], MemOpChains.size());
1244 // Build a sequence of copy-to-reg nodes chained together with token chain
1245 // and flag operands which copy the outgoing args into the appropriate regs.
1247 // Tail call byval lowering might overwrite argument registers so in case of
1248 // tail call optimization the copies to registers are lowered later.
1250 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1251 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1252 RegsToPass[i].second, InFlag);
1253 InFlag = Chain.getValue(1);
1256 // For tail calls lower the arguments to the 'real' stack slot.
1258 // Force all the incoming stack arguments to be loaded from the stack
1259 // before any new outgoing arguments are stored to the stack, because the
1260 // outgoing stack slots may alias the incoming argument stack slots, and
1261 // the alias isn't otherwise explicit. This is slightly more conservative
1262 // than necessary, because it means that each store effectively depends
1263 // on every argument instead of just those arguments it would clobber.
1265 // Do not flag preceeding copytoreg stuff together with the following stuff.
1267 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1268 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1269 RegsToPass[i].second, InFlag);
1270 InFlag = Chain.getValue(1);
1275 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1276 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1277 // node so that legalize doesn't hack it.
1278 bool isDirect = false;
1279 bool isARMFunc = false;
1280 bool isLocalARMFunc = false;
1281 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1283 if (EnableARMLongCalls) {
1284 assert (getTargetMachine().getRelocationModel() == Reloc::Static
1285 && "long-calls with non-static relocation model!");
1286 // Handle a global address or an external symbol. If it's not one of
1287 // those, the target's already in a register, so we don't need to do
1289 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1290 const GlobalValue *GV = G->getGlobal();
1291 // Create a constant pool entry for the callee address
1292 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1293 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1296 // Get the address of the callee into a register
1297 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1298 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1299 Callee = DAG.getLoad(getPointerTy(), dl,
1300 DAG.getEntryNode(), CPAddr,
1301 PseudoSourceValue::getConstantPool(), 0,
1303 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1304 const char *Sym = S->getSymbol();
1306 // Create a constant pool entry for the callee address
1307 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1308 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1309 Sym, ARMPCLabelIndex, 0);
1310 // Get the address of the callee into a register
1311 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1312 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1313 Callee = DAG.getLoad(getPointerTy(), dl,
1314 DAG.getEntryNode(), CPAddr,
1315 PseudoSourceValue::getConstantPool(), 0,
1318 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1319 const GlobalValue *GV = G->getGlobal();
1321 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1322 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
1323 getTargetMachine().getRelocationModel() != Reloc::Static;
1324 isARMFunc = !Subtarget->isThumb() || isStub;
1325 // ARM call to a local ARM function is predicable.
1326 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
1327 // tBX takes a register source operand.
1328 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1329 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1330 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1333 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1334 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1335 Callee = DAG.getLoad(getPointerTy(), dl,
1336 DAG.getEntryNode(), CPAddr,
1337 PseudoSourceValue::getConstantPool(), 0,
1339 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1340 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1341 getPointerTy(), Callee, PICLabel);
1343 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy());
1344 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1346 bool isStub = Subtarget->isTargetDarwin() &&
1347 getTargetMachine().getRelocationModel() != Reloc::Static;
1348 isARMFunc = !Subtarget->isThumb() || isStub;
1349 // tBX takes a register source operand.
1350 const char *Sym = S->getSymbol();
1351 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1352 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1353 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1354 Sym, ARMPCLabelIndex, 4);
1355 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1356 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1357 Callee = DAG.getLoad(getPointerTy(), dl,
1358 DAG.getEntryNode(), CPAddr,
1359 PseudoSourceValue::getConstantPool(), 0,
1361 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1362 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1363 getPointerTy(), Callee, PICLabel);
1365 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
1368 // FIXME: handle tail calls differently.
1370 if (Subtarget->isThumb()) {
1371 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1372 CallOpc = ARMISD::CALL_NOLINK;
1374 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1376 CallOpc = (isDirect || Subtarget->hasV5TOps())
1377 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
1378 : ARMISD::CALL_NOLINK;
1381 std::vector<SDValue> Ops;
1382 Ops.push_back(Chain);
1383 Ops.push_back(Callee);
1385 // Add argument registers to the end of the list so that they are known live
1387 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1388 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1389 RegsToPass[i].second.getValueType()));
1391 if (InFlag.getNode())
1392 Ops.push_back(InFlag);
1394 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1396 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
1398 // Returns a chain and a flag for retval copy to use.
1399 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
1400 InFlag = Chain.getValue(1);
1402 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1403 DAG.getIntPtrConstant(0, true), InFlag);
1405 InFlag = Chain.getValue(1);
1407 // Handle result values, copying them out of physregs into vregs that we
1409 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1413 /// MatchingStackOffset - Return true if the given stack call argument is
1414 /// already available in the same position (relatively) of the caller's
1415 /// incoming argument stack.
1417 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1418 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1419 const ARMInstrInfo *TII) {
1420 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
1422 if (Arg.getOpcode() == ISD::CopyFromReg) {
1423 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
1424 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR))
1426 MachineInstr *Def = MRI->getVRegDef(VR);
1429 if (!Flags.isByVal()) {
1430 if (!TII->isLoadFromStackSlot(Def, FI))
1435 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
1436 if (Flags.isByVal())
1437 // ByVal argument is passed in as a pointer but it's now being
1438 // dereferenced. e.g.
1439 // define @foo(%struct.X* %A) {
1440 // tail call @bar(%struct.X* byval %A)
1443 SDValue Ptr = Ld->getBasePtr();
1444 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
1447 FI = FINode->getIndex();
1451 assert(FI != INT_MAX);
1452 if (!MFI->isFixedObjectIndex(FI))
1454 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
1457 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1458 /// for tail call optimization. Targets which want to do tail call
1459 /// optimization should implement this function.
1461 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1462 CallingConv::ID CalleeCC,
1464 bool isCalleeStructRet,
1465 bool isCallerStructRet,
1466 const SmallVectorImpl<ISD::OutputArg> &Outs,
1467 const SmallVectorImpl<SDValue> &OutVals,
1468 const SmallVectorImpl<ISD::InputArg> &Ins,
1469 SelectionDAG& DAG) const {
1470 const Function *CallerF = DAG.getMachineFunction().getFunction();
1471 CallingConv::ID CallerCC = CallerF->getCallingConv();
1472 bool CCMatch = CallerCC == CalleeCC;
1474 // Look for obvious safe cases to perform tail call optimization that do not
1475 // require ABI changes. This is what gcc calls sibcall.
1477 // Do not sibcall optimize vararg calls unless the call site is not passing
1479 if (isVarArg && !Outs.empty())
1482 // Also avoid sibcall optimization if either caller or callee uses struct
1483 // return semantics.
1484 if (isCalleeStructRet || isCallerStructRet)
1487 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
1488 // emitEpilogue is not ready for them.
1489 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
1490 // LR. This means if we need to reload LR, it takes an extra instructions,
1491 // which outweighs the value of the tail call; but here we don't know yet
1492 // whether LR is going to be used. Probably the right approach is to
1493 // generate the tail call here and turn it back into CALL/RET in
1494 // emitEpilogue if LR is used.
1495 if (Subtarget->isThumb1Only())
1498 // For the moment, we can only do this to functions defined in this
1499 // compilation, or to indirect calls. A Thumb B to an ARM function,
1500 // or vice versa, is not easily fixed up in the linker unlike BL.
1501 // (We could do this by loading the address of the callee into a register;
1502 // that is an extra instruction over the direct call and burns a register
1503 // as well, so is not likely to be a win.)
1505 // It might be safe to remove this restriction on non-Darwin.
1507 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
1508 // but we need to make sure there are enough registers; the only valid
1509 // registers are the 4 used for parameters. We don't currently do this
1511 if (isa<ExternalSymbolSDNode>(Callee))
1514 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1515 const GlobalValue *GV = G->getGlobal();
1516 if (GV->isDeclaration() || GV->isWeakForLinker())
1520 // If the calling conventions do not match, then we'd better make sure the
1521 // results are returned in the same way as what the caller expects.
1523 SmallVector<CCValAssign, 16> RVLocs1;
1524 CCState CCInfo1(CalleeCC, false, getTargetMachine(),
1525 RVLocs1, *DAG.getContext());
1526 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
1528 SmallVector<CCValAssign, 16> RVLocs2;
1529 CCState CCInfo2(CallerCC, false, getTargetMachine(),
1530 RVLocs2, *DAG.getContext());
1531 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
1533 if (RVLocs1.size() != RVLocs2.size())
1535 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
1536 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
1538 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
1540 if (RVLocs1[i].isRegLoc()) {
1541 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
1544 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
1550 // If the callee takes no arguments then go on to check the results of the
1552 if (!Outs.empty()) {
1553 // Check if stack adjustment is needed. For now, do not do this if any
1554 // argument is passed on the stack.
1555 SmallVector<CCValAssign, 16> ArgLocs;
1556 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
1557 ArgLocs, *DAG.getContext());
1558 CCInfo.AnalyzeCallOperands(Outs,
1559 CCAssignFnForNode(CalleeCC, false, isVarArg));
1560 if (CCInfo.getNextStackOffset()) {
1561 MachineFunction &MF = DAG.getMachineFunction();
1563 // Check if the arguments are already laid out in the right way as
1564 // the caller's fixed stack objects.
1565 MachineFrameInfo *MFI = MF.getFrameInfo();
1566 const MachineRegisterInfo *MRI = &MF.getRegInfo();
1567 const ARMInstrInfo *TII =
1568 ((ARMTargetMachine&)getTargetMachine()).getInstrInfo();
1569 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1571 ++i, ++realArgIdx) {
1572 CCValAssign &VA = ArgLocs[i];
1573 EVT RegVT = VA.getLocVT();
1574 SDValue Arg = OutVals[realArgIdx];
1575 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1576 if (VA.getLocInfo() == CCValAssign::Indirect)
1578 if (VA.needsCustom()) {
1579 // f64 and vector types are split into multiple registers or
1580 // register/stack-slot combinations. The types will not match
1581 // the registers; give up on memory f64 refs until we figure
1582 // out what to do about this.
1585 if (!ArgLocs[++i].isRegLoc())
1587 if (RegVT == MVT::v2f64) {
1588 if (!ArgLocs[++i].isRegLoc())
1590 if (!ArgLocs[++i].isRegLoc())
1593 } else if (!VA.isRegLoc()) {
1594 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
1606 ARMTargetLowering::LowerReturn(SDValue Chain,
1607 CallingConv::ID CallConv, bool isVarArg,
1608 const SmallVectorImpl<ISD::OutputArg> &Outs,
1609 const SmallVectorImpl<SDValue> &OutVals,
1610 DebugLoc dl, SelectionDAG &DAG) const {
1612 // CCValAssign - represent the assignment of the return value to a location.
1613 SmallVector<CCValAssign, 16> RVLocs;
1615 // CCState - Info about the registers and stack slots.
1616 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
1619 // Analyze outgoing return values.
1620 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1623 // If this is the first return lowered for this function, add
1624 // the regs to the liveout set for the function.
1625 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1626 for (unsigned i = 0; i != RVLocs.size(); ++i)
1627 if (RVLocs[i].isRegLoc())
1628 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1633 // Copy the result values into the output registers.
1634 for (unsigned i = 0, realRVLocIdx = 0;
1636 ++i, ++realRVLocIdx) {
1637 CCValAssign &VA = RVLocs[i];
1638 assert(VA.isRegLoc() && "Can only return in registers!");
1640 SDValue Arg = OutVals[realRVLocIdx];
1642 switch (VA.getLocInfo()) {
1643 default: llvm_unreachable("Unknown loc info!");
1644 case CCValAssign::Full: break;
1645 case CCValAssign::BCvt:
1646 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1650 if (VA.needsCustom()) {
1651 if (VA.getLocVT() == MVT::v2f64) {
1652 // Extract the first half and return it in two registers.
1653 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1654 DAG.getConstant(0, MVT::i32));
1655 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
1656 DAG.getVTList(MVT::i32, MVT::i32), Half);
1658 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1659 Flag = Chain.getValue(1);
1660 VA = RVLocs[++i]; // skip ahead to next loc
1661 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1662 HalfGPRs.getValue(1), Flag);
1663 Flag = Chain.getValue(1);
1664 VA = RVLocs[++i]; // skip ahead to next loc
1666 // Extract the 2nd half and fall through to handle it as an f64 value.
1667 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1668 DAG.getConstant(1, MVT::i32));
1670 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1672 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1673 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1674 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1675 Flag = Chain.getValue(1);
1676 VA = RVLocs[++i]; // skip ahead to next loc
1677 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1680 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1682 // Guarantee that all emitted copies are
1683 // stuck together, avoiding something bad.
1684 Flag = Chain.getValue(1);
1689 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1691 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1696 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1697 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1698 // one of the above mentioned nodes. It has to be wrapped because otherwise
1699 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1700 // be used to form addressing mode. These wrapped nodes will be selected
1702 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1703 EVT PtrVT = Op.getValueType();
1704 // FIXME there is no actual debug info here
1705 DebugLoc dl = Op.getDebugLoc();
1706 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1708 if (CP->isMachineConstantPoolEntry())
1709 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1710 CP->getAlignment());
1712 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1713 CP->getAlignment());
1714 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1717 unsigned ARMTargetLowering::getJumpTableEncoding() const {
1718 return MachineJumpTableInfo::EK_Inline;
1721 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
1722 SelectionDAG &DAG) const {
1723 MachineFunction &MF = DAG.getMachineFunction();
1724 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1725 unsigned ARMPCLabelIndex = 0;
1726 DebugLoc DL = Op.getDebugLoc();
1727 EVT PtrVT = getPointerTy();
1728 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1729 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1731 if (RelocM == Reloc::Static) {
1732 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
1734 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1735 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1736 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(BA, ARMPCLabelIndex,
1737 ARMCP::CPBlockAddress,
1739 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1741 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
1742 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
1743 PseudoSourceValue::getConstantPool(), 0,
1745 if (RelocM == Reloc::Static)
1747 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1748 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
1751 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
1753 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1754 SelectionDAG &DAG) const {
1755 DebugLoc dl = GA->getDebugLoc();
1756 EVT PtrVT = getPointerTy();
1757 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1758 MachineFunction &MF = DAG.getMachineFunction();
1759 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1760 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1761 ARMConstantPoolValue *CPV =
1762 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1763 ARMCP::CPValue, PCAdj, "tlsgd", true);
1764 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1765 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
1766 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
1767 PseudoSourceValue::getConstantPool(), 0,
1769 SDValue Chain = Argument.getValue(1);
1771 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1772 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
1774 // call __tls_get_addr.
1777 Entry.Node = Argument;
1778 Entry.Ty = (const Type *) Type::getInt32Ty(*DAG.getContext());
1779 Args.push_back(Entry);
1780 // FIXME: is there useful debug info available here?
1781 std::pair<SDValue, SDValue> CallResult =
1782 LowerCallTo(Chain, (const Type *) Type::getInt32Ty(*DAG.getContext()),
1783 false, false, false, false,
1784 0, CallingConv::C, false, /*isReturnValueUsed=*/true,
1785 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
1786 return CallResult.first;
1789 // Lower ISD::GlobalTLSAddress using the "initial exec" or
1790 // "local exec" model.
1792 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
1793 SelectionDAG &DAG) const {
1794 const GlobalValue *GV = GA->getGlobal();
1795 DebugLoc dl = GA->getDebugLoc();
1797 SDValue Chain = DAG.getEntryNode();
1798 EVT PtrVT = getPointerTy();
1799 // Get the Thread Pointer
1800 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1802 if (GV->isDeclaration()) {
1803 MachineFunction &MF = DAG.getMachineFunction();
1804 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1805 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1806 // Initial exec model.
1807 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1808 ARMConstantPoolValue *CPV =
1809 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1810 ARMCP::CPValue, PCAdj, "gottpoff", true);
1811 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1812 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1813 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1814 PseudoSourceValue::getConstantPool(), 0,
1816 Chain = Offset.getValue(1);
1818 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1819 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
1821 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1822 PseudoSourceValue::getConstantPool(), 0,
1826 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, "tpoff");
1827 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1828 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1829 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1830 PseudoSourceValue::getConstantPool(), 0,
1834 // The address of the thread local variable is the add of the thread
1835 // pointer with the offset of the variable.
1836 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
1840 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
1841 // TODO: implement the "local dynamic" model
1842 assert(Subtarget->isTargetELF() &&
1843 "TLS not implemented for non-ELF targets");
1844 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1845 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
1846 // otherwise use the "Local Exec" TLS Model
1847 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
1848 return LowerToTLSGeneralDynamicModel(GA, DAG);
1850 return LowerToTLSExecModels(GA, DAG);
1853 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
1854 SelectionDAG &DAG) const {
1855 EVT PtrVT = getPointerTy();
1856 DebugLoc dl = Op.getDebugLoc();
1857 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1858 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1859 if (RelocM == Reloc::PIC_) {
1860 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
1861 ARMConstantPoolValue *CPV =
1862 new ARMConstantPoolValue(GV, UseGOTOFF ? "GOTOFF" : "GOT");
1863 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1864 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1865 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1867 PseudoSourceValue::getConstantPool(), 0,
1869 SDValue Chain = Result.getValue(1);
1870 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1871 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
1873 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
1874 PseudoSourceValue::getGOT(), 0,
1878 // If we have T2 ops, we can materialize the address directly via movt/movw
1879 // pair. This is always cheaper.
1880 if (Subtarget->useMovt()) {
1881 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
1882 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
1884 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1885 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1886 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1887 PseudoSourceValue::getConstantPool(), 0,
1893 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
1894 SelectionDAG &DAG) const {
1895 MachineFunction &MF = DAG.getMachineFunction();
1896 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1897 unsigned ARMPCLabelIndex = 0;
1898 EVT PtrVT = getPointerTy();
1899 DebugLoc dl = Op.getDebugLoc();
1900 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1901 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1903 if (RelocM == Reloc::Static)
1904 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1906 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1907 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8);
1908 ARMConstantPoolValue *CPV =
1909 new ARMConstantPoolValue(GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj);
1910 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1912 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1914 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1915 PseudoSourceValue::getConstantPool(), 0,
1917 SDValue Chain = Result.getValue(1);
1919 if (RelocM == Reloc::PIC_) {
1920 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1921 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1924 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
1925 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
1926 PseudoSourceValue::getGOT(), 0,
1932 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
1933 SelectionDAG &DAG) const {
1934 assert(Subtarget->isTargetELF() &&
1935 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
1936 MachineFunction &MF = DAG.getMachineFunction();
1937 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1938 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1939 EVT PtrVT = getPointerTy();
1940 DebugLoc dl = Op.getDebugLoc();
1941 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1942 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1943 "_GLOBAL_OFFSET_TABLE_",
1944 ARMPCLabelIndex, PCAdj);
1945 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1946 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1947 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1948 PseudoSourceValue::getConstantPool(), 0,
1950 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1951 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1955 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
1956 DebugLoc dl = Op.getDebugLoc();
1957 SDValue Val = DAG.getConstant(0, MVT::i32);
1958 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(0),
1959 Op.getOperand(1), Val);
1963 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
1964 DebugLoc dl = Op.getDebugLoc();
1965 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
1966 Op.getOperand(1), DAG.getConstant(0, MVT::i32));
1970 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
1971 const ARMSubtarget *Subtarget) const {
1972 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1973 DebugLoc dl = Op.getDebugLoc();
1975 default: return SDValue(); // Don't custom lower most intrinsics.
1976 case Intrinsic::arm_thread_pointer: {
1977 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1978 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1980 case Intrinsic::eh_sjlj_lsda: {
1981 MachineFunction &MF = DAG.getMachineFunction();
1982 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1983 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1984 EVT PtrVT = getPointerTy();
1985 DebugLoc dl = Op.getDebugLoc();
1986 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1988 unsigned PCAdj = (RelocM != Reloc::PIC_)
1989 ? 0 : (Subtarget->isThumb() ? 4 : 8);
1990 ARMConstantPoolValue *CPV =
1991 new ARMConstantPoolValue(MF.getFunction(), ARMPCLabelIndex,
1992 ARMCP::CPLSDA, PCAdj);
1993 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1994 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1996 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1997 PseudoSourceValue::getConstantPool(), 0,
2000 if (RelocM == Reloc::PIC_) {
2001 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2002 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2009 static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG,
2010 const ARMSubtarget *Subtarget) {
2011 DebugLoc dl = Op.getDebugLoc();
2012 SDValue Op5 = Op.getOperand(5);
2013 unsigned isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue();
2014 // Some subtargets which have dmb and dsb instructions can handle barriers
2015 // directly. Some ARMv6 cpus can support them with the help of mcr
2016 // instruction. Thumb1 and pre-v6 ARM mode use a libcall instead and should
2018 unsigned Opc = isDeviceBarrier ? ARMISD::SYNCBARRIER : ARMISD::MEMBARRIER;
2019 if (Subtarget->hasDataBarrier())
2020 return DAG.getNode(Opc, dl, MVT::Other, Op.getOperand(0));
2022 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb1Only() &&
2023 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!");
2024 return DAG.getNode(Opc, dl, MVT::Other, Op.getOperand(0),
2025 DAG.getConstant(0, MVT::i32));
2029 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
2030 MachineFunction &MF = DAG.getMachineFunction();
2031 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
2033 // vastart just stores the address of the VarArgsFrameIndex slot into the
2034 // memory location argument.
2035 DebugLoc dl = Op.getDebugLoc();
2036 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2037 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2038 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2039 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0,
2044 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
2045 SDValue &Root, SelectionDAG &DAG,
2046 DebugLoc dl) const {
2047 MachineFunction &MF = DAG.getMachineFunction();
2048 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2050 TargetRegisterClass *RC;
2051 if (AFI->isThumb1OnlyFunction())
2052 RC = ARM::tGPRRegisterClass;
2054 RC = ARM::GPRRegisterClass;
2056 // Transform the arguments stored in physical registers into virtual ones.
2057 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2058 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2061 if (NextVA.isMemLoc()) {
2062 MachineFrameInfo *MFI = MF.getFrameInfo();
2063 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
2065 // Create load node to retrieve arguments from the stack.
2066 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2067 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
2068 PseudoSourceValue::getFixedStack(FI), 0,
2071 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2072 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2075 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
2079 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
2080 CallingConv::ID CallConv, bool isVarArg,
2081 const SmallVectorImpl<ISD::InputArg>
2083 DebugLoc dl, SelectionDAG &DAG,
2084 SmallVectorImpl<SDValue> &InVals)
2087 MachineFunction &MF = DAG.getMachineFunction();
2088 MachineFrameInfo *MFI = MF.getFrameInfo();
2090 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2092 // Assign locations to all of the incoming arguments.
2093 SmallVector<CCValAssign, 16> ArgLocs;
2094 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
2096 CCInfo.AnalyzeFormalArguments(Ins,
2097 CCAssignFnForNode(CallConv, /* Return*/ false,
2100 SmallVector<SDValue, 16> ArgValues;
2102 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2103 CCValAssign &VA = ArgLocs[i];
2105 // Arguments stored in registers.
2106 if (VA.isRegLoc()) {
2107 EVT RegVT = VA.getLocVT();
2110 if (VA.needsCustom()) {
2111 // f64 and vector types are split up into multiple registers or
2112 // combinations of registers and stack slots.
2113 if (VA.getLocVT() == MVT::v2f64) {
2114 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
2116 VA = ArgLocs[++i]; // skip ahead to next loc
2118 if (VA.isMemLoc()) {
2119 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
2120 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2121 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
2122 PseudoSourceValue::getFixedStack(FI), 0,
2125 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
2128 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2129 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2130 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
2131 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2132 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
2134 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
2137 TargetRegisterClass *RC;
2139 if (RegVT == MVT::f32)
2140 RC = ARM::SPRRegisterClass;
2141 else if (RegVT == MVT::f64)
2142 RC = ARM::DPRRegisterClass;
2143 else if (RegVT == MVT::v2f64)
2144 RC = ARM::QPRRegisterClass;
2145 else if (RegVT == MVT::i32)
2146 RC = (AFI->isThumb1OnlyFunction() ?
2147 ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
2149 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2151 // Transform the arguments in physical registers into virtual ones.
2152 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2153 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2156 // If this is an 8 or 16-bit value, it is really passed promoted
2157 // to 32 bits. Insert an assert[sz]ext to capture this, then
2158 // truncate to the right size.
2159 switch (VA.getLocInfo()) {
2160 default: llvm_unreachable("Unknown loc info!");
2161 case CCValAssign::Full: break;
2162 case CCValAssign::BCvt:
2163 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
2165 case CCValAssign::SExt:
2166 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2167 DAG.getValueType(VA.getValVT()));
2168 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2170 case CCValAssign::ZExt:
2171 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2172 DAG.getValueType(VA.getValVT()));
2173 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2177 InVals.push_back(ArgValue);
2179 } else { // VA.isRegLoc()
2182 assert(VA.isMemLoc());
2183 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
2185 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
2186 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(), true);
2188 // Create load nodes to retrieve arguments from the stack.
2189 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2190 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2191 PseudoSourceValue::getFixedStack(FI), 0,
2198 static const unsigned GPRArgRegs[] = {
2199 ARM::R0, ARM::R1, ARM::R2, ARM::R3
2202 unsigned NumGPRs = CCInfo.getFirstUnallocated
2203 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
2205 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
2206 unsigned VARegSize = (4 - NumGPRs) * 4;
2207 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
2208 unsigned ArgOffset = CCInfo.getNextStackOffset();
2209 if (VARegSaveSize) {
2210 // If this function is vararg, store any remaining integer argument regs
2211 // to their spots on the stack so that they may be loaded by deferencing
2212 // the result of va_next.
2213 AFI->setVarArgsRegSaveSize(VARegSaveSize);
2214 AFI->setVarArgsFrameIndex(
2215 MFI->CreateFixedObject(VARegSaveSize,
2216 ArgOffset + VARegSaveSize - VARegSize,
2218 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(),
2221 SmallVector<SDValue, 4> MemOps;
2222 for (; NumGPRs < 4; ++NumGPRs) {
2223 TargetRegisterClass *RC;
2224 if (AFI->isThumb1OnlyFunction())
2225 RC = ARM::tGPRRegisterClass;
2227 RC = ARM::GPRRegisterClass;
2229 unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
2230 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2232 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2233 PseudoSourceValue::getFixedStack(AFI->getVarArgsFrameIndex()),
2234 0, false, false, 0);
2235 MemOps.push_back(Store);
2236 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
2237 DAG.getConstant(4, getPointerTy()));
2239 if (!MemOps.empty())
2240 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2241 &MemOps[0], MemOps.size());
2243 // This will point to the next argument passed via stack.
2244 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset, true));
2250 /// isFloatingPointZero - Return true if this is +0.0.
2251 static bool isFloatingPointZero(SDValue Op) {
2252 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
2253 return CFP->getValueAPF().isPosZero();
2254 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
2255 // Maybe this has already been legalized into the constant pool?
2256 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
2257 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
2258 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
2259 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
2260 return CFP->getValueAPF().isPosZero();
2266 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
2267 /// the given operands.
2269 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2270 SDValue &ARMcc, SelectionDAG &DAG,
2271 DebugLoc dl) const {
2272 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
2273 unsigned C = RHSC->getZExtValue();
2274 if (!isLegalICmpImmediate(C)) {
2275 // Constant does not fit, try adjusting it by one?
2280 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
2281 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
2282 RHS = DAG.getConstant(C-1, MVT::i32);
2287 if (C != 0 && isLegalICmpImmediate(C-1)) {
2288 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
2289 RHS = DAG.getConstant(C-1, MVT::i32);
2294 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
2295 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
2296 RHS = DAG.getConstant(C+1, MVT::i32);
2301 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
2302 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2303 RHS = DAG.getConstant(C+1, MVT::i32);
2310 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2311 ARMISD::NodeType CompareType;
2314 CompareType = ARMISD::CMP;
2319 CompareType = ARMISD::CMPZ;
2322 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2323 return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS);
2326 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
2328 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
2329 DebugLoc dl) const {
2331 if (!isFloatingPointZero(RHS))
2332 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS);
2334 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS);
2335 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp);
2338 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2339 SDValue Cond = Op.getOperand(0);
2340 SDValue SelectTrue = Op.getOperand(1);
2341 SDValue SelectFalse = Op.getOperand(2);
2342 DebugLoc dl = Op.getDebugLoc();
2346 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
2347 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
2349 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
2350 const ConstantSDNode *CMOVTrue =
2351 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
2352 const ConstantSDNode *CMOVFalse =
2353 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
2355 if (CMOVTrue && CMOVFalse) {
2356 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
2357 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
2361 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
2363 False = SelectFalse;
2364 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
2369 if (True.getNode() && False.getNode()) {
2370 EVT VT = Cond.getValueType();
2371 SDValue ARMcc = Cond.getOperand(2);
2372 SDValue CCR = Cond.getOperand(3);
2373 SDValue Cmp = Cond.getOperand(4);
2374 return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp);
2379 return DAG.getSelectCC(dl, Cond,
2380 DAG.getConstant(0, Cond.getValueType()),
2381 SelectTrue, SelectFalse, ISD::SETNE);
2384 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
2385 EVT VT = Op.getValueType();
2386 SDValue LHS = Op.getOperand(0);
2387 SDValue RHS = Op.getOperand(1);
2388 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2389 SDValue TrueVal = Op.getOperand(2);
2390 SDValue FalseVal = Op.getOperand(3);
2391 DebugLoc dl = Op.getDebugLoc();
2393 if (LHS.getValueType() == MVT::i32) {
2395 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2396 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2397 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,Cmp);
2400 ARMCC::CondCodes CondCode, CondCode2;
2401 FPCCToARMCC(CC, CondCode, CondCode2);
2403 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2404 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2405 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2406 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
2408 if (CondCode2 != ARMCC::AL) {
2409 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32);
2410 // FIXME: Needs another CMP because flag can have but one use.
2411 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
2412 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
2413 Result, TrueVal, ARMcc2, CCR, Cmp2);
2418 /// canChangeToInt - Given the fp compare operand, return true if it is suitable
2419 /// to morph to an integer compare sequence.
2420 static bool canChangeToInt(SDValue Op, bool &SeenZero,
2421 const ARMSubtarget *Subtarget) {
2422 SDNode *N = Op.getNode();
2423 if (!N->hasOneUse())
2424 // Otherwise it requires moving the value from fp to integer registers.
2426 if (!N->getNumValues())
2428 EVT VT = Op.getValueType();
2429 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
2430 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
2431 // vmrs are very slow, e.g. cortex-a8.
2434 if (isFloatingPointZero(Op)) {
2438 return ISD::isNormalLoad(N);
2441 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
2442 if (isFloatingPointZero(Op))
2443 return DAG.getConstant(0, MVT::i32);
2445 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
2446 return DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2447 Ld->getChain(), Ld->getBasePtr(),
2448 Ld->getSrcValue(), Ld->getSrcValueOffset(),
2449 Ld->isVolatile(), Ld->isNonTemporal(),
2450 Ld->getAlignment());
2452 llvm_unreachable("Unknown VFP cmp argument!");
2455 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
2456 SDValue &RetVal1, SDValue &RetVal2) {
2457 if (isFloatingPointZero(Op)) {
2458 RetVal1 = DAG.getConstant(0, MVT::i32);
2459 RetVal2 = DAG.getConstant(0, MVT::i32);
2463 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
2464 SDValue Ptr = Ld->getBasePtr();
2465 RetVal1 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2466 Ld->getChain(), Ptr,
2467 Ld->getSrcValue(), Ld->getSrcValueOffset(),
2468 Ld->isVolatile(), Ld->isNonTemporal(),
2469 Ld->getAlignment());
2471 EVT PtrType = Ptr.getValueType();
2472 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
2473 SDValue NewPtr = DAG.getNode(ISD::ADD, Op.getDebugLoc(),
2474 PtrType, Ptr, DAG.getConstant(4, PtrType));
2475 RetVal2 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2476 Ld->getChain(), NewPtr,
2477 Ld->getSrcValue(), Ld->getSrcValueOffset() + 4,
2478 Ld->isVolatile(), Ld->isNonTemporal(),
2483 llvm_unreachable("Unknown VFP cmp argument!");
2486 /// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
2487 /// f32 and even f64 comparisons to integer ones.
2489 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
2490 SDValue Chain = Op.getOperand(0);
2491 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2492 SDValue LHS = Op.getOperand(2);
2493 SDValue RHS = Op.getOperand(3);
2494 SDValue Dest = Op.getOperand(4);
2495 DebugLoc dl = Op.getDebugLoc();
2497 bool SeenZero = false;
2498 if (canChangeToInt(LHS, SeenZero, Subtarget) &&
2499 canChangeToInt(RHS, SeenZero, Subtarget) &&
2500 // If one of the operand is zero, it's safe to ignore the NaN case since
2501 // we only care about equality comparisons.
2502 (SeenZero || (DAG.isKnownNeverNaN(LHS) && DAG.isKnownNeverNaN(RHS)))) {
2503 // If unsafe fp math optimization is enabled and there are no othter uses of
2504 // the CMP operands, and the condition code is EQ oe NE, we can optimize it
2505 // to an integer comparison.
2506 if (CC == ISD::SETOEQ)
2508 else if (CC == ISD::SETUNE)
2512 if (LHS.getValueType() == MVT::f32) {
2513 LHS = bitcastf32Toi32(LHS, DAG);
2514 RHS = bitcastf32Toi32(RHS, DAG);
2515 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2516 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2517 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2518 Chain, Dest, ARMcc, CCR, Cmp);
2523 expandf64Toi32(LHS, DAG, LHS1, LHS2);
2524 expandf64Toi32(RHS, DAG, RHS1, RHS2);
2525 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2526 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2527 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
2528 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
2529 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7);
2535 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2536 SDValue Chain = Op.getOperand(0);
2537 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2538 SDValue LHS = Op.getOperand(2);
2539 SDValue RHS = Op.getOperand(3);
2540 SDValue Dest = Op.getOperand(4);
2541 DebugLoc dl = Op.getDebugLoc();
2543 if (LHS.getValueType() == MVT::i32) {
2545 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2546 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2547 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2548 Chain, Dest, ARMcc, CCR, Cmp);
2551 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
2554 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
2555 CC == ISD::SETNE || CC == ISD::SETUNE)) {
2556 SDValue Result = OptimizeVFPBrcond(Op, DAG);
2557 if (Result.getNode())
2561 ARMCC::CondCodes CondCode, CondCode2;
2562 FPCCToARMCC(CC, CondCode, CondCode2);
2564 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2565 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2566 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2567 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
2568 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
2569 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2570 if (CondCode2 != ARMCC::AL) {
2571 ARMcc = DAG.getConstant(CondCode2, MVT::i32);
2572 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
2573 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2578 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
2579 SDValue Chain = Op.getOperand(0);
2580 SDValue Table = Op.getOperand(1);
2581 SDValue Index = Op.getOperand(2);
2582 DebugLoc dl = Op.getDebugLoc();
2584 EVT PTy = getPointerTy();
2585 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
2586 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
2587 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
2588 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
2589 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
2590 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
2591 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2592 if (Subtarget->isThumb2()) {
2593 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
2594 // which does another jump to the destination. This also makes it easier
2595 // to translate it to TBB / TBH later.
2596 // FIXME: This might not work if the function is extremely large.
2597 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
2598 Addr, Op.getOperand(2), JTI, UId);
2600 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2601 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
2602 PseudoSourceValue::getJumpTable(), 0,
2604 Chain = Addr.getValue(1);
2605 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
2606 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2608 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
2609 PseudoSourceValue::getJumpTable(), 0, false, false, 0);
2610 Chain = Addr.getValue(1);
2611 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2615 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
2616 DebugLoc dl = Op.getDebugLoc();
2619 switch (Op.getOpcode()) {
2621 assert(0 && "Invalid opcode!");
2622 case ISD::FP_TO_SINT:
2623 Opc = ARMISD::FTOSI;
2625 case ISD::FP_TO_UINT:
2626 Opc = ARMISD::FTOUI;
2629 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
2630 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
2633 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
2634 EVT VT = Op.getValueType();
2635 DebugLoc dl = Op.getDebugLoc();
2638 switch (Op.getOpcode()) {
2640 assert(0 && "Invalid opcode!");
2641 case ISD::SINT_TO_FP:
2642 Opc = ARMISD::SITOF;
2644 case ISD::UINT_TO_FP:
2645 Opc = ARMISD::UITOF;
2649 Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
2650 return DAG.getNode(Opc, dl, VT, Op);
2653 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
2654 // Implement fcopysign with a fabs and a conditional fneg.
2655 SDValue Tmp0 = Op.getOperand(0);
2656 SDValue Tmp1 = Op.getOperand(1);
2657 DebugLoc dl = Op.getDebugLoc();
2658 EVT VT = Op.getValueType();
2659 EVT SrcVT = Tmp1.getValueType();
2660 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
2661 SDValue ARMcc = DAG.getConstant(ARMCC::LT, MVT::i32);
2662 SDValue FP0 = DAG.getConstantFP(0.0, SrcVT);
2663 SDValue Cmp = getVFPCmp(Tmp1, FP0, DAG, dl);
2664 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2665 return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMcc, CCR, Cmp);
2668 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
2669 MachineFunction &MF = DAG.getMachineFunction();
2670 MachineFrameInfo *MFI = MF.getFrameInfo();
2671 MFI->setReturnAddressIsTaken(true);
2673 EVT VT = Op.getValueType();
2674 DebugLoc dl = Op.getDebugLoc();
2675 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2677 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
2678 SDValue Offset = DAG.getConstant(4, MVT::i32);
2679 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
2680 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
2681 NULL, 0, false, false, 0);
2684 // Return LR, which contains the return address. Mark it an implicit live-in.
2685 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
2686 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
2689 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2690 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2691 MFI->setFrameAddressIsTaken(true);
2693 EVT VT = Op.getValueType();
2694 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
2695 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2696 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
2697 ? ARM::R7 : ARM::R11;
2698 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
2700 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0,
2705 /// ExpandBIT_CONVERT - If the target supports VFP, this function is called to
2706 /// expand a bit convert where either the source or destination type is i64 to
2707 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
2708 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
2709 /// vectors), since the legalizer won't know what to do with that.
2710 static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
2711 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2712 DebugLoc dl = N->getDebugLoc();
2713 SDValue Op = N->getOperand(0);
2715 // This function is only supposed to be called for i64 types, either as the
2716 // source or destination of the bit convert.
2717 EVT SrcVT = Op.getValueType();
2718 EVT DstVT = N->getValueType(0);
2719 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
2720 "ExpandBIT_CONVERT called for non-i64 type");
2722 // Turn i64->f64 into VMOVDRR.
2723 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
2724 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2725 DAG.getConstant(0, MVT::i32));
2726 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2727 DAG.getConstant(1, MVT::i32));
2728 return DAG.getNode(ISD::BIT_CONVERT, dl, DstVT,
2729 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
2732 // Turn f64->i64 into VMOVRRD.
2733 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
2734 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
2735 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
2736 // Merge the pieces into a single i64 value.
2737 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
2743 /// getZeroVector - Returns a vector of specified type with all zero elements.
2744 /// Zero vectors are used to represent vector negation and in those cases
2745 /// will be implemented with the NEON VNEG instruction. However, VNEG does
2746 /// not support i64 elements, so sometimes the zero vectors will need to be
2747 /// explicitly constructed. Regardless, use a canonical VMOV to create the
2749 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2750 assert(VT.isVector() && "Expected a vector type");
2751 // The canonical modified immediate encoding of a zero vector is....0!
2752 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32);
2753 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
2754 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
2755 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov);
2758 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
2759 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2760 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
2761 SelectionDAG &DAG) const {
2762 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2763 EVT VT = Op.getValueType();
2764 unsigned VTBits = VT.getSizeInBits();
2765 DebugLoc dl = Op.getDebugLoc();
2766 SDValue ShOpLo = Op.getOperand(0);
2767 SDValue ShOpHi = Op.getOperand(1);
2768 SDValue ShAmt = Op.getOperand(2);
2770 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
2772 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
2774 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2775 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2776 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
2777 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2778 DAG.getConstant(VTBits, MVT::i32));
2779 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
2780 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2781 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
2783 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2784 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
2786 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
2787 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
2790 SDValue Ops[2] = { Lo, Hi };
2791 return DAG.getMergeValues(Ops, 2, dl);
2794 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
2795 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2796 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
2797 SelectionDAG &DAG) const {
2798 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2799 EVT VT = Op.getValueType();
2800 unsigned VTBits = VT.getSizeInBits();
2801 DebugLoc dl = Op.getDebugLoc();
2802 SDValue ShOpLo = Op.getOperand(0);
2803 SDValue ShOpHi = Op.getOperand(1);
2804 SDValue ShAmt = Op.getOperand(2);
2807 assert(Op.getOpcode() == ISD::SHL_PARTS);
2808 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2809 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2810 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
2811 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2812 DAG.getConstant(VTBits, MVT::i32));
2813 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
2814 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
2816 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2817 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2818 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
2820 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
2821 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
2824 SDValue Ops[2] = { Lo, Hi };
2825 return DAG.getMergeValues(Ops, 2, dl);
2828 SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
2829 SelectionDAG &DAG) const {
2830 // The rounding mode is in bits 23:22 of the FPSCR.
2831 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
2832 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
2833 // so that the shift + and get folded into a bitfield extract.
2834 DebugLoc dl = Op.getDebugLoc();
2835 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
2836 DAG.getConstant(Intrinsic::arm_get_fpscr,
2838 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
2839 DAG.getConstant(1U << 22, MVT::i32));
2840 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
2841 DAG.getConstant(22, MVT::i32));
2842 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
2843 DAG.getConstant(3, MVT::i32));
2846 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
2847 const ARMSubtarget *ST) {
2848 EVT VT = N->getValueType(0);
2849 DebugLoc dl = N->getDebugLoc();
2851 if (!ST->hasV6T2Ops())
2854 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
2855 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
2858 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
2859 const ARMSubtarget *ST) {
2860 EVT VT = N->getValueType(0);
2861 DebugLoc dl = N->getDebugLoc();
2863 // Lower vector shifts on NEON to use VSHL.
2864 if (VT.isVector()) {
2865 assert(ST->hasNEON() && "unexpected vector shift");
2867 // Left shifts translate directly to the vshiftu intrinsic.
2868 if (N->getOpcode() == ISD::SHL)
2869 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2870 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
2871 N->getOperand(0), N->getOperand(1));
2873 assert((N->getOpcode() == ISD::SRA ||
2874 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
2876 // NEON uses the same intrinsics for both left and right shifts. For
2877 // right shifts, the shift amounts are negative, so negate the vector of
2879 EVT ShiftVT = N->getOperand(1).getValueType();
2880 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
2881 getZeroVector(ShiftVT, DAG, dl),
2883 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
2884 Intrinsic::arm_neon_vshifts :
2885 Intrinsic::arm_neon_vshiftu);
2886 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2887 DAG.getConstant(vshiftInt, MVT::i32),
2888 N->getOperand(0), NegatedCount);
2891 // We can get here for a node like i32 = ISD::SHL i32, i64
2895 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
2896 "Unknown shift to lower!");
2898 // We only lower SRA, SRL of 1 here, all others use generic lowering.
2899 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
2900 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
2903 // If we are in thumb mode, we don't have RRX.
2904 if (ST->isThumb1Only()) return SDValue();
2906 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
2907 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2908 DAG.getConstant(0, MVT::i32));
2909 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2910 DAG.getConstant(1, MVT::i32));
2912 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
2913 // captures the result into a carry flag.
2914 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
2915 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
2917 // The low part is an ARMISD::RRX operand, which shifts the carry in.
2918 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
2920 // Merge the pieces into a single i64 value.
2921 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
2924 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
2925 SDValue TmpOp0, TmpOp1;
2926 bool Invert = false;
2930 SDValue Op0 = Op.getOperand(0);
2931 SDValue Op1 = Op.getOperand(1);
2932 SDValue CC = Op.getOperand(2);
2933 EVT VT = Op.getValueType();
2934 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
2935 DebugLoc dl = Op.getDebugLoc();
2937 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
2938 switch (SetCCOpcode) {
2939 default: llvm_unreachable("Illegal FP comparison"); break;
2941 case ISD::SETNE: Invert = true; // Fallthrough
2943 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2945 case ISD::SETLT: Swap = true; // Fallthrough
2947 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2949 case ISD::SETLE: Swap = true; // Fallthrough
2951 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2952 case ISD::SETUGE: Swap = true; // Fallthrough
2953 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
2954 case ISD::SETUGT: Swap = true; // Fallthrough
2955 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
2956 case ISD::SETUEQ: Invert = true; // Fallthrough
2958 // Expand this to (OLT | OGT).
2962 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2963 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
2965 case ISD::SETUO: Invert = true; // Fallthrough
2967 // Expand this to (OLT | OGE).
2971 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2972 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
2976 // Integer comparisons.
2977 switch (SetCCOpcode) {
2978 default: llvm_unreachable("Illegal integer comparison"); break;
2979 case ISD::SETNE: Invert = true;
2980 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2981 case ISD::SETLT: Swap = true;
2982 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2983 case ISD::SETLE: Swap = true;
2984 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2985 case ISD::SETULT: Swap = true;
2986 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
2987 case ISD::SETULE: Swap = true;
2988 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
2991 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
2992 if (Opc == ARMISD::VCEQ) {
2995 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
2997 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
3000 // Ignore bitconvert.
3001 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BIT_CONVERT)
3002 AndOp = AndOp.getOperand(0);
3004 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
3006 Op0 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(0));
3007 Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(1));
3014 std::swap(Op0, Op1);
3016 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3019 Result = DAG.getNOT(dl, Result, VT);
3024 /// isNEONModifiedImm - Check if the specified splat value corresponds to a
3025 /// valid vector constant for a NEON instruction with a "modified immediate"
3026 /// operand (e.g., VMOV). If so, return the encoded value.
3027 static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
3028 unsigned SplatBitSize, SelectionDAG &DAG,
3029 EVT &VT, bool is128Bits, bool isVMOV) {
3030 unsigned OpCmode, Imm;
3032 // SplatBitSize is set to the smallest size that splats the vector, so a
3033 // zero vector will always have SplatBitSize == 8. However, NEON modified
3034 // immediate instructions others than VMOV do not support the 8-bit encoding
3035 // of a zero vector, and the default encoding of zero is supposed to be the
3040 switch (SplatBitSize) {
3044 // Any 1-byte value is OK. Op=0, Cmode=1110.
3045 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
3048 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
3052 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
3053 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
3054 if ((SplatBits & ~0xff) == 0) {
3055 // Value = 0x00nn: Op=x, Cmode=100x.
3060 if ((SplatBits & ~0xff00) == 0) {
3061 // Value = 0xnn00: Op=x, Cmode=101x.
3063 Imm = SplatBits >> 8;
3069 // NEON's 32-bit VMOV supports splat values where:
3070 // * only one byte is nonzero, or
3071 // * the least significant byte is 0xff and the second byte is nonzero, or
3072 // * the least significant 2 bytes are 0xff and the third is nonzero.
3073 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
3074 if ((SplatBits & ~0xff) == 0) {
3075 // Value = 0x000000nn: Op=x, Cmode=000x.
3080 if ((SplatBits & ~0xff00) == 0) {
3081 // Value = 0x0000nn00: Op=x, Cmode=001x.
3083 Imm = SplatBits >> 8;
3086 if ((SplatBits & ~0xff0000) == 0) {
3087 // Value = 0x00nn0000: Op=x, Cmode=010x.
3089 Imm = SplatBits >> 16;
3092 if ((SplatBits & ~0xff000000) == 0) {
3093 // Value = 0xnn000000: Op=x, Cmode=011x.
3095 Imm = SplatBits >> 24;
3099 if ((SplatBits & ~0xffff) == 0 &&
3100 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
3101 // Value = 0x0000nnff: Op=x, Cmode=1100.
3103 Imm = SplatBits >> 8;
3108 if ((SplatBits & ~0xffffff) == 0 &&
3109 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
3110 // Value = 0x00nnffff: Op=x, Cmode=1101.
3112 Imm = SplatBits >> 16;
3113 SplatBits |= 0xffff;
3117 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
3118 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
3119 // VMOV.I32. A (very) minor optimization would be to replicate the value
3120 // and fall through here to test for a valid 64-bit splat. But, then the
3121 // caller would also need to check and handle the change in size.
3127 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
3128 uint64_t BitMask = 0xff;
3130 unsigned ImmMask = 1;
3132 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
3133 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
3136 } else if ((SplatBits & BitMask) != 0) {
3142 // Op=1, Cmode=1110.
3145 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
3150 llvm_unreachable("unexpected size for isNEONModifiedImm");
3154 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
3155 return DAG.getTargetConstant(EncodedVal, MVT::i32);
3158 static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT,
3159 bool &ReverseVEXT, unsigned &Imm) {
3160 unsigned NumElts = VT.getVectorNumElements();
3161 ReverseVEXT = false;
3163 // Assume that the first shuffle index is not UNDEF. Fail if it is.
3169 // If this is a VEXT shuffle, the immediate value is the index of the first
3170 // element. The other shuffle indices must be the successive elements after
3172 unsigned ExpectedElt = Imm;
3173 for (unsigned i = 1; i < NumElts; ++i) {
3174 // Increment the expected index. If it wraps around, it may still be
3175 // a VEXT but the source vectors must be swapped.
3177 if (ExpectedElt == NumElts * 2) {
3182 if (M[i] < 0) continue; // ignore UNDEF indices
3183 if (ExpectedElt != static_cast<unsigned>(M[i]))
3187 // Adjust the index value if the source operands will be swapped.
3194 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
3195 /// instruction with the specified blocksize. (The order of the elements
3196 /// within each block of the vector is reversed.)
3197 static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT,
3198 unsigned BlockSize) {
3199 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
3200 "Only possible block sizes for VREV are: 16, 32, 64");
3202 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3206 unsigned NumElts = VT.getVectorNumElements();
3207 unsigned BlockElts = M[0] + 1;
3208 // If the first shuffle index is UNDEF, be optimistic.
3210 BlockElts = BlockSize / EltSz;
3212 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
3215 for (unsigned i = 0; i < NumElts; ++i) {
3216 if (M[i] < 0) continue; // ignore UNDEF indices
3217 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
3224 static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT,
3225 unsigned &WhichResult) {
3226 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3230 unsigned NumElts = VT.getVectorNumElements();
3231 WhichResult = (M[0] == 0 ? 0 : 1);
3232 for (unsigned i = 0; i < NumElts; i += 2) {
3233 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3234 (M[i+1] >= 0 && (unsigned) M[i+1] != i + NumElts + WhichResult))
3240 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
3241 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3242 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
3243 static bool isVTRN_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3244 unsigned &WhichResult) {
3245 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3249 unsigned NumElts = VT.getVectorNumElements();
3250 WhichResult = (M[0] == 0 ? 0 : 1);
3251 for (unsigned i = 0; i < NumElts; i += 2) {
3252 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3253 (M[i+1] >= 0 && (unsigned) M[i+1] != i + WhichResult))
3259 static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT,
3260 unsigned &WhichResult) {
3261 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3265 unsigned NumElts = VT.getVectorNumElements();
3266 WhichResult = (M[0] == 0 ? 0 : 1);
3267 for (unsigned i = 0; i != NumElts; ++i) {
3268 if (M[i] < 0) continue; // ignore UNDEF indices
3269 if ((unsigned) M[i] != 2 * i + WhichResult)
3273 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3274 if (VT.is64BitVector() && EltSz == 32)
3280 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
3281 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3282 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
3283 static bool isVUZP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3284 unsigned &WhichResult) {
3285 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3289 unsigned Half = VT.getVectorNumElements() / 2;
3290 WhichResult = (M[0] == 0 ? 0 : 1);
3291 for (unsigned j = 0; j != 2; ++j) {
3292 unsigned Idx = WhichResult;
3293 for (unsigned i = 0; i != Half; ++i) {
3294 int MIdx = M[i + j * Half];
3295 if (MIdx >= 0 && (unsigned) MIdx != Idx)
3301 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3302 if (VT.is64BitVector() && EltSz == 32)
3308 static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT,
3309 unsigned &WhichResult) {
3310 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3314 unsigned NumElts = VT.getVectorNumElements();
3315 WhichResult = (M[0] == 0 ? 0 : 1);
3316 unsigned Idx = WhichResult * NumElts / 2;
3317 for (unsigned i = 0; i != NumElts; i += 2) {
3318 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3319 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts))
3324 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3325 if (VT.is64BitVector() && EltSz == 32)
3331 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
3332 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3333 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
3334 static bool isVZIP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3335 unsigned &WhichResult) {
3336 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3340 unsigned NumElts = VT.getVectorNumElements();
3341 WhichResult = (M[0] == 0 ? 0 : 1);
3342 unsigned Idx = WhichResult * NumElts / 2;
3343 for (unsigned i = 0; i != NumElts; i += 2) {
3344 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3345 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx))
3350 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3351 if (VT.is64BitVector() && EltSz == 32)
3357 // If N is an integer constant that can be moved into a register in one
3358 // instruction, return an SDValue of such a constant (will become a MOV
3359 // instruction). Otherwise return null.
3360 static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG,
3361 const ARMSubtarget *ST, DebugLoc dl) {
3363 if (!isa<ConstantSDNode>(N))
3365 Val = cast<ConstantSDNode>(N)->getZExtValue();
3367 if (ST->isThumb1Only()) {
3368 if (Val <= 255 || ~Val <= 255)
3369 return DAG.getConstant(Val, MVT::i32);
3371 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1)
3372 return DAG.getConstant(Val, MVT::i32);
3377 // If this is a case we can't handle, return null and let the default
3378 // expansion code take care of it.
3379 static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
3380 const ARMSubtarget *ST) {
3381 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
3382 DebugLoc dl = Op.getDebugLoc();
3383 EVT VT = Op.getValueType();
3385 APInt SplatBits, SplatUndef;
3386 unsigned SplatBitSize;
3388 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
3389 if (SplatBitSize <= 64) {
3390 // Check if an immediate VMOV works.
3392 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
3393 SplatUndef.getZExtValue(), SplatBitSize,
3394 DAG, VmovVT, VT.is128BitVector(), true);
3395 if (Val.getNode()) {
3396 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
3397 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov);
3400 // Try an immediate VMVN.
3401 uint64_t NegatedImm = (SplatBits.getZExtValue() ^
3402 ((1LL << SplatBitSize) - 1));
3403 Val = isNEONModifiedImm(NegatedImm,
3404 SplatUndef.getZExtValue(), SplatBitSize,
3405 DAG, VmovVT, VT.is128BitVector(), false);
3406 if (Val.getNode()) {
3407 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
3408 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov);
3413 // Scan through the operands to see if only one value is used.
3414 unsigned NumElts = VT.getVectorNumElements();
3415 bool isOnlyLowElement = true;
3416 bool usesOnlyOneValue = true;
3417 bool isConstant = true;
3419 for (unsigned i = 0; i < NumElts; ++i) {
3420 SDValue V = Op.getOperand(i);
3421 if (V.getOpcode() == ISD::UNDEF)
3424 isOnlyLowElement = false;
3425 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
3428 if (!Value.getNode())
3430 else if (V != Value)
3431 usesOnlyOneValue = false;
3434 if (!Value.getNode())
3435 return DAG.getUNDEF(VT);
3437 if (isOnlyLowElement)
3438 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
3440 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3442 if (EnableARMVDUPsplat) {
3443 // Use VDUP for non-constant splats. For f32 constant splats, reduce to
3444 // i32 and try again.
3445 if (usesOnlyOneValue && EltSize <= 32) {
3447 return DAG.getNode(ARMISD::VDUP, dl, VT, Value);
3448 if (VT.getVectorElementType().isFloatingPoint()) {
3449 SmallVector<SDValue, 8> Ops;
3450 for (unsigned i = 0; i < NumElts; ++i)
3451 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32,
3453 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &Ops[0],
3455 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3456 LowerBUILD_VECTOR(Val, DAG, ST));
3458 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
3460 return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
3464 // If all elements are constants and the case above didn't get hit, fall back
3465 // to the default expansion, which will generate a load from the constant
3470 if (!EnableARMVDUPsplat) {
3471 // Use VDUP for non-constant splats.
3472 if (usesOnlyOneValue && EltSize <= 32)
3473 return DAG.getNode(ARMISD::VDUP, dl, VT, Value);
3476 // Vectors with 32- or 64-bit elements can be built by directly assigning
3477 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
3478 // will be legalized.
3479 if (EltSize >= 32) {
3480 // Do the expansion with floating-point types, since that is what the VFP
3481 // registers are defined to use, and since i64 is not legal.
3482 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3483 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3484 SmallVector<SDValue, 8> Ops;
3485 for (unsigned i = 0; i < NumElts; ++i)
3486 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, EltVT, Op.getOperand(i)));
3487 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
3488 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val);
3494 /// isShuffleMaskLegal - Targets can use this to indicate that they only
3495 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
3496 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
3497 /// are assumed to be legal.
3499 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
3501 if (VT.getVectorNumElements() == 4 &&
3502 (VT.is128BitVector() || VT.is64BitVector())) {
3503 unsigned PFIndexes[4];
3504 for (unsigned i = 0; i != 4; ++i) {
3508 PFIndexes[i] = M[i];
3511 // Compute the index in the perfect shuffle table.
3512 unsigned PFTableIndex =
3513 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3514 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3515 unsigned Cost = (PFEntry >> 30);
3522 unsigned Imm, WhichResult;
3524 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3525 return (EltSize >= 32 ||
3526 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
3527 isVREVMask(M, VT, 64) ||
3528 isVREVMask(M, VT, 32) ||
3529 isVREVMask(M, VT, 16) ||
3530 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
3531 isVTRNMask(M, VT, WhichResult) ||
3532 isVUZPMask(M, VT, WhichResult) ||
3533 isVZIPMask(M, VT, WhichResult) ||
3534 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
3535 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
3536 isVZIP_v_undef_Mask(M, VT, WhichResult));
3539 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
3540 /// the specified operations to build the shuffle.
3541 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
3542 SDValue RHS, SelectionDAG &DAG,
3544 unsigned OpNum = (PFEntry >> 26) & 0x0F;
3545 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
3546 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
3549 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
3558 OP_VUZPL, // VUZP, left result
3559 OP_VUZPR, // VUZP, right result
3560 OP_VZIPL, // VZIP, left result
3561 OP_VZIPR, // VZIP, right result
3562 OP_VTRNL, // VTRN, left result
3563 OP_VTRNR // VTRN, right result
3566 if (OpNum == OP_COPY) {
3567 if (LHSID == (1*9+2)*9+3) return LHS;
3568 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
3572 SDValue OpLHS, OpRHS;
3573 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
3574 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
3575 EVT VT = OpLHS.getValueType();
3578 default: llvm_unreachable("Unknown shuffle opcode!");
3580 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
3585 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
3586 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
3590 return DAG.getNode(ARMISD::VEXT, dl, VT,
3592 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
3595 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3596 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
3599 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3600 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
3603 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3604 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
3608 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
3609 SDValue V1 = Op.getOperand(0);
3610 SDValue V2 = Op.getOperand(1);
3611 DebugLoc dl = Op.getDebugLoc();
3612 EVT VT = Op.getValueType();
3613 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
3614 SmallVector<int, 8> ShuffleMask;
3616 // Convert shuffles that are directly supported on NEON to target-specific
3617 // DAG nodes, instead of keeping them as shuffles and matching them again
3618 // during code selection. This is more efficient and avoids the possibility
3619 // of inconsistencies between legalization and selection.
3620 // FIXME: floating-point vectors should be canonicalized to integer vectors
3621 // of the same time so that they get CSEd properly.
3622 SVN->getMask(ShuffleMask);
3624 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3625 if (EltSize <= 32) {
3626 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
3627 int Lane = SVN->getSplatIndex();
3628 // If this is undef splat, generate it via "just" vdup, if possible.
3629 if (Lane == -1) Lane = 0;
3631 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
3632 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
3634 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
3635 DAG.getConstant(Lane, MVT::i32));
3640 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
3643 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
3644 DAG.getConstant(Imm, MVT::i32));
3647 if (isVREVMask(ShuffleMask, VT, 64))
3648 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
3649 if (isVREVMask(ShuffleMask, VT, 32))
3650 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
3651 if (isVREVMask(ShuffleMask, VT, 16))
3652 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
3654 // Check for Neon shuffles that modify both input vectors in place.
3655 // If both results are used, i.e., if there are two shuffles with the same
3656 // source operands and with masks corresponding to both results of one of
3657 // these operations, DAG memoization will ensure that a single node is
3658 // used for both shuffles.
3659 unsigned WhichResult;
3660 if (isVTRNMask(ShuffleMask, VT, WhichResult))
3661 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3662 V1, V2).getValue(WhichResult);
3663 if (isVUZPMask(ShuffleMask, VT, WhichResult))
3664 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3665 V1, V2).getValue(WhichResult);
3666 if (isVZIPMask(ShuffleMask, VT, WhichResult))
3667 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3668 V1, V2).getValue(WhichResult);
3670 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
3671 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3672 V1, V1).getValue(WhichResult);
3673 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
3674 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3675 V1, V1).getValue(WhichResult);
3676 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
3677 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3678 V1, V1).getValue(WhichResult);
3681 // If the shuffle is not directly supported and it has 4 elements, use
3682 // the PerfectShuffle-generated table to synthesize it from other shuffles.
3683 unsigned NumElts = VT.getVectorNumElements();
3685 unsigned PFIndexes[4];
3686 for (unsigned i = 0; i != 4; ++i) {
3687 if (ShuffleMask[i] < 0)
3690 PFIndexes[i] = ShuffleMask[i];
3693 // Compute the index in the perfect shuffle table.
3694 unsigned PFTableIndex =
3695 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3696 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3697 unsigned Cost = (PFEntry >> 30);
3700 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
3703 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
3704 if (EltSize >= 32) {
3705 // Do the expansion with floating-point types, since that is what the VFP
3706 // registers are defined to use, and since i64 is not legal.
3707 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3708 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3709 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, V1);
3710 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, V2);
3711 SmallVector<SDValue, 8> Ops;
3712 for (unsigned i = 0; i < NumElts; ++i) {
3713 if (ShuffleMask[i] < 0)
3714 Ops.push_back(DAG.getUNDEF(EltVT));
3716 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3717 ShuffleMask[i] < (int)NumElts ? V1 : V2,
3718 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
3721 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
3722 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val);
3728 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
3729 EVT VT = Op.getValueType();
3730 DebugLoc dl = Op.getDebugLoc();
3731 SDValue Vec = Op.getOperand(0);
3732 SDValue Lane = Op.getOperand(1);
3733 assert(VT == MVT::i32 &&
3734 Vec.getValueType().getVectorElementType().getSizeInBits() < 32 &&
3735 "unexpected type for custom-lowering vector extract");
3736 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
3739 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
3740 // The only time a CONCAT_VECTORS operation can have legal types is when
3741 // two 64-bit vectors are concatenated to a 128-bit vector.
3742 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
3743 "unexpected CONCAT_VECTORS");
3744 DebugLoc dl = Op.getDebugLoc();
3745 SDValue Val = DAG.getUNDEF(MVT::v2f64);
3746 SDValue Op0 = Op.getOperand(0);
3747 SDValue Op1 = Op.getOperand(1);
3748 if (Op0.getOpcode() != ISD::UNDEF)
3749 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
3750 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op0),
3751 DAG.getIntPtrConstant(0));
3752 if (Op1.getOpcode() != ISD::UNDEF)
3753 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
3754 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op1),
3755 DAG.getIntPtrConstant(1));
3756 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Val);
3759 /// SkipExtension - For a node that is either a SIGN_EXTEND, ZERO_EXTEND, or
3760 /// an extending load, return the unextended value.
3761 static SDValue SkipExtension(SDNode *N, SelectionDAG &DAG) {
3762 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
3763 return N->getOperand(0);
3764 LoadSDNode *LD = cast<LoadSDNode>(N);
3765 return DAG.getLoad(LD->getMemoryVT(), N->getDebugLoc(), LD->getChain(),
3766 LD->getBasePtr(), LD->getSrcValue(),
3767 LD->getSrcValueOffset(), LD->isVolatile(),
3768 LD->isNonTemporal(), LD->getAlignment());
3771 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
3772 // Multiplications are only custom-lowered for 128-bit vectors so that
3773 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
3774 EVT VT = Op.getValueType();
3775 assert(VT.is128BitVector() && "unexpected type for custom-lowering ISD::MUL");
3776 SDNode *N0 = Op.getOperand(0).getNode();
3777 SDNode *N1 = Op.getOperand(1).getNode();
3778 unsigned NewOpc = 0;
3779 if ((N0->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N0)) &&
3780 (N1->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N1))) {
3781 NewOpc = ARMISD::VMULLs;
3782 } else if ((N0->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N0)) &&
3783 (N1->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N1))) {
3784 NewOpc = ARMISD::VMULLu;
3785 } else if (VT.getSimpleVT().SimpleTy == MVT::v2i64) {
3786 // Fall through to expand this. It is not legal.
3789 // Other vector multiplications are legal.
3793 // Legalize to a VMULL instruction.
3794 DebugLoc DL = Op.getDebugLoc();
3795 SDValue Op0 = SkipExtension(N0, DAG);
3796 SDValue Op1 = SkipExtension(N1, DAG);
3798 assert(Op0.getValueType().is64BitVector() &&
3799 Op1.getValueType().is64BitVector() &&
3800 "unexpected types for extended operands to VMULL");
3801 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
3804 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
3805 switch (Op.getOpcode()) {
3806 default: llvm_unreachable("Don't know how to custom lower this!");
3807 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3808 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
3809 case ISD::GlobalAddress:
3810 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
3811 LowerGlobalAddressELF(Op, DAG);
3812 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
3813 case ISD::SELECT: return LowerSELECT(Op, DAG);
3814 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
3815 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
3816 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
3817 case ISD::VASTART: return LowerVASTART(Op, DAG);
3818 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget);
3819 case ISD::SINT_TO_FP:
3820 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
3821 case ISD::FP_TO_SINT:
3822 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
3823 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
3824 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
3825 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
3826 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
3827 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
3828 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
3829 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
3831 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(Op.getNode(), DAG);
3834 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
3835 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
3836 case ISD::SRL_PARTS:
3837 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
3838 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
3839 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
3840 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
3841 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
3842 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
3843 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
3844 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
3845 case ISD::MUL: return LowerMUL(Op, DAG);
3850 /// ReplaceNodeResults - Replace the results of node with an illegal result
3851 /// type with new values built out of custom code.
3852 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
3853 SmallVectorImpl<SDValue>&Results,
3854 SelectionDAG &DAG) const {
3856 switch (N->getOpcode()) {
3858 llvm_unreachable("Don't know how to custom expand this!");
3860 case ISD::BIT_CONVERT:
3861 Res = ExpandBIT_CONVERT(N, DAG);
3865 Res = LowerShift(N, DAG, Subtarget);
3869 Results.push_back(Res);
3872 //===----------------------------------------------------------------------===//
3873 // ARM Scheduler Hooks
3874 //===----------------------------------------------------------------------===//
3877 ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
3878 MachineBasicBlock *BB,
3879 unsigned Size) const {
3880 unsigned dest = MI->getOperand(0).getReg();
3881 unsigned ptr = MI->getOperand(1).getReg();
3882 unsigned oldval = MI->getOperand(2).getReg();
3883 unsigned newval = MI->getOperand(3).getReg();
3884 unsigned scratch = BB->getParent()->getRegInfo()
3885 .createVirtualRegister(ARM::GPRRegisterClass);
3886 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3887 DebugLoc dl = MI->getDebugLoc();
3888 bool isThumb2 = Subtarget->isThumb2();
3890 unsigned ldrOpc, strOpc;
3892 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
3894 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
3895 strOpc = isThumb2 ? ARM::t2LDREXB : ARM::STREXB;
3898 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
3899 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
3902 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
3903 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
3907 MachineFunction *MF = BB->getParent();
3908 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3909 MachineFunction::iterator It = BB;
3910 ++It; // insert the new blocks after the current block
3912 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
3913 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
3914 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3915 MF->insert(It, loop1MBB);
3916 MF->insert(It, loop2MBB);
3917 MF->insert(It, exitMBB);
3919 // Transfer the remainder of BB and its successor edges to exitMBB.
3920 exitMBB->splice(exitMBB->begin(), BB,
3921 llvm::next(MachineBasicBlock::iterator(MI)),
3923 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
3927 // fallthrough --> loop1MBB
3928 BB->addSuccessor(loop1MBB);
3931 // ldrex dest, [ptr]
3935 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
3936 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
3937 .addReg(dest).addReg(oldval));
3938 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3939 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
3940 BB->addSuccessor(loop2MBB);
3941 BB->addSuccessor(exitMBB);
3944 // strex scratch, newval, [ptr]
3948 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval)
3950 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
3951 .addReg(scratch).addImm(0));
3952 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3953 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
3954 BB->addSuccessor(loop1MBB);
3955 BB->addSuccessor(exitMBB);
3961 MI->eraseFromParent(); // The instruction is gone now.
3967 ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
3968 unsigned Size, unsigned BinOpcode) const {
3969 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
3970 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3972 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3973 MachineFunction *MF = BB->getParent();
3974 MachineFunction::iterator It = BB;
3977 unsigned dest = MI->getOperand(0).getReg();
3978 unsigned ptr = MI->getOperand(1).getReg();
3979 unsigned incr = MI->getOperand(2).getReg();
3980 DebugLoc dl = MI->getDebugLoc();
3982 bool isThumb2 = Subtarget->isThumb2();
3983 unsigned ldrOpc, strOpc;
3985 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
3987 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
3988 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
3991 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
3992 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
3995 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
3996 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
4000 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
4001 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
4002 MF->insert(It, loopMBB);
4003 MF->insert(It, exitMBB);
4005 // Transfer the remainder of BB and its successor edges to exitMBB.
4006 exitMBB->splice(exitMBB->begin(), BB,
4007 llvm::next(MachineBasicBlock::iterator(MI)),
4009 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4011 MachineRegisterInfo &RegInfo = MF->getRegInfo();
4012 unsigned scratch = RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
4013 unsigned scratch2 = (!BinOpcode) ? incr :
4014 RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
4018 // fallthrough --> loopMBB
4019 BB->addSuccessor(loopMBB);
4023 // <binop> scratch2, dest, incr
4024 // strex scratch, scratch2, ptr
4027 // fallthrough --> exitMBB
4029 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
4031 // operand order needs to go the other way for NAND
4032 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr)
4033 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
4034 addReg(incr).addReg(dest)).addReg(0);
4036 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
4037 addReg(dest).addReg(incr)).addReg(0);
4040 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2)
4042 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4043 .addReg(scratch).addImm(0));
4044 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4045 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
4047 BB->addSuccessor(loopMBB);
4048 BB->addSuccessor(exitMBB);
4054 MI->eraseFromParent(); // The instruction is gone now.
4060 MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
4061 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
4062 E = MBB->succ_end(); I != E; ++I)
4065 llvm_unreachable("Expecting a BB with two successors!");
4069 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4070 MachineBasicBlock *BB) const {
4071 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4072 DebugLoc dl = MI->getDebugLoc();
4073 bool isThumb2 = Subtarget->isThumb2();
4074 switch (MI->getOpcode()) {
4077 llvm_unreachable("Unexpected instr type to insert");
4079 case ARM::ATOMIC_LOAD_ADD_I8:
4080 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
4081 case ARM::ATOMIC_LOAD_ADD_I16:
4082 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
4083 case ARM::ATOMIC_LOAD_ADD_I32:
4084 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
4086 case ARM::ATOMIC_LOAD_AND_I8:
4087 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
4088 case ARM::ATOMIC_LOAD_AND_I16:
4089 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
4090 case ARM::ATOMIC_LOAD_AND_I32:
4091 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
4093 case ARM::ATOMIC_LOAD_OR_I8:
4094 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
4095 case ARM::ATOMIC_LOAD_OR_I16:
4096 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
4097 case ARM::ATOMIC_LOAD_OR_I32:
4098 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
4100 case ARM::ATOMIC_LOAD_XOR_I8:
4101 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
4102 case ARM::ATOMIC_LOAD_XOR_I16:
4103 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
4104 case ARM::ATOMIC_LOAD_XOR_I32:
4105 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
4107 case ARM::ATOMIC_LOAD_NAND_I8:
4108 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
4109 case ARM::ATOMIC_LOAD_NAND_I16:
4110 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
4111 case ARM::ATOMIC_LOAD_NAND_I32:
4112 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
4114 case ARM::ATOMIC_LOAD_SUB_I8:
4115 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
4116 case ARM::ATOMIC_LOAD_SUB_I16:
4117 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
4118 case ARM::ATOMIC_LOAD_SUB_I32:
4119 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
4121 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0);
4122 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0);
4123 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0);
4125 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1);
4126 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
4127 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
4129 case ARM::tMOVCCr_pseudo: {
4130 // To "insert" a SELECT_CC instruction, we actually have to insert the
4131 // diamond control-flow pattern. The incoming instruction knows the
4132 // destination vreg to set, the condition code register to branch on, the
4133 // true/false values to select between, and a branch opcode to use.
4134 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4135 MachineFunction::iterator It = BB;
4141 // cmpTY ccX, r1, r2
4143 // fallthrough --> copy0MBB
4144 MachineBasicBlock *thisMBB = BB;
4145 MachineFunction *F = BB->getParent();
4146 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4147 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
4148 F->insert(It, copy0MBB);
4149 F->insert(It, sinkMBB);
4151 // Transfer the remainder of BB and its successor edges to sinkMBB.
4152 sinkMBB->splice(sinkMBB->begin(), BB,
4153 llvm::next(MachineBasicBlock::iterator(MI)),
4155 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
4157 BB->addSuccessor(copy0MBB);
4158 BB->addSuccessor(sinkMBB);
4160 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
4161 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
4164 // %FalseValue = ...
4165 // # fallthrough to sinkMBB
4168 // Update machine-CFG edges
4169 BB->addSuccessor(sinkMBB);
4172 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
4175 BuildMI(*BB, BB->begin(), dl,
4176 TII->get(ARM::PHI), MI->getOperand(0).getReg())
4177 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
4178 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
4180 MI->eraseFromParent(); // The pseudo instruction is gone now.
4185 case ARM::BCCZi64: {
4186 // Compare both parts that make up the double comparison separately for
4188 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
4190 unsigned LHS1 = MI->getOperand(1).getReg();
4191 unsigned LHS2 = MI->getOperand(2).getReg();
4193 AddDefaultPred(BuildMI(BB, dl,
4194 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4195 .addReg(LHS1).addImm(0));
4196 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4197 .addReg(LHS2).addImm(0)
4198 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
4200 unsigned RHS1 = MI->getOperand(3).getReg();
4201 unsigned RHS2 = MI->getOperand(4).getReg();
4202 AddDefaultPred(BuildMI(BB, dl,
4203 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
4204 .addReg(LHS1).addReg(RHS1));
4205 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
4206 .addReg(LHS2).addReg(RHS2)
4207 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
4210 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB();
4211 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
4212 if (MI->getOperand(0).getImm() == ARMCC::NE)
4213 std::swap(destMBB, exitMBB);
4215 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4216 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
4217 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2B : ARM::B))
4220 MI->eraseFromParent(); // The pseudo instruction is gone now.
4226 //===----------------------------------------------------------------------===//
4227 // ARM Optimization Hooks
4228 //===----------------------------------------------------------------------===//
4231 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
4232 TargetLowering::DAGCombinerInfo &DCI) {
4233 SelectionDAG &DAG = DCI.DAG;
4234 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4235 EVT VT = N->getValueType(0);
4236 unsigned Opc = N->getOpcode();
4237 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
4238 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
4239 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
4240 ISD::CondCode CC = ISD::SETCC_INVALID;
4243 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
4245 SDValue CCOp = Slct.getOperand(0);
4246 if (CCOp.getOpcode() == ISD::SETCC)
4247 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
4250 bool DoXform = false;
4252 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
4255 if (LHS.getOpcode() == ISD::Constant &&
4256 cast<ConstantSDNode>(LHS)->isNullValue()) {
4258 } else if (CC != ISD::SETCC_INVALID &&
4259 RHS.getOpcode() == ISD::Constant &&
4260 cast<ConstantSDNode>(RHS)->isNullValue()) {
4261 std::swap(LHS, RHS);
4262 SDValue Op0 = Slct.getOperand(0);
4263 EVT OpVT = isSlctCC ? Op0.getValueType() :
4264 Op0.getOperand(0).getValueType();
4265 bool isInt = OpVT.isInteger();
4266 CC = ISD::getSetCCInverse(CC, isInt);
4268 if (!TLI.isCondCodeLegal(CC, OpVT))
4269 return SDValue(); // Inverse operator isn't legal.
4276 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
4278 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
4279 Slct.getOperand(0), Slct.getOperand(1), CC);
4280 SDValue CCOp = Slct.getOperand(0);
4282 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
4283 CCOp.getOperand(0), CCOp.getOperand(1), CC);
4284 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
4285 CCOp, OtherOp, Result);
4290 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
4291 /// operands N0 and N1. This is a helper for PerformADDCombine that is
4292 /// called with the default operands, and if that fails, with commuted
4294 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
4295 TargetLowering::DAGCombinerInfo &DCI) {
4296 SelectionDAG &DAG = DCI.DAG;
4298 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
4299 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
4300 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
4301 if (Result.getNode()) return Result;
4304 // fold (add (arm_neon_vabd a, b) c) -> (arm_neon_vaba c, a, b)
4305 EVT VT = N->getValueType(0);
4306 if (N0.getOpcode() == ISD::INTRINSIC_WO_CHAIN && VT.isInteger()) {
4307 unsigned IntNo = cast<ConstantSDNode>(N0.getOperand(0))->getZExtValue();
4308 if (IntNo == Intrinsic::arm_neon_vabds)
4309 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(), VT,
4310 DAG.getConstant(Intrinsic::arm_neon_vabas, MVT::i32),
4311 N1, N0.getOperand(1), N0.getOperand(2));
4312 if (IntNo == Intrinsic::arm_neon_vabdu)
4313 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(), VT,
4314 DAG.getConstant(Intrinsic::arm_neon_vabau, MVT::i32),
4315 N1, N0.getOperand(1), N0.getOperand(2));
4321 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
4323 static SDValue PerformADDCombine(SDNode *N,
4324 TargetLowering::DAGCombinerInfo &DCI) {
4325 SDValue N0 = N->getOperand(0);
4326 SDValue N1 = N->getOperand(1);
4328 // First try with the default operand order.
4329 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI);
4330 if (Result.getNode())
4333 // If that didn't work, try again with the operands commuted.
4334 return PerformADDCombineWithOperands(N, N1, N0, DCI);
4337 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
4339 static SDValue PerformSUBCombine(SDNode *N,
4340 TargetLowering::DAGCombinerInfo &DCI) {
4341 SDValue N0 = N->getOperand(0);
4342 SDValue N1 = N->getOperand(1);
4344 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
4345 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
4346 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
4347 if (Result.getNode()) return Result;
4353 static SDValue PerformMULCombine(SDNode *N,
4354 TargetLowering::DAGCombinerInfo &DCI,
4355 const ARMSubtarget *Subtarget) {
4356 SelectionDAG &DAG = DCI.DAG;
4358 if (Subtarget->isThumb1Only())
4361 if (DAG.getMachineFunction().
4362 getFunction()->hasFnAttr(Attribute::OptimizeForSize))
4365 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
4368 EVT VT = N->getValueType(0);
4372 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
4376 uint64_t MulAmt = C->getZExtValue();
4377 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt);
4378 ShiftAmt = ShiftAmt & (32 - 1);
4379 SDValue V = N->getOperand(0);
4380 DebugLoc DL = N->getDebugLoc();
4383 MulAmt >>= ShiftAmt;
4384 if (isPowerOf2_32(MulAmt - 1)) {
4385 // (mul x, 2^N + 1) => (add (shl x, N), x)
4386 Res = DAG.getNode(ISD::ADD, DL, VT,
4387 V, DAG.getNode(ISD::SHL, DL, VT,
4388 V, DAG.getConstant(Log2_32(MulAmt-1),
4390 } else if (isPowerOf2_32(MulAmt + 1)) {
4391 // (mul x, 2^N - 1) => (sub (shl x, N), x)
4392 Res = DAG.getNode(ISD::SUB, DL, VT,
4393 DAG.getNode(ISD::SHL, DL, VT,
4394 V, DAG.getConstant(Log2_32(MulAmt+1),
4401 Res = DAG.getNode(ISD::SHL, DL, VT, Res,
4402 DAG.getConstant(ShiftAmt, MVT::i32));
4404 // Do not add new nodes to DAG combiner worklist.
4405 DCI.CombineTo(N, Res, false);
4409 /// PerformORCombine - Target-specific dag combine xforms for ISD::OR
4410 static SDValue PerformORCombine(SDNode *N,
4411 TargetLowering::DAGCombinerInfo &DCI,
4412 const ARMSubtarget *Subtarget) {
4413 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when
4416 // BFI is only available on V6T2+
4417 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops())
4420 SelectionDAG &DAG = DCI.DAG;
4421 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
4422 DebugLoc DL = N->getDebugLoc();
4423 // 1) or (and A, mask), val => ARMbfi A, val, mask
4424 // iff (val & mask) == val
4426 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
4427 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2)
4428 // && CountPopulation_32(mask) == CountPopulation_32(~mask2)
4429 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2)
4430 // && CountPopulation_32(mask) == CountPopulation_32(~mask2)
4431 // (i.e., copy a bitfield value into another bitfield of the same width)
4432 if (N0.getOpcode() != ISD::AND)
4435 EVT VT = N->getValueType(0);
4440 // The value and the mask need to be constants so we can verify this is
4441 // actually a bitfield set. If the mask is 0xffff, we can do better
4442 // via a movt instruction, so don't use BFI in that case.
4443 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
4446 unsigned Mask = C->getZExtValue();
4450 // Case (1): or (and A, mask), val => ARMbfi A, val, mask
4451 if ((C = dyn_cast<ConstantSDNode>(N1))) {
4452 unsigned Val = C->getZExtValue();
4453 if (!ARM::isBitFieldInvertedMask(Mask) || (Val & ~Mask) != Val)
4455 Val >>= CountTrailingZeros_32(~Mask);
4457 Res = DAG.getNode(ARMISD::BFI, DL, VT, N0.getOperand(0),
4458 DAG.getConstant(Val, MVT::i32),
4459 DAG.getConstant(Mask, MVT::i32));
4461 // Do not add new nodes to DAG combiner worklist.
4462 DCI.CombineTo(N, Res, false);
4463 } else if (N1.getOpcode() == ISD::AND) {
4464 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
4465 C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
4468 unsigned Mask2 = C->getZExtValue();
4470 if (ARM::isBitFieldInvertedMask(Mask) &&
4471 ARM::isBitFieldInvertedMask(~Mask2) &&
4472 (CountPopulation_32(Mask) == CountPopulation_32(~Mask2))) {
4473 // The pack halfword instruction works better for masks that fit it,
4474 // so use that when it's available.
4475 if (Subtarget->hasT2ExtractPack() &&
4476 (Mask == 0xffff || Mask == 0xffff0000))
4479 unsigned lsb = CountTrailingZeros_32(Mask2);
4480 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
4481 DAG.getConstant(lsb, MVT::i32));
4482 Res = DAG.getNode(ARMISD::BFI, DL, VT, N0.getOperand(0), Res,
4483 DAG.getConstant(Mask, MVT::i32));
4484 // Do not add new nodes to DAG combiner worklist.
4485 DCI.CombineTo(N, Res, false);
4486 } else if (ARM::isBitFieldInvertedMask(~Mask) &&
4487 ARM::isBitFieldInvertedMask(Mask2) &&
4488 (CountPopulation_32(~Mask) == CountPopulation_32(Mask2))) {
4489 // The pack halfword instruction works better for masks that fit it,
4490 // so use that when it's available.
4491 if (Subtarget->hasT2ExtractPack() &&
4492 (Mask2 == 0xffff || Mask2 == 0xffff0000))
4495 unsigned lsb = CountTrailingZeros_32(Mask);
4496 Res = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0),
4497 DAG.getConstant(lsb, MVT::i32));
4498 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
4499 DAG.getConstant(Mask2, MVT::i32));
4500 // Do not add new nodes to DAG combiner worklist.
4501 DCI.CombineTo(N, Res, false);
4508 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
4509 /// ARMISD::VMOVRRD.
4510 static SDValue PerformVMOVRRDCombine(SDNode *N,
4511 TargetLowering::DAGCombinerInfo &DCI) {
4512 // fmrrd(fmdrr x, y) -> x,y
4513 SDValue InDouble = N->getOperand(0);
4514 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
4515 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
4519 /// PerformVDUPLANECombine - Target-specific dag combine xforms for
4520 /// ARMISD::VDUPLANE.
4521 static SDValue PerformVDUPLANECombine(SDNode *N,
4522 TargetLowering::DAGCombinerInfo &DCI) {
4523 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
4525 SDValue Op = N->getOperand(0);
4526 EVT VT = N->getValueType(0);
4528 // Ignore bit_converts.
4529 while (Op.getOpcode() == ISD::BIT_CONVERT)
4530 Op = Op.getOperand(0);
4531 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
4534 // Make sure the VMOV element size is not bigger than the VDUPLANE elements.
4535 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits();
4536 // The canonical VMOV for a zero vector uses a 32-bit element size.
4537 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4539 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
4541 if (EltSize > VT.getVectorElementType().getSizeInBits())
4544 SDValue Res = DCI.DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
4545 return DCI.CombineTo(N, Res, false);
4548 /// getVShiftImm - Check if this is a valid build_vector for the immediate
4549 /// operand of a vector shift operation, where all the elements of the
4550 /// build_vector must have the same constant integer value.
4551 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
4552 // Ignore bit_converts.
4553 while (Op.getOpcode() == ISD::BIT_CONVERT)
4554 Op = Op.getOperand(0);
4555 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
4556 APInt SplatBits, SplatUndef;
4557 unsigned SplatBitSize;
4559 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
4560 HasAnyUndefs, ElementBits) ||
4561 SplatBitSize > ElementBits)
4563 Cnt = SplatBits.getSExtValue();
4567 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
4568 /// operand of a vector shift left operation. That value must be in the range:
4569 /// 0 <= Value < ElementBits for a left shift; or
4570 /// 0 <= Value <= ElementBits for a long left shift.
4571 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
4572 assert(VT.isVector() && "vector shift count is not a vector type");
4573 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
4574 if (! getVShiftImm(Op, ElementBits, Cnt))
4576 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
4579 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
4580 /// operand of a vector shift right operation. For a shift opcode, the value
4581 /// is positive, but for an intrinsic the value count must be negative. The
4582 /// absolute value must be in the range:
4583 /// 1 <= |Value| <= ElementBits for a right shift; or
4584 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
4585 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
4587 assert(VT.isVector() && "vector shift count is not a vector type");
4588 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
4589 if (! getVShiftImm(Op, ElementBits, Cnt))
4593 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
4596 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
4597 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
4598 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
4601 // Don't do anything for most intrinsics.
4604 // Vector shifts: check for immediate versions and lower them.
4605 // Note: This is done during DAG combining instead of DAG legalizing because
4606 // the build_vectors for 64-bit vector element shift counts are generally
4607 // not legal, and it is hard to see their values after they get legalized to
4608 // loads from a constant pool.
4609 case Intrinsic::arm_neon_vshifts:
4610 case Intrinsic::arm_neon_vshiftu:
4611 case Intrinsic::arm_neon_vshiftls:
4612 case Intrinsic::arm_neon_vshiftlu:
4613 case Intrinsic::arm_neon_vshiftn:
4614 case Intrinsic::arm_neon_vrshifts:
4615 case Intrinsic::arm_neon_vrshiftu:
4616 case Intrinsic::arm_neon_vrshiftn:
4617 case Intrinsic::arm_neon_vqshifts:
4618 case Intrinsic::arm_neon_vqshiftu:
4619 case Intrinsic::arm_neon_vqshiftsu:
4620 case Intrinsic::arm_neon_vqshiftns:
4621 case Intrinsic::arm_neon_vqshiftnu:
4622 case Intrinsic::arm_neon_vqshiftnsu:
4623 case Intrinsic::arm_neon_vqrshiftns:
4624 case Intrinsic::arm_neon_vqrshiftnu:
4625 case Intrinsic::arm_neon_vqrshiftnsu: {
4626 EVT VT = N->getOperand(1).getValueType();
4628 unsigned VShiftOpc = 0;
4631 case Intrinsic::arm_neon_vshifts:
4632 case Intrinsic::arm_neon_vshiftu:
4633 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
4634 VShiftOpc = ARMISD::VSHL;
4637 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
4638 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
4639 ARMISD::VSHRs : ARMISD::VSHRu);
4644 case Intrinsic::arm_neon_vshiftls:
4645 case Intrinsic::arm_neon_vshiftlu:
4646 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
4648 llvm_unreachable("invalid shift count for vshll intrinsic");
4650 case Intrinsic::arm_neon_vrshifts:
4651 case Intrinsic::arm_neon_vrshiftu:
4652 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
4656 case Intrinsic::arm_neon_vqshifts:
4657 case Intrinsic::arm_neon_vqshiftu:
4658 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
4662 case Intrinsic::arm_neon_vqshiftsu:
4663 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
4665 llvm_unreachable("invalid shift count for vqshlu intrinsic");
4667 case Intrinsic::arm_neon_vshiftn:
4668 case Intrinsic::arm_neon_vrshiftn:
4669 case Intrinsic::arm_neon_vqshiftns:
4670 case Intrinsic::arm_neon_vqshiftnu:
4671 case Intrinsic::arm_neon_vqshiftnsu:
4672 case Intrinsic::arm_neon_vqrshiftns:
4673 case Intrinsic::arm_neon_vqrshiftnu:
4674 case Intrinsic::arm_neon_vqrshiftnsu:
4675 // Narrowing shifts require an immediate right shift.
4676 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
4678 llvm_unreachable("invalid shift count for narrowing vector shift "
4682 llvm_unreachable("unhandled vector shift");
4686 case Intrinsic::arm_neon_vshifts:
4687 case Intrinsic::arm_neon_vshiftu:
4688 // Opcode already set above.
4690 case Intrinsic::arm_neon_vshiftls:
4691 case Intrinsic::arm_neon_vshiftlu:
4692 if (Cnt == VT.getVectorElementType().getSizeInBits())
4693 VShiftOpc = ARMISD::VSHLLi;
4695 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
4696 ARMISD::VSHLLs : ARMISD::VSHLLu);
4698 case Intrinsic::arm_neon_vshiftn:
4699 VShiftOpc = ARMISD::VSHRN; break;
4700 case Intrinsic::arm_neon_vrshifts:
4701 VShiftOpc = ARMISD::VRSHRs; break;
4702 case Intrinsic::arm_neon_vrshiftu:
4703 VShiftOpc = ARMISD::VRSHRu; break;
4704 case Intrinsic::arm_neon_vrshiftn:
4705 VShiftOpc = ARMISD::VRSHRN; break;
4706 case Intrinsic::arm_neon_vqshifts:
4707 VShiftOpc = ARMISD::VQSHLs; break;
4708 case Intrinsic::arm_neon_vqshiftu:
4709 VShiftOpc = ARMISD::VQSHLu; break;
4710 case Intrinsic::arm_neon_vqshiftsu:
4711 VShiftOpc = ARMISD::VQSHLsu; break;
4712 case Intrinsic::arm_neon_vqshiftns:
4713 VShiftOpc = ARMISD::VQSHRNs; break;
4714 case Intrinsic::arm_neon_vqshiftnu:
4715 VShiftOpc = ARMISD::VQSHRNu; break;
4716 case Intrinsic::arm_neon_vqshiftnsu:
4717 VShiftOpc = ARMISD::VQSHRNsu; break;
4718 case Intrinsic::arm_neon_vqrshiftns:
4719 VShiftOpc = ARMISD::VQRSHRNs; break;
4720 case Intrinsic::arm_neon_vqrshiftnu:
4721 VShiftOpc = ARMISD::VQRSHRNu; break;
4722 case Intrinsic::arm_neon_vqrshiftnsu:
4723 VShiftOpc = ARMISD::VQRSHRNsu; break;
4726 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
4727 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
4730 case Intrinsic::arm_neon_vshiftins: {
4731 EVT VT = N->getOperand(1).getValueType();
4733 unsigned VShiftOpc = 0;
4735 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
4736 VShiftOpc = ARMISD::VSLI;
4737 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
4738 VShiftOpc = ARMISD::VSRI;
4740 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
4743 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
4744 N->getOperand(1), N->getOperand(2),
4745 DAG.getConstant(Cnt, MVT::i32));
4748 case Intrinsic::arm_neon_vqrshifts:
4749 case Intrinsic::arm_neon_vqrshiftu:
4750 // No immediate versions of these to check for.
4757 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
4758 /// lowers them. As with the vector shift intrinsics, this is done during DAG
4759 /// combining instead of DAG legalizing because the build_vectors for 64-bit
4760 /// vector element shift counts are generally not legal, and it is hard to see
4761 /// their values after they get legalized to loads from a constant pool.
4762 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
4763 const ARMSubtarget *ST) {
4764 EVT VT = N->getValueType(0);
4766 // Nothing to be done for scalar shifts.
4767 if (! VT.isVector())
4770 assert(ST->hasNEON() && "unexpected vector shift");
4773 switch (N->getOpcode()) {
4774 default: llvm_unreachable("unexpected shift opcode");
4777 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
4778 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
4779 DAG.getConstant(Cnt, MVT::i32));
4784 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
4785 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
4786 ARMISD::VSHRs : ARMISD::VSHRu);
4787 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
4788 DAG.getConstant(Cnt, MVT::i32));
4794 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
4795 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
4796 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
4797 const ARMSubtarget *ST) {
4798 SDValue N0 = N->getOperand(0);
4800 // Check for sign- and zero-extensions of vector extract operations of 8-
4801 // and 16-bit vector elements. NEON supports these directly. They are
4802 // handled during DAG combining because type legalization will promote them
4803 // to 32-bit types and it is messy to recognize the operations after that.
4804 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
4805 SDValue Vec = N0.getOperand(0);
4806 SDValue Lane = N0.getOperand(1);
4807 EVT VT = N->getValueType(0);
4808 EVT EltVT = N0.getValueType();
4809 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4811 if (VT == MVT::i32 &&
4812 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
4813 TLI.isTypeLegal(Vec.getValueType())) {
4816 switch (N->getOpcode()) {
4817 default: llvm_unreachable("unexpected opcode");
4818 case ISD::SIGN_EXTEND:
4819 Opc = ARMISD::VGETLANEs;
4821 case ISD::ZERO_EXTEND:
4822 case ISD::ANY_EXTEND:
4823 Opc = ARMISD::VGETLANEu;
4826 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
4833 /// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
4834 /// to match f32 max/min patterns to use NEON vmax/vmin instructions.
4835 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
4836 const ARMSubtarget *ST) {
4837 // If the target supports NEON, try to use vmax/vmin instructions for f32
4838 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set,
4839 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
4840 // a NaN; only do the transformation when it matches that behavior.
4842 // For now only do this when using NEON for FP operations; if using VFP, it
4843 // is not obvious that the benefit outweighs the cost of switching to the
4845 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
4846 N->getValueType(0) != MVT::f32)
4849 SDValue CondLHS = N->getOperand(0);
4850 SDValue CondRHS = N->getOperand(1);
4851 SDValue LHS = N->getOperand(2);
4852 SDValue RHS = N->getOperand(3);
4853 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
4855 unsigned Opcode = 0;
4857 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
4858 IsReversed = false; // x CC y ? x : y
4859 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
4860 IsReversed = true ; // x CC y ? y : x
4874 // If LHS is NaN, an ordered comparison will be false and the result will
4875 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
4876 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
4877 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
4878 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
4880 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
4881 // will return -0, so vmin can only be used for unsafe math or if one of
4882 // the operands is known to be nonzero.
4883 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
4885 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
4887 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
4896 // If LHS is NaN, an ordered comparison will be false and the result will
4897 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
4898 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
4899 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
4900 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
4902 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
4903 // will return +0, so vmax can only be used for unsafe math or if one of
4904 // the operands is known to be nonzero.
4905 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
4907 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
4909 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
4915 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS);
4918 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
4919 DAGCombinerInfo &DCI) const {
4920 switch (N->getOpcode()) {
4922 case ISD::ADD: return PerformADDCombine(N, DCI);
4923 case ISD::SUB: return PerformSUBCombine(N, DCI);
4924 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
4925 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
4926 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
4927 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
4928 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
4931 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
4932 case ISD::SIGN_EXTEND:
4933 case ISD::ZERO_EXTEND:
4934 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
4935 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
4940 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
4941 if (!Subtarget->hasV6Ops())
4942 // Pre-v6 does not support unaligned mem access.
4945 // v6+ may or may not support unaligned mem access depending on the system
4947 // FIXME: This is pretty conservative. Should we provide cmdline option to
4948 // control the behaviour?
4949 if (!Subtarget->isTargetDarwin())
4952 switch (VT.getSimpleVT().SimpleTy) {
4959 // FIXME: VLD1 etc with standard alignment is legal.
4963 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
4968 switch (VT.getSimpleVT().SimpleTy) {
4969 default: return false;
4984 if ((V & (Scale - 1)) != 0)
4987 return V == (V & ((1LL << 5) - 1));
4990 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
4991 const ARMSubtarget *Subtarget) {
4998 switch (VT.getSimpleVT().SimpleTy) {
4999 default: return false;
5004 // + imm12 or - imm8
5006 return V == (V & ((1LL << 8) - 1));
5007 return V == (V & ((1LL << 12) - 1));
5010 // Same as ARM mode. FIXME: NEON?
5011 if (!Subtarget->hasVFP2())
5016 return V == (V & ((1LL << 8) - 1));
5020 /// isLegalAddressImmediate - Return true if the integer value can be used
5021 /// as the offset of the target addressing mode for load / store of the
5023 static bool isLegalAddressImmediate(int64_t V, EVT VT,
5024 const ARMSubtarget *Subtarget) {
5031 if (Subtarget->isThumb1Only())
5032 return isLegalT1AddressImmediate(V, VT);
5033 else if (Subtarget->isThumb2())
5034 return isLegalT2AddressImmediate(V, VT, Subtarget);
5039 switch (VT.getSimpleVT().SimpleTy) {
5040 default: return false;
5045 return V == (V & ((1LL << 12) - 1));
5048 return V == (V & ((1LL << 8) - 1));
5051 if (!Subtarget->hasVFP2()) // FIXME: NEON?
5056 return V == (V & ((1LL << 8) - 1));
5060 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
5062 int Scale = AM.Scale;
5066 switch (VT.getSimpleVT().SimpleTy) {
5067 default: return false;
5076 return Scale == 2 || Scale == 4 || Scale == 8;
5079 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
5083 // Note, we allow "void" uses (basically, uses that aren't loads or
5084 // stores), because arm allows folding a scale into many arithmetic
5085 // operations. This should be made more precise and revisited later.
5087 // Allow r << imm, but the imm has to be a multiple of two.
5088 if (Scale & 1) return false;
5089 return isPowerOf2_32(Scale);
5093 /// isLegalAddressingMode - Return true if the addressing mode represented
5094 /// by AM is legal for this target, for a load/store of the specified type.
5095 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
5096 const Type *Ty) const {
5097 EVT VT = getValueType(Ty, true);
5098 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
5101 // Can never fold addr of global into load/store.
5106 case 0: // no scale reg, must be "r+i" or "r", or "i".
5109 if (Subtarget->isThumb1Only())
5113 // ARM doesn't support any R+R*scale+imm addr modes.
5120 if (Subtarget->isThumb2())
5121 return isLegalT2ScaledAddressingMode(AM, VT);
5123 int Scale = AM.Scale;
5124 switch (VT.getSimpleVT().SimpleTy) {
5125 default: return false;
5129 if (Scale < 0) Scale = -Scale;
5133 return isPowerOf2_32(Scale & ~1);
5137 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
5142 // Note, we allow "void" uses (basically, uses that aren't loads or
5143 // stores), because arm allows folding a scale into many arithmetic
5144 // operations. This should be made more precise and revisited later.
5146 // Allow r << imm, but the imm has to be a multiple of two.
5147 if (Scale & 1) return false;
5148 return isPowerOf2_32(Scale);
5155 /// isLegalICmpImmediate - Return true if the specified immediate is legal
5156 /// icmp immediate, that is the target has icmp instructions which can compare
5157 /// a register against the immediate without having to materialize the
5158 /// immediate into a register.
5159 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
5160 if (!Subtarget->isThumb())
5161 return ARM_AM::getSOImmVal(Imm) != -1;
5162 if (Subtarget->isThumb2())
5163 return ARM_AM::getT2SOImmVal(Imm) != -1;
5164 return Imm >= 0 && Imm <= 255;
5167 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
5168 bool isSEXTLoad, SDValue &Base,
5169 SDValue &Offset, bool &isInc,
5170 SelectionDAG &DAG) {
5171 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
5174 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
5176 Base = Ptr->getOperand(0);
5177 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
5178 int RHSC = (int)RHS->getZExtValue();
5179 if (RHSC < 0 && RHSC > -256) {
5180 assert(Ptr->getOpcode() == ISD::ADD);
5182 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
5186 isInc = (Ptr->getOpcode() == ISD::ADD);
5187 Offset = Ptr->getOperand(1);
5189 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
5191 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
5192 int RHSC = (int)RHS->getZExtValue();
5193 if (RHSC < 0 && RHSC > -0x1000) {
5194 assert(Ptr->getOpcode() == ISD::ADD);
5196 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
5197 Base = Ptr->getOperand(0);
5202 if (Ptr->getOpcode() == ISD::ADD) {
5204 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
5205 if (ShOpcVal != ARM_AM::no_shift) {
5206 Base = Ptr->getOperand(1);
5207 Offset = Ptr->getOperand(0);
5209 Base = Ptr->getOperand(0);
5210 Offset = Ptr->getOperand(1);
5215 isInc = (Ptr->getOpcode() == ISD::ADD);
5216 Base = Ptr->getOperand(0);
5217 Offset = Ptr->getOperand(1);
5221 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
5225 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
5226 bool isSEXTLoad, SDValue &Base,
5227 SDValue &Offset, bool &isInc,
5228 SelectionDAG &DAG) {
5229 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
5232 Base = Ptr->getOperand(0);
5233 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
5234 int RHSC = (int)RHS->getZExtValue();
5235 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
5236 assert(Ptr->getOpcode() == ISD::ADD);
5238 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
5240 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
5241 isInc = Ptr->getOpcode() == ISD::ADD;
5242 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
5250 /// getPreIndexedAddressParts - returns true by value, base pointer and
5251 /// offset pointer and addressing mode by reference if the node's address
5252 /// can be legally represented as pre-indexed load / store address.
5254 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
5256 ISD::MemIndexedMode &AM,
5257 SelectionDAG &DAG) const {
5258 if (Subtarget->isThumb1Only())
5263 bool isSEXTLoad = false;
5264 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5265 Ptr = LD->getBasePtr();
5266 VT = LD->getMemoryVT();
5267 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
5268 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5269 Ptr = ST->getBasePtr();
5270 VT = ST->getMemoryVT();
5275 bool isLegal = false;
5276 if (Subtarget->isThumb2())
5277 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
5278 Offset, isInc, DAG);
5280 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
5281 Offset, isInc, DAG);
5285 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
5289 /// getPostIndexedAddressParts - returns true by value, base pointer and
5290 /// offset pointer and addressing mode by reference if this node can be
5291 /// combined with a load / store to form a post-indexed load / store.
5292 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
5295 ISD::MemIndexedMode &AM,
5296 SelectionDAG &DAG) const {
5297 if (Subtarget->isThumb1Only())
5302 bool isSEXTLoad = false;
5303 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5304 VT = LD->getMemoryVT();
5305 Ptr = LD->getBasePtr();
5306 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
5307 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5308 VT = ST->getMemoryVT();
5309 Ptr = ST->getBasePtr();
5314 bool isLegal = false;
5315 if (Subtarget->isThumb2())
5316 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
5319 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
5325 // Swap base ptr and offset to catch more post-index load / store when
5326 // it's legal. In Thumb2 mode, offset must be an immediate.
5327 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
5328 !Subtarget->isThumb2())
5329 std::swap(Base, Offset);
5331 // Post-indexed load / store update the base pointer.
5336 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
5340 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
5344 const SelectionDAG &DAG,
5345 unsigned Depth) const {
5346 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
5347 switch (Op.getOpcode()) {
5349 case ARMISD::CMOV: {
5350 // Bits are known zero/one if known on the LHS and RHS.
5351 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
5352 if (KnownZero == 0 && KnownOne == 0) return;
5354 APInt KnownZeroRHS, KnownOneRHS;
5355 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
5356 KnownZeroRHS, KnownOneRHS, Depth+1);
5357 KnownZero &= KnownZeroRHS;
5358 KnownOne &= KnownOneRHS;
5364 //===----------------------------------------------------------------------===//
5365 // ARM Inline Assembly Support
5366 //===----------------------------------------------------------------------===//
5368 /// getConstraintType - Given a constraint letter, return the type of
5369 /// constraint it is for this target.
5370 ARMTargetLowering::ConstraintType
5371 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
5372 if (Constraint.size() == 1) {
5373 switch (Constraint[0]) {
5375 case 'l': return C_RegisterClass;
5376 case 'w': return C_RegisterClass;
5379 return TargetLowering::getConstraintType(Constraint);
5382 std::pair<unsigned, const TargetRegisterClass*>
5383 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
5385 if (Constraint.size() == 1) {
5386 // GCC ARM Constraint Letters
5387 switch (Constraint[0]) {
5389 if (Subtarget->isThumb())
5390 return std::make_pair(0U, ARM::tGPRRegisterClass);
5392 return std::make_pair(0U, ARM::GPRRegisterClass);
5394 return std::make_pair(0U, ARM::GPRRegisterClass);
5397 return std::make_pair(0U, ARM::SPRRegisterClass);
5398 if (VT.getSizeInBits() == 64)
5399 return std::make_pair(0U, ARM::DPRRegisterClass);
5400 if (VT.getSizeInBits() == 128)
5401 return std::make_pair(0U, ARM::QPRRegisterClass);
5405 if (StringRef("{cc}").equals_lower(Constraint))
5406 return std::make_pair(unsigned(ARM::CPSR), ARM::CCRRegisterClass);
5408 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
5411 std::vector<unsigned> ARMTargetLowering::
5412 getRegClassForInlineAsmConstraint(const std::string &Constraint,
5414 if (Constraint.size() != 1)
5415 return std::vector<unsigned>();
5417 switch (Constraint[0]) { // GCC ARM Constraint Letters
5420 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
5421 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
5424 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
5425 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
5426 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
5427 ARM::R12, ARM::LR, 0);
5430 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
5431 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
5432 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
5433 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
5434 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
5435 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
5436 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
5437 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
5438 if (VT.getSizeInBits() == 64)
5439 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
5440 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
5441 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
5442 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
5443 if (VT.getSizeInBits() == 128)
5444 return make_vector<unsigned>(ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
5445 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 0);
5449 return std::vector<unsigned>();
5452 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
5453 /// vector. If it is invalid, don't add anything to Ops.
5454 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
5456 std::vector<SDValue>&Ops,
5457 SelectionDAG &DAG) const {
5458 SDValue Result(0, 0);
5460 switch (Constraint) {
5462 case 'I': case 'J': case 'K': case 'L':
5463 case 'M': case 'N': case 'O':
5464 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
5468 int64_t CVal64 = C->getSExtValue();
5469 int CVal = (int) CVal64;
5470 // None of these constraints allow values larger than 32 bits. Check
5471 // that the value fits in an int.
5475 switch (Constraint) {
5477 if (Subtarget->isThumb1Only()) {
5478 // This must be a constant between 0 and 255, for ADD
5480 if (CVal >= 0 && CVal <= 255)
5482 } else if (Subtarget->isThumb2()) {
5483 // A constant that can be used as an immediate value in a
5484 // data-processing instruction.
5485 if (ARM_AM::getT2SOImmVal(CVal) != -1)
5488 // A constant that can be used as an immediate value in a
5489 // data-processing instruction.
5490 if (ARM_AM::getSOImmVal(CVal) != -1)
5496 if (Subtarget->isThumb()) { // FIXME thumb2
5497 // This must be a constant between -255 and -1, for negated ADD
5498 // immediates. This can be used in GCC with an "n" modifier that
5499 // prints the negated value, for use with SUB instructions. It is
5500 // not useful otherwise but is implemented for compatibility.
5501 if (CVal >= -255 && CVal <= -1)
5504 // This must be a constant between -4095 and 4095. It is not clear
5505 // what this constraint is intended for. Implemented for
5506 // compatibility with GCC.
5507 if (CVal >= -4095 && CVal <= 4095)
5513 if (Subtarget->isThumb1Only()) {
5514 // A 32-bit value where only one byte has a nonzero value. Exclude
5515 // zero to match GCC. This constraint is used by GCC internally for
5516 // constants that can be loaded with a move/shift combination.
5517 // It is not useful otherwise but is implemented for compatibility.
5518 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
5520 } else if (Subtarget->isThumb2()) {
5521 // A constant whose bitwise inverse can be used as an immediate
5522 // value in a data-processing instruction. This can be used in GCC
5523 // with a "B" modifier that prints the inverted value, for use with
5524 // BIC and MVN instructions. It is not useful otherwise but is
5525 // implemented for compatibility.
5526 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
5529 // A constant whose bitwise inverse can be used as an immediate
5530 // value in a data-processing instruction. This can be used in GCC
5531 // with a "B" modifier that prints the inverted value, for use with
5532 // BIC and MVN instructions. It is not useful otherwise but is
5533 // implemented for compatibility.
5534 if (ARM_AM::getSOImmVal(~CVal) != -1)
5540 if (Subtarget->isThumb1Only()) {
5541 // This must be a constant between -7 and 7,
5542 // for 3-operand ADD/SUB immediate instructions.
5543 if (CVal >= -7 && CVal < 7)
5545 } else if (Subtarget->isThumb2()) {
5546 // A constant whose negation can be used as an immediate value in a
5547 // data-processing instruction. This can be used in GCC with an "n"
5548 // modifier that prints the negated value, for use with SUB
5549 // instructions. It is not useful otherwise but is implemented for
5551 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
5554 // A constant whose negation can be used as an immediate value in a
5555 // data-processing instruction. This can be used in GCC with an "n"
5556 // modifier that prints the negated value, for use with SUB
5557 // instructions. It is not useful otherwise but is implemented for
5559 if (ARM_AM::getSOImmVal(-CVal) != -1)
5565 if (Subtarget->isThumb()) { // FIXME thumb2
5566 // This must be a multiple of 4 between 0 and 1020, for
5567 // ADD sp + immediate.
5568 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
5571 // A power of two or a constant between 0 and 32. This is used in
5572 // GCC for the shift amount on shifted register operands, but it is
5573 // useful in general for any shift amounts.
5574 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
5580 if (Subtarget->isThumb()) { // FIXME thumb2
5581 // This must be a constant between 0 and 31, for shift amounts.
5582 if (CVal >= 0 && CVal <= 31)
5588 if (Subtarget->isThumb()) { // FIXME thumb2
5589 // This must be a multiple of 4 between -508 and 508, for
5590 // ADD/SUB sp = sp + immediate.
5591 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
5596 Result = DAG.getTargetConstant(CVal, Op.getValueType());
5600 if (Result.getNode()) {
5601 Ops.push_back(Result);
5604 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
5608 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
5609 // The ARM target isn't yet aware of offsets.
5613 int ARM::getVFPf32Imm(const APFloat &FPImm) {
5614 APInt Imm = FPImm.bitcastToAPInt();
5615 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
5616 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127
5617 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits
5619 // We can handle 4 bits of mantissa.
5620 // mantissa = (16+UInt(e:f:g:h))/16.
5621 if (Mantissa & 0x7ffff)
5624 if ((Mantissa & 0xf) != Mantissa)
5627 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
5628 if (Exp < -3 || Exp > 4)
5630 Exp = ((Exp+3) & 0x7) ^ 4;
5632 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
5635 int ARM::getVFPf64Imm(const APFloat &FPImm) {
5636 APInt Imm = FPImm.bitcastToAPInt();
5637 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
5638 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
5639 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffLL;
5641 // We can handle 4 bits of mantissa.
5642 // mantissa = (16+UInt(e:f:g:h))/16.
5643 if (Mantissa & 0xffffffffffffLL)
5646 if ((Mantissa & 0xf) != Mantissa)
5649 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
5650 if (Exp < -3 || Exp > 4)
5652 Exp = ((Exp+3) & 0x7) ^ 4;
5654 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
5657 bool ARM::isBitFieldInvertedMask(unsigned v) {
5658 if (v == 0xffffffff)
5660 // there can be 1's on either or both "outsides", all the "inside"
5662 unsigned int lsb = 0, msb = 31;
5663 while (v & (1 << msb)) --msb;
5664 while (v & (1 << lsb)) ++lsb;
5665 for (unsigned int i = lsb; i <= msb; ++i) {
5672 /// isFPImmLegal - Returns true if the target can instruction select the
5673 /// specified FP immediate natively. If false, the legalizer will
5674 /// materialize the FP immediate as a load from a constant pool.
5675 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
5676 if (!Subtarget->hasVFP3())
5679 return ARM::getVFPf32Imm(Imm) != -1;
5681 return ARM::getVFPf64Imm(Imm) != -1;