1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "arm-isel"
16 #include "ARMISelLowering.h"
18 #include "ARMCallingConv.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMPerfectShuffle.h"
22 #include "ARMSubtarget.h"
23 #include "ARMTargetMachine.h"
24 #include "ARMTargetObjectFile.h"
25 #include "MCTargetDesc/ARMAddressingModes.h"
26 #include "llvm/ADT/Statistic.h"
27 #include "llvm/ADT/StringExtras.h"
28 #include "llvm/CodeGen/CallingConvLower.h"
29 #include "llvm/CodeGen/IntrinsicLowering.h"
30 #include "llvm/CodeGen/MachineBasicBlock.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineInstrBuilder.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SelectionDAG.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalValue.h"
41 #include "llvm/IR/Instruction.h"
42 #include "llvm/IR/Instructions.h"
43 #include "llvm/IR/Intrinsics.h"
44 #include "llvm/IR/Type.h"
45 #include "llvm/MC/MCSectionMachO.h"
46 #include "llvm/Support/CommandLine.h"
47 #include "llvm/Support/ErrorHandling.h"
48 #include "llvm/Support/MathExtras.h"
49 #include "llvm/Support/raw_ostream.h"
50 #include "llvm/Target/TargetOptions.h"
54 STATISTIC(NumTailCalls, "Number of tail calls");
55 STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt");
56 STATISTIC(NumLoopByVals, "Number of loops generated for byval arguments");
58 // This option should go away when tail calls fully work.
60 EnableARMTailCalls("arm-tail-calls", cl::Hidden,
61 cl::desc("Generate tail calls (TEMPORARY OPTION)."),
65 EnableARMLongCalls("arm-long-calls", cl::Hidden,
66 cl::desc("Generate calls via indirect call instructions"),
70 ARMInterworking("arm-interworking", cl::Hidden,
71 cl::desc("Enable / disable ARM interworking (for debugging only)"),
75 class ARMCCState : public CCState {
77 ARMCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
78 const TargetMachine &TM, SmallVectorImpl<CCValAssign> &locs,
79 LLVMContext &C, ParmContext PC)
80 : CCState(CC, isVarArg, MF, TM, locs, C) {
81 assert(((PC == Call) || (PC == Prologue)) &&
82 "ARMCCState users must specify whether their context is call"
83 "or prologue generation.");
89 // The APCS parameter registers.
90 static const uint16_t GPRArgRegs[] = {
91 ARM::R0, ARM::R1, ARM::R2, ARM::R3
94 void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT,
95 MVT PromotedBitwiseVT) {
96 if (VT != PromotedLdStVT) {
97 setOperationAction(ISD::LOAD, VT, Promote);
98 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
100 setOperationAction(ISD::STORE, VT, Promote);
101 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
104 MVT ElemTy = VT.getVectorElementType();
105 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
106 setOperationAction(ISD::SETCC, VT, Custom);
107 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
108 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
109 if (ElemTy == MVT::i32) {
110 setOperationAction(ISD::SINT_TO_FP, VT, Custom);
111 setOperationAction(ISD::UINT_TO_FP, VT, Custom);
112 setOperationAction(ISD::FP_TO_SINT, VT, Custom);
113 setOperationAction(ISD::FP_TO_UINT, VT, Custom);
115 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
116 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
117 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
118 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
120 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
121 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
122 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
123 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
124 setOperationAction(ISD::SELECT, VT, Expand);
125 setOperationAction(ISD::SELECT_CC, VT, Expand);
126 setOperationAction(ISD::VSELECT, VT, Expand);
127 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
128 if (VT.isInteger()) {
129 setOperationAction(ISD::SHL, VT, Custom);
130 setOperationAction(ISD::SRA, VT, Custom);
131 setOperationAction(ISD::SRL, VT, Custom);
134 // Promote all bit-wise operations.
135 if (VT.isInteger() && VT != PromotedBitwiseVT) {
136 setOperationAction(ISD::AND, VT, Promote);
137 AddPromotedToType (ISD::AND, VT, PromotedBitwiseVT);
138 setOperationAction(ISD::OR, VT, Promote);
139 AddPromotedToType (ISD::OR, VT, PromotedBitwiseVT);
140 setOperationAction(ISD::XOR, VT, Promote);
141 AddPromotedToType (ISD::XOR, VT, PromotedBitwiseVT);
144 // Neon does not support vector divide/remainder operations.
145 setOperationAction(ISD::SDIV, VT, Expand);
146 setOperationAction(ISD::UDIV, VT, Expand);
147 setOperationAction(ISD::FDIV, VT, Expand);
148 setOperationAction(ISD::SREM, VT, Expand);
149 setOperationAction(ISD::UREM, VT, Expand);
150 setOperationAction(ISD::FREM, VT, Expand);
153 void ARMTargetLowering::addDRTypeForNEON(MVT VT) {
154 addRegisterClass(VT, &ARM::DPRRegClass);
155 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
158 void ARMTargetLowering::addQRTypeForNEON(MVT VT) {
159 addRegisterClass(VT, &ARM::DPairRegClass);
160 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
163 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
164 if (TM.getSubtarget<ARMSubtarget>().isTargetMachO())
165 return new TargetLoweringObjectFileMachO();
167 return new ARMElfTargetObjectFile();
170 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
171 : TargetLowering(TM, createTLOF(TM)) {
172 Subtarget = &TM.getSubtarget<ARMSubtarget>();
173 RegInfo = TM.getRegisterInfo();
174 Itins = TM.getInstrItineraryData();
176 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
178 if (Subtarget->isTargetMachO()) {
179 // Uses VFP for Thumb libfuncs if available.
180 if (Subtarget->isThumb() && Subtarget->hasVFP2() &&
181 Subtarget->hasARMOps()) {
182 // Single-precision floating-point arithmetic.
183 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
184 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
185 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
186 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
188 // Double-precision floating-point arithmetic.
189 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
190 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
191 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
192 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
194 // Single-precision comparisons.
195 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
196 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
197 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
198 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
199 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
200 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
201 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
202 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
204 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
205 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
206 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
207 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
208 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
209 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
210 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
211 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
213 // Double-precision comparisons.
214 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
215 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
216 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
217 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
218 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
219 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
220 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
221 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
223 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
224 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
225 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
226 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
227 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
228 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
229 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
230 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
232 // Floating-point to integer conversions.
233 // i64 conversions are done via library routines even when generating VFP
234 // instructions, so use the same ones.
235 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
236 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
237 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
238 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
240 // Conversions between floating types.
241 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
242 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
244 // Integer to floating-point conversions.
245 // i64 conversions are done via library routines even when generating VFP
246 // instructions, so use the same ones.
247 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
248 // e.g., __floatunsidf vs. __floatunssidfvfp.
249 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
250 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
251 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
252 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
256 // These libcalls are not available in 32-bit.
257 setLibcallName(RTLIB::SHL_I128, 0);
258 setLibcallName(RTLIB::SRL_I128, 0);
259 setLibcallName(RTLIB::SRA_I128, 0);
261 if (Subtarget->isAAPCS_ABI() && !Subtarget->isTargetMachO()) {
262 // Double-precision floating-point arithmetic helper functions
263 // RTABI chapter 4.1.2, Table 2
264 setLibcallName(RTLIB::ADD_F64, "__aeabi_dadd");
265 setLibcallName(RTLIB::DIV_F64, "__aeabi_ddiv");
266 setLibcallName(RTLIB::MUL_F64, "__aeabi_dmul");
267 setLibcallName(RTLIB::SUB_F64, "__aeabi_dsub");
268 setLibcallCallingConv(RTLIB::ADD_F64, CallingConv::ARM_AAPCS);
269 setLibcallCallingConv(RTLIB::DIV_F64, CallingConv::ARM_AAPCS);
270 setLibcallCallingConv(RTLIB::MUL_F64, CallingConv::ARM_AAPCS);
271 setLibcallCallingConv(RTLIB::SUB_F64, CallingConv::ARM_AAPCS);
273 // Double-precision floating-point comparison helper functions
274 // RTABI chapter 4.1.2, Table 3
275 setLibcallName(RTLIB::OEQ_F64, "__aeabi_dcmpeq");
276 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
277 setLibcallName(RTLIB::UNE_F64, "__aeabi_dcmpeq");
278 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETEQ);
279 setLibcallName(RTLIB::OLT_F64, "__aeabi_dcmplt");
280 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
281 setLibcallName(RTLIB::OLE_F64, "__aeabi_dcmple");
282 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
283 setLibcallName(RTLIB::OGE_F64, "__aeabi_dcmpge");
284 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
285 setLibcallName(RTLIB::OGT_F64, "__aeabi_dcmpgt");
286 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
287 setLibcallName(RTLIB::UO_F64, "__aeabi_dcmpun");
288 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
289 setLibcallName(RTLIB::O_F64, "__aeabi_dcmpun");
290 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
291 setLibcallCallingConv(RTLIB::OEQ_F64, CallingConv::ARM_AAPCS);
292 setLibcallCallingConv(RTLIB::UNE_F64, CallingConv::ARM_AAPCS);
293 setLibcallCallingConv(RTLIB::OLT_F64, CallingConv::ARM_AAPCS);
294 setLibcallCallingConv(RTLIB::OLE_F64, CallingConv::ARM_AAPCS);
295 setLibcallCallingConv(RTLIB::OGE_F64, CallingConv::ARM_AAPCS);
296 setLibcallCallingConv(RTLIB::OGT_F64, CallingConv::ARM_AAPCS);
297 setLibcallCallingConv(RTLIB::UO_F64, CallingConv::ARM_AAPCS);
298 setLibcallCallingConv(RTLIB::O_F64, CallingConv::ARM_AAPCS);
300 // Single-precision floating-point arithmetic helper functions
301 // RTABI chapter 4.1.2, Table 4
302 setLibcallName(RTLIB::ADD_F32, "__aeabi_fadd");
303 setLibcallName(RTLIB::DIV_F32, "__aeabi_fdiv");
304 setLibcallName(RTLIB::MUL_F32, "__aeabi_fmul");
305 setLibcallName(RTLIB::SUB_F32, "__aeabi_fsub");
306 setLibcallCallingConv(RTLIB::ADD_F32, CallingConv::ARM_AAPCS);
307 setLibcallCallingConv(RTLIB::DIV_F32, CallingConv::ARM_AAPCS);
308 setLibcallCallingConv(RTLIB::MUL_F32, CallingConv::ARM_AAPCS);
309 setLibcallCallingConv(RTLIB::SUB_F32, CallingConv::ARM_AAPCS);
311 // Single-precision floating-point comparison helper functions
312 // RTABI chapter 4.1.2, Table 5
313 setLibcallName(RTLIB::OEQ_F32, "__aeabi_fcmpeq");
314 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
315 setLibcallName(RTLIB::UNE_F32, "__aeabi_fcmpeq");
316 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETEQ);
317 setLibcallName(RTLIB::OLT_F32, "__aeabi_fcmplt");
318 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
319 setLibcallName(RTLIB::OLE_F32, "__aeabi_fcmple");
320 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
321 setLibcallName(RTLIB::OGE_F32, "__aeabi_fcmpge");
322 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
323 setLibcallName(RTLIB::OGT_F32, "__aeabi_fcmpgt");
324 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
325 setLibcallName(RTLIB::UO_F32, "__aeabi_fcmpun");
326 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
327 setLibcallName(RTLIB::O_F32, "__aeabi_fcmpun");
328 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
329 setLibcallCallingConv(RTLIB::OEQ_F32, CallingConv::ARM_AAPCS);
330 setLibcallCallingConv(RTLIB::UNE_F32, CallingConv::ARM_AAPCS);
331 setLibcallCallingConv(RTLIB::OLT_F32, CallingConv::ARM_AAPCS);
332 setLibcallCallingConv(RTLIB::OLE_F32, CallingConv::ARM_AAPCS);
333 setLibcallCallingConv(RTLIB::OGE_F32, CallingConv::ARM_AAPCS);
334 setLibcallCallingConv(RTLIB::OGT_F32, CallingConv::ARM_AAPCS);
335 setLibcallCallingConv(RTLIB::UO_F32, CallingConv::ARM_AAPCS);
336 setLibcallCallingConv(RTLIB::O_F32, CallingConv::ARM_AAPCS);
338 // Floating-point to integer conversions.
339 // RTABI chapter 4.1.2, Table 6
340 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz");
341 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz");
342 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz");
343 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz");
344 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz");
345 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz");
346 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz");
347 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz");
348 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I32, CallingConv::ARM_AAPCS);
349 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I32, CallingConv::ARM_AAPCS);
350 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I64, CallingConv::ARM_AAPCS);
351 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::ARM_AAPCS);
352 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I32, CallingConv::ARM_AAPCS);
353 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I32, CallingConv::ARM_AAPCS);
354 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I64, CallingConv::ARM_AAPCS);
355 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::ARM_AAPCS);
357 // Conversions between floating types.
358 // RTABI chapter 4.1.2, Table 7
359 setLibcallName(RTLIB::FPROUND_F64_F32, "__aeabi_d2f");
360 setLibcallName(RTLIB::FPEXT_F32_F64, "__aeabi_f2d");
361 setLibcallCallingConv(RTLIB::FPROUND_F64_F32, CallingConv::ARM_AAPCS);
362 setLibcallCallingConv(RTLIB::FPEXT_F32_F64, CallingConv::ARM_AAPCS);
364 // Integer to floating-point conversions.
365 // RTABI chapter 4.1.2, Table 8
366 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d");
367 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d");
368 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d");
369 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d");
370 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f");
371 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f");
372 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f");
373 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f");
374 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
375 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
376 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
377 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
378 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
379 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
380 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
381 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
383 // Long long helper functions
384 // RTABI chapter 4.2, Table 9
385 setLibcallName(RTLIB::MUL_I64, "__aeabi_lmul");
386 setLibcallName(RTLIB::SHL_I64, "__aeabi_llsl");
387 setLibcallName(RTLIB::SRL_I64, "__aeabi_llsr");
388 setLibcallName(RTLIB::SRA_I64, "__aeabi_lasr");
389 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::ARM_AAPCS);
390 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::ARM_AAPCS);
391 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::ARM_AAPCS);
392 setLibcallCallingConv(RTLIB::SHL_I64, CallingConv::ARM_AAPCS);
393 setLibcallCallingConv(RTLIB::SRL_I64, CallingConv::ARM_AAPCS);
394 setLibcallCallingConv(RTLIB::SRA_I64, CallingConv::ARM_AAPCS);
396 // Integer division functions
397 // RTABI chapter 4.3.1
398 setLibcallName(RTLIB::SDIV_I8, "__aeabi_idiv");
399 setLibcallName(RTLIB::SDIV_I16, "__aeabi_idiv");
400 setLibcallName(RTLIB::SDIV_I32, "__aeabi_idiv");
401 setLibcallName(RTLIB::SDIV_I64, "__aeabi_ldivmod");
402 setLibcallName(RTLIB::UDIV_I8, "__aeabi_uidiv");
403 setLibcallName(RTLIB::UDIV_I16, "__aeabi_uidiv");
404 setLibcallName(RTLIB::UDIV_I32, "__aeabi_uidiv");
405 setLibcallName(RTLIB::UDIV_I64, "__aeabi_uldivmod");
406 setLibcallCallingConv(RTLIB::SDIV_I8, CallingConv::ARM_AAPCS);
407 setLibcallCallingConv(RTLIB::SDIV_I16, CallingConv::ARM_AAPCS);
408 setLibcallCallingConv(RTLIB::SDIV_I32, CallingConv::ARM_AAPCS);
409 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::ARM_AAPCS);
410 setLibcallCallingConv(RTLIB::UDIV_I8, CallingConv::ARM_AAPCS);
411 setLibcallCallingConv(RTLIB::UDIV_I16, CallingConv::ARM_AAPCS);
412 setLibcallCallingConv(RTLIB::UDIV_I32, CallingConv::ARM_AAPCS);
413 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::ARM_AAPCS);
416 // RTABI chapter 4.3.4
417 setLibcallName(RTLIB::MEMCPY, "__aeabi_memcpy");
418 setLibcallName(RTLIB::MEMMOVE, "__aeabi_memmove");
419 setLibcallName(RTLIB::MEMSET, "__aeabi_memset");
420 setLibcallCallingConv(RTLIB::MEMCPY, CallingConv::ARM_AAPCS);
421 setLibcallCallingConv(RTLIB::MEMMOVE, CallingConv::ARM_AAPCS);
422 setLibcallCallingConv(RTLIB::MEMSET, CallingConv::ARM_AAPCS);
425 // Use divmod compiler-rt calls for iOS 5.0 and later.
426 if (Subtarget->getTargetTriple().isiOS() &&
427 !Subtarget->getTargetTriple().isOSVersionLT(5, 0)) {
428 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
429 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
432 if (Subtarget->isThumb1Only())
433 addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
435 addRegisterClass(MVT::i32, &ARM::GPRRegClass);
436 if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
437 !Subtarget->isThumb1Only()) {
438 addRegisterClass(MVT::f32, &ARM::SPRRegClass);
439 if (!Subtarget->isFPOnlySP())
440 addRegisterClass(MVT::f64, &ARM::DPRRegClass);
442 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
445 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
446 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
447 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
448 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
449 setTruncStoreAction((MVT::SimpleValueType)VT,
450 (MVT::SimpleValueType)InnerVT, Expand);
451 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
452 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
453 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
456 setOperationAction(ISD::ConstantFP, MVT::f32, Custom);
457 setOperationAction(ISD::ConstantFP, MVT::f64, Custom);
459 if (Subtarget->hasNEON()) {
460 addDRTypeForNEON(MVT::v2f32);
461 addDRTypeForNEON(MVT::v8i8);
462 addDRTypeForNEON(MVT::v4i16);
463 addDRTypeForNEON(MVT::v2i32);
464 addDRTypeForNEON(MVT::v1i64);
466 addQRTypeForNEON(MVT::v4f32);
467 addQRTypeForNEON(MVT::v2f64);
468 addQRTypeForNEON(MVT::v16i8);
469 addQRTypeForNEON(MVT::v8i16);
470 addQRTypeForNEON(MVT::v4i32);
471 addQRTypeForNEON(MVT::v2i64);
473 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
474 // neither Neon nor VFP support any arithmetic operations on it.
475 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
476 // supported for v4f32.
477 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
478 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
479 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
480 // FIXME: Code duplication: FDIV and FREM are expanded always, see
481 // ARMTargetLowering::addTypeForNEON method for details.
482 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
483 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
484 // FIXME: Create unittest.
485 // In another words, find a way when "copysign" appears in DAG with vector
487 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
488 // FIXME: Code duplication: SETCC has custom operation action, see
489 // ARMTargetLowering::addTypeForNEON method for details.
490 setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
491 // FIXME: Create unittest for FNEG and for FABS.
492 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
493 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
494 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
495 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
496 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
497 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
498 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
499 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
500 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
501 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
502 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
503 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
504 // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR.
505 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
506 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
507 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
508 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
509 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
510 setOperationAction(ISD::FMA, MVT::v2f64, Expand);
512 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
513 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
514 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
515 setOperationAction(ISD::FPOWI, MVT::v4f32, Expand);
516 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
517 setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
518 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
519 setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
520 setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
521 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
522 setOperationAction(ISD::FCEIL, MVT::v4f32, Expand);
523 setOperationAction(ISD::FTRUNC, MVT::v4f32, Expand);
524 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
525 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
526 setOperationAction(ISD::FFLOOR, MVT::v4f32, Expand);
528 // Mark v2f32 intrinsics.
529 setOperationAction(ISD::FSQRT, MVT::v2f32, Expand);
530 setOperationAction(ISD::FSIN, MVT::v2f32, Expand);
531 setOperationAction(ISD::FCOS, MVT::v2f32, Expand);
532 setOperationAction(ISD::FPOWI, MVT::v2f32, Expand);
533 setOperationAction(ISD::FPOW, MVT::v2f32, Expand);
534 setOperationAction(ISD::FLOG, MVT::v2f32, Expand);
535 setOperationAction(ISD::FLOG2, MVT::v2f32, Expand);
536 setOperationAction(ISD::FLOG10, MVT::v2f32, Expand);
537 setOperationAction(ISD::FEXP, MVT::v2f32, Expand);
538 setOperationAction(ISD::FEXP2, MVT::v2f32, Expand);
539 setOperationAction(ISD::FCEIL, MVT::v2f32, Expand);
540 setOperationAction(ISD::FTRUNC, MVT::v2f32, Expand);
541 setOperationAction(ISD::FRINT, MVT::v2f32, Expand);
542 setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Expand);
543 setOperationAction(ISD::FFLOOR, MVT::v2f32, Expand);
545 // Neon does not support some operations on v1i64 and v2i64 types.
546 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
547 // Custom handling for some quad-vector types to detect VMULL.
548 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
549 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
550 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
551 // Custom handling for some vector types to avoid expensive expansions
552 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
553 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
554 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
555 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
556 setOperationAction(ISD::SETCC, MVT::v1i64, Expand);
557 setOperationAction(ISD::SETCC, MVT::v2i64, Expand);
558 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
559 // a destination type that is wider than the source, and nor does
560 // it have a FP_TO_[SU]INT instruction with a narrower destination than
562 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
563 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
564 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
565 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
567 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
568 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand);
570 // NEON does not have single instruction CTPOP for vectors with element
571 // types wider than 8-bits. However, custom lowering can leverage the
572 // v8i8/v16i8 vcnt instruction.
573 setOperationAction(ISD::CTPOP, MVT::v2i32, Custom);
574 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
575 setOperationAction(ISD::CTPOP, MVT::v4i16, Custom);
576 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
578 // NEON only has FMA instructions as of VFP4.
579 if (!Subtarget->hasVFP4()) {
580 setOperationAction(ISD::FMA, MVT::v2f32, Expand);
581 setOperationAction(ISD::FMA, MVT::v4f32, Expand);
584 setTargetDAGCombine(ISD::INTRINSIC_VOID);
585 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
586 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
587 setTargetDAGCombine(ISD::SHL);
588 setTargetDAGCombine(ISD::SRL);
589 setTargetDAGCombine(ISD::SRA);
590 setTargetDAGCombine(ISD::SIGN_EXTEND);
591 setTargetDAGCombine(ISD::ZERO_EXTEND);
592 setTargetDAGCombine(ISD::ANY_EXTEND);
593 setTargetDAGCombine(ISD::SELECT_CC);
594 setTargetDAGCombine(ISD::BUILD_VECTOR);
595 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
596 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
597 setTargetDAGCombine(ISD::STORE);
598 setTargetDAGCombine(ISD::FP_TO_SINT);
599 setTargetDAGCombine(ISD::FP_TO_UINT);
600 setTargetDAGCombine(ISD::FDIV);
602 // It is legal to extload from v4i8 to v4i16 or v4i32.
603 MVT Tys[6] = {MVT::v8i8, MVT::v4i8, MVT::v2i8,
604 MVT::v4i16, MVT::v2i16,
606 for (unsigned i = 0; i < 6; ++i) {
607 setLoadExtAction(ISD::EXTLOAD, Tys[i], Legal);
608 setLoadExtAction(ISD::ZEXTLOAD, Tys[i], Legal);
609 setLoadExtAction(ISD::SEXTLOAD, Tys[i], Legal);
613 // ARM and Thumb2 support UMLAL/SMLAL.
614 if (!Subtarget->isThumb1Only())
615 setTargetDAGCombine(ISD::ADDC);
618 computeRegisterProperties();
620 // ARM does not have f32 extending load.
621 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
623 // ARM does not have i1 sign extending load.
624 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
626 // ARM supports all 4 flavors of integer indexed load / store.
627 if (!Subtarget->isThumb1Only()) {
628 for (unsigned im = (unsigned)ISD::PRE_INC;
629 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
630 setIndexedLoadAction(im, MVT::i1, Legal);
631 setIndexedLoadAction(im, MVT::i8, Legal);
632 setIndexedLoadAction(im, MVT::i16, Legal);
633 setIndexedLoadAction(im, MVT::i32, Legal);
634 setIndexedStoreAction(im, MVT::i1, Legal);
635 setIndexedStoreAction(im, MVT::i8, Legal);
636 setIndexedStoreAction(im, MVT::i16, Legal);
637 setIndexedStoreAction(im, MVT::i32, Legal);
641 // i64 operation support.
642 setOperationAction(ISD::MUL, MVT::i64, Expand);
643 setOperationAction(ISD::MULHU, MVT::i32, Expand);
644 if (Subtarget->isThumb1Only()) {
645 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
646 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
648 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
649 || (Subtarget->isThumb2() && !Subtarget->hasThumb2DSP()))
650 setOperationAction(ISD::MULHS, MVT::i32, Expand);
652 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
653 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
654 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
655 setOperationAction(ISD::SRL, MVT::i64, Custom);
656 setOperationAction(ISD::SRA, MVT::i64, Custom);
658 if (!Subtarget->isThumb1Only()) {
659 // FIXME: We should do this for Thumb1 as well.
660 setOperationAction(ISD::ADDC, MVT::i32, Custom);
661 setOperationAction(ISD::ADDE, MVT::i32, Custom);
662 setOperationAction(ISD::SUBC, MVT::i32, Custom);
663 setOperationAction(ISD::SUBE, MVT::i32, Custom);
666 // ARM does not have ROTL.
667 setOperationAction(ISD::ROTL, MVT::i32, Expand);
668 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
669 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
670 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
671 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
673 // These just redirect to CTTZ and CTLZ on ARM.
674 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i32 , Expand);
675 setOperationAction(ISD::CTLZ_ZERO_UNDEF , MVT::i32 , Expand);
677 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
679 // Only ARMv6 has BSWAP.
680 if (!Subtarget->hasV6Ops())
681 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
683 if (!(Subtarget->hasDivide() && Subtarget->isThumb2()) &&
684 !(Subtarget->hasDivideInARMMode() && !Subtarget->isThumb())) {
685 // These are expanded into libcalls if the cpu doesn't have HW divider.
686 setOperationAction(ISD::SDIV, MVT::i32, Expand);
687 setOperationAction(ISD::UDIV, MVT::i32, Expand);
690 // FIXME: Also set divmod for SREM on EABI
691 setOperationAction(ISD::SREM, MVT::i32, Expand);
692 setOperationAction(ISD::UREM, MVT::i32, Expand);
693 // Register based DivRem for AEABI (RTABI 4.2)
694 if (Subtarget->isTargetAEABI()) {
695 setLibcallName(RTLIB::SDIVREM_I8, "__aeabi_idivmod");
696 setLibcallName(RTLIB::SDIVREM_I16, "__aeabi_idivmod");
697 setLibcallName(RTLIB::SDIVREM_I32, "__aeabi_idivmod");
698 setLibcallName(RTLIB::SDIVREM_I64, "__aeabi_ldivmod");
699 setLibcallName(RTLIB::UDIVREM_I8, "__aeabi_uidivmod");
700 setLibcallName(RTLIB::UDIVREM_I16, "__aeabi_uidivmod");
701 setLibcallName(RTLIB::UDIVREM_I32, "__aeabi_uidivmod");
702 setLibcallName(RTLIB::UDIVREM_I64, "__aeabi_uldivmod");
704 setLibcallCallingConv(RTLIB::SDIVREM_I8, CallingConv::ARM_AAPCS);
705 setLibcallCallingConv(RTLIB::SDIVREM_I16, CallingConv::ARM_AAPCS);
706 setLibcallCallingConv(RTLIB::SDIVREM_I32, CallingConv::ARM_AAPCS);
707 setLibcallCallingConv(RTLIB::SDIVREM_I64, CallingConv::ARM_AAPCS);
708 setLibcallCallingConv(RTLIB::UDIVREM_I8, CallingConv::ARM_AAPCS);
709 setLibcallCallingConv(RTLIB::UDIVREM_I16, CallingConv::ARM_AAPCS);
710 setLibcallCallingConv(RTLIB::UDIVREM_I32, CallingConv::ARM_AAPCS);
711 setLibcallCallingConv(RTLIB::UDIVREM_I64, CallingConv::ARM_AAPCS);
713 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
714 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
716 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
717 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
720 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
721 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
722 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
723 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
724 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
726 setOperationAction(ISD::TRAP, MVT::Other, Legal);
728 // Use the default implementation.
729 setOperationAction(ISD::VASTART, MVT::Other, Custom);
730 setOperationAction(ISD::VAARG, MVT::Other, Expand);
731 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
732 setOperationAction(ISD::VAEND, MVT::Other, Expand);
733 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
734 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
736 if (!Subtarget->isTargetMachO()) {
737 // Non-MachO platforms may return values in these registers via the
738 // personality function.
739 setExceptionPointerRegister(ARM::R0);
740 setExceptionSelectorRegister(ARM::R1);
743 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
744 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
745 // the default expansion.
746 if (Subtarget->hasAnyDataBarrier() && !Subtarget->isThumb1Only()) {
747 // ATOMIC_FENCE needs custom lowering; the other 32-bit ones are legal and
749 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
750 // Custom lowering for 64-bit ops
751 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
752 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
753 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
754 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
755 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
756 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
757 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i64, Custom);
758 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i64, Custom);
759 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i64, Custom);
760 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i64, Custom);
761 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
762 // On v8, we have particularly efficient implementations of atomic fences
763 // if they can be combined with nearby atomic loads and stores.
764 if (!Subtarget->hasV8Ops()) {
765 // Automatically insert fences (dmb ist) around ATOMIC_SWAP etc.
766 setInsertFencesForAtomic(true);
768 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
770 // If there's anything we can use as a barrier, go through custom lowering
772 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other,
773 Subtarget->hasAnyDataBarrier() ? Custom : Expand);
775 // Set them all for expansion, which will force libcalls.
776 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
777 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
778 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
779 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
780 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
781 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
782 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
783 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
784 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
785 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
786 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
787 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
788 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the
789 // Unordered/Monotonic case.
790 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
791 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
794 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
796 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
797 if (!Subtarget->hasV6Ops()) {
798 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
799 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
801 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
803 if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
804 !Subtarget->isThumb1Only()) {
805 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
806 // iff target supports vfp2.
807 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
808 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
811 // We want to custom lower some of our intrinsics.
812 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
813 if (Subtarget->isTargetDarwin()) {
814 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
815 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
816 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
819 setOperationAction(ISD::SETCC, MVT::i32, Expand);
820 setOperationAction(ISD::SETCC, MVT::f32, Expand);
821 setOperationAction(ISD::SETCC, MVT::f64, Expand);
822 setOperationAction(ISD::SELECT, MVT::i32, Custom);
823 setOperationAction(ISD::SELECT, MVT::f32, Custom);
824 setOperationAction(ISD::SELECT, MVT::f64, Custom);
825 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
826 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
827 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
829 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
830 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
831 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
832 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
833 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
835 // We don't support sin/cos/fmod/copysign/pow
836 setOperationAction(ISD::FSIN, MVT::f64, Expand);
837 setOperationAction(ISD::FSIN, MVT::f32, Expand);
838 setOperationAction(ISD::FCOS, MVT::f32, Expand);
839 setOperationAction(ISD::FCOS, MVT::f64, Expand);
840 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
841 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
842 setOperationAction(ISD::FREM, MVT::f64, Expand);
843 setOperationAction(ISD::FREM, MVT::f32, Expand);
844 if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
845 !Subtarget->isThumb1Only()) {
846 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
847 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
849 setOperationAction(ISD::FPOW, MVT::f64, Expand);
850 setOperationAction(ISD::FPOW, MVT::f32, Expand);
852 if (!Subtarget->hasVFP4()) {
853 setOperationAction(ISD::FMA, MVT::f64, Expand);
854 setOperationAction(ISD::FMA, MVT::f32, Expand);
857 // Various VFP goodness
858 if (!TM.Options.UseSoftFloat && !Subtarget->isThumb1Only()) {
859 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
860 if (Subtarget->hasVFP2()) {
861 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
862 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
863 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
864 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
866 // Special handling for half-precision FP.
867 if (!Subtarget->hasFP16()) {
868 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
869 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand);
873 // Combine sin / cos into one node or libcall if possible.
874 if (Subtarget->hasSinCos()) {
875 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
876 setLibcallName(RTLIB::SINCOS_F64, "sincos");
877 if (Subtarget->getTargetTriple().getOS() == Triple::IOS) {
878 // For iOS, we don't want to the normal expansion of a libcall to
879 // sincos. We want to issue a libcall to __sincos_stret.
880 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
881 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
885 // We have target-specific dag combine patterns for the following nodes:
886 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
887 setTargetDAGCombine(ISD::ADD);
888 setTargetDAGCombine(ISD::SUB);
889 setTargetDAGCombine(ISD::MUL);
890 setTargetDAGCombine(ISD::AND);
891 setTargetDAGCombine(ISD::OR);
892 setTargetDAGCombine(ISD::XOR);
894 if (Subtarget->hasV6Ops())
895 setTargetDAGCombine(ISD::SRL);
897 setStackPointerRegisterToSaveRestore(ARM::SP);
899 if (TM.Options.UseSoftFloat || Subtarget->isThumb1Only() ||
900 !Subtarget->hasVFP2())
901 setSchedulingPreference(Sched::RegPressure);
903 setSchedulingPreference(Sched::Hybrid);
905 //// temporary - rewrite interface to use type
906 MaxStoresPerMemset = 8;
907 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
908 MaxStoresPerMemcpy = 4; // For @llvm.memcpy -> sequence of stores
909 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 4 : 2;
910 MaxStoresPerMemmove = 4; // For @llvm.memmove -> sequence of stores
911 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 4 : 2;
913 // On ARM arguments smaller than 4 bytes are extended, so all arguments
914 // are at least 4 bytes aligned.
915 setMinStackArgumentAlignment(4);
917 // Prefer likely predicted branches to selects on out-of-order cores.
918 PredictableSelectIsExpensive = Subtarget->isLikeA9();
920 setMinFunctionAlignment(Subtarget->isThumb() ? 1 : 2);
923 static void getExclusiveOperation(unsigned Size, AtomicOrdering Ord,
924 bool isThumb2, unsigned &LdrOpc,
926 static const unsigned LoadBares[4][2] = {{ARM::LDREXB, ARM::t2LDREXB},
927 {ARM::LDREXH, ARM::t2LDREXH},
928 {ARM::LDREX, ARM::t2LDREX},
929 {ARM::LDREXD, ARM::t2LDREXD}};
930 static const unsigned LoadAcqs[4][2] = {{ARM::LDAEXB, ARM::t2LDAEXB},
931 {ARM::LDAEXH, ARM::t2LDAEXH},
932 {ARM::LDAEX, ARM::t2LDAEX},
933 {ARM::LDAEXD, ARM::t2LDAEXD}};
934 static const unsigned StoreBares[4][2] = {{ARM::STREXB, ARM::t2STREXB},
935 {ARM::STREXH, ARM::t2STREXH},
936 {ARM::STREX, ARM::t2STREX},
937 {ARM::STREXD, ARM::t2STREXD}};
938 static const unsigned StoreRels[4][2] = {{ARM::STLEXB, ARM::t2STLEXB},
939 {ARM::STLEXH, ARM::t2STLEXH},
940 {ARM::STLEX, ARM::t2STLEX},
941 {ARM::STLEXD, ARM::t2STLEXD}};
943 const unsigned (*LoadOps)[2], (*StoreOps)[2];
944 if (Ord == Acquire || Ord == AcquireRelease || Ord == SequentiallyConsistent)
949 if (Ord == Release || Ord == AcquireRelease || Ord == SequentiallyConsistent)
950 StoreOps = StoreRels;
952 StoreOps = StoreBares;
954 assert(isPowerOf2_32(Size) && Size <= 8 &&
955 "unsupported size for atomic binary op!");
957 LdrOpc = LoadOps[Log2_32(Size)][isThumb2];
958 StrOpc = StoreOps[Log2_32(Size)][isThumb2];
961 // FIXME: It might make sense to define the representative register class as the
962 // nearest super-register that has a non-null superset. For example, DPR_VFP2 is
963 // a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
964 // SPR's representative would be DPR_VFP2. This should work well if register
965 // pressure tracking were modified such that a register use would increment the
966 // pressure of the register class's representative and all of it's super
967 // classes' representatives transitively. We have not implemented this because
968 // of the difficulty prior to coalescing of modeling operand register classes
969 // due to the common occurrence of cross class copies and subregister insertions
971 std::pair<const TargetRegisterClass*, uint8_t>
972 ARMTargetLowering::findRepresentativeClass(MVT VT) const{
973 const TargetRegisterClass *RRC = 0;
975 switch (VT.SimpleTy) {
977 return TargetLowering::findRepresentativeClass(VT);
978 // Use DPR as representative register class for all floating point
979 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
980 // the cost is 1 for both f32 and f64.
981 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
982 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
983 RRC = &ARM::DPRRegClass;
984 // When NEON is used for SP, only half of the register file is available
985 // because operations that define both SP and DP results will be constrained
986 // to the VFP2 class (D0-D15). We currently model this constraint prior to
987 // coalescing by double-counting the SP regs. See the FIXME above.
988 if (Subtarget->useNEONForSinglePrecisionFP())
991 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
992 case MVT::v4f32: case MVT::v2f64:
993 RRC = &ARM::DPRRegClass;
997 RRC = &ARM::DPRRegClass;
1001 RRC = &ARM::DPRRegClass;
1005 return std::make_pair(RRC, Cost);
1008 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
1011 case ARMISD::Wrapper: return "ARMISD::Wrapper";
1012 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
1013 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
1014 case ARMISD::CALL: return "ARMISD::CALL";
1015 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
1016 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
1017 case ARMISD::tCALL: return "ARMISD::tCALL";
1018 case ARMISD::BRCOND: return "ARMISD::BRCOND";
1019 case ARMISD::BR_JT: return "ARMISD::BR_JT";
1020 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
1021 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
1022 case ARMISD::INTRET_FLAG: return "ARMISD::INTRET_FLAG";
1023 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
1024 case ARMISD::CMP: return "ARMISD::CMP";
1025 case ARMISD::CMN: return "ARMISD::CMN";
1026 case ARMISD::CMPZ: return "ARMISD::CMPZ";
1027 case ARMISD::CMPFP: return "ARMISD::CMPFP";
1028 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
1029 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
1030 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
1032 case ARMISD::CMOV: return "ARMISD::CMOV";
1034 case ARMISD::RBIT: return "ARMISD::RBIT";
1036 case ARMISD::FTOSI: return "ARMISD::FTOSI";
1037 case ARMISD::FTOUI: return "ARMISD::FTOUI";
1038 case ARMISD::SITOF: return "ARMISD::SITOF";
1039 case ARMISD::UITOF: return "ARMISD::UITOF";
1041 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
1042 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
1043 case ARMISD::RRX: return "ARMISD::RRX";
1045 case ARMISD::ADDC: return "ARMISD::ADDC";
1046 case ARMISD::ADDE: return "ARMISD::ADDE";
1047 case ARMISD::SUBC: return "ARMISD::SUBC";
1048 case ARMISD::SUBE: return "ARMISD::SUBE";
1050 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
1051 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
1053 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
1054 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
1056 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
1058 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
1060 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
1062 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
1064 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
1066 case ARMISD::VCEQ: return "ARMISD::VCEQ";
1067 case ARMISD::VCEQZ: return "ARMISD::VCEQZ";
1068 case ARMISD::VCGE: return "ARMISD::VCGE";
1069 case ARMISD::VCGEZ: return "ARMISD::VCGEZ";
1070 case ARMISD::VCLEZ: return "ARMISD::VCLEZ";
1071 case ARMISD::VCGEU: return "ARMISD::VCGEU";
1072 case ARMISD::VCGT: return "ARMISD::VCGT";
1073 case ARMISD::VCGTZ: return "ARMISD::VCGTZ";
1074 case ARMISD::VCLTZ: return "ARMISD::VCLTZ";
1075 case ARMISD::VCGTU: return "ARMISD::VCGTU";
1076 case ARMISD::VTST: return "ARMISD::VTST";
1078 case ARMISD::VSHL: return "ARMISD::VSHL";
1079 case ARMISD::VSHRs: return "ARMISD::VSHRs";
1080 case ARMISD::VSHRu: return "ARMISD::VSHRu";
1081 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
1082 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
1083 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
1084 case ARMISD::VSHRN: return "ARMISD::VSHRN";
1085 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
1086 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
1087 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
1088 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
1089 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
1090 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
1091 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
1092 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
1093 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
1094 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
1095 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
1096 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
1097 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
1098 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
1099 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
1100 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
1101 case ARMISD::VMOVFPIMM: return "ARMISD::VMOVFPIMM";
1102 case ARMISD::VDUP: return "ARMISD::VDUP";
1103 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
1104 case ARMISD::VEXT: return "ARMISD::VEXT";
1105 case ARMISD::VREV64: return "ARMISD::VREV64";
1106 case ARMISD::VREV32: return "ARMISD::VREV32";
1107 case ARMISD::VREV16: return "ARMISD::VREV16";
1108 case ARMISD::VZIP: return "ARMISD::VZIP";
1109 case ARMISD::VUZP: return "ARMISD::VUZP";
1110 case ARMISD::VTRN: return "ARMISD::VTRN";
1111 case ARMISD::VTBL1: return "ARMISD::VTBL1";
1112 case ARMISD::VTBL2: return "ARMISD::VTBL2";
1113 case ARMISD::VMULLs: return "ARMISD::VMULLs";
1114 case ARMISD::VMULLu: return "ARMISD::VMULLu";
1115 case ARMISD::UMLAL: return "ARMISD::UMLAL";
1116 case ARMISD::SMLAL: return "ARMISD::SMLAL";
1117 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
1118 case ARMISD::FMAX: return "ARMISD::FMAX";
1119 case ARMISD::FMIN: return "ARMISD::FMIN";
1120 case ARMISD::VMAXNM: return "ARMISD::VMAX";
1121 case ARMISD::VMINNM: return "ARMISD::VMIN";
1122 case ARMISD::BFI: return "ARMISD::BFI";
1123 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
1124 case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
1125 case ARMISD::VBSL: return "ARMISD::VBSL";
1126 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
1127 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
1128 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
1129 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD";
1130 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD";
1131 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD";
1132 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD";
1133 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD";
1134 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD";
1135 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD";
1136 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD";
1137 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD";
1138 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD";
1139 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD";
1140 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD";
1141 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD";
1142 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD";
1143 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD";
1144 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD";
1145 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD";
1149 EVT ARMTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1150 if (!VT.isVector()) return getPointerTy();
1151 return VT.changeVectorElementTypeToInteger();
1154 /// getRegClassFor - Return the register class that should be used for the
1155 /// specified value type.
1156 const TargetRegisterClass *ARMTargetLowering::getRegClassFor(MVT VT) const {
1157 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
1158 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
1159 // load / store 4 to 8 consecutive D registers.
1160 if (Subtarget->hasNEON()) {
1161 if (VT == MVT::v4i64)
1162 return &ARM::QQPRRegClass;
1163 if (VT == MVT::v8i64)
1164 return &ARM::QQQQPRRegClass;
1166 return TargetLowering::getRegClassFor(VT);
1169 // Create a fast isel object.
1171 ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
1172 const TargetLibraryInfo *libInfo) const {
1173 return ARM::createFastISel(funcInfo, libInfo);
1176 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
1177 /// be used for loads / stores from the global.
1178 unsigned ARMTargetLowering::getMaximalGlobalOffset() const {
1179 return (Subtarget->isThumb1Only() ? 127 : 4095);
1182 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
1183 unsigned NumVals = N->getNumValues();
1185 return Sched::RegPressure;
1187 for (unsigned i = 0; i != NumVals; ++i) {
1188 EVT VT = N->getValueType(i);
1189 if (VT == MVT::Glue || VT == MVT::Other)
1191 if (VT.isFloatingPoint() || VT.isVector())
1195 if (!N->isMachineOpcode())
1196 return Sched::RegPressure;
1198 // Load are scheduled for latency even if there instruction itinerary
1199 // is not available.
1200 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1201 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1203 if (MCID.getNumDefs() == 0)
1204 return Sched::RegPressure;
1205 if (!Itins->isEmpty() &&
1206 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
1209 return Sched::RegPressure;
1212 //===----------------------------------------------------------------------===//
1214 //===----------------------------------------------------------------------===//
1216 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
1217 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
1219 default: llvm_unreachable("Unknown condition code!");
1220 case ISD::SETNE: return ARMCC::NE;
1221 case ISD::SETEQ: return ARMCC::EQ;
1222 case ISD::SETGT: return ARMCC::GT;
1223 case ISD::SETGE: return ARMCC::GE;
1224 case ISD::SETLT: return ARMCC::LT;
1225 case ISD::SETLE: return ARMCC::LE;
1226 case ISD::SETUGT: return ARMCC::HI;
1227 case ISD::SETUGE: return ARMCC::HS;
1228 case ISD::SETULT: return ARMCC::LO;
1229 case ISD::SETULE: return ARMCC::LS;
1233 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
1234 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
1235 ARMCC::CondCodes &CondCode2) {
1236 CondCode2 = ARMCC::AL;
1238 default: llvm_unreachable("Unknown FP condition!");
1240 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
1242 case ISD::SETOGT: CondCode = ARMCC::GT; break;
1244 case ISD::SETOGE: CondCode = ARMCC::GE; break;
1245 case ISD::SETOLT: CondCode = ARMCC::MI; break;
1246 case ISD::SETOLE: CondCode = ARMCC::LS; break;
1247 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
1248 case ISD::SETO: CondCode = ARMCC::VC; break;
1249 case ISD::SETUO: CondCode = ARMCC::VS; break;
1250 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
1251 case ISD::SETUGT: CondCode = ARMCC::HI; break;
1252 case ISD::SETUGE: CondCode = ARMCC::PL; break;
1254 case ISD::SETULT: CondCode = ARMCC::LT; break;
1256 case ISD::SETULE: CondCode = ARMCC::LE; break;
1258 case ISD::SETUNE: CondCode = ARMCC::NE; break;
1262 //===----------------------------------------------------------------------===//
1263 // Calling Convention Implementation
1264 //===----------------------------------------------------------------------===//
1266 #include "ARMGenCallingConv.inc"
1268 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1269 /// given CallingConvention value.
1270 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
1272 bool isVarArg) const {
1275 llvm_unreachable("Unsupported calling convention");
1276 case CallingConv::Fast:
1277 if (Subtarget->hasVFP2() && !isVarArg) {
1278 if (!Subtarget->isAAPCS_ABI())
1279 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1280 // For AAPCS ABI targets, just use VFP variant of the calling convention.
1281 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1284 case CallingConv::C: {
1285 // Use target triple & subtarget features to do actual dispatch.
1286 if (!Subtarget->isAAPCS_ABI())
1287 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1288 else if (Subtarget->hasVFP2() &&
1289 getTargetMachine().Options.FloatABIType == FloatABI::Hard &&
1291 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1292 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1294 case CallingConv::ARM_AAPCS_VFP:
1296 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1298 case CallingConv::ARM_AAPCS:
1299 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1300 case CallingConv::ARM_APCS:
1301 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1302 case CallingConv::GHC:
1303 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC);
1307 /// LowerCallResult - Lower the result values of a call into the
1308 /// appropriate copies out of appropriate physical registers.
1310 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1311 CallingConv::ID CallConv, bool isVarArg,
1312 const SmallVectorImpl<ISD::InputArg> &Ins,
1313 SDLoc dl, SelectionDAG &DAG,
1314 SmallVectorImpl<SDValue> &InVals,
1315 bool isThisReturn, SDValue ThisVal) const {
1317 // Assign locations to each value returned by this call.
1318 SmallVector<CCValAssign, 16> RVLocs;
1319 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1320 getTargetMachine(), RVLocs, *DAG.getContext(), Call);
1321 CCInfo.AnalyzeCallResult(Ins,
1322 CCAssignFnForNode(CallConv, /* Return*/ true,
1325 // Copy all of the result registers out of their specified physreg.
1326 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1327 CCValAssign VA = RVLocs[i];
1329 // Pass 'this' value directly from the argument to return value, to avoid
1330 // reg unit interference
1331 if (i == 0 && isThisReturn) {
1332 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&
1333 "unexpected return calling convention register assignment");
1334 InVals.push_back(ThisVal);
1339 if (VA.needsCustom()) {
1340 // Handle f64 or half of a v2f64.
1341 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1343 Chain = Lo.getValue(1);
1344 InFlag = Lo.getValue(2);
1345 VA = RVLocs[++i]; // skip ahead to next loc
1346 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1348 Chain = Hi.getValue(1);
1349 InFlag = Hi.getValue(2);
1350 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1352 if (VA.getLocVT() == MVT::v2f64) {
1353 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1354 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1355 DAG.getConstant(0, MVT::i32));
1357 VA = RVLocs[++i]; // skip ahead to next loc
1358 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1359 Chain = Lo.getValue(1);
1360 InFlag = Lo.getValue(2);
1361 VA = RVLocs[++i]; // skip ahead to next loc
1362 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1363 Chain = Hi.getValue(1);
1364 InFlag = Hi.getValue(2);
1365 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1366 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1367 DAG.getConstant(1, MVT::i32));
1370 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1372 Chain = Val.getValue(1);
1373 InFlag = Val.getValue(2);
1376 switch (VA.getLocInfo()) {
1377 default: llvm_unreachable("Unknown loc info!");
1378 case CCValAssign::Full: break;
1379 case CCValAssign::BCvt:
1380 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1384 InVals.push_back(Val);
1390 /// LowerMemOpCallTo - Store the argument to the stack.
1392 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
1393 SDValue StackPtr, SDValue Arg,
1394 SDLoc dl, SelectionDAG &DAG,
1395 const CCValAssign &VA,
1396 ISD::ArgFlagsTy Flags) const {
1397 unsigned LocMemOffset = VA.getLocMemOffset();
1398 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1399 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1400 return DAG.getStore(Chain, dl, Arg, PtrOff,
1401 MachinePointerInfo::getStack(LocMemOffset),
1405 void ARMTargetLowering::PassF64ArgInRegs(SDLoc dl, SelectionDAG &DAG,
1406 SDValue Chain, SDValue &Arg,
1407 RegsToPassVector &RegsToPass,
1408 CCValAssign &VA, CCValAssign &NextVA,
1410 SmallVectorImpl<SDValue> &MemOpChains,
1411 ISD::ArgFlagsTy Flags) const {
1413 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1414 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1415 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
1417 if (NextVA.isRegLoc())
1418 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
1420 assert(NextVA.isMemLoc());
1421 if (StackPtr.getNode() == 0)
1422 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1424 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
1430 /// LowerCall - Lowering a call into a callseq_start <-
1431 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1434 ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1435 SmallVectorImpl<SDValue> &InVals) const {
1436 SelectionDAG &DAG = CLI.DAG;
1438 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1439 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1440 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1441 SDValue Chain = CLI.Chain;
1442 SDValue Callee = CLI.Callee;
1443 bool &isTailCall = CLI.IsTailCall;
1444 CallingConv::ID CallConv = CLI.CallConv;
1445 bool doesNotRet = CLI.DoesNotReturn;
1446 bool isVarArg = CLI.IsVarArg;
1448 MachineFunction &MF = DAG.getMachineFunction();
1449 bool isStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1450 bool isThisReturn = false;
1451 bool isSibCall = false;
1452 // Disable tail calls if they're not supported.
1453 if (!EnableARMTailCalls && !Subtarget->supportsTailCall())
1456 // Check if it's really possible to do a tail call.
1457 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1458 isVarArg, isStructRet, MF.getFunction()->hasStructRetAttr(),
1459 Outs, OutVals, Ins, DAG);
1460 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1461 // detected sibcalls.
1468 // Analyze operands of the call, assigning locations to each operand.
1469 SmallVector<CCValAssign, 16> ArgLocs;
1470 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1471 getTargetMachine(), ArgLocs, *DAG.getContext(), Call);
1472 CCInfo.AnalyzeCallOperands(Outs,
1473 CCAssignFnForNode(CallConv, /* Return*/ false,
1476 // Get a count of how many bytes are to be pushed on the stack.
1477 unsigned NumBytes = CCInfo.getNextStackOffset();
1479 // For tail calls, memory operands are available in our caller's stack.
1483 // Adjust the stack pointer for the new arguments...
1484 // These operations are automatically eliminated by the prolog/epilog pass
1486 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
1489 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1491 RegsToPassVector RegsToPass;
1492 SmallVector<SDValue, 8> MemOpChains;
1494 // Walk the register/memloc assignments, inserting copies/loads. In the case
1495 // of tail call optimization, arguments are handled later.
1496 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1498 ++i, ++realArgIdx) {
1499 CCValAssign &VA = ArgLocs[i];
1500 SDValue Arg = OutVals[realArgIdx];
1501 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1502 bool isByVal = Flags.isByVal();
1504 // Promote the value if needed.
1505 switch (VA.getLocInfo()) {
1506 default: llvm_unreachable("Unknown loc info!");
1507 case CCValAssign::Full: break;
1508 case CCValAssign::SExt:
1509 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1511 case CCValAssign::ZExt:
1512 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1514 case CCValAssign::AExt:
1515 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1517 case CCValAssign::BCvt:
1518 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1522 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1523 if (VA.needsCustom()) {
1524 if (VA.getLocVT() == MVT::v2f64) {
1525 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1526 DAG.getConstant(0, MVT::i32));
1527 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1528 DAG.getConstant(1, MVT::i32));
1530 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1531 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1533 VA = ArgLocs[++i]; // skip ahead to next loc
1534 if (VA.isRegLoc()) {
1535 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1536 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1538 assert(VA.isMemLoc());
1540 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1541 dl, DAG, VA, Flags));
1544 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1545 StackPtr, MemOpChains, Flags);
1547 } else if (VA.isRegLoc()) {
1548 if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i32) {
1549 assert(VA.getLocVT() == MVT::i32 &&
1550 "unexpected calling convention register assignment");
1551 assert(!Ins.empty() && Ins[0].VT == MVT::i32 &&
1552 "unexpected use of 'returned'");
1553 isThisReturn = true;
1555 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1556 } else if (isByVal) {
1557 assert(VA.isMemLoc());
1558 unsigned offset = 0;
1560 // True if this byval aggregate will be split between registers
1562 unsigned ByValArgsCount = CCInfo.getInRegsParamsCount();
1563 unsigned CurByValIdx = CCInfo.getInRegsParamsProceed();
1565 if (CurByValIdx < ByValArgsCount) {
1567 unsigned RegBegin, RegEnd;
1568 CCInfo.getInRegsParamInfo(CurByValIdx, RegBegin, RegEnd);
1570 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1572 for (i = 0, j = RegBegin; j < RegEnd; i++, j++) {
1573 SDValue Const = DAG.getConstant(4*i, MVT::i32);
1574 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
1575 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
1576 MachinePointerInfo(),
1577 false, false, false,
1578 DAG.InferPtrAlignment(AddArg));
1579 MemOpChains.push_back(Load.getValue(1));
1580 RegsToPass.push_back(std::make_pair(j, Load));
1583 // If parameter size outsides register area, "offset" value
1584 // helps us to calculate stack slot for remained part properly.
1585 offset = RegEnd - RegBegin;
1587 CCInfo.nextInRegsParam();
1590 if (Flags.getByValSize() > 4*offset) {
1591 unsigned LocMemOffset = VA.getLocMemOffset();
1592 SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset);
1593 SDValue Dst = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr,
1595 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset);
1596 SDValue Src = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg, SrcOffset);
1597 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset,
1599 SDValue AlignNode = DAG.getConstant(Flags.getByValAlign(), MVT::i32);
1601 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
1602 SDValue Ops[] = { Chain, Dst, Src, SizeNode, AlignNode};
1603 MemOpChains.push_back(DAG.getNode(ARMISD::COPY_STRUCT_BYVAL, dl, VTs,
1604 Ops, array_lengthof(Ops)));
1606 } else if (!isSibCall) {
1607 assert(VA.isMemLoc());
1609 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1610 dl, DAG, VA, Flags));
1614 if (!MemOpChains.empty())
1615 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1616 &MemOpChains[0], MemOpChains.size());
1618 // Build a sequence of copy-to-reg nodes chained together with token chain
1619 // and flag operands which copy the outgoing args into the appropriate regs.
1621 // Tail call byval lowering might overwrite argument registers so in case of
1622 // tail call optimization the copies to registers are lowered later.
1624 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1625 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1626 RegsToPass[i].second, InFlag);
1627 InFlag = Chain.getValue(1);
1630 // For tail calls lower the arguments to the 'real' stack slot.
1632 // Force all the incoming stack arguments to be loaded from the stack
1633 // before any new outgoing arguments are stored to the stack, because the
1634 // outgoing stack slots may alias the incoming argument stack slots, and
1635 // the alias isn't otherwise explicit. This is slightly more conservative
1636 // than necessary, because it means that each store effectively depends
1637 // on every argument instead of just those arguments it would clobber.
1639 // Do not flag preceding copytoreg stuff together with the following stuff.
1641 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1642 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1643 RegsToPass[i].second, InFlag);
1644 InFlag = Chain.getValue(1);
1649 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1650 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1651 // node so that legalize doesn't hack it.
1652 bool isDirect = false;
1653 bool isARMFunc = false;
1654 bool isLocalARMFunc = false;
1655 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1657 if (EnableARMLongCalls) {
1658 assert (getTargetMachine().getRelocationModel() == Reloc::Static
1659 && "long-calls with non-static relocation model!");
1660 // Handle a global address or an external symbol. If it's not one of
1661 // those, the target's already in a register, so we don't need to do
1663 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1664 const GlobalValue *GV = G->getGlobal();
1665 // Create a constant pool entry for the callee address
1666 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1667 ARMConstantPoolValue *CPV =
1668 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0);
1670 // Get the address of the callee into a register
1671 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1672 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1673 Callee = DAG.getLoad(getPointerTy(), dl,
1674 DAG.getEntryNode(), CPAddr,
1675 MachinePointerInfo::getConstantPool(),
1676 false, false, false, 0);
1677 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1678 const char *Sym = S->getSymbol();
1680 // Create a constant pool entry for the callee address
1681 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1682 ARMConstantPoolValue *CPV =
1683 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
1684 ARMPCLabelIndex, 0);
1685 // Get the address of the callee into a register
1686 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1687 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1688 Callee = DAG.getLoad(getPointerTy(), dl,
1689 DAG.getEntryNode(), CPAddr,
1690 MachinePointerInfo::getConstantPool(),
1691 false, false, false, 0);
1693 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1694 const GlobalValue *GV = G->getGlobal();
1696 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1697 bool isStub = (isExt && Subtarget->isTargetMachO()) &&
1698 getTargetMachine().getRelocationModel() != Reloc::Static;
1699 isARMFunc = !Subtarget->isThumb() || isStub;
1700 // ARM call to a local ARM function is predicable.
1701 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
1702 // tBX takes a register source operand.
1703 if (isStub && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1704 assert(Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?");
1705 Callee = DAG.getNode(ARMISD::WrapperPIC, dl, getPointerTy(),
1706 DAG.getTargetGlobalAddress(GV, dl, getPointerTy()));
1708 // On ELF targets for PIC code, direct calls should go through the PLT
1709 unsigned OpFlags = 0;
1710 if (Subtarget->isTargetELF() &&
1711 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1712 OpFlags = ARMII::MO_PLT;
1713 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
1715 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1717 bool isStub = Subtarget->isTargetMachO() &&
1718 getTargetMachine().getRelocationModel() != Reloc::Static;
1719 isARMFunc = !Subtarget->isThumb() || isStub;
1720 // tBX takes a register source operand.
1721 const char *Sym = S->getSymbol();
1722 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1723 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1724 ARMConstantPoolValue *CPV =
1725 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
1726 ARMPCLabelIndex, 4);
1727 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1728 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1729 Callee = DAG.getLoad(getPointerTy(), dl,
1730 DAG.getEntryNode(), CPAddr,
1731 MachinePointerInfo::getConstantPool(),
1732 false, false, false, 0);
1733 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1734 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1735 getPointerTy(), Callee, PICLabel);
1737 unsigned OpFlags = 0;
1738 // On ELF targets for PIC code, direct calls should go through the PLT
1739 if (Subtarget->isTargetELF() &&
1740 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1741 OpFlags = ARMII::MO_PLT;
1742 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags);
1746 // FIXME: handle tail calls differently.
1748 bool HasMinSizeAttr = Subtarget->isMinSize();
1749 if (Subtarget->isThumb()) {
1750 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1751 CallOpc = ARMISD::CALL_NOLINK;
1753 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1755 if (!isDirect && !Subtarget->hasV5TOps())
1756 CallOpc = ARMISD::CALL_NOLINK;
1757 else if (doesNotRet && isDirect && Subtarget->hasRAS() &&
1758 // Emit regular call when code size is the priority
1760 // "mov lr, pc; b _foo" to avoid confusing the RSP
1761 CallOpc = ARMISD::CALL_NOLINK;
1763 CallOpc = isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL;
1766 std::vector<SDValue> Ops;
1767 Ops.push_back(Chain);
1768 Ops.push_back(Callee);
1770 // Add argument registers to the end of the list so that they are known live
1772 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1773 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1774 RegsToPass[i].second.getValueType()));
1776 // Add a register mask operand representing the call-preserved registers.
1778 const uint32_t *Mask;
1779 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
1780 const ARMBaseRegisterInfo *ARI = static_cast<const ARMBaseRegisterInfo*>(TRI);
1782 // For 'this' returns, use the R0-preserving mask if applicable
1783 Mask = ARI->getThisReturnPreservedMask(CallConv);
1785 // Set isThisReturn to false if the calling convention is not one that
1786 // allows 'returned' to be modeled in this way, so LowerCallResult does
1787 // not try to pass 'this' straight through
1788 isThisReturn = false;
1789 Mask = ARI->getCallPreservedMask(CallConv);
1792 Mask = ARI->getCallPreservedMask(CallConv);
1794 assert(Mask && "Missing call preserved mask for calling convention");
1795 Ops.push_back(DAG.getRegisterMask(Mask));
1798 if (InFlag.getNode())
1799 Ops.push_back(InFlag);
1801 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1803 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
1805 // Returns a chain and a flag for retval copy to use.
1806 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
1807 InFlag = Chain.getValue(1);
1809 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1810 DAG.getIntPtrConstant(0, true), InFlag, dl);
1812 InFlag = Chain.getValue(1);
1814 // Handle result values, copying them out of physregs into vregs that we
1816 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
1817 InVals, isThisReturn,
1818 isThisReturn ? OutVals[0] : SDValue());
1821 /// HandleByVal - Every parameter *after* a byval parameter is passed
1822 /// on the stack. Remember the next parameter register to allocate,
1823 /// and then confiscate the rest of the parameter registers to insure
1826 ARMTargetLowering::HandleByVal(
1827 CCState *State, unsigned &size, unsigned Align) const {
1828 unsigned reg = State->AllocateReg(GPRArgRegs, 4);
1829 assert((State->getCallOrPrologue() == Prologue ||
1830 State->getCallOrPrologue() == Call) &&
1831 "unhandled ParmContext");
1833 // For in-prologue parameters handling, we also introduce stack offset
1834 // for byval registers: see CallingConvLower.cpp, CCState::HandleByVal.
1835 // This behaviour outsides AAPCS rules (5.5 Parameters Passing) of how
1836 // NSAA should be evaluted (NSAA means "next stacked argument address").
1837 // So: NextStackOffset = NSAAOffset + SizeOfByValParamsStoredInRegs.
1838 // Then: NSAAOffset = NextStackOffset - SizeOfByValParamsStoredInRegs.
1839 unsigned NSAAOffset = State->getNextStackOffset();
1840 if (State->getCallOrPrologue() != Call) {
1841 for (unsigned i = 0, e = State->getInRegsParamsCount(); i != e; ++i) {
1843 State->getInRegsParamInfo(i, RB, RE);
1844 assert(NSAAOffset >= (RE-RB)*4 &&
1845 "Stack offset for byval regs doesn't introduced anymore?");
1846 NSAAOffset -= (RE-RB)*4;
1849 if ((ARM::R0 <= reg) && (reg <= ARM::R3)) {
1850 if (Subtarget->isAAPCS_ABI() && Align > 4) {
1851 unsigned AlignInRegs = Align / 4;
1852 unsigned Waste = (ARM::R4 - reg) % AlignInRegs;
1853 for (unsigned i = 0; i < Waste; ++i)
1854 reg = State->AllocateReg(GPRArgRegs, 4);
1857 unsigned excess = 4 * (ARM::R4 - reg);
1859 // Special case when NSAA != SP and parameter size greater than size of
1860 // all remained GPR regs. In that case we can't split parameter, we must
1861 // send it to stack. We also must set NCRN to R4, so waste all
1862 // remained registers.
1863 if (Subtarget->isAAPCS_ABI() && NSAAOffset != 0 && size > excess) {
1864 while (State->AllocateReg(GPRArgRegs, 4))
1869 // First register for byval parameter is the first register that wasn't
1870 // allocated before this method call, so it would be "reg".
1871 // If parameter is small enough to be saved in range [reg, r4), then
1872 // the end (first after last) register would be reg + param-size-in-regs,
1873 // else parameter would be splitted between registers and stack,
1874 // end register would be r4 in this case.
1875 unsigned ByValRegBegin = reg;
1876 unsigned ByValRegEnd = (size < excess) ? reg + size/4 : (unsigned)ARM::R4;
1877 State->addInRegsParamInfo(ByValRegBegin, ByValRegEnd);
1878 // Note, first register is allocated in the beginning of function already,
1879 // allocate remained amount of registers we need.
1880 for (unsigned i = reg+1; i != ByValRegEnd; ++i)
1881 State->AllocateReg(GPRArgRegs, 4);
1882 // At a call site, a byval parameter that is split between
1883 // registers and memory needs its size truncated here. In a
1884 // function prologue, such byval parameters are reassembled in
1885 // memory, and are not truncated.
1886 if (State->getCallOrPrologue() == Call) {
1887 // Make remained size equal to 0 in case, when
1888 // the whole structure may be stored into registers.
1898 /// MatchingStackOffset - Return true if the given stack call argument is
1899 /// already available in the same position (relatively) of the caller's
1900 /// incoming argument stack.
1902 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1903 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1904 const TargetInstrInfo *TII) {
1905 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
1907 if (Arg.getOpcode() == ISD::CopyFromReg) {
1908 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
1909 if (!TargetRegisterInfo::isVirtualRegister(VR))
1911 MachineInstr *Def = MRI->getVRegDef(VR);
1914 if (!Flags.isByVal()) {
1915 if (!TII->isLoadFromStackSlot(Def, FI))
1920 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
1921 if (Flags.isByVal())
1922 // ByVal argument is passed in as a pointer but it's now being
1923 // dereferenced. e.g.
1924 // define @foo(%struct.X* %A) {
1925 // tail call @bar(%struct.X* byval %A)
1928 SDValue Ptr = Ld->getBasePtr();
1929 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
1932 FI = FINode->getIndex();
1936 assert(FI != INT_MAX);
1937 if (!MFI->isFixedObjectIndex(FI))
1939 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
1942 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1943 /// for tail call optimization. Targets which want to do tail call
1944 /// optimization should implement this function.
1946 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1947 CallingConv::ID CalleeCC,
1949 bool isCalleeStructRet,
1950 bool isCallerStructRet,
1951 const SmallVectorImpl<ISD::OutputArg> &Outs,
1952 const SmallVectorImpl<SDValue> &OutVals,
1953 const SmallVectorImpl<ISD::InputArg> &Ins,
1954 SelectionDAG& DAG) const {
1955 const Function *CallerF = DAG.getMachineFunction().getFunction();
1956 CallingConv::ID CallerCC = CallerF->getCallingConv();
1957 bool CCMatch = CallerCC == CalleeCC;
1959 // Look for obvious safe cases to perform tail call optimization that do not
1960 // require ABI changes. This is what gcc calls sibcall.
1962 // Do not sibcall optimize vararg calls unless the call site is not passing
1964 if (isVarArg && !Outs.empty())
1967 // Exception-handling functions need a special set of instructions to indicate
1968 // a return to the hardware. Tail-calling another function would probably
1970 if (CallerF->hasFnAttribute("interrupt"))
1973 // Also avoid sibcall optimization if either caller or callee uses struct
1974 // return semantics.
1975 if (isCalleeStructRet || isCallerStructRet)
1978 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
1979 // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
1980 // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
1981 // support in the assembler and linker to be used. This would need to be
1982 // fixed to fully support tail calls in Thumb1.
1984 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
1985 // LR. This means if we need to reload LR, it takes an extra instructions,
1986 // which outweighs the value of the tail call; but here we don't know yet
1987 // whether LR is going to be used. Probably the right approach is to
1988 // generate the tail call here and turn it back into CALL/RET in
1989 // emitEpilogue if LR is used.
1991 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
1992 // but we need to make sure there are enough registers; the only valid
1993 // registers are the 4 used for parameters. We don't currently do this
1995 if (Subtarget->isThumb1Only())
1998 // If the calling conventions do not match, then we'd better make sure the
1999 // results are returned in the same way as what the caller expects.
2001 SmallVector<CCValAssign, 16> RVLocs1;
2002 ARMCCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
2003 getTargetMachine(), RVLocs1, *DAG.getContext(), Call);
2004 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
2006 SmallVector<CCValAssign, 16> RVLocs2;
2007 ARMCCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
2008 getTargetMachine(), RVLocs2, *DAG.getContext(), Call);
2009 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
2011 if (RVLocs1.size() != RVLocs2.size())
2013 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2014 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2016 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2018 if (RVLocs1[i].isRegLoc()) {
2019 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2022 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2028 // If Caller's vararg or byval argument has been split between registers and
2029 // stack, do not perform tail call, since part of the argument is in caller's
2031 const ARMFunctionInfo *AFI_Caller = DAG.getMachineFunction().
2032 getInfo<ARMFunctionInfo>();
2033 if (AFI_Caller->getArgRegsSaveSize())
2036 // If the callee takes no arguments then go on to check the results of the
2038 if (!Outs.empty()) {
2039 // Check if stack adjustment is needed. For now, do not do this if any
2040 // argument is passed on the stack.
2041 SmallVector<CCValAssign, 16> ArgLocs;
2042 ARMCCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
2043 getTargetMachine(), ArgLocs, *DAG.getContext(), Call);
2044 CCInfo.AnalyzeCallOperands(Outs,
2045 CCAssignFnForNode(CalleeCC, false, isVarArg));
2046 if (CCInfo.getNextStackOffset()) {
2047 MachineFunction &MF = DAG.getMachineFunction();
2049 // Check if the arguments are already laid out in the right way as
2050 // the caller's fixed stack objects.
2051 MachineFrameInfo *MFI = MF.getFrameInfo();
2052 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2053 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2054 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
2056 ++i, ++realArgIdx) {
2057 CCValAssign &VA = ArgLocs[i];
2058 EVT RegVT = VA.getLocVT();
2059 SDValue Arg = OutVals[realArgIdx];
2060 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2061 if (VA.getLocInfo() == CCValAssign::Indirect)
2063 if (VA.needsCustom()) {
2064 // f64 and vector types are split into multiple registers or
2065 // register/stack-slot combinations. The types will not match
2066 // the registers; give up on memory f64 refs until we figure
2067 // out what to do about this.
2070 if (!ArgLocs[++i].isRegLoc())
2072 if (RegVT == MVT::v2f64) {
2073 if (!ArgLocs[++i].isRegLoc())
2075 if (!ArgLocs[++i].isRegLoc())
2078 } else if (!VA.isRegLoc()) {
2079 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2091 ARMTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
2092 MachineFunction &MF, bool isVarArg,
2093 const SmallVectorImpl<ISD::OutputArg> &Outs,
2094 LLVMContext &Context) const {
2095 SmallVector<CCValAssign, 16> RVLocs;
2096 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), RVLocs, Context);
2097 return CCInfo.CheckReturn(Outs, CCAssignFnForNode(CallConv, /*Return=*/true,
2101 static SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
2102 SDLoc DL, SelectionDAG &DAG) {
2103 const MachineFunction &MF = DAG.getMachineFunction();
2104 const Function *F = MF.getFunction();
2106 StringRef IntKind = F->getFnAttribute("interrupt").getValueAsString();
2108 // See ARM ARM v7 B1.8.3. On exception entry LR is set to a possibly offset
2109 // version of the "preferred return address". These offsets affect the return
2110 // instruction if this is a return from PL1 without hypervisor extensions.
2111 // IRQ/FIQ: +4 "subs pc, lr, #4"
2112 // SWI: 0 "subs pc, lr, #0"
2113 // ABORT: +4 "subs pc, lr, #4"
2114 // UNDEF: +4/+2 "subs pc, lr, #0"
2115 // UNDEF varies depending on where the exception came from ARM or Thumb
2116 // mode. Alongside GCC, we throw our hands up in disgust and pretend it's 0.
2119 if (IntKind == "" || IntKind == "IRQ" || IntKind == "FIQ" ||
2122 else if (IntKind == "SWI" || IntKind == "UNDEF")
2125 report_fatal_error("Unsupported interrupt attribute. If present, value "
2126 "must be one of: IRQ, FIQ, SWI, ABORT or UNDEF");
2128 RetOps.insert(RetOps.begin() + 1, DAG.getConstant(LROffset, MVT::i32, false));
2130 return DAG.getNode(ARMISD::INTRET_FLAG, DL, MVT::Other,
2131 RetOps.data(), RetOps.size());
2135 ARMTargetLowering::LowerReturn(SDValue Chain,
2136 CallingConv::ID CallConv, bool isVarArg,
2137 const SmallVectorImpl<ISD::OutputArg> &Outs,
2138 const SmallVectorImpl<SDValue> &OutVals,
2139 SDLoc dl, SelectionDAG &DAG) const {
2141 // CCValAssign - represent the assignment of the return value to a location.
2142 SmallVector<CCValAssign, 16> RVLocs;
2144 // CCState - Info about the registers and stack slots.
2145 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2146 getTargetMachine(), RVLocs, *DAG.getContext(), Call);
2148 // Analyze outgoing return values.
2149 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
2153 SmallVector<SDValue, 4> RetOps;
2154 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2156 // Copy the result values into the output registers.
2157 for (unsigned i = 0, realRVLocIdx = 0;
2159 ++i, ++realRVLocIdx) {
2160 CCValAssign &VA = RVLocs[i];
2161 assert(VA.isRegLoc() && "Can only return in registers!");
2163 SDValue Arg = OutVals[realRVLocIdx];
2165 switch (VA.getLocInfo()) {
2166 default: llvm_unreachable("Unknown loc info!");
2167 case CCValAssign::Full: break;
2168 case CCValAssign::BCvt:
2169 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2173 if (VA.needsCustom()) {
2174 if (VA.getLocVT() == MVT::v2f64) {
2175 // Extract the first half and return it in two registers.
2176 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2177 DAG.getConstant(0, MVT::i32));
2178 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
2179 DAG.getVTList(MVT::i32, MVT::i32), Half);
2181 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
2182 Flag = Chain.getValue(1);
2183 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2184 VA = RVLocs[++i]; // skip ahead to next loc
2185 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2186 HalfGPRs.getValue(1), Flag);
2187 Flag = Chain.getValue(1);
2188 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2189 VA = RVLocs[++i]; // skip ahead to next loc
2191 // Extract the 2nd half and fall through to handle it as an f64 value.
2192 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2193 DAG.getConstant(1, MVT::i32));
2195 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
2197 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
2198 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
2199 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
2200 Flag = Chain.getValue(1);
2201 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2202 VA = RVLocs[++i]; // skip ahead to next loc
2203 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
2206 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
2208 // Guarantee that all emitted copies are
2209 // stuck together, avoiding something bad.
2210 Flag = Chain.getValue(1);
2211 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2214 // Update chain and glue.
2217 RetOps.push_back(Flag);
2219 // CPUs which aren't M-class use a special sequence to return from
2220 // exceptions (roughly, any instruction setting pc and cpsr simultaneously,
2221 // though we use "subs pc, lr, #N").
2223 // M-class CPUs actually use a normal return sequence with a special
2224 // (hardware-provided) value in LR, so the normal code path works.
2225 if (DAG.getMachineFunction().getFunction()->hasFnAttribute("interrupt") &&
2226 !Subtarget->isMClass()) {
2227 if (Subtarget->isThumb1Only())
2228 report_fatal_error("interrupt attribute is not supported in Thumb1");
2229 return LowerInterruptReturn(RetOps, dl, DAG);
2232 return DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other,
2233 RetOps.data(), RetOps.size());
2236 bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2237 if (N->getNumValues() != 1)
2239 if (!N->hasNUsesOfValue(1, 0))
2242 SDValue TCChain = Chain;
2243 SDNode *Copy = *N->use_begin();
2244 if (Copy->getOpcode() == ISD::CopyToReg) {
2245 // If the copy has a glue operand, we conservatively assume it isn't safe to
2246 // perform a tail call.
2247 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2249 TCChain = Copy->getOperand(0);
2250 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) {
2251 SDNode *VMov = Copy;
2252 // f64 returned in a pair of GPRs.
2253 SmallPtrSet<SDNode*, 2> Copies;
2254 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2256 if (UI->getOpcode() != ISD::CopyToReg)
2260 if (Copies.size() > 2)
2263 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2265 SDValue UseChain = UI->getOperand(0);
2266 if (Copies.count(UseChain.getNode()))
2273 } else if (Copy->getOpcode() == ISD::BITCAST) {
2274 // f32 returned in a single GPR.
2275 if (!Copy->hasOneUse())
2277 Copy = *Copy->use_begin();
2278 if (Copy->getOpcode() != ISD::CopyToReg || !Copy->hasNUsesOfValue(1, 0))
2280 TCChain = Copy->getOperand(0);
2285 bool HasRet = false;
2286 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2288 if (UI->getOpcode() != ARMISD::RET_FLAG &&
2289 UI->getOpcode() != ARMISD::INTRET_FLAG)
2301 bool ARMTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2302 if (!EnableARMTailCalls && !Subtarget->supportsTailCall())
2305 if (!CI->isTailCall())
2308 return !Subtarget->isThumb1Only();
2311 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
2312 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
2313 // one of the above mentioned nodes. It has to be wrapped because otherwise
2314 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
2315 // be used to form addressing mode. These wrapped nodes will be selected
2317 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
2318 EVT PtrVT = Op.getValueType();
2319 // FIXME there is no actual debug info here
2321 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2323 if (CP->isMachineConstantPoolEntry())
2324 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
2325 CP->getAlignment());
2327 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
2328 CP->getAlignment());
2329 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
2332 unsigned ARMTargetLowering::getJumpTableEncoding() const {
2333 return MachineJumpTableInfo::EK_Inline;
2336 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
2337 SelectionDAG &DAG) const {
2338 MachineFunction &MF = DAG.getMachineFunction();
2339 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2340 unsigned ARMPCLabelIndex = 0;
2342 EVT PtrVT = getPointerTy();
2343 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
2344 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2346 if (RelocM == Reloc::Static) {
2347 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
2349 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2350 ARMPCLabelIndex = AFI->createPICLabelUId();
2351 ARMConstantPoolValue *CPV =
2352 ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex,
2353 ARMCP::CPBlockAddress, PCAdj);
2354 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2356 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
2357 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
2358 MachinePointerInfo::getConstantPool(),
2359 false, false, false, 0);
2360 if (RelocM == Reloc::Static)
2362 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2363 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
2366 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
2368 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
2369 SelectionDAG &DAG) const {
2371 EVT PtrVT = getPointerTy();
2372 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2373 MachineFunction &MF = DAG.getMachineFunction();
2374 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2375 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2376 ARMConstantPoolValue *CPV =
2377 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2378 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
2379 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2380 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
2381 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
2382 MachinePointerInfo::getConstantPool(),
2383 false, false, false, 0);
2384 SDValue Chain = Argument.getValue(1);
2386 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2387 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
2389 // call __tls_get_addr.
2392 Entry.Node = Argument;
2393 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
2394 Args.push_back(Entry);
2395 // FIXME: is there useful debug info available here?
2396 TargetLowering::CallLoweringInfo CLI(Chain,
2397 (Type *) Type::getInt32Ty(*DAG.getContext()),
2398 false, false, false, false,
2399 0, CallingConv::C, /*isTailCall=*/false,
2400 /*doesNotRet=*/false, /*isReturnValueUsed=*/true,
2401 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
2402 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2403 return CallResult.first;
2406 // Lower ISD::GlobalTLSAddress using the "initial exec" or
2407 // "local exec" model.
2409 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
2411 TLSModel::Model model) const {
2412 const GlobalValue *GV = GA->getGlobal();
2415 SDValue Chain = DAG.getEntryNode();
2416 EVT PtrVT = getPointerTy();
2417 // Get the Thread Pointer
2418 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2420 if (model == TLSModel::InitialExec) {
2421 MachineFunction &MF = DAG.getMachineFunction();
2422 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2423 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2424 // Initial exec model.
2425 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2426 ARMConstantPoolValue *CPV =
2427 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2428 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF,
2430 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2431 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2432 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2433 MachinePointerInfo::getConstantPool(),
2434 false, false, false, 0);
2435 Chain = Offset.getValue(1);
2437 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2438 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
2440 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2441 MachinePointerInfo::getConstantPool(),
2442 false, false, false, 0);
2445 assert(model == TLSModel::LocalExec);
2446 ARMConstantPoolValue *CPV =
2447 ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF);
2448 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2449 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2450 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2451 MachinePointerInfo::getConstantPool(),
2452 false, false, false, 0);
2455 // The address of the thread local variable is the add of the thread
2456 // pointer with the offset of the variable.
2457 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
2461 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
2462 // TODO: implement the "local dynamic" model
2463 assert(Subtarget->isTargetELF() &&
2464 "TLS not implemented for non-ELF targets");
2465 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2467 TLSModel::Model model = getTargetMachine().getTLSModel(GA->getGlobal());
2470 case TLSModel::GeneralDynamic:
2471 case TLSModel::LocalDynamic:
2472 return LowerToTLSGeneralDynamicModel(GA, DAG);
2473 case TLSModel::InitialExec:
2474 case TLSModel::LocalExec:
2475 return LowerToTLSExecModels(GA, DAG, model);
2477 llvm_unreachable("bogus TLS model");
2480 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
2481 SelectionDAG &DAG) const {
2482 EVT PtrVT = getPointerTy();
2484 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2485 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2486 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
2487 ARMConstantPoolValue *CPV =
2488 ARMConstantPoolConstant::Create(GV,
2489 UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
2490 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2491 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2492 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
2494 MachinePointerInfo::getConstantPool(),
2495 false, false, false, 0);
2496 SDValue Chain = Result.getValue(1);
2497 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
2498 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
2500 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
2501 MachinePointerInfo::getGOT(),
2502 false, false, false, 0);
2506 // If we have T2 ops, we can materialize the address directly via movt/movw
2507 // pair. This is always cheaper.
2508 if (Subtarget->useMovt()) {
2510 // FIXME: Once remat is capable of dealing with instructions with register
2511 // operands, expand this into two nodes.
2512 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2513 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2515 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
2516 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2517 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2518 MachinePointerInfo::getConstantPool(),
2519 false, false, false, 0);
2523 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
2524 SelectionDAG &DAG) const {
2525 EVT PtrVT = getPointerTy();
2527 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2528 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2530 if (Subtarget->useMovt())
2533 // FIXME: Once remat is capable of dealing with instructions with register
2534 // operands, expand this into multiple nodes
2536 RelocM == Reloc::PIC_ ? ARMISD::WrapperPIC : ARMISD::Wrapper;
2538 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_NONLAZY);
2539 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT, G);
2541 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
2542 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
2543 MachinePointerInfo::getGOT(), false, false, false, 0);
2547 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
2548 SelectionDAG &DAG) const {
2549 assert(Subtarget->isTargetELF() &&
2550 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
2551 MachineFunction &MF = DAG.getMachineFunction();
2552 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2553 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2554 EVT PtrVT = getPointerTy();
2556 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2557 ARMConstantPoolValue *CPV =
2558 ARMConstantPoolSymbol::Create(*DAG.getContext(), "_GLOBAL_OFFSET_TABLE_",
2559 ARMPCLabelIndex, PCAdj);
2560 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2561 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2562 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2563 MachinePointerInfo::getConstantPool(),
2564 false, false, false, 0);
2565 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2566 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2570 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
2572 SDValue Val = DAG.getConstant(0, MVT::i32);
2573 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl,
2574 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
2575 Op.getOperand(1), Val);
2579 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
2581 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
2582 Op.getOperand(1), DAG.getConstant(0, MVT::i32));
2586 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
2587 const ARMSubtarget *Subtarget) const {
2588 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2591 default: return SDValue(); // Don't custom lower most intrinsics.
2592 case Intrinsic::arm_thread_pointer: {
2593 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2594 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2596 case Intrinsic::eh_sjlj_lsda: {
2597 MachineFunction &MF = DAG.getMachineFunction();
2598 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2599 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2600 EVT PtrVT = getPointerTy();
2601 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2603 unsigned PCAdj = (RelocM != Reloc::PIC_)
2604 ? 0 : (Subtarget->isThumb() ? 4 : 8);
2605 ARMConstantPoolValue *CPV =
2606 ARMConstantPoolConstant::Create(MF.getFunction(), ARMPCLabelIndex,
2607 ARMCP::CPLSDA, PCAdj);
2608 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2609 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2611 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2612 MachinePointerInfo::getConstantPool(),
2613 false, false, false, 0);
2615 if (RelocM == Reloc::PIC_) {
2616 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2617 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2621 case Intrinsic::arm_neon_vmulls:
2622 case Intrinsic::arm_neon_vmullu: {
2623 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
2624 ? ARMISD::VMULLs : ARMISD::VMULLu;
2625 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
2626 Op.getOperand(1), Op.getOperand(2));
2631 static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
2632 const ARMSubtarget *Subtarget) {
2633 // FIXME: handle "fence singlethread" more efficiently.
2635 if (!Subtarget->hasDataBarrier()) {
2636 // Some ARMv6 cpus can support data barriers with an mcr instruction.
2637 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
2639 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&
2640 "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!");
2641 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2642 DAG.getConstant(0, MVT::i32));
2645 ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1));
2646 AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue());
2647 unsigned Domain = ARM_MB::ISH;
2648 if (Subtarget->isMClass()) {
2649 // Only a full system barrier exists in the M-class architectures.
2650 Domain = ARM_MB::SY;
2651 } else if (Subtarget->isSwift() && Ord == Release) {
2652 // Swift happens to implement ISHST barriers in a way that's compatible with
2653 // Release semantics but weaker than ISH so we'd be fools not to use
2654 // it. Beware: other processors probably don't!
2655 Domain = ARM_MB::ISHST;
2658 return DAG.getNode(ISD::INTRINSIC_VOID, dl, MVT::Other, Op.getOperand(0),
2659 DAG.getConstant(Intrinsic::arm_dmb, MVT::i32),
2660 DAG.getConstant(Domain, MVT::i32));
2663 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
2664 const ARMSubtarget *Subtarget) {
2665 // ARM pre v5TE and Thumb1 does not have preload instructions.
2666 if (!(Subtarget->isThumb2() ||
2667 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
2668 // Just preserve the chain.
2669 return Op.getOperand(0);
2672 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
2674 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
2675 // ARMv7 with MP extension has PLDW.
2676 return Op.getOperand(0);
2678 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
2679 if (Subtarget->isThumb()) {
2681 isRead = ~isRead & 1;
2682 isData = ~isData & 1;
2685 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
2686 Op.getOperand(1), DAG.getConstant(isRead, MVT::i32),
2687 DAG.getConstant(isData, MVT::i32));
2690 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
2691 MachineFunction &MF = DAG.getMachineFunction();
2692 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
2694 // vastart just stores the address of the VarArgsFrameIndex slot into the
2695 // memory location argument.
2697 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2698 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2699 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2700 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2701 MachinePointerInfo(SV), false, false, 0);
2705 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
2706 SDValue &Root, SelectionDAG &DAG,
2708 MachineFunction &MF = DAG.getMachineFunction();
2709 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2711 const TargetRegisterClass *RC;
2712 if (AFI->isThumb1OnlyFunction())
2713 RC = &ARM::tGPRRegClass;
2715 RC = &ARM::GPRRegClass;
2717 // Transform the arguments stored in physical registers into virtual ones.
2718 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2719 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2722 if (NextVA.isMemLoc()) {
2723 MachineFrameInfo *MFI = MF.getFrameInfo();
2724 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
2726 // Create load node to retrieve arguments from the stack.
2727 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2728 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
2729 MachinePointerInfo::getFixedStack(FI),
2730 false, false, false, 0);
2732 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2733 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2736 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
2740 ARMTargetLowering::computeRegArea(CCState &CCInfo, MachineFunction &MF,
2741 unsigned InRegsParamRecordIdx,
2743 unsigned &ArgRegsSize,
2744 unsigned &ArgRegsSaveSize)
2747 if (InRegsParamRecordIdx < CCInfo.getInRegsParamsCount()) {
2748 unsigned RBegin, REnd;
2749 CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd);
2750 NumGPRs = REnd - RBegin;
2752 unsigned int firstUnalloced;
2753 firstUnalloced = CCInfo.getFirstUnallocated(GPRArgRegs,
2754 sizeof(GPRArgRegs) /
2755 sizeof(GPRArgRegs[0]));
2756 NumGPRs = (firstUnalloced <= 3) ? (4 - firstUnalloced) : 0;
2759 unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment();
2760 ArgRegsSize = NumGPRs * 4;
2762 // If parameter is split between stack and GPRs...
2763 if (NumGPRs && Align == 8 &&
2764 (ArgRegsSize < ArgSize ||
2765 InRegsParamRecordIdx >= CCInfo.getInRegsParamsCount())) {
2766 // Add padding for part of param recovered from GPRs, so
2767 // its last byte must be at address K*8 - 1.
2768 // We need to do it, since remained (stack) part of parameter has
2769 // stack alignment, and we need to "attach" "GPRs head" without gaps
2772 // |---- 8 bytes block ----| |---- 8 bytes block ----| |---- 8 bytes...
2773 // [ [padding] [GPRs head] ] [ Tail passed via stack ....
2775 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2777 ((ArgRegsSize + AFI->getArgRegsSaveSize() + Align - 1) & ~(Align-1)) -
2778 (ArgRegsSize + AFI->getArgRegsSaveSize());
2779 ArgRegsSaveSize = ArgRegsSize + Padding;
2781 // We don't need to extend regs save size for byval parameters if they
2782 // are passed via GPRs only.
2783 ArgRegsSaveSize = ArgRegsSize;
2786 // The remaining GPRs hold either the beginning of variable-argument
2787 // data, or the beginning of an aggregate passed by value (usually
2788 // byval). Either way, we allocate stack slots adjacent to the data
2789 // provided by our caller, and store the unallocated registers there.
2790 // If this is a variadic function, the va_list pointer will begin with
2791 // these values; otherwise, this reassembles a (byval) structure that
2792 // was split between registers and memory.
2793 // Return: The frame index registers were stored into.
2795 ARMTargetLowering::StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
2796 SDLoc dl, SDValue &Chain,
2797 const Value *OrigArg,
2798 unsigned InRegsParamRecordIdx,
2799 unsigned OffsetFromOrigArg,
2802 bool ForceMutable) const {
2804 // Currently, two use-cases possible:
2805 // Case #1. Non-var-args function, and we meet first byval parameter.
2806 // Setup first unallocated register as first byval register;
2807 // eat all remained registers
2808 // (these two actions are performed by HandleByVal method).
2809 // Then, here, we initialize stack frame with
2810 // "store-reg" instructions.
2811 // Case #2. Var-args function, that doesn't contain byval parameters.
2812 // The same: eat all remained unallocated registers,
2813 // initialize stack frame.
2815 MachineFunction &MF = DAG.getMachineFunction();
2816 MachineFrameInfo *MFI = MF.getFrameInfo();
2817 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2818 unsigned firstRegToSaveIndex, lastRegToSaveIndex;
2819 unsigned RBegin, REnd;
2820 if (InRegsParamRecordIdx < CCInfo.getInRegsParamsCount()) {
2821 CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd);
2822 firstRegToSaveIndex = RBegin - ARM::R0;
2823 lastRegToSaveIndex = REnd - ARM::R0;
2825 firstRegToSaveIndex = CCInfo.getFirstUnallocated
2826 (GPRArgRegs, array_lengthof(GPRArgRegs));
2827 lastRegToSaveIndex = 4;
2830 unsigned ArgRegsSize, ArgRegsSaveSize;
2831 computeRegArea(CCInfo, MF, InRegsParamRecordIdx, ArgSize,
2832 ArgRegsSize, ArgRegsSaveSize);
2834 // Store any by-val regs to their spots on the stack so that they may be
2835 // loaded by deferencing the result of formal parameter pointer or va_next.
2836 // Note: once stack area for byval/varargs registers
2837 // was initialized, it can't be initialized again.
2838 if (ArgRegsSaveSize) {
2840 unsigned Padding = ArgRegsSaveSize - ArgRegsSize;
2843 assert(AFI->getStoredByValParamsPadding() == 0 &&
2844 "The only parameter may be padded.");
2845 AFI->setStoredByValParamsPadding(Padding);
2848 int FrameIndex = MFI->CreateFixedObject(
2850 Padding + ArgOffset,
2852 SDValue FIN = DAG.getFrameIndex(FrameIndex, getPointerTy());
2854 SmallVector<SDValue, 4> MemOps;
2855 for (unsigned i = 0; firstRegToSaveIndex < lastRegToSaveIndex;
2856 ++firstRegToSaveIndex, ++i) {
2857 const TargetRegisterClass *RC;
2858 if (AFI->isThumb1OnlyFunction())
2859 RC = &ARM::tGPRRegClass;
2861 RC = &ARM::GPRRegClass;
2863 unsigned VReg = MF.addLiveIn(GPRArgRegs[firstRegToSaveIndex], RC);
2864 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2866 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2867 MachinePointerInfo(OrigArg, OffsetFromOrigArg + 4*i),
2869 MemOps.push_back(Store);
2870 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
2871 DAG.getConstant(4, getPointerTy()));
2874 AFI->setArgRegsSaveSize(ArgRegsSaveSize + AFI->getArgRegsSaveSize());
2876 if (!MemOps.empty())
2877 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2878 &MemOps[0], MemOps.size());
2881 // This will point to the next argument passed via stack.
2882 return MFI->CreateFixedObject(
2883 4, AFI->getStoredByValParamsPadding() + ArgOffset, !ForceMutable);
2886 // Setup stack frame, the va_list pointer will start from.
2888 ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
2889 SDLoc dl, SDValue &Chain,
2891 bool ForceMutable) const {
2892 MachineFunction &MF = DAG.getMachineFunction();
2893 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2895 // Try to store any remaining integer argument regs
2896 // to their spots on the stack so that they may be loaded by deferencing
2897 // the result of va_next.
2898 // If there is no regs to be stored, just point address after last
2899 // argument passed via stack.
2901 StoreByValRegs(CCInfo, DAG, dl, Chain, 0, CCInfo.getInRegsParamsCount(),
2902 0, ArgOffset, 0, ForceMutable);
2904 AFI->setVarArgsFrameIndex(FrameIndex);
2908 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
2909 CallingConv::ID CallConv, bool isVarArg,
2910 const SmallVectorImpl<ISD::InputArg>
2912 SDLoc dl, SelectionDAG &DAG,
2913 SmallVectorImpl<SDValue> &InVals)
2915 MachineFunction &MF = DAG.getMachineFunction();
2916 MachineFrameInfo *MFI = MF.getFrameInfo();
2918 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2920 // Assign locations to all of the incoming arguments.
2921 SmallVector<CCValAssign, 16> ArgLocs;
2922 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2923 getTargetMachine(), ArgLocs, *DAG.getContext(), Prologue);
2924 CCInfo.AnalyzeFormalArguments(Ins,
2925 CCAssignFnForNode(CallConv, /* Return*/ false,
2928 SmallVector<SDValue, 16> ArgValues;
2929 int lastInsIndex = -1;
2931 Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin();
2932 unsigned CurArgIdx = 0;
2934 // Initially ArgRegsSaveSize is zero.
2935 // Then we increase this value each time we meet byval parameter.
2936 // We also increase this value in case of varargs function.
2937 AFI->setArgRegsSaveSize(0);
2939 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2940 CCValAssign &VA = ArgLocs[i];
2941 std::advance(CurOrigArg, Ins[VA.getValNo()].OrigArgIndex - CurArgIdx);
2942 CurArgIdx = Ins[VA.getValNo()].OrigArgIndex;
2943 // Arguments stored in registers.
2944 if (VA.isRegLoc()) {
2945 EVT RegVT = VA.getLocVT();
2947 if (VA.needsCustom()) {
2948 // f64 and vector types are split up into multiple registers or
2949 // combinations of registers and stack slots.
2950 if (VA.getLocVT() == MVT::v2f64) {
2951 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
2953 VA = ArgLocs[++i]; // skip ahead to next loc
2955 if (VA.isMemLoc()) {
2956 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
2957 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2958 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
2959 MachinePointerInfo::getFixedStack(FI),
2960 false, false, false, 0);
2962 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
2965 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2966 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2967 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
2968 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2969 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
2971 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
2974 const TargetRegisterClass *RC;
2976 if (RegVT == MVT::f32)
2977 RC = &ARM::SPRRegClass;
2978 else if (RegVT == MVT::f64)
2979 RC = &ARM::DPRRegClass;
2980 else if (RegVT == MVT::v2f64)
2981 RC = &ARM::QPRRegClass;
2982 else if (RegVT == MVT::i32)
2983 RC = AFI->isThumb1OnlyFunction() ?
2984 (const TargetRegisterClass*)&ARM::tGPRRegClass :
2985 (const TargetRegisterClass*)&ARM::GPRRegClass;
2987 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2989 // Transform the arguments in physical registers into virtual ones.
2990 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2991 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2994 // If this is an 8 or 16-bit value, it is really passed promoted
2995 // to 32 bits. Insert an assert[sz]ext to capture this, then
2996 // truncate to the right size.
2997 switch (VA.getLocInfo()) {
2998 default: llvm_unreachable("Unknown loc info!");
2999 case CCValAssign::Full: break;
3000 case CCValAssign::BCvt:
3001 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
3003 case CCValAssign::SExt:
3004 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
3005 DAG.getValueType(VA.getValVT()));
3006 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3008 case CCValAssign::ZExt:
3009 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
3010 DAG.getValueType(VA.getValVT()));
3011 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3015 InVals.push_back(ArgValue);
3017 } else { // VA.isRegLoc()
3020 assert(VA.isMemLoc());
3021 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
3023 int index = ArgLocs[i].getValNo();
3025 // Some Ins[] entries become multiple ArgLoc[] entries.
3026 // Process them only once.
3027 if (index != lastInsIndex)
3029 ISD::ArgFlagsTy Flags = Ins[index].Flags;
3030 // FIXME: For now, all byval parameter objects are marked mutable.
3031 // This can be changed with more analysis.
3032 // In case of tail call optimization mark all arguments mutable.
3033 // Since they could be overwritten by lowering of arguments in case of
3035 if (Flags.isByVal()) {
3036 unsigned CurByValIndex = CCInfo.getInRegsParamsProceed();
3037 int FrameIndex = StoreByValRegs(
3038 CCInfo, DAG, dl, Chain, CurOrigArg,
3040 Ins[VA.getValNo()].PartOffset,
3041 VA.getLocMemOffset(),
3042 Flags.getByValSize(),
3043 true /*force mutable frames*/);
3044 InVals.push_back(DAG.getFrameIndex(FrameIndex, getPointerTy()));
3045 CCInfo.nextInRegsParam();
3047 unsigned FIOffset = VA.getLocMemOffset() +
3048 AFI->getStoredByValParamsPadding();
3049 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
3052 // Create load nodes to retrieve arguments from the stack.
3053 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
3054 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
3055 MachinePointerInfo::getFixedStack(FI),
3056 false, false, false, 0));
3058 lastInsIndex = index;
3065 VarArgStyleRegisters(CCInfo, DAG, dl, Chain,
3066 CCInfo.getNextStackOffset());
3071 /// isFloatingPointZero - Return true if this is +0.0.
3072 static bool isFloatingPointZero(SDValue Op) {
3073 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
3074 return CFP->getValueAPF().isPosZero();
3075 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
3076 // Maybe this has already been legalized into the constant pool?
3077 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
3078 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
3079 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
3080 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
3081 return CFP->getValueAPF().isPosZero();
3087 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
3088 /// the given operands.
3090 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
3091 SDValue &ARMcc, SelectionDAG &DAG,
3093 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
3094 unsigned C = RHSC->getZExtValue();
3095 if (!isLegalICmpImmediate(C)) {
3096 // Constant does not fit, try adjusting it by one?
3101 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
3102 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
3103 RHS = DAG.getConstant(C-1, MVT::i32);
3108 if (C != 0 && isLegalICmpImmediate(C-1)) {
3109 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
3110 RHS = DAG.getConstant(C-1, MVT::i32);
3115 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
3116 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
3117 RHS = DAG.getConstant(C+1, MVT::i32);
3122 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
3123 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
3124 RHS = DAG.getConstant(C+1, MVT::i32);
3131 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3132 ARMISD::NodeType CompareType;
3135 CompareType = ARMISD::CMP;
3140 CompareType = ARMISD::CMPZ;
3143 ARMcc = DAG.getConstant(CondCode, MVT::i32);
3144 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
3147 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
3149 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
3152 if (!isFloatingPointZero(RHS))
3153 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS);
3155 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS);
3156 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
3159 /// duplicateCmp - Glue values can have only one use, so this function
3160 /// duplicates a comparison node.
3162 ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
3163 unsigned Opc = Cmp.getOpcode();
3165 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
3166 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
3168 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation");
3169 Cmp = Cmp.getOperand(0);
3170 Opc = Cmp.getOpcode();
3171 if (Opc == ARMISD::CMPFP)
3172 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
3174 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT");
3175 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0));
3177 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
3180 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
3181 SDValue Cond = Op.getOperand(0);
3182 SDValue SelectTrue = Op.getOperand(1);
3183 SDValue SelectFalse = Op.getOperand(2);
3188 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
3189 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
3191 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
3192 const ConstantSDNode *CMOVTrue =
3193 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
3194 const ConstantSDNode *CMOVFalse =
3195 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
3197 if (CMOVTrue && CMOVFalse) {
3198 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
3199 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
3203 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
3205 False = SelectFalse;
3206 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
3211 if (True.getNode() && False.getNode()) {
3212 EVT VT = Op.getValueType();
3213 SDValue ARMcc = Cond.getOperand(2);
3214 SDValue CCR = Cond.getOperand(3);
3215 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
3216 assert(True.getValueType() == VT);
3217 return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp);
3222 // ARM's BooleanContents value is UndefinedBooleanContent. Mask out the
3223 // undefined bits before doing a full-word comparison with zero.
3224 Cond = DAG.getNode(ISD::AND, dl, Cond.getValueType(), Cond,
3225 DAG.getConstant(1, Cond.getValueType()));
3227 return DAG.getSelectCC(dl, Cond,
3228 DAG.getConstant(0, Cond.getValueType()),
3229 SelectTrue, SelectFalse, ISD::SETNE);
3232 static ISD::CondCode getInverseCCForVSEL(ISD::CondCode CC) {
3233 if (CC == ISD::SETNE)
3235 return ISD::getSetCCInverse(CC, true);
3238 static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
3239 bool &swpCmpOps, bool &swpVselOps) {
3240 // Start by selecting the GE condition code for opcodes that return true for
3242 if (CC == ISD::SETUGE || CC == ISD::SETOGE || CC == ISD::SETOLE ||
3244 CondCode = ARMCC::GE;
3246 // and GT for opcodes that return false for 'equality'.
3247 else if (CC == ISD::SETUGT || CC == ISD::SETOGT || CC == ISD::SETOLT ||
3249 CondCode = ARMCC::GT;
3251 // Since we are constrained to GE/GT, if the opcode contains 'less', we need
3252 // to swap the compare operands.
3253 if (CC == ISD::SETOLE || CC == ISD::SETULE || CC == ISD::SETOLT ||
3257 // Both GT and GE are ordered comparisons, and return false for 'unordered'.
3258 // If we have an unordered opcode, we need to swap the operands to the VSEL
3259 // instruction (effectively negating the condition).
3261 // This also has the effect of swapping which one of 'less' or 'greater'
3262 // returns true, so we also swap the compare operands. It also switches
3263 // whether we return true for 'equality', so we compensate by picking the
3264 // opposite condition code to our original choice.
3265 if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE ||
3266 CC == ISD::SETUGT) {
3267 swpCmpOps = !swpCmpOps;
3268 swpVselOps = !swpVselOps;
3269 CondCode = CondCode == ARMCC::GT ? ARMCC::GE : ARMCC::GT;
3272 // 'ordered' is 'anything but unordered', so use the VS condition code and
3273 // swap the VSEL operands.
3274 if (CC == ISD::SETO) {
3275 CondCode = ARMCC::VS;
3279 // 'unordered or not equal' is 'anything but equal', so use the EQ condition
3280 // code and swap the VSEL operands.
3281 if (CC == ISD::SETUNE) {
3282 CondCode = ARMCC::EQ;
3287 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
3288 EVT VT = Op.getValueType();
3289 SDValue LHS = Op.getOperand(0);
3290 SDValue RHS = Op.getOperand(1);
3291 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3292 SDValue TrueVal = Op.getOperand(2);
3293 SDValue FalseVal = Op.getOperand(3);
3296 if (LHS.getValueType() == MVT::i32) {
3297 // Try to generate VSEL on ARMv8.
3298 // The VSEL instruction can't use all the usual ARM condition
3299 // codes: it only has two bits to select the condition code, so it's
3300 // constrained to use only GE, GT, VS and EQ.
3302 // To implement all the various ISD::SETXXX opcodes, we sometimes need to
3303 // swap the operands of the previous compare instruction (effectively
3304 // inverting the compare condition, swapping 'less' and 'greater') and
3305 // sometimes need to swap the operands to the VSEL (which inverts the
3306 // condition in the sense of firing whenever the previous condition didn't)
3307 if (getSubtarget()->hasFPARMv8() && (TrueVal.getValueType() == MVT::f32 ||
3308 TrueVal.getValueType() == MVT::f64)) {
3309 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3310 if (CondCode == ARMCC::LT || CondCode == ARMCC::LE ||
3311 CondCode == ARMCC::VC || CondCode == ARMCC::NE) {
3312 CC = getInverseCCForVSEL(CC);
3313 std::swap(TrueVal, FalseVal);
3318 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3319 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3320 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,
3324 ARMCC::CondCodes CondCode, CondCode2;
3325 FPCCToARMCC(CC, CondCode, CondCode2);
3327 // Try to generate VSEL on ARMv8.
3328 if (getSubtarget()->hasFPARMv8() && (TrueVal.getValueType() == MVT::f32 ||
3329 TrueVal.getValueType() == MVT::f64)) {
3330 // We can select VMAXNM/VMINNM from a compare followed by a select with the
3331 // same operands, as follows:
3332 // c = fcmp [ogt, olt, ugt, ult] a, b
3334 // We only do this in unsafe-fp-math, because signed zeros and NaNs are
3335 // handled differently than the original code sequence.
3336 if (getTargetMachine().Options.UnsafeFPMath && LHS == TrueVal &&
3338 if (CC == ISD::SETOGT || CC == ISD::SETUGT)
3339 return DAG.getNode(ARMISD::VMAXNM, dl, VT, TrueVal, FalseVal);
3340 if (CC == ISD::SETOLT || CC == ISD::SETULT)
3341 return DAG.getNode(ARMISD::VMINNM, dl, VT, TrueVal, FalseVal);
3344 bool swpCmpOps = false;
3345 bool swpVselOps = false;
3346 checkVSELConstraints(CC, CondCode, swpCmpOps, swpVselOps);
3348 if (CondCode == ARMCC::GT || CondCode == ARMCC::GE ||
3349 CondCode == ARMCC::VS || CondCode == ARMCC::EQ) {
3351 std::swap(LHS, RHS);
3353 std::swap(TrueVal, FalseVal);
3357 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
3358 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
3359 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3360 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
3362 if (CondCode2 != ARMCC::AL) {
3363 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32);
3364 // FIXME: Needs another CMP because flag can have but one use.
3365 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
3366 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
3367 Result, TrueVal, ARMcc2, CCR, Cmp2);
3372 /// canChangeToInt - Given the fp compare operand, return true if it is suitable
3373 /// to morph to an integer compare sequence.
3374 static bool canChangeToInt(SDValue Op, bool &SeenZero,
3375 const ARMSubtarget *Subtarget) {
3376 SDNode *N = Op.getNode();
3377 if (!N->hasOneUse())
3378 // Otherwise it requires moving the value from fp to integer registers.
3380 if (!N->getNumValues())
3382 EVT VT = Op.getValueType();
3383 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
3384 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
3385 // vmrs are very slow, e.g. cortex-a8.
3388 if (isFloatingPointZero(Op)) {
3392 return ISD::isNormalLoad(N);
3395 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
3396 if (isFloatingPointZero(Op))
3397 return DAG.getConstant(0, MVT::i32);
3399 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
3400 return DAG.getLoad(MVT::i32, SDLoc(Op),
3401 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(),
3402 Ld->isVolatile(), Ld->isNonTemporal(),
3403 Ld->isInvariant(), Ld->getAlignment());
3405 llvm_unreachable("Unknown VFP cmp argument!");
3408 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
3409 SDValue &RetVal1, SDValue &RetVal2) {
3410 if (isFloatingPointZero(Op)) {
3411 RetVal1 = DAG.getConstant(0, MVT::i32);
3412 RetVal2 = DAG.getConstant(0, MVT::i32);
3416 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
3417 SDValue Ptr = Ld->getBasePtr();
3418 RetVal1 = DAG.getLoad(MVT::i32, SDLoc(Op),
3419 Ld->getChain(), Ptr,
3420 Ld->getPointerInfo(),
3421 Ld->isVolatile(), Ld->isNonTemporal(),
3422 Ld->isInvariant(), Ld->getAlignment());
3424 EVT PtrType = Ptr.getValueType();
3425 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
3426 SDValue NewPtr = DAG.getNode(ISD::ADD, SDLoc(Op),
3427 PtrType, Ptr, DAG.getConstant(4, PtrType));
3428 RetVal2 = DAG.getLoad(MVT::i32, SDLoc(Op),
3429 Ld->getChain(), NewPtr,
3430 Ld->getPointerInfo().getWithOffset(4),
3431 Ld->isVolatile(), Ld->isNonTemporal(),
3432 Ld->isInvariant(), NewAlign);
3436 llvm_unreachable("Unknown VFP cmp argument!");
3439 /// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
3440 /// f32 and even f64 comparisons to integer ones.
3442 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
3443 SDValue Chain = Op.getOperand(0);
3444 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3445 SDValue LHS = Op.getOperand(2);
3446 SDValue RHS = Op.getOperand(3);
3447 SDValue Dest = Op.getOperand(4);
3450 bool LHSSeenZero = false;
3451 bool LHSOk = canChangeToInt(LHS, LHSSeenZero, Subtarget);
3452 bool RHSSeenZero = false;
3453 bool RHSOk = canChangeToInt(RHS, RHSSeenZero, Subtarget);
3454 if (LHSOk && RHSOk && (LHSSeenZero || RHSSeenZero)) {
3455 // If unsafe fp math optimization is enabled and there are no other uses of
3456 // the CMP operands, and the condition code is EQ or NE, we can optimize it
3457 // to an integer comparison.
3458 if (CC == ISD::SETOEQ)
3460 else if (CC == ISD::SETUNE)
3463 SDValue Mask = DAG.getConstant(0x7fffffff, MVT::i32);
3465 if (LHS.getValueType() == MVT::f32) {
3466 LHS = DAG.getNode(ISD::AND, dl, MVT::i32,
3467 bitcastf32Toi32(LHS, DAG), Mask);
3468 RHS = DAG.getNode(ISD::AND, dl, MVT::i32,
3469 bitcastf32Toi32(RHS, DAG), Mask);
3470 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3471 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3472 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
3473 Chain, Dest, ARMcc, CCR, Cmp);
3478 expandf64Toi32(LHS, DAG, LHS1, LHS2);
3479 expandf64Toi32(RHS, DAG, RHS1, RHS2);
3480 LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask);
3481 RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask);
3482 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3483 ARMcc = DAG.getConstant(CondCode, MVT::i32);
3484 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
3485 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
3486 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7);
3492 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
3493 SDValue Chain = Op.getOperand(0);
3494 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3495 SDValue LHS = Op.getOperand(2);
3496 SDValue RHS = Op.getOperand(3);
3497 SDValue Dest = Op.getOperand(4);
3500 if (LHS.getValueType() == MVT::i32) {
3502 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3503 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3504 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
3505 Chain, Dest, ARMcc, CCR, Cmp);
3508 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3510 if (getTargetMachine().Options.UnsafeFPMath &&
3511 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
3512 CC == ISD::SETNE || CC == ISD::SETUNE)) {
3513 SDValue Result = OptimizeVFPBrcond(Op, DAG);
3514 if (Result.getNode())
3518 ARMCC::CondCodes CondCode, CondCode2;
3519 FPCCToARMCC(CC, CondCode, CondCode2);
3521 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
3522 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
3523 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3524 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
3525 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
3526 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
3527 if (CondCode2 != ARMCC::AL) {
3528 ARMcc = DAG.getConstant(CondCode2, MVT::i32);
3529 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
3530 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
3535 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
3536 SDValue Chain = Op.getOperand(0);
3537 SDValue Table = Op.getOperand(1);
3538 SDValue Index = Op.getOperand(2);
3541 EVT PTy = getPointerTy();
3542 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
3543 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
3544 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
3545 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
3546 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
3547 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
3548 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
3549 if (Subtarget->isThumb2()) {
3550 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
3551 // which does another jump to the destination. This also makes it easier
3552 // to translate it to TBB / TBH later.
3553 // FIXME: This might not work if the function is extremely large.
3554 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
3555 Addr, Op.getOperand(2), JTI, UId);
3557 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
3558 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
3559 MachinePointerInfo::getJumpTable(),
3560 false, false, false, 0);
3561 Chain = Addr.getValue(1);
3562 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
3563 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
3565 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
3566 MachinePointerInfo::getJumpTable(),
3567 false, false, false, 0);
3568 Chain = Addr.getValue(1);
3569 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
3573 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
3574 EVT VT = Op.getValueType();
3577 if (Op.getValueType().getVectorElementType() == MVT::i32) {
3578 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32)
3580 return DAG.UnrollVectorOp(Op.getNode());
3583 assert(Op.getOperand(0).getValueType() == MVT::v4f32 &&
3584 "Invalid type for custom lowering!");
3585 if (VT != MVT::v4i16)
3586 return DAG.UnrollVectorOp(Op.getNode());
3588 Op = DAG.getNode(Op.getOpcode(), dl, MVT::v4i32, Op.getOperand(0));
3589 return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
3592 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
3593 EVT VT = Op.getValueType();
3595 return LowerVectorFP_TO_INT(Op, DAG);
3600 switch (Op.getOpcode()) {
3601 default: llvm_unreachable("Invalid opcode!");
3602 case ISD::FP_TO_SINT:
3603 Opc = ARMISD::FTOSI;
3605 case ISD::FP_TO_UINT:
3606 Opc = ARMISD::FTOUI;
3609 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
3610 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3613 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
3614 EVT VT = Op.getValueType();
3617 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) {
3618 if (VT.getVectorElementType() == MVT::f32)
3620 return DAG.UnrollVectorOp(Op.getNode());
3623 assert(Op.getOperand(0).getValueType() == MVT::v4i16 &&
3624 "Invalid type for custom lowering!");
3625 if (VT != MVT::v4f32)
3626 return DAG.UnrollVectorOp(Op.getNode());
3630 switch (Op.getOpcode()) {
3631 default: llvm_unreachable("Invalid opcode!");
3632 case ISD::SINT_TO_FP:
3633 CastOpc = ISD::SIGN_EXTEND;
3634 Opc = ISD::SINT_TO_FP;
3636 case ISD::UINT_TO_FP:
3637 CastOpc = ISD::ZERO_EXTEND;
3638 Opc = ISD::UINT_TO_FP;
3642 Op = DAG.getNode(CastOpc, dl, MVT::v4i32, Op.getOperand(0));
3643 return DAG.getNode(Opc, dl, VT, Op);
3646 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
3647 EVT VT = Op.getValueType();
3649 return LowerVectorINT_TO_FP(Op, DAG);
3654 switch (Op.getOpcode()) {
3655 default: llvm_unreachable("Invalid opcode!");
3656 case ISD::SINT_TO_FP:
3657 Opc = ARMISD::SITOF;
3659 case ISD::UINT_TO_FP:
3660 Opc = ARMISD::UITOF;
3664 Op = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0));
3665 return DAG.getNode(Opc, dl, VT, Op);
3668 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
3669 // Implement fcopysign with a fabs and a conditional fneg.
3670 SDValue Tmp0 = Op.getOperand(0);
3671 SDValue Tmp1 = Op.getOperand(1);
3673 EVT VT = Op.getValueType();
3674 EVT SrcVT = Tmp1.getValueType();
3675 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
3676 Tmp0.getOpcode() == ARMISD::VMOVDRR;
3677 bool UseNEON = !InGPR && Subtarget->hasNEON();
3680 // Use VBSL to copy the sign bit.
3681 unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80);
3682 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
3683 DAG.getTargetConstant(EncodedVal, MVT::i32));
3684 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
3686 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT,
3687 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
3688 DAG.getConstant(32, MVT::i32));
3689 else /*if (VT == MVT::f32)*/
3690 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
3691 if (SrcVT == MVT::f32) {
3692 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
3694 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT,
3695 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
3696 DAG.getConstant(32, MVT::i32));
3697 } else if (VT == MVT::f32)
3698 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64,
3699 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
3700 DAG.getConstant(32, MVT::i32));
3701 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
3702 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
3704 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff),
3706 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
3707 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
3708 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
3710 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
3711 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
3712 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
3713 if (VT == MVT::f32) {
3714 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
3715 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
3716 DAG.getConstant(0, MVT::i32));
3718 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
3724 // Bitcast operand 1 to i32.
3725 if (SrcVT == MVT::f64)
3726 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
3727 &Tmp1, 1).getValue(1);
3728 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
3730 // Or in the signbit with integer operations.
3731 SDValue Mask1 = DAG.getConstant(0x80000000, MVT::i32);
3732 SDValue Mask2 = DAG.getConstant(0x7fffffff, MVT::i32);
3733 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
3734 if (VT == MVT::f32) {
3735 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
3736 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
3737 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3738 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
3741 // f64: Or the high part with signbit and then combine two parts.
3742 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
3744 SDValue Lo = Tmp0.getValue(0);
3745 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
3746 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
3747 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
3750 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
3751 MachineFunction &MF = DAG.getMachineFunction();
3752 MachineFrameInfo *MFI = MF.getFrameInfo();
3753 MFI->setReturnAddressIsTaken(true);
3755 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
3758 EVT VT = Op.getValueType();
3760 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3762 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
3763 SDValue Offset = DAG.getConstant(4, MVT::i32);
3764 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
3765 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
3766 MachinePointerInfo(), false, false, false, 0);
3769 // Return LR, which contains the return address. Mark it an implicit live-in.
3770 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
3771 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
3774 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
3775 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3776 MFI->setFrameAddressIsTaken(true);
3778 EVT VT = Op.getValueType();
3779 SDLoc dl(Op); // FIXME probably not meaningful
3780 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3781 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetMachO())
3782 ? ARM::R7 : ARM::R11;
3783 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
3785 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
3786 MachinePointerInfo(),
3787 false, false, false, 0);
3791 /// ExpandBITCAST - If the target supports VFP, this function is called to
3792 /// expand a bit convert where either the source or destination type is i64 to
3793 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
3794 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
3795 /// vectors), since the legalizer won't know what to do with that.
3796 static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) {
3797 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3799 SDValue Op = N->getOperand(0);
3801 // This function is only supposed to be called for i64 types, either as the
3802 // source or destination of the bit convert.
3803 EVT SrcVT = Op.getValueType();
3804 EVT DstVT = N->getValueType(0);
3805 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
3806 "ExpandBITCAST called for non-i64 type");
3808 // Turn i64->f64 into VMOVDRR.
3809 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
3810 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
3811 DAG.getConstant(0, MVT::i32));
3812 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
3813 DAG.getConstant(1, MVT::i32));
3814 return DAG.getNode(ISD::BITCAST, dl, DstVT,
3815 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
3818 // Turn f64->i64 into VMOVRRD.
3819 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
3820 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
3821 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
3822 // Merge the pieces into a single i64 value.
3823 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
3829 /// getZeroVector - Returns a vector of specified type with all zero elements.
3830 /// Zero vectors are used to represent vector negation and in those cases
3831 /// will be implemented with the NEON VNEG instruction. However, VNEG does
3832 /// not support i64 elements, so sometimes the zero vectors will need to be
3833 /// explicitly constructed. Regardless, use a canonical VMOV to create the
3835 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, SDLoc dl) {
3836 assert(VT.isVector() && "Expected a vector type");
3837 // The canonical modified immediate encoding of a zero vector is....0!
3838 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32);
3839 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
3840 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
3841 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3844 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
3845 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
3846 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
3847 SelectionDAG &DAG) const {
3848 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3849 EVT VT = Op.getValueType();
3850 unsigned VTBits = VT.getSizeInBits();
3852 SDValue ShOpLo = Op.getOperand(0);
3853 SDValue ShOpHi = Op.getOperand(1);
3854 SDValue ShAmt = Op.getOperand(2);
3856 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
3858 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
3860 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
3861 DAG.getConstant(VTBits, MVT::i32), ShAmt);
3862 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
3863 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
3864 DAG.getConstant(VTBits, MVT::i32));
3865 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
3866 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3867 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
3869 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3870 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
3872 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
3873 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
3876 SDValue Ops[2] = { Lo, Hi };
3877 return DAG.getMergeValues(Ops, 2, dl);
3880 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
3881 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
3882 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
3883 SelectionDAG &DAG) const {
3884 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3885 EVT VT = Op.getValueType();
3886 unsigned VTBits = VT.getSizeInBits();
3888 SDValue ShOpLo = Op.getOperand(0);
3889 SDValue ShOpHi = Op.getOperand(1);
3890 SDValue ShAmt = Op.getOperand(2);
3893 assert(Op.getOpcode() == ISD::SHL_PARTS);
3894 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
3895 DAG.getConstant(VTBits, MVT::i32), ShAmt);
3896 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
3897 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
3898 DAG.getConstant(VTBits, MVT::i32));
3899 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
3900 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
3902 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3903 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3904 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
3906 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
3907 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
3910 SDValue Ops[2] = { Lo, Hi };
3911 return DAG.getMergeValues(Ops, 2, dl);
3914 SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
3915 SelectionDAG &DAG) const {
3916 // The rounding mode is in bits 23:22 of the FPSCR.
3917 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
3918 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
3919 // so that the shift + and get folded into a bitfield extract.
3921 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
3922 DAG.getConstant(Intrinsic::arm_get_fpscr,
3924 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
3925 DAG.getConstant(1U << 22, MVT::i32));
3926 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
3927 DAG.getConstant(22, MVT::i32));
3928 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
3929 DAG.getConstant(3, MVT::i32));
3932 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
3933 const ARMSubtarget *ST) {
3934 EVT VT = N->getValueType(0);
3937 if (!ST->hasV6T2Ops())
3940 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
3941 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
3944 /// getCTPOP16BitCounts - Returns a v8i8/v16i8 vector containing the bit-count
3945 /// for each 16-bit element from operand, repeated. The basic idea is to
3946 /// leverage vcnt to get the 8-bit counts, gather and add the results.
3948 /// Trace for v4i16:
3949 /// input = [v0 v1 v2 v3 ] (vi 16-bit element)
3950 /// cast: N0 = [w0 w1 w2 w3 w4 w5 w6 w7] (v0 = [w0 w1], wi 8-bit element)
3951 /// vcnt: N1 = [b0 b1 b2 b3 b4 b5 b6 b7] (bi = bit-count of 8-bit element wi)
3952 /// vrev: N2 = [b1 b0 b3 b2 b5 b4 b7 b6]
3953 /// [b0 b1 b2 b3 b4 b5 b6 b7]
3954 /// +[b1 b0 b3 b2 b5 b4 b7 b6]
3955 /// N3=N1+N2 = [k0 k0 k1 k1 k2 k2 k3 k3] (k0 = b0+b1 = bit-count of 16-bit v0,
3956 /// vuzp: = [k0 k1 k2 k3 k0 k1 k2 k3] each ki is 8-bits)
3957 static SDValue getCTPOP16BitCounts(SDNode *N, SelectionDAG &DAG) {
3958 EVT VT = N->getValueType(0);
3961 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8;
3962 SDValue N0 = DAG.getNode(ISD::BITCAST, DL, VT8Bit, N->getOperand(0));
3963 SDValue N1 = DAG.getNode(ISD::CTPOP, DL, VT8Bit, N0);
3964 SDValue N2 = DAG.getNode(ARMISD::VREV16, DL, VT8Bit, N1);
3965 SDValue N3 = DAG.getNode(ISD::ADD, DL, VT8Bit, N1, N2);
3966 return DAG.getNode(ARMISD::VUZP, DL, VT8Bit, N3, N3);
3969 /// lowerCTPOP16BitElements - Returns a v4i16/v8i16 vector containing the
3970 /// bit-count for each 16-bit element from the operand. We need slightly
3971 /// different sequencing for v4i16 and v8i16 to stay within NEON's available
3972 /// 64/128-bit registers.
3974 /// Trace for v4i16:
3975 /// input = [v0 v1 v2 v3 ] (vi 16-bit element)
3976 /// v8i8: BitCounts = [k0 k1 k2 k3 k0 k1 k2 k3 ] (ki is the bit-count of vi)
3977 /// v8i16:Extended = [k0 k1 k2 k3 k0 k1 k2 k3 ]
3978 /// v4i16:Extracted = [k0 k1 k2 k3 ]
3979 static SDValue lowerCTPOP16BitElements(SDNode *N, SelectionDAG &DAG) {
3980 EVT VT = N->getValueType(0);
3983 SDValue BitCounts = getCTPOP16BitCounts(N, DAG);
3984 if (VT.is64BitVector()) {
3985 SDValue Extended = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v8i16, BitCounts);
3986 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, Extended,
3987 DAG.getIntPtrConstant(0));
3989 SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v8i8,
3990 BitCounts, DAG.getIntPtrConstant(0));
3991 return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v8i16, Extracted);
3995 /// lowerCTPOP32BitElements - Returns a v2i32/v4i32 vector containing the
3996 /// bit-count for each 32-bit element from the operand. The idea here is
3997 /// to split the vector into 16-bit elements, leverage the 16-bit count
3998 /// routine, and then combine the results.
4000 /// Trace for v2i32 (v4i32 similar with Extracted/Extended exchanged):
4001 /// input = [v0 v1 ] (vi: 32-bit elements)
4002 /// Bitcast = [w0 w1 w2 w3 ] (wi: 16-bit elements, v0 = [w0 w1])
4003 /// Counts16 = [k0 k1 k2 k3 ] (ki: 16-bit elements, bit-count of wi)
4004 /// vrev: N0 = [k1 k0 k3 k2 ]
4006 /// N1 =+[k1 k0 k3 k2 ]
4008 /// N2 =+[k1 k3 k0 k2 ]
4010 /// Extended =+[k1 k3 k0 k2 ]
4012 /// Extracted=+[k1 k3 ]
4014 static SDValue lowerCTPOP32BitElements(SDNode *N, SelectionDAG &DAG) {
4015 EVT VT = N->getValueType(0);
4018 EVT VT16Bit = VT.is64BitVector() ? MVT::v4i16 : MVT::v8i16;
4020 SDValue Bitcast = DAG.getNode(ISD::BITCAST, DL, VT16Bit, N->getOperand(0));
4021 SDValue Counts16 = lowerCTPOP16BitElements(Bitcast.getNode(), DAG);
4022 SDValue N0 = DAG.getNode(ARMISD::VREV32, DL, VT16Bit, Counts16);
4023 SDValue N1 = DAG.getNode(ISD::ADD, DL, VT16Bit, Counts16, N0);
4024 SDValue N2 = DAG.getNode(ARMISD::VUZP, DL, VT16Bit, N1, N1);
4026 if (VT.is64BitVector()) {
4027 SDValue Extended = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v4i32, N2);
4028 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i32, Extended,
4029 DAG.getIntPtrConstant(0));
4031 SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, N2,
4032 DAG.getIntPtrConstant(0));
4033 return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v4i32, Extracted);
4037 static SDValue LowerCTPOP(SDNode *N, SelectionDAG &DAG,
4038 const ARMSubtarget *ST) {
4039 EVT VT = N->getValueType(0);
4041 assert(ST->hasNEON() && "Custom ctpop lowering requires NEON.");
4042 assert((VT == MVT::v2i32 || VT == MVT::v4i32 ||
4043 VT == MVT::v4i16 || VT == MVT::v8i16) &&
4044 "Unexpected type for custom ctpop lowering");
4046 if (VT.getVectorElementType() == MVT::i32)
4047 return lowerCTPOP32BitElements(N, DAG);
4049 return lowerCTPOP16BitElements(N, DAG);
4052 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
4053 const ARMSubtarget *ST) {
4054 EVT VT = N->getValueType(0);
4060 // Lower vector shifts on NEON to use VSHL.
4061 assert(ST->hasNEON() && "unexpected vector shift");
4063 // Left shifts translate directly to the vshiftu intrinsic.
4064 if (N->getOpcode() == ISD::SHL)
4065 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
4066 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
4067 N->getOperand(0), N->getOperand(1));
4069 assert((N->getOpcode() == ISD::SRA ||
4070 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
4072 // NEON uses the same intrinsics for both left and right shifts. For
4073 // right shifts, the shift amounts are negative, so negate the vector of
4075 EVT ShiftVT = N->getOperand(1).getValueType();
4076 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
4077 getZeroVector(ShiftVT, DAG, dl),
4079 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
4080 Intrinsic::arm_neon_vshifts :
4081 Intrinsic::arm_neon_vshiftu);
4082 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
4083 DAG.getConstant(vshiftInt, MVT::i32),
4084 N->getOperand(0), NegatedCount);
4087 static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
4088 const ARMSubtarget *ST) {
4089 EVT VT = N->getValueType(0);
4092 // We can get here for a node like i32 = ISD::SHL i32, i64
4096 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
4097 "Unknown shift to lower!");
4099 // We only lower SRA, SRL of 1 here, all others use generic lowering.
4100 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
4101 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
4104 // If we are in thumb mode, we don't have RRX.
4105 if (ST->isThumb1Only()) return SDValue();
4107 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
4108 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
4109 DAG.getConstant(0, MVT::i32));
4110 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
4111 DAG.getConstant(1, MVT::i32));
4113 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
4114 // captures the result into a carry flag.
4115 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
4116 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), &Hi, 1);
4118 // The low part is an ARMISD::RRX operand, which shifts the carry in.
4119 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
4121 // Merge the pieces into a single i64 value.
4122 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
4125 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
4126 SDValue TmpOp0, TmpOp1;
4127 bool Invert = false;
4131 SDValue Op0 = Op.getOperand(0);
4132 SDValue Op1 = Op.getOperand(1);
4133 SDValue CC = Op.getOperand(2);
4134 EVT VT = Op.getValueType();
4135 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
4138 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
4139 switch (SetCCOpcode) {
4140 default: llvm_unreachable("Illegal FP comparison");
4142 case ISD::SETNE: Invert = true; // Fallthrough
4144 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
4146 case ISD::SETLT: Swap = true; // Fallthrough
4148 case ISD::SETGT: Opc = ARMISD::VCGT; break;
4150 case ISD::SETLE: Swap = true; // Fallthrough
4152 case ISD::SETGE: Opc = ARMISD::VCGE; break;
4153 case ISD::SETUGE: Swap = true; // Fallthrough
4154 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
4155 case ISD::SETUGT: Swap = true; // Fallthrough
4156 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
4157 case ISD::SETUEQ: Invert = true; // Fallthrough
4159 // Expand this to (OLT | OGT).
4163 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
4164 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
4166 case ISD::SETUO: Invert = true; // Fallthrough
4168 // Expand this to (OLT | OGE).
4172 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
4173 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
4177 // Integer comparisons.
4178 switch (SetCCOpcode) {
4179 default: llvm_unreachable("Illegal integer comparison");
4180 case ISD::SETNE: Invert = true;
4181 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
4182 case ISD::SETLT: Swap = true;
4183 case ISD::SETGT: Opc = ARMISD::VCGT; break;
4184 case ISD::SETLE: Swap = true;
4185 case ISD::SETGE: Opc = ARMISD::VCGE; break;
4186 case ISD::SETULT: Swap = true;
4187 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
4188 case ISD::SETULE: Swap = true;
4189 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
4192 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
4193 if (Opc == ARMISD::VCEQ) {
4196 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
4198 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
4201 // Ignore bitconvert.
4202 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST)
4203 AndOp = AndOp.getOperand(0);
4205 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
4207 Op0 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(0));
4208 Op1 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(1));
4215 std::swap(Op0, Op1);
4217 // If one of the operands is a constant vector zero, attempt to fold the
4218 // comparison to a specialized compare-against-zero form.
4220 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
4222 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) {
4223 if (Opc == ARMISD::VCGE)
4224 Opc = ARMISD::VCLEZ;
4225 else if (Opc == ARMISD::VCGT)
4226 Opc = ARMISD::VCLTZ;
4231 if (SingleOp.getNode()) {
4234 Result = DAG.getNode(ARMISD::VCEQZ, dl, VT, SingleOp); break;
4236 Result = DAG.getNode(ARMISD::VCGEZ, dl, VT, SingleOp); break;
4238 Result = DAG.getNode(ARMISD::VCLEZ, dl, VT, SingleOp); break;
4240 Result = DAG.getNode(ARMISD::VCGTZ, dl, VT, SingleOp); break;
4242 Result = DAG.getNode(ARMISD::VCLTZ, dl, VT, SingleOp); break;
4244 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
4247 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
4251 Result = DAG.getNOT(dl, Result, VT);
4256 /// isNEONModifiedImm - Check if the specified splat value corresponds to a
4257 /// valid vector constant for a NEON instruction with a "modified immediate"
4258 /// operand (e.g., VMOV). If so, return the encoded value.
4259 static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
4260 unsigned SplatBitSize, SelectionDAG &DAG,
4261 EVT &VT, bool is128Bits, NEONModImmType type) {
4262 unsigned OpCmode, Imm;
4264 // SplatBitSize is set to the smallest size that splats the vector, so a
4265 // zero vector will always have SplatBitSize == 8. However, NEON modified
4266 // immediate instructions others than VMOV do not support the 8-bit encoding
4267 // of a zero vector, and the default encoding of zero is supposed to be the
4272 switch (SplatBitSize) {
4274 if (type != VMOVModImm)
4276 // Any 1-byte value is OK. Op=0, Cmode=1110.
4277 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
4280 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
4284 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
4285 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
4286 if ((SplatBits & ~0xff) == 0) {
4287 // Value = 0x00nn: Op=x, Cmode=100x.
4292 if ((SplatBits & ~0xff00) == 0) {
4293 // Value = 0xnn00: Op=x, Cmode=101x.
4295 Imm = SplatBits >> 8;
4301 // NEON's 32-bit VMOV supports splat values where:
4302 // * only one byte is nonzero, or
4303 // * the least significant byte is 0xff and the second byte is nonzero, or
4304 // * the least significant 2 bytes are 0xff and the third is nonzero.
4305 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
4306 if ((SplatBits & ~0xff) == 0) {
4307 // Value = 0x000000nn: Op=x, Cmode=000x.
4312 if ((SplatBits & ~0xff00) == 0) {
4313 // Value = 0x0000nn00: Op=x, Cmode=001x.
4315 Imm = SplatBits >> 8;
4318 if ((SplatBits & ~0xff0000) == 0) {
4319 // Value = 0x00nn0000: Op=x, Cmode=010x.
4321 Imm = SplatBits >> 16;
4324 if ((SplatBits & ~0xff000000) == 0) {
4325 // Value = 0xnn000000: Op=x, Cmode=011x.
4327 Imm = SplatBits >> 24;
4331 // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC
4332 if (type == OtherModImm) return SDValue();
4334 if ((SplatBits & ~0xffff) == 0 &&
4335 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
4336 // Value = 0x0000nnff: Op=x, Cmode=1100.
4338 Imm = SplatBits >> 8;
4343 if ((SplatBits & ~0xffffff) == 0 &&
4344 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
4345 // Value = 0x00nnffff: Op=x, Cmode=1101.
4347 Imm = SplatBits >> 16;
4348 SplatBits |= 0xffff;
4352 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
4353 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
4354 // VMOV.I32. A (very) minor optimization would be to replicate the value
4355 // and fall through here to test for a valid 64-bit splat. But, then the
4356 // caller would also need to check and handle the change in size.
4360 if (type != VMOVModImm)
4362 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
4363 uint64_t BitMask = 0xff;
4365 unsigned ImmMask = 1;
4367 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
4368 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
4371 } else if ((SplatBits & BitMask) != 0) {
4377 // Op=1, Cmode=1110.
4380 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
4385 llvm_unreachable("unexpected size for isNEONModifiedImm");
4388 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
4389 return DAG.getTargetConstant(EncodedVal, MVT::i32);
4392 SDValue ARMTargetLowering::LowerConstantFP(SDValue Op, SelectionDAG &DAG,
4393 const ARMSubtarget *ST) const {
4397 bool IsDouble = Op.getValueType() == MVT::f64;
4398 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Op);
4400 // Try splatting with a VMOV.f32...
4401 APFloat FPVal = CFP->getValueAPF();
4402 int ImmVal = IsDouble ? ARM_AM::getFP64Imm(FPVal) : ARM_AM::getFP32Imm(FPVal);
4405 if (IsDouble || !ST->useNEONForSinglePrecisionFP()) {
4406 // We have code in place to select a valid ConstantFP already, no need to
4411 // It's a float and we are trying to use NEON operations where
4412 // possible. Lower it to a splat followed by an extract.
4414 SDValue NewVal = DAG.getTargetConstant(ImmVal, MVT::i32);
4415 SDValue VecConstant = DAG.getNode(ARMISD::VMOVFPIMM, DL, MVT::v2f32,
4417 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecConstant,
4418 DAG.getConstant(0, MVT::i32));
4421 // The rest of our options are NEON only, make sure that's allowed before
4423 if (!ST->hasNEON() || (!IsDouble && !ST->useNEONForSinglePrecisionFP()))
4427 uint64_t iVal = FPVal.bitcastToAPInt().getZExtValue();
4429 // It wouldn't really be worth bothering for doubles except for one very
4430 // important value, which does happen to match: 0.0. So make sure we don't do
4432 if (IsDouble && (iVal & 0xffffffff) != (iVal >> 32))
4435 // Try a VMOV.i32 (FIXME: i8, i16, or i64 could work too).
4436 SDValue NewVal = isNEONModifiedImm(iVal & 0xffffffffU, 0, 32, DAG, VMovVT,
4438 if (NewVal != SDValue()) {
4440 SDValue VecConstant = DAG.getNode(ARMISD::VMOVIMM, DL, VMovVT,
4443 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant);
4445 // It's a float: cast and extract a vector element.
4446 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32,
4448 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant,
4449 DAG.getConstant(0, MVT::i32));
4452 // Finally, try a VMVN.i32
4453 NewVal = isNEONModifiedImm(~iVal & 0xffffffffU, 0, 32, DAG, VMovVT,
4455 if (NewVal != SDValue()) {
4457 SDValue VecConstant = DAG.getNode(ARMISD::VMVNIMM, DL, VMovVT, NewVal);
4460 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant);
4462 // It's a float: cast and extract a vector element.
4463 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32,
4465 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant,
4466 DAG.getConstant(0, MVT::i32));
4472 // check if an VEXT instruction can handle the shuffle mask when the
4473 // vector sources of the shuffle are the same.
4474 static bool isSingletonVEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
4475 unsigned NumElts = VT.getVectorNumElements();
4477 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4483 // If this is a VEXT shuffle, the immediate value is the index of the first
4484 // element. The other shuffle indices must be the successive elements after
4486 unsigned ExpectedElt = Imm;
4487 for (unsigned i = 1; i < NumElts; ++i) {
4488 // Increment the expected index. If it wraps around, just follow it
4489 // back to index zero and keep going.
4491 if (ExpectedElt == NumElts)
4494 if (M[i] < 0) continue; // ignore UNDEF indices
4495 if (ExpectedElt != static_cast<unsigned>(M[i]))
4503 static bool isVEXTMask(ArrayRef<int> M, EVT VT,
4504 bool &ReverseVEXT, unsigned &Imm) {
4505 unsigned NumElts = VT.getVectorNumElements();
4506 ReverseVEXT = false;
4508 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4514 // If this is a VEXT shuffle, the immediate value is the index of the first
4515 // element. The other shuffle indices must be the successive elements after
4517 unsigned ExpectedElt = Imm;
4518 for (unsigned i = 1; i < NumElts; ++i) {
4519 // Increment the expected index. If it wraps around, it may still be
4520 // a VEXT but the source vectors must be swapped.
4522 if (ExpectedElt == NumElts * 2) {
4527 if (M[i] < 0) continue; // ignore UNDEF indices
4528 if (ExpectedElt != static_cast<unsigned>(M[i]))
4532 // Adjust the index value if the source operands will be swapped.
4539 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
4540 /// instruction with the specified blocksize. (The order of the elements
4541 /// within each block of the vector is reversed.)
4542 static bool isVREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
4543 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
4544 "Only possible block sizes for VREV are: 16, 32, 64");
4546 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4550 unsigned NumElts = VT.getVectorNumElements();
4551 unsigned BlockElts = M[0] + 1;
4552 // If the first shuffle index is UNDEF, be optimistic.
4554 BlockElts = BlockSize / EltSz;
4556 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
4559 for (unsigned i = 0; i < NumElts; ++i) {
4560 if (M[i] < 0) continue; // ignore UNDEF indices
4561 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
4568 static bool isVTBLMask(ArrayRef<int> M, EVT VT) {
4569 // We can handle <8 x i8> vector shuffles. If the index in the mask is out of
4570 // range, then 0 is placed into the resulting vector. So pretty much any mask
4571 // of 8 elements can work here.
4572 return VT == MVT::v8i8 && M.size() == 8;
4575 static bool isVTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4576 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4580 unsigned NumElts = VT.getVectorNumElements();
4581 WhichResult = (M[0] == 0 ? 0 : 1);
4582 for (unsigned i = 0; i < NumElts; i += 2) {
4583 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
4584 (M[i+1] >= 0 && (unsigned) M[i+1] != i + NumElts + WhichResult))
4590 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
4591 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4592 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
4593 static bool isVTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
4594 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4598 unsigned NumElts = VT.getVectorNumElements();
4599 WhichResult = (M[0] == 0 ? 0 : 1);
4600 for (unsigned i = 0; i < NumElts; i += 2) {
4601 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
4602 (M[i+1] >= 0 && (unsigned) M[i+1] != i + WhichResult))
4608 static bool isVUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4609 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4613 unsigned NumElts = VT.getVectorNumElements();
4614 WhichResult = (M[0] == 0 ? 0 : 1);
4615 for (unsigned i = 0; i != NumElts; ++i) {
4616 if (M[i] < 0) continue; // ignore UNDEF indices
4617 if ((unsigned) M[i] != 2 * i + WhichResult)
4621 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
4622 if (VT.is64BitVector() && EltSz == 32)
4628 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
4629 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4630 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
4631 static bool isVUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
4632 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4636 unsigned Half = VT.getVectorNumElements() / 2;
4637 WhichResult = (M[0] == 0 ? 0 : 1);
4638 for (unsigned j = 0; j != 2; ++j) {
4639 unsigned Idx = WhichResult;
4640 for (unsigned i = 0; i != Half; ++i) {
4641 int MIdx = M[i + j * Half];
4642 if (MIdx >= 0 && (unsigned) MIdx != Idx)
4648 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
4649 if (VT.is64BitVector() && EltSz == 32)
4655 static bool isVZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4656 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4660 unsigned NumElts = VT.getVectorNumElements();
4661 WhichResult = (M[0] == 0 ? 0 : 1);
4662 unsigned Idx = WhichResult * NumElts / 2;
4663 for (unsigned i = 0; i != NumElts; i += 2) {
4664 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
4665 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts))
4670 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
4671 if (VT.is64BitVector() && EltSz == 32)
4677 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
4678 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4679 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
4680 static bool isVZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
4681 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4685 unsigned NumElts = VT.getVectorNumElements();
4686 WhichResult = (M[0] == 0 ? 0 : 1);
4687 unsigned Idx = WhichResult * NumElts / 2;
4688 for (unsigned i = 0; i != NumElts; i += 2) {
4689 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
4690 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx))
4695 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
4696 if (VT.is64BitVector() && EltSz == 32)
4702 /// \return true if this is a reverse operation on an vector.
4703 static bool isReverseMask(ArrayRef<int> M, EVT VT) {
4704 unsigned NumElts = VT.getVectorNumElements();
4705 // Make sure the mask has the right size.
4706 if (NumElts != M.size())
4709 // Look for <15, ..., 3, -1, 1, 0>.
4710 for (unsigned i = 0; i != NumElts; ++i)
4711 if (M[i] >= 0 && M[i] != (int) (NumElts - 1 - i))
4717 // If N is an integer constant that can be moved into a register in one
4718 // instruction, return an SDValue of such a constant (will become a MOV
4719 // instruction). Otherwise return null.
4720 static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG,
4721 const ARMSubtarget *ST, SDLoc dl) {
4723 if (!isa<ConstantSDNode>(N))
4725 Val = cast<ConstantSDNode>(N)->getZExtValue();
4727 if (ST->isThumb1Only()) {
4728 if (Val <= 255 || ~Val <= 255)
4729 return DAG.getConstant(Val, MVT::i32);
4731 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1)
4732 return DAG.getConstant(Val, MVT::i32);
4737 // If this is a case we can't handle, return null and let the default
4738 // expansion code take care of it.
4739 SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
4740 const ARMSubtarget *ST) const {
4741 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
4743 EVT VT = Op.getValueType();
4745 APInt SplatBits, SplatUndef;
4746 unsigned SplatBitSize;
4748 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
4749 if (SplatBitSize <= 64) {
4750 // Check if an immediate VMOV works.
4752 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
4753 SplatUndef.getZExtValue(), SplatBitSize,
4754 DAG, VmovVT, VT.is128BitVector(),
4756 if (Val.getNode()) {
4757 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
4758 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
4761 // Try an immediate VMVN.
4762 uint64_t NegatedImm = (~SplatBits).getZExtValue();
4763 Val = isNEONModifiedImm(NegatedImm,
4764 SplatUndef.getZExtValue(), SplatBitSize,
4765 DAG, VmovVT, VT.is128BitVector(),
4767 if (Val.getNode()) {
4768 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
4769 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
4772 // Use vmov.f32 to materialize other v2f32 and v4f32 splats.
4773 if ((VT == MVT::v2f32 || VT == MVT::v4f32) && SplatBitSize == 32) {
4774 int ImmVal = ARM_AM::getFP32Imm(SplatBits);
4776 SDValue Val = DAG.getTargetConstant(ImmVal, MVT::i32);
4777 return DAG.getNode(ARMISD::VMOVFPIMM, dl, VT, Val);
4783 // Scan through the operands to see if only one value is used.
4785 // As an optimisation, even if more than one value is used it may be more
4786 // profitable to splat with one value then change some lanes.
4788 // Heuristically we decide to do this if the vector has a "dominant" value,
4789 // defined as splatted to more than half of the lanes.
4790 unsigned NumElts = VT.getVectorNumElements();
4791 bool isOnlyLowElement = true;
4792 bool usesOnlyOneValue = true;
4793 bool hasDominantValue = false;
4794 bool isConstant = true;
4796 // Map of the number of times a particular SDValue appears in the
4798 DenseMap<SDValue, unsigned> ValueCounts;
4800 for (unsigned i = 0; i < NumElts; ++i) {
4801 SDValue V = Op.getOperand(i);
4802 if (V.getOpcode() == ISD::UNDEF)
4805 isOnlyLowElement = false;
4806 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
4809 ValueCounts.insert(std::make_pair(V, 0));
4810 unsigned &Count = ValueCounts[V];
4812 // Is this value dominant? (takes up more than half of the lanes)
4813 if (++Count > (NumElts / 2)) {
4814 hasDominantValue = true;
4818 if (ValueCounts.size() != 1)
4819 usesOnlyOneValue = false;
4820 if (!Value.getNode() && ValueCounts.size() > 0)
4821 Value = ValueCounts.begin()->first;
4823 if (ValueCounts.size() == 0)
4824 return DAG.getUNDEF(VT);
4826 // Loads are better lowered with insert_vector_elt/ARMISD::BUILD_VECTOR.
4827 // Keep going if we are hitting this case.
4828 if (isOnlyLowElement && !ISD::isNormalLoad(Value.getNode()))
4829 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
4831 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4833 // Use VDUP for non-constant splats. For f32 constant splats, reduce to
4834 // i32 and try again.
4835 if (hasDominantValue && EltSize <= 32) {
4839 // If we are VDUPing a value that comes directly from a vector, that will
4840 // cause an unnecessary move to and from a GPR, where instead we could
4841 // just use VDUPLANE. We can only do this if the lane being extracted
4842 // is at a constant index, as the VDUP from lane instructions only have
4843 // constant-index forms.
4844 if (Value->getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
4845 isa<ConstantSDNode>(Value->getOperand(1))) {
4846 // We need to create a new undef vector to use for the VDUPLANE if the
4847 // size of the vector from which we get the value is different than the
4848 // size of the vector that we need to create. We will insert the element
4849 // such that the register coalescer will remove unnecessary copies.
4850 if (VT != Value->getOperand(0).getValueType()) {
4851 ConstantSDNode *constIndex;
4852 constIndex = dyn_cast<ConstantSDNode>(Value->getOperand(1));
4853 assert(constIndex && "The index is not a constant!");
4854 unsigned index = constIndex->getAPIntValue().getLimitedValue() %
4855 VT.getVectorNumElements();
4856 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT,
4857 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DAG.getUNDEF(VT),
4858 Value, DAG.getConstant(index, MVT::i32)),
4859 DAG.getConstant(index, MVT::i32));
4861 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT,
4862 Value->getOperand(0), Value->getOperand(1));
4864 N = DAG.getNode(ARMISD::VDUP, dl, VT, Value);
4866 if (!usesOnlyOneValue) {
4867 // The dominant value was splatted as 'N', but we now have to insert
4868 // all differing elements.
4869 for (unsigned I = 0; I < NumElts; ++I) {
4870 if (Op.getOperand(I) == Value)
4872 SmallVector<SDValue, 3> Ops;
4874 Ops.push_back(Op.getOperand(I));
4875 Ops.push_back(DAG.getConstant(I, MVT::i32));
4876 N = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, &Ops[0], 3);
4881 if (VT.getVectorElementType().isFloatingPoint()) {
4882 SmallVector<SDValue, 8> Ops;
4883 for (unsigned i = 0; i < NumElts; ++i)
4884 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32,
4886 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
4887 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], NumElts);
4888 Val = LowerBUILD_VECTOR(Val, DAG, ST);
4890 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
4892 if (usesOnlyOneValue) {
4893 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
4894 if (isConstant && Val.getNode())
4895 return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
4899 // If all elements are constants and the case above didn't get hit, fall back
4900 // to the default expansion, which will generate a load from the constant
4905 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
4907 SDValue shuffle = ReconstructShuffle(Op, DAG);
4908 if (shuffle != SDValue())
4912 // Vectors with 32- or 64-bit elements can be built by directly assigning
4913 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
4914 // will be legalized.
4915 if (EltSize >= 32) {
4916 // Do the expansion with floating-point types, since that is what the VFP
4917 // registers are defined to use, and since i64 is not legal.
4918 EVT EltVT = EVT::getFloatingPointVT(EltSize);
4919 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
4920 SmallVector<SDValue, 8> Ops;
4921 for (unsigned i = 0; i < NumElts; ++i)
4922 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i)));
4923 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
4924 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
4927 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
4928 // know the default expansion would otherwise fall back on something even
4929 // worse. For a vector with one or two non-undef values, that's
4930 // scalar_to_vector for the elements followed by a shuffle (provided the
4931 // shuffle is valid for the target) and materialization element by element
4932 // on the stack followed by a load for everything else.
4933 if (!isConstant && !usesOnlyOneValue) {
4934 SDValue Vec = DAG.getUNDEF(VT);
4935 for (unsigned i = 0 ; i < NumElts; ++i) {
4936 SDValue V = Op.getOperand(i);
4937 if (V.getOpcode() == ISD::UNDEF)
4939 SDValue LaneIdx = DAG.getConstant(i, MVT::i32);
4940 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
4948 // Gather data to see if the operation can be modelled as a
4949 // shuffle in combination with VEXTs.
4950 SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
4951 SelectionDAG &DAG) const {
4953 EVT VT = Op.getValueType();
4954 unsigned NumElts = VT.getVectorNumElements();
4956 SmallVector<SDValue, 2> SourceVecs;
4957 SmallVector<unsigned, 2> MinElts;
4958 SmallVector<unsigned, 2> MaxElts;
4960 for (unsigned i = 0; i < NumElts; ++i) {
4961 SDValue V = Op.getOperand(i);
4962 if (V.getOpcode() == ISD::UNDEF)
4964 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
4965 // A shuffle can only come from building a vector from various
4966 // elements of other vectors.
4968 } else if (V.getOperand(0).getValueType().getVectorElementType() !=
4969 VT.getVectorElementType()) {
4970 // This code doesn't know how to handle shuffles where the vector
4971 // element types do not match (this happens because type legalization
4972 // promotes the return type of EXTRACT_VECTOR_ELT).
4973 // FIXME: It might be appropriate to extend this code to handle
4974 // mismatched types.
4978 // Record this extraction against the appropriate vector if possible...
4979 SDValue SourceVec = V.getOperand(0);
4980 // If the element number isn't a constant, we can't effectively
4981 // analyze what's going on.
4982 if (!isa<ConstantSDNode>(V.getOperand(1)))
4984 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
4985 bool FoundSource = false;
4986 for (unsigned j = 0; j < SourceVecs.size(); ++j) {
4987 if (SourceVecs[j] == SourceVec) {
4988 if (MinElts[j] > EltNo)
4990 if (MaxElts[j] < EltNo)
4997 // Or record a new source if not...
4999 SourceVecs.push_back(SourceVec);
5000 MinElts.push_back(EltNo);
5001 MaxElts.push_back(EltNo);
5005 // Currently only do something sane when at most two source vectors
5007 if (SourceVecs.size() > 2)
5010 SDValue ShuffleSrcs[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT) };
5011 int VEXTOffsets[2] = {0, 0};
5013 // This loop extracts the usage patterns of the source vectors
5014 // and prepares appropriate SDValues for a shuffle if possible.
5015 for (unsigned i = 0; i < SourceVecs.size(); ++i) {
5016 if (SourceVecs[i].getValueType() == VT) {
5017 // No VEXT necessary
5018 ShuffleSrcs[i] = SourceVecs[i];
5021 } else if (SourceVecs[i].getValueType().getVectorNumElements() < NumElts) {
5022 // It probably isn't worth padding out a smaller vector just to
5023 // break it down again in a shuffle.
5027 // Since only 64-bit and 128-bit vectors are legal on ARM and
5028 // we've eliminated the other cases...
5029 assert(SourceVecs[i].getValueType().getVectorNumElements() == 2*NumElts &&
5030 "unexpected vector sizes in ReconstructShuffle");
5032 if (MaxElts[i] - MinElts[i] >= NumElts) {
5033 // Span too large for a VEXT to cope
5037 if (MinElts[i] >= NumElts) {
5038 // The extraction can just take the second half
5039 VEXTOffsets[i] = NumElts;
5040 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
5042 DAG.getIntPtrConstant(NumElts));
5043 } else if (MaxElts[i] < NumElts) {
5044 // The extraction can just take the first half
5046 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
5048 DAG.getIntPtrConstant(0));
5050 // An actual VEXT is needed
5051 VEXTOffsets[i] = MinElts[i];
5052 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
5054 DAG.getIntPtrConstant(0));
5055 SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
5057 DAG.getIntPtrConstant(NumElts));
5058 ShuffleSrcs[i] = DAG.getNode(ARMISD::VEXT, dl, VT, VEXTSrc1, VEXTSrc2,
5059 DAG.getConstant(VEXTOffsets[i], MVT::i32));
5063 SmallVector<int, 8> Mask;
5065 for (unsigned i = 0; i < NumElts; ++i) {
5066 SDValue Entry = Op.getOperand(i);
5067 if (Entry.getOpcode() == ISD::UNDEF) {
5072 SDValue ExtractVec = Entry.getOperand(0);
5073 int ExtractElt = cast<ConstantSDNode>(Op.getOperand(i)
5074 .getOperand(1))->getSExtValue();
5075 if (ExtractVec == SourceVecs[0]) {
5076 Mask.push_back(ExtractElt - VEXTOffsets[0]);
5078 Mask.push_back(ExtractElt + NumElts - VEXTOffsets[1]);
5082 // Final check before we try to produce nonsense...
5083 if (isShuffleMaskLegal(Mask, VT))
5084 return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1],
5090 /// isShuffleMaskLegal - Targets can use this to indicate that they only
5091 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
5092 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
5093 /// are assumed to be legal.
5095 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
5097 if (VT.getVectorNumElements() == 4 &&
5098 (VT.is128BitVector() || VT.is64BitVector())) {
5099 unsigned PFIndexes[4];
5100 for (unsigned i = 0; i != 4; ++i) {
5104 PFIndexes[i] = M[i];
5107 // Compute the index in the perfect shuffle table.
5108 unsigned PFTableIndex =
5109 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5110 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5111 unsigned Cost = (PFEntry >> 30);
5118 unsigned Imm, WhichResult;
5120 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5121 return (EltSize >= 32 ||
5122 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
5123 isVREVMask(M, VT, 64) ||
5124 isVREVMask(M, VT, 32) ||
5125 isVREVMask(M, VT, 16) ||
5126 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
5127 isVTBLMask(M, VT) ||
5128 isVTRNMask(M, VT, WhichResult) ||
5129 isVUZPMask(M, VT, WhichResult) ||
5130 isVZIPMask(M, VT, WhichResult) ||
5131 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
5132 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
5133 isVZIP_v_undef_Mask(M, VT, WhichResult) ||
5134 ((VT == MVT::v8i16 || VT == MVT::v16i8) && isReverseMask(M, VT)));
5137 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5138 /// the specified operations to build the shuffle.
5139 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5140 SDValue RHS, SelectionDAG &DAG,
5142 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5143 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5144 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5147 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5156 OP_VUZPL, // VUZP, left result
5157 OP_VUZPR, // VUZP, right result
5158 OP_VZIPL, // VZIP, left result
5159 OP_VZIPR, // VZIP, right result
5160 OP_VTRNL, // VTRN, left result
5161 OP_VTRNR // VTRN, right result
5164 if (OpNum == OP_COPY) {
5165 if (LHSID == (1*9+2)*9+3) return LHS;
5166 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5170 SDValue OpLHS, OpRHS;
5171 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5172 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5173 EVT VT = OpLHS.getValueType();
5176 default: llvm_unreachable("Unknown shuffle opcode!");
5178 // VREV divides the vector in half and swaps within the half.
5179 if (VT.getVectorElementType() == MVT::i32 ||
5180 VT.getVectorElementType() == MVT::f32)
5181 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
5182 // vrev <4 x i16> -> VREV32
5183 if (VT.getVectorElementType() == MVT::i16)
5184 return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS);
5185 // vrev <4 x i8> -> VREV16
5186 assert(VT.getVectorElementType() == MVT::i8);
5187 return DAG.getNode(ARMISD::VREV16, dl, VT, OpLHS);
5192 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
5193 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
5197 return DAG.getNode(ARMISD::VEXT, dl, VT,
5199 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
5202 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
5203 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
5206 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
5207 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
5210 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
5211 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
5215 static SDValue LowerVECTOR_SHUFFLEv8i8(SDValue Op,
5216 ArrayRef<int> ShuffleMask,
5217 SelectionDAG &DAG) {
5218 // Check to see if we can use the VTBL instruction.
5219 SDValue V1 = Op.getOperand(0);
5220 SDValue V2 = Op.getOperand(1);
5223 SmallVector<SDValue, 8> VTBLMask;
5224 for (ArrayRef<int>::iterator
5225 I = ShuffleMask.begin(), E = ShuffleMask.end(); I != E; ++I)
5226 VTBLMask.push_back(DAG.getConstant(*I, MVT::i32));
5228 if (V2.getNode()->getOpcode() == ISD::UNDEF)
5229 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1,
5230 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
5233 return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2,
5234 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
5238 static SDValue LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(SDValue Op,
5239 SelectionDAG &DAG) {
5241 SDValue OpLHS = Op.getOperand(0);
5242 EVT VT = OpLHS.getValueType();
5244 assert((VT == MVT::v8i16 || VT == MVT::v16i8) &&
5245 "Expect an v8i16/v16i8 type");
5246 OpLHS = DAG.getNode(ARMISD::VREV64, DL, VT, OpLHS);
5247 // For a v16i8 type: After the VREV, we have got <8, ...15, 8, ..., 0>. Now,
5248 // extract the first 8 bytes into the top double word and the last 8 bytes
5249 // into the bottom double word. The v8i16 case is similar.
5250 unsigned ExtractNum = (VT == MVT::v16i8) ? 8 : 4;
5251 return DAG.getNode(ARMISD::VEXT, DL, VT, OpLHS, OpLHS,
5252 DAG.getConstant(ExtractNum, MVT::i32));
5255 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
5256 SDValue V1 = Op.getOperand(0);
5257 SDValue V2 = Op.getOperand(1);
5259 EVT VT = Op.getValueType();
5260 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
5262 // Convert shuffles that are directly supported on NEON to target-specific
5263 // DAG nodes, instead of keeping them as shuffles and matching them again
5264 // during code selection. This is more efficient and avoids the possibility
5265 // of inconsistencies between legalization and selection.
5266 // FIXME: floating-point vectors should be canonicalized to integer vectors
5267 // of the same time so that they get CSEd properly.
5268 ArrayRef<int> ShuffleMask = SVN->getMask();
5270 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5271 if (EltSize <= 32) {
5272 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
5273 int Lane = SVN->getSplatIndex();
5274 // If this is undef splat, generate it via "just" vdup, if possible.
5275 if (Lane == -1) Lane = 0;
5277 // Test if V1 is a SCALAR_TO_VECTOR.
5278 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5279 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
5281 // Test if V1 is a BUILD_VECTOR which is equivalent to a SCALAR_TO_VECTOR
5282 // (and probably will turn into a SCALAR_TO_VECTOR once legalization
5284 if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
5285 !isa<ConstantSDNode>(V1.getOperand(0))) {
5286 bool IsScalarToVector = true;
5287 for (unsigned i = 1, e = V1.getNumOperands(); i != e; ++i)
5288 if (V1.getOperand(i).getOpcode() != ISD::UNDEF) {
5289 IsScalarToVector = false;
5292 if (IsScalarToVector)
5293 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
5295 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
5296 DAG.getConstant(Lane, MVT::i32));
5301 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
5304 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
5305 DAG.getConstant(Imm, MVT::i32));
5308 if (isVREVMask(ShuffleMask, VT, 64))
5309 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
5310 if (isVREVMask(ShuffleMask, VT, 32))
5311 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
5312 if (isVREVMask(ShuffleMask, VT, 16))
5313 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
5315 if (V2->getOpcode() == ISD::UNDEF &&
5316 isSingletonVEXTMask(ShuffleMask, VT, Imm)) {
5317 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V1,
5318 DAG.getConstant(Imm, MVT::i32));
5321 // Check for Neon shuffles that modify both input vectors in place.
5322 // If both results are used, i.e., if there are two shuffles with the same
5323 // source operands and with masks corresponding to both results of one of
5324 // these operations, DAG memoization will ensure that a single node is
5325 // used for both shuffles.
5326 unsigned WhichResult;
5327 if (isVTRNMask(ShuffleMask, VT, WhichResult))
5328 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
5329 V1, V2).getValue(WhichResult);
5330 if (isVUZPMask(ShuffleMask, VT, WhichResult))
5331 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
5332 V1, V2).getValue(WhichResult);
5333 if (isVZIPMask(ShuffleMask, VT, WhichResult))
5334 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
5335 V1, V2).getValue(WhichResult);
5337 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
5338 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
5339 V1, V1).getValue(WhichResult);
5340 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
5341 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
5342 V1, V1).getValue(WhichResult);
5343 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
5344 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
5345 V1, V1).getValue(WhichResult);
5348 // If the shuffle is not directly supported and it has 4 elements, use
5349 // the PerfectShuffle-generated table to synthesize it from other shuffles.
5350 unsigned NumElts = VT.getVectorNumElements();
5352 unsigned PFIndexes[4];
5353 for (unsigned i = 0; i != 4; ++i) {
5354 if (ShuffleMask[i] < 0)
5357 PFIndexes[i] = ShuffleMask[i];
5360 // Compute the index in the perfect shuffle table.
5361 unsigned PFTableIndex =
5362 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5363 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5364 unsigned Cost = (PFEntry >> 30);
5367 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5370 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
5371 if (EltSize >= 32) {
5372 // Do the expansion with floating-point types, since that is what the VFP
5373 // registers are defined to use, and since i64 is not legal.
5374 EVT EltVT = EVT::getFloatingPointVT(EltSize);
5375 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
5376 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1);
5377 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2);
5378 SmallVector<SDValue, 8> Ops;
5379 for (unsigned i = 0; i < NumElts; ++i) {
5380 if (ShuffleMask[i] < 0)
5381 Ops.push_back(DAG.getUNDEF(EltVT));
5383 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
5384 ShuffleMask[i] < (int)NumElts ? V1 : V2,
5385 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
5388 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
5389 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5392 if ((VT == MVT::v8i16 || VT == MVT::v16i8) && isReverseMask(ShuffleMask, VT))
5393 return LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(Op, DAG);
5395 if (VT == MVT::v8i8) {
5396 SDValue NewOp = LowerVECTOR_SHUFFLEv8i8(Op, ShuffleMask, DAG);
5397 if (NewOp.getNode())
5404 static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
5405 // INSERT_VECTOR_ELT is legal only for immediate indexes.
5406 SDValue Lane = Op.getOperand(2);
5407 if (!isa<ConstantSDNode>(Lane))
5413 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
5414 // EXTRACT_VECTOR_ELT is legal only for immediate indexes.
5415 SDValue Lane = Op.getOperand(1);
5416 if (!isa<ConstantSDNode>(Lane))
5419 SDValue Vec = Op.getOperand(0);
5420 if (Op.getValueType() == MVT::i32 &&
5421 Vec.getValueType().getVectorElementType().getSizeInBits() < 32) {
5423 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
5429 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5430 // The only time a CONCAT_VECTORS operation can have legal types is when
5431 // two 64-bit vectors are concatenated to a 128-bit vector.
5432 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
5433 "unexpected CONCAT_VECTORS");
5435 SDValue Val = DAG.getUNDEF(MVT::v2f64);
5436 SDValue Op0 = Op.getOperand(0);
5437 SDValue Op1 = Op.getOperand(1);
5438 if (Op0.getOpcode() != ISD::UNDEF)
5439 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
5440 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0),
5441 DAG.getIntPtrConstant(0));
5442 if (Op1.getOpcode() != ISD::UNDEF)
5443 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
5444 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1),
5445 DAG.getIntPtrConstant(1));
5446 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val);
5449 /// isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each
5450 /// element has been zero/sign-extended, depending on the isSigned parameter,
5451 /// from an integer type half its size.
5452 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
5454 // A v2i64 BUILD_VECTOR will have been legalized to a BITCAST from v4i32.
5455 EVT VT = N->getValueType(0);
5456 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) {
5457 SDNode *BVN = N->getOperand(0).getNode();
5458 if (BVN->getValueType(0) != MVT::v4i32 ||
5459 BVN->getOpcode() != ISD::BUILD_VECTOR)
5461 unsigned LoElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
5462 unsigned HiElt = 1 - LoElt;
5463 ConstantSDNode *Lo0 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt));
5464 ConstantSDNode *Hi0 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt));
5465 ConstantSDNode *Lo1 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt+2));
5466 ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2));
5467 if (!Lo0 || !Hi0 || !Lo1 || !Hi1)
5470 if (Hi0->getSExtValue() == Lo0->getSExtValue() >> 32 &&
5471 Hi1->getSExtValue() == Lo1->getSExtValue() >> 32)
5474 if (Hi0->isNullValue() && Hi1->isNullValue())
5480 if (N->getOpcode() != ISD::BUILD_VECTOR)
5483 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
5484 SDNode *Elt = N->getOperand(i).getNode();
5485 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
5486 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5487 unsigned HalfSize = EltSize / 2;
5489 if (!isIntN(HalfSize, C->getSExtValue()))
5492 if (!isUIntN(HalfSize, C->getZExtValue()))
5503 /// isSignExtended - Check if a node is a vector value that is sign-extended
5504 /// or a constant BUILD_VECTOR with sign-extended elements.
5505 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
5506 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N))
5508 if (isExtendedBUILD_VECTOR(N, DAG, true))
5513 /// isZeroExtended - Check if a node is a vector value that is zero-extended
5514 /// or a constant BUILD_VECTOR with zero-extended elements.
5515 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
5516 if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N))
5518 if (isExtendedBUILD_VECTOR(N, DAG, false))
5523 static EVT getExtensionTo64Bits(const EVT &OrigVT) {
5524 if (OrigVT.getSizeInBits() >= 64)
5527 assert(OrigVT.isSimple() && "Expecting a simple value type");
5529 MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy;
5530 switch (OrigSimpleTy) {
5531 default: llvm_unreachable("Unexpected Vector Type");
5540 /// AddRequiredExtensionForVMULL - Add a sign/zero extension to extend the total
5541 /// value size to 64 bits. We need a 64-bit D register as an operand to VMULL.
5542 /// We insert the required extension here to get the vector to fill a D register.
5543 static SDValue AddRequiredExtensionForVMULL(SDValue N, SelectionDAG &DAG,
5546 unsigned ExtOpcode) {
5547 // The vector originally had a size of OrigTy. It was then extended to ExtTy.
5548 // We expect the ExtTy to be 128-bits total. If the OrigTy is less than
5549 // 64-bits we need to insert a new extension so that it will be 64-bits.
5550 assert(ExtTy.is128BitVector() && "Unexpected extension size");
5551 if (OrigTy.getSizeInBits() >= 64)
5554 // Must extend size to at least 64 bits to be used as an operand for VMULL.
5555 EVT NewVT = getExtensionTo64Bits(OrigTy);
5557 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N);
5560 /// SkipLoadExtensionForVMULL - return a load of the original vector size that
5561 /// does not do any sign/zero extension. If the original vector is less
5562 /// than 64 bits, an appropriate extension will be added after the load to
5563 /// reach a total size of 64 bits. We have to add the extension separately
5564 /// because ARM does not have a sign/zero extending load for vectors.
5565 static SDValue SkipLoadExtensionForVMULL(LoadSDNode *LD, SelectionDAG& DAG) {
5566 EVT ExtendedTy = getExtensionTo64Bits(LD->getMemoryVT());
5568 // The load already has the right type.
5569 if (ExtendedTy == LD->getMemoryVT())
5570 return DAG.getLoad(LD->getMemoryVT(), SDLoc(LD), LD->getChain(),
5571 LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(),
5572 LD->isNonTemporal(), LD->isInvariant(),
5573 LD->getAlignment());
5575 // We need to create a zextload/sextload. We cannot just create a load
5576 // followed by a zext/zext node because LowerMUL is also run during normal
5577 // operation legalization where we can't create illegal types.
5578 return DAG.getExtLoad(LD->getExtensionType(), SDLoc(LD), ExtendedTy,
5579 LD->getChain(), LD->getBasePtr(), LD->getPointerInfo(),
5580 LD->getMemoryVT(), LD->isVolatile(),
5581 LD->isNonTemporal(), LD->getAlignment());
5584 /// SkipExtensionForVMULL - For a node that is a SIGN_EXTEND, ZERO_EXTEND,
5585 /// extending load, or BUILD_VECTOR with extended elements, return the
5586 /// unextended value. The unextended vector should be 64 bits so that it can
5587 /// be used as an operand to a VMULL instruction. If the original vector size
5588 /// before extension is less than 64 bits we add a an extension to resize
5589 /// the vector to 64 bits.
5590 static SDValue SkipExtensionForVMULL(SDNode *N, SelectionDAG &DAG) {
5591 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
5592 return AddRequiredExtensionForVMULL(N->getOperand(0), DAG,
5593 N->getOperand(0)->getValueType(0),
5597 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
5598 return SkipLoadExtensionForVMULL(LD, DAG);
5600 // Otherwise, the value must be a BUILD_VECTOR. For v2i64, it will
5601 // have been legalized as a BITCAST from v4i32.
5602 if (N->getOpcode() == ISD::BITCAST) {
5603 SDNode *BVN = N->getOperand(0).getNode();
5604 assert(BVN->getOpcode() == ISD::BUILD_VECTOR &&
5605 BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR");
5606 unsigned LowElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
5607 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), MVT::v2i32,
5608 BVN->getOperand(LowElt), BVN->getOperand(LowElt+2));
5610 // Construct a new BUILD_VECTOR with elements truncated to half the size.
5611 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
5612 EVT VT = N->getValueType(0);
5613 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
5614 unsigned NumElts = VT.getVectorNumElements();
5615 MVT TruncVT = MVT::getIntegerVT(EltSize);
5616 SmallVector<SDValue, 8> Ops;
5617 for (unsigned i = 0; i != NumElts; ++i) {
5618 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
5619 const APInt &CInt = C->getAPIntValue();
5620 // Element types smaller than 32 bits are not legal, so use i32 elements.
5621 // The values are implicitly truncated so sext vs. zext doesn't matter.
5622 Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), MVT::i32));
5624 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N),
5625 MVT::getVectorVT(TruncVT, NumElts), Ops.data(), NumElts);
5628 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
5629 unsigned Opcode = N->getOpcode();
5630 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
5631 SDNode *N0 = N->getOperand(0).getNode();
5632 SDNode *N1 = N->getOperand(1).getNode();
5633 return N0->hasOneUse() && N1->hasOneUse() &&
5634 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
5639 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
5640 unsigned Opcode = N->getOpcode();
5641 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
5642 SDNode *N0 = N->getOperand(0).getNode();
5643 SDNode *N1 = N->getOperand(1).getNode();
5644 return N0->hasOneUse() && N1->hasOneUse() &&
5645 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
5650 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
5651 // Multiplications are only custom-lowered for 128-bit vectors so that
5652 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
5653 EVT VT = Op.getValueType();
5654 assert(VT.is128BitVector() && VT.isInteger() &&
5655 "unexpected type for custom-lowering ISD::MUL");
5656 SDNode *N0 = Op.getOperand(0).getNode();
5657 SDNode *N1 = Op.getOperand(1).getNode();
5658 unsigned NewOpc = 0;
5660 bool isN0SExt = isSignExtended(N0, DAG);
5661 bool isN1SExt = isSignExtended(N1, DAG);
5662 if (isN0SExt && isN1SExt)
5663 NewOpc = ARMISD::VMULLs;
5665 bool isN0ZExt = isZeroExtended(N0, DAG);
5666 bool isN1ZExt = isZeroExtended(N1, DAG);
5667 if (isN0ZExt && isN1ZExt)
5668 NewOpc = ARMISD::VMULLu;
5669 else if (isN1SExt || isN1ZExt) {
5670 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
5671 // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
5672 if (isN1SExt && isAddSubSExt(N0, DAG)) {
5673 NewOpc = ARMISD::VMULLs;
5675 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
5676 NewOpc = ARMISD::VMULLu;
5678 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
5680 NewOpc = ARMISD::VMULLu;
5686 if (VT == MVT::v2i64)
5687 // Fall through to expand this. It is not legal.
5690 // Other vector multiplications are legal.
5695 // Legalize to a VMULL instruction.
5698 SDValue Op1 = SkipExtensionForVMULL(N1, DAG);
5700 Op0 = SkipExtensionForVMULL(N0, DAG);
5701 assert(Op0.getValueType().is64BitVector() &&
5702 Op1.getValueType().is64BitVector() &&
5703 "unexpected types for extended operands to VMULL");
5704 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
5707 // Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during
5708 // isel lowering to take advantage of no-stall back to back vmul + vmla.
5715 SDValue N00 = SkipExtensionForVMULL(N0->getOperand(0).getNode(), DAG);
5716 SDValue N01 = SkipExtensionForVMULL(N0->getOperand(1).getNode(), DAG);
5717 EVT Op1VT = Op1.getValueType();
5718 return DAG.getNode(N0->getOpcode(), DL, VT,
5719 DAG.getNode(NewOpc, DL, VT,
5720 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
5721 DAG.getNode(NewOpc, DL, VT,
5722 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
5726 LowerSDIV_v4i8(SDValue X, SDValue Y, SDLoc dl, SelectionDAG &DAG) {
5728 // float4 xf = vcvt_f32_s32(vmovl_s16(a.lo));
5729 // float4 yf = vcvt_f32_s32(vmovl_s16(b.lo));
5730 X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X);
5731 Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y);
5732 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X);
5733 Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y);
5734 // Get reciprocal estimate.
5735 // float4 recip = vrecpeq_f32(yf);
5736 Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
5737 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), Y);
5738 // Because char has a smaller range than uchar, we can actually get away
5739 // without any newton steps. This requires that we use a weird bias
5740 // of 0xb000, however (again, this has been exhaustively tested).
5741 // float4 result = as_float4(as_int4(xf*recip) + 0xb000);
5742 X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y);
5743 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X);
5744 Y = DAG.getConstant(0xb000, MVT::i32);
5745 Y = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Y, Y, Y, Y);
5746 X = DAG.getNode(ISD::ADD, dl, MVT::v4i32, X, Y);
5747 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X);
5748 // Convert back to short.
5749 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X);
5750 X = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, X);
5755 LowerSDIV_v4i16(SDValue N0, SDValue N1, SDLoc dl, SelectionDAG &DAG) {
5757 // Convert to float.
5758 // float4 yf = vcvt_f32_s32(vmovl_s16(y));
5759 // float4 xf = vcvt_f32_s32(vmovl_s16(x));
5760 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0);
5761 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1);
5762 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
5763 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
5765 // Use reciprocal estimate and one refinement step.
5766 // float4 recip = vrecpeq_f32(yf);
5767 // recip *= vrecpsq_f32(yf, recip);
5768 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
5769 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1);
5770 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
5771 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
5773 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
5774 // Because short has a smaller range than ushort, we can actually get away
5775 // with only a single newton step. This requires that we use a weird bias
5776 // of 89, however (again, this has been exhaustively tested).
5777 // float4 result = as_float4(as_int4(xf*recip) + 0x89);
5778 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
5779 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
5780 N1 = DAG.getConstant(0x89, MVT::i32);
5781 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
5782 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
5783 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
5784 // Convert back to integer and return.
5785 // return vmovn_s32(vcvt_s32_f32(result));
5786 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
5787 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
5791 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
5792 EVT VT = Op.getValueType();
5793 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
5794 "unexpected type for custom-lowering ISD::SDIV");
5797 SDValue N0 = Op.getOperand(0);
5798 SDValue N1 = Op.getOperand(1);
5801 if (VT == MVT::v8i8) {
5802 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0);
5803 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1);
5805 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
5806 DAG.getIntPtrConstant(4));
5807 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
5808 DAG.getIntPtrConstant(4));
5809 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
5810 DAG.getIntPtrConstant(0));
5811 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
5812 DAG.getIntPtrConstant(0));
5814 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16
5815 N2 = LowerSDIV_v4i8(N2, N3, dl, DAG); // v4i16
5817 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
5818 N0 = LowerCONCAT_VECTORS(N0, DAG);
5820 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0);
5823 return LowerSDIV_v4i16(N0, N1, dl, DAG);
5826 static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG) {
5827 EVT VT = Op.getValueType();
5828 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
5829 "unexpected type for custom-lowering ISD::UDIV");
5832 SDValue N0 = Op.getOperand(0);
5833 SDValue N1 = Op.getOperand(1);
5836 if (VT == MVT::v8i8) {
5837 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0);
5838 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1);
5840 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
5841 DAG.getIntPtrConstant(4));
5842 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
5843 DAG.getIntPtrConstant(4));
5844 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
5845 DAG.getIntPtrConstant(0));
5846 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
5847 DAG.getIntPtrConstant(0));
5849 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16
5850 N2 = LowerSDIV_v4i16(N2, N3, dl, DAG); // v4i16
5852 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
5853 N0 = LowerCONCAT_VECTORS(N0, DAG);
5855 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8,
5856 DAG.getConstant(Intrinsic::arm_neon_vqmovnsu, MVT::i32),
5861 // v4i16 sdiv ... Convert to float.
5862 // float4 yf = vcvt_f32_s32(vmovl_u16(y));
5863 // float4 xf = vcvt_f32_s32(vmovl_u16(x));
5864 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0);
5865 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1);
5866 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
5867 SDValue BN1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
5869 // Use reciprocal estimate and two refinement steps.
5870 // float4 recip = vrecpeq_f32(yf);
5871 // recip *= vrecpsq_f32(yf, recip);
5872 // recip *= vrecpsq_f32(yf, recip);
5873 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
5874 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), BN1);
5875 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
5876 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
5878 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
5879 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
5880 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
5882 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
5883 // Simply multiplying by the reciprocal estimate can leave us a few ulps
5884 // too low, so we add 2 ulps (exhaustive testing shows that this is enough,
5885 // and that it will never cause us to return an answer too large).
5886 // float4 result = as_float4(as_int4(xf*recip) + 2);
5887 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
5888 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
5889 N1 = DAG.getConstant(2, MVT::i32);
5890 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
5891 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
5892 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
5893 // Convert back to integer and return.
5894 // return vmovn_u32(vcvt_s32_f32(result));
5895 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
5896 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
5900 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
5901 EVT VT = Op.getNode()->getValueType(0);
5902 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
5905 bool ExtraOp = false;
5906 switch (Op.getOpcode()) {
5907 default: llvm_unreachable("Invalid code");
5908 case ISD::ADDC: Opc = ARMISD::ADDC; break;
5909 case ISD::ADDE: Opc = ARMISD::ADDE; ExtraOp = true; break;
5910 case ISD::SUBC: Opc = ARMISD::SUBC; break;
5911 case ISD::SUBE: Opc = ARMISD::SUBE; ExtraOp = true; break;
5915 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
5917 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
5918 Op.getOperand(1), Op.getOperand(2));
5921 SDValue ARMTargetLowering::LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const {
5922 assert(Subtarget->isTargetDarwin());
5924 // For iOS, we want to call an alternative entry point: __sincos_stret,
5925 // return values are passed via sret.
5927 SDValue Arg = Op.getOperand(0);
5928 EVT ArgVT = Arg.getValueType();
5929 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
5931 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
5932 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5934 // Pair of floats / doubles used to pass the result.
5935 StructType *RetTy = StructType::get(ArgTy, ArgTy, NULL);
5937 // Create stack object for sret.
5938 const uint64_t ByteSize = TLI.getDataLayout()->getTypeAllocSize(RetTy);
5939 const unsigned StackAlign = TLI.getDataLayout()->getPrefTypeAlignment(RetTy);
5940 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign, false);
5941 SDValue SRet = DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
5947 Entry.Ty = RetTy->getPointerTo();
5948 Entry.isSExt = false;
5949 Entry.isZExt = false;
5950 Entry.isSRet = true;
5951 Args.push_back(Entry);
5955 Entry.isSExt = false;
5956 Entry.isZExt = false;
5957 Args.push_back(Entry);
5959 const char *LibcallName = (ArgVT == MVT::f64)
5960 ? "__sincos_stret" : "__sincosf_stret";
5961 SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy());
5964 CallLoweringInfo CLI(DAG.getEntryNode(), Type::getVoidTy(*DAG.getContext()),
5965 false, false, false, false, 0,
5966 CallingConv::C, /*isTaillCall=*/false,
5967 /*doesNotRet=*/false, /*isReturnValueUsed*/false,
5968 Callee, Args, DAG, dl);
5969 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
5971 SDValue LoadSin = DAG.getLoad(ArgVT, dl, CallResult.second, SRet,
5972 MachinePointerInfo(), false, false, false, 0);
5974 // Address of cos field.
5975 SDValue Add = DAG.getNode(ISD::ADD, dl, getPointerTy(), SRet,
5976 DAG.getIntPtrConstant(ArgVT.getStoreSize()));
5977 SDValue LoadCos = DAG.getLoad(ArgVT, dl, LoadSin.getValue(1), Add,
5978 MachinePointerInfo(), false, false, false, 0);
5980 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
5981 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys,
5982 LoadSin.getValue(0), LoadCos.getValue(0));
5985 static SDValue LowerAtomicLoadStore(SDValue Op, SelectionDAG &DAG) {
5986 // Monotonic load/store is legal for all targets
5987 if (cast<AtomicSDNode>(Op)->getOrdering() <= Monotonic)
5990 // Aquire/Release load/store is not legal for targets without a
5991 // dmb or equivalent available.
5996 ReplaceATOMIC_OP_64(SDNode *Node, SmallVectorImpl<SDValue>& Results,
5997 SelectionDAG &DAG) {
5999 assert (Node->getValueType(0) == MVT::i64 &&
6000 "Only know how to expand i64 atomics");
6001 AtomicSDNode *AN = cast<AtomicSDNode>(Node);
6003 SmallVector<SDValue, 6> Ops;
6004 Ops.push_back(Node->getOperand(0)); // Chain
6005 Ops.push_back(Node->getOperand(1)); // Ptr
6006 for(unsigned i=2; i<Node->getNumOperands(); i++) {
6008 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6009 Node->getOperand(i), DAG.getIntPtrConstant(0)));
6011 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
6012 Node->getOperand(i), DAG.getIntPtrConstant(1)));
6014 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
6016 DAG.getAtomic(Node->getOpcode(), dl, MVT::i64, Tys, Ops.data(), Ops.size(),
6017 cast<MemSDNode>(Node)->getMemOperand(), AN->getOrdering(),
6018 AN->getSynchScope());
6019 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1) };
6020 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
6021 Results.push_back(Result.getValue(2));
6024 static void ReplaceREADCYCLECOUNTER(SDNode *N,
6025 SmallVectorImpl<SDValue> &Results,
6027 const ARMSubtarget *Subtarget) {
6029 SDValue Cycles32, OutChain;
6031 if (Subtarget->hasPerfMon()) {
6032 // Under Power Management extensions, the cycle-count is:
6033 // mrc p15, #0, <Rt>, c9, c13, #0
6034 SDValue Ops[] = { N->getOperand(0), // Chain
6035 DAG.getConstant(Intrinsic::arm_mrc, MVT::i32),
6036 DAG.getConstant(15, MVT::i32),
6037 DAG.getConstant(0, MVT::i32),
6038 DAG.getConstant(9, MVT::i32),
6039 DAG.getConstant(13, MVT::i32),
6040 DAG.getConstant(0, MVT::i32)
6043 Cycles32 = DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL,
6044 DAG.getVTList(MVT::i32, MVT::Other), &Ops[0],
6045 array_lengthof(Ops));
6046 OutChain = Cycles32.getValue(1);
6048 // Intrinsic is defined to return 0 on unsupported platforms. Technically
6049 // there are older ARM CPUs that have implementation-specific ways of
6050 // obtaining this information (FIXME!).
6051 Cycles32 = DAG.getConstant(0, MVT::i32);
6052 OutChain = DAG.getEntryNode();
6056 SDValue Cycles64 = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64,
6057 Cycles32, DAG.getConstant(0, MVT::i32));
6058 Results.push_back(Cycles64);
6059 Results.push_back(OutChain);
6062 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6063 switch (Op.getOpcode()) {
6064 default: llvm_unreachable("Don't know how to custom lower this!");
6065 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6066 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
6067 case ISD::GlobalAddress:
6068 return Subtarget->isTargetMachO() ? LowerGlobalAddressDarwin(Op, DAG) :
6069 LowerGlobalAddressELF(Op, DAG);
6070 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6071 case ISD::SELECT: return LowerSELECT(Op, DAG);
6072 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
6073 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
6074 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
6075 case ISD::VASTART: return LowerVASTART(Op, DAG);
6076 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG, Subtarget);
6077 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget);
6078 case ISD::SINT_TO_FP:
6079 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
6080 case ISD::FP_TO_SINT:
6081 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
6082 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
6083 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6084 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6085 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
6086 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
6087 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
6088 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
6090 case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG);
6093 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
6094 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
6095 case ISD::SRL_PARTS:
6096 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
6097 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
6098 case ISD::CTPOP: return LowerCTPOP(Op.getNode(), DAG, Subtarget);
6099 case ISD::SETCC: return LowerVSETCC(Op, DAG);
6100 case ISD::ConstantFP: return LowerConstantFP(Op, DAG, Subtarget);
6101 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
6102 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6103 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
6104 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
6105 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
6106 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6107 case ISD::MUL: return LowerMUL(Op, DAG);
6108 case ISD::SDIV: return LowerSDIV(Op, DAG);
6109 case ISD::UDIV: return LowerUDIV(Op, DAG);
6113 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
6114 case ISD::ATOMIC_LOAD:
6115 case ISD::ATOMIC_STORE: return LowerAtomicLoadStore(Op, DAG);
6116 case ISD::FSINCOS: return LowerFSINCOS(Op, DAG);
6118 case ISD::UDIVREM: return LowerDivRem(Op, DAG);
6122 /// ReplaceNodeResults - Replace the results of node with an illegal result
6123 /// type with new values built out of custom code.
6124 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
6125 SmallVectorImpl<SDValue>&Results,
6126 SelectionDAG &DAG) const {
6128 switch (N->getOpcode()) {
6130 llvm_unreachable("Don't know how to custom expand this!");
6132 Res = ExpandBITCAST(N, DAG);
6136 Res = Expand64BitShift(N, DAG, Subtarget);
6138 case ISD::READCYCLECOUNTER:
6139 ReplaceREADCYCLECOUNTER(N, Results, DAG, Subtarget);
6141 case ISD::ATOMIC_STORE:
6142 case ISD::ATOMIC_LOAD:
6143 case ISD::ATOMIC_LOAD_ADD:
6144 case ISD::ATOMIC_LOAD_AND:
6145 case ISD::ATOMIC_LOAD_NAND:
6146 case ISD::ATOMIC_LOAD_OR:
6147 case ISD::ATOMIC_LOAD_SUB:
6148 case ISD::ATOMIC_LOAD_XOR:
6149 case ISD::ATOMIC_SWAP:
6150 case ISD::ATOMIC_CMP_SWAP:
6151 case ISD::ATOMIC_LOAD_MIN:
6152 case ISD::ATOMIC_LOAD_UMIN:
6153 case ISD::ATOMIC_LOAD_MAX:
6154 case ISD::ATOMIC_LOAD_UMAX:
6155 ReplaceATOMIC_OP_64(N, Results, DAG);
6159 Results.push_back(Res);
6162 //===----------------------------------------------------------------------===//
6163 // ARM Scheduler Hooks
6164 //===----------------------------------------------------------------------===//
6167 ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
6168 MachineBasicBlock *BB,
6169 unsigned Size) const {
6170 unsigned dest = MI->getOperand(0).getReg();
6171 unsigned ptr = MI->getOperand(1).getReg();
6172 unsigned oldval = MI->getOperand(2).getReg();
6173 unsigned newval = MI->getOperand(3).getReg();
6174 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6175 AtomicOrdering Ord = static_cast<AtomicOrdering>(MI->getOperand(4).getImm());
6176 DebugLoc dl = MI->getDebugLoc();
6177 bool isThumb2 = Subtarget->isThumb2();
6179 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
6180 unsigned scratch = MRI.createVirtualRegister(isThumb2 ?
6181 (const TargetRegisterClass*)&ARM::rGPRRegClass :
6182 (const TargetRegisterClass*)&ARM::GPRRegClass);
6185 MRI.constrainRegClass(dest, &ARM::rGPRRegClass);
6186 MRI.constrainRegClass(oldval, &ARM::rGPRRegClass);
6187 MRI.constrainRegClass(newval, &ARM::rGPRRegClass);
6190 unsigned ldrOpc, strOpc;
6191 getExclusiveOperation(Size, Ord, isThumb2, ldrOpc, strOpc);
6193 MachineFunction *MF = BB->getParent();
6194 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6195 MachineFunction::iterator It = BB;
6196 ++It; // insert the new blocks after the current block
6198 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
6199 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
6200 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
6201 MF->insert(It, loop1MBB);
6202 MF->insert(It, loop2MBB);
6203 MF->insert(It, exitMBB);
6205 // Transfer the remainder of BB and its successor edges to exitMBB.
6206 exitMBB->splice(exitMBB->begin(), BB,
6207 llvm::next(MachineBasicBlock::iterator(MI)),
6209 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6213 // fallthrough --> loop1MBB
6214 BB->addSuccessor(loop1MBB);
6217 // ldrex dest, [ptr]
6221 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
6222 if (ldrOpc == ARM::t2LDREX)
6224 AddDefaultPred(MIB);
6225 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
6226 .addReg(dest).addReg(oldval));
6227 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
6228 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
6229 BB->addSuccessor(loop2MBB);
6230 BB->addSuccessor(exitMBB);
6233 // strex scratch, newval, [ptr]
6237 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval).addReg(ptr);
6238 if (strOpc == ARM::t2STREX)
6240 AddDefaultPred(MIB);
6241 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
6242 .addReg(scratch).addImm(0));
6243 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
6244 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
6245 BB->addSuccessor(loop1MBB);
6246 BB->addSuccessor(exitMBB);
6252 MI->eraseFromParent(); // The instruction is gone now.
6258 ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
6259 unsigned Size, unsigned BinOpcode) const {
6260 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6261 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6263 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6264 MachineFunction *MF = BB->getParent();
6265 MachineFunction::iterator It = BB;
6268 unsigned dest = MI->getOperand(0).getReg();
6269 unsigned ptr = MI->getOperand(1).getReg();
6270 unsigned incr = MI->getOperand(2).getReg();
6271 AtomicOrdering Ord = static_cast<AtomicOrdering>(MI->getOperand(3).getImm());
6272 DebugLoc dl = MI->getDebugLoc();
6273 bool isThumb2 = Subtarget->isThumb2();
6275 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
6277 MRI.constrainRegClass(dest, &ARM::rGPRRegClass);
6278 MRI.constrainRegClass(ptr, &ARM::rGPRRegClass);
6279 MRI.constrainRegClass(incr, &ARM::rGPRRegClass);
6282 unsigned ldrOpc, strOpc;
6283 getExclusiveOperation(Size, Ord, isThumb2, ldrOpc, strOpc);
6285 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
6286 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
6287 MF->insert(It, loopMBB);
6288 MF->insert(It, exitMBB);
6290 // Transfer the remainder of BB and its successor edges to exitMBB.
6291 exitMBB->splice(exitMBB->begin(), BB,
6292 llvm::next(MachineBasicBlock::iterator(MI)),
6294 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6296 const TargetRegisterClass *TRC = isThumb2 ?
6297 (const TargetRegisterClass*)&ARM::rGPRRegClass :
6298 (const TargetRegisterClass*)&ARM::GPRRegClass;
6299 unsigned scratch = MRI.createVirtualRegister(TRC);
6300 unsigned scratch2 = (!BinOpcode) ? incr : MRI.createVirtualRegister(TRC);
6304 // fallthrough --> loopMBB
6305 BB->addSuccessor(loopMBB);
6309 // <binop> scratch2, dest, incr
6310 // strex scratch, scratch2, ptr
6313 // fallthrough --> exitMBB
6315 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
6316 if (ldrOpc == ARM::t2LDREX)
6318 AddDefaultPred(MIB);
6320 // operand order needs to go the other way for NAND
6321 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr)
6322 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
6323 addReg(incr).addReg(dest)).addReg(0);
6325 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
6326 addReg(dest).addReg(incr)).addReg(0);
6329 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2).addReg(ptr);
6330 if (strOpc == ARM::t2STREX)
6332 AddDefaultPred(MIB);
6333 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
6334 .addReg(scratch).addImm(0));
6335 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
6336 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
6338 BB->addSuccessor(loopMBB);
6339 BB->addSuccessor(exitMBB);
6345 MI->eraseFromParent(); // The instruction is gone now.
6351 ARMTargetLowering::EmitAtomicBinaryMinMax(MachineInstr *MI,
6352 MachineBasicBlock *BB,
6355 ARMCC::CondCodes Cond) const {
6356 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6358 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6359 MachineFunction *MF = BB->getParent();
6360 MachineFunction::iterator It = BB;
6363 unsigned dest = MI->getOperand(0).getReg();
6364 unsigned ptr = MI->getOperand(1).getReg();
6365 unsigned incr = MI->getOperand(2).getReg();
6366 unsigned oldval = dest;
6367 AtomicOrdering Ord = static_cast<AtomicOrdering>(MI->getOperand(3).getImm());
6368 DebugLoc dl = MI->getDebugLoc();
6369 bool isThumb2 = Subtarget->isThumb2();
6371 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
6373 MRI.constrainRegClass(dest, &ARM::rGPRRegClass);
6374 MRI.constrainRegClass(ptr, &ARM::rGPRRegClass);
6375 MRI.constrainRegClass(incr, &ARM::rGPRRegClass);
6378 unsigned ldrOpc, strOpc, extendOpc;
6379 getExclusiveOperation(Size, Ord, isThumb2, ldrOpc, strOpc);
6381 default: llvm_unreachable("unsupported size for AtomicBinaryMinMax!");
6383 extendOpc = isThumb2 ? ARM::t2SXTB : ARM::SXTB;
6386 extendOpc = isThumb2 ? ARM::t2SXTH : ARM::SXTH;
6393 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
6394 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
6395 MF->insert(It, loopMBB);
6396 MF->insert(It, exitMBB);
6398 // Transfer the remainder of BB and its successor edges to exitMBB.
6399 exitMBB->splice(exitMBB->begin(), BB,
6400 llvm::next(MachineBasicBlock::iterator(MI)),
6402 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6404 const TargetRegisterClass *TRC = isThumb2 ?
6405 (const TargetRegisterClass*)&ARM::rGPRRegClass :
6406 (const TargetRegisterClass*)&ARM::GPRRegClass;
6407 unsigned scratch = MRI.createVirtualRegister(TRC);
6408 unsigned scratch2 = MRI.createVirtualRegister(TRC);
6412 // fallthrough --> loopMBB
6413 BB->addSuccessor(loopMBB);
6417 // (sign extend dest, if required)
6419 // cmov.cond scratch2, incr, dest
6420 // strex scratch, scratch2, ptr
6423 // fallthrough --> exitMBB
6425 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
6426 if (ldrOpc == ARM::t2LDREX)
6428 AddDefaultPred(MIB);
6430 // Sign extend the value, if necessary.
6431 if (signExtend && extendOpc) {
6432 oldval = MRI.createVirtualRegister(isThumb2 ? &ARM::rGPRRegClass
6433 : &ARM::GPRnopcRegClass);
6435 MRI.constrainRegClass(dest, &ARM::GPRnopcRegClass);
6436 AddDefaultPred(BuildMI(BB, dl, TII->get(extendOpc), oldval)
6441 // Build compare and cmov instructions.
6442 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
6443 .addReg(oldval).addReg(incr));
6444 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr), scratch2)
6445 .addReg(incr).addReg(oldval).addImm(Cond).addReg(ARM::CPSR);
6447 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2).addReg(ptr);
6448 if (strOpc == ARM::t2STREX)
6450 AddDefaultPred(MIB);
6451 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
6452 .addReg(scratch).addImm(0));
6453 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
6454 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
6456 BB->addSuccessor(loopMBB);
6457 BB->addSuccessor(exitMBB);
6463 MI->eraseFromParent(); // The instruction is gone now.
6469 ARMTargetLowering::EmitAtomicBinary64(MachineInstr *MI, MachineBasicBlock *BB,
6470 unsigned Op1, unsigned Op2,
6471 bool NeedsCarry, bool IsCmpxchg,
6472 bool IsMinMax, ARMCC::CondCodes CC) const {
6473 // This also handles ATOMIC_SWAP and ATOMIC_STORE, indicated by Op1==0.
6474 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6476 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6477 MachineFunction *MF = BB->getParent();
6478 MachineFunction::iterator It = BB;
6481 bool isStore = (MI->getOpcode() == ARM::ATOMIC_STORE_I64);
6482 unsigned offset = (isStore ? -2 : 0);
6483 unsigned destlo = MI->getOperand(0).getReg();
6484 unsigned desthi = MI->getOperand(1).getReg();
6485 unsigned ptr = MI->getOperand(offset+2).getReg();
6486 unsigned vallo = MI->getOperand(offset+3).getReg();
6487 unsigned valhi = MI->getOperand(offset+4).getReg();
6488 unsigned OrdIdx = offset + (IsCmpxchg ? 7 : 5);
6489 AtomicOrdering Ord = static_cast<AtomicOrdering>(MI->getOperand(OrdIdx).getImm());
6490 DebugLoc dl = MI->getDebugLoc();
6491 bool isThumb2 = Subtarget->isThumb2();
6493 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
6495 MRI.constrainRegClass(destlo, &ARM::rGPRRegClass);
6496 MRI.constrainRegClass(desthi, &ARM::rGPRRegClass);
6497 MRI.constrainRegClass(ptr, &ARM::rGPRRegClass);
6498 MRI.constrainRegClass(vallo, &ARM::rGPRRegClass);
6499 MRI.constrainRegClass(valhi, &ARM::rGPRRegClass);
6502 unsigned ldrOpc, strOpc;
6503 getExclusiveOperation(8, Ord, isThumb2, ldrOpc, strOpc);
6505 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
6506 MachineBasicBlock *contBB = 0, *cont2BB = 0;
6507 if (IsCmpxchg || IsMinMax)
6508 contBB = MF->CreateMachineBasicBlock(LLVM_BB);
6510 cont2BB = MF->CreateMachineBasicBlock(LLVM_BB);
6511 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
6513 MF->insert(It, loopMBB);
6514 if (IsCmpxchg || IsMinMax) MF->insert(It, contBB);
6515 if (IsCmpxchg) MF->insert(It, cont2BB);
6516 MF->insert(It, exitMBB);
6518 // Transfer the remainder of BB and its successor edges to exitMBB.
6519 exitMBB->splice(exitMBB->begin(), BB,
6520 llvm::next(MachineBasicBlock::iterator(MI)),
6522 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6524 const TargetRegisterClass *TRC = isThumb2 ?
6525 (const TargetRegisterClass*)&ARM::tGPRRegClass :
6526 (const TargetRegisterClass*)&ARM::GPRRegClass;
6527 unsigned storesuccess = MRI.createVirtualRegister(TRC);
6531 // fallthrough --> loopMBB
6532 BB->addSuccessor(loopMBB);
6535 // ldrexd r2, r3, ptr
6536 // <binopa> r0, r2, incr
6537 // <binopb> r1, r3, incr
6538 // strexd storesuccess, r0, r1, ptr
6539 // cmp storesuccess, #0
6541 // fallthrough --> exitMBB
6547 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc))
6548 .addReg(destlo, RegState::Define)
6549 .addReg(desthi, RegState::Define)
6552 unsigned GPRPair0 = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
6553 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc))
6554 .addReg(GPRPair0, RegState::Define).addReg(ptr));
6555 // Copy r2/r3 into dest. (This copy will normally be coalesced.)
6556 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), destlo)
6557 .addReg(GPRPair0, 0, ARM::gsub_0);
6558 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), desthi)
6559 .addReg(GPRPair0, 0, ARM::gsub_1);
6563 unsigned StoreLo, StoreHi;
6566 for (unsigned i = 0; i < 2; i++) {
6567 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr :
6569 .addReg(i == 0 ? destlo : desthi)
6570 .addReg(i == 0 ? vallo : valhi));
6571 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
6572 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
6573 BB->addSuccessor(exitMBB);
6574 BB->addSuccessor(i == 0 ? contBB : cont2BB);
6575 BB = (i == 0 ? contBB : cont2BB);
6578 // Copy to physregs for strexd
6579 StoreLo = MI->getOperand(5).getReg();
6580 StoreHi = MI->getOperand(6).getReg();
6582 // Perform binary operation
6583 unsigned tmpRegLo = MRI.createVirtualRegister(TRC);
6584 AddDefaultPred(BuildMI(BB, dl, TII->get(Op1), tmpRegLo)
6585 .addReg(destlo).addReg(vallo))
6586 .addReg(NeedsCarry ? ARM::CPSR : 0, getDefRegState(NeedsCarry));
6587 unsigned tmpRegHi = MRI.createVirtualRegister(TRC);
6588 AddDefaultPred(BuildMI(BB, dl, TII->get(Op2), tmpRegHi)
6589 .addReg(desthi).addReg(valhi))
6590 .addReg(IsMinMax ? ARM::CPSR : 0, getDefRegState(IsMinMax));
6595 // Copy to physregs for strexd
6600 // Compare and branch to exit block.
6601 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
6602 .addMBB(exitMBB).addImm(CC).addReg(ARM::CPSR);
6603 BB->addSuccessor(exitMBB);
6604 BB->addSuccessor(contBB);
6612 MRI.constrainRegClass(StoreLo, &ARM::rGPRRegClass);
6613 MRI.constrainRegClass(StoreHi, &ARM::rGPRRegClass);
6614 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), storesuccess)
6615 .addReg(StoreLo).addReg(StoreHi).addReg(ptr));
6617 // Marshal a pair...
6618 unsigned StorePair = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
6619 unsigned UndefPair = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
6620 unsigned r1 = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
6621 BuildMI(BB, dl, TII->get(TargetOpcode::IMPLICIT_DEF), UndefPair);
6622 BuildMI(BB, dl, TII->get(TargetOpcode::INSERT_SUBREG), r1)
6625 .addImm(ARM::gsub_0);
6626 BuildMI(BB, dl, TII->get(TargetOpcode::INSERT_SUBREG), StorePair)
6629 .addImm(ARM::gsub_1);
6632 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), storesuccess)
6633 .addReg(StorePair).addReg(ptr));
6636 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
6637 .addReg(storesuccess).addImm(0));
6638 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
6639 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
6641 BB->addSuccessor(loopMBB);
6642 BB->addSuccessor(exitMBB);
6648 MI->eraseFromParent(); // The instruction is gone now.
6654 ARMTargetLowering::EmitAtomicLoad64(MachineInstr *MI, MachineBasicBlock *BB) const {
6656 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6658 unsigned destlo = MI->getOperand(0).getReg();
6659 unsigned desthi = MI->getOperand(1).getReg();
6660 unsigned ptr = MI->getOperand(2).getReg();
6661 AtomicOrdering Ord = static_cast<AtomicOrdering>(MI->getOperand(3).getImm());
6662 DebugLoc dl = MI->getDebugLoc();
6663 bool isThumb2 = Subtarget->isThumb2();
6665 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
6667 MRI.constrainRegClass(destlo, &ARM::rGPRRegClass);
6668 MRI.constrainRegClass(desthi, &ARM::rGPRRegClass);
6669 MRI.constrainRegClass(ptr, &ARM::rGPRRegClass);
6671 unsigned ldrOpc, strOpc;
6672 getExclusiveOperation(8, Ord, isThumb2, ldrOpc, strOpc);
6674 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(ldrOpc));
6677 MIB.addReg(destlo, RegState::Define)
6678 .addReg(desthi, RegState::Define)
6682 unsigned GPRPair0 = MRI.createVirtualRegister(&ARM::GPRPairRegClass);
6683 MIB.addReg(GPRPair0, RegState::Define).addReg(ptr);
6685 // Copy GPRPair0 into dest. (This copy will normally be coalesced.)
6686 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), destlo)
6687 .addReg(GPRPair0, 0, ARM::gsub_0);
6688 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), desthi)
6689 .addReg(GPRPair0, 0, ARM::gsub_1);
6691 AddDefaultPred(MIB);
6693 MI->eraseFromParent(); // The instruction is gone now.
6698 /// SetupEntryBlockForSjLj - Insert code into the entry block that creates and
6699 /// registers the function context.
6700 void ARMTargetLowering::
6701 SetupEntryBlockForSjLj(MachineInstr *MI, MachineBasicBlock *MBB,
6702 MachineBasicBlock *DispatchBB, int FI) const {
6703 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6704 DebugLoc dl = MI->getDebugLoc();
6705 MachineFunction *MF = MBB->getParent();
6706 MachineRegisterInfo *MRI = &MF->getRegInfo();
6707 MachineConstantPool *MCP = MF->getConstantPool();
6708 ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>();
6709 const Function *F = MF->getFunction();
6711 bool isThumb = Subtarget->isThumb();
6712 bool isThumb2 = Subtarget->isThumb2();
6714 unsigned PCLabelId = AFI->createPICLabelUId();
6715 unsigned PCAdj = (isThumb || isThumb2) ? 4 : 8;
6716 ARMConstantPoolValue *CPV =
6717 ARMConstantPoolMBB::Create(F->getContext(), DispatchBB, PCLabelId, PCAdj);
6718 unsigned CPI = MCP->getConstantPoolIndex(CPV, 4);
6720 const TargetRegisterClass *TRC = isThumb ?
6721 (const TargetRegisterClass*)&ARM::tGPRRegClass :
6722 (const TargetRegisterClass*)&ARM::GPRRegClass;
6724 // Grab constant pool and fixed stack memory operands.
6725 MachineMemOperand *CPMMO =
6726 MF->getMachineMemOperand(MachinePointerInfo::getConstantPool(),
6727 MachineMemOperand::MOLoad, 4, 4);
6729 MachineMemOperand *FIMMOSt =
6730 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
6731 MachineMemOperand::MOStore, 4, 4);
6733 // Load the address of the dispatch MBB into the jump buffer.
6735 // Incoming value: jbuf
6736 // ldr.n r5, LCPI1_1
6739 // str r5, [$jbuf, #+4] ; &jbuf[1]
6740 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6741 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2LDRpci), NewVReg1)
6742 .addConstantPoolIndex(CPI)
6743 .addMemOperand(CPMMO));
6744 // Set the low bit because of thumb mode.
6745 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6747 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2ORRri), NewVReg2)
6748 .addReg(NewVReg1, RegState::Kill)
6750 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6751 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg3)
6752 .addReg(NewVReg2, RegState::Kill)
6754 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2STRi12))
6755 .addReg(NewVReg3, RegState::Kill)
6757 .addImm(36) // &jbuf[1] :: pc
6758 .addMemOperand(FIMMOSt));
6759 } else if (isThumb) {
6760 // Incoming value: jbuf
6761 // ldr.n r1, LCPI1_4
6765 // add r2, $jbuf, #+4 ; &jbuf[1]
6767 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6768 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tLDRpci), NewVReg1)
6769 .addConstantPoolIndex(CPI)
6770 .addMemOperand(CPMMO));
6771 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6772 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg2)
6773 .addReg(NewVReg1, RegState::Kill)
6775 // Set the low bit because of thumb mode.
6776 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6777 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tMOVi8), NewVReg3)
6778 .addReg(ARM::CPSR, RegState::Define)
6780 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
6781 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tORR), NewVReg4)
6782 .addReg(ARM::CPSR, RegState::Define)
6783 .addReg(NewVReg2, RegState::Kill)
6784 .addReg(NewVReg3, RegState::Kill));
6785 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
6786 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tADDrSPi), NewVReg5)
6788 .addImm(36)); // &jbuf[1] :: pc
6789 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tSTRi))
6790 .addReg(NewVReg4, RegState::Kill)
6791 .addReg(NewVReg5, RegState::Kill)
6793 .addMemOperand(FIMMOSt));
6795 // Incoming value: jbuf
6798 // str r1, [$jbuf, #+4] ; &jbuf[1]
6799 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6800 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::LDRi12), NewVReg1)
6801 .addConstantPoolIndex(CPI)
6803 .addMemOperand(CPMMO));
6804 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6805 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::PICADD), NewVReg2)
6806 .addReg(NewVReg1, RegState::Kill)
6807 .addImm(PCLabelId));
6808 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::STRi12))
6809 .addReg(NewVReg2, RegState::Kill)
6811 .addImm(36) // &jbuf[1] :: pc
6812 .addMemOperand(FIMMOSt));
6816 MachineBasicBlock *ARMTargetLowering::
6817 EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const {
6818 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6819 DebugLoc dl = MI->getDebugLoc();
6820 MachineFunction *MF = MBB->getParent();
6821 MachineRegisterInfo *MRI = &MF->getRegInfo();
6822 ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>();
6823 MachineFrameInfo *MFI = MF->getFrameInfo();
6824 int FI = MFI->getFunctionContextIndex();
6826 const TargetRegisterClass *TRC = Subtarget->isThumb() ?
6827 (const TargetRegisterClass*)&ARM::tGPRRegClass :
6828 (const TargetRegisterClass*)&ARM::GPRnopcRegClass;
6830 // Get a mapping of the call site numbers to all of the landing pads they're
6832 DenseMap<unsigned, SmallVector<MachineBasicBlock*, 2> > CallSiteNumToLPad;
6833 unsigned MaxCSNum = 0;
6834 MachineModuleInfo &MMI = MF->getMMI();
6835 for (MachineFunction::iterator BB = MF->begin(), E = MF->end(); BB != E;
6837 if (!BB->isLandingPad()) continue;
6839 // FIXME: We should assert that the EH_LABEL is the first MI in the landing
6841 for (MachineBasicBlock::iterator
6842 II = BB->begin(), IE = BB->end(); II != IE; ++II) {
6843 if (!II->isEHLabel()) continue;
6845 MCSymbol *Sym = II->getOperand(0).getMCSymbol();
6846 if (!MMI.hasCallSiteLandingPad(Sym)) continue;
6848 SmallVectorImpl<unsigned> &CallSiteIdxs = MMI.getCallSiteLandingPad(Sym);
6849 for (SmallVectorImpl<unsigned>::iterator
6850 CSI = CallSiteIdxs.begin(), CSE = CallSiteIdxs.end();
6851 CSI != CSE; ++CSI) {
6852 CallSiteNumToLPad[*CSI].push_back(BB);
6853 MaxCSNum = std::max(MaxCSNum, *CSI);
6859 // Get an ordered list of the machine basic blocks for the jump table.
6860 std::vector<MachineBasicBlock*> LPadList;
6861 SmallPtrSet<MachineBasicBlock*, 64> InvokeBBs;
6862 LPadList.reserve(CallSiteNumToLPad.size());
6863 for (unsigned I = 1; I <= MaxCSNum; ++I) {
6864 SmallVectorImpl<MachineBasicBlock*> &MBBList = CallSiteNumToLPad[I];
6865 for (SmallVectorImpl<MachineBasicBlock*>::iterator
6866 II = MBBList.begin(), IE = MBBList.end(); II != IE; ++II) {
6867 LPadList.push_back(*II);
6868 InvokeBBs.insert((*II)->pred_begin(), (*II)->pred_end());
6872 assert(!LPadList.empty() &&
6873 "No landing pad destinations for the dispatch jump table!");
6875 // Create the jump table and associated information.
6876 MachineJumpTableInfo *JTI =
6877 MF->getOrCreateJumpTableInfo(MachineJumpTableInfo::EK_Inline);
6878 unsigned MJTI = JTI->createJumpTableIndex(LPadList);
6879 unsigned UId = AFI->createJumpTableUId();
6880 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
6882 // Create the MBBs for the dispatch code.
6884 // Shove the dispatch's address into the return slot in the function context.
6885 MachineBasicBlock *DispatchBB = MF->CreateMachineBasicBlock();
6886 DispatchBB->setIsLandingPad();
6888 MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock();
6889 unsigned trap_opcode;
6890 if (Subtarget->isThumb())
6891 trap_opcode = ARM::tTRAP;
6893 trap_opcode = Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP;
6895 BuildMI(TrapBB, dl, TII->get(trap_opcode));
6896 DispatchBB->addSuccessor(TrapBB);
6898 MachineBasicBlock *DispContBB = MF->CreateMachineBasicBlock();
6899 DispatchBB->addSuccessor(DispContBB);
6902 MF->insert(MF->end(), DispatchBB);
6903 MF->insert(MF->end(), DispContBB);
6904 MF->insert(MF->end(), TrapBB);
6906 // Insert code into the entry block that creates and registers the function
6908 SetupEntryBlockForSjLj(MI, MBB, DispatchBB, FI);
6910 MachineMemOperand *FIMMOLd =
6911 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
6912 MachineMemOperand::MOLoad |
6913 MachineMemOperand::MOVolatile, 4, 4);
6915 MachineInstrBuilder MIB;
6916 MIB = BuildMI(DispatchBB, dl, TII->get(ARM::Int_eh_sjlj_dispatchsetup));
6918 const ARMBaseInstrInfo *AII = static_cast<const ARMBaseInstrInfo*>(TII);
6919 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
6921 // Add a register mask with no preserved registers. This results in all
6922 // registers being marked as clobbered.
6923 MIB.addRegMask(RI.getNoPreservedMask());
6925 unsigned NumLPads = LPadList.size();
6926 if (Subtarget->isThumb2()) {
6927 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6928 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2LDRi12), NewVReg1)
6931 .addMemOperand(FIMMOLd));
6933 if (NumLPads < 256) {
6934 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPri))
6936 .addImm(LPadList.size()));
6938 unsigned VReg1 = MRI->createVirtualRegister(TRC);
6939 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVi16), VReg1)
6940 .addImm(NumLPads & 0xFFFF));
6942 unsigned VReg2 = VReg1;
6943 if ((NumLPads & 0xFFFF0000) != 0) {
6944 VReg2 = MRI->createVirtualRegister(TRC);
6945 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVTi16), VReg2)
6947 .addImm(NumLPads >> 16));
6950 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPrr))
6955 BuildMI(DispatchBB, dl, TII->get(ARM::t2Bcc))
6960 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6961 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::t2LEApcrelJT),NewVReg3)
6962 .addJumpTableIndex(MJTI)
6965 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
6968 BuildMI(DispContBB, dl, TII->get(ARM::t2ADDrs), NewVReg4)
6969 .addReg(NewVReg3, RegState::Kill)
6971 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))));
6973 BuildMI(DispContBB, dl, TII->get(ARM::t2BR_JT))
6974 .addReg(NewVReg4, RegState::Kill)
6976 .addJumpTableIndex(MJTI)
6978 } else if (Subtarget->isThumb()) {
6979 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6980 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRspi), NewVReg1)
6983 .addMemOperand(FIMMOLd));
6985 if (NumLPads < 256) {
6986 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPi8))
6990 MachineConstantPool *ConstantPool = MF->getConstantPool();
6991 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
6992 const Constant *C = ConstantInt::get(Int32Ty, NumLPads);
6994 // MachineConstantPool wants an explicit alignment.
6995 unsigned Align = getDataLayout()->getPrefTypeAlignment(Int32Ty);
6997 Align = getDataLayout()->getTypeAllocSize(C->getType());
6998 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
7000 unsigned VReg1 = MRI->createVirtualRegister(TRC);
7001 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRpci))
7002 .addReg(VReg1, RegState::Define)
7003 .addConstantPoolIndex(Idx));
7004 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPr))
7009 BuildMI(DispatchBB, dl, TII->get(ARM::tBcc))
7014 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
7015 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLSLri), NewVReg2)
7016 .addReg(ARM::CPSR, RegState::Define)
7020 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
7021 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLEApcrelJT), NewVReg3)
7022 .addJumpTableIndex(MJTI)
7025 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
7026 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg4)
7027 .addReg(ARM::CPSR, RegState::Define)
7028 .addReg(NewVReg2, RegState::Kill)
7031 MachineMemOperand *JTMMOLd =
7032 MF->getMachineMemOperand(MachinePointerInfo::getJumpTable(),
7033 MachineMemOperand::MOLoad, 4, 4);
7035 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
7036 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLDRi), NewVReg5)
7037 .addReg(NewVReg4, RegState::Kill)
7039 .addMemOperand(JTMMOLd));
7041 unsigned NewVReg6 = NewVReg5;
7042 if (RelocM == Reloc::PIC_) {
7043 NewVReg6 = MRI->createVirtualRegister(TRC);
7044 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg6)
7045 .addReg(ARM::CPSR, RegState::Define)
7046 .addReg(NewVReg5, RegState::Kill)
7050 BuildMI(DispContBB, dl, TII->get(ARM::tBR_JTr))
7051 .addReg(NewVReg6, RegState::Kill)
7052 .addJumpTableIndex(MJTI)
7055 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
7056 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRi12), NewVReg1)
7059 .addMemOperand(FIMMOLd));
7061 if (NumLPads < 256) {
7062 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPri))
7065 } else if (Subtarget->hasV6T2Ops() && isUInt<16>(NumLPads)) {
7066 unsigned VReg1 = MRI->createVirtualRegister(TRC);
7067 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVi16), VReg1)
7068 .addImm(NumLPads & 0xFFFF));
7070 unsigned VReg2 = VReg1;
7071 if ((NumLPads & 0xFFFF0000) != 0) {
7072 VReg2 = MRI->createVirtualRegister(TRC);
7073 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVTi16), VReg2)
7075 .addImm(NumLPads >> 16));
7078 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
7082 MachineConstantPool *ConstantPool = MF->getConstantPool();
7083 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
7084 const Constant *C = ConstantInt::get(Int32Ty, NumLPads);
7086 // MachineConstantPool wants an explicit alignment.
7087 unsigned Align = getDataLayout()->getPrefTypeAlignment(Int32Ty);
7089 Align = getDataLayout()->getTypeAllocSize(C->getType());
7090 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
7092 unsigned VReg1 = MRI->createVirtualRegister(TRC);
7093 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRcp))
7094 .addReg(VReg1, RegState::Define)
7095 .addConstantPoolIndex(Idx)
7097 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
7099 .addReg(VReg1, RegState::Kill));
7102 BuildMI(DispatchBB, dl, TII->get(ARM::Bcc))
7107 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
7109 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::MOVsi), NewVReg3)
7111 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))));
7112 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
7113 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::LEApcrelJT), NewVReg4)
7114 .addJumpTableIndex(MJTI)
7117 MachineMemOperand *JTMMOLd =
7118 MF->getMachineMemOperand(MachinePointerInfo::getJumpTable(),
7119 MachineMemOperand::MOLoad, 4, 4);
7120 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
7122 BuildMI(DispContBB, dl, TII->get(ARM::LDRrs), NewVReg5)
7123 .addReg(NewVReg3, RegState::Kill)
7126 .addMemOperand(JTMMOLd));
7128 if (RelocM == Reloc::PIC_) {
7129 BuildMI(DispContBB, dl, TII->get(ARM::BR_JTadd))
7130 .addReg(NewVReg5, RegState::Kill)
7132 .addJumpTableIndex(MJTI)
7135 BuildMI(DispContBB, dl, TII->get(ARM::BR_JTr))
7136 .addReg(NewVReg5, RegState::Kill)
7137 .addJumpTableIndex(MJTI)
7142 // Add the jump table entries as successors to the MBB.
7143 SmallPtrSet<MachineBasicBlock*, 8> SeenMBBs;
7144 for (std::vector<MachineBasicBlock*>::iterator
7145 I = LPadList.begin(), E = LPadList.end(); I != E; ++I) {
7146 MachineBasicBlock *CurMBB = *I;
7147 if (SeenMBBs.insert(CurMBB))
7148 DispContBB->addSuccessor(CurMBB);
7151 // N.B. the order the invoke BBs are processed in doesn't matter here.
7152 const uint16_t *SavedRegs = RI.getCalleeSavedRegs(MF);
7153 SmallVector<MachineBasicBlock*, 64> MBBLPads;
7154 for (SmallPtrSet<MachineBasicBlock*, 64>::iterator
7155 I = InvokeBBs.begin(), E = InvokeBBs.end(); I != E; ++I) {
7156 MachineBasicBlock *BB = *I;
7158 // Remove the landing pad successor from the invoke block and replace it
7159 // with the new dispatch block.
7160 SmallVector<MachineBasicBlock*, 4> Successors(BB->succ_begin(),
7162 while (!Successors.empty()) {
7163 MachineBasicBlock *SMBB = Successors.pop_back_val();
7164 if (SMBB->isLandingPad()) {
7165 BB->removeSuccessor(SMBB);
7166 MBBLPads.push_back(SMBB);
7170 BB->addSuccessor(DispatchBB);
7172 // Find the invoke call and mark all of the callee-saved registers as
7173 // 'implicit defined' so that they're spilled. This prevents code from
7174 // moving instructions to before the EH block, where they will never be
7176 for (MachineBasicBlock::reverse_iterator
7177 II = BB->rbegin(), IE = BB->rend(); II != IE; ++II) {
7178 if (!II->isCall()) continue;
7180 DenseMap<unsigned, bool> DefRegs;
7181 for (MachineInstr::mop_iterator
7182 OI = II->operands_begin(), OE = II->operands_end();
7184 if (!OI->isReg()) continue;
7185 DefRegs[OI->getReg()] = true;
7188 MachineInstrBuilder MIB(*MF, &*II);
7190 for (unsigned i = 0; SavedRegs[i] != 0; ++i) {
7191 unsigned Reg = SavedRegs[i];
7192 if (Subtarget->isThumb2() &&
7193 !ARM::tGPRRegClass.contains(Reg) &&
7194 !ARM::hGPRRegClass.contains(Reg))
7196 if (Subtarget->isThumb1Only() && !ARM::tGPRRegClass.contains(Reg))
7198 if (!Subtarget->isThumb() && !ARM::GPRRegClass.contains(Reg))
7201 MIB.addReg(Reg, RegState::ImplicitDefine | RegState::Dead);
7208 // Mark all former landing pads as non-landing pads. The dispatch is the only
7210 for (SmallVectorImpl<MachineBasicBlock*>::iterator
7211 I = MBBLPads.begin(), E = MBBLPads.end(); I != E; ++I)
7212 (*I)->setIsLandingPad(false);
7214 // The instruction is gone now.
7215 MI->eraseFromParent();
7221 MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
7222 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
7223 E = MBB->succ_end(); I != E; ++I)
7226 llvm_unreachable("Expecting a BB with two successors!");
7229 /// Return the load opcode for a given load size. If load size >= 8,
7230 /// neon opcode will be returned.
7231 static unsigned getLdOpcode(unsigned LdSize, bool IsThumb1, bool IsThumb2) {
7233 return LdSize == 16 ? ARM::VLD1q32wb_fixed
7234 : LdSize == 8 ? ARM::VLD1d32wb_fixed : 0;
7236 return LdSize == 4 ? ARM::tLDRi
7237 : LdSize == 2 ? ARM::tLDRHi
7238 : LdSize == 1 ? ARM::tLDRBi : 0;
7240 return LdSize == 4 ? ARM::t2LDR_POST
7241 : LdSize == 2 ? ARM::t2LDRH_POST
7242 : LdSize == 1 ? ARM::t2LDRB_POST : 0;
7243 return LdSize == 4 ? ARM::LDR_POST_IMM
7244 : LdSize == 2 ? ARM::LDRH_POST
7245 : LdSize == 1 ? ARM::LDRB_POST_IMM : 0;
7248 /// Return the store opcode for a given store size. If store size >= 8,
7249 /// neon opcode will be returned.
7250 static unsigned getStOpcode(unsigned StSize, bool IsThumb1, bool IsThumb2) {
7252 return StSize == 16 ? ARM::VST1q32wb_fixed
7253 : StSize == 8 ? ARM::VST1d32wb_fixed : 0;
7255 return StSize == 4 ? ARM::tSTRi
7256 : StSize == 2 ? ARM::tSTRHi
7257 : StSize == 1 ? ARM::tSTRBi : 0;
7259 return StSize == 4 ? ARM::t2STR_POST
7260 : StSize == 2 ? ARM::t2STRH_POST
7261 : StSize == 1 ? ARM::t2STRB_POST : 0;
7262 return StSize == 4 ? ARM::STR_POST_IMM
7263 : StSize == 2 ? ARM::STRH_POST
7264 : StSize == 1 ? ARM::STRB_POST_IMM : 0;
7267 /// Emit a post-increment load operation with given size. The instructions
7268 /// will be added to BB at Pos.
7269 static void emitPostLd(MachineBasicBlock *BB, MachineInstr *Pos,
7270 const TargetInstrInfo *TII, DebugLoc dl,
7271 unsigned LdSize, unsigned Data, unsigned AddrIn,
7272 unsigned AddrOut, bool IsThumb1, bool IsThumb2) {
7273 unsigned LdOpc = getLdOpcode(LdSize, IsThumb1, IsThumb2);
7274 assert(LdOpc != 0 && "Should have a load opcode");
7276 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
7277 .addReg(AddrOut, RegState::Define).addReg(AddrIn)
7279 } else if (IsThumb1) {
7280 // load + update AddrIn
7281 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
7282 .addReg(AddrIn).addImm(0));
7283 MachineInstrBuilder MIB =
7284 BuildMI(*BB, Pos, dl, TII->get(ARM::tADDi8), AddrOut);
7285 MIB = AddDefaultT1CC(MIB);
7286 MIB.addReg(AddrIn).addImm(LdSize);
7287 AddDefaultPred(MIB);
7288 } else if (IsThumb2) {
7289 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
7290 .addReg(AddrOut, RegState::Define).addReg(AddrIn)
7293 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
7294 .addReg(AddrOut, RegState::Define).addReg(AddrIn)
7295 .addReg(0).addImm(LdSize));
7299 /// Emit a post-increment store operation with given size. The instructions
7300 /// will be added to BB at Pos.
7301 static void emitPostSt(MachineBasicBlock *BB, MachineInstr *Pos,
7302 const TargetInstrInfo *TII, DebugLoc dl,
7303 unsigned StSize, unsigned Data, unsigned AddrIn,
7304 unsigned AddrOut, bool IsThumb1, bool IsThumb2) {
7305 unsigned StOpc = getStOpcode(StSize, IsThumb1, IsThumb2);
7306 assert(StOpc != 0 && "Should have a store opcode");
7308 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
7309 .addReg(AddrIn).addImm(0).addReg(Data));
7310 } else if (IsThumb1) {
7311 // store + update AddrIn
7312 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc)).addReg(Data)
7313 .addReg(AddrIn).addImm(0));
7314 MachineInstrBuilder MIB =
7315 BuildMI(*BB, Pos, dl, TII->get(ARM::tADDi8), AddrOut);
7316 MIB = AddDefaultT1CC(MIB);
7317 MIB.addReg(AddrIn).addImm(StSize);
7318 AddDefaultPred(MIB);
7319 } else if (IsThumb2) {
7320 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
7321 .addReg(Data).addReg(AddrIn).addImm(StSize));
7323 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
7324 .addReg(Data).addReg(AddrIn).addReg(0)
7330 ARMTargetLowering::EmitStructByval(MachineInstr *MI,
7331 MachineBasicBlock *BB) const {
7332 // This pseudo instruction has 3 operands: dst, src, size
7333 // We expand it to a loop if size > Subtarget->getMaxInlineSizeThreshold().
7334 // Otherwise, we will generate unrolled scalar copies.
7335 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7336 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7337 MachineFunction::iterator It = BB;
7340 unsigned dest = MI->getOperand(0).getReg();
7341 unsigned src = MI->getOperand(1).getReg();
7342 unsigned SizeVal = MI->getOperand(2).getImm();
7343 unsigned Align = MI->getOperand(3).getImm();
7344 DebugLoc dl = MI->getDebugLoc();
7346 MachineFunction *MF = BB->getParent();
7347 MachineRegisterInfo &MRI = MF->getRegInfo();
7348 unsigned UnitSize = 0;
7349 const TargetRegisterClass *TRC = 0;
7350 const TargetRegisterClass *VecTRC = 0;
7352 bool IsThumb1 = Subtarget->isThumb1Only();
7353 bool IsThumb2 = Subtarget->isThumb2();
7357 } else if (Align & 2) {
7360 // Check whether we can use NEON instructions.
7361 if (!MF->getFunction()->getAttributes().
7362 hasAttribute(AttributeSet::FunctionIndex,
7363 Attribute::NoImplicitFloat) &&
7364 Subtarget->hasNEON()) {
7365 if ((Align % 16 == 0) && SizeVal >= 16)
7367 else if ((Align % 8 == 0) && SizeVal >= 8)
7370 // Can't use NEON instructions.
7375 // Select the correct opcode and register class for unit size load/store
7376 bool IsNeon = UnitSize >= 8;
7377 TRC = (IsThumb1 || IsThumb2) ? (const TargetRegisterClass *)&ARM::tGPRRegClass
7378 : (const TargetRegisterClass *)&ARM::GPRRegClass;
7380 VecTRC = UnitSize == 16
7381 ? (const TargetRegisterClass *)&ARM::DPairRegClass
7383 ? (const TargetRegisterClass *)&ARM::DPRRegClass
7386 unsigned BytesLeft = SizeVal % UnitSize;
7387 unsigned LoopSize = SizeVal - BytesLeft;
7389 if (SizeVal <= Subtarget->getMaxInlineSizeThreshold()) {
7390 // Use LDR and STR to copy.
7391 // [scratch, srcOut] = LDR_POST(srcIn, UnitSize)
7392 // [destOut] = STR_POST(scratch, destIn, UnitSize)
7393 unsigned srcIn = src;
7394 unsigned destIn = dest;
7395 for (unsigned i = 0; i < LoopSize; i+=UnitSize) {
7396 unsigned srcOut = MRI.createVirtualRegister(TRC);
7397 unsigned destOut = MRI.createVirtualRegister(TRC);
7398 unsigned scratch = MRI.createVirtualRegister(IsNeon ? VecTRC : TRC);
7399 emitPostLd(BB, MI, TII, dl, UnitSize, scratch, srcIn, srcOut,
7400 IsThumb1, IsThumb2);
7401 emitPostSt(BB, MI, TII, dl, UnitSize, scratch, destIn, destOut,
7402 IsThumb1, IsThumb2);
7407 // Handle the leftover bytes with LDRB and STRB.
7408 // [scratch, srcOut] = LDRB_POST(srcIn, 1)
7409 // [destOut] = STRB_POST(scratch, destIn, 1)
7410 for (unsigned i = 0; i < BytesLeft; i++) {
7411 unsigned srcOut = MRI.createVirtualRegister(TRC);
7412 unsigned destOut = MRI.createVirtualRegister(TRC);
7413 unsigned scratch = MRI.createVirtualRegister(TRC);
7414 emitPostLd(BB, MI, TII, dl, 1, scratch, srcIn, srcOut,
7415 IsThumb1, IsThumb2);
7416 emitPostSt(BB, MI, TII, dl, 1, scratch, destIn, destOut,
7417 IsThumb1, IsThumb2);
7421 MI->eraseFromParent(); // The instruction is gone now.
7425 // Expand the pseudo op to a loop.
7428 // movw varEnd, # --> with thumb2
7430 // ldrcp varEnd, idx --> without thumb2
7431 // fallthrough --> loopMBB
7433 // PHI varPhi, varEnd, varLoop
7434 // PHI srcPhi, src, srcLoop
7435 // PHI destPhi, dst, destLoop
7436 // [scratch, srcLoop] = LDR_POST(srcPhi, UnitSize)
7437 // [destLoop] = STR_POST(scratch, destPhi, UnitSize)
7438 // subs varLoop, varPhi, #UnitSize
7440 // fallthrough --> exitMBB
7442 // epilogue to handle left-over bytes
7443 // [scratch, srcOut] = LDRB_POST(srcLoop, 1)
7444 // [destOut] = STRB_POST(scratch, destLoop, 1)
7445 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
7446 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
7447 MF->insert(It, loopMBB);
7448 MF->insert(It, exitMBB);
7450 // Transfer the remainder of BB and its successor edges to exitMBB.
7451 exitMBB->splice(exitMBB->begin(), BB,
7452 llvm::next(MachineBasicBlock::iterator(MI)),
7454 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7456 // Load an immediate to varEnd.
7457 unsigned varEnd = MRI.createVirtualRegister(TRC);
7459 unsigned Vtmp = varEnd;
7460 if ((LoopSize & 0xFFFF0000) != 0)
7461 Vtmp = MRI.createVirtualRegister(TRC);
7462 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2MOVi16), Vtmp)
7463 .addImm(LoopSize & 0xFFFF));
7465 if ((LoopSize & 0xFFFF0000) != 0)
7466 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2MOVTi16), varEnd)
7467 .addReg(Vtmp).addImm(LoopSize >> 16));
7469 MachineConstantPool *ConstantPool = MF->getConstantPool();
7470 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
7471 const Constant *C = ConstantInt::get(Int32Ty, LoopSize);
7473 // MachineConstantPool wants an explicit alignment.
7474 unsigned Align = getDataLayout()->getPrefTypeAlignment(Int32Ty);
7476 Align = getDataLayout()->getTypeAllocSize(C->getType());
7477 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
7480 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(ARM::tLDRpci)).addReg(
7481 varEnd, RegState::Define).addConstantPoolIndex(Idx));
7483 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(ARM::LDRcp)).addReg(
7484 varEnd, RegState::Define).addConstantPoolIndex(Idx).addImm(0));
7486 BB->addSuccessor(loopMBB);
7488 // Generate the loop body:
7489 // varPhi = PHI(varLoop, varEnd)
7490 // srcPhi = PHI(srcLoop, src)
7491 // destPhi = PHI(destLoop, dst)
7492 MachineBasicBlock *entryBB = BB;
7494 unsigned varLoop = MRI.createVirtualRegister(TRC);
7495 unsigned varPhi = MRI.createVirtualRegister(TRC);
7496 unsigned srcLoop = MRI.createVirtualRegister(TRC);
7497 unsigned srcPhi = MRI.createVirtualRegister(TRC);
7498 unsigned destLoop = MRI.createVirtualRegister(TRC);
7499 unsigned destPhi = MRI.createVirtualRegister(TRC);
7501 BuildMI(*BB, BB->begin(), dl, TII->get(ARM::PHI), varPhi)
7502 .addReg(varLoop).addMBB(loopMBB)
7503 .addReg(varEnd).addMBB(entryBB);
7504 BuildMI(BB, dl, TII->get(ARM::PHI), srcPhi)
7505 .addReg(srcLoop).addMBB(loopMBB)
7506 .addReg(src).addMBB(entryBB);
7507 BuildMI(BB, dl, TII->get(ARM::PHI), destPhi)
7508 .addReg(destLoop).addMBB(loopMBB)
7509 .addReg(dest).addMBB(entryBB);
7511 // [scratch, srcLoop] = LDR_POST(srcPhi, UnitSize)
7512 // [destLoop] = STR_POST(scratch, destPhi, UnitSiz)
7513 unsigned scratch = MRI.createVirtualRegister(IsNeon ? VecTRC : TRC);
7514 emitPostLd(BB, BB->end(), TII, dl, UnitSize, scratch, srcPhi, srcLoop,
7515 IsThumb1, IsThumb2);
7516 emitPostSt(BB, BB->end(), TII, dl, UnitSize, scratch, destPhi, destLoop,
7517 IsThumb1, IsThumb2);
7519 // Decrement loop variable by UnitSize.
7521 MachineInstrBuilder MIB =
7522 BuildMI(*BB, BB->end(), dl, TII->get(ARM::tSUBi8), varLoop);
7523 MIB = AddDefaultT1CC(MIB);
7524 MIB.addReg(varPhi).addImm(UnitSize);
7525 AddDefaultPred(MIB);
7527 MachineInstrBuilder MIB =
7528 BuildMI(*BB, BB->end(), dl,
7529 TII->get(IsThumb2 ? ARM::t2SUBri : ARM::SUBri), varLoop);
7530 AddDefaultCC(AddDefaultPred(MIB.addReg(varPhi).addImm(UnitSize)));
7531 MIB->getOperand(5).setReg(ARM::CPSR);
7532 MIB->getOperand(5).setIsDef(true);
7534 BuildMI(*BB, BB->end(), dl,
7535 TII->get(IsThumb1 ? ARM::tBcc : IsThumb2 ? ARM::t2Bcc : ARM::Bcc))
7536 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
7538 // loopMBB can loop back to loopMBB or fall through to exitMBB.
7539 BB->addSuccessor(loopMBB);
7540 BB->addSuccessor(exitMBB);
7542 // Add epilogue to handle BytesLeft.
7544 MachineInstr *StartOfExit = exitMBB->begin();
7546 // [scratch, srcOut] = LDRB_POST(srcLoop, 1)
7547 // [destOut] = STRB_POST(scratch, destLoop, 1)
7548 unsigned srcIn = srcLoop;
7549 unsigned destIn = destLoop;
7550 for (unsigned i = 0; i < BytesLeft; i++) {
7551 unsigned srcOut = MRI.createVirtualRegister(TRC);
7552 unsigned destOut = MRI.createVirtualRegister(TRC);
7553 unsigned scratch = MRI.createVirtualRegister(TRC);
7554 emitPostLd(BB, StartOfExit, TII, dl, 1, scratch, srcIn, srcOut,
7555 IsThumb1, IsThumb2);
7556 emitPostSt(BB, StartOfExit, TII, dl, 1, scratch, destIn, destOut,
7557 IsThumb1, IsThumb2);
7562 MI->eraseFromParent(); // The instruction is gone now.
7567 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
7568 MachineBasicBlock *BB) const {
7569 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
7570 DebugLoc dl = MI->getDebugLoc();
7571 bool isThumb2 = Subtarget->isThumb2();
7572 switch (MI->getOpcode()) {
7575 llvm_unreachable("Unexpected instr type to insert");
7577 // The Thumb2 pre-indexed stores have the same MI operands, they just
7578 // define them differently in the .td files from the isel patterns, so
7579 // they need pseudos.
7580 case ARM::t2STR_preidx:
7581 MI->setDesc(TII->get(ARM::t2STR_PRE));
7583 case ARM::t2STRB_preidx:
7584 MI->setDesc(TII->get(ARM::t2STRB_PRE));
7586 case ARM::t2STRH_preidx:
7587 MI->setDesc(TII->get(ARM::t2STRH_PRE));
7590 case ARM::STRi_preidx:
7591 case ARM::STRBi_preidx: {
7592 unsigned NewOpc = MI->getOpcode() == ARM::STRi_preidx ?
7593 ARM::STR_PRE_IMM : ARM::STRB_PRE_IMM;
7594 // Decode the offset.
7595 unsigned Offset = MI->getOperand(4).getImm();
7596 bool isSub = ARM_AM::getAM2Op(Offset) == ARM_AM::sub;
7597 Offset = ARM_AM::getAM2Offset(Offset);
7601 MachineMemOperand *MMO = *MI->memoperands_begin();
7602 BuildMI(*BB, MI, dl, TII->get(NewOpc))
7603 .addOperand(MI->getOperand(0)) // Rn_wb
7604 .addOperand(MI->getOperand(1)) // Rt
7605 .addOperand(MI->getOperand(2)) // Rn
7606 .addImm(Offset) // offset (skip GPR==zero_reg)
7607 .addOperand(MI->getOperand(5)) // pred
7608 .addOperand(MI->getOperand(6))
7609 .addMemOperand(MMO);
7610 MI->eraseFromParent();
7613 case ARM::STRr_preidx:
7614 case ARM::STRBr_preidx:
7615 case ARM::STRH_preidx: {
7617 switch (MI->getOpcode()) {
7618 default: llvm_unreachable("unexpected opcode!");
7619 case ARM::STRr_preidx: NewOpc = ARM::STR_PRE_REG; break;
7620 case ARM::STRBr_preidx: NewOpc = ARM::STRB_PRE_REG; break;
7621 case ARM::STRH_preidx: NewOpc = ARM::STRH_PRE; break;
7623 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc));
7624 for (unsigned i = 0; i < MI->getNumOperands(); ++i)
7625 MIB.addOperand(MI->getOperand(i));
7626 MI->eraseFromParent();
7629 case ARM::ATOMIC_LOAD_ADD_I8:
7630 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
7631 case ARM::ATOMIC_LOAD_ADD_I16:
7632 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
7633 case ARM::ATOMIC_LOAD_ADD_I32:
7634 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
7636 case ARM::ATOMIC_LOAD_AND_I8:
7637 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
7638 case ARM::ATOMIC_LOAD_AND_I16:
7639 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
7640 case ARM::ATOMIC_LOAD_AND_I32:
7641 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
7643 case ARM::ATOMIC_LOAD_OR_I8:
7644 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
7645 case ARM::ATOMIC_LOAD_OR_I16:
7646 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
7647 case ARM::ATOMIC_LOAD_OR_I32:
7648 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
7650 case ARM::ATOMIC_LOAD_XOR_I8:
7651 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
7652 case ARM::ATOMIC_LOAD_XOR_I16:
7653 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
7654 case ARM::ATOMIC_LOAD_XOR_I32:
7655 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
7657 case ARM::ATOMIC_LOAD_NAND_I8:
7658 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
7659 case ARM::ATOMIC_LOAD_NAND_I16:
7660 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
7661 case ARM::ATOMIC_LOAD_NAND_I32:
7662 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
7664 case ARM::ATOMIC_LOAD_SUB_I8:
7665 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
7666 case ARM::ATOMIC_LOAD_SUB_I16:
7667 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
7668 case ARM::ATOMIC_LOAD_SUB_I32:
7669 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
7671 case ARM::ATOMIC_LOAD_MIN_I8:
7672 return EmitAtomicBinaryMinMax(MI, BB, 1, true, ARMCC::LT);
7673 case ARM::ATOMIC_LOAD_MIN_I16:
7674 return EmitAtomicBinaryMinMax(MI, BB, 2, true, ARMCC::LT);
7675 case ARM::ATOMIC_LOAD_MIN_I32:
7676 return EmitAtomicBinaryMinMax(MI, BB, 4, true, ARMCC::LT);
7678 case ARM::ATOMIC_LOAD_MAX_I8:
7679 return EmitAtomicBinaryMinMax(MI, BB, 1, true, ARMCC::GT);
7680 case ARM::ATOMIC_LOAD_MAX_I16:
7681 return EmitAtomicBinaryMinMax(MI, BB, 2, true, ARMCC::GT);
7682 case ARM::ATOMIC_LOAD_MAX_I32:
7683 return EmitAtomicBinaryMinMax(MI, BB, 4, true, ARMCC::GT);
7685 case ARM::ATOMIC_LOAD_UMIN_I8:
7686 return EmitAtomicBinaryMinMax(MI, BB, 1, false, ARMCC::LO);
7687 case ARM::ATOMIC_LOAD_UMIN_I16:
7688 return EmitAtomicBinaryMinMax(MI, BB, 2, false, ARMCC::LO);
7689 case ARM::ATOMIC_LOAD_UMIN_I32:
7690 return EmitAtomicBinaryMinMax(MI, BB, 4, false, ARMCC::LO);
7692 case ARM::ATOMIC_LOAD_UMAX_I8:
7693 return EmitAtomicBinaryMinMax(MI, BB, 1, false, ARMCC::HI);
7694 case ARM::ATOMIC_LOAD_UMAX_I16:
7695 return EmitAtomicBinaryMinMax(MI, BB, 2, false, ARMCC::HI);
7696 case ARM::ATOMIC_LOAD_UMAX_I32:
7697 return EmitAtomicBinaryMinMax(MI, BB, 4, false, ARMCC::HI);
7699 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0);
7700 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0);
7701 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0);
7703 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1);
7704 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
7705 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
7707 case ARM::ATOMIC_LOAD_I64:
7708 return EmitAtomicLoad64(MI, BB);
7710 case ARM::ATOMIC_LOAD_ADD_I64:
7711 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr,
7712 isThumb2 ? ARM::t2ADCrr : ARM::ADCrr,
7713 /*NeedsCarry*/ true);
7714 case ARM::ATOMIC_LOAD_SUB_I64:
7715 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr,
7716 isThumb2 ? ARM::t2SBCrr : ARM::SBCrr,
7717 /*NeedsCarry*/ true);
7718 case ARM::ATOMIC_LOAD_OR_I64:
7719 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr,
7720 isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
7721 case ARM::ATOMIC_LOAD_XOR_I64:
7722 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2EORrr : ARM::EORrr,
7723 isThumb2 ? ARM::t2EORrr : ARM::EORrr);
7724 case ARM::ATOMIC_LOAD_AND_I64:
7725 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr,
7726 isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
7727 case ARM::ATOMIC_STORE_I64:
7728 case ARM::ATOMIC_SWAP_I64:
7729 return EmitAtomicBinary64(MI, BB, 0, 0, false);
7730 case ARM::ATOMIC_CMP_SWAP_I64:
7731 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr,
7732 isThumb2 ? ARM::t2SBCrr : ARM::SBCrr,
7733 /*NeedsCarry*/ false, /*IsCmpxchg*/true);
7734 case ARM::ATOMIC_LOAD_MIN_I64:
7735 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr,
7736 isThumb2 ? ARM::t2SBCrr : ARM::SBCrr,
7737 /*NeedsCarry*/ true, /*IsCmpxchg*/false,
7738 /*IsMinMax*/ true, ARMCC::LT);
7739 case ARM::ATOMIC_LOAD_MAX_I64:
7740 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr,
7741 isThumb2 ? ARM::t2SBCrr : ARM::SBCrr,
7742 /*NeedsCarry*/ true, /*IsCmpxchg*/false,
7743 /*IsMinMax*/ true, ARMCC::GE);
7744 case ARM::ATOMIC_LOAD_UMIN_I64:
7745 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr,
7746 isThumb2 ? ARM::t2SBCrr : ARM::SBCrr,
7747 /*NeedsCarry*/ true, /*IsCmpxchg*/false,
7748 /*IsMinMax*/ true, ARMCC::LO);
7749 case ARM::ATOMIC_LOAD_UMAX_I64:
7750 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr,
7751 isThumb2 ? ARM::t2SBCrr : ARM::SBCrr,
7752 /*NeedsCarry*/ true, /*IsCmpxchg*/false,
7753 /*IsMinMax*/ true, ARMCC::HS);
7755 case ARM::tMOVCCr_pseudo: {
7756 // To "insert" a SELECT_CC instruction, we actually have to insert the
7757 // diamond control-flow pattern. The incoming instruction knows the
7758 // destination vreg to set, the condition code register to branch on, the
7759 // true/false values to select between, and a branch opcode to use.
7760 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7761 MachineFunction::iterator It = BB;
7767 // cmpTY ccX, r1, r2
7769 // fallthrough --> copy0MBB
7770 MachineBasicBlock *thisMBB = BB;
7771 MachineFunction *F = BB->getParent();
7772 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7773 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7774 F->insert(It, copy0MBB);
7775 F->insert(It, sinkMBB);
7777 // Transfer the remainder of BB and its successor edges to sinkMBB.
7778 sinkMBB->splice(sinkMBB->begin(), BB,
7779 llvm::next(MachineBasicBlock::iterator(MI)),
7781 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
7783 BB->addSuccessor(copy0MBB);
7784 BB->addSuccessor(sinkMBB);
7786 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
7787 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
7790 // %FalseValue = ...
7791 // # fallthrough to sinkMBB
7794 // Update machine-CFG edges
7795 BB->addSuccessor(sinkMBB);
7798 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7801 BuildMI(*BB, BB->begin(), dl,
7802 TII->get(ARM::PHI), MI->getOperand(0).getReg())
7803 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
7804 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7806 MI->eraseFromParent(); // The pseudo instruction is gone now.
7811 case ARM::BCCZi64: {
7812 // If there is an unconditional branch to the other successor, remove it.
7813 BB->erase(llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
7815 // Compare both parts that make up the double comparison separately for
7817 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
7819 unsigned LHS1 = MI->getOperand(1).getReg();
7820 unsigned LHS2 = MI->getOperand(2).getReg();
7822 AddDefaultPred(BuildMI(BB, dl,
7823 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
7824 .addReg(LHS1).addImm(0));
7825 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
7826 .addReg(LHS2).addImm(0)
7827 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
7829 unsigned RHS1 = MI->getOperand(3).getReg();
7830 unsigned RHS2 = MI->getOperand(4).getReg();
7831 AddDefaultPred(BuildMI(BB, dl,
7832 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
7833 .addReg(LHS1).addReg(RHS1));
7834 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
7835 .addReg(LHS2).addReg(RHS2)
7836 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
7839 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB();
7840 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
7841 if (MI->getOperand(0).getImm() == ARMCC::NE)
7842 std::swap(destMBB, exitMBB);
7844 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
7845 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
7847 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2B)).addMBB(exitMBB));
7849 BuildMI(BB, dl, TII->get(ARM::B)) .addMBB(exitMBB);
7851 MI->eraseFromParent(); // The pseudo instruction is gone now.
7855 case ARM::Int_eh_sjlj_setjmp:
7856 case ARM::Int_eh_sjlj_setjmp_nofp:
7857 case ARM::tInt_eh_sjlj_setjmp:
7858 case ARM::t2Int_eh_sjlj_setjmp:
7859 case ARM::t2Int_eh_sjlj_setjmp_nofp:
7860 EmitSjLjDispatchBlock(MI, BB);
7865 // To insert an ABS instruction, we have to insert the
7866 // diamond control-flow pattern. The incoming instruction knows the
7867 // source vreg to test against 0, the destination vreg to set,
7868 // the condition code register to branch on, the
7869 // true/false values to select between, and a branch opcode to use.
7874 // BCC (branch to SinkBB if V0 >= 0)
7875 // RSBBB: V3 = RSBri V2, 0 (compute ABS if V2 < 0)
7876 // SinkBB: V1 = PHI(V2, V3)
7877 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7878 MachineFunction::iterator BBI = BB;
7880 MachineFunction *Fn = BB->getParent();
7881 MachineBasicBlock *RSBBB = Fn->CreateMachineBasicBlock(LLVM_BB);
7882 MachineBasicBlock *SinkBB = Fn->CreateMachineBasicBlock(LLVM_BB);
7883 Fn->insert(BBI, RSBBB);
7884 Fn->insert(BBI, SinkBB);
7886 unsigned int ABSSrcReg = MI->getOperand(1).getReg();
7887 unsigned int ABSDstReg = MI->getOperand(0).getReg();
7888 bool isThumb2 = Subtarget->isThumb2();
7889 MachineRegisterInfo &MRI = Fn->getRegInfo();
7890 // In Thumb mode S must not be specified if source register is the SP or
7891 // PC and if destination register is the SP, so restrict register class
7892 unsigned NewRsbDstReg = MRI.createVirtualRegister(isThumb2 ?
7893 (const TargetRegisterClass*)&ARM::rGPRRegClass :
7894 (const TargetRegisterClass*)&ARM::GPRRegClass);
7896 // Transfer the remainder of BB and its successor edges to sinkMBB.
7897 SinkBB->splice(SinkBB->begin(), BB,
7898 llvm::next(MachineBasicBlock::iterator(MI)),
7900 SinkBB->transferSuccessorsAndUpdatePHIs(BB);
7902 BB->addSuccessor(RSBBB);
7903 BB->addSuccessor(SinkBB);
7905 // fall through to SinkMBB
7906 RSBBB->addSuccessor(SinkBB);
7908 // insert a cmp at the end of BB
7909 AddDefaultPred(BuildMI(BB, dl,
7910 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
7911 .addReg(ABSSrcReg).addImm(0));
7913 // insert a bcc with opposite CC to ARMCC::MI at the end of BB
7915 TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)).addMBB(SinkBB)
7916 .addImm(ARMCC::getOppositeCondition(ARMCC::MI)).addReg(ARM::CPSR);
7918 // insert rsbri in RSBBB
7919 // Note: BCC and rsbri will be converted into predicated rsbmi
7920 // by if-conversion pass
7921 BuildMI(*RSBBB, RSBBB->begin(), dl,
7922 TII->get(isThumb2 ? ARM::t2RSBri : ARM::RSBri), NewRsbDstReg)
7923 .addReg(ABSSrcReg, RegState::Kill)
7924 .addImm(0).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
7926 // insert PHI in SinkBB,
7927 // reuse ABSDstReg to not change uses of ABS instruction
7928 BuildMI(*SinkBB, SinkBB->begin(), dl,
7929 TII->get(ARM::PHI), ABSDstReg)
7930 .addReg(NewRsbDstReg).addMBB(RSBBB)
7931 .addReg(ABSSrcReg).addMBB(BB);
7933 // remove ABS instruction
7934 MI->eraseFromParent();
7936 // return last added BB
7939 case ARM::COPY_STRUCT_BYVAL_I32:
7941 return EmitStructByval(MI, BB);
7945 void ARMTargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
7946 SDNode *Node) const {
7947 if (!MI->hasPostISelHook()) {
7948 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
7949 "Pseudo flag-setting opcodes must be marked with 'hasPostISelHook'");
7953 const MCInstrDesc *MCID = &MI->getDesc();
7954 // Adjust potentially 's' setting instructions after isel, i.e. ADC, SBC, RSB,
7955 // RSC. Coming out of isel, they have an implicit CPSR def, but the optional
7956 // operand is still set to noreg. If needed, set the optional operand's
7957 // register to CPSR, and remove the redundant implicit def.
7959 // e.g. ADCS (..., CPSR<imp-def>) -> ADC (... opt:CPSR<def>).
7961 // Rename pseudo opcodes.
7962 unsigned NewOpc = convertAddSubFlagsOpcode(MI->getOpcode());
7964 const ARMBaseInstrInfo *TII =
7965 static_cast<const ARMBaseInstrInfo*>(getTargetMachine().getInstrInfo());
7966 MCID = &TII->get(NewOpc);
7968 assert(MCID->getNumOperands() == MI->getDesc().getNumOperands() + 1 &&
7969 "converted opcode should be the same except for cc_out");
7973 // Add the optional cc_out operand
7974 MI->addOperand(MachineOperand::CreateReg(0, /*isDef=*/true));
7976 unsigned ccOutIdx = MCID->getNumOperands() - 1;
7978 // Any ARM instruction that sets the 's' bit should specify an optional
7979 // "cc_out" operand in the last operand position.
7980 if (!MI->hasOptionalDef() || !MCID->OpInfo[ccOutIdx].isOptionalDef()) {
7981 assert(!NewOpc && "Optional cc_out operand required");
7984 // Look for an implicit def of CPSR added by MachineInstr ctor. Remove it
7985 // since we already have an optional CPSR def.
7986 bool definesCPSR = false;
7987 bool deadCPSR = false;
7988 for (unsigned i = MCID->getNumOperands(), e = MI->getNumOperands();
7990 const MachineOperand &MO = MI->getOperand(i);
7991 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) {
7995 MI->RemoveOperand(i);
8000 assert(!NewOpc && "Optional cc_out operand required");
8003 assert(deadCPSR == !Node->hasAnyUseOfValue(1) && "inconsistent dead flag");
8005 assert(!MI->getOperand(ccOutIdx).getReg() &&
8006 "expect uninitialized optional cc_out operand");
8010 // If this instruction was defined with an optional CPSR def and its dag node
8011 // had a live implicit CPSR def, then activate the optional CPSR def.
8012 MachineOperand &MO = MI->getOperand(ccOutIdx);
8013 MO.setReg(ARM::CPSR);
8017 //===----------------------------------------------------------------------===//
8018 // ARM Optimization Hooks
8019 //===----------------------------------------------------------------------===//
8021 // Helper function that checks if N is a null or all ones constant.
8022 static inline bool isZeroOrAllOnes(SDValue N, bool AllOnes) {
8023 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
8026 return AllOnes ? C->isAllOnesValue() : C->isNullValue();
8029 // Return true if N is conditionally 0 or all ones.
8030 // Detects these expressions where cc is an i1 value:
8032 // (select cc 0, y) [AllOnes=0]
8033 // (select cc y, 0) [AllOnes=0]
8034 // (zext cc) [AllOnes=0]
8035 // (sext cc) [AllOnes=0/1]
8036 // (select cc -1, y) [AllOnes=1]
8037 // (select cc y, -1) [AllOnes=1]
8039 // Invert is set when N is the null/all ones constant when CC is false.
8040 // OtherOp is set to the alternative value of N.
8041 static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes,
8042 SDValue &CC, bool &Invert,
8044 SelectionDAG &DAG) {
8045 switch (N->getOpcode()) {
8046 default: return false;
8048 CC = N->getOperand(0);
8049 SDValue N1 = N->getOperand(1);
8050 SDValue N2 = N->getOperand(2);
8051 if (isZeroOrAllOnes(N1, AllOnes)) {
8056 if (isZeroOrAllOnes(N2, AllOnes)) {
8063 case ISD::ZERO_EXTEND:
8064 // (zext cc) can never be the all ones value.
8068 case ISD::SIGN_EXTEND: {
8069 EVT VT = N->getValueType(0);
8070 CC = N->getOperand(0);
8071 if (CC.getValueType() != MVT::i1)
8075 // When looking for an AllOnes constant, N is an sext, and the 'other'
8077 OtherOp = DAG.getConstant(0, VT);
8078 else if (N->getOpcode() == ISD::ZERO_EXTEND)
8079 // When looking for a 0 constant, N can be zext or sext.
8080 OtherOp = DAG.getConstant(1, VT);
8082 OtherOp = DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT);
8088 // Combine a constant select operand into its use:
8090 // (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
8091 // (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
8092 // (and (select cc, -1, c), x) -> (select cc, x, (and, x, c)) [AllOnes=1]
8093 // (or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
8094 // (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
8096 // The transform is rejected if the select doesn't have a constant operand that
8097 // is null, or all ones when AllOnes is set.
8099 // Also recognize sext/zext from i1:
8101 // (add (zext cc), x) -> (select cc (add x, 1), x)
8102 // (add (sext cc), x) -> (select cc (add x, -1), x)
8104 // These transformations eventually create predicated instructions.
8106 // @param N The node to transform.
8107 // @param Slct The N operand that is a select.
8108 // @param OtherOp The other N operand (x above).
8109 // @param DCI Context.
8110 // @param AllOnes Require the select constant to be all ones instead of null.
8111 // @returns The new node, or SDValue() on failure.
8113 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
8114 TargetLowering::DAGCombinerInfo &DCI,
8115 bool AllOnes = false) {
8116 SelectionDAG &DAG = DCI.DAG;
8117 EVT VT = N->getValueType(0);
8118 SDValue NonConstantVal;
8121 if (!isConditionalZeroOrAllOnes(Slct.getNode(), AllOnes, CCOp, SwapSelectOps,
8122 NonConstantVal, DAG))
8125 // Slct is now know to be the desired identity constant when CC is true.
8126 SDValue TrueVal = OtherOp;
8127 SDValue FalseVal = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
8128 OtherOp, NonConstantVal);
8129 // Unless SwapSelectOps says CC should be false.
8131 std::swap(TrueVal, FalseVal);
8133 return DAG.getNode(ISD::SELECT, SDLoc(N), VT,
8134 CCOp, TrueVal, FalseVal);
8137 // Attempt combineSelectAndUse on each operand of a commutative operator N.
8139 SDValue combineSelectAndUseCommutative(SDNode *N, bool AllOnes,
8140 TargetLowering::DAGCombinerInfo &DCI) {
8141 SDValue N0 = N->getOperand(0);
8142 SDValue N1 = N->getOperand(1);
8143 if (N0.getNode()->hasOneUse()) {
8144 SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes);
8145 if (Result.getNode())
8148 if (N1.getNode()->hasOneUse()) {
8149 SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes);
8150 if (Result.getNode())
8156 // AddCombineToVPADDL- For pair-wise add on neon, use the vpaddl instruction
8157 // (only after legalization).
8158 static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1,
8159 TargetLowering::DAGCombinerInfo &DCI,
8160 const ARMSubtarget *Subtarget) {
8162 // Only perform optimization if after legalize, and if NEON is available. We
8163 // also expected both operands to be BUILD_VECTORs.
8164 if (DCI.isBeforeLegalize() || !Subtarget->hasNEON()
8165 || N0.getOpcode() != ISD::BUILD_VECTOR
8166 || N1.getOpcode() != ISD::BUILD_VECTOR)
8169 // Check output type since VPADDL operand elements can only be 8, 16, or 32.
8170 EVT VT = N->getValueType(0);
8171 if (!VT.isInteger() || VT.getVectorElementType() == MVT::i64)
8174 // Check that the vector operands are of the right form.
8175 // N0 and N1 are BUILD_VECTOR nodes with N number of EXTRACT_VECTOR
8176 // operands, where N is the size of the formed vector.
8177 // Each EXTRACT_VECTOR should have the same input vector and odd or even
8178 // index such that we have a pair wise add pattern.
8180 // Grab the vector that all EXTRACT_VECTOR nodes should be referencing.
8181 if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
8183 SDValue Vec = N0->getOperand(0)->getOperand(0);
8184 SDNode *V = Vec.getNode();
8185 unsigned nextIndex = 0;
8187 // For each operands to the ADD which are BUILD_VECTORs,
8188 // check to see if each of their operands are an EXTRACT_VECTOR with
8189 // the same vector and appropriate index.
8190 for (unsigned i = 0, e = N0->getNumOperands(); i != e; ++i) {
8191 if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT
8192 && N1->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
8194 SDValue ExtVec0 = N0->getOperand(i);
8195 SDValue ExtVec1 = N1->getOperand(i);
8197 // First operand is the vector, verify its the same.
8198 if (V != ExtVec0->getOperand(0).getNode() ||
8199 V != ExtVec1->getOperand(0).getNode())
8202 // Second is the constant, verify its correct.
8203 ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(ExtVec0->getOperand(1));
8204 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(ExtVec1->getOperand(1));
8206 // For the constant, we want to see all the even or all the odd.
8207 if (!C0 || !C1 || C0->getZExtValue() != nextIndex
8208 || C1->getZExtValue() != nextIndex+1)
8217 // Create VPADDL node.
8218 SelectionDAG &DAG = DCI.DAG;
8219 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8221 // Build operand list.
8222 SmallVector<SDValue, 8> Ops;
8223 Ops.push_back(DAG.getConstant(Intrinsic::arm_neon_vpaddls,
8224 TLI.getPointerTy()));
8226 // Input is the vector.
8229 // Get widened type and narrowed type.
8231 unsigned numElem = VT.getVectorNumElements();
8232 switch (VT.getVectorElementType().getSimpleVT().SimpleTy) {
8233 case MVT::i8: widenType = MVT::getVectorVT(MVT::i16, numElem); break;
8234 case MVT::i16: widenType = MVT::getVectorVT(MVT::i32, numElem); break;
8235 case MVT::i32: widenType = MVT::getVectorVT(MVT::i64, numElem); break;
8237 llvm_unreachable("Invalid vector element type for padd optimization.");
8240 SDValue tmp = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N),
8241 widenType, &Ops[0], Ops.size());
8242 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, tmp);
8245 static SDValue findMUL_LOHI(SDValue V) {
8246 if (V->getOpcode() == ISD::UMUL_LOHI ||
8247 V->getOpcode() == ISD::SMUL_LOHI)
8252 static SDValue AddCombineTo64bitMLAL(SDNode *AddcNode,
8253 TargetLowering::DAGCombinerInfo &DCI,
8254 const ARMSubtarget *Subtarget) {
8256 if (Subtarget->isThumb1Only()) return SDValue();
8258 // Only perform the checks after legalize when the pattern is available.
8259 if (DCI.isBeforeLegalize()) return SDValue();
8261 // Look for multiply add opportunities.
8262 // The pattern is a ISD::UMUL_LOHI followed by two add nodes, where
8263 // each add nodes consumes a value from ISD::UMUL_LOHI and there is
8264 // a glue link from the first add to the second add.
8265 // If we find this pattern, we can replace the U/SMUL_LOHI, ADDC, and ADDE by
8266 // a S/UMLAL instruction.
8269 // \ / \ [no multiline comment]
8275 assert(AddcNode->getOpcode() == ISD::ADDC && "Expect an ADDC");
8276 SDValue AddcOp0 = AddcNode->getOperand(0);
8277 SDValue AddcOp1 = AddcNode->getOperand(1);
8279 // Check if the two operands are from the same mul_lohi node.
8280 if (AddcOp0.getNode() == AddcOp1.getNode())
8283 assert(AddcNode->getNumValues() == 2 &&
8284 AddcNode->getValueType(0) == MVT::i32 &&
8285 "Expect ADDC with two result values. First: i32");
8287 // Check that we have a glued ADDC node.
8288 if (AddcNode->getValueType(1) != MVT::Glue)
8291 // Check that the ADDC adds the low result of the S/UMUL_LOHI.
8292 if (AddcOp0->getOpcode() != ISD::UMUL_LOHI &&
8293 AddcOp0->getOpcode() != ISD::SMUL_LOHI &&
8294 AddcOp1->getOpcode() != ISD::UMUL_LOHI &&
8295 AddcOp1->getOpcode() != ISD::SMUL_LOHI)
8298 // Look for the glued ADDE.
8299 SDNode* AddeNode = AddcNode->getGluedUser();
8300 if (AddeNode == NULL)
8303 // Make sure it is really an ADDE.
8304 if (AddeNode->getOpcode() != ISD::ADDE)
8307 assert(AddeNode->getNumOperands() == 3 &&
8308 AddeNode->getOperand(2).getValueType() == MVT::Glue &&
8309 "ADDE node has the wrong inputs");
8311 // Check for the triangle shape.
8312 SDValue AddeOp0 = AddeNode->getOperand(0);
8313 SDValue AddeOp1 = AddeNode->getOperand(1);
8315 // Make sure that the ADDE operands are not coming from the same node.
8316 if (AddeOp0.getNode() == AddeOp1.getNode())
8319 // Find the MUL_LOHI node walking up ADDE's operands.
8320 bool IsLeftOperandMUL = false;
8321 SDValue MULOp = findMUL_LOHI(AddeOp0);
8322 if (MULOp == SDValue())
8323 MULOp = findMUL_LOHI(AddeOp1);
8325 IsLeftOperandMUL = true;
8326 if (MULOp == SDValue())
8329 // Figure out the right opcode.
8330 unsigned Opc = MULOp->getOpcode();
8331 unsigned FinalOpc = (Opc == ISD::SMUL_LOHI) ? ARMISD::SMLAL : ARMISD::UMLAL;
8333 // Figure out the high and low input values to the MLAL node.
8334 SDValue* HiMul = &MULOp;
8335 SDValue* HiAdd = NULL;
8336 SDValue* LoMul = NULL;
8337 SDValue* LowAdd = NULL;
8339 if (IsLeftOperandMUL)
8345 if (AddcOp0->getOpcode() == Opc) {
8349 if (AddcOp1->getOpcode() == Opc) {
8357 if (LoMul->getNode() != HiMul->getNode())
8360 // Create the merged node.
8361 SelectionDAG &DAG = DCI.DAG;
8363 // Build operand list.
8364 SmallVector<SDValue, 8> Ops;
8365 Ops.push_back(LoMul->getOperand(0));
8366 Ops.push_back(LoMul->getOperand(1));
8367 Ops.push_back(*LowAdd);
8368 Ops.push_back(*HiAdd);
8370 SDValue MLALNode = DAG.getNode(FinalOpc, SDLoc(AddcNode),
8371 DAG.getVTList(MVT::i32, MVT::i32),
8372 &Ops[0], Ops.size());
8374 // Replace the ADDs' nodes uses by the MLA node's values.
8375 SDValue HiMLALResult(MLALNode.getNode(), 1);
8376 DAG.ReplaceAllUsesOfValueWith(SDValue(AddeNode, 0), HiMLALResult);
8378 SDValue LoMLALResult(MLALNode.getNode(), 0);
8379 DAG.ReplaceAllUsesOfValueWith(SDValue(AddcNode, 0), LoMLALResult);
8381 // Return original node to notify the driver to stop replacing.
8382 SDValue resNode(AddcNode, 0);
8386 /// PerformADDCCombine - Target-specific dag combine transform from
8387 /// ISD::ADDC, ISD::ADDE, and ISD::MUL_LOHI to MLAL.
8388 static SDValue PerformADDCCombine(SDNode *N,
8389 TargetLowering::DAGCombinerInfo &DCI,
8390 const ARMSubtarget *Subtarget) {
8392 return AddCombineTo64bitMLAL(N, DCI, Subtarget);
8396 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
8397 /// operands N0 and N1. This is a helper for PerformADDCombine that is
8398 /// called with the default operands, and if that fails, with commuted
8400 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
8401 TargetLowering::DAGCombinerInfo &DCI,
8402 const ARMSubtarget *Subtarget){
8404 // Attempt to create vpaddl for this add.
8405 SDValue Result = AddCombineToVPADDL(N, N0, N1, DCI, Subtarget);
8406 if (Result.getNode())
8409 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
8410 if (N0.getNode()->hasOneUse()) {
8411 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
8412 if (Result.getNode()) return Result;
8417 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
8419 static SDValue PerformADDCombine(SDNode *N,
8420 TargetLowering::DAGCombinerInfo &DCI,
8421 const ARMSubtarget *Subtarget) {
8422 SDValue N0 = N->getOperand(0);
8423 SDValue N1 = N->getOperand(1);
8425 // First try with the default operand order.
8426 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget);
8427 if (Result.getNode())
8430 // If that didn't work, try again with the operands commuted.
8431 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget);
8434 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
8436 static SDValue PerformSUBCombine(SDNode *N,
8437 TargetLowering::DAGCombinerInfo &DCI) {
8438 SDValue N0 = N->getOperand(0);
8439 SDValue N1 = N->getOperand(1);
8441 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
8442 if (N1.getNode()->hasOneUse()) {
8443 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
8444 if (Result.getNode()) return Result;
8450 /// PerformVMULCombine
8451 /// Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the
8452 /// special multiplier accumulator forwarding.
8458 // However, for (A + B) * (A + B),
8465 static SDValue PerformVMULCombine(SDNode *N,
8466 TargetLowering::DAGCombinerInfo &DCI,
8467 const ARMSubtarget *Subtarget) {
8468 if (!Subtarget->hasVMLxForwarding())
8471 SelectionDAG &DAG = DCI.DAG;
8472 SDValue N0 = N->getOperand(0);
8473 SDValue N1 = N->getOperand(1);
8474 unsigned Opcode = N0.getOpcode();
8475 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
8476 Opcode != ISD::FADD && Opcode != ISD::FSUB) {
8477 Opcode = N1.getOpcode();
8478 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
8479 Opcode != ISD::FADD && Opcode != ISD::FSUB)
8487 EVT VT = N->getValueType(0);
8489 SDValue N00 = N0->getOperand(0);
8490 SDValue N01 = N0->getOperand(1);
8491 return DAG.getNode(Opcode, DL, VT,
8492 DAG.getNode(ISD::MUL, DL, VT, N00, N1),
8493 DAG.getNode(ISD::MUL, DL, VT, N01, N1));
8496 static SDValue PerformMULCombine(SDNode *N,
8497 TargetLowering::DAGCombinerInfo &DCI,
8498 const ARMSubtarget *Subtarget) {
8499 SelectionDAG &DAG = DCI.DAG;
8501 if (Subtarget->isThumb1Only())
8504 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
8507 EVT VT = N->getValueType(0);
8508 if (VT.is64BitVector() || VT.is128BitVector())
8509 return PerformVMULCombine(N, DCI, Subtarget);
8513 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
8517 int64_t MulAmt = C->getSExtValue();
8518 unsigned ShiftAmt = countTrailingZeros<uint64_t>(MulAmt);
8520 ShiftAmt = ShiftAmt & (32 - 1);
8521 SDValue V = N->getOperand(0);
8525 MulAmt >>= ShiftAmt;
8528 if (isPowerOf2_32(MulAmt - 1)) {
8529 // (mul x, 2^N + 1) => (add (shl x, N), x)
8530 Res = DAG.getNode(ISD::ADD, DL, VT,
8532 DAG.getNode(ISD::SHL, DL, VT,
8534 DAG.getConstant(Log2_32(MulAmt - 1),
8536 } else if (isPowerOf2_32(MulAmt + 1)) {
8537 // (mul x, 2^N - 1) => (sub (shl x, N), x)
8538 Res = DAG.getNode(ISD::SUB, DL, VT,
8539 DAG.getNode(ISD::SHL, DL, VT,
8541 DAG.getConstant(Log2_32(MulAmt + 1),
8547 uint64_t MulAmtAbs = -MulAmt;
8548 if (isPowerOf2_32(MulAmtAbs + 1)) {
8549 // (mul x, -(2^N - 1)) => (sub x, (shl x, N))
8550 Res = DAG.getNode(ISD::SUB, DL, VT,
8552 DAG.getNode(ISD::SHL, DL, VT,
8554 DAG.getConstant(Log2_32(MulAmtAbs + 1),
8556 } else if (isPowerOf2_32(MulAmtAbs - 1)) {
8557 // (mul x, -(2^N + 1)) => - (add (shl x, N), x)
8558 Res = DAG.getNode(ISD::ADD, DL, VT,
8560 DAG.getNode(ISD::SHL, DL, VT,
8562 DAG.getConstant(Log2_32(MulAmtAbs-1),
8564 Res = DAG.getNode(ISD::SUB, DL, VT,
8565 DAG.getConstant(0, MVT::i32),Res);
8572 Res = DAG.getNode(ISD::SHL, DL, VT,
8573 Res, DAG.getConstant(ShiftAmt, MVT::i32));
8575 // Do not add new nodes to DAG combiner worklist.
8576 DCI.CombineTo(N, Res, false);
8580 static SDValue PerformANDCombine(SDNode *N,
8581 TargetLowering::DAGCombinerInfo &DCI,
8582 const ARMSubtarget *Subtarget) {
8584 // Attempt to use immediate-form VBIC
8585 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
8587 EVT VT = N->getValueType(0);
8588 SelectionDAG &DAG = DCI.DAG;
8590 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
8593 APInt SplatBits, SplatUndef;
8594 unsigned SplatBitSize;
8597 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
8598 if (SplatBitSize <= 64) {
8600 SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(),
8601 SplatUndef.getZExtValue(), SplatBitSize,
8602 DAG, VbicVT, VT.is128BitVector(),
8604 if (Val.getNode()) {
8606 DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0));
8607 SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val);
8608 return DAG.getNode(ISD::BITCAST, dl, VT, Vbic);
8613 if (!Subtarget->isThumb1Only()) {
8614 // fold (and (select cc, -1, c), x) -> (select cc, x, (and, x, c))
8615 SDValue Result = combineSelectAndUseCommutative(N, true, DCI);
8616 if (Result.getNode())
8623 /// PerformORCombine - Target-specific dag combine xforms for ISD::OR
8624 static SDValue PerformORCombine(SDNode *N,
8625 TargetLowering::DAGCombinerInfo &DCI,
8626 const ARMSubtarget *Subtarget) {
8627 // Attempt to use immediate-form VORR
8628 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
8630 EVT VT = N->getValueType(0);
8631 SelectionDAG &DAG = DCI.DAG;
8633 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
8636 APInt SplatBits, SplatUndef;
8637 unsigned SplatBitSize;
8639 if (BVN && Subtarget->hasNEON() &&
8640 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
8641 if (SplatBitSize <= 64) {
8643 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
8644 SplatUndef.getZExtValue(), SplatBitSize,
8645 DAG, VorrVT, VT.is128BitVector(),
8647 if (Val.getNode()) {
8649 DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0));
8650 SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val);
8651 return DAG.getNode(ISD::BITCAST, dl, VT, Vorr);
8656 if (!Subtarget->isThumb1Only()) {
8657 // fold (or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
8658 SDValue Result = combineSelectAndUseCommutative(N, false, DCI);
8659 if (Result.getNode())
8663 // The code below optimizes (or (and X, Y), Z).
8664 // The AND operand needs to have a single user to make these optimizations
8666 SDValue N0 = N->getOperand(0);
8667 if (N0.getOpcode() != ISD::AND || !N0.hasOneUse())
8669 SDValue N1 = N->getOperand(1);
8671 // (or (and B, A), (and C, ~A)) => (VBSL A, B, C) when A is a constant.
8672 if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() &&
8673 DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
8675 unsigned SplatBitSize;
8678 APInt SplatBits0, SplatBits1;
8679 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1));
8680 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(1));
8681 // Ensure that the second operand of both ands are constants
8682 if (BVN0 && BVN0->isConstantSplat(SplatBits0, SplatUndef, SplatBitSize,
8683 HasAnyUndefs) && !HasAnyUndefs) {
8684 if (BVN1 && BVN1->isConstantSplat(SplatBits1, SplatUndef, SplatBitSize,
8685 HasAnyUndefs) && !HasAnyUndefs) {
8686 // Ensure that the bit width of the constants are the same and that
8687 // the splat arguments are logical inverses as per the pattern we
8688 // are trying to simplify.
8689 if (SplatBits0.getBitWidth() == SplatBits1.getBitWidth() &&
8690 SplatBits0 == ~SplatBits1) {
8691 // Canonicalize the vector type to make instruction selection
8693 EVT CanonicalVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
8694 SDValue Result = DAG.getNode(ARMISD::VBSL, dl, CanonicalVT,
8698 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
8704 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when
8707 // BFI is only available on V6T2+
8708 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops())
8712 // 1) or (and A, mask), val => ARMbfi A, val, mask
8713 // iff (val & mask) == val
8715 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
8716 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2)
8717 // && mask == ~mask2
8718 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2)
8719 // && ~mask == mask2
8720 // (i.e., copy a bitfield value into another bitfield of the same width)
8725 SDValue N00 = N0.getOperand(0);
8727 // The value and the mask need to be constants so we can verify this is
8728 // actually a bitfield set. If the mask is 0xffff, we can do better
8729 // via a movt instruction, so don't use BFI in that case.
8730 SDValue MaskOp = N0.getOperand(1);
8731 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(MaskOp);
8734 unsigned Mask = MaskC->getZExtValue();
8738 // Case (1): or (and A, mask), val => ARMbfi A, val, mask
8739 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
8741 unsigned Val = N1C->getZExtValue();
8742 if ((Val & ~Mask) != Val)
8745 if (ARM::isBitFieldInvertedMask(Mask)) {
8746 Val >>= countTrailingZeros(~Mask);
8748 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00,
8749 DAG.getConstant(Val, MVT::i32),
8750 DAG.getConstant(Mask, MVT::i32));
8752 // Do not add new nodes to DAG combiner worklist.
8753 DCI.CombineTo(N, Res, false);
8756 } else if (N1.getOpcode() == ISD::AND) {
8757 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
8758 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
8761 unsigned Mask2 = N11C->getZExtValue();
8763 // Mask and ~Mask2 (or reverse) must be equivalent for the BFI pattern
8765 if (ARM::isBitFieldInvertedMask(Mask) &&
8767 // The pack halfword instruction works better for masks that fit it,
8768 // so use that when it's available.
8769 if (Subtarget->hasT2ExtractPack() &&
8770 (Mask == 0xffff || Mask == 0xffff0000))
8773 unsigned amt = countTrailingZeros(Mask2);
8774 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
8775 DAG.getConstant(amt, MVT::i32));
8776 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res,
8777 DAG.getConstant(Mask, MVT::i32));
8778 // Do not add new nodes to DAG combiner worklist.
8779 DCI.CombineTo(N, Res, false);
8781 } else if (ARM::isBitFieldInvertedMask(~Mask) &&
8783 // The pack halfword instruction works better for masks that fit it,
8784 // so use that when it's available.
8785 if (Subtarget->hasT2ExtractPack() &&
8786 (Mask2 == 0xffff || Mask2 == 0xffff0000))
8789 unsigned lsb = countTrailingZeros(Mask);
8790 Res = DAG.getNode(ISD::SRL, DL, VT, N00,
8791 DAG.getConstant(lsb, MVT::i32));
8792 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
8793 DAG.getConstant(Mask2, MVT::i32));
8794 // Do not add new nodes to DAG combiner worklist.
8795 DCI.CombineTo(N, Res, false);
8800 if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) &&
8801 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) &&
8802 ARM::isBitFieldInvertedMask(~Mask)) {
8803 // Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask
8804 // where lsb(mask) == #shamt and masked bits of B are known zero.
8805 SDValue ShAmt = N00.getOperand(1);
8806 unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue();
8807 unsigned LSB = countTrailingZeros(Mask);
8811 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0),
8812 DAG.getConstant(~Mask, MVT::i32));
8814 // Do not add new nodes to DAG combiner worklist.
8815 DCI.CombineTo(N, Res, false);
8821 static SDValue PerformXORCombine(SDNode *N,
8822 TargetLowering::DAGCombinerInfo &DCI,
8823 const ARMSubtarget *Subtarget) {
8824 EVT VT = N->getValueType(0);
8825 SelectionDAG &DAG = DCI.DAG;
8827 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
8830 if (!Subtarget->isThumb1Only()) {
8831 // fold (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
8832 SDValue Result = combineSelectAndUseCommutative(N, false, DCI);
8833 if (Result.getNode())
8840 /// PerformBFICombine - (bfi A, (and B, Mask1), Mask2) -> (bfi A, B, Mask2) iff
8841 /// the bits being cleared by the AND are not demanded by the BFI.
8842 static SDValue PerformBFICombine(SDNode *N,
8843 TargetLowering::DAGCombinerInfo &DCI) {
8844 SDValue N1 = N->getOperand(1);
8845 if (N1.getOpcode() == ISD::AND) {
8846 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
8849 unsigned InvMask = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
8850 unsigned LSB = countTrailingZeros(~InvMask);
8851 unsigned Width = (32 - countLeadingZeros(~InvMask)) - LSB;
8852 unsigned Mask = (1 << Width)-1;
8853 unsigned Mask2 = N11C->getZExtValue();
8854 if ((Mask & (~Mask2)) == 0)
8855 return DCI.DAG.getNode(ARMISD::BFI, SDLoc(N), N->getValueType(0),
8856 N->getOperand(0), N1.getOperand(0),
8862 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
8863 /// ARMISD::VMOVRRD.
8864 static SDValue PerformVMOVRRDCombine(SDNode *N,
8865 TargetLowering::DAGCombinerInfo &DCI) {
8866 // vmovrrd(vmovdrr x, y) -> x,y
8867 SDValue InDouble = N->getOperand(0);
8868 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
8869 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
8871 // vmovrrd(load f64) -> (load i32), (load i32)
8872 SDNode *InNode = InDouble.getNode();
8873 if (ISD::isNormalLoad(InNode) && InNode->hasOneUse() &&
8874 InNode->getValueType(0) == MVT::f64 &&
8875 InNode->getOperand(1).getOpcode() == ISD::FrameIndex &&
8876 !cast<LoadSDNode>(InNode)->isVolatile()) {
8877 // TODO: Should this be done for non-FrameIndex operands?
8878 LoadSDNode *LD = cast<LoadSDNode>(InNode);
8880 SelectionDAG &DAG = DCI.DAG;
8882 SDValue BasePtr = LD->getBasePtr();
8883 SDValue NewLD1 = DAG.getLoad(MVT::i32, DL, LD->getChain(), BasePtr,
8884 LD->getPointerInfo(), LD->isVolatile(),
8885 LD->isNonTemporal(), LD->isInvariant(),
8886 LD->getAlignment());
8888 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
8889 DAG.getConstant(4, MVT::i32));
8890 SDValue NewLD2 = DAG.getLoad(MVT::i32, DL, NewLD1.getValue(1), OffsetPtr,
8891 LD->getPointerInfo(), LD->isVolatile(),
8892 LD->isNonTemporal(), LD->isInvariant(),
8893 std::min(4U, LD->getAlignment() / 2));
8895 DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), NewLD2.getValue(1));
8896 SDValue Result = DCI.CombineTo(N, NewLD1, NewLD2);
8897 DCI.RemoveFromWorklist(LD);
8905 /// PerformVMOVDRRCombine - Target-specific dag combine xforms for
8906 /// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands.
8907 static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) {
8908 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X)
8909 SDValue Op0 = N->getOperand(0);
8910 SDValue Op1 = N->getOperand(1);
8911 if (Op0.getOpcode() == ISD::BITCAST)
8912 Op0 = Op0.getOperand(0);
8913 if (Op1.getOpcode() == ISD::BITCAST)
8914 Op1 = Op1.getOperand(0);
8915 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
8916 Op0.getNode() == Op1.getNode() &&
8917 Op0.getResNo() == 0 && Op1.getResNo() == 1)
8918 return DAG.getNode(ISD::BITCAST, SDLoc(N),
8919 N->getValueType(0), Op0.getOperand(0));
8923 /// PerformSTORECombine - Target-specific dag combine xforms for
8925 static SDValue PerformSTORECombine(SDNode *N,
8926 TargetLowering::DAGCombinerInfo &DCI) {
8927 StoreSDNode *St = cast<StoreSDNode>(N);
8928 if (St->isVolatile())
8931 // Optimize trunc store (of multiple scalars) to shuffle and store. First,
8932 // pack all of the elements in one place. Next, store to memory in fewer
8934 SDValue StVal = St->getValue();
8935 EVT VT = StVal.getValueType();
8936 if (St->isTruncatingStore() && VT.isVector()) {
8937 SelectionDAG &DAG = DCI.DAG;
8938 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8939 EVT StVT = St->getMemoryVT();
8940 unsigned NumElems = VT.getVectorNumElements();
8941 assert(StVT != VT && "Cannot truncate to the same type");
8942 unsigned FromEltSz = VT.getVectorElementType().getSizeInBits();
8943 unsigned ToEltSz = StVT.getVectorElementType().getSizeInBits();
8945 // From, To sizes and ElemCount must be pow of two
8946 if (!isPowerOf2_32(NumElems * FromEltSz * ToEltSz)) return SDValue();
8948 // We are going to use the original vector elt for storing.
8949 // Accumulated smaller vector elements must be a multiple of the store size.
8950 if (0 != (NumElems * FromEltSz) % ToEltSz) return SDValue();
8952 unsigned SizeRatio = FromEltSz / ToEltSz;
8953 assert(SizeRatio * NumElems * ToEltSz == VT.getSizeInBits());
8955 // Create a type on which we perform the shuffle.
8956 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), StVT.getScalarType(),
8957 NumElems*SizeRatio);
8958 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
8961 SDValue WideVec = DAG.getNode(ISD::BITCAST, DL, WideVecVT, StVal);
8962 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
8963 for (unsigned i = 0; i < NumElems; ++i) ShuffleVec[i] = i * SizeRatio;
8965 // Can't shuffle using an illegal type.
8966 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
8968 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, DL, WideVec,
8969 DAG.getUNDEF(WideVec.getValueType()),
8971 // At this point all of the data is stored at the bottom of the
8972 // register. We now need to save it to mem.
8974 // Find the largest store unit
8975 MVT StoreType = MVT::i8;
8976 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
8977 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
8978 MVT Tp = (MVT::SimpleValueType)tp;
8979 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToEltSz)
8982 // Didn't find a legal store type.
8983 if (!TLI.isTypeLegal(StoreType))
8986 // Bitcast the original vector into a vector of store-size units
8987 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
8988 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
8989 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
8990 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, DL, StoreVecVT, Shuff);
8991 SmallVector<SDValue, 8> Chains;
8992 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
8993 TLI.getPointerTy());
8994 SDValue BasePtr = St->getBasePtr();
8996 // Perform one or more big stores into memory.
8997 unsigned E = (ToEltSz*NumElems)/StoreType.getSizeInBits();
8998 for (unsigned I = 0; I < E; I++) {
8999 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
9000 StoreType, ShuffWide,
9001 DAG.getIntPtrConstant(I));
9002 SDValue Ch = DAG.getStore(St->getChain(), DL, SubVec, BasePtr,
9003 St->getPointerInfo(), St->isVolatile(),
9004 St->isNonTemporal(), St->getAlignment());
9005 BasePtr = DAG.getNode(ISD::ADD, DL, BasePtr.getValueType(), BasePtr,
9007 Chains.push_back(Ch);
9009 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, &Chains[0],
9013 if (!ISD::isNormalStore(St))
9016 // Split a store of a VMOVDRR into two integer stores to avoid mixing NEON and
9017 // ARM stores of arguments in the same cache line.
9018 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR &&
9019 StVal.getNode()->hasOneUse()) {
9020 SelectionDAG &DAG = DCI.DAG;
9022 SDValue BasePtr = St->getBasePtr();
9023 SDValue NewST1 = DAG.getStore(St->getChain(), DL,
9024 StVal.getNode()->getOperand(0), BasePtr,
9025 St->getPointerInfo(), St->isVolatile(),
9026 St->isNonTemporal(), St->getAlignment());
9028 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
9029 DAG.getConstant(4, MVT::i32));
9030 return DAG.getStore(NewST1.getValue(0), DL, StVal.getNode()->getOperand(1),
9031 OffsetPtr, St->getPointerInfo(), St->isVolatile(),
9032 St->isNonTemporal(),
9033 std::min(4U, St->getAlignment() / 2));
9036 if (StVal.getValueType() != MVT::i64 ||
9037 StVal.getNode()->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
9040 // Bitcast an i64 store extracted from a vector to f64.
9041 // Otherwise, the i64 value will be legalized to a pair of i32 values.
9042 SelectionDAG &DAG = DCI.DAG;
9044 SDValue IntVec = StVal.getOperand(0);
9045 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
9046 IntVec.getValueType().getVectorNumElements());
9047 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec);
9048 SDValue ExtElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
9049 Vec, StVal.getOperand(1));
9051 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt);
9052 // Make the DAGCombiner fold the bitcasts.
9053 DCI.AddToWorklist(Vec.getNode());
9054 DCI.AddToWorklist(ExtElt.getNode());
9055 DCI.AddToWorklist(V.getNode());
9056 return DAG.getStore(St->getChain(), dl, V, St->getBasePtr(),
9057 St->getPointerInfo(), St->isVolatile(),
9058 St->isNonTemporal(), St->getAlignment(),
9062 /// hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node
9063 /// are normal, non-volatile loads. If so, it is profitable to bitcast an
9064 /// i64 vector to have f64 elements, since the value can then be loaded
9065 /// directly into a VFP register.
9066 static bool hasNormalLoadOperand(SDNode *N) {
9067 unsigned NumElts = N->getValueType(0).getVectorNumElements();
9068 for (unsigned i = 0; i < NumElts; ++i) {
9069 SDNode *Elt = N->getOperand(i).getNode();
9070 if (ISD::isNormalLoad(Elt) && !cast<LoadSDNode>(Elt)->isVolatile())
9076 /// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for
9077 /// ISD::BUILD_VECTOR.
9078 static SDValue PerformBUILD_VECTORCombine(SDNode *N,
9079 TargetLowering::DAGCombinerInfo &DCI){
9080 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X):
9081 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value
9082 // into a pair of GPRs, which is fine when the value is used as a scalar,
9083 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD.
9084 SelectionDAG &DAG = DCI.DAG;
9085 if (N->getNumOperands() == 2) {
9086 SDValue RV = PerformVMOVDRRCombine(N, DAG);
9091 // Load i64 elements as f64 values so that type legalization does not split
9092 // them up into i32 values.
9093 EVT VT = N->getValueType(0);
9094 if (VT.getVectorElementType() != MVT::i64 || !hasNormalLoadOperand(N))
9097 SmallVector<SDValue, 8> Ops;
9098 unsigned NumElts = VT.getVectorNumElements();
9099 for (unsigned i = 0; i < NumElts; ++i) {
9100 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(i));
9102 // Make the DAGCombiner fold the bitcast.
9103 DCI.AddToWorklist(V.getNode());
9105 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, NumElts);
9106 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, FloatVT, Ops.data(), NumElts);
9107 return DAG.getNode(ISD::BITCAST, dl, VT, BV);
9110 /// \brief Target-specific dag combine xforms for ARMISD::BUILD_VECTOR.
9112 PerformARMBUILD_VECTORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
9113 // ARMISD::BUILD_VECTOR is introduced when legalizing ISD::BUILD_VECTOR.
9114 // At that time, we may have inserted bitcasts from integer to float.
9115 // If these bitcasts have survived DAGCombine, change the lowering of this
9116 // BUILD_VECTOR in something more vector friendly, i.e., that does not
9117 // force to use floating point types.
9119 // Make sure we can change the type of the vector.
9120 // This is possible iff:
9121 // 1. The vector is only used in a bitcast to a integer type. I.e.,
9122 // 1.1. Vector is used only once.
9123 // 1.2. Use is a bit convert to an integer type.
9124 // 2. The size of its operands are 32-bits (64-bits are not legal).
9125 EVT VT = N->getValueType(0);
9126 EVT EltVT = VT.getVectorElementType();
9128 // Check 1.1. and 2.
9129 if (EltVT.getSizeInBits() != 32 || !N->hasOneUse())
9132 // By construction, the input type must be float.
9133 assert(EltVT == MVT::f32 && "Unexpected type!");
9136 SDNode *Use = *N->use_begin();
9137 if (Use->getOpcode() != ISD::BITCAST ||
9138 Use->getValueType(0).isFloatingPoint())
9141 // Check profitability.
9142 // Model is, if more than half of the relevant operands are bitcast from
9143 // i32, turn the build_vector into a sequence of insert_vector_elt.
9144 // Relevant operands are everything that is not statically
9145 // (i.e., at compile time) bitcasted.
9146 unsigned NumOfBitCastedElts = 0;
9147 unsigned NumElts = VT.getVectorNumElements();
9148 unsigned NumOfRelevantElts = NumElts;
9149 for (unsigned Idx = 0; Idx < NumElts; ++Idx) {
9150 SDValue Elt = N->getOperand(Idx);
9151 if (Elt->getOpcode() == ISD::BITCAST) {
9152 // Assume only bit cast to i32 will go away.
9153 if (Elt->getOperand(0).getValueType() == MVT::i32)
9154 ++NumOfBitCastedElts;
9155 } else if (Elt.getOpcode() == ISD::UNDEF || isa<ConstantSDNode>(Elt))
9156 // Constants are statically casted, thus do not count them as
9157 // relevant operands.
9158 --NumOfRelevantElts;
9161 // Check if more than half of the elements require a non-free bitcast.
9162 if (NumOfBitCastedElts <= NumOfRelevantElts / 2)
9165 SelectionDAG &DAG = DCI.DAG;
9166 // Create the new vector type.
9167 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
9168 // Check if the type is legal.
9169 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9170 if (!TLI.isTypeLegal(VecVT))
9174 // ARMISD::BUILD_VECTOR E1, E2, ..., EN.
9175 // => BITCAST INSERT_VECTOR_ELT
9176 // (INSERT_VECTOR_ELT (...), (BITCAST EN-1), N-1),
9178 SDValue Vec = DAG.getUNDEF(VecVT);
9180 for (unsigned Idx = 0 ; Idx < NumElts; ++Idx) {
9181 SDValue V = N->getOperand(Idx);
9182 if (V.getOpcode() == ISD::UNDEF)
9184 if (V.getOpcode() == ISD::BITCAST &&
9185 V->getOperand(0).getValueType() == MVT::i32)
9186 // Fold obvious case.
9187 V = V.getOperand(0);
9189 V = DAG.getNode(ISD::BITCAST, SDLoc(V), MVT::i32, V);
9190 // Make the DAGCombiner fold the bitcasts.
9191 DCI.AddToWorklist(V.getNode());
9193 SDValue LaneIdx = DAG.getConstant(Idx, MVT::i32);
9194 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecVT, Vec, V, LaneIdx);
9196 Vec = DAG.getNode(ISD::BITCAST, dl, VT, Vec);
9197 // Make the DAGCombiner fold the bitcasts.
9198 DCI.AddToWorklist(Vec.getNode());
9202 /// PerformInsertEltCombine - Target-specific dag combine xforms for
9203 /// ISD::INSERT_VECTOR_ELT.
9204 static SDValue PerformInsertEltCombine(SDNode *N,
9205 TargetLowering::DAGCombinerInfo &DCI) {
9206 // Bitcast an i64 load inserted into a vector to f64.
9207 // Otherwise, the i64 value will be legalized to a pair of i32 values.
9208 EVT VT = N->getValueType(0);
9209 SDNode *Elt = N->getOperand(1).getNode();
9210 if (VT.getVectorElementType() != MVT::i64 ||
9211 !ISD::isNormalLoad(Elt) || cast<LoadSDNode>(Elt)->isVolatile())
9214 SelectionDAG &DAG = DCI.DAG;
9216 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
9217 VT.getVectorNumElements());
9218 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, N->getOperand(0));
9219 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(1));
9220 // Make the DAGCombiner fold the bitcasts.
9221 DCI.AddToWorklist(Vec.getNode());
9222 DCI.AddToWorklist(V.getNode());
9223 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT,
9224 Vec, V, N->getOperand(2));
9225 return DAG.getNode(ISD::BITCAST, dl, VT, InsElt);
9228 /// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for
9229 /// ISD::VECTOR_SHUFFLE.
9230 static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) {
9231 // The LLVM shufflevector instruction does not require the shuffle mask
9232 // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does
9233 // have that requirement. When translating to ISD::VECTOR_SHUFFLE, if the
9234 // operands do not match the mask length, they are extended by concatenating
9235 // them with undef vectors. That is probably the right thing for other
9236 // targets, but for NEON it is better to concatenate two double-register
9237 // size vector operands into a single quad-register size vector. Do that
9238 // transformation here:
9239 // shuffle(concat(v1, undef), concat(v2, undef)) ->
9240 // shuffle(concat(v1, v2), undef)
9241 SDValue Op0 = N->getOperand(0);
9242 SDValue Op1 = N->getOperand(1);
9243 if (Op0.getOpcode() != ISD::CONCAT_VECTORS ||
9244 Op1.getOpcode() != ISD::CONCAT_VECTORS ||
9245 Op0.getNumOperands() != 2 ||
9246 Op1.getNumOperands() != 2)
9248 SDValue Concat0Op1 = Op0.getOperand(1);
9249 SDValue Concat1Op1 = Op1.getOperand(1);
9250 if (Concat0Op1.getOpcode() != ISD::UNDEF ||
9251 Concat1Op1.getOpcode() != ISD::UNDEF)
9253 // Skip the transformation if any of the types are illegal.
9254 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9255 EVT VT = N->getValueType(0);
9256 if (!TLI.isTypeLegal(VT) ||
9257 !TLI.isTypeLegal(Concat0Op1.getValueType()) ||
9258 !TLI.isTypeLegal(Concat1Op1.getValueType()))
9261 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT,
9262 Op0.getOperand(0), Op1.getOperand(0));
9263 // Translate the shuffle mask.
9264 SmallVector<int, 16> NewMask;
9265 unsigned NumElts = VT.getVectorNumElements();
9266 unsigned HalfElts = NumElts/2;
9267 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
9268 for (unsigned n = 0; n < NumElts; ++n) {
9269 int MaskElt = SVN->getMaskElt(n);
9271 if (MaskElt < (int)HalfElts)
9273 else if (MaskElt >= (int)NumElts && MaskElt < (int)(NumElts + HalfElts))
9274 NewElt = HalfElts + MaskElt - NumElts;
9275 NewMask.push_back(NewElt);
9277 return DAG.getVectorShuffle(VT, SDLoc(N), NewConcat,
9278 DAG.getUNDEF(VT), NewMask.data());
9281 /// CombineBaseUpdate - Target-specific DAG combine function for VLDDUP and
9282 /// NEON load/store intrinsics to merge base address updates.
9283 static SDValue CombineBaseUpdate(SDNode *N,
9284 TargetLowering::DAGCombinerInfo &DCI) {
9285 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
9288 SelectionDAG &DAG = DCI.DAG;
9289 bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID ||
9290 N->getOpcode() == ISD::INTRINSIC_W_CHAIN);
9291 unsigned AddrOpIdx = (isIntrinsic ? 2 : 1);
9292 SDValue Addr = N->getOperand(AddrOpIdx);
9294 // Search for a use of the address operand that is an increment.
9295 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
9296 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
9298 if (User->getOpcode() != ISD::ADD ||
9299 UI.getUse().getResNo() != Addr.getResNo())
9302 // Check that the add is independent of the load/store. Otherwise, folding
9303 // it would create a cycle.
9304 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
9307 // Find the new opcode for the updating load/store.
9309 bool isLaneOp = false;
9310 unsigned NewOpc = 0;
9311 unsigned NumVecs = 0;
9313 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
9315 default: llvm_unreachable("unexpected intrinsic for Neon base update");
9316 case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD;
9318 case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD;
9320 case Intrinsic::arm_neon_vld3: NewOpc = ARMISD::VLD3_UPD;
9322 case Intrinsic::arm_neon_vld4: NewOpc = ARMISD::VLD4_UPD;
9324 case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD;
9325 NumVecs = 2; isLaneOp = true; break;
9326 case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD;
9327 NumVecs = 3; isLaneOp = true; break;
9328 case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD;
9329 NumVecs = 4; isLaneOp = true; break;
9330 case Intrinsic::arm_neon_vst1: NewOpc = ARMISD::VST1_UPD;
9331 NumVecs = 1; isLoad = false; break;
9332 case Intrinsic::arm_neon_vst2: NewOpc = ARMISD::VST2_UPD;
9333 NumVecs = 2; isLoad = false; break;
9334 case Intrinsic::arm_neon_vst3: NewOpc = ARMISD::VST3_UPD;
9335 NumVecs = 3; isLoad = false; break;
9336 case Intrinsic::arm_neon_vst4: NewOpc = ARMISD::VST4_UPD;
9337 NumVecs = 4; isLoad = false; break;
9338 case Intrinsic::arm_neon_vst2lane: NewOpc = ARMISD::VST2LN_UPD;
9339 NumVecs = 2; isLoad = false; isLaneOp = true; break;
9340 case Intrinsic::arm_neon_vst3lane: NewOpc = ARMISD::VST3LN_UPD;
9341 NumVecs = 3; isLoad = false; isLaneOp = true; break;
9342 case Intrinsic::arm_neon_vst4lane: NewOpc = ARMISD::VST4LN_UPD;
9343 NumVecs = 4; isLoad = false; isLaneOp = true; break;
9347 switch (N->getOpcode()) {
9348 default: llvm_unreachable("unexpected opcode for Neon base update");
9349 case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break;
9350 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break;
9351 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break;
9355 // Find the size of memory referenced by the load/store.
9358 VecTy = N->getValueType(0);
9360 VecTy = N->getOperand(AddrOpIdx+1).getValueType();
9361 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
9363 NumBytes /= VecTy.getVectorNumElements();
9365 // If the increment is a constant, it must match the memory ref size.
9366 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
9367 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
9368 uint64_t IncVal = CInc->getZExtValue();
9369 if (IncVal != NumBytes)
9371 } else if (NumBytes >= 3 * 16) {
9372 // VLD3/4 and VST3/4 for 128-bit vectors are implemented with two
9373 // separate instructions that make it harder to use a non-constant update.
9377 // Create the new updating load/store node.
9379 unsigned NumResultVecs = (isLoad ? NumVecs : 0);
9381 for (n = 0; n < NumResultVecs; ++n)
9383 Tys[n++] = MVT::i32;
9384 Tys[n] = MVT::Other;
9385 SDVTList SDTys = DAG.getVTList(Tys, NumResultVecs+2);
9386 SmallVector<SDValue, 8> Ops;
9387 Ops.push_back(N->getOperand(0)); // incoming chain
9388 Ops.push_back(N->getOperand(AddrOpIdx));
9390 for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands(); ++i) {
9391 Ops.push_back(N->getOperand(i));
9393 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
9394 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys,
9395 Ops.data(), Ops.size(),
9396 MemInt->getMemoryVT(),
9397 MemInt->getMemOperand());
9400 std::vector<SDValue> NewResults;
9401 for (unsigned i = 0; i < NumResultVecs; ++i) {
9402 NewResults.push_back(SDValue(UpdN.getNode(), i));
9404 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs+1)); // chain
9405 DCI.CombineTo(N, NewResults);
9406 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
9413 /// CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a
9414 /// vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic
9415 /// are also VDUPLANEs. If so, combine them to a vldN-dup operation and
9417 static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
9418 SelectionDAG &DAG = DCI.DAG;
9419 EVT VT = N->getValueType(0);
9420 // vldN-dup instructions only support 64-bit vectors for N > 1.
9421 if (!VT.is64BitVector())
9424 // Check if the VDUPLANE operand is a vldN-dup intrinsic.
9425 SDNode *VLD = N->getOperand(0).getNode();
9426 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN)
9428 unsigned NumVecs = 0;
9429 unsigned NewOpc = 0;
9430 unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue();
9431 if (IntNo == Intrinsic::arm_neon_vld2lane) {
9433 NewOpc = ARMISD::VLD2DUP;
9434 } else if (IntNo == Intrinsic::arm_neon_vld3lane) {
9436 NewOpc = ARMISD::VLD3DUP;
9437 } else if (IntNo == Intrinsic::arm_neon_vld4lane) {
9439 NewOpc = ARMISD::VLD4DUP;
9444 // First check that all the vldN-lane uses are VDUPLANEs and that the lane
9445 // numbers match the load.
9446 unsigned VLDLaneNo =
9447 cast<ConstantSDNode>(VLD->getOperand(NumVecs+3))->getZExtValue();
9448 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
9450 // Ignore uses of the chain result.
9451 if (UI.getUse().getResNo() == NumVecs)
9454 if (User->getOpcode() != ARMISD::VDUPLANE ||
9455 VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue())
9459 // Create the vldN-dup node.
9462 for (n = 0; n < NumVecs; ++n)
9464 Tys[n] = MVT::Other;
9465 SDVTList SDTys = DAG.getVTList(Tys, NumVecs+1);
9466 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) };
9467 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD);
9468 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, SDLoc(VLD), SDTys,
9469 Ops, 2, VLDMemInt->getMemoryVT(),
9470 VLDMemInt->getMemOperand());
9473 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
9475 unsigned ResNo = UI.getUse().getResNo();
9476 // Ignore uses of the chain result.
9477 if (ResNo == NumVecs)
9480 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo));
9483 // Now the vldN-lane intrinsic is dead except for its chain result.
9484 // Update uses of the chain.
9485 std::vector<SDValue> VLDDupResults;
9486 for (unsigned n = 0; n < NumVecs; ++n)
9487 VLDDupResults.push_back(SDValue(VLDDup.getNode(), n));
9488 VLDDupResults.push_back(SDValue(VLDDup.getNode(), NumVecs));
9489 DCI.CombineTo(VLD, VLDDupResults);
9494 /// PerformVDUPLANECombine - Target-specific dag combine xforms for
9495 /// ARMISD::VDUPLANE.
9496 static SDValue PerformVDUPLANECombine(SDNode *N,
9497 TargetLowering::DAGCombinerInfo &DCI) {
9498 SDValue Op = N->getOperand(0);
9500 // If the source is a vldN-lane (N > 1) intrinsic, and all the other uses
9501 // of that intrinsic are also VDUPLANEs, combine them to a vldN-dup operation.
9502 if (CombineVLDDUP(N, DCI))
9503 return SDValue(N, 0);
9505 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
9506 // redundant. Ignore bit_converts for now; element sizes are checked below.
9507 while (Op.getOpcode() == ISD::BITCAST)
9508 Op = Op.getOperand(0);
9509 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
9512 // Make sure the VMOV element size is not bigger than the VDUPLANE elements.
9513 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits();
9514 // The canonical VMOV for a zero vector uses a 32-bit element size.
9515 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9517 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
9519 EVT VT = N->getValueType(0);
9520 if (EltSize > VT.getVectorElementType().getSizeInBits())
9523 return DCI.DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
9526 // isConstVecPow2 - Return true if each vector element is a power of 2, all
9527 // elements are the same constant, C, and Log2(C) ranges from 1 to 32.
9528 static bool isConstVecPow2(SDValue ConstVec, bool isSigned, uint64_t &C)
9532 for (unsigned I = 0, E = ConstVec.getValueType().getVectorNumElements();
9534 ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(ConstVec.getOperand(I));
9539 APFloat APF = C->getValueAPF();
9540 if (APF.convertToInteger(&cN, 64, isSigned, APFloat::rmTowardZero, &isExact)
9541 != APFloat::opOK || !isExact)
9544 c0 = (I == 0) ? cN : c0;
9545 if (!isPowerOf2_64(cN) || c0 != cN || Log2_64(c0) < 1 || Log2_64(c0) > 32)
9552 /// PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD)
9553 /// can replace combinations of VMUL and VCVT (floating-point to integer)
9554 /// when the VMUL has a constant operand that is a power of 2.
9556 /// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
9557 /// vmul.f32 d16, d17, d16
9558 /// vcvt.s32.f32 d16, d16
9560 /// vcvt.s32.f32 d16, d16, #3
9561 static SDValue PerformVCVTCombine(SDNode *N,
9562 TargetLowering::DAGCombinerInfo &DCI,
9563 const ARMSubtarget *Subtarget) {
9564 SelectionDAG &DAG = DCI.DAG;
9565 SDValue Op = N->getOperand(0);
9567 if (!Subtarget->hasNEON() || !Op.getValueType().isVector() ||
9568 Op.getOpcode() != ISD::FMUL)
9572 SDValue N0 = Op->getOperand(0);
9573 SDValue ConstVec = Op->getOperand(1);
9574 bool isSigned = N->getOpcode() == ISD::FP_TO_SINT;
9576 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
9577 !isConstVecPow2(ConstVec, isSigned, C))
9580 MVT FloatTy = Op.getSimpleValueType().getVectorElementType();
9581 MVT IntTy = N->getSimpleValueType(0).getVectorElementType();
9582 if (FloatTy.getSizeInBits() != 32 || IntTy.getSizeInBits() > 32) {
9583 // These instructions only exist converting from f32 to i32. We can handle
9584 // smaller integers by generating an extra truncate, but larger ones would
9589 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfp2fxs :
9590 Intrinsic::arm_neon_vcvtfp2fxu;
9591 unsigned NumLanes = Op.getValueType().getVectorNumElements();
9592 SDValue FixConv = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N),
9593 NumLanes == 2 ? MVT::v2i32 : MVT::v4i32,
9594 DAG.getConstant(IntrinsicOpcode, MVT::i32), N0,
9595 DAG.getConstant(Log2_64(C), MVT::i32));
9597 if (IntTy.getSizeInBits() < FloatTy.getSizeInBits())
9598 FixConv = DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), FixConv);
9603 /// PerformVDIVCombine - VCVT (fixed-point to floating-point, Advanced SIMD)
9604 /// can replace combinations of VCVT (integer to floating-point) and VDIV
9605 /// when the VDIV has a constant operand that is a power of 2.
9607 /// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
9608 /// vcvt.f32.s32 d16, d16
9609 /// vdiv.f32 d16, d17, d16
9611 /// vcvt.f32.s32 d16, d16, #3
9612 static SDValue PerformVDIVCombine(SDNode *N,
9613 TargetLowering::DAGCombinerInfo &DCI,
9614 const ARMSubtarget *Subtarget) {
9615 SelectionDAG &DAG = DCI.DAG;
9616 SDValue Op = N->getOperand(0);
9617 unsigned OpOpcode = Op.getNode()->getOpcode();
9619 if (!Subtarget->hasNEON() || !N->getValueType(0).isVector() ||
9620 (OpOpcode != ISD::SINT_TO_FP && OpOpcode != ISD::UINT_TO_FP))
9624 SDValue ConstVec = N->getOperand(1);
9625 bool isSigned = OpOpcode == ISD::SINT_TO_FP;
9627 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
9628 !isConstVecPow2(ConstVec, isSigned, C))
9631 MVT FloatTy = N->getSimpleValueType(0).getVectorElementType();
9632 MVT IntTy = Op.getOperand(0).getSimpleValueType().getVectorElementType();
9633 if (FloatTy.getSizeInBits() != 32 || IntTy.getSizeInBits() > 32) {
9634 // These instructions only exist converting from i32 to f32. We can handle
9635 // smaller integers by generating an extra extend, but larger ones would
9640 SDValue ConvInput = Op.getOperand(0);
9641 unsigned NumLanes = Op.getValueType().getVectorNumElements();
9642 if (IntTy.getSizeInBits() < FloatTy.getSizeInBits())
9643 ConvInput = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
9644 SDLoc(N), NumLanes == 2 ? MVT::v2i32 : MVT::v4i32,
9647 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfxs2fp :
9648 Intrinsic::arm_neon_vcvtfxu2fp;
9649 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N),
9651 DAG.getConstant(IntrinsicOpcode, MVT::i32),
9652 ConvInput, DAG.getConstant(Log2_64(C), MVT::i32));
9655 /// Getvshiftimm - Check if this is a valid build_vector for the immediate
9656 /// operand of a vector shift operation, where all the elements of the
9657 /// build_vector must have the same constant integer value.
9658 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
9659 // Ignore bit_converts.
9660 while (Op.getOpcode() == ISD::BITCAST)
9661 Op = Op.getOperand(0);
9662 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
9663 APInt SplatBits, SplatUndef;
9664 unsigned SplatBitSize;
9666 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
9667 HasAnyUndefs, ElementBits) ||
9668 SplatBitSize > ElementBits)
9670 Cnt = SplatBits.getSExtValue();
9674 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
9675 /// operand of a vector shift left operation. That value must be in the range:
9676 /// 0 <= Value < ElementBits for a left shift; or
9677 /// 0 <= Value <= ElementBits for a long left shift.
9678 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
9679 assert(VT.isVector() && "vector shift count is not a vector type");
9680 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
9681 if (! getVShiftImm(Op, ElementBits, Cnt))
9683 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
9686 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
9687 /// operand of a vector shift right operation. For a shift opcode, the value
9688 /// is positive, but for an intrinsic the value count must be negative. The
9689 /// absolute value must be in the range:
9690 /// 1 <= |Value| <= ElementBits for a right shift; or
9691 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
9692 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
9694 assert(VT.isVector() && "vector shift count is not a vector type");
9695 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
9696 if (! getVShiftImm(Op, ElementBits, Cnt))
9700 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
9703 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
9704 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
9705 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
9708 // Don't do anything for most intrinsics.
9711 // Vector shifts: check for immediate versions and lower them.
9712 // Note: This is done during DAG combining instead of DAG legalizing because
9713 // the build_vectors for 64-bit vector element shift counts are generally
9714 // not legal, and it is hard to see their values after they get legalized to
9715 // loads from a constant pool.
9716 case Intrinsic::arm_neon_vshifts:
9717 case Intrinsic::arm_neon_vshiftu:
9718 case Intrinsic::arm_neon_vshiftls:
9719 case Intrinsic::arm_neon_vshiftlu:
9720 case Intrinsic::arm_neon_vshiftn:
9721 case Intrinsic::arm_neon_vrshifts:
9722 case Intrinsic::arm_neon_vrshiftu:
9723 case Intrinsic::arm_neon_vrshiftn:
9724 case Intrinsic::arm_neon_vqshifts:
9725 case Intrinsic::arm_neon_vqshiftu:
9726 case Intrinsic::arm_neon_vqshiftsu:
9727 case Intrinsic::arm_neon_vqshiftns:
9728 case Intrinsic::arm_neon_vqshiftnu:
9729 case Intrinsic::arm_neon_vqshiftnsu:
9730 case Intrinsic::arm_neon_vqrshiftns:
9731 case Intrinsic::arm_neon_vqrshiftnu:
9732 case Intrinsic::arm_neon_vqrshiftnsu: {
9733 EVT VT = N->getOperand(1).getValueType();
9735 unsigned VShiftOpc = 0;
9738 case Intrinsic::arm_neon_vshifts:
9739 case Intrinsic::arm_neon_vshiftu:
9740 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
9741 VShiftOpc = ARMISD::VSHL;
9744 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
9745 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
9746 ARMISD::VSHRs : ARMISD::VSHRu);
9751 case Intrinsic::arm_neon_vshiftls:
9752 case Intrinsic::arm_neon_vshiftlu:
9753 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
9755 llvm_unreachable("invalid shift count for vshll intrinsic");
9757 case Intrinsic::arm_neon_vrshifts:
9758 case Intrinsic::arm_neon_vrshiftu:
9759 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
9763 case Intrinsic::arm_neon_vqshifts:
9764 case Intrinsic::arm_neon_vqshiftu:
9765 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
9769 case Intrinsic::arm_neon_vqshiftsu:
9770 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
9772 llvm_unreachable("invalid shift count for vqshlu intrinsic");
9774 case Intrinsic::arm_neon_vshiftn:
9775 case Intrinsic::arm_neon_vrshiftn:
9776 case Intrinsic::arm_neon_vqshiftns:
9777 case Intrinsic::arm_neon_vqshiftnu:
9778 case Intrinsic::arm_neon_vqshiftnsu:
9779 case Intrinsic::arm_neon_vqrshiftns:
9780 case Intrinsic::arm_neon_vqrshiftnu:
9781 case Intrinsic::arm_neon_vqrshiftnsu:
9782 // Narrowing shifts require an immediate right shift.
9783 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
9785 llvm_unreachable("invalid shift count for narrowing vector shift "
9789 llvm_unreachable("unhandled vector shift");
9793 case Intrinsic::arm_neon_vshifts:
9794 case Intrinsic::arm_neon_vshiftu:
9795 // Opcode already set above.
9797 case Intrinsic::arm_neon_vshiftls:
9798 case Intrinsic::arm_neon_vshiftlu:
9799 if (Cnt == VT.getVectorElementType().getSizeInBits())
9800 VShiftOpc = ARMISD::VSHLLi;
9802 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
9803 ARMISD::VSHLLs : ARMISD::VSHLLu);
9805 case Intrinsic::arm_neon_vshiftn:
9806 VShiftOpc = ARMISD::VSHRN; break;
9807 case Intrinsic::arm_neon_vrshifts:
9808 VShiftOpc = ARMISD::VRSHRs; break;
9809 case Intrinsic::arm_neon_vrshiftu:
9810 VShiftOpc = ARMISD::VRSHRu; break;
9811 case Intrinsic::arm_neon_vrshiftn:
9812 VShiftOpc = ARMISD::VRSHRN; break;
9813 case Intrinsic::arm_neon_vqshifts:
9814 VShiftOpc = ARMISD::VQSHLs; break;
9815 case Intrinsic::arm_neon_vqshiftu:
9816 VShiftOpc = ARMISD::VQSHLu; break;
9817 case Intrinsic::arm_neon_vqshiftsu:
9818 VShiftOpc = ARMISD::VQSHLsu; break;
9819 case Intrinsic::arm_neon_vqshiftns:
9820 VShiftOpc = ARMISD::VQSHRNs; break;
9821 case Intrinsic::arm_neon_vqshiftnu:
9822 VShiftOpc = ARMISD::VQSHRNu; break;
9823 case Intrinsic::arm_neon_vqshiftnsu:
9824 VShiftOpc = ARMISD::VQSHRNsu; break;
9825 case Intrinsic::arm_neon_vqrshiftns:
9826 VShiftOpc = ARMISD::VQRSHRNs; break;
9827 case Intrinsic::arm_neon_vqrshiftnu:
9828 VShiftOpc = ARMISD::VQRSHRNu; break;
9829 case Intrinsic::arm_neon_vqrshiftnsu:
9830 VShiftOpc = ARMISD::VQRSHRNsu; break;
9833 return DAG.getNode(VShiftOpc, SDLoc(N), N->getValueType(0),
9834 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
9837 case Intrinsic::arm_neon_vshiftins: {
9838 EVT VT = N->getOperand(1).getValueType();
9840 unsigned VShiftOpc = 0;
9842 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
9843 VShiftOpc = ARMISD::VSLI;
9844 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
9845 VShiftOpc = ARMISD::VSRI;
9847 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
9850 return DAG.getNode(VShiftOpc, SDLoc(N), N->getValueType(0),
9851 N->getOperand(1), N->getOperand(2),
9852 DAG.getConstant(Cnt, MVT::i32));
9855 case Intrinsic::arm_neon_vqrshifts:
9856 case Intrinsic::arm_neon_vqrshiftu:
9857 // No immediate versions of these to check for.
9864 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
9865 /// lowers them. As with the vector shift intrinsics, this is done during DAG
9866 /// combining instead of DAG legalizing because the build_vectors for 64-bit
9867 /// vector element shift counts are generally not legal, and it is hard to see
9868 /// their values after they get legalized to loads from a constant pool.
9869 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
9870 const ARMSubtarget *ST) {
9871 EVT VT = N->getValueType(0);
9872 if (N->getOpcode() == ISD::SRL && VT == MVT::i32 && ST->hasV6Ops()) {
9873 // Canonicalize (srl (bswap x), 16) to (rotr (bswap x), 16) if the high
9874 // 16-bits of x is zero. This optimizes rev + lsr 16 to rev16.
9875 SDValue N1 = N->getOperand(1);
9876 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
9877 SDValue N0 = N->getOperand(0);
9878 if (C->getZExtValue() == 16 && N0.getOpcode() == ISD::BSWAP &&
9879 DAG.MaskedValueIsZero(N0.getOperand(0),
9880 APInt::getHighBitsSet(32, 16)))
9881 return DAG.getNode(ISD::ROTR, SDLoc(N), VT, N0, N1);
9885 // Nothing to be done for scalar shifts.
9886 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9887 if (!VT.isVector() || !TLI.isTypeLegal(VT))
9890 assert(ST->hasNEON() && "unexpected vector shift");
9893 switch (N->getOpcode()) {
9894 default: llvm_unreachable("unexpected shift opcode");
9897 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
9898 return DAG.getNode(ARMISD::VSHL, SDLoc(N), VT, N->getOperand(0),
9899 DAG.getConstant(Cnt, MVT::i32));
9904 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
9905 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
9906 ARMISD::VSHRs : ARMISD::VSHRu);
9907 return DAG.getNode(VShiftOpc, SDLoc(N), VT, N->getOperand(0),
9908 DAG.getConstant(Cnt, MVT::i32));
9914 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
9915 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
9916 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
9917 const ARMSubtarget *ST) {
9918 SDValue N0 = N->getOperand(0);
9920 // Check for sign- and zero-extensions of vector extract operations of 8-
9921 // and 16-bit vector elements. NEON supports these directly. They are
9922 // handled during DAG combining because type legalization will promote them
9923 // to 32-bit types and it is messy to recognize the operations after that.
9924 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
9925 SDValue Vec = N0.getOperand(0);
9926 SDValue Lane = N0.getOperand(1);
9927 EVT VT = N->getValueType(0);
9928 EVT EltVT = N0.getValueType();
9929 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9931 if (VT == MVT::i32 &&
9932 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
9933 TLI.isTypeLegal(Vec.getValueType()) &&
9934 isa<ConstantSDNode>(Lane)) {
9937 switch (N->getOpcode()) {
9938 default: llvm_unreachable("unexpected opcode");
9939 case ISD::SIGN_EXTEND:
9940 Opc = ARMISD::VGETLANEs;
9942 case ISD::ZERO_EXTEND:
9943 case ISD::ANY_EXTEND:
9944 Opc = ARMISD::VGETLANEu;
9947 return DAG.getNode(Opc, SDLoc(N), VT, Vec, Lane);
9954 /// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
9955 /// to match f32 max/min patterns to use NEON vmax/vmin instructions.
9956 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
9957 const ARMSubtarget *ST) {
9958 // If the target supports NEON, try to use vmax/vmin instructions for f32
9959 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set,
9960 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
9961 // a NaN; only do the transformation when it matches that behavior.
9963 // For now only do this when using NEON for FP operations; if using VFP, it
9964 // is not obvious that the benefit outweighs the cost of switching to the
9966 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
9967 N->getValueType(0) != MVT::f32)
9970 SDValue CondLHS = N->getOperand(0);
9971 SDValue CondRHS = N->getOperand(1);
9972 SDValue LHS = N->getOperand(2);
9973 SDValue RHS = N->getOperand(3);
9974 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
9976 unsigned Opcode = 0;
9978 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
9979 IsReversed = false; // x CC y ? x : y
9980 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
9981 IsReversed = true ; // x CC y ? y : x
9995 // If LHS is NaN, an ordered comparison will be false and the result will
9996 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
9997 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
9998 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
9999 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
10001 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
10002 // will return -0, so vmin can only be used for unsafe math or if one of
10003 // the operands is known to be nonzero.
10004 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
10005 !DAG.getTarget().Options.UnsafeFPMath &&
10006 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
10008 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
10017 // If LHS is NaN, an ordered comparison will be false and the result will
10018 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
10019 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
10020 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
10021 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
10023 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
10024 // will return +0, so vmax can only be used for unsafe math or if one of
10025 // the operands is known to be nonzero.
10026 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
10027 !DAG.getTarget().Options.UnsafeFPMath &&
10028 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
10030 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
10036 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), LHS, RHS);
10039 /// PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV.
10041 ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const {
10042 SDValue Cmp = N->getOperand(4);
10043 if (Cmp.getOpcode() != ARMISD::CMPZ)
10044 // Only looking at EQ and NE cases.
10047 EVT VT = N->getValueType(0);
10049 SDValue LHS = Cmp.getOperand(0);
10050 SDValue RHS = Cmp.getOperand(1);
10051 SDValue FalseVal = N->getOperand(0);
10052 SDValue TrueVal = N->getOperand(1);
10053 SDValue ARMcc = N->getOperand(2);
10054 ARMCC::CondCodes CC =
10055 (ARMCC::CondCodes)cast<ConstantSDNode>(ARMcc)->getZExtValue();
10073 /// FIXME: Turn this into a target neutral optimization?
10075 if (CC == ARMCC::NE && FalseVal == RHS && FalseVal != LHS) {
10076 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, TrueVal, ARMcc,
10077 N->getOperand(3), Cmp);
10078 } else if (CC == ARMCC::EQ && TrueVal == RHS) {
10080 SDValue NewCmp = getARMCmp(LHS, RHS, ISD::SETNE, ARMcc, DAG, dl);
10081 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, FalseVal, ARMcc,
10082 N->getOperand(3), NewCmp);
10085 if (Res.getNode()) {
10086 APInt KnownZero, KnownOne;
10087 DAG.ComputeMaskedBits(SDValue(N,0), KnownZero, KnownOne);
10088 // Capture demanded bits information that would be otherwise lost.
10089 if (KnownZero == 0xfffffffe)
10090 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
10091 DAG.getValueType(MVT::i1));
10092 else if (KnownZero == 0xffffff00)
10093 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
10094 DAG.getValueType(MVT::i8));
10095 else if (KnownZero == 0xffff0000)
10096 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
10097 DAG.getValueType(MVT::i16));
10103 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
10104 DAGCombinerInfo &DCI) const {
10105 switch (N->getOpcode()) {
10107 case ISD::ADDC: return PerformADDCCombine(N, DCI, Subtarget);
10108 case ISD::ADD: return PerformADDCombine(N, DCI, Subtarget);
10109 case ISD::SUB: return PerformSUBCombine(N, DCI);
10110 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
10111 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
10112 case ISD::XOR: return PerformXORCombine(N, DCI, Subtarget);
10113 case ISD::AND: return PerformANDCombine(N, DCI, Subtarget);
10114 case ARMISD::BFI: return PerformBFICombine(N, DCI);
10115 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
10116 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
10117 case ISD::STORE: return PerformSTORECombine(N, DCI);
10118 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI);
10119 case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI);
10120 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
10121 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
10122 case ISD::FP_TO_SINT:
10123 case ISD::FP_TO_UINT: return PerformVCVTCombine(N, DCI, Subtarget);
10124 case ISD::FDIV: return PerformVDIVCombine(N, DCI, Subtarget);
10125 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
10128 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
10129 case ISD::SIGN_EXTEND:
10130 case ISD::ZERO_EXTEND:
10131 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
10132 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
10133 case ARMISD::CMOV: return PerformCMOVCombine(N, DCI.DAG);
10134 case ARMISD::VLD2DUP:
10135 case ARMISD::VLD3DUP:
10136 case ARMISD::VLD4DUP:
10137 return CombineBaseUpdate(N, DCI);
10138 case ARMISD::BUILD_VECTOR:
10139 return PerformARMBUILD_VECTORCombine(N, DCI);
10140 case ISD::INTRINSIC_VOID:
10141 case ISD::INTRINSIC_W_CHAIN:
10142 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
10143 case Intrinsic::arm_neon_vld1:
10144 case Intrinsic::arm_neon_vld2:
10145 case Intrinsic::arm_neon_vld3:
10146 case Intrinsic::arm_neon_vld4:
10147 case Intrinsic::arm_neon_vld2lane:
10148 case Intrinsic::arm_neon_vld3lane:
10149 case Intrinsic::arm_neon_vld4lane:
10150 case Intrinsic::arm_neon_vst1:
10151 case Intrinsic::arm_neon_vst2:
10152 case Intrinsic::arm_neon_vst3:
10153 case Intrinsic::arm_neon_vst4:
10154 case Intrinsic::arm_neon_vst2lane:
10155 case Intrinsic::arm_neon_vst3lane:
10156 case Intrinsic::arm_neon_vst4lane:
10157 return CombineBaseUpdate(N, DCI);
10165 bool ARMTargetLowering::isDesirableToTransformToIntegerOp(unsigned Opc,
10167 return (VT == MVT::f32) && (Opc == ISD::LOAD || Opc == ISD::STORE);
10170 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const {
10171 // The AllowsUnaliged flag models the SCTLR.A setting in ARM cpus
10172 bool AllowsUnaligned = Subtarget->allowsUnalignedMem();
10174 switch (VT.getSimpleVT().SimpleTy) {
10180 // Unaligned access can use (for example) LRDB, LRDH, LDR
10181 if (AllowsUnaligned) {
10183 *Fast = Subtarget->hasV7Ops();
10190 // For any little-endian targets with neon, we can support unaligned ld/st
10191 // of D and Q (e.g. {D0,D1}) registers by using vld1.i8/vst1.i8.
10192 // A big-endian target may also explictly support unaligned accesses
10193 if (Subtarget->hasNEON() && (AllowsUnaligned || isLittleEndian())) {
10203 static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign,
10204 unsigned AlignCheck) {
10205 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) &&
10206 (DstAlign == 0 || DstAlign % AlignCheck == 0));
10209 EVT ARMTargetLowering::getOptimalMemOpType(uint64_t Size,
10210 unsigned DstAlign, unsigned SrcAlign,
10211 bool IsMemset, bool ZeroMemset,
10213 MachineFunction &MF) const {
10214 const Function *F = MF.getFunction();
10216 // See if we can use NEON instructions for this...
10217 if ((!IsMemset || ZeroMemset) &&
10218 Subtarget->hasNEON() &&
10219 !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
10220 Attribute::NoImplicitFloat)) {
10223 (memOpAlign(SrcAlign, DstAlign, 16) ||
10224 (allowsUnalignedMemoryAccesses(MVT::v2f64, &Fast) && Fast))) {
10226 } else if (Size >= 8 &&
10227 (memOpAlign(SrcAlign, DstAlign, 8) ||
10228 (allowsUnalignedMemoryAccesses(MVT::f64, &Fast) && Fast))) {
10233 // Lowering to i32/i16 if the size permits.
10236 else if (Size >= 2)
10239 // Let the target-independent logic figure it out.
10243 bool ARMTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
10244 if (Val.getOpcode() != ISD::LOAD)
10247 EVT VT1 = Val.getValueType();
10248 if (!VT1.isSimple() || !VT1.isInteger() ||
10249 !VT2.isSimple() || !VT2.isInteger())
10252 switch (VT1.getSimpleVT().SimpleTy) {
10257 // 8-bit and 16-bit loads implicitly zero-extend to 32-bits.
10264 bool ARMTargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
10265 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
10268 if (!isTypeLegal(EVT::getEVT(Ty1)))
10271 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
10273 // Assuming the caller doesn't have a zeroext or signext return parameter,
10274 // truncation all the way down to i1 is valid.
10279 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
10283 unsigned Scale = 1;
10284 switch (VT.getSimpleVT().SimpleTy) {
10285 default: return false;
10300 if ((V & (Scale - 1)) != 0)
10303 return V == (V & ((1LL << 5) - 1));
10306 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
10307 const ARMSubtarget *Subtarget) {
10308 bool isNeg = false;
10314 switch (VT.getSimpleVT().SimpleTy) {
10315 default: return false;
10320 // + imm12 or - imm8
10322 return V == (V & ((1LL << 8) - 1));
10323 return V == (V & ((1LL << 12) - 1));
10326 // Same as ARM mode. FIXME: NEON?
10327 if (!Subtarget->hasVFP2())
10332 return V == (V & ((1LL << 8) - 1));
10336 /// isLegalAddressImmediate - Return true if the integer value can be used
10337 /// as the offset of the target addressing mode for load / store of the
10339 static bool isLegalAddressImmediate(int64_t V, EVT VT,
10340 const ARMSubtarget *Subtarget) {
10344 if (!VT.isSimple())
10347 if (Subtarget->isThumb1Only())
10348 return isLegalT1AddressImmediate(V, VT);
10349 else if (Subtarget->isThumb2())
10350 return isLegalT2AddressImmediate(V, VT, Subtarget);
10355 switch (VT.getSimpleVT().SimpleTy) {
10356 default: return false;
10361 return V == (V & ((1LL << 12) - 1));
10364 return V == (V & ((1LL << 8) - 1));
10367 if (!Subtarget->hasVFP2()) // FIXME: NEON?
10372 return V == (V & ((1LL << 8) - 1));
10376 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
10378 int Scale = AM.Scale;
10382 switch (VT.getSimpleVT().SimpleTy) {
10383 default: return false;
10391 Scale = Scale & ~1;
10392 return Scale == 2 || Scale == 4 || Scale == 8;
10395 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
10399 // Note, we allow "void" uses (basically, uses that aren't loads or
10400 // stores), because arm allows folding a scale into many arithmetic
10401 // operations. This should be made more precise and revisited later.
10403 // Allow r << imm, but the imm has to be a multiple of two.
10404 if (Scale & 1) return false;
10405 return isPowerOf2_32(Scale);
10409 /// isLegalAddressingMode - Return true if the addressing mode represented
10410 /// by AM is legal for this target, for a load/store of the specified type.
10411 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
10413 EVT VT = getValueType(Ty, true);
10414 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
10417 // Can never fold addr of global into load/store.
10421 switch (AM.Scale) {
10422 case 0: // no scale reg, must be "r+i" or "r", or "i".
10425 if (Subtarget->isThumb1Only())
10429 // ARM doesn't support any R+R*scale+imm addr modes.
10433 if (!VT.isSimple())
10436 if (Subtarget->isThumb2())
10437 return isLegalT2ScaledAddressingMode(AM, VT);
10439 int Scale = AM.Scale;
10440 switch (VT.getSimpleVT().SimpleTy) {
10441 default: return false;
10445 if (Scale < 0) Scale = -Scale;
10449 return isPowerOf2_32(Scale & ~1);
10453 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
10458 // Note, we allow "void" uses (basically, uses that aren't loads or
10459 // stores), because arm allows folding a scale into many arithmetic
10460 // operations. This should be made more precise and revisited later.
10462 // Allow r << imm, but the imm has to be a multiple of two.
10463 if (Scale & 1) return false;
10464 return isPowerOf2_32(Scale);
10470 /// isLegalICmpImmediate - Return true if the specified immediate is legal
10471 /// icmp immediate, that is the target has icmp instructions which can compare
10472 /// a register against the immediate without having to materialize the
10473 /// immediate into a register.
10474 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
10475 // Thumb2 and ARM modes can use cmn for negative immediates.
10476 if (!Subtarget->isThumb())
10477 return ARM_AM::getSOImmVal(llvm::abs64(Imm)) != -1;
10478 if (Subtarget->isThumb2())
10479 return ARM_AM::getT2SOImmVal(llvm::abs64(Imm)) != -1;
10480 // Thumb1 doesn't have cmn, and only 8-bit immediates.
10481 return Imm >= 0 && Imm <= 255;
10484 /// isLegalAddImmediate - Return true if the specified immediate is a legal add
10485 /// *or sub* immediate, that is the target has add or sub instructions which can
10486 /// add a register with the immediate without having to materialize the
10487 /// immediate into a register.
10488 bool ARMTargetLowering::isLegalAddImmediate(int64_t Imm) const {
10489 // Same encoding for add/sub, just flip the sign.
10490 int64_t AbsImm = llvm::abs64(Imm);
10491 if (!Subtarget->isThumb())
10492 return ARM_AM::getSOImmVal(AbsImm) != -1;
10493 if (Subtarget->isThumb2())
10494 return ARM_AM::getT2SOImmVal(AbsImm) != -1;
10495 // Thumb1 only has 8-bit unsigned immediate.
10496 return AbsImm >= 0 && AbsImm <= 255;
10499 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
10500 bool isSEXTLoad, SDValue &Base,
10501 SDValue &Offset, bool &isInc,
10502 SelectionDAG &DAG) {
10503 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
10506 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
10507 // AddressingMode 3
10508 Base = Ptr->getOperand(0);
10509 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
10510 int RHSC = (int)RHS->getZExtValue();
10511 if (RHSC < 0 && RHSC > -256) {
10512 assert(Ptr->getOpcode() == ISD::ADD);
10514 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
10518 isInc = (Ptr->getOpcode() == ISD::ADD);
10519 Offset = Ptr->getOperand(1);
10521 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
10522 // AddressingMode 2
10523 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
10524 int RHSC = (int)RHS->getZExtValue();
10525 if (RHSC < 0 && RHSC > -0x1000) {
10526 assert(Ptr->getOpcode() == ISD::ADD);
10528 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
10529 Base = Ptr->getOperand(0);
10534 if (Ptr->getOpcode() == ISD::ADD) {
10536 ARM_AM::ShiftOpc ShOpcVal=
10537 ARM_AM::getShiftOpcForNode(Ptr->getOperand(0).getOpcode());
10538 if (ShOpcVal != ARM_AM::no_shift) {
10539 Base = Ptr->getOperand(1);
10540 Offset = Ptr->getOperand(0);
10542 Base = Ptr->getOperand(0);
10543 Offset = Ptr->getOperand(1);
10548 isInc = (Ptr->getOpcode() == ISD::ADD);
10549 Base = Ptr->getOperand(0);
10550 Offset = Ptr->getOperand(1);
10554 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
10558 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
10559 bool isSEXTLoad, SDValue &Base,
10560 SDValue &Offset, bool &isInc,
10561 SelectionDAG &DAG) {
10562 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
10565 Base = Ptr->getOperand(0);
10566 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
10567 int RHSC = (int)RHS->getZExtValue();
10568 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
10569 assert(Ptr->getOpcode() == ISD::ADD);
10571 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
10573 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
10574 isInc = Ptr->getOpcode() == ISD::ADD;
10575 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
10583 /// getPreIndexedAddressParts - returns true by value, base pointer and
10584 /// offset pointer and addressing mode by reference if the node's address
10585 /// can be legally represented as pre-indexed load / store address.
10587 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
10589 ISD::MemIndexedMode &AM,
10590 SelectionDAG &DAG) const {
10591 if (Subtarget->isThumb1Only())
10596 bool isSEXTLoad = false;
10597 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
10598 Ptr = LD->getBasePtr();
10599 VT = LD->getMemoryVT();
10600 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
10601 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
10602 Ptr = ST->getBasePtr();
10603 VT = ST->getMemoryVT();
10608 bool isLegal = false;
10609 if (Subtarget->isThumb2())
10610 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
10611 Offset, isInc, DAG);
10613 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
10614 Offset, isInc, DAG);
10618 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
10622 /// getPostIndexedAddressParts - returns true by value, base pointer and
10623 /// offset pointer and addressing mode by reference if this node can be
10624 /// combined with a load / store to form a post-indexed load / store.
10625 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
10628 ISD::MemIndexedMode &AM,
10629 SelectionDAG &DAG) const {
10630 if (Subtarget->isThumb1Only())
10635 bool isSEXTLoad = false;
10636 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
10637 VT = LD->getMemoryVT();
10638 Ptr = LD->getBasePtr();
10639 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
10640 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
10641 VT = ST->getMemoryVT();
10642 Ptr = ST->getBasePtr();
10647 bool isLegal = false;
10648 if (Subtarget->isThumb2())
10649 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
10652 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
10658 // Swap base ptr and offset to catch more post-index load / store when
10659 // it's legal. In Thumb2 mode, offset must be an immediate.
10660 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
10661 !Subtarget->isThumb2())
10662 std::swap(Base, Offset);
10664 // Post-indexed load / store update the base pointer.
10669 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
10673 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
10676 const SelectionDAG &DAG,
10677 unsigned Depth) const {
10678 unsigned BitWidth = KnownOne.getBitWidth();
10679 KnownZero = KnownOne = APInt(BitWidth, 0);
10680 switch (Op.getOpcode()) {
10686 // These nodes' second result is a boolean
10687 if (Op.getResNo() == 0)
10689 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
10691 case ARMISD::CMOV: {
10692 // Bits are known zero/one if known on the LHS and RHS.
10693 DAG.ComputeMaskedBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1);
10694 if (KnownZero == 0 && KnownOne == 0) return;
10696 APInt KnownZeroRHS, KnownOneRHS;
10697 DAG.ComputeMaskedBits(Op.getOperand(1), KnownZeroRHS, KnownOneRHS, Depth+1);
10698 KnownZero &= KnownZeroRHS;
10699 KnownOne &= KnownOneRHS;
10705 //===----------------------------------------------------------------------===//
10706 // ARM Inline Assembly Support
10707 //===----------------------------------------------------------------------===//
10709 bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const {
10710 // Looking for "rev" which is V6+.
10711 if (!Subtarget->hasV6Ops())
10714 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
10715 std::string AsmStr = IA->getAsmString();
10716 SmallVector<StringRef, 4> AsmPieces;
10717 SplitString(AsmStr, AsmPieces, ";\n");
10719 switch (AsmPieces.size()) {
10720 default: return false;
10722 AsmStr = AsmPieces[0];
10724 SplitString(AsmStr, AsmPieces, " \t,");
10727 if (AsmPieces.size() == 3 &&
10728 AsmPieces[0] == "rev" && AsmPieces[1] == "$0" && AsmPieces[2] == "$1" &&
10729 IA->getConstraintString().compare(0, 4, "=l,l") == 0) {
10730 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
10731 if (Ty && Ty->getBitWidth() == 32)
10732 return IntrinsicLowering::LowerToByteSwap(CI);
10740 /// getConstraintType - Given a constraint letter, return the type of
10741 /// constraint it is for this target.
10742 ARMTargetLowering::ConstraintType
10743 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
10744 if (Constraint.size() == 1) {
10745 switch (Constraint[0]) {
10747 case 'l': return C_RegisterClass;
10748 case 'w': return C_RegisterClass;
10749 case 'h': return C_RegisterClass;
10750 case 'x': return C_RegisterClass;
10751 case 't': return C_RegisterClass;
10752 case 'j': return C_Other; // Constant for movw.
10753 // An address with a single base register. Due to the way we
10754 // currently handle addresses it is the same as an 'r' memory constraint.
10755 case 'Q': return C_Memory;
10757 } else if (Constraint.size() == 2) {
10758 switch (Constraint[0]) {
10760 // All 'U+' constraints are addresses.
10761 case 'U': return C_Memory;
10764 return TargetLowering::getConstraintType(Constraint);
10767 /// Examine constraint type and operand type and determine a weight value.
10768 /// This object must already have been set up with the operand type
10769 /// and the current alternative constraint selected.
10770 TargetLowering::ConstraintWeight
10771 ARMTargetLowering::getSingleConstraintMatchWeight(
10772 AsmOperandInfo &info, const char *constraint) const {
10773 ConstraintWeight weight = CW_Invalid;
10774 Value *CallOperandVal = info.CallOperandVal;
10775 // If we don't have a value, we can't do a match,
10776 // but allow it at the lowest weight.
10777 if (CallOperandVal == NULL)
10779 Type *type = CallOperandVal->getType();
10780 // Look at the constraint type.
10781 switch (*constraint) {
10783 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
10786 if (type->isIntegerTy()) {
10787 if (Subtarget->isThumb())
10788 weight = CW_SpecificReg;
10790 weight = CW_Register;
10794 if (type->isFloatingPointTy())
10795 weight = CW_Register;
10801 typedef std::pair<unsigned, const TargetRegisterClass*> RCPair;
10803 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
10805 if (Constraint.size() == 1) {
10806 // GCC ARM Constraint Letters
10807 switch (Constraint[0]) {
10808 case 'l': // Low regs or general regs.
10809 if (Subtarget->isThumb())
10810 return RCPair(0U, &ARM::tGPRRegClass);
10811 return RCPair(0U, &ARM::GPRRegClass);
10812 case 'h': // High regs or no regs.
10813 if (Subtarget->isThumb())
10814 return RCPair(0U, &ARM::hGPRRegClass);
10817 return RCPair(0U, &ARM::GPRRegClass);
10819 if (VT == MVT::Other)
10821 if (VT == MVT::f32)
10822 return RCPair(0U, &ARM::SPRRegClass);
10823 if (VT.getSizeInBits() == 64)
10824 return RCPair(0U, &ARM::DPRRegClass);
10825 if (VT.getSizeInBits() == 128)
10826 return RCPair(0U, &ARM::QPRRegClass);
10829 if (VT == MVT::Other)
10831 if (VT == MVT::f32)
10832 return RCPair(0U, &ARM::SPR_8RegClass);
10833 if (VT.getSizeInBits() == 64)
10834 return RCPair(0U, &ARM::DPR_8RegClass);
10835 if (VT.getSizeInBits() == 128)
10836 return RCPair(0U, &ARM::QPR_8RegClass);
10839 if (VT == MVT::f32)
10840 return RCPair(0U, &ARM::SPRRegClass);
10844 if (StringRef("{cc}").equals_lower(Constraint))
10845 return std::make_pair(unsigned(ARM::CPSR), &ARM::CCRRegClass);
10847 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
10850 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
10851 /// vector. If it is invalid, don't add anything to Ops.
10852 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
10853 std::string &Constraint,
10854 std::vector<SDValue>&Ops,
10855 SelectionDAG &DAG) const {
10856 SDValue Result(0, 0);
10858 // Currently only support length 1 constraints.
10859 if (Constraint.length() != 1) return;
10861 char ConstraintLetter = Constraint[0];
10862 switch (ConstraintLetter) {
10865 case 'I': case 'J': case 'K': case 'L':
10866 case 'M': case 'N': case 'O':
10867 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
10871 int64_t CVal64 = C->getSExtValue();
10872 int CVal = (int) CVal64;
10873 // None of these constraints allow values larger than 32 bits. Check
10874 // that the value fits in an int.
10875 if (CVal != CVal64)
10878 switch (ConstraintLetter) {
10880 // Constant suitable for movw, must be between 0 and
10882 if (Subtarget->hasV6T2Ops())
10883 if (CVal >= 0 && CVal <= 65535)
10887 if (Subtarget->isThumb1Only()) {
10888 // This must be a constant between 0 and 255, for ADD
10890 if (CVal >= 0 && CVal <= 255)
10892 } else if (Subtarget->isThumb2()) {
10893 // A constant that can be used as an immediate value in a
10894 // data-processing instruction.
10895 if (ARM_AM::getT2SOImmVal(CVal) != -1)
10898 // A constant that can be used as an immediate value in a
10899 // data-processing instruction.
10900 if (ARM_AM::getSOImmVal(CVal) != -1)
10906 if (Subtarget->isThumb()) { // FIXME thumb2
10907 // This must be a constant between -255 and -1, for negated ADD
10908 // immediates. This can be used in GCC with an "n" modifier that
10909 // prints the negated value, for use with SUB instructions. It is
10910 // not useful otherwise but is implemented for compatibility.
10911 if (CVal >= -255 && CVal <= -1)
10914 // This must be a constant between -4095 and 4095. It is not clear
10915 // what this constraint is intended for. Implemented for
10916 // compatibility with GCC.
10917 if (CVal >= -4095 && CVal <= 4095)
10923 if (Subtarget->isThumb1Only()) {
10924 // A 32-bit value where only one byte has a nonzero value. Exclude
10925 // zero to match GCC. This constraint is used by GCC internally for
10926 // constants that can be loaded with a move/shift combination.
10927 // It is not useful otherwise but is implemented for compatibility.
10928 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
10930 } else if (Subtarget->isThumb2()) {
10931 // A constant whose bitwise inverse can be used as an immediate
10932 // value in a data-processing instruction. This can be used in GCC
10933 // with a "B" modifier that prints the inverted value, for use with
10934 // BIC and MVN instructions. It is not useful otherwise but is
10935 // implemented for compatibility.
10936 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
10939 // A constant whose bitwise inverse can be used as an immediate
10940 // value in a data-processing instruction. This can be used in GCC
10941 // with a "B" modifier that prints the inverted value, for use with
10942 // BIC and MVN instructions. It is not useful otherwise but is
10943 // implemented for compatibility.
10944 if (ARM_AM::getSOImmVal(~CVal) != -1)
10950 if (Subtarget->isThumb1Only()) {
10951 // This must be a constant between -7 and 7,
10952 // for 3-operand ADD/SUB immediate instructions.
10953 if (CVal >= -7 && CVal < 7)
10955 } else if (Subtarget->isThumb2()) {
10956 // A constant whose negation can be used as an immediate value in a
10957 // data-processing instruction. This can be used in GCC with an "n"
10958 // modifier that prints the negated value, for use with SUB
10959 // instructions. It is not useful otherwise but is implemented for
10961 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
10964 // A constant whose negation can be used as an immediate value in a
10965 // data-processing instruction. This can be used in GCC with an "n"
10966 // modifier that prints the negated value, for use with SUB
10967 // instructions. It is not useful otherwise but is implemented for
10969 if (ARM_AM::getSOImmVal(-CVal) != -1)
10975 if (Subtarget->isThumb()) { // FIXME thumb2
10976 // This must be a multiple of 4 between 0 and 1020, for
10977 // ADD sp + immediate.
10978 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
10981 // A power of two or a constant between 0 and 32. This is used in
10982 // GCC for the shift amount on shifted register operands, but it is
10983 // useful in general for any shift amounts.
10984 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
10990 if (Subtarget->isThumb()) { // FIXME thumb2
10991 // This must be a constant between 0 and 31, for shift amounts.
10992 if (CVal >= 0 && CVal <= 31)
10998 if (Subtarget->isThumb()) { // FIXME thumb2
10999 // This must be a multiple of 4 between -508 and 508, for
11000 // ADD/SUB sp = sp + immediate.
11001 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
11006 Result = DAG.getTargetConstant(CVal, Op.getValueType());
11010 if (Result.getNode()) {
11011 Ops.push_back(Result);
11014 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
11017 SDValue ARMTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const {
11018 assert(Subtarget->isTargetAEABI() && "Register-based DivRem lowering only");
11019 unsigned Opcode = Op->getOpcode();
11020 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
11021 "Invalid opcode for Div/Rem lowering");
11022 bool isSigned = (Opcode == ISD::SDIVREM);
11023 EVT VT = Op->getValueType(0);
11024 Type *Ty = VT.getTypeForEVT(*DAG.getContext());
11027 switch (VT.getSimpleVT().SimpleTy) {
11028 default: llvm_unreachable("Unexpected request for libcall!");
11029 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
11030 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
11031 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
11032 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
11035 SDValue InChain = DAG.getEntryNode();
11037 TargetLowering::ArgListTy Args;
11038 TargetLowering::ArgListEntry Entry;
11039 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
11040 EVT ArgVT = Op->getOperand(i).getValueType();
11041 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
11042 Entry.Node = Op->getOperand(i);
11044 Entry.isSExt = isSigned;
11045 Entry.isZExt = !isSigned;
11046 Args.push_back(Entry);
11049 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
11052 Type *RetTy = (Type*)StructType::get(Ty, Ty, NULL);
11056 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, true,
11057 0, getLibcallCallingConv(LC), /*isTailCall=*/false,
11058 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
11059 Callee, Args, DAG, dl);
11060 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
11062 return CallInfo.first;
11066 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
11067 // The ARM target isn't yet aware of offsets.
11071 bool ARM::isBitFieldInvertedMask(unsigned v) {
11072 if (v == 0xffffffff)
11075 // there can be 1's on either or both "outsides", all the "inside"
11076 // bits must be 0's
11077 unsigned TO = CountTrailingOnes_32(v);
11078 unsigned LO = CountLeadingOnes_32(v);
11079 v = (v >> TO) << TO;
11080 v = (v << LO) >> LO;
11084 /// isFPImmLegal - Returns true if the target can instruction select the
11085 /// specified FP immediate natively. If false, the legalizer will
11086 /// materialize the FP immediate as a load from a constant pool.
11087 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
11088 if (!Subtarget->hasVFP3())
11090 if (VT == MVT::f32)
11091 return ARM_AM::getFP32Imm(Imm) != -1;
11092 if (VT == MVT::f64)
11093 return ARM_AM::getFP64Imm(Imm) != -1;
11097 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
11098 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
11099 /// specified in the intrinsic calls.
11100 bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
11102 unsigned Intrinsic) const {
11103 switch (Intrinsic) {
11104 case Intrinsic::arm_neon_vld1:
11105 case Intrinsic::arm_neon_vld2:
11106 case Intrinsic::arm_neon_vld3:
11107 case Intrinsic::arm_neon_vld4:
11108 case Intrinsic::arm_neon_vld2lane:
11109 case Intrinsic::arm_neon_vld3lane:
11110 case Intrinsic::arm_neon_vld4lane: {
11111 Info.opc = ISD::INTRINSIC_W_CHAIN;
11112 // Conservatively set memVT to the entire set of vectors loaded.
11113 uint64_t NumElts = getDataLayout()->getTypeAllocSize(I.getType()) / 8;
11114 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
11115 Info.ptrVal = I.getArgOperand(0);
11117 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
11118 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
11119 Info.vol = false; // volatile loads with NEON intrinsics not supported
11120 Info.readMem = true;
11121 Info.writeMem = false;
11124 case Intrinsic::arm_neon_vst1:
11125 case Intrinsic::arm_neon_vst2:
11126 case Intrinsic::arm_neon_vst3:
11127 case Intrinsic::arm_neon_vst4:
11128 case Intrinsic::arm_neon_vst2lane:
11129 case Intrinsic::arm_neon_vst3lane:
11130 case Intrinsic::arm_neon_vst4lane: {
11131 Info.opc = ISD::INTRINSIC_VOID;
11132 // Conservatively set memVT to the entire set of vectors stored.
11133 unsigned NumElts = 0;
11134 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
11135 Type *ArgTy = I.getArgOperand(ArgI)->getType();
11136 if (!ArgTy->isVectorTy())
11138 NumElts += getDataLayout()->getTypeAllocSize(ArgTy) / 8;
11140 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
11141 Info.ptrVal = I.getArgOperand(0);
11143 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
11144 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
11145 Info.vol = false; // volatile stores with NEON intrinsics not supported
11146 Info.readMem = false;
11147 Info.writeMem = true;
11150 case Intrinsic::arm_ldrex: {
11151 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
11152 Info.opc = ISD::INTRINSIC_W_CHAIN;
11153 Info.memVT = MVT::getVT(PtrTy->getElementType());
11154 Info.ptrVal = I.getArgOperand(0);
11156 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
11158 Info.readMem = true;
11159 Info.writeMem = false;
11162 case Intrinsic::arm_strex: {
11163 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
11164 Info.opc = ISD::INTRINSIC_W_CHAIN;
11165 Info.memVT = MVT::getVT(PtrTy->getElementType());
11166 Info.ptrVal = I.getArgOperand(1);
11168 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
11170 Info.readMem = false;
11171 Info.writeMem = true;
11174 case Intrinsic::arm_strexd: {
11175 Info.opc = ISD::INTRINSIC_W_CHAIN;
11176 Info.memVT = MVT::i64;
11177 Info.ptrVal = I.getArgOperand(2);
11181 Info.readMem = false;
11182 Info.writeMem = true;
11185 case Intrinsic::arm_ldrexd: {
11186 Info.opc = ISD::INTRINSIC_W_CHAIN;
11187 Info.memVT = MVT::i64;
11188 Info.ptrVal = I.getArgOperand(0);
11192 Info.readMem = true;
11193 Info.writeMem = false;