1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "arm-isel"
17 #include "ARMAddressingModes.h"
18 #include "ARMCallingConv.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMISelLowering.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMPerfectShuffle.h"
23 #include "ARMRegisterInfo.h"
24 #include "ARMSubtarget.h"
25 #include "ARMTargetMachine.h"
26 #include "ARMTargetObjectFile.h"
27 #include "llvm/CallingConv.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Function.h"
30 #include "llvm/GlobalValue.h"
31 #include "llvm/Instruction.h"
32 #include "llvm/Instructions.h"
33 #include "llvm/Intrinsics.h"
34 #include "llvm/Type.h"
35 #include "llvm/CodeGen/CallingConvLower.h"
36 #include "llvm/CodeGen/MachineBasicBlock.h"
37 #include "llvm/CodeGen/MachineFrameInfo.h"
38 #include "llvm/CodeGen/MachineFunction.h"
39 #include "llvm/CodeGen/MachineInstrBuilder.h"
40 #include "llvm/CodeGen/MachineRegisterInfo.h"
41 #include "llvm/CodeGen/PseudoSourceValue.h"
42 #include "llvm/CodeGen/SelectionDAG.h"
43 #include "llvm/MC/MCSectionMachO.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/ADT/VectorExtras.h"
46 #include "llvm/ADT/Statistic.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Support/raw_ostream.h"
54 STATISTIC(NumTailCalls, "Number of tail calls");
56 // This option should go away when tail calls fully work.
58 EnableARMTailCalls("arm-tail-calls", cl::Hidden,
59 cl::desc("Generate tail calls (TEMPORARY OPTION)."),
63 EnableARMLongCalls("arm-long-calls", cl::Hidden,
64 cl::desc("Generate calls via indirect call instructions"),
68 ARMInterworking("arm-interworking", cl::Hidden,
69 cl::desc("Enable / disable ARM interworking (for debugging only)"),
72 void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
73 EVT PromotedBitwiseVT) {
74 if (VT != PromotedLdStVT) {
75 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
76 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
77 PromotedLdStVT.getSimpleVT());
79 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
80 AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
81 PromotedLdStVT.getSimpleVT());
84 EVT ElemTy = VT.getVectorElementType();
85 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
86 setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
87 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
88 if (ElemTy != MVT::i32) {
89 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
90 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand);
91 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand);
92 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand);
94 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
95 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
96 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
97 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Expand);
98 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
99 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
100 if (VT.isInteger()) {
101 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
102 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
103 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
104 setLoadExtAction(ISD::SEXTLOAD, VT.getSimpleVT(), Expand);
105 setLoadExtAction(ISD::ZEXTLOAD, VT.getSimpleVT(), Expand);
106 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
107 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
108 setTruncStoreAction(VT.getSimpleVT(),
109 (MVT::SimpleValueType)InnerVT, Expand);
111 setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand);
113 // Promote all bit-wise operations.
114 if (VT.isInteger() && VT != PromotedBitwiseVT) {
115 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
116 AddPromotedToType (ISD::AND, VT.getSimpleVT(),
117 PromotedBitwiseVT.getSimpleVT());
118 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
119 AddPromotedToType (ISD::OR, VT.getSimpleVT(),
120 PromotedBitwiseVT.getSimpleVT());
121 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
122 AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
123 PromotedBitwiseVT.getSimpleVT());
126 // Neon does not support vector divide/remainder operations.
127 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
128 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
129 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand);
130 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
131 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
132 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
135 void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
136 addRegisterClass(VT, ARM::DPRRegisterClass);
137 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
140 void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
141 addRegisterClass(VT, ARM::QPRRegisterClass);
142 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
145 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
146 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
147 return new TargetLoweringObjectFileMachO();
149 return new ARMElfTargetObjectFile();
152 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
153 : TargetLowering(TM, createTLOF(TM)) {
154 Subtarget = &TM.getSubtarget<ARMSubtarget>();
155 RegInfo = TM.getRegisterInfo();
156 Itins = TM.getInstrItineraryData();
158 if (Subtarget->isTargetDarwin()) {
159 // Uses VFP for Thumb libfuncs if available.
160 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
161 // Single-precision floating-point arithmetic.
162 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
163 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
164 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
165 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
167 // Double-precision floating-point arithmetic.
168 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
169 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
170 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
171 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
173 // Single-precision comparisons.
174 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
175 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
176 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
177 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
178 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
179 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
180 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
181 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
183 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
184 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
185 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
186 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
187 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
188 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
189 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
190 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
192 // Double-precision comparisons.
193 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
194 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
195 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
196 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
197 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
198 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
199 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
200 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
202 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
203 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
204 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
205 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
206 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
207 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
208 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
209 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
211 // Floating-point to integer conversions.
212 // i64 conversions are done via library routines even when generating VFP
213 // instructions, so use the same ones.
214 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
215 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
216 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
217 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
219 // Conversions between floating types.
220 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
221 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
223 // Integer to floating-point conversions.
224 // i64 conversions are done via library routines even when generating VFP
225 // instructions, so use the same ones.
226 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
227 // e.g., __floatunsidf vs. __floatunssidfvfp.
228 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
229 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
230 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
231 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
235 // These libcalls are not available in 32-bit.
236 setLibcallName(RTLIB::SHL_I128, 0);
237 setLibcallName(RTLIB::SRL_I128, 0);
238 setLibcallName(RTLIB::SRA_I128, 0);
240 if (Subtarget->isAAPCS_ABI()) {
241 // Double-precision floating-point arithmetic helper functions
242 // RTABI chapter 4.1.2, Table 2
243 setLibcallName(RTLIB::ADD_F64, "__aeabi_dadd");
244 setLibcallName(RTLIB::DIV_F64, "__aeabi_ddiv");
245 setLibcallName(RTLIB::MUL_F64, "__aeabi_dmul");
246 setLibcallName(RTLIB::SUB_F64, "__aeabi_dsub");
247 setLibcallCallingConv(RTLIB::ADD_F64, CallingConv::ARM_AAPCS);
248 setLibcallCallingConv(RTLIB::DIV_F64, CallingConv::ARM_AAPCS);
249 setLibcallCallingConv(RTLIB::MUL_F64, CallingConv::ARM_AAPCS);
250 setLibcallCallingConv(RTLIB::SUB_F64, CallingConv::ARM_AAPCS);
252 // Double-precision floating-point comparison helper functions
253 // RTABI chapter 4.1.2, Table 3
254 setLibcallName(RTLIB::OEQ_F64, "__aeabi_dcmpeq");
255 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
256 setLibcallName(RTLIB::UNE_F64, "__aeabi_dcmpeq");
257 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETEQ);
258 setLibcallName(RTLIB::OLT_F64, "__aeabi_dcmplt");
259 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
260 setLibcallName(RTLIB::OLE_F64, "__aeabi_dcmple");
261 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
262 setLibcallName(RTLIB::OGE_F64, "__aeabi_dcmpge");
263 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
264 setLibcallName(RTLIB::OGT_F64, "__aeabi_dcmpgt");
265 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
266 setLibcallName(RTLIB::UO_F64, "__aeabi_dcmpun");
267 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
268 setLibcallName(RTLIB::O_F64, "__aeabi_dcmpun");
269 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
270 setLibcallCallingConv(RTLIB::OEQ_F64, CallingConv::ARM_AAPCS);
271 setLibcallCallingConv(RTLIB::UNE_F64, CallingConv::ARM_AAPCS);
272 setLibcallCallingConv(RTLIB::OLT_F64, CallingConv::ARM_AAPCS);
273 setLibcallCallingConv(RTLIB::OLE_F64, CallingConv::ARM_AAPCS);
274 setLibcallCallingConv(RTLIB::OGE_F64, CallingConv::ARM_AAPCS);
275 setLibcallCallingConv(RTLIB::OGT_F64, CallingConv::ARM_AAPCS);
276 setLibcallCallingConv(RTLIB::UO_F64, CallingConv::ARM_AAPCS);
277 setLibcallCallingConv(RTLIB::O_F64, CallingConv::ARM_AAPCS);
279 // Single-precision floating-point arithmetic helper functions
280 // RTABI chapter 4.1.2, Table 4
281 setLibcallName(RTLIB::ADD_F32, "__aeabi_fadd");
282 setLibcallName(RTLIB::DIV_F32, "__aeabi_fdiv");
283 setLibcallName(RTLIB::MUL_F32, "__aeabi_fmul");
284 setLibcallName(RTLIB::SUB_F32, "__aeabi_fsub");
285 setLibcallCallingConv(RTLIB::ADD_F32, CallingConv::ARM_AAPCS);
286 setLibcallCallingConv(RTLIB::DIV_F32, CallingConv::ARM_AAPCS);
287 setLibcallCallingConv(RTLIB::MUL_F32, CallingConv::ARM_AAPCS);
288 setLibcallCallingConv(RTLIB::SUB_F32, CallingConv::ARM_AAPCS);
290 // Single-precision floating-point comparison helper functions
291 // RTABI chapter 4.1.2, Table 5
292 setLibcallName(RTLIB::OEQ_F32, "__aeabi_fcmpeq");
293 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
294 setLibcallName(RTLIB::UNE_F32, "__aeabi_fcmpeq");
295 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETEQ);
296 setLibcallName(RTLIB::OLT_F32, "__aeabi_fcmplt");
297 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
298 setLibcallName(RTLIB::OLE_F32, "__aeabi_fcmple");
299 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
300 setLibcallName(RTLIB::OGE_F32, "__aeabi_fcmpge");
301 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
302 setLibcallName(RTLIB::OGT_F32, "__aeabi_fcmpgt");
303 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
304 setLibcallName(RTLIB::UO_F32, "__aeabi_fcmpun");
305 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
306 setLibcallName(RTLIB::O_F32, "__aeabi_fcmpun");
307 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
308 setLibcallCallingConv(RTLIB::OEQ_F32, CallingConv::ARM_AAPCS);
309 setLibcallCallingConv(RTLIB::UNE_F32, CallingConv::ARM_AAPCS);
310 setLibcallCallingConv(RTLIB::OLT_F32, CallingConv::ARM_AAPCS);
311 setLibcallCallingConv(RTLIB::OLE_F32, CallingConv::ARM_AAPCS);
312 setLibcallCallingConv(RTLIB::OGE_F32, CallingConv::ARM_AAPCS);
313 setLibcallCallingConv(RTLIB::OGT_F32, CallingConv::ARM_AAPCS);
314 setLibcallCallingConv(RTLIB::UO_F32, CallingConv::ARM_AAPCS);
315 setLibcallCallingConv(RTLIB::O_F32, CallingConv::ARM_AAPCS);
317 // Floating-point to integer conversions.
318 // RTABI chapter 4.1.2, Table 6
319 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz");
320 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz");
321 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz");
322 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz");
323 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz");
324 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz");
325 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz");
326 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz");
327 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I32, CallingConv::ARM_AAPCS);
328 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I32, CallingConv::ARM_AAPCS);
329 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I64, CallingConv::ARM_AAPCS);
330 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::ARM_AAPCS);
331 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I32, CallingConv::ARM_AAPCS);
332 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I32, CallingConv::ARM_AAPCS);
333 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I64, CallingConv::ARM_AAPCS);
334 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::ARM_AAPCS);
336 // Conversions between floating types.
337 // RTABI chapter 4.1.2, Table 7
338 setLibcallName(RTLIB::FPROUND_F64_F32, "__aeabi_d2f");
339 setLibcallName(RTLIB::FPEXT_F32_F64, "__aeabi_f2d");
340 setLibcallCallingConv(RTLIB::FPROUND_F64_F32, CallingConv::ARM_AAPCS);
341 setLibcallCallingConv(RTLIB::FPEXT_F32_F64, CallingConv::ARM_AAPCS);
343 // Integer to floating-point conversions.
344 // RTABI chapter 4.1.2, Table 8
345 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d");
346 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d");
347 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d");
348 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d");
349 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f");
350 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f");
351 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f");
352 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f");
353 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
354 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
355 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
356 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
357 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
358 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
359 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
360 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
362 // Long long helper functions
363 // RTABI chapter 4.2, Table 9
364 setLibcallName(RTLIB::MUL_I64, "__aeabi_lmul");
365 setLibcallName(RTLIB::SDIV_I64, "__aeabi_ldivmod");
366 setLibcallName(RTLIB::UDIV_I64, "__aeabi_uldivmod");
367 setLibcallName(RTLIB::SHL_I64, "__aeabi_llsl");
368 setLibcallName(RTLIB::SRL_I64, "__aeabi_llsr");
369 setLibcallName(RTLIB::SRA_I64, "__aeabi_lasr");
370 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::ARM_AAPCS);
371 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::ARM_AAPCS);
372 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::ARM_AAPCS);
373 setLibcallCallingConv(RTLIB::SHL_I64, CallingConv::ARM_AAPCS);
374 setLibcallCallingConv(RTLIB::SRL_I64, CallingConv::ARM_AAPCS);
375 setLibcallCallingConv(RTLIB::SRA_I64, CallingConv::ARM_AAPCS);
377 // Integer division functions
378 // RTABI chapter 4.3.1
379 setLibcallName(RTLIB::SDIV_I8, "__aeabi_idiv");
380 setLibcallName(RTLIB::SDIV_I16, "__aeabi_idiv");
381 setLibcallName(RTLIB::SDIV_I32, "__aeabi_idiv");
382 setLibcallName(RTLIB::UDIV_I8, "__aeabi_uidiv");
383 setLibcallName(RTLIB::UDIV_I16, "__aeabi_uidiv");
384 setLibcallName(RTLIB::UDIV_I32, "__aeabi_uidiv");
385 setLibcallCallingConv(RTLIB::SDIV_I8, CallingConv::ARM_AAPCS);
386 setLibcallCallingConv(RTLIB::SDIV_I16, CallingConv::ARM_AAPCS);
387 setLibcallCallingConv(RTLIB::SDIV_I32, CallingConv::ARM_AAPCS);
388 setLibcallCallingConv(RTLIB::UDIV_I8, CallingConv::ARM_AAPCS);
389 setLibcallCallingConv(RTLIB::UDIV_I16, CallingConv::ARM_AAPCS);
390 setLibcallCallingConv(RTLIB::UDIV_I32, CallingConv::ARM_AAPCS);
393 if (Subtarget->isThumb1Only())
394 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
396 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
397 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
398 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
399 if (!Subtarget->isFPOnlySP())
400 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
402 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
405 if (Subtarget->hasNEON()) {
406 addDRTypeForNEON(MVT::v2f32);
407 addDRTypeForNEON(MVT::v8i8);
408 addDRTypeForNEON(MVT::v4i16);
409 addDRTypeForNEON(MVT::v2i32);
410 addDRTypeForNEON(MVT::v1i64);
412 addQRTypeForNEON(MVT::v4f32);
413 addQRTypeForNEON(MVT::v2f64);
414 addQRTypeForNEON(MVT::v16i8);
415 addQRTypeForNEON(MVT::v8i16);
416 addQRTypeForNEON(MVT::v4i32);
417 addQRTypeForNEON(MVT::v2i64);
419 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
420 // neither Neon nor VFP support any arithmetic operations on it.
421 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
422 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
423 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
424 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
425 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
426 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
427 setOperationAction(ISD::VSETCC, MVT::v2f64, Expand);
428 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
429 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
430 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
431 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
432 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
433 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
434 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
435 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
436 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
437 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
438 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
439 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
440 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
441 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
442 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
443 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
444 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
446 setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand);
448 // Neon does not support some operations on v1i64 and v2i64 types.
449 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
450 // Custom handling for some quad-vector types to detect VMULL.
451 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
452 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
453 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
454 setOperationAction(ISD::VSETCC, MVT::v1i64, Expand);
455 setOperationAction(ISD::VSETCC, MVT::v2i64, Expand);
457 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
458 setTargetDAGCombine(ISD::SHL);
459 setTargetDAGCombine(ISD::SRL);
460 setTargetDAGCombine(ISD::SRA);
461 setTargetDAGCombine(ISD::SIGN_EXTEND);
462 setTargetDAGCombine(ISD::ZERO_EXTEND);
463 setTargetDAGCombine(ISD::ANY_EXTEND);
464 setTargetDAGCombine(ISD::SELECT_CC);
465 setTargetDAGCombine(ISD::BUILD_VECTOR);
466 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
469 computeRegisterProperties();
471 // ARM does not have f32 extending load.
472 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
474 // ARM does not have i1 sign extending load.
475 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
477 // ARM supports all 4 flavors of integer indexed load / store.
478 if (!Subtarget->isThumb1Only()) {
479 for (unsigned im = (unsigned)ISD::PRE_INC;
480 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
481 setIndexedLoadAction(im, MVT::i1, Legal);
482 setIndexedLoadAction(im, MVT::i8, Legal);
483 setIndexedLoadAction(im, MVT::i16, Legal);
484 setIndexedLoadAction(im, MVT::i32, Legal);
485 setIndexedStoreAction(im, MVT::i1, Legal);
486 setIndexedStoreAction(im, MVT::i8, Legal);
487 setIndexedStoreAction(im, MVT::i16, Legal);
488 setIndexedStoreAction(im, MVT::i32, Legal);
492 // i64 operation support.
493 if (Subtarget->isThumb1Only()) {
494 setOperationAction(ISD::MUL, MVT::i64, Expand);
495 setOperationAction(ISD::MULHU, MVT::i32, Expand);
496 setOperationAction(ISD::MULHS, MVT::i32, Expand);
497 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
498 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
500 setOperationAction(ISD::MUL, MVT::i64, Expand);
501 setOperationAction(ISD::MULHU, MVT::i32, Expand);
502 if (!Subtarget->hasV6Ops())
503 setOperationAction(ISD::MULHS, MVT::i32, Expand);
505 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
506 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
507 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
508 setOperationAction(ISD::SRL, MVT::i64, Custom);
509 setOperationAction(ISD::SRA, MVT::i64, Custom);
511 // ARM does not have ROTL.
512 setOperationAction(ISD::ROTL, MVT::i32, Expand);
513 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
514 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
515 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
516 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
518 // Only ARMv6 has BSWAP.
519 if (!Subtarget->hasV6Ops())
520 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
522 // These are expanded into libcalls.
523 if (!Subtarget->hasDivide() || !Subtarget->isThumb2()) {
524 // v7M has a hardware divider
525 setOperationAction(ISD::SDIV, MVT::i32, Expand);
526 setOperationAction(ISD::UDIV, MVT::i32, Expand);
528 setOperationAction(ISD::SREM, MVT::i32, Expand);
529 setOperationAction(ISD::UREM, MVT::i32, Expand);
530 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
531 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
533 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
534 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
535 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
536 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
537 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
539 setOperationAction(ISD::TRAP, MVT::Other, Legal);
541 // Use the default implementation.
542 setOperationAction(ISD::VASTART, MVT::Other, Custom);
543 setOperationAction(ISD::VAARG, MVT::Other, Expand);
544 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
545 setOperationAction(ISD::VAEND, MVT::Other, Expand);
546 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
547 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
548 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
549 // FIXME: Shouldn't need this, since no register is used, but the legalizer
550 // doesn't yet know how to not do that for SjLj.
551 setExceptionSelectorRegister(ARM::R0);
552 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
553 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
554 // the default expansion.
555 if (Subtarget->hasDataBarrier() ||
556 (Subtarget->hasV6Ops() && !Subtarget->isThumb())) {
557 // membarrier needs custom lowering; the rest are legal and handled
559 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
561 // Set them all for expansion, which will force libcalls.
562 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
563 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Expand);
564 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Expand);
565 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
566 setOperationAction(ISD::ATOMIC_SWAP, MVT::i8, Expand);
567 setOperationAction(ISD::ATOMIC_SWAP, MVT::i16, Expand);
568 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
569 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i8, Expand);
570 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i16, Expand);
571 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
572 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Expand);
573 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Expand);
574 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
575 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i8, Expand);
576 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i16, Expand);
577 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
578 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i8, Expand);
579 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i16, Expand);
580 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
581 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i8, Expand);
582 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i16, Expand);
583 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
584 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i8, Expand);
585 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i16, Expand);
586 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
587 // Since the libcalls include locking, fold in the fences
588 setShouldFoldAtomicFences(true);
590 // 64-bit versions are always libcalls (for now)
591 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Expand);
592 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Expand);
593 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Expand);
594 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Expand);
595 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Expand);
596 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Expand);
597 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Expand);
598 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Expand);
600 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
602 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
603 if (!Subtarget->hasV6Ops()) {
604 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
605 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
607 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
609 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
610 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
611 // iff target supports vfp2.
612 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
613 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
616 // We want to custom lower some of our intrinsics.
617 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
618 if (Subtarget->isTargetDarwin()) {
619 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
620 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
621 setOperationAction(ISD::EH_SJLJ_DISPATCHSETUP, MVT::Other, Custom);
624 setOperationAction(ISD::SETCC, MVT::i32, Expand);
625 setOperationAction(ISD::SETCC, MVT::f32, Expand);
626 setOperationAction(ISD::SETCC, MVT::f64, Expand);
627 setOperationAction(ISD::SELECT, MVT::i32, Custom);
628 setOperationAction(ISD::SELECT, MVT::f32, Custom);
629 setOperationAction(ISD::SELECT, MVT::f64, Custom);
630 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
631 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
632 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
634 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
635 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
636 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
637 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
638 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
640 // We don't support sin/cos/fmod/copysign/pow
641 setOperationAction(ISD::FSIN, MVT::f64, Expand);
642 setOperationAction(ISD::FSIN, MVT::f32, Expand);
643 setOperationAction(ISD::FCOS, MVT::f32, Expand);
644 setOperationAction(ISD::FCOS, MVT::f64, Expand);
645 setOperationAction(ISD::FREM, MVT::f64, Expand);
646 setOperationAction(ISD::FREM, MVT::f32, Expand);
647 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
648 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
649 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
651 setOperationAction(ISD::FPOW, MVT::f64, Expand);
652 setOperationAction(ISD::FPOW, MVT::f32, Expand);
654 // Various VFP goodness
655 if (!UseSoftFloat && !Subtarget->isThumb1Only()) {
656 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
657 if (Subtarget->hasVFP2()) {
658 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
659 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
660 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
661 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
663 // Special handling for half-precision FP.
664 if (!Subtarget->hasFP16()) {
665 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
666 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand);
670 // We have target-specific dag combine patterns for the following nodes:
671 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
672 setTargetDAGCombine(ISD::ADD);
673 setTargetDAGCombine(ISD::SUB);
674 setTargetDAGCombine(ISD::MUL);
676 if (Subtarget->hasV6T2Ops() || Subtarget->hasNEON())
677 setTargetDAGCombine(ISD::OR);
678 if (Subtarget->hasNEON())
679 setTargetDAGCombine(ISD::AND);
681 setStackPointerRegisterToSaveRestore(ARM::SP);
683 if (UseSoftFloat || Subtarget->isThumb1Only() || !Subtarget->hasVFP2())
684 setSchedulingPreference(Sched::RegPressure);
686 setSchedulingPreference(Sched::Hybrid);
688 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
690 // On ARM arguments smaller than 4 bytes are extended, so all arguments
691 // are at least 4 bytes aligned.
692 setMinStackArgumentAlignment(4);
694 benefitFromCodePlacementOpt = true;
697 std::pair<const TargetRegisterClass*, uint8_t>
698 ARMTargetLowering::findRepresentativeClass(EVT VT) const{
699 const TargetRegisterClass *RRC = 0;
701 switch (VT.getSimpleVT().SimpleTy) {
703 return TargetLowering::findRepresentativeClass(VT);
704 // Use DPR as representative register class for all floating point
705 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
706 // the cost is 1 for both f32 and f64.
707 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
708 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
709 RRC = ARM::DPRRegisterClass;
711 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
712 case MVT::v4f32: case MVT::v2f64:
713 RRC = ARM::DPRRegisterClass;
717 RRC = ARM::DPRRegisterClass;
721 RRC = ARM::DPRRegisterClass;
725 return std::make_pair(RRC, Cost);
728 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
731 case ARMISD::Wrapper: return "ARMISD::Wrapper";
732 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
733 case ARMISD::CALL: return "ARMISD::CALL";
734 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
735 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
736 case ARMISD::tCALL: return "ARMISD::tCALL";
737 case ARMISD::BRCOND: return "ARMISD::BRCOND";
738 case ARMISD::BR_JT: return "ARMISD::BR_JT";
739 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
740 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
741 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
742 case ARMISD::CMP: return "ARMISD::CMP";
743 case ARMISD::CMPZ: return "ARMISD::CMPZ";
744 case ARMISD::CMPFP: return "ARMISD::CMPFP";
745 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
746 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
747 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
748 case ARMISD::CMOV: return "ARMISD::CMOV";
749 case ARMISD::CNEG: return "ARMISD::CNEG";
751 case ARMISD::RBIT: return "ARMISD::RBIT";
753 case ARMISD::FTOSI: return "ARMISD::FTOSI";
754 case ARMISD::FTOUI: return "ARMISD::FTOUI";
755 case ARMISD::SITOF: return "ARMISD::SITOF";
756 case ARMISD::UITOF: return "ARMISD::UITOF";
758 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
759 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
760 case ARMISD::RRX: return "ARMISD::RRX";
762 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
763 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
765 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
766 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
767 case ARMISD::EH_SJLJ_DISPATCHSETUP:return "ARMISD::EH_SJLJ_DISPATCHSETUP";
769 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
771 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
773 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
775 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER";
776 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
778 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
780 case ARMISD::VCEQ: return "ARMISD::VCEQ";
781 case ARMISD::VCGE: return "ARMISD::VCGE";
782 case ARMISD::VCGEU: return "ARMISD::VCGEU";
783 case ARMISD::VCGT: return "ARMISD::VCGT";
784 case ARMISD::VCGTU: return "ARMISD::VCGTU";
785 case ARMISD::VTST: return "ARMISD::VTST";
787 case ARMISD::VSHL: return "ARMISD::VSHL";
788 case ARMISD::VSHRs: return "ARMISD::VSHRs";
789 case ARMISD::VSHRu: return "ARMISD::VSHRu";
790 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
791 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
792 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
793 case ARMISD::VSHRN: return "ARMISD::VSHRN";
794 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
795 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
796 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
797 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
798 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
799 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
800 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
801 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
802 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
803 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
804 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
805 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
806 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
807 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
808 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
809 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
810 case ARMISD::VDUP: return "ARMISD::VDUP";
811 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
812 case ARMISD::VEXT: return "ARMISD::VEXT";
813 case ARMISD::VREV64: return "ARMISD::VREV64";
814 case ARMISD::VREV32: return "ARMISD::VREV32";
815 case ARMISD::VREV16: return "ARMISD::VREV16";
816 case ARMISD::VZIP: return "ARMISD::VZIP";
817 case ARMISD::VUZP: return "ARMISD::VUZP";
818 case ARMISD::VTRN: return "ARMISD::VTRN";
819 case ARMISD::VMULLs: return "ARMISD::VMULLs";
820 case ARMISD::VMULLu: return "ARMISD::VMULLu";
821 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
822 case ARMISD::FMAX: return "ARMISD::FMAX";
823 case ARMISD::FMIN: return "ARMISD::FMIN";
824 case ARMISD::BFI: return "ARMISD::BFI";
825 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
826 case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
827 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
828 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
829 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
833 /// getRegClassFor - Return the register class that should be used for the
834 /// specified value type.
835 TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const {
836 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
837 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
838 // load / store 4 to 8 consecutive D registers.
839 if (Subtarget->hasNEON()) {
840 if (VT == MVT::v4i64)
841 return ARM::QQPRRegisterClass;
842 else if (VT == MVT::v8i64)
843 return ARM::QQQQPRRegisterClass;
845 return TargetLowering::getRegClassFor(VT);
848 // Create a fast isel object.
850 ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
851 return ARM::createFastISel(funcInfo);
854 /// getFunctionAlignment - Return the Log2 alignment of this function.
855 unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
856 return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 1 : 2;
859 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
860 /// be used for loads / stores from the global.
861 unsigned ARMTargetLowering::getMaximalGlobalOffset() const {
862 return (Subtarget->isThumb1Only() ? 127 : 4095);
865 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
866 unsigned NumVals = N->getNumValues();
868 return Sched::RegPressure;
870 for (unsigned i = 0; i != NumVals; ++i) {
871 EVT VT = N->getValueType(i);
872 if (VT == MVT::Flag || VT == MVT::Other)
874 if (VT.isFloatingPoint() || VT.isVector())
875 return Sched::Latency;
878 if (!N->isMachineOpcode())
879 return Sched::RegPressure;
881 // Load are scheduled for latency even if there instruction itinerary
883 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
884 const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
886 if (TID.getNumDefs() == 0)
887 return Sched::RegPressure;
888 if (!Itins->isEmpty() &&
889 Itins->getOperandCycle(TID.getSchedClass(), 0) > 2)
890 return Sched::Latency;
892 return Sched::RegPressure;
896 ARMTargetLowering::getRegPressureLimit(const TargetRegisterClass *RC,
897 MachineFunction &MF) const {
898 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
900 switch (RC->getID()) {
903 case ARM::tGPRRegClassID:
904 return TFI->hasFP(MF) ? 4 : 5;
905 case ARM::GPRRegClassID: {
906 unsigned FP = TFI->hasFP(MF) ? 1 : 0;
907 return 10 - FP - (Subtarget->isR9Reserved() ? 1 : 0);
909 case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
910 case ARM::DPRRegClassID:
915 //===----------------------------------------------------------------------===//
917 //===----------------------------------------------------------------------===//
919 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
920 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
922 default: llvm_unreachable("Unknown condition code!");
923 case ISD::SETNE: return ARMCC::NE;
924 case ISD::SETEQ: return ARMCC::EQ;
925 case ISD::SETGT: return ARMCC::GT;
926 case ISD::SETGE: return ARMCC::GE;
927 case ISD::SETLT: return ARMCC::LT;
928 case ISD::SETLE: return ARMCC::LE;
929 case ISD::SETUGT: return ARMCC::HI;
930 case ISD::SETUGE: return ARMCC::HS;
931 case ISD::SETULT: return ARMCC::LO;
932 case ISD::SETULE: return ARMCC::LS;
936 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
937 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
938 ARMCC::CondCodes &CondCode2) {
939 CondCode2 = ARMCC::AL;
941 default: llvm_unreachable("Unknown FP condition!");
943 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
945 case ISD::SETOGT: CondCode = ARMCC::GT; break;
947 case ISD::SETOGE: CondCode = ARMCC::GE; break;
948 case ISD::SETOLT: CondCode = ARMCC::MI; break;
949 case ISD::SETOLE: CondCode = ARMCC::LS; break;
950 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
951 case ISD::SETO: CondCode = ARMCC::VC; break;
952 case ISD::SETUO: CondCode = ARMCC::VS; break;
953 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
954 case ISD::SETUGT: CondCode = ARMCC::HI; break;
955 case ISD::SETUGE: CondCode = ARMCC::PL; break;
957 case ISD::SETULT: CondCode = ARMCC::LT; break;
959 case ISD::SETULE: CondCode = ARMCC::LE; break;
961 case ISD::SETUNE: CondCode = ARMCC::NE; break;
965 //===----------------------------------------------------------------------===//
966 // Calling Convention Implementation
967 //===----------------------------------------------------------------------===//
969 #include "ARMGenCallingConv.inc"
971 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
972 /// given CallingConvention value.
973 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
975 bool isVarArg) const {
978 llvm_unreachable("Unsupported calling convention");
979 case CallingConv::Fast:
980 if (Subtarget->hasVFP2() && !isVarArg) {
981 if (!Subtarget->isAAPCS_ABI())
982 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
983 // For AAPCS ABI targets, just use VFP variant of the calling convention.
984 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
987 case CallingConv::C: {
988 // Use target triple & subtarget features to do actual dispatch.
989 if (!Subtarget->isAAPCS_ABI())
990 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
991 else if (Subtarget->hasVFP2() &&
992 FloatABIType == FloatABI::Hard && !isVarArg)
993 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
994 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
996 case CallingConv::ARM_AAPCS_VFP:
997 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
998 case CallingConv::ARM_AAPCS:
999 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1000 case CallingConv::ARM_APCS:
1001 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1005 /// LowerCallResult - Lower the result values of a call into the
1006 /// appropriate copies out of appropriate physical registers.
1008 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1009 CallingConv::ID CallConv, bool isVarArg,
1010 const SmallVectorImpl<ISD::InputArg> &Ins,
1011 DebugLoc dl, SelectionDAG &DAG,
1012 SmallVectorImpl<SDValue> &InVals) const {
1014 // Assign locations to each value returned by this call.
1015 SmallVector<CCValAssign, 16> RVLocs;
1016 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1017 RVLocs, *DAG.getContext());
1018 CCInfo.AnalyzeCallResult(Ins,
1019 CCAssignFnForNode(CallConv, /* Return*/ true,
1022 // Copy all of the result registers out of their specified physreg.
1023 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1024 CCValAssign VA = RVLocs[i];
1027 if (VA.needsCustom()) {
1028 // Handle f64 or half of a v2f64.
1029 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1031 Chain = Lo.getValue(1);
1032 InFlag = Lo.getValue(2);
1033 VA = RVLocs[++i]; // skip ahead to next loc
1034 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1036 Chain = Hi.getValue(1);
1037 InFlag = Hi.getValue(2);
1038 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1040 if (VA.getLocVT() == MVT::v2f64) {
1041 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1042 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1043 DAG.getConstant(0, MVT::i32));
1045 VA = RVLocs[++i]; // skip ahead to next loc
1046 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1047 Chain = Lo.getValue(1);
1048 InFlag = Lo.getValue(2);
1049 VA = RVLocs[++i]; // skip ahead to next loc
1050 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1051 Chain = Hi.getValue(1);
1052 InFlag = Hi.getValue(2);
1053 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1054 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1055 DAG.getConstant(1, MVT::i32));
1058 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1060 Chain = Val.getValue(1);
1061 InFlag = Val.getValue(2);
1064 switch (VA.getLocInfo()) {
1065 default: llvm_unreachable("Unknown loc info!");
1066 case CCValAssign::Full: break;
1067 case CCValAssign::BCvt:
1068 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1072 InVals.push_back(Val);
1078 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1079 /// by "Src" to address "Dst" of size "Size". Alignment information is
1080 /// specified by the specific parameter attribute. The copy will be passed as
1081 /// a byval function parameter.
1082 /// Sometimes what we are copying is the end of a larger object, the part that
1083 /// does not fit in registers.
1085 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1086 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1088 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1089 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1090 /*isVolatile=*/false, /*AlwaysInline=*/false,
1091 MachinePointerInfo(0), MachinePointerInfo(0));
1094 /// LowerMemOpCallTo - Store the argument to the stack.
1096 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
1097 SDValue StackPtr, SDValue Arg,
1098 DebugLoc dl, SelectionDAG &DAG,
1099 const CCValAssign &VA,
1100 ISD::ArgFlagsTy Flags) const {
1101 unsigned LocMemOffset = VA.getLocMemOffset();
1102 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1103 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1104 if (Flags.isByVal())
1105 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1107 return DAG.getStore(Chain, dl, Arg, PtrOff,
1108 MachinePointerInfo::getStack(LocMemOffset),
1112 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
1113 SDValue Chain, SDValue &Arg,
1114 RegsToPassVector &RegsToPass,
1115 CCValAssign &VA, CCValAssign &NextVA,
1117 SmallVector<SDValue, 8> &MemOpChains,
1118 ISD::ArgFlagsTy Flags) const {
1120 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1121 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1122 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
1124 if (NextVA.isRegLoc())
1125 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
1127 assert(NextVA.isMemLoc());
1128 if (StackPtr.getNode() == 0)
1129 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1131 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
1137 /// LowerCall - Lowering a call into a callseq_start <-
1138 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1141 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1142 CallingConv::ID CallConv, bool isVarArg,
1144 const SmallVectorImpl<ISD::OutputArg> &Outs,
1145 const SmallVectorImpl<SDValue> &OutVals,
1146 const SmallVectorImpl<ISD::InputArg> &Ins,
1147 DebugLoc dl, SelectionDAG &DAG,
1148 SmallVectorImpl<SDValue> &InVals) const {
1149 MachineFunction &MF = DAG.getMachineFunction();
1150 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1151 bool IsSibCall = false;
1152 // Temporarily disable tail calls so things don't break.
1153 if (!EnableARMTailCalls)
1156 // Check if it's really possible to do a tail call.
1157 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1158 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1159 Outs, OutVals, Ins, DAG);
1160 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1161 // detected sibcalls.
1168 // Analyze operands of the call, assigning locations to each operand.
1169 SmallVector<CCValAssign, 16> ArgLocs;
1170 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1172 CCInfo.AnalyzeCallOperands(Outs,
1173 CCAssignFnForNode(CallConv, /* Return*/ false,
1176 // Get a count of how many bytes are to be pushed on the stack.
1177 unsigned NumBytes = CCInfo.getNextStackOffset();
1179 // For tail calls, memory operands are available in our caller's stack.
1183 // Adjust the stack pointer for the new arguments...
1184 // These operations are automatically eliminated by the prolog/epilog pass
1186 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1188 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1190 RegsToPassVector RegsToPass;
1191 SmallVector<SDValue, 8> MemOpChains;
1193 // Walk the register/memloc assignments, inserting copies/loads. In the case
1194 // of tail call optimization, arguments are handled later.
1195 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1197 ++i, ++realArgIdx) {
1198 CCValAssign &VA = ArgLocs[i];
1199 SDValue Arg = OutVals[realArgIdx];
1200 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1202 // Promote the value if needed.
1203 switch (VA.getLocInfo()) {
1204 default: llvm_unreachable("Unknown loc info!");
1205 case CCValAssign::Full: break;
1206 case CCValAssign::SExt:
1207 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1209 case CCValAssign::ZExt:
1210 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1212 case CCValAssign::AExt:
1213 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1215 case CCValAssign::BCvt:
1216 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1220 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1221 if (VA.needsCustom()) {
1222 if (VA.getLocVT() == MVT::v2f64) {
1223 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1224 DAG.getConstant(0, MVT::i32));
1225 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1226 DAG.getConstant(1, MVT::i32));
1228 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1229 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1231 VA = ArgLocs[++i]; // skip ahead to next loc
1232 if (VA.isRegLoc()) {
1233 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1234 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1236 assert(VA.isMemLoc());
1238 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1239 dl, DAG, VA, Flags));
1242 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1243 StackPtr, MemOpChains, Flags);
1245 } else if (VA.isRegLoc()) {
1246 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1247 } else if (!IsSibCall) {
1248 assert(VA.isMemLoc());
1250 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1251 dl, DAG, VA, Flags));
1255 if (!MemOpChains.empty())
1256 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1257 &MemOpChains[0], MemOpChains.size());
1259 // Build a sequence of copy-to-reg nodes chained together with token chain
1260 // and flag operands which copy the outgoing args into the appropriate regs.
1262 // Tail call byval lowering might overwrite argument registers so in case of
1263 // tail call optimization the copies to registers are lowered later.
1265 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1266 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1267 RegsToPass[i].second, InFlag);
1268 InFlag = Chain.getValue(1);
1271 // For tail calls lower the arguments to the 'real' stack slot.
1273 // Force all the incoming stack arguments to be loaded from the stack
1274 // before any new outgoing arguments are stored to the stack, because the
1275 // outgoing stack slots may alias the incoming argument stack slots, and
1276 // the alias isn't otherwise explicit. This is slightly more conservative
1277 // than necessary, because it means that each store effectively depends
1278 // on every argument instead of just those arguments it would clobber.
1280 // Do not flag preceeding copytoreg stuff together with the following stuff.
1282 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1283 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1284 RegsToPass[i].second, InFlag);
1285 InFlag = Chain.getValue(1);
1290 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1291 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1292 // node so that legalize doesn't hack it.
1293 bool isDirect = false;
1294 bool isARMFunc = false;
1295 bool isLocalARMFunc = false;
1296 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1298 if (EnableARMLongCalls) {
1299 assert (getTargetMachine().getRelocationModel() == Reloc::Static
1300 && "long-calls with non-static relocation model!");
1301 // Handle a global address or an external symbol. If it's not one of
1302 // those, the target's already in a register, so we don't need to do
1304 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1305 const GlobalValue *GV = G->getGlobal();
1306 // Create a constant pool entry for the callee address
1307 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1308 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1311 // Get the address of the callee into a register
1312 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1313 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1314 Callee = DAG.getLoad(getPointerTy(), dl,
1315 DAG.getEntryNode(), CPAddr,
1316 MachinePointerInfo::getConstantPool(),
1318 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1319 const char *Sym = S->getSymbol();
1321 // Create a constant pool entry for the callee address
1322 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1323 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1324 Sym, ARMPCLabelIndex, 0);
1325 // Get the address of the callee into a register
1326 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1327 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1328 Callee = DAG.getLoad(getPointerTy(), dl,
1329 DAG.getEntryNode(), CPAddr,
1330 MachinePointerInfo::getConstantPool(),
1333 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1334 const GlobalValue *GV = G->getGlobal();
1336 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1337 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
1338 getTargetMachine().getRelocationModel() != Reloc::Static;
1339 isARMFunc = !Subtarget->isThumb() || isStub;
1340 // ARM call to a local ARM function is predicable.
1341 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
1342 // tBX takes a register source operand.
1343 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1344 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1345 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1348 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1349 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1350 Callee = DAG.getLoad(getPointerTy(), dl,
1351 DAG.getEntryNode(), CPAddr,
1352 MachinePointerInfo::getConstantPool(),
1354 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1355 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1356 getPointerTy(), Callee, PICLabel);
1358 // On ELF targets for PIC code, direct calls should go through the PLT
1359 unsigned OpFlags = 0;
1360 if (Subtarget->isTargetELF() &&
1361 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1362 OpFlags = ARMII::MO_PLT;
1363 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
1365 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1367 bool isStub = Subtarget->isTargetDarwin() &&
1368 getTargetMachine().getRelocationModel() != Reloc::Static;
1369 isARMFunc = !Subtarget->isThumb() || isStub;
1370 // tBX takes a register source operand.
1371 const char *Sym = S->getSymbol();
1372 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1373 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1374 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1375 Sym, ARMPCLabelIndex, 4);
1376 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1377 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1378 Callee = DAG.getLoad(getPointerTy(), dl,
1379 DAG.getEntryNode(), CPAddr,
1380 MachinePointerInfo::getConstantPool(),
1382 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1383 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1384 getPointerTy(), Callee, PICLabel);
1386 unsigned OpFlags = 0;
1387 // On ELF targets for PIC code, direct calls should go through the PLT
1388 if (Subtarget->isTargetELF() &&
1389 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1390 OpFlags = ARMII::MO_PLT;
1391 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags);
1395 // FIXME: handle tail calls differently.
1397 if (Subtarget->isThumb()) {
1398 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1399 CallOpc = ARMISD::CALL_NOLINK;
1401 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1403 CallOpc = (isDirect || Subtarget->hasV5TOps())
1404 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
1405 : ARMISD::CALL_NOLINK;
1408 std::vector<SDValue> Ops;
1409 Ops.push_back(Chain);
1410 Ops.push_back(Callee);
1412 // Add argument registers to the end of the list so that they are known live
1414 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1415 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1416 RegsToPass[i].second.getValueType()));
1418 if (InFlag.getNode())
1419 Ops.push_back(InFlag);
1421 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1423 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
1425 // Returns a chain and a flag for retval copy to use.
1426 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
1427 InFlag = Chain.getValue(1);
1429 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1430 DAG.getIntPtrConstant(0, true), InFlag);
1432 InFlag = Chain.getValue(1);
1434 // Handle result values, copying them out of physregs into vregs that we
1436 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1440 /// MatchingStackOffset - Return true if the given stack call argument is
1441 /// already available in the same position (relatively) of the caller's
1442 /// incoming argument stack.
1444 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1445 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1446 const ARMInstrInfo *TII) {
1447 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
1449 if (Arg.getOpcode() == ISD::CopyFromReg) {
1450 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
1451 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR))
1453 MachineInstr *Def = MRI->getVRegDef(VR);
1456 if (!Flags.isByVal()) {
1457 if (!TII->isLoadFromStackSlot(Def, FI))
1462 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
1463 if (Flags.isByVal())
1464 // ByVal argument is passed in as a pointer but it's now being
1465 // dereferenced. e.g.
1466 // define @foo(%struct.X* %A) {
1467 // tail call @bar(%struct.X* byval %A)
1470 SDValue Ptr = Ld->getBasePtr();
1471 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
1474 FI = FINode->getIndex();
1478 assert(FI != INT_MAX);
1479 if (!MFI->isFixedObjectIndex(FI))
1481 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
1484 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1485 /// for tail call optimization. Targets which want to do tail call
1486 /// optimization should implement this function.
1488 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1489 CallingConv::ID CalleeCC,
1491 bool isCalleeStructRet,
1492 bool isCallerStructRet,
1493 const SmallVectorImpl<ISD::OutputArg> &Outs,
1494 const SmallVectorImpl<SDValue> &OutVals,
1495 const SmallVectorImpl<ISD::InputArg> &Ins,
1496 SelectionDAG& DAG) const {
1497 const Function *CallerF = DAG.getMachineFunction().getFunction();
1498 CallingConv::ID CallerCC = CallerF->getCallingConv();
1499 bool CCMatch = CallerCC == CalleeCC;
1501 // Look for obvious safe cases to perform tail call optimization that do not
1502 // require ABI changes. This is what gcc calls sibcall.
1504 // Do not sibcall optimize vararg calls unless the call site is not passing
1506 if (isVarArg && !Outs.empty())
1509 // Also avoid sibcall optimization if either caller or callee uses struct
1510 // return semantics.
1511 if (isCalleeStructRet || isCallerStructRet)
1514 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
1515 // emitEpilogue is not ready for them.
1516 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
1517 // LR. This means if we need to reload LR, it takes an extra instructions,
1518 // which outweighs the value of the tail call; but here we don't know yet
1519 // whether LR is going to be used. Probably the right approach is to
1520 // generate the tail call here and turn it back into CALL/RET in
1521 // emitEpilogue if LR is used.
1523 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
1524 // but we need to make sure there are enough registers; the only valid
1525 // registers are the 4 used for parameters. We don't currently do this
1527 if (Subtarget->isThumb1Only())
1530 // If the calling conventions do not match, then we'd better make sure the
1531 // results are returned in the same way as what the caller expects.
1533 SmallVector<CCValAssign, 16> RVLocs1;
1534 CCState CCInfo1(CalleeCC, false, getTargetMachine(),
1535 RVLocs1, *DAG.getContext());
1536 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
1538 SmallVector<CCValAssign, 16> RVLocs2;
1539 CCState CCInfo2(CallerCC, false, getTargetMachine(),
1540 RVLocs2, *DAG.getContext());
1541 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
1543 if (RVLocs1.size() != RVLocs2.size())
1545 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
1546 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
1548 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
1550 if (RVLocs1[i].isRegLoc()) {
1551 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
1554 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
1560 // If the callee takes no arguments then go on to check the results of the
1562 if (!Outs.empty()) {
1563 // Check if stack adjustment is needed. For now, do not do this if any
1564 // argument is passed on the stack.
1565 SmallVector<CCValAssign, 16> ArgLocs;
1566 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
1567 ArgLocs, *DAG.getContext());
1568 CCInfo.AnalyzeCallOperands(Outs,
1569 CCAssignFnForNode(CalleeCC, false, isVarArg));
1570 if (CCInfo.getNextStackOffset()) {
1571 MachineFunction &MF = DAG.getMachineFunction();
1573 // Check if the arguments are already laid out in the right way as
1574 // the caller's fixed stack objects.
1575 MachineFrameInfo *MFI = MF.getFrameInfo();
1576 const MachineRegisterInfo *MRI = &MF.getRegInfo();
1577 const ARMInstrInfo *TII =
1578 ((ARMTargetMachine&)getTargetMachine()).getInstrInfo();
1579 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1581 ++i, ++realArgIdx) {
1582 CCValAssign &VA = ArgLocs[i];
1583 EVT RegVT = VA.getLocVT();
1584 SDValue Arg = OutVals[realArgIdx];
1585 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1586 if (VA.getLocInfo() == CCValAssign::Indirect)
1588 if (VA.needsCustom()) {
1589 // f64 and vector types are split into multiple registers or
1590 // register/stack-slot combinations. The types will not match
1591 // the registers; give up on memory f64 refs until we figure
1592 // out what to do about this.
1595 if (!ArgLocs[++i].isRegLoc())
1597 if (RegVT == MVT::v2f64) {
1598 if (!ArgLocs[++i].isRegLoc())
1600 if (!ArgLocs[++i].isRegLoc())
1603 } else if (!VA.isRegLoc()) {
1604 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
1616 ARMTargetLowering::LowerReturn(SDValue Chain,
1617 CallingConv::ID CallConv, bool isVarArg,
1618 const SmallVectorImpl<ISD::OutputArg> &Outs,
1619 const SmallVectorImpl<SDValue> &OutVals,
1620 DebugLoc dl, SelectionDAG &DAG) const {
1622 // CCValAssign - represent the assignment of the return value to a location.
1623 SmallVector<CCValAssign, 16> RVLocs;
1625 // CCState - Info about the registers and stack slots.
1626 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
1629 // Analyze outgoing return values.
1630 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1633 // If this is the first return lowered for this function, add
1634 // the regs to the liveout set for the function.
1635 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1636 for (unsigned i = 0; i != RVLocs.size(); ++i)
1637 if (RVLocs[i].isRegLoc())
1638 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1643 // Copy the result values into the output registers.
1644 for (unsigned i = 0, realRVLocIdx = 0;
1646 ++i, ++realRVLocIdx) {
1647 CCValAssign &VA = RVLocs[i];
1648 assert(VA.isRegLoc() && "Can only return in registers!");
1650 SDValue Arg = OutVals[realRVLocIdx];
1652 switch (VA.getLocInfo()) {
1653 default: llvm_unreachable("Unknown loc info!");
1654 case CCValAssign::Full: break;
1655 case CCValAssign::BCvt:
1656 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1660 if (VA.needsCustom()) {
1661 if (VA.getLocVT() == MVT::v2f64) {
1662 // Extract the first half and return it in two registers.
1663 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1664 DAG.getConstant(0, MVT::i32));
1665 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
1666 DAG.getVTList(MVT::i32, MVT::i32), Half);
1668 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1669 Flag = Chain.getValue(1);
1670 VA = RVLocs[++i]; // skip ahead to next loc
1671 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1672 HalfGPRs.getValue(1), Flag);
1673 Flag = Chain.getValue(1);
1674 VA = RVLocs[++i]; // skip ahead to next loc
1676 // Extract the 2nd half and fall through to handle it as an f64 value.
1677 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1678 DAG.getConstant(1, MVT::i32));
1680 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1682 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1683 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1684 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1685 Flag = Chain.getValue(1);
1686 VA = RVLocs[++i]; // skip ahead to next loc
1687 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1690 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1692 // Guarantee that all emitted copies are
1693 // stuck together, avoiding something bad.
1694 Flag = Chain.getValue(1);
1699 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1701 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1706 bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N) const {
1707 if (N->getNumValues() != 1)
1709 if (!N->hasNUsesOfValue(1, 0))
1712 unsigned NumCopies = 0;
1714 SDNode *Use = *N->use_begin();
1715 if (Use->getOpcode() == ISD::CopyToReg) {
1716 Copies[NumCopies++] = Use;
1717 } else if (Use->getOpcode() == ARMISD::VMOVRRD) {
1718 // f64 returned in a pair of GPRs.
1719 for (SDNode::use_iterator UI = Use->use_begin(), UE = Use->use_end();
1721 if (UI->getOpcode() != ISD::CopyToReg)
1723 Copies[UI.getUse().getResNo()] = *UI;
1726 } else if (Use->getOpcode() == ISD::BITCAST) {
1727 // f32 returned in a single GPR.
1728 if (!Use->hasNUsesOfValue(1, 0))
1730 Use = *Use->use_begin();
1731 if (Use->getOpcode() != ISD::CopyToReg || !Use->hasNUsesOfValue(1, 0))
1733 Copies[NumCopies++] = Use;
1738 if (NumCopies != 1 && NumCopies != 2)
1741 bool HasRet = false;
1742 for (unsigned i = 0; i < NumCopies; ++i) {
1743 SDNode *Copy = Copies[i];
1744 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1746 if (UI->getOpcode() == ISD::CopyToReg) {
1748 if (Use == Copies[0] || Use == Copies[1])
1752 if (UI->getOpcode() != ARMISD::RET_FLAG)
1761 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1762 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1763 // one of the above mentioned nodes. It has to be wrapped because otherwise
1764 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1765 // be used to form addressing mode. These wrapped nodes will be selected
1767 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1768 EVT PtrVT = Op.getValueType();
1769 // FIXME there is no actual debug info here
1770 DebugLoc dl = Op.getDebugLoc();
1771 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1773 if (CP->isMachineConstantPoolEntry())
1774 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1775 CP->getAlignment());
1777 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1778 CP->getAlignment());
1779 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1782 unsigned ARMTargetLowering::getJumpTableEncoding() const {
1783 return MachineJumpTableInfo::EK_Inline;
1786 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
1787 SelectionDAG &DAG) const {
1788 MachineFunction &MF = DAG.getMachineFunction();
1789 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1790 unsigned ARMPCLabelIndex = 0;
1791 DebugLoc DL = Op.getDebugLoc();
1792 EVT PtrVT = getPointerTy();
1793 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1794 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1796 if (RelocM == Reloc::Static) {
1797 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
1799 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1800 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1801 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(BA, ARMPCLabelIndex,
1802 ARMCP::CPBlockAddress,
1804 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1806 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
1807 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
1808 MachinePointerInfo::getConstantPool(),
1810 if (RelocM == Reloc::Static)
1812 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1813 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
1816 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
1818 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1819 SelectionDAG &DAG) const {
1820 DebugLoc dl = GA->getDebugLoc();
1821 EVT PtrVT = getPointerTy();
1822 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1823 MachineFunction &MF = DAG.getMachineFunction();
1824 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1825 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1826 ARMConstantPoolValue *CPV =
1827 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1828 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
1829 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1830 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
1831 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
1832 MachinePointerInfo::getConstantPool(),
1834 SDValue Chain = Argument.getValue(1);
1836 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1837 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
1839 // call __tls_get_addr.
1842 Entry.Node = Argument;
1843 Entry.Ty = (const Type *) Type::getInt32Ty(*DAG.getContext());
1844 Args.push_back(Entry);
1845 // FIXME: is there useful debug info available here?
1846 std::pair<SDValue, SDValue> CallResult =
1847 LowerCallTo(Chain, (const Type *) Type::getInt32Ty(*DAG.getContext()),
1848 false, false, false, false,
1849 0, CallingConv::C, false, /*isReturnValueUsed=*/true,
1850 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
1851 return CallResult.first;
1854 // Lower ISD::GlobalTLSAddress using the "initial exec" or
1855 // "local exec" model.
1857 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
1858 SelectionDAG &DAG) const {
1859 const GlobalValue *GV = GA->getGlobal();
1860 DebugLoc dl = GA->getDebugLoc();
1862 SDValue Chain = DAG.getEntryNode();
1863 EVT PtrVT = getPointerTy();
1864 // Get the Thread Pointer
1865 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1867 if (GV->isDeclaration()) {
1868 MachineFunction &MF = DAG.getMachineFunction();
1869 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1870 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1871 // Initial exec model.
1872 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1873 ARMConstantPoolValue *CPV =
1874 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1875 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF, true);
1876 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1877 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1878 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1879 MachinePointerInfo::getConstantPool(),
1881 Chain = Offset.getValue(1);
1883 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1884 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
1886 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1887 MachinePointerInfo::getConstantPool(),
1891 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMCP::TPOFF);
1892 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1893 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1894 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1895 MachinePointerInfo::getConstantPool(),
1899 // The address of the thread local variable is the add of the thread
1900 // pointer with the offset of the variable.
1901 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
1905 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
1906 // TODO: implement the "local dynamic" model
1907 assert(Subtarget->isTargetELF() &&
1908 "TLS not implemented for non-ELF targets");
1909 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1910 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
1911 // otherwise use the "Local Exec" TLS Model
1912 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
1913 return LowerToTLSGeneralDynamicModel(GA, DAG);
1915 return LowerToTLSExecModels(GA, DAG);
1918 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
1919 SelectionDAG &DAG) const {
1920 EVT PtrVT = getPointerTy();
1921 DebugLoc dl = Op.getDebugLoc();
1922 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1923 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1924 if (RelocM == Reloc::PIC_) {
1925 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
1926 ARMConstantPoolValue *CPV =
1927 new ARMConstantPoolValue(GV, UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
1928 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1929 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1930 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1932 MachinePointerInfo::getConstantPool(),
1934 SDValue Chain = Result.getValue(1);
1935 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1936 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
1938 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
1939 MachinePointerInfo::getGOT(), false, false, 0);
1942 // If we have T2 ops, we can materialize the address directly via movt/movw
1943 // pair. This is always cheaper.
1944 if (Subtarget->useMovt()) {
1945 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
1946 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
1948 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1949 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1950 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1951 MachinePointerInfo::getConstantPool(),
1957 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
1958 SelectionDAG &DAG) const {
1959 MachineFunction &MF = DAG.getMachineFunction();
1960 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1961 unsigned ARMPCLabelIndex = 0;
1962 EVT PtrVT = getPointerTy();
1963 DebugLoc dl = Op.getDebugLoc();
1964 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1965 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1967 if (RelocM == Reloc::Static)
1968 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1970 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1971 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8);
1972 ARMConstantPoolValue *CPV =
1973 new ARMConstantPoolValue(GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj);
1974 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1976 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1978 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1979 MachinePointerInfo::getConstantPool(),
1981 SDValue Chain = Result.getValue(1);
1983 if (RelocM == Reloc::PIC_) {
1984 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1985 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1988 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
1989 Result = DAG.getLoad(PtrVT, dl, Chain, Result, MachinePointerInfo::getGOT(),
1995 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
1996 SelectionDAG &DAG) const {
1997 assert(Subtarget->isTargetELF() &&
1998 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
1999 MachineFunction &MF = DAG.getMachineFunction();
2000 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2001 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
2002 EVT PtrVT = getPointerTy();
2003 DebugLoc dl = Op.getDebugLoc();
2004 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2005 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
2006 "_GLOBAL_OFFSET_TABLE_",
2007 ARMPCLabelIndex, PCAdj);
2008 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2009 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2010 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2011 MachinePointerInfo::getConstantPool(),
2013 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2014 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2018 ARMTargetLowering::LowerEH_SJLJ_DISPATCHSETUP(SDValue Op, SelectionDAG &DAG)
2020 DebugLoc dl = Op.getDebugLoc();
2021 return DAG.getNode(ARMISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other,
2022 Op.getOperand(0), Op.getOperand(1));
2026 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
2027 DebugLoc dl = Op.getDebugLoc();
2028 SDValue Val = DAG.getConstant(0, MVT::i32);
2029 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(0),
2030 Op.getOperand(1), Val);
2034 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
2035 DebugLoc dl = Op.getDebugLoc();
2036 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
2037 Op.getOperand(1), DAG.getConstant(0, MVT::i32));
2041 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
2042 const ARMSubtarget *Subtarget) const {
2043 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2044 DebugLoc dl = Op.getDebugLoc();
2046 default: return SDValue(); // Don't custom lower most intrinsics.
2047 case Intrinsic::arm_thread_pointer: {
2048 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2049 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2051 case Intrinsic::eh_sjlj_lsda: {
2052 MachineFunction &MF = DAG.getMachineFunction();
2053 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2054 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
2055 EVT PtrVT = getPointerTy();
2056 DebugLoc dl = Op.getDebugLoc();
2057 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2059 unsigned PCAdj = (RelocM != Reloc::PIC_)
2060 ? 0 : (Subtarget->isThumb() ? 4 : 8);
2061 ARMConstantPoolValue *CPV =
2062 new ARMConstantPoolValue(MF.getFunction(), ARMPCLabelIndex,
2063 ARMCP::CPLSDA, PCAdj);
2064 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2065 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2067 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2068 MachinePointerInfo::getConstantPool(),
2071 if (RelocM == Reloc::PIC_) {
2072 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2073 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2080 static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG,
2081 const ARMSubtarget *Subtarget) {
2082 DebugLoc dl = Op.getDebugLoc();
2083 if (!Subtarget->hasDataBarrier()) {
2084 // Some ARMv6 cpus can support data barriers with an mcr instruction.
2085 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
2087 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&
2088 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!");
2089 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2090 DAG.getConstant(0, MVT::i32));
2093 SDValue Op5 = Op.getOperand(5);
2094 bool isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue() != 0;
2095 unsigned isLL = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
2096 unsigned isLS = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
2097 bool isOnlyStoreBarrier = (isLL == 0 && isLS == 0);
2099 ARM_MB::MemBOpt DMBOpt;
2100 if (isDeviceBarrier)
2101 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ST : ARM_MB::SY;
2103 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ISHST : ARM_MB::ISH;
2104 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
2105 DAG.getConstant(DMBOpt, MVT::i32));
2108 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
2109 const ARMSubtarget *Subtarget) {
2110 // ARM pre v5TE and Thumb1 does not have preload instructions.
2111 if (!(Subtarget->isThumb2() ||
2112 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
2113 // Just preserve the chain.
2114 return Op.getOperand(0);
2116 DebugLoc dl = Op.getDebugLoc();
2117 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
2119 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
2120 // ARMv7 with MP extension has PLDW.
2121 return Op.getOperand(0);
2123 if (Subtarget->isThumb())
2125 isRead = ~isRead & 1;
2126 unsigned isData = Subtarget->isThumb() ? 0 : 1;
2128 // Currently there is no intrinsic that matches pli.
2129 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
2130 Op.getOperand(1), DAG.getConstant(isRead, MVT::i32),
2131 DAG.getConstant(isData, MVT::i32));
2134 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
2135 MachineFunction &MF = DAG.getMachineFunction();
2136 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
2138 // vastart just stores the address of the VarArgsFrameIndex slot into the
2139 // memory location argument.
2140 DebugLoc dl = Op.getDebugLoc();
2141 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2142 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2143 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2144 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2145 MachinePointerInfo(SV), false, false, 0);
2149 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
2150 SDValue &Root, SelectionDAG &DAG,
2151 DebugLoc dl) const {
2152 MachineFunction &MF = DAG.getMachineFunction();
2153 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2155 TargetRegisterClass *RC;
2156 if (AFI->isThumb1OnlyFunction())
2157 RC = ARM::tGPRRegisterClass;
2159 RC = ARM::GPRRegisterClass;
2161 // Transform the arguments stored in physical registers into virtual ones.
2162 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2163 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2166 if (NextVA.isMemLoc()) {
2167 MachineFrameInfo *MFI = MF.getFrameInfo();
2168 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
2170 // Create load node to retrieve arguments from the stack.
2171 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2172 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
2173 MachinePointerInfo::getFixedStack(FI),
2176 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2177 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2180 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
2184 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
2185 CallingConv::ID CallConv, bool isVarArg,
2186 const SmallVectorImpl<ISD::InputArg>
2188 DebugLoc dl, SelectionDAG &DAG,
2189 SmallVectorImpl<SDValue> &InVals)
2192 MachineFunction &MF = DAG.getMachineFunction();
2193 MachineFrameInfo *MFI = MF.getFrameInfo();
2195 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2197 // Assign locations to all of the incoming arguments.
2198 SmallVector<CCValAssign, 16> ArgLocs;
2199 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
2201 CCInfo.AnalyzeFormalArguments(Ins,
2202 CCAssignFnForNode(CallConv, /* Return*/ false,
2205 SmallVector<SDValue, 16> ArgValues;
2207 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2208 CCValAssign &VA = ArgLocs[i];
2210 // Arguments stored in registers.
2211 if (VA.isRegLoc()) {
2212 EVT RegVT = VA.getLocVT();
2215 if (VA.needsCustom()) {
2216 // f64 and vector types are split up into multiple registers or
2217 // combinations of registers and stack slots.
2218 if (VA.getLocVT() == MVT::v2f64) {
2219 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
2221 VA = ArgLocs[++i]; // skip ahead to next loc
2223 if (VA.isMemLoc()) {
2224 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
2225 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2226 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
2227 MachinePointerInfo::getFixedStack(FI),
2230 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
2233 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2234 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2235 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
2236 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2237 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
2239 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
2242 TargetRegisterClass *RC;
2244 if (RegVT == MVT::f32)
2245 RC = ARM::SPRRegisterClass;
2246 else if (RegVT == MVT::f64)
2247 RC = ARM::DPRRegisterClass;
2248 else if (RegVT == MVT::v2f64)
2249 RC = ARM::QPRRegisterClass;
2250 else if (RegVT == MVT::i32)
2251 RC = (AFI->isThumb1OnlyFunction() ?
2252 ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
2254 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2256 // Transform the arguments in physical registers into virtual ones.
2257 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2258 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2261 // If this is an 8 or 16-bit value, it is really passed promoted
2262 // to 32 bits. Insert an assert[sz]ext to capture this, then
2263 // truncate to the right size.
2264 switch (VA.getLocInfo()) {
2265 default: llvm_unreachable("Unknown loc info!");
2266 case CCValAssign::Full: break;
2267 case CCValAssign::BCvt:
2268 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2270 case CCValAssign::SExt:
2271 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2272 DAG.getValueType(VA.getValVT()));
2273 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2275 case CCValAssign::ZExt:
2276 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2277 DAG.getValueType(VA.getValVT()));
2278 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2282 InVals.push_back(ArgValue);
2284 } else { // VA.isRegLoc()
2287 assert(VA.isMemLoc());
2288 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
2290 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
2291 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(), true);
2293 // Create load nodes to retrieve arguments from the stack.
2294 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2295 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2296 MachinePointerInfo::getFixedStack(FI),
2303 static const unsigned GPRArgRegs[] = {
2304 ARM::R0, ARM::R1, ARM::R2, ARM::R3
2307 unsigned NumGPRs = CCInfo.getFirstUnallocated
2308 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
2310 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
2311 unsigned VARegSize = (4 - NumGPRs) * 4;
2312 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
2313 unsigned ArgOffset = CCInfo.getNextStackOffset();
2314 if (VARegSaveSize) {
2315 // If this function is vararg, store any remaining integer argument regs
2316 // to their spots on the stack so that they may be loaded by deferencing
2317 // the result of va_next.
2318 AFI->setVarArgsRegSaveSize(VARegSaveSize);
2319 AFI->setVarArgsFrameIndex(
2320 MFI->CreateFixedObject(VARegSaveSize,
2321 ArgOffset + VARegSaveSize - VARegSize,
2323 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(),
2326 SmallVector<SDValue, 4> MemOps;
2327 for (; NumGPRs < 4; ++NumGPRs) {
2328 TargetRegisterClass *RC;
2329 if (AFI->isThumb1OnlyFunction())
2330 RC = ARM::tGPRRegisterClass;
2332 RC = ARM::GPRRegisterClass;
2334 unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
2335 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2337 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2338 MachinePointerInfo::getFixedStack(AFI->getVarArgsFrameIndex()),
2340 MemOps.push_back(Store);
2341 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
2342 DAG.getConstant(4, getPointerTy()));
2344 if (!MemOps.empty())
2345 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2346 &MemOps[0], MemOps.size());
2348 // This will point to the next argument passed via stack.
2349 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset, true));
2355 /// isFloatingPointZero - Return true if this is +0.0.
2356 static bool isFloatingPointZero(SDValue Op) {
2357 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
2358 return CFP->getValueAPF().isPosZero();
2359 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
2360 // Maybe this has already been legalized into the constant pool?
2361 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
2362 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
2363 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
2364 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
2365 return CFP->getValueAPF().isPosZero();
2371 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
2372 /// the given operands.
2374 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2375 SDValue &ARMcc, SelectionDAG &DAG,
2376 DebugLoc dl) const {
2377 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
2378 unsigned C = RHSC->getZExtValue();
2379 if (!isLegalICmpImmediate(C)) {
2380 // Constant does not fit, try adjusting it by one?
2385 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
2386 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
2387 RHS = DAG.getConstant(C-1, MVT::i32);
2392 if (C != 0 && isLegalICmpImmediate(C-1)) {
2393 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
2394 RHS = DAG.getConstant(C-1, MVT::i32);
2399 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
2400 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
2401 RHS = DAG.getConstant(C+1, MVT::i32);
2406 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
2407 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2408 RHS = DAG.getConstant(C+1, MVT::i32);
2415 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2416 ARMISD::NodeType CompareType;
2419 CompareType = ARMISD::CMP;
2424 CompareType = ARMISD::CMPZ;
2427 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2428 return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS);
2431 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
2433 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
2434 DebugLoc dl) const {
2436 if (!isFloatingPointZero(RHS))
2437 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS);
2439 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS);
2440 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp);
2443 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2444 SDValue Cond = Op.getOperand(0);
2445 SDValue SelectTrue = Op.getOperand(1);
2446 SDValue SelectFalse = Op.getOperand(2);
2447 DebugLoc dl = Op.getDebugLoc();
2451 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
2452 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
2454 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
2455 const ConstantSDNode *CMOVTrue =
2456 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
2457 const ConstantSDNode *CMOVFalse =
2458 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
2460 if (CMOVTrue && CMOVFalse) {
2461 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
2462 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
2466 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
2468 False = SelectFalse;
2469 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
2474 if (True.getNode() && False.getNode()) {
2475 EVT VT = Cond.getValueType();
2476 SDValue ARMcc = Cond.getOperand(2);
2477 SDValue CCR = Cond.getOperand(3);
2478 SDValue Cmp = Cond.getOperand(4);
2479 return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp);
2484 return DAG.getSelectCC(dl, Cond,
2485 DAG.getConstant(0, Cond.getValueType()),
2486 SelectTrue, SelectFalse, ISD::SETNE);
2489 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
2490 EVT VT = Op.getValueType();
2491 SDValue LHS = Op.getOperand(0);
2492 SDValue RHS = Op.getOperand(1);
2493 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2494 SDValue TrueVal = Op.getOperand(2);
2495 SDValue FalseVal = Op.getOperand(3);
2496 DebugLoc dl = Op.getDebugLoc();
2498 if (LHS.getValueType() == MVT::i32) {
2500 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2501 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2502 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,Cmp);
2505 ARMCC::CondCodes CondCode, CondCode2;
2506 FPCCToARMCC(CC, CondCode, CondCode2);
2508 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2509 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2510 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2511 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
2513 if (CondCode2 != ARMCC::AL) {
2514 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32);
2515 // FIXME: Needs another CMP because flag can have but one use.
2516 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
2517 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
2518 Result, TrueVal, ARMcc2, CCR, Cmp2);
2523 /// canChangeToInt - Given the fp compare operand, return true if it is suitable
2524 /// to morph to an integer compare sequence.
2525 static bool canChangeToInt(SDValue Op, bool &SeenZero,
2526 const ARMSubtarget *Subtarget) {
2527 SDNode *N = Op.getNode();
2528 if (!N->hasOneUse())
2529 // Otherwise it requires moving the value from fp to integer registers.
2531 if (!N->getNumValues())
2533 EVT VT = Op.getValueType();
2534 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
2535 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
2536 // vmrs are very slow, e.g. cortex-a8.
2539 if (isFloatingPointZero(Op)) {
2543 return ISD::isNormalLoad(N);
2546 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
2547 if (isFloatingPointZero(Op))
2548 return DAG.getConstant(0, MVT::i32);
2550 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
2551 return DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2552 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(),
2553 Ld->isVolatile(), Ld->isNonTemporal(),
2554 Ld->getAlignment());
2556 llvm_unreachable("Unknown VFP cmp argument!");
2559 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
2560 SDValue &RetVal1, SDValue &RetVal2) {
2561 if (isFloatingPointZero(Op)) {
2562 RetVal1 = DAG.getConstant(0, MVT::i32);
2563 RetVal2 = DAG.getConstant(0, MVT::i32);
2567 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
2568 SDValue Ptr = Ld->getBasePtr();
2569 RetVal1 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2570 Ld->getChain(), Ptr,
2571 Ld->getPointerInfo(),
2572 Ld->isVolatile(), Ld->isNonTemporal(),
2573 Ld->getAlignment());
2575 EVT PtrType = Ptr.getValueType();
2576 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
2577 SDValue NewPtr = DAG.getNode(ISD::ADD, Op.getDebugLoc(),
2578 PtrType, Ptr, DAG.getConstant(4, PtrType));
2579 RetVal2 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2580 Ld->getChain(), NewPtr,
2581 Ld->getPointerInfo().getWithOffset(4),
2582 Ld->isVolatile(), Ld->isNonTemporal(),
2587 llvm_unreachable("Unknown VFP cmp argument!");
2590 /// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
2591 /// f32 and even f64 comparisons to integer ones.
2593 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
2594 SDValue Chain = Op.getOperand(0);
2595 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2596 SDValue LHS = Op.getOperand(2);
2597 SDValue RHS = Op.getOperand(3);
2598 SDValue Dest = Op.getOperand(4);
2599 DebugLoc dl = Op.getDebugLoc();
2601 bool SeenZero = false;
2602 if (canChangeToInt(LHS, SeenZero, Subtarget) &&
2603 canChangeToInt(RHS, SeenZero, Subtarget) &&
2604 // If one of the operand is zero, it's safe to ignore the NaN case since
2605 // we only care about equality comparisons.
2606 (SeenZero || (DAG.isKnownNeverNaN(LHS) && DAG.isKnownNeverNaN(RHS)))) {
2607 // If unsafe fp math optimization is enabled and there are no othter uses of
2608 // the CMP operands, and the condition code is EQ oe NE, we can optimize it
2609 // to an integer comparison.
2610 if (CC == ISD::SETOEQ)
2612 else if (CC == ISD::SETUNE)
2616 if (LHS.getValueType() == MVT::f32) {
2617 LHS = bitcastf32Toi32(LHS, DAG);
2618 RHS = bitcastf32Toi32(RHS, DAG);
2619 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2620 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2621 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2622 Chain, Dest, ARMcc, CCR, Cmp);
2627 expandf64Toi32(LHS, DAG, LHS1, LHS2);
2628 expandf64Toi32(RHS, DAG, RHS1, RHS2);
2629 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2630 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2631 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
2632 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
2633 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7);
2639 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2640 SDValue Chain = Op.getOperand(0);
2641 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2642 SDValue LHS = Op.getOperand(2);
2643 SDValue RHS = Op.getOperand(3);
2644 SDValue Dest = Op.getOperand(4);
2645 DebugLoc dl = Op.getDebugLoc();
2647 if (LHS.getValueType() == MVT::i32) {
2649 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2650 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2651 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2652 Chain, Dest, ARMcc, CCR, Cmp);
2655 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
2658 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
2659 CC == ISD::SETNE || CC == ISD::SETUNE)) {
2660 SDValue Result = OptimizeVFPBrcond(Op, DAG);
2661 if (Result.getNode())
2665 ARMCC::CondCodes CondCode, CondCode2;
2666 FPCCToARMCC(CC, CondCode, CondCode2);
2668 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2669 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2670 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2671 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
2672 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
2673 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2674 if (CondCode2 != ARMCC::AL) {
2675 ARMcc = DAG.getConstant(CondCode2, MVT::i32);
2676 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
2677 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2682 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
2683 SDValue Chain = Op.getOperand(0);
2684 SDValue Table = Op.getOperand(1);
2685 SDValue Index = Op.getOperand(2);
2686 DebugLoc dl = Op.getDebugLoc();
2688 EVT PTy = getPointerTy();
2689 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
2690 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
2691 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
2692 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
2693 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
2694 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
2695 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2696 if (Subtarget->isThumb2()) {
2697 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
2698 // which does another jump to the destination. This also makes it easier
2699 // to translate it to TBB / TBH later.
2700 // FIXME: This might not work if the function is extremely large.
2701 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
2702 Addr, Op.getOperand(2), JTI, UId);
2704 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2705 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
2706 MachinePointerInfo::getJumpTable(),
2708 Chain = Addr.getValue(1);
2709 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
2710 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2712 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
2713 MachinePointerInfo::getJumpTable(), false, false, 0);
2714 Chain = Addr.getValue(1);
2715 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2719 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
2720 DebugLoc dl = Op.getDebugLoc();
2723 switch (Op.getOpcode()) {
2725 assert(0 && "Invalid opcode!");
2726 case ISD::FP_TO_SINT:
2727 Opc = ARMISD::FTOSI;
2729 case ISD::FP_TO_UINT:
2730 Opc = ARMISD::FTOUI;
2733 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
2734 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
2737 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
2738 EVT VT = Op.getValueType();
2739 DebugLoc dl = Op.getDebugLoc();
2742 switch (Op.getOpcode()) {
2744 assert(0 && "Invalid opcode!");
2745 case ISD::SINT_TO_FP:
2746 Opc = ARMISD::SITOF;
2748 case ISD::UINT_TO_FP:
2749 Opc = ARMISD::UITOF;
2753 Op = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0));
2754 return DAG.getNode(Opc, dl, VT, Op);
2757 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
2758 // Implement fcopysign with a fabs and a conditional fneg.
2759 SDValue Tmp0 = Op.getOperand(0);
2760 SDValue Tmp1 = Op.getOperand(1);
2761 DebugLoc dl = Op.getDebugLoc();
2762 EVT VT = Op.getValueType();
2763 EVT SrcVT = Tmp1.getValueType();
2764 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
2765 SDValue ARMcc = DAG.getConstant(ARMCC::LT, MVT::i32);
2766 SDValue FP0 = DAG.getConstantFP(0.0, SrcVT);
2767 SDValue Cmp = getVFPCmp(Tmp1, FP0, DAG, dl);
2768 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2769 return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMcc, CCR, Cmp);
2772 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
2773 MachineFunction &MF = DAG.getMachineFunction();
2774 MachineFrameInfo *MFI = MF.getFrameInfo();
2775 MFI->setReturnAddressIsTaken(true);
2777 EVT VT = Op.getValueType();
2778 DebugLoc dl = Op.getDebugLoc();
2779 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2781 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
2782 SDValue Offset = DAG.getConstant(4, MVT::i32);
2783 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
2784 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
2785 MachinePointerInfo(), false, false, 0);
2788 // Return LR, which contains the return address. Mark it an implicit live-in.
2789 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
2790 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
2793 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2794 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2795 MFI->setFrameAddressIsTaken(true);
2797 EVT VT = Op.getValueType();
2798 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
2799 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2800 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
2801 ? ARM::R7 : ARM::R11;
2802 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
2804 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
2805 MachinePointerInfo(),
2810 /// ExpandBITCAST - If the target supports VFP, this function is called to
2811 /// expand a bit convert where either the source or destination type is i64 to
2812 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
2813 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
2814 /// vectors), since the legalizer won't know what to do with that.
2815 static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) {
2816 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2817 DebugLoc dl = N->getDebugLoc();
2818 SDValue Op = N->getOperand(0);
2820 // This function is only supposed to be called for i64 types, either as the
2821 // source or destination of the bit convert.
2822 EVT SrcVT = Op.getValueType();
2823 EVT DstVT = N->getValueType(0);
2824 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
2825 "ExpandBITCAST called for non-i64 type");
2827 // Turn i64->f64 into VMOVDRR.
2828 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
2829 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2830 DAG.getConstant(0, MVT::i32));
2831 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2832 DAG.getConstant(1, MVT::i32));
2833 return DAG.getNode(ISD::BITCAST, dl, DstVT,
2834 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
2837 // Turn f64->i64 into VMOVRRD.
2838 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
2839 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
2840 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
2841 // Merge the pieces into a single i64 value.
2842 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
2848 /// getZeroVector - Returns a vector of specified type with all zero elements.
2849 /// Zero vectors are used to represent vector negation and in those cases
2850 /// will be implemented with the NEON VNEG instruction. However, VNEG does
2851 /// not support i64 elements, so sometimes the zero vectors will need to be
2852 /// explicitly constructed. Regardless, use a canonical VMOV to create the
2854 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2855 assert(VT.isVector() && "Expected a vector type");
2856 // The canonical modified immediate encoding of a zero vector is....0!
2857 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32);
2858 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
2859 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
2860 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
2863 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
2864 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2865 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
2866 SelectionDAG &DAG) const {
2867 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2868 EVT VT = Op.getValueType();
2869 unsigned VTBits = VT.getSizeInBits();
2870 DebugLoc dl = Op.getDebugLoc();
2871 SDValue ShOpLo = Op.getOperand(0);
2872 SDValue ShOpHi = Op.getOperand(1);
2873 SDValue ShAmt = Op.getOperand(2);
2875 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
2877 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
2879 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2880 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2881 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
2882 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2883 DAG.getConstant(VTBits, MVT::i32));
2884 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
2885 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2886 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
2888 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2889 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
2891 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
2892 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
2895 SDValue Ops[2] = { Lo, Hi };
2896 return DAG.getMergeValues(Ops, 2, dl);
2899 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
2900 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2901 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
2902 SelectionDAG &DAG) const {
2903 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2904 EVT VT = Op.getValueType();
2905 unsigned VTBits = VT.getSizeInBits();
2906 DebugLoc dl = Op.getDebugLoc();
2907 SDValue ShOpLo = Op.getOperand(0);
2908 SDValue ShOpHi = Op.getOperand(1);
2909 SDValue ShAmt = Op.getOperand(2);
2912 assert(Op.getOpcode() == ISD::SHL_PARTS);
2913 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2914 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2915 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
2916 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2917 DAG.getConstant(VTBits, MVT::i32));
2918 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
2919 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
2921 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2922 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2923 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
2925 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
2926 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
2929 SDValue Ops[2] = { Lo, Hi };
2930 return DAG.getMergeValues(Ops, 2, dl);
2933 SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
2934 SelectionDAG &DAG) const {
2935 // The rounding mode is in bits 23:22 of the FPSCR.
2936 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
2937 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
2938 // so that the shift + and get folded into a bitfield extract.
2939 DebugLoc dl = Op.getDebugLoc();
2940 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
2941 DAG.getConstant(Intrinsic::arm_get_fpscr,
2943 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
2944 DAG.getConstant(1U << 22, MVT::i32));
2945 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
2946 DAG.getConstant(22, MVT::i32));
2947 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
2948 DAG.getConstant(3, MVT::i32));
2951 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
2952 const ARMSubtarget *ST) {
2953 EVT VT = N->getValueType(0);
2954 DebugLoc dl = N->getDebugLoc();
2956 if (!ST->hasV6T2Ops())
2959 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
2960 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
2963 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
2964 const ARMSubtarget *ST) {
2965 EVT VT = N->getValueType(0);
2966 DebugLoc dl = N->getDebugLoc();
2971 // Lower vector shifts on NEON to use VSHL.
2972 assert(ST->hasNEON() && "unexpected vector shift");
2974 // Left shifts translate directly to the vshiftu intrinsic.
2975 if (N->getOpcode() == ISD::SHL)
2976 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2977 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
2978 N->getOperand(0), N->getOperand(1));
2980 assert((N->getOpcode() == ISD::SRA ||
2981 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
2983 // NEON uses the same intrinsics for both left and right shifts. For
2984 // right shifts, the shift amounts are negative, so negate the vector of
2986 EVT ShiftVT = N->getOperand(1).getValueType();
2987 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
2988 getZeroVector(ShiftVT, DAG, dl),
2990 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
2991 Intrinsic::arm_neon_vshifts :
2992 Intrinsic::arm_neon_vshiftu);
2993 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2994 DAG.getConstant(vshiftInt, MVT::i32),
2995 N->getOperand(0), NegatedCount);
2998 static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
2999 const ARMSubtarget *ST) {
3000 EVT VT = N->getValueType(0);
3001 DebugLoc dl = N->getDebugLoc();
3003 // We can get here for a node like i32 = ISD::SHL i32, i64
3007 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
3008 "Unknown shift to lower!");
3010 // We only lower SRA, SRL of 1 here, all others use generic lowering.
3011 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
3012 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
3015 // If we are in thumb mode, we don't have RRX.
3016 if (ST->isThumb1Only()) return SDValue();
3018 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
3019 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
3020 DAG.getConstant(0, MVT::i32));
3021 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
3022 DAG.getConstant(1, MVT::i32));
3024 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
3025 // captures the result into a carry flag.
3026 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
3027 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
3029 // The low part is an ARMISD::RRX operand, which shifts the carry in.
3030 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
3032 // Merge the pieces into a single i64 value.
3033 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
3036 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
3037 SDValue TmpOp0, TmpOp1;
3038 bool Invert = false;
3042 SDValue Op0 = Op.getOperand(0);
3043 SDValue Op1 = Op.getOperand(1);
3044 SDValue CC = Op.getOperand(2);
3045 EVT VT = Op.getValueType();
3046 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
3047 DebugLoc dl = Op.getDebugLoc();
3049 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
3050 switch (SetCCOpcode) {
3051 default: llvm_unreachable("Illegal FP comparison"); break;
3053 case ISD::SETNE: Invert = true; // Fallthrough
3055 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3057 case ISD::SETLT: Swap = true; // Fallthrough
3059 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3061 case ISD::SETLE: Swap = true; // Fallthrough
3063 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3064 case ISD::SETUGE: Swap = true; // Fallthrough
3065 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
3066 case ISD::SETUGT: Swap = true; // Fallthrough
3067 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
3068 case ISD::SETUEQ: Invert = true; // Fallthrough
3070 // Expand this to (OLT | OGT).
3074 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3075 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
3077 case ISD::SETUO: Invert = true; // Fallthrough
3079 // Expand this to (OLT | OGE).
3083 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3084 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
3088 // Integer comparisons.
3089 switch (SetCCOpcode) {
3090 default: llvm_unreachable("Illegal integer comparison"); break;
3091 case ISD::SETNE: Invert = true;
3092 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3093 case ISD::SETLT: Swap = true;
3094 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3095 case ISD::SETLE: Swap = true;
3096 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3097 case ISD::SETULT: Swap = true;
3098 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
3099 case ISD::SETULE: Swap = true;
3100 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
3103 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
3104 if (Opc == ARMISD::VCEQ) {
3107 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
3109 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
3112 // Ignore bitconvert.
3113 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST)
3114 AndOp = AndOp.getOperand(0);
3116 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
3118 Op0 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(0));
3119 Op1 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(1));
3126 std::swap(Op0, Op1);
3128 // If one of the operands is a constant vector zero, attempt to fold the
3129 // comparison to a specialized compare-against-zero form.
3131 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
3133 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) {
3134 if (Opc == ARMISD::VCGE)
3135 Opc = ARMISD::VCLEZ;
3136 else if (Opc == ARMISD::VCGT)
3137 Opc = ARMISD::VCLTZ;
3142 if (SingleOp.getNode()) {
3145 Result = DAG.getNode(ARMISD::VCEQZ, dl, VT, SingleOp); break;
3147 Result = DAG.getNode(ARMISD::VCGEZ, dl, VT, SingleOp); break;
3149 Result = DAG.getNode(ARMISD::VCLEZ, dl, VT, SingleOp); break;
3151 Result = DAG.getNode(ARMISD::VCGTZ, dl, VT, SingleOp); break;
3153 Result = DAG.getNode(ARMISD::VCLTZ, dl, VT, SingleOp); break;
3155 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3158 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3162 Result = DAG.getNOT(dl, Result, VT);
3167 /// isNEONModifiedImm - Check if the specified splat value corresponds to a
3168 /// valid vector constant for a NEON instruction with a "modified immediate"
3169 /// operand (e.g., VMOV). If so, return the encoded value.
3170 static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
3171 unsigned SplatBitSize, SelectionDAG &DAG,
3172 EVT &VT, bool is128Bits, NEONModImmType type) {
3173 unsigned OpCmode, Imm;
3175 // SplatBitSize is set to the smallest size that splats the vector, so a
3176 // zero vector will always have SplatBitSize == 8. However, NEON modified
3177 // immediate instructions others than VMOV do not support the 8-bit encoding
3178 // of a zero vector, and the default encoding of zero is supposed to be the
3183 switch (SplatBitSize) {
3185 if (type != VMOVModImm)
3187 // Any 1-byte value is OK. Op=0, Cmode=1110.
3188 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
3191 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
3195 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
3196 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
3197 if ((SplatBits & ~0xff) == 0) {
3198 // Value = 0x00nn: Op=x, Cmode=100x.
3203 if ((SplatBits & ~0xff00) == 0) {
3204 // Value = 0xnn00: Op=x, Cmode=101x.
3206 Imm = SplatBits >> 8;
3212 // NEON's 32-bit VMOV supports splat values where:
3213 // * only one byte is nonzero, or
3214 // * the least significant byte is 0xff and the second byte is nonzero, or
3215 // * the least significant 2 bytes are 0xff and the third is nonzero.
3216 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
3217 if ((SplatBits & ~0xff) == 0) {
3218 // Value = 0x000000nn: Op=x, Cmode=000x.
3223 if ((SplatBits & ~0xff00) == 0) {
3224 // Value = 0x0000nn00: Op=x, Cmode=001x.
3226 Imm = SplatBits >> 8;
3229 if ((SplatBits & ~0xff0000) == 0) {
3230 // Value = 0x00nn0000: Op=x, Cmode=010x.
3232 Imm = SplatBits >> 16;
3235 if ((SplatBits & ~0xff000000) == 0) {
3236 // Value = 0xnn000000: Op=x, Cmode=011x.
3238 Imm = SplatBits >> 24;
3242 // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC
3243 if (type == OtherModImm) return SDValue();
3245 if ((SplatBits & ~0xffff) == 0 &&
3246 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
3247 // Value = 0x0000nnff: Op=x, Cmode=1100.
3249 Imm = SplatBits >> 8;
3254 if ((SplatBits & ~0xffffff) == 0 &&
3255 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
3256 // Value = 0x00nnffff: Op=x, Cmode=1101.
3258 Imm = SplatBits >> 16;
3259 SplatBits |= 0xffff;
3263 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
3264 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
3265 // VMOV.I32. A (very) minor optimization would be to replicate the value
3266 // and fall through here to test for a valid 64-bit splat. But, then the
3267 // caller would also need to check and handle the change in size.
3271 if (type != VMOVModImm)
3273 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
3274 uint64_t BitMask = 0xff;
3276 unsigned ImmMask = 1;
3278 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
3279 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
3282 } else if ((SplatBits & BitMask) != 0) {
3288 // Op=1, Cmode=1110.
3291 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
3296 llvm_unreachable("unexpected size for isNEONModifiedImm");
3300 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
3301 return DAG.getTargetConstant(EncodedVal, MVT::i32);
3304 static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT,
3305 bool &ReverseVEXT, unsigned &Imm) {
3306 unsigned NumElts = VT.getVectorNumElements();
3307 ReverseVEXT = false;
3309 // Assume that the first shuffle index is not UNDEF. Fail if it is.
3315 // If this is a VEXT shuffle, the immediate value is the index of the first
3316 // element. The other shuffle indices must be the successive elements after
3318 unsigned ExpectedElt = Imm;
3319 for (unsigned i = 1; i < NumElts; ++i) {
3320 // Increment the expected index. If it wraps around, it may still be
3321 // a VEXT but the source vectors must be swapped.
3323 if (ExpectedElt == NumElts * 2) {
3328 if (M[i] < 0) continue; // ignore UNDEF indices
3329 if (ExpectedElt != static_cast<unsigned>(M[i]))
3333 // Adjust the index value if the source operands will be swapped.
3340 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
3341 /// instruction with the specified blocksize. (The order of the elements
3342 /// within each block of the vector is reversed.)
3343 static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT,
3344 unsigned BlockSize) {
3345 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
3346 "Only possible block sizes for VREV are: 16, 32, 64");
3348 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3352 unsigned NumElts = VT.getVectorNumElements();
3353 unsigned BlockElts = M[0] + 1;
3354 // If the first shuffle index is UNDEF, be optimistic.
3356 BlockElts = BlockSize / EltSz;
3358 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
3361 for (unsigned i = 0; i < NumElts; ++i) {
3362 if (M[i] < 0) continue; // ignore UNDEF indices
3363 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
3370 static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT,
3371 unsigned &WhichResult) {
3372 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3376 unsigned NumElts = VT.getVectorNumElements();
3377 WhichResult = (M[0] == 0 ? 0 : 1);
3378 for (unsigned i = 0; i < NumElts; i += 2) {
3379 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3380 (M[i+1] >= 0 && (unsigned) M[i+1] != i + NumElts + WhichResult))
3386 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
3387 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3388 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
3389 static bool isVTRN_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3390 unsigned &WhichResult) {
3391 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3395 unsigned NumElts = VT.getVectorNumElements();
3396 WhichResult = (M[0] == 0 ? 0 : 1);
3397 for (unsigned i = 0; i < NumElts; i += 2) {
3398 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3399 (M[i+1] >= 0 && (unsigned) M[i+1] != i + WhichResult))
3405 static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT,
3406 unsigned &WhichResult) {
3407 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3411 unsigned NumElts = VT.getVectorNumElements();
3412 WhichResult = (M[0] == 0 ? 0 : 1);
3413 for (unsigned i = 0; i != NumElts; ++i) {
3414 if (M[i] < 0) continue; // ignore UNDEF indices
3415 if ((unsigned) M[i] != 2 * i + WhichResult)
3419 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3420 if (VT.is64BitVector() && EltSz == 32)
3426 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
3427 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3428 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
3429 static bool isVUZP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3430 unsigned &WhichResult) {
3431 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3435 unsigned Half = VT.getVectorNumElements() / 2;
3436 WhichResult = (M[0] == 0 ? 0 : 1);
3437 for (unsigned j = 0; j != 2; ++j) {
3438 unsigned Idx = WhichResult;
3439 for (unsigned i = 0; i != Half; ++i) {
3440 int MIdx = M[i + j * Half];
3441 if (MIdx >= 0 && (unsigned) MIdx != Idx)
3447 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3448 if (VT.is64BitVector() && EltSz == 32)
3454 static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT,
3455 unsigned &WhichResult) {
3456 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3460 unsigned NumElts = VT.getVectorNumElements();
3461 WhichResult = (M[0] == 0 ? 0 : 1);
3462 unsigned Idx = WhichResult * NumElts / 2;
3463 for (unsigned i = 0; i != NumElts; i += 2) {
3464 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3465 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts))
3470 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3471 if (VT.is64BitVector() && EltSz == 32)
3477 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
3478 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3479 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
3480 static bool isVZIP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3481 unsigned &WhichResult) {
3482 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3486 unsigned NumElts = VT.getVectorNumElements();
3487 WhichResult = (M[0] == 0 ? 0 : 1);
3488 unsigned Idx = WhichResult * NumElts / 2;
3489 for (unsigned i = 0; i != NumElts; i += 2) {
3490 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3491 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx))
3496 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3497 if (VT.is64BitVector() && EltSz == 32)
3503 // If N is an integer constant that can be moved into a register in one
3504 // instruction, return an SDValue of such a constant (will become a MOV
3505 // instruction). Otherwise return null.
3506 static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG,
3507 const ARMSubtarget *ST, DebugLoc dl) {
3509 if (!isa<ConstantSDNode>(N))
3511 Val = cast<ConstantSDNode>(N)->getZExtValue();
3513 if (ST->isThumb1Only()) {
3514 if (Val <= 255 || ~Val <= 255)
3515 return DAG.getConstant(Val, MVT::i32);
3517 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1)
3518 return DAG.getConstant(Val, MVT::i32);
3523 // If this is a case we can't handle, return null and let the default
3524 // expansion code take care of it.
3525 static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
3526 const ARMSubtarget *ST) {
3527 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
3528 DebugLoc dl = Op.getDebugLoc();
3529 EVT VT = Op.getValueType();
3531 APInt SplatBits, SplatUndef;
3532 unsigned SplatBitSize;
3534 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
3535 if (SplatBitSize <= 64) {
3536 // Check if an immediate VMOV works.
3538 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
3539 SplatUndef.getZExtValue(), SplatBitSize,
3540 DAG, VmovVT, VT.is128BitVector(),
3542 if (Val.getNode()) {
3543 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
3544 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3547 // Try an immediate VMVN.
3548 uint64_t NegatedImm = (SplatBits.getZExtValue() ^
3549 ((1LL << SplatBitSize) - 1));
3550 Val = isNEONModifiedImm(NegatedImm,
3551 SplatUndef.getZExtValue(), SplatBitSize,
3552 DAG, VmovVT, VT.is128BitVector(),
3554 if (Val.getNode()) {
3555 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
3556 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3561 // Scan through the operands to see if only one value is used.
3562 unsigned NumElts = VT.getVectorNumElements();
3563 bool isOnlyLowElement = true;
3564 bool usesOnlyOneValue = true;
3565 bool isConstant = true;
3567 for (unsigned i = 0; i < NumElts; ++i) {
3568 SDValue V = Op.getOperand(i);
3569 if (V.getOpcode() == ISD::UNDEF)
3572 isOnlyLowElement = false;
3573 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
3576 if (!Value.getNode())
3578 else if (V != Value)
3579 usesOnlyOneValue = false;
3582 if (!Value.getNode())
3583 return DAG.getUNDEF(VT);
3585 if (isOnlyLowElement)
3586 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
3588 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3590 // Use VDUP for non-constant splats. For f32 constant splats, reduce to
3591 // i32 and try again.
3592 if (usesOnlyOneValue && EltSize <= 32) {
3594 return DAG.getNode(ARMISD::VDUP, dl, VT, Value);
3595 if (VT.getVectorElementType().isFloatingPoint()) {
3596 SmallVector<SDValue, 8> Ops;
3597 for (unsigned i = 0; i < NumElts; ++i)
3598 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32,
3600 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
3601 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], NumElts);
3602 Val = LowerBUILD_VECTOR(Val, DAG, ST);
3604 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
3606 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
3608 return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
3611 // If all elements are constants and the case above didn't get hit, fall back
3612 // to the default expansion, which will generate a load from the constant
3617 // Vectors with 32- or 64-bit elements can be built by directly assigning
3618 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
3619 // will be legalized.
3620 if (EltSize >= 32) {
3621 // Do the expansion with floating-point types, since that is what the VFP
3622 // registers are defined to use, and since i64 is not legal.
3623 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3624 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3625 SmallVector<SDValue, 8> Ops;
3626 for (unsigned i = 0; i < NumElts; ++i)
3627 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i)));
3628 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
3629 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
3635 /// isShuffleMaskLegal - Targets can use this to indicate that they only
3636 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
3637 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
3638 /// are assumed to be legal.
3640 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
3642 if (VT.getVectorNumElements() == 4 &&
3643 (VT.is128BitVector() || VT.is64BitVector())) {
3644 unsigned PFIndexes[4];
3645 for (unsigned i = 0; i != 4; ++i) {
3649 PFIndexes[i] = M[i];
3652 // Compute the index in the perfect shuffle table.
3653 unsigned PFTableIndex =
3654 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3655 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3656 unsigned Cost = (PFEntry >> 30);
3663 unsigned Imm, WhichResult;
3665 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3666 return (EltSize >= 32 ||
3667 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
3668 isVREVMask(M, VT, 64) ||
3669 isVREVMask(M, VT, 32) ||
3670 isVREVMask(M, VT, 16) ||
3671 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
3672 isVTRNMask(M, VT, WhichResult) ||
3673 isVUZPMask(M, VT, WhichResult) ||
3674 isVZIPMask(M, VT, WhichResult) ||
3675 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
3676 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
3677 isVZIP_v_undef_Mask(M, VT, WhichResult));
3680 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
3681 /// the specified operations to build the shuffle.
3682 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
3683 SDValue RHS, SelectionDAG &DAG,
3685 unsigned OpNum = (PFEntry >> 26) & 0x0F;
3686 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
3687 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
3690 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
3699 OP_VUZPL, // VUZP, left result
3700 OP_VUZPR, // VUZP, right result
3701 OP_VZIPL, // VZIP, left result
3702 OP_VZIPR, // VZIP, right result
3703 OP_VTRNL, // VTRN, left result
3704 OP_VTRNR // VTRN, right result
3707 if (OpNum == OP_COPY) {
3708 if (LHSID == (1*9+2)*9+3) return LHS;
3709 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
3713 SDValue OpLHS, OpRHS;
3714 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
3715 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
3716 EVT VT = OpLHS.getValueType();
3719 default: llvm_unreachable("Unknown shuffle opcode!");
3721 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
3726 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
3727 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
3731 return DAG.getNode(ARMISD::VEXT, dl, VT,
3733 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
3736 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3737 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
3740 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3741 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
3744 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3745 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
3749 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
3750 SDValue V1 = Op.getOperand(0);
3751 SDValue V2 = Op.getOperand(1);
3752 DebugLoc dl = Op.getDebugLoc();
3753 EVT VT = Op.getValueType();
3754 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
3755 SmallVector<int, 8> ShuffleMask;
3757 // Convert shuffles that are directly supported on NEON to target-specific
3758 // DAG nodes, instead of keeping them as shuffles and matching them again
3759 // during code selection. This is more efficient and avoids the possibility
3760 // of inconsistencies between legalization and selection.
3761 // FIXME: floating-point vectors should be canonicalized to integer vectors
3762 // of the same time so that they get CSEd properly.
3763 SVN->getMask(ShuffleMask);
3765 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3766 if (EltSize <= 32) {
3767 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
3768 int Lane = SVN->getSplatIndex();
3769 // If this is undef splat, generate it via "just" vdup, if possible.
3770 if (Lane == -1) Lane = 0;
3772 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
3773 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
3775 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
3776 DAG.getConstant(Lane, MVT::i32));
3781 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
3784 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
3785 DAG.getConstant(Imm, MVT::i32));
3788 if (isVREVMask(ShuffleMask, VT, 64))
3789 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
3790 if (isVREVMask(ShuffleMask, VT, 32))
3791 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
3792 if (isVREVMask(ShuffleMask, VT, 16))
3793 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
3795 // Check for Neon shuffles that modify both input vectors in place.
3796 // If both results are used, i.e., if there are two shuffles with the same
3797 // source operands and with masks corresponding to both results of one of
3798 // these operations, DAG memoization will ensure that a single node is
3799 // used for both shuffles.
3800 unsigned WhichResult;
3801 if (isVTRNMask(ShuffleMask, VT, WhichResult))
3802 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3803 V1, V2).getValue(WhichResult);
3804 if (isVUZPMask(ShuffleMask, VT, WhichResult))
3805 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3806 V1, V2).getValue(WhichResult);
3807 if (isVZIPMask(ShuffleMask, VT, WhichResult))
3808 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3809 V1, V2).getValue(WhichResult);
3811 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
3812 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3813 V1, V1).getValue(WhichResult);
3814 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
3815 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3816 V1, V1).getValue(WhichResult);
3817 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
3818 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3819 V1, V1).getValue(WhichResult);
3822 // If the shuffle is not directly supported and it has 4 elements, use
3823 // the PerfectShuffle-generated table to synthesize it from other shuffles.
3824 unsigned NumElts = VT.getVectorNumElements();
3826 unsigned PFIndexes[4];
3827 for (unsigned i = 0; i != 4; ++i) {
3828 if (ShuffleMask[i] < 0)
3831 PFIndexes[i] = ShuffleMask[i];
3834 // Compute the index in the perfect shuffle table.
3835 unsigned PFTableIndex =
3836 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3837 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3838 unsigned Cost = (PFEntry >> 30);
3841 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
3844 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
3845 if (EltSize >= 32) {
3846 // Do the expansion with floating-point types, since that is what the VFP
3847 // registers are defined to use, and since i64 is not legal.
3848 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3849 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3850 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1);
3851 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2);
3852 SmallVector<SDValue, 8> Ops;
3853 for (unsigned i = 0; i < NumElts; ++i) {
3854 if (ShuffleMask[i] < 0)
3855 Ops.push_back(DAG.getUNDEF(EltVT));
3857 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3858 ShuffleMask[i] < (int)NumElts ? V1 : V2,
3859 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
3862 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
3863 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
3869 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
3870 // EXTRACT_VECTOR_ELT is legal only for immediate indexes.
3871 SDValue Lane = Op.getOperand(1);
3872 if (!isa<ConstantSDNode>(Lane))
3875 SDValue Vec = Op.getOperand(0);
3876 if (Op.getValueType() == MVT::i32 &&
3877 Vec.getValueType().getVectorElementType().getSizeInBits() < 32) {
3878 DebugLoc dl = Op.getDebugLoc();
3879 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
3885 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
3886 // The only time a CONCAT_VECTORS operation can have legal types is when
3887 // two 64-bit vectors are concatenated to a 128-bit vector.
3888 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
3889 "unexpected CONCAT_VECTORS");
3890 DebugLoc dl = Op.getDebugLoc();
3891 SDValue Val = DAG.getUNDEF(MVT::v2f64);
3892 SDValue Op0 = Op.getOperand(0);
3893 SDValue Op1 = Op.getOperand(1);
3894 if (Op0.getOpcode() != ISD::UNDEF)
3895 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
3896 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0),
3897 DAG.getIntPtrConstant(0));
3898 if (Op1.getOpcode() != ISD::UNDEF)
3899 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
3900 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1),
3901 DAG.getIntPtrConstant(1));
3902 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val);
3905 /// isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each
3906 /// element has been zero/sign-extended, depending on the isSigned parameter,
3907 /// from an integer type half its size.
3908 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
3910 // A v2i64 BUILD_VECTOR will have been legalized to a BITCAST from v4i32.
3911 EVT VT = N->getValueType(0);
3912 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) {
3913 SDNode *BVN = N->getOperand(0).getNode();
3914 if (BVN->getValueType(0) != MVT::v4i32 ||
3915 BVN->getOpcode() != ISD::BUILD_VECTOR)
3917 unsigned LoElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
3918 unsigned HiElt = 1 - LoElt;
3919 ConstantSDNode *Lo0 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt));
3920 ConstantSDNode *Hi0 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt));
3921 ConstantSDNode *Lo1 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt+2));
3922 ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2));
3923 if (!Lo0 || !Hi0 || !Lo1 || !Hi1)
3926 if (Hi0->getSExtValue() == Lo0->getSExtValue() >> 32 &&
3927 Hi1->getSExtValue() == Lo1->getSExtValue() >> 32)
3930 if (Hi0->isNullValue() && Hi1->isNullValue())
3936 if (N->getOpcode() != ISD::BUILD_VECTOR)
3939 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
3940 SDNode *Elt = N->getOperand(i).getNode();
3941 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
3942 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3943 unsigned HalfSize = EltSize / 2;
3945 int64_t SExtVal = C->getSExtValue();
3946 if ((SExtVal >> HalfSize) != (SExtVal >> EltSize))
3949 if ((C->getZExtValue() >> HalfSize) != 0)
3960 /// isSignExtended - Check if a node is a vector value that is sign-extended
3961 /// or a constant BUILD_VECTOR with sign-extended elements.
3962 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
3963 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N))
3965 if (isExtendedBUILD_VECTOR(N, DAG, true))
3970 /// isZeroExtended - Check if a node is a vector value that is zero-extended
3971 /// or a constant BUILD_VECTOR with zero-extended elements.
3972 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
3973 if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N))
3975 if (isExtendedBUILD_VECTOR(N, DAG, false))
3980 /// SkipExtension - For a node that is a SIGN_EXTEND, ZERO_EXTEND, extending
3981 /// load, or BUILD_VECTOR with extended elements, return the unextended value.
3982 static SDValue SkipExtension(SDNode *N, SelectionDAG &DAG) {
3983 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
3984 return N->getOperand(0);
3985 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
3986 return DAG.getLoad(LD->getMemoryVT(), N->getDebugLoc(), LD->getChain(),
3987 LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(),
3988 LD->isNonTemporal(), LD->getAlignment());
3989 // Otherwise, the value must be a BUILD_VECTOR. For v2i64, it will
3990 // have been legalized as a BITCAST from v4i32.
3991 if (N->getOpcode() == ISD::BITCAST) {
3992 SDNode *BVN = N->getOperand(0).getNode();
3993 assert(BVN->getOpcode() == ISD::BUILD_VECTOR &&
3994 BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR");
3995 unsigned LowElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
3996 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), MVT::v2i32,
3997 BVN->getOperand(LowElt), BVN->getOperand(LowElt+2));
3999 // Construct a new BUILD_VECTOR with elements truncated to half the size.
4000 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
4001 EVT VT = N->getValueType(0);
4002 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
4003 unsigned NumElts = VT.getVectorNumElements();
4004 MVT TruncVT = MVT::getIntegerVT(EltSize);
4005 SmallVector<SDValue, 8> Ops;
4006 for (unsigned i = 0; i != NumElts; ++i) {
4007 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
4008 const APInt &CInt = C->getAPIntValue();
4009 Ops.push_back(DAG.getConstant(CInt.trunc(EltSize), TruncVT));
4011 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
4012 MVT::getVectorVT(TruncVT, NumElts), Ops.data(), NumElts);
4015 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
4016 // Multiplications are only custom-lowered for 128-bit vectors so that
4017 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
4018 EVT VT = Op.getValueType();
4019 assert(VT.is128BitVector() && "unexpected type for custom-lowering ISD::MUL");
4020 SDNode *N0 = Op.getOperand(0).getNode();
4021 SDNode *N1 = Op.getOperand(1).getNode();
4022 unsigned NewOpc = 0;
4023 if (isSignExtended(N0, DAG) && isSignExtended(N1, DAG))
4024 NewOpc = ARMISD::VMULLs;
4025 else if (isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG))
4026 NewOpc = ARMISD::VMULLu;
4027 else if (VT == MVT::v2i64)
4028 // Fall through to expand this. It is not legal.
4031 // Other vector multiplications are legal.
4034 // Legalize to a VMULL instruction.
4035 DebugLoc DL = Op.getDebugLoc();
4036 SDValue Op0 = SkipExtension(N0, DAG);
4037 SDValue Op1 = SkipExtension(N1, DAG);
4039 assert(Op0.getValueType().is64BitVector() &&
4040 Op1.getValueType().is64BitVector() &&
4041 "unexpected types for extended operands to VMULL");
4042 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
4045 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
4046 switch (Op.getOpcode()) {
4047 default: llvm_unreachable("Don't know how to custom lower this!");
4048 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
4049 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
4050 case ISD::GlobalAddress:
4051 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
4052 LowerGlobalAddressELF(Op, DAG);
4053 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
4054 case ISD::SELECT: return LowerSELECT(Op, DAG);
4055 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
4056 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
4057 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
4058 case ISD::VASTART: return LowerVASTART(Op, DAG);
4059 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget);
4060 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget);
4061 case ISD::SINT_TO_FP:
4062 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
4063 case ISD::FP_TO_SINT:
4064 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
4065 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
4066 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
4067 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
4068 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
4069 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
4070 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
4071 case ISD::EH_SJLJ_DISPATCHSETUP: return LowerEH_SJLJ_DISPATCHSETUP(Op, DAG);
4072 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
4074 case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG);
4077 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
4078 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
4079 case ISD::SRL_PARTS:
4080 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
4081 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
4082 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
4083 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
4084 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
4085 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
4086 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
4087 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
4088 case ISD::MUL: return LowerMUL(Op, DAG);
4093 /// ReplaceNodeResults - Replace the results of node with an illegal result
4094 /// type with new values built out of custom code.
4095 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
4096 SmallVectorImpl<SDValue>&Results,
4097 SelectionDAG &DAG) const {
4099 switch (N->getOpcode()) {
4101 llvm_unreachable("Don't know how to custom expand this!");
4104 Res = ExpandBITCAST(N, DAG);
4108 Res = Expand64BitShift(N, DAG, Subtarget);
4112 Results.push_back(Res);
4115 //===----------------------------------------------------------------------===//
4116 // ARM Scheduler Hooks
4117 //===----------------------------------------------------------------------===//
4120 ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
4121 MachineBasicBlock *BB,
4122 unsigned Size) const {
4123 unsigned dest = MI->getOperand(0).getReg();
4124 unsigned ptr = MI->getOperand(1).getReg();
4125 unsigned oldval = MI->getOperand(2).getReg();
4126 unsigned newval = MI->getOperand(3).getReg();
4127 unsigned scratch = BB->getParent()->getRegInfo()
4128 .createVirtualRegister(ARM::GPRRegisterClass);
4129 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4130 DebugLoc dl = MI->getDebugLoc();
4131 bool isThumb2 = Subtarget->isThumb2();
4133 unsigned ldrOpc, strOpc;
4135 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
4137 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
4138 strOpc = isThumb2 ? ARM::t2LDREXB : ARM::STREXB;
4141 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
4142 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
4145 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
4146 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
4150 MachineFunction *MF = BB->getParent();
4151 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4152 MachineFunction::iterator It = BB;
4153 ++It; // insert the new blocks after the current block
4155 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
4156 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
4157 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
4158 MF->insert(It, loop1MBB);
4159 MF->insert(It, loop2MBB);
4160 MF->insert(It, exitMBB);
4162 // Transfer the remainder of BB and its successor edges to exitMBB.
4163 exitMBB->splice(exitMBB->begin(), BB,
4164 llvm::next(MachineBasicBlock::iterator(MI)),
4166 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4170 // fallthrough --> loop1MBB
4171 BB->addSuccessor(loop1MBB);
4174 // ldrex dest, [ptr]
4178 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
4179 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
4180 .addReg(dest).addReg(oldval));
4181 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4182 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
4183 BB->addSuccessor(loop2MBB);
4184 BB->addSuccessor(exitMBB);
4187 // strex scratch, newval, [ptr]
4191 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval)
4193 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4194 .addReg(scratch).addImm(0));
4195 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4196 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
4197 BB->addSuccessor(loop1MBB);
4198 BB->addSuccessor(exitMBB);
4204 MI->eraseFromParent(); // The instruction is gone now.
4210 ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
4211 unsigned Size, unsigned BinOpcode) const {
4212 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4213 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4215 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4216 MachineFunction *MF = BB->getParent();
4217 MachineFunction::iterator It = BB;
4220 unsigned dest = MI->getOperand(0).getReg();
4221 unsigned ptr = MI->getOperand(1).getReg();
4222 unsigned incr = MI->getOperand(2).getReg();
4223 DebugLoc dl = MI->getDebugLoc();
4225 bool isThumb2 = Subtarget->isThumb2();
4226 unsigned ldrOpc, strOpc;
4228 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
4230 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
4231 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
4234 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
4235 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
4238 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
4239 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
4243 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
4244 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
4245 MF->insert(It, loopMBB);
4246 MF->insert(It, exitMBB);
4248 // Transfer the remainder of BB and its successor edges to exitMBB.
4249 exitMBB->splice(exitMBB->begin(), BB,
4250 llvm::next(MachineBasicBlock::iterator(MI)),
4252 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4254 MachineRegisterInfo &RegInfo = MF->getRegInfo();
4255 unsigned scratch = RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
4256 unsigned scratch2 = (!BinOpcode) ? incr :
4257 RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
4261 // fallthrough --> loopMBB
4262 BB->addSuccessor(loopMBB);
4266 // <binop> scratch2, dest, incr
4267 // strex scratch, scratch2, ptr
4270 // fallthrough --> exitMBB
4272 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
4274 // operand order needs to go the other way for NAND
4275 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr)
4276 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
4277 addReg(incr).addReg(dest)).addReg(0);
4279 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
4280 addReg(dest).addReg(incr)).addReg(0);
4283 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2)
4285 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4286 .addReg(scratch).addImm(0));
4287 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4288 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
4290 BB->addSuccessor(loopMBB);
4291 BB->addSuccessor(exitMBB);
4297 MI->eraseFromParent(); // The instruction is gone now.
4303 MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
4304 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
4305 E = MBB->succ_end(); I != E; ++I)
4308 llvm_unreachable("Expecting a BB with two successors!");
4312 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4313 MachineBasicBlock *BB) const {
4314 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4315 DebugLoc dl = MI->getDebugLoc();
4316 bool isThumb2 = Subtarget->isThumb2();
4317 switch (MI->getOpcode()) {
4320 llvm_unreachable("Unexpected instr type to insert");
4322 case ARM::ATOMIC_LOAD_ADD_I8:
4323 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
4324 case ARM::ATOMIC_LOAD_ADD_I16:
4325 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
4326 case ARM::ATOMIC_LOAD_ADD_I32:
4327 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
4329 case ARM::ATOMIC_LOAD_AND_I8:
4330 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
4331 case ARM::ATOMIC_LOAD_AND_I16:
4332 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
4333 case ARM::ATOMIC_LOAD_AND_I32:
4334 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
4336 case ARM::ATOMIC_LOAD_OR_I8:
4337 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
4338 case ARM::ATOMIC_LOAD_OR_I16:
4339 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
4340 case ARM::ATOMIC_LOAD_OR_I32:
4341 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
4343 case ARM::ATOMIC_LOAD_XOR_I8:
4344 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
4345 case ARM::ATOMIC_LOAD_XOR_I16:
4346 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
4347 case ARM::ATOMIC_LOAD_XOR_I32:
4348 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
4350 case ARM::ATOMIC_LOAD_NAND_I8:
4351 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
4352 case ARM::ATOMIC_LOAD_NAND_I16:
4353 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
4354 case ARM::ATOMIC_LOAD_NAND_I32:
4355 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
4357 case ARM::ATOMIC_LOAD_SUB_I8:
4358 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
4359 case ARM::ATOMIC_LOAD_SUB_I16:
4360 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
4361 case ARM::ATOMIC_LOAD_SUB_I32:
4362 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
4364 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0);
4365 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0);
4366 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0);
4368 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1);
4369 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
4370 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
4372 case ARM::tMOVCCr_pseudo: {
4373 // To "insert" a SELECT_CC instruction, we actually have to insert the
4374 // diamond control-flow pattern. The incoming instruction knows the
4375 // destination vreg to set, the condition code register to branch on, the
4376 // true/false values to select between, and a branch opcode to use.
4377 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4378 MachineFunction::iterator It = BB;
4384 // cmpTY ccX, r1, r2
4386 // fallthrough --> copy0MBB
4387 MachineBasicBlock *thisMBB = BB;
4388 MachineFunction *F = BB->getParent();
4389 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4390 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
4391 F->insert(It, copy0MBB);
4392 F->insert(It, sinkMBB);
4394 // Transfer the remainder of BB and its successor edges to sinkMBB.
4395 sinkMBB->splice(sinkMBB->begin(), BB,
4396 llvm::next(MachineBasicBlock::iterator(MI)),
4398 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
4400 BB->addSuccessor(copy0MBB);
4401 BB->addSuccessor(sinkMBB);
4403 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
4404 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
4407 // %FalseValue = ...
4408 // # fallthrough to sinkMBB
4411 // Update machine-CFG edges
4412 BB->addSuccessor(sinkMBB);
4415 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
4418 BuildMI(*BB, BB->begin(), dl,
4419 TII->get(ARM::PHI), MI->getOperand(0).getReg())
4420 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
4421 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
4423 MI->eraseFromParent(); // The pseudo instruction is gone now.
4428 case ARM::BCCZi64: {
4429 // Compare both parts that make up the double comparison separately for
4431 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
4433 unsigned LHS1 = MI->getOperand(1).getReg();
4434 unsigned LHS2 = MI->getOperand(2).getReg();
4436 AddDefaultPred(BuildMI(BB, dl,
4437 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4438 .addReg(LHS1).addImm(0));
4439 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4440 .addReg(LHS2).addImm(0)
4441 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
4443 unsigned RHS1 = MI->getOperand(3).getReg();
4444 unsigned RHS2 = MI->getOperand(4).getReg();
4445 AddDefaultPred(BuildMI(BB, dl,
4446 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
4447 .addReg(LHS1).addReg(RHS1));
4448 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
4449 .addReg(LHS2).addReg(RHS2)
4450 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
4453 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB();
4454 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
4455 if (MI->getOperand(0).getImm() == ARMCC::NE)
4456 std::swap(destMBB, exitMBB);
4458 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4459 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
4460 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2B : ARM::B))
4463 MI->eraseFromParent(); // The pseudo instruction is gone now.
4469 //===----------------------------------------------------------------------===//
4470 // ARM Optimization Hooks
4471 //===----------------------------------------------------------------------===//
4474 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
4475 TargetLowering::DAGCombinerInfo &DCI) {
4476 SelectionDAG &DAG = DCI.DAG;
4477 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4478 EVT VT = N->getValueType(0);
4479 unsigned Opc = N->getOpcode();
4480 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
4481 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
4482 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
4483 ISD::CondCode CC = ISD::SETCC_INVALID;
4486 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
4488 SDValue CCOp = Slct.getOperand(0);
4489 if (CCOp.getOpcode() == ISD::SETCC)
4490 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
4493 bool DoXform = false;
4495 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
4498 if (LHS.getOpcode() == ISD::Constant &&
4499 cast<ConstantSDNode>(LHS)->isNullValue()) {
4501 } else if (CC != ISD::SETCC_INVALID &&
4502 RHS.getOpcode() == ISD::Constant &&
4503 cast<ConstantSDNode>(RHS)->isNullValue()) {
4504 std::swap(LHS, RHS);
4505 SDValue Op0 = Slct.getOperand(0);
4506 EVT OpVT = isSlctCC ? Op0.getValueType() :
4507 Op0.getOperand(0).getValueType();
4508 bool isInt = OpVT.isInteger();
4509 CC = ISD::getSetCCInverse(CC, isInt);
4511 if (!TLI.isCondCodeLegal(CC, OpVT))
4512 return SDValue(); // Inverse operator isn't legal.
4519 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
4521 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
4522 Slct.getOperand(0), Slct.getOperand(1), CC);
4523 SDValue CCOp = Slct.getOperand(0);
4525 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
4526 CCOp.getOperand(0), CCOp.getOperand(1), CC);
4527 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
4528 CCOp, OtherOp, Result);
4533 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
4534 /// operands N0 and N1. This is a helper for PerformADDCombine that is
4535 /// called with the default operands, and if that fails, with commuted
4537 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
4538 TargetLowering::DAGCombinerInfo &DCI) {
4539 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
4540 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
4541 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
4542 if (Result.getNode()) return Result;
4547 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
4549 static SDValue PerformADDCombine(SDNode *N,
4550 TargetLowering::DAGCombinerInfo &DCI) {
4551 SDValue N0 = N->getOperand(0);
4552 SDValue N1 = N->getOperand(1);
4554 // First try with the default operand order.
4555 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI);
4556 if (Result.getNode())
4559 // If that didn't work, try again with the operands commuted.
4560 return PerformADDCombineWithOperands(N, N1, N0, DCI);
4563 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
4565 static SDValue PerformSUBCombine(SDNode *N,
4566 TargetLowering::DAGCombinerInfo &DCI) {
4567 SDValue N0 = N->getOperand(0);
4568 SDValue N1 = N->getOperand(1);
4570 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
4571 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
4572 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
4573 if (Result.getNode()) return Result;
4579 static SDValue PerformMULCombine(SDNode *N,
4580 TargetLowering::DAGCombinerInfo &DCI,
4581 const ARMSubtarget *Subtarget) {
4582 SelectionDAG &DAG = DCI.DAG;
4584 if (Subtarget->isThumb1Only())
4587 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
4590 EVT VT = N->getValueType(0);
4594 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
4598 uint64_t MulAmt = C->getZExtValue();
4599 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt);
4600 ShiftAmt = ShiftAmt & (32 - 1);
4601 SDValue V = N->getOperand(0);
4602 DebugLoc DL = N->getDebugLoc();
4605 MulAmt >>= ShiftAmt;
4606 if (isPowerOf2_32(MulAmt - 1)) {
4607 // (mul x, 2^N + 1) => (add (shl x, N), x)
4608 Res = DAG.getNode(ISD::ADD, DL, VT,
4609 V, DAG.getNode(ISD::SHL, DL, VT,
4610 V, DAG.getConstant(Log2_32(MulAmt-1),
4612 } else if (isPowerOf2_32(MulAmt + 1)) {
4613 // (mul x, 2^N - 1) => (sub (shl x, N), x)
4614 Res = DAG.getNode(ISD::SUB, DL, VT,
4615 DAG.getNode(ISD::SHL, DL, VT,
4616 V, DAG.getConstant(Log2_32(MulAmt+1),
4623 Res = DAG.getNode(ISD::SHL, DL, VT, Res,
4624 DAG.getConstant(ShiftAmt, MVT::i32));
4626 // Do not add new nodes to DAG combiner worklist.
4627 DCI.CombineTo(N, Res, false);
4631 static SDValue PerformANDCombine(SDNode *N,
4632 TargetLowering::DAGCombinerInfo &DCI) {
4633 // Attempt to use immediate-form VBIC
4634 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
4635 DebugLoc dl = N->getDebugLoc();
4636 EVT VT = N->getValueType(0);
4637 SelectionDAG &DAG = DCI.DAG;
4639 APInt SplatBits, SplatUndef;
4640 unsigned SplatBitSize;
4643 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
4644 if (SplatBitSize <= 64) {
4646 SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(),
4647 SplatUndef.getZExtValue(), SplatBitSize,
4648 DAG, VbicVT, VT.is128BitVector(),
4650 if (Val.getNode()) {
4652 DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0));
4653 SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val);
4654 return DAG.getNode(ISD::BITCAST, dl, VT, Vbic);
4662 /// PerformORCombine - Target-specific dag combine xforms for ISD::OR
4663 static SDValue PerformORCombine(SDNode *N,
4664 TargetLowering::DAGCombinerInfo &DCI,
4665 const ARMSubtarget *Subtarget) {
4666 // Attempt to use immediate-form VORR
4667 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
4668 DebugLoc dl = N->getDebugLoc();
4669 EVT VT = N->getValueType(0);
4670 SelectionDAG &DAG = DCI.DAG;
4672 APInt SplatBits, SplatUndef;
4673 unsigned SplatBitSize;
4675 if (BVN && Subtarget->hasNEON() &&
4676 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
4677 if (SplatBitSize <= 64) {
4679 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
4680 SplatUndef.getZExtValue(), SplatBitSize,
4681 DAG, VorrVT, VT.is128BitVector(),
4683 if (Val.getNode()) {
4685 DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0));
4686 SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val);
4687 return DAG.getNode(ISD::BITCAST, dl, VT, Vorr);
4692 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when
4695 // BFI is only available on V6T2+
4696 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops())
4699 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
4700 DebugLoc DL = N->getDebugLoc();
4701 // 1) or (and A, mask), val => ARMbfi A, val, mask
4702 // iff (val & mask) == val
4704 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
4705 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2)
4706 // && CountPopulation_32(mask) == CountPopulation_32(~mask2)
4707 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2)
4708 // && CountPopulation_32(mask) == CountPopulation_32(~mask2)
4709 // (i.e., copy a bitfield value into another bitfield of the same width)
4710 if (N0.getOpcode() != ISD::AND)
4717 // The value and the mask need to be constants so we can verify this is
4718 // actually a bitfield set. If the mask is 0xffff, we can do better
4719 // via a movt instruction, so don't use BFI in that case.
4720 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
4723 unsigned Mask = C->getZExtValue();
4727 // Case (1): or (and A, mask), val => ARMbfi A, val, mask
4728 if ((C = dyn_cast<ConstantSDNode>(N1))) {
4729 unsigned Val = C->getZExtValue();
4730 if (!ARM::isBitFieldInvertedMask(Mask) || (Val & ~Mask) != Val)
4732 Val >>= CountTrailingZeros_32(~Mask);
4734 Res = DAG.getNode(ARMISD::BFI, DL, VT, N0.getOperand(0),
4735 DAG.getConstant(Val, MVT::i32),
4736 DAG.getConstant(Mask, MVT::i32));
4738 // Do not add new nodes to DAG combiner worklist.
4739 DCI.CombineTo(N, Res, false);
4740 } else if (N1.getOpcode() == ISD::AND) {
4741 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
4742 C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
4745 unsigned Mask2 = C->getZExtValue();
4747 if (ARM::isBitFieldInvertedMask(Mask) &&
4748 ARM::isBitFieldInvertedMask(~Mask2) &&
4749 (CountPopulation_32(Mask) == CountPopulation_32(~Mask2))) {
4750 // The pack halfword instruction works better for masks that fit it,
4751 // so use that when it's available.
4752 if (Subtarget->hasT2ExtractPack() &&
4753 (Mask == 0xffff || Mask == 0xffff0000))
4756 unsigned lsb = CountTrailingZeros_32(Mask2);
4757 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
4758 DAG.getConstant(lsb, MVT::i32));
4759 Res = DAG.getNode(ARMISD::BFI, DL, VT, N0.getOperand(0), Res,
4760 DAG.getConstant(Mask, MVT::i32));
4761 // Do not add new nodes to DAG combiner worklist.
4762 DCI.CombineTo(N, Res, false);
4763 } else if (ARM::isBitFieldInvertedMask(~Mask) &&
4764 ARM::isBitFieldInvertedMask(Mask2) &&
4765 (CountPopulation_32(~Mask) == CountPopulation_32(Mask2))) {
4766 // The pack halfword instruction works better for masks that fit it,
4767 // so use that when it's available.
4768 if (Subtarget->hasT2ExtractPack() &&
4769 (Mask2 == 0xffff || Mask2 == 0xffff0000))
4772 unsigned lsb = CountTrailingZeros_32(Mask);
4773 Res = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0),
4774 DAG.getConstant(lsb, MVT::i32));
4775 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
4776 DAG.getConstant(Mask2, MVT::i32));
4777 // Do not add new nodes to DAG combiner worklist.
4778 DCI.CombineTo(N, Res, false);
4785 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
4786 /// ARMISD::VMOVRRD.
4787 static SDValue PerformVMOVRRDCombine(SDNode *N,
4788 TargetLowering::DAGCombinerInfo &DCI) {
4789 // vmovrrd(vmovdrr x, y) -> x,y
4790 SDValue InDouble = N->getOperand(0);
4791 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
4792 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
4796 /// PerformVMOVDRRCombine - Target-specific dag combine xforms for
4797 /// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands.
4798 static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) {
4799 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X)
4800 SDValue Op0 = N->getOperand(0);
4801 SDValue Op1 = N->getOperand(1);
4802 if (Op0.getOpcode() == ISD::BITCAST)
4803 Op0 = Op0.getOperand(0);
4804 if (Op1.getOpcode() == ISD::BITCAST)
4805 Op1 = Op1.getOperand(0);
4806 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
4807 Op0.getNode() == Op1.getNode() &&
4808 Op0.getResNo() == 0 && Op1.getResNo() == 1)
4809 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
4810 N->getValueType(0), Op0.getOperand(0));
4814 /// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for
4815 /// ISD::BUILD_VECTOR.
4816 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG) {
4817 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X):
4818 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value
4819 // into a pair of GPRs, which is fine when the value is used as a scalar,
4820 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD.
4821 if (N->getNumOperands() == 2)
4822 return PerformVMOVDRRCombine(N, DAG);
4827 /// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for
4828 /// ISD::VECTOR_SHUFFLE.
4829 static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) {
4830 // The LLVM shufflevector instruction does not require the shuffle mask
4831 // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does
4832 // have that requirement. When translating to ISD::VECTOR_SHUFFLE, if the
4833 // operands do not match the mask length, they are extended by concatenating
4834 // them with undef vectors. That is probably the right thing for other
4835 // targets, but for NEON it is better to concatenate two double-register
4836 // size vector operands into a single quad-register size vector. Do that
4837 // transformation here:
4838 // shuffle(concat(v1, undef), concat(v2, undef)) ->
4839 // shuffle(concat(v1, v2), undef)
4840 SDValue Op0 = N->getOperand(0);
4841 SDValue Op1 = N->getOperand(1);
4842 if (Op0.getOpcode() != ISD::CONCAT_VECTORS ||
4843 Op1.getOpcode() != ISD::CONCAT_VECTORS ||
4844 Op0.getNumOperands() != 2 ||
4845 Op1.getNumOperands() != 2)
4847 SDValue Concat0Op1 = Op0.getOperand(1);
4848 SDValue Concat1Op1 = Op1.getOperand(1);
4849 if (Concat0Op1.getOpcode() != ISD::UNDEF ||
4850 Concat1Op1.getOpcode() != ISD::UNDEF)
4852 // Skip the transformation if any of the types are illegal.
4853 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4854 EVT VT = N->getValueType(0);
4855 if (!TLI.isTypeLegal(VT) ||
4856 !TLI.isTypeLegal(Concat0Op1.getValueType()) ||
4857 !TLI.isTypeLegal(Concat1Op1.getValueType()))
4860 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT,
4861 Op0.getOperand(0), Op1.getOperand(0));
4862 // Translate the shuffle mask.
4863 SmallVector<int, 16> NewMask;
4864 unsigned NumElts = VT.getVectorNumElements();
4865 unsigned HalfElts = NumElts/2;
4866 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
4867 for (unsigned n = 0; n < NumElts; ++n) {
4868 int MaskElt = SVN->getMaskElt(n);
4870 if (MaskElt < (int)HalfElts)
4872 else if (MaskElt >= (int)NumElts && MaskElt < (int)(NumElts + HalfElts))
4873 NewElt = HalfElts + MaskElt - NumElts;
4874 NewMask.push_back(NewElt);
4876 return DAG.getVectorShuffle(VT, N->getDebugLoc(), NewConcat,
4877 DAG.getUNDEF(VT), NewMask.data());
4880 /// CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a
4881 /// vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic
4882 /// are also VDUPLANEs. If so, combine them to a vldN-dup operation and
4884 static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
4885 SelectionDAG &DAG = DCI.DAG;
4886 EVT VT = N->getValueType(0);
4887 // vldN-dup instructions only support 64-bit vectors for N > 1.
4888 if (!VT.is64BitVector())
4891 // Check if the VDUPLANE operand is a vldN-dup intrinsic.
4892 SDNode *VLD = N->getOperand(0).getNode();
4893 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN)
4895 unsigned NumVecs = 0;
4896 unsigned NewOpc = 0;
4897 unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue();
4898 if (IntNo == Intrinsic::arm_neon_vld2lane) {
4900 NewOpc = ARMISD::VLD2DUP;
4901 } else if (IntNo == Intrinsic::arm_neon_vld3lane) {
4903 NewOpc = ARMISD::VLD3DUP;
4904 } else if (IntNo == Intrinsic::arm_neon_vld4lane) {
4906 NewOpc = ARMISD::VLD4DUP;
4911 // First check that all the vldN-lane uses are VDUPLANEs and that the lane
4912 // numbers match the load.
4913 unsigned VLDLaneNo =
4914 cast<ConstantSDNode>(VLD->getOperand(NumVecs+3))->getZExtValue();
4915 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
4917 // Ignore uses of the chain result.
4918 if (UI.getUse().getResNo() == NumVecs)
4921 if (User->getOpcode() != ARMISD::VDUPLANE ||
4922 VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue())
4926 // Create the vldN-dup node.
4929 for (n = 0; n < NumVecs; ++n)
4931 Tys[n] = MVT::Other;
4932 SDVTList SDTys = DAG.getVTList(Tys, NumVecs+1);
4933 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) };
4934 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD);
4935 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, VLD->getDebugLoc(), SDTys,
4936 Ops, 2, VLDMemInt->getMemoryVT(),
4937 VLDMemInt->getMemOperand());
4940 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
4942 unsigned ResNo = UI.getUse().getResNo();
4943 // Ignore uses of the chain result.
4944 if (ResNo == NumVecs)
4947 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo));
4950 // Now the vldN-lane intrinsic is dead except for its chain result.
4951 // Update uses of the chain.
4952 std::vector<SDValue> VLDDupResults;
4953 for (unsigned n = 0; n < NumVecs; ++n)
4954 VLDDupResults.push_back(SDValue(VLDDup.getNode(), n));
4955 VLDDupResults.push_back(SDValue(VLDDup.getNode(), NumVecs));
4956 DCI.CombineTo(VLD, VLDDupResults);
4961 /// PerformVDUPLANECombine - Target-specific dag combine xforms for
4962 /// ARMISD::VDUPLANE.
4963 static SDValue PerformVDUPLANECombine(SDNode *N,
4964 TargetLowering::DAGCombinerInfo &DCI) {
4965 SDValue Op = N->getOperand(0);
4967 // If the source is a vldN-lane (N > 1) intrinsic, and all the other uses
4968 // of that intrinsic are also VDUPLANEs, combine them to a vldN-dup operation.
4969 if (CombineVLDDUP(N, DCI))
4970 return SDValue(N, 0);
4972 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
4973 // redundant. Ignore bit_converts for now; element sizes are checked below.
4974 while (Op.getOpcode() == ISD::BITCAST)
4975 Op = Op.getOperand(0);
4976 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
4979 // Make sure the VMOV element size is not bigger than the VDUPLANE elements.
4980 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits();
4981 // The canonical VMOV for a zero vector uses a 32-bit element size.
4982 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4984 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
4986 EVT VT = N->getValueType(0);
4987 if (EltSize > VT.getVectorElementType().getSizeInBits())
4990 return DCI.DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
4993 /// getVShiftImm - Check if this is a valid build_vector for the immediate
4994 /// operand of a vector shift operation, where all the elements of the
4995 /// build_vector must have the same constant integer value.
4996 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
4997 // Ignore bit_converts.
4998 while (Op.getOpcode() == ISD::BITCAST)
4999 Op = Op.getOperand(0);
5000 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5001 APInt SplatBits, SplatUndef;
5002 unsigned SplatBitSize;
5004 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
5005 HasAnyUndefs, ElementBits) ||
5006 SplatBitSize > ElementBits)
5008 Cnt = SplatBits.getSExtValue();
5012 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
5013 /// operand of a vector shift left operation. That value must be in the range:
5014 /// 0 <= Value < ElementBits for a left shift; or
5015 /// 0 <= Value <= ElementBits for a long left shift.
5016 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
5017 assert(VT.isVector() && "vector shift count is not a vector type");
5018 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
5019 if (! getVShiftImm(Op, ElementBits, Cnt))
5021 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
5024 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
5025 /// operand of a vector shift right operation. For a shift opcode, the value
5026 /// is positive, but for an intrinsic the value count must be negative. The
5027 /// absolute value must be in the range:
5028 /// 1 <= |Value| <= ElementBits for a right shift; or
5029 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
5030 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
5032 assert(VT.isVector() && "vector shift count is not a vector type");
5033 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
5034 if (! getVShiftImm(Op, ElementBits, Cnt))
5038 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
5041 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
5042 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
5043 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
5046 // Don't do anything for most intrinsics.
5049 // Vector shifts: check for immediate versions and lower them.
5050 // Note: This is done during DAG combining instead of DAG legalizing because
5051 // the build_vectors for 64-bit vector element shift counts are generally
5052 // not legal, and it is hard to see their values after they get legalized to
5053 // loads from a constant pool.
5054 case Intrinsic::arm_neon_vshifts:
5055 case Intrinsic::arm_neon_vshiftu:
5056 case Intrinsic::arm_neon_vshiftls:
5057 case Intrinsic::arm_neon_vshiftlu:
5058 case Intrinsic::arm_neon_vshiftn:
5059 case Intrinsic::arm_neon_vrshifts:
5060 case Intrinsic::arm_neon_vrshiftu:
5061 case Intrinsic::arm_neon_vrshiftn:
5062 case Intrinsic::arm_neon_vqshifts:
5063 case Intrinsic::arm_neon_vqshiftu:
5064 case Intrinsic::arm_neon_vqshiftsu:
5065 case Intrinsic::arm_neon_vqshiftns:
5066 case Intrinsic::arm_neon_vqshiftnu:
5067 case Intrinsic::arm_neon_vqshiftnsu:
5068 case Intrinsic::arm_neon_vqrshiftns:
5069 case Intrinsic::arm_neon_vqrshiftnu:
5070 case Intrinsic::arm_neon_vqrshiftnsu: {
5071 EVT VT = N->getOperand(1).getValueType();
5073 unsigned VShiftOpc = 0;
5076 case Intrinsic::arm_neon_vshifts:
5077 case Intrinsic::arm_neon_vshiftu:
5078 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
5079 VShiftOpc = ARMISD::VSHL;
5082 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
5083 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
5084 ARMISD::VSHRs : ARMISD::VSHRu);
5089 case Intrinsic::arm_neon_vshiftls:
5090 case Intrinsic::arm_neon_vshiftlu:
5091 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
5093 llvm_unreachable("invalid shift count for vshll intrinsic");
5095 case Intrinsic::arm_neon_vrshifts:
5096 case Intrinsic::arm_neon_vrshiftu:
5097 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
5101 case Intrinsic::arm_neon_vqshifts:
5102 case Intrinsic::arm_neon_vqshiftu:
5103 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
5107 case Intrinsic::arm_neon_vqshiftsu:
5108 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
5110 llvm_unreachable("invalid shift count for vqshlu intrinsic");
5112 case Intrinsic::arm_neon_vshiftn:
5113 case Intrinsic::arm_neon_vrshiftn:
5114 case Intrinsic::arm_neon_vqshiftns:
5115 case Intrinsic::arm_neon_vqshiftnu:
5116 case Intrinsic::arm_neon_vqshiftnsu:
5117 case Intrinsic::arm_neon_vqrshiftns:
5118 case Intrinsic::arm_neon_vqrshiftnu:
5119 case Intrinsic::arm_neon_vqrshiftnsu:
5120 // Narrowing shifts require an immediate right shift.
5121 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
5123 llvm_unreachable("invalid shift count for narrowing vector shift "
5127 llvm_unreachable("unhandled vector shift");
5131 case Intrinsic::arm_neon_vshifts:
5132 case Intrinsic::arm_neon_vshiftu:
5133 // Opcode already set above.
5135 case Intrinsic::arm_neon_vshiftls:
5136 case Intrinsic::arm_neon_vshiftlu:
5137 if (Cnt == VT.getVectorElementType().getSizeInBits())
5138 VShiftOpc = ARMISD::VSHLLi;
5140 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
5141 ARMISD::VSHLLs : ARMISD::VSHLLu);
5143 case Intrinsic::arm_neon_vshiftn:
5144 VShiftOpc = ARMISD::VSHRN; break;
5145 case Intrinsic::arm_neon_vrshifts:
5146 VShiftOpc = ARMISD::VRSHRs; break;
5147 case Intrinsic::arm_neon_vrshiftu:
5148 VShiftOpc = ARMISD::VRSHRu; break;
5149 case Intrinsic::arm_neon_vrshiftn:
5150 VShiftOpc = ARMISD::VRSHRN; break;
5151 case Intrinsic::arm_neon_vqshifts:
5152 VShiftOpc = ARMISD::VQSHLs; break;
5153 case Intrinsic::arm_neon_vqshiftu:
5154 VShiftOpc = ARMISD::VQSHLu; break;
5155 case Intrinsic::arm_neon_vqshiftsu:
5156 VShiftOpc = ARMISD::VQSHLsu; break;
5157 case Intrinsic::arm_neon_vqshiftns:
5158 VShiftOpc = ARMISD::VQSHRNs; break;
5159 case Intrinsic::arm_neon_vqshiftnu:
5160 VShiftOpc = ARMISD::VQSHRNu; break;
5161 case Intrinsic::arm_neon_vqshiftnsu:
5162 VShiftOpc = ARMISD::VQSHRNsu; break;
5163 case Intrinsic::arm_neon_vqrshiftns:
5164 VShiftOpc = ARMISD::VQRSHRNs; break;
5165 case Intrinsic::arm_neon_vqrshiftnu:
5166 VShiftOpc = ARMISD::VQRSHRNu; break;
5167 case Intrinsic::arm_neon_vqrshiftnsu:
5168 VShiftOpc = ARMISD::VQRSHRNsu; break;
5171 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
5172 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
5175 case Intrinsic::arm_neon_vshiftins: {
5176 EVT VT = N->getOperand(1).getValueType();
5178 unsigned VShiftOpc = 0;
5180 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
5181 VShiftOpc = ARMISD::VSLI;
5182 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
5183 VShiftOpc = ARMISD::VSRI;
5185 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
5188 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
5189 N->getOperand(1), N->getOperand(2),
5190 DAG.getConstant(Cnt, MVT::i32));
5193 case Intrinsic::arm_neon_vqrshifts:
5194 case Intrinsic::arm_neon_vqrshiftu:
5195 // No immediate versions of these to check for.
5202 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
5203 /// lowers them. As with the vector shift intrinsics, this is done during DAG
5204 /// combining instead of DAG legalizing because the build_vectors for 64-bit
5205 /// vector element shift counts are generally not legal, and it is hard to see
5206 /// their values after they get legalized to loads from a constant pool.
5207 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
5208 const ARMSubtarget *ST) {
5209 EVT VT = N->getValueType(0);
5211 // Nothing to be done for scalar shifts.
5212 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5213 if (!VT.isVector() || !TLI.isTypeLegal(VT))
5216 assert(ST->hasNEON() && "unexpected vector shift");
5219 switch (N->getOpcode()) {
5220 default: llvm_unreachable("unexpected shift opcode");
5223 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
5224 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
5225 DAG.getConstant(Cnt, MVT::i32));
5230 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
5231 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
5232 ARMISD::VSHRs : ARMISD::VSHRu);
5233 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
5234 DAG.getConstant(Cnt, MVT::i32));
5240 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
5241 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
5242 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
5243 const ARMSubtarget *ST) {
5244 SDValue N0 = N->getOperand(0);
5246 // Check for sign- and zero-extensions of vector extract operations of 8-
5247 // and 16-bit vector elements. NEON supports these directly. They are
5248 // handled during DAG combining because type legalization will promote them
5249 // to 32-bit types and it is messy to recognize the operations after that.
5250 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
5251 SDValue Vec = N0.getOperand(0);
5252 SDValue Lane = N0.getOperand(1);
5253 EVT VT = N->getValueType(0);
5254 EVT EltVT = N0.getValueType();
5255 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5257 if (VT == MVT::i32 &&
5258 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
5259 TLI.isTypeLegal(Vec.getValueType()) &&
5260 isa<ConstantSDNode>(Lane)) {
5263 switch (N->getOpcode()) {
5264 default: llvm_unreachable("unexpected opcode");
5265 case ISD::SIGN_EXTEND:
5266 Opc = ARMISD::VGETLANEs;
5268 case ISD::ZERO_EXTEND:
5269 case ISD::ANY_EXTEND:
5270 Opc = ARMISD::VGETLANEu;
5273 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
5280 /// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
5281 /// to match f32 max/min patterns to use NEON vmax/vmin instructions.
5282 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
5283 const ARMSubtarget *ST) {
5284 // If the target supports NEON, try to use vmax/vmin instructions for f32
5285 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set,
5286 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
5287 // a NaN; only do the transformation when it matches that behavior.
5289 // For now only do this when using NEON for FP operations; if using VFP, it
5290 // is not obvious that the benefit outweighs the cost of switching to the
5292 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
5293 N->getValueType(0) != MVT::f32)
5296 SDValue CondLHS = N->getOperand(0);
5297 SDValue CondRHS = N->getOperand(1);
5298 SDValue LHS = N->getOperand(2);
5299 SDValue RHS = N->getOperand(3);
5300 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
5302 unsigned Opcode = 0;
5304 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
5305 IsReversed = false; // x CC y ? x : y
5306 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
5307 IsReversed = true ; // x CC y ? y : x
5321 // If LHS is NaN, an ordered comparison will be false and the result will
5322 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
5323 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
5324 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
5325 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
5327 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
5328 // will return -0, so vmin can only be used for unsafe math or if one of
5329 // the operands is known to be nonzero.
5330 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
5332 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
5334 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
5343 // If LHS is NaN, an ordered comparison will be false and the result will
5344 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
5345 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
5346 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
5347 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
5349 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
5350 // will return +0, so vmax can only be used for unsafe math or if one of
5351 // the operands is known to be nonzero.
5352 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
5354 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
5356 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
5362 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS);
5365 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
5366 DAGCombinerInfo &DCI) const {
5367 switch (N->getOpcode()) {
5369 case ISD::ADD: return PerformADDCombine(N, DCI);
5370 case ISD::SUB: return PerformSUBCombine(N, DCI);
5371 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
5372 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
5373 case ISD::AND: return PerformANDCombine(N, DCI);
5374 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
5375 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
5376 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI.DAG);
5377 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
5378 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
5379 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
5382 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
5383 case ISD::SIGN_EXTEND:
5384 case ISD::ZERO_EXTEND:
5385 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
5386 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
5391 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
5392 if (!Subtarget->allowsUnalignedMem())
5395 switch (VT.getSimpleVT().SimpleTy) {
5402 // FIXME: VLD1 etc with standard alignment is legal.
5406 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
5411 switch (VT.getSimpleVT().SimpleTy) {
5412 default: return false;
5427 if ((V & (Scale - 1)) != 0)
5430 return V == (V & ((1LL << 5) - 1));
5433 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
5434 const ARMSubtarget *Subtarget) {
5441 switch (VT.getSimpleVT().SimpleTy) {
5442 default: return false;
5447 // + imm12 or - imm8
5449 return V == (V & ((1LL << 8) - 1));
5450 return V == (V & ((1LL << 12) - 1));
5453 // Same as ARM mode. FIXME: NEON?
5454 if (!Subtarget->hasVFP2())
5459 return V == (V & ((1LL << 8) - 1));
5463 /// isLegalAddressImmediate - Return true if the integer value can be used
5464 /// as the offset of the target addressing mode for load / store of the
5466 static bool isLegalAddressImmediate(int64_t V, EVT VT,
5467 const ARMSubtarget *Subtarget) {
5474 if (Subtarget->isThumb1Only())
5475 return isLegalT1AddressImmediate(V, VT);
5476 else if (Subtarget->isThumb2())
5477 return isLegalT2AddressImmediate(V, VT, Subtarget);
5482 switch (VT.getSimpleVT().SimpleTy) {
5483 default: return false;
5488 return V == (V & ((1LL << 12) - 1));
5491 return V == (V & ((1LL << 8) - 1));
5494 if (!Subtarget->hasVFP2()) // FIXME: NEON?
5499 return V == (V & ((1LL << 8) - 1));
5503 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
5505 int Scale = AM.Scale;
5509 switch (VT.getSimpleVT().SimpleTy) {
5510 default: return false;
5519 return Scale == 2 || Scale == 4 || Scale == 8;
5522 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
5526 // Note, we allow "void" uses (basically, uses that aren't loads or
5527 // stores), because arm allows folding a scale into many arithmetic
5528 // operations. This should be made more precise and revisited later.
5530 // Allow r << imm, but the imm has to be a multiple of two.
5531 if (Scale & 1) return false;
5532 return isPowerOf2_32(Scale);
5536 /// isLegalAddressingMode - Return true if the addressing mode represented
5537 /// by AM is legal for this target, for a load/store of the specified type.
5538 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
5539 const Type *Ty) const {
5540 EVT VT = getValueType(Ty, true);
5541 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
5544 // Can never fold addr of global into load/store.
5549 case 0: // no scale reg, must be "r+i" or "r", or "i".
5552 if (Subtarget->isThumb1Only())
5556 // ARM doesn't support any R+R*scale+imm addr modes.
5563 if (Subtarget->isThumb2())
5564 return isLegalT2ScaledAddressingMode(AM, VT);
5566 int Scale = AM.Scale;
5567 switch (VT.getSimpleVT().SimpleTy) {
5568 default: return false;
5572 if (Scale < 0) Scale = -Scale;
5576 return isPowerOf2_32(Scale & ~1);
5580 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
5585 // Note, we allow "void" uses (basically, uses that aren't loads or
5586 // stores), because arm allows folding a scale into many arithmetic
5587 // operations. This should be made more precise and revisited later.
5589 // Allow r << imm, but the imm has to be a multiple of two.
5590 if (Scale & 1) return false;
5591 return isPowerOf2_32(Scale);
5598 /// isLegalICmpImmediate - Return true if the specified immediate is legal
5599 /// icmp immediate, that is the target has icmp instructions which can compare
5600 /// a register against the immediate without having to materialize the
5601 /// immediate into a register.
5602 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
5603 if (!Subtarget->isThumb())
5604 return ARM_AM::getSOImmVal(Imm) != -1;
5605 if (Subtarget->isThumb2())
5606 return ARM_AM::getT2SOImmVal(Imm) != -1;
5607 return Imm >= 0 && Imm <= 255;
5610 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
5611 bool isSEXTLoad, SDValue &Base,
5612 SDValue &Offset, bool &isInc,
5613 SelectionDAG &DAG) {
5614 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
5617 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
5619 Base = Ptr->getOperand(0);
5620 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
5621 int RHSC = (int)RHS->getZExtValue();
5622 if (RHSC < 0 && RHSC > -256) {
5623 assert(Ptr->getOpcode() == ISD::ADD);
5625 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
5629 isInc = (Ptr->getOpcode() == ISD::ADD);
5630 Offset = Ptr->getOperand(1);
5632 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
5634 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
5635 int RHSC = (int)RHS->getZExtValue();
5636 if (RHSC < 0 && RHSC > -0x1000) {
5637 assert(Ptr->getOpcode() == ISD::ADD);
5639 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
5640 Base = Ptr->getOperand(0);
5645 if (Ptr->getOpcode() == ISD::ADD) {
5647 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
5648 if (ShOpcVal != ARM_AM::no_shift) {
5649 Base = Ptr->getOperand(1);
5650 Offset = Ptr->getOperand(0);
5652 Base = Ptr->getOperand(0);
5653 Offset = Ptr->getOperand(1);
5658 isInc = (Ptr->getOpcode() == ISD::ADD);
5659 Base = Ptr->getOperand(0);
5660 Offset = Ptr->getOperand(1);
5664 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
5668 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
5669 bool isSEXTLoad, SDValue &Base,
5670 SDValue &Offset, bool &isInc,
5671 SelectionDAG &DAG) {
5672 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
5675 Base = Ptr->getOperand(0);
5676 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
5677 int RHSC = (int)RHS->getZExtValue();
5678 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
5679 assert(Ptr->getOpcode() == ISD::ADD);
5681 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
5683 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
5684 isInc = Ptr->getOpcode() == ISD::ADD;
5685 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
5693 /// getPreIndexedAddressParts - returns true by value, base pointer and
5694 /// offset pointer and addressing mode by reference if the node's address
5695 /// can be legally represented as pre-indexed load / store address.
5697 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
5699 ISD::MemIndexedMode &AM,
5700 SelectionDAG &DAG) const {
5701 if (Subtarget->isThumb1Only())
5706 bool isSEXTLoad = false;
5707 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5708 Ptr = LD->getBasePtr();
5709 VT = LD->getMemoryVT();
5710 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
5711 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5712 Ptr = ST->getBasePtr();
5713 VT = ST->getMemoryVT();
5718 bool isLegal = false;
5719 if (Subtarget->isThumb2())
5720 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
5721 Offset, isInc, DAG);
5723 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
5724 Offset, isInc, DAG);
5728 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
5732 /// getPostIndexedAddressParts - returns true by value, base pointer and
5733 /// offset pointer and addressing mode by reference if this node can be
5734 /// combined with a load / store to form a post-indexed load / store.
5735 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
5738 ISD::MemIndexedMode &AM,
5739 SelectionDAG &DAG) const {
5740 if (Subtarget->isThumb1Only())
5745 bool isSEXTLoad = false;
5746 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5747 VT = LD->getMemoryVT();
5748 Ptr = LD->getBasePtr();
5749 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
5750 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5751 VT = ST->getMemoryVT();
5752 Ptr = ST->getBasePtr();
5757 bool isLegal = false;
5758 if (Subtarget->isThumb2())
5759 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
5762 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
5768 // Swap base ptr and offset to catch more post-index load / store when
5769 // it's legal. In Thumb2 mode, offset must be an immediate.
5770 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
5771 !Subtarget->isThumb2())
5772 std::swap(Base, Offset);
5774 // Post-indexed load / store update the base pointer.
5779 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
5783 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
5787 const SelectionDAG &DAG,
5788 unsigned Depth) const {
5789 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
5790 switch (Op.getOpcode()) {
5792 case ARMISD::CMOV: {
5793 // Bits are known zero/one if known on the LHS and RHS.
5794 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
5795 if (KnownZero == 0 && KnownOne == 0) return;
5797 APInt KnownZeroRHS, KnownOneRHS;
5798 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
5799 KnownZeroRHS, KnownOneRHS, Depth+1);
5800 KnownZero &= KnownZeroRHS;
5801 KnownOne &= KnownOneRHS;
5807 //===----------------------------------------------------------------------===//
5808 // ARM Inline Assembly Support
5809 //===----------------------------------------------------------------------===//
5811 /// getConstraintType - Given a constraint letter, return the type of
5812 /// constraint it is for this target.
5813 ARMTargetLowering::ConstraintType
5814 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
5815 if (Constraint.size() == 1) {
5816 switch (Constraint[0]) {
5818 case 'l': return C_RegisterClass;
5819 case 'w': return C_RegisterClass;
5822 return TargetLowering::getConstraintType(Constraint);
5825 /// Examine constraint type and operand type and determine a weight value.
5826 /// This object must already have been set up with the operand type
5827 /// and the current alternative constraint selected.
5828 TargetLowering::ConstraintWeight
5829 ARMTargetLowering::getSingleConstraintMatchWeight(
5830 AsmOperandInfo &info, const char *constraint) const {
5831 ConstraintWeight weight = CW_Invalid;
5832 Value *CallOperandVal = info.CallOperandVal;
5833 // If we don't have a value, we can't do a match,
5834 // but allow it at the lowest weight.
5835 if (CallOperandVal == NULL)
5837 const Type *type = CallOperandVal->getType();
5838 // Look at the constraint type.
5839 switch (*constraint) {
5841 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
5844 if (type->isIntegerTy()) {
5845 if (Subtarget->isThumb())
5846 weight = CW_SpecificReg;
5848 weight = CW_Register;
5852 if (type->isFloatingPointTy())
5853 weight = CW_Register;
5859 std::pair<unsigned, const TargetRegisterClass*>
5860 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
5862 if (Constraint.size() == 1) {
5863 // GCC ARM Constraint Letters
5864 switch (Constraint[0]) {
5866 if (Subtarget->isThumb())
5867 return std::make_pair(0U, ARM::tGPRRegisterClass);
5869 return std::make_pair(0U, ARM::GPRRegisterClass);
5871 return std::make_pair(0U, ARM::GPRRegisterClass);
5874 return std::make_pair(0U, ARM::SPRRegisterClass);
5875 if (VT.getSizeInBits() == 64)
5876 return std::make_pair(0U, ARM::DPRRegisterClass);
5877 if (VT.getSizeInBits() == 128)
5878 return std::make_pair(0U, ARM::QPRRegisterClass);
5882 if (StringRef("{cc}").equals_lower(Constraint))
5883 return std::make_pair(unsigned(ARM::CPSR), ARM::CCRRegisterClass);
5885 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
5888 std::vector<unsigned> ARMTargetLowering::
5889 getRegClassForInlineAsmConstraint(const std::string &Constraint,
5891 if (Constraint.size() != 1)
5892 return std::vector<unsigned>();
5894 switch (Constraint[0]) { // GCC ARM Constraint Letters
5897 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
5898 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
5901 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
5902 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
5903 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
5904 ARM::R12, ARM::LR, 0);
5907 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
5908 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
5909 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
5910 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
5911 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
5912 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
5913 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
5914 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
5915 if (VT.getSizeInBits() == 64)
5916 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
5917 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
5918 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
5919 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
5920 if (VT.getSizeInBits() == 128)
5921 return make_vector<unsigned>(ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
5922 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 0);
5926 return std::vector<unsigned>();
5929 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
5930 /// vector. If it is invalid, don't add anything to Ops.
5931 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
5933 std::vector<SDValue>&Ops,
5934 SelectionDAG &DAG) const {
5935 SDValue Result(0, 0);
5937 switch (Constraint) {
5939 case 'I': case 'J': case 'K': case 'L':
5940 case 'M': case 'N': case 'O':
5941 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
5945 int64_t CVal64 = C->getSExtValue();
5946 int CVal = (int) CVal64;
5947 // None of these constraints allow values larger than 32 bits. Check
5948 // that the value fits in an int.
5952 switch (Constraint) {
5954 if (Subtarget->isThumb1Only()) {
5955 // This must be a constant between 0 and 255, for ADD
5957 if (CVal >= 0 && CVal <= 255)
5959 } else if (Subtarget->isThumb2()) {
5960 // A constant that can be used as an immediate value in a
5961 // data-processing instruction.
5962 if (ARM_AM::getT2SOImmVal(CVal) != -1)
5965 // A constant that can be used as an immediate value in a
5966 // data-processing instruction.
5967 if (ARM_AM::getSOImmVal(CVal) != -1)
5973 if (Subtarget->isThumb()) { // FIXME thumb2
5974 // This must be a constant between -255 and -1, for negated ADD
5975 // immediates. This can be used in GCC with an "n" modifier that
5976 // prints the negated value, for use with SUB instructions. It is
5977 // not useful otherwise but is implemented for compatibility.
5978 if (CVal >= -255 && CVal <= -1)
5981 // This must be a constant between -4095 and 4095. It is not clear
5982 // what this constraint is intended for. Implemented for
5983 // compatibility with GCC.
5984 if (CVal >= -4095 && CVal <= 4095)
5990 if (Subtarget->isThumb1Only()) {
5991 // A 32-bit value where only one byte has a nonzero value. Exclude
5992 // zero to match GCC. This constraint is used by GCC internally for
5993 // constants that can be loaded with a move/shift combination.
5994 // It is not useful otherwise but is implemented for compatibility.
5995 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
5997 } else if (Subtarget->isThumb2()) {
5998 // A constant whose bitwise inverse can be used as an immediate
5999 // value in a data-processing instruction. This can be used in GCC
6000 // with a "B" modifier that prints the inverted value, for use with
6001 // BIC and MVN instructions. It is not useful otherwise but is
6002 // implemented for compatibility.
6003 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
6006 // A constant whose bitwise inverse can be used as an immediate
6007 // value in a data-processing instruction. This can be used in GCC
6008 // with a "B" modifier that prints the inverted value, for use with
6009 // BIC and MVN instructions. It is not useful otherwise but is
6010 // implemented for compatibility.
6011 if (ARM_AM::getSOImmVal(~CVal) != -1)
6017 if (Subtarget->isThumb1Only()) {
6018 // This must be a constant between -7 and 7,
6019 // for 3-operand ADD/SUB immediate instructions.
6020 if (CVal >= -7 && CVal < 7)
6022 } else if (Subtarget->isThumb2()) {
6023 // A constant whose negation can be used as an immediate value in a
6024 // data-processing instruction. This can be used in GCC with an "n"
6025 // modifier that prints the negated value, for use with SUB
6026 // instructions. It is not useful otherwise but is implemented for
6028 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
6031 // A constant whose negation can be used as an immediate value in a
6032 // data-processing instruction. This can be used in GCC with an "n"
6033 // modifier that prints the negated value, for use with SUB
6034 // instructions. It is not useful otherwise but is implemented for
6036 if (ARM_AM::getSOImmVal(-CVal) != -1)
6042 if (Subtarget->isThumb()) { // FIXME thumb2
6043 // This must be a multiple of 4 between 0 and 1020, for
6044 // ADD sp + immediate.
6045 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
6048 // A power of two or a constant between 0 and 32. This is used in
6049 // GCC for the shift amount on shifted register operands, but it is
6050 // useful in general for any shift amounts.
6051 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
6057 if (Subtarget->isThumb()) { // FIXME thumb2
6058 // This must be a constant between 0 and 31, for shift amounts.
6059 if (CVal >= 0 && CVal <= 31)
6065 if (Subtarget->isThumb()) { // FIXME thumb2
6066 // This must be a multiple of 4 between -508 and 508, for
6067 // ADD/SUB sp = sp + immediate.
6068 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
6073 Result = DAG.getTargetConstant(CVal, Op.getValueType());
6077 if (Result.getNode()) {
6078 Ops.push_back(Result);
6081 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
6085 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
6086 // The ARM target isn't yet aware of offsets.
6090 int ARM::getVFPf32Imm(const APFloat &FPImm) {
6091 APInt Imm = FPImm.bitcastToAPInt();
6092 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
6093 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127
6094 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits
6096 // We can handle 4 bits of mantissa.
6097 // mantissa = (16+UInt(e:f:g:h))/16.
6098 if (Mantissa & 0x7ffff)
6101 if ((Mantissa & 0xf) != Mantissa)
6104 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
6105 if (Exp < -3 || Exp > 4)
6107 Exp = ((Exp+3) & 0x7) ^ 4;
6109 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
6112 int ARM::getVFPf64Imm(const APFloat &FPImm) {
6113 APInt Imm = FPImm.bitcastToAPInt();
6114 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
6115 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
6116 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffLL;
6118 // We can handle 4 bits of mantissa.
6119 // mantissa = (16+UInt(e:f:g:h))/16.
6120 if (Mantissa & 0xffffffffffffLL)
6123 if ((Mantissa & 0xf) != Mantissa)
6126 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
6127 if (Exp < -3 || Exp > 4)
6129 Exp = ((Exp+3) & 0x7) ^ 4;
6131 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
6134 bool ARM::isBitFieldInvertedMask(unsigned v) {
6135 if (v == 0xffffffff)
6137 // there can be 1's on either or both "outsides", all the "inside"
6139 unsigned int lsb = 0, msb = 31;
6140 while (v & (1 << msb)) --msb;
6141 while (v & (1 << lsb)) ++lsb;
6142 for (unsigned int i = lsb; i <= msb; ++i) {
6149 /// isFPImmLegal - Returns true if the target can instruction select the
6150 /// specified FP immediate natively. If false, the legalizer will
6151 /// materialize the FP immediate as a load from a constant pool.
6152 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
6153 if (!Subtarget->hasVFP3())
6156 return ARM::getVFPf32Imm(Imm) != -1;
6158 return ARM::getVFPf64Imm(Imm) != -1;
6162 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
6163 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
6164 /// specified in the intrinsic calls.
6165 bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
6167 unsigned Intrinsic) const {
6168 switch (Intrinsic) {
6169 case Intrinsic::arm_neon_vld1:
6170 case Intrinsic::arm_neon_vld2:
6171 case Intrinsic::arm_neon_vld3:
6172 case Intrinsic::arm_neon_vld4:
6173 case Intrinsic::arm_neon_vld2lane:
6174 case Intrinsic::arm_neon_vld3lane:
6175 case Intrinsic::arm_neon_vld4lane: {
6176 Info.opc = ISD::INTRINSIC_W_CHAIN;
6177 // Conservatively set memVT to the entire set of vectors loaded.
6178 uint64_t NumElts = getTargetData()->getTypeAllocSize(I.getType()) / 8;
6179 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6180 Info.ptrVal = I.getArgOperand(0);
6182 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
6183 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
6184 Info.vol = false; // volatile loads with NEON intrinsics not supported
6185 Info.readMem = true;
6186 Info.writeMem = false;
6189 case Intrinsic::arm_neon_vst1:
6190 case Intrinsic::arm_neon_vst2:
6191 case Intrinsic::arm_neon_vst3:
6192 case Intrinsic::arm_neon_vst4:
6193 case Intrinsic::arm_neon_vst2lane:
6194 case Intrinsic::arm_neon_vst3lane:
6195 case Intrinsic::arm_neon_vst4lane: {
6196 Info.opc = ISD::INTRINSIC_VOID;
6197 // Conservatively set memVT to the entire set of vectors stored.
6198 unsigned NumElts = 0;
6199 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
6200 const Type *ArgTy = I.getArgOperand(ArgI)->getType();
6201 if (!ArgTy->isVectorTy())
6203 NumElts += getTargetData()->getTypeAllocSize(ArgTy) / 8;
6205 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6206 Info.ptrVal = I.getArgOperand(0);
6208 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
6209 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
6210 Info.vol = false; // volatile stores with NEON intrinsics not supported
6211 Info.readMem = false;
6212 Info.writeMem = true;