1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "ARMISelLowering.h"
16 #include "ARMCallingConv.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMPerfectShuffle.h"
20 #include "ARMSubtarget.h"
21 #include "ARMTargetMachine.h"
22 #include "ARMTargetObjectFile.h"
23 #include "MCTargetDesc/ARMAddressingModes.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/CodeGen/CallingConvLower.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineBasicBlock.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SelectionDAG.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalValue.h"
41 #include "llvm/IR/IRBuilder.h"
42 #include "llvm/IR/Instruction.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/IntrinsicInst.h"
45 #include "llvm/IR/Intrinsics.h"
46 #include "llvm/IR/Type.h"
47 #include "llvm/MC/MCSectionMachO.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Support/raw_ostream.h"
53 #include "llvm/Target/TargetOptions.h"
57 #define DEBUG_TYPE "arm-isel"
59 STATISTIC(NumTailCalls, "Number of tail calls");
60 STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt");
61 STATISTIC(NumLoopByVals, "Number of loops generated for byval arguments");
64 EnableARMLongCalls("arm-long-calls", cl::Hidden,
65 cl::desc("Generate calls via indirect call instructions"),
69 ARMInterworking("arm-interworking", cl::Hidden,
70 cl::desc("Enable / disable ARM interworking (for debugging only)"),
74 class ARMCCState : public CCState {
76 ARMCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
77 SmallVectorImpl<CCValAssign> &locs, LLVMContext &C,
79 : CCState(CC, isVarArg, MF, locs, C) {
80 assert(((PC == Call) || (PC == Prologue)) &&
81 "ARMCCState users must specify whether their context is call"
82 "or prologue generation.");
88 // The APCS parameter registers.
89 static const MCPhysReg GPRArgRegs[] = {
90 ARM::R0, ARM::R1, ARM::R2, ARM::R3
93 void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT,
94 MVT PromotedBitwiseVT) {
95 if (VT != PromotedLdStVT) {
96 setOperationAction(ISD::LOAD, VT, Promote);
97 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
99 setOperationAction(ISD::STORE, VT, Promote);
100 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
103 MVT ElemTy = VT.getVectorElementType();
104 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
105 setOperationAction(ISD::SETCC, VT, Custom);
106 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
107 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
108 if (ElemTy == MVT::i32) {
109 setOperationAction(ISD::SINT_TO_FP, VT, Custom);
110 setOperationAction(ISD::UINT_TO_FP, VT, Custom);
111 setOperationAction(ISD::FP_TO_SINT, VT, Custom);
112 setOperationAction(ISD::FP_TO_UINT, VT, Custom);
114 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
115 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
116 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
117 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
119 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
120 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
121 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
122 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
123 setOperationAction(ISD::SELECT, VT, Expand);
124 setOperationAction(ISD::SELECT_CC, VT, Expand);
125 setOperationAction(ISD::VSELECT, VT, Expand);
126 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
127 if (VT.isInteger()) {
128 setOperationAction(ISD::SHL, VT, Custom);
129 setOperationAction(ISD::SRA, VT, Custom);
130 setOperationAction(ISD::SRL, VT, Custom);
133 // Promote all bit-wise operations.
134 if (VT.isInteger() && VT != PromotedBitwiseVT) {
135 setOperationAction(ISD::AND, VT, Promote);
136 AddPromotedToType (ISD::AND, VT, PromotedBitwiseVT);
137 setOperationAction(ISD::OR, VT, Promote);
138 AddPromotedToType (ISD::OR, VT, PromotedBitwiseVT);
139 setOperationAction(ISD::XOR, VT, Promote);
140 AddPromotedToType (ISD::XOR, VT, PromotedBitwiseVT);
143 // Neon does not support vector divide/remainder operations.
144 setOperationAction(ISD::SDIV, VT, Expand);
145 setOperationAction(ISD::UDIV, VT, Expand);
146 setOperationAction(ISD::FDIV, VT, Expand);
147 setOperationAction(ISD::SREM, VT, Expand);
148 setOperationAction(ISD::UREM, VT, Expand);
149 setOperationAction(ISD::FREM, VT, Expand);
152 void ARMTargetLowering::addDRTypeForNEON(MVT VT) {
153 addRegisterClass(VT, &ARM::DPRRegClass);
154 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
157 void ARMTargetLowering::addQRTypeForNEON(MVT VT) {
158 addRegisterClass(VT, &ARM::DPairRegClass);
159 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
162 ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
163 const ARMSubtarget &STI)
164 : TargetLowering(TM), Subtarget(&STI) {
165 RegInfo = Subtarget->getRegisterInfo();
166 Itins = Subtarget->getInstrItineraryData();
168 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
170 if (Subtarget->isTargetMachO()) {
171 // Uses VFP for Thumb libfuncs if available.
172 if (Subtarget->isThumb() && Subtarget->hasVFP2() &&
173 Subtarget->hasARMOps() && !Subtarget->useSoftFloat()) {
174 // Single-precision floating-point arithmetic.
175 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
176 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
177 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
178 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
180 // Double-precision floating-point arithmetic.
181 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
182 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
183 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
184 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
186 // Single-precision comparisons.
187 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
188 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
189 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
190 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
191 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
192 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
193 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
194 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
196 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
197 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
198 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
199 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
200 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
201 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
202 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
203 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
205 // Double-precision comparisons.
206 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
207 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
208 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
209 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
210 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
211 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
212 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
213 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
215 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
216 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
217 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
218 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
219 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
220 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
221 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
222 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
224 // Floating-point to integer conversions.
225 // i64 conversions are done via library routines even when generating VFP
226 // instructions, so use the same ones.
227 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
228 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
229 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
230 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
232 // Conversions between floating types.
233 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
234 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
236 // Integer to floating-point conversions.
237 // i64 conversions are done via library routines even when generating VFP
238 // instructions, so use the same ones.
239 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
240 // e.g., __floatunsidf vs. __floatunssidfvfp.
241 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
242 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
243 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
244 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
248 // These libcalls are not available in 32-bit.
249 setLibcallName(RTLIB::SHL_I128, nullptr);
250 setLibcallName(RTLIB::SRL_I128, nullptr);
251 setLibcallName(RTLIB::SRA_I128, nullptr);
253 if (Subtarget->isAAPCS_ABI() && !Subtarget->isTargetMachO() &&
254 !Subtarget->isTargetWindows()) {
255 static const struct {
256 const RTLIB::Libcall Op;
257 const char * const Name;
258 const CallingConv::ID CC;
259 const ISD::CondCode Cond;
261 // Double-precision floating-point arithmetic helper functions
262 // RTABI chapter 4.1.2, Table 2
263 { RTLIB::ADD_F64, "__aeabi_dadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
264 { RTLIB::DIV_F64, "__aeabi_ddiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
265 { RTLIB::MUL_F64, "__aeabi_dmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
266 { RTLIB::SUB_F64, "__aeabi_dsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
268 // Double-precision floating-point comparison helper functions
269 // RTABI chapter 4.1.2, Table 3
270 { RTLIB::OEQ_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
271 { RTLIB::UNE_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
272 { RTLIB::OLT_F64, "__aeabi_dcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
273 { RTLIB::OLE_F64, "__aeabi_dcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
274 { RTLIB::OGE_F64, "__aeabi_dcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
275 { RTLIB::OGT_F64, "__aeabi_dcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
276 { RTLIB::UO_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
277 { RTLIB::O_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ },
279 // Single-precision floating-point arithmetic helper functions
280 // RTABI chapter 4.1.2, Table 4
281 { RTLIB::ADD_F32, "__aeabi_fadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
282 { RTLIB::DIV_F32, "__aeabi_fdiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
283 { RTLIB::MUL_F32, "__aeabi_fmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
284 { RTLIB::SUB_F32, "__aeabi_fsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
286 // Single-precision floating-point comparison helper functions
287 // RTABI chapter 4.1.2, Table 5
288 { RTLIB::OEQ_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
289 { RTLIB::UNE_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
290 { RTLIB::OLT_F32, "__aeabi_fcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
291 { RTLIB::OLE_F32, "__aeabi_fcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
292 { RTLIB::OGE_F32, "__aeabi_fcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
293 { RTLIB::OGT_F32, "__aeabi_fcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
294 { RTLIB::UO_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
295 { RTLIB::O_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ },
297 // Floating-point to integer conversions.
298 // RTABI chapter 4.1.2, Table 6
299 { RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
300 { RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
301 { RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
302 { RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
303 { RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
304 { RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
305 { RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
306 { RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
308 // Conversions between floating types.
309 // RTABI chapter 4.1.2, Table 7
310 { RTLIB::FPROUND_F64_F32, "__aeabi_d2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
311 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
312 { RTLIB::FPEXT_F32_F64, "__aeabi_f2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
314 // Integer to floating-point conversions.
315 // RTABI chapter 4.1.2, Table 8
316 { RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
317 { RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
318 { RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
319 { RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
320 { RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
321 { RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
322 { RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
323 { RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
325 // Long long helper functions
326 // RTABI chapter 4.2, Table 9
327 { RTLIB::MUL_I64, "__aeabi_lmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
328 { RTLIB::SHL_I64, "__aeabi_llsl", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
329 { RTLIB::SRL_I64, "__aeabi_llsr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
330 { RTLIB::SRA_I64, "__aeabi_lasr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
332 // Integer division functions
333 // RTABI chapter 4.3.1
334 { RTLIB::SDIV_I8, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
335 { RTLIB::SDIV_I16, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
336 { RTLIB::SDIV_I32, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
337 { RTLIB::SDIV_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
338 { RTLIB::UDIV_I8, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
339 { RTLIB::UDIV_I16, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
340 { RTLIB::UDIV_I32, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
341 { RTLIB::UDIV_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
344 // RTABI chapter 4.3.4
345 { RTLIB::MEMCPY, "__aeabi_memcpy", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
346 { RTLIB::MEMMOVE, "__aeabi_memmove", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
347 { RTLIB::MEMSET, "__aeabi_memset", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
350 for (const auto &LC : LibraryCalls) {
351 setLibcallName(LC.Op, LC.Name);
352 setLibcallCallingConv(LC.Op, LC.CC);
353 if (LC.Cond != ISD::SETCC_INVALID)
354 setCmpLibcallCC(LC.Op, LC.Cond);
358 if (Subtarget->isTargetWindows()) {
359 static const struct {
360 const RTLIB::Libcall Op;
361 const char * const Name;
362 const CallingConv::ID CC;
364 { RTLIB::FPTOSINT_F32_I64, "__stoi64", CallingConv::ARM_AAPCS_VFP },
365 { RTLIB::FPTOSINT_F64_I64, "__dtoi64", CallingConv::ARM_AAPCS_VFP },
366 { RTLIB::FPTOUINT_F32_I64, "__stou64", CallingConv::ARM_AAPCS_VFP },
367 { RTLIB::FPTOUINT_F64_I64, "__dtou64", CallingConv::ARM_AAPCS_VFP },
368 { RTLIB::SINTTOFP_I64_F32, "__i64tos", CallingConv::ARM_AAPCS_VFP },
369 { RTLIB::SINTTOFP_I64_F64, "__i64tod", CallingConv::ARM_AAPCS_VFP },
370 { RTLIB::UINTTOFP_I64_F32, "__u64tos", CallingConv::ARM_AAPCS_VFP },
371 { RTLIB::UINTTOFP_I64_F64, "__u64tod", CallingConv::ARM_AAPCS_VFP },
374 for (const auto &LC : LibraryCalls) {
375 setLibcallName(LC.Op, LC.Name);
376 setLibcallCallingConv(LC.Op, LC.CC);
380 // Use divmod compiler-rt calls for iOS 5.0 and later.
381 if (Subtarget->getTargetTriple().isiOS() &&
382 !Subtarget->getTargetTriple().isOSVersionLT(5, 0)) {
383 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
384 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
387 // The half <-> float conversion functions are always soft-float, but are
388 // needed for some targets which use a hard-float calling convention by
390 if (Subtarget->isAAPCS_ABI()) {
391 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_AAPCS);
392 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_AAPCS);
393 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_AAPCS);
395 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_APCS);
396 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_APCS);
397 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_APCS);
400 if (Subtarget->isThumb1Only())
401 addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
403 addRegisterClass(MVT::i32, &ARM::GPRRegClass);
404 if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2() &&
405 !Subtarget->isThumb1Only()) {
406 addRegisterClass(MVT::f32, &ARM::SPRRegClass);
407 addRegisterClass(MVT::f64, &ARM::DPRRegClass);
410 for (MVT VT : MVT::vector_valuetypes()) {
411 for (MVT InnerVT : MVT::vector_valuetypes()) {
412 setTruncStoreAction(VT, InnerVT, Expand);
413 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
414 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
415 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
418 setOperationAction(ISD::MULHS, VT, Expand);
419 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
420 setOperationAction(ISD::MULHU, VT, Expand);
421 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
423 setOperationAction(ISD::BSWAP, VT, Expand);
426 setOperationAction(ISD::ConstantFP, MVT::f32, Custom);
427 setOperationAction(ISD::ConstantFP, MVT::f64, Custom);
429 setOperationAction(ISD::READ_REGISTER, MVT::i64, Custom);
430 setOperationAction(ISD::WRITE_REGISTER, MVT::i64, Custom);
432 if (Subtarget->hasNEON()) {
433 addDRTypeForNEON(MVT::v2f32);
434 addDRTypeForNEON(MVT::v8i8);
435 addDRTypeForNEON(MVT::v4i16);
436 addDRTypeForNEON(MVT::v2i32);
437 addDRTypeForNEON(MVT::v1i64);
439 addQRTypeForNEON(MVT::v4f32);
440 addQRTypeForNEON(MVT::v2f64);
441 addQRTypeForNEON(MVT::v16i8);
442 addQRTypeForNEON(MVT::v8i16);
443 addQRTypeForNEON(MVT::v4i32);
444 addQRTypeForNEON(MVT::v2i64);
446 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
447 // neither Neon nor VFP support any arithmetic operations on it.
448 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
449 // supported for v4f32.
450 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
451 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
452 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
453 // FIXME: Code duplication: FDIV and FREM are expanded always, see
454 // ARMTargetLowering::addTypeForNEON method for details.
455 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
456 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
457 // FIXME: Create unittest.
458 // In another words, find a way when "copysign" appears in DAG with vector
460 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
461 // FIXME: Code duplication: SETCC has custom operation action, see
462 // ARMTargetLowering::addTypeForNEON method for details.
463 setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
464 // FIXME: Create unittest for FNEG and for FABS.
465 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
466 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
467 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
468 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
469 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
470 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
471 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
472 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
473 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
474 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
475 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
476 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
477 // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR.
478 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
479 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
480 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
481 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
482 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
483 setOperationAction(ISD::FMA, MVT::v2f64, Expand);
485 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
486 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
487 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
488 setOperationAction(ISD::FPOWI, MVT::v4f32, Expand);
489 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
490 setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
491 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
492 setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
493 setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
494 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
495 setOperationAction(ISD::FCEIL, MVT::v4f32, Expand);
496 setOperationAction(ISD::FTRUNC, MVT::v4f32, Expand);
497 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
498 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
499 setOperationAction(ISD::FFLOOR, MVT::v4f32, Expand);
501 // Mark v2f32 intrinsics.
502 setOperationAction(ISD::FSQRT, MVT::v2f32, Expand);
503 setOperationAction(ISD::FSIN, MVT::v2f32, Expand);
504 setOperationAction(ISD::FCOS, MVT::v2f32, Expand);
505 setOperationAction(ISD::FPOWI, MVT::v2f32, Expand);
506 setOperationAction(ISD::FPOW, MVT::v2f32, Expand);
507 setOperationAction(ISD::FLOG, MVT::v2f32, Expand);
508 setOperationAction(ISD::FLOG2, MVT::v2f32, Expand);
509 setOperationAction(ISD::FLOG10, MVT::v2f32, Expand);
510 setOperationAction(ISD::FEXP, MVT::v2f32, Expand);
511 setOperationAction(ISD::FEXP2, MVT::v2f32, Expand);
512 setOperationAction(ISD::FCEIL, MVT::v2f32, Expand);
513 setOperationAction(ISD::FTRUNC, MVT::v2f32, Expand);
514 setOperationAction(ISD::FRINT, MVT::v2f32, Expand);
515 setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Expand);
516 setOperationAction(ISD::FFLOOR, MVT::v2f32, Expand);
518 // Neon does not support some operations on v1i64 and v2i64 types.
519 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
520 // Custom handling for some quad-vector types to detect VMULL.
521 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
522 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
523 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
524 // Custom handling for some vector types to avoid expensive expansions
525 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
526 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
527 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
528 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
529 setOperationAction(ISD::SETCC, MVT::v1i64, Expand);
530 setOperationAction(ISD::SETCC, MVT::v2i64, Expand);
531 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
532 // a destination type that is wider than the source, and nor does
533 // it have a FP_TO_[SU]INT instruction with a narrower destination than
535 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
536 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
537 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
538 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
540 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
541 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand);
543 // NEON does not have single instruction CTPOP for vectors with element
544 // types wider than 8-bits. However, custom lowering can leverage the
545 // v8i8/v16i8 vcnt instruction.
546 setOperationAction(ISD::CTPOP, MVT::v2i32, Custom);
547 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
548 setOperationAction(ISD::CTPOP, MVT::v4i16, Custom);
549 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
551 // NEON only has FMA instructions as of VFP4.
552 if (!Subtarget->hasVFP4()) {
553 setOperationAction(ISD::FMA, MVT::v2f32, Expand);
554 setOperationAction(ISD::FMA, MVT::v4f32, Expand);
557 setTargetDAGCombine(ISD::INTRINSIC_VOID);
558 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
559 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
560 setTargetDAGCombine(ISD::SHL);
561 setTargetDAGCombine(ISD::SRL);
562 setTargetDAGCombine(ISD::SRA);
563 setTargetDAGCombine(ISD::SIGN_EXTEND);
564 setTargetDAGCombine(ISD::ZERO_EXTEND);
565 setTargetDAGCombine(ISD::ANY_EXTEND);
566 setTargetDAGCombine(ISD::SELECT_CC);
567 setTargetDAGCombine(ISD::BUILD_VECTOR);
568 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
569 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
570 setTargetDAGCombine(ISD::STORE);
571 setTargetDAGCombine(ISD::FP_TO_SINT);
572 setTargetDAGCombine(ISD::FP_TO_UINT);
573 setTargetDAGCombine(ISD::FDIV);
574 setTargetDAGCombine(ISD::LOAD);
576 // It is legal to extload from v4i8 to v4i16 or v4i32.
577 for (MVT Ty : {MVT::v8i8, MVT::v4i8, MVT::v2i8, MVT::v4i16, MVT::v2i16,
579 for (MVT VT : MVT::integer_vector_valuetypes()) {
580 setLoadExtAction(ISD::EXTLOAD, VT, Ty, Legal);
581 setLoadExtAction(ISD::ZEXTLOAD, VT, Ty, Legal);
582 setLoadExtAction(ISD::SEXTLOAD, VT, Ty, Legal);
587 // ARM and Thumb2 support UMLAL/SMLAL.
588 if (!Subtarget->isThumb1Only())
589 setTargetDAGCombine(ISD::ADDC);
591 if (Subtarget->isFPOnlySP()) {
592 // When targetting a floating-point unit with only single-precision
593 // operations, f64 is legal for the few double-precision instructions which
594 // are present However, no double-precision operations other than moves,
595 // loads and stores are provided by the hardware.
596 setOperationAction(ISD::FADD, MVT::f64, Expand);
597 setOperationAction(ISD::FSUB, MVT::f64, Expand);
598 setOperationAction(ISD::FMUL, MVT::f64, Expand);
599 setOperationAction(ISD::FMA, MVT::f64, Expand);
600 setOperationAction(ISD::FDIV, MVT::f64, Expand);
601 setOperationAction(ISD::FREM, MVT::f64, Expand);
602 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
603 setOperationAction(ISD::FGETSIGN, MVT::f64, Expand);
604 setOperationAction(ISD::FNEG, MVT::f64, Expand);
605 setOperationAction(ISD::FABS, MVT::f64, Expand);
606 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
607 setOperationAction(ISD::FSIN, MVT::f64, Expand);
608 setOperationAction(ISD::FCOS, MVT::f64, Expand);
609 setOperationAction(ISD::FPOWI, MVT::f64, Expand);
610 setOperationAction(ISD::FPOW, MVT::f64, Expand);
611 setOperationAction(ISD::FLOG, MVT::f64, Expand);
612 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
613 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
614 setOperationAction(ISD::FEXP, MVT::f64, Expand);
615 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
616 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
617 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
618 setOperationAction(ISD::FRINT, MVT::f64, Expand);
619 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
620 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
621 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
622 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
623 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
624 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
625 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Custom);
626 setOperationAction(ISD::FP_TO_UINT, MVT::f64, Custom);
627 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
628 setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom);
631 computeRegisterProperties(Subtarget->getRegisterInfo());
633 // ARM does not have floating-point extending loads.
634 for (MVT VT : MVT::fp_valuetypes()) {
635 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
636 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
639 // ... or truncating stores
640 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
641 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
642 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
644 // ARM does not have i1 sign extending load.
645 for (MVT VT : MVT::integer_valuetypes())
646 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
648 // ARM supports all 4 flavors of integer indexed load / store.
649 if (!Subtarget->isThumb1Only()) {
650 for (unsigned im = (unsigned)ISD::PRE_INC;
651 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
652 setIndexedLoadAction(im, MVT::i1, Legal);
653 setIndexedLoadAction(im, MVT::i8, Legal);
654 setIndexedLoadAction(im, MVT::i16, Legal);
655 setIndexedLoadAction(im, MVT::i32, Legal);
656 setIndexedStoreAction(im, MVT::i1, Legal);
657 setIndexedStoreAction(im, MVT::i8, Legal);
658 setIndexedStoreAction(im, MVT::i16, Legal);
659 setIndexedStoreAction(im, MVT::i32, Legal);
663 setOperationAction(ISD::SADDO, MVT::i32, Custom);
664 setOperationAction(ISD::UADDO, MVT::i32, Custom);
665 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
666 setOperationAction(ISD::USUBO, MVT::i32, Custom);
668 // i64 operation support.
669 setOperationAction(ISD::MUL, MVT::i64, Expand);
670 setOperationAction(ISD::MULHU, MVT::i32, Expand);
671 if (Subtarget->isThumb1Only()) {
672 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
673 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
675 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
676 || (Subtarget->isThumb2() && !Subtarget->hasThumb2DSP()))
677 setOperationAction(ISD::MULHS, MVT::i32, Expand);
679 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
680 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
681 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
682 setOperationAction(ISD::SRL, MVT::i64, Custom);
683 setOperationAction(ISD::SRA, MVT::i64, Custom);
685 if (!Subtarget->isThumb1Only()) {
686 // FIXME: We should do this for Thumb1 as well.
687 setOperationAction(ISD::ADDC, MVT::i32, Custom);
688 setOperationAction(ISD::ADDE, MVT::i32, Custom);
689 setOperationAction(ISD::SUBC, MVT::i32, Custom);
690 setOperationAction(ISD::SUBE, MVT::i32, Custom);
693 // ARM does not have ROTL.
694 setOperationAction(ISD::ROTL, MVT::i32, Expand);
695 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
696 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
697 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
698 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
700 // These just redirect to CTTZ and CTLZ on ARM.
701 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i32 , Expand);
702 setOperationAction(ISD::CTLZ_ZERO_UNDEF , MVT::i32 , Expand);
704 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
706 // Only ARMv6 has BSWAP.
707 if (!Subtarget->hasV6Ops())
708 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
710 if (!(Subtarget->hasDivide() && Subtarget->isThumb2()) &&
711 !(Subtarget->hasDivideInARMMode() && !Subtarget->isThumb())) {
712 // These are expanded into libcalls if the cpu doesn't have HW divider.
713 setOperationAction(ISD::SDIV, MVT::i32, Expand);
714 setOperationAction(ISD::UDIV, MVT::i32, Expand);
717 // FIXME: Also set divmod for SREM on EABI
718 setOperationAction(ISD::SREM, MVT::i32, Expand);
719 setOperationAction(ISD::UREM, MVT::i32, Expand);
720 // Register based DivRem for AEABI (RTABI 4.2)
721 if (Subtarget->isTargetAEABI()) {
722 setLibcallName(RTLIB::SDIVREM_I8, "__aeabi_idivmod");
723 setLibcallName(RTLIB::SDIVREM_I16, "__aeabi_idivmod");
724 setLibcallName(RTLIB::SDIVREM_I32, "__aeabi_idivmod");
725 setLibcallName(RTLIB::SDIVREM_I64, "__aeabi_ldivmod");
726 setLibcallName(RTLIB::UDIVREM_I8, "__aeabi_uidivmod");
727 setLibcallName(RTLIB::UDIVREM_I16, "__aeabi_uidivmod");
728 setLibcallName(RTLIB::UDIVREM_I32, "__aeabi_uidivmod");
729 setLibcallName(RTLIB::UDIVREM_I64, "__aeabi_uldivmod");
731 setLibcallCallingConv(RTLIB::SDIVREM_I8, CallingConv::ARM_AAPCS);
732 setLibcallCallingConv(RTLIB::SDIVREM_I16, CallingConv::ARM_AAPCS);
733 setLibcallCallingConv(RTLIB::SDIVREM_I32, CallingConv::ARM_AAPCS);
734 setLibcallCallingConv(RTLIB::SDIVREM_I64, CallingConv::ARM_AAPCS);
735 setLibcallCallingConv(RTLIB::UDIVREM_I8, CallingConv::ARM_AAPCS);
736 setLibcallCallingConv(RTLIB::UDIVREM_I16, CallingConv::ARM_AAPCS);
737 setLibcallCallingConv(RTLIB::UDIVREM_I32, CallingConv::ARM_AAPCS);
738 setLibcallCallingConv(RTLIB::UDIVREM_I64, CallingConv::ARM_AAPCS);
740 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
741 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
743 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
744 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
747 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
748 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
749 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
750 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
751 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
753 setOperationAction(ISD::TRAP, MVT::Other, Legal);
755 // Use the default implementation.
756 setOperationAction(ISD::VASTART, MVT::Other, Custom);
757 setOperationAction(ISD::VAARG, MVT::Other, Expand);
758 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
759 setOperationAction(ISD::VAEND, MVT::Other, Expand);
760 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
761 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
763 if (!Subtarget->isTargetMachO()) {
764 // Non-MachO platforms may return values in these registers via the
765 // personality function.
766 setExceptionPointerRegister(ARM::R0);
767 setExceptionSelectorRegister(ARM::R1);
770 if (Subtarget->getTargetTriple().isWindowsItaniumEnvironment())
771 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
773 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
775 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
776 // the default expansion. If we are targeting a single threaded system,
777 // then set them all for expand so we can lower them later into their
779 if (TM.Options.ThreadModel == ThreadModel::Single)
780 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
781 else if (Subtarget->hasAnyDataBarrier() && !Subtarget->isThumb1Only()) {
782 // ATOMIC_FENCE needs custom lowering; the others should have been expanded
783 // to ldrex/strex loops already.
784 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
786 // On v8, we have particularly efficient implementations of atomic fences
787 // if they can be combined with nearby atomic loads and stores.
788 if (!Subtarget->hasV8Ops()) {
789 // Automatically insert fences (dmb ish) around ATOMIC_SWAP etc.
790 setInsertFencesForAtomic(true);
793 // If there's anything we can use as a barrier, go through custom lowering
795 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other,
796 Subtarget->hasAnyDataBarrier() ? Custom : Expand);
798 // Set them all for expansion, which will force libcalls.
799 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
800 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
801 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
802 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
803 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
804 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
805 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
806 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
807 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
808 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
809 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
810 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
811 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the
812 // Unordered/Monotonic case.
813 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
814 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
817 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
819 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
820 if (!Subtarget->hasV6Ops()) {
821 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
822 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
824 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
826 if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2() &&
827 !Subtarget->isThumb1Only()) {
828 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
829 // iff target supports vfp2.
830 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
831 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
834 // We want to custom lower some of our intrinsics.
835 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
836 if (Subtarget->isTargetDarwin()) {
837 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
838 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
839 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
842 setOperationAction(ISD::SETCC, MVT::i32, Expand);
843 setOperationAction(ISD::SETCC, MVT::f32, Expand);
844 setOperationAction(ISD::SETCC, MVT::f64, Expand);
845 setOperationAction(ISD::SELECT, MVT::i32, Custom);
846 setOperationAction(ISD::SELECT, MVT::f32, Custom);
847 setOperationAction(ISD::SELECT, MVT::f64, Custom);
848 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
849 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
850 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
852 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
853 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
854 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
855 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
856 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
858 // We don't support sin/cos/fmod/copysign/pow
859 setOperationAction(ISD::FSIN, MVT::f64, Expand);
860 setOperationAction(ISD::FSIN, MVT::f32, Expand);
861 setOperationAction(ISD::FCOS, MVT::f32, Expand);
862 setOperationAction(ISD::FCOS, MVT::f64, Expand);
863 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
864 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
865 setOperationAction(ISD::FREM, MVT::f64, Expand);
866 setOperationAction(ISD::FREM, MVT::f32, Expand);
867 if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2() &&
868 !Subtarget->isThumb1Only()) {
869 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
870 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
872 setOperationAction(ISD::FPOW, MVT::f64, Expand);
873 setOperationAction(ISD::FPOW, MVT::f32, Expand);
875 if (!Subtarget->hasVFP4()) {
876 setOperationAction(ISD::FMA, MVT::f64, Expand);
877 setOperationAction(ISD::FMA, MVT::f32, Expand);
880 // Various VFP goodness
881 if (!Subtarget->useSoftFloat() && !Subtarget->isThumb1Only()) {
882 // FP-ARMv8 adds f64 <-> f16 conversion. Before that it should be expanded.
883 if (!Subtarget->hasFPARMv8() || Subtarget->isFPOnlySP()) {
884 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
885 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
888 // fp16 is a special v7 extension that adds f16 <-> f32 conversions.
889 if (!Subtarget->hasFP16()) {
890 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
891 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
895 // Combine sin / cos into one node or libcall if possible.
896 if (Subtarget->hasSinCos()) {
897 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
898 setLibcallName(RTLIB::SINCOS_F64, "sincos");
899 if (Subtarget->getTargetTriple().isiOS()) {
900 // For iOS, we don't want to the normal expansion of a libcall to
901 // sincos. We want to issue a libcall to __sincos_stret.
902 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
903 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
907 // FP-ARMv8 implements a lot of rounding-like FP operations.
908 if (Subtarget->hasFPARMv8()) {
909 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
910 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
911 setOperationAction(ISD::FROUND, MVT::f32, Legal);
912 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
913 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
914 setOperationAction(ISD::FRINT, MVT::f32, Legal);
915 if (!Subtarget->isFPOnlySP()) {
916 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
917 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
918 setOperationAction(ISD::FROUND, MVT::f64, Legal);
919 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
920 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
921 setOperationAction(ISD::FRINT, MVT::f64, Legal);
924 // We have target-specific dag combine patterns for the following nodes:
925 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
926 setTargetDAGCombine(ISD::ADD);
927 setTargetDAGCombine(ISD::SUB);
928 setTargetDAGCombine(ISD::MUL);
929 setTargetDAGCombine(ISD::AND);
930 setTargetDAGCombine(ISD::OR);
931 setTargetDAGCombine(ISD::XOR);
933 if (Subtarget->hasV6Ops())
934 setTargetDAGCombine(ISD::SRL);
936 setStackPointerRegisterToSaveRestore(ARM::SP);
938 if (Subtarget->useSoftFloat() || Subtarget->isThumb1Only() ||
939 !Subtarget->hasVFP2())
940 setSchedulingPreference(Sched::RegPressure);
942 setSchedulingPreference(Sched::Hybrid);
944 //// temporary - rewrite interface to use type
945 MaxStoresPerMemset = 8;
946 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
947 MaxStoresPerMemcpy = 4; // For @llvm.memcpy -> sequence of stores
948 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 4 : 2;
949 MaxStoresPerMemmove = 4; // For @llvm.memmove -> sequence of stores
950 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 4 : 2;
952 // On ARM arguments smaller than 4 bytes are extended, so all arguments
953 // are at least 4 bytes aligned.
954 setMinStackArgumentAlignment(4);
956 // Prefer likely predicted branches to selects on out-of-order cores.
957 PredictableSelectIsExpensive = Subtarget->isLikeA9();
959 setMinFunctionAlignment(Subtarget->isThumb() ? 1 : 2);
962 bool ARMTargetLowering::useSoftFloat() const {
963 return Subtarget->useSoftFloat();
966 // FIXME: It might make sense to define the representative register class as the
967 // nearest super-register that has a non-null superset. For example, DPR_VFP2 is
968 // a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
969 // SPR's representative would be DPR_VFP2. This should work well if register
970 // pressure tracking were modified such that a register use would increment the
971 // pressure of the register class's representative and all of it's super
972 // classes' representatives transitively. We have not implemented this because
973 // of the difficulty prior to coalescing of modeling operand register classes
974 // due to the common occurrence of cross class copies and subregister insertions
976 std::pair<const TargetRegisterClass *, uint8_t>
977 ARMTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
979 const TargetRegisterClass *RRC = nullptr;
981 switch (VT.SimpleTy) {
983 return TargetLowering::findRepresentativeClass(TRI, VT);
984 // Use DPR as representative register class for all floating point
985 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
986 // the cost is 1 for both f32 and f64.
987 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
988 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
989 RRC = &ARM::DPRRegClass;
990 // When NEON is used for SP, only half of the register file is available
991 // because operations that define both SP and DP results will be constrained
992 // to the VFP2 class (D0-D15). We currently model this constraint prior to
993 // coalescing by double-counting the SP regs. See the FIXME above.
994 if (Subtarget->useNEONForSinglePrecisionFP())
997 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
998 case MVT::v4f32: case MVT::v2f64:
999 RRC = &ARM::DPRRegClass;
1003 RRC = &ARM::DPRRegClass;
1007 RRC = &ARM::DPRRegClass;
1011 return std::make_pair(RRC, Cost);
1014 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
1015 switch ((ARMISD::NodeType)Opcode) {
1016 case ARMISD::FIRST_NUMBER: break;
1017 case ARMISD::Wrapper: return "ARMISD::Wrapper";
1018 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
1019 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
1020 case ARMISD::COPY_STRUCT_BYVAL: return "ARMISD::COPY_STRUCT_BYVAL";
1021 case ARMISD::CALL: return "ARMISD::CALL";
1022 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
1023 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
1024 case ARMISD::tCALL: return "ARMISD::tCALL";
1025 case ARMISD::BRCOND: return "ARMISD::BRCOND";
1026 case ARMISD::BR_JT: return "ARMISD::BR_JT";
1027 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
1028 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
1029 case ARMISD::INTRET_FLAG: return "ARMISD::INTRET_FLAG";
1030 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
1031 case ARMISD::CMP: return "ARMISD::CMP";
1032 case ARMISD::CMN: return "ARMISD::CMN";
1033 case ARMISD::CMPZ: return "ARMISD::CMPZ";
1034 case ARMISD::CMPFP: return "ARMISD::CMPFP";
1035 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
1036 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
1037 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
1039 case ARMISD::CMOV: return "ARMISD::CMOV";
1041 case ARMISD::RBIT: return "ARMISD::RBIT";
1043 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
1044 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
1045 case ARMISD::RRX: return "ARMISD::RRX";
1047 case ARMISD::ADDC: return "ARMISD::ADDC";
1048 case ARMISD::ADDE: return "ARMISD::ADDE";
1049 case ARMISD::SUBC: return "ARMISD::SUBC";
1050 case ARMISD::SUBE: return "ARMISD::SUBE";
1052 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
1053 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
1055 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
1056 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
1058 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
1060 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
1062 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
1064 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
1066 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
1068 case ARMISD::WIN__CHKSTK: return "ARMISD:::WIN__CHKSTK";
1070 case ARMISD::VCEQ: return "ARMISD::VCEQ";
1071 case ARMISD::VCEQZ: return "ARMISD::VCEQZ";
1072 case ARMISD::VCGE: return "ARMISD::VCGE";
1073 case ARMISD::VCGEZ: return "ARMISD::VCGEZ";
1074 case ARMISD::VCLEZ: return "ARMISD::VCLEZ";
1075 case ARMISD::VCGEU: return "ARMISD::VCGEU";
1076 case ARMISD::VCGT: return "ARMISD::VCGT";
1077 case ARMISD::VCGTZ: return "ARMISD::VCGTZ";
1078 case ARMISD::VCLTZ: return "ARMISD::VCLTZ";
1079 case ARMISD::VCGTU: return "ARMISD::VCGTU";
1080 case ARMISD::VTST: return "ARMISD::VTST";
1082 case ARMISD::VSHL: return "ARMISD::VSHL";
1083 case ARMISD::VSHRs: return "ARMISD::VSHRs";
1084 case ARMISD::VSHRu: return "ARMISD::VSHRu";
1085 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
1086 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
1087 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
1088 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
1089 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
1090 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
1091 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
1092 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
1093 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
1094 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
1095 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
1096 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
1097 case ARMISD::VSLI: return "ARMISD::VSLI";
1098 case ARMISD::VSRI: return "ARMISD::VSRI";
1099 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
1100 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
1101 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
1102 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
1103 case ARMISD::VMOVFPIMM: return "ARMISD::VMOVFPIMM";
1104 case ARMISD::VDUP: return "ARMISD::VDUP";
1105 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
1106 case ARMISD::VEXT: return "ARMISD::VEXT";
1107 case ARMISD::VREV64: return "ARMISD::VREV64";
1108 case ARMISD::VREV32: return "ARMISD::VREV32";
1109 case ARMISD::VREV16: return "ARMISD::VREV16";
1110 case ARMISD::VZIP: return "ARMISD::VZIP";
1111 case ARMISD::VUZP: return "ARMISD::VUZP";
1112 case ARMISD::VTRN: return "ARMISD::VTRN";
1113 case ARMISD::VTBL1: return "ARMISD::VTBL1";
1114 case ARMISD::VTBL2: return "ARMISD::VTBL2";
1115 case ARMISD::VMULLs: return "ARMISD::VMULLs";
1116 case ARMISD::VMULLu: return "ARMISD::VMULLu";
1117 case ARMISD::UMLAL: return "ARMISD::UMLAL";
1118 case ARMISD::SMLAL: return "ARMISD::SMLAL";
1119 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
1120 case ARMISD::FMAX: return "ARMISD::FMAX";
1121 case ARMISD::FMIN: return "ARMISD::FMIN";
1122 case ARMISD::VMAXNM: return "ARMISD::VMAX";
1123 case ARMISD::VMINNM: return "ARMISD::VMIN";
1124 case ARMISD::BFI: return "ARMISD::BFI";
1125 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
1126 case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
1127 case ARMISD::VBSL: return "ARMISD::VBSL";
1128 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
1129 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
1130 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
1131 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD";
1132 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD";
1133 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD";
1134 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD";
1135 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD";
1136 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD";
1137 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD";
1138 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD";
1139 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD";
1140 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD";
1141 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD";
1142 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD";
1143 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD";
1144 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD";
1145 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD";
1146 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD";
1147 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD";
1152 EVT ARMTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1153 if (!VT.isVector()) return getPointerTy();
1154 return VT.changeVectorElementTypeToInteger();
1157 /// getRegClassFor - Return the register class that should be used for the
1158 /// specified value type.
1159 const TargetRegisterClass *ARMTargetLowering::getRegClassFor(MVT VT) const {
1160 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
1161 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
1162 // load / store 4 to 8 consecutive D registers.
1163 if (Subtarget->hasNEON()) {
1164 if (VT == MVT::v4i64)
1165 return &ARM::QQPRRegClass;
1166 if (VT == MVT::v8i64)
1167 return &ARM::QQQQPRRegClass;
1169 return TargetLowering::getRegClassFor(VT);
1172 // memcpy, and other memory intrinsics, typically tries to use LDM/STM if the
1173 // source/dest is aligned and the copy size is large enough. We therefore want
1174 // to align such objects passed to memory intrinsics.
1175 bool ARMTargetLowering::shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
1176 unsigned &PrefAlign) const {
1177 if (!isa<MemIntrinsic>(CI))
1180 // On ARM11 onwards (excluding M class) 8-byte aligned LDM is typically 1
1181 // cycle faster than 4-byte aligned LDM.
1182 PrefAlign = (Subtarget->hasV6Ops() && !Subtarget->isMClass() ? 8 : 4);
1186 // Create a fast isel object.
1188 ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
1189 const TargetLibraryInfo *libInfo) const {
1190 return ARM::createFastISel(funcInfo, libInfo);
1193 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
1194 unsigned NumVals = N->getNumValues();
1196 return Sched::RegPressure;
1198 for (unsigned i = 0; i != NumVals; ++i) {
1199 EVT VT = N->getValueType(i);
1200 if (VT == MVT::Glue || VT == MVT::Other)
1202 if (VT.isFloatingPoint() || VT.isVector())
1206 if (!N->isMachineOpcode())
1207 return Sched::RegPressure;
1209 // Load are scheduled for latency even if there instruction itinerary
1210 // is not available.
1211 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
1212 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1214 if (MCID.getNumDefs() == 0)
1215 return Sched::RegPressure;
1216 if (!Itins->isEmpty() &&
1217 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
1220 return Sched::RegPressure;
1223 //===----------------------------------------------------------------------===//
1225 //===----------------------------------------------------------------------===//
1227 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
1228 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
1230 default: llvm_unreachable("Unknown condition code!");
1231 case ISD::SETNE: return ARMCC::NE;
1232 case ISD::SETEQ: return ARMCC::EQ;
1233 case ISD::SETGT: return ARMCC::GT;
1234 case ISD::SETGE: return ARMCC::GE;
1235 case ISD::SETLT: return ARMCC::LT;
1236 case ISD::SETLE: return ARMCC::LE;
1237 case ISD::SETUGT: return ARMCC::HI;
1238 case ISD::SETUGE: return ARMCC::HS;
1239 case ISD::SETULT: return ARMCC::LO;
1240 case ISD::SETULE: return ARMCC::LS;
1244 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
1245 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
1246 ARMCC::CondCodes &CondCode2) {
1247 CondCode2 = ARMCC::AL;
1249 default: llvm_unreachable("Unknown FP condition!");
1251 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
1253 case ISD::SETOGT: CondCode = ARMCC::GT; break;
1255 case ISD::SETOGE: CondCode = ARMCC::GE; break;
1256 case ISD::SETOLT: CondCode = ARMCC::MI; break;
1257 case ISD::SETOLE: CondCode = ARMCC::LS; break;
1258 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
1259 case ISD::SETO: CondCode = ARMCC::VC; break;
1260 case ISD::SETUO: CondCode = ARMCC::VS; break;
1261 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
1262 case ISD::SETUGT: CondCode = ARMCC::HI; break;
1263 case ISD::SETUGE: CondCode = ARMCC::PL; break;
1265 case ISD::SETULT: CondCode = ARMCC::LT; break;
1267 case ISD::SETULE: CondCode = ARMCC::LE; break;
1269 case ISD::SETUNE: CondCode = ARMCC::NE; break;
1273 //===----------------------------------------------------------------------===//
1274 // Calling Convention Implementation
1275 //===----------------------------------------------------------------------===//
1277 #include "ARMGenCallingConv.inc"
1279 /// getEffectiveCallingConv - Get the effective calling convention, taking into
1280 /// account presence of floating point hardware and calling convention
1281 /// limitations, such as support for variadic functions.
1283 ARMTargetLowering::getEffectiveCallingConv(CallingConv::ID CC,
1284 bool isVarArg) const {
1287 llvm_unreachable("Unsupported calling convention");
1288 case CallingConv::ARM_AAPCS:
1289 case CallingConv::ARM_APCS:
1290 case CallingConv::GHC:
1292 case CallingConv::ARM_AAPCS_VFP:
1293 return isVarArg ? CallingConv::ARM_AAPCS : CallingConv::ARM_AAPCS_VFP;
1294 case CallingConv::C:
1295 if (!Subtarget->isAAPCS_ABI())
1296 return CallingConv::ARM_APCS;
1297 else if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() &&
1298 getTargetMachine().Options.FloatABIType == FloatABI::Hard &&
1300 return CallingConv::ARM_AAPCS_VFP;
1302 return CallingConv::ARM_AAPCS;
1303 case CallingConv::Fast:
1304 if (!Subtarget->isAAPCS_ABI()) {
1305 if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() && !isVarArg)
1306 return CallingConv::Fast;
1307 return CallingConv::ARM_APCS;
1308 } else if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() && !isVarArg)
1309 return CallingConv::ARM_AAPCS_VFP;
1311 return CallingConv::ARM_AAPCS;
1315 /// CCAssignFnForNode - Selects the correct CCAssignFn for the given
1316 /// CallingConvention.
1317 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
1319 bool isVarArg) const {
1320 switch (getEffectiveCallingConv(CC, isVarArg)) {
1322 llvm_unreachable("Unsupported calling convention");
1323 case CallingConv::ARM_APCS:
1324 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1325 case CallingConv::ARM_AAPCS:
1326 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1327 case CallingConv::ARM_AAPCS_VFP:
1328 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1329 case CallingConv::Fast:
1330 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1331 case CallingConv::GHC:
1332 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC);
1336 /// LowerCallResult - Lower the result values of a call into the
1337 /// appropriate copies out of appropriate physical registers.
1339 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1340 CallingConv::ID CallConv, bool isVarArg,
1341 const SmallVectorImpl<ISD::InputArg> &Ins,
1342 SDLoc dl, SelectionDAG &DAG,
1343 SmallVectorImpl<SDValue> &InVals,
1344 bool isThisReturn, SDValue ThisVal) const {
1346 // Assign locations to each value returned by this call.
1347 SmallVector<CCValAssign, 16> RVLocs;
1348 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1349 *DAG.getContext(), Call);
1350 CCInfo.AnalyzeCallResult(Ins,
1351 CCAssignFnForNode(CallConv, /* Return*/ true,
1354 // Copy all of the result registers out of their specified physreg.
1355 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1356 CCValAssign VA = RVLocs[i];
1358 // Pass 'this' value directly from the argument to return value, to avoid
1359 // reg unit interference
1360 if (i == 0 && isThisReturn) {
1361 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&
1362 "unexpected return calling convention register assignment");
1363 InVals.push_back(ThisVal);
1368 if (VA.needsCustom()) {
1369 // Handle f64 or half of a v2f64.
1370 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1372 Chain = Lo.getValue(1);
1373 InFlag = Lo.getValue(2);
1374 VA = RVLocs[++i]; // skip ahead to next loc
1375 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1377 Chain = Hi.getValue(1);
1378 InFlag = Hi.getValue(2);
1379 if (!Subtarget->isLittle())
1381 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1383 if (VA.getLocVT() == MVT::v2f64) {
1384 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1385 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1386 DAG.getConstant(0, dl, MVT::i32));
1388 VA = RVLocs[++i]; // skip ahead to next loc
1389 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1390 Chain = Lo.getValue(1);
1391 InFlag = Lo.getValue(2);
1392 VA = RVLocs[++i]; // skip ahead to next loc
1393 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1394 Chain = Hi.getValue(1);
1395 InFlag = Hi.getValue(2);
1396 if (!Subtarget->isLittle())
1398 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1399 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1400 DAG.getConstant(1, dl, MVT::i32));
1403 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1405 Chain = Val.getValue(1);
1406 InFlag = Val.getValue(2);
1409 switch (VA.getLocInfo()) {
1410 default: llvm_unreachable("Unknown loc info!");
1411 case CCValAssign::Full: break;
1412 case CCValAssign::BCvt:
1413 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1417 InVals.push_back(Val);
1423 /// LowerMemOpCallTo - Store the argument to the stack.
1425 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
1426 SDValue StackPtr, SDValue Arg,
1427 SDLoc dl, SelectionDAG &DAG,
1428 const CCValAssign &VA,
1429 ISD::ArgFlagsTy Flags) const {
1430 unsigned LocMemOffset = VA.getLocMemOffset();
1431 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
1432 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1433 return DAG.getStore(Chain, dl, Arg, PtrOff,
1434 MachinePointerInfo::getStack(LocMemOffset),
1438 void ARMTargetLowering::PassF64ArgInRegs(SDLoc dl, SelectionDAG &DAG,
1439 SDValue Chain, SDValue &Arg,
1440 RegsToPassVector &RegsToPass,
1441 CCValAssign &VA, CCValAssign &NextVA,
1443 SmallVectorImpl<SDValue> &MemOpChains,
1444 ISD::ArgFlagsTy Flags) const {
1446 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1447 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1448 unsigned id = Subtarget->isLittle() ? 0 : 1;
1449 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(id)));
1451 if (NextVA.isRegLoc())
1452 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1-id)));
1454 assert(NextVA.isMemLoc());
1455 if (!StackPtr.getNode())
1456 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1458 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1-id),
1464 /// LowerCall - Lowering a call into a callseq_start <-
1465 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1468 ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1469 SmallVectorImpl<SDValue> &InVals) const {
1470 SelectionDAG &DAG = CLI.DAG;
1472 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1473 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1474 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1475 SDValue Chain = CLI.Chain;
1476 SDValue Callee = CLI.Callee;
1477 bool &isTailCall = CLI.IsTailCall;
1478 CallingConv::ID CallConv = CLI.CallConv;
1479 bool doesNotRet = CLI.DoesNotReturn;
1480 bool isVarArg = CLI.IsVarArg;
1482 MachineFunction &MF = DAG.getMachineFunction();
1483 bool isStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1484 bool isThisReturn = false;
1485 bool isSibCall = false;
1486 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
1488 // Disable tail calls if they're not supported.
1489 if (!Subtarget->supportsTailCall() || Attr.getValueAsString() == "true")
1493 // Check if it's really possible to do a tail call.
1494 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1495 isVarArg, isStructRet, MF.getFunction()->hasStructRetAttr(),
1496 Outs, OutVals, Ins, DAG);
1497 if (!isTailCall && CLI.CS && CLI.CS->isMustTailCall())
1498 report_fatal_error("failed to perform tail call elimination on a call "
1499 "site marked musttail");
1500 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1501 // detected sibcalls.
1508 // Analyze operands of the call, assigning locations to each operand.
1509 SmallVector<CCValAssign, 16> ArgLocs;
1510 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1511 *DAG.getContext(), Call);
1512 CCInfo.AnalyzeCallOperands(Outs,
1513 CCAssignFnForNode(CallConv, /* Return*/ false,
1516 // Get a count of how many bytes are to be pushed on the stack.
1517 unsigned NumBytes = CCInfo.getNextStackOffset();
1519 // For tail calls, memory operands are available in our caller's stack.
1523 // Adjust the stack pointer for the new arguments...
1524 // These operations are automatically eliminated by the prolog/epilog pass
1526 Chain = DAG.getCALLSEQ_START(Chain,
1527 DAG.getIntPtrConstant(NumBytes, dl, true), dl);
1529 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1531 RegsToPassVector RegsToPass;
1532 SmallVector<SDValue, 8> MemOpChains;
1534 // Walk the register/memloc assignments, inserting copies/loads. In the case
1535 // of tail call optimization, arguments are handled later.
1536 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1538 ++i, ++realArgIdx) {
1539 CCValAssign &VA = ArgLocs[i];
1540 SDValue Arg = OutVals[realArgIdx];
1541 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1542 bool isByVal = Flags.isByVal();
1544 // Promote the value if needed.
1545 switch (VA.getLocInfo()) {
1546 default: llvm_unreachable("Unknown loc info!");
1547 case CCValAssign::Full: break;
1548 case CCValAssign::SExt:
1549 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1551 case CCValAssign::ZExt:
1552 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1554 case CCValAssign::AExt:
1555 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1557 case CCValAssign::BCvt:
1558 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1562 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1563 if (VA.needsCustom()) {
1564 if (VA.getLocVT() == MVT::v2f64) {
1565 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1566 DAG.getConstant(0, dl, MVT::i32));
1567 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1568 DAG.getConstant(1, dl, MVT::i32));
1570 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1571 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1573 VA = ArgLocs[++i]; // skip ahead to next loc
1574 if (VA.isRegLoc()) {
1575 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1576 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1578 assert(VA.isMemLoc());
1580 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1581 dl, DAG, VA, Flags));
1584 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1585 StackPtr, MemOpChains, Flags);
1587 } else if (VA.isRegLoc()) {
1588 if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i32) {
1589 assert(VA.getLocVT() == MVT::i32 &&
1590 "unexpected calling convention register assignment");
1591 assert(!Ins.empty() && Ins[0].VT == MVT::i32 &&
1592 "unexpected use of 'returned'");
1593 isThisReturn = true;
1595 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1596 } else if (isByVal) {
1597 assert(VA.isMemLoc());
1598 unsigned offset = 0;
1600 // True if this byval aggregate will be split between registers
1602 unsigned ByValArgsCount = CCInfo.getInRegsParamsCount();
1603 unsigned CurByValIdx = CCInfo.getInRegsParamsProcessed();
1605 if (CurByValIdx < ByValArgsCount) {
1607 unsigned RegBegin, RegEnd;
1608 CCInfo.getInRegsParamInfo(CurByValIdx, RegBegin, RegEnd);
1610 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1612 for (i = 0, j = RegBegin; j < RegEnd; i++, j++) {
1613 SDValue Const = DAG.getConstant(4*i, dl, MVT::i32);
1614 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
1615 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
1616 MachinePointerInfo(),
1617 false, false, false,
1618 DAG.InferPtrAlignment(AddArg));
1619 MemOpChains.push_back(Load.getValue(1));
1620 RegsToPass.push_back(std::make_pair(j, Load));
1623 // If parameter size outsides register area, "offset" value
1624 // helps us to calculate stack slot for remained part properly.
1625 offset = RegEnd - RegBegin;
1627 CCInfo.nextInRegsParam();
1630 if (Flags.getByValSize() > 4*offset) {
1631 unsigned LocMemOffset = VA.getLocMemOffset();
1632 SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
1633 SDValue Dst = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr,
1635 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset, dl);
1636 SDValue Src = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg, SrcOffset);
1637 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset, dl,
1639 SDValue AlignNode = DAG.getConstant(Flags.getByValAlign(), dl,
1642 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
1643 SDValue Ops[] = { Chain, Dst, Src, SizeNode, AlignNode};
1644 MemOpChains.push_back(DAG.getNode(ARMISD::COPY_STRUCT_BYVAL, dl, VTs,
1647 } else if (!isSibCall) {
1648 assert(VA.isMemLoc());
1650 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1651 dl, DAG, VA, Flags));
1655 if (!MemOpChains.empty())
1656 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
1658 // Build a sequence of copy-to-reg nodes chained together with token chain
1659 // and flag operands which copy the outgoing args into the appropriate regs.
1661 // Tail call byval lowering might overwrite argument registers so in case of
1662 // tail call optimization the copies to registers are lowered later.
1664 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1665 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1666 RegsToPass[i].second, InFlag);
1667 InFlag = Chain.getValue(1);
1670 // For tail calls lower the arguments to the 'real' stack slot.
1672 // Force all the incoming stack arguments to be loaded from the stack
1673 // before any new outgoing arguments are stored to the stack, because the
1674 // outgoing stack slots may alias the incoming argument stack slots, and
1675 // the alias isn't otherwise explicit. This is slightly more conservative
1676 // than necessary, because it means that each store effectively depends
1677 // on every argument instead of just those arguments it would clobber.
1679 // Do not flag preceding copytoreg stuff together with the following stuff.
1681 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1682 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1683 RegsToPass[i].second, InFlag);
1684 InFlag = Chain.getValue(1);
1689 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1690 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1691 // node so that legalize doesn't hack it.
1692 bool isDirect = false;
1693 bool isARMFunc = false;
1694 bool isLocalARMFunc = false;
1695 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1697 if (EnableARMLongCalls) {
1698 assert((Subtarget->isTargetWindows() ||
1699 getTargetMachine().getRelocationModel() == Reloc::Static) &&
1700 "long-calls with non-static relocation model!");
1701 // Handle a global address or an external symbol. If it's not one of
1702 // those, the target's already in a register, so we don't need to do
1704 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1705 const GlobalValue *GV = G->getGlobal();
1706 // Create a constant pool entry for the callee address
1707 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1708 ARMConstantPoolValue *CPV =
1709 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0);
1711 // Get the address of the callee into a register
1712 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1713 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1714 Callee = DAG.getLoad(getPointerTy(), dl,
1715 DAG.getEntryNode(), CPAddr,
1716 MachinePointerInfo::getConstantPool(),
1717 false, false, false, 0);
1718 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1719 const char *Sym = S->getSymbol();
1721 // Create a constant pool entry for the callee address
1722 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1723 ARMConstantPoolValue *CPV =
1724 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
1725 ARMPCLabelIndex, 0);
1726 // Get the address of the callee into a register
1727 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1728 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1729 Callee = DAG.getLoad(getPointerTy(), dl,
1730 DAG.getEntryNode(), CPAddr,
1731 MachinePointerInfo::getConstantPool(),
1732 false, false, false, 0);
1734 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1735 const GlobalValue *GV = G->getGlobal();
1737 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1738 bool isStub = (isExt && Subtarget->isTargetMachO()) &&
1739 getTargetMachine().getRelocationModel() != Reloc::Static;
1740 isARMFunc = !Subtarget->isThumb() || (isStub && !Subtarget->isMClass());
1741 // ARM call to a local ARM function is predicable.
1742 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
1743 // tBX takes a register source operand.
1744 if (isStub && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1745 assert(Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?");
1746 Callee = DAG.getNode(ARMISD::WrapperPIC, dl, getPointerTy(),
1747 DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
1748 0, ARMII::MO_NONLAZY));
1749 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
1750 MachinePointerInfo::getGOT(), false, false, true, 0);
1751 } else if (Subtarget->isTargetCOFF()) {
1752 assert(Subtarget->isTargetWindows() &&
1753 "Windows is the only supported COFF target");
1754 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), /*Offset=*/0,
1756 if (GV->hasDLLImportStorageClass())
1757 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
1758 DAG.getNode(ARMISD::Wrapper, dl, getPointerTy(),
1759 Callee), MachinePointerInfo::getGOT(),
1760 false, false, false, 0);
1762 // On ELF targets for PIC code, direct calls should go through the PLT
1763 unsigned OpFlags = 0;
1764 if (Subtarget->isTargetELF() &&
1765 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1766 OpFlags = ARMII::MO_PLT;
1767 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
1769 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1771 bool isStub = Subtarget->isTargetMachO() &&
1772 getTargetMachine().getRelocationModel() != Reloc::Static;
1773 isARMFunc = !Subtarget->isThumb() || (isStub && !Subtarget->isMClass());
1774 // tBX takes a register source operand.
1775 const char *Sym = S->getSymbol();
1776 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1777 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1778 ARMConstantPoolValue *CPV =
1779 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
1780 ARMPCLabelIndex, 4);
1781 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1782 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1783 Callee = DAG.getLoad(getPointerTy(), dl,
1784 DAG.getEntryNode(), CPAddr,
1785 MachinePointerInfo::getConstantPool(),
1786 false, false, false, 0);
1787 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
1788 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1789 getPointerTy(), Callee, PICLabel);
1791 unsigned OpFlags = 0;
1792 // On ELF targets for PIC code, direct calls should go through the PLT
1793 if (Subtarget->isTargetELF() &&
1794 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1795 OpFlags = ARMII::MO_PLT;
1796 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags);
1800 // FIXME: handle tail calls differently.
1802 bool HasMinSizeAttr = MF.getFunction()->hasFnAttribute(Attribute::MinSize);
1803 if (Subtarget->isThumb()) {
1804 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1805 CallOpc = ARMISD::CALL_NOLINK;
1807 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1809 if (!isDirect && !Subtarget->hasV5TOps())
1810 CallOpc = ARMISD::CALL_NOLINK;
1811 else if (doesNotRet && isDirect && Subtarget->hasRAS() &&
1812 // Emit regular call when code size is the priority
1814 // "mov lr, pc; b _foo" to avoid confusing the RSP
1815 CallOpc = ARMISD::CALL_NOLINK;
1817 CallOpc = isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL;
1820 std::vector<SDValue> Ops;
1821 Ops.push_back(Chain);
1822 Ops.push_back(Callee);
1824 // Add argument registers to the end of the list so that they are known live
1826 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1827 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1828 RegsToPass[i].second.getValueType()));
1830 // Add a register mask operand representing the call-preserved registers.
1832 const uint32_t *Mask;
1833 const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo();
1835 // For 'this' returns, use the R0-preserving mask if applicable
1836 Mask = ARI->getThisReturnPreservedMask(MF, CallConv);
1838 // Set isThisReturn to false if the calling convention is not one that
1839 // allows 'returned' to be modeled in this way, so LowerCallResult does
1840 // not try to pass 'this' straight through
1841 isThisReturn = false;
1842 Mask = ARI->getCallPreservedMask(MF, CallConv);
1845 Mask = ARI->getCallPreservedMask(MF, CallConv);
1847 assert(Mask && "Missing call preserved mask for calling convention");
1848 Ops.push_back(DAG.getRegisterMask(Mask));
1851 if (InFlag.getNode())
1852 Ops.push_back(InFlag);
1854 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1856 MF.getFrameInfo()->setHasTailCall();
1857 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, Ops);
1860 // Returns a chain and a flag for retval copy to use.
1861 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
1862 InFlag = Chain.getValue(1);
1864 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
1865 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
1867 InFlag = Chain.getValue(1);
1869 // Handle result values, copying them out of physregs into vregs that we
1871 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
1872 InVals, isThisReturn,
1873 isThisReturn ? OutVals[0] : SDValue());
1876 /// HandleByVal - Every parameter *after* a byval parameter is passed
1877 /// on the stack. Remember the next parameter register to allocate,
1878 /// and then confiscate the rest of the parameter registers to insure
1880 void ARMTargetLowering::HandleByVal(CCState *State, unsigned &Size,
1881 unsigned Align) const {
1882 assert((State->getCallOrPrologue() == Prologue ||
1883 State->getCallOrPrologue() == Call) &&
1884 "unhandled ParmContext");
1886 // Byval (as with any stack) slots are always at least 4 byte aligned.
1887 Align = std::max(Align, 4U);
1889 unsigned Reg = State->AllocateReg(GPRArgRegs);
1893 unsigned AlignInRegs = Align / 4;
1894 unsigned Waste = (ARM::R4 - Reg) % AlignInRegs;
1895 for (unsigned i = 0; i < Waste; ++i)
1896 Reg = State->AllocateReg(GPRArgRegs);
1901 unsigned Excess = 4 * (ARM::R4 - Reg);
1903 // Special case when NSAA != SP and parameter size greater than size of
1904 // all remained GPR regs. In that case we can't split parameter, we must
1905 // send it to stack. We also must set NCRN to R4, so waste all
1906 // remained registers.
1907 const unsigned NSAAOffset = State->getNextStackOffset();
1908 if (NSAAOffset != 0 && Size > Excess) {
1909 while (State->AllocateReg(GPRArgRegs))
1914 // First register for byval parameter is the first register that wasn't
1915 // allocated before this method call, so it would be "reg".
1916 // If parameter is small enough to be saved in range [reg, r4), then
1917 // the end (first after last) register would be reg + param-size-in-regs,
1918 // else parameter would be splitted between registers and stack,
1919 // end register would be r4 in this case.
1920 unsigned ByValRegBegin = Reg;
1921 unsigned ByValRegEnd = std::min<unsigned>(Reg + Size / 4, ARM::R4);
1922 State->addInRegsParamInfo(ByValRegBegin, ByValRegEnd);
1923 // Note, first register is allocated in the beginning of function already,
1924 // allocate remained amount of registers we need.
1925 for (unsigned i = Reg + 1; i != ByValRegEnd; ++i)
1926 State->AllocateReg(GPRArgRegs);
1927 // A byval parameter that is split between registers and memory needs its
1928 // size truncated here.
1929 // In the case where the entire structure fits in registers, we set the
1930 // size in memory to zero.
1931 Size = std::max<int>(Size - Excess, 0);
1934 /// MatchingStackOffset - Return true if the given stack call argument is
1935 /// already available in the same position (relatively) of the caller's
1936 /// incoming argument stack.
1938 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1939 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1940 const TargetInstrInfo *TII) {
1941 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
1943 if (Arg.getOpcode() == ISD::CopyFromReg) {
1944 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
1945 if (!TargetRegisterInfo::isVirtualRegister(VR))
1947 MachineInstr *Def = MRI->getVRegDef(VR);
1950 if (!Flags.isByVal()) {
1951 if (!TII->isLoadFromStackSlot(Def, FI))
1956 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
1957 if (Flags.isByVal())
1958 // ByVal argument is passed in as a pointer but it's now being
1959 // dereferenced. e.g.
1960 // define @foo(%struct.X* %A) {
1961 // tail call @bar(%struct.X* byval %A)
1964 SDValue Ptr = Ld->getBasePtr();
1965 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
1968 FI = FINode->getIndex();
1972 assert(FI != INT_MAX);
1973 if (!MFI->isFixedObjectIndex(FI))
1975 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
1978 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1979 /// for tail call optimization. Targets which want to do tail call
1980 /// optimization should implement this function.
1982 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1983 CallingConv::ID CalleeCC,
1985 bool isCalleeStructRet,
1986 bool isCallerStructRet,
1987 const SmallVectorImpl<ISD::OutputArg> &Outs,
1988 const SmallVectorImpl<SDValue> &OutVals,
1989 const SmallVectorImpl<ISD::InputArg> &Ins,
1990 SelectionDAG& DAG) const {
1991 const Function *CallerF = DAG.getMachineFunction().getFunction();
1992 CallingConv::ID CallerCC = CallerF->getCallingConv();
1993 bool CCMatch = CallerCC == CalleeCC;
1995 // Look for obvious safe cases to perform tail call optimization that do not
1996 // require ABI changes. This is what gcc calls sibcall.
1998 // Do not sibcall optimize vararg calls unless the call site is not passing
2000 if (isVarArg && !Outs.empty())
2003 // Exception-handling functions need a special set of instructions to indicate
2004 // a return to the hardware. Tail-calling another function would probably
2006 if (CallerF->hasFnAttribute("interrupt"))
2009 // Also avoid sibcall optimization if either caller or callee uses struct
2010 // return semantics.
2011 if (isCalleeStructRet || isCallerStructRet)
2014 // FIXME: Completely disable sibcall for Thumb1 since ThumbRegisterInfo::
2015 // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
2016 // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
2017 // support in the assembler and linker to be used. This would need to be
2018 // fixed to fully support tail calls in Thumb1.
2020 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
2021 // LR. This means if we need to reload LR, it takes an extra instructions,
2022 // which outweighs the value of the tail call; but here we don't know yet
2023 // whether LR is going to be used. Probably the right approach is to
2024 // generate the tail call here and turn it back into CALL/RET in
2025 // emitEpilogue if LR is used.
2027 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
2028 // but we need to make sure there are enough registers; the only valid
2029 // registers are the 4 used for parameters. We don't currently do this
2031 if (Subtarget->isThumb1Only())
2034 // Externally-defined functions with weak linkage should not be
2035 // tail-called on ARM when the OS does not support dynamic
2036 // pre-emption of symbols, as the AAELF spec requires normal calls
2037 // to undefined weak functions to be replaced with a NOP or jump to the
2038 // next instruction. The behaviour of branch instructions in this
2039 // situation (as used for tail calls) is implementation-defined, so we
2040 // cannot rely on the linker replacing the tail call with a return.
2041 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2042 const GlobalValue *GV = G->getGlobal();
2043 const Triple TT(getTargetMachine().getTargetTriple());
2044 if (GV->hasExternalWeakLinkage() &&
2045 (!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
2049 // If the calling conventions do not match, then we'd better make sure the
2050 // results are returned in the same way as what the caller expects.
2052 SmallVector<CCValAssign, 16> RVLocs1;
2053 ARMCCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
2054 *DAG.getContext(), Call);
2055 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
2057 SmallVector<CCValAssign, 16> RVLocs2;
2058 ARMCCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
2059 *DAG.getContext(), Call);
2060 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
2062 if (RVLocs1.size() != RVLocs2.size())
2064 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2065 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2067 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2069 if (RVLocs1[i].isRegLoc()) {
2070 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2073 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2079 // If Caller's vararg or byval argument has been split between registers and
2080 // stack, do not perform tail call, since part of the argument is in caller's
2082 const ARMFunctionInfo *AFI_Caller = DAG.getMachineFunction().
2083 getInfo<ARMFunctionInfo>();
2084 if (AFI_Caller->getArgRegsSaveSize())
2087 // If the callee takes no arguments then go on to check the results of the
2089 if (!Outs.empty()) {
2090 // Check if stack adjustment is needed. For now, do not do this if any
2091 // argument is passed on the stack.
2092 SmallVector<CCValAssign, 16> ArgLocs;
2093 ARMCCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2094 *DAG.getContext(), Call);
2095 CCInfo.AnalyzeCallOperands(Outs,
2096 CCAssignFnForNode(CalleeCC, false, isVarArg));
2097 if (CCInfo.getNextStackOffset()) {
2098 MachineFunction &MF = DAG.getMachineFunction();
2100 // Check if the arguments are already laid out in the right way as
2101 // the caller's fixed stack objects.
2102 MachineFrameInfo *MFI = MF.getFrameInfo();
2103 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2104 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
2105 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
2107 ++i, ++realArgIdx) {
2108 CCValAssign &VA = ArgLocs[i];
2109 EVT RegVT = VA.getLocVT();
2110 SDValue Arg = OutVals[realArgIdx];
2111 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2112 if (VA.getLocInfo() == CCValAssign::Indirect)
2114 if (VA.needsCustom()) {
2115 // f64 and vector types are split into multiple registers or
2116 // register/stack-slot combinations. The types will not match
2117 // the registers; give up on memory f64 refs until we figure
2118 // out what to do about this.
2121 if (!ArgLocs[++i].isRegLoc())
2123 if (RegVT == MVT::v2f64) {
2124 if (!ArgLocs[++i].isRegLoc())
2126 if (!ArgLocs[++i].isRegLoc())
2129 } else if (!VA.isRegLoc()) {
2130 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2142 ARMTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
2143 MachineFunction &MF, bool isVarArg,
2144 const SmallVectorImpl<ISD::OutputArg> &Outs,
2145 LLVMContext &Context) const {
2146 SmallVector<CCValAssign, 16> RVLocs;
2147 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2148 return CCInfo.CheckReturn(Outs, CCAssignFnForNode(CallConv, /*Return=*/true,
2152 static SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
2153 SDLoc DL, SelectionDAG &DAG) {
2154 const MachineFunction &MF = DAG.getMachineFunction();
2155 const Function *F = MF.getFunction();
2157 StringRef IntKind = F->getFnAttribute("interrupt").getValueAsString();
2159 // See ARM ARM v7 B1.8.3. On exception entry LR is set to a possibly offset
2160 // version of the "preferred return address". These offsets affect the return
2161 // instruction if this is a return from PL1 without hypervisor extensions.
2162 // IRQ/FIQ: +4 "subs pc, lr, #4"
2163 // SWI: 0 "subs pc, lr, #0"
2164 // ABORT: +4 "subs pc, lr, #4"
2165 // UNDEF: +4/+2 "subs pc, lr, #0"
2166 // UNDEF varies depending on where the exception came from ARM or Thumb
2167 // mode. Alongside GCC, we throw our hands up in disgust and pretend it's 0.
2170 if (IntKind == "" || IntKind == "IRQ" || IntKind == "FIQ" ||
2173 else if (IntKind == "SWI" || IntKind == "UNDEF")
2176 report_fatal_error("Unsupported interrupt attribute. If present, value "
2177 "must be one of: IRQ, FIQ, SWI, ABORT or UNDEF");
2179 RetOps.insert(RetOps.begin() + 1,
2180 DAG.getConstant(LROffset, DL, MVT::i32, false));
2182 return DAG.getNode(ARMISD::INTRET_FLAG, DL, MVT::Other, RetOps);
2186 ARMTargetLowering::LowerReturn(SDValue Chain,
2187 CallingConv::ID CallConv, bool isVarArg,
2188 const SmallVectorImpl<ISD::OutputArg> &Outs,
2189 const SmallVectorImpl<SDValue> &OutVals,
2190 SDLoc dl, SelectionDAG &DAG) const {
2192 // CCValAssign - represent the assignment of the return value to a location.
2193 SmallVector<CCValAssign, 16> RVLocs;
2195 // CCState - Info about the registers and stack slots.
2196 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2197 *DAG.getContext(), Call);
2199 // Analyze outgoing return values.
2200 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
2204 SmallVector<SDValue, 4> RetOps;
2205 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2206 bool isLittleEndian = Subtarget->isLittle();
2208 MachineFunction &MF = DAG.getMachineFunction();
2209 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2210 AFI->setReturnRegsCount(RVLocs.size());
2212 // Copy the result values into the output registers.
2213 for (unsigned i = 0, realRVLocIdx = 0;
2215 ++i, ++realRVLocIdx) {
2216 CCValAssign &VA = RVLocs[i];
2217 assert(VA.isRegLoc() && "Can only return in registers!");
2219 SDValue Arg = OutVals[realRVLocIdx];
2221 switch (VA.getLocInfo()) {
2222 default: llvm_unreachable("Unknown loc info!");
2223 case CCValAssign::Full: break;
2224 case CCValAssign::BCvt:
2225 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2229 if (VA.needsCustom()) {
2230 if (VA.getLocVT() == MVT::v2f64) {
2231 // Extract the first half and return it in two registers.
2232 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2233 DAG.getConstant(0, dl, MVT::i32));
2234 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
2235 DAG.getVTList(MVT::i32, MVT::i32), Half);
2237 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2238 HalfGPRs.getValue(isLittleEndian ? 0 : 1),
2240 Flag = Chain.getValue(1);
2241 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2242 VA = RVLocs[++i]; // skip ahead to next loc
2243 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2244 HalfGPRs.getValue(isLittleEndian ? 1 : 0),
2246 Flag = Chain.getValue(1);
2247 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2248 VA = RVLocs[++i]; // skip ahead to next loc
2250 // Extract the 2nd half and fall through to handle it as an f64 value.
2251 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2252 DAG.getConstant(1, dl, MVT::i32));
2254 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
2256 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
2257 DAG.getVTList(MVT::i32, MVT::i32), Arg);
2258 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2259 fmrrd.getValue(isLittleEndian ? 0 : 1),
2261 Flag = Chain.getValue(1);
2262 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2263 VA = RVLocs[++i]; // skip ahead to next loc
2264 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2265 fmrrd.getValue(isLittleEndian ? 1 : 0),
2268 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
2270 // Guarantee that all emitted copies are
2271 // stuck together, avoiding something bad.
2272 Flag = Chain.getValue(1);
2273 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2276 // Update chain and glue.
2279 RetOps.push_back(Flag);
2281 // CPUs which aren't M-class use a special sequence to return from
2282 // exceptions (roughly, any instruction setting pc and cpsr simultaneously,
2283 // though we use "subs pc, lr, #N").
2285 // M-class CPUs actually use a normal return sequence with a special
2286 // (hardware-provided) value in LR, so the normal code path works.
2287 if (DAG.getMachineFunction().getFunction()->hasFnAttribute("interrupt") &&
2288 !Subtarget->isMClass()) {
2289 if (Subtarget->isThumb1Only())
2290 report_fatal_error("interrupt attribute is not supported in Thumb1");
2291 return LowerInterruptReturn(RetOps, dl, DAG);
2294 return DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, RetOps);
2297 bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2298 if (N->getNumValues() != 1)
2300 if (!N->hasNUsesOfValue(1, 0))
2303 SDValue TCChain = Chain;
2304 SDNode *Copy = *N->use_begin();
2305 if (Copy->getOpcode() == ISD::CopyToReg) {
2306 // If the copy has a glue operand, we conservatively assume it isn't safe to
2307 // perform a tail call.
2308 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2310 TCChain = Copy->getOperand(0);
2311 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) {
2312 SDNode *VMov = Copy;
2313 // f64 returned in a pair of GPRs.
2314 SmallPtrSet<SDNode*, 2> Copies;
2315 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2317 if (UI->getOpcode() != ISD::CopyToReg)
2321 if (Copies.size() > 2)
2324 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2326 SDValue UseChain = UI->getOperand(0);
2327 if (Copies.count(UseChain.getNode()))
2331 // We are at the top of this chain.
2332 // If the copy has a glue operand, we conservatively assume it
2333 // isn't safe to perform a tail call.
2334 if (UI->getOperand(UI->getNumOperands()-1).getValueType() == MVT::Glue)
2340 } else if (Copy->getOpcode() == ISD::BITCAST) {
2341 // f32 returned in a single GPR.
2342 if (!Copy->hasOneUse())
2344 Copy = *Copy->use_begin();
2345 if (Copy->getOpcode() != ISD::CopyToReg || !Copy->hasNUsesOfValue(1, 0))
2347 // If the copy has a glue operand, we conservatively assume it isn't safe to
2348 // perform a tail call.
2349 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2351 TCChain = Copy->getOperand(0);
2356 bool HasRet = false;
2357 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2359 if (UI->getOpcode() != ARMISD::RET_FLAG &&
2360 UI->getOpcode() != ARMISD::INTRET_FLAG)
2372 bool ARMTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2373 if (!Subtarget->supportsTailCall())
2377 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2378 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2381 return !Subtarget->isThumb1Only();
2384 // Trying to write a 64 bit value so need to split into two 32 bit values first,
2385 // and pass the lower and high parts through.
2386 static SDValue LowerWRITE_REGISTER(SDValue Op, SelectionDAG &DAG) {
2388 SDValue WriteValue = Op->getOperand(2);
2390 // This function is only supposed to be called for i64 type argument.
2391 assert(WriteValue.getValueType() == MVT::i64
2392 && "LowerWRITE_REGISTER called for non-i64 type argument.");
2394 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
2395 DAG.getConstant(0, DL, MVT::i32));
2396 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
2397 DAG.getConstant(1, DL, MVT::i32));
2398 SDValue Ops[] = { Op->getOperand(0), Op->getOperand(1), Lo, Hi };
2399 return DAG.getNode(ISD::WRITE_REGISTER, DL, MVT::Other, Ops);
2402 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
2403 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
2404 // one of the above mentioned nodes. It has to be wrapped because otherwise
2405 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
2406 // be used to form addressing mode. These wrapped nodes will be selected
2408 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
2409 EVT PtrVT = Op.getValueType();
2410 // FIXME there is no actual debug info here
2412 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2414 if (CP->isMachineConstantPoolEntry())
2415 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
2416 CP->getAlignment());
2418 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
2419 CP->getAlignment());
2420 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
2423 unsigned ARMTargetLowering::getJumpTableEncoding() const {
2424 return MachineJumpTableInfo::EK_Inline;
2427 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
2428 SelectionDAG &DAG) const {
2429 MachineFunction &MF = DAG.getMachineFunction();
2430 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2431 unsigned ARMPCLabelIndex = 0;
2433 EVT PtrVT = getPointerTy();
2434 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
2435 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2437 if (RelocM == Reloc::Static) {
2438 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
2440 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2441 ARMPCLabelIndex = AFI->createPICLabelUId();
2442 ARMConstantPoolValue *CPV =
2443 ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex,
2444 ARMCP::CPBlockAddress, PCAdj);
2445 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2447 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
2448 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
2449 MachinePointerInfo::getConstantPool(),
2450 false, false, false, 0);
2451 if (RelocM == Reloc::Static)
2453 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, DL, MVT::i32);
2454 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
2457 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
2459 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
2460 SelectionDAG &DAG) const {
2462 EVT PtrVT = getPointerTy();
2463 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2464 MachineFunction &MF = DAG.getMachineFunction();
2465 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2466 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2467 ARMConstantPoolValue *CPV =
2468 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2469 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
2470 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2471 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
2472 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
2473 MachinePointerInfo::getConstantPool(),
2474 false, false, false, 0);
2475 SDValue Chain = Argument.getValue(1);
2477 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2478 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
2480 // call __tls_get_addr.
2483 Entry.Node = Argument;
2484 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
2485 Args.push_back(Entry);
2487 // FIXME: is there useful debug info available here?
2488 TargetLowering::CallLoweringInfo CLI(DAG);
2489 CLI.setDebugLoc(dl).setChain(Chain)
2490 .setCallee(CallingConv::C, Type::getInt32Ty(*DAG.getContext()),
2491 DAG.getExternalSymbol("__tls_get_addr", PtrVT), std::move(Args),
2494 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2495 return CallResult.first;
2498 // Lower ISD::GlobalTLSAddress using the "initial exec" or
2499 // "local exec" model.
2501 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
2503 TLSModel::Model model) const {
2504 const GlobalValue *GV = GA->getGlobal();
2507 SDValue Chain = DAG.getEntryNode();
2508 EVT PtrVT = getPointerTy();
2509 // Get the Thread Pointer
2510 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2512 if (model == TLSModel::InitialExec) {
2513 MachineFunction &MF = DAG.getMachineFunction();
2514 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2515 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2516 // Initial exec model.
2517 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2518 ARMConstantPoolValue *CPV =
2519 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2520 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF,
2522 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2523 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2524 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2525 MachinePointerInfo::getConstantPool(),
2526 false, false, false, 0);
2527 Chain = Offset.getValue(1);
2529 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2530 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
2532 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2533 MachinePointerInfo::getConstantPool(),
2534 false, false, false, 0);
2537 assert(model == TLSModel::LocalExec);
2538 ARMConstantPoolValue *CPV =
2539 ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF);
2540 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2541 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2542 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2543 MachinePointerInfo::getConstantPool(),
2544 false, false, false, 0);
2547 // The address of the thread local variable is the add of the thread
2548 // pointer with the offset of the variable.
2549 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
2553 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
2554 // TODO: implement the "local dynamic" model
2555 assert(Subtarget->isTargetELF() &&
2556 "TLS not implemented for non-ELF targets");
2557 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2559 TLSModel::Model model = getTargetMachine().getTLSModel(GA->getGlobal());
2562 case TLSModel::GeneralDynamic:
2563 case TLSModel::LocalDynamic:
2564 return LowerToTLSGeneralDynamicModel(GA, DAG);
2565 case TLSModel::InitialExec:
2566 case TLSModel::LocalExec:
2567 return LowerToTLSExecModels(GA, DAG, model);
2569 llvm_unreachable("bogus TLS model");
2572 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
2573 SelectionDAG &DAG) const {
2574 EVT PtrVT = getPointerTy();
2576 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2577 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2578 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
2579 ARMConstantPoolValue *CPV =
2580 ARMConstantPoolConstant::Create(GV,
2581 UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
2582 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2583 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2584 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
2586 MachinePointerInfo::getConstantPool(),
2587 false, false, false, 0);
2588 SDValue Chain = Result.getValue(1);
2589 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
2590 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
2592 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
2593 MachinePointerInfo::getGOT(),
2594 false, false, false, 0);
2598 // If we have T2 ops, we can materialize the address directly via movt/movw
2599 // pair. This is always cheaper.
2600 if (Subtarget->useMovt(DAG.getMachineFunction())) {
2602 // FIXME: Once remat is capable of dealing with instructions with register
2603 // operands, expand this into two nodes.
2604 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2605 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2607 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
2608 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2609 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2610 MachinePointerInfo::getConstantPool(),
2611 false, false, false, 0);
2615 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
2616 SelectionDAG &DAG) const {
2617 EVT PtrVT = getPointerTy();
2619 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2620 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2622 if (Subtarget->useMovt(DAG.getMachineFunction()))
2625 // FIXME: Once remat is capable of dealing with instructions with register
2626 // operands, expand this into multiple nodes
2628 RelocM == Reloc::PIC_ ? ARMISD::WrapperPIC : ARMISD::Wrapper;
2630 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_NONLAZY);
2631 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT, G);
2633 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
2634 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
2635 MachinePointerInfo::getGOT(), false, false, false, 0);
2639 SDValue ARMTargetLowering::LowerGlobalAddressWindows(SDValue Op,
2640 SelectionDAG &DAG) const {
2641 assert(Subtarget->isTargetWindows() && "non-Windows COFF is not supported");
2642 assert(Subtarget->useMovt(DAG.getMachineFunction()) &&
2643 "Windows on ARM expects to use movw/movt");
2645 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2646 EVT PtrVT = getPointerTy();
2652 // FIXME: Once remat is capable of dealing with instructions with register
2653 // operands, expand this into two nodes.
2654 Result = DAG.getNode(ARMISD::Wrapper, DL, PtrVT,
2655 DAG.getTargetGlobalAddress(GV, DL, PtrVT, /*Offset=*/0,
2656 ARMII::MO_NO_FLAG));
2657 if (GV->hasDLLImportStorageClass())
2658 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
2659 MachinePointerInfo::getGOT(), false, false, false, 0);
2663 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
2664 SelectionDAG &DAG) const {
2665 assert(Subtarget->isTargetELF() &&
2666 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
2667 MachineFunction &MF = DAG.getMachineFunction();
2668 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2669 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2670 EVT PtrVT = getPointerTy();
2672 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2673 ARMConstantPoolValue *CPV =
2674 ARMConstantPoolSymbol::Create(*DAG.getContext(), "_GLOBAL_OFFSET_TABLE_",
2675 ARMPCLabelIndex, PCAdj);
2676 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2677 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2678 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2679 MachinePointerInfo::getConstantPool(),
2680 false, false, false, 0);
2681 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2682 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2686 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
2688 SDValue Val = DAG.getConstant(0, dl, MVT::i32);
2689 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl,
2690 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
2691 Op.getOperand(1), Val);
2695 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
2697 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
2698 Op.getOperand(1), DAG.getConstant(0, dl, MVT::i32));
2702 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
2703 const ARMSubtarget *Subtarget) const {
2704 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2707 default: return SDValue(); // Don't custom lower most intrinsics.
2708 case Intrinsic::arm_rbit: {
2709 assert(Op.getOperand(1).getValueType() == MVT::i32 &&
2710 "RBIT intrinsic must have i32 type!");
2711 return DAG.getNode(ARMISD::RBIT, dl, MVT::i32, Op.getOperand(1));
2713 case Intrinsic::arm_thread_pointer: {
2714 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2715 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2717 case Intrinsic::eh_sjlj_lsda: {
2718 MachineFunction &MF = DAG.getMachineFunction();
2719 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2720 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2721 EVT PtrVT = getPointerTy();
2722 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2724 unsigned PCAdj = (RelocM != Reloc::PIC_)
2725 ? 0 : (Subtarget->isThumb() ? 4 : 8);
2726 ARMConstantPoolValue *CPV =
2727 ARMConstantPoolConstant::Create(MF.getFunction(), ARMPCLabelIndex,
2728 ARMCP::CPLSDA, PCAdj);
2729 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2730 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2732 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2733 MachinePointerInfo::getConstantPool(),
2734 false, false, false, 0);
2736 if (RelocM == Reloc::PIC_) {
2737 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2738 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2742 case Intrinsic::arm_neon_vmulls:
2743 case Intrinsic::arm_neon_vmullu: {
2744 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
2745 ? ARMISD::VMULLs : ARMISD::VMULLu;
2746 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
2747 Op.getOperand(1), Op.getOperand(2));
2752 static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
2753 const ARMSubtarget *Subtarget) {
2754 // FIXME: handle "fence singlethread" more efficiently.
2756 if (!Subtarget->hasDataBarrier()) {
2757 // Some ARMv6 cpus can support data barriers with an mcr instruction.
2758 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
2760 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&
2761 "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!");
2762 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2763 DAG.getConstant(0, dl, MVT::i32));
2766 ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1));
2767 AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue());
2768 ARM_MB::MemBOpt Domain = ARM_MB::ISH;
2769 if (Subtarget->isMClass()) {
2770 // Only a full system barrier exists in the M-class architectures.
2771 Domain = ARM_MB::SY;
2772 } else if (Subtarget->isSwift() && Ord == Release) {
2773 // Swift happens to implement ISHST barriers in a way that's compatible with
2774 // Release semantics but weaker than ISH so we'd be fools not to use
2775 // it. Beware: other processors probably don't!
2776 Domain = ARM_MB::ISHST;
2779 return DAG.getNode(ISD::INTRINSIC_VOID, dl, MVT::Other, Op.getOperand(0),
2780 DAG.getConstant(Intrinsic::arm_dmb, dl, MVT::i32),
2781 DAG.getConstant(Domain, dl, MVT::i32));
2784 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
2785 const ARMSubtarget *Subtarget) {
2786 // ARM pre v5TE and Thumb1 does not have preload instructions.
2787 if (!(Subtarget->isThumb2() ||
2788 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
2789 // Just preserve the chain.
2790 return Op.getOperand(0);
2793 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
2795 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
2796 // ARMv7 with MP extension has PLDW.
2797 return Op.getOperand(0);
2799 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
2800 if (Subtarget->isThumb()) {
2802 isRead = ~isRead & 1;
2803 isData = ~isData & 1;
2806 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
2807 Op.getOperand(1), DAG.getConstant(isRead, dl, MVT::i32),
2808 DAG.getConstant(isData, dl, MVT::i32));
2811 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
2812 MachineFunction &MF = DAG.getMachineFunction();
2813 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
2815 // vastart just stores the address of the VarArgsFrameIndex slot into the
2816 // memory location argument.
2818 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2819 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2820 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2821 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2822 MachinePointerInfo(SV), false, false, 0);
2826 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
2827 SDValue &Root, SelectionDAG &DAG,
2829 MachineFunction &MF = DAG.getMachineFunction();
2830 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2832 const TargetRegisterClass *RC;
2833 if (AFI->isThumb1OnlyFunction())
2834 RC = &ARM::tGPRRegClass;
2836 RC = &ARM::GPRRegClass;
2838 // Transform the arguments stored in physical registers into virtual ones.
2839 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2840 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2843 if (NextVA.isMemLoc()) {
2844 MachineFrameInfo *MFI = MF.getFrameInfo();
2845 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
2847 // Create load node to retrieve arguments from the stack.
2848 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2849 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
2850 MachinePointerInfo::getFixedStack(FI),
2851 false, false, false, 0);
2853 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2854 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2856 if (!Subtarget->isLittle())
2857 std::swap (ArgValue, ArgValue2);
2858 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
2861 // The remaining GPRs hold either the beginning of variable-argument
2862 // data, or the beginning of an aggregate passed by value (usually
2863 // byval). Either way, we allocate stack slots adjacent to the data
2864 // provided by our caller, and store the unallocated registers there.
2865 // If this is a variadic function, the va_list pointer will begin with
2866 // these values; otherwise, this reassembles a (byval) structure that
2867 // was split between registers and memory.
2868 // Return: The frame index registers were stored into.
2870 ARMTargetLowering::StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
2871 SDLoc dl, SDValue &Chain,
2872 const Value *OrigArg,
2873 unsigned InRegsParamRecordIdx,
2875 unsigned ArgSize) const {
2876 // Currently, two use-cases possible:
2877 // Case #1. Non-var-args function, and we meet first byval parameter.
2878 // Setup first unallocated register as first byval register;
2879 // eat all remained registers
2880 // (these two actions are performed by HandleByVal method).
2881 // Then, here, we initialize stack frame with
2882 // "store-reg" instructions.
2883 // Case #2. Var-args function, that doesn't contain byval parameters.
2884 // The same: eat all remained unallocated registers,
2885 // initialize stack frame.
2887 MachineFunction &MF = DAG.getMachineFunction();
2888 MachineFrameInfo *MFI = MF.getFrameInfo();
2889 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2890 unsigned RBegin, REnd;
2891 if (InRegsParamRecordIdx < CCInfo.getInRegsParamsCount()) {
2892 CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd);
2894 unsigned RBeginIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
2895 RBegin = RBeginIdx == 4 ? (unsigned)ARM::R4 : GPRArgRegs[RBeginIdx];
2900 ArgOffset = -4 * (ARM::R4 - RBegin);
2902 int FrameIndex = MFI->CreateFixedObject(ArgSize, ArgOffset, false);
2903 SDValue FIN = DAG.getFrameIndex(FrameIndex, getPointerTy());
2905 SmallVector<SDValue, 4> MemOps;
2906 const TargetRegisterClass *RC =
2907 AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
2909 for (unsigned Reg = RBegin, i = 0; Reg < REnd; ++Reg, ++i) {
2910 unsigned VReg = MF.addLiveIn(Reg, RC);
2911 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2913 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2914 MachinePointerInfo(OrigArg, 4 * i), false, false, 0);
2915 MemOps.push_back(Store);
2916 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
2917 DAG.getConstant(4, dl, getPointerTy()));
2920 if (!MemOps.empty())
2921 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2925 // Setup stack frame, the va_list pointer will start from.
2927 ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
2928 SDLoc dl, SDValue &Chain,
2930 unsigned TotalArgRegsSaveSize,
2931 bool ForceMutable) const {
2932 MachineFunction &MF = DAG.getMachineFunction();
2933 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2935 // Try to store any remaining integer argument regs
2936 // to their spots on the stack so that they may be loaded by deferencing
2937 // the result of va_next.
2938 // If there is no regs to be stored, just point address after last
2939 // argument passed via stack.
2940 int FrameIndex = StoreByValRegs(CCInfo, DAG, dl, Chain, nullptr,
2941 CCInfo.getInRegsParamsCount(),
2942 CCInfo.getNextStackOffset(), 4);
2943 AFI->setVarArgsFrameIndex(FrameIndex);
2947 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
2948 CallingConv::ID CallConv, bool isVarArg,
2949 const SmallVectorImpl<ISD::InputArg>
2951 SDLoc dl, SelectionDAG &DAG,
2952 SmallVectorImpl<SDValue> &InVals)
2954 MachineFunction &MF = DAG.getMachineFunction();
2955 MachineFrameInfo *MFI = MF.getFrameInfo();
2957 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2959 // Assign locations to all of the incoming arguments.
2960 SmallVector<CCValAssign, 16> ArgLocs;
2961 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2962 *DAG.getContext(), Prologue);
2963 CCInfo.AnalyzeFormalArguments(Ins,
2964 CCAssignFnForNode(CallConv, /* Return*/ false,
2967 SmallVector<SDValue, 16> ArgValues;
2969 Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin();
2970 unsigned CurArgIdx = 0;
2972 // Initially ArgRegsSaveSize is zero.
2973 // Then we increase this value each time we meet byval parameter.
2974 // We also increase this value in case of varargs function.
2975 AFI->setArgRegsSaveSize(0);
2977 // Calculate the amount of stack space that we need to allocate to store
2978 // byval and variadic arguments that are passed in registers.
2979 // We need to know this before we allocate the first byval or variadic
2980 // argument, as they will be allocated a stack slot below the CFA (Canonical
2981 // Frame Address, the stack pointer at entry to the function).
2982 unsigned ArgRegBegin = ARM::R4;
2983 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2984 if (CCInfo.getInRegsParamsProcessed() >= CCInfo.getInRegsParamsCount())
2987 CCValAssign &VA = ArgLocs[i];
2988 unsigned Index = VA.getValNo();
2989 ISD::ArgFlagsTy Flags = Ins[Index].Flags;
2990 if (!Flags.isByVal())
2993 assert(VA.isMemLoc() && "unexpected byval pointer in reg");
2994 unsigned RBegin, REnd;
2995 CCInfo.getInRegsParamInfo(CCInfo.getInRegsParamsProcessed(), RBegin, REnd);
2996 ArgRegBegin = std::min(ArgRegBegin, RBegin);
2998 CCInfo.nextInRegsParam();
3000 CCInfo.rewindByValRegsInfo();
3002 int lastInsIndex = -1;
3003 if (isVarArg && MFI->hasVAStart()) {
3004 unsigned RegIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
3005 if (RegIdx != array_lengthof(GPRArgRegs))
3006 ArgRegBegin = std::min(ArgRegBegin, (unsigned)GPRArgRegs[RegIdx]);
3009 unsigned TotalArgRegsSaveSize = 4 * (ARM::R4 - ArgRegBegin);
3010 AFI->setArgRegsSaveSize(TotalArgRegsSaveSize);
3012 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3013 CCValAssign &VA = ArgLocs[i];
3014 if (Ins[VA.getValNo()].isOrigArg()) {
3015 std::advance(CurOrigArg,
3016 Ins[VA.getValNo()].getOrigArgIndex() - CurArgIdx);
3017 CurArgIdx = Ins[VA.getValNo()].getOrigArgIndex();
3019 // Arguments stored in registers.
3020 if (VA.isRegLoc()) {
3021 EVT RegVT = VA.getLocVT();
3023 if (VA.needsCustom()) {
3024 // f64 and vector types are split up into multiple registers or
3025 // combinations of registers and stack slots.
3026 if (VA.getLocVT() == MVT::v2f64) {
3027 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
3029 VA = ArgLocs[++i]; // skip ahead to next loc
3031 if (VA.isMemLoc()) {
3032 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
3033 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
3034 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
3035 MachinePointerInfo::getFixedStack(FI),
3036 false, false, false, 0);
3038 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
3041 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
3042 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
3043 ArgValue, ArgValue1,
3044 DAG.getIntPtrConstant(0, dl));
3045 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
3046 ArgValue, ArgValue2,
3047 DAG.getIntPtrConstant(1, dl));
3049 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
3052 const TargetRegisterClass *RC;
3054 if (RegVT == MVT::f32)
3055 RC = &ARM::SPRRegClass;
3056 else if (RegVT == MVT::f64)
3057 RC = &ARM::DPRRegClass;
3058 else if (RegVT == MVT::v2f64)
3059 RC = &ARM::QPRRegClass;
3060 else if (RegVT == MVT::i32)
3061 RC = AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass
3062 : &ARM::GPRRegClass;
3064 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
3066 // Transform the arguments in physical registers into virtual ones.
3067 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3068 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
3071 // If this is an 8 or 16-bit value, it is really passed promoted
3072 // to 32 bits. Insert an assert[sz]ext to capture this, then
3073 // truncate to the right size.
3074 switch (VA.getLocInfo()) {
3075 default: llvm_unreachable("Unknown loc info!");
3076 case CCValAssign::Full: break;
3077 case CCValAssign::BCvt:
3078 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
3080 case CCValAssign::SExt:
3081 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
3082 DAG.getValueType(VA.getValVT()));
3083 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3085 case CCValAssign::ZExt:
3086 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
3087 DAG.getValueType(VA.getValVT()));
3088 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3092 InVals.push_back(ArgValue);
3094 } else { // VA.isRegLoc()
3097 assert(VA.isMemLoc());
3098 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
3100 int index = VA.getValNo();
3102 // Some Ins[] entries become multiple ArgLoc[] entries.
3103 // Process them only once.
3104 if (index != lastInsIndex)
3106 ISD::ArgFlagsTy Flags = Ins[index].Flags;
3107 // FIXME: For now, all byval parameter objects are marked mutable.
3108 // This can be changed with more analysis.
3109 // In case of tail call optimization mark all arguments mutable.
3110 // Since they could be overwritten by lowering of arguments in case of
3112 if (Flags.isByVal()) {
3113 assert(Ins[index].isOrigArg() &&
3114 "Byval arguments cannot be implicit");
3115 unsigned CurByValIndex = CCInfo.getInRegsParamsProcessed();
3117 int FrameIndex = StoreByValRegs(CCInfo, DAG, dl, Chain, CurOrigArg,
3118 CurByValIndex, VA.getLocMemOffset(),
3119 Flags.getByValSize());
3120 InVals.push_back(DAG.getFrameIndex(FrameIndex, getPointerTy()));
3121 CCInfo.nextInRegsParam();
3123 unsigned FIOffset = VA.getLocMemOffset();
3124 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
3127 // Create load nodes to retrieve arguments from the stack.
3128 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
3129 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
3130 MachinePointerInfo::getFixedStack(FI),
3131 false, false, false, 0));
3133 lastInsIndex = index;
3139 if (isVarArg && MFI->hasVAStart())
3140 VarArgStyleRegisters(CCInfo, DAG, dl, Chain,
3141 CCInfo.getNextStackOffset(),
3142 TotalArgRegsSaveSize);
3144 AFI->setArgumentStackSize(CCInfo.getNextStackOffset());
3149 /// isFloatingPointZero - Return true if this is +0.0.
3150 static bool isFloatingPointZero(SDValue Op) {
3151 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
3152 return CFP->getValueAPF().isPosZero();
3153 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
3154 // Maybe this has already been legalized into the constant pool?
3155 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
3156 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
3157 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
3158 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
3159 return CFP->getValueAPF().isPosZero();
3161 } else if (Op->getOpcode() == ISD::BITCAST &&
3162 Op->getValueType(0) == MVT::f64) {
3163 // Handle (ISD::BITCAST (ARMISD::VMOVIMM (ISD::TargetConstant 0)) MVT::f64)
3164 // created by LowerConstantFP().
3165 SDValue BitcastOp = Op->getOperand(0);
3166 if (BitcastOp->getOpcode() == ARMISD::VMOVIMM) {
3167 SDValue MoveOp = BitcastOp->getOperand(0);
3168 if (MoveOp->getOpcode() == ISD::TargetConstant &&
3169 cast<ConstantSDNode>(MoveOp)->getZExtValue() == 0) {
3177 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
3178 /// the given operands.
3180 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
3181 SDValue &ARMcc, SelectionDAG &DAG,
3183 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
3184 unsigned C = RHSC->getZExtValue();
3185 if (!isLegalICmpImmediate(C)) {
3186 // Constant does not fit, try adjusting it by one?
3191 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
3192 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
3193 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
3198 if (C != 0 && isLegalICmpImmediate(C-1)) {
3199 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
3200 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
3205 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
3206 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
3207 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
3212 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
3213 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
3214 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
3221 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3222 ARMISD::NodeType CompareType;
3225 CompareType = ARMISD::CMP;
3230 CompareType = ARMISD::CMPZ;
3233 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
3234 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
3237 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
3239 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
3241 assert(!Subtarget->isFPOnlySP() || RHS.getValueType() != MVT::f64);
3243 if (!isFloatingPointZero(RHS))
3244 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS);
3246 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS);
3247 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
3250 /// duplicateCmp - Glue values can have only one use, so this function
3251 /// duplicates a comparison node.
3253 ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
3254 unsigned Opc = Cmp.getOpcode();
3256 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
3257 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
3259 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation");
3260 Cmp = Cmp.getOperand(0);
3261 Opc = Cmp.getOpcode();
3262 if (Opc == ARMISD::CMPFP)
3263 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
3265 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT");
3266 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0));
3268 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
3271 std::pair<SDValue, SDValue>
3272 ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG,
3273 SDValue &ARMcc) const {
3274 assert(Op.getValueType() == MVT::i32 && "Unsupported value type");
3276 SDValue Value, OverflowCmp;
3277 SDValue LHS = Op.getOperand(0);
3278 SDValue RHS = Op.getOperand(1);
3281 // FIXME: We are currently always generating CMPs because we don't support
3282 // generating CMN through the backend. This is not as good as the natural
3283 // CMP case because it causes a register dependency and cannot be folded
3286 switch (Op.getOpcode()) {
3288 llvm_unreachable("Unknown overflow instruction!");
3290 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
3291 Value = DAG.getNode(ISD::ADD, dl, Op.getValueType(), LHS, RHS);
3292 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
3295 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
3296 Value = DAG.getNode(ISD::ADD, dl, Op.getValueType(), LHS, RHS);
3297 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
3300 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
3301 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
3302 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
3305 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
3306 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
3307 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
3311 return std::make_pair(Value, OverflowCmp);
3316 ARMTargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
3317 // Let legalize expand this if it isn't a legal type yet.
3318 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
3321 SDValue Value, OverflowCmp;
3323 std::tie(Value, OverflowCmp) = getARMXALUOOp(Op, DAG, ARMcc);
3324 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3326 // We use 0 and 1 as false and true values.
3327 SDValue TVal = DAG.getConstant(1, dl, MVT::i32);
3328 SDValue FVal = DAG.getConstant(0, dl, MVT::i32);
3329 EVT VT = Op.getValueType();
3331 SDValue Overflow = DAG.getNode(ARMISD::CMOV, dl, VT, TVal, FVal,
3332 ARMcc, CCR, OverflowCmp);
3334 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
3335 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
3339 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
3340 SDValue Cond = Op.getOperand(0);
3341 SDValue SelectTrue = Op.getOperand(1);
3342 SDValue SelectFalse = Op.getOperand(2);
3344 unsigned Opc = Cond.getOpcode();
3346 if (Cond.getResNo() == 1 &&
3347 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3348 Opc == ISD::USUBO)) {
3349 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
3352 SDValue Value, OverflowCmp;
3354 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
3355 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3356 EVT VT = Op.getValueType();
3358 return getCMOV(dl, VT, SelectTrue, SelectFalse, ARMcc, CCR,
3364 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
3365 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
3367 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
3368 const ConstantSDNode *CMOVTrue =
3369 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
3370 const ConstantSDNode *CMOVFalse =
3371 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
3373 if (CMOVTrue && CMOVFalse) {
3374 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
3375 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
3379 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
3381 False = SelectFalse;
3382 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
3387 if (True.getNode() && False.getNode()) {
3388 EVT VT = Op.getValueType();
3389 SDValue ARMcc = Cond.getOperand(2);
3390 SDValue CCR = Cond.getOperand(3);
3391 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
3392 assert(True.getValueType() == VT);
3393 return getCMOV(dl, VT, True, False, ARMcc, CCR, Cmp, DAG);
3398 // ARM's BooleanContents value is UndefinedBooleanContent. Mask out the
3399 // undefined bits before doing a full-word comparison with zero.
3400 Cond = DAG.getNode(ISD::AND, dl, Cond.getValueType(), Cond,
3401 DAG.getConstant(1, dl, Cond.getValueType()));
3403 return DAG.getSelectCC(dl, Cond,
3404 DAG.getConstant(0, dl, Cond.getValueType()),
3405 SelectTrue, SelectFalse, ISD::SETNE);
3408 static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
3409 bool &swpCmpOps, bool &swpVselOps) {
3410 // Start by selecting the GE condition code for opcodes that return true for
3412 if (CC == ISD::SETUGE || CC == ISD::SETOGE || CC == ISD::SETOLE ||
3414 CondCode = ARMCC::GE;
3416 // and GT for opcodes that return false for 'equality'.
3417 else if (CC == ISD::SETUGT || CC == ISD::SETOGT || CC == ISD::SETOLT ||
3419 CondCode = ARMCC::GT;
3421 // Since we are constrained to GE/GT, if the opcode contains 'less', we need
3422 // to swap the compare operands.
3423 if (CC == ISD::SETOLE || CC == ISD::SETULE || CC == ISD::SETOLT ||
3427 // Both GT and GE are ordered comparisons, and return false for 'unordered'.
3428 // If we have an unordered opcode, we need to swap the operands to the VSEL
3429 // instruction (effectively negating the condition).
3431 // This also has the effect of swapping which one of 'less' or 'greater'
3432 // returns true, so we also swap the compare operands. It also switches
3433 // whether we return true for 'equality', so we compensate by picking the
3434 // opposite condition code to our original choice.
3435 if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE ||
3436 CC == ISD::SETUGT) {
3437 swpCmpOps = !swpCmpOps;
3438 swpVselOps = !swpVselOps;
3439 CondCode = CondCode == ARMCC::GT ? ARMCC::GE : ARMCC::GT;
3442 // 'ordered' is 'anything but unordered', so use the VS condition code and
3443 // swap the VSEL operands.
3444 if (CC == ISD::SETO) {
3445 CondCode = ARMCC::VS;
3449 // 'unordered or not equal' is 'anything but equal', so use the EQ condition
3450 // code and swap the VSEL operands.
3451 if (CC == ISD::SETUNE) {
3452 CondCode = ARMCC::EQ;
3457 SDValue ARMTargetLowering::getCMOV(SDLoc dl, EVT VT, SDValue FalseVal,
3458 SDValue TrueVal, SDValue ARMcc, SDValue CCR,
3459 SDValue Cmp, SelectionDAG &DAG) const {
3460 if (Subtarget->isFPOnlySP() && VT == MVT::f64) {
3461 FalseVal = DAG.getNode(ARMISD::VMOVRRD, dl,
3462 DAG.getVTList(MVT::i32, MVT::i32), FalseVal);
3463 TrueVal = DAG.getNode(ARMISD::VMOVRRD, dl,
3464 DAG.getVTList(MVT::i32, MVT::i32), TrueVal);
3466 SDValue TrueLow = TrueVal.getValue(0);
3467 SDValue TrueHigh = TrueVal.getValue(1);
3468 SDValue FalseLow = FalseVal.getValue(0);
3469 SDValue FalseHigh = FalseVal.getValue(1);
3471 SDValue Low = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseLow, TrueLow,
3473 SDValue High = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseHigh, TrueHigh,
3474 ARMcc, CCR, duplicateCmp(Cmp, DAG));
3476 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Low, High);
3478 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,
3483 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
3484 EVT VT = Op.getValueType();
3485 SDValue LHS = Op.getOperand(0);
3486 SDValue RHS = Op.getOperand(1);
3487 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3488 SDValue TrueVal = Op.getOperand(2);
3489 SDValue FalseVal = Op.getOperand(3);
3492 if (Subtarget->isFPOnlySP() && LHS.getValueType() == MVT::f64) {
3493 DAG.getTargetLoweringInfo().softenSetCCOperands(DAG, MVT::f64, LHS, RHS, CC,
3496 // If softenSetCCOperands only returned one value, we should compare it to
3498 if (!RHS.getNode()) {
3499 RHS = DAG.getConstant(0, dl, LHS.getValueType());
3504 if (LHS.getValueType() == MVT::i32) {
3505 // Try to generate VSEL on ARMv8.
3506 // The VSEL instruction can't use all the usual ARM condition
3507 // codes: it only has two bits to select the condition code, so it's
3508 // constrained to use only GE, GT, VS and EQ.
3510 // To implement all the various ISD::SETXXX opcodes, we sometimes need to
3511 // swap the operands of the previous compare instruction (effectively
3512 // inverting the compare condition, swapping 'less' and 'greater') and
3513 // sometimes need to swap the operands to the VSEL (which inverts the
3514 // condition in the sense of firing whenever the previous condition didn't)
3515 if (Subtarget->hasFPARMv8() && (TrueVal.getValueType() == MVT::f32 ||
3516 TrueVal.getValueType() == MVT::f64)) {
3517 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3518 if (CondCode == ARMCC::LT || CondCode == ARMCC::LE ||
3519 CondCode == ARMCC::VC || CondCode == ARMCC::NE) {
3520 CC = ISD::getSetCCInverse(CC, true);
3521 std::swap(TrueVal, FalseVal);
3526 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3527 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3528 return getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
3531 ARMCC::CondCodes CondCode, CondCode2;
3532 FPCCToARMCC(CC, CondCode, CondCode2);
3534 // Try to generate VMAXNM/VMINNM on ARMv8.
3535 if (Subtarget->hasFPARMv8() && (TrueVal.getValueType() == MVT::f32 ||
3536 TrueVal.getValueType() == MVT::f64)) {
3537 // We can use VMAXNM/VMINNM for a compare followed by a select with the
3538 // same operands, as follows:
3539 // c = fcmp [?gt, ?ge, ?lt, ?le] a, b
3541 // In NoNaNsFPMath the CC will have been changed from, e.g., 'ogt' to 'gt'.
3542 bool swapSides = false;
3543 if (!getTargetMachine().Options.NoNaNsFPMath) {
3544 // transformability may depend on which way around we compare
3552 // the non-NaN should be RHS
3553 swapSides = DAG.isKnownNeverNaN(LHS) && !DAG.isKnownNeverNaN(RHS);
3559 // the non-NaN should be LHS
3560 swapSides = DAG.isKnownNeverNaN(RHS) && !DAG.isKnownNeverNaN(LHS);
3564 swapSides = swapSides || (LHS == FalseVal && RHS == TrueVal);
3566 CC = ISD::getSetCCSwappedOperands(CC);
3567 std::swap(LHS, RHS);
3569 if (LHS == TrueVal && RHS == FalseVal) {
3570 bool canTransform = true;
3571 // FIXME: FastMathFlags::noSignedZeros() doesn't appear reachable from here
3572 if (!getTargetMachine().Options.UnsafeFPMath &&
3573 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
3574 const ConstantFPSDNode *Zero;
3581 // RHS must not be -0
3582 canTransform = (Zero = dyn_cast<ConstantFPSDNode>(RHS)) &&
3583 !Zero->isNegative();
3588 // LHS must not be -0
3589 canTransform = (Zero = dyn_cast<ConstantFPSDNode>(LHS)) &&
3590 !Zero->isNegative();
3595 // RHS must not be +0
3596 canTransform = (Zero = dyn_cast<ConstantFPSDNode>(RHS)) &&
3602 // LHS must not be +0
3603 canTransform = (Zero = dyn_cast<ConstantFPSDNode>(LHS)) &&
3609 // Note: If one of the elements in a pair is a number and the other
3610 // element is NaN, the corresponding result element is the number.
3611 // This is consistent with the IEEE 754-2008 standard.
3612 // Therefore, a > b ? a : b <=> vmax(a,b), if b is constant and a is NaN
3618 if (!DAG.isKnownNeverNaN(RHS))
3620 return DAG.getNode(ARMISD::VMAXNM, dl, VT, LHS, RHS);
3623 if (!DAG.isKnownNeverNaN(LHS))
3627 return DAG.getNode(ARMISD::VMAXNM, dl, VT, LHS, RHS);
3630 if (!DAG.isKnownNeverNaN(RHS))
3632 return DAG.getNode(ARMISD::VMINNM, dl, VT, LHS, RHS);
3635 if (!DAG.isKnownNeverNaN(LHS))
3639 return DAG.getNode(ARMISD::VMINNM, dl, VT, LHS, RHS);
3644 bool swpCmpOps = false;
3645 bool swpVselOps = false;
3646 checkVSELConstraints(CC, CondCode, swpCmpOps, swpVselOps);
3648 if (CondCode == ARMCC::GT || CondCode == ARMCC::GE ||
3649 CondCode == ARMCC::VS || CondCode == ARMCC::EQ) {
3651 std::swap(LHS, RHS);
3653 std::swap(TrueVal, FalseVal);
3657 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
3658 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
3659 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3660 SDValue Result = getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
3661 if (CondCode2 != ARMCC::AL) {
3662 SDValue ARMcc2 = DAG.getConstant(CondCode2, dl, MVT::i32);
3663 // FIXME: Needs another CMP because flag can have but one use.
3664 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
3665 Result = getCMOV(dl, VT, Result, TrueVal, ARMcc2, CCR, Cmp2, DAG);
3670 /// canChangeToInt - Given the fp compare operand, return true if it is suitable
3671 /// to morph to an integer compare sequence.
3672 static bool canChangeToInt(SDValue Op, bool &SeenZero,
3673 const ARMSubtarget *Subtarget) {
3674 SDNode *N = Op.getNode();
3675 if (!N->hasOneUse())
3676 // Otherwise it requires moving the value from fp to integer registers.
3678 if (!N->getNumValues())
3680 EVT VT = Op.getValueType();
3681 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
3682 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
3683 // vmrs are very slow, e.g. cortex-a8.
3686 if (isFloatingPointZero(Op)) {
3690 return ISD::isNormalLoad(N);
3693 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
3694 if (isFloatingPointZero(Op))
3695 return DAG.getConstant(0, SDLoc(Op), MVT::i32);
3697 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
3698 return DAG.getLoad(MVT::i32, SDLoc(Op),
3699 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(),
3700 Ld->isVolatile(), Ld->isNonTemporal(),
3701 Ld->isInvariant(), Ld->getAlignment());
3703 llvm_unreachable("Unknown VFP cmp argument!");
3706 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
3707 SDValue &RetVal1, SDValue &RetVal2) {
3710 if (isFloatingPointZero(Op)) {
3711 RetVal1 = DAG.getConstant(0, dl, MVT::i32);
3712 RetVal2 = DAG.getConstant(0, dl, MVT::i32);
3716 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
3717 SDValue Ptr = Ld->getBasePtr();
3718 RetVal1 = DAG.getLoad(MVT::i32, dl,
3719 Ld->getChain(), Ptr,
3720 Ld->getPointerInfo(),
3721 Ld->isVolatile(), Ld->isNonTemporal(),
3722 Ld->isInvariant(), Ld->getAlignment());
3724 EVT PtrType = Ptr.getValueType();
3725 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
3726 SDValue NewPtr = DAG.getNode(ISD::ADD, dl,
3727 PtrType, Ptr, DAG.getConstant(4, dl, PtrType));
3728 RetVal2 = DAG.getLoad(MVT::i32, dl,
3729 Ld->getChain(), NewPtr,
3730 Ld->getPointerInfo().getWithOffset(4),
3731 Ld->isVolatile(), Ld->isNonTemporal(),
3732 Ld->isInvariant(), NewAlign);
3736 llvm_unreachable("Unknown VFP cmp argument!");
3739 /// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
3740 /// f32 and even f64 comparisons to integer ones.
3742 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
3743 SDValue Chain = Op.getOperand(0);
3744 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3745 SDValue LHS = Op.getOperand(2);
3746 SDValue RHS = Op.getOperand(3);
3747 SDValue Dest = Op.getOperand(4);
3750 bool LHSSeenZero = false;
3751 bool LHSOk = canChangeToInt(LHS, LHSSeenZero, Subtarget);
3752 bool RHSSeenZero = false;
3753 bool RHSOk = canChangeToInt(RHS, RHSSeenZero, Subtarget);
3754 if (LHSOk && RHSOk && (LHSSeenZero || RHSSeenZero)) {
3755 // If unsafe fp math optimization is enabled and there are no other uses of
3756 // the CMP operands, and the condition code is EQ or NE, we can optimize it
3757 // to an integer comparison.
3758 if (CC == ISD::SETOEQ)
3760 else if (CC == ISD::SETUNE)
3763 SDValue Mask = DAG.getConstant(0x7fffffff, dl, MVT::i32);
3765 if (LHS.getValueType() == MVT::f32) {
3766 LHS = DAG.getNode(ISD::AND, dl, MVT::i32,
3767 bitcastf32Toi32(LHS, DAG), Mask);
3768 RHS = DAG.getNode(ISD::AND, dl, MVT::i32,
3769 bitcastf32Toi32(RHS, DAG), Mask);
3770 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3771 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3772 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
3773 Chain, Dest, ARMcc, CCR, Cmp);
3778 expandf64Toi32(LHS, DAG, LHS1, LHS2);
3779 expandf64Toi32(RHS, DAG, RHS1, RHS2);
3780 LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask);
3781 RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask);
3782 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3783 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
3784 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
3785 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
3786 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops);
3792 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
3793 SDValue Chain = Op.getOperand(0);
3794 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3795 SDValue LHS = Op.getOperand(2);
3796 SDValue RHS = Op.getOperand(3);
3797 SDValue Dest = Op.getOperand(4);
3800 if (Subtarget->isFPOnlySP() && LHS.getValueType() == MVT::f64) {
3801 DAG.getTargetLoweringInfo().softenSetCCOperands(DAG, MVT::f64, LHS, RHS, CC,
3804 // If softenSetCCOperands only returned one value, we should compare it to
3806 if (!RHS.getNode()) {
3807 RHS = DAG.getConstant(0, dl, LHS.getValueType());
3812 if (LHS.getValueType() == MVT::i32) {
3814 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3815 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3816 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
3817 Chain, Dest, ARMcc, CCR, Cmp);
3820 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3822 if (getTargetMachine().Options.UnsafeFPMath &&
3823 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
3824 CC == ISD::SETNE || CC == ISD::SETUNE)) {
3825 SDValue Result = OptimizeVFPBrcond(Op, DAG);
3826 if (Result.getNode())
3830 ARMCC::CondCodes CondCode, CondCode2;
3831 FPCCToARMCC(CC, CondCode, CondCode2);
3833 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
3834 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
3835 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3836 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
3837 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
3838 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
3839 if (CondCode2 != ARMCC::AL) {
3840 ARMcc = DAG.getConstant(CondCode2, dl, MVT::i32);
3841 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
3842 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
3847 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
3848 SDValue Chain = Op.getOperand(0);
3849 SDValue Table = Op.getOperand(1);
3850 SDValue Index = Op.getOperand(2);
3853 EVT PTy = getPointerTy();
3854 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
3855 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
3856 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI);
3857 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, dl, PTy));
3858 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
3859 if (Subtarget->isThumb2()) {
3860 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
3861 // which does another jump to the destination. This also makes it easier
3862 // to translate it to TBB / TBH later.
3863 // FIXME: This might not work if the function is extremely large.
3864 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
3865 Addr, Op.getOperand(2), JTI);
3867 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
3868 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
3869 MachinePointerInfo::getJumpTable(),
3870 false, false, false, 0);
3871 Chain = Addr.getValue(1);
3872 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
3873 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
3875 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
3876 MachinePointerInfo::getJumpTable(),
3877 false, false, false, 0);
3878 Chain = Addr.getValue(1);
3879 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
3883 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
3884 EVT VT = Op.getValueType();
3887 if (Op.getValueType().getVectorElementType() == MVT::i32) {
3888 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32)
3890 return DAG.UnrollVectorOp(Op.getNode());
3893 assert(Op.getOperand(0).getValueType() == MVT::v4f32 &&
3894 "Invalid type for custom lowering!");
3895 if (VT != MVT::v4i16)
3896 return DAG.UnrollVectorOp(Op.getNode());
3898 Op = DAG.getNode(Op.getOpcode(), dl, MVT::v4i32, Op.getOperand(0));
3899 return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
3902 SDValue ARMTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const {
3903 EVT VT = Op.getValueType();
3905 return LowerVectorFP_TO_INT(Op, DAG);
3906 if (Subtarget->isFPOnlySP() && Op.getOperand(0).getValueType() == MVT::f64) {
3908 if (Op.getOpcode() == ISD::FP_TO_SINT)
3909 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(),
3912 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(),
3914 return makeLibCall(DAG, LC, Op.getValueType(), &Op.getOperand(0), 1,
3915 /*isSigned*/ false, SDLoc(Op)).first;
3921 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
3922 EVT VT = Op.getValueType();
3925 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) {
3926 if (VT.getVectorElementType() == MVT::f32)
3928 return DAG.UnrollVectorOp(Op.getNode());
3931 assert(Op.getOperand(0).getValueType() == MVT::v4i16 &&
3932 "Invalid type for custom lowering!");
3933 if (VT != MVT::v4f32)
3934 return DAG.UnrollVectorOp(Op.getNode());
3938 switch (Op.getOpcode()) {
3939 default: llvm_unreachable("Invalid opcode!");
3940 case ISD::SINT_TO_FP:
3941 CastOpc = ISD::SIGN_EXTEND;
3942 Opc = ISD::SINT_TO_FP;
3944 case ISD::UINT_TO_FP:
3945 CastOpc = ISD::ZERO_EXTEND;
3946 Opc = ISD::UINT_TO_FP;
3950 Op = DAG.getNode(CastOpc, dl, MVT::v4i32, Op.getOperand(0));
3951 return DAG.getNode(Opc, dl, VT, Op);
3954 SDValue ARMTargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const {
3955 EVT VT = Op.getValueType();
3957 return LowerVectorINT_TO_FP(Op, DAG);
3958 if (Subtarget->isFPOnlySP() && Op.getValueType() == MVT::f64) {
3960 if (Op.getOpcode() == ISD::SINT_TO_FP)
3961 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(),
3964 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(),
3966 return makeLibCall(DAG, LC, Op.getValueType(), &Op.getOperand(0), 1,
3967 /*isSigned*/ false, SDLoc(Op)).first;
3973 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
3974 // Implement fcopysign with a fabs and a conditional fneg.
3975 SDValue Tmp0 = Op.getOperand(0);
3976 SDValue Tmp1 = Op.getOperand(1);
3978 EVT VT = Op.getValueType();
3979 EVT SrcVT = Tmp1.getValueType();
3980 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
3981 Tmp0.getOpcode() == ARMISD::VMOVDRR;
3982 bool UseNEON = !InGPR && Subtarget->hasNEON();
3985 // Use VBSL to copy the sign bit.
3986 unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80);
3987 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
3988 DAG.getTargetConstant(EncodedVal, dl, MVT::i32));
3989 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
3991 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT,
3992 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
3993 DAG.getConstant(32, dl, MVT::i32));
3994 else /*if (VT == MVT::f32)*/
3995 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
3996 if (SrcVT == MVT::f32) {
3997 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
3999 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT,
4000 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
4001 DAG.getConstant(32, dl, MVT::i32));
4002 } else if (VT == MVT::f32)
4003 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64,
4004 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
4005 DAG.getConstant(32, dl, MVT::i32));
4006 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
4007 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
4009 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff),
4011 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
4012 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
4013 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
4015 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
4016 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
4017 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
4018 if (VT == MVT::f32) {
4019 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
4020 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
4021 DAG.getConstant(0, dl, MVT::i32));
4023 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
4029 // Bitcast operand 1 to i32.
4030 if (SrcVT == MVT::f64)
4031 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
4033 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
4035 // Or in the signbit with integer operations.
4036 SDValue Mask1 = DAG.getConstant(0x80000000, dl, MVT::i32);
4037 SDValue Mask2 = DAG.getConstant(0x7fffffff, dl, MVT::i32);
4038 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
4039 if (VT == MVT::f32) {
4040 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
4041 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
4042 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4043 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
4046 // f64: Or the high part with signbit and then combine two parts.
4047 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
4049 SDValue Lo = Tmp0.getValue(0);
4050 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
4051 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
4052 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
4055 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
4056 MachineFunction &MF = DAG.getMachineFunction();
4057 MachineFrameInfo *MFI = MF.getFrameInfo();
4058 MFI->setReturnAddressIsTaken(true);
4060 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
4063 EVT VT = Op.getValueType();
4065 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4067 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
4068 SDValue Offset = DAG.getConstant(4, dl, MVT::i32);
4069 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
4070 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
4071 MachinePointerInfo(), false, false, false, 0);
4074 // Return LR, which contains the return address. Mark it an implicit live-in.
4075 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
4076 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
4079 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
4080 const ARMBaseRegisterInfo &ARI =
4081 *static_cast<const ARMBaseRegisterInfo*>(RegInfo);
4082 MachineFunction &MF = DAG.getMachineFunction();
4083 MachineFrameInfo *MFI = MF.getFrameInfo();
4084 MFI->setFrameAddressIsTaken(true);
4086 EVT VT = Op.getValueType();
4087 SDLoc dl(Op); // FIXME probably not meaningful
4088 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4089 unsigned FrameReg = ARI.getFrameRegister(MF);
4090 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
4092 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
4093 MachinePointerInfo(),
4094 false, false, false, 0);
4098 // FIXME? Maybe this could be a TableGen attribute on some registers and
4099 // this table could be generated automatically from RegInfo.
4100 unsigned ARMTargetLowering::getRegisterByName(const char* RegName,
4102 unsigned Reg = StringSwitch<unsigned>(RegName)
4103 .Case("sp", ARM::SP)
4107 report_fatal_error(Twine("Invalid register name \""
4108 + StringRef(RegName) + "\"."));
4111 // Result is 64 bit value so split into two 32 bit values and return as a
4113 static void ExpandREAD_REGISTER(SDNode *N, SmallVectorImpl<SDValue> &Results,
4114 SelectionDAG &DAG) {
4117 // This function is only supposed to be called for i64 type destination.
4118 assert(N->getValueType(0) == MVT::i64
4119 && "ExpandREAD_REGISTER called for non-i64 type result.");
4121 SDValue Read = DAG.getNode(ISD::READ_REGISTER, DL,
4122 DAG.getVTList(MVT::i32, MVT::i32, MVT::Other),
4126 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Read.getValue(0),
4128 Results.push_back(Read.getOperand(0));
4131 /// ExpandBITCAST - If the target supports VFP, this function is called to
4132 /// expand a bit convert where either the source or destination type is i64 to
4133 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
4134 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
4135 /// vectors), since the legalizer won't know what to do with that.
4136 static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) {
4137 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4139 SDValue Op = N->getOperand(0);
4141 // This function is only supposed to be called for i64 types, either as the
4142 // source or destination of the bit convert.
4143 EVT SrcVT = Op.getValueType();
4144 EVT DstVT = N->getValueType(0);
4145 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
4146 "ExpandBITCAST called for non-i64 type");
4148 // Turn i64->f64 into VMOVDRR.
4149 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
4150 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
4151 DAG.getConstant(0, dl, MVT::i32));
4152 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
4153 DAG.getConstant(1, dl, MVT::i32));
4154 return DAG.getNode(ISD::BITCAST, dl, DstVT,
4155 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
4158 // Turn f64->i64 into VMOVRRD.
4159 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
4161 if (TLI.isBigEndian() && SrcVT.isVector() &&
4162 SrcVT.getVectorNumElements() > 1)
4163 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
4164 DAG.getVTList(MVT::i32, MVT::i32),
4165 DAG.getNode(ARMISD::VREV64, dl, SrcVT, Op));
4167 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
4168 DAG.getVTList(MVT::i32, MVT::i32), Op);
4169 // Merge the pieces into a single i64 value.
4170 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
4176 /// getZeroVector - Returns a vector of specified type with all zero elements.
4177 /// Zero vectors are used to represent vector negation and in those cases
4178 /// will be implemented with the NEON VNEG instruction. However, VNEG does
4179 /// not support i64 elements, so sometimes the zero vectors will need to be
4180 /// explicitly constructed. Regardless, use a canonical VMOV to create the
4182 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, SDLoc dl) {
4183 assert(VT.isVector() && "Expected a vector type");
4184 // The canonical modified immediate encoding of a zero vector is....0!
4185 SDValue EncodedVal = DAG.getTargetConstant(0, dl, MVT::i32);
4186 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
4187 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
4188 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
4191 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
4192 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
4193 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
4194 SelectionDAG &DAG) const {
4195 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4196 EVT VT = Op.getValueType();
4197 unsigned VTBits = VT.getSizeInBits();
4199 SDValue ShOpLo = Op.getOperand(0);
4200 SDValue ShOpHi = Op.getOperand(1);
4201 SDValue ShAmt = Op.getOperand(2);
4203 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
4205 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
4207 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
4208 DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
4209 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
4210 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
4211 DAG.getConstant(VTBits, dl, MVT::i32));
4212 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
4213 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4214 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
4216 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4217 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
4218 ISD::SETGE, ARMcc, DAG, dl);
4219 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
4220 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
4223 SDValue Ops[2] = { Lo, Hi };
4224 return DAG.getMergeValues(Ops, dl);
4227 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
4228 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
4229 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
4230 SelectionDAG &DAG) const {
4231 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4232 EVT VT = Op.getValueType();
4233 unsigned VTBits = VT.getSizeInBits();
4235 SDValue ShOpLo = Op.getOperand(0);
4236 SDValue ShOpHi = Op.getOperand(1);
4237 SDValue ShAmt = Op.getOperand(2);
4240 assert(Op.getOpcode() == ISD::SHL_PARTS);
4241 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
4242 DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
4243 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
4244 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
4245 DAG.getConstant(VTBits, dl, MVT::i32));
4246 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
4247 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
4249 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4250 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4251 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
4252 ISD::SETGE, ARMcc, DAG, dl);
4253 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
4254 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
4257 SDValue Ops[2] = { Lo, Hi };
4258 return DAG.getMergeValues(Ops, dl);
4261 SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
4262 SelectionDAG &DAG) const {
4263 // The rounding mode is in bits 23:22 of the FPSCR.
4264 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
4265 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
4266 // so that the shift + and get folded into a bitfield extract.
4268 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
4269 DAG.getConstant(Intrinsic::arm_get_fpscr, dl,
4271 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
4272 DAG.getConstant(1U << 22, dl, MVT::i32));
4273 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
4274 DAG.getConstant(22, dl, MVT::i32));
4275 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
4276 DAG.getConstant(3, dl, MVT::i32));
4279 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
4280 const ARMSubtarget *ST) {
4281 EVT VT = N->getValueType(0);
4284 if (!ST->hasV6T2Ops())
4287 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
4288 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
4291 /// getCTPOP16BitCounts - Returns a v8i8/v16i8 vector containing the bit-count
4292 /// for each 16-bit element from operand, repeated. The basic idea is to
4293 /// leverage vcnt to get the 8-bit counts, gather and add the results.
4295 /// Trace for v4i16:
4296 /// input = [v0 v1 v2 v3 ] (vi 16-bit element)
4297 /// cast: N0 = [w0 w1 w2 w3 w4 w5 w6 w7] (v0 = [w0 w1], wi 8-bit element)
4298 /// vcnt: N1 = [b0 b1 b2 b3 b4 b5 b6 b7] (bi = bit-count of 8-bit element wi)
4299 /// vrev: N2 = [b1 b0 b3 b2 b5 b4 b7 b6]
4300 /// [b0 b1 b2 b3 b4 b5 b6 b7]
4301 /// +[b1 b0 b3 b2 b5 b4 b7 b6]
4302 /// N3=N1+N2 = [k0 k0 k1 k1 k2 k2 k3 k3] (k0 = b0+b1 = bit-count of 16-bit v0,
4303 /// vuzp: = [k0 k1 k2 k3 k0 k1 k2 k3] each ki is 8-bits)
4304 static SDValue getCTPOP16BitCounts(SDNode *N, SelectionDAG &DAG) {
4305 EVT VT = N->getValueType(0);
4308 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8;
4309 SDValue N0 = DAG.getNode(ISD::BITCAST, DL, VT8Bit, N->getOperand(0));
4310 SDValue N1 = DAG.getNode(ISD::CTPOP, DL, VT8Bit, N0);
4311 SDValue N2 = DAG.getNode(ARMISD::VREV16, DL, VT8Bit, N1);
4312 SDValue N3 = DAG.getNode(ISD::ADD, DL, VT8Bit, N1, N2);
4313 return DAG.getNode(ARMISD::VUZP, DL, VT8Bit, N3, N3);
4316 /// lowerCTPOP16BitElements - Returns a v4i16/v8i16 vector containing the
4317 /// bit-count for each 16-bit element from the operand. We need slightly
4318 /// different sequencing for v4i16 and v8i16 to stay within NEON's available
4319 /// 64/128-bit registers.
4321 /// Trace for v4i16:
4322 /// input = [v0 v1 v2 v3 ] (vi 16-bit element)
4323 /// v8i8: BitCounts = [k0 k1 k2 k3 k0 k1 k2 k3 ] (ki is the bit-count of vi)
4324 /// v8i16:Extended = [k0 k1 k2 k3 k0 k1 k2 k3 ]
4325 /// v4i16:Extracted = [k0 k1 k2 k3 ]
4326 static SDValue lowerCTPOP16BitElements(SDNode *N, SelectionDAG &DAG) {
4327 EVT VT = N->getValueType(0);
4330 SDValue BitCounts = getCTPOP16BitCounts(N, DAG);
4331 if (VT.is64BitVector()) {
4332 SDValue Extended = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v8i16, BitCounts);
4333 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, Extended,
4334 DAG.getIntPtrConstant(0, DL));
4336 SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v8i8,
4337 BitCounts, DAG.getIntPtrConstant(0, DL));
4338 return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v8i16, Extracted);
4342 /// lowerCTPOP32BitElements - Returns a v2i32/v4i32 vector containing the
4343 /// bit-count for each 32-bit element from the operand. The idea here is
4344 /// to split the vector into 16-bit elements, leverage the 16-bit count
4345 /// routine, and then combine the results.
4347 /// Trace for v2i32 (v4i32 similar with Extracted/Extended exchanged):
4348 /// input = [v0 v1 ] (vi: 32-bit elements)
4349 /// Bitcast = [w0 w1 w2 w3 ] (wi: 16-bit elements, v0 = [w0 w1])
4350 /// Counts16 = [k0 k1 k2 k3 ] (ki: 16-bit elements, bit-count of wi)
4351 /// vrev: N0 = [k1 k0 k3 k2 ]
4353 /// N1 =+[k1 k0 k3 k2 ]
4355 /// N2 =+[k1 k3 k0 k2 ]
4357 /// Extended =+[k1 k3 k0 k2 ]
4359 /// Extracted=+[k1 k3 ]
4361 static SDValue lowerCTPOP32BitElements(SDNode *N, SelectionDAG &DAG) {
4362 EVT VT = N->getValueType(0);
4365 EVT VT16Bit = VT.is64BitVector() ? MVT::v4i16 : MVT::v8i16;
4367 SDValue Bitcast = DAG.getNode(ISD::BITCAST, DL, VT16Bit, N->getOperand(0));
4368 SDValue Counts16 = lowerCTPOP16BitElements(Bitcast.getNode(), DAG);
4369 SDValue N0 = DAG.getNode(ARMISD::VREV32, DL, VT16Bit, Counts16);
4370 SDValue N1 = DAG.getNode(ISD::ADD, DL, VT16Bit, Counts16, N0);
4371 SDValue N2 = DAG.getNode(ARMISD::VUZP, DL, VT16Bit, N1, N1);
4373 if (VT.is64BitVector()) {
4374 SDValue Extended = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v4i32, N2);
4375 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i32, Extended,
4376 DAG.getIntPtrConstant(0, DL));
4378 SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, N2,
4379 DAG.getIntPtrConstant(0, DL));
4380 return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v4i32, Extracted);
4384 static SDValue LowerCTPOP(SDNode *N, SelectionDAG &DAG,
4385 const ARMSubtarget *ST) {
4386 EVT VT = N->getValueType(0);
4388 assert(ST->hasNEON() && "Custom ctpop lowering requires NEON.");
4389 assert((VT == MVT::v2i32 || VT == MVT::v4i32 ||
4390 VT == MVT::v4i16 || VT == MVT::v8i16) &&
4391 "Unexpected type for custom ctpop lowering");
4393 if (VT.getVectorElementType() == MVT::i32)
4394 return lowerCTPOP32BitElements(N, DAG);
4396 return lowerCTPOP16BitElements(N, DAG);
4399 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
4400 const ARMSubtarget *ST) {
4401 EVT VT = N->getValueType(0);
4407 // Lower vector shifts on NEON to use VSHL.
4408 assert(ST->hasNEON() && "unexpected vector shift");
4410 // Left shifts translate directly to the vshiftu intrinsic.
4411 if (N->getOpcode() == ISD::SHL)
4412 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
4413 DAG.getConstant(Intrinsic::arm_neon_vshiftu, dl,
4415 N->getOperand(0), N->getOperand(1));
4417 assert((N->getOpcode() == ISD::SRA ||
4418 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
4420 // NEON uses the same intrinsics for both left and right shifts. For
4421 // right shifts, the shift amounts are negative, so negate the vector of
4423 EVT ShiftVT = N->getOperand(1).getValueType();
4424 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
4425 getZeroVector(ShiftVT, DAG, dl),
4427 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
4428 Intrinsic::arm_neon_vshifts :
4429 Intrinsic::arm_neon_vshiftu);
4430 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
4431 DAG.getConstant(vshiftInt, dl, MVT::i32),
4432 N->getOperand(0), NegatedCount);
4435 static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
4436 const ARMSubtarget *ST) {
4437 EVT VT = N->getValueType(0);
4440 // We can get here for a node like i32 = ISD::SHL i32, i64
4444 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
4445 "Unknown shift to lower!");
4447 // We only lower SRA, SRL of 1 here, all others use generic lowering.
4448 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
4449 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
4452 // If we are in thumb mode, we don't have RRX.
4453 if (ST->isThumb1Only()) return SDValue();
4455 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
4456 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
4457 DAG.getConstant(0, dl, MVT::i32));
4458 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
4459 DAG.getConstant(1, dl, MVT::i32));
4461 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
4462 // captures the result into a carry flag.
4463 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
4464 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), Hi);
4466 // The low part is an ARMISD::RRX operand, which shifts the carry in.
4467 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
4469 // Merge the pieces into a single i64 value.
4470 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
4473 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
4474 SDValue TmpOp0, TmpOp1;
4475 bool Invert = false;
4479 SDValue Op0 = Op.getOperand(0);
4480 SDValue Op1 = Op.getOperand(1);
4481 SDValue CC = Op.getOperand(2);
4482 EVT CmpVT = Op0.getValueType().changeVectorElementTypeToInteger();
4483 EVT VT = Op.getValueType();
4484 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
4487 if (Op1.getValueType().isFloatingPoint()) {
4488 switch (SetCCOpcode) {
4489 default: llvm_unreachable("Illegal FP comparison");
4491 case ISD::SETNE: Invert = true; // Fallthrough
4493 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
4495 case ISD::SETLT: Swap = true; // Fallthrough
4497 case ISD::SETGT: Opc = ARMISD::VCGT; break;
4499 case ISD::SETLE: Swap = true; // Fallthrough
4501 case ISD::SETGE: Opc = ARMISD::VCGE; break;
4502 case ISD::SETUGE: Swap = true; // Fallthrough
4503 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
4504 case ISD::SETUGT: Swap = true; // Fallthrough
4505 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
4506 case ISD::SETUEQ: Invert = true; // Fallthrough
4508 // Expand this to (OLT | OGT).
4512 Op0 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp1, TmpOp0);
4513 Op1 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp0, TmpOp1);
4515 case ISD::SETUO: Invert = true; // Fallthrough
4517 // Expand this to (OLT | OGE).
4521 Op0 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp1, TmpOp0);
4522 Op1 = DAG.getNode(ARMISD::VCGE, dl, CmpVT, TmpOp0, TmpOp1);
4526 // Integer comparisons.
4527 switch (SetCCOpcode) {
4528 default: llvm_unreachable("Illegal integer comparison");
4529 case ISD::SETNE: Invert = true;
4530 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
4531 case ISD::SETLT: Swap = true;
4532 case ISD::SETGT: Opc = ARMISD::VCGT; break;
4533 case ISD::SETLE: Swap = true;
4534 case ISD::SETGE: Opc = ARMISD::VCGE; break;
4535 case ISD::SETULT: Swap = true;
4536 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
4537 case ISD::SETULE: Swap = true;
4538 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
4541 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
4542 if (Opc == ARMISD::VCEQ) {
4545 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
4547 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
4550 // Ignore bitconvert.
4551 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST)
4552 AndOp = AndOp.getOperand(0);
4554 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
4556 Op0 = DAG.getNode(ISD::BITCAST, dl, CmpVT, AndOp.getOperand(0));
4557 Op1 = DAG.getNode(ISD::BITCAST, dl, CmpVT, AndOp.getOperand(1));
4564 std::swap(Op0, Op1);
4566 // If one of the operands is a constant vector zero, attempt to fold the
4567 // comparison to a specialized compare-against-zero form.
4569 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
4571 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) {
4572 if (Opc == ARMISD::VCGE)
4573 Opc = ARMISD::VCLEZ;
4574 else if (Opc == ARMISD::VCGT)
4575 Opc = ARMISD::VCLTZ;
4580 if (SingleOp.getNode()) {
4583 Result = DAG.getNode(ARMISD::VCEQZ, dl, CmpVT, SingleOp); break;
4585 Result = DAG.getNode(ARMISD::VCGEZ, dl, CmpVT, SingleOp); break;
4587 Result = DAG.getNode(ARMISD::VCLEZ, dl, CmpVT, SingleOp); break;
4589 Result = DAG.getNode(ARMISD::VCGTZ, dl, CmpVT, SingleOp); break;
4591 Result = DAG.getNode(ARMISD::VCLTZ, dl, CmpVT, SingleOp); break;
4593 Result = DAG.getNode(Opc, dl, CmpVT, Op0, Op1);
4596 Result = DAG.getNode(Opc, dl, CmpVT, Op0, Op1);
4599 Result = DAG.getSExtOrTrunc(Result, dl, VT);
4602 Result = DAG.getNOT(dl, Result, VT);
4607 /// isNEONModifiedImm - Check if the specified splat value corresponds to a
4608 /// valid vector constant for a NEON instruction with a "modified immediate"
4609 /// operand (e.g., VMOV). If so, return the encoded value.
4610 static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
4611 unsigned SplatBitSize, SelectionDAG &DAG,
4612 SDLoc dl, EVT &VT, bool is128Bits,
4613 NEONModImmType type) {
4614 unsigned OpCmode, Imm;
4616 // SplatBitSize is set to the smallest size that splats the vector, so a
4617 // zero vector will always have SplatBitSize == 8. However, NEON modified
4618 // immediate instructions others than VMOV do not support the 8-bit encoding
4619 // of a zero vector, and the default encoding of zero is supposed to be the
4624 switch (SplatBitSize) {
4626 if (type != VMOVModImm)
4628 // Any 1-byte value is OK. Op=0, Cmode=1110.
4629 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
4632 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
4636 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
4637 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
4638 if ((SplatBits & ~0xff) == 0) {
4639 // Value = 0x00nn: Op=x, Cmode=100x.
4644 if ((SplatBits & ~0xff00) == 0) {
4645 // Value = 0xnn00: Op=x, Cmode=101x.
4647 Imm = SplatBits >> 8;
4653 // NEON's 32-bit VMOV supports splat values where:
4654 // * only one byte is nonzero, or
4655 // * the least significant byte is 0xff and the second byte is nonzero, or
4656 // * the least significant 2 bytes are 0xff and the third is nonzero.
4657 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
4658 if ((SplatBits & ~0xff) == 0) {
4659 // Value = 0x000000nn: Op=x, Cmode=000x.
4664 if ((SplatBits & ~0xff00) == 0) {
4665 // Value = 0x0000nn00: Op=x, Cmode=001x.
4667 Imm = SplatBits >> 8;
4670 if ((SplatBits & ~0xff0000) == 0) {
4671 // Value = 0x00nn0000: Op=x, Cmode=010x.
4673 Imm = SplatBits >> 16;
4676 if ((SplatBits & ~0xff000000) == 0) {
4677 // Value = 0xnn000000: Op=x, Cmode=011x.
4679 Imm = SplatBits >> 24;
4683 // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC
4684 if (type == OtherModImm) return SDValue();
4686 if ((SplatBits & ~0xffff) == 0 &&
4687 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
4688 // Value = 0x0000nnff: Op=x, Cmode=1100.
4690 Imm = SplatBits >> 8;
4694 if ((SplatBits & ~0xffffff) == 0 &&
4695 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
4696 // Value = 0x00nnffff: Op=x, Cmode=1101.
4698 Imm = SplatBits >> 16;
4702 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
4703 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
4704 // VMOV.I32. A (very) minor optimization would be to replicate the value
4705 // and fall through here to test for a valid 64-bit splat. But, then the
4706 // caller would also need to check and handle the change in size.
4710 if (type != VMOVModImm)
4712 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
4713 uint64_t BitMask = 0xff;
4715 unsigned ImmMask = 1;
4717 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
4718 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
4721 } else if ((SplatBits & BitMask) != 0) {
4728 if (DAG.getTargetLoweringInfo().isBigEndian())
4729 // swap higher and lower 32 bit word
4730 Imm = ((Imm & 0xf) << 4) | ((Imm & 0xf0) >> 4);
4732 // Op=1, Cmode=1110.
4734 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
4739 llvm_unreachable("unexpected size for isNEONModifiedImm");
4742 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
4743 return DAG.getTargetConstant(EncodedVal, dl, MVT::i32);
4746 SDValue ARMTargetLowering::LowerConstantFP(SDValue Op, SelectionDAG &DAG,
4747 const ARMSubtarget *ST) const {
4751 bool IsDouble = Op.getValueType() == MVT::f64;
4752 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Op);
4754 // Use the default (constant pool) lowering for double constants when we have
4756 if (IsDouble && Subtarget->isFPOnlySP())
4759 // Try splatting with a VMOV.f32...
4760 APFloat FPVal = CFP->getValueAPF();
4761 int ImmVal = IsDouble ? ARM_AM::getFP64Imm(FPVal) : ARM_AM::getFP32Imm(FPVal);
4764 if (IsDouble || !ST->useNEONForSinglePrecisionFP()) {
4765 // We have code in place to select a valid ConstantFP already, no need to
4770 // It's a float and we are trying to use NEON operations where
4771 // possible. Lower it to a splat followed by an extract.
4773 SDValue NewVal = DAG.getTargetConstant(ImmVal, DL, MVT::i32);
4774 SDValue VecConstant = DAG.getNode(ARMISD::VMOVFPIMM, DL, MVT::v2f32,
4776 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecConstant,
4777 DAG.getConstant(0, DL, MVT::i32));
4780 // The rest of our options are NEON only, make sure that's allowed before
4782 if (!ST->hasNEON() || (!IsDouble && !ST->useNEONForSinglePrecisionFP()))
4786 uint64_t iVal = FPVal.bitcastToAPInt().getZExtValue();
4788 // It wouldn't really be worth bothering for doubles except for one very
4789 // important value, which does happen to match: 0.0. So make sure we don't do
4791 if (IsDouble && (iVal & 0xffffffff) != (iVal >> 32))
4794 // Try a VMOV.i32 (FIXME: i8, i16, or i64 could work too).
4795 SDValue NewVal = isNEONModifiedImm(iVal & 0xffffffffU, 0, 32, DAG, SDLoc(Op),
4796 VMovVT, false, VMOVModImm);
4797 if (NewVal != SDValue()) {
4799 SDValue VecConstant = DAG.getNode(ARMISD::VMOVIMM, DL, VMovVT,
4802 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant);
4804 // It's a float: cast and extract a vector element.
4805 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32,
4807 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant,
4808 DAG.getConstant(0, DL, MVT::i32));
4811 // Finally, try a VMVN.i32
4812 NewVal = isNEONModifiedImm(~iVal & 0xffffffffU, 0, 32, DAG, SDLoc(Op), VMovVT,
4814 if (NewVal != SDValue()) {
4816 SDValue VecConstant = DAG.getNode(ARMISD::VMVNIMM, DL, VMovVT, NewVal);
4819 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant);
4821 // It's a float: cast and extract a vector element.
4822 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32,
4824 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant,
4825 DAG.getConstant(0, DL, MVT::i32));
4831 // check if an VEXT instruction can handle the shuffle mask when the
4832 // vector sources of the shuffle are the same.
4833 static bool isSingletonVEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
4834 unsigned NumElts = VT.getVectorNumElements();
4836 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4842 // If this is a VEXT shuffle, the immediate value is the index of the first
4843 // element. The other shuffle indices must be the successive elements after
4845 unsigned ExpectedElt = Imm;
4846 for (unsigned i = 1; i < NumElts; ++i) {
4847 // Increment the expected index. If it wraps around, just follow it
4848 // back to index zero and keep going.
4850 if (ExpectedElt == NumElts)
4853 if (M[i] < 0) continue; // ignore UNDEF indices
4854 if (ExpectedElt != static_cast<unsigned>(M[i]))
4862 static bool isVEXTMask(ArrayRef<int> M, EVT VT,
4863 bool &ReverseVEXT, unsigned &Imm) {
4864 unsigned NumElts = VT.getVectorNumElements();
4865 ReverseVEXT = false;
4867 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4873 // If this is a VEXT shuffle, the immediate value is the index of the first
4874 // element. The other shuffle indices must be the successive elements after
4876 unsigned ExpectedElt = Imm;
4877 for (unsigned i = 1; i < NumElts; ++i) {
4878 // Increment the expected index. If it wraps around, it may still be
4879 // a VEXT but the source vectors must be swapped.
4881 if (ExpectedElt == NumElts * 2) {
4886 if (M[i] < 0) continue; // ignore UNDEF indices
4887 if (ExpectedElt != static_cast<unsigned>(M[i]))
4891 // Adjust the index value if the source operands will be swapped.
4898 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
4899 /// instruction with the specified blocksize. (The order of the elements
4900 /// within each block of the vector is reversed.)
4901 static bool isVREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
4902 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
4903 "Only possible block sizes for VREV are: 16, 32, 64");
4905 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4909 unsigned NumElts = VT.getVectorNumElements();
4910 unsigned BlockElts = M[0] + 1;
4911 // If the first shuffle index is UNDEF, be optimistic.
4913 BlockElts = BlockSize / EltSz;
4915 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
4918 for (unsigned i = 0; i < NumElts; ++i) {
4919 if (M[i] < 0) continue; // ignore UNDEF indices
4920 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
4927 static bool isVTBLMask(ArrayRef<int> M, EVT VT) {
4928 // We can handle <8 x i8> vector shuffles. If the index in the mask is out of
4929 // range, then 0 is placed into the resulting vector. So pretty much any mask
4930 // of 8 elements can work here.
4931 return VT == MVT::v8i8 && M.size() == 8;
4934 static bool isVTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4935 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4939 unsigned NumElts = VT.getVectorNumElements();
4940 WhichResult = (M[0] == 0 ? 0 : 1);
4941 for (unsigned i = 0; i < NumElts; i += 2) {
4942 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
4943 (M[i+1] >= 0 && (unsigned) M[i+1] != i + NumElts + WhichResult))
4949 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
4950 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4951 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
4952 static bool isVTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
4953 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4957 unsigned NumElts = VT.getVectorNumElements();
4958 WhichResult = (M[0] == 0 ? 0 : 1);
4959 for (unsigned i = 0; i < NumElts; i += 2) {
4960 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
4961 (M[i+1] >= 0 && (unsigned) M[i+1] != i + WhichResult))
4967 static bool isVUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4968 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4972 unsigned NumElts = VT.getVectorNumElements();
4973 WhichResult = (M[0] == 0 ? 0 : 1);
4974 for (unsigned i = 0; i != NumElts; ++i) {
4975 if (M[i] < 0) continue; // ignore UNDEF indices
4976 if ((unsigned) M[i] != 2 * i + WhichResult)
4980 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
4981 if (VT.is64BitVector() && EltSz == 32)
4987 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
4988 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4989 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
4990 static bool isVUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
4991 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4995 unsigned Half = VT.getVectorNumElements() / 2;
4996 WhichResult = (M[0] == 0 ? 0 : 1);
4997 for (unsigned j = 0; j != 2; ++j) {
4998 unsigned Idx = WhichResult;
4999 for (unsigned i = 0; i != Half; ++i) {
5000 int MIdx = M[i + j * Half];
5001 if (MIdx >= 0 && (unsigned) MIdx != Idx)
5007 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
5008 if (VT.is64BitVector() && EltSz == 32)
5014 static bool isVZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5015 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
5019 unsigned NumElts = VT.getVectorNumElements();
5020 WhichResult = (M[0] == 0 ? 0 : 1);
5021 unsigned Idx = WhichResult * NumElts / 2;
5022 for (unsigned i = 0; i != NumElts; i += 2) {
5023 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
5024 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts))
5029 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
5030 if (VT.is64BitVector() && EltSz == 32)
5036 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
5037 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
5038 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
5039 static bool isVZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
5040 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
5044 unsigned NumElts = VT.getVectorNumElements();
5045 WhichResult = (M[0] == 0 ? 0 : 1);
5046 unsigned Idx = WhichResult * NumElts / 2;
5047 for (unsigned i = 0; i != NumElts; i += 2) {
5048 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
5049 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx))
5054 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
5055 if (VT.is64BitVector() && EltSz == 32)
5061 /// \return true if this is a reverse operation on an vector.
5062 static bool isReverseMask(ArrayRef<int> M, EVT VT) {
5063 unsigned NumElts = VT.getVectorNumElements();
5064 // Make sure the mask has the right size.
5065 if (NumElts != M.size())
5068 // Look for <15, ..., 3, -1, 1, 0>.
5069 for (unsigned i = 0; i != NumElts; ++i)
5070 if (M[i] >= 0 && M[i] != (int) (NumElts - 1 - i))
5076 // If N is an integer constant that can be moved into a register in one
5077 // instruction, return an SDValue of such a constant (will become a MOV
5078 // instruction). Otherwise return null.
5079 static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG,
5080 const ARMSubtarget *ST, SDLoc dl) {
5082 if (!isa<ConstantSDNode>(N))
5084 Val = cast<ConstantSDNode>(N)->getZExtValue();
5086 if (ST->isThumb1Only()) {
5087 if (Val <= 255 || ~Val <= 255)
5088 return DAG.getConstant(Val, dl, MVT::i32);
5090 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1)
5091 return DAG.getConstant(Val, dl, MVT::i32);
5096 // If this is a case we can't handle, return null and let the default
5097 // expansion code take care of it.
5098 SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
5099 const ARMSubtarget *ST) const {
5100 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
5102 EVT VT = Op.getValueType();
5104 APInt SplatBits, SplatUndef;
5105 unsigned SplatBitSize;
5107 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5108 if (SplatBitSize <= 64) {
5109 // Check if an immediate VMOV works.
5111 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
5112 SplatUndef.getZExtValue(), SplatBitSize,
5113 DAG, dl, VmovVT, VT.is128BitVector(),
5115 if (Val.getNode()) {
5116 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
5117 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
5120 // Try an immediate VMVN.
5121 uint64_t NegatedImm = (~SplatBits).getZExtValue();
5122 Val = isNEONModifiedImm(NegatedImm,
5123 SplatUndef.getZExtValue(), SplatBitSize,
5124 DAG, dl, VmovVT, VT.is128BitVector(),
5126 if (Val.getNode()) {
5127 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
5128 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
5131 // Use vmov.f32 to materialize other v2f32 and v4f32 splats.
5132 if ((VT == MVT::v2f32 || VT == MVT::v4f32) && SplatBitSize == 32) {
5133 int ImmVal = ARM_AM::getFP32Imm(SplatBits);
5135 SDValue Val = DAG.getTargetConstant(ImmVal, dl, MVT::i32);
5136 return DAG.getNode(ARMISD::VMOVFPIMM, dl, VT, Val);
5142 // Scan through the operands to see if only one value is used.
5144 // As an optimisation, even if more than one value is used it may be more
5145 // profitable to splat with one value then change some lanes.
5147 // Heuristically we decide to do this if the vector has a "dominant" value,
5148 // defined as splatted to more than half of the lanes.
5149 unsigned NumElts = VT.getVectorNumElements();
5150 bool isOnlyLowElement = true;
5151 bool usesOnlyOneValue = true;
5152 bool hasDominantValue = false;
5153 bool isConstant = true;
5155 // Map of the number of times a particular SDValue appears in the
5157 DenseMap<SDValue, unsigned> ValueCounts;
5159 for (unsigned i = 0; i < NumElts; ++i) {
5160 SDValue V = Op.getOperand(i);
5161 if (V.getOpcode() == ISD::UNDEF)
5164 isOnlyLowElement = false;
5165 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
5168 ValueCounts.insert(std::make_pair(V, 0));
5169 unsigned &Count = ValueCounts[V];
5171 // Is this value dominant? (takes up more than half of the lanes)
5172 if (++Count > (NumElts / 2)) {
5173 hasDominantValue = true;
5177 if (ValueCounts.size() != 1)
5178 usesOnlyOneValue = false;
5179 if (!Value.getNode() && ValueCounts.size() > 0)
5180 Value = ValueCounts.begin()->first;
5182 if (ValueCounts.size() == 0)
5183 return DAG.getUNDEF(VT);
5185 // Loads are better lowered with insert_vector_elt/ARMISD::BUILD_VECTOR.
5186 // Keep going if we are hitting this case.
5187 if (isOnlyLowElement && !ISD::isNormalLoad(Value.getNode()))
5188 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
5190 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5192 // Use VDUP for non-constant splats. For f32 constant splats, reduce to
5193 // i32 and try again.
5194 if (hasDominantValue && EltSize <= 32) {
5198 // If we are VDUPing a value that comes directly from a vector, that will
5199 // cause an unnecessary move to and from a GPR, where instead we could
5200 // just use VDUPLANE. We can only do this if the lane being extracted
5201 // is at a constant index, as the VDUP from lane instructions only have
5202 // constant-index forms.
5203 if (Value->getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5204 isa<ConstantSDNode>(Value->getOperand(1))) {
5205 // We need to create a new undef vector to use for the VDUPLANE if the
5206 // size of the vector from which we get the value is different than the
5207 // size of the vector that we need to create. We will insert the element
5208 // such that the register coalescer will remove unnecessary copies.
5209 if (VT != Value->getOperand(0).getValueType()) {
5210 ConstantSDNode *constIndex;
5211 constIndex = dyn_cast<ConstantSDNode>(Value->getOperand(1));
5212 assert(constIndex && "The index is not a constant!");
5213 unsigned index = constIndex->getAPIntValue().getLimitedValue() %
5214 VT.getVectorNumElements();
5215 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT,
5216 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DAG.getUNDEF(VT),
5217 Value, DAG.getConstant(index, dl, MVT::i32)),
5218 DAG.getConstant(index, dl, MVT::i32));
5220 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT,
5221 Value->getOperand(0), Value->getOperand(1));
5223 N = DAG.getNode(ARMISD::VDUP, dl, VT, Value);
5225 if (!usesOnlyOneValue) {
5226 // The dominant value was splatted as 'N', but we now have to insert
5227 // all differing elements.
5228 for (unsigned I = 0; I < NumElts; ++I) {
5229 if (Op.getOperand(I) == Value)
5231 SmallVector<SDValue, 3> Ops;
5233 Ops.push_back(Op.getOperand(I));
5234 Ops.push_back(DAG.getConstant(I, dl, MVT::i32));
5235 N = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Ops);
5240 if (VT.getVectorElementType().isFloatingPoint()) {
5241 SmallVector<SDValue, 8> Ops;
5242 for (unsigned i = 0; i < NumElts; ++i)
5243 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32,
5245 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
5246 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
5247 Val = LowerBUILD_VECTOR(Val, DAG, ST);
5249 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5251 if (usesOnlyOneValue) {
5252 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
5253 if (isConstant && Val.getNode())
5254 return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
5258 // If all elements are constants and the case above didn't get hit, fall back
5259 // to the default expansion, which will generate a load from the constant
5264 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
5266 SDValue shuffle = ReconstructShuffle(Op, DAG);
5267 if (shuffle != SDValue())
5271 // Vectors with 32- or 64-bit elements can be built by directly assigning
5272 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
5273 // will be legalized.
5274 if (EltSize >= 32) {
5275 // Do the expansion with floating-point types, since that is what the VFP
5276 // registers are defined to use, and since i64 is not legal.
5277 EVT EltVT = EVT::getFloatingPointVT(EltSize);
5278 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
5279 SmallVector<SDValue, 8> Ops;
5280 for (unsigned i = 0; i < NumElts; ++i)
5281 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i)));
5282 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops);
5283 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5286 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
5287 // know the default expansion would otherwise fall back on something even
5288 // worse. For a vector with one or two non-undef values, that's
5289 // scalar_to_vector for the elements followed by a shuffle (provided the
5290 // shuffle is valid for the target) and materialization element by element
5291 // on the stack followed by a load for everything else.
5292 if (!isConstant && !usesOnlyOneValue) {
5293 SDValue Vec = DAG.getUNDEF(VT);
5294 for (unsigned i = 0 ; i < NumElts; ++i) {
5295 SDValue V = Op.getOperand(i);
5296 if (V.getOpcode() == ISD::UNDEF)
5298 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i32);
5299 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
5307 // Gather data to see if the operation can be modelled as a
5308 // shuffle in combination with VEXTs.
5309 SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
5310 SelectionDAG &DAG) const {
5312 EVT VT = Op.getValueType();
5313 unsigned NumElts = VT.getVectorNumElements();
5315 SmallVector<SDValue, 2> SourceVecs;
5316 SmallVector<unsigned, 2> MinElts;
5317 SmallVector<unsigned, 2> MaxElts;
5319 for (unsigned i = 0; i < NumElts; ++i) {
5320 SDValue V = Op.getOperand(i);
5321 if (V.getOpcode() == ISD::UNDEF)
5323 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
5324 // A shuffle can only come from building a vector from various
5325 // elements of other vectors.
5327 } else if (V.getOperand(0).getValueType().getVectorElementType() !=
5328 VT.getVectorElementType()) {
5329 // This code doesn't know how to handle shuffles where the vector
5330 // element types do not match (this happens because type legalization
5331 // promotes the return type of EXTRACT_VECTOR_ELT).
5332 // FIXME: It might be appropriate to extend this code to handle
5333 // mismatched types.
5337 // Record this extraction against the appropriate vector if possible...
5338 SDValue SourceVec = V.getOperand(0);
5339 // If the element number isn't a constant, we can't effectively
5340 // analyze what's going on.
5341 if (!isa<ConstantSDNode>(V.getOperand(1)))
5343 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
5344 bool FoundSource = false;
5345 for (unsigned j = 0; j < SourceVecs.size(); ++j) {
5346 if (SourceVecs[j] == SourceVec) {
5347 if (MinElts[j] > EltNo)
5349 if (MaxElts[j] < EltNo)
5356 // Or record a new source if not...
5358 SourceVecs.push_back(SourceVec);
5359 MinElts.push_back(EltNo);
5360 MaxElts.push_back(EltNo);
5364 // Currently only do something sane when at most two source vectors
5366 if (SourceVecs.size() > 2)
5369 SDValue ShuffleSrcs[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT) };
5370 int VEXTOffsets[2] = {0, 0};
5372 // This loop extracts the usage patterns of the source vectors
5373 // and prepares appropriate SDValues for a shuffle if possible.
5374 for (unsigned i = 0; i < SourceVecs.size(); ++i) {
5375 if (SourceVecs[i].getValueType() == VT) {
5376 // No VEXT necessary
5377 ShuffleSrcs[i] = SourceVecs[i];
5380 } else if (SourceVecs[i].getValueType().getVectorNumElements() < NumElts) {
5381 // It probably isn't worth padding out a smaller vector just to
5382 // break it down again in a shuffle.
5386 // Since only 64-bit and 128-bit vectors are legal on ARM and
5387 // we've eliminated the other cases...
5388 assert(SourceVecs[i].getValueType().getVectorNumElements() == 2*NumElts &&
5389 "unexpected vector sizes in ReconstructShuffle");
5391 if (MaxElts[i] - MinElts[i] >= NumElts) {
5392 // Span too large for a VEXT to cope
5396 if (MinElts[i] >= NumElts) {
5397 // The extraction can just take the second half
5398 VEXTOffsets[i] = NumElts;
5399 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
5401 DAG.getIntPtrConstant(NumElts, dl));
5402 } else if (MaxElts[i] < NumElts) {
5403 // The extraction can just take the first half
5405 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
5407 DAG.getIntPtrConstant(0, dl));
5409 // An actual VEXT is needed
5410 VEXTOffsets[i] = MinElts[i];
5411 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
5413 DAG.getIntPtrConstant(0, dl));
5414 SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
5416 DAG.getIntPtrConstant(NumElts, dl));
5417 ShuffleSrcs[i] = DAG.getNode(ARMISD::VEXT, dl, VT, VEXTSrc1, VEXTSrc2,
5418 DAG.getConstant(VEXTOffsets[i], dl,
5423 SmallVector<int, 8> Mask;
5425 for (unsigned i = 0; i < NumElts; ++i) {
5426 SDValue Entry = Op.getOperand(i);
5427 if (Entry.getOpcode() == ISD::UNDEF) {
5432 SDValue ExtractVec = Entry.getOperand(0);
5433 int ExtractElt = cast<ConstantSDNode>(Op.getOperand(i)
5434 .getOperand(1))->getSExtValue();
5435 if (ExtractVec == SourceVecs[0]) {
5436 Mask.push_back(ExtractElt - VEXTOffsets[0]);
5438 Mask.push_back(ExtractElt + NumElts - VEXTOffsets[1]);
5442 // Final check before we try to produce nonsense...
5443 if (isShuffleMaskLegal(Mask, VT))
5444 return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1],
5450 /// isShuffleMaskLegal - Targets can use this to indicate that they only
5451 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
5452 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
5453 /// are assumed to be legal.
5455 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
5457 if (VT.getVectorNumElements() == 4 &&
5458 (VT.is128BitVector() || VT.is64BitVector())) {
5459 unsigned PFIndexes[4];
5460 for (unsigned i = 0; i != 4; ++i) {
5464 PFIndexes[i] = M[i];
5467 // Compute the index in the perfect shuffle table.
5468 unsigned PFTableIndex =
5469 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5470 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5471 unsigned Cost = (PFEntry >> 30);
5478 unsigned Imm, WhichResult;
5480 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5481 return (EltSize >= 32 ||
5482 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
5483 isVREVMask(M, VT, 64) ||
5484 isVREVMask(M, VT, 32) ||
5485 isVREVMask(M, VT, 16) ||
5486 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
5487 isVTBLMask(M, VT) ||
5488 isVTRNMask(M, VT, WhichResult) ||
5489 isVUZPMask(M, VT, WhichResult) ||
5490 isVZIPMask(M, VT, WhichResult) ||
5491 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
5492 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
5493 isVZIP_v_undef_Mask(M, VT, WhichResult) ||
5494 ((VT == MVT::v8i16 || VT == MVT::v16i8) && isReverseMask(M, VT)));
5497 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5498 /// the specified operations to build the shuffle.
5499 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5500 SDValue RHS, SelectionDAG &DAG,
5502 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5503 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5504 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5507 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5516 OP_VUZPL, // VUZP, left result
5517 OP_VUZPR, // VUZP, right result
5518 OP_VZIPL, // VZIP, left result
5519 OP_VZIPR, // VZIP, right result
5520 OP_VTRNL, // VTRN, left result
5521 OP_VTRNR // VTRN, right result
5524 if (OpNum == OP_COPY) {
5525 if (LHSID == (1*9+2)*9+3) return LHS;
5526 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5530 SDValue OpLHS, OpRHS;
5531 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5532 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5533 EVT VT = OpLHS.getValueType();
5536 default: llvm_unreachable("Unknown shuffle opcode!");
5538 // VREV divides the vector in half and swaps within the half.
5539 if (VT.getVectorElementType() == MVT::i32 ||
5540 VT.getVectorElementType() == MVT::f32)
5541 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
5542 // vrev <4 x i16> -> VREV32
5543 if (VT.getVectorElementType() == MVT::i16)
5544 return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS);
5545 // vrev <4 x i8> -> VREV16
5546 assert(VT.getVectorElementType() == MVT::i8);
5547 return DAG.getNode(ARMISD::VREV16, dl, VT, OpLHS);
5552 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
5553 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, dl, MVT::i32));
5557 return DAG.getNode(ARMISD::VEXT, dl, VT,
5559 DAG.getConstant(OpNum - OP_VEXT1 + 1, dl, MVT::i32));
5562 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
5563 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
5566 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
5567 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
5570 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
5571 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
5575 static SDValue LowerVECTOR_SHUFFLEv8i8(SDValue Op,
5576 ArrayRef<int> ShuffleMask,
5577 SelectionDAG &DAG) {
5578 // Check to see if we can use the VTBL instruction.
5579 SDValue V1 = Op.getOperand(0);
5580 SDValue V2 = Op.getOperand(1);
5583 SmallVector<SDValue, 8> VTBLMask;
5584 for (ArrayRef<int>::iterator
5585 I = ShuffleMask.begin(), E = ShuffleMask.end(); I != E; ++I)
5586 VTBLMask.push_back(DAG.getConstant(*I, DL, MVT::i32));
5588 if (V2.getNode()->getOpcode() == ISD::UNDEF)
5589 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1,
5590 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, VTBLMask));
5592 return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2,
5593 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, VTBLMask));
5596 static SDValue LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(SDValue Op,
5597 SelectionDAG &DAG) {
5599 SDValue OpLHS = Op.getOperand(0);
5600 EVT VT = OpLHS.getValueType();
5602 assert((VT == MVT::v8i16 || VT == MVT::v16i8) &&
5603 "Expect an v8i16/v16i8 type");
5604 OpLHS = DAG.getNode(ARMISD::VREV64, DL, VT, OpLHS);
5605 // For a v16i8 type: After the VREV, we have got <8, ...15, 8, ..., 0>. Now,
5606 // extract the first 8 bytes into the top double word and the last 8 bytes
5607 // into the bottom double word. The v8i16 case is similar.
5608 unsigned ExtractNum = (VT == MVT::v16i8) ? 8 : 4;
5609 return DAG.getNode(ARMISD::VEXT, DL, VT, OpLHS, OpLHS,
5610 DAG.getConstant(ExtractNum, DL, MVT::i32));
5613 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
5614 SDValue V1 = Op.getOperand(0);
5615 SDValue V2 = Op.getOperand(1);
5617 EVT VT = Op.getValueType();
5618 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
5620 // Convert shuffles that are directly supported on NEON to target-specific
5621 // DAG nodes, instead of keeping them as shuffles and matching them again
5622 // during code selection. This is more efficient and avoids the possibility
5623 // of inconsistencies between legalization and selection.
5624 // FIXME: floating-point vectors should be canonicalized to integer vectors
5625 // of the same time so that they get CSEd properly.
5626 ArrayRef<int> ShuffleMask = SVN->getMask();
5628 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5629 if (EltSize <= 32) {
5630 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
5631 int Lane = SVN->getSplatIndex();
5632 // If this is undef splat, generate it via "just" vdup, if possible.
5633 if (Lane == -1) Lane = 0;
5635 // Test if V1 is a SCALAR_TO_VECTOR.
5636 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5637 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
5639 // Test if V1 is a BUILD_VECTOR which is equivalent to a SCALAR_TO_VECTOR
5640 // (and probably will turn into a SCALAR_TO_VECTOR once legalization
5642 if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
5643 !isa<ConstantSDNode>(V1.getOperand(0))) {
5644 bool IsScalarToVector = true;
5645 for (unsigned i = 1, e = V1.getNumOperands(); i != e; ++i)
5646 if (V1.getOperand(i).getOpcode() != ISD::UNDEF) {
5647 IsScalarToVector = false;
5650 if (IsScalarToVector)
5651 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
5653 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
5654 DAG.getConstant(Lane, dl, MVT::i32));
5659 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
5662 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
5663 DAG.getConstant(Imm, dl, MVT::i32));
5666 if (isVREVMask(ShuffleMask, VT, 64))
5667 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
5668 if (isVREVMask(ShuffleMask, VT, 32))
5669 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
5670 if (isVREVMask(ShuffleMask, VT, 16))
5671 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
5673 if (V2->getOpcode() == ISD::UNDEF &&
5674 isSingletonVEXTMask(ShuffleMask, VT, Imm)) {
5675 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V1,
5676 DAG.getConstant(Imm, dl, MVT::i32));
5679 // Check for Neon shuffles that modify both input vectors in place.
5680 // If both results are used, i.e., if there are two shuffles with the same
5681 // source operands and with masks corresponding to both results of one of
5682 // these operations, DAG memoization will ensure that a single node is
5683 // used for both shuffles.
5684 unsigned WhichResult;
5685 if (isVTRNMask(ShuffleMask, VT, WhichResult))
5686 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
5687 V1, V2).getValue(WhichResult);
5688 if (isVUZPMask(ShuffleMask, VT, WhichResult))
5689 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
5690 V1, V2).getValue(WhichResult);
5691 if (isVZIPMask(ShuffleMask, VT, WhichResult))
5692 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
5693 V1, V2).getValue(WhichResult);
5695 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
5696 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
5697 V1, V1).getValue(WhichResult);
5698 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
5699 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
5700 V1, V1).getValue(WhichResult);
5701 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
5702 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
5703 V1, V1).getValue(WhichResult);
5706 // If the shuffle is not directly supported and it has 4 elements, use
5707 // the PerfectShuffle-generated table to synthesize it from other shuffles.
5708 unsigned NumElts = VT.getVectorNumElements();
5710 unsigned PFIndexes[4];
5711 for (unsigned i = 0; i != 4; ++i) {
5712 if (ShuffleMask[i] < 0)
5715 PFIndexes[i] = ShuffleMask[i];
5718 // Compute the index in the perfect shuffle table.
5719 unsigned PFTableIndex =
5720 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5721 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5722 unsigned Cost = (PFEntry >> 30);
5725 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5728 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
5729 if (EltSize >= 32) {
5730 // Do the expansion with floating-point types, since that is what the VFP
5731 // registers are defined to use, and since i64 is not legal.
5732 EVT EltVT = EVT::getFloatingPointVT(EltSize);
5733 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
5734 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1);
5735 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2);
5736 SmallVector<SDValue, 8> Ops;
5737 for (unsigned i = 0; i < NumElts; ++i) {
5738 if (ShuffleMask[i] < 0)
5739 Ops.push_back(DAG.getUNDEF(EltVT));
5741 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
5742 ShuffleMask[i] < (int)NumElts ? V1 : V2,
5743 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
5746 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops);
5747 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5750 if ((VT == MVT::v8i16 || VT == MVT::v16i8) && isReverseMask(ShuffleMask, VT))
5751 return LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(Op, DAG);
5753 if (VT == MVT::v8i8) {
5754 SDValue NewOp = LowerVECTOR_SHUFFLEv8i8(Op, ShuffleMask, DAG);
5755 if (NewOp.getNode())
5762 static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
5763 // INSERT_VECTOR_ELT is legal only for immediate indexes.
5764 SDValue Lane = Op.getOperand(2);
5765 if (!isa<ConstantSDNode>(Lane))
5771 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
5772 // EXTRACT_VECTOR_ELT is legal only for immediate indexes.
5773 SDValue Lane = Op.getOperand(1);
5774 if (!isa<ConstantSDNode>(Lane))
5777 SDValue Vec = Op.getOperand(0);
5778 if (Op.getValueType() == MVT::i32 &&
5779 Vec.getValueType().getVectorElementType().getSizeInBits() < 32) {
5781 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
5787 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5788 // The only time a CONCAT_VECTORS operation can have legal types is when
5789 // two 64-bit vectors are concatenated to a 128-bit vector.
5790 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
5791 "unexpected CONCAT_VECTORS");
5793 SDValue Val = DAG.getUNDEF(MVT::v2f64);
5794 SDValue Op0 = Op.getOperand(0);
5795 SDValue Op1 = Op.getOperand(1);
5796 if (Op0.getOpcode() != ISD::UNDEF)
5797 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
5798 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0),
5799 DAG.getIntPtrConstant(0, dl));
5800 if (Op1.getOpcode() != ISD::UNDEF)
5801 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
5802 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1),
5803 DAG.getIntPtrConstant(1, dl));
5804 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val);
5807 /// isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each
5808 /// element has been zero/sign-extended, depending on the isSigned parameter,
5809 /// from an integer type half its size.
5810 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
5812 // A v2i64 BUILD_VECTOR will have been legalized to a BITCAST from v4i32.
5813 EVT VT = N->getValueType(0);
5814 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) {
5815 SDNode *BVN = N->getOperand(0).getNode();
5816 if (BVN->getValueType(0) != MVT::v4i32 ||
5817 BVN->getOpcode() != ISD::BUILD_VECTOR)
5819 unsigned LoElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
5820 unsigned HiElt = 1 - LoElt;
5821 ConstantSDNode *Lo0 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt));
5822 ConstantSDNode *Hi0 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt));
5823 ConstantSDNode *Lo1 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt+2));
5824 ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2));
5825 if (!Lo0 || !Hi0 || !Lo1 || !Hi1)
5828 if (Hi0->getSExtValue() == Lo0->getSExtValue() >> 32 &&
5829 Hi1->getSExtValue() == Lo1->getSExtValue() >> 32)
5832 if (Hi0->isNullValue() && Hi1->isNullValue())
5838 if (N->getOpcode() != ISD::BUILD_VECTOR)
5841 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
5842 SDNode *Elt = N->getOperand(i).getNode();
5843 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
5844 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5845 unsigned HalfSize = EltSize / 2;
5847 if (!isIntN(HalfSize, C->getSExtValue()))
5850 if (!isUIntN(HalfSize, C->getZExtValue()))
5861 /// isSignExtended - Check if a node is a vector value that is sign-extended
5862 /// or a constant BUILD_VECTOR with sign-extended elements.
5863 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
5864 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N))
5866 if (isExtendedBUILD_VECTOR(N, DAG, true))
5871 /// isZeroExtended - Check if a node is a vector value that is zero-extended
5872 /// or a constant BUILD_VECTOR with zero-extended elements.
5873 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
5874 if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N))
5876 if (isExtendedBUILD_VECTOR(N, DAG, false))
5881 static EVT getExtensionTo64Bits(const EVT &OrigVT) {
5882 if (OrigVT.getSizeInBits() >= 64)
5885 assert(OrigVT.isSimple() && "Expecting a simple value type");
5887 MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy;
5888 switch (OrigSimpleTy) {
5889 default: llvm_unreachable("Unexpected Vector Type");
5898 /// AddRequiredExtensionForVMULL - Add a sign/zero extension to extend the total
5899 /// value size to 64 bits. We need a 64-bit D register as an operand to VMULL.
5900 /// We insert the required extension here to get the vector to fill a D register.
5901 static SDValue AddRequiredExtensionForVMULL(SDValue N, SelectionDAG &DAG,
5904 unsigned ExtOpcode) {
5905 // The vector originally had a size of OrigTy. It was then extended to ExtTy.
5906 // We expect the ExtTy to be 128-bits total. If the OrigTy is less than
5907 // 64-bits we need to insert a new extension so that it will be 64-bits.
5908 assert(ExtTy.is128BitVector() && "Unexpected extension size");
5909 if (OrigTy.getSizeInBits() >= 64)
5912 // Must extend size to at least 64 bits to be used as an operand for VMULL.
5913 EVT NewVT = getExtensionTo64Bits(OrigTy);
5915 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N);
5918 /// SkipLoadExtensionForVMULL - return a load of the original vector size that
5919 /// does not do any sign/zero extension. If the original vector is less
5920 /// than 64 bits, an appropriate extension will be added after the load to
5921 /// reach a total size of 64 bits. We have to add the extension separately
5922 /// because ARM does not have a sign/zero extending load for vectors.
5923 static SDValue SkipLoadExtensionForVMULL(LoadSDNode *LD, SelectionDAG& DAG) {
5924 EVT ExtendedTy = getExtensionTo64Bits(LD->getMemoryVT());
5926 // The load already has the right type.
5927 if (ExtendedTy == LD->getMemoryVT())
5928 return DAG.getLoad(LD->getMemoryVT(), SDLoc(LD), LD->getChain(),
5929 LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(),
5930 LD->isNonTemporal(), LD->isInvariant(),
5931 LD->getAlignment());
5933 // We need to create a zextload/sextload. We cannot just create a load
5934 // followed by a zext/zext node because LowerMUL is also run during normal
5935 // operation legalization where we can't create illegal types.
5936 return DAG.getExtLoad(LD->getExtensionType(), SDLoc(LD), ExtendedTy,
5937 LD->getChain(), LD->getBasePtr(), LD->getPointerInfo(),
5938 LD->getMemoryVT(), LD->isVolatile(), LD->isInvariant(),
5939 LD->isNonTemporal(), LD->getAlignment());
5942 /// SkipExtensionForVMULL - For a node that is a SIGN_EXTEND, ZERO_EXTEND,
5943 /// extending load, or BUILD_VECTOR with extended elements, return the
5944 /// unextended value. The unextended vector should be 64 bits so that it can
5945 /// be used as an operand to a VMULL instruction. If the original vector size
5946 /// before extension is less than 64 bits we add a an extension to resize
5947 /// the vector to 64 bits.
5948 static SDValue SkipExtensionForVMULL(SDNode *N, SelectionDAG &DAG) {
5949 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
5950 return AddRequiredExtensionForVMULL(N->getOperand(0), DAG,
5951 N->getOperand(0)->getValueType(0),
5955 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
5956 return SkipLoadExtensionForVMULL(LD, DAG);
5958 // Otherwise, the value must be a BUILD_VECTOR. For v2i64, it will
5959 // have been legalized as a BITCAST from v4i32.
5960 if (N->getOpcode() == ISD::BITCAST) {
5961 SDNode *BVN = N->getOperand(0).getNode();
5962 assert(BVN->getOpcode() == ISD::BUILD_VECTOR &&
5963 BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR");
5964 unsigned LowElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
5965 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), MVT::v2i32,
5966 BVN->getOperand(LowElt), BVN->getOperand(LowElt+2));
5968 // Construct a new BUILD_VECTOR with elements truncated to half the size.
5969 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
5970 EVT VT = N->getValueType(0);
5971 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
5972 unsigned NumElts = VT.getVectorNumElements();
5973 MVT TruncVT = MVT::getIntegerVT(EltSize);
5974 SmallVector<SDValue, 8> Ops;
5976 for (unsigned i = 0; i != NumElts; ++i) {
5977 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
5978 const APInt &CInt = C->getAPIntValue();
5979 // Element types smaller than 32 bits are not legal, so use i32 elements.
5980 // The values are implicitly truncated so sext vs. zext doesn't matter.
5981 Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), dl, MVT::i32));
5983 return DAG.getNode(ISD::BUILD_VECTOR, dl,
5984 MVT::getVectorVT(TruncVT, NumElts), Ops);
5987 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
5988 unsigned Opcode = N->getOpcode();
5989 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
5990 SDNode *N0 = N->getOperand(0).getNode();
5991 SDNode *N1 = N->getOperand(1).getNode();
5992 return N0->hasOneUse() && N1->hasOneUse() &&
5993 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
5998 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
5999 unsigned Opcode = N->getOpcode();
6000 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
6001 SDNode *N0 = N->getOperand(0).getNode();
6002 SDNode *N1 = N->getOperand(1).getNode();
6003 return N0->hasOneUse() && N1->hasOneUse() &&
6004 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
6009 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
6010 // Multiplications are only custom-lowered for 128-bit vectors so that
6011 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
6012 EVT VT = Op.getValueType();
6013 assert(VT.is128BitVector() && VT.isInteger() &&
6014 "unexpected type for custom-lowering ISD::MUL");
6015 SDNode *N0 = Op.getOperand(0).getNode();
6016 SDNode *N1 = Op.getOperand(1).getNode();
6017 unsigned NewOpc = 0;
6019 bool isN0SExt = isSignExtended(N0, DAG);
6020 bool isN1SExt = isSignExtended(N1, DAG);
6021 if (isN0SExt && isN1SExt)
6022 NewOpc = ARMISD::VMULLs;
6024 bool isN0ZExt = isZeroExtended(N0, DAG);
6025 bool isN1ZExt = isZeroExtended(N1, DAG);
6026 if (isN0ZExt && isN1ZExt)
6027 NewOpc = ARMISD::VMULLu;
6028 else if (isN1SExt || isN1ZExt) {
6029 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
6030 // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
6031 if (isN1SExt && isAddSubSExt(N0, DAG)) {
6032 NewOpc = ARMISD::VMULLs;
6034 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
6035 NewOpc = ARMISD::VMULLu;
6037 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
6039 NewOpc = ARMISD::VMULLu;
6045 if (VT == MVT::v2i64)
6046 // Fall through to expand this. It is not legal.
6049 // Other vector multiplications are legal.
6054 // Legalize to a VMULL instruction.
6057 SDValue Op1 = SkipExtensionForVMULL(N1, DAG);
6059 Op0 = SkipExtensionForVMULL(N0, DAG);
6060 assert(Op0.getValueType().is64BitVector() &&
6061 Op1.getValueType().is64BitVector() &&
6062 "unexpected types for extended operands to VMULL");
6063 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
6066 // Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during
6067 // isel lowering to take advantage of no-stall back to back vmul + vmla.
6074 SDValue N00 = SkipExtensionForVMULL(N0->getOperand(0).getNode(), DAG);
6075 SDValue N01 = SkipExtensionForVMULL(N0->getOperand(1).getNode(), DAG);
6076 EVT Op1VT = Op1.getValueType();
6077 return DAG.getNode(N0->getOpcode(), DL, VT,
6078 DAG.getNode(NewOpc, DL, VT,
6079 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
6080 DAG.getNode(NewOpc, DL, VT,
6081 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
6085 LowerSDIV_v4i8(SDValue X, SDValue Y, SDLoc dl, SelectionDAG &DAG) {
6087 // float4 xf = vcvt_f32_s32(vmovl_s16(a.lo));
6088 // float4 yf = vcvt_f32_s32(vmovl_s16(b.lo));
6089 X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X);
6090 Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y);
6091 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X);
6092 Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y);
6093 // Get reciprocal estimate.
6094 // float4 recip = vrecpeq_f32(yf);
6095 Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6096 DAG.getConstant(Intrinsic::arm_neon_vrecpe, dl, MVT::i32),
6098 // Because char has a smaller range than uchar, we can actually get away
6099 // without any newton steps. This requires that we use a weird bias
6100 // of 0xb000, however (again, this has been exhaustively tested).
6101 // float4 result = as_float4(as_int4(xf*recip) + 0xb000);
6102 X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y);
6103 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X);
6104 Y = DAG.getConstant(0xb000, dl, MVT::i32);
6105 Y = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Y, Y, Y, Y);
6106 X = DAG.getNode(ISD::ADD, dl, MVT::v4i32, X, Y);
6107 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X);
6108 // Convert back to short.
6109 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X);
6110 X = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, X);
6115 LowerSDIV_v4i16(SDValue N0, SDValue N1, SDLoc dl, SelectionDAG &DAG) {
6117 // Convert to float.
6118 // float4 yf = vcvt_f32_s32(vmovl_s16(y));
6119 // float4 xf = vcvt_f32_s32(vmovl_s16(x));
6120 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0);
6121 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1);
6122 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
6123 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
6125 // Use reciprocal estimate and one refinement step.
6126 // float4 recip = vrecpeq_f32(yf);
6127 // recip *= vrecpsq_f32(yf, recip);
6128 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6129 DAG.getConstant(Intrinsic::arm_neon_vrecpe, dl, MVT::i32),
6131 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6132 DAG.getConstant(Intrinsic::arm_neon_vrecps, dl, MVT::i32),
6134 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
6135 // Because short has a smaller range than ushort, we can actually get away
6136 // with only a single newton step. This requires that we use a weird bias
6137 // of 89, however (again, this has been exhaustively tested).
6138 // float4 result = as_float4(as_int4(xf*recip) + 0x89);
6139 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
6140 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
6141 N1 = DAG.getConstant(0x89, dl, MVT::i32);
6142 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
6143 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
6144 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
6145 // Convert back to integer and return.
6146 // return vmovn_s32(vcvt_s32_f32(result));
6147 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
6148 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
6152 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
6153 EVT VT = Op.getValueType();
6154 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
6155 "unexpected type for custom-lowering ISD::SDIV");
6158 SDValue N0 = Op.getOperand(0);
6159 SDValue N1 = Op.getOperand(1);
6162 if (VT == MVT::v8i8) {
6163 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0);
6164 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1);
6166 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
6167 DAG.getIntPtrConstant(4, dl));
6168 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
6169 DAG.getIntPtrConstant(4, dl));
6170 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
6171 DAG.getIntPtrConstant(0, dl));
6172 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
6173 DAG.getIntPtrConstant(0, dl));
6175 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16
6176 N2 = LowerSDIV_v4i8(N2, N3, dl, DAG); // v4i16
6178 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
6179 N0 = LowerCONCAT_VECTORS(N0, DAG);
6181 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0);
6184 return LowerSDIV_v4i16(N0, N1, dl, DAG);
6187 static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG) {
6188 EVT VT = Op.getValueType();
6189 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
6190 "unexpected type for custom-lowering ISD::UDIV");
6193 SDValue N0 = Op.getOperand(0);
6194 SDValue N1 = Op.getOperand(1);
6197 if (VT == MVT::v8i8) {
6198 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0);
6199 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1);
6201 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
6202 DAG.getIntPtrConstant(4, dl));
6203 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
6204 DAG.getIntPtrConstant(4, dl));
6205 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
6206 DAG.getIntPtrConstant(0, dl));
6207 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
6208 DAG.getIntPtrConstant(0, dl));
6210 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16
6211 N2 = LowerSDIV_v4i16(N2, N3, dl, DAG); // v4i16
6213 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
6214 N0 = LowerCONCAT_VECTORS(N0, DAG);
6216 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8,
6217 DAG.getConstant(Intrinsic::arm_neon_vqmovnsu, dl,
6223 // v4i16 sdiv ... Convert to float.
6224 // float4 yf = vcvt_f32_s32(vmovl_u16(y));
6225 // float4 xf = vcvt_f32_s32(vmovl_u16(x));
6226 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0);
6227 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1);
6228 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
6229 SDValue BN1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
6231 // Use reciprocal estimate and two refinement steps.
6232 // float4 recip = vrecpeq_f32(yf);
6233 // recip *= vrecpsq_f32(yf, recip);
6234 // recip *= vrecpsq_f32(yf, recip);
6235 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6236 DAG.getConstant(Intrinsic::arm_neon_vrecpe, dl, MVT::i32),
6238 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6239 DAG.getConstant(Intrinsic::arm_neon_vrecps, dl, MVT::i32),
6241 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
6242 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6243 DAG.getConstant(Intrinsic::arm_neon_vrecps, dl, MVT::i32),
6245 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
6246 // Simply multiplying by the reciprocal estimate can leave us a few ulps
6247 // too low, so we add 2 ulps (exhaustive testing shows that this is enough,
6248 // and that it will never cause us to return an answer too large).
6249 // float4 result = as_float4(as_int4(xf*recip) + 2);
6250 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
6251 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
6252 N1 = DAG.getConstant(2, dl, MVT::i32);
6253 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
6254 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
6255 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
6256 // Convert back to integer and return.
6257 // return vmovn_u32(vcvt_s32_f32(result));
6258 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
6259 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
6263 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
6264 EVT VT = Op.getNode()->getValueType(0);
6265 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
6268 bool ExtraOp = false;
6269 switch (Op.getOpcode()) {
6270 default: llvm_unreachable("Invalid code");
6271 case ISD::ADDC: Opc = ARMISD::ADDC; break;
6272 case ISD::ADDE: Opc = ARMISD::ADDE; ExtraOp = true; break;
6273 case ISD::SUBC: Opc = ARMISD::SUBC; break;
6274 case ISD::SUBE: Opc = ARMISD::SUBE; ExtraOp = true; break;
6278 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
6280 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
6281 Op.getOperand(1), Op.getOperand(2));
6284 SDValue ARMTargetLowering::LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const {
6285 assert(Subtarget->isTargetDarwin());
6287 // For iOS, we want to call an alternative entry point: __sincos_stret,
6288 // return values are passed via sret.
6290 SDValue Arg = Op.getOperand(0);
6291 EVT ArgVT = Arg.getValueType();
6292 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
6294 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6295 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6297 // Pair of floats / doubles used to pass the result.
6298 StructType *RetTy = StructType::get(ArgTy, ArgTy, nullptr);
6300 // Create stack object for sret.
6301 const uint64_t ByteSize = TLI.getDataLayout()->getTypeAllocSize(RetTy);
6302 const unsigned StackAlign = TLI.getDataLayout()->getPrefTypeAlignment(RetTy);
6303 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign, false);
6304 SDValue SRet = DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
6310 Entry.Ty = RetTy->getPointerTo();
6311 Entry.isSExt = false;
6312 Entry.isZExt = false;
6313 Entry.isSRet = true;
6314 Args.push_back(Entry);
6318 Entry.isSExt = false;
6319 Entry.isZExt = false;
6320 Args.push_back(Entry);
6322 const char *LibcallName = (ArgVT == MVT::f64)
6323 ? "__sincos_stret" : "__sincosf_stret";
6324 SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy());
6326 TargetLowering::CallLoweringInfo CLI(DAG);
6327 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
6328 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()), Callee,
6330 .setDiscardResult();
6332 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
6334 SDValue LoadSin = DAG.getLoad(ArgVT, dl, CallResult.second, SRet,
6335 MachinePointerInfo(), false, false, false, 0);
6337 // Address of cos field.
6338 SDValue Add = DAG.getNode(ISD::ADD, dl, getPointerTy(), SRet,
6339 DAG.getIntPtrConstant(ArgVT.getStoreSize(), dl));
6340 SDValue LoadCos = DAG.getLoad(ArgVT, dl, LoadSin.getValue(1), Add,
6341 MachinePointerInfo(), false, false, false, 0);
6343 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
6344 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys,
6345 LoadSin.getValue(0), LoadCos.getValue(0));
6348 static SDValue LowerAtomicLoadStore(SDValue Op, SelectionDAG &DAG) {
6349 // Monotonic load/store is legal for all targets
6350 if (cast<AtomicSDNode>(Op)->getOrdering() <= Monotonic)
6353 // Acquire/Release load/store is not legal for targets without a
6354 // dmb or equivalent available.
6358 static void ReplaceREADCYCLECOUNTER(SDNode *N,
6359 SmallVectorImpl<SDValue> &Results,
6361 const ARMSubtarget *Subtarget) {
6363 SDValue Cycles32, OutChain;
6365 if (Subtarget->hasPerfMon()) {
6366 // Under Power Management extensions, the cycle-count is:
6367 // mrc p15, #0, <Rt>, c9, c13, #0
6368 SDValue Ops[] = { N->getOperand(0), // Chain
6369 DAG.getConstant(Intrinsic::arm_mrc, DL, MVT::i32),
6370 DAG.getConstant(15, DL, MVT::i32),
6371 DAG.getConstant(0, DL, MVT::i32),
6372 DAG.getConstant(9, DL, MVT::i32),
6373 DAG.getConstant(13, DL, MVT::i32),
6374 DAG.getConstant(0, DL, MVT::i32)
6377 Cycles32 = DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL,
6378 DAG.getVTList(MVT::i32, MVT::Other), Ops);
6379 OutChain = Cycles32.getValue(1);
6381 // Intrinsic is defined to return 0 on unsupported platforms. Technically
6382 // there are older ARM CPUs that have implementation-specific ways of
6383 // obtaining this information (FIXME!).
6384 Cycles32 = DAG.getConstant(0, DL, MVT::i32);
6385 OutChain = DAG.getEntryNode();
6389 SDValue Cycles64 = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64,
6390 Cycles32, DAG.getConstant(0, DL, MVT::i32));
6391 Results.push_back(Cycles64);
6392 Results.push_back(OutChain);
6395 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6396 switch (Op.getOpcode()) {
6397 default: llvm_unreachable("Don't know how to custom lower this!");
6398 case ISD::WRITE_REGISTER: return LowerWRITE_REGISTER(Op, DAG);
6399 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6400 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
6401 case ISD::GlobalAddress:
6402 switch (Subtarget->getTargetTriple().getObjectFormat()) {
6403 default: llvm_unreachable("unknown object format");
6405 return LowerGlobalAddressWindows(Op, DAG);
6407 return LowerGlobalAddressELF(Op, DAG);
6409 return LowerGlobalAddressDarwin(Op, DAG);
6411 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6412 case ISD::SELECT: return LowerSELECT(Op, DAG);
6413 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
6414 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
6415 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
6416 case ISD::VASTART: return LowerVASTART(Op, DAG);
6417 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG, Subtarget);
6418 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget);
6419 case ISD::SINT_TO_FP:
6420 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
6421 case ISD::FP_TO_SINT:
6422 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
6423 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
6424 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6425 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6426 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
6427 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
6428 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
6429 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
6431 case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG);
6434 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
6435 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
6436 case ISD::SRL_PARTS:
6437 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
6438 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
6439 case ISD::CTPOP: return LowerCTPOP(Op.getNode(), DAG, Subtarget);
6440 case ISD::SETCC: return LowerVSETCC(Op, DAG);
6441 case ISD::ConstantFP: return LowerConstantFP(Op, DAG, Subtarget);
6442 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
6443 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6444 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
6445 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
6446 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
6447 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6448 case ISD::MUL: return LowerMUL(Op, DAG);
6449 case ISD::SDIV: return LowerSDIV(Op, DAG);
6450 case ISD::UDIV: return LowerUDIV(Op, DAG);
6454 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
6459 return LowerXALUO(Op, DAG);
6460 case ISD::ATOMIC_LOAD:
6461 case ISD::ATOMIC_STORE: return LowerAtomicLoadStore(Op, DAG);
6462 case ISD::FSINCOS: return LowerFSINCOS(Op, DAG);
6464 case ISD::UDIVREM: return LowerDivRem(Op, DAG);
6465 case ISD::DYNAMIC_STACKALLOC:
6466 if (Subtarget->getTargetTriple().isWindowsItaniumEnvironment())
6467 return LowerDYNAMIC_STACKALLOC(Op, DAG);
6468 llvm_unreachable("Don't know how to custom lower this!");
6469 case ISD::FP_ROUND: return LowerFP_ROUND(Op, DAG);
6470 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
6474 /// ReplaceNodeResults - Replace the results of node with an illegal result
6475 /// type with new values built out of custom code.
6476 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
6477 SmallVectorImpl<SDValue>&Results,
6478 SelectionDAG &DAG) const {
6480 switch (N->getOpcode()) {
6482 llvm_unreachable("Don't know how to custom expand this!");
6483 case ISD::READ_REGISTER:
6484 ExpandREAD_REGISTER(N, Results, DAG);
6487 Res = ExpandBITCAST(N, DAG);
6491 Res = Expand64BitShift(N, DAG, Subtarget);
6493 case ISD::READCYCLECOUNTER:
6494 ReplaceREADCYCLECOUNTER(N, Results, DAG, Subtarget);
6498 Results.push_back(Res);
6501 //===----------------------------------------------------------------------===//
6502 // ARM Scheduler Hooks
6503 //===----------------------------------------------------------------------===//
6505 /// SetupEntryBlockForSjLj - Insert code into the entry block that creates and
6506 /// registers the function context.
6507 void ARMTargetLowering::
6508 SetupEntryBlockForSjLj(MachineInstr *MI, MachineBasicBlock *MBB,
6509 MachineBasicBlock *DispatchBB, int FI) const {
6510 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
6511 DebugLoc dl = MI->getDebugLoc();
6512 MachineFunction *MF = MBB->getParent();
6513 MachineRegisterInfo *MRI = &MF->getRegInfo();
6514 MachineConstantPool *MCP = MF->getConstantPool();
6515 ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>();
6516 const Function *F = MF->getFunction();
6518 bool isThumb = Subtarget->isThumb();
6519 bool isThumb2 = Subtarget->isThumb2();
6521 unsigned PCLabelId = AFI->createPICLabelUId();
6522 unsigned PCAdj = (isThumb || isThumb2) ? 4 : 8;
6523 ARMConstantPoolValue *CPV =
6524 ARMConstantPoolMBB::Create(F->getContext(), DispatchBB, PCLabelId, PCAdj);
6525 unsigned CPI = MCP->getConstantPoolIndex(CPV, 4);
6527 const TargetRegisterClass *TRC = isThumb ? &ARM::tGPRRegClass
6528 : &ARM::GPRRegClass;
6530 // Grab constant pool and fixed stack memory operands.
6531 MachineMemOperand *CPMMO =
6532 MF->getMachineMemOperand(MachinePointerInfo::getConstantPool(),
6533 MachineMemOperand::MOLoad, 4, 4);
6535 MachineMemOperand *FIMMOSt =
6536 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
6537 MachineMemOperand::MOStore, 4, 4);
6539 // Load the address of the dispatch MBB into the jump buffer.
6541 // Incoming value: jbuf
6542 // ldr.n r5, LCPI1_1
6545 // str r5, [$jbuf, #+4] ; &jbuf[1]
6546 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6547 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2LDRpci), NewVReg1)
6548 .addConstantPoolIndex(CPI)
6549 .addMemOperand(CPMMO));
6550 // Set the low bit because of thumb mode.
6551 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6553 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2ORRri), NewVReg2)
6554 .addReg(NewVReg1, RegState::Kill)
6556 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6557 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg3)
6558 .addReg(NewVReg2, RegState::Kill)
6560 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2STRi12))
6561 .addReg(NewVReg3, RegState::Kill)
6563 .addImm(36) // &jbuf[1] :: pc
6564 .addMemOperand(FIMMOSt));
6565 } else if (isThumb) {
6566 // Incoming value: jbuf
6567 // ldr.n r1, LCPI1_4
6571 // add r2, $jbuf, #+4 ; &jbuf[1]
6573 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6574 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tLDRpci), NewVReg1)
6575 .addConstantPoolIndex(CPI)
6576 .addMemOperand(CPMMO));
6577 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6578 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg2)
6579 .addReg(NewVReg1, RegState::Kill)
6581 // Set the low bit because of thumb mode.
6582 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6583 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tMOVi8), NewVReg3)
6584 .addReg(ARM::CPSR, RegState::Define)
6586 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
6587 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tORR), NewVReg4)
6588 .addReg(ARM::CPSR, RegState::Define)
6589 .addReg(NewVReg2, RegState::Kill)
6590 .addReg(NewVReg3, RegState::Kill));
6591 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
6592 BuildMI(*MBB, MI, dl, TII->get(ARM::tADDframe), NewVReg5)
6594 .addImm(36); // &jbuf[1] :: pc
6595 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tSTRi))
6596 .addReg(NewVReg4, RegState::Kill)
6597 .addReg(NewVReg5, RegState::Kill)
6599 .addMemOperand(FIMMOSt));
6601 // Incoming value: jbuf
6604 // str r1, [$jbuf, #+4] ; &jbuf[1]
6605 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6606 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::LDRi12), NewVReg1)
6607 .addConstantPoolIndex(CPI)
6609 .addMemOperand(CPMMO));
6610 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6611 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::PICADD), NewVReg2)
6612 .addReg(NewVReg1, RegState::Kill)
6613 .addImm(PCLabelId));
6614 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::STRi12))
6615 .addReg(NewVReg2, RegState::Kill)
6617 .addImm(36) // &jbuf[1] :: pc
6618 .addMemOperand(FIMMOSt));
6622 void ARMTargetLowering::EmitSjLjDispatchBlock(MachineInstr *MI,
6623 MachineBasicBlock *MBB) const {
6624 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
6625 DebugLoc dl = MI->getDebugLoc();
6626 MachineFunction *MF = MBB->getParent();
6627 MachineRegisterInfo *MRI = &MF->getRegInfo();
6628 MachineFrameInfo *MFI = MF->getFrameInfo();
6629 int FI = MFI->getFunctionContextIndex();
6631 const TargetRegisterClass *TRC = Subtarget->isThumb() ? &ARM::tGPRRegClass
6632 : &ARM::GPRnopcRegClass;
6634 // Get a mapping of the call site numbers to all of the landing pads they're
6636 DenseMap<unsigned, SmallVector<MachineBasicBlock*, 2> > CallSiteNumToLPad;
6637 unsigned MaxCSNum = 0;
6638 MachineModuleInfo &MMI = MF->getMMI();
6639 for (MachineFunction::iterator BB = MF->begin(), E = MF->end(); BB != E;
6641 if (!BB->isLandingPad()) continue;
6643 // FIXME: We should assert that the EH_LABEL is the first MI in the landing
6645 for (MachineBasicBlock::iterator
6646 II = BB->begin(), IE = BB->end(); II != IE; ++II) {
6647 if (!II->isEHLabel()) continue;
6649 MCSymbol *Sym = II->getOperand(0).getMCSymbol();
6650 if (!MMI.hasCallSiteLandingPad(Sym)) continue;
6652 SmallVectorImpl<unsigned> &CallSiteIdxs = MMI.getCallSiteLandingPad(Sym);
6653 for (SmallVectorImpl<unsigned>::iterator
6654 CSI = CallSiteIdxs.begin(), CSE = CallSiteIdxs.end();
6655 CSI != CSE; ++CSI) {
6656 CallSiteNumToLPad[*CSI].push_back(BB);
6657 MaxCSNum = std::max(MaxCSNum, *CSI);
6663 // Get an ordered list of the machine basic blocks for the jump table.
6664 std::vector<MachineBasicBlock*> LPadList;
6665 SmallPtrSet<MachineBasicBlock*, 64> InvokeBBs;
6666 LPadList.reserve(CallSiteNumToLPad.size());
6667 for (unsigned I = 1; I <= MaxCSNum; ++I) {
6668 SmallVectorImpl<MachineBasicBlock*> &MBBList = CallSiteNumToLPad[I];
6669 for (SmallVectorImpl<MachineBasicBlock*>::iterator
6670 II = MBBList.begin(), IE = MBBList.end(); II != IE; ++II) {
6671 LPadList.push_back(*II);
6672 InvokeBBs.insert((*II)->pred_begin(), (*II)->pred_end());
6676 assert(!LPadList.empty() &&
6677 "No landing pad destinations for the dispatch jump table!");
6679 // Create the jump table and associated information.
6680 MachineJumpTableInfo *JTI =
6681 MF->getOrCreateJumpTableInfo(MachineJumpTableInfo::EK_Inline);
6682 unsigned MJTI = JTI->createJumpTableIndex(LPadList);
6683 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
6685 // Create the MBBs for the dispatch code.
6687 // Shove the dispatch's address into the return slot in the function context.
6688 MachineBasicBlock *DispatchBB = MF->CreateMachineBasicBlock();
6689 DispatchBB->setIsLandingPad();
6691 MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock();
6692 unsigned trap_opcode;
6693 if (Subtarget->isThumb())
6694 trap_opcode = ARM::tTRAP;
6696 trap_opcode = Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP;
6698 BuildMI(TrapBB, dl, TII->get(trap_opcode));
6699 DispatchBB->addSuccessor(TrapBB);
6701 MachineBasicBlock *DispContBB = MF->CreateMachineBasicBlock();
6702 DispatchBB->addSuccessor(DispContBB);
6705 MF->insert(MF->end(), DispatchBB);
6706 MF->insert(MF->end(), DispContBB);
6707 MF->insert(MF->end(), TrapBB);
6709 // Insert code into the entry block that creates and registers the function
6711 SetupEntryBlockForSjLj(MI, MBB, DispatchBB, FI);
6713 MachineMemOperand *FIMMOLd =
6714 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
6715 MachineMemOperand::MOLoad |
6716 MachineMemOperand::MOVolatile, 4, 4);
6718 MachineInstrBuilder MIB;
6719 MIB = BuildMI(DispatchBB, dl, TII->get(ARM::Int_eh_sjlj_dispatchsetup));
6721 const ARMBaseInstrInfo *AII = static_cast<const ARMBaseInstrInfo*>(TII);
6722 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
6724 // Add a register mask with no preserved registers. This results in all
6725 // registers being marked as clobbered.
6726 MIB.addRegMask(RI.getNoPreservedMask());
6728 unsigned NumLPads = LPadList.size();
6729 if (Subtarget->isThumb2()) {
6730 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6731 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2LDRi12), NewVReg1)
6734 .addMemOperand(FIMMOLd));
6736 if (NumLPads < 256) {
6737 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPri))
6739 .addImm(LPadList.size()));
6741 unsigned VReg1 = MRI->createVirtualRegister(TRC);
6742 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVi16), VReg1)
6743 .addImm(NumLPads & 0xFFFF));
6745 unsigned VReg2 = VReg1;
6746 if ((NumLPads & 0xFFFF0000) != 0) {
6747 VReg2 = MRI->createVirtualRegister(TRC);
6748 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVTi16), VReg2)
6750 .addImm(NumLPads >> 16));
6753 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPrr))
6758 BuildMI(DispatchBB, dl, TII->get(ARM::t2Bcc))
6763 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6764 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::t2LEApcrelJT),NewVReg3)
6765 .addJumpTableIndex(MJTI));
6767 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
6770 BuildMI(DispContBB, dl, TII->get(ARM::t2ADDrs), NewVReg4)
6771 .addReg(NewVReg3, RegState::Kill)
6773 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))));
6775 BuildMI(DispContBB, dl, TII->get(ARM::t2BR_JT))
6776 .addReg(NewVReg4, RegState::Kill)
6778 .addJumpTableIndex(MJTI);
6779 } else if (Subtarget->isThumb()) {
6780 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6781 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRspi), NewVReg1)
6784 .addMemOperand(FIMMOLd));
6786 if (NumLPads < 256) {
6787 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPi8))
6791 MachineConstantPool *ConstantPool = MF->getConstantPool();
6792 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
6793 const Constant *C = ConstantInt::get(Int32Ty, NumLPads);
6795 // MachineConstantPool wants an explicit alignment.
6796 unsigned Align = getDataLayout()->getPrefTypeAlignment(Int32Ty);
6798 Align = getDataLayout()->getTypeAllocSize(C->getType());
6799 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
6801 unsigned VReg1 = MRI->createVirtualRegister(TRC);
6802 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRpci))
6803 .addReg(VReg1, RegState::Define)
6804 .addConstantPoolIndex(Idx));
6805 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPr))
6810 BuildMI(DispatchBB, dl, TII->get(ARM::tBcc))
6815 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6816 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLSLri), NewVReg2)
6817 .addReg(ARM::CPSR, RegState::Define)
6821 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6822 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLEApcrelJT), NewVReg3)
6823 .addJumpTableIndex(MJTI));
6825 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
6826 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg4)
6827 .addReg(ARM::CPSR, RegState::Define)
6828 .addReg(NewVReg2, RegState::Kill)
6831 MachineMemOperand *JTMMOLd =
6832 MF->getMachineMemOperand(MachinePointerInfo::getJumpTable(),
6833 MachineMemOperand::MOLoad, 4, 4);
6835 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
6836 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLDRi), NewVReg5)
6837 .addReg(NewVReg4, RegState::Kill)
6839 .addMemOperand(JTMMOLd));
6841 unsigned NewVReg6 = NewVReg5;
6842 if (RelocM == Reloc::PIC_) {
6843 NewVReg6 = MRI->createVirtualRegister(TRC);
6844 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg6)
6845 .addReg(ARM::CPSR, RegState::Define)
6846 .addReg(NewVReg5, RegState::Kill)
6850 BuildMI(DispContBB, dl, TII->get(ARM::tBR_JTr))
6851 .addReg(NewVReg6, RegState::Kill)
6852 .addJumpTableIndex(MJTI);
6854 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6855 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRi12), NewVReg1)
6858 .addMemOperand(FIMMOLd));
6860 if (NumLPads < 256) {
6861 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPri))
6864 } else if (Subtarget->hasV6T2Ops() && isUInt<16>(NumLPads)) {
6865 unsigned VReg1 = MRI->createVirtualRegister(TRC);
6866 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVi16), VReg1)
6867 .addImm(NumLPads & 0xFFFF));
6869 unsigned VReg2 = VReg1;
6870 if ((NumLPads & 0xFFFF0000) != 0) {
6871 VReg2 = MRI->createVirtualRegister(TRC);
6872 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVTi16), VReg2)
6874 .addImm(NumLPads >> 16));
6877 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
6881 MachineConstantPool *ConstantPool = MF->getConstantPool();
6882 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
6883 const Constant *C = ConstantInt::get(Int32Ty, NumLPads);
6885 // MachineConstantPool wants an explicit alignment.
6886 unsigned Align = getDataLayout()->getPrefTypeAlignment(Int32Ty);
6888 Align = getDataLayout()->getTypeAllocSize(C->getType());
6889 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
6891 unsigned VReg1 = MRI->createVirtualRegister(TRC);
6892 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRcp))
6893 .addReg(VReg1, RegState::Define)
6894 .addConstantPoolIndex(Idx)
6896 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
6898 .addReg(VReg1, RegState::Kill));
6901 BuildMI(DispatchBB, dl, TII->get(ARM::Bcc))
6906 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6908 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::MOVsi), NewVReg3)
6910 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))));
6911 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
6912 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::LEApcrelJT), NewVReg4)
6913 .addJumpTableIndex(MJTI));
6915 MachineMemOperand *JTMMOLd =
6916 MF->getMachineMemOperand(MachinePointerInfo::getJumpTable(),
6917 MachineMemOperand::MOLoad, 4, 4);
6918 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
6920 BuildMI(DispContBB, dl, TII->get(ARM::LDRrs), NewVReg5)
6921 .addReg(NewVReg3, RegState::Kill)
6924 .addMemOperand(JTMMOLd));
6926 if (RelocM == Reloc::PIC_) {
6927 BuildMI(DispContBB, dl, TII->get(ARM::BR_JTadd))
6928 .addReg(NewVReg5, RegState::Kill)
6930 .addJumpTableIndex(MJTI);
6932 BuildMI(DispContBB, dl, TII->get(ARM::BR_JTr))
6933 .addReg(NewVReg5, RegState::Kill)
6934 .addJumpTableIndex(MJTI);
6938 // Add the jump table entries as successors to the MBB.
6939 SmallPtrSet<MachineBasicBlock*, 8> SeenMBBs;
6940 for (std::vector<MachineBasicBlock*>::iterator
6941 I = LPadList.begin(), E = LPadList.end(); I != E; ++I) {
6942 MachineBasicBlock *CurMBB = *I;
6943 if (SeenMBBs.insert(CurMBB).second)
6944 DispContBB->addSuccessor(CurMBB);
6947 // N.B. the order the invoke BBs are processed in doesn't matter here.
6948 const MCPhysReg *SavedRegs = RI.getCalleeSavedRegs(MF);
6949 SmallVector<MachineBasicBlock*, 64> MBBLPads;
6950 for (MachineBasicBlock *BB : InvokeBBs) {
6952 // Remove the landing pad successor from the invoke block and replace it
6953 // with the new dispatch block.
6954 SmallVector<MachineBasicBlock*, 4> Successors(BB->succ_begin(),
6956 while (!Successors.empty()) {
6957 MachineBasicBlock *SMBB = Successors.pop_back_val();
6958 if (SMBB->isLandingPad()) {
6959 BB->removeSuccessor(SMBB);
6960 MBBLPads.push_back(SMBB);
6964 BB->addSuccessor(DispatchBB);
6966 // Find the invoke call and mark all of the callee-saved registers as
6967 // 'implicit defined' so that they're spilled. This prevents code from
6968 // moving instructions to before the EH block, where they will never be
6970 for (MachineBasicBlock::reverse_iterator
6971 II = BB->rbegin(), IE = BB->rend(); II != IE; ++II) {
6972 if (!II->isCall()) continue;
6974 DenseMap<unsigned, bool> DefRegs;
6975 for (MachineInstr::mop_iterator
6976 OI = II->operands_begin(), OE = II->operands_end();
6978 if (!OI->isReg()) continue;
6979 DefRegs[OI->getReg()] = true;
6982 MachineInstrBuilder MIB(*MF, &*II);
6984 for (unsigned i = 0; SavedRegs[i] != 0; ++i) {
6985 unsigned Reg = SavedRegs[i];
6986 if (Subtarget->isThumb2() &&
6987 !ARM::tGPRRegClass.contains(Reg) &&
6988 !ARM::hGPRRegClass.contains(Reg))
6990 if (Subtarget->isThumb1Only() && !ARM::tGPRRegClass.contains(Reg))
6992 if (!Subtarget->isThumb() && !ARM::GPRRegClass.contains(Reg))
6995 MIB.addReg(Reg, RegState::ImplicitDefine | RegState::Dead);
7002 // Mark all former landing pads as non-landing pads. The dispatch is the only
7004 for (SmallVectorImpl<MachineBasicBlock*>::iterator
7005 I = MBBLPads.begin(), E = MBBLPads.end(); I != E; ++I)
7006 (*I)->setIsLandingPad(false);
7008 // The instruction is gone now.
7009 MI->eraseFromParent();
7013 MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
7014 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
7015 E = MBB->succ_end(); I != E; ++I)
7018 llvm_unreachable("Expecting a BB with two successors!");
7021 /// Return the load opcode for a given load size. If load size >= 8,
7022 /// neon opcode will be returned.
7023 static unsigned getLdOpcode(unsigned LdSize, bool IsThumb1, bool IsThumb2) {
7025 return LdSize == 16 ? ARM::VLD1q32wb_fixed
7026 : LdSize == 8 ? ARM::VLD1d32wb_fixed : 0;
7028 return LdSize == 4 ? ARM::tLDRi
7029 : LdSize == 2 ? ARM::tLDRHi
7030 : LdSize == 1 ? ARM::tLDRBi : 0;
7032 return LdSize == 4 ? ARM::t2LDR_POST
7033 : LdSize == 2 ? ARM::t2LDRH_POST
7034 : LdSize == 1 ? ARM::t2LDRB_POST : 0;
7035 return LdSize == 4 ? ARM::LDR_POST_IMM
7036 : LdSize == 2 ? ARM::LDRH_POST
7037 : LdSize == 1 ? ARM::LDRB_POST_IMM : 0;
7040 /// Return the store opcode for a given store size. If store size >= 8,
7041 /// neon opcode will be returned.
7042 static unsigned getStOpcode(unsigned StSize, bool IsThumb1, bool IsThumb2) {
7044 return StSize == 16 ? ARM::VST1q32wb_fixed
7045 : StSize == 8 ? ARM::VST1d32wb_fixed : 0;
7047 return StSize == 4 ? ARM::tSTRi
7048 : StSize == 2 ? ARM::tSTRHi
7049 : StSize == 1 ? ARM::tSTRBi : 0;
7051 return StSize == 4 ? ARM::t2STR_POST
7052 : StSize == 2 ? ARM::t2STRH_POST
7053 : StSize == 1 ? ARM::t2STRB_POST : 0;
7054 return StSize == 4 ? ARM::STR_POST_IMM
7055 : StSize == 2 ? ARM::STRH_POST
7056 : StSize == 1 ? ARM::STRB_POST_IMM : 0;
7059 /// Emit a post-increment load operation with given size. The instructions
7060 /// will be added to BB at Pos.
7061 static void emitPostLd(MachineBasicBlock *BB, MachineInstr *Pos,
7062 const TargetInstrInfo *TII, DebugLoc dl,
7063 unsigned LdSize, unsigned Data, unsigned AddrIn,
7064 unsigned AddrOut, bool IsThumb1, bool IsThumb2) {
7065 unsigned LdOpc = getLdOpcode(LdSize, IsThumb1, IsThumb2);
7066 assert(LdOpc != 0 && "Should have a load opcode");
7068 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
7069 .addReg(AddrOut, RegState::Define).addReg(AddrIn)
7071 } else if (IsThumb1) {
7072 // load + update AddrIn
7073 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
7074 .addReg(AddrIn).addImm(0));
7075 MachineInstrBuilder MIB =
7076 BuildMI(*BB, Pos, dl, TII->get(ARM::tADDi8), AddrOut);
7077 MIB = AddDefaultT1CC(MIB);
7078 MIB.addReg(AddrIn).addImm(LdSize);
7079 AddDefaultPred(MIB);
7080 } else if (IsThumb2) {
7081 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
7082 .addReg(AddrOut, RegState::Define).addReg(AddrIn)
7085 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
7086 .addReg(AddrOut, RegState::Define).addReg(AddrIn)
7087 .addReg(0).addImm(LdSize));
7091 /// Emit a post-increment store operation with given size. The instructions
7092 /// will be added to BB at Pos.
7093 static void emitPostSt(MachineBasicBlock *BB, MachineInstr *Pos,
7094 const TargetInstrInfo *TII, DebugLoc dl,
7095 unsigned StSize, unsigned Data, unsigned AddrIn,
7096 unsigned AddrOut, bool IsThumb1, bool IsThumb2) {
7097 unsigned StOpc = getStOpcode(StSize, IsThumb1, IsThumb2);
7098 assert(StOpc != 0 && "Should have a store opcode");
7100 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
7101 .addReg(AddrIn).addImm(0).addReg(Data));
7102 } else if (IsThumb1) {
7103 // store + update AddrIn
7104 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc)).addReg(Data)
7105 .addReg(AddrIn).addImm(0));
7106 MachineInstrBuilder MIB =
7107 BuildMI(*BB, Pos, dl, TII->get(ARM::tADDi8), AddrOut);
7108 MIB = AddDefaultT1CC(MIB);
7109 MIB.addReg(AddrIn).addImm(StSize);
7110 AddDefaultPred(MIB);
7111 } else if (IsThumb2) {
7112 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
7113 .addReg(Data).addReg(AddrIn).addImm(StSize));
7115 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
7116 .addReg(Data).addReg(AddrIn).addReg(0)
7122 ARMTargetLowering::EmitStructByval(MachineInstr *MI,
7123 MachineBasicBlock *BB) const {
7124 // This pseudo instruction has 3 operands: dst, src, size
7125 // We expand it to a loop if size > Subtarget->getMaxInlineSizeThreshold().
7126 // Otherwise, we will generate unrolled scalar copies.
7127 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
7128 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7129 MachineFunction::iterator It = BB;
7132 unsigned dest = MI->getOperand(0).getReg();
7133 unsigned src = MI->getOperand(1).getReg();
7134 unsigned SizeVal = MI->getOperand(2).getImm();
7135 unsigned Align = MI->getOperand(3).getImm();
7136 DebugLoc dl = MI->getDebugLoc();
7138 MachineFunction *MF = BB->getParent();
7139 MachineRegisterInfo &MRI = MF->getRegInfo();
7140 unsigned UnitSize = 0;
7141 const TargetRegisterClass *TRC = nullptr;
7142 const TargetRegisterClass *VecTRC = nullptr;
7144 bool IsThumb1 = Subtarget->isThumb1Only();
7145 bool IsThumb2 = Subtarget->isThumb2();
7149 } else if (Align & 2) {
7152 // Check whether we can use NEON instructions.
7153 if (!MF->getFunction()->hasFnAttribute(Attribute::NoImplicitFloat) &&
7154 Subtarget->hasNEON()) {
7155 if ((Align % 16 == 0) && SizeVal >= 16)
7157 else if ((Align % 8 == 0) && SizeVal >= 8)
7160 // Can't use NEON instructions.
7165 // Select the correct opcode and register class for unit size load/store
7166 bool IsNeon = UnitSize >= 8;
7167 TRC = (IsThumb1 || IsThumb2) ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
7169 VecTRC = UnitSize == 16 ? &ARM::DPairRegClass
7170 : UnitSize == 8 ? &ARM::DPRRegClass
7173 unsigned BytesLeft = SizeVal % UnitSize;
7174 unsigned LoopSize = SizeVal - BytesLeft;
7176 if (SizeVal <= Subtarget->getMaxInlineSizeThreshold()) {
7177 // Use LDR and STR to copy.
7178 // [scratch, srcOut] = LDR_POST(srcIn, UnitSize)
7179 // [destOut] = STR_POST(scratch, destIn, UnitSize)
7180 unsigned srcIn = src;
7181 unsigned destIn = dest;
7182 for (unsigned i = 0; i < LoopSize; i+=UnitSize) {
7183 unsigned srcOut = MRI.createVirtualRegister(TRC);
7184 unsigned destOut = MRI.createVirtualRegister(TRC);
7185 unsigned scratch = MRI.createVirtualRegister(IsNeon ? VecTRC : TRC);
7186 emitPostLd(BB, MI, TII, dl, UnitSize, scratch, srcIn, srcOut,
7187 IsThumb1, IsThumb2);
7188 emitPostSt(BB, MI, TII, dl, UnitSize, scratch, destIn, destOut,
7189 IsThumb1, IsThumb2);
7194 // Handle the leftover bytes with LDRB and STRB.
7195 // [scratch, srcOut] = LDRB_POST(srcIn, 1)
7196 // [destOut] = STRB_POST(scratch, destIn, 1)
7197 for (unsigned i = 0; i < BytesLeft; i++) {
7198 unsigned srcOut = MRI.createVirtualRegister(TRC);
7199 unsigned destOut = MRI.createVirtualRegister(TRC);
7200 unsigned scratch = MRI.createVirtualRegister(TRC);
7201 emitPostLd(BB, MI, TII, dl, 1, scratch, srcIn, srcOut,
7202 IsThumb1, IsThumb2);
7203 emitPostSt(BB, MI, TII, dl, 1, scratch, destIn, destOut,
7204 IsThumb1, IsThumb2);
7208 MI->eraseFromParent(); // The instruction is gone now.
7212 // Expand the pseudo op to a loop.
7215 // movw varEnd, # --> with thumb2
7217 // ldrcp varEnd, idx --> without thumb2
7218 // fallthrough --> loopMBB
7220 // PHI varPhi, varEnd, varLoop
7221 // PHI srcPhi, src, srcLoop
7222 // PHI destPhi, dst, destLoop
7223 // [scratch, srcLoop] = LDR_POST(srcPhi, UnitSize)
7224 // [destLoop] = STR_POST(scratch, destPhi, UnitSize)
7225 // subs varLoop, varPhi, #UnitSize
7227 // fallthrough --> exitMBB
7229 // epilogue to handle left-over bytes
7230 // [scratch, srcOut] = LDRB_POST(srcLoop, 1)
7231 // [destOut] = STRB_POST(scratch, destLoop, 1)
7232 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
7233 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
7234 MF->insert(It, loopMBB);
7235 MF->insert(It, exitMBB);
7237 // Transfer the remainder of BB and its successor edges to exitMBB.
7238 exitMBB->splice(exitMBB->begin(), BB,
7239 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7240 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7242 // Load an immediate to varEnd.
7243 unsigned varEnd = MRI.createVirtualRegister(TRC);
7244 if (Subtarget->useMovt(*MF)) {
7245 unsigned Vtmp = varEnd;
7246 if ((LoopSize & 0xFFFF0000) != 0)
7247 Vtmp = MRI.createVirtualRegister(TRC);
7248 AddDefaultPred(BuildMI(BB, dl,
7249 TII->get(IsThumb2 ? ARM::t2MOVi16 : ARM::MOVi16),
7250 Vtmp).addImm(LoopSize & 0xFFFF));
7252 if ((LoopSize & 0xFFFF0000) != 0)
7253 AddDefaultPred(BuildMI(BB, dl,
7254 TII->get(IsThumb2 ? ARM::t2MOVTi16 : ARM::MOVTi16),
7257 .addImm(LoopSize >> 16));
7259 MachineConstantPool *ConstantPool = MF->getConstantPool();
7260 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
7261 const Constant *C = ConstantInt::get(Int32Ty, LoopSize);
7263 // MachineConstantPool wants an explicit alignment.
7264 unsigned Align = getDataLayout()->getPrefTypeAlignment(Int32Ty);
7266 Align = getDataLayout()->getTypeAllocSize(C->getType());
7267 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
7270 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(ARM::tLDRpci)).addReg(
7271 varEnd, RegState::Define).addConstantPoolIndex(Idx));
7273 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(ARM::LDRcp)).addReg(
7274 varEnd, RegState::Define).addConstantPoolIndex(Idx).addImm(0));
7276 BB->addSuccessor(loopMBB);
7278 // Generate the loop body:
7279 // varPhi = PHI(varLoop, varEnd)
7280 // srcPhi = PHI(srcLoop, src)
7281 // destPhi = PHI(destLoop, dst)
7282 MachineBasicBlock *entryBB = BB;
7284 unsigned varLoop = MRI.createVirtualRegister(TRC);
7285 unsigned varPhi = MRI.createVirtualRegister(TRC);
7286 unsigned srcLoop = MRI.createVirtualRegister(TRC);
7287 unsigned srcPhi = MRI.createVirtualRegister(TRC);
7288 unsigned destLoop = MRI.createVirtualRegister(TRC);
7289 unsigned destPhi = MRI.createVirtualRegister(TRC);
7291 BuildMI(*BB, BB->begin(), dl, TII->get(ARM::PHI), varPhi)
7292 .addReg(varLoop).addMBB(loopMBB)
7293 .addReg(varEnd).addMBB(entryBB);
7294 BuildMI(BB, dl, TII->get(ARM::PHI), srcPhi)
7295 .addReg(srcLoop).addMBB(loopMBB)
7296 .addReg(src).addMBB(entryBB);
7297 BuildMI(BB, dl, TII->get(ARM::PHI), destPhi)
7298 .addReg(destLoop).addMBB(loopMBB)
7299 .addReg(dest).addMBB(entryBB);
7301 // [scratch, srcLoop] = LDR_POST(srcPhi, UnitSize)
7302 // [destLoop] = STR_POST(scratch, destPhi, UnitSiz)
7303 unsigned scratch = MRI.createVirtualRegister(IsNeon ? VecTRC : TRC);
7304 emitPostLd(BB, BB->end(), TII, dl, UnitSize, scratch, srcPhi, srcLoop,
7305 IsThumb1, IsThumb2);
7306 emitPostSt(BB, BB->end(), TII, dl, UnitSize, scratch, destPhi, destLoop,
7307 IsThumb1, IsThumb2);
7309 // Decrement loop variable by UnitSize.
7311 MachineInstrBuilder MIB =
7312 BuildMI(*BB, BB->end(), dl, TII->get(ARM::tSUBi8), varLoop);
7313 MIB = AddDefaultT1CC(MIB);
7314 MIB.addReg(varPhi).addImm(UnitSize);
7315 AddDefaultPred(MIB);
7317 MachineInstrBuilder MIB =
7318 BuildMI(*BB, BB->end(), dl,
7319 TII->get(IsThumb2 ? ARM::t2SUBri : ARM::SUBri), varLoop);
7320 AddDefaultCC(AddDefaultPred(MIB.addReg(varPhi).addImm(UnitSize)));
7321 MIB->getOperand(5).setReg(ARM::CPSR);
7322 MIB->getOperand(5).setIsDef(true);
7324 BuildMI(*BB, BB->end(), dl,
7325 TII->get(IsThumb1 ? ARM::tBcc : IsThumb2 ? ARM::t2Bcc : ARM::Bcc))
7326 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
7328 // loopMBB can loop back to loopMBB or fall through to exitMBB.
7329 BB->addSuccessor(loopMBB);
7330 BB->addSuccessor(exitMBB);
7332 // Add epilogue to handle BytesLeft.
7334 MachineInstr *StartOfExit = exitMBB->begin();
7336 // [scratch, srcOut] = LDRB_POST(srcLoop, 1)
7337 // [destOut] = STRB_POST(scratch, destLoop, 1)
7338 unsigned srcIn = srcLoop;
7339 unsigned destIn = destLoop;
7340 for (unsigned i = 0; i < BytesLeft; i++) {
7341 unsigned srcOut = MRI.createVirtualRegister(TRC);
7342 unsigned destOut = MRI.createVirtualRegister(TRC);
7343 unsigned scratch = MRI.createVirtualRegister(TRC);
7344 emitPostLd(BB, StartOfExit, TII, dl, 1, scratch, srcIn, srcOut,
7345 IsThumb1, IsThumb2);
7346 emitPostSt(BB, StartOfExit, TII, dl, 1, scratch, destIn, destOut,
7347 IsThumb1, IsThumb2);
7352 MI->eraseFromParent(); // The instruction is gone now.
7357 ARMTargetLowering::EmitLowered__chkstk(MachineInstr *MI,
7358 MachineBasicBlock *MBB) const {
7359 const TargetMachine &TM = getTargetMachine();
7360 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
7361 DebugLoc DL = MI->getDebugLoc();
7363 assert(Subtarget->isTargetWindows() &&
7364 "__chkstk is only supported on Windows");
7365 assert(Subtarget->isThumb2() && "Windows on ARM requires Thumb-2 mode");
7367 // __chkstk takes the number of words to allocate on the stack in R4, and
7368 // returns the stack adjustment in number of bytes in R4. This will not
7369 // clober any other registers (other than the obvious lr).
7371 // Although, technically, IP should be considered a register which may be
7372 // clobbered, the call itself will not touch it. Windows on ARM is a pure
7373 // thumb-2 environment, so there is no interworking required. As a result, we
7374 // do not expect a veneer to be emitted by the linker, clobbering IP.
7376 // Each module receives its own copy of __chkstk, so no import thunk is
7377 // required, again, ensuring that IP is not clobbered.
7379 // Finally, although some linkers may theoretically provide a trampoline for
7380 // out of range calls (which is quite common due to a 32M range limitation of
7381 // branches for Thumb), we can generate the long-call version via
7382 // -mcmodel=large, alleviating the need for the trampoline which may clobber
7385 switch (TM.getCodeModel()) {
7386 case CodeModel::Small:
7387 case CodeModel::Medium:
7388 case CodeModel::Default:
7389 case CodeModel::Kernel:
7390 BuildMI(*MBB, MI, DL, TII.get(ARM::tBL))
7391 .addImm((unsigned)ARMCC::AL).addReg(0)
7392 .addExternalSymbol("__chkstk")
7393 .addReg(ARM::R4, RegState::Implicit | RegState::Kill)
7394 .addReg(ARM::R4, RegState::Implicit | RegState::Define)
7395 .addReg(ARM::R12, RegState::Implicit | RegState::Define | RegState::Dead);
7397 case CodeModel::Large:
7398 case CodeModel::JITDefault: {
7399 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
7400 unsigned Reg = MRI.createVirtualRegister(&ARM::rGPRRegClass);
7402 BuildMI(*MBB, MI, DL, TII.get(ARM::t2MOVi32imm), Reg)
7403 .addExternalSymbol("__chkstk");
7404 BuildMI(*MBB, MI, DL, TII.get(ARM::tBLXr))
7405 .addImm((unsigned)ARMCC::AL).addReg(0)
7406 .addReg(Reg, RegState::Kill)
7407 .addReg(ARM::R4, RegState::Implicit | RegState::Kill)
7408 .addReg(ARM::R4, RegState::Implicit | RegState::Define)
7409 .addReg(ARM::R12, RegState::Implicit | RegState::Define | RegState::Dead);
7414 AddDefaultCC(AddDefaultPred(BuildMI(*MBB, MI, DL, TII.get(ARM::t2SUBrr),
7416 .addReg(ARM::SP).addReg(ARM::R4)));
7418 MI->eraseFromParent();
7423 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
7424 MachineBasicBlock *BB) const {
7425 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
7426 DebugLoc dl = MI->getDebugLoc();
7427 bool isThumb2 = Subtarget->isThumb2();
7428 switch (MI->getOpcode()) {
7431 llvm_unreachable("Unexpected instr type to insert");
7433 // The Thumb2 pre-indexed stores have the same MI operands, they just
7434 // define them differently in the .td files from the isel patterns, so
7435 // they need pseudos.
7436 case ARM::t2STR_preidx:
7437 MI->setDesc(TII->get(ARM::t2STR_PRE));
7439 case ARM::t2STRB_preidx:
7440 MI->setDesc(TII->get(ARM::t2STRB_PRE));
7442 case ARM::t2STRH_preidx:
7443 MI->setDesc(TII->get(ARM::t2STRH_PRE));
7446 case ARM::STRi_preidx:
7447 case ARM::STRBi_preidx: {
7448 unsigned NewOpc = MI->getOpcode() == ARM::STRi_preidx ?
7449 ARM::STR_PRE_IMM : ARM::STRB_PRE_IMM;
7450 // Decode the offset.
7451 unsigned Offset = MI->getOperand(4).getImm();
7452 bool isSub = ARM_AM::getAM2Op(Offset) == ARM_AM::sub;
7453 Offset = ARM_AM::getAM2Offset(Offset);
7457 MachineMemOperand *MMO = *MI->memoperands_begin();
7458 BuildMI(*BB, MI, dl, TII->get(NewOpc))
7459 .addOperand(MI->getOperand(0)) // Rn_wb
7460 .addOperand(MI->getOperand(1)) // Rt
7461 .addOperand(MI->getOperand(2)) // Rn
7462 .addImm(Offset) // offset (skip GPR==zero_reg)
7463 .addOperand(MI->getOperand(5)) // pred
7464 .addOperand(MI->getOperand(6))
7465 .addMemOperand(MMO);
7466 MI->eraseFromParent();
7469 case ARM::STRr_preidx:
7470 case ARM::STRBr_preidx:
7471 case ARM::STRH_preidx: {
7473 switch (MI->getOpcode()) {
7474 default: llvm_unreachable("unexpected opcode!");
7475 case ARM::STRr_preidx: NewOpc = ARM::STR_PRE_REG; break;
7476 case ARM::STRBr_preidx: NewOpc = ARM::STRB_PRE_REG; break;
7477 case ARM::STRH_preidx: NewOpc = ARM::STRH_PRE; break;
7479 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc));
7480 for (unsigned i = 0; i < MI->getNumOperands(); ++i)
7481 MIB.addOperand(MI->getOperand(i));
7482 MI->eraseFromParent();
7486 case ARM::tMOVCCr_pseudo: {
7487 // To "insert" a SELECT_CC instruction, we actually have to insert the
7488 // diamond control-flow pattern. The incoming instruction knows the
7489 // destination vreg to set, the condition code register to branch on, the
7490 // true/false values to select between, and a branch opcode to use.
7491 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7492 MachineFunction::iterator It = BB;
7498 // cmpTY ccX, r1, r2
7500 // fallthrough --> copy0MBB
7501 MachineBasicBlock *thisMBB = BB;
7502 MachineFunction *F = BB->getParent();
7503 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7504 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7505 F->insert(It, copy0MBB);
7506 F->insert(It, sinkMBB);
7508 // Transfer the remainder of BB and its successor edges to sinkMBB.
7509 sinkMBB->splice(sinkMBB->begin(), BB,
7510 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7511 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
7513 BB->addSuccessor(copy0MBB);
7514 BB->addSuccessor(sinkMBB);
7516 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
7517 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
7520 // %FalseValue = ...
7521 // # fallthrough to sinkMBB
7524 // Update machine-CFG edges
7525 BB->addSuccessor(sinkMBB);
7528 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7531 BuildMI(*BB, BB->begin(), dl,
7532 TII->get(ARM::PHI), MI->getOperand(0).getReg())
7533 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
7534 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7536 MI->eraseFromParent(); // The pseudo instruction is gone now.
7541 case ARM::BCCZi64: {
7542 // If there is an unconditional branch to the other successor, remove it.
7543 BB->erase(std::next(MachineBasicBlock::iterator(MI)), BB->end());
7545 // Compare both parts that make up the double comparison separately for
7547 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
7549 unsigned LHS1 = MI->getOperand(1).getReg();
7550 unsigned LHS2 = MI->getOperand(2).getReg();
7552 AddDefaultPred(BuildMI(BB, dl,
7553 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
7554 .addReg(LHS1).addImm(0));
7555 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
7556 .addReg(LHS2).addImm(0)
7557 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
7559 unsigned RHS1 = MI->getOperand(3).getReg();
7560 unsigned RHS2 = MI->getOperand(4).getReg();
7561 AddDefaultPred(BuildMI(BB, dl,
7562 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
7563 .addReg(LHS1).addReg(RHS1));
7564 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
7565 .addReg(LHS2).addReg(RHS2)
7566 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
7569 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB();
7570 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
7571 if (MI->getOperand(0).getImm() == ARMCC::NE)
7572 std::swap(destMBB, exitMBB);
7574 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
7575 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
7577 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2B)).addMBB(exitMBB));
7579 BuildMI(BB, dl, TII->get(ARM::B)) .addMBB(exitMBB);
7581 MI->eraseFromParent(); // The pseudo instruction is gone now.
7585 case ARM::Int_eh_sjlj_setjmp:
7586 case ARM::Int_eh_sjlj_setjmp_nofp:
7587 case ARM::tInt_eh_sjlj_setjmp:
7588 case ARM::t2Int_eh_sjlj_setjmp:
7589 case ARM::t2Int_eh_sjlj_setjmp_nofp:
7590 EmitSjLjDispatchBlock(MI, BB);
7595 // To insert an ABS instruction, we have to insert the
7596 // diamond control-flow pattern. The incoming instruction knows the
7597 // source vreg to test against 0, the destination vreg to set,
7598 // the condition code register to branch on, the
7599 // true/false values to select between, and a branch opcode to use.
7604 // BCC (branch to SinkBB if V0 >= 0)
7605 // RSBBB: V3 = RSBri V2, 0 (compute ABS if V2 < 0)
7606 // SinkBB: V1 = PHI(V2, V3)
7607 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7608 MachineFunction::iterator BBI = BB;
7610 MachineFunction *Fn = BB->getParent();
7611 MachineBasicBlock *RSBBB = Fn->CreateMachineBasicBlock(LLVM_BB);
7612 MachineBasicBlock *SinkBB = Fn->CreateMachineBasicBlock(LLVM_BB);
7613 Fn->insert(BBI, RSBBB);
7614 Fn->insert(BBI, SinkBB);
7616 unsigned int ABSSrcReg = MI->getOperand(1).getReg();
7617 unsigned int ABSDstReg = MI->getOperand(0).getReg();
7618 bool ABSSrcKIll = MI->getOperand(1).isKill();
7619 bool isThumb2 = Subtarget->isThumb2();
7620 MachineRegisterInfo &MRI = Fn->getRegInfo();
7621 // In Thumb mode S must not be specified if source register is the SP or
7622 // PC and if destination register is the SP, so restrict register class
7623 unsigned NewRsbDstReg =
7624 MRI.createVirtualRegister(isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass);
7626 // Transfer the remainder of BB and its successor edges to sinkMBB.
7627 SinkBB->splice(SinkBB->begin(), BB,
7628 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7629 SinkBB->transferSuccessorsAndUpdatePHIs(BB);
7631 BB->addSuccessor(RSBBB);
7632 BB->addSuccessor(SinkBB);
7634 // fall through to SinkMBB
7635 RSBBB->addSuccessor(SinkBB);
7637 // insert a cmp at the end of BB
7638 AddDefaultPred(BuildMI(BB, dl,
7639 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
7640 .addReg(ABSSrcReg).addImm(0));
7642 // insert a bcc with opposite CC to ARMCC::MI at the end of BB
7644 TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)).addMBB(SinkBB)
7645 .addImm(ARMCC::getOppositeCondition(ARMCC::MI)).addReg(ARM::CPSR);
7647 // insert rsbri in RSBBB
7648 // Note: BCC and rsbri will be converted into predicated rsbmi
7649 // by if-conversion pass
7650 BuildMI(*RSBBB, RSBBB->begin(), dl,
7651 TII->get(isThumb2 ? ARM::t2RSBri : ARM::RSBri), NewRsbDstReg)
7652 .addReg(ABSSrcReg, ABSSrcKIll ? RegState::Kill : 0)
7653 .addImm(0).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
7655 // insert PHI in SinkBB,
7656 // reuse ABSDstReg to not change uses of ABS instruction
7657 BuildMI(*SinkBB, SinkBB->begin(), dl,
7658 TII->get(ARM::PHI), ABSDstReg)
7659 .addReg(NewRsbDstReg).addMBB(RSBBB)
7660 .addReg(ABSSrcReg).addMBB(BB);
7662 // remove ABS instruction
7663 MI->eraseFromParent();
7665 // return last added BB
7668 case ARM::COPY_STRUCT_BYVAL_I32:
7670 return EmitStructByval(MI, BB);
7671 case ARM::WIN__CHKSTK:
7672 return EmitLowered__chkstk(MI, BB);
7676 void ARMTargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
7677 SDNode *Node) const {
7678 const MCInstrDesc *MCID = &MI->getDesc();
7679 // Adjust potentially 's' setting instructions after isel, i.e. ADC, SBC, RSB,
7680 // RSC. Coming out of isel, they have an implicit CPSR def, but the optional
7681 // operand is still set to noreg. If needed, set the optional operand's
7682 // register to CPSR, and remove the redundant implicit def.
7684 // e.g. ADCS (..., CPSR<imp-def>) -> ADC (... opt:CPSR<def>).
7686 // Rename pseudo opcodes.
7687 unsigned NewOpc = convertAddSubFlagsOpcode(MI->getOpcode());
7689 const ARMBaseInstrInfo *TII = Subtarget->getInstrInfo();
7690 MCID = &TII->get(NewOpc);
7692 assert(MCID->getNumOperands() == MI->getDesc().getNumOperands() + 1 &&
7693 "converted opcode should be the same except for cc_out");
7697 // Add the optional cc_out operand
7698 MI->addOperand(MachineOperand::CreateReg(0, /*isDef=*/true));
7700 unsigned ccOutIdx = MCID->getNumOperands() - 1;
7702 // Any ARM instruction that sets the 's' bit should specify an optional
7703 // "cc_out" operand in the last operand position.
7704 if (!MI->hasOptionalDef() || !MCID->OpInfo[ccOutIdx].isOptionalDef()) {
7705 assert(!NewOpc && "Optional cc_out operand required");
7708 // Look for an implicit def of CPSR added by MachineInstr ctor. Remove it
7709 // since we already have an optional CPSR def.
7710 bool definesCPSR = false;
7711 bool deadCPSR = false;
7712 for (unsigned i = MCID->getNumOperands(), e = MI->getNumOperands();
7714 const MachineOperand &MO = MI->getOperand(i);
7715 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) {
7719 MI->RemoveOperand(i);
7724 assert(!NewOpc && "Optional cc_out operand required");
7727 assert(deadCPSR == !Node->hasAnyUseOfValue(1) && "inconsistent dead flag");
7729 assert(!MI->getOperand(ccOutIdx).getReg() &&
7730 "expect uninitialized optional cc_out operand");
7734 // If this instruction was defined with an optional CPSR def and its dag node
7735 // had a live implicit CPSR def, then activate the optional CPSR def.
7736 MachineOperand &MO = MI->getOperand(ccOutIdx);
7737 MO.setReg(ARM::CPSR);
7741 //===----------------------------------------------------------------------===//
7742 // ARM Optimization Hooks
7743 //===----------------------------------------------------------------------===//
7745 // Helper function that checks if N is a null or all ones constant.
7746 static inline bool isZeroOrAllOnes(SDValue N, bool AllOnes) {
7747 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
7750 return AllOnes ? C->isAllOnesValue() : C->isNullValue();
7753 // Return true if N is conditionally 0 or all ones.
7754 // Detects these expressions where cc is an i1 value:
7756 // (select cc 0, y) [AllOnes=0]
7757 // (select cc y, 0) [AllOnes=0]
7758 // (zext cc) [AllOnes=0]
7759 // (sext cc) [AllOnes=0/1]
7760 // (select cc -1, y) [AllOnes=1]
7761 // (select cc y, -1) [AllOnes=1]
7763 // Invert is set when N is the null/all ones constant when CC is false.
7764 // OtherOp is set to the alternative value of N.
7765 static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes,
7766 SDValue &CC, bool &Invert,
7768 SelectionDAG &DAG) {
7769 switch (N->getOpcode()) {
7770 default: return false;
7772 CC = N->getOperand(0);
7773 SDValue N1 = N->getOperand(1);
7774 SDValue N2 = N->getOperand(2);
7775 if (isZeroOrAllOnes(N1, AllOnes)) {
7780 if (isZeroOrAllOnes(N2, AllOnes)) {
7787 case ISD::ZERO_EXTEND:
7788 // (zext cc) can never be the all ones value.
7792 case ISD::SIGN_EXTEND: {
7794 EVT VT = N->getValueType(0);
7795 CC = N->getOperand(0);
7796 if (CC.getValueType() != MVT::i1)
7800 // When looking for an AllOnes constant, N is an sext, and the 'other'
7802 OtherOp = DAG.getConstant(0, dl, VT);
7803 else if (N->getOpcode() == ISD::ZERO_EXTEND)
7804 // When looking for a 0 constant, N can be zext or sext.
7805 OtherOp = DAG.getConstant(1, dl, VT);
7807 OtherOp = DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), dl,
7814 // Combine a constant select operand into its use:
7816 // (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
7817 // (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
7818 // (and (select cc, -1, c), x) -> (select cc, x, (and, x, c)) [AllOnes=1]
7819 // (or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
7820 // (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
7822 // The transform is rejected if the select doesn't have a constant operand that
7823 // is null, or all ones when AllOnes is set.
7825 // Also recognize sext/zext from i1:
7827 // (add (zext cc), x) -> (select cc (add x, 1), x)
7828 // (add (sext cc), x) -> (select cc (add x, -1), x)
7830 // These transformations eventually create predicated instructions.
7832 // @param N The node to transform.
7833 // @param Slct The N operand that is a select.
7834 // @param OtherOp The other N operand (x above).
7835 // @param DCI Context.
7836 // @param AllOnes Require the select constant to be all ones instead of null.
7837 // @returns The new node, or SDValue() on failure.
7839 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
7840 TargetLowering::DAGCombinerInfo &DCI,
7841 bool AllOnes = false) {
7842 SelectionDAG &DAG = DCI.DAG;
7843 EVT VT = N->getValueType(0);
7844 SDValue NonConstantVal;
7847 if (!isConditionalZeroOrAllOnes(Slct.getNode(), AllOnes, CCOp, SwapSelectOps,
7848 NonConstantVal, DAG))
7851 // Slct is now know to be the desired identity constant when CC is true.
7852 SDValue TrueVal = OtherOp;
7853 SDValue FalseVal = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
7854 OtherOp, NonConstantVal);
7855 // Unless SwapSelectOps says CC should be false.
7857 std::swap(TrueVal, FalseVal);
7859 return DAG.getNode(ISD::SELECT, SDLoc(N), VT,
7860 CCOp, TrueVal, FalseVal);
7863 // Attempt combineSelectAndUse on each operand of a commutative operator N.
7865 SDValue combineSelectAndUseCommutative(SDNode *N, bool AllOnes,
7866 TargetLowering::DAGCombinerInfo &DCI) {
7867 SDValue N0 = N->getOperand(0);
7868 SDValue N1 = N->getOperand(1);
7869 if (N0.getNode()->hasOneUse()) {
7870 SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes);
7871 if (Result.getNode())
7874 if (N1.getNode()->hasOneUse()) {
7875 SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes);
7876 if (Result.getNode())
7882 // AddCombineToVPADDL- For pair-wise add on neon, use the vpaddl instruction
7883 // (only after legalization).
7884 static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1,
7885 TargetLowering::DAGCombinerInfo &DCI,
7886 const ARMSubtarget *Subtarget) {
7888 // Only perform optimization if after legalize, and if NEON is available. We
7889 // also expected both operands to be BUILD_VECTORs.
7890 if (DCI.isBeforeLegalize() || !Subtarget->hasNEON()
7891 || N0.getOpcode() != ISD::BUILD_VECTOR
7892 || N1.getOpcode() != ISD::BUILD_VECTOR)
7895 // Check output type since VPADDL operand elements can only be 8, 16, or 32.
7896 EVT VT = N->getValueType(0);
7897 if (!VT.isInteger() || VT.getVectorElementType() == MVT::i64)
7900 // Check that the vector operands are of the right form.
7901 // N0 and N1 are BUILD_VECTOR nodes with N number of EXTRACT_VECTOR
7902 // operands, where N is the size of the formed vector.
7903 // Each EXTRACT_VECTOR should have the same input vector and odd or even
7904 // index such that we have a pair wise add pattern.
7906 // Grab the vector that all EXTRACT_VECTOR nodes should be referencing.
7907 if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
7909 SDValue Vec = N0->getOperand(0)->getOperand(0);
7910 SDNode *V = Vec.getNode();
7911 unsigned nextIndex = 0;
7913 // For each operands to the ADD which are BUILD_VECTORs,
7914 // check to see if each of their operands are an EXTRACT_VECTOR with
7915 // the same vector and appropriate index.
7916 for (unsigned i = 0, e = N0->getNumOperands(); i != e; ++i) {
7917 if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT
7918 && N1->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
7920 SDValue ExtVec0 = N0->getOperand(i);
7921 SDValue ExtVec1 = N1->getOperand(i);
7923 // First operand is the vector, verify its the same.
7924 if (V != ExtVec0->getOperand(0).getNode() ||
7925 V != ExtVec1->getOperand(0).getNode())
7928 // Second is the constant, verify its correct.
7929 ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(ExtVec0->getOperand(1));
7930 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(ExtVec1->getOperand(1));
7932 // For the constant, we want to see all the even or all the odd.
7933 if (!C0 || !C1 || C0->getZExtValue() != nextIndex
7934 || C1->getZExtValue() != nextIndex+1)
7943 // Create VPADDL node.
7944 SelectionDAG &DAG = DCI.DAG;
7945 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7949 // Build operand list.
7950 SmallVector<SDValue, 8> Ops;
7951 Ops.push_back(DAG.getConstant(Intrinsic::arm_neon_vpaddls, dl,
7952 TLI.getPointerTy()));
7954 // Input is the vector.
7957 // Get widened type and narrowed type.
7959 unsigned numElem = VT.getVectorNumElements();
7961 EVT inputLaneType = Vec.getValueType().getVectorElementType();
7962 switch (inputLaneType.getSimpleVT().SimpleTy) {
7963 case MVT::i8: widenType = MVT::getVectorVT(MVT::i16, numElem); break;
7964 case MVT::i16: widenType = MVT::getVectorVT(MVT::i32, numElem); break;
7965 case MVT::i32: widenType = MVT::getVectorVT(MVT::i64, numElem); break;
7967 llvm_unreachable("Invalid vector element type for padd optimization.");
7970 SDValue tmp = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, widenType, Ops);
7971 unsigned ExtOp = VT.bitsGT(tmp.getValueType()) ? ISD::ANY_EXTEND : ISD::TRUNCATE;
7972 return DAG.getNode(ExtOp, dl, VT, tmp);
7975 static SDValue findMUL_LOHI(SDValue V) {
7976 if (V->getOpcode() == ISD::UMUL_LOHI ||
7977 V->getOpcode() == ISD::SMUL_LOHI)
7982 static SDValue AddCombineTo64bitMLAL(SDNode *AddcNode,
7983 TargetLowering::DAGCombinerInfo &DCI,
7984 const ARMSubtarget *Subtarget) {
7986 if (Subtarget->isThumb1Only()) return SDValue();
7988 // Only perform the checks after legalize when the pattern is available.
7989 if (DCI.isBeforeLegalize()) return SDValue();
7991 // Look for multiply add opportunities.
7992 // The pattern is a ISD::UMUL_LOHI followed by two add nodes, where
7993 // each add nodes consumes a value from ISD::UMUL_LOHI and there is
7994 // a glue link from the first add to the second add.
7995 // If we find this pattern, we can replace the U/SMUL_LOHI, ADDC, and ADDE by
7996 // a S/UMLAL instruction.
7999 // / \ [no multiline comment]
8005 assert(AddcNode->getOpcode() == ISD::ADDC && "Expect an ADDC");
8006 SDValue AddcOp0 = AddcNode->getOperand(0);
8007 SDValue AddcOp1 = AddcNode->getOperand(1);
8009 // Check if the two operands are from the same mul_lohi node.
8010 if (AddcOp0.getNode() == AddcOp1.getNode())
8013 assert(AddcNode->getNumValues() == 2 &&
8014 AddcNode->getValueType(0) == MVT::i32 &&
8015 "Expect ADDC with two result values. First: i32");
8017 // Check that we have a glued ADDC node.
8018 if (AddcNode->getValueType(1) != MVT::Glue)
8021 // Check that the ADDC adds the low result of the S/UMUL_LOHI.
8022 if (AddcOp0->getOpcode() != ISD::UMUL_LOHI &&
8023 AddcOp0->getOpcode() != ISD::SMUL_LOHI &&
8024 AddcOp1->getOpcode() != ISD::UMUL_LOHI &&
8025 AddcOp1->getOpcode() != ISD::SMUL_LOHI)
8028 // Look for the glued ADDE.
8029 SDNode* AddeNode = AddcNode->getGluedUser();
8033 // Make sure it is really an ADDE.
8034 if (AddeNode->getOpcode() != ISD::ADDE)
8037 assert(AddeNode->getNumOperands() == 3 &&
8038 AddeNode->getOperand(2).getValueType() == MVT::Glue &&
8039 "ADDE node has the wrong inputs");
8041 // Check for the triangle shape.
8042 SDValue AddeOp0 = AddeNode->getOperand(0);
8043 SDValue AddeOp1 = AddeNode->getOperand(1);
8045 // Make sure that the ADDE operands are not coming from the same node.
8046 if (AddeOp0.getNode() == AddeOp1.getNode())
8049 // Find the MUL_LOHI node walking up ADDE's operands.
8050 bool IsLeftOperandMUL = false;
8051 SDValue MULOp = findMUL_LOHI(AddeOp0);
8052 if (MULOp == SDValue())
8053 MULOp = findMUL_LOHI(AddeOp1);
8055 IsLeftOperandMUL = true;
8056 if (MULOp == SDValue())
8059 // Figure out the right opcode.
8060 unsigned Opc = MULOp->getOpcode();
8061 unsigned FinalOpc = (Opc == ISD::SMUL_LOHI) ? ARMISD::SMLAL : ARMISD::UMLAL;
8063 // Figure out the high and low input values to the MLAL node.
8064 SDValue* HiAdd = nullptr;
8065 SDValue* LoMul = nullptr;
8066 SDValue* LowAdd = nullptr;
8068 // Ensure that ADDE is from high result of ISD::SMUL_LOHI.
8069 if ((AddeOp0 != MULOp.getValue(1)) && (AddeOp1 != MULOp.getValue(1)))
8072 if (IsLeftOperandMUL)
8078 // Ensure that LoMul and LowAdd are taken from correct ISD::SMUL_LOHI node
8079 // whose low result is fed to the ADDC we are checking.
8081 if (AddcOp0 == MULOp.getValue(0)) {
8085 if (AddcOp1 == MULOp.getValue(0)) {
8093 // Create the merged node.
8094 SelectionDAG &DAG = DCI.DAG;
8096 // Build operand list.
8097 SmallVector<SDValue, 8> Ops;
8098 Ops.push_back(LoMul->getOperand(0));
8099 Ops.push_back(LoMul->getOperand(1));
8100 Ops.push_back(*LowAdd);
8101 Ops.push_back(*HiAdd);
8103 SDValue MLALNode = DAG.getNode(FinalOpc, SDLoc(AddcNode),
8104 DAG.getVTList(MVT::i32, MVT::i32), Ops);
8106 // Replace the ADDs' nodes uses by the MLA node's values.
8107 SDValue HiMLALResult(MLALNode.getNode(), 1);
8108 DAG.ReplaceAllUsesOfValueWith(SDValue(AddeNode, 0), HiMLALResult);
8110 SDValue LoMLALResult(MLALNode.getNode(), 0);
8111 DAG.ReplaceAllUsesOfValueWith(SDValue(AddcNode, 0), LoMLALResult);
8113 // Return original node to notify the driver to stop replacing.
8114 SDValue resNode(AddcNode, 0);
8118 /// PerformADDCCombine - Target-specific dag combine transform from
8119 /// ISD::ADDC, ISD::ADDE, and ISD::MUL_LOHI to MLAL.
8120 static SDValue PerformADDCCombine(SDNode *N,
8121 TargetLowering::DAGCombinerInfo &DCI,
8122 const ARMSubtarget *Subtarget) {
8124 return AddCombineTo64bitMLAL(N, DCI, Subtarget);
8128 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
8129 /// operands N0 and N1. This is a helper for PerformADDCombine that is
8130 /// called with the default operands, and if that fails, with commuted
8132 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
8133 TargetLowering::DAGCombinerInfo &DCI,
8134 const ARMSubtarget *Subtarget){
8136 // Attempt to create vpaddl for this add.
8137 SDValue Result = AddCombineToVPADDL(N, N0, N1, DCI, Subtarget);
8138 if (Result.getNode())
8141 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
8142 if (N0.getNode()->hasOneUse()) {
8143 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
8144 if (Result.getNode()) return Result;
8149 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
8151 static SDValue PerformADDCombine(SDNode *N,
8152 TargetLowering::DAGCombinerInfo &DCI,
8153 const ARMSubtarget *Subtarget) {
8154 SDValue N0 = N->getOperand(0);
8155 SDValue N1 = N->getOperand(1);
8157 // First try with the default operand order.
8158 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget);
8159 if (Result.getNode())
8162 // If that didn't work, try again with the operands commuted.
8163 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget);
8166 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
8168 static SDValue PerformSUBCombine(SDNode *N,
8169 TargetLowering::DAGCombinerInfo &DCI) {
8170 SDValue N0 = N->getOperand(0);
8171 SDValue N1 = N->getOperand(1);
8173 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
8174 if (N1.getNode()->hasOneUse()) {
8175 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
8176 if (Result.getNode()) return Result;
8182 /// PerformVMULCombine
8183 /// Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the
8184 /// special multiplier accumulator forwarding.
8190 // However, for (A + B) * (A + B),
8197 static SDValue PerformVMULCombine(SDNode *N,
8198 TargetLowering::DAGCombinerInfo &DCI,
8199 const ARMSubtarget *Subtarget) {
8200 if (!Subtarget->hasVMLxForwarding())
8203 SelectionDAG &DAG = DCI.DAG;
8204 SDValue N0 = N->getOperand(0);
8205 SDValue N1 = N->getOperand(1);
8206 unsigned Opcode = N0.getOpcode();
8207 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
8208 Opcode != ISD::FADD && Opcode != ISD::FSUB) {
8209 Opcode = N1.getOpcode();
8210 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
8211 Opcode != ISD::FADD && Opcode != ISD::FSUB)
8219 EVT VT = N->getValueType(0);
8221 SDValue N00 = N0->getOperand(0);
8222 SDValue N01 = N0->getOperand(1);
8223 return DAG.getNode(Opcode, DL, VT,
8224 DAG.getNode(ISD::MUL, DL, VT, N00, N1),
8225 DAG.getNode(ISD::MUL, DL, VT, N01, N1));
8228 static SDValue PerformMULCombine(SDNode *N,
8229 TargetLowering::DAGCombinerInfo &DCI,
8230 const ARMSubtarget *Subtarget) {
8231 SelectionDAG &DAG = DCI.DAG;
8233 if (Subtarget->isThumb1Only())
8236 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
8239 EVT VT = N->getValueType(0);
8240 if (VT.is64BitVector() || VT.is128BitVector())
8241 return PerformVMULCombine(N, DCI, Subtarget);
8245 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
8249 int64_t MulAmt = C->getSExtValue();
8250 unsigned ShiftAmt = countTrailingZeros<uint64_t>(MulAmt);
8252 ShiftAmt = ShiftAmt & (32 - 1);
8253 SDValue V = N->getOperand(0);
8257 MulAmt >>= ShiftAmt;
8260 if (isPowerOf2_32(MulAmt - 1)) {
8261 // (mul x, 2^N + 1) => (add (shl x, N), x)
8262 Res = DAG.getNode(ISD::ADD, DL, VT,
8264 DAG.getNode(ISD::SHL, DL, VT,
8266 DAG.getConstant(Log2_32(MulAmt - 1), DL,
8268 } else if (isPowerOf2_32(MulAmt + 1)) {
8269 // (mul x, 2^N - 1) => (sub (shl x, N), x)
8270 Res = DAG.getNode(ISD::SUB, DL, VT,
8271 DAG.getNode(ISD::SHL, DL, VT,
8273 DAG.getConstant(Log2_32(MulAmt + 1), DL,
8279 uint64_t MulAmtAbs = -MulAmt;
8280 if (isPowerOf2_32(MulAmtAbs + 1)) {
8281 // (mul x, -(2^N - 1)) => (sub x, (shl x, N))
8282 Res = DAG.getNode(ISD::SUB, DL, VT,
8284 DAG.getNode(ISD::SHL, DL, VT,
8286 DAG.getConstant(Log2_32(MulAmtAbs + 1), DL,
8288 } else if (isPowerOf2_32(MulAmtAbs - 1)) {
8289 // (mul x, -(2^N + 1)) => - (add (shl x, N), x)
8290 Res = DAG.getNode(ISD::ADD, DL, VT,
8292 DAG.getNode(ISD::SHL, DL, VT,
8294 DAG.getConstant(Log2_32(MulAmtAbs - 1), DL,
8296 Res = DAG.getNode(ISD::SUB, DL, VT,
8297 DAG.getConstant(0, DL, MVT::i32), Res);
8304 Res = DAG.getNode(ISD::SHL, DL, VT,
8305 Res, DAG.getConstant(ShiftAmt, DL, MVT::i32));
8307 // Do not add new nodes to DAG combiner worklist.
8308 DCI.CombineTo(N, Res, false);
8312 static SDValue PerformANDCombine(SDNode *N,
8313 TargetLowering::DAGCombinerInfo &DCI,
8314 const ARMSubtarget *Subtarget) {
8316 // Attempt to use immediate-form VBIC
8317 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
8319 EVT VT = N->getValueType(0);
8320 SelectionDAG &DAG = DCI.DAG;
8322 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
8325 APInt SplatBits, SplatUndef;
8326 unsigned SplatBitSize;
8329 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
8330 if (SplatBitSize <= 64) {
8332 SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(),
8333 SplatUndef.getZExtValue(), SplatBitSize,
8334 DAG, dl, VbicVT, VT.is128BitVector(),
8336 if (Val.getNode()) {
8338 DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0));
8339 SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val);
8340 return DAG.getNode(ISD::BITCAST, dl, VT, Vbic);
8345 if (!Subtarget->isThumb1Only()) {
8346 // fold (and (select cc, -1, c), x) -> (select cc, x, (and, x, c))
8347 SDValue Result = combineSelectAndUseCommutative(N, true, DCI);
8348 if (Result.getNode())
8355 /// PerformORCombine - Target-specific dag combine xforms for ISD::OR
8356 static SDValue PerformORCombine(SDNode *N,
8357 TargetLowering::DAGCombinerInfo &DCI,
8358 const ARMSubtarget *Subtarget) {
8359 // Attempt to use immediate-form VORR
8360 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
8362 EVT VT = N->getValueType(0);
8363 SelectionDAG &DAG = DCI.DAG;
8365 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
8368 APInt SplatBits, SplatUndef;
8369 unsigned SplatBitSize;
8371 if (BVN && Subtarget->hasNEON() &&
8372 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
8373 if (SplatBitSize <= 64) {
8375 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
8376 SplatUndef.getZExtValue(), SplatBitSize,
8377 DAG, dl, VorrVT, VT.is128BitVector(),
8379 if (Val.getNode()) {
8381 DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0));
8382 SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val);
8383 return DAG.getNode(ISD::BITCAST, dl, VT, Vorr);
8388 if (!Subtarget->isThumb1Only()) {
8389 // fold (or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
8390 SDValue Result = combineSelectAndUseCommutative(N, false, DCI);
8391 if (Result.getNode())
8395 // The code below optimizes (or (and X, Y), Z).
8396 // The AND operand needs to have a single user to make these optimizations
8398 SDValue N0 = N->getOperand(0);
8399 if (N0.getOpcode() != ISD::AND || !N0.hasOneUse())
8401 SDValue N1 = N->getOperand(1);
8403 // (or (and B, A), (and C, ~A)) => (VBSL A, B, C) when A is a constant.
8404 if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() &&
8405 DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
8407 unsigned SplatBitSize;
8410 APInt SplatBits0, SplatBits1;
8411 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1));
8412 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(1));
8413 // Ensure that the second operand of both ands are constants
8414 if (BVN0 && BVN0->isConstantSplat(SplatBits0, SplatUndef, SplatBitSize,
8415 HasAnyUndefs) && !HasAnyUndefs) {
8416 if (BVN1 && BVN1->isConstantSplat(SplatBits1, SplatUndef, SplatBitSize,
8417 HasAnyUndefs) && !HasAnyUndefs) {
8418 // Ensure that the bit width of the constants are the same and that
8419 // the splat arguments are logical inverses as per the pattern we
8420 // are trying to simplify.
8421 if (SplatBits0.getBitWidth() == SplatBits1.getBitWidth() &&
8422 SplatBits0 == ~SplatBits1) {
8423 // Canonicalize the vector type to make instruction selection
8425 EVT CanonicalVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
8426 SDValue Result = DAG.getNode(ARMISD::VBSL, dl, CanonicalVT,
8430 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
8436 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when
8439 // BFI is only available on V6T2+
8440 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops())
8444 // 1) or (and A, mask), val => ARMbfi A, val, mask
8445 // iff (val & mask) == val
8447 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
8448 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2)
8449 // && mask == ~mask2
8450 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2)
8451 // && ~mask == mask2
8452 // (i.e., copy a bitfield value into another bitfield of the same width)
8457 SDValue N00 = N0.getOperand(0);
8459 // The value and the mask need to be constants so we can verify this is
8460 // actually a bitfield set. If the mask is 0xffff, we can do better
8461 // via a movt instruction, so don't use BFI in that case.
8462 SDValue MaskOp = N0.getOperand(1);
8463 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(MaskOp);
8466 unsigned Mask = MaskC->getZExtValue();
8470 // Case (1): or (and A, mask), val => ARMbfi A, val, mask
8471 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
8473 unsigned Val = N1C->getZExtValue();
8474 if ((Val & ~Mask) != Val)
8477 if (ARM::isBitFieldInvertedMask(Mask)) {
8478 Val >>= countTrailingZeros(~Mask);
8480 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00,
8481 DAG.getConstant(Val, DL, MVT::i32),
8482 DAG.getConstant(Mask, DL, MVT::i32));
8484 // Do not add new nodes to DAG combiner worklist.
8485 DCI.CombineTo(N, Res, false);
8488 } else if (N1.getOpcode() == ISD::AND) {
8489 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
8490 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
8493 unsigned Mask2 = N11C->getZExtValue();
8495 // Mask and ~Mask2 (or reverse) must be equivalent for the BFI pattern
8497 if (ARM::isBitFieldInvertedMask(Mask) &&
8499 // The pack halfword instruction works better for masks that fit it,
8500 // so use that when it's available.
8501 if (Subtarget->hasT2ExtractPack() &&
8502 (Mask == 0xffff || Mask == 0xffff0000))
8505 unsigned amt = countTrailingZeros(Mask2);
8506 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
8507 DAG.getConstant(amt, DL, MVT::i32));
8508 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res,
8509 DAG.getConstant(Mask, DL, MVT::i32));
8510 // Do not add new nodes to DAG combiner worklist.
8511 DCI.CombineTo(N, Res, false);
8513 } else if (ARM::isBitFieldInvertedMask(~Mask) &&
8515 // The pack halfword instruction works better for masks that fit it,
8516 // so use that when it's available.
8517 if (Subtarget->hasT2ExtractPack() &&
8518 (Mask2 == 0xffff || Mask2 == 0xffff0000))
8521 unsigned lsb = countTrailingZeros(Mask);
8522 Res = DAG.getNode(ISD::SRL, DL, VT, N00,
8523 DAG.getConstant(lsb, DL, MVT::i32));
8524 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
8525 DAG.getConstant(Mask2, DL, MVT::i32));
8526 // Do not add new nodes to DAG combiner worklist.
8527 DCI.CombineTo(N, Res, false);
8532 if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) &&
8533 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) &&
8534 ARM::isBitFieldInvertedMask(~Mask)) {
8535 // Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask
8536 // where lsb(mask) == #shamt and masked bits of B are known zero.
8537 SDValue ShAmt = N00.getOperand(1);
8538 unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue();
8539 unsigned LSB = countTrailingZeros(Mask);
8543 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0),
8544 DAG.getConstant(~Mask, DL, MVT::i32));
8546 // Do not add new nodes to DAG combiner worklist.
8547 DCI.CombineTo(N, Res, false);
8553 static SDValue PerformXORCombine(SDNode *N,
8554 TargetLowering::DAGCombinerInfo &DCI,
8555 const ARMSubtarget *Subtarget) {
8556 EVT VT = N->getValueType(0);
8557 SelectionDAG &DAG = DCI.DAG;
8559 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
8562 if (!Subtarget->isThumb1Only()) {
8563 // fold (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
8564 SDValue Result = combineSelectAndUseCommutative(N, false, DCI);
8565 if (Result.getNode())
8572 /// PerformBFICombine - (bfi A, (and B, Mask1), Mask2) -> (bfi A, B, Mask2) iff
8573 /// the bits being cleared by the AND are not demanded by the BFI.
8574 static SDValue PerformBFICombine(SDNode *N,
8575 TargetLowering::DAGCombinerInfo &DCI) {
8576 SDValue N1 = N->getOperand(1);
8577 if (N1.getOpcode() == ISD::AND) {
8578 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
8581 unsigned InvMask = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
8582 unsigned LSB = countTrailingZeros(~InvMask);
8583 unsigned Width = (32 - countLeadingZeros(~InvMask)) - LSB;
8585 static_cast<unsigned>(std::numeric_limits<unsigned>::digits) &&
8586 "undefined behavior");
8587 unsigned Mask = (1u << Width) - 1;
8588 unsigned Mask2 = N11C->getZExtValue();
8589 if ((Mask & (~Mask2)) == 0)
8590 return DCI.DAG.getNode(ARMISD::BFI, SDLoc(N), N->getValueType(0),
8591 N->getOperand(0), N1.getOperand(0),
8597 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
8598 /// ARMISD::VMOVRRD.
8599 static SDValue PerformVMOVRRDCombine(SDNode *N,
8600 TargetLowering::DAGCombinerInfo &DCI,
8601 const ARMSubtarget *Subtarget) {
8602 // vmovrrd(vmovdrr x, y) -> x,y
8603 SDValue InDouble = N->getOperand(0);
8604 if (InDouble.getOpcode() == ARMISD::VMOVDRR && !Subtarget->isFPOnlySP())
8605 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
8607 // vmovrrd(load f64) -> (load i32), (load i32)
8608 SDNode *InNode = InDouble.getNode();
8609 if (ISD::isNormalLoad(InNode) && InNode->hasOneUse() &&
8610 InNode->getValueType(0) == MVT::f64 &&
8611 InNode->getOperand(1).getOpcode() == ISD::FrameIndex &&
8612 !cast<LoadSDNode>(InNode)->isVolatile()) {
8613 // TODO: Should this be done for non-FrameIndex operands?
8614 LoadSDNode *LD = cast<LoadSDNode>(InNode);
8616 SelectionDAG &DAG = DCI.DAG;
8618 SDValue BasePtr = LD->getBasePtr();
8619 SDValue NewLD1 = DAG.getLoad(MVT::i32, DL, LD->getChain(), BasePtr,
8620 LD->getPointerInfo(), LD->isVolatile(),
8621 LD->isNonTemporal(), LD->isInvariant(),
8622 LD->getAlignment());
8624 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
8625 DAG.getConstant(4, DL, MVT::i32));
8626 SDValue NewLD2 = DAG.getLoad(MVT::i32, DL, NewLD1.getValue(1), OffsetPtr,
8627 LD->getPointerInfo(), LD->isVolatile(),
8628 LD->isNonTemporal(), LD->isInvariant(),
8629 std::min(4U, LD->getAlignment() / 2));
8631 DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), NewLD2.getValue(1));
8632 if (DCI.DAG.getTargetLoweringInfo().isBigEndian())
8633 std::swap (NewLD1, NewLD2);
8634 SDValue Result = DCI.CombineTo(N, NewLD1, NewLD2);
8641 /// PerformVMOVDRRCombine - Target-specific dag combine xforms for
8642 /// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands.
8643 static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) {
8644 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X)
8645 SDValue Op0 = N->getOperand(0);
8646 SDValue Op1 = N->getOperand(1);
8647 if (Op0.getOpcode() == ISD::BITCAST)
8648 Op0 = Op0.getOperand(0);
8649 if (Op1.getOpcode() == ISD::BITCAST)
8650 Op1 = Op1.getOperand(0);
8651 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
8652 Op0.getNode() == Op1.getNode() &&
8653 Op0.getResNo() == 0 && Op1.getResNo() == 1)
8654 return DAG.getNode(ISD::BITCAST, SDLoc(N),
8655 N->getValueType(0), Op0.getOperand(0));
8659 /// hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node
8660 /// are normal, non-volatile loads. If so, it is profitable to bitcast an
8661 /// i64 vector to have f64 elements, since the value can then be loaded
8662 /// directly into a VFP register.
8663 static bool hasNormalLoadOperand(SDNode *N) {
8664 unsigned NumElts = N->getValueType(0).getVectorNumElements();
8665 for (unsigned i = 0; i < NumElts; ++i) {
8666 SDNode *Elt = N->getOperand(i).getNode();
8667 if (ISD::isNormalLoad(Elt) && !cast<LoadSDNode>(Elt)->isVolatile())
8673 /// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for
8674 /// ISD::BUILD_VECTOR.
8675 static SDValue PerformBUILD_VECTORCombine(SDNode *N,
8676 TargetLowering::DAGCombinerInfo &DCI,
8677 const ARMSubtarget *Subtarget) {
8678 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X):
8679 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value
8680 // into a pair of GPRs, which is fine when the value is used as a scalar,
8681 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD.
8682 SelectionDAG &DAG = DCI.DAG;
8683 if (N->getNumOperands() == 2) {
8684 SDValue RV = PerformVMOVDRRCombine(N, DAG);
8689 // Load i64 elements as f64 values so that type legalization does not split
8690 // them up into i32 values.
8691 EVT VT = N->getValueType(0);
8692 if (VT.getVectorElementType() != MVT::i64 || !hasNormalLoadOperand(N))
8695 SmallVector<SDValue, 8> Ops;
8696 unsigned NumElts = VT.getVectorNumElements();
8697 for (unsigned i = 0; i < NumElts; ++i) {
8698 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(i));
8700 // Make the DAGCombiner fold the bitcast.
8701 DCI.AddToWorklist(V.getNode());
8703 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, NumElts);
8704 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, FloatVT, Ops);
8705 return DAG.getNode(ISD::BITCAST, dl, VT, BV);
8708 /// \brief Target-specific dag combine xforms for ARMISD::BUILD_VECTOR.
8710 PerformARMBUILD_VECTORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
8711 // ARMISD::BUILD_VECTOR is introduced when legalizing ISD::BUILD_VECTOR.
8712 // At that time, we may have inserted bitcasts from integer to float.
8713 // If these bitcasts have survived DAGCombine, change the lowering of this
8714 // BUILD_VECTOR in something more vector friendly, i.e., that does not
8715 // force to use floating point types.
8717 // Make sure we can change the type of the vector.
8718 // This is possible iff:
8719 // 1. The vector is only used in a bitcast to a integer type. I.e.,
8720 // 1.1. Vector is used only once.
8721 // 1.2. Use is a bit convert to an integer type.
8722 // 2. The size of its operands are 32-bits (64-bits are not legal).
8723 EVT VT = N->getValueType(0);
8724 EVT EltVT = VT.getVectorElementType();
8726 // Check 1.1. and 2.
8727 if (EltVT.getSizeInBits() != 32 || !N->hasOneUse())
8730 // By construction, the input type must be float.
8731 assert(EltVT == MVT::f32 && "Unexpected type!");
8734 SDNode *Use = *N->use_begin();
8735 if (Use->getOpcode() != ISD::BITCAST ||
8736 Use->getValueType(0).isFloatingPoint())
8739 // Check profitability.
8740 // Model is, if more than half of the relevant operands are bitcast from
8741 // i32, turn the build_vector into a sequence of insert_vector_elt.
8742 // Relevant operands are everything that is not statically
8743 // (i.e., at compile time) bitcasted.
8744 unsigned NumOfBitCastedElts = 0;
8745 unsigned NumElts = VT.getVectorNumElements();
8746 unsigned NumOfRelevantElts = NumElts;
8747 for (unsigned Idx = 0; Idx < NumElts; ++Idx) {
8748 SDValue Elt = N->getOperand(Idx);
8749 if (Elt->getOpcode() == ISD::BITCAST) {
8750 // Assume only bit cast to i32 will go away.
8751 if (Elt->getOperand(0).getValueType() == MVT::i32)
8752 ++NumOfBitCastedElts;
8753 } else if (Elt.getOpcode() == ISD::UNDEF || isa<ConstantSDNode>(Elt))
8754 // Constants are statically casted, thus do not count them as
8755 // relevant operands.
8756 --NumOfRelevantElts;
8759 // Check if more than half of the elements require a non-free bitcast.
8760 if (NumOfBitCastedElts <= NumOfRelevantElts / 2)
8763 SelectionDAG &DAG = DCI.DAG;
8764 // Create the new vector type.
8765 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
8766 // Check if the type is legal.
8767 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8768 if (!TLI.isTypeLegal(VecVT))
8772 // ARMISD::BUILD_VECTOR E1, E2, ..., EN.
8773 // => BITCAST INSERT_VECTOR_ELT
8774 // (INSERT_VECTOR_ELT (...), (BITCAST EN-1), N-1),
8776 SDValue Vec = DAG.getUNDEF(VecVT);
8778 for (unsigned Idx = 0 ; Idx < NumElts; ++Idx) {
8779 SDValue V = N->getOperand(Idx);
8780 if (V.getOpcode() == ISD::UNDEF)
8782 if (V.getOpcode() == ISD::BITCAST &&
8783 V->getOperand(0).getValueType() == MVT::i32)
8784 // Fold obvious case.
8785 V = V.getOperand(0);
8787 V = DAG.getNode(ISD::BITCAST, SDLoc(V), MVT::i32, V);
8788 // Make the DAGCombiner fold the bitcasts.
8789 DCI.AddToWorklist(V.getNode());
8791 SDValue LaneIdx = DAG.getConstant(Idx, dl, MVT::i32);
8792 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecVT, Vec, V, LaneIdx);
8794 Vec = DAG.getNode(ISD::BITCAST, dl, VT, Vec);
8795 // Make the DAGCombiner fold the bitcasts.
8796 DCI.AddToWorklist(Vec.getNode());
8800 /// PerformInsertEltCombine - Target-specific dag combine xforms for
8801 /// ISD::INSERT_VECTOR_ELT.
8802 static SDValue PerformInsertEltCombine(SDNode *N,
8803 TargetLowering::DAGCombinerInfo &DCI) {
8804 // Bitcast an i64 load inserted into a vector to f64.
8805 // Otherwise, the i64 value will be legalized to a pair of i32 values.
8806 EVT VT = N->getValueType(0);
8807 SDNode *Elt = N->getOperand(1).getNode();
8808 if (VT.getVectorElementType() != MVT::i64 ||
8809 !ISD::isNormalLoad(Elt) || cast<LoadSDNode>(Elt)->isVolatile())
8812 SelectionDAG &DAG = DCI.DAG;
8814 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
8815 VT.getVectorNumElements());
8816 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, N->getOperand(0));
8817 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(1));
8818 // Make the DAGCombiner fold the bitcasts.
8819 DCI.AddToWorklist(Vec.getNode());
8820 DCI.AddToWorklist(V.getNode());
8821 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT,
8822 Vec, V, N->getOperand(2));
8823 return DAG.getNode(ISD::BITCAST, dl, VT, InsElt);
8826 /// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for
8827 /// ISD::VECTOR_SHUFFLE.
8828 static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) {
8829 // The LLVM shufflevector instruction does not require the shuffle mask
8830 // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does
8831 // have that requirement. When translating to ISD::VECTOR_SHUFFLE, if the
8832 // operands do not match the mask length, they are extended by concatenating
8833 // them with undef vectors. That is probably the right thing for other
8834 // targets, but for NEON it is better to concatenate two double-register
8835 // size vector operands into a single quad-register size vector. Do that
8836 // transformation here:
8837 // shuffle(concat(v1, undef), concat(v2, undef)) ->
8838 // shuffle(concat(v1, v2), undef)
8839 SDValue Op0 = N->getOperand(0);
8840 SDValue Op1 = N->getOperand(1);
8841 if (Op0.getOpcode() != ISD::CONCAT_VECTORS ||
8842 Op1.getOpcode() != ISD::CONCAT_VECTORS ||
8843 Op0.getNumOperands() != 2 ||
8844 Op1.getNumOperands() != 2)
8846 SDValue Concat0Op1 = Op0.getOperand(1);
8847 SDValue Concat1Op1 = Op1.getOperand(1);
8848 if (Concat0Op1.getOpcode() != ISD::UNDEF ||
8849 Concat1Op1.getOpcode() != ISD::UNDEF)
8851 // Skip the transformation if any of the types are illegal.
8852 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8853 EVT VT = N->getValueType(0);
8854 if (!TLI.isTypeLegal(VT) ||
8855 !TLI.isTypeLegal(Concat0Op1.getValueType()) ||
8856 !TLI.isTypeLegal(Concat1Op1.getValueType()))
8859 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT,
8860 Op0.getOperand(0), Op1.getOperand(0));
8861 // Translate the shuffle mask.
8862 SmallVector<int, 16> NewMask;
8863 unsigned NumElts = VT.getVectorNumElements();
8864 unsigned HalfElts = NumElts/2;
8865 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
8866 for (unsigned n = 0; n < NumElts; ++n) {
8867 int MaskElt = SVN->getMaskElt(n);
8869 if (MaskElt < (int)HalfElts)
8871 else if (MaskElt >= (int)NumElts && MaskElt < (int)(NumElts + HalfElts))
8872 NewElt = HalfElts + MaskElt - NumElts;
8873 NewMask.push_back(NewElt);
8875 return DAG.getVectorShuffle(VT, SDLoc(N), NewConcat,
8876 DAG.getUNDEF(VT), NewMask.data());
8879 /// CombineBaseUpdate - Target-specific DAG combine function for VLDDUP,
8880 /// NEON load/store intrinsics, and generic vector load/stores, to merge
8881 /// base address updates.
8882 /// For generic load/stores, the memory type is assumed to be a vector.
8883 /// The caller is assumed to have checked legality.
8884 static SDValue CombineBaseUpdate(SDNode *N,
8885 TargetLowering::DAGCombinerInfo &DCI) {
8886 SelectionDAG &DAG = DCI.DAG;
8887 const bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID ||
8888 N->getOpcode() == ISD::INTRINSIC_W_CHAIN);
8889 const bool isStore = N->getOpcode() == ISD::STORE;
8890 const unsigned AddrOpIdx = ((isIntrinsic || isStore) ? 2 : 1);
8891 SDValue Addr = N->getOperand(AddrOpIdx);
8892 MemSDNode *MemN = cast<MemSDNode>(N);
8895 // Search for a use of the address operand that is an increment.
8896 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
8897 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
8899 if (User->getOpcode() != ISD::ADD ||
8900 UI.getUse().getResNo() != Addr.getResNo())
8903 // Check that the add is independent of the load/store. Otherwise, folding
8904 // it would create a cycle.
8905 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
8908 // Find the new opcode for the updating load/store.
8909 bool isLoadOp = true;
8910 bool isLaneOp = false;
8911 unsigned NewOpc = 0;
8912 unsigned NumVecs = 0;
8914 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
8916 default: llvm_unreachable("unexpected intrinsic for Neon base update");
8917 case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD;
8919 case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD;
8921 case Intrinsic::arm_neon_vld3: NewOpc = ARMISD::VLD3_UPD;
8923 case Intrinsic::arm_neon_vld4: NewOpc = ARMISD::VLD4_UPD;
8925 case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD;
8926 NumVecs = 2; isLaneOp = true; break;
8927 case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD;
8928 NumVecs = 3; isLaneOp = true; break;
8929 case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD;
8930 NumVecs = 4; isLaneOp = true; break;
8931 case Intrinsic::arm_neon_vst1: NewOpc = ARMISD::VST1_UPD;
8932 NumVecs = 1; isLoadOp = false; break;
8933 case Intrinsic::arm_neon_vst2: NewOpc = ARMISD::VST2_UPD;
8934 NumVecs = 2; isLoadOp = false; break;
8935 case Intrinsic::arm_neon_vst3: NewOpc = ARMISD::VST3_UPD;
8936 NumVecs = 3; isLoadOp = false; break;
8937 case Intrinsic::arm_neon_vst4: NewOpc = ARMISD::VST4_UPD;
8938 NumVecs = 4; isLoadOp = false; break;
8939 case Intrinsic::arm_neon_vst2lane: NewOpc = ARMISD::VST2LN_UPD;
8940 NumVecs = 2; isLoadOp = false; isLaneOp = true; break;
8941 case Intrinsic::arm_neon_vst3lane: NewOpc = ARMISD::VST3LN_UPD;
8942 NumVecs = 3; isLoadOp = false; isLaneOp = true; break;
8943 case Intrinsic::arm_neon_vst4lane: NewOpc = ARMISD::VST4LN_UPD;
8944 NumVecs = 4; isLoadOp = false; isLaneOp = true; break;
8948 switch (N->getOpcode()) {
8949 default: llvm_unreachable("unexpected opcode for Neon base update");
8950 case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break;
8951 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break;
8952 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break;
8953 case ISD::LOAD: NewOpc = ARMISD::VLD1_UPD;
8954 NumVecs = 1; isLaneOp = false; break;
8955 case ISD::STORE: NewOpc = ARMISD::VST1_UPD;
8956 NumVecs = 1; isLaneOp = false; isLoadOp = false; break;
8960 // Find the size of memory referenced by the load/store.
8963 VecTy = N->getValueType(0);
8964 } else if (isIntrinsic) {
8965 VecTy = N->getOperand(AddrOpIdx+1).getValueType();
8967 assert(isStore && "Node has to be a load, a store, or an intrinsic!");
8968 VecTy = N->getOperand(1).getValueType();
8971 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
8973 NumBytes /= VecTy.getVectorNumElements();
8975 // If the increment is a constant, it must match the memory ref size.
8976 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
8977 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
8978 uint64_t IncVal = CInc->getZExtValue();
8979 if (IncVal != NumBytes)
8981 } else if (NumBytes >= 3 * 16) {
8982 // VLD3/4 and VST3/4 for 128-bit vectors are implemented with two
8983 // separate instructions that make it harder to use a non-constant update.
8987 // OK, we found an ADD we can fold into the base update.
8988 // Now, create a _UPD node, taking care of not breaking alignment.
8990 EVT AlignedVecTy = VecTy;
8991 unsigned Alignment = MemN->getAlignment();
8993 // If this is a less-than-standard-aligned load/store, change the type to
8994 // match the standard alignment.
8995 // The alignment is overlooked when selecting _UPD variants; and it's
8996 // easier to introduce bitcasts here than fix that.
8997 // There are 3 ways to get to this base-update combine:
8998 // - intrinsics: they are assumed to be properly aligned (to the standard
8999 // alignment of the memory type), so we don't need to do anything.
9000 // - ARMISD::VLDx nodes: they are only generated from the aforementioned
9001 // intrinsics, so, likewise, there's nothing to do.
9002 // - generic load/store instructions: the alignment is specified as an
9003 // explicit operand, rather than implicitly as the standard alignment
9004 // of the memory type (like the intrisics). We need to change the
9005 // memory type to match the explicit alignment. That way, we don't
9006 // generate non-standard-aligned ARMISD::VLDx nodes.
9007 if (isa<LSBaseSDNode>(N)) {
9010 if (Alignment < VecTy.getScalarSizeInBits() / 8) {
9011 MVT EltTy = MVT::getIntegerVT(Alignment * 8);
9012 assert(NumVecs == 1 && "Unexpected multi-element generic load/store.");
9013 assert(!isLaneOp && "Unexpected generic load/store lane.");
9014 unsigned NumElts = NumBytes / (EltTy.getSizeInBits() / 8);
9015 AlignedVecTy = MVT::getVectorVT(EltTy, NumElts);
9017 // Don't set an explicit alignment on regular load/stores that we want
9018 // to transform to VLD/VST 1_UPD nodes.
9019 // This matches the behavior of regular load/stores, which only get an
9020 // explicit alignment if the MMO alignment is larger than the standard
9021 // alignment of the memory type.
9022 // Intrinsics, however, always get an explicit alignment, set to the
9023 // alignment of the MMO.
9027 // Create the new updating load/store node.
9028 // First, create an SDVTList for the new updating node's results.
9030 unsigned NumResultVecs = (isLoadOp ? NumVecs : 0);
9032 for (n = 0; n < NumResultVecs; ++n)
9033 Tys[n] = AlignedVecTy;
9034 Tys[n++] = MVT::i32;
9035 Tys[n] = MVT::Other;
9036 SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumResultVecs+2));
9038 // Then, gather the new node's operands.
9039 SmallVector<SDValue, 8> Ops;
9040 Ops.push_back(N->getOperand(0)); // incoming chain
9041 Ops.push_back(N->getOperand(AddrOpIdx));
9044 if (StoreSDNode *StN = dyn_cast<StoreSDNode>(N)) {
9045 // Try to match the intrinsic's signature
9046 Ops.push_back(StN->getValue());
9048 // Loads (and of course intrinsics) match the intrinsics' signature,
9049 // so just add all but the alignment operand.
9050 for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands() - 1; ++i)
9051 Ops.push_back(N->getOperand(i));
9054 // For all node types, the alignment operand is always the last one.
9055 Ops.push_back(DAG.getConstant(Alignment, dl, MVT::i32));
9057 // If this is a non-standard-aligned STORE, the penultimate operand is the
9058 // stored value. Bitcast it to the aligned type.
9059 if (AlignedVecTy != VecTy && N->getOpcode() == ISD::STORE) {
9060 SDValue &StVal = Ops[Ops.size()-2];
9061 StVal = DAG.getNode(ISD::BITCAST, dl, AlignedVecTy, StVal);
9064 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, dl, SDTys,
9066 MemN->getMemOperand());
9069 SmallVector<SDValue, 5> NewResults;
9070 for (unsigned i = 0; i < NumResultVecs; ++i)
9071 NewResults.push_back(SDValue(UpdN.getNode(), i));
9073 // If this is an non-standard-aligned LOAD, the first result is the loaded
9074 // value. Bitcast it to the expected result type.
9075 if (AlignedVecTy != VecTy && N->getOpcode() == ISD::LOAD) {
9076 SDValue &LdVal = NewResults[0];
9077 LdVal = DAG.getNode(ISD::BITCAST, dl, VecTy, LdVal);
9080 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs+1)); // chain
9081 DCI.CombineTo(N, NewResults);
9082 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
9089 static SDValue PerformVLDCombine(SDNode *N,
9090 TargetLowering::DAGCombinerInfo &DCI) {
9091 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
9094 return CombineBaseUpdate(N, DCI);
9097 /// CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a
9098 /// vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic
9099 /// are also VDUPLANEs. If so, combine them to a vldN-dup operation and
9101 static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
9102 SelectionDAG &DAG = DCI.DAG;
9103 EVT VT = N->getValueType(0);
9104 // vldN-dup instructions only support 64-bit vectors for N > 1.
9105 if (!VT.is64BitVector())
9108 // Check if the VDUPLANE operand is a vldN-dup intrinsic.
9109 SDNode *VLD = N->getOperand(0).getNode();
9110 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN)
9112 unsigned NumVecs = 0;
9113 unsigned NewOpc = 0;
9114 unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue();
9115 if (IntNo == Intrinsic::arm_neon_vld2lane) {
9117 NewOpc = ARMISD::VLD2DUP;
9118 } else if (IntNo == Intrinsic::arm_neon_vld3lane) {
9120 NewOpc = ARMISD::VLD3DUP;
9121 } else if (IntNo == Intrinsic::arm_neon_vld4lane) {
9123 NewOpc = ARMISD::VLD4DUP;
9128 // First check that all the vldN-lane uses are VDUPLANEs and that the lane
9129 // numbers match the load.
9130 unsigned VLDLaneNo =
9131 cast<ConstantSDNode>(VLD->getOperand(NumVecs+3))->getZExtValue();
9132 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
9134 // Ignore uses of the chain result.
9135 if (UI.getUse().getResNo() == NumVecs)
9138 if (User->getOpcode() != ARMISD::VDUPLANE ||
9139 VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue())
9143 // Create the vldN-dup node.
9146 for (n = 0; n < NumVecs; ++n)
9148 Tys[n] = MVT::Other;
9149 SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumVecs+1));
9150 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) };
9151 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD);
9152 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, SDLoc(VLD), SDTys,
9153 Ops, VLDMemInt->getMemoryVT(),
9154 VLDMemInt->getMemOperand());
9157 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
9159 unsigned ResNo = UI.getUse().getResNo();
9160 // Ignore uses of the chain result.
9161 if (ResNo == NumVecs)
9164 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo));
9167 // Now the vldN-lane intrinsic is dead except for its chain result.
9168 // Update uses of the chain.
9169 std::vector<SDValue> VLDDupResults;
9170 for (unsigned n = 0; n < NumVecs; ++n)
9171 VLDDupResults.push_back(SDValue(VLDDup.getNode(), n));
9172 VLDDupResults.push_back(SDValue(VLDDup.getNode(), NumVecs));
9173 DCI.CombineTo(VLD, VLDDupResults);
9178 /// PerformVDUPLANECombine - Target-specific dag combine xforms for
9179 /// ARMISD::VDUPLANE.
9180 static SDValue PerformVDUPLANECombine(SDNode *N,
9181 TargetLowering::DAGCombinerInfo &DCI) {
9182 SDValue Op = N->getOperand(0);
9184 // If the source is a vldN-lane (N > 1) intrinsic, and all the other uses
9185 // of that intrinsic are also VDUPLANEs, combine them to a vldN-dup operation.
9186 if (CombineVLDDUP(N, DCI))
9187 return SDValue(N, 0);
9189 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
9190 // redundant. Ignore bit_converts for now; element sizes are checked below.
9191 while (Op.getOpcode() == ISD::BITCAST)
9192 Op = Op.getOperand(0);
9193 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
9196 // Make sure the VMOV element size is not bigger than the VDUPLANE elements.
9197 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits();
9198 // The canonical VMOV for a zero vector uses a 32-bit element size.
9199 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9201 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
9203 EVT VT = N->getValueType(0);
9204 if (EltSize > VT.getVectorElementType().getSizeInBits())
9207 return DCI.DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
9210 static SDValue PerformLOADCombine(SDNode *N,
9211 TargetLowering::DAGCombinerInfo &DCI) {
9212 EVT VT = N->getValueType(0);
9214 // If this is a legal vector load, try to combine it into a VLD1_UPD.
9215 if (ISD::isNormalLoad(N) && VT.isVector() &&
9216 DCI.DAG.getTargetLoweringInfo().isTypeLegal(VT))
9217 return CombineBaseUpdate(N, DCI);
9222 /// PerformSTORECombine - Target-specific dag combine xforms for
9224 static SDValue PerformSTORECombine(SDNode *N,
9225 TargetLowering::DAGCombinerInfo &DCI) {
9226 StoreSDNode *St = cast<StoreSDNode>(N);
9227 if (St->isVolatile())
9230 // Optimize trunc store (of multiple scalars) to shuffle and store. First,
9231 // pack all of the elements in one place. Next, store to memory in fewer
9233 SDValue StVal = St->getValue();
9234 EVT VT = StVal.getValueType();
9235 if (St->isTruncatingStore() && VT.isVector()) {
9236 SelectionDAG &DAG = DCI.DAG;
9237 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9238 EVT StVT = St->getMemoryVT();
9239 unsigned NumElems = VT.getVectorNumElements();
9240 assert(StVT != VT && "Cannot truncate to the same type");
9241 unsigned FromEltSz = VT.getVectorElementType().getSizeInBits();
9242 unsigned ToEltSz = StVT.getVectorElementType().getSizeInBits();
9244 // From, To sizes and ElemCount must be pow of two
9245 if (!isPowerOf2_32(NumElems * FromEltSz * ToEltSz)) return SDValue();
9247 // We are going to use the original vector elt for storing.
9248 // Accumulated smaller vector elements must be a multiple of the store size.
9249 if (0 != (NumElems * FromEltSz) % ToEltSz) return SDValue();
9251 unsigned SizeRatio = FromEltSz / ToEltSz;
9252 assert(SizeRatio * NumElems * ToEltSz == VT.getSizeInBits());
9254 // Create a type on which we perform the shuffle.
9255 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), StVT.getScalarType(),
9256 NumElems*SizeRatio);
9257 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
9260 SDValue WideVec = DAG.getNode(ISD::BITCAST, DL, WideVecVT, StVal);
9261 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
9262 for (unsigned i = 0; i < NumElems; ++i)
9263 ShuffleVec[i] = TLI.isBigEndian() ? (i+1) * SizeRatio - 1 : i * SizeRatio;
9265 // Can't shuffle using an illegal type.
9266 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
9268 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, DL, WideVec,
9269 DAG.getUNDEF(WideVec.getValueType()),
9271 // At this point all of the data is stored at the bottom of the
9272 // register. We now need to save it to mem.
9274 // Find the largest store unit
9275 MVT StoreType = MVT::i8;
9276 for (MVT Tp : MVT::integer_valuetypes()) {
9277 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToEltSz)
9280 // Didn't find a legal store type.
9281 if (!TLI.isTypeLegal(StoreType))
9284 // Bitcast the original vector into a vector of store-size units
9285 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
9286 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
9287 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
9288 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, DL, StoreVecVT, Shuff);
9289 SmallVector<SDValue, 8> Chains;
9290 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8, DL,
9291 TLI.getPointerTy());
9292 SDValue BasePtr = St->getBasePtr();
9294 // Perform one or more big stores into memory.
9295 unsigned E = (ToEltSz*NumElems)/StoreType.getSizeInBits();
9296 for (unsigned I = 0; I < E; I++) {
9297 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
9298 StoreType, ShuffWide,
9299 DAG.getIntPtrConstant(I, DL));
9300 SDValue Ch = DAG.getStore(St->getChain(), DL, SubVec, BasePtr,
9301 St->getPointerInfo(), St->isVolatile(),
9302 St->isNonTemporal(), St->getAlignment());
9303 BasePtr = DAG.getNode(ISD::ADD, DL, BasePtr.getValueType(), BasePtr,
9305 Chains.push_back(Ch);
9307 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
9310 if (!ISD::isNormalStore(St))
9313 // Split a store of a VMOVDRR into two integer stores to avoid mixing NEON and
9314 // ARM stores of arguments in the same cache line.
9315 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR &&
9316 StVal.getNode()->hasOneUse()) {
9317 SelectionDAG &DAG = DCI.DAG;
9318 bool isBigEndian = DAG.getTargetLoweringInfo().isBigEndian();
9320 SDValue BasePtr = St->getBasePtr();
9321 SDValue NewST1 = DAG.getStore(St->getChain(), DL,
9322 StVal.getNode()->getOperand(isBigEndian ? 1 : 0 ),
9323 BasePtr, St->getPointerInfo(), St->isVolatile(),
9324 St->isNonTemporal(), St->getAlignment());
9326 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
9327 DAG.getConstant(4, DL, MVT::i32));
9328 return DAG.getStore(NewST1.getValue(0), DL,
9329 StVal.getNode()->getOperand(isBigEndian ? 0 : 1),
9330 OffsetPtr, St->getPointerInfo(), St->isVolatile(),
9331 St->isNonTemporal(),
9332 std::min(4U, St->getAlignment() / 2));
9335 if (StVal.getValueType() == MVT::i64 &&
9336 StVal.getNode()->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
9338 // Bitcast an i64 store extracted from a vector to f64.
9339 // Otherwise, the i64 value will be legalized to a pair of i32 values.
9340 SelectionDAG &DAG = DCI.DAG;
9342 SDValue IntVec = StVal.getOperand(0);
9343 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
9344 IntVec.getValueType().getVectorNumElements());
9345 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec);
9346 SDValue ExtElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
9347 Vec, StVal.getOperand(1));
9349 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt);
9350 // Make the DAGCombiner fold the bitcasts.
9351 DCI.AddToWorklist(Vec.getNode());
9352 DCI.AddToWorklist(ExtElt.getNode());
9353 DCI.AddToWorklist(V.getNode());
9354 return DAG.getStore(St->getChain(), dl, V, St->getBasePtr(),
9355 St->getPointerInfo(), St->isVolatile(),
9356 St->isNonTemporal(), St->getAlignment(),
9360 // If this is a legal vector store, try to combine it into a VST1_UPD.
9361 if (ISD::isNormalStore(N) && VT.isVector() &&
9362 DCI.DAG.getTargetLoweringInfo().isTypeLegal(VT))
9363 return CombineBaseUpdate(N, DCI);
9368 // isConstVecPow2 - Return true if each vector element is a power of 2, all
9369 // elements are the same constant, C, and Log2(C) ranges from 1 to 32.
9370 static bool isConstVecPow2(SDValue ConstVec, bool isSigned, uint64_t &C)
9374 for (unsigned I = 0, E = ConstVec.getValueType().getVectorNumElements();
9376 ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(ConstVec.getOperand(I));
9381 APFloat APF = C->getValueAPF();
9382 if (APF.convertToInteger(&cN, 64, isSigned, APFloat::rmTowardZero, &isExact)
9383 != APFloat::opOK || !isExact)
9386 c0 = (I == 0) ? cN : c0;
9387 if (!isPowerOf2_64(cN) || c0 != cN || Log2_64(c0) < 1 || Log2_64(c0) > 32)
9394 /// PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD)
9395 /// can replace combinations of VMUL and VCVT (floating-point to integer)
9396 /// when the VMUL has a constant operand that is a power of 2.
9398 /// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
9399 /// vmul.f32 d16, d17, d16
9400 /// vcvt.s32.f32 d16, d16
9402 /// vcvt.s32.f32 d16, d16, #3
9403 static SDValue PerformVCVTCombine(SDNode *N,
9404 TargetLowering::DAGCombinerInfo &DCI,
9405 const ARMSubtarget *Subtarget) {
9406 SelectionDAG &DAG = DCI.DAG;
9407 SDValue Op = N->getOperand(0);
9409 if (!Subtarget->hasNEON() || !Op.getValueType().isVector() ||
9410 Op.getOpcode() != ISD::FMUL)
9414 SDValue N0 = Op->getOperand(0);
9415 SDValue ConstVec = Op->getOperand(1);
9416 bool isSigned = N->getOpcode() == ISD::FP_TO_SINT;
9418 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
9419 !isConstVecPow2(ConstVec, isSigned, C))
9422 MVT FloatTy = Op.getSimpleValueType().getVectorElementType();
9423 MVT IntTy = N->getSimpleValueType(0).getVectorElementType();
9424 unsigned NumLanes = Op.getValueType().getVectorNumElements();
9425 if (FloatTy.getSizeInBits() != 32 || IntTy.getSizeInBits() > 32 ||
9427 // These instructions only exist converting from f32 to i32. We can handle
9428 // smaller integers by generating an extra truncate, but larger ones would
9429 // be lossy. We also can't handle more then 4 lanes, since these intructions
9430 // only support v2i32/v4i32 types.
9435 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfp2fxs :
9436 Intrinsic::arm_neon_vcvtfp2fxu;
9437 SDValue FixConv = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl,
9438 NumLanes == 2 ? MVT::v2i32 : MVT::v4i32,
9439 DAG.getConstant(IntrinsicOpcode, dl, MVT::i32),
9441 DAG.getConstant(Log2_64(C), dl, MVT::i32));
9443 if (IntTy.getSizeInBits() < FloatTy.getSizeInBits())
9444 FixConv = DAG.getNode(ISD::TRUNCATE, dl, N->getValueType(0), FixConv);
9449 /// PerformVDIVCombine - VCVT (fixed-point to floating-point, Advanced SIMD)
9450 /// can replace combinations of VCVT (integer to floating-point) and VDIV
9451 /// when the VDIV has a constant operand that is a power of 2.
9453 /// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
9454 /// vcvt.f32.s32 d16, d16
9455 /// vdiv.f32 d16, d17, d16
9457 /// vcvt.f32.s32 d16, d16, #3
9458 static SDValue PerformVDIVCombine(SDNode *N,
9459 TargetLowering::DAGCombinerInfo &DCI,
9460 const ARMSubtarget *Subtarget) {
9461 SelectionDAG &DAG = DCI.DAG;
9462 SDValue Op = N->getOperand(0);
9463 unsigned OpOpcode = Op.getNode()->getOpcode();
9465 if (!Subtarget->hasNEON() || !N->getValueType(0).isVector() ||
9466 (OpOpcode != ISD::SINT_TO_FP && OpOpcode != ISD::UINT_TO_FP))
9470 SDValue ConstVec = N->getOperand(1);
9471 bool isSigned = OpOpcode == ISD::SINT_TO_FP;
9473 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
9474 !isConstVecPow2(ConstVec, isSigned, C))
9477 MVT FloatTy = N->getSimpleValueType(0).getVectorElementType();
9478 MVT IntTy = Op.getOperand(0).getSimpleValueType().getVectorElementType();
9479 if (FloatTy.getSizeInBits() != 32 || IntTy.getSizeInBits() > 32) {
9480 // These instructions only exist converting from i32 to f32. We can handle
9481 // smaller integers by generating an extra extend, but larger ones would
9487 SDValue ConvInput = Op.getOperand(0);
9488 unsigned NumLanes = Op.getValueType().getVectorNumElements();
9489 if (IntTy.getSizeInBits() < FloatTy.getSizeInBits())
9490 ConvInput = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
9491 dl, NumLanes == 2 ? MVT::v2i32 : MVT::v4i32,
9494 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfxs2fp :
9495 Intrinsic::arm_neon_vcvtfxu2fp;
9496 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl,
9498 DAG.getConstant(IntrinsicOpcode, dl, MVT::i32),
9499 ConvInput, DAG.getConstant(Log2_64(C), dl, MVT::i32));
9502 /// Getvshiftimm - Check if this is a valid build_vector for the immediate
9503 /// operand of a vector shift operation, where all the elements of the
9504 /// build_vector must have the same constant integer value.
9505 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
9506 // Ignore bit_converts.
9507 while (Op.getOpcode() == ISD::BITCAST)
9508 Op = Op.getOperand(0);
9509 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
9510 APInt SplatBits, SplatUndef;
9511 unsigned SplatBitSize;
9513 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
9514 HasAnyUndefs, ElementBits) ||
9515 SplatBitSize > ElementBits)
9517 Cnt = SplatBits.getSExtValue();
9521 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
9522 /// operand of a vector shift left operation. That value must be in the range:
9523 /// 0 <= Value < ElementBits for a left shift; or
9524 /// 0 <= Value <= ElementBits for a long left shift.
9525 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
9526 assert(VT.isVector() && "vector shift count is not a vector type");
9527 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
9528 if (! getVShiftImm(Op, ElementBits, Cnt))
9530 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
9533 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
9534 /// operand of a vector shift right operation. For a shift opcode, the value
9535 /// is positive, but for an intrinsic the value count must be negative. The
9536 /// absolute value must be in the range:
9537 /// 1 <= |Value| <= ElementBits for a right shift; or
9538 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
9539 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
9541 assert(VT.isVector() && "vector shift count is not a vector type");
9542 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
9543 if (! getVShiftImm(Op, ElementBits, Cnt))
9547 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
9550 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
9551 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
9552 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
9555 // Don't do anything for most intrinsics.
9558 // Vector shifts: check for immediate versions and lower them.
9559 // Note: This is done during DAG combining instead of DAG legalizing because
9560 // the build_vectors for 64-bit vector element shift counts are generally
9561 // not legal, and it is hard to see their values after they get legalized to
9562 // loads from a constant pool.
9563 case Intrinsic::arm_neon_vshifts:
9564 case Intrinsic::arm_neon_vshiftu:
9565 case Intrinsic::arm_neon_vrshifts:
9566 case Intrinsic::arm_neon_vrshiftu:
9567 case Intrinsic::arm_neon_vrshiftn:
9568 case Intrinsic::arm_neon_vqshifts:
9569 case Intrinsic::arm_neon_vqshiftu:
9570 case Intrinsic::arm_neon_vqshiftsu:
9571 case Intrinsic::arm_neon_vqshiftns:
9572 case Intrinsic::arm_neon_vqshiftnu:
9573 case Intrinsic::arm_neon_vqshiftnsu:
9574 case Intrinsic::arm_neon_vqrshiftns:
9575 case Intrinsic::arm_neon_vqrshiftnu:
9576 case Intrinsic::arm_neon_vqrshiftnsu: {
9577 EVT VT = N->getOperand(1).getValueType();
9579 unsigned VShiftOpc = 0;
9582 case Intrinsic::arm_neon_vshifts:
9583 case Intrinsic::arm_neon_vshiftu:
9584 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
9585 VShiftOpc = ARMISD::VSHL;
9588 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
9589 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
9590 ARMISD::VSHRs : ARMISD::VSHRu);
9595 case Intrinsic::arm_neon_vrshifts:
9596 case Intrinsic::arm_neon_vrshiftu:
9597 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
9601 case Intrinsic::arm_neon_vqshifts:
9602 case Intrinsic::arm_neon_vqshiftu:
9603 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
9607 case Intrinsic::arm_neon_vqshiftsu:
9608 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
9610 llvm_unreachable("invalid shift count for vqshlu intrinsic");
9612 case Intrinsic::arm_neon_vrshiftn:
9613 case Intrinsic::arm_neon_vqshiftns:
9614 case Intrinsic::arm_neon_vqshiftnu:
9615 case Intrinsic::arm_neon_vqshiftnsu:
9616 case Intrinsic::arm_neon_vqrshiftns:
9617 case Intrinsic::arm_neon_vqrshiftnu:
9618 case Intrinsic::arm_neon_vqrshiftnsu:
9619 // Narrowing shifts require an immediate right shift.
9620 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
9622 llvm_unreachable("invalid shift count for narrowing vector shift "
9626 llvm_unreachable("unhandled vector shift");
9630 case Intrinsic::arm_neon_vshifts:
9631 case Intrinsic::arm_neon_vshiftu:
9632 // Opcode already set above.
9634 case Intrinsic::arm_neon_vrshifts:
9635 VShiftOpc = ARMISD::VRSHRs; break;
9636 case Intrinsic::arm_neon_vrshiftu:
9637 VShiftOpc = ARMISD::VRSHRu; break;
9638 case Intrinsic::arm_neon_vrshiftn:
9639 VShiftOpc = ARMISD::VRSHRN; break;
9640 case Intrinsic::arm_neon_vqshifts:
9641 VShiftOpc = ARMISD::VQSHLs; break;
9642 case Intrinsic::arm_neon_vqshiftu:
9643 VShiftOpc = ARMISD::VQSHLu; break;
9644 case Intrinsic::arm_neon_vqshiftsu:
9645 VShiftOpc = ARMISD::VQSHLsu; break;
9646 case Intrinsic::arm_neon_vqshiftns:
9647 VShiftOpc = ARMISD::VQSHRNs; break;
9648 case Intrinsic::arm_neon_vqshiftnu:
9649 VShiftOpc = ARMISD::VQSHRNu; break;
9650 case Intrinsic::arm_neon_vqshiftnsu:
9651 VShiftOpc = ARMISD::VQSHRNsu; break;
9652 case Intrinsic::arm_neon_vqrshiftns:
9653 VShiftOpc = ARMISD::VQRSHRNs; break;
9654 case Intrinsic::arm_neon_vqrshiftnu:
9655 VShiftOpc = ARMISD::VQRSHRNu; break;
9656 case Intrinsic::arm_neon_vqrshiftnsu:
9657 VShiftOpc = ARMISD::VQRSHRNsu; break;
9661 return DAG.getNode(VShiftOpc, dl, N->getValueType(0),
9662 N->getOperand(1), DAG.getConstant(Cnt, dl, MVT::i32));
9665 case Intrinsic::arm_neon_vshiftins: {
9666 EVT VT = N->getOperand(1).getValueType();
9668 unsigned VShiftOpc = 0;
9670 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
9671 VShiftOpc = ARMISD::VSLI;
9672 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
9673 VShiftOpc = ARMISD::VSRI;
9675 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
9679 return DAG.getNode(VShiftOpc, dl, N->getValueType(0),
9680 N->getOperand(1), N->getOperand(2),
9681 DAG.getConstant(Cnt, dl, MVT::i32));
9684 case Intrinsic::arm_neon_vqrshifts:
9685 case Intrinsic::arm_neon_vqrshiftu:
9686 // No immediate versions of these to check for.
9693 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
9694 /// lowers them. As with the vector shift intrinsics, this is done during DAG
9695 /// combining instead of DAG legalizing because the build_vectors for 64-bit
9696 /// vector element shift counts are generally not legal, and it is hard to see
9697 /// their values after they get legalized to loads from a constant pool.
9698 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
9699 const ARMSubtarget *ST) {
9700 EVT VT = N->getValueType(0);
9701 if (N->getOpcode() == ISD::SRL && VT == MVT::i32 && ST->hasV6Ops()) {
9702 // Canonicalize (srl (bswap x), 16) to (rotr (bswap x), 16) if the high
9703 // 16-bits of x is zero. This optimizes rev + lsr 16 to rev16.
9704 SDValue N1 = N->getOperand(1);
9705 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
9706 SDValue N0 = N->getOperand(0);
9707 if (C->getZExtValue() == 16 && N0.getOpcode() == ISD::BSWAP &&
9708 DAG.MaskedValueIsZero(N0.getOperand(0),
9709 APInt::getHighBitsSet(32, 16)))
9710 return DAG.getNode(ISD::ROTR, SDLoc(N), VT, N0, N1);
9714 // Nothing to be done for scalar shifts.
9715 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9716 if (!VT.isVector() || !TLI.isTypeLegal(VT))
9719 assert(ST->hasNEON() && "unexpected vector shift");
9722 switch (N->getOpcode()) {
9723 default: llvm_unreachable("unexpected shift opcode");
9726 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt)) {
9728 return DAG.getNode(ARMISD::VSHL, dl, VT, N->getOperand(0),
9729 DAG.getConstant(Cnt, dl, MVT::i32));
9735 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
9736 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
9737 ARMISD::VSHRs : ARMISD::VSHRu);
9739 return DAG.getNode(VShiftOpc, dl, VT, N->getOperand(0),
9740 DAG.getConstant(Cnt, dl, MVT::i32));
9746 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
9747 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
9748 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
9749 const ARMSubtarget *ST) {
9750 SDValue N0 = N->getOperand(0);
9752 // Check for sign- and zero-extensions of vector extract operations of 8-
9753 // and 16-bit vector elements. NEON supports these directly. They are
9754 // handled during DAG combining because type legalization will promote them
9755 // to 32-bit types and it is messy to recognize the operations after that.
9756 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
9757 SDValue Vec = N0.getOperand(0);
9758 SDValue Lane = N0.getOperand(1);
9759 EVT VT = N->getValueType(0);
9760 EVT EltVT = N0.getValueType();
9761 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9763 if (VT == MVT::i32 &&
9764 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
9765 TLI.isTypeLegal(Vec.getValueType()) &&
9766 isa<ConstantSDNode>(Lane)) {
9769 switch (N->getOpcode()) {
9770 default: llvm_unreachable("unexpected opcode");
9771 case ISD::SIGN_EXTEND:
9772 Opc = ARMISD::VGETLANEs;
9774 case ISD::ZERO_EXTEND:
9775 case ISD::ANY_EXTEND:
9776 Opc = ARMISD::VGETLANEu;
9779 return DAG.getNode(Opc, SDLoc(N), VT, Vec, Lane);
9786 /// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
9787 /// to match f32 max/min patterns to use NEON vmax/vmin instructions.
9788 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
9789 const ARMSubtarget *ST) {
9790 // If the target supports NEON, try to use vmax/vmin instructions for f32
9791 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set,
9792 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
9793 // a NaN; only do the transformation when it matches that behavior.
9795 // For now only do this when using NEON for FP operations; if using VFP, it
9796 // is not obvious that the benefit outweighs the cost of switching to the
9798 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
9799 N->getValueType(0) != MVT::f32)
9802 SDValue CondLHS = N->getOperand(0);
9803 SDValue CondRHS = N->getOperand(1);
9804 SDValue LHS = N->getOperand(2);
9805 SDValue RHS = N->getOperand(3);
9806 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
9808 unsigned Opcode = 0;
9810 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
9811 IsReversed = false; // x CC y ? x : y
9812 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
9813 IsReversed = true ; // x CC y ? y : x
9827 // If LHS is NaN, an ordered comparison will be false and the result will
9828 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
9829 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
9830 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
9831 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
9833 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
9834 // will return -0, so vmin can only be used for unsafe math or if one of
9835 // the operands is known to be nonzero.
9836 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
9837 !DAG.getTarget().Options.UnsafeFPMath &&
9838 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
9840 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
9849 // If LHS is NaN, an ordered comparison will be false and the result will
9850 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
9851 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
9852 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
9853 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
9855 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
9856 // will return +0, so vmax can only be used for unsafe math or if one of
9857 // the operands is known to be nonzero.
9858 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
9859 !DAG.getTarget().Options.UnsafeFPMath &&
9860 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
9862 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
9868 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), LHS, RHS);
9871 /// PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV.
9873 ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const {
9874 SDValue Cmp = N->getOperand(4);
9875 if (Cmp.getOpcode() != ARMISD::CMPZ)
9876 // Only looking at EQ and NE cases.
9879 EVT VT = N->getValueType(0);
9881 SDValue LHS = Cmp.getOperand(0);
9882 SDValue RHS = Cmp.getOperand(1);
9883 SDValue FalseVal = N->getOperand(0);
9884 SDValue TrueVal = N->getOperand(1);
9885 SDValue ARMcc = N->getOperand(2);
9886 ARMCC::CondCodes CC =
9887 (ARMCC::CondCodes)cast<ConstantSDNode>(ARMcc)->getZExtValue();
9905 /// FIXME: Turn this into a target neutral optimization?
9907 if (CC == ARMCC::NE && FalseVal == RHS && FalseVal != LHS) {
9908 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, TrueVal, ARMcc,
9909 N->getOperand(3), Cmp);
9910 } else if (CC == ARMCC::EQ && TrueVal == RHS) {
9912 SDValue NewCmp = getARMCmp(LHS, RHS, ISD::SETNE, ARMcc, DAG, dl);
9913 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, FalseVal, ARMcc,
9914 N->getOperand(3), NewCmp);
9917 if (Res.getNode()) {
9918 APInt KnownZero, KnownOne;
9919 DAG.computeKnownBits(SDValue(N,0), KnownZero, KnownOne);
9920 // Capture demanded bits information that would be otherwise lost.
9921 if (KnownZero == 0xfffffffe)
9922 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
9923 DAG.getValueType(MVT::i1));
9924 else if (KnownZero == 0xffffff00)
9925 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
9926 DAG.getValueType(MVT::i8));
9927 else if (KnownZero == 0xffff0000)
9928 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
9929 DAG.getValueType(MVT::i16));
9935 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
9936 DAGCombinerInfo &DCI) const {
9937 switch (N->getOpcode()) {
9939 case ISD::ADDC: return PerformADDCCombine(N, DCI, Subtarget);
9940 case ISD::ADD: return PerformADDCombine(N, DCI, Subtarget);
9941 case ISD::SUB: return PerformSUBCombine(N, DCI);
9942 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
9943 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
9944 case ISD::XOR: return PerformXORCombine(N, DCI, Subtarget);
9945 case ISD::AND: return PerformANDCombine(N, DCI, Subtarget);
9946 case ARMISD::BFI: return PerformBFICombine(N, DCI);
9947 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI, Subtarget);
9948 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
9949 case ISD::STORE: return PerformSTORECombine(N, DCI);
9950 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI, Subtarget);
9951 case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI);
9952 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
9953 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
9954 case ISD::FP_TO_SINT:
9955 case ISD::FP_TO_UINT: return PerformVCVTCombine(N, DCI, Subtarget);
9956 case ISD::FDIV: return PerformVDIVCombine(N, DCI, Subtarget);
9957 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
9960 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
9961 case ISD::SIGN_EXTEND:
9962 case ISD::ZERO_EXTEND:
9963 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
9964 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
9965 case ARMISD::CMOV: return PerformCMOVCombine(N, DCI.DAG);
9966 case ISD::LOAD: return PerformLOADCombine(N, DCI);
9967 case ARMISD::VLD2DUP:
9968 case ARMISD::VLD3DUP:
9969 case ARMISD::VLD4DUP:
9970 return PerformVLDCombine(N, DCI);
9971 case ARMISD::BUILD_VECTOR:
9972 return PerformARMBUILD_VECTORCombine(N, DCI);
9973 case ISD::INTRINSIC_VOID:
9974 case ISD::INTRINSIC_W_CHAIN:
9975 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9976 case Intrinsic::arm_neon_vld1:
9977 case Intrinsic::arm_neon_vld2:
9978 case Intrinsic::arm_neon_vld3:
9979 case Intrinsic::arm_neon_vld4:
9980 case Intrinsic::arm_neon_vld2lane:
9981 case Intrinsic::arm_neon_vld3lane:
9982 case Intrinsic::arm_neon_vld4lane:
9983 case Intrinsic::arm_neon_vst1:
9984 case Intrinsic::arm_neon_vst2:
9985 case Intrinsic::arm_neon_vst3:
9986 case Intrinsic::arm_neon_vst4:
9987 case Intrinsic::arm_neon_vst2lane:
9988 case Intrinsic::arm_neon_vst3lane:
9989 case Intrinsic::arm_neon_vst4lane:
9990 return PerformVLDCombine(N, DCI);
9998 bool ARMTargetLowering::isDesirableToTransformToIntegerOp(unsigned Opc,
10000 return (VT == MVT::f32) && (Opc == ISD::LOAD || Opc == ISD::STORE);
10003 bool ARMTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
10006 bool *Fast) const {
10007 // The AllowsUnaliged flag models the SCTLR.A setting in ARM cpus
10008 bool AllowsUnaligned = Subtarget->allowsUnalignedMem();
10010 switch (VT.getSimpleVT().SimpleTy) {
10016 // Unaligned access can use (for example) LRDB, LRDH, LDR
10017 if (AllowsUnaligned) {
10019 *Fast = Subtarget->hasV7Ops();
10026 // For any little-endian targets with neon, we can support unaligned ld/st
10027 // of D and Q (e.g. {D0,D1}) registers by using vld1.i8/vst1.i8.
10028 // A big-endian target may also explicitly support unaligned accesses
10029 if (Subtarget->hasNEON() && (AllowsUnaligned || isLittleEndian())) {
10039 static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign,
10040 unsigned AlignCheck) {
10041 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) &&
10042 (DstAlign == 0 || DstAlign % AlignCheck == 0));
10045 EVT ARMTargetLowering::getOptimalMemOpType(uint64_t Size,
10046 unsigned DstAlign, unsigned SrcAlign,
10047 bool IsMemset, bool ZeroMemset,
10049 MachineFunction &MF) const {
10050 const Function *F = MF.getFunction();
10052 // See if we can use NEON instructions for this...
10053 if ((!IsMemset || ZeroMemset) && Subtarget->hasNEON() &&
10054 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
10057 (memOpAlign(SrcAlign, DstAlign, 16) ||
10058 (allowsMisalignedMemoryAccesses(MVT::v2f64, 0, 1, &Fast) && Fast))) {
10060 } else if (Size >= 8 &&
10061 (memOpAlign(SrcAlign, DstAlign, 8) ||
10062 (allowsMisalignedMemoryAccesses(MVT::f64, 0, 1, &Fast) &&
10068 // Lowering to i32/i16 if the size permits.
10071 else if (Size >= 2)
10074 // Let the target-independent logic figure it out.
10078 bool ARMTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
10079 if (Val.getOpcode() != ISD::LOAD)
10082 EVT VT1 = Val.getValueType();
10083 if (!VT1.isSimple() || !VT1.isInteger() ||
10084 !VT2.isSimple() || !VT2.isInteger())
10087 switch (VT1.getSimpleVT().SimpleTy) {
10092 // 8-bit and 16-bit loads implicitly zero-extend to 32-bits.
10099 bool ARMTargetLowering::isVectorLoadExtDesirable(SDValue ExtVal) const {
10100 EVT VT = ExtVal.getValueType();
10102 if (!isTypeLegal(VT))
10105 // Don't create a loadext if we can fold the extension into a wide/long
10107 // If there's more than one user instruction, the loadext is desirable no
10108 // matter what. There can be two uses by the same instruction.
10109 if (ExtVal->use_empty() ||
10110 !ExtVal->use_begin()->isOnlyUserOf(ExtVal.getNode()))
10113 SDNode *U = *ExtVal->use_begin();
10114 if ((U->getOpcode() == ISD::ADD || U->getOpcode() == ISD::SUB ||
10115 U->getOpcode() == ISD::SHL || U->getOpcode() == ARMISD::VSHL))
10121 bool ARMTargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
10122 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
10125 if (!isTypeLegal(EVT::getEVT(Ty1)))
10128 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
10130 // Assuming the caller doesn't have a zeroext or signext return parameter,
10131 // truncation all the way down to i1 is valid.
10136 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
10140 unsigned Scale = 1;
10141 switch (VT.getSimpleVT().SimpleTy) {
10142 default: return false;
10157 if ((V & (Scale - 1)) != 0)
10160 return V == (V & ((1LL << 5) - 1));
10163 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
10164 const ARMSubtarget *Subtarget) {
10165 bool isNeg = false;
10171 switch (VT.getSimpleVT().SimpleTy) {
10172 default: return false;
10177 // + imm12 or - imm8
10179 return V == (V & ((1LL << 8) - 1));
10180 return V == (V & ((1LL << 12) - 1));
10183 // Same as ARM mode. FIXME: NEON?
10184 if (!Subtarget->hasVFP2())
10189 return V == (V & ((1LL << 8) - 1));
10193 /// isLegalAddressImmediate - Return true if the integer value can be used
10194 /// as the offset of the target addressing mode for load / store of the
10196 static bool isLegalAddressImmediate(int64_t V, EVT VT,
10197 const ARMSubtarget *Subtarget) {
10201 if (!VT.isSimple())
10204 if (Subtarget->isThumb1Only())
10205 return isLegalT1AddressImmediate(V, VT);
10206 else if (Subtarget->isThumb2())
10207 return isLegalT2AddressImmediate(V, VT, Subtarget);
10212 switch (VT.getSimpleVT().SimpleTy) {
10213 default: return false;
10218 return V == (V & ((1LL << 12) - 1));
10221 return V == (V & ((1LL << 8) - 1));
10224 if (!Subtarget->hasVFP2()) // FIXME: NEON?
10229 return V == (V & ((1LL << 8) - 1));
10233 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
10235 int Scale = AM.Scale;
10239 switch (VT.getSimpleVT().SimpleTy) {
10240 default: return false;
10248 Scale = Scale & ~1;
10249 return Scale == 2 || Scale == 4 || Scale == 8;
10252 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
10256 // Note, we allow "void" uses (basically, uses that aren't loads or
10257 // stores), because arm allows folding a scale into many arithmetic
10258 // operations. This should be made more precise and revisited later.
10260 // Allow r << imm, but the imm has to be a multiple of two.
10261 if (Scale & 1) return false;
10262 return isPowerOf2_32(Scale);
10266 /// isLegalAddressingMode - Return true if the addressing mode represented
10267 /// by AM is legal for this target, for a load/store of the specified type.
10268 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
10270 unsigned AS) const {
10271 EVT VT = getValueType(Ty, true);
10272 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
10275 // Can never fold addr of global into load/store.
10279 switch (AM.Scale) {
10280 case 0: // no scale reg, must be "r+i" or "r", or "i".
10283 if (Subtarget->isThumb1Only())
10287 // ARM doesn't support any R+R*scale+imm addr modes.
10291 if (!VT.isSimple())
10294 if (Subtarget->isThumb2())
10295 return isLegalT2ScaledAddressingMode(AM, VT);
10297 int Scale = AM.Scale;
10298 switch (VT.getSimpleVT().SimpleTy) {
10299 default: return false;
10303 if (Scale < 0) Scale = -Scale;
10307 return isPowerOf2_32(Scale & ~1);
10311 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
10316 // Note, we allow "void" uses (basically, uses that aren't loads or
10317 // stores), because arm allows folding a scale into many arithmetic
10318 // operations. This should be made more precise and revisited later.
10320 // Allow r << imm, but the imm has to be a multiple of two.
10321 if (Scale & 1) return false;
10322 return isPowerOf2_32(Scale);
10328 /// isLegalICmpImmediate - Return true if the specified immediate is legal
10329 /// icmp immediate, that is the target has icmp instructions which can compare
10330 /// a register against the immediate without having to materialize the
10331 /// immediate into a register.
10332 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
10333 // Thumb2 and ARM modes can use cmn for negative immediates.
10334 if (!Subtarget->isThumb())
10335 return ARM_AM::getSOImmVal(std::abs(Imm)) != -1;
10336 if (Subtarget->isThumb2())
10337 return ARM_AM::getT2SOImmVal(std::abs(Imm)) != -1;
10338 // Thumb1 doesn't have cmn, and only 8-bit immediates.
10339 return Imm >= 0 && Imm <= 255;
10342 /// isLegalAddImmediate - Return true if the specified immediate is a legal add
10343 /// *or sub* immediate, that is the target has add or sub instructions which can
10344 /// add a register with the immediate without having to materialize the
10345 /// immediate into a register.
10346 bool ARMTargetLowering::isLegalAddImmediate(int64_t Imm) const {
10347 // Same encoding for add/sub, just flip the sign.
10348 int64_t AbsImm = std::abs(Imm);
10349 if (!Subtarget->isThumb())
10350 return ARM_AM::getSOImmVal(AbsImm) != -1;
10351 if (Subtarget->isThumb2())
10352 return ARM_AM::getT2SOImmVal(AbsImm) != -1;
10353 // Thumb1 only has 8-bit unsigned immediate.
10354 return AbsImm >= 0 && AbsImm <= 255;
10357 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
10358 bool isSEXTLoad, SDValue &Base,
10359 SDValue &Offset, bool &isInc,
10360 SelectionDAG &DAG) {
10361 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
10364 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
10365 // AddressingMode 3
10366 Base = Ptr->getOperand(0);
10367 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
10368 int RHSC = (int)RHS->getZExtValue();
10369 if (RHSC < 0 && RHSC > -256) {
10370 assert(Ptr->getOpcode() == ISD::ADD);
10372 Offset = DAG.getConstant(-RHSC, SDLoc(Ptr), RHS->getValueType(0));
10376 isInc = (Ptr->getOpcode() == ISD::ADD);
10377 Offset = Ptr->getOperand(1);
10379 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
10380 // AddressingMode 2
10381 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
10382 int RHSC = (int)RHS->getZExtValue();
10383 if (RHSC < 0 && RHSC > -0x1000) {
10384 assert(Ptr->getOpcode() == ISD::ADD);
10386 Offset = DAG.getConstant(-RHSC, SDLoc(Ptr), RHS->getValueType(0));
10387 Base = Ptr->getOperand(0);
10392 if (Ptr->getOpcode() == ISD::ADD) {
10394 ARM_AM::ShiftOpc ShOpcVal=
10395 ARM_AM::getShiftOpcForNode(Ptr->getOperand(0).getOpcode());
10396 if (ShOpcVal != ARM_AM::no_shift) {
10397 Base = Ptr->getOperand(1);
10398 Offset = Ptr->getOperand(0);
10400 Base = Ptr->getOperand(0);
10401 Offset = Ptr->getOperand(1);
10406 isInc = (Ptr->getOpcode() == ISD::ADD);
10407 Base = Ptr->getOperand(0);
10408 Offset = Ptr->getOperand(1);
10412 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
10416 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
10417 bool isSEXTLoad, SDValue &Base,
10418 SDValue &Offset, bool &isInc,
10419 SelectionDAG &DAG) {
10420 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
10423 Base = Ptr->getOperand(0);
10424 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
10425 int RHSC = (int)RHS->getZExtValue();
10426 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
10427 assert(Ptr->getOpcode() == ISD::ADD);
10429 Offset = DAG.getConstant(-RHSC, SDLoc(Ptr), RHS->getValueType(0));
10431 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
10432 isInc = Ptr->getOpcode() == ISD::ADD;
10433 Offset = DAG.getConstant(RHSC, SDLoc(Ptr), RHS->getValueType(0));
10441 /// getPreIndexedAddressParts - returns true by value, base pointer and
10442 /// offset pointer and addressing mode by reference if the node's address
10443 /// can be legally represented as pre-indexed load / store address.
10445 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
10447 ISD::MemIndexedMode &AM,
10448 SelectionDAG &DAG) const {
10449 if (Subtarget->isThumb1Only())
10454 bool isSEXTLoad = false;
10455 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
10456 Ptr = LD->getBasePtr();
10457 VT = LD->getMemoryVT();
10458 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
10459 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
10460 Ptr = ST->getBasePtr();
10461 VT = ST->getMemoryVT();
10466 bool isLegal = false;
10467 if (Subtarget->isThumb2())
10468 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
10469 Offset, isInc, DAG);
10471 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
10472 Offset, isInc, DAG);
10476 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
10480 /// getPostIndexedAddressParts - returns true by value, base pointer and
10481 /// offset pointer and addressing mode by reference if this node can be
10482 /// combined with a load / store to form a post-indexed load / store.
10483 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
10486 ISD::MemIndexedMode &AM,
10487 SelectionDAG &DAG) const {
10488 if (Subtarget->isThumb1Only())
10493 bool isSEXTLoad = false;
10494 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
10495 VT = LD->getMemoryVT();
10496 Ptr = LD->getBasePtr();
10497 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
10498 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
10499 VT = ST->getMemoryVT();
10500 Ptr = ST->getBasePtr();
10505 bool isLegal = false;
10506 if (Subtarget->isThumb2())
10507 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
10510 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
10516 // Swap base ptr and offset to catch more post-index load / store when
10517 // it's legal. In Thumb2 mode, offset must be an immediate.
10518 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
10519 !Subtarget->isThumb2())
10520 std::swap(Base, Offset);
10522 // Post-indexed load / store update the base pointer.
10527 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
10531 void ARMTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
10534 const SelectionDAG &DAG,
10535 unsigned Depth) const {
10536 unsigned BitWidth = KnownOne.getBitWidth();
10537 KnownZero = KnownOne = APInt(BitWidth, 0);
10538 switch (Op.getOpcode()) {
10544 // These nodes' second result is a boolean
10545 if (Op.getResNo() == 0)
10547 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
10549 case ARMISD::CMOV: {
10550 // Bits are known zero/one if known on the LHS and RHS.
10551 DAG.computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1);
10552 if (KnownZero == 0 && KnownOne == 0) return;
10554 APInt KnownZeroRHS, KnownOneRHS;
10555 DAG.computeKnownBits(Op.getOperand(1), KnownZeroRHS, KnownOneRHS, Depth+1);
10556 KnownZero &= KnownZeroRHS;
10557 KnownOne &= KnownOneRHS;
10560 case ISD::INTRINSIC_W_CHAIN: {
10561 ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
10562 Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
10565 case Intrinsic::arm_ldaex:
10566 case Intrinsic::arm_ldrex: {
10567 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();
10568 unsigned MemBits = VT.getScalarType().getSizeInBits();
10569 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
10577 //===----------------------------------------------------------------------===//
10578 // ARM Inline Assembly Support
10579 //===----------------------------------------------------------------------===//
10581 bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const {
10582 // Looking for "rev" which is V6+.
10583 if (!Subtarget->hasV6Ops())
10586 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
10587 std::string AsmStr = IA->getAsmString();
10588 SmallVector<StringRef, 4> AsmPieces;
10589 SplitString(AsmStr, AsmPieces, ";\n");
10591 switch (AsmPieces.size()) {
10592 default: return false;
10594 AsmStr = AsmPieces[0];
10596 SplitString(AsmStr, AsmPieces, " \t,");
10599 if (AsmPieces.size() == 3 &&
10600 AsmPieces[0] == "rev" && AsmPieces[1] == "$0" && AsmPieces[2] == "$1" &&
10601 IA->getConstraintString().compare(0, 4, "=l,l") == 0) {
10602 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
10603 if (Ty && Ty->getBitWidth() == 32)
10604 return IntrinsicLowering::LowerToByteSwap(CI);
10612 /// getConstraintType - Given a constraint letter, return the type of
10613 /// constraint it is for this target.
10614 ARMTargetLowering::ConstraintType
10615 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
10616 if (Constraint.size() == 1) {
10617 switch (Constraint[0]) {
10619 case 'l': return C_RegisterClass;
10620 case 'w': return C_RegisterClass;
10621 case 'h': return C_RegisterClass;
10622 case 'x': return C_RegisterClass;
10623 case 't': return C_RegisterClass;
10624 case 'j': return C_Other; // Constant for movw.
10625 // An address with a single base register. Due to the way we
10626 // currently handle addresses it is the same as an 'r' memory constraint.
10627 case 'Q': return C_Memory;
10629 } else if (Constraint.size() == 2) {
10630 switch (Constraint[0]) {
10632 // All 'U+' constraints are addresses.
10633 case 'U': return C_Memory;
10636 return TargetLowering::getConstraintType(Constraint);
10639 /// Examine constraint type and operand type and determine a weight value.
10640 /// This object must already have been set up with the operand type
10641 /// and the current alternative constraint selected.
10642 TargetLowering::ConstraintWeight
10643 ARMTargetLowering::getSingleConstraintMatchWeight(
10644 AsmOperandInfo &info, const char *constraint) const {
10645 ConstraintWeight weight = CW_Invalid;
10646 Value *CallOperandVal = info.CallOperandVal;
10647 // If we don't have a value, we can't do a match,
10648 // but allow it at the lowest weight.
10649 if (!CallOperandVal)
10651 Type *type = CallOperandVal->getType();
10652 // Look at the constraint type.
10653 switch (*constraint) {
10655 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
10658 if (type->isIntegerTy()) {
10659 if (Subtarget->isThumb())
10660 weight = CW_SpecificReg;
10662 weight = CW_Register;
10666 if (type->isFloatingPointTy())
10667 weight = CW_Register;
10673 typedef std::pair<unsigned, const TargetRegisterClass*> RCPair;
10675 ARMTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
10676 const std::string &Constraint,
10678 if (Constraint.size() == 1) {
10679 // GCC ARM Constraint Letters
10680 switch (Constraint[0]) {
10681 case 'l': // Low regs or general regs.
10682 if (Subtarget->isThumb())
10683 return RCPair(0U, &ARM::tGPRRegClass);
10684 return RCPair(0U, &ARM::GPRRegClass);
10685 case 'h': // High regs or no regs.
10686 if (Subtarget->isThumb())
10687 return RCPair(0U, &ARM::hGPRRegClass);
10690 if (Subtarget->isThumb1Only())
10691 return RCPair(0U, &ARM::tGPRRegClass);
10692 return RCPair(0U, &ARM::GPRRegClass);
10694 if (VT == MVT::Other)
10696 if (VT == MVT::f32)
10697 return RCPair(0U, &ARM::SPRRegClass);
10698 if (VT.getSizeInBits() == 64)
10699 return RCPair(0U, &ARM::DPRRegClass);
10700 if (VT.getSizeInBits() == 128)
10701 return RCPair(0U, &ARM::QPRRegClass);
10704 if (VT == MVT::Other)
10706 if (VT == MVT::f32)
10707 return RCPair(0U, &ARM::SPR_8RegClass);
10708 if (VT.getSizeInBits() == 64)
10709 return RCPair(0U, &ARM::DPR_8RegClass);
10710 if (VT.getSizeInBits() == 128)
10711 return RCPair(0U, &ARM::QPR_8RegClass);
10714 if (VT == MVT::f32)
10715 return RCPair(0U, &ARM::SPRRegClass);
10719 if (StringRef("{cc}").equals_lower(Constraint))
10720 return std::make_pair(unsigned(ARM::CPSR), &ARM::CCRRegClass);
10722 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
10725 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
10726 /// vector. If it is invalid, don't add anything to Ops.
10727 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
10728 std::string &Constraint,
10729 std::vector<SDValue>&Ops,
10730 SelectionDAG &DAG) const {
10733 // Currently only support length 1 constraints.
10734 if (Constraint.length() != 1) return;
10736 char ConstraintLetter = Constraint[0];
10737 switch (ConstraintLetter) {
10740 case 'I': case 'J': case 'K': case 'L':
10741 case 'M': case 'N': case 'O':
10742 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
10746 int64_t CVal64 = C->getSExtValue();
10747 int CVal = (int) CVal64;
10748 // None of these constraints allow values larger than 32 bits. Check
10749 // that the value fits in an int.
10750 if (CVal != CVal64)
10753 switch (ConstraintLetter) {
10755 // Constant suitable for movw, must be between 0 and
10757 if (Subtarget->hasV6T2Ops())
10758 if (CVal >= 0 && CVal <= 65535)
10762 if (Subtarget->isThumb1Only()) {
10763 // This must be a constant between 0 and 255, for ADD
10765 if (CVal >= 0 && CVal <= 255)
10767 } else if (Subtarget->isThumb2()) {
10768 // A constant that can be used as an immediate value in a
10769 // data-processing instruction.
10770 if (ARM_AM::getT2SOImmVal(CVal) != -1)
10773 // A constant that can be used as an immediate value in a
10774 // data-processing instruction.
10775 if (ARM_AM::getSOImmVal(CVal) != -1)
10781 if (Subtarget->isThumb()) { // FIXME thumb2
10782 // This must be a constant between -255 and -1, for negated ADD
10783 // immediates. This can be used in GCC with an "n" modifier that
10784 // prints the negated value, for use with SUB instructions. It is
10785 // not useful otherwise but is implemented for compatibility.
10786 if (CVal >= -255 && CVal <= -1)
10789 // This must be a constant between -4095 and 4095. It is not clear
10790 // what this constraint is intended for. Implemented for
10791 // compatibility with GCC.
10792 if (CVal >= -4095 && CVal <= 4095)
10798 if (Subtarget->isThumb1Only()) {
10799 // A 32-bit value where only one byte has a nonzero value. Exclude
10800 // zero to match GCC. This constraint is used by GCC internally for
10801 // constants that can be loaded with a move/shift combination.
10802 // It is not useful otherwise but is implemented for compatibility.
10803 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
10805 } else if (Subtarget->isThumb2()) {
10806 // A constant whose bitwise inverse can be used as an immediate
10807 // value in a data-processing instruction. This can be used in GCC
10808 // with a "B" modifier that prints the inverted value, for use with
10809 // BIC and MVN instructions. It is not useful otherwise but is
10810 // implemented for compatibility.
10811 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
10814 // A constant whose bitwise inverse can be used as an immediate
10815 // value in a data-processing instruction. This can be used in GCC
10816 // with a "B" modifier that prints the inverted value, for use with
10817 // BIC and MVN instructions. It is not useful otherwise but is
10818 // implemented for compatibility.
10819 if (ARM_AM::getSOImmVal(~CVal) != -1)
10825 if (Subtarget->isThumb1Only()) {
10826 // This must be a constant between -7 and 7,
10827 // for 3-operand ADD/SUB immediate instructions.
10828 if (CVal >= -7 && CVal < 7)
10830 } else if (Subtarget->isThumb2()) {
10831 // A constant whose negation can be used as an immediate value in a
10832 // data-processing instruction. This can be used in GCC with an "n"
10833 // modifier that prints the negated value, for use with SUB
10834 // instructions. It is not useful otherwise but is implemented for
10836 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
10839 // A constant whose negation can be used as an immediate value in a
10840 // data-processing instruction. This can be used in GCC with an "n"
10841 // modifier that prints the negated value, for use with SUB
10842 // instructions. It is not useful otherwise but is implemented for
10844 if (ARM_AM::getSOImmVal(-CVal) != -1)
10850 if (Subtarget->isThumb()) { // FIXME thumb2
10851 // This must be a multiple of 4 between 0 and 1020, for
10852 // ADD sp + immediate.
10853 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
10856 // A power of two or a constant between 0 and 32. This is used in
10857 // GCC for the shift amount on shifted register operands, but it is
10858 // useful in general for any shift amounts.
10859 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
10865 if (Subtarget->isThumb()) { // FIXME thumb2
10866 // This must be a constant between 0 and 31, for shift amounts.
10867 if (CVal >= 0 && CVal <= 31)
10873 if (Subtarget->isThumb()) { // FIXME thumb2
10874 // This must be a multiple of 4 between -508 and 508, for
10875 // ADD/SUB sp = sp + immediate.
10876 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
10881 Result = DAG.getTargetConstant(CVal, SDLoc(Op), Op.getValueType());
10885 if (Result.getNode()) {
10886 Ops.push_back(Result);
10889 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
10892 SDValue ARMTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const {
10893 assert(Subtarget->isTargetAEABI() && "Register-based DivRem lowering only");
10894 unsigned Opcode = Op->getOpcode();
10895 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
10896 "Invalid opcode for Div/Rem lowering");
10897 bool isSigned = (Opcode == ISD::SDIVREM);
10898 EVT VT = Op->getValueType(0);
10899 Type *Ty = VT.getTypeForEVT(*DAG.getContext());
10902 switch (VT.getSimpleVT().SimpleTy) {
10903 default: llvm_unreachable("Unexpected request for libcall!");
10904 case MVT::i8: LC = isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
10905 case MVT::i16: LC = isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
10906 case MVT::i32: LC = isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
10907 case MVT::i64: LC = isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
10910 SDValue InChain = DAG.getEntryNode();
10912 TargetLowering::ArgListTy Args;
10913 TargetLowering::ArgListEntry Entry;
10914 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
10915 EVT ArgVT = Op->getOperand(i).getValueType();
10916 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
10917 Entry.Node = Op->getOperand(i);
10919 Entry.isSExt = isSigned;
10920 Entry.isZExt = !isSigned;
10921 Args.push_back(Entry);
10924 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
10927 Type *RetTy = (Type*)StructType::get(Ty, Ty, nullptr);
10930 TargetLowering::CallLoweringInfo CLI(DAG);
10931 CLI.setDebugLoc(dl).setChain(InChain)
10932 .setCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
10933 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
10935 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
10936 return CallInfo.first;
10940 ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const {
10941 assert(Subtarget->isTargetWindows() && "unsupported target platform");
10945 SDValue Chain = Op.getOperand(0);
10946 SDValue Size = Op.getOperand(1);
10948 SDValue Words = DAG.getNode(ISD::SRL, DL, MVT::i32, Size,
10949 DAG.getConstant(2, DL, MVT::i32));
10952 Chain = DAG.getCopyToReg(Chain, DL, ARM::R4, Words, Flag);
10953 Flag = Chain.getValue(1);
10955 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10956 Chain = DAG.getNode(ARMISD::WIN__CHKSTK, DL, NodeTys, Chain, Flag);
10958 SDValue NewSP = DAG.getCopyFromReg(Chain, DL, ARM::SP, MVT::i32);
10959 Chain = NewSP.getValue(1);
10961 SDValue Ops[2] = { NewSP, Chain };
10962 return DAG.getMergeValues(Ops, DL);
10965 SDValue ARMTargetLowering::LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const {
10966 assert(Op.getValueType() == MVT::f64 && Subtarget->isFPOnlySP() &&
10967 "Unexpected type for custom-lowering FP_EXTEND");
10970 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType());
10972 SDValue SrcVal = Op.getOperand(0);
10973 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
10974 /*isSigned*/ false, SDLoc(Op)).first;
10977 SDValue ARMTargetLowering::LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const {
10978 assert(Op.getOperand(0).getValueType() == MVT::f64 &&
10979 Subtarget->isFPOnlySP() &&
10980 "Unexpected type for custom-lowering FP_ROUND");
10983 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
10985 SDValue SrcVal = Op.getOperand(0);
10986 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
10987 /*isSigned*/ false, SDLoc(Op)).first;
10991 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
10992 // The ARM target isn't yet aware of offsets.
10996 bool ARM::isBitFieldInvertedMask(unsigned v) {
10997 if (v == 0xffffffff)
11000 // there can be 1's on either or both "outsides", all the "inside"
11001 // bits must be 0's
11002 return isShiftedMask_32(~v);
11005 /// isFPImmLegal - Returns true if the target can instruction select the
11006 /// specified FP immediate natively. If false, the legalizer will
11007 /// materialize the FP immediate as a load from a constant pool.
11008 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
11009 if (!Subtarget->hasVFP3())
11011 if (VT == MVT::f32)
11012 return ARM_AM::getFP32Imm(Imm) != -1;
11013 if (VT == MVT::f64 && !Subtarget->isFPOnlySP())
11014 return ARM_AM::getFP64Imm(Imm) != -1;
11018 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
11019 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
11020 /// specified in the intrinsic calls.
11021 bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
11023 unsigned Intrinsic) const {
11024 switch (Intrinsic) {
11025 case Intrinsic::arm_neon_vld1:
11026 case Intrinsic::arm_neon_vld2:
11027 case Intrinsic::arm_neon_vld3:
11028 case Intrinsic::arm_neon_vld4:
11029 case Intrinsic::arm_neon_vld2lane:
11030 case Intrinsic::arm_neon_vld3lane:
11031 case Intrinsic::arm_neon_vld4lane: {
11032 Info.opc = ISD::INTRINSIC_W_CHAIN;
11033 // Conservatively set memVT to the entire set of vectors loaded.
11034 uint64_t NumElts = getDataLayout()->getTypeAllocSize(I.getType()) / 8;
11035 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
11036 Info.ptrVal = I.getArgOperand(0);
11038 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
11039 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
11040 Info.vol = false; // volatile loads with NEON intrinsics not supported
11041 Info.readMem = true;
11042 Info.writeMem = false;
11045 case Intrinsic::arm_neon_vst1:
11046 case Intrinsic::arm_neon_vst2:
11047 case Intrinsic::arm_neon_vst3:
11048 case Intrinsic::arm_neon_vst4:
11049 case Intrinsic::arm_neon_vst2lane:
11050 case Intrinsic::arm_neon_vst3lane:
11051 case Intrinsic::arm_neon_vst4lane: {
11052 Info.opc = ISD::INTRINSIC_VOID;
11053 // Conservatively set memVT to the entire set of vectors stored.
11054 unsigned NumElts = 0;
11055 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
11056 Type *ArgTy = I.getArgOperand(ArgI)->getType();
11057 if (!ArgTy->isVectorTy())
11059 NumElts += getDataLayout()->getTypeAllocSize(ArgTy) / 8;
11061 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
11062 Info.ptrVal = I.getArgOperand(0);
11064 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
11065 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
11066 Info.vol = false; // volatile stores with NEON intrinsics not supported
11067 Info.readMem = false;
11068 Info.writeMem = true;
11071 case Intrinsic::arm_ldaex:
11072 case Intrinsic::arm_ldrex: {
11073 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
11074 Info.opc = ISD::INTRINSIC_W_CHAIN;
11075 Info.memVT = MVT::getVT(PtrTy->getElementType());
11076 Info.ptrVal = I.getArgOperand(0);
11078 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
11080 Info.readMem = true;
11081 Info.writeMem = false;
11084 case Intrinsic::arm_stlex:
11085 case Intrinsic::arm_strex: {
11086 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
11087 Info.opc = ISD::INTRINSIC_W_CHAIN;
11088 Info.memVT = MVT::getVT(PtrTy->getElementType());
11089 Info.ptrVal = I.getArgOperand(1);
11091 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
11093 Info.readMem = false;
11094 Info.writeMem = true;
11097 case Intrinsic::arm_stlexd:
11098 case Intrinsic::arm_strexd: {
11099 Info.opc = ISD::INTRINSIC_W_CHAIN;
11100 Info.memVT = MVT::i64;
11101 Info.ptrVal = I.getArgOperand(2);
11105 Info.readMem = false;
11106 Info.writeMem = true;
11109 case Intrinsic::arm_ldaexd:
11110 case Intrinsic::arm_ldrexd: {
11111 Info.opc = ISD::INTRINSIC_W_CHAIN;
11112 Info.memVT = MVT::i64;
11113 Info.ptrVal = I.getArgOperand(0);
11117 Info.readMem = true;
11118 Info.writeMem = false;
11128 /// \brief Returns true if it is beneficial to convert a load of a constant
11129 /// to just the constant itself.
11130 bool ARMTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
11132 assert(Ty->isIntegerTy());
11134 unsigned Bits = Ty->getPrimitiveSizeInBits();
11135 if (Bits == 0 || Bits > 32)
11140 bool ARMTargetLowering::hasLoadLinkedStoreConditional() const { return true; }
11142 Instruction* ARMTargetLowering::makeDMB(IRBuilder<> &Builder,
11143 ARM_MB::MemBOpt Domain) const {
11144 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
11146 // First, if the target has no DMB, see what fallback we can use.
11147 if (!Subtarget->hasDataBarrier()) {
11148 // Some ARMv6 cpus can support data barriers with an mcr instruction.
11149 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
11151 if (Subtarget->hasV6Ops() && !Subtarget->isThumb()) {
11152 Function *MCR = llvm::Intrinsic::getDeclaration(M, Intrinsic::arm_mcr);
11153 Value* args[6] = {Builder.getInt32(15), Builder.getInt32(0),
11154 Builder.getInt32(0), Builder.getInt32(7),
11155 Builder.getInt32(10), Builder.getInt32(5)};
11156 return Builder.CreateCall(MCR, args);
11158 // Instead of using barriers, atomic accesses on these subtargets use
11160 llvm_unreachable("makeDMB on a target so old that it has no barriers");
11163 Function *DMB = llvm::Intrinsic::getDeclaration(M, Intrinsic::arm_dmb);
11164 // Only a full system barrier exists in the M-class architectures.
11165 Domain = Subtarget->isMClass() ? ARM_MB::SY : Domain;
11166 Constant *CDomain = Builder.getInt32(Domain);
11167 return Builder.CreateCall(DMB, CDomain);
11171 // Based on http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
11172 Instruction* ARMTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
11173 AtomicOrdering Ord, bool IsStore,
11174 bool IsLoad) const {
11175 if (!getInsertFencesForAtomic())
11181 llvm_unreachable("Invalid fence: unordered/non-atomic");
11184 return nullptr; // Nothing to do
11185 case SequentiallyConsistent:
11187 return nullptr; // Nothing to do
11190 case AcquireRelease:
11191 if (Subtarget->isSwift())
11192 return makeDMB(Builder, ARM_MB::ISHST);
11193 // FIXME: add a comment with a link to documentation justifying this.
11195 return makeDMB(Builder, ARM_MB::ISH);
11197 llvm_unreachable("Unknown fence ordering in emitLeadingFence");
11200 Instruction* ARMTargetLowering::emitTrailingFence(IRBuilder<> &Builder,
11201 AtomicOrdering Ord, bool IsStore,
11202 bool IsLoad) const {
11203 if (!getInsertFencesForAtomic())
11209 llvm_unreachable("Invalid fence: unordered/not-atomic");
11212 return nullptr; // Nothing to do
11214 case AcquireRelease:
11215 case SequentiallyConsistent:
11216 return makeDMB(Builder, ARM_MB::ISH);
11218 llvm_unreachable("Unknown fence ordering in emitTrailingFence");
11221 // Loads and stores less than 64-bits are already atomic; ones above that
11222 // are doomed anyway, so defer to the default libcall and blame the OS when
11223 // things go wrong. Cortex M doesn't have ldrexd/strexd though, so don't emit
11224 // anything for those.
11225 bool ARMTargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
11226 unsigned Size = SI->getValueOperand()->getType()->getPrimitiveSizeInBits();
11227 return (Size == 64) && !Subtarget->isMClass();
11230 // Loads and stores less than 64-bits are already atomic; ones above that
11231 // are doomed anyway, so defer to the default libcall and blame the OS when
11232 // things go wrong. Cortex M doesn't have ldrexd/strexd though, so don't emit
11233 // anything for those.
11234 // FIXME: ldrd and strd are atomic if the CPU has LPAE (e.g. A15 has that
11235 // guarantee, see DDI0406C ARM architecture reference manual,
11236 // sections A8.8.72-74 LDRD)
11237 bool ARMTargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
11238 unsigned Size = LI->getType()->getPrimitiveSizeInBits();
11239 return (Size == 64) && !Subtarget->isMClass();
11242 // For the real atomic operations, we have ldrex/strex up to 32 bits,
11243 // and up to 64 bits on the non-M profiles
11244 TargetLoweringBase::AtomicRMWExpansionKind
11245 ARMTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
11246 unsigned Size = AI->getType()->getPrimitiveSizeInBits();
11247 return (Size <= (Subtarget->isMClass() ? 32U : 64U))
11248 ? AtomicRMWExpansionKind::LLSC
11249 : AtomicRMWExpansionKind::None;
11252 // This has so far only been implemented for MachO.
11253 bool ARMTargetLowering::useLoadStackGuardNode() const {
11254 return Subtarget->isTargetMachO();
11257 bool ARMTargetLowering::canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
11258 unsigned &Cost) const {
11259 // If we do not have NEON, vector types are not natively supported.
11260 if (!Subtarget->hasNEON())
11263 // Floating point values and vector values map to the same register file.
11264 // Therefore, althought we could do a store extract of a vector type, this is
11265 // better to leave at float as we have more freedom in the addressing mode for
11267 if (VectorTy->isFPOrFPVectorTy())
11270 // If the index is unknown at compile time, this is very expensive to lower
11271 // and it is not possible to combine the store with the extract.
11272 if (!isa<ConstantInt>(Idx))
11275 assert(VectorTy->isVectorTy() && "VectorTy is not a vector type");
11276 unsigned BitWidth = cast<VectorType>(VectorTy)->getBitWidth();
11277 // We can do a store + vector extract on any vector that fits perfectly in a D
11279 if (BitWidth == 64 || BitWidth == 128) {
11286 Value *ARMTargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
11287 AtomicOrdering Ord) const {
11288 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
11289 Type *ValTy = cast<PointerType>(Addr->getType())->getElementType();
11290 bool IsAcquire = isAtLeastAcquire(Ord);
11292 // Since i64 isn't legal and intrinsics don't get type-lowered, the ldrexd
11293 // intrinsic must return {i32, i32} and we have to recombine them into a
11294 // single i64 here.
11295 if (ValTy->getPrimitiveSizeInBits() == 64) {
11296 Intrinsic::ID Int =
11297 IsAcquire ? Intrinsic::arm_ldaexd : Intrinsic::arm_ldrexd;
11298 Function *Ldrex = llvm::Intrinsic::getDeclaration(M, Int);
11300 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
11301 Value *LoHi = Builder.CreateCall(Ldrex, Addr, "lohi");
11303 Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo");
11304 Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi");
11305 if (!Subtarget->isLittle())
11306 std::swap (Lo, Hi);
11307 Lo = Builder.CreateZExt(Lo, ValTy, "lo64");
11308 Hi = Builder.CreateZExt(Hi, ValTy, "hi64");
11309 return Builder.CreateOr(
11310 Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 32)), "val64");
11313 Type *Tys[] = { Addr->getType() };
11314 Intrinsic::ID Int = IsAcquire ? Intrinsic::arm_ldaex : Intrinsic::arm_ldrex;
11315 Function *Ldrex = llvm::Intrinsic::getDeclaration(M, Int, Tys);
11317 return Builder.CreateTruncOrBitCast(
11318 Builder.CreateCall(Ldrex, Addr),
11319 cast<PointerType>(Addr->getType())->getElementType());
11322 Value *ARMTargetLowering::emitStoreConditional(IRBuilder<> &Builder, Value *Val,
11324 AtomicOrdering Ord) const {
11325 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
11326 bool IsRelease = isAtLeastRelease(Ord);
11328 // Since the intrinsics must have legal type, the i64 intrinsics take two
11329 // parameters: "i32, i32". We must marshal Val into the appropriate form
11330 // before the call.
11331 if (Val->getType()->getPrimitiveSizeInBits() == 64) {
11332 Intrinsic::ID Int =
11333 IsRelease ? Intrinsic::arm_stlexd : Intrinsic::arm_strexd;
11334 Function *Strex = Intrinsic::getDeclaration(M, Int);
11335 Type *Int32Ty = Type::getInt32Ty(M->getContext());
11337 Value *Lo = Builder.CreateTrunc(Val, Int32Ty, "lo");
11338 Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 32), Int32Ty, "hi");
11339 if (!Subtarget->isLittle())
11340 std::swap (Lo, Hi);
11341 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
11342 return Builder.CreateCall(Strex, {Lo, Hi, Addr});
11345 Intrinsic::ID Int = IsRelease ? Intrinsic::arm_stlex : Intrinsic::arm_strex;
11346 Type *Tys[] = { Addr->getType() };
11347 Function *Strex = Intrinsic::getDeclaration(M, Int, Tys);
11349 return Builder.CreateCall(
11350 Strex, {Builder.CreateZExtOrBitCast(
11351 Val, Strex->getFunctionType()->getParamType(0)),
11363 static bool isHomogeneousAggregate(Type *Ty, HABaseType &Base,
11364 uint64_t &Members) {
11365 if (const StructType *ST = dyn_cast<StructType>(Ty)) {
11366 for (unsigned i = 0; i < ST->getNumElements(); ++i) {
11367 uint64_t SubMembers = 0;
11368 if (!isHomogeneousAggregate(ST->getElementType(i), Base, SubMembers))
11370 Members += SubMembers;
11372 } else if (const ArrayType *AT = dyn_cast<ArrayType>(Ty)) {
11373 uint64_t SubMembers = 0;
11374 if (!isHomogeneousAggregate(AT->getElementType(), Base, SubMembers))
11376 Members += SubMembers * AT->getNumElements();
11377 } else if (Ty->isFloatTy()) {
11378 if (Base != HA_UNKNOWN && Base != HA_FLOAT)
11382 } else if (Ty->isDoubleTy()) {
11383 if (Base != HA_UNKNOWN && Base != HA_DOUBLE)
11387 } else if (const VectorType *VT = dyn_cast<VectorType>(Ty)) {
11394 return VT->getBitWidth() == 64;
11396 return VT->getBitWidth() == 128;
11398 switch (VT->getBitWidth()) {
11411 return (Members > 0 && Members <= 4);
11414 /// \brief Return true if a type is an AAPCS-VFP homogeneous aggregate or one of
11415 /// [N x i32] or [N x i64]. This allows front-ends to skip emitting padding when
11416 /// passing according to AAPCS rules.
11417 bool ARMTargetLowering::functionArgumentNeedsConsecutiveRegisters(
11418 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const {
11419 if (getEffectiveCallingConv(CallConv, isVarArg) !=
11420 CallingConv::ARM_AAPCS_VFP)
11423 HABaseType Base = HA_UNKNOWN;
11424 uint64_t Members = 0;
11425 bool IsHA = isHomogeneousAggregate(Ty, Base, Members);
11426 DEBUG(dbgs() << "isHA: " << IsHA << " "; Ty->dump());
11428 bool IsIntArray = Ty->isArrayTy() && Ty->getArrayElementType()->isIntegerTy();
11429 return IsHA || IsIntArray;