1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "arm-isel"
17 #include "ARMAddressingModes.h"
18 #include "ARMCallingConv.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMISelLowering.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMPerfectShuffle.h"
23 #include "ARMRegisterInfo.h"
24 #include "ARMSubtarget.h"
25 #include "ARMTargetMachine.h"
26 #include "ARMTargetObjectFile.h"
27 #include "llvm/CallingConv.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Function.h"
30 #include "llvm/GlobalValue.h"
31 #include "llvm/Instruction.h"
32 #include "llvm/Instructions.h"
33 #include "llvm/Intrinsics.h"
34 #include "llvm/Type.h"
35 #include "llvm/CodeGen/CallingConvLower.h"
36 #include "llvm/CodeGen/MachineBasicBlock.h"
37 #include "llvm/CodeGen/MachineFrameInfo.h"
38 #include "llvm/CodeGen/MachineFunction.h"
39 #include "llvm/CodeGen/MachineInstrBuilder.h"
40 #include "llvm/CodeGen/MachineRegisterInfo.h"
41 #include "llvm/CodeGen/PseudoSourceValue.h"
42 #include "llvm/CodeGen/SelectionDAG.h"
43 #include "llvm/MC/MCSectionMachO.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/ADT/VectorExtras.h"
46 #include "llvm/ADT/Statistic.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Support/raw_ostream.h"
54 STATISTIC(NumTailCalls, "Number of tail calls");
56 // This option should go away when tail calls fully work.
58 EnableARMTailCalls("arm-tail-calls", cl::Hidden,
59 cl::desc("Generate tail calls (TEMPORARY OPTION)."),
63 EnableARMLongCalls("arm-long-calls", cl::Hidden,
64 cl::desc("Generate calls via indirect call instructions"),
68 ARMInterworking("arm-interworking", cl::Hidden,
69 cl::desc("Enable / disable ARM interworking (for debugging only)"),
72 void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
73 EVT PromotedBitwiseVT) {
74 if (VT != PromotedLdStVT) {
75 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
76 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
77 PromotedLdStVT.getSimpleVT());
79 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
80 AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
81 PromotedLdStVT.getSimpleVT());
84 EVT ElemTy = VT.getVectorElementType();
85 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
86 setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
87 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
88 if (ElemTy != MVT::i32) {
89 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
90 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand);
91 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand);
92 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand);
94 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
95 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
96 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
97 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Expand);
98 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
99 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
100 if (VT.isInteger()) {
101 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
102 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
103 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
104 setLoadExtAction(ISD::SEXTLOAD, VT.getSimpleVT(), Expand);
105 setLoadExtAction(ISD::ZEXTLOAD, VT.getSimpleVT(), Expand);
106 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
107 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
108 setTruncStoreAction(VT.getSimpleVT(),
109 (MVT::SimpleValueType)InnerVT, Expand);
111 setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand);
113 // Promote all bit-wise operations.
114 if (VT.isInteger() && VT != PromotedBitwiseVT) {
115 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
116 AddPromotedToType (ISD::AND, VT.getSimpleVT(),
117 PromotedBitwiseVT.getSimpleVT());
118 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
119 AddPromotedToType (ISD::OR, VT.getSimpleVT(),
120 PromotedBitwiseVT.getSimpleVT());
121 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
122 AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
123 PromotedBitwiseVT.getSimpleVT());
126 // Neon does not support vector divide/remainder operations.
127 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
128 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
129 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand);
130 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
131 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
132 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
135 void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
136 addRegisterClass(VT, ARM::DPRRegisterClass);
137 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
140 void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
141 addRegisterClass(VT, ARM::QPRRegisterClass);
142 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
145 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
146 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
147 return new TargetLoweringObjectFileMachO();
149 return new ARMElfTargetObjectFile();
152 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
153 : TargetLowering(TM, createTLOF(TM)) {
154 Subtarget = &TM.getSubtarget<ARMSubtarget>();
155 RegInfo = TM.getRegisterInfo();
156 Itins = TM.getInstrItineraryData();
158 if (Subtarget->isTargetDarwin()) {
159 // Uses VFP for Thumb libfuncs if available.
160 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
161 // Single-precision floating-point arithmetic.
162 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
163 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
164 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
165 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
167 // Double-precision floating-point arithmetic.
168 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
169 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
170 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
171 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
173 // Single-precision comparisons.
174 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
175 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
176 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
177 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
178 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
179 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
180 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
181 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
183 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
184 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
185 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
186 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
187 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
188 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
189 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
190 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
192 // Double-precision comparisons.
193 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
194 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
195 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
196 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
197 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
198 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
199 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
200 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
202 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
203 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
204 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
205 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
206 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
207 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
208 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
209 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
211 // Floating-point to integer conversions.
212 // i64 conversions are done via library routines even when generating VFP
213 // instructions, so use the same ones.
214 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
215 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
216 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
217 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
219 // Conversions between floating types.
220 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
221 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
223 // Integer to floating-point conversions.
224 // i64 conversions are done via library routines even when generating VFP
225 // instructions, so use the same ones.
226 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
227 // e.g., __floatunsidf vs. __floatunssidfvfp.
228 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
229 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
230 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
231 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
235 // These libcalls are not available in 32-bit.
236 setLibcallName(RTLIB::SHL_I128, 0);
237 setLibcallName(RTLIB::SRL_I128, 0);
238 setLibcallName(RTLIB::SRA_I128, 0);
240 if (Subtarget->isAAPCS_ABI()) {
241 // Double-precision floating-point arithmetic helper functions
242 // RTABI chapter 4.1.2, Table 2
243 setLibcallName(RTLIB::ADD_F64, "__aeabi_dadd");
244 setLibcallName(RTLIB::DIV_F64, "__aeabi_ddiv");
245 setLibcallName(RTLIB::MUL_F64, "__aeabi_dmul");
246 setLibcallName(RTLIB::SUB_F64, "__aeabi_dsub");
247 setLibcallCallingConv(RTLIB::ADD_F64, CallingConv::ARM_AAPCS);
248 setLibcallCallingConv(RTLIB::DIV_F64, CallingConv::ARM_AAPCS);
249 setLibcallCallingConv(RTLIB::MUL_F64, CallingConv::ARM_AAPCS);
250 setLibcallCallingConv(RTLIB::SUB_F64, CallingConv::ARM_AAPCS);
252 // Double-precision floating-point comparison helper functions
253 // RTABI chapter 4.1.2, Table 3
254 setLibcallName(RTLIB::OEQ_F64, "__aeabi_dcmpeq");
255 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
256 setLibcallName(RTLIB::UNE_F64, "__aeabi_dcmpeq");
257 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETEQ);
258 setLibcallName(RTLIB::OLT_F64, "__aeabi_dcmplt");
259 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
260 setLibcallName(RTLIB::OLE_F64, "__aeabi_dcmple");
261 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
262 setLibcallName(RTLIB::OGE_F64, "__aeabi_dcmpge");
263 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
264 setLibcallName(RTLIB::OGT_F64, "__aeabi_dcmpgt");
265 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
266 setLibcallName(RTLIB::UO_F64, "__aeabi_dcmpun");
267 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
268 setLibcallName(RTLIB::O_F64, "__aeabi_dcmpun");
269 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
270 setLibcallCallingConv(RTLIB::OEQ_F64, CallingConv::ARM_AAPCS);
271 setLibcallCallingConv(RTLIB::UNE_F64, CallingConv::ARM_AAPCS);
272 setLibcallCallingConv(RTLIB::OLT_F64, CallingConv::ARM_AAPCS);
273 setLibcallCallingConv(RTLIB::OLE_F64, CallingConv::ARM_AAPCS);
274 setLibcallCallingConv(RTLIB::OGE_F64, CallingConv::ARM_AAPCS);
275 setLibcallCallingConv(RTLIB::OGT_F64, CallingConv::ARM_AAPCS);
276 setLibcallCallingConv(RTLIB::UO_F64, CallingConv::ARM_AAPCS);
277 setLibcallCallingConv(RTLIB::O_F64, CallingConv::ARM_AAPCS);
279 // Single-precision floating-point arithmetic helper functions
280 // RTABI chapter 4.1.2, Table 4
281 setLibcallName(RTLIB::ADD_F32, "__aeabi_fadd");
282 setLibcallName(RTLIB::DIV_F32, "__aeabi_fdiv");
283 setLibcallName(RTLIB::MUL_F32, "__aeabi_fmul");
284 setLibcallName(RTLIB::SUB_F32, "__aeabi_fsub");
285 setLibcallCallingConv(RTLIB::ADD_F32, CallingConv::ARM_AAPCS);
286 setLibcallCallingConv(RTLIB::DIV_F32, CallingConv::ARM_AAPCS);
287 setLibcallCallingConv(RTLIB::MUL_F32, CallingConv::ARM_AAPCS);
288 setLibcallCallingConv(RTLIB::SUB_F32, CallingConv::ARM_AAPCS);
290 // Single-precision floating-point comparison helper functions
291 // RTABI chapter 4.1.2, Table 5
292 setLibcallName(RTLIB::OEQ_F32, "__aeabi_fcmpeq");
293 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
294 setLibcallName(RTLIB::UNE_F32, "__aeabi_fcmpeq");
295 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETEQ);
296 setLibcallName(RTLIB::OLT_F32, "__aeabi_fcmplt");
297 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
298 setLibcallName(RTLIB::OLE_F32, "__aeabi_fcmple");
299 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
300 setLibcallName(RTLIB::OGE_F32, "__aeabi_fcmpge");
301 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
302 setLibcallName(RTLIB::OGT_F32, "__aeabi_fcmpgt");
303 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
304 setLibcallName(RTLIB::UO_F32, "__aeabi_fcmpun");
305 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
306 setLibcallName(RTLIB::O_F32, "__aeabi_fcmpun");
307 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
308 setLibcallCallingConv(RTLIB::OEQ_F32, CallingConv::ARM_AAPCS);
309 setLibcallCallingConv(RTLIB::UNE_F32, CallingConv::ARM_AAPCS);
310 setLibcallCallingConv(RTLIB::OLT_F32, CallingConv::ARM_AAPCS);
311 setLibcallCallingConv(RTLIB::OLE_F32, CallingConv::ARM_AAPCS);
312 setLibcallCallingConv(RTLIB::OGE_F32, CallingConv::ARM_AAPCS);
313 setLibcallCallingConv(RTLIB::OGT_F32, CallingConv::ARM_AAPCS);
314 setLibcallCallingConv(RTLIB::UO_F32, CallingConv::ARM_AAPCS);
315 setLibcallCallingConv(RTLIB::O_F32, CallingConv::ARM_AAPCS);
317 // Floating-point to integer conversions.
318 // RTABI chapter 4.1.2, Table 6
319 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz");
320 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz");
321 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz");
322 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz");
323 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz");
324 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz");
325 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz");
326 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz");
327 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I32, CallingConv::ARM_AAPCS);
328 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I32, CallingConv::ARM_AAPCS);
329 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I64, CallingConv::ARM_AAPCS);
330 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::ARM_AAPCS);
331 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I32, CallingConv::ARM_AAPCS);
332 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I32, CallingConv::ARM_AAPCS);
333 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I64, CallingConv::ARM_AAPCS);
334 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::ARM_AAPCS);
336 // Conversions between floating types.
337 // RTABI chapter 4.1.2, Table 7
338 setLibcallName(RTLIB::FPROUND_F64_F32, "__aeabi_d2f");
339 setLibcallName(RTLIB::FPEXT_F32_F64, "__aeabi_f2d");
340 setLibcallCallingConv(RTLIB::FPROUND_F64_F32, CallingConv::ARM_AAPCS);
341 setLibcallCallingConv(RTLIB::FPEXT_F32_F64, CallingConv::ARM_AAPCS);
343 // Integer to floating-point conversions.
344 // RTABI chapter 4.1.2, Table 8
345 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d");
346 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d");
347 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d");
348 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d");
349 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f");
350 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f");
351 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f");
352 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f");
353 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
354 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
355 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
356 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
357 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
358 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
359 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
360 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
362 // Long long helper functions
363 // RTABI chapter 4.2, Table 9
364 setLibcallName(RTLIB::MUL_I64, "__aeabi_lmul");
365 setLibcallName(RTLIB::SDIV_I64, "__aeabi_ldivmod");
366 setLibcallName(RTLIB::UDIV_I64, "__aeabi_uldivmod");
367 setLibcallName(RTLIB::SHL_I64, "__aeabi_llsl");
368 setLibcallName(RTLIB::SRL_I64, "__aeabi_llsr");
369 setLibcallName(RTLIB::SRA_I64, "__aeabi_lasr");
370 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::ARM_AAPCS);
371 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::ARM_AAPCS);
372 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::ARM_AAPCS);
373 setLibcallCallingConv(RTLIB::SHL_I64, CallingConv::ARM_AAPCS);
374 setLibcallCallingConv(RTLIB::SRL_I64, CallingConv::ARM_AAPCS);
375 setLibcallCallingConv(RTLIB::SRA_I64, CallingConv::ARM_AAPCS);
377 // Integer division functions
378 // RTABI chapter 4.3.1
379 setLibcallName(RTLIB::SDIV_I8, "__aeabi_idiv");
380 setLibcallName(RTLIB::SDIV_I16, "__aeabi_idiv");
381 setLibcallName(RTLIB::SDIV_I32, "__aeabi_idiv");
382 setLibcallName(RTLIB::UDIV_I8, "__aeabi_uidiv");
383 setLibcallName(RTLIB::UDIV_I16, "__aeabi_uidiv");
384 setLibcallName(RTLIB::UDIV_I32, "__aeabi_uidiv");
385 setLibcallCallingConv(RTLIB::SDIV_I8, CallingConv::ARM_AAPCS);
386 setLibcallCallingConv(RTLIB::SDIV_I16, CallingConv::ARM_AAPCS);
387 setLibcallCallingConv(RTLIB::SDIV_I32, CallingConv::ARM_AAPCS);
388 setLibcallCallingConv(RTLIB::UDIV_I8, CallingConv::ARM_AAPCS);
389 setLibcallCallingConv(RTLIB::UDIV_I16, CallingConv::ARM_AAPCS);
390 setLibcallCallingConv(RTLIB::UDIV_I32, CallingConv::ARM_AAPCS);
393 if (Subtarget->isThumb1Only())
394 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
396 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
397 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
398 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
399 if (!Subtarget->isFPOnlySP())
400 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
402 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
405 if (Subtarget->hasNEON()) {
406 addDRTypeForNEON(MVT::v2f32);
407 addDRTypeForNEON(MVT::v8i8);
408 addDRTypeForNEON(MVT::v4i16);
409 addDRTypeForNEON(MVT::v2i32);
410 addDRTypeForNEON(MVT::v1i64);
412 addQRTypeForNEON(MVT::v4f32);
413 addQRTypeForNEON(MVT::v2f64);
414 addQRTypeForNEON(MVT::v16i8);
415 addQRTypeForNEON(MVT::v8i16);
416 addQRTypeForNEON(MVT::v4i32);
417 addQRTypeForNEON(MVT::v2i64);
419 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
420 // neither Neon nor VFP support any arithmetic operations on it.
421 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
422 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
423 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
424 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
425 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
426 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
427 setOperationAction(ISD::VSETCC, MVT::v2f64, Expand);
428 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
429 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
430 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
431 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
432 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
433 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
434 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
435 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
436 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
437 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
438 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
439 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
440 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
441 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
442 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
443 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
444 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
446 setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand);
448 // Neon does not support some operations on v1i64 and v2i64 types.
449 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
450 // Custom handling for some quad-vector types to detect VMULL.
451 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
452 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
453 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
454 setOperationAction(ISD::VSETCC, MVT::v1i64, Expand);
455 setOperationAction(ISD::VSETCC, MVT::v2i64, Expand);
457 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
458 setTargetDAGCombine(ISD::SHL);
459 setTargetDAGCombine(ISD::SRL);
460 setTargetDAGCombine(ISD::SRA);
461 setTargetDAGCombine(ISD::SIGN_EXTEND);
462 setTargetDAGCombine(ISD::ZERO_EXTEND);
463 setTargetDAGCombine(ISD::ANY_EXTEND);
464 setTargetDAGCombine(ISD::SELECT_CC);
465 setTargetDAGCombine(ISD::BUILD_VECTOR);
466 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
469 computeRegisterProperties();
471 // ARM does not have f32 extending load.
472 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
474 // ARM does not have i1 sign extending load.
475 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
477 // ARM supports all 4 flavors of integer indexed load / store.
478 if (!Subtarget->isThumb1Only()) {
479 for (unsigned im = (unsigned)ISD::PRE_INC;
480 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
481 setIndexedLoadAction(im, MVT::i1, Legal);
482 setIndexedLoadAction(im, MVT::i8, Legal);
483 setIndexedLoadAction(im, MVT::i16, Legal);
484 setIndexedLoadAction(im, MVT::i32, Legal);
485 setIndexedStoreAction(im, MVT::i1, Legal);
486 setIndexedStoreAction(im, MVT::i8, Legal);
487 setIndexedStoreAction(im, MVT::i16, Legal);
488 setIndexedStoreAction(im, MVT::i32, Legal);
492 // i64 operation support.
493 if (Subtarget->isThumb1Only()) {
494 setOperationAction(ISD::MUL, MVT::i64, Expand);
495 setOperationAction(ISD::MULHU, MVT::i32, Expand);
496 setOperationAction(ISD::MULHS, MVT::i32, Expand);
497 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
498 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
500 setOperationAction(ISD::MUL, MVT::i64, Expand);
501 setOperationAction(ISD::MULHU, MVT::i32, Expand);
502 if (!Subtarget->hasV6Ops())
503 setOperationAction(ISD::MULHS, MVT::i32, Expand);
505 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
506 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
507 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
508 setOperationAction(ISD::SRL, MVT::i64, Custom);
509 setOperationAction(ISD::SRA, MVT::i64, Custom);
511 // ARM does not have ROTL.
512 setOperationAction(ISD::ROTL, MVT::i32, Expand);
513 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
514 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
515 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
516 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
518 // Only ARMv6 has BSWAP.
519 if (!Subtarget->hasV6Ops())
520 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
522 // These are expanded into libcalls.
523 if (!Subtarget->hasDivide()) {
524 // v7M has a hardware divider
525 setOperationAction(ISD::SDIV, MVT::i32, Expand);
526 setOperationAction(ISD::UDIV, MVT::i32, Expand);
528 setOperationAction(ISD::SREM, MVT::i32, Expand);
529 setOperationAction(ISD::UREM, MVT::i32, Expand);
530 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
531 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
533 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
534 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
535 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
536 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
537 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
539 setOperationAction(ISD::TRAP, MVT::Other, Legal);
541 // Use the default implementation.
542 setOperationAction(ISD::VASTART, MVT::Other, Custom);
543 setOperationAction(ISD::VAARG, MVT::Other, Expand);
544 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
545 setOperationAction(ISD::VAEND, MVT::Other, Expand);
546 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
547 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
548 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
549 // FIXME: Shouldn't need this, since no register is used, but the legalizer
550 // doesn't yet know how to not do that for SjLj.
551 setExceptionSelectorRegister(ARM::R0);
552 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
553 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
554 // the default expansion.
555 if (Subtarget->hasDataBarrier() ||
556 (Subtarget->hasV6Ops() && !Subtarget->isThumb1Only())) {
557 // membarrier needs custom lowering; the rest are legal and handled
559 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
561 // Set them all for expansion, which will force libcalls.
562 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
563 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Expand);
564 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Expand);
565 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
566 setOperationAction(ISD::ATOMIC_SWAP, MVT::i8, Expand);
567 setOperationAction(ISD::ATOMIC_SWAP, MVT::i16, Expand);
568 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
569 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i8, Expand);
570 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i16, Expand);
571 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
572 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Expand);
573 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Expand);
574 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
575 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i8, Expand);
576 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i16, Expand);
577 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
578 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i8, Expand);
579 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i16, Expand);
580 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
581 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i8, Expand);
582 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i16, Expand);
583 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
584 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i8, Expand);
585 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i16, Expand);
586 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
587 // Since the libcalls include locking, fold in the fences
588 setShouldFoldAtomicFences(true);
590 // 64-bit versions are always libcalls (for now)
591 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Expand);
592 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Expand);
593 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Expand);
594 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Expand);
595 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Expand);
596 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Expand);
597 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Expand);
598 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Expand);
600 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
602 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
603 if (!Subtarget->hasV6Ops()) {
604 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
605 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
607 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
609 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
610 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
611 // iff target supports vfp2.
612 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
613 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
616 // We want to custom lower some of our intrinsics.
617 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
618 if (Subtarget->isTargetDarwin()) {
619 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
620 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
621 setOperationAction(ISD::EH_SJLJ_DISPATCHSETUP, MVT::Other, Custom);
624 setOperationAction(ISD::SETCC, MVT::i32, Expand);
625 setOperationAction(ISD::SETCC, MVT::f32, Expand);
626 setOperationAction(ISD::SETCC, MVT::f64, Expand);
627 setOperationAction(ISD::SELECT, MVT::i32, Custom);
628 setOperationAction(ISD::SELECT, MVT::f32, Custom);
629 setOperationAction(ISD::SELECT, MVT::f64, Custom);
630 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
631 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
632 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
634 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
635 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
636 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
637 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
638 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
640 // We don't support sin/cos/fmod/copysign/pow
641 setOperationAction(ISD::FSIN, MVT::f64, Expand);
642 setOperationAction(ISD::FSIN, MVT::f32, Expand);
643 setOperationAction(ISD::FCOS, MVT::f32, Expand);
644 setOperationAction(ISD::FCOS, MVT::f64, Expand);
645 setOperationAction(ISD::FREM, MVT::f64, Expand);
646 setOperationAction(ISD::FREM, MVT::f32, Expand);
647 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
648 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
649 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
651 setOperationAction(ISD::FPOW, MVT::f64, Expand);
652 setOperationAction(ISD::FPOW, MVT::f32, Expand);
654 // Various VFP goodness
655 if (!UseSoftFloat && !Subtarget->isThumb1Only()) {
656 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
657 if (Subtarget->hasVFP2()) {
658 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
659 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
660 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
661 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
663 // Special handling for half-precision FP.
664 if (!Subtarget->hasFP16()) {
665 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
666 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand);
670 // We have target-specific dag combine patterns for the following nodes:
671 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
672 setTargetDAGCombine(ISD::ADD);
673 setTargetDAGCombine(ISD::SUB);
674 setTargetDAGCombine(ISD::MUL);
676 if (Subtarget->hasV6T2Ops())
677 setTargetDAGCombine(ISD::OR);
679 setStackPointerRegisterToSaveRestore(ARM::SP);
681 if (UseSoftFloat || Subtarget->isThumb1Only() || !Subtarget->hasVFP2())
682 setSchedulingPreference(Sched::RegPressure);
684 setSchedulingPreference(Sched::Hybrid);
686 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
688 // On ARM arguments smaller than 4 bytes are extended, so all arguments
689 // are at least 4 bytes aligned.
690 setMinStackArgumentAlignment(4);
692 benefitFromCodePlacementOpt = true;
695 std::pair<const TargetRegisterClass*, uint8_t>
696 ARMTargetLowering::findRepresentativeClass(EVT VT) const{
697 const TargetRegisterClass *RRC = 0;
699 switch (VT.getSimpleVT().SimpleTy) {
701 return TargetLowering::findRepresentativeClass(VT);
702 // Use DPR as representative register class for all floating point
703 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
704 // the cost is 1 for both f32 and f64.
705 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
706 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
707 RRC = ARM::DPRRegisterClass;
709 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
710 case MVT::v4f32: case MVT::v2f64:
711 RRC = ARM::DPRRegisterClass;
715 RRC = ARM::DPRRegisterClass;
719 RRC = ARM::DPRRegisterClass;
723 return std::make_pair(RRC, Cost);
726 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
729 case ARMISD::Wrapper: return "ARMISD::Wrapper";
730 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
731 case ARMISD::CALL: return "ARMISD::CALL";
732 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
733 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
734 case ARMISD::tCALL: return "ARMISD::tCALL";
735 case ARMISD::BRCOND: return "ARMISD::BRCOND";
736 case ARMISD::BR_JT: return "ARMISD::BR_JT";
737 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
738 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
739 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
740 case ARMISD::CMP: return "ARMISD::CMP";
741 case ARMISD::CMPZ: return "ARMISD::CMPZ";
742 case ARMISD::CMPFP: return "ARMISD::CMPFP";
743 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
744 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
745 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
746 case ARMISD::CMOV: return "ARMISD::CMOV";
747 case ARMISD::CNEG: return "ARMISD::CNEG";
749 case ARMISD::RBIT: return "ARMISD::RBIT";
751 case ARMISD::FTOSI: return "ARMISD::FTOSI";
752 case ARMISD::FTOUI: return "ARMISD::FTOUI";
753 case ARMISD::SITOF: return "ARMISD::SITOF";
754 case ARMISD::UITOF: return "ARMISD::UITOF";
756 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
757 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
758 case ARMISD::RRX: return "ARMISD::RRX";
760 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
761 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
763 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
764 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
765 case ARMISD::EH_SJLJ_DISPATCHSETUP:return "ARMISD::EH_SJLJ_DISPATCHSETUP";
767 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
769 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
771 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
773 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER";
774 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
776 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
778 case ARMISD::VCEQ: return "ARMISD::VCEQ";
779 case ARMISD::VCGE: return "ARMISD::VCGE";
780 case ARMISD::VCGEU: return "ARMISD::VCGEU";
781 case ARMISD::VCGT: return "ARMISD::VCGT";
782 case ARMISD::VCGTU: return "ARMISD::VCGTU";
783 case ARMISD::VTST: return "ARMISD::VTST";
785 case ARMISD::VSHL: return "ARMISD::VSHL";
786 case ARMISD::VSHRs: return "ARMISD::VSHRs";
787 case ARMISD::VSHRu: return "ARMISD::VSHRu";
788 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
789 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
790 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
791 case ARMISD::VSHRN: return "ARMISD::VSHRN";
792 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
793 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
794 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
795 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
796 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
797 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
798 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
799 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
800 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
801 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
802 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
803 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
804 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
805 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
806 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
807 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
808 case ARMISD::VDUP: return "ARMISD::VDUP";
809 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
810 case ARMISD::VEXT: return "ARMISD::VEXT";
811 case ARMISD::VREV64: return "ARMISD::VREV64";
812 case ARMISD::VREV32: return "ARMISD::VREV32";
813 case ARMISD::VREV16: return "ARMISD::VREV16";
814 case ARMISD::VZIP: return "ARMISD::VZIP";
815 case ARMISD::VUZP: return "ARMISD::VUZP";
816 case ARMISD::VTRN: return "ARMISD::VTRN";
817 case ARMISD::VMULLs: return "ARMISD::VMULLs";
818 case ARMISD::VMULLu: return "ARMISD::VMULLu";
819 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
820 case ARMISD::FMAX: return "ARMISD::FMAX";
821 case ARMISD::FMIN: return "ARMISD::FMIN";
822 case ARMISD::BFI: return "ARMISD::BFI";
826 /// getRegClassFor - Return the register class that should be used for the
827 /// specified value type.
828 TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const {
829 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
830 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
831 // load / store 4 to 8 consecutive D registers.
832 if (Subtarget->hasNEON()) {
833 if (VT == MVT::v4i64)
834 return ARM::QQPRRegisterClass;
835 else if (VT == MVT::v8i64)
836 return ARM::QQQQPRRegisterClass;
838 return TargetLowering::getRegClassFor(VT);
841 // Create a fast isel object.
843 ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
844 return ARM::createFastISel(funcInfo);
847 /// getFunctionAlignment - Return the Log2 alignment of this function.
848 unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
849 return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 1 : 2;
852 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
853 /// be used for loads / stores from the global.
854 unsigned ARMTargetLowering::getMaximalGlobalOffset() const {
855 return (Subtarget->isThumb1Only() ? 127 : 4095);
858 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
859 unsigned NumVals = N->getNumValues();
861 return Sched::RegPressure;
863 for (unsigned i = 0; i != NumVals; ++i) {
864 EVT VT = N->getValueType(i);
865 if (VT == MVT::Flag || VT == MVT::Other)
867 if (VT.isFloatingPoint() || VT.isVector())
868 return Sched::Latency;
871 if (!N->isMachineOpcode())
872 return Sched::RegPressure;
874 // Load are scheduled for latency even if there instruction itinerary
876 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
877 const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
879 if (TID.getNumDefs() == 0)
880 return Sched::RegPressure;
881 if (!Itins->isEmpty() &&
882 Itins->getOperandCycle(TID.getSchedClass(), 0) > 2)
883 return Sched::Latency;
885 return Sched::RegPressure;
889 ARMTargetLowering::getRegPressureLimit(const TargetRegisterClass *RC,
890 MachineFunction &MF) const {
891 switch (RC->getID()) {
894 case ARM::tGPRRegClassID:
895 return RegInfo->hasFP(MF) ? 4 : 5;
896 case ARM::GPRRegClassID: {
897 unsigned FP = RegInfo->hasFP(MF) ? 1 : 0;
898 return 10 - FP - (Subtarget->isR9Reserved() ? 1 : 0);
900 case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
901 case ARM::DPRRegClassID:
906 //===----------------------------------------------------------------------===//
908 //===----------------------------------------------------------------------===//
910 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
911 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
913 default: llvm_unreachable("Unknown condition code!");
914 case ISD::SETNE: return ARMCC::NE;
915 case ISD::SETEQ: return ARMCC::EQ;
916 case ISD::SETGT: return ARMCC::GT;
917 case ISD::SETGE: return ARMCC::GE;
918 case ISD::SETLT: return ARMCC::LT;
919 case ISD::SETLE: return ARMCC::LE;
920 case ISD::SETUGT: return ARMCC::HI;
921 case ISD::SETUGE: return ARMCC::HS;
922 case ISD::SETULT: return ARMCC::LO;
923 case ISD::SETULE: return ARMCC::LS;
927 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
928 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
929 ARMCC::CondCodes &CondCode2) {
930 CondCode2 = ARMCC::AL;
932 default: llvm_unreachable("Unknown FP condition!");
934 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
936 case ISD::SETOGT: CondCode = ARMCC::GT; break;
938 case ISD::SETOGE: CondCode = ARMCC::GE; break;
939 case ISD::SETOLT: CondCode = ARMCC::MI; break;
940 case ISD::SETOLE: CondCode = ARMCC::LS; break;
941 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
942 case ISD::SETO: CondCode = ARMCC::VC; break;
943 case ISD::SETUO: CondCode = ARMCC::VS; break;
944 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
945 case ISD::SETUGT: CondCode = ARMCC::HI; break;
946 case ISD::SETUGE: CondCode = ARMCC::PL; break;
948 case ISD::SETULT: CondCode = ARMCC::LT; break;
950 case ISD::SETULE: CondCode = ARMCC::LE; break;
952 case ISD::SETUNE: CondCode = ARMCC::NE; break;
956 //===----------------------------------------------------------------------===//
957 // Calling Convention Implementation
958 //===----------------------------------------------------------------------===//
960 #include "ARMGenCallingConv.inc"
962 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
963 /// given CallingConvention value.
964 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
966 bool isVarArg) const {
969 llvm_unreachable("Unsupported calling convention");
970 case CallingConv::Fast:
971 if (Subtarget->hasVFP2() && !isVarArg) {
972 if (!Subtarget->isAAPCS_ABI())
973 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
974 // For AAPCS ABI targets, just use VFP variant of the calling convention.
975 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
978 case CallingConv::C: {
979 // Use target triple & subtarget features to do actual dispatch.
980 if (!Subtarget->isAAPCS_ABI())
981 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
982 else if (Subtarget->hasVFP2() &&
983 FloatABIType == FloatABI::Hard && !isVarArg)
984 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
985 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
987 case CallingConv::ARM_AAPCS_VFP:
988 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
989 case CallingConv::ARM_AAPCS:
990 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
991 case CallingConv::ARM_APCS:
992 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
996 /// LowerCallResult - Lower the result values of a call into the
997 /// appropriate copies out of appropriate physical registers.
999 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1000 CallingConv::ID CallConv, bool isVarArg,
1001 const SmallVectorImpl<ISD::InputArg> &Ins,
1002 DebugLoc dl, SelectionDAG &DAG,
1003 SmallVectorImpl<SDValue> &InVals) const {
1005 // Assign locations to each value returned by this call.
1006 SmallVector<CCValAssign, 16> RVLocs;
1007 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1008 RVLocs, *DAG.getContext());
1009 CCInfo.AnalyzeCallResult(Ins,
1010 CCAssignFnForNode(CallConv, /* Return*/ true,
1013 // Copy all of the result registers out of their specified physreg.
1014 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1015 CCValAssign VA = RVLocs[i];
1018 if (VA.needsCustom()) {
1019 // Handle f64 or half of a v2f64.
1020 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1022 Chain = Lo.getValue(1);
1023 InFlag = Lo.getValue(2);
1024 VA = RVLocs[++i]; // skip ahead to next loc
1025 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1027 Chain = Hi.getValue(1);
1028 InFlag = Hi.getValue(2);
1029 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1031 if (VA.getLocVT() == MVT::v2f64) {
1032 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1033 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1034 DAG.getConstant(0, MVT::i32));
1036 VA = RVLocs[++i]; // skip ahead to next loc
1037 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1038 Chain = Lo.getValue(1);
1039 InFlag = Lo.getValue(2);
1040 VA = RVLocs[++i]; // skip ahead to next loc
1041 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1042 Chain = Hi.getValue(1);
1043 InFlag = Hi.getValue(2);
1044 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1045 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1046 DAG.getConstant(1, MVT::i32));
1049 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1051 Chain = Val.getValue(1);
1052 InFlag = Val.getValue(2);
1055 switch (VA.getLocInfo()) {
1056 default: llvm_unreachable("Unknown loc info!");
1057 case CCValAssign::Full: break;
1058 case CCValAssign::BCvt:
1059 Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val);
1063 InVals.push_back(Val);
1069 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1070 /// by "Src" to address "Dst" of size "Size". Alignment information is
1071 /// specified by the specific parameter attribute. The copy will be passed as
1072 /// a byval function parameter.
1073 /// Sometimes what we are copying is the end of a larger object, the part that
1074 /// does not fit in registers.
1076 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1077 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1079 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1080 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1081 /*isVolatile=*/false, /*AlwaysInline=*/false,
1082 MachinePointerInfo(0), MachinePointerInfo(0));
1085 /// LowerMemOpCallTo - Store the argument to the stack.
1087 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
1088 SDValue StackPtr, SDValue Arg,
1089 DebugLoc dl, SelectionDAG &DAG,
1090 const CCValAssign &VA,
1091 ISD::ArgFlagsTy Flags) const {
1092 unsigned LocMemOffset = VA.getLocMemOffset();
1093 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1094 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1095 if (Flags.isByVal())
1096 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1098 return DAG.getStore(Chain, dl, Arg, PtrOff,
1099 MachinePointerInfo::getStack(LocMemOffset),
1103 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
1104 SDValue Chain, SDValue &Arg,
1105 RegsToPassVector &RegsToPass,
1106 CCValAssign &VA, CCValAssign &NextVA,
1108 SmallVector<SDValue, 8> &MemOpChains,
1109 ISD::ArgFlagsTy Flags) const {
1111 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1112 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1113 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
1115 if (NextVA.isRegLoc())
1116 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
1118 assert(NextVA.isMemLoc());
1119 if (StackPtr.getNode() == 0)
1120 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1122 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
1128 /// LowerCall - Lowering a call into a callseq_start <-
1129 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1132 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1133 CallingConv::ID CallConv, bool isVarArg,
1135 const SmallVectorImpl<ISD::OutputArg> &Outs,
1136 const SmallVectorImpl<SDValue> &OutVals,
1137 const SmallVectorImpl<ISD::InputArg> &Ins,
1138 DebugLoc dl, SelectionDAG &DAG,
1139 SmallVectorImpl<SDValue> &InVals) const {
1140 MachineFunction &MF = DAG.getMachineFunction();
1141 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1142 bool IsSibCall = false;
1143 // Temporarily disable tail calls so things don't break.
1144 if (!EnableARMTailCalls)
1147 // Check if it's really possible to do a tail call.
1148 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1149 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1150 Outs, OutVals, Ins, DAG);
1151 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1152 // detected sibcalls.
1159 // Analyze operands of the call, assigning locations to each operand.
1160 SmallVector<CCValAssign, 16> ArgLocs;
1161 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1163 CCInfo.AnalyzeCallOperands(Outs,
1164 CCAssignFnForNode(CallConv, /* Return*/ false,
1167 // Get a count of how many bytes are to be pushed on the stack.
1168 unsigned NumBytes = CCInfo.getNextStackOffset();
1170 // For tail calls, memory operands are available in our caller's stack.
1174 // Adjust the stack pointer for the new arguments...
1175 // These operations are automatically eliminated by the prolog/epilog pass
1177 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1179 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1181 RegsToPassVector RegsToPass;
1182 SmallVector<SDValue, 8> MemOpChains;
1184 // Walk the register/memloc assignments, inserting copies/loads. In the case
1185 // of tail call optimization, arguments are handled later.
1186 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1188 ++i, ++realArgIdx) {
1189 CCValAssign &VA = ArgLocs[i];
1190 SDValue Arg = OutVals[realArgIdx];
1191 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1193 // Promote the value if needed.
1194 switch (VA.getLocInfo()) {
1195 default: llvm_unreachable("Unknown loc info!");
1196 case CCValAssign::Full: break;
1197 case CCValAssign::SExt:
1198 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1200 case CCValAssign::ZExt:
1201 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1203 case CCValAssign::AExt:
1204 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1206 case CCValAssign::BCvt:
1207 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1211 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1212 if (VA.needsCustom()) {
1213 if (VA.getLocVT() == MVT::v2f64) {
1214 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1215 DAG.getConstant(0, MVT::i32));
1216 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1217 DAG.getConstant(1, MVT::i32));
1219 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1220 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1222 VA = ArgLocs[++i]; // skip ahead to next loc
1223 if (VA.isRegLoc()) {
1224 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1225 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1227 assert(VA.isMemLoc());
1229 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1230 dl, DAG, VA, Flags));
1233 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1234 StackPtr, MemOpChains, Flags);
1236 } else if (VA.isRegLoc()) {
1237 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1238 } else if (!IsSibCall) {
1239 assert(VA.isMemLoc());
1241 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1242 dl, DAG, VA, Flags));
1246 if (!MemOpChains.empty())
1247 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1248 &MemOpChains[0], MemOpChains.size());
1250 // Build a sequence of copy-to-reg nodes chained together with token chain
1251 // and flag operands which copy the outgoing args into the appropriate regs.
1253 // Tail call byval lowering might overwrite argument registers so in case of
1254 // tail call optimization the copies to registers are lowered later.
1256 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1257 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1258 RegsToPass[i].second, InFlag);
1259 InFlag = Chain.getValue(1);
1262 // For tail calls lower the arguments to the 'real' stack slot.
1264 // Force all the incoming stack arguments to be loaded from the stack
1265 // before any new outgoing arguments are stored to the stack, because the
1266 // outgoing stack slots may alias the incoming argument stack slots, and
1267 // the alias isn't otherwise explicit. This is slightly more conservative
1268 // than necessary, because it means that each store effectively depends
1269 // on every argument instead of just those arguments it would clobber.
1271 // Do not flag preceeding copytoreg stuff together with the following stuff.
1273 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1274 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1275 RegsToPass[i].second, InFlag);
1276 InFlag = Chain.getValue(1);
1281 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1282 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1283 // node so that legalize doesn't hack it.
1284 bool isDirect = false;
1285 bool isARMFunc = false;
1286 bool isLocalARMFunc = false;
1287 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1289 if (EnableARMLongCalls) {
1290 assert (getTargetMachine().getRelocationModel() == Reloc::Static
1291 && "long-calls with non-static relocation model!");
1292 // Handle a global address or an external symbol. If it's not one of
1293 // those, the target's already in a register, so we don't need to do
1295 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1296 const GlobalValue *GV = G->getGlobal();
1297 // Create a constant pool entry for the callee address
1298 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1299 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1302 // Get the address of the callee into a register
1303 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1304 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1305 Callee = DAG.getLoad(getPointerTy(), dl,
1306 DAG.getEntryNode(), CPAddr,
1307 MachinePointerInfo::getConstantPool(),
1309 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1310 const char *Sym = S->getSymbol();
1312 // Create a constant pool entry for the callee address
1313 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1314 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1315 Sym, ARMPCLabelIndex, 0);
1316 // Get the address of the callee into a register
1317 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1318 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1319 Callee = DAG.getLoad(getPointerTy(), dl,
1320 DAG.getEntryNode(), CPAddr,
1321 MachinePointerInfo::getConstantPool(),
1324 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1325 const GlobalValue *GV = G->getGlobal();
1327 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1328 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
1329 getTargetMachine().getRelocationModel() != Reloc::Static;
1330 isARMFunc = !Subtarget->isThumb() || isStub;
1331 // ARM call to a local ARM function is predicable.
1332 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
1333 // tBX takes a register source operand.
1334 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1335 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1336 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1339 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1340 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1341 Callee = DAG.getLoad(getPointerTy(), dl,
1342 DAG.getEntryNode(), CPAddr,
1343 MachinePointerInfo::getConstantPool(),
1345 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1346 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1347 getPointerTy(), Callee, PICLabel);
1349 // On ELF targets for PIC code, direct calls should go through the PLT
1350 unsigned OpFlags = 0;
1351 if (Subtarget->isTargetELF() &&
1352 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1353 OpFlags = ARMII::MO_PLT;
1354 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
1356 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1358 bool isStub = Subtarget->isTargetDarwin() &&
1359 getTargetMachine().getRelocationModel() != Reloc::Static;
1360 isARMFunc = !Subtarget->isThumb() || isStub;
1361 // tBX takes a register source operand.
1362 const char *Sym = S->getSymbol();
1363 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1364 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1365 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1366 Sym, ARMPCLabelIndex, 4);
1367 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1368 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1369 Callee = DAG.getLoad(getPointerTy(), dl,
1370 DAG.getEntryNode(), CPAddr,
1371 MachinePointerInfo::getConstantPool(),
1373 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1374 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1375 getPointerTy(), Callee, PICLabel);
1377 unsigned OpFlags = 0;
1378 // On ELF targets for PIC code, direct calls should go through the PLT
1379 if (Subtarget->isTargetELF() &&
1380 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1381 OpFlags = ARMII::MO_PLT;
1382 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags);
1386 // FIXME: handle tail calls differently.
1388 if (Subtarget->isThumb()) {
1389 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1390 CallOpc = ARMISD::CALL_NOLINK;
1392 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1394 CallOpc = (isDirect || Subtarget->hasV5TOps())
1395 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
1396 : ARMISD::CALL_NOLINK;
1399 std::vector<SDValue> Ops;
1400 Ops.push_back(Chain);
1401 Ops.push_back(Callee);
1403 // Add argument registers to the end of the list so that they are known live
1405 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1406 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1407 RegsToPass[i].second.getValueType()));
1409 if (InFlag.getNode())
1410 Ops.push_back(InFlag);
1412 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1414 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
1416 // Returns a chain and a flag for retval copy to use.
1417 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
1418 InFlag = Chain.getValue(1);
1420 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1421 DAG.getIntPtrConstant(0, true), InFlag);
1423 InFlag = Chain.getValue(1);
1425 // Handle result values, copying them out of physregs into vregs that we
1427 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1431 /// MatchingStackOffset - Return true if the given stack call argument is
1432 /// already available in the same position (relatively) of the caller's
1433 /// incoming argument stack.
1435 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1436 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1437 const ARMInstrInfo *TII) {
1438 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
1440 if (Arg.getOpcode() == ISD::CopyFromReg) {
1441 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
1442 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR))
1444 MachineInstr *Def = MRI->getVRegDef(VR);
1447 if (!Flags.isByVal()) {
1448 if (!TII->isLoadFromStackSlot(Def, FI))
1453 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
1454 if (Flags.isByVal())
1455 // ByVal argument is passed in as a pointer but it's now being
1456 // dereferenced. e.g.
1457 // define @foo(%struct.X* %A) {
1458 // tail call @bar(%struct.X* byval %A)
1461 SDValue Ptr = Ld->getBasePtr();
1462 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
1465 FI = FINode->getIndex();
1469 assert(FI != INT_MAX);
1470 if (!MFI->isFixedObjectIndex(FI))
1472 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
1475 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1476 /// for tail call optimization. Targets which want to do tail call
1477 /// optimization should implement this function.
1479 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1480 CallingConv::ID CalleeCC,
1482 bool isCalleeStructRet,
1483 bool isCallerStructRet,
1484 const SmallVectorImpl<ISD::OutputArg> &Outs,
1485 const SmallVectorImpl<SDValue> &OutVals,
1486 const SmallVectorImpl<ISD::InputArg> &Ins,
1487 SelectionDAG& DAG) const {
1488 const Function *CallerF = DAG.getMachineFunction().getFunction();
1489 CallingConv::ID CallerCC = CallerF->getCallingConv();
1490 bool CCMatch = CallerCC == CalleeCC;
1492 // Look for obvious safe cases to perform tail call optimization that do not
1493 // require ABI changes. This is what gcc calls sibcall.
1495 // Do not sibcall optimize vararg calls unless the call site is not passing
1497 if (isVarArg && !Outs.empty())
1500 // Also avoid sibcall optimization if either caller or callee uses struct
1501 // return semantics.
1502 if (isCalleeStructRet || isCallerStructRet)
1505 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
1506 // emitEpilogue is not ready for them.
1507 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
1508 // LR. This means if we need to reload LR, it takes an extra instructions,
1509 // which outweighs the value of the tail call; but here we don't know yet
1510 // whether LR is going to be used. Probably the right approach is to
1511 // generate the tail call here and turn it back into CALL/RET in
1512 // emitEpilogue if LR is used.
1513 if (Subtarget->isThumb1Only())
1516 // For the moment, we can only do this to functions defined in this
1517 // compilation, or to indirect calls. A Thumb B to an ARM function,
1518 // or vice versa, is not easily fixed up in the linker unlike BL.
1519 // (We could do this by loading the address of the callee into a register;
1520 // that is an extra instruction over the direct call and burns a register
1521 // as well, so is not likely to be a win.)
1523 // It might be safe to remove this restriction on non-Darwin.
1525 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
1526 // but we need to make sure there are enough registers; the only valid
1527 // registers are the 4 used for parameters. We don't currently do this
1529 if (isa<ExternalSymbolSDNode>(Callee))
1532 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1533 const GlobalValue *GV = G->getGlobal();
1534 if (GV->isDeclaration() || GV->isWeakForLinker())
1538 // If the calling conventions do not match, then we'd better make sure the
1539 // results are returned in the same way as what the caller expects.
1541 SmallVector<CCValAssign, 16> RVLocs1;
1542 CCState CCInfo1(CalleeCC, false, getTargetMachine(),
1543 RVLocs1, *DAG.getContext());
1544 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
1546 SmallVector<CCValAssign, 16> RVLocs2;
1547 CCState CCInfo2(CallerCC, false, getTargetMachine(),
1548 RVLocs2, *DAG.getContext());
1549 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
1551 if (RVLocs1.size() != RVLocs2.size())
1553 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
1554 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
1556 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
1558 if (RVLocs1[i].isRegLoc()) {
1559 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
1562 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
1568 // If the callee takes no arguments then go on to check the results of the
1570 if (!Outs.empty()) {
1571 // Check if stack adjustment is needed. For now, do not do this if any
1572 // argument is passed on the stack.
1573 SmallVector<CCValAssign, 16> ArgLocs;
1574 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
1575 ArgLocs, *DAG.getContext());
1576 CCInfo.AnalyzeCallOperands(Outs,
1577 CCAssignFnForNode(CalleeCC, false, isVarArg));
1578 if (CCInfo.getNextStackOffset()) {
1579 MachineFunction &MF = DAG.getMachineFunction();
1581 // Check if the arguments are already laid out in the right way as
1582 // the caller's fixed stack objects.
1583 MachineFrameInfo *MFI = MF.getFrameInfo();
1584 const MachineRegisterInfo *MRI = &MF.getRegInfo();
1585 const ARMInstrInfo *TII =
1586 ((ARMTargetMachine&)getTargetMachine()).getInstrInfo();
1587 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1589 ++i, ++realArgIdx) {
1590 CCValAssign &VA = ArgLocs[i];
1591 EVT RegVT = VA.getLocVT();
1592 SDValue Arg = OutVals[realArgIdx];
1593 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1594 if (VA.getLocInfo() == CCValAssign::Indirect)
1596 if (VA.needsCustom()) {
1597 // f64 and vector types are split into multiple registers or
1598 // register/stack-slot combinations. The types will not match
1599 // the registers; give up on memory f64 refs until we figure
1600 // out what to do about this.
1603 if (!ArgLocs[++i].isRegLoc())
1605 if (RegVT == MVT::v2f64) {
1606 if (!ArgLocs[++i].isRegLoc())
1608 if (!ArgLocs[++i].isRegLoc())
1611 } else if (!VA.isRegLoc()) {
1612 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
1624 ARMTargetLowering::LowerReturn(SDValue Chain,
1625 CallingConv::ID CallConv, bool isVarArg,
1626 const SmallVectorImpl<ISD::OutputArg> &Outs,
1627 const SmallVectorImpl<SDValue> &OutVals,
1628 DebugLoc dl, SelectionDAG &DAG) const {
1630 // CCValAssign - represent the assignment of the return value to a location.
1631 SmallVector<CCValAssign, 16> RVLocs;
1633 // CCState - Info about the registers and stack slots.
1634 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
1637 // Analyze outgoing return values.
1638 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1641 // If this is the first return lowered for this function, add
1642 // the regs to the liveout set for the function.
1643 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1644 for (unsigned i = 0; i != RVLocs.size(); ++i)
1645 if (RVLocs[i].isRegLoc())
1646 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1651 // Copy the result values into the output registers.
1652 for (unsigned i = 0, realRVLocIdx = 0;
1654 ++i, ++realRVLocIdx) {
1655 CCValAssign &VA = RVLocs[i];
1656 assert(VA.isRegLoc() && "Can only return in registers!");
1658 SDValue Arg = OutVals[realRVLocIdx];
1660 switch (VA.getLocInfo()) {
1661 default: llvm_unreachable("Unknown loc info!");
1662 case CCValAssign::Full: break;
1663 case CCValAssign::BCvt:
1664 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1668 if (VA.needsCustom()) {
1669 if (VA.getLocVT() == MVT::v2f64) {
1670 // Extract the first half and return it in two registers.
1671 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1672 DAG.getConstant(0, MVT::i32));
1673 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
1674 DAG.getVTList(MVT::i32, MVT::i32), Half);
1676 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1677 Flag = Chain.getValue(1);
1678 VA = RVLocs[++i]; // skip ahead to next loc
1679 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1680 HalfGPRs.getValue(1), Flag);
1681 Flag = Chain.getValue(1);
1682 VA = RVLocs[++i]; // skip ahead to next loc
1684 // Extract the 2nd half and fall through to handle it as an f64 value.
1685 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1686 DAG.getConstant(1, MVT::i32));
1688 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1690 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1691 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1692 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1693 Flag = Chain.getValue(1);
1694 VA = RVLocs[++i]; // skip ahead to next loc
1695 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1698 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1700 // Guarantee that all emitted copies are
1701 // stuck together, avoiding something bad.
1702 Flag = Chain.getValue(1);
1707 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1709 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1714 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1715 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1716 // one of the above mentioned nodes. It has to be wrapped because otherwise
1717 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1718 // be used to form addressing mode. These wrapped nodes will be selected
1720 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1721 EVT PtrVT = Op.getValueType();
1722 // FIXME there is no actual debug info here
1723 DebugLoc dl = Op.getDebugLoc();
1724 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1726 if (CP->isMachineConstantPoolEntry())
1727 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1728 CP->getAlignment());
1730 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1731 CP->getAlignment());
1732 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1735 unsigned ARMTargetLowering::getJumpTableEncoding() const {
1736 return MachineJumpTableInfo::EK_Inline;
1739 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
1740 SelectionDAG &DAG) const {
1741 MachineFunction &MF = DAG.getMachineFunction();
1742 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1743 unsigned ARMPCLabelIndex = 0;
1744 DebugLoc DL = Op.getDebugLoc();
1745 EVT PtrVT = getPointerTy();
1746 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1747 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1749 if (RelocM == Reloc::Static) {
1750 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
1752 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1753 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1754 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(BA, ARMPCLabelIndex,
1755 ARMCP::CPBlockAddress,
1757 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1759 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
1760 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
1761 MachinePointerInfo::getConstantPool(),
1763 if (RelocM == Reloc::Static)
1765 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1766 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
1769 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
1771 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1772 SelectionDAG &DAG) const {
1773 DebugLoc dl = GA->getDebugLoc();
1774 EVT PtrVT = getPointerTy();
1775 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1776 MachineFunction &MF = DAG.getMachineFunction();
1777 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1778 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1779 ARMConstantPoolValue *CPV =
1780 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1781 ARMCP::CPValue, PCAdj, "tlsgd", true);
1782 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1783 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
1784 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
1785 MachinePointerInfo::getConstantPool(),
1787 SDValue Chain = Argument.getValue(1);
1789 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1790 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
1792 // call __tls_get_addr.
1795 Entry.Node = Argument;
1796 Entry.Ty = (const Type *) Type::getInt32Ty(*DAG.getContext());
1797 Args.push_back(Entry);
1798 // FIXME: is there useful debug info available here?
1799 std::pair<SDValue, SDValue> CallResult =
1800 LowerCallTo(Chain, (const Type *) Type::getInt32Ty(*DAG.getContext()),
1801 false, false, false, false,
1802 0, CallingConv::C, false, /*isReturnValueUsed=*/true,
1803 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
1804 return CallResult.first;
1807 // Lower ISD::GlobalTLSAddress using the "initial exec" or
1808 // "local exec" model.
1810 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
1811 SelectionDAG &DAG) const {
1812 const GlobalValue *GV = GA->getGlobal();
1813 DebugLoc dl = GA->getDebugLoc();
1815 SDValue Chain = DAG.getEntryNode();
1816 EVT PtrVT = getPointerTy();
1817 // Get the Thread Pointer
1818 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1820 if (GV->isDeclaration()) {
1821 MachineFunction &MF = DAG.getMachineFunction();
1822 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1823 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1824 // Initial exec model.
1825 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1826 ARMConstantPoolValue *CPV =
1827 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1828 ARMCP::CPValue, PCAdj, "gottpoff", true);
1829 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1830 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1831 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1832 MachinePointerInfo::getConstantPool(),
1834 Chain = Offset.getValue(1);
1836 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1837 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
1839 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1840 MachinePointerInfo::getConstantPool(),
1844 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, "tpoff");
1845 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1846 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1847 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1848 MachinePointerInfo::getConstantPool(),
1852 // The address of the thread local variable is the add of the thread
1853 // pointer with the offset of the variable.
1854 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
1858 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
1859 // TODO: implement the "local dynamic" model
1860 assert(Subtarget->isTargetELF() &&
1861 "TLS not implemented for non-ELF targets");
1862 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1863 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
1864 // otherwise use the "Local Exec" TLS Model
1865 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
1866 return LowerToTLSGeneralDynamicModel(GA, DAG);
1868 return LowerToTLSExecModels(GA, DAG);
1871 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
1872 SelectionDAG &DAG) const {
1873 EVT PtrVT = getPointerTy();
1874 DebugLoc dl = Op.getDebugLoc();
1875 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1876 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1877 if (RelocM == Reloc::PIC_) {
1878 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
1879 ARMConstantPoolValue *CPV =
1880 new ARMConstantPoolValue(GV, UseGOTOFF ? "GOTOFF" : "GOT");
1881 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1882 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1883 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1885 MachinePointerInfo::getConstantPool(),
1887 SDValue Chain = Result.getValue(1);
1888 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1889 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
1891 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
1892 MachinePointerInfo::getGOT(), false, false, 0);
1895 // If we have T2 ops, we can materialize the address directly via movt/movw
1896 // pair. This is always cheaper.
1897 if (Subtarget->useMovt()) {
1898 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
1899 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
1901 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1902 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1903 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1904 MachinePointerInfo::getConstantPool(),
1910 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
1911 SelectionDAG &DAG) const {
1912 MachineFunction &MF = DAG.getMachineFunction();
1913 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1914 unsigned ARMPCLabelIndex = 0;
1915 EVT PtrVT = getPointerTy();
1916 DebugLoc dl = Op.getDebugLoc();
1917 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1918 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1920 if (RelocM == Reloc::Static)
1921 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1923 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1924 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8);
1925 ARMConstantPoolValue *CPV =
1926 new ARMConstantPoolValue(GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj);
1927 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1929 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1931 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1932 MachinePointerInfo::getConstantPool(),
1934 SDValue Chain = Result.getValue(1);
1936 if (RelocM == Reloc::PIC_) {
1937 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1938 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1941 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
1942 Result = DAG.getLoad(PtrVT, dl, Chain, Result, MachinePointerInfo::getGOT(),
1948 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
1949 SelectionDAG &DAG) const {
1950 assert(Subtarget->isTargetELF() &&
1951 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
1952 MachineFunction &MF = DAG.getMachineFunction();
1953 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1954 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1955 EVT PtrVT = getPointerTy();
1956 DebugLoc dl = Op.getDebugLoc();
1957 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1958 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1959 "_GLOBAL_OFFSET_TABLE_",
1960 ARMPCLabelIndex, PCAdj);
1961 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1962 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1963 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1964 MachinePointerInfo::getConstantPool(),
1966 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1967 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1971 ARMTargetLowering::LowerEH_SJLJ_DISPATCHSETUP(SDValue Op, SelectionDAG &DAG)
1973 DebugLoc dl = Op.getDebugLoc();
1974 return DAG.getNode(ARMISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other,
1975 Op.getOperand(0), Op.getOperand(1));
1979 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
1980 DebugLoc dl = Op.getDebugLoc();
1981 SDValue Val = DAG.getConstant(0, MVT::i32);
1982 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(0),
1983 Op.getOperand(1), Val);
1987 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
1988 DebugLoc dl = Op.getDebugLoc();
1989 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
1990 Op.getOperand(1), DAG.getConstant(0, MVT::i32));
1994 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
1995 const ARMSubtarget *Subtarget) const {
1996 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1997 DebugLoc dl = Op.getDebugLoc();
1999 default: return SDValue(); // Don't custom lower most intrinsics.
2000 case Intrinsic::arm_thread_pointer: {
2001 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2002 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2004 case Intrinsic::eh_sjlj_lsda: {
2005 MachineFunction &MF = DAG.getMachineFunction();
2006 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2007 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
2008 EVT PtrVT = getPointerTy();
2009 DebugLoc dl = Op.getDebugLoc();
2010 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2012 unsigned PCAdj = (RelocM != Reloc::PIC_)
2013 ? 0 : (Subtarget->isThumb() ? 4 : 8);
2014 ARMConstantPoolValue *CPV =
2015 new ARMConstantPoolValue(MF.getFunction(), ARMPCLabelIndex,
2016 ARMCP::CPLSDA, PCAdj);
2017 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2018 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2020 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2021 MachinePointerInfo::getConstantPool(),
2024 if (RelocM == Reloc::PIC_) {
2025 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2026 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2033 static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG,
2034 const ARMSubtarget *Subtarget) {
2035 DebugLoc dl = Op.getDebugLoc();
2036 if (!Subtarget->hasDataBarrier()) {
2037 // Some ARMv6 cpus can support data barriers with an mcr instruction.
2038 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
2040 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb1Only() &&
2041 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!");
2042 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2043 DAG.getConstant(0, MVT::i32));
2046 SDValue Op5 = Op.getOperand(5);
2047 bool isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue() != 0;
2048 unsigned isLL = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
2049 unsigned isLS = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
2050 bool isOnlyStoreBarrier = (isLL == 0 && isLS == 0);
2052 ARM_MB::MemBOpt DMBOpt;
2053 if (isDeviceBarrier)
2054 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ST : ARM_MB::SY;
2056 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ISHST : ARM_MB::ISH;
2057 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
2058 DAG.getConstant(DMBOpt, MVT::i32));
2061 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
2062 const ARMSubtarget *Subtarget) {
2063 // ARM pre v5TE and Thumb1 does not have preload instructions.
2064 if (!(Subtarget->isThumb2() ||
2065 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
2066 // Just preserve the chain.
2067 return Op.getOperand(0);
2069 DebugLoc dl = Op.getDebugLoc();
2070 unsigned Flavor = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
2072 if (!Subtarget->hasV7Ops())
2073 return Op.getOperand(0);
2074 else if (Flavor == 2 && !Subtarget->hasMPExtension())
2075 return Op.getOperand(0);
2078 if (Subtarget->isThumb())
2080 Flavor = ~Flavor & 0x3;
2082 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
2083 Op.getOperand(1), DAG.getConstant(Flavor, MVT::i32));
2086 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
2087 MachineFunction &MF = DAG.getMachineFunction();
2088 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
2090 // vastart just stores the address of the VarArgsFrameIndex slot into the
2091 // memory location argument.
2092 DebugLoc dl = Op.getDebugLoc();
2093 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2094 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2095 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2096 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2097 MachinePointerInfo(SV), false, false, 0);
2101 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
2102 SDValue &Root, SelectionDAG &DAG,
2103 DebugLoc dl) const {
2104 MachineFunction &MF = DAG.getMachineFunction();
2105 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2107 TargetRegisterClass *RC;
2108 if (AFI->isThumb1OnlyFunction())
2109 RC = ARM::tGPRRegisterClass;
2111 RC = ARM::GPRRegisterClass;
2113 // Transform the arguments stored in physical registers into virtual ones.
2114 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2115 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2118 if (NextVA.isMemLoc()) {
2119 MachineFrameInfo *MFI = MF.getFrameInfo();
2120 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
2122 // Create load node to retrieve arguments from the stack.
2123 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2124 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
2125 MachinePointerInfo::getFixedStack(FI),
2128 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2129 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2132 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
2136 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
2137 CallingConv::ID CallConv, bool isVarArg,
2138 const SmallVectorImpl<ISD::InputArg>
2140 DebugLoc dl, SelectionDAG &DAG,
2141 SmallVectorImpl<SDValue> &InVals)
2144 MachineFunction &MF = DAG.getMachineFunction();
2145 MachineFrameInfo *MFI = MF.getFrameInfo();
2147 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2149 // Assign locations to all of the incoming arguments.
2150 SmallVector<CCValAssign, 16> ArgLocs;
2151 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
2153 CCInfo.AnalyzeFormalArguments(Ins,
2154 CCAssignFnForNode(CallConv, /* Return*/ false,
2157 SmallVector<SDValue, 16> ArgValues;
2159 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2160 CCValAssign &VA = ArgLocs[i];
2162 // Arguments stored in registers.
2163 if (VA.isRegLoc()) {
2164 EVT RegVT = VA.getLocVT();
2167 if (VA.needsCustom()) {
2168 // f64 and vector types are split up into multiple registers or
2169 // combinations of registers and stack slots.
2170 if (VA.getLocVT() == MVT::v2f64) {
2171 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
2173 VA = ArgLocs[++i]; // skip ahead to next loc
2175 if (VA.isMemLoc()) {
2176 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
2177 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2178 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
2179 MachinePointerInfo::getFixedStack(FI),
2182 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
2185 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2186 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2187 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
2188 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2189 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
2191 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
2194 TargetRegisterClass *RC;
2196 if (RegVT == MVT::f32)
2197 RC = ARM::SPRRegisterClass;
2198 else if (RegVT == MVT::f64)
2199 RC = ARM::DPRRegisterClass;
2200 else if (RegVT == MVT::v2f64)
2201 RC = ARM::QPRRegisterClass;
2202 else if (RegVT == MVT::i32)
2203 RC = (AFI->isThumb1OnlyFunction() ?
2204 ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
2206 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2208 // Transform the arguments in physical registers into virtual ones.
2209 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2210 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2213 // If this is an 8 or 16-bit value, it is really passed promoted
2214 // to 32 bits. Insert an assert[sz]ext to capture this, then
2215 // truncate to the right size.
2216 switch (VA.getLocInfo()) {
2217 default: llvm_unreachable("Unknown loc info!");
2218 case CCValAssign::Full: break;
2219 case CCValAssign::BCvt:
2220 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
2222 case CCValAssign::SExt:
2223 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2224 DAG.getValueType(VA.getValVT()));
2225 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2227 case CCValAssign::ZExt:
2228 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2229 DAG.getValueType(VA.getValVT()));
2230 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2234 InVals.push_back(ArgValue);
2236 } else { // VA.isRegLoc()
2239 assert(VA.isMemLoc());
2240 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
2242 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
2243 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(), true);
2245 // Create load nodes to retrieve arguments from the stack.
2246 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2247 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2248 MachinePointerInfo::getFixedStack(FI),
2255 static const unsigned GPRArgRegs[] = {
2256 ARM::R0, ARM::R1, ARM::R2, ARM::R3
2259 unsigned NumGPRs = CCInfo.getFirstUnallocated
2260 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
2262 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
2263 unsigned VARegSize = (4 - NumGPRs) * 4;
2264 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
2265 unsigned ArgOffset = CCInfo.getNextStackOffset();
2266 if (VARegSaveSize) {
2267 // If this function is vararg, store any remaining integer argument regs
2268 // to their spots on the stack so that they may be loaded by deferencing
2269 // the result of va_next.
2270 AFI->setVarArgsRegSaveSize(VARegSaveSize);
2271 AFI->setVarArgsFrameIndex(
2272 MFI->CreateFixedObject(VARegSaveSize,
2273 ArgOffset + VARegSaveSize - VARegSize,
2275 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(),
2278 SmallVector<SDValue, 4> MemOps;
2279 for (; NumGPRs < 4; ++NumGPRs) {
2280 TargetRegisterClass *RC;
2281 if (AFI->isThumb1OnlyFunction())
2282 RC = ARM::tGPRRegisterClass;
2284 RC = ARM::GPRRegisterClass;
2286 unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
2287 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2289 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2290 MachinePointerInfo::getFixedStack(AFI->getVarArgsFrameIndex()),
2292 MemOps.push_back(Store);
2293 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
2294 DAG.getConstant(4, getPointerTy()));
2296 if (!MemOps.empty())
2297 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2298 &MemOps[0], MemOps.size());
2300 // This will point to the next argument passed via stack.
2301 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset, true));
2307 /// isFloatingPointZero - Return true if this is +0.0.
2308 static bool isFloatingPointZero(SDValue Op) {
2309 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
2310 return CFP->getValueAPF().isPosZero();
2311 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
2312 // Maybe this has already been legalized into the constant pool?
2313 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
2314 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
2315 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
2316 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
2317 return CFP->getValueAPF().isPosZero();
2323 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
2324 /// the given operands.
2326 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2327 SDValue &ARMcc, SelectionDAG &DAG,
2328 DebugLoc dl) const {
2329 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
2330 unsigned C = RHSC->getZExtValue();
2331 if (!isLegalICmpImmediate(C)) {
2332 // Constant does not fit, try adjusting it by one?
2337 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
2338 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
2339 RHS = DAG.getConstant(C-1, MVT::i32);
2344 if (C != 0 && isLegalICmpImmediate(C-1)) {
2345 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
2346 RHS = DAG.getConstant(C-1, MVT::i32);
2351 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
2352 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
2353 RHS = DAG.getConstant(C+1, MVT::i32);
2358 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
2359 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2360 RHS = DAG.getConstant(C+1, MVT::i32);
2367 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2368 ARMISD::NodeType CompareType;
2371 CompareType = ARMISD::CMP;
2376 CompareType = ARMISD::CMPZ;
2379 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2380 return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS);
2383 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
2385 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
2386 DebugLoc dl) const {
2388 if (!isFloatingPointZero(RHS))
2389 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS);
2391 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS);
2392 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp);
2395 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2396 SDValue Cond = Op.getOperand(0);
2397 SDValue SelectTrue = Op.getOperand(1);
2398 SDValue SelectFalse = Op.getOperand(2);
2399 DebugLoc dl = Op.getDebugLoc();
2403 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
2404 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
2406 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
2407 const ConstantSDNode *CMOVTrue =
2408 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
2409 const ConstantSDNode *CMOVFalse =
2410 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
2412 if (CMOVTrue && CMOVFalse) {
2413 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
2414 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
2418 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
2420 False = SelectFalse;
2421 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
2426 if (True.getNode() && False.getNode()) {
2427 EVT VT = Cond.getValueType();
2428 SDValue ARMcc = Cond.getOperand(2);
2429 SDValue CCR = Cond.getOperand(3);
2430 SDValue Cmp = Cond.getOperand(4);
2431 return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp);
2436 return DAG.getSelectCC(dl, Cond,
2437 DAG.getConstant(0, Cond.getValueType()),
2438 SelectTrue, SelectFalse, ISD::SETNE);
2441 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
2442 EVT VT = Op.getValueType();
2443 SDValue LHS = Op.getOperand(0);
2444 SDValue RHS = Op.getOperand(1);
2445 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2446 SDValue TrueVal = Op.getOperand(2);
2447 SDValue FalseVal = Op.getOperand(3);
2448 DebugLoc dl = Op.getDebugLoc();
2450 if (LHS.getValueType() == MVT::i32) {
2452 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2453 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2454 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,Cmp);
2457 ARMCC::CondCodes CondCode, CondCode2;
2458 FPCCToARMCC(CC, CondCode, CondCode2);
2460 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2461 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2462 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2463 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
2465 if (CondCode2 != ARMCC::AL) {
2466 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32);
2467 // FIXME: Needs another CMP because flag can have but one use.
2468 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
2469 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
2470 Result, TrueVal, ARMcc2, CCR, Cmp2);
2475 /// canChangeToInt - Given the fp compare operand, return true if it is suitable
2476 /// to morph to an integer compare sequence.
2477 static bool canChangeToInt(SDValue Op, bool &SeenZero,
2478 const ARMSubtarget *Subtarget) {
2479 SDNode *N = Op.getNode();
2480 if (!N->hasOneUse())
2481 // Otherwise it requires moving the value from fp to integer registers.
2483 if (!N->getNumValues())
2485 EVT VT = Op.getValueType();
2486 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
2487 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
2488 // vmrs are very slow, e.g. cortex-a8.
2491 if (isFloatingPointZero(Op)) {
2495 return ISD::isNormalLoad(N);
2498 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
2499 if (isFloatingPointZero(Op))
2500 return DAG.getConstant(0, MVT::i32);
2502 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
2503 return DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2504 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(),
2505 Ld->isVolatile(), Ld->isNonTemporal(),
2506 Ld->getAlignment());
2508 llvm_unreachable("Unknown VFP cmp argument!");
2511 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
2512 SDValue &RetVal1, SDValue &RetVal2) {
2513 if (isFloatingPointZero(Op)) {
2514 RetVal1 = DAG.getConstant(0, MVT::i32);
2515 RetVal2 = DAG.getConstant(0, MVT::i32);
2519 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
2520 SDValue Ptr = Ld->getBasePtr();
2521 RetVal1 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2522 Ld->getChain(), Ptr,
2523 Ld->getPointerInfo(),
2524 Ld->isVolatile(), Ld->isNonTemporal(),
2525 Ld->getAlignment());
2527 EVT PtrType = Ptr.getValueType();
2528 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
2529 SDValue NewPtr = DAG.getNode(ISD::ADD, Op.getDebugLoc(),
2530 PtrType, Ptr, DAG.getConstant(4, PtrType));
2531 RetVal2 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2532 Ld->getChain(), NewPtr,
2533 Ld->getPointerInfo().getWithOffset(4),
2534 Ld->isVolatile(), Ld->isNonTemporal(),
2539 llvm_unreachable("Unknown VFP cmp argument!");
2542 /// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
2543 /// f32 and even f64 comparisons to integer ones.
2545 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
2546 SDValue Chain = Op.getOperand(0);
2547 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2548 SDValue LHS = Op.getOperand(2);
2549 SDValue RHS = Op.getOperand(3);
2550 SDValue Dest = Op.getOperand(4);
2551 DebugLoc dl = Op.getDebugLoc();
2553 bool SeenZero = false;
2554 if (canChangeToInt(LHS, SeenZero, Subtarget) &&
2555 canChangeToInt(RHS, SeenZero, Subtarget) &&
2556 // If one of the operand is zero, it's safe to ignore the NaN case since
2557 // we only care about equality comparisons.
2558 (SeenZero || (DAG.isKnownNeverNaN(LHS) && DAG.isKnownNeverNaN(RHS)))) {
2559 // If unsafe fp math optimization is enabled and there are no othter uses of
2560 // the CMP operands, and the condition code is EQ oe NE, we can optimize it
2561 // to an integer comparison.
2562 if (CC == ISD::SETOEQ)
2564 else if (CC == ISD::SETUNE)
2568 if (LHS.getValueType() == MVT::f32) {
2569 LHS = bitcastf32Toi32(LHS, DAG);
2570 RHS = bitcastf32Toi32(RHS, DAG);
2571 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2572 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2573 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2574 Chain, Dest, ARMcc, CCR, Cmp);
2579 expandf64Toi32(LHS, DAG, LHS1, LHS2);
2580 expandf64Toi32(RHS, DAG, RHS1, RHS2);
2581 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2582 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2583 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
2584 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
2585 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7);
2591 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2592 SDValue Chain = Op.getOperand(0);
2593 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2594 SDValue LHS = Op.getOperand(2);
2595 SDValue RHS = Op.getOperand(3);
2596 SDValue Dest = Op.getOperand(4);
2597 DebugLoc dl = Op.getDebugLoc();
2599 if (LHS.getValueType() == MVT::i32) {
2601 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2602 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2603 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2604 Chain, Dest, ARMcc, CCR, Cmp);
2607 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
2610 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
2611 CC == ISD::SETNE || CC == ISD::SETUNE)) {
2612 SDValue Result = OptimizeVFPBrcond(Op, DAG);
2613 if (Result.getNode())
2617 ARMCC::CondCodes CondCode, CondCode2;
2618 FPCCToARMCC(CC, CondCode, CondCode2);
2620 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2621 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2622 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2623 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
2624 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
2625 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2626 if (CondCode2 != ARMCC::AL) {
2627 ARMcc = DAG.getConstant(CondCode2, MVT::i32);
2628 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
2629 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2634 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
2635 SDValue Chain = Op.getOperand(0);
2636 SDValue Table = Op.getOperand(1);
2637 SDValue Index = Op.getOperand(2);
2638 DebugLoc dl = Op.getDebugLoc();
2640 EVT PTy = getPointerTy();
2641 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
2642 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
2643 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
2644 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
2645 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
2646 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
2647 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2648 if (Subtarget->isThumb2()) {
2649 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
2650 // which does another jump to the destination. This also makes it easier
2651 // to translate it to TBB / TBH later.
2652 // FIXME: This might not work if the function is extremely large.
2653 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
2654 Addr, Op.getOperand(2), JTI, UId);
2656 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2657 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
2658 MachinePointerInfo::getJumpTable(),
2660 Chain = Addr.getValue(1);
2661 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
2662 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2664 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
2665 MachinePointerInfo::getJumpTable(), false, false, 0);
2666 Chain = Addr.getValue(1);
2667 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2671 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
2672 DebugLoc dl = Op.getDebugLoc();
2675 switch (Op.getOpcode()) {
2677 assert(0 && "Invalid opcode!");
2678 case ISD::FP_TO_SINT:
2679 Opc = ARMISD::FTOSI;
2681 case ISD::FP_TO_UINT:
2682 Opc = ARMISD::FTOUI;
2685 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
2686 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
2689 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
2690 EVT VT = Op.getValueType();
2691 DebugLoc dl = Op.getDebugLoc();
2694 switch (Op.getOpcode()) {
2696 assert(0 && "Invalid opcode!");
2697 case ISD::SINT_TO_FP:
2698 Opc = ARMISD::SITOF;
2700 case ISD::UINT_TO_FP:
2701 Opc = ARMISD::UITOF;
2705 Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
2706 return DAG.getNode(Opc, dl, VT, Op);
2709 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
2710 // Implement fcopysign with a fabs and a conditional fneg.
2711 SDValue Tmp0 = Op.getOperand(0);
2712 SDValue Tmp1 = Op.getOperand(1);
2713 DebugLoc dl = Op.getDebugLoc();
2714 EVT VT = Op.getValueType();
2715 EVT SrcVT = Tmp1.getValueType();
2716 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
2717 SDValue ARMcc = DAG.getConstant(ARMCC::LT, MVT::i32);
2718 SDValue FP0 = DAG.getConstantFP(0.0, SrcVT);
2719 SDValue Cmp = getVFPCmp(Tmp1, FP0, DAG, dl);
2720 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2721 return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMcc, CCR, Cmp);
2724 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
2725 MachineFunction &MF = DAG.getMachineFunction();
2726 MachineFrameInfo *MFI = MF.getFrameInfo();
2727 MFI->setReturnAddressIsTaken(true);
2729 EVT VT = Op.getValueType();
2730 DebugLoc dl = Op.getDebugLoc();
2731 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2733 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
2734 SDValue Offset = DAG.getConstant(4, MVT::i32);
2735 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
2736 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
2737 MachinePointerInfo(), false, false, 0);
2740 // Return LR, which contains the return address. Mark it an implicit live-in.
2741 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
2742 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
2745 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2746 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2747 MFI->setFrameAddressIsTaken(true);
2749 EVT VT = Op.getValueType();
2750 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
2751 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2752 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
2753 ? ARM::R7 : ARM::R11;
2754 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
2756 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
2757 MachinePointerInfo(),
2762 /// ExpandBIT_CONVERT - If the target supports VFP, this function is called to
2763 /// expand a bit convert where either the source or destination type is i64 to
2764 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
2765 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
2766 /// vectors), since the legalizer won't know what to do with that.
2767 static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
2768 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2769 DebugLoc dl = N->getDebugLoc();
2770 SDValue Op = N->getOperand(0);
2772 // This function is only supposed to be called for i64 types, either as the
2773 // source or destination of the bit convert.
2774 EVT SrcVT = Op.getValueType();
2775 EVT DstVT = N->getValueType(0);
2776 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
2777 "ExpandBIT_CONVERT called for non-i64 type");
2779 // Turn i64->f64 into VMOVDRR.
2780 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
2781 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2782 DAG.getConstant(0, MVT::i32));
2783 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2784 DAG.getConstant(1, MVT::i32));
2785 return DAG.getNode(ISD::BIT_CONVERT, dl, DstVT,
2786 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
2789 // Turn f64->i64 into VMOVRRD.
2790 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
2791 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
2792 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
2793 // Merge the pieces into a single i64 value.
2794 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
2800 /// getZeroVector - Returns a vector of specified type with all zero elements.
2801 /// Zero vectors are used to represent vector negation and in those cases
2802 /// will be implemented with the NEON VNEG instruction. However, VNEG does
2803 /// not support i64 elements, so sometimes the zero vectors will need to be
2804 /// explicitly constructed. Regardless, use a canonical VMOV to create the
2806 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2807 assert(VT.isVector() && "Expected a vector type");
2808 // The canonical modified immediate encoding of a zero vector is....0!
2809 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32);
2810 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
2811 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
2812 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov);
2815 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
2816 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2817 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
2818 SelectionDAG &DAG) const {
2819 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2820 EVT VT = Op.getValueType();
2821 unsigned VTBits = VT.getSizeInBits();
2822 DebugLoc dl = Op.getDebugLoc();
2823 SDValue ShOpLo = Op.getOperand(0);
2824 SDValue ShOpHi = Op.getOperand(1);
2825 SDValue ShAmt = Op.getOperand(2);
2827 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
2829 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
2831 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2832 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2833 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
2834 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2835 DAG.getConstant(VTBits, MVT::i32));
2836 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
2837 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2838 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
2840 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2841 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
2843 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
2844 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
2847 SDValue Ops[2] = { Lo, Hi };
2848 return DAG.getMergeValues(Ops, 2, dl);
2851 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
2852 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2853 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
2854 SelectionDAG &DAG) const {
2855 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2856 EVT VT = Op.getValueType();
2857 unsigned VTBits = VT.getSizeInBits();
2858 DebugLoc dl = Op.getDebugLoc();
2859 SDValue ShOpLo = Op.getOperand(0);
2860 SDValue ShOpHi = Op.getOperand(1);
2861 SDValue ShAmt = Op.getOperand(2);
2864 assert(Op.getOpcode() == ISD::SHL_PARTS);
2865 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2866 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2867 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
2868 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2869 DAG.getConstant(VTBits, MVT::i32));
2870 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
2871 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
2873 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2874 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2875 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
2877 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
2878 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
2881 SDValue Ops[2] = { Lo, Hi };
2882 return DAG.getMergeValues(Ops, 2, dl);
2885 SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
2886 SelectionDAG &DAG) const {
2887 // The rounding mode is in bits 23:22 of the FPSCR.
2888 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
2889 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
2890 // so that the shift + and get folded into a bitfield extract.
2891 DebugLoc dl = Op.getDebugLoc();
2892 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
2893 DAG.getConstant(Intrinsic::arm_get_fpscr,
2895 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
2896 DAG.getConstant(1U << 22, MVT::i32));
2897 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
2898 DAG.getConstant(22, MVT::i32));
2899 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
2900 DAG.getConstant(3, MVT::i32));
2903 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
2904 const ARMSubtarget *ST) {
2905 EVT VT = N->getValueType(0);
2906 DebugLoc dl = N->getDebugLoc();
2908 if (!ST->hasV6T2Ops())
2911 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
2912 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
2915 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
2916 const ARMSubtarget *ST) {
2917 EVT VT = N->getValueType(0);
2918 DebugLoc dl = N->getDebugLoc();
2920 // Lower vector shifts on NEON to use VSHL.
2921 if (VT.isVector()) {
2922 assert(ST->hasNEON() && "unexpected vector shift");
2924 // Left shifts translate directly to the vshiftu intrinsic.
2925 if (N->getOpcode() == ISD::SHL)
2926 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2927 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
2928 N->getOperand(0), N->getOperand(1));
2930 assert((N->getOpcode() == ISD::SRA ||
2931 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
2933 // NEON uses the same intrinsics for both left and right shifts. For
2934 // right shifts, the shift amounts are negative, so negate the vector of
2936 EVT ShiftVT = N->getOperand(1).getValueType();
2937 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
2938 getZeroVector(ShiftVT, DAG, dl),
2940 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
2941 Intrinsic::arm_neon_vshifts :
2942 Intrinsic::arm_neon_vshiftu);
2943 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2944 DAG.getConstant(vshiftInt, MVT::i32),
2945 N->getOperand(0), NegatedCount);
2948 // We can get here for a node like i32 = ISD::SHL i32, i64
2952 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
2953 "Unknown shift to lower!");
2955 // We only lower SRA, SRL of 1 here, all others use generic lowering.
2956 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
2957 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
2960 // If we are in thumb mode, we don't have RRX.
2961 if (ST->isThumb1Only()) return SDValue();
2963 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
2964 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2965 DAG.getConstant(0, MVT::i32));
2966 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2967 DAG.getConstant(1, MVT::i32));
2969 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
2970 // captures the result into a carry flag.
2971 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
2972 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
2974 // The low part is an ARMISD::RRX operand, which shifts the carry in.
2975 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
2977 // Merge the pieces into a single i64 value.
2978 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
2981 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
2982 SDValue TmpOp0, TmpOp1;
2983 bool Invert = false;
2987 SDValue Op0 = Op.getOperand(0);
2988 SDValue Op1 = Op.getOperand(1);
2989 SDValue CC = Op.getOperand(2);
2990 EVT VT = Op.getValueType();
2991 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
2992 DebugLoc dl = Op.getDebugLoc();
2994 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
2995 switch (SetCCOpcode) {
2996 default: llvm_unreachable("Illegal FP comparison"); break;
2998 case ISD::SETNE: Invert = true; // Fallthrough
3000 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3002 case ISD::SETLT: Swap = true; // Fallthrough
3004 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3006 case ISD::SETLE: Swap = true; // Fallthrough
3008 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3009 case ISD::SETUGE: Swap = true; // Fallthrough
3010 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
3011 case ISD::SETUGT: Swap = true; // Fallthrough
3012 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
3013 case ISD::SETUEQ: Invert = true; // Fallthrough
3015 // Expand this to (OLT | OGT).
3019 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3020 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
3022 case ISD::SETUO: Invert = true; // Fallthrough
3024 // Expand this to (OLT | OGE).
3028 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3029 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
3033 // Integer comparisons.
3034 switch (SetCCOpcode) {
3035 default: llvm_unreachable("Illegal integer comparison"); break;
3036 case ISD::SETNE: Invert = true;
3037 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3038 case ISD::SETLT: Swap = true;
3039 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3040 case ISD::SETLE: Swap = true;
3041 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3042 case ISD::SETULT: Swap = true;
3043 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
3044 case ISD::SETULE: Swap = true;
3045 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
3048 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
3049 if (Opc == ARMISD::VCEQ) {
3052 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
3054 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
3057 // Ignore bitconvert.
3058 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BIT_CONVERT)
3059 AndOp = AndOp.getOperand(0);
3061 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
3063 Op0 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(0));
3064 Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(1));
3071 std::swap(Op0, Op1);
3073 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3076 Result = DAG.getNOT(dl, Result, VT);
3081 /// isNEONModifiedImm - Check if the specified splat value corresponds to a
3082 /// valid vector constant for a NEON instruction with a "modified immediate"
3083 /// operand (e.g., VMOV). If so, return the encoded value.
3084 static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
3085 unsigned SplatBitSize, SelectionDAG &DAG,
3086 EVT &VT, bool is128Bits, bool isVMOV) {
3087 unsigned OpCmode, Imm;
3089 // SplatBitSize is set to the smallest size that splats the vector, so a
3090 // zero vector will always have SplatBitSize == 8. However, NEON modified
3091 // immediate instructions others than VMOV do not support the 8-bit encoding
3092 // of a zero vector, and the default encoding of zero is supposed to be the
3097 switch (SplatBitSize) {
3101 // Any 1-byte value is OK. Op=0, Cmode=1110.
3102 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
3105 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
3109 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
3110 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
3111 if ((SplatBits & ~0xff) == 0) {
3112 // Value = 0x00nn: Op=x, Cmode=100x.
3117 if ((SplatBits & ~0xff00) == 0) {
3118 // Value = 0xnn00: Op=x, Cmode=101x.
3120 Imm = SplatBits >> 8;
3126 // NEON's 32-bit VMOV supports splat values where:
3127 // * only one byte is nonzero, or
3128 // * the least significant byte is 0xff and the second byte is nonzero, or
3129 // * the least significant 2 bytes are 0xff and the third is nonzero.
3130 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
3131 if ((SplatBits & ~0xff) == 0) {
3132 // Value = 0x000000nn: Op=x, Cmode=000x.
3137 if ((SplatBits & ~0xff00) == 0) {
3138 // Value = 0x0000nn00: Op=x, Cmode=001x.
3140 Imm = SplatBits >> 8;
3143 if ((SplatBits & ~0xff0000) == 0) {
3144 // Value = 0x00nn0000: Op=x, Cmode=010x.
3146 Imm = SplatBits >> 16;
3149 if ((SplatBits & ~0xff000000) == 0) {
3150 // Value = 0xnn000000: Op=x, Cmode=011x.
3152 Imm = SplatBits >> 24;
3156 if ((SplatBits & ~0xffff) == 0 &&
3157 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
3158 // Value = 0x0000nnff: Op=x, Cmode=1100.
3160 Imm = SplatBits >> 8;
3165 if ((SplatBits & ~0xffffff) == 0 &&
3166 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
3167 // Value = 0x00nnffff: Op=x, Cmode=1101.
3169 Imm = SplatBits >> 16;
3170 SplatBits |= 0xffff;
3174 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
3175 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
3176 // VMOV.I32. A (very) minor optimization would be to replicate the value
3177 // and fall through here to test for a valid 64-bit splat. But, then the
3178 // caller would also need to check and handle the change in size.
3184 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
3185 uint64_t BitMask = 0xff;
3187 unsigned ImmMask = 1;
3189 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
3190 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
3193 } else if ((SplatBits & BitMask) != 0) {
3199 // Op=1, Cmode=1110.
3202 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
3207 llvm_unreachable("unexpected size for isNEONModifiedImm");
3211 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
3212 return DAG.getTargetConstant(EncodedVal, MVT::i32);
3215 static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT,
3216 bool &ReverseVEXT, unsigned &Imm) {
3217 unsigned NumElts = VT.getVectorNumElements();
3218 ReverseVEXT = false;
3220 // Assume that the first shuffle index is not UNDEF. Fail if it is.
3226 // If this is a VEXT shuffle, the immediate value is the index of the first
3227 // element. The other shuffle indices must be the successive elements after
3229 unsigned ExpectedElt = Imm;
3230 for (unsigned i = 1; i < NumElts; ++i) {
3231 // Increment the expected index. If it wraps around, it may still be
3232 // a VEXT but the source vectors must be swapped.
3234 if (ExpectedElt == NumElts * 2) {
3239 if (M[i] < 0) continue; // ignore UNDEF indices
3240 if (ExpectedElt != static_cast<unsigned>(M[i]))
3244 // Adjust the index value if the source operands will be swapped.
3251 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
3252 /// instruction with the specified blocksize. (The order of the elements
3253 /// within each block of the vector is reversed.)
3254 static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT,
3255 unsigned BlockSize) {
3256 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
3257 "Only possible block sizes for VREV are: 16, 32, 64");
3259 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3263 unsigned NumElts = VT.getVectorNumElements();
3264 unsigned BlockElts = M[0] + 1;
3265 // If the first shuffle index is UNDEF, be optimistic.
3267 BlockElts = BlockSize / EltSz;
3269 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
3272 for (unsigned i = 0; i < NumElts; ++i) {
3273 if (M[i] < 0) continue; // ignore UNDEF indices
3274 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
3281 static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT,
3282 unsigned &WhichResult) {
3283 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3287 unsigned NumElts = VT.getVectorNumElements();
3288 WhichResult = (M[0] == 0 ? 0 : 1);
3289 for (unsigned i = 0; i < NumElts; i += 2) {
3290 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3291 (M[i+1] >= 0 && (unsigned) M[i+1] != i + NumElts + WhichResult))
3297 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
3298 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3299 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
3300 static bool isVTRN_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3301 unsigned &WhichResult) {
3302 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3306 unsigned NumElts = VT.getVectorNumElements();
3307 WhichResult = (M[0] == 0 ? 0 : 1);
3308 for (unsigned i = 0; i < NumElts; i += 2) {
3309 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3310 (M[i+1] >= 0 && (unsigned) M[i+1] != i + WhichResult))
3316 static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT,
3317 unsigned &WhichResult) {
3318 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3322 unsigned NumElts = VT.getVectorNumElements();
3323 WhichResult = (M[0] == 0 ? 0 : 1);
3324 for (unsigned i = 0; i != NumElts; ++i) {
3325 if (M[i] < 0) continue; // ignore UNDEF indices
3326 if ((unsigned) M[i] != 2 * i + WhichResult)
3330 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3331 if (VT.is64BitVector() && EltSz == 32)
3337 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
3338 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3339 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
3340 static bool isVUZP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3341 unsigned &WhichResult) {
3342 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3346 unsigned Half = VT.getVectorNumElements() / 2;
3347 WhichResult = (M[0] == 0 ? 0 : 1);
3348 for (unsigned j = 0; j != 2; ++j) {
3349 unsigned Idx = WhichResult;
3350 for (unsigned i = 0; i != Half; ++i) {
3351 int MIdx = M[i + j * Half];
3352 if (MIdx >= 0 && (unsigned) MIdx != Idx)
3358 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3359 if (VT.is64BitVector() && EltSz == 32)
3365 static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT,
3366 unsigned &WhichResult) {
3367 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3371 unsigned NumElts = VT.getVectorNumElements();
3372 WhichResult = (M[0] == 0 ? 0 : 1);
3373 unsigned Idx = WhichResult * NumElts / 2;
3374 for (unsigned i = 0; i != NumElts; i += 2) {
3375 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3376 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts))
3381 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3382 if (VT.is64BitVector() && EltSz == 32)
3388 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
3389 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3390 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
3391 static bool isVZIP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3392 unsigned &WhichResult) {
3393 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3397 unsigned NumElts = VT.getVectorNumElements();
3398 WhichResult = (M[0] == 0 ? 0 : 1);
3399 unsigned Idx = WhichResult * NumElts / 2;
3400 for (unsigned i = 0; i != NumElts; i += 2) {
3401 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3402 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx))
3407 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3408 if (VT.is64BitVector() && EltSz == 32)
3414 // If N is an integer constant that can be moved into a register in one
3415 // instruction, return an SDValue of such a constant (will become a MOV
3416 // instruction). Otherwise return null.
3417 static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG,
3418 const ARMSubtarget *ST, DebugLoc dl) {
3420 if (!isa<ConstantSDNode>(N))
3422 Val = cast<ConstantSDNode>(N)->getZExtValue();
3424 if (ST->isThumb1Only()) {
3425 if (Val <= 255 || ~Val <= 255)
3426 return DAG.getConstant(Val, MVT::i32);
3428 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1)
3429 return DAG.getConstant(Val, MVT::i32);
3434 // If this is a case we can't handle, return null and let the default
3435 // expansion code take care of it.
3436 static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
3437 const ARMSubtarget *ST) {
3438 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
3439 DebugLoc dl = Op.getDebugLoc();
3440 EVT VT = Op.getValueType();
3442 APInt SplatBits, SplatUndef;
3443 unsigned SplatBitSize;
3445 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
3446 if (SplatBitSize <= 64) {
3447 // Check if an immediate VMOV works.
3449 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
3450 SplatUndef.getZExtValue(), SplatBitSize,
3451 DAG, VmovVT, VT.is128BitVector(), true);
3452 if (Val.getNode()) {
3453 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
3454 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov);
3457 // Try an immediate VMVN.
3458 uint64_t NegatedImm = (SplatBits.getZExtValue() ^
3459 ((1LL << SplatBitSize) - 1));
3460 Val = isNEONModifiedImm(NegatedImm,
3461 SplatUndef.getZExtValue(), SplatBitSize,
3462 DAG, VmovVT, VT.is128BitVector(), false);
3463 if (Val.getNode()) {
3464 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
3465 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov);
3470 // Scan through the operands to see if only one value is used.
3471 unsigned NumElts = VT.getVectorNumElements();
3472 bool isOnlyLowElement = true;
3473 bool usesOnlyOneValue = true;
3474 bool isConstant = true;
3476 for (unsigned i = 0; i < NumElts; ++i) {
3477 SDValue V = Op.getOperand(i);
3478 if (V.getOpcode() == ISD::UNDEF)
3481 isOnlyLowElement = false;
3482 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
3485 if (!Value.getNode())
3487 else if (V != Value)
3488 usesOnlyOneValue = false;
3491 if (!Value.getNode())
3492 return DAG.getUNDEF(VT);
3494 if (isOnlyLowElement)
3495 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
3497 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3499 // Use VDUP for non-constant splats. For f32 constant splats, reduce to
3500 // i32 and try again.
3501 if (usesOnlyOneValue && EltSize <= 32) {
3503 return DAG.getNode(ARMISD::VDUP, dl, VT, Value);
3504 if (VT.getVectorElementType().isFloatingPoint()) {
3505 SmallVector<SDValue, 8> Ops;
3506 for (unsigned i = 0; i < NumElts; ++i)
3507 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32,
3509 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &Ops[0],
3511 Val = LowerBUILD_VECTOR(Val, DAG, ST);
3513 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val);
3515 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
3517 return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
3520 // If all elements are constants and the case above didn't get hit, fall back
3521 // to the default expansion, which will generate a load from the constant
3526 // Vectors with 32- or 64-bit elements can be built by directly assigning
3527 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
3528 // will be legalized.
3529 if (EltSize >= 32) {
3530 // Do the expansion with floating-point types, since that is what the VFP
3531 // registers are defined to use, and since i64 is not legal.
3532 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3533 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3534 SmallVector<SDValue, 8> Ops;
3535 for (unsigned i = 0; i < NumElts; ++i)
3536 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, EltVT, Op.getOperand(i)));
3537 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
3538 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val);
3544 /// isShuffleMaskLegal - Targets can use this to indicate that they only
3545 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
3546 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
3547 /// are assumed to be legal.
3549 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
3551 if (VT.getVectorNumElements() == 4 &&
3552 (VT.is128BitVector() || VT.is64BitVector())) {
3553 unsigned PFIndexes[4];
3554 for (unsigned i = 0; i != 4; ++i) {
3558 PFIndexes[i] = M[i];
3561 // Compute the index in the perfect shuffle table.
3562 unsigned PFTableIndex =
3563 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3564 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3565 unsigned Cost = (PFEntry >> 30);
3572 unsigned Imm, WhichResult;
3574 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3575 return (EltSize >= 32 ||
3576 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
3577 isVREVMask(M, VT, 64) ||
3578 isVREVMask(M, VT, 32) ||
3579 isVREVMask(M, VT, 16) ||
3580 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
3581 isVTRNMask(M, VT, WhichResult) ||
3582 isVUZPMask(M, VT, WhichResult) ||
3583 isVZIPMask(M, VT, WhichResult) ||
3584 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
3585 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
3586 isVZIP_v_undef_Mask(M, VT, WhichResult));
3589 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
3590 /// the specified operations to build the shuffle.
3591 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
3592 SDValue RHS, SelectionDAG &DAG,
3594 unsigned OpNum = (PFEntry >> 26) & 0x0F;
3595 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
3596 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
3599 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
3608 OP_VUZPL, // VUZP, left result
3609 OP_VUZPR, // VUZP, right result
3610 OP_VZIPL, // VZIP, left result
3611 OP_VZIPR, // VZIP, right result
3612 OP_VTRNL, // VTRN, left result
3613 OP_VTRNR // VTRN, right result
3616 if (OpNum == OP_COPY) {
3617 if (LHSID == (1*9+2)*9+3) return LHS;
3618 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
3622 SDValue OpLHS, OpRHS;
3623 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
3624 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
3625 EVT VT = OpLHS.getValueType();
3628 default: llvm_unreachable("Unknown shuffle opcode!");
3630 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
3635 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
3636 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
3640 return DAG.getNode(ARMISD::VEXT, dl, VT,
3642 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
3645 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3646 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
3649 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3650 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
3653 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3654 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
3658 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
3659 SDValue V1 = Op.getOperand(0);
3660 SDValue V2 = Op.getOperand(1);
3661 DebugLoc dl = Op.getDebugLoc();
3662 EVT VT = Op.getValueType();
3663 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
3664 SmallVector<int, 8> ShuffleMask;
3666 // Convert shuffles that are directly supported on NEON to target-specific
3667 // DAG nodes, instead of keeping them as shuffles and matching them again
3668 // during code selection. This is more efficient and avoids the possibility
3669 // of inconsistencies between legalization and selection.
3670 // FIXME: floating-point vectors should be canonicalized to integer vectors
3671 // of the same time so that they get CSEd properly.
3672 SVN->getMask(ShuffleMask);
3674 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3675 if (EltSize <= 32) {
3676 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
3677 int Lane = SVN->getSplatIndex();
3678 // If this is undef splat, generate it via "just" vdup, if possible.
3679 if (Lane == -1) Lane = 0;
3681 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
3682 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
3684 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
3685 DAG.getConstant(Lane, MVT::i32));
3690 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
3693 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
3694 DAG.getConstant(Imm, MVT::i32));
3697 if (isVREVMask(ShuffleMask, VT, 64))
3698 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
3699 if (isVREVMask(ShuffleMask, VT, 32))
3700 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
3701 if (isVREVMask(ShuffleMask, VT, 16))
3702 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
3704 // Check for Neon shuffles that modify both input vectors in place.
3705 // If both results are used, i.e., if there are two shuffles with the same
3706 // source operands and with masks corresponding to both results of one of
3707 // these operations, DAG memoization will ensure that a single node is
3708 // used for both shuffles.
3709 unsigned WhichResult;
3710 if (isVTRNMask(ShuffleMask, VT, WhichResult))
3711 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3712 V1, V2).getValue(WhichResult);
3713 if (isVUZPMask(ShuffleMask, VT, WhichResult))
3714 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3715 V1, V2).getValue(WhichResult);
3716 if (isVZIPMask(ShuffleMask, VT, WhichResult))
3717 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3718 V1, V2).getValue(WhichResult);
3720 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
3721 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3722 V1, V1).getValue(WhichResult);
3723 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
3724 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3725 V1, V1).getValue(WhichResult);
3726 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
3727 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3728 V1, V1).getValue(WhichResult);
3731 // If the shuffle is not directly supported and it has 4 elements, use
3732 // the PerfectShuffle-generated table to synthesize it from other shuffles.
3733 unsigned NumElts = VT.getVectorNumElements();
3735 unsigned PFIndexes[4];
3736 for (unsigned i = 0; i != 4; ++i) {
3737 if (ShuffleMask[i] < 0)
3740 PFIndexes[i] = ShuffleMask[i];
3743 // Compute the index in the perfect shuffle table.
3744 unsigned PFTableIndex =
3745 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3746 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3747 unsigned Cost = (PFEntry >> 30);
3750 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
3753 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
3754 if (EltSize >= 32) {
3755 // Do the expansion with floating-point types, since that is what the VFP
3756 // registers are defined to use, and since i64 is not legal.
3757 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3758 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3759 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, V1);
3760 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, V2);
3761 SmallVector<SDValue, 8> Ops;
3762 for (unsigned i = 0; i < NumElts; ++i) {
3763 if (ShuffleMask[i] < 0)
3764 Ops.push_back(DAG.getUNDEF(EltVT));
3766 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3767 ShuffleMask[i] < (int)NumElts ? V1 : V2,
3768 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
3771 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
3772 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val);
3778 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
3779 // EXTRACT_VECTOR_ELT is legal only for immediate indexes.
3780 SDValue Lane = Op.getOperand(1);
3781 if (!isa<ConstantSDNode>(Lane))
3784 SDValue Vec = Op.getOperand(0);
3785 if (Op.getValueType() == MVT::i32 &&
3786 Vec.getValueType().getVectorElementType().getSizeInBits() < 32) {
3787 DebugLoc dl = Op.getDebugLoc();
3788 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
3794 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
3795 // The only time a CONCAT_VECTORS operation can have legal types is when
3796 // two 64-bit vectors are concatenated to a 128-bit vector.
3797 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
3798 "unexpected CONCAT_VECTORS");
3799 DebugLoc dl = Op.getDebugLoc();
3800 SDValue Val = DAG.getUNDEF(MVT::v2f64);
3801 SDValue Op0 = Op.getOperand(0);
3802 SDValue Op1 = Op.getOperand(1);
3803 if (Op0.getOpcode() != ISD::UNDEF)
3804 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
3805 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op0),
3806 DAG.getIntPtrConstant(0));
3807 if (Op1.getOpcode() != ISD::UNDEF)
3808 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
3809 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op1),
3810 DAG.getIntPtrConstant(1));
3811 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Val);
3814 /// SkipExtension - For a node that is either a SIGN_EXTEND, ZERO_EXTEND, or
3815 /// an extending load, return the unextended value.
3816 static SDValue SkipExtension(SDNode *N, SelectionDAG &DAG) {
3817 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
3818 return N->getOperand(0);
3819 LoadSDNode *LD = cast<LoadSDNode>(N);
3820 return DAG.getLoad(LD->getMemoryVT(), N->getDebugLoc(), LD->getChain(),
3821 LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(),
3822 LD->isNonTemporal(), LD->getAlignment());
3825 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
3826 // Multiplications are only custom-lowered for 128-bit vectors so that
3827 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
3828 EVT VT = Op.getValueType();
3829 assert(VT.is128BitVector() && "unexpected type for custom-lowering ISD::MUL");
3830 SDNode *N0 = Op.getOperand(0).getNode();
3831 SDNode *N1 = Op.getOperand(1).getNode();
3832 unsigned NewOpc = 0;
3833 if ((N0->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N0)) &&
3834 (N1->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N1))) {
3835 NewOpc = ARMISD::VMULLs;
3836 } else if ((N0->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N0)) &&
3837 (N1->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N1))) {
3838 NewOpc = ARMISD::VMULLu;
3839 } else if (VT == MVT::v2i64) {
3840 // Fall through to expand this. It is not legal.
3843 // Other vector multiplications are legal.
3847 // Legalize to a VMULL instruction.
3848 DebugLoc DL = Op.getDebugLoc();
3849 SDValue Op0 = SkipExtension(N0, DAG);
3850 SDValue Op1 = SkipExtension(N1, DAG);
3852 assert(Op0.getValueType().is64BitVector() &&
3853 Op1.getValueType().is64BitVector() &&
3854 "unexpected types for extended operands to VMULL");
3855 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
3858 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
3859 switch (Op.getOpcode()) {
3860 default: llvm_unreachable("Don't know how to custom lower this!");
3861 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3862 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
3863 case ISD::GlobalAddress:
3864 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
3865 LowerGlobalAddressELF(Op, DAG);
3866 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
3867 case ISD::SELECT: return LowerSELECT(Op, DAG);
3868 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
3869 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
3870 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
3871 case ISD::VASTART: return LowerVASTART(Op, DAG);
3872 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget);
3873 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget);
3874 case ISD::SINT_TO_FP:
3875 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
3876 case ISD::FP_TO_SINT:
3877 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
3878 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
3879 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
3880 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
3881 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
3882 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
3883 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
3884 case ISD::EH_SJLJ_DISPATCHSETUP: return LowerEH_SJLJ_DISPATCHSETUP(Op, DAG);
3885 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
3887 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(Op.getNode(), DAG);
3890 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
3891 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
3892 case ISD::SRL_PARTS:
3893 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
3894 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
3895 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
3896 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
3897 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
3898 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
3899 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
3900 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
3901 case ISD::MUL: return LowerMUL(Op, DAG);
3906 /// ReplaceNodeResults - Replace the results of node with an illegal result
3907 /// type with new values built out of custom code.
3908 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
3909 SmallVectorImpl<SDValue>&Results,
3910 SelectionDAG &DAG) const {
3912 switch (N->getOpcode()) {
3914 llvm_unreachable("Don't know how to custom expand this!");
3916 case ISD::BIT_CONVERT:
3917 Res = ExpandBIT_CONVERT(N, DAG);
3921 Res = LowerShift(N, DAG, Subtarget);
3925 Results.push_back(Res);
3928 //===----------------------------------------------------------------------===//
3929 // ARM Scheduler Hooks
3930 //===----------------------------------------------------------------------===//
3933 ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
3934 MachineBasicBlock *BB,
3935 unsigned Size) const {
3936 unsigned dest = MI->getOperand(0).getReg();
3937 unsigned ptr = MI->getOperand(1).getReg();
3938 unsigned oldval = MI->getOperand(2).getReg();
3939 unsigned newval = MI->getOperand(3).getReg();
3940 unsigned scratch = BB->getParent()->getRegInfo()
3941 .createVirtualRegister(ARM::GPRRegisterClass);
3942 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3943 DebugLoc dl = MI->getDebugLoc();
3944 bool isThumb2 = Subtarget->isThumb2();
3946 unsigned ldrOpc, strOpc;
3948 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
3950 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
3951 strOpc = isThumb2 ? ARM::t2LDREXB : ARM::STREXB;
3954 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
3955 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
3958 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
3959 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
3963 MachineFunction *MF = BB->getParent();
3964 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3965 MachineFunction::iterator It = BB;
3966 ++It; // insert the new blocks after the current block
3968 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
3969 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
3970 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3971 MF->insert(It, loop1MBB);
3972 MF->insert(It, loop2MBB);
3973 MF->insert(It, exitMBB);
3975 // Transfer the remainder of BB and its successor edges to exitMBB.
3976 exitMBB->splice(exitMBB->begin(), BB,
3977 llvm::next(MachineBasicBlock::iterator(MI)),
3979 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
3983 // fallthrough --> loop1MBB
3984 BB->addSuccessor(loop1MBB);
3987 // ldrex dest, [ptr]
3991 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
3992 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
3993 .addReg(dest).addReg(oldval));
3994 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3995 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
3996 BB->addSuccessor(loop2MBB);
3997 BB->addSuccessor(exitMBB);
4000 // strex scratch, newval, [ptr]
4004 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval)
4006 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4007 .addReg(scratch).addImm(0));
4008 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4009 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
4010 BB->addSuccessor(loop1MBB);
4011 BB->addSuccessor(exitMBB);
4017 MI->eraseFromParent(); // The instruction is gone now.
4023 ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
4024 unsigned Size, unsigned BinOpcode) const {
4025 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4026 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4028 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4029 MachineFunction *MF = BB->getParent();
4030 MachineFunction::iterator It = BB;
4033 unsigned dest = MI->getOperand(0).getReg();
4034 unsigned ptr = MI->getOperand(1).getReg();
4035 unsigned incr = MI->getOperand(2).getReg();
4036 DebugLoc dl = MI->getDebugLoc();
4038 bool isThumb2 = Subtarget->isThumb2();
4039 unsigned ldrOpc, strOpc;
4041 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
4043 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
4044 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
4047 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
4048 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
4051 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
4052 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
4056 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
4057 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
4058 MF->insert(It, loopMBB);
4059 MF->insert(It, exitMBB);
4061 // Transfer the remainder of BB and its successor edges to exitMBB.
4062 exitMBB->splice(exitMBB->begin(), BB,
4063 llvm::next(MachineBasicBlock::iterator(MI)),
4065 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4067 MachineRegisterInfo &RegInfo = MF->getRegInfo();
4068 unsigned scratch = RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
4069 unsigned scratch2 = (!BinOpcode) ? incr :
4070 RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
4074 // fallthrough --> loopMBB
4075 BB->addSuccessor(loopMBB);
4079 // <binop> scratch2, dest, incr
4080 // strex scratch, scratch2, ptr
4083 // fallthrough --> exitMBB
4085 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
4087 // operand order needs to go the other way for NAND
4088 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr)
4089 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
4090 addReg(incr).addReg(dest)).addReg(0);
4092 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
4093 addReg(dest).addReg(incr)).addReg(0);
4096 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2)
4098 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4099 .addReg(scratch).addImm(0));
4100 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4101 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
4103 BB->addSuccessor(loopMBB);
4104 BB->addSuccessor(exitMBB);
4110 MI->eraseFromParent(); // The instruction is gone now.
4116 MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
4117 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
4118 E = MBB->succ_end(); I != E; ++I)
4121 llvm_unreachable("Expecting a BB with two successors!");
4125 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4126 MachineBasicBlock *BB) const {
4127 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4128 DebugLoc dl = MI->getDebugLoc();
4129 bool isThumb2 = Subtarget->isThumb2();
4130 switch (MI->getOpcode()) {
4133 llvm_unreachable("Unexpected instr type to insert");
4135 case ARM::ATOMIC_LOAD_ADD_I8:
4136 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
4137 case ARM::ATOMIC_LOAD_ADD_I16:
4138 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
4139 case ARM::ATOMIC_LOAD_ADD_I32:
4140 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
4142 case ARM::ATOMIC_LOAD_AND_I8:
4143 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
4144 case ARM::ATOMIC_LOAD_AND_I16:
4145 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
4146 case ARM::ATOMIC_LOAD_AND_I32:
4147 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
4149 case ARM::ATOMIC_LOAD_OR_I8:
4150 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
4151 case ARM::ATOMIC_LOAD_OR_I16:
4152 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
4153 case ARM::ATOMIC_LOAD_OR_I32:
4154 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
4156 case ARM::ATOMIC_LOAD_XOR_I8:
4157 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
4158 case ARM::ATOMIC_LOAD_XOR_I16:
4159 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
4160 case ARM::ATOMIC_LOAD_XOR_I32:
4161 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
4163 case ARM::ATOMIC_LOAD_NAND_I8:
4164 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
4165 case ARM::ATOMIC_LOAD_NAND_I16:
4166 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
4167 case ARM::ATOMIC_LOAD_NAND_I32:
4168 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
4170 case ARM::ATOMIC_LOAD_SUB_I8:
4171 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
4172 case ARM::ATOMIC_LOAD_SUB_I16:
4173 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
4174 case ARM::ATOMIC_LOAD_SUB_I32:
4175 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
4177 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0);
4178 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0);
4179 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0);
4181 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1);
4182 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
4183 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
4185 case ARM::tMOVCCr_pseudo: {
4186 // To "insert" a SELECT_CC instruction, we actually have to insert the
4187 // diamond control-flow pattern. The incoming instruction knows the
4188 // destination vreg to set, the condition code register to branch on, the
4189 // true/false values to select between, and a branch opcode to use.
4190 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4191 MachineFunction::iterator It = BB;
4197 // cmpTY ccX, r1, r2
4199 // fallthrough --> copy0MBB
4200 MachineBasicBlock *thisMBB = BB;
4201 MachineFunction *F = BB->getParent();
4202 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4203 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
4204 F->insert(It, copy0MBB);
4205 F->insert(It, sinkMBB);
4207 // Transfer the remainder of BB and its successor edges to sinkMBB.
4208 sinkMBB->splice(sinkMBB->begin(), BB,
4209 llvm::next(MachineBasicBlock::iterator(MI)),
4211 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
4213 BB->addSuccessor(copy0MBB);
4214 BB->addSuccessor(sinkMBB);
4216 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
4217 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
4220 // %FalseValue = ...
4221 // # fallthrough to sinkMBB
4224 // Update machine-CFG edges
4225 BB->addSuccessor(sinkMBB);
4228 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
4231 BuildMI(*BB, BB->begin(), dl,
4232 TII->get(ARM::PHI), MI->getOperand(0).getReg())
4233 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
4234 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
4236 MI->eraseFromParent(); // The pseudo instruction is gone now.
4241 case ARM::BCCZi64: {
4242 // Compare both parts that make up the double comparison separately for
4244 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
4246 unsigned LHS1 = MI->getOperand(1).getReg();
4247 unsigned LHS2 = MI->getOperand(2).getReg();
4249 AddDefaultPred(BuildMI(BB, dl,
4250 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4251 .addReg(LHS1).addImm(0));
4252 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4253 .addReg(LHS2).addImm(0)
4254 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
4256 unsigned RHS1 = MI->getOperand(3).getReg();
4257 unsigned RHS2 = MI->getOperand(4).getReg();
4258 AddDefaultPred(BuildMI(BB, dl,
4259 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
4260 .addReg(LHS1).addReg(RHS1));
4261 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
4262 .addReg(LHS2).addReg(RHS2)
4263 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
4266 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB();
4267 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
4268 if (MI->getOperand(0).getImm() == ARMCC::NE)
4269 std::swap(destMBB, exitMBB);
4271 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4272 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
4273 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2B : ARM::B))
4276 MI->eraseFromParent(); // The pseudo instruction is gone now.
4282 //===----------------------------------------------------------------------===//
4283 // ARM Optimization Hooks
4284 //===----------------------------------------------------------------------===//
4287 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
4288 TargetLowering::DAGCombinerInfo &DCI) {
4289 SelectionDAG &DAG = DCI.DAG;
4290 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4291 EVT VT = N->getValueType(0);
4292 unsigned Opc = N->getOpcode();
4293 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
4294 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
4295 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
4296 ISD::CondCode CC = ISD::SETCC_INVALID;
4299 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
4301 SDValue CCOp = Slct.getOperand(0);
4302 if (CCOp.getOpcode() == ISD::SETCC)
4303 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
4306 bool DoXform = false;
4308 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
4311 if (LHS.getOpcode() == ISD::Constant &&
4312 cast<ConstantSDNode>(LHS)->isNullValue()) {
4314 } else if (CC != ISD::SETCC_INVALID &&
4315 RHS.getOpcode() == ISD::Constant &&
4316 cast<ConstantSDNode>(RHS)->isNullValue()) {
4317 std::swap(LHS, RHS);
4318 SDValue Op0 = Slct.getOperand(0);
4319 EVT OpVT = isSlctCC ? Op0.getValueType() :
4320 Op0.getOperand(0).getValueType();
4321 bool isInt = OpVT.isInteger();
4322 CC = ISD::getSetCCInverse(CC, isInt);
4324 if (!TLI.isCondCodeLegal(CC, OpVT))
4325 return SDValue(); // Inverse operator isn't legal.
4332 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
4334 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
4335 Slct.getOperand(0), Slct.getOperand(1), CC);
4336 SDValue CCOp = Slct.getOperand(0);
4338 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
4339 CCOp.getOperand(0), CCOp.getOperand(1), CC);
4340 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
4341 CCOp, OtherOp, Result);
4346 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
4347 /// operands N0 and N1. This is a helper for PerformADDCombine that is
4348 /// called with the default operands, and if that fails, with commuted
4350 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
4351 TargetLowering::DAGCombinerInfo &DCI) {
4352 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
4353 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
4354 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
4355 if (Result.getNode()) return Result;
4360 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
4362 static SDValue PerformADDCombine(SDNode *N,
4363 TargetLowering::DAGCombinerInfo &DCI) {
4364 SDValue N0 = N->getOperand(0);
4365 SDValue N1 = N->getOperand(1);
4367 // First try with the default operand order.
4368 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI);
4369 if (Result.getNode())
4372 // If that didn't work, try again with the operands commuted.
4373 return PerformADDCombineWithOperands(N, N1, N0, DCI);
4376 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
4378 static SDValue PerformSUBCombine(SDNode *N,
4379 TargetLowering::DAGCombinerInfo &DCI) {
4380 SDValue N0 = N->getOperand(0);
4381 SDValue N1 = N->getOperand(1);
4383 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
4384 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
4385 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
4386 if (Result.getNode()) return Result;
4392 static SDValue PerformMULCombine(SDNode *N,
4393 TargetLowering::DAGCombinerInfo &DCI,
4394 const ARMSubtarget *Subtarget) {
4395 SelectionDAG &DAG = DCI.DAG;
4397 if (Subtarget->isThumb1Only())
4400 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
4403 EVT VT = N->getValueType(0);
4407 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
4411 uint64_t MulAmt = C->getZExtValue();
4412 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt);
4413 ShiftAmt = ShiftAmt & (32 - 1);
4414 SDValue V = N->getOperand(0);
4415 DebugLoc DL = N->getDebugLoc();
4418 MulAmt >>= ShiftAmt;
4419 if (isPowerOf2_32(MulAmt - 1)) {
4420 // (mul x, 2^N + 1) => (add (shl x, N), x)
4421 Res = DAG.getNode(ISD::ADD, DL, VT,
4422 V, DAG.getNode(ISD::SHL, DL, VT,
4423 V, DAG.getConstant(Log2_32(MulAmt-1),
4425 } else if (isPowerOf2_32(MulAmt + 1)) {
4426 // (mul x, 2^N - 1) => (sub (shl x, N), x)
4427 Res = DAG.getNode(ISD::SUB, DL, VT,
4428 DAG.getNode(ISD::SHL, DL, VT,
4429 V, DAG.getConstant(Log2_32(MulAmt+1),
4436 Res = DAG.getNode(ISD::SHL, DL, VT, Res,
4437 DAG.getConstant(ShiftAmt, MVT::i32));
4439 // Do not add new nodes to DAG combiner worklist.
4440 DCI.CombineTo(N, Res, false);
4444 /// PerformORCombine - Target-specific dag combine xforms for ISD::OR
4445 static SDValue PerformORCombine(SDNode *N,
4446 TargetLowering::DAGCombinerInfo &DCI,
4447 const ARMSubtarget *Subtarget) {
4448 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when
4451 // BFI is only available on V6T2+
4452 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops())
4455 SelectionDAG &DAG = DCI.DAG;
4456 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
4457 DebugLoc DL = N->getDebugLoc();
4458 // 1) or (and A, mask), val => ARMbfi A, val, mask
4459 // iff (val & mask) == val
4461 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
4462 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2)
4463 // && CountPopulation_32(mask) == CountPopulation_32(~mask2)
4464 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2)
4465 // && CountPopulation_32(mask) == CountPopulation_32(~mask2)
4466 // (i.e., copy a bitfield value into another bitfield of the same width)
4467 if (N0.getOpcode() != ISD::AND)
4470 EVT VT = N->getValueType(0);
4475 // The value and the mask need to be constants so we can verify this is
4476 // actually a bitfield set. If the mask is 0xffff, we can do better
4477 // via a movt instruction, so don't use BFI in that case.
4478 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
4481 unsigned Mask = C->getZExtValue();
4485 // Case (1): or (and A, mask), val => ARMbfi A, val, mask
4486 if ((C = dyn_cast<ConstantSDNode>(N1))) {
4487 unsigned Val = C->getZExtValue();
4488 if (!ARM::isBitFieldInvertedMask(Mask) || (Val & ~Mask) != Val)
4490 Val >>= CountTrailingZeros_32(~Mask);
4492 Res = DAG.getNode(ARMISD::BFI, DL, VT, N0.getOperand(0),
4493 DAG.getConstant(Val, MVT::i32),
4494 DAG.getConstant(Mask, MVT::i32));
4496 // Do not add new nodes to DAG combiner worklist.
4497 DCI.CombineTo(N, Res, false);
4498 } else if (N1.getOpcode() == ISD::AND) {
4499 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
4500 C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
4503 unsigned Mask2 = C->getZExtValue();
4505 if (ARM::isBitFieldInvertedMask(Mask) &&
4506 ARM::isBitFieldInvertedMask(~Mask2) &&
4507 (CountPopulation_32(Mask) == CountPopulation_32(~Mask2))) {
4508 // The pack halfword instruction works better for masks that fit it,
4509 // so use that when it's available.
4510 if (Subtarget->hasT2ExtractPack() &&
4511 (Mask == 0xffff || Mask == 0xffff0000))
4514 unsigned lsb = CountTrailingZeros_32(Mask2);
4515 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
4516 DAG.getConstant(lsb, MVT::i32));
4517 Res = DAG.getNode(ARMISD::BFI, DL, VT, N0.getOperand(0), Res,
4518 DAG.getConstant(Mask, MVT::i32));
4519 // Do not add new nodes to DAG combiner worklist.
4520 DCI.CombineTo(N, Res, false);
4521 } else if (ARM::isBitFieldInvertedMask(~Mask) &&
4522 ARM::isBitFieldInvertedMask(Mask2) &&
4523 (CountPopulation_32(~Mask) == CountPopulation_32(Mask2))) {
4524 // The pack halfword instruction works better for masks that fit it,
4525 // so use that when it's available.
4526 if (Subtarget->hasT2ExtractPack() &&
4527 (Mask2 == 0xffff || Mask2 == 0xffff0000))
4530 unsigned lsb = CountTrailingZeros_32(Mask);
4531 Res = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0),
4532 DAG.getConstant(lsb, MVT::i32));
4533 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
4534 DAG.getConstant(Mask2, MVT::i32));
4535 // Do not add new nodes to DAG combiner worklist.
4536 DCI.CombineTo(N, Res, false);
4543 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
4544 /// ARMISD::VMOVRRD.
4545 static SDValue PerformVMOVRRDCombine(SDNode *N,
4546 TargetLowering::DAGCombinerInfo &DCI) {
4547 // vmovrrd(vmovdrr x, y) -> x,y
4548 SDValue InDouble = N->getOperand(0);
4549 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
4550 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
4554 /// PerformVMOVDRRCombine - Target-specific dag combine xforms for
4555 /// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands.
4556 static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) {
4557 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X)
4558 SDValue Op0 = N->getOperand(0);
4559 SDValue Op1 = N->getOperand(1);
4560 if (Op0.getOpcode() == ISD::BIT_CONVERT)
4561 Op0 = Op0.getOperand(0);
4562 if (Op1.getOpcode() == ISD::BIT_CONVERT)
4563 Op1 = Op1.getOperand(0);
4564 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
4565 Op0.getNode() == Op1.getNode() &&
4566 Op0.getResNo() == 0 && Op1.getResNo() == 1)
4567 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
4568 N->getValueType(0), Op0.getOperand(0));
4572 /// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for
4573 /// ISD::BUILD_VECTOR.
4574 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG) {
4575 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X):
4576 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value
4577 // into a pair of GPRs, which is fine when the value is used as a scalar,
4578 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD.
4579 if (N->getNumOperands() == 2)
4580 return PerformVMOVDRRCombine(N, DAG);
4585 /// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for
4586 /// ISD::VECTOR_SHUFFLE.
4587 static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) {
4588 // The LLVM shufflevector instruction does not require the shuffle mask
4589 // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does
4590 // have that requirement. When translating to ISD::VECTOR_SHUFFLE, if the
4591 // operands do not match the mask length, they are extended by concatenating
4592 // them with undef vectors. That is probably the right thing for other
4593 // targets, but for NEON it is better to concatenate two double-register
4594 // size vector operands into a single quad-register size vector. Do that
4595 // transformation here:
4596 // shuffle(concat(v1, undef), concat(v2, undef)) ->
4597 // shuffle(concat(v1, v2), undef)
4598 SDValue Op0 = N->getOperand(0);
4599 SDValue Op1 = N->getOperand(1);
4600 if (Op0.getOpcode() != ISD::CONCAT_VECTORS ||
4601 Op1.getOpcode() != ISD::CONCAT_VECTORS ||
4602 Op0.getNumOperands() != 2 ||
4603 Op1.getNumOperands() != 2)
4605 SDValue Concat0Op1 = Op0.getOperand(1);
4606 SDValue Concat1Op1 = Op1.getOperand(1);
4607 if (Concat0Op1.getOpcode() != ISD::UNDEF ||
4608 Concat1Op1.getOpcode() != ISD::UNDEF)
4610 // Skip the transformation if any of the types are illegal.
4611 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4612 EVT VT = N->getValueType(0);
4613 if (!TLI.isTypeLegal(VT) ||
4614 !TLI.isTypeLegal(Concat0Op1.getValueType()) ||
4615 !TLI.isTypeLegal(Concat1Op1.getValueType()))
4618 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT,
4619 Op0.getOperand(0), Op1.getOperand(0));
4620 // Translate the shuffle mask.
4621 SmallVector<int, 16> NewMask;
4622 unsigned NumElts = VT.getVectorNumElements();
4623 unsigned HalfElts = NumElts/2;
4624 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
4625 for (unsigned n = 0; n < NumElts; ++n) {
4626 int MaskElt = SVN->getMaskElt(n);
4628 if (MaskElt < (int)HalfElts)
4630 else if (MaskElt >= (int)NumElts && MaskElt < (int)(NumElts + HalfElts))
4631 NewElt = HalfElts + MaskElt - NumElts;
4632 NewMask.push_back(NewElt);
4634 return DAG.getVectorShuffle(VT, N->getDebugLoc(), NewConcat,
4635 DAG.getUNDEF(VT), NewMask.data());
4638 /// PerformVDUPLANECombine - Target-specific dag combine xforms for
4639 /// ARMISD::VDUPLANE.
4640 static SDValue PerformVDUPLANECombine(SDNode *N, SelectionDAG &DAG) {
4641 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
4643 SDValue Op = N->getOperand(0);
4644 EVT VT = N->getValueType(0);
4646 // Ignore bit_converts.
4647 while (Op.getOpcode() == ISD::BIT_CONVERT)
4648 Op = Op.getOperand(0);
4649 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
4652 // Make sure the VMOV element size is not bigger than the VDUPLANE elements.
4653 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits();
4654 // The canonical VMOV for a zero vector uses a 32-bit element size.
4655 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4657 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
4659 if (EltSize > VT.getVectorElementType().getSizeInBits())
4662 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
4665 /// getVShiftImm - Check if this is a valid build_vector for the immediate
4666 /// operand of a vector shift operation, where all the elements of the
4667 /// build_vector must have the same constant integer value.
4668 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
4669 // Ignore bit_converts.
4670 while (Op.getOpcode() == ISD::BIT_CONVERT)
4671 Op = Op.getOperand(0);
4672 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
4673 APInt SplatBits, SplatUndef;
4674 unsigned SplatBitSize;
4676 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
4677 HasAnyUndefs, ElementBits) ||
4678 SplatBitSize > ElementBits)
4680 Cnt = SplatBits.getSExtValue();
4684 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
4685 /// operand of a vector shift left operation. That value must be in the range:
4686 /// 0 <= Value < ElementBits for a left shift; or
4687 /// 0 <= Value <= ElementBits for a long left shift.
4688 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
4689 assert(VT.isVector() && "vector shift count is not a vector type");
4690 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
4691 if (! getVShiftImm(Op, ElementBits, Cnt))
4693 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
4696 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
4697 /// operand of a vector shift right operation. For a shift opcode, the value
4698 /// is positive, but for an intrinsic the value count must be negative. The
4699 /// absolute value must be in the range:
4700 /// 1 <= |Value| <= ElementBits for a right shift; or
4701 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
4702 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
4704 assert(VT.isVector() && "vector shift count is not a vector type");
4705 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
4706 if (! getVShiftImm(Op, ElementBits, Cnt))
4710 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
4713 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
4714 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
4715 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
4718 // Don't do anything for most intrinsics.
4721 // Vector shifts: check for immediate versions and lower them.
4722 // Note: This is done during DAG combining instead of DAG legalizing because
4723 // the build_vectors for 64-bit vector element shift counts are generally
4724 // not legal, and it is hard to see their values after they get legalized to
4725 // loads from a constant pool.
4726 case Intrinsic::arm_neon_vshifts:
4727 case Intrinsic::arm_neon_vshiftu:
4728 case Intrinsic::arm_neon_vshiftls:
4729 case Intrinsic::arm_neon_vshiftlu:
4730 case Intrinsic::arm_neon_vshiftn:
4731 case Intrinsic::arm_neon_vrshifts:
4732 case Intrinsic::arm_neon_vrshiftu:
4733 case Intrinsic::arm_neon_vrshiftn:
4734 case Intrinsic::arm_neon_vqshifts:
4735 case Intrinsic::arm_neon_vqshiftu:
4736 case Intrinsic::arm_neon_vqshiftsu:
4737 case Intrinsic::arm_neon_vqshiftns:
4738 case Intrinsic::arm_neon_vqshiftnu:
4739 case Intrinsic::arm_neon_vqshiftnsu:
4740 case Intrinsic::arm_neon_vqrshiftns:
4741 case Intrinsic::arm_neon_vqrshiftnu:
4742 case Intrinsic::arm_neon_vqrshiftnsu: {
4743 EVT VT = N->getOperand(1).getValueType();
4745 unsigned VShiftOpc = 0;
4748 case Intrinsic::arm_neon_vshifts:
4749 case Intrinsic::arm_neon_vshiftu:
4750 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
4751 VShiftOpc = ARMISD::VSHL;
4754 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
4755 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
4756 ARMISD::VSHRs : ARMISD::VSHRu);
4761 case Intrinsic::arm_neon_vshiftls:
4762 case Intrinsic::arm_neon_vshiftlu:
4763 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
4765 llvm_unreachable("invalid shift count for vshll intrinsic");
4767 case Intrinsic::arm_neon_vrshifts:
4768 case Intrinsic::arm_neon_vrshiftu:
4769 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
4773 case Intrinsic::arm_neon_vqshifts:
4774 case Intrinsic::arm_neon_vqshiftu:
4775 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
4779 case Intrinsic::arm_neon_vqshiftsu:
4780 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
4782 llvm_unreachable("invalid shift count for vqshlu intrinsic");
4784 case Intrinsic::arm_neon_vshiftn:
4785 case Intrinsic::arm_neon_vrshiftn:
4786 case Intrinsic::arm_neon_vqshiftns:
4787 case Intrinsic::arm_neon_vqshiftnu:
4788 case Intrinsic::arm_neon_vqshiftnsu:
4789 case Intrinsic::arm_neon_vqrshiftns:
4790 case Intrinsic::arm_neon_vqrshiftnu:
4791 case Intrinsic::arm_neon_vqrshiftnsu:
4792 // Narrowing shifts require an immediate right shift.
4793 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
4795 llvm_unreachable("invalid shift count for narrowing vector shift "
4799 llvm_unreachable("unhandled vector shift");
4803 case Intrinsic::arm_neon_vshifts:
4804 case Intrinsic::arm_neon_vshiftu:
4805 // Opcode already set above.
4807 case Intrinsic::arm_neon_vshiftls:
4808 case Intrinsic::arm_neon_vshiftlu:
4809 if (Cnt == VT.getVectorElementType().getSizeInBits())
4810 VShiftOpc = ARMISD::VSHLLi;
4812 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
4813 ARMISD::VSHLLs : ARMISD::VSHLLu);
4815 case Intrinsic::arm_neon_vshiftn:
4816 VShiftOpc = ARMISD::VSHRN; break;
4817 case Intrinsic::arm_neon_vrshifts:
4818 VShiftOpc = ARMISD::VRSHRs; break;
4819 case Intrinsic::arm_neon_vrshiftu:
4820 VShiftOpc = ARMISD::VRSHRu; break;
4821 case Intrinsic::arm_neon_vrshiftn:
4822 VShiftOpc = ARMISD::VRSHRN; break;
4823 case Intrinsic::arm_neon_vqshifts:
4824 VShiftOpc = ARMISD::VQSHLs; break;
4825 case Intrinsic::arm_neon_vqshiftu:
4826 VShiftOpc = ARMISD::VQSHLu; break;
4827 case Intrinsic::arm_neon_vqshiftsu:
4828 VShiftOpc = ARMISD::VQSHLsu; break;
4829 case Intrinsic::arm_neon_vqshiftns:
4830 VShiftOpc = ARMISD::VQSHRNs; break;
4831 case Intrinsic::arm_neon_vqshiftnu:
4832 VShiftOpc = ARMISD::VQSHRNu; break;
4833 case Intrinsic::arm_neon_vqshiftnsu:
4834 VShiftOpc = ARMISD::VQSHRNsu; break;
4835 case Intrinsic::arm_neon_vqrshiftns:
4836 VShiftOpc = ARMISD::VQRSHRNs; break;
4837 case Intrinsic::arm_neon_vqrshiftnu:
4838 VShiftOpc = ARMISD::VQRSHRNu; break;
4839 case Intrinsic::arm_neon_vqrshiftnsu:
4840 VShiftOpc = ARMISD::VQRSHRNsu; break;
4843 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
4844 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
4847 case Intrinsic::arm_neon_vshiftins: {
4848 EVT VT = N->getOperand(1).getValueType();
4850 unsigned VShiftOpc = 0;
4852 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
4853 VShiftOpc = ARMISD::VSLI;
4854 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
4855 VShiftOpc = ARMISD::VSRI;
4857 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
4860 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
4861 N->getOperand(1), N->getOperand(2),
4862 DAG.getConstant(Cnt, MVT::i32));
4865 case Intrinsic::arm_neon_vqrshifts:
4866 case Intrinsic::arm_neon_vqrshiftu:
4867 // No immediate versions of these to check for.
4874 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
4875 /// lowers them. As with the vector shift intrinsics, this is done during DAG
4876 /// combining instead of DAG legalizing because the build_vectors for 64-bit
4877 /// vector element shift counts are generally not legal, and it is hard to see
4878 /// their values after they get legalized to loads from a constant pool.
4879 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
4880 const ARMSubtarget *ST) {
4881 EVT VT = N->getValueType(0);
4883 // Nothing to be done for scalar shifts.
4884 if (! VT.isVector())
4887 assert(ST->hasNEON() && "unexpected vector shift");
4890 switch (N->getOpcode()) {
4891 default: llvm_unreachable("unexpected shift opcode");
4894 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
4895 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
4896 DAG.getConstant(Cnt, MVT::i32));
4901 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
4902 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
4903 ARMISD::VSHRs : ARMISD::VSHRu);
4904 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
4905 DAG.getConstant(Cnt, MVT::i32));
4911 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
4912 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
4913 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
4914 const ARMSubtarget *ST) {
4915 SDValue N0 = N->getOperand(0);
4917 // Check for sign- and zero-extensions of vector extract operations of 8-
4918 // and 16-bit vector elements. NEON supports these directly. They are
4919 // handled during DAG combining because type legalization will promote them
4920 // to 32-bit types and it is messy to recognize the operations after that.
4921 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
4922 SDValue Vec = N0.getOperand(0);
4923 SDValue Lane = N0.getOperand(1);
4924 EVT VT = N->getValueType(0);
4925 EVT EltVT = N0.getValueType();
4926 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4928 if (VT == MVT::i32 &&
4929 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
4930 TLI.isTypeLegal(Vec.getValueType()) &&
4931 isa<ConstantSDNode>(Lane)) {
4934 switch (N->getOpcode()) {
4935 default: llvm_unreachable("unexpected opcode");
4936 case ISD::SIGN_EXTEND:
4937 Opc = ARMISD::VGETLANEs;
4939 case ISD::ZERO_EXTEND:
4940 case ISD::ANY_EXTEND:
4941 Opc = ARMISD::VGETLANEu;
4944 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
4951 /// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
4952 /// to match f32 max/min patterns to use NEON vmax/vmin instructions.
4953 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
4954 const ARMSubtarget *ST) {
4955 // If the target supports NEON, try to use vmax/vmin instructions for f32
4956 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set,
4957 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
4958 // a NaN; only do the transformation when it matches that behavior.
4960 // For now only do this when using NEON for FP operations; if using VFP, it
4961 // is not obvious that the benefit outweighs the cost of switching to the
4963 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
4964 N->getValueType(0) != MVT::f32)
4967 SDValue CondLHS = N->getOperand(0);
4968 SDValue CondRHS = N->getOperand(1);
4969 SDValue LHS = N->getOperand(2);
4970 SDValue RHS = N->getOperand(3);
4971 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
4973 unsigned Opcode = 0;
4975 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
4976 IsReversed = false; // x CC y ? x : y
4977 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
4978 IsReversed = true ; // x CC y ? y : x
4992 // If LHS is NaN, an ordered comparison will be false and the result will
4993 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
4994 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
4995 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
4996 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
4998 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
4999 // will return -0, so vmin can only be used for unsafe math or if one of
5000 // the operands is known to be nonzero.
5001 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
5003 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
5005 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
5014 // If LHS is NaN, an ordered comparison will be false and the result will
5015 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
5016 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
5017 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
5018 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
5020 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
5021 // will return +0, so vmax can only be used for unsafe math or if one of
5022 // the operands is known to be nonzero.
5023 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
5025 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
5027 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
5033 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS);
5036 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
5037 DAGCombinerInfo &DCI) const {
5038 switch (N->getOpcode()) {
5040 case ISD::ADD: return PerformADDCombine(N, DCI);
5041 case ISD::SUB: return PerformSUBCombine(N, DCI);
5042 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
5043 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
5044 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
5045 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
5046 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI.DAG);
5047 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
5048 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI.DAG);
5049 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
5052 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
5053 case ISD::SIGN_EXTEND:
5054 case ISD::ZERO_EXTEND:
5055 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
5056 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
5061 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
5062 if (!Subtarget->allowsUnalignedMem())
5065 switch (VT.getSimpleVT().SimpleTy) {
5072 // FIXME: VLD1 etc with standard alignment is legal.
5076 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
5081 switch (VT.getSimpleVT().SimpleTy) {
5082 default: return false;
5097 if ((V & (Scale - 1)) != 0)
5100 return V == (V & ((1LL << 5) - 1));
5103 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
5104 const ARMSubtarget *Subtarget) {
5111 switch (VT.getSimpleVT().SimpleTy) {
5112 default: return false;
5117 // + imm12 or - imm8
5119 return V == (V & ((1LL << 8) - 1));
5120 return V == (V & ((1LL << 12) - 1));
5123 // Same as ARM mode. FIXME: NEON?
5124 if (!Subtarget->hasVFP2())
5129 return V == (V & ((1LL << 8) - 1));
5133 /// isLegalAddressImmediate - Return true if the integer value can be used
5134 /// as the offset of the target addressing mode for load / store of the
5136 static bool isLegalAddressImmediate(int64_t V, EVT VT,
5137 const ARMSubtarget *Subtarget) {
5144 if (Subtarget->isThumb1Only())
5145 return isLegalT1AddressImmediate(V, VT);
5146 else if (Subtarget->isThumb2())
5147 return isLegalT2AddressImmediate(V, VT, Subtarget);
5152 switch (VT.getSimpleVT().SimpleTy) {
5153 default: return false;
5158 return V == (V & ((1LL << 12) - 1));
5161 return V == (V & ((1LL << 8) - 1));
5164 if (!Subtarget->hasVFP2()) // FIXME: NEON?
5169 return V == (V & ((1LL << 8) - 1));
5173 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
5175 int Scale = AM.Scale;
5179 switch (VT.getSimpleVT().SimpleTy) {
5180 default: return false;
5189 return Scale == 2 || Scale == 4 || Scale == 8;
5192 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
5196 // Note, we allow "void" uses (basically, uses that aren't loads or
5197 // stores), because arm allows folding a scale into many arithmetic
5198 // operations. This should be made more precise and revisited later.
5200 // Allow r << imm, but the imm has to be a multiple of two.
5201 if (Scale & 1) return false;
5202 return isPowerOf2_32(Scale);
5206 /// isLegalAddressingMode - Return true if the addressing mode represented
5207 /// by AM is legal for this target, for a load/store of the specified type.
5208 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
5209 const Type *Ty) const {
5210 EVT VT = getValueType(Ty, true);
5211 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
5214 // Can never fold addr of global into load/store.
5219 case 0: // no scale reg, must be "r+i" or "r", or "i".
5222 if (Subtarget->isThumb1Only())
5226 // ARM doesn't support any R+R*scale+imm addr modes.
5233 if (Subtarget->isThumb2())
5234 return isLegalT2ScaledAddressingMode(AM, VT);
5236 int Scale = AM.Scale;
5237 switch (VT.getSimpleVT().SimpleTy) {
5238 default: return false;
5242 if (Scale < 0) Scale = -Scale;
5246 return isPowerOf2_32(Scale & ~1);
5250 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
5255 // Note, we allow "void" uses (basically, uses that aren't loads or
5256 // stores), because arm allows folding a scale into many arithmetic
5257 // operations. This should be made more precise and revisited later.
5259 // Allow r << imm, but the imm has to be a multiple of two.
5260 if (Scale & 1) return false;
5261 return isPowerOf2_32(Scale);
5268 /// isLegalICmpImmediate - Return true if the specified immediate is legal
5269 /// icmp immediate, that is the target has icmp instructions which can compare
5270 /// a register against the immediate without having to materialize the
5271 /// immediate into a register.
5272 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
5273 if (!Subtarget->isThumb())
5274 return ARM_AM::getSOImmVal(Imm) != -1;
5275 if (Subtarget->isThumb2())
5276 return ARM_AM::getT2SOImmVal(Imm) != -1;
5277 return Imm >= 0 && Imm <= 255;
5280 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
5281 bool isSEXTLoad, SDValue &Base,
5282 SDValue &Offset, bool &isInc,
5283 SelectionDAG &DAG) {
5284 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
5287 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
5289 Base = Ptr->getOperand(0);
5290 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
5291 int RHSC = (int)RHS->getZExtValue();
5292 if (RHSC < 0 && RHSC > -256) {
5293 assert(Ptr->getOpcode() == ISD::ADD);
5295 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
5299 isInc = (Ptr->getOpcode() == ISD::ADD);
5300 Offset = Ptr->getOperand(1);
5302 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
5304 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
5305 int RHSC = (int)RHS->getZExtValue();
5306 if (RHSC < 0 && RHSC > -0x1000) {
5307 assert(Ptr->getOpcode() == ISD::ADD);
5309 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
5310 Base = Ptr->getOperand(0);
5315 if (Ptr->getOpcode() == ISD::ADD) {
5317 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
5318 if (ShOpcVal != ARM_AM::no_shift) {
5319 Base = Ptr->getOperand(1);
5320 Offset = Ptr->getOperand(0);
5322 Base = Ptr->getOperand(0);
5323 Offset = Ptr->getOperand(1);
5328 isInc = (Ptr->getOpcode() == ISD::ADD);
5329 Base = Ptr->getOperand(0);
5330 Offset = Ptr->getOperand(1);
5334 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
5338 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
5339 bool isSEXTLoad, SDValue &Base,
5340 SDValue &Offset, bool &isInc,
5341 SelectionDAG &DAG) {
5342 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
5345 Base = Ptr->getOperand(0);
5346 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
5347 int RHSC = (int)RHS->getZExtValue();
5348 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
5349 assert(Ptr->getOpcode() == ISD::ADD);
5351 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
5353 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
5354 isInc = Ptr->getOpcode() == ISD::ADD;
5355 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
5363 /// getPreIndexedAddressParts - returns true by value, base pointer and
5364 /// offset pointer and addressing mode by reference if the node's address
5365 /// can be legally represented as pre-indexed load / store address.
5367 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
5369 ISD::MemIndexedMode &AM,
5370 SelectionDAG &DAG) const {
5371 if (Subtarget->isThumb1Only())
5376 bool isSEXTLoad = false;
5377 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5378 Ptr = LD->getBasePtr();
5379 VT = LD->getMemoryVT();
5380 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
5381 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5382 Ptr = ST->getBasePtr();
5383 VT = ST->getMemoryVT();
5388 bool isLegal = false;
5389 if (Subtarget->isThumb2())
5390 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
5391 Offset, isInc, DAG);
5393 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
5394 Offset, isInc, DAG);
5398 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
5402 /// getPostIndexedAddressParts - returns true by value, base pointer and
5403 /// offset pointer and addressing mode by reference if this node can be
5404 /// combined with a load / store to form a post-indexed load / store.
5405 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
5408 ISD::MemIndexedMode &AM,
5409 SelectionDAG &DAG) const {
5410 if (Subtarget->isThumb1Only())
5415 bool isSEXTLoad = false;
5416 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5417 VT = LD->getMemoryVT();
5418 Ptr = LD->getBasePtr();
5419 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
5420 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5421 VT = ST->getMemoryVT();
5422 Ptr = ST->getBasePtr();
5427 bool isLegal = false;
5428 if (Subtarget->isThumb2())
5429 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
5432 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
5438 // Swap base ptr and offset to catch more post-index load / store when
5439 // it's legal. In Thumb2 mode, offset must be an immediate.
5440 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
5441 !Subtarget->isThumb2())
5442 std::swap(Base, Offset);
5444 // Post-indexed load / store update the base pointer.
5449 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
5453 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
5457 const SelectionDAG &DAG,
5458 unsigned Depth) const {
5459 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
5460 switch (Op.getOpcode()) {
5462 case ARMISD::CMOV: {
5463 // Bits are known zero/one if known on the LHS and RHS.
5464 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
5465 if (KnownZero == 0 && KnownOne == 0) return;
5467 APInt KnownZeroRHS, KnownOneRHS;
5468 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
5469 KnownZeroRHS, KnownOneRHS, Depth+1);
5470 KnownZero &= KnownZeroRHS;
5471 KnownOne &= KnownOneRHS;
5477 //===----------------------------------------------------------------------===//
5478 // ARM Inline Assembly Support
5479 //===----------------------------------------------------------------------===//
5481 /// getConstraintType - Given a constraint letter, return the type of
5482 /// constraint it is for this target.
5483 ARMTargetLowering::ConstraintType
5484 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
5485 if (Constraint.size() == 1) {
5486 switch (Constraint[0]) {
5488 case 'l': return C_RegisterClass;
5489 case 'w': return C_RegisterClass;
5492 return TargetLowering::getConstraintType(Constraint);
5495 /// Examine constraint type and operand type and determine a weight value.
5496 /// This object must already have been set up with the operand type
5497 /// and the current alternative constraint selected.
5498 TargetLowering::ConstraintWeight
5499 ARMTargetLowering::getSingleConstraintMatchWeight(
5500 AsmOperandInfo &info, const char *constraint) const {
5501 ConstraintWeight weight = CW_Invalid;
5502 Value *CallOperandVal = info.CallOperandVal;
5503 // If we don't have a value, we can't do a match,
5504 // but allow it at the lowest weight.
5505 if (CallOperandVal == NULL)
5507 const Type *type = CallOperandVal->getType();
5508 // Look at the constraint type.
5509 switch (*constraint) {
5511 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
5514 if (type->isIntegerTy()) {
5515 if (Subtarget->isThumb())
5516 weight = CW_SpecificReg;
5518 weight = CW_Register;
5522 if (type->isFloatingPointTy())
5523 weight = CW_Register;
5529 std::pair<unsigned, const TargetRegisterClass*>
5530 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
5532 if (Constraint.size() == 1) {
5533 // GCC ARM Constraint Letters
5534 switch (Constraint[0]) {
5536 if (Subtarget->isThumb())
5537 return std::make_pair(0U, ARM::tGPRRegisterClass);
5539 return std::make_pair(0U, ARM::GPRRegisterClass);
5541 return std::make_pair(0U, ARM::GPRRegisterClass);
5544 return std::make_pair(0U, ARM::SPRRegisterClass);
5545 if (VT.getSizeInBits() == 64)
5546 return std::make_pair(0U, ARM::DPRRegisterClass);
5547 if (VT.getSizeInBits() == 128)
5548 return std::make_pair(0U, ARM::QPRRegisterClass);
5552 if (StringRef("{cc}").equals_lower(Constraint))
5553 return std::make_pair(unsigned(ARM::CPSR), ARM::CCRRegisterClass);
5555 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
5558 std::vector<unsigned> ARMTargetLowering::
5559 getRegClassForInlineAsmConstraint(const std::string &Constraint,
5561 if (Constraint.size() != 1)
5562 return std::vector<unsigned>();
5564 switch (Constraint[0]) { // GCC ARM Constraint Letters
5567 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
5568 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
5571 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
5572 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
5573 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
5574 ARM::R12, ARM::LR, 0);
5577 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
5578 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
5579 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
5580 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
5581 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
5582 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
5583 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
5584 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
5585 if (VT.getSizeInBits() == 64)
5586 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
5587 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
5588 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
5589 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
5590 if (VT.getSizeInBits() == 128)
5591 return make_vector<unsigned>(ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
5592 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 0);
5596 return std::vector<unsigned>();
5599 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
5600 /// vector. If it is invalid, don't add anything to Ops.
5601 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
5603 std::vector<SDValue>&Ops,
5604 SelectionDAG &DAG) const {
5605 SDValue Result(0, 0);
5607 switch (Constraint) {
5609 case 'I': case 'J': case 'K': case 'L':
5610 case 'M': case 'N': case 'O':
5611 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
5615 int64_t CVal64 = C->getSExtValue();
5616 int CVal = (int) CVal64;
5617 // None of these constraints allow values larger than 32 bits. Check
5618 // that the value fits in an int.
5622 switch (Constraint) {
5624 if (Subtarget->isThumb1Only()) {
5625 // This must be a constant between 0 and 255, for ADD
5627 if (CVal >= 0 && CVal <= 255)
5629 } else if (Subtarget->isThumb2()) {
5630 // A constant that can be used as an immediate value in a
5631 // data-processing instruction.
5632 if (ARM_AM::getT2SOImmVal(CVal) != -1)
5635 // A constant that can be used as an immediate value in a
5636 // data-processing instruction.
5637 if (ARM_AM::getSOImmVal(CVal) != -1)
5643 if (Subtarget->isThumb()) { // FIXME thumb2
5644 // This must be a constant between -255 and -1, for negated ADD
5645 // immediates. This can be used in GCC with an "n" modifier that
5646 // prints the negated value, for use with SUB instructions. It is
5647 // not useful otherwise but is implemented for compatibility.
5648 if (CVal >= -255 && CVal <= -1)
5651 // This must be a constant between -4095 and 4095. It is not clear
5652 // what this constraint is intended for. Implemented for
5653 // compatibility with GCC.
5654 if (CVal >= -4095 && CVal <= 4095)
5660 if (Subtarget->isThumb1Only()) {
5661 // A 32-bit value where only one byte has a nonzero value. Exclude
5662 // zero to match GCC. This constraint is used by GCC internally for
5663 // constants that can be loaded with a move/shift combination.
5664 // It is not useful otherwise but is implemented for compatibility.
5665 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
5667 } else if (Subtarget->isThumb2()) {
5668 // A constant whose bitwise inverse can be used as an immediate
5669 // value in a data-processing instruction. This can be used in GCC
5670 // with a "B" modifier that prints the inverted value, for use with
5671 // BIC and MVN instructions. It is not useful otherwise but is
5672 // implemented for compatibility.
5673 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
5676 // A constant whose bitwise inverse can be used as an immediate
5677 // value in a data-processing instruction. This can be used in GCC
5678 // with a "B" modifier that prints the inverted value, for use with
5679 // BIC and MVN instructions. It is not useful otherwise but is
5680 // implemented for compatibility.
5681 if (ARM_AM::getSOImmVal(~CVal) != -1)
5687 if (Subtarget->isThumb1Only()) {
5688 // This must be a constant between -7 and 7,
5689 // for 3-operand ADD/SUB immediate instructions.
5690 if (CVal >= -7 && CVal < 7)
5692 } else if (Subtarget->isThumb2()) {
5693 // A constant whose negation can be used as an immediate value in a
5694 // data-processing instruction. This can be used in GCC with an "n"
5695 // modifier that prints the negated value, for use with SUB
5696 // instructions. It is not useful otherwise but is implemented for
5698 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
5701 // A constant whose negation can be used as an immediate value in a
5702 // data-processing instruction. This can be used in GCC with an "n"
5703 // modifier that prints the negated value, for use with SUB
5704 // instructions. It is not useful otherwise but is implemented for
5706 if (ARM_AM::getSOImmVal(-CVal) != -1)
5712 if (Subtarget->isThumb()) { // FIXME thumb2
5713 // This must be a multiple of 4 between 0 and 1020, for
5714 // ADD sp + immediate.
5715 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
5718 // A power of two or a constant between 0 and 32. This is used in
5719 // GCC for the shift amount on shifted register operands, but it is
5720 // useful in general for any shift amounts.
5721 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
5727 if (Subtarget->isThumb()) { // FIXME thumb2
5728 // This must be a constant between 0 and 31, for shift amounts.
5729 if (CVal >= 0 && CVal <= 31)
5735 if (Subtarget->isThumb()) { // FIXME thumb2
5736 // This must be a multiple of 4 between -508 and 508, for
5737 // ADD/SUB sp = sp + immediate.
5738 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
5743 Result = DAG.getTargetConstant(CVal, Op.getValueType());
5747 if (Result.getNode()) {
5748 Ops.push_back(Result);
5751 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
5755 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
5756 // The ARM target isn't yet aware of offsets.
5760 int ARM::getVFPf32Imm(const APFloat &FPImm) {
5761 APInt Imm = FPImm.bitcastToAPInt();
5762 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
5763 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127
5764 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits
5766 // We can handle 4 bits of mantissa.
5767 // mantissa = (16+UInt(e:f:g:h))/16.
5768 if (Mantissa & 0x7ffff)
5771 if ((Mantissa & 0xf) != Mantissa)
5774 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
5775 if (Exp < -3 || Exp > 4)
5777 Exp = ((Exp+3) & 0x7) ^ 4;
5779 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
5782 int ARM::getVFPf64Imm(const APFloat &FPImm) {
5783 APInt Imm = FPImm.bitcastToAPInt();
5784 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
5785 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
5786 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffLL;
5788 // We can handle 4 bits of mantissa.
5789 // mantissa = (16+UInt(e:f:g:h))/16.
5790 if (Mantissa & 0xffffffffffffLL)
5793 if ((Mantissa & 0xf) != Mantissa)
5796 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
5797 if (Exp < -3 || Exp > 4)
5799 Exp = ((Exp+3) & 0x7) ^ 4;
5801 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
5804 bool ARM::isBitFieldInvertedMask(unsigned v) {
5805 if (v == 0xffffffff)
5807 // there can be 1's on either or both "outsides", all the "inside"
5809 unsigned int lsb = 0, msb = 31;
5810 while (v & (1 << msb)) --msb;
5811 while (v & (1 << lsb)) ++lsb;
5812 for (unsigned int i = lsb; i <= msb; ++i) {
5819 /// isFPImmLegal - Returns true if the target can instruction select the
5820 /// specified FP immediate natively. If false, the legalizer will
5821 /// materialize the FP immediate as a load from a constant pool.
5822 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
5823 if (!Subtarget->hasVFP3())
5826 return ARM::getVFPf32Imm(Imm) != -1;
5828 return ARM::getVFPf64Imm(Imm) != -1;
5832 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
5833 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
5834 /// specified in the intrinsic calls.
5835 bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
5837 unsigned Intrinsic) const {
5838 switch (Intrinsic) {
5839 case Intrinsic::arm_neon_vld1:
5840 case Intrinsic::arm_neon_vld2:
5841 case Intrinsic::arm_neon_vld3:
5842 case Intrinsic::arm_neon_vld4:
5843 case Intrinsic::arm_neon_vld2lane:
5844 case Intrinsic::arm_neon_vld3lane:
5845 case Intrinsic::arm_neon_vld4lane: {
5846 Info.opc = ISD::INTRINSIC_W_CHAIN;
5847 // Conservatively set memVT to the entire set of vectors loaded.
5848 uint64_t NumElts = getTargetData()->getTypeAllocSize(I.getType()) / 8;
5849 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
5850 Info.ptrVal = I.getArgOperand(0);
5852 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
5853 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
5854 Info.vol = false; // volatile loads with NEON intrinsics not supported
5855 Info.readMem = true;
5856 Info.writeMem = false;
5859 case Intrinsic::arm_neon_vst1:
5860 case Intrinsic::arm_neon_vst2:
5861 case Intrinsic::arm_neon_vst3:
5862 case Intrinsic::arm_neon_vst4:
5863 case Intrinsic::arm_neon_vst2lane:
5864 case Intrinsic::arm_neon_vst3lane:
5865 case Intrinsic::arm_neon_vst4lane: {
5866 Info.opc = ISD::INTRINSIC_VOID;
5867 // Conservatively set memVT to the entire set of vectors stored.
5868 unsigned NumElts = 0;
5869 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
5870 const Type *ArgTy = I.getArgOperand(ArgI)->getType();
5871 if (!ArgTy->isVectorTy())
5873 NumElts += getTargetData()->getTypeAllocSize(ArgTy) / 8;
5875 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
5876 Info.ptrVal = I.getArgOperand(0);
5878 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
5879 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
5880 Info.vol = false; // volatile stores with NEON intrinsics not supported
5881 Info.readMem = false;
5882 Info.writeMem = true;