1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "ARMAddressingModes.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMISelLowering.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMRegisterInfo.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/Constants.h"
25 #include "llvm/Instruction.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/GlobalValue.h"
28 #include "llvm/CodeGen/MachineBasicBlock.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/SelectionDAG.h"
34 #include "llvm/Target/TargetOptions.h"
35 #include "llvm/ADT/VectorExtras.h"
36 #include "llvm/Support/MathExtras.h"
39 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
40 : TargetLowering(TM), ARMPCLabelIndex(0) {
41 Subtarget = &TM.getSubtarget<ARMSubtarget>();
43 if (Subtarget->isTargetDarwin()) {
45 setLibcallName(RTLIB::UINTTOFP_I64_F32, NULL);
46 setLibcallName(RTLIB::UINTTOFP_I64_F64, NULL);
48 // Uses VFP for Thumb libfuncs if available.
49 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
50 // Single-precision floating-point arithmetic.
51 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
52 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
53 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
54 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
56 // Double-precision floating-point arithmetic.
57 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
58 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
59 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
60 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
62 // Single-precision comparisons.
63 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
64 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
65 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
66 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
67 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
68 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
69 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
70 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
72 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
73 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
74 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
75 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
76 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
77 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
78 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
79 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
81 // Double-precision comparisons.
82 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
83 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
84 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
85 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
86 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
87 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
88 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
89 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
91 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
92 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
93 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
94 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
95 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
96 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
97 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
98 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
100 // Floating-point to integer conversions.
101 // i64 conversions are done via library routines even when generating VFP
102 // instructions, so use the same ones.
103 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
104 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
105 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
106 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
108 // Conversions between floating types.
109 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
110 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
112 // Integer to floating-point conversions.
113 // i64 conversions are done via library routines even when generating VFP
114 // instructions, so use the same ones.
115 // FIXME: There appears to be some naming inconsistency in ARM libgcc: e.g.
116 // __floatunsidf vs. __floatunssidfvfp.
117 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
118 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
119 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
120 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
124 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
125 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) {
126 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
127 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
129 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
131 computeRegisterProperties();
133 // ARM does not have f32 extending load.
134 setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
136 // ARM does not have i1 sign extending load.
137 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
139 // ARM supports all 4 flavors of integer indexed load / store.
140 for (unsigned im = (unsigned)ISD::PRE_INC;
141 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
142 setIndexedLoadAction(im, MVT::i1, Legal);
143 setIndexedLoadAction(im, MVT::i8, Legal);
144 setIndexedLoadAction(im, MVT::i16, Legal);
145 setIndexedLoadAction(im, MVT::i32, Legal);
146 setIndexedStoreAction(im, MVT::i1, Legal);
147 setIndexedStoreAction(im, MVT::i8, Legal);
148 setIndexedStoreAction(im, MVT::i16, Legal);
149 setIndexedStoreAction(im, MVT::i32, Legal);
152 // i64 operation support.
153 if (Subtarget->isThumb()) {
154 setOperationAction(ISD::MUL, MVT::i64, Expand);
155 setOperationAction(ISD::MULHU, MVT::i32, Expand);
156 setOperationAction(ISD::MULHS, MVT::i32, Expand);
157 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
158 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
160 setOperationAction(ISD::MUL, MVT::i64, Expand);
161 setOperationAction(ISD::MULHU, MVT::i32, Expand);
162 if (!Subtarget->hasV6Ops())
163 setOperationAction(ISD::MULHS, MVT::i32, Expand);
165 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
166 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
167 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
168 setOperationAction(ISD::SRL, MVT::i64, Custom);
169 setOperationAction(ISD::SRA, MVT::i64, Custom);
171 // ARM does not have ROTL.
172 setOperationAction(ISD::ROTL, MVT::i32, Expand);
173 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
174 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
175 if (!Subtarget->hasV5TOps() || Subtarget->isThumb())
176 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
178 // Only ARMv6 has BSWAP.
179 if (!Subtarget->hasV6Ops())
180 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
182 // These are expanded into libcalls.
183 setOperationAction(ISD::SDIV, MVT::i32, Expand);
184 setOperationAction(ISD::UDIV, MVT::i32, Expand);
185 setOperationAction(ISD::SREM, MVT::i32, Expand);
186 setOperationAction(ISD::UREM, MVT::i32, Expand);
187 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
188 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
190 // Support label based line numbers.
191 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
192 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
194 setOperationAction(ISD::RET, MVT::Other, Custom);
195 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
196 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
197 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
198 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
200 // Expand mem operations genericly.
201 setOperationAction(ISD::MEMSET , MVT::Other, Expand);
202 setOperationAction(ISD::MEMCPY , MVT::Other, Custom);
203 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
205 // Use the default implementation.
206 setOperationAction(ISD::VASTART , MVT::Other, Custom);
207 setOperationAction(ISD::VAARG , MVT::Other, Expand);
208 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
209 setOperationAction(ISD::VAEND , MVT::Other, Expand);
210 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
211 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
212 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
213 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
214 setOperationAction(ISD::PREFETCH , MVT::Other, Expand);
216 if (!Subtarget->hasV6Ops()) {
217 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
218 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
220 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
222 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb())
223 // Turn f64->i64 into FMRRD iff target supports vfp2.
224 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
226 // We want to custom lower some of our intrinsics.
227 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
229 setOperationAction(ISD::SETCC , MVT::i32, Expand);
230 setOperationAction(ISD::SETCC , MVT::f32, Expand);
231 setOperationAction(ISD::SETCC , MVT::f64, Expand);
232 setOperationAction(ISD::SELECT , MVT::i32, Expand);
233 setOperationAction(ISD::SELECT , MVT::f32, Expand);
234 setOperationAction(ISD::SELECT , MVT::f64, Expand);
235 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
236 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
237 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
239 setOperationAction(ISD::BRCOND , MVT::Other, Expand);
240 setOperationAction(ISD::BR_CC , MVT::i32, Custom);
241 setOperationAction(ISD::BR_CC , MVT::f32, Custom);
242 setOperationAction(ISD::BR_CC , MVT::f64, Custom);
243 setOperationAction(ISD::BR_JT , MVT::Other, Custom);
245 // We don't support sin/cos/fmod/copysign/pow
246 setOperationAction(ISD::FSIN , MVT::f64, Expand);
247 setOperationAction(ISD::FSIN , MVT::f32, Expand);
248 setOperationAction(ISD::FCOS , MVT::f32, Expand);
249 setOperationAction(ISD::FCOS , MVT::f64, Expand);
250 setOperationAction(ISD::FREM , MVT::f64, Expand);
251 setOperationAction(ISD::FREM , MVT::f32, Expand);
252 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
253 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
254 setOperationAction(ISD::FPOW , MVT::f64, Expand);
255 setOperationAction(ISD::FPOW , MVT::f32, Expand);
257 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
258 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
259 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
260 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
261 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
263 // We have target-specific dag combine patterns for the following nodes:
264 // ARMISD::FMRRD - No need to call setTargetDAGCombine
266 setStackPointerRegisterToSaveRestore(ARM::SP);
267 setSchedulingPreference(SchedulingForRegPressure);
268 setIfCvtBlockSizeLimit(Subtarget->isThumb() ? 0 : 10);
269 setIfCvtDupBlockSizeLimit(Subtarget->isThumb() ? 0 : 2);
271 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
275 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
278 case ARMISD::Wrapper: return "ARMISD::Wrapper";
279 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
280 case ARMISD::CALL: return "ARMISD::CALL";
281 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
282 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
283 case ARMISD::tCALL: return "ARMISD::tCALL";
284 case ARMISD::BRCOND: return "ARMISD::BRCOND";
285 case ARMISD::BR_JT: return "ARMISD::BR_JT";
286 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
287 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
288 case ARMISD::CMP: return "ARMISD::CMP";
289 case ARMISD::CMPNZ: return "ARMISD::CMPNZ";
290 case ARMISD::CMPFP: return "ARMISD::CMPFP";
291 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
292 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
293 case ARMISD::CMOV: return "ARMISD::CMOV";
294 case ARMISD::CNEG: return "ARMISD::CNEG";
296 case ARMISD::FTOSI: return "ARMISD::FTOSI";
297 case ARMISD::FTOUI: return "ARMISD::FTOUI";
298 case ARMISD::SITOF: return "ARMISD::SITOF";
299 case ARMISD::UITOF: return "ARMISD::UITOF";
301 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
302 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
303 case ARMISD::RRX: return "ARMISD::RRX";
305 case ARMISD::FMRRD: return "ARMISD::FMRRD";
306 case ARMISD::FMDRR: return "ARMISD::FMDRR";
308 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
312 //===----------------------------------------------------------------------===//
314 //===----------------------------------------------------------------------===//
317 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
318 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
320 default: assert(0 && "Unknown condition code!");
321 case ISD::SETNE: return ARMCC::NE;
322 case ISD::SETEQ: return ARMCC::EQ;
323 case ISD::SETGT: return ARMCC::GT;
324 case ISD::SETGE: return ARMCC::GE;
325 case ISD::SETLT: return ARMCC::LT;
326 case ISD::SETLE: return ARMCC::LE;
327 case ISD::SETUGT: return ARMCC::HI;
328 case ISD::SETUGE: return ARMCC::HS;
329 case ISD::SETULT: return ARMCC::LO;
330 case ISD::SETULE: return ARMCC::LS;
334 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. It
335 /// returns true if the operands should be inverted to form the proper
337 static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
338 ARMCC::CondCodes &CondCode2) {
340 CondCode2 = ARMCC::AL;
342 default: assert(0 && "Unknown FP condition!");
344 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
346 case ISD::SETOGT: CondCode = ARMCC::GT; break;
348 case ISD::SETOGE: CondCode = ARMCC::GE; break;
349 case ISD::SETOLT: CondCode = ARMCC::MI; break;
350 case ISD::SETOLE: CondCode = ARMCC::GT; Invert = true; break;
351 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
352 case ISD::SETO: CondCode = ARMCC::VC; break;
353 case ISD::SETUO: CondCode = ARMCC::VS; break;
354 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
355 case ISD::SETUGT: CondCode = ARMCC::HI; break;
356 case ISD::SETUGE: CondCode = ARMCC::PL; break;
358 case ISD::SETULT: CondCode = ARMCC::LT; break;
360 case ISD::SETULE: CondCode = ARMCC::LE; break;
362 case ISD::SETUNE: CondCode = ARMCC::NE; break;
368 HowToPassArgument(MVT::ValueType ObjectVT, unsigned NumGPRs,
369 unsigned StackOffset, unsigned &NeededGPRs,
370 unsigned &NeededStackSize, unsigned &GPRPad,
371 unsigned &StackPad, unsigned Flags) {
376 unsigned align = (Flags >> ISD::ParamFlags::OrigAlignmentOffs);
377 GPRPad = NumGPRs % ((align + 3)/4);
378 StackPad = StackOffset % align;
379 unsigned firstGPR = NumGPRs + GPRPad;
381 default: assert(0 && "Unhandled argument type!");
393 else if (firstGPR == 3) {
401 /// LowerCALL - Lowering a ISD::CALL node into a callseq_start <-
402 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
404 SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
405 MVT::ValueType RetVT= Op.Val->getValueType(0);
406 SDOperand Chain = Op.getOperand(0);
407 unsigned CallConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
408 assert((CallConv == CallingConv::C ||
409 CallConv == CallingConv::Fast) && "unknown calling convention");
410 SDOperand Callee = Op.getOperand(4);
411 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
412 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
413 unsigned NumGPRs = 0; // GPRs used for parameter passing.
415 // Count how many bytes are to be pushed on the stack.
416 unsigned NumBytes = 0;
418 // Add up all the space actually used.
419 for (unsigned i = 0; i < NumOps; ++i) {
424 MVT::ValueType ObjectVT = Op.getOperand(5+2*i).getValueType();
425 unsigned Flags = Op.getConstantOperandVal(5+2*i+1);
426 HowToPassArgument(ObjectVT, NumGPRs, NumBytes, ObjGPRs, ObjSize,
427 GPRPad, StackPad, Flags);
428 NumBytes += ObjSize + StackPad;
429 NumGPRs += ObjGPRs + GPRPad;
432 // Adjust the stack pointer for the new arguments...
433 // These operations are automatically eliminated by the prolog/epilog pass
434 Chain = DAG.getCALLSEQ_START(Chain,
435 DAG.getConstant(NumBytes, MVT::i32));
437 SDOperand StackPtr = DAG.getRegister(ARM::SP, MVT::i32);
439 static const unsigned GPRArgRegs[] = {
440 ARM::R0, ARM::R1, ARM::R2, ARM::R3
444 std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
445 std::vector<SDOperand> MemOpChains;
446 for (unsigned i = 0; i != NumOps; ++i) {
447 SDOperand Arg = Op.getOperand(5+2*i);
448 unsigned Flags = Op.getConstantOperandVal(5+2*i+1);
449 MVT::ValueType ArgVT = Arg.getValueType();
455 HowToPassArgument(ArgVT, NumGPRs, ArgOffset, ObjGPRs,
456 ObjSize, GPRPad, StackPad, Flags);
458 ArgOffset += StackPad;
461 default: assert(0 && "Unexpected ValueType for argument!");
463 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Arg));
466 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs],
467 DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Arg)));
470 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg,
471 DAG.getConstant(0, getPointerTy()));
472 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg,
473 DAG.getConstant(1, getPointerTy()));
474 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Lo));
476 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1], Hi));
478 SDOperand PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType());
479 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
480 MemOpChains.push_back(DAG.getStore(Chain, Hi, PtrOff, NULL, 0));
485 SDOperand Cvt = DAG.getNode(ARMISD::FMRRD,
486 DAG.getVTList(MVT::i32, MVT::i32),
488 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Cvt));
490 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1],
493 SDOperand PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType());
494 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
495 MemOpChains.push_back(DAG.getStore(Chain, Cvt.getValue(1), PtrOff,
502 assert(ObjSize != 0);
503 SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
504 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
505 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
509 ArgOffset += ObjSize;
512 if (!MemOpChains.empty())
513 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
514 &MemOpChains[0], MemOpChains.size());
516 // Build a sequence of copy-to-reg nodes chained together with token chain
517 // and flag operands which copy the outgoing args into the appropriate regs.
519 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
520 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
522 InFlag = Chain.getValue(1);
525 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
526 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
527 // node so that legalize doesn't hack it.
528 bool isDirect = false;
529 bool isARMFunc = false;
530 bool isLocalARMFunc = false;
531 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
532 GlobalValue *GV = G->getGlobal();
534 bool isExt = (GV->isDeclaration() || GV->hasWeakLinkage() ||
535 GV->hasLinkOnceLinkage());
536 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
537 getTargetMachine().getRelocationModel() != Reloc::Static;
538 isARMFunc = !Subtarget->isThumb() || isStub;
539 // ARM call to a local ARM function is predicable.
540 isLocalARMFunc = !Subtarget->isThumb() && !isExt;
541 // tBX takes a register source operand.
542 if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) {
543 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
545 SDOperand CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2);
546 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
547 Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0);
548 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
549 Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel);
551 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy());
552 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
554 bool isStub = Subtarget->isTargetDarwin() &&
555 getTargetMachine().getRelocationModel() != Reloc::Static;
556 isARMFunc = !Subtarget->isThumb() || isStub;
557 // tBX takes a register source operand.
558 const char *Sym = S->getSymbol();
559 if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) {
560 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(Sym, ARMPCLabelIndex,
562 SDOperand CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2);
563 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
564 Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0);
565 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
566 Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel);
568 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
571 // FIXME: handle tail calls differently.
573 if (Subtarget->isThumb()) {
574 if (!Subtarget->hasV5TOps() && (!isDirect || isARMFunc))
575 CallOpc = ARMISD::CALL_NOLINK;
577 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
579 CallOpc = (isDirect || Subtarget->hasV5TOps())
580 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
581 : ARMISD::CALL_NOLINK;
583 if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb()) {
584 // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK
585 Chain = DAG.getCopyToReg(Chain, ARM::LR,
586 DAG.getNode(ISD::UNDEF, MVT::i32), InFlag);
587 InFlag = Chain.getValue(1);
590 std::vector<MVT::ValueType> NodeTys;
591 NodeTys.push_back(MVT::Other); // Returns a chain
592 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
594 std::vector<SDOperand> Ops;
595 Ops.push_back(Chain);
596 Ops.push_back(Callee);
598 // Add argument registers to the end of the list so that they are known live
600 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
601 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
602 RegsToPass[i].second.getValueType()));
605 Ops.push_back(InFlag);
606 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
607 InFlag = Chain.getValue(1);
609 Chain = DAG.getCALLSEQ_END(Chain,
610 DAG.getConstant(NumBytes, MVT::i32),
611 DAG.getConstant(0, MVT::i32),
613 if (RetVT != MVT::Other)
614 InFlag = Chain.getValue(1);
616 std::vector<SDOperand> ResultVals;
619 // If the call has results, copy the values out of the ret val registers.
621 default: assert(0 && "Unexpected ret value!");
625 Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1);
626 ResultVals.push_back(Chain.getValue(0));
627 if (Op.Val->getValueType(1) == MVT::i32) {
628 // Returns a i64 value.
629 Chain = DAG.getCopyFromReg(Chain, ARM::R1, MVT::i32,
630 Chain.getValue(2)).getValue(1);
631 ResultVals.push_back(Chain.getValue(0));
632 NodeTys.push_back(MVT::i32);
634 NodeTys.push_back(MVT::i32);
637 Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1);
638 ResultVals.push_back(DAG.getNode(ISD::BIT_CONVERT, MVT::f32,
640 NodeTys.push_back(MVT::f32);
643 SDOperand Lo = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag);
644 SDOperand Hi = DAG.getCopyFromReg(Lo, ARM::R1, MVT::i32, Lo.getValue(2));
645 ResultVals.push_back(DAG.getNode(ARMISD::FMDRR, MVT::f64, Lo, Hi));
646 NodeTys.push_back(MVT::f64);
651 NodeTys.push_back(MVT::Other);
653 if (ResultVals.empty())
656 ResultVals.push_back(Chain);
657 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, &ResultVals[0],
659 return Res.getValue(Op.ResNo);
662 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
664 SDOperand Chain = Op.getOperand(0);
665 switch(Op.getNumOperands()) {
667 assert(0 && "Do not know how to return this many arguments!");
670 SDOperand LR = DAG.getRegister(ARM::LR, MVT::i32);
671 return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Chain);
674 Op = Op.getOperand(1);
675 if (Op.getValueType() == MVT::f32) {
676 Op = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
677 } else if (Op.getValueType() == MVT::f64) {
678 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
680 Op = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32), &Op,1);
681 SDOperand Sign = DAG.getConstant(0, MVT::i32);
682 return DAG.getNode(ISD::RET, MVT::Other, Chain, Op, Sign,
683 Op.getValue(1), Sign);
685 Copy = DAG.getCopyToReg(Chain, ARM::R0, Op, SDOperand());
686 if (DAG.getMachineFunction().getRegInfo().liveout_empty())
687 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0);
690 Copy = DAG.getCopyToReg(Chain, ARM::R1, Op.getOperand(3), SDOperand());
691 Copy = DAG.getCopyToReg(Copy, ARM::R0, Op.getOperand(1), Copy.getValue(1));
692 // If we haven't noted the R0+R1 are live out, do so now.
693 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
694 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0);
695 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R1);
700 //We must use RET_FLAG instead of BRIND because BRIND doesn't have a flag
701 return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
704 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
705 // their target countpart wrapped in the ARMISD::Wrapper node. Suppose N is
706 // one of the above mentioned nodes. It has to be wrapped because otherwise
707 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
708 // be used to form addressing mode. These wrapped nodes will be selected
710 static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
711 MVT::ValueType PtrVT = Op.getValueType();
712 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
714 if (CP->isMachineConstantPoolEntry())
715 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
718 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
720 return DAG.getNode(ARMISD::Wrapper, MVT::i32, Res);
723 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
725 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
727 MVT::ValueType PtrVT = getPointerTy();
728 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
729 ARMConstantPoolValue *CPV =
730 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
731 PCAdj, "tlsgd", true);
732 SDOperand Argument = DAG.getTargetConstantPool(CPV, PtrVT, 2);
733 Argument = DAG.getNode(ARMISD::Wrapper, MVT::i32, Argument);
734 Argument = DAG.getLoad(PtrVT, DAG.getEntryNode(), Argument, NULL, 0);
735 SDOperand Chain = Argument.getValue(1);
737 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
738 Argument = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Argument, PICLabel);
740 // call __tls_get_addr.
743 Entry.Node = Argument;
744 Entry.Ty = (const Type *) Type::Int32Ty;
745 Args.push_back(Entry);
746 std::pair<SDOperand, SDOperand> CallResult =
747 LowerCallTo(Chain, (const Type *) Type::Int32Ty, false, false, false,
748 CallingConv::C, false,
749 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG);
750 return CallResult.first;
753 // Lower ISD::GlobalTLSAddress using the "initial exec" or
754 // "local exec" model.
756 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
758 GlobalValue *GV = GA->getGlobal();
760 SDOperand Chain = DAG.getEntryNode();
761 MVT::ValueType PtrVT = getPointerTy();
762 // Get the Thread Pointer
763 SDOperand ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, PtrVT);
765 if (GV->isDeclaration()){
766 // initial exec model
767 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
768 ARMConstantPoolValue *CPV =
769 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
770 PCAdj, "gottpoff", true);
771 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 2);
772 Offset = DAG.getNode(ARMISD::Wrapper, MVT::i32, Offset);
773 Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0);
774 Chain = Offset.getValue(1);
776 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
777 Offset = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Offset, PICLabel);
779 Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0);
782 ARMConstantPoolValue *CPV =
783 new ARMConstantPoolValue(GV, ARMCP::CPValue, "tpoff");
784 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 2);
785 Offset = DAG.getNode(ARMISD::Wrapper, MVT::i32, Offset);
786 Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0);
789 // The address of the thread local variable is the add of the thread
790 // pointer with the offset of the variable.
791 return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset);
795 ARMTargetLowering::LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) {
796 // TODO: implement the "local dynamic" model
797 assert(Subtarget->isTargetELF() &&
798 "TLS not implemented for non-ELF targets");
799 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
800 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
801 // otherwise use the "Local Exec" TLS Model
802 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
803 return LowerToTLSGeneralDynamicModel(GA, DAG);
805 return LowerToTLSExecModels(GA, DAG);
808 SDOperand ARMTargetLowering::LowerGlobalAddressELF(SDOperand Op,
810 MVT::ValueType PtrVT = getPointerTy();
811 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
812 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
813 if (RelocM == Reloc::PIC_) {
814 bool UseGOTOFF = GV->hasInternalLinkage() || GV->hasHiddenVisibility();
815 ARMConstantPoolValue *CPV =
816 new ARMConstantPoolValue(GV, ARMCP::CPValue, UseGOTOFF ? "GOTOFF":"GOT");
817 SDOperand CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
818 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
819 SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
820 SDOperand Chain = Result.getValue(1);
821 SDOperand GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PtrVT);
822 Result = DAG.getNode(ISD::ADD, PtrVT, Result, GOT);
824 Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0);
827 SDOperand CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2);
828 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
829 return DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
833 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol
834 /// even in non-static mode.
835 static bool GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model RelocM) {
836 return RelocM != Reloc::Static &&
837 (GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
838 (GV->isDeclaration() && !GV->hasNotBeenReadFromBitcode()));
841 SDOperand ARMTargetLowering::LowerGlobalAddressDarwin(SDOperand Op,
843 MVT::ValueType PtrVT = getPointerTy();
844 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
845 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
846 bool IsIndirect = GVIsIndirectSymbol(GV, RelocM);
848 if (RelocM == Reloc::Static)
849 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2);
851 unsigned PCAdj = (RelocM != Reloc::PIC_)
852 ? 0 : (Subtarget->isThumb() ? 4 : 8);
853 ARMCP::ARMCPKind Kind = IsIndirect ? ARMCP::CPNonLazyPtr
855 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
857 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
859 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
861 SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
862 SDOperand Chain = Result.getValue(1);
864 if (RelocM == Reloc::PIC_) {
865 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
866 Result = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel);
869 Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0);
874 SDOperand ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDOperand Op,
876 assert(Subtarget->isTargetELF() &&
877 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
878 MVT::ValueType PtrVT = getPointerTy();
879 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
880 ARMConstantPoolValue *CPV = new ARMConstantPoolValue("_GLOBAL_OFFSET_TABLE_",
882 ARMCP::CPValue, PCAdj);
883 SDOperand CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
884 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
885 SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
886 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
887 return DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel);
890 static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
891 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
892 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue();
894 default: return SDOperand(); // Don't custom lower most intrinsics.
895 case Intrinsic::arm_thread_pointer:
896 return DAG.getNode(ARMISD::THREAD_POINTER, PtrVT);
900 static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
901 unsigned VarArgsFrameIndex) {
902 // vastart just stores the address of the VarArgsFrameIndex slot into the
903 // memory location argument.
904 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
905 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
906 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
907 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0);
910 static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG,
911 unsigned ArgNo, unsigned &NumGPRs,
912 unsigned &ArgOffset) {
913 MachineFunction &MF = DAG.getMachineFunction();
914 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
915 SDOperand Root = Op.getOperand(0);
916 std::vector<SDOperand> ArgValues;
917 MachineRegisterInfo &RegInfo = MF.getRegInfo();
919 static const unsigned GPRArgRegs[] = {
920 ARM::R0, ARM::R1, ARM::R2, ARM::R3
927 unsigned Flags = Op.getConstantOperandVal(ArgNo + 3);
928 HowToPassArgument(ObjectVT, NumGPRs, ArgOffset, ObjGPRs,
929 ObjSize, GPRPad, StackPad, Flags);
931 ArgOffset += StackPad;
935 unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
936 RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
937 ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32);
938 if (ObjectVT == MVT::f32)
939 ArgValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, ArgValue);
940 } else if (ObjGPRs == 2) {
941 unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
942 RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
943 ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32);
945 VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
946 RegInfo.addLiveIn(GPRArgRegs[NumGPRs+1], VReg);
947 SDOperand ArgValue2 = DAG.getCopyFromReg(Root, VReg, MVT::i32);
949 assert(ObjectVT != MVT::i64 && "i64 should already be lowered");
950 ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2);
955 MachineFrameInfo *MFI = MF.getFrameInfo();
956 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
957 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
959 ArgValue = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
961 SDOperand ArgValue2 = DAG.getLoad(MVT::i32, Root, FIN, NULL, 0);
962 assert(ObjectVT != MVT::i64 && "i64 should already be lowered");
963 ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2);
966 ArgOffset += ObjSize; // Move on to the next argument.
973 ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
974 std::vector<SDOperand> ArgValues;
975 SDOperand Root = Op.getOperand(0);
976 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
977 unsigned NumGPRs = 0; // GPRs used for parameter passing.
979 unsigned NumArgs = Op.Val->getNumValues()-1;
980 for (unsigned ArgNo = 0; ArgNo < NumArgs; ++ArgNo)
981 ArgValues.push_back(LowerFORMAL_ARGUMENT(Op, DAG, ArgNo,
982 NumGPRs, ArgOffset));
984 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
986 static const unsigned GPRArgRegs[] = {
987 ARM::R0, ARM::R1, ARM::R2, ARM::R3
990 MachineFunction &MF = DAG.getMachineFunction();
991 MachineRegisterInfo &RegInfo = MF.getRegInfo();
992 MachineFrameInfo *MFI = MF.getFrameInfo();
993 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
994 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
995 unsigned VARegSize = (4 - NumGPRs) * 4;
996 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
998 // If this function is vararg, store any remaining integer argument regs
999 // to their spots on the stack so that they may be loaded by deferencing
1000 // the result of va_next.
1001 AFI->setVarArgsRegSaveSize(VARegSaveSize);
1002 VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset +
1003 VARegSaveSize - VARegSize);
1004 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
1006 SmallVector<SDOperand, 4> MemOps;
1007 for (; NumGPRs < 4; ++NumGPRs) {
1008 unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
1009 RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
1010 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i32);
1011 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1012 MemOps.push_back(Store);
1013 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1014 DAG.getConstant(4, getPointerTy()));
1016 if (!MemOps.empty())
1017 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
1018 &MemOps[0], MemOps.size());
1020 // This will point to the next argument passed via stack.
1021 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
1024 ArgValues.push_back(Root);
1026 // Return the new list of results.
1027 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
1028 Op.Val->value_end());
1029 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
1032 /// isFloatingPointZero - Return true if this is +0.0.
1033 static bool isFloatingPointZero(SDOperand Op) {
1034 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1035 return CFP->getValueAPF().isPosZero();
1036 else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
1037 // Maybe this has already been legalized into the constant pool?
1038 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
1039 SDOperand WrapperOp = Op.getOperand(1).getOperand(0);
1040 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
1041 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1042 return CFP->getValueAPF().isPosZero();
1048 static bool isLegalCmpImmediate(unsigned C, bool isThumb) {
1049 return ( isThumb && (C & ~255U) == 0) ||
1050 (!isThumb && ARM_AM::getSOImmVal(C) != -1);
1053 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
1054 /// the given operands.
1055 static SDOperand getARMCmp(SDOperand LHS, SDOperand RHS, ISD::CondCode CC,
1056 SDOperand &ARMCC, SelectionDAG &DAG, bool isThumb) {
1057 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.Val)) {
1058 unsigned C = RHSC->getValue();
1059 if (!isLegalCmpImmediate(C, isThumb)) {
1060 // Constant does not fit, try adjusting it by one?
1065 if (isLegalCmpImmediate(C-1, isThumb)) {
1066 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1067 RHS = DAG.getConstant(C-1, MVT::i32);
1072 if (C > 0 && isLegalCmpImmediate(C-1, isThumb)) {
1073 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1074 RHS = DAG.getConstant(C-1, MVT::i32);
1079 if (isLegalCmpImmediate(C+1, isThumb)) {
1080 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1081 RHS = DAG.getConstant(C+1, MVT::i32);
1086 if (C < 0xffffffff && isLegalCmpImmediate(C+1, isThumb)) {
1087 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1088 RHS = DAG.getConstant(C+1, MVT::i32);
1095 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
1096 ARMISD::NodeType CompareType;
1099 CompareType = ARMISD::CMP;
1105 // Uses only N and Z Flags
1106 CompareType = ARMISD::CMPNZ;
1109 ARMCC = DAG.getConstant(CondCode, MVT::i32);
1110 return DAG.getNode(CompareType, MVT::Flag, LHS, RHS);
1113 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
1114 static SDOperand getVFPCmp(SDOperand LHS, SDOperand RHS, SelectionDAG &DAG) {
1116 if (!isFloatingPointZero(RHS))
1117 Cmp = DAG.getNode(ARMISD::CMPFP, MVT::Flag, LHS, RHS);
1119 Cmp = DAG.getNode(ARMISD::CMPFPw0, MVT::Flag, LHS);
1120 return DAG.getNode(ARMISD::FMSTAT, MVT::Flag, Cmp);
1123 static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG,
1124 const ARMSubtarget *ST) {
1125 MVT::ValueType VT = Op.getValueType();
1126 SDOperand LHS = Op.getOperand(0);
1127 SDOperand RHS = Op.getOperand(1);
1128 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1129 SDOperand TrueVal = Op.getOperand(2);
1130 SDOperand FalseVal = Op.getOperand(3);
1132 if (LHS.getValueType() == MVT::i32) {
1134 SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1135 SDOperand Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb());
1136 return DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal, ARMCC, CCR, Cmp);
1139 ARMCC::CondCodes CondCode, CondCode2;
1140 if (FPCCToARMCC(CC, CondCode, CondCode2))
1141 std::swap(TrueVal, FalseVal);
1143 SDOperand ARMCC = DAG.getConstant(CondCode, MVT::i32);
1144 SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1145 SDOperand Cmp = getVFPCmp(LHS, RHS, DAG);
1146 SDOperand Result = DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal,
1148 if (CondCode2 != ARMCC::AL) {
1149 SDOperand ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
1150 // FIXME: Needs another CMP because flag can have but one use.
1151 SDOperand Cmp2 = getVFPCmp(LHS, RHS, DAG);
1152 Result = DAG.getNode(ARMISD::CMOV, VT, Result, TrueVal, ARMCC2, CCR, Cmp2);
1157 static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG,
1158 const ARMSubtarget *ST) {
1159 SDOperand Chain = Op.getOperand(0);
1160 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1161 SDOperand LHS = Op.getOperand(2);
1162 SDOperand RHS = Op.getOperand(3);
1163 SDOperand Dest = Op.getOperand(4);
1165 if (LHS.getValueType() == MVT::i32) {
1167 SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1168 SDOperand Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb());
1169 return DAG.getNode(ARMISD::BRCOND, MVT::Other, Chain, Dest, ARMCC, CCR,Cmp);
1172 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
1173 ARMCC::CondCodes CondCode, CondCode2;
1174 if (FPCCToARMCC(CC, CondCode, CondCode2))
1175 // Swap the LHS/RHS of the comparison if needed.
1176 std::swap(LHS, RHS);
1178 SDOperand Cmp = getVFPCmp(LHS, RHS, DAG);
1179 SDOperand ARMCC = DAG.getConstant(CondCode, MVT::i32);
1180 SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1181 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
1182 SDOperand Ops[] = { Chain, Dest, ARMCC, CCR, Cmp };
1183 SDOperand Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5);
1184 if (CondCode2 != ARMCC::AL) {
1185 ARMCC = DAG.getConstant(CondCode2, MVT::i32);
1186 SDOperand Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) };
1187 Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5);
1192 SDOperand ARMTargetLowering::LowerBR_JT(SDOperand Op, SelectionDAG &DAG) {
1193 SDOperand Chain = Op.getOperand(0);
1194 SDOperand Table = Op.getOperand(1);
1195 SDOperand Index = Op.getOperand(2);
1197 MVT::ValueType PTy = getPointerTy();
1198 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
1199 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
1200 SDOperand UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
1201 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
1202 Table = DAG.getNode(ARMISD::WrapperJT, MVT::i32, JTI, UId);
1203 Index = DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(4, PTy));
1204 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1205 bool isPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
1206 Addr = DAG.getLoad(isPIC ? (MVT::ValueType)MVT::i32 : PTy,
1207 Chain, Addr, NULL, 0);
1208 Chain = Addr.getValue(1);
1210 Addr = DAG.getNode(ISD::ADD, PTy, Addr, Table);
1211 return DAG.getNode(ARMISD::BR_JT, MVT::Other, Chain, Addr, JTI, UId);
1214 static SDOperand LowerFP_TO_INT(SDOperand Op, SelectionDAG &DAG) {
1216 Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI;
1217 Op = DAG.getNode(Opc, MVT::f32, Op.getOperand(0));
1218 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
1221 static SDOperand LowerINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
1222 MVT::ValueType VT = Op.getValueType();
1224 Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF;
1226 Op = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
1227 return DAG.getNode(Opc, VT, Op);
1230 static SDOperand LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) {
1231 // Implement fcopysign with a fabs and a conditional fneg.
1232 SDOperand Tmp0 = Op.getOperand(0);
1233 SDOperand Tmp1 = Op.getOperand(1);
1234 MVT::ValueType VT = Op.getValueType();
1235 MVT::ValueType SrcVT = Tmp1.getValueType();
1236 SDOperand AbsVal = DAG.getNode(ISD::FABS, VT, Tmp0);
1237 SDOperand Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG);
1238 SDOperand ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
1239 SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1240 return DAG.getNode(ARMISD::CNEG, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp);
1243 SDOperand ARMTargetLowering::LowerMEMCPYInline(SDOperand Chain,
1248 SelectionDAG &DAG) {
1249 // Do repeated 4-byte loads and stores. To be improved.
1250 assert((Align & 3) == 0 && "Expected 4-byte aligned addresses!");
1251 unsigned BytesLeft = Size & 3;
1252 unsigned NumMemOps = Size >> 2;
1253 unsigned EmittedNumMemOps = 0;
1254 unsigned SrcOff = 0, DstOff = 0;
1255 MVT::ValueType VT = MVT::i32;
1256 unsigned VTSize = 4;
1258 const unsigned MAX_LOADS_IN_LDM = 6;
1259 SDOperand TFOps[MAX_LOADS_IN_LDM];
1260 SDOperand Loads[MAX_LOADS_IN_LDM];
1262 // Emit up to MAX_LOADS_IN_LDM loads, then a TokenFactor barrier, then the
1263 // same number of stores. The loads and stores will get combined into
1264 // ldm/stm later on.
1265 while (EmittedNumMemOps < NumMemOps) {
1267 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
1268 Loads[i] = DAG.getLoad(VT, Chain,
1269 DAG.getNode(ISD::ADD, MVT::i32, Source,
1270 DAG.getConstant(SrcOff, MVT::i32)),
1272 TFOps[i] = Loads[i].getValue(1);
1275 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i);
1278 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
1279 TFOps[i] = DAG.getStore(Chain, Loads[i],
1280 DAG.getNode(ISD::ADD, MVT::i32, Dest,
1281 DAG.getConstant(DstOff, MVT::i32)),
1285 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i);
1287 EmittedNumMemOps += i;
1293 // Issue loads / stores for the trailing (1 - 3) bytes.
1294 unsigned BytesLeftSave = BytesLeft;
1297 if (BytesLeft >= 2) {
1305 Loads[i] = DAG.getLoad(VT, Chain,
1306 DAG.getNode(ISD::ADD, MVT::i32, Source,
1307 DAG.getConstant(SrcOff, MVT::i32)),
1309 TFOps[i] = Loads[i].getValue(1);
1312 BytesLeft -= VTSize;
1314 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i);
1317 BytesLeft = BytesLeftSave;
1319 if (BytesLeft >= 2) {
1327 TFOps[i] = DAG.getStore(Chain, Loads[i],
1328 DAG.getNode(ISD::ADD, MVT::i32, Dest,
1329 DAG.getConstant(DstOff, MVT::i32)),
1333 BytesLeft -= VTSize;
1335 return DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i);
1338 static SDNode *ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
1339 // Turn f64->i64 into FMRRD.
1340 assert(N->getValueType(0) == MVT::i64 &&
1341 N->getOperand(0).getValueType() == MVT::f64);
1343 SDOperand Op = N->getOperand(0);
1344 SDOperand Cvt = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32),
1347 // Merge the pieces into a single i64 value.
1348 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Cvt, Cvt.getValue(1)).Val;
1351 static SDNode *ExpandSRx(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) {
1352 assert(N->getValueType(0) == MVT::i64 &&
1353 (N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
1354 "Unknown shift to lower!");
1356 // We only lower SRA, SRL of 1 here, all others use generic lowering.
1357 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
1358 cast<ConstantSDNode>(N->getOperand(1))->getValue() != 1)
1361 // If we are in thumb mode, we don't have RRX.
1362 if (ST->isThumb()) return 0;
1364 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
1365 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0),
1366 DAG.getConstant(0, MVT::i32));
1367 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0),
1368 DAG.getConstant(1, MVT::i32));
1370 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
1371 // captures the result into a carry flag.
1372 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
1373 Hi = DAG.getNode(Opc, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
1375 // The low part is an ARMISD::RRX operand, which shifts the carry in.
1376 Lo = DAG.getNode(ARMISD::RRX, MVT::i32, Lo, Hi.getValue(1));
1378 // Merge the pieces into a single i64 value.
1379 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi).Val;
1383 SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
1384 switch (Op.getOpcode()) {
1385 default: assert(0 && "Don't know how to custom lower this!"); abort();
1386 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
1387 case ISD::GlobalAddress:
1388 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
1389 LowerGlobalAddressELF(Op, DAG);
1390 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
1391 case ISD::CALL: return LowerCALL(Op, DAG);
1392 case ISD::RET: return LowerRET(Op, DAG);
1393 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, Subtarget);
1394 case ISD::BR_CC: return LowerBR_CC(Op, DAG, Subtarget);
1395 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
1396 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex);
1397 case ISD::SINT_TO_FP:
1398 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
1399 case ISD::FP_TO_SINT:
1400 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
1401 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
1402 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
1403 case ISD::RETURNADDR: break;
1404 case ISD::FRAMEADDR: break;
1405 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
1406 case ISD::MEMCPY: return LowerMEMCPY(Op, DAG);
1407 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
1410 // FIXME: Remove these when LegalizeDAGTypes lands.
1411 case ISD::BIT_CONVERT: return SDOperand(ExpandBIT_CONVERT(Op.Val, DAG), 0);
1413 case ISD::SRA: return SDOperand(ExpandSRx(Op.Val, DAG,Subtarget),0);
1419 /// ExpandOperationResult - Provide custom lowering hooks for expanding
1421 SDNode *ARMTargetLowering::ExpandOperationResult(SDNode *N, SelectionDAG &DAG) {
1422 switch (N->getOpcode()) {
1423 default: assert(0 && "Don't know how to custom expand this!"); abort();
1424 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(N, DAG);
1426 case ISD::SRA: return ExpandSRx(N, DAG, Subtarget);
1431 //===----------------------------------------------------------------------===//
1432 // ARM Scheduler Hooks
1433 //===----------------------------------------------------------------------===//
1436 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1437 MachineBasicBlock *BB) {
1438 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1439 switch (MI->getOpcode()) {
1440 default: assert(false && "Unexpected instr type to insert");
1441 case ARM::tMOVCCr: {
1442 // To "insert" a SELECT_CC instruction, we actually have to insert the
1443 // diamond control-flow pattern. The incoming instruction knows the
1444 // destination vreg to set, the condition code register to branch on, the
1445 // true/false values to select between, and a branch opcode to use.
1446 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1447 ilist<MachineBasicBlock>::iterator It = BB;
1453 // cmpTY ccX, r1, r2
1455 // fallthrough --> copy0MBB
1456 MachineBasicBlock *thisMBB = BB;
1457 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
1458 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
1459 BuildMI(BB, TII->get(ARM::tBcc)).addMBB(sinkMBB)
1460 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
1461 MachineFunction *F = BB->getParent();
1462 F->getBasicBlockList().insert(It, copy0MBB);
1463 F->getBasicBlockList().insert(It, sinkMBB);
1464 // Update machine-CFG edges by first adding all successors of the current
1465 // block to the new block which will contain the Phi node for the select.
1466 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
1467 e = BB->succ_end(); i != e; ++i)
1468 sinkMBB->addSuccessor(*i);
1469 // Next, remove all successors of the current block, and add the true
1470 // and fallthrough blocks as its successors.
1471 while(!BB->succ_empty())
1472 BB->removeSuccessor(BB->succ_begin());
1473 BB->addSuccessor(copy0MBB);
1474 BB->addSuccessor(sinkMBB);
1477 // %FalseValue = ...
1478 // # fallthrough to sinkMBB
1481 // Update machine-CFG edges
1482 BB->addSuccessor(sinkMBB);
1485 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1488 BuildMI(BB, TII->get(ARM::PHI), MI->getOperand(0).getReg())
1489 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
1490 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
1492 delete MI; // The pseudo instruction is gone now.
1498 //===----------------------------------------------------------------------===//
1499 // ARM Optimization Hooks
1500 //===----------------------------------------------------------------------===//
1502 /// PerformFMRRDCombine - Target-specific dag combine xforms for ARMISD::FMRRD.
1503 static SDOperand PerformFMRRDCombine(SDNode *N,
1504 TargetLowering::DAGCombinerInfo &DCI) {
1505 // fmrrd(fmdrr x, y) -> x,y
1506 SDOperand InDouble = N->getOperand(0);
1507 if (InDouble.getOpcode() == ARMISD::FMDRR)
1508 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
1512 SDOperand ARMTargetLowering::PerformDAGCombine(SDNode *N,
1513 DAGCombinerInfo &DCI) const {
1514 switch (N->getOpcode()) {
1516 case ARMISD::FMRRD: return PerformFMRRDCombine(N, DCI);
1523 /// isLegalAddressImmediate - Return true if the integer value can be used
1524 /// as the offset of the target addressing mode for load / store of the
1526 static bool isLegalAddressImmediate(int64_t V, MVT::ValueType VT,
1527 const ARMSubtarget *Subtarget) {
1531 if (Subtarget->isThumb()) {
1537 default: return false;
1552 if ((V & (Scale - 1)) != 0)
1555 return V == (V & ((1LL << 5) - 1));
1561 default: return false;
1566 return V == (V & ((1LL << 12) - 1));
1569 return V == (V & ((1LL << 8) - 1));
1572 if (!Subtarget->hasVFP2())
1577 return V == (V & ((1LL << 8) - 1));
1581 /// isLegalAddressingMode - Return true if the addressing mode represented
1582 /// by AM is legal for this target, for a load/store of the specified type.
1583 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
1584 const Type *Ty) const {
1585 if (!isLegalAddressImmediate(AM.BaseOffs, getValueType(Ty), Subtarget))
1588 // Can never fold addr of global into load/store.
1593 case 0: // no scale reg, must be "r+i" or "r", or "i".
1596 if (Subtarget->isThumb())
1600 // ARM doesn't support any R+R*scale+imm addr modes.
1604 int Scale = AM.Scale;
1605 switch (getValueType(Ty)) {
1606 default: return false;
1611 // This assumes i64 is legalized to a pair of i32. If not (i.e.
1612 // ldrd / strd are used, then its address mode is same as i16.
1614 if (Scale < 0) Scale = -Scale;
1618 return isPowerOf2_32(Scale & ~1);
1621 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
1626 // Note, we allow "void" uses (basically, uses that aren't loads or
1627 // stores), because arm allows folding a scale into many arithmetic
1628 // operations. This should be made more precise and revisited later.
1630 // Allow r << imm, but the imm has to be a multiple of two.
1631 if (AM.Scale & 1) return false;
1632 return isPowerOf2_32(AM.Scale);
1640 static bool getIndexedAddressParts(SDNode *Ptr, MVT::ValueType VT,
1641 bool isSEXTLoad, SDOperand &Base,
1642 SDOperand &Offset, bool &isInc,
1643 SelectionDAG &DAG) {
1644 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
1647 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
1649 Base = Ptr->getOperand(0);
1650 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
1651 int RHSC = (int)RHS->getValue();
1652 if (RHSC < 0 && RHSC > -256) {
1654 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
1658 isInc = (Ptr->getOpcode() == ISD::ADD);
1659 Offset = Ptr->getOperand(1);
1661 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
1663 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
1664 int RHSC = (int)RHS->getValue();
1665 if (RHSC < 0 && RHSC > -0x1000) {
1667 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
1668 Base = Ptr->getOperand(0);
1673 if (Ptr->getOpcode() == ISD::ADD) {
1675 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
1676 if (ShOpcVal != ARM_AM::no_shift) {
1677 Base = Ptr->getOperand(1);
1678 Offset = Ptr->getOperand(0);
1680 Base = Ptr->getOperand(0);
1681 Offset = Ptr->getOperand(1);
1686 isInc = (Ptr->getOpcode() == ISD::ADD);
1687 Base = Ptr->getOperand(0);
1688 Offset = Ptr->getOperand(1);
1692 // FIXME: Use FLDM / FSTM to emulate indexed FP load / store.
1696 /// getPreIndexedAddressParts - returns true by value, base pointer and
1697 /// offset pointer and addressing mode by reference if the node's address
1698 /// can be legally represented as pre-indexed load / store address.
1700 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
1702 ISD::MemIndexedMode &AM,
1703 SelectionDAG &DAG) {
1704 if (Subtarget->isThumb())
1709 bool isSEXTLoad = false;
1710 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1711 Ptr = LD->getBasePtr();
1712 VT = LD->getMemoryVT();
1713 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
1714 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1715 Ptr = ST->getBasePtr();
1716 VT = ST->getMemoryVT();
1721 bool isLegal = getIndexedAddressParts(Ptr.Val, VT, isSEXTLoad, Base, Offset,
1724 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
1730 /// getPostIndexedAddressParts - returns true by value, base pointer and
1731 /// offset pointer and addressing mode by reference if this node can be
1732 /// combined with a load / store to form a post-indexed load / store.
1733 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
1736 ISD::MemIndexedMode &AM,
1737 SelectionDAG &DAG) {
1738 if (Subtarget->isThumb())
1743 bool isSEXTLoad = false;
1744 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1745 VT = LD->getMemoryVT();
1746 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
1747 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1748 VT = ST->getMemoryVT();
1753 bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
1756 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
1762 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
1766 const SelectionDAG &DAG,
1767 unsigned Depth) const {
1768 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
1769 switch (Op.getOpcode()) {
1771 case ARMISD::CMOV: {
1772 // Bits are known zero/one if known on the LHS and RHS.
1773 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
1774 if (KnownZero == 0 && KnownOne == 0) return;
1776 APInt KnownZeroRHS, KnownOneRHS;
1777 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
1778 KnownZeroRHS, KnownOneRHS, Depth+1);
1779 KnownZero &= KnownZeroRHS;
1780 KnownOne &= KnownOneRHS;
1786 //===----------------------------------------------------------------------===//
1787 // ARM Inline Assembly Support
1788 //===----------------------------------------------------------------------===//
1790 /// getConstraintType - Given a constraint letter, return the type of
1791 /// constraint it is for this target.
1792 ARMTargetLowering::ConstraintType
1793 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
1794 if (Constraint.size() == 1) {
1795 switch (Constraint[0]) {
1797 case 'l': return C_RegisterClass;
1798 case 'w': return C_RegisterClass;
1801 return TargetLowering::getConstraintType(Constraint);
1804 std::pair<unsigned, const TargetRegisterClass*>
1805 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
1806 MVT::ValueType VT) const {
1807 if (Constraint.size() == 1) {
1808 // GCC RS6000 Constraint Letters
1809 switch (Constraint[0]) {
1811 // FIXME: in thumb mode, 'l' is only low-regs.
1814 return std::make_pair(0U, ARM::GPRRegisterClass);
1817 return std::make_pair(0U, ARM::SPRRegisterClass);
1819 return std::make_pair(0U, ARM::DPRRegisterClass);
1823 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1826 std::vector<unsigned> ARMTargetLowering::
1827 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1828 MVT::ValueType VT) const {
1829 if (Constraint.size() != 1)
1830 return std::vector<unsigned>();
1832 switch (Constraint[0]) { // GCC ARM Constraint Letters
1836 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1837 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1838 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1839 ARM::R12, ARM::LR, 0);
1842 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
1843 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
1844 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
1845 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
1846 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
1847 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
1848 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
1849 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
1851 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1852 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1853 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
1854 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
1858 return std::vector<unsigned>();