1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "ARMISelLowering.h"
16 #include "ARMCallingConv.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMPerfectShuffle.h"
20 #include "ARMSubtarget.h"
21 #include "ARMTargetMachine.h"
22 #include "ARMTargetObjectFile.h"
23 #include "MCTargetDesc/ARMAddressingModes.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/CodeGen/CallingConvLower.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineBasicBlock.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SelectionDAG.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalValue.h"
41 #include "llvm/IR/IRBuilder.h"
42 #include "llvm/IR/Instruction.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/IntrinsicInst.h"
45 #include "llvm/IR/Intrinsics.h"
46 #include "llvm/IR/Type.h"
47 #include "llvm/MC/MCSectionMachO.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Support/raw_ostream.h"
53 #include "llvm/Target/TargetOptions.h"
57 #define DEBUG_TYPE "arm-isel"
59 STATISTIC(NumTailCalls, "Number of tail calls");
60 STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt");
61 STATISTIC(NumLoopByVals, "Number of loops generated for byval arguments");
64 ARMInterworking("arm-interworking", cl::Hidden,
65 cl::desc("Enable / disable ARM interworking (for debugging only)"),
69 class ARMCCState : public CCState {
71 ARMCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
72 SmallVectorImpl<CCValAssign> &locs, LLVMContext &C,
74 : CCState(CC, isVarArg, MF, locs, C) {
75 assert(((PC == Call) || (PC == Prologue)) &&
76 "ARMCCState users must specify whether their context is call"
77 "or prologue generation.");
83 // The APCS parameter registers.
84 static const MCPhysReg GPRArgRegs[] = {
85 ARM::R0, ARM::R1, ARM::R2, ARM::R3
88 void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT,
89 MVT PromotedBitwiseVT) {
90 if (VT != PromotedLdStVT) {
91 setOperationAction(ISD::LOAD, VT, Promote);
92 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
94 setOperationAction(ISD::STORE, VT, Promote);
95 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
98 MVT ElemTy = VT.getVectorElementType();
99 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
100 setOperationAction(ISD::SETCC, VT, Custom);
101 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
102 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
103 if (ElemTy == MVT::i32) {
104 setOperationAction(ISD::SINT_TO_FP, VT, Custom);
105 setOperationAction(ISD::UINT_TO_FP, VT, Custom);
106 setOperationAction(ISD::FP_TO_SINT, VT, Custom);
107 setOperationAction(ISD::FP_TO_UINT, VT, Custom);
109 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
110 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
111 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
112 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
114 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
115 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
116 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
117 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
118 setOperationAction(ISD::SELECT, VT, Expand);
119 setOperationAction(ISD::SELECT_CC, VT, Expand);
120 setOperationAction(ISD::VSELECT, VT, Expand);
121 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
122 if (VT.isInteger()) {
123 setOperationAction(ISD::SHL, VT, Custom);
124 setOperationAction(ISD::SRA, VT, Custom);
125 setOperationAction(ISD::SRL, VT, Custom);
128 // Promote all bit-wise operations.
129 if (VT.isInteger() && VT != PromotedBitwiseVT) {
130 setOperationAction(ISD::AND, VT, Promote);
131 AddPromotedToType (ISD::AND, VT, PromotedBitwiseVT);
132 setOperationAction(ISD::OR, VT, Promote);
133 AddPromotedToType (ISD::OR, VT, PromotedBitwiseVT);
134 setOperationAction(ISD::XOR, VT, Promote);
135 AddPromotedToType (ISD::XOR, VT, PromotedBitwiseVT);
138 // Neon does not support vector divide/remainder operations.
139 setOperationAction(ISD::SDIV, VT, Expand);
140 setOperationAction(ISD::UDIV, VT, Expand);
141 setOperationAction(ISD::FDIV, VT, Expand);
142 setOperationAction(ISD::SREM, VT, Expand);
143 setOperationAction(ISD::UREM, VT, Expand);
144 setOperationAction(ISD::FREM, VT, Expand);
146 if (!VT.isFloatingPoint() &&
147 VT != MVT::v2i64 && VT != MVT::v1i64)
148 for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
149 setOperationAction(Opcode, VT, Legal);
152 void ARMTargetLowering::addDRTypeForNEON(MVT VT) {
153 addRegisterClass(VT, &ARM::DPRRegClass);
154 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
157 void ARMTargetLowering::addQRTypeForNEON(MVT VT) {
158 addRegisterClass(VT, &ARM::DPairRegClass);
159 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
162 ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
163 const ARMSubtarget &STI)
164 : TargetLowering(TM), Subtarget(&STI) {
165 RegInfo = Subtarget->getRegisterInfo();
166 Itins = Subtarget->getInstrItineraryData();
168 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
170 if (Subtarget->isTargetMachO()) {
171 // Uses VFP for Thumb libfuncs if available.
172 if (Subtarget->isThumb() && Subtarget->hasVFP2() &&
173 Subtarget->hasARMOps() && !Subtarget->useSoftFloat()) {
174 static const struct {
175 const RTLIB::Libcall Op;
176 const char * const Name;
177 const ISD::CondCode Cond;
179 // Single-precision floating-point arithmetic.
180 { RTLIB::ADD_F32, "__addsf3vfp", ISD::SETCC_INVALID },
181 { RTLIB::SUB_F32, "__subsf3vfp", ISD::SETCC_INVALID },
182 { RTLIB::MUL_F32, "__mulsf3vfp", ISD::SETCC_INVALID },
183 { RTLIB::DIV_F32, "__divsf3vfp", ISD::SETCC_INVALID },
185 // Double-precision floating-point arithmetic.
186 { RTLIB::ADD_F64, "__adddf3vfp", ISD::SETCC_INVALID },
187 { RTLIB::SUB_F64, "__subdf3vfp", ISD::SETCC_INVALID },
188 { RTLIB::MUL_F64, "__muldf3vfp", ISD::SETCC_INVALID },
189 { RTLIB::DIV_F64, "__divdf3vfp", ISD::SETCC_INVALID },
191 // Single-precision comparisons.
192 { RTLIB::OEQ_F32, "__eqsf2vfp", ISD::SETNE },
193 { RTLIB::UNE_F32, "__nesf2vfp", ISD::SETNE },
194 { RTLIB::OLT_F32, "__ltsf2vfp", ISD::SETNE },
195 { RTLIB::OLE_F32, "__lesf2vfp", ISD::SETNE },
196 { RTLIB::OGE_F32, "__gesf2vfp", ISD::SETNE },
197 { RTLIB::OGT_F32, "__gtsf2vfp", ISD::SETNE },
198 { RTLIB::UO_F32, "__unordsf2vfp", ISD::SETNE },
199 { RTLIB::O_F32, "__unordsf2vfp", ISD::SETEQ },
201 // Double-precision comparisons.
202 { RTLIB::OEQ_F64, "__eqdf2vfp", ISD::SETNE },
203 { RTLIB::UNE_F64, "__nedf2vfp", ISD::SETNE },
204 { RTLIB::OLT_F64, "__ltdf2vfp", ISD::SETNE },
205 { RTLIB::OLE_F64, "__ledf2vfp", ISD::SETNE },
206 { RTLIB::OGE_F64, "__gedf2vfp", ISD::SETNE },
207 { RTLIB::OGT_F64, "__gtdf2vfp", ISD::SETNE },
208 { RTLIB::UO_F64, "__unorddf2vfp", ISD::SETNE },
209 { RTLIB::O_F64, "__unorddf2vfp", ISD::SETEQ },
211 // Floating-point to integer conversions.
212 // i64 conversions are done via library routines even when generating VFP
213 // instructions, so use the same ones.
214 { RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp", ISD::SETCC_INVALID },
215 { RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp", ISD::SETCC_INVALID },
216 { RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp", ISD::SETCC_INVALID },
217 { RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp", ISD::SETCC_INVALID },
219 // Conversions between floating types.
220 { RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp", ISD::SETCC_INVALID },
221 { RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp", ISD::SETCC_INVALID },
223 // Integer to floating-point conversions.
224 // i64 conversions are done via library routines even when generating VFP
225 // instructions, so use the same ones.
226 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
227 // e.g., __floatunsidf vs. __floatunssidfvfp.
228 { RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp", ISD::SETCC_INVALID },
229 { RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp", ISD::SETCC_INVALID },
230 { RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp", ISD::SETCC_INVALID },
231 { RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp", ISD::SETCC_INVALID },
234 for (const auto &LC : LibraryCalls) {
235 setLibcallName(LC.Op, LC.Name);
236 if (LC.Cond != ISD::SETCC_INVALID)
237 setCmpLibcallCC(LC.Op, LC.Cond);
241 // Set the correct calling convention for ARMv7k WatchOS. It's just
242 // AAPCS_VFP for functions as simple as libcalls.
243 if (Subtarget->isTargetWatchOS()) {
244 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i)
245 setLibcallCallingConv((RTLIB::Libcall)i, CallingConv::ARM_AAPCS_VFP);
249 // These libcalls are not available in 32-bit.
250 setLibcallName(RTLIB::SHL_I128, nullptr);
251 setLibcallName(RTLIB::SRL_I128, nullptr);
252 setLibcallName(RTLIB::SRA_I128, nullptr);
255 if (Subtarget->isAAPCS_ABI() &&
256 (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() ||
257 Subtarget->isTargetAndroid())) {
258 static const struct {
259 const RTLIB::Libcall Op;
260 const char * const Name;
261 const CallingConv::ID CC;
262 const ISD::CondCode Cond;
264 // Double-precision floating-point arithmetic helper functions
265 // RTABI chapter 4.1.2, Table 2
266 { RTLIB::ADD_F64, "__aeabi_dadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
267 { RTLIB::DIV_F64, "__aeabi_ddiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
268 { RTLIB::MUL_F64, "__aeabi_dmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
269 { RTLIB::SUB_F64, "__aeabi_dsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
271 // Double-precision floating-point comparison helper functions
272 // RTABI chapter 4.1.2, Table 3
273 { RTLIB::OEQ_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
274 { RTLIB::UNE_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
275 { RTLIB::OLT_F64, "__aeabi_dcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
276 { RTLIB::OLE_F64, "__aeabi_dcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
277 { RTLIB::OGE_F64, "__aeabi_dcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
278 { RTLIB::OGT_F64, "__aeabi_dcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
279 { RTLIB::UO_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
280 { RTLIB::O_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ },
282 // Single-precision floating-point arithmetic helper functions
283 // RTABI chapter 4.1.2, Table 4
284 { RTLIB::ADD_F32, "__aeabi_fadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
285 { RTLIB::DIV_F32, "__aeabi_fdiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
286 { RTLIB::MUL_F32, "__aeabi_fmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
287 { RTLIB::SUB_F32, "__aeabi_fsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
289 // Single-precision floating-point comparison helper functions
290 // RTABI chapter 4.1.2, Table 5
291 { RTLIB::OEQ_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
292 { RTLIB::UNE_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
293 { RTLIB::OLT_F32, "__aeabi_fcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
294 { RTLIB::OLE_F32, "__aeabi_fcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
295 { RTLIB::OGE_F32, "__aeabi_fcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
296 { RTLIB::OGT_F32, "__aeabi_fcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
297 { RTLIB::UO_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
298 { RTLIB::O_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ },
300 // Floating-point to integer conversions.
301 // RTABI chapter 4.1.2, Table 6
302 { RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
303 { RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
304 { RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
305 { RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
306 { RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
307 { RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
308 { RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
309 { RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
311 // Conversions between floating types.
312 // RTABI chapter 4.1.2, Table 7
313 { RTLIB::FPROUND_F64_F32, "__aeabi_d2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
314 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
315 { RTLIB::FPEXT_F32_F64, "__aeabi_f2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
317 // Integer to floating-point conversions.
318 // RTABI chapter 4.1.2, Table 8
319 { RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
320 { RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
321 { RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
322 { RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
323 { RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
324 { RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
325 { RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
326 { RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
328 // Long long helper functions
329 // RTABI chapter 4.2, Table 9
330 { RTLIB::MUL_I64, "__aeabi_lmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
331 { RTLIB::SHL_I64, "__aeabi_llsl", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
332 { RTLIB::SRL_I64, "__aeabi_llsr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
333 { RTLIB::SRA_I64, "__aeabi_lasr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
335 // Integer division functions
336 // RTABI chapter 4.3.1
337 { RTLIB::SDIV_I8, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
338 { RTLIB::SDIV_I16, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
339 { RTLIB::SDIV_I32, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
340 { RTLIB::SDIV_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
341 { RTLIB::UDIV_I8, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
342 { RTLIB::UDIV_I16, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
343 { RTLIB::UDIV_I32, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
344 { RTLIB::UDIV_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
347 for (const auto &LC : LibraryCalls) {
348 setLibcallName(LC.Op, LC.Name);
349 setLibcallCallingConv(LC.Op, LC.CC);
350 if (LC.Cond != ISD::SETCC_INVALID)
351 setCmpLibcallCC(LC.Op, LC.Cond);
354 // EABI dependent RTLIB
355 if (TM.Options.EABIVersion == EABI::EABI4 ||
356 TM.Options.EABIVersion == EABI::EABI5) {
357 static const struct {
358 const RTLIB::Libcall Op;
359 const char *const Name;
360 const CallingConv::ID CC;
361 const ISD::CondCode Cond;
362 } MemOpsLibraryCalls[] = {
364 // RTABI chapter 4.3.4
365 { RTLIB::MEMCPY, "__aeabi_memcpy", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
366 { RTLIB::MEMMOVE, "__aeabi_memmove", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
367 { RTLIB::MEMSET, "__aeabi_memset", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
370 for (const auto &LC : MemOpsLibraryCalls) {
371 setLibcallName(LC.Op, LC.Name);
372 setLibcallCallingConv(LC.Op, LC.CC);
373 if (LC.Cond != ISD::SETCC_INVALID)
374 setCmpLibcallCC(LC.Op, LC.Cond);
379 if (Subtarget->isTargetWindows()) {
380 static const struct {
381 const RTLIB::Libcall Op;
382 const char * const Name;
383 const CallingConv::ID CC;
385 { RTLIB::FPTOSINT_F32_I64, "__stoi64", CallingConv::ARM_AAPCS_VFP },
386 { RTLIB::FPTOSINT_F64_I64, "__dtoi64", CallingConv::ARM_AAPCS_VFP },
387 { RTLIB::FPTOUINT_F32_I64, "__stou64", CallingConv::ARM_AAPCS_VFP },
388 { RTLIB::FPTOUINT_F64_I64, "__dtou64", CallingConv::ARM_AAPCS_VFP },
389 { RTLIB::SINTTOFP_I64_F32, "__i64tos", CallingConv::ARM_AAPCS_VFP },
390 { RTLIB::SINTTOFP_I64_F64, "__i64tod", CallingConv::ARM_AAPCS_VFP },
391 { RTLIB::UINTTOFP_I64_F32, "__u64tos", CallingConv::ARM_AAPCS_VFP },
392 { RTLIB::UINTTOFP_I64_F64, "__u64tod", CallingConv::ARM_AAPCS_VFP },
393 { RTLIB::SDIV_I32, "__rt_sdiv", CallingConv::ARM_AAPCS_VFP },
394 { RTLIB::UDIV_I32, "__rt_udiv", CallingConv::ARM_AAPCS_VFP },
395 { RTLIB::SDIV_I64, "__rt_sdiv64", CallingConv::ARM_AAPCS_VFP },
396 { RTLIB::UDIV_I64, "__rt_udiv64", CallingConv::ARM_AAPCS_VFP },
399 for (const auto &LC : LibraryCalls) {
400 setLibcallName(LC.Op, LC.Name);
401 setLibcallCallingConv(LC.Op, LC.CC);
405 // Use divmod compiler-rt calls for iOS 5.0 and later.
406 if (Subtarget->isTargetWatchOS() ||
407 (Subtarget->isTargetIOS() &&
408 !Subtarget->getTargetTriple().isOSVersionLT(5, 0))) {
409 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
410 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
413 // The half <-> float conversion functions are always soft-float, but are
414 // needed for some targets which use a hard-float calling convention by
416 if (Subtarget->isAAPCS_ABI()) {
417 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_AAPCS);
418 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_AAPCS);
419 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_AAPCS);
421 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_APCS);
422 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_APCS);
423 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_APCS);
426 // In EABI, these functions have an __aeabi_ prefix, but in GNUEABI they have
427 // a __gnu_ prefix (which is the default).
428 if (Subtarget->isTargetAEABI()) {
429 setLibcallName(RTLIB::FPROUND_F32_F16, "__aeabi_f2h");
430 setLibcallName(RTLIB::FPROUND_F64_F16, "__aeabi_d2h");
431 setLibcallName(RTLIB::FPEXT_F16_F32, "__aeabi_h2f");
434 if (Subtarget->isThumb1Only())
435 addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
437 addRegisterClass(MVT::i32, &ARM::GPRRegClass);
438 if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2() &&
439 !Subtarget->isThumb1Only()) {
440 addRegisterClass(MVT::f32, &ARM::SPRRegClass);
441 addRegisterClass(MVT::f64, &ARM::DPRRegClass);
444 for (MVT VT : MVT::vector_valuetypes()) {
445 for (MVT InnerVT : MVT::vector_valuetypes()) {
446 setTruncStoreAction(VT, InnerVT, Expand);
447 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
448 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
449 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
452 setOperationAction(ISD::MULHS, VT, Expand);
453 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
454 setOperationAction(ISD::MULHU, VT, Expand);
455 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
457 setOperationAction(ISD::BSWAP, VT, Expand);
460 setOperationAction(ISD::ConstantFP, MVT::f32, Custom);
461 setOperationAction(ISD::ConstantFP, MVT::f64, Custom);
463 setOperationAction(ISD::READ_REGISTER, MVT::i64, Custom);
464 setOperationAction(ISD::WRITE_REGISTER, MVT::i64, Custom);
466 if (Subtarget->hasNEON()) {
467 addDRTypeForNEON(MVT::v2f32);
468 addDRTypeForNEON(MVT::v8i8);
469 addDRTypeForNEON(MVT::v4i16);
470 addDRTypeForNEON(MVT::v2i32);
471 addDRTypeForNEON(MVT::v1i64);
473 addQRTypeForNEON(MVT::v4f32);
474 addQRTypeForNEON(MVT::v2f64);
475 addQRTypeForNEON(MVT::v16i8);
476 addQRTypeForNEON(MVT::v8i16);
477 addQRTypeForNEON(MVT::v4i32);
478 addQRTypeForNEON(MVT::v2i64);
480 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
481 // neither Neon nor VFP support any arithmetic operations on it.
482 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
483 // supported for v4f32.
484 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
485 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
486 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
487 // FIXME: Code duplication: FDIV and FREM are expanded always, see
488 // ARMTargetLowering::addTypeForNEON method for details.
489 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
490 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
491 // FIXME: Create unittest.
492 // In another words, find a way when "copysign" appears in DAG with vector
494 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
495 // FIXME: Code duplication: SETCC has custom operation action, see
496 // ARMTargetLowering::addTypeForNEON method for details.
497 setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
498 // FIXME: Create unittest for FNEG and for FABS.
499 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
500 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
501 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
502 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
503 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
504 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
505 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
506 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
507 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
508 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
509 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
510 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
511 // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR.
512 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
513 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
514 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
515 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
516 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
517 setOperationAction(ISD::FMA, MVT::v2f64, Expand);
519 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
520 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
521 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
522 setOperationAction(ISD::FPOWI, MVT::v4f32, Expand);
523 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
524 setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
525 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
526 setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
527 setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
528 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
529 setOperationAction(ISD::FCEIL, MVT::v4f32, Expand);
530 setOperationAction(ISD::FTRUNC, MVT::v4f32, Expand);
531 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
532 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
533 setOperationAction(ISD::FFLOOR, MVT::v4f32, Expand);
535 // Mark v2f32 intrinsics.
536 setOperationAction(ISD::FSQRT, MVT::v2f32, Expand);
537 setOperationAction(ISD::FSIN, MVT::v2f32, Expand);
538 setOperationAction(ISD::FCOS, MVT::v2f32, Expand);
539 setOperationAction(ISD::FPOWI, MVT::v2f32, Expand);
540 setOperationAction(ISD::FPOW, MVT::v2f32, Expand);
541 setOperationAction(ISD::FLOG, MVT::v2f32, Expand);
542 setOperationAction(ISD::FLOG2, MVT::v2f32, Expand);
543 setOperationAction(ISD::FLOG10, MVT::v2f32, Expand);
544 setOperationAction(ISD::FEXP, MVT::v2f32, Expand);
545 setOperationAction(ISD::FEXP2, MVT::v2f32, Expand);
546 setOperationAction(ISD::FCEIL, MVT::v2f32, Expand);
547 setOperationAction(ISD::FTRUNC, MVT::v2f32, Expand);
548 setOperationAction(ISD::FRINT, MVT::v2f32, Expand);
549 setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Expand);
550 setOperationAction(ISD::FFLOOR, MVT::v2f32, Expand);
552 // Neon does not support some operations on v1i64 and v2i64 types.
553 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
554 // Custom handling for some quad-vector types to detect VMULL.
555 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
556 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
557 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
558 // Custom handling for some vector types to avoid expensive expansions
559 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
560 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
561 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
562 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
563 setOperationAction(ISD::SETCC, MVT::v1i64, Expand);
564 setOperationAction(ISD::SETCC, MVT::v2i64, Expand);
565 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
566 // a destination type that is wider than the source, and nor does
567 // it have a FP_TO_[SU]INT instruction with a narrower destination than
569 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
570 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
571 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
572 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
574 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
575 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand);
577 // NEON does not have single instruction CTPOP for vectors with element
578 // types wider than 8-bits. However, custom lowering can leverage the
579 // v8i8/v16i8 vcnt instruction.
580 setOperationAction(ISD::CTPOP, MVT::v2i32, Custom);
581 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
582 setOperationAction(ISD::CTPOP, MVT::v4i16, Custom);
583 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
585 // NEON does not have single instruction CTTZ for vectors.
586 setOperationAction(ISD::CTTZ, MVT::v8i8, Custom);
587 setOperationAction(ISD::CTTZ, MVT::v4i16, Custom);
588 setOperationAction(ISD::CTTZ, MVT::v2i32, Custom);
589 setOperationAction(ISD::CTTZ, MVT::v1i64, Custom);
591 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
592 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
593 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
594 setOperationAction(ISD::CTTZ, MVT::v2i64, Custom);
596 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i8, Custom);
597 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i16, Custom);
598 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i32, Custom);
599 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v1i64, Custom);
601 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
602 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
603 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
604 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
606 // NEON only has FMA instructions as of VFP4.
607 if (!Subtarget->hasVFP4()) {
608 setOperationAction(ISD::FMA, MVT::v2f32, Expand);
609 setOperationAction(ISD::FMA, MVT::v4f32, Expand);
612 setTargetDAGCombine(ISD::INTRINSIC_VOID);
613 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
614 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
615 setTargetDAGCombine(ISD::SHL);
616 setTargetDAGCombine(ISD::SRL);
617 setTargetDAGCombine(ISD::SRA);
618 setTargetDAGCombine(ISD::SIGN_EXTEND);
619 setTargetDAGCombine(ISD::ZERO_EXTEND);
620 setTargetDAGCombine(ISD::ANY_EXTEND);
621 setTargetDAGCombine(ISD::BUILD_VECTOR);
622 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
623 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
624 setTargetDAGCombine(ISD::STORE);
625 setTargetDAGCombine(ISD::FP_TO_SINT);
626 setTargetDAGCombine(ISD::FP_TO_UINT);
627 setTargetDAGCombine(ISD::FDIV);
628 setTargetDAGCombine(ISD::LOAD);
630 // It is legal to extload from v4i8 to v4i16 or v4i32.
631 for (MVT Ty : {MVT::v8i8, MVT::v4i8, MVT::v2i8, MVT::v4i16, MVT::v2i16,
633 for (MVT VT : MVT::integer_vector_valuetypes()) {
634 setLoadExtAction(ISD::EXTLOAD, VT, Ty, Legal);
635 setLoadExtAction(ISD::ZEXTLOAD, VT, Ty, Legal);
636 setLoadExtAction(ISD::SEXTLOAD, VT, Ty, Legal);
641 // ARM and Thumb2 support UMLAL/SMLAL.
642 if (!Subtarget->isThumb1Only())
643 setTargetDAGCombine(ISD::ADDC);
645 if (Subtarget->isFPOnlySP()) {
646 // When targeting a floating-point unit with only single-precision
647 // operations, f64 is legal for the few double-precision instructions which
648 // are present However, no double-precision operations other than moves,
649 // loads and stores are provided by the hardware.
650 setOperationAction(ISD::FADD, MVT::f64, Expand);
651 setOperationAction(ISD::FSUB, MVT::f64, Expand);
652 setOperationAction(ISD::FMUL, MVT::f64, Expand);
653 setOperationAction(ISD::FMA, MVT::f64, Expand);
654 setOperationAction(ISD::FDIV, MVT::f64, Expand);
655 setOperationAction(ISD::FREM, MVT::f64, Expand);
656 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
657 setOperationAction(ISD::FGETSIGN, MVT::f64, Expand);
658 setOperationAction(ISD::FNEG, MVT::f64, Expand);
659 setOperationAction(ISD::FABS, MVT::f64, Expand);
660 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
661 setOperationAction(ISD::FSIN, MVT::f64, Expand);
662 setOperationAction(ISD::FCOS, MVT::f64, Expand);
663 setOperationAction(ISD::FPOWI, MVT::f64, Expand);
664 setOperationAction(ISD::FPOW, MVT::f64, Expand);
665 setOperationAction(ISD::FLOG, MVT::f64, Expand);
666 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
667 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
668 setOperationAction(ISD::FEXP, MVT::f64, Expand);
669 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
670 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
671 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
672 setOperationAction(ISD::FRINT, MVT::f64, Expand);
673 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
674 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
675 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
676 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
677 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
678 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
679 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Custom);
680 setOperationAction(ISD::FP_TO_UINT, MVT::f64, Custom);
681 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
682 setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom);
685 computeRegisterProperties(Subtarget->getRegisterInfo());
687 // ARM does not have floating-point extending loads.
688 for (MVT VT : MVT::fp_valuetypes()) {
689 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
690 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
693 // ... or truncating stores
694 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
695 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
696 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
698 // ARM does not have i1 sign extending load.
699 for (MVT VT : MVT::integer_valuetypes())
700 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
702 // ARM supports all 4 flavors of integer indexed load / store.
703 if (!Subtarget->isThumb1Only()) {
704 for (unsigned im = (unsigned)ISD::PRE_INC;
705 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
706 setIndexedLoadAction(im, MVT::i1, Legal);
707 setIndexedLoadAction(im, MVT::i8, Legal);
708 setIndexedLoadAction(im, MVT::i16, Legal);
709 setIndexedLoadAction(im, MVT::i32, Legal);
710 setIndexedStoreAction(im, MVT::i1, Legal);
711 setIndexedStoreAction(im, MVT::i8, Legal);
712 setIndexedStoreAction(im, MVT::i16, Legal);
713 setIndexedStoreAction(im, MVT::i32, Legal);
717 setOperationAction(ISD::SADDO, MVT::i32, Custom);
718 setOperationAction(ISD::UADDO, MVT::i32, Custom);
719 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
720 setOperationAction(ISD::USUBO, MVT::i32, Custom);
722 // i64 operation support.
723 setOperationAction(ISD::MUL, MVT::i64, Expand);
724 setOperationAction(ISD::MULHU, MVT::i32, Expand);
725 if (Subtarget->isThumb1Only()) {
726 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
727 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
729 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
730 || (Subtarget->isThumb2() && !Subtarget->hasDSP()))
731 setOperationAction(ISD::MULHS, MVT::i32, Expand);
733 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
734 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
735 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
736 setOperationAction(ISD::SRL, MVT::i64, Custom);
737 setOperationAction(ISD::SRA, MVT::i64, Custom);
739 if (!Subtarget->isThumb1Only()) {
740 // FIXME: We should do this for Thumb1 as well.
741 setOperationAction(ISD::ADDC, MVT::i32, Custom);
742 setOperationAction(ISD::ADDE, MVT::i32, Custom);
743 setOperationAction(ISD::SUBC, MVT::i32, Custom);
744 setOperationAction(ISD::SUBE, MVT::i32, Custom);
747 if (!Subtarget->isThumb1Only() && Subtarget->hasV6T2Ops())
748 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
750 // ARM does not have ROTL.
751 setOperationAction(ISD::ROTL, MVT::i32, Expand);
752 for (MVT VT : MVT::vector_valuetypes()) {
753 setOperationAction(ISD::ROTL, VT, Expand);
754 setOperationAction(ISD::ROTR, VT, Expand);
756 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
757 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
758 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
759 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
761 // These just redirect to CTTZ and CTLZ on ARM.
762 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i32 , Expand);
763 setOperationAction(ISD::CTLZ_ZERO_UNDEF , MVT::i32 , Expand);
765 // @llvm.readcyclecounter requires the Performance Monitors extension.
766 // Default to the 0 expansion on unsupported platforms.
767 // FIXME: Technically there are older ARM CPUs that have
768 // implementation-specific ways of obtaining this information.
769 if (Subtarget->hasPerfMon())
770 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
772 // Only ARMv6 has BSWAP.
773 if (!Subtarget->hasV6Ops())
774 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
776 if (!(Subtarget->hasDivide() && Subtarget->isThumb2()) &&
777 !(Subtarget->hasDivideInARMMode() && !Subtarget->isThumb())) {
778 // These are expanded into libcalls if the cpu doesn't have HW divider.
779 setOperationAction(ISD::SDIV, MVT::i32, LibCall);
780 setOperationAction(ISD::UDIV, MVT::i32, LibCall);
783 setOperationAction(ISD::SREM, MVT::i32, Expand);
784 setOperationAction(ISD::UREM, MVT::i32, Expand);
785 // Register based DivRem for AEABI (RTABI 4.2)
786 if (Subtarget->isTargetAEABI() || Subtarget->isTargetAndroid()) {
787 setOperationAction(ISD::SREM, MVT::i64, Custom);
788 setOperationAction(ISD::UREM, MVT::i64, Custom);
790 setLibcallName(RTLIB::SDIVREM_I8, "__aeabi_idivmod");
791 setLibcallName(RTLIB::SDIVREM_I16, "__aeabi_idivmod");
792 setLibcallName(RTLIB::SDIVREM_I32, "__aeabi_idivmod");
793 setLibcallName(RTLIB::SDIVREM_I64, "__aeabi_ldivmod");
794 setLibcallName(RTLIB::UDIVREM_I8, "__aeabi_uidivmod");
795 setLibcallName(RTLIB::UDIVREM_I16, "__aeabi_uidivmod");
796 setLibcallName(RTLIB::UDIVREM_I32, "__aeabi_uidivmod");
797 setLibcallName(RTLIB::UDIVREM_I64, "__aeabi_uldivmod");
799 setLibcallCallingConv(RTLIB::SDIVREM_I8, CallingConv::ARM_AAPCS);
800 setLibcallCallingConv(RTLIB::SDIVREM_I16, CallingConv::ARM_AAPCS);
801 setLibcallCallingConv(RTLIB::SDIVREM_I32, CallingConv::ARM_AAPCS);
802 setLibcallCallingConv(RTLIB::SDIVREM_I64, CallingConv::ARM_AAPCS);
803 setLibcallCallingConv(RTLIB::UDIVREM_I8, CallingConv::ARM_AAPCS);
804 setLibcallCallingConv(RTLIB::UDIVREM_I16, CallingConv::ARM_AAPCS);
805 setLibcallCallingConv(RTLIB::UDIVREM_I32, CallingConv::ARM_AAPCS);
806 setLibcallCallingConv(RTLIB::UDIVREM_I64, CallingConv::ARM_AAPCS);
808 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
809 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
811 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
812 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
815 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
816 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
817 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
818 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
820 setOperationAction(ISD::TRAP, MVT::Other, Legal);
822 // Use the default implementation.
823 setOperationAction(ISD::VASTART, MVT::Other, Custom);
824 setOperationAction(ISD::VAARG, MVT::Other, Expand);
825 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
826 setOperationAction(ISD::VAEND, MVT::Other, Expand);
827 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
828 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
830 if (Subtarget->getTargetTriple().isWindowsItaniumEnvironment())
831 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
833 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
835 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
836 // the default expansion. If we are targeting a single threaded system,
837 // then set them all for expand so we can lower them later into their
839 if (TM.Options.ThreadModel == ThreadModel::Single)
840 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
841 else if (Subtarget->hasAnyDataBarrier() && !Subtarget->isThumb1Only()) {
842 // ATOMIC_FENCE needs custom lowering; the others should have been expanded
843 // to ldrex/strex loops already.
844 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
846 // On v8, we have particularly efficient implementations of atomic fences
847 // if they can be combined with nearby atomic loads and stores.
848 if (!Subtarget->hasV8Ops()) {
849 // Automatically insert fences (dmb ish) around ATOMIC_SWAP etc.
850 setInsertFencesForAtomic(true);
853 // If there's anything we can use as a barrier, go through custom lowering
855 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other,
856 Subtarget->hasAnyDataBarrier() ? Custom : Expand);
858 // Set them all for expansion, which will force libcalls.
859 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
860 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
861 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
862 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
863 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
864 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
865 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
866 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
867 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
868 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
869 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
870 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
871 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the
872 // Unordered/Monotonic case.
873 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
874 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
877 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
879 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
880 if (!Subtarget->hasV6Ops()) {
881 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
882 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
884 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
886 if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2() &&
887 !Subtarget->isThumb1Only()) {
888 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
889 // iff target supports vfp2.
890 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
891 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
894 // We want to custom lower some of our intrinsics.
895 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
896 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
897 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
898 setOperationAction(ISD::EH_SJLJ_SETUP_DISPATCH, MVT::Other, Custom);
899 if (Subtarget->useSjLjEH())
900 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
902 setOperationAction(ISD::SETCC, MVT::i32, Expand);
903 setOperationAction(ISD::SETCC, MVT::f32, Expand);
904 setOperationAction(ISD::SETCC, MVT::f64, Expand);
905 setOperationAction(ISD::SELECT, MVT::i32, Custom);
906 setOperationAction(ISD::SELECT, MVT::f32, Custom);
907 setOperationAction(ISD::SELECT, MVT::f64, Custom);
908 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
909 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
910 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
912 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
913 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
914 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
915 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
916 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
918 // We don't support sin/cos/fmod/copysign/pow
919 setOperationAction(ISD::FSIN, MVT::f64, Expand);
920 setOperationAction(ISD::FSIN, MVT::f32, Expand);
921 setOperationAction(ISD::FCOS, MVT::f32, Expand);
922 setOperationAction(ISD::FCOS, MVT::f64, Expand);
923 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
924 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
925 setOperationAction(ISD::FREM, MVT::f64, Expand);
926 setOperationAction(ISD::FREM, MVT::f32, Expand);
927 if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2() &&
928 !Subtarget->isThumb1Only()) {
929 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
930 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
932 setOperationAction(ISD::FPOW, MVT::f64, Expand);
933 setOperationAction(ISD::FPOW, MVT::f32, Expand);
935 if (!Subtarget->hasVFP4()) {
936 setOperationAction(ISD::FMA, MVT::f64, Expand);
937 setOperationAction(ISD::FMA, MVT::f32, Expand);
940 // Various VFP goodness
941 if (!Subtarget->useSoftFloat() && !Subtarget->isThumb1Only()) {
942 // FP-ARMv8 adds f64 <-> f16 conversion. Before that it should be expanded.
943 if (!Subtarget->hasFPARMv8() || Subtarget->isFPOnlySP()) {
944 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
945 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
948 // fp16 is a special v7 extension that adds f16 <-> f32 conversions.
949 if (!Subtarget->hasFP16()) {
950 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
951 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
955 // Combine sin / cos into one node or libcall if possible.
956 if (Subtarget->hasSinCos()) {
957 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
958 setLibcallName(RTLIB::SINCOS_F64, "sincos");
959 if (Subtarget->isTargetWatchOS()) {
960 setLibcallCallingConv(RTLIB::SINCOS_F32, CallingConv::ARM_AAPCS_VFP);
961 setLibcallCallingConv(RTLIB::SINCOS_F64, CallingConv::ARM_AAPCS_VFP);
963 if (Subtarget->isTargetIOS() || Subtarget->isTargetWatchOS()) {
964 // For iOS, we don't want to the normal expansion of a libcall to
965 // sincos. We want to issue a libcall to __sincos_stret.
966 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
967 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
971 // FP-ARMv8 implements a lot of rounding-like FP operations.
972 if (Subtarget->hasFPARMv8()) {
973 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
974 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
975 setOperationAction(ISD::FROUND, MVT::f32, Legal);
976 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
977 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
978 setOperationAction(ISD::FRINT, MVT::f32, Legal);
979 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
980 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
981 setOperationAction(ISD::FMINNUM, MVT::v2f32, Legal);
982 setOperationAction(ISD::FMAXNUM, MVT::v2f32, Legal);
983 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
984 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
986 if (!Subtarget->isFPOnlySP()) {
987 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
988 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
989 setOperationAction(ISD::FROUND, MVT::f64, Legal);
990 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
991 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
992 setOperationAction(ISD::FRINT, MVT::f64, Legal);
993 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
994 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
998 if (Subtarget->hasNEON()) {
999 // vmin and vmax aren't available in a scalar form, so we use
1000 // a NEON instruction with an undef lane instead.
1001 setOperationAction(ISD::FMINNAN, MVT::f32, Legal);
1002 setOperationAction(ISD::FMAXNAN, MVT::f32, Legal);
1003 setOperationAction(ISD::FMINNAN, MVT::v2f32, Legal);
1004 setOperationAction(ISD::FMAXNAN, MVT::v2f32, Legal);
1005 setOperationAction(ISD::FMINNAN, MVT::v4f32, Legal);
1006 setOperationAction(ISD::FMAXNAN, MVT::v4f32, Legal);
1009 // We have target-specific dag combine patterns for the following nodes:
1010 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
1011 setTargetDAGCombine(ISD::ADD);
1012 setTargetDAGCombine(ISD::SUB);
1013 setTargetDAGCombine(ISD::MUL);
1014 setTargetDAGCombine(ISD::AND);
1015 setTargetDAGCombine(ISD::OR);
1016 setTargetDAGCombine(ISD::XOR);
1018 if (Subtarget->hasV6Ops())
1019 setTargetDAGCombine(ISD::SRL);
1021 setStackPointerRegisterToSaveRestore(ARM::SP);
1023 if (Subtarget->useSoftFloat() || Subtarget->isThumb1Only() ||
1024 !Subtarget->hasVFP2())
1025 setSchedulingPreference(Sched::RegPressure);
1027 setSchedulingPreference(Sched::Hybrid);
1029 //// temporary - rewrite interface to use type
1030 MaxStoresPerMemset = 8;
1031 MaxStoresPerMemsetOptSize = 4;
1032 MaxStoresPerMemcpy = 4; // For @llvm.memcpy -> sequence of stores
1033 MaxStoresPerMemcpyOptSize = 2;
1034 MaxStoresPerMemmove = 4; // For @llvm.memmove -> sequence of stores
1035 MaxStoresPerMemmoveOptSize = 2;
1037 // On ARM arguments smaller than 4 bytes are extended, so all arguments
1038 // are at least 4 bytes aligned.
1039 setMinStackArgumentAlignment(4);
1041 // Prefer likely predicted branches to selects on out-of-order cores.
1042 PredictableSelectIsExpensive = Subtarget->isLikeA9();
1044 setMinFunctionAlignment(Subtarget->isThumb() ? 1 : 2);
1047 bool ARMTargetLowering::useSoftFloat() const {
1048 return Subtarget->useSoftFloat();
1051 // FIXME: It might make sense to define the representative register class as the
1052 // nearest super-register that has a non-null superset. For example, DPR_VFP2 is
1053 // a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
1054 // SPR's representative would be DPR_VFP2. This should work well if register
1055 // pressure tracking were modified such that a register use would increment the
1056 // pressure of the register class's representative and all of it's super
1057 // classes' representatives transitively. We have not implemented this because
1058 // of the difficulty prior to coalescing of modeling operand register classes
1059 // due to the common occurrence of cross class copies and subregister insertions
1061 std::pair<const TargetRegisterClass *, uint8_t>
1062 ARMTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
1064 const TargetRegisterClass *RRC = nullptr;
1066 switch (VT.SimpleTy) {
1068 return TargetLowering::findRepresentativeClass(TRI, VT);
1069 // Use DPR as representative register class for all floating point
1070 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
1071 // the cost is 1 for both f32 and f64.
1072 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
1073 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
1074 RRC = &ARM::DPRRegClass;
1075 // When NEON is used for SP, only half of the register file is available
1076 // because operations that define both SP and DP results will be constrained
1077 // to the VFP2 class (D0-D15). We currently model this constraint prior to
1078 // coalescing by double-counting the SP regs. See the FIXME above.
1079 if (Subtarget->useNEONForSinglePrecisionFP())
1082 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1083 case MVT::v4f32: case MVT::v2f64:
1084 RRC = &ARM::DPRRegClass;
1088 RRC = &ARM::DPRRegClass;
1092 RRC = &ARM::DPRRegClass;
1096 return std::make_pair(RRC, Cost);
1099 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
1100 switch ((ARMISD::NodeType)Opcode) {
1101 case ARMISD::FIRST_NUMBER: break;
1102 case ARMISD::Wrapper: return "ARMISD::Wrapper";
1103 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
1104 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
1105 case ARMISD::COPY_STRUCT_BYVAL: return "ARMISD::COPY_STRUCT_BYVAL";
1106 case ARMISD::CALL: return "ARMISD::CALL";
1107 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
1108 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
1109 case ARMISD::tCALL: return "ARMISD::tCALL";
1110 case ARMISD::BRCOND: return "ARMISD::BRCOND";
1111 case ARMISD::BR_JT: return "ARMISD::BR_JT";
1112 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
1113 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
1114 case ARMISD::INTRET_FLAG: return "ARMISD::INTRET_FLAG";
1115 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
1116 case ARMISD::CMP: return "ARMISD::CMP";
1117 case ARMISD::CMN: return "ARMISD::CMN";
1118 case ARMISD::CMPZ: return "ARMISD::CMPZ";
1119 case ARMISD::CMPFP: return "ARMISD::CMPFP";
1120 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
1121 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
1122 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
1124 case ARMISD::CMOV: return "ARMISD::CMOV";
1126 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
1127 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
1128 case ARMISD::RRX: return "ARMISD::RRX";
1130 case ARMISD::ADDC: return "ARMISD::ADDC";
1131 case ARMISD::ADDE: return "ARMISD::ADDE";
1132 case ARMISD::SUBC: return "ARMISD::SUBC";
1133 case ARMISD::SUBE: return "ARMISD::SUBE";
1135 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
1136 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
1138 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
1139 case ARMISD::EH_SJLJ_LONGJMP: return "ARMISD::EH_SJLJ_LONGJMP";
1140 case ARMISD::EH_SJLJ_SETUP_DISPATCH: return "ARMISD::EH_SJLJ_SETUP_DISPATCH";
1142 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
1144 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
1146 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
1148 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
1150 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
1152 case ARMISD::WIN__CHKSTK: return "ARMISD:::WIN__CHKSTK";
1153 case ARMISD::WIN__DBZCHK: return "ARMISD::WIN__DBZCHK";
1155 case ARMISD::VCEQ: return "ARMISD::VCEQ";
1156 case ARMISD::VCEQZ: return "ARMISD::VCEQZ";
1157 case ARMISD::VCGE: return "ARMISD::VCGE";
1158 case ARMISD::VCGEZ: return "ARMISD::VCGEZ";
1159 case ARMISD::VCLEZ: return "ARMISD::VCLEZ";
1160 case ARMISD::VCGEU: return "ARMISD::VCGEU";
1161 case ARMISD::VCGT: return "ARMISD::VCGT";
1162 case ARMISD::VCGTZ: return "ARMISD::VCGTZ";
1163 case ARMISD::VCLTZ: return "ARMISD::VCLTZ";
1164 case ARMISD::VCGTU: return "ARMISD::VCGTU";
1165 case ARMISD::VTST: return "ARMISD::VTST";
1167 case ARMISD::VSHL: return "ARMISD::VSHL";
1168 case ARMISD::VSHRs: return "ARMISD::VSHRs";
1169 case ARMISD::VSHRu: return "ARMISD::VSHRu";
1170 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
1171 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
1172 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
1173 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
1174 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
1175 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
1176 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
1177 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
1178 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
1179 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
1180 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
1181 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
1182 case ARMISD::VSLI: return "ARMISD::VSLI";
1183 case ARMISD::VSRI: return "ARMISD::VSRI";
1184 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
1185 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
1186 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
1187 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
1188 case ARMISD::VMOVFPIMM: return "ARMISD::VMOVFPIMM";
1189 case ARMISD::VDUP: return "ARMISD::VDUP";
1190 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
1191 case ARMISD::VEXT: return "ARMISD::VEXT";
1192 case ARMISD::VREV64: return "ARMISD::VREV64";
1193 case ARMISD::VREV32: return "ARMISD::VREV32";
1194 case ARMISD::VREV16: return "ARMISD::VREV16";
1195 case ARMISD::VZIP: return "ARMISD::VZIP";
1196 case ARMISD::VUZP: return "ARMISD::VUZP";
1197 case ARMISD::VTRN: return "ARMISD::VTRN";
1198 case ARMISD::VTBL1: return "ARMISD::VTBL1";
1199 case ARMISD::VTBL2: return "ARMISD::VTBL2";
1200 case ARMISD::VMULLs: return "ARMISD::VMULLs";
1201 case ARMISD::VMULLu: return "ARMISD::VMULLu";
1202 case ARMISD::UMLAL: return "ARMISD::UMLAL";
1203 case ARMISD::SMLAL: return "ARMISD::SMLAL";
1204 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
1205 case ARMISD::BFI: return "ARMISD::BFI";
1206 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
1207 case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
1208 case ARMISD::VBSL: return "ARMISD::VBSL";
1209 case ARMISD::MEMCPY: return "ARMISD::MEMCPY";
1210 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
1211 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
1212 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
1213 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD";
1214 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD";
1215 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD";
1216 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD";
1217 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD";
1218 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD";
1219 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD";
1220 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD";
1221 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD";
1222 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD";
1223 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD";
1224 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD";
1225 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD";
1226 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD";
1227 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD";
1228 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD";
1229 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD";
1234 EVT ARMTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1237 return getPointerTy(DL);
1238 return VT.changeVectorElementTypeToInteger();
1241 /// getRegClassFor - Return the register class that should be used for the
1242 /// specified value type.
1243 const TargetRegisterClass *ARMTargetLowering::getRegClassFor(MVT VT) const {
1244 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
1245 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
1246 // load / store 4 to 8 consecutive D registers.
1247 if (Subtarget->hasNEON()) {
1248 if (VT == MVT::v4i64)
1249 return &ARM::QQPRRegClass;
1250 if (VT == MVT::v8i64)
1251 return &ARM::QQQQPRRegClass;
1253 return TargetLowering::getRegClassFor(VT);
1256 // memcpy, and other memory intrinsics, typically tries to use LDM/STM if the
1257 // source/dest is aligned and the copy size is large enough. We therefore want
1258 // to align such objects passed to memory intrinsics.
1259 bool ARMTargetLowering::shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
1260 unsigned &PrefAlign) const {
1261 if (!isa<MemIntrinsic>(CI))
1264 // On ARM11 onwards (excluding M class) 8-byte aligned LDM is typically 1
1265 // cycle faster than 4-byte aligned LDM.
1266 PrefAlign = (Subtarget->hasV6Ops() && !Subtarget->isMClass() ? 8 : 4);
1270 // Create a fast isel object.
1272 ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
1273 const TargetLibraryInfo *libInfo) const {
1274 return ARM::createFastISel(funcInfo, libInfo);
1277 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
1278 unsigned NumVals = N->getNumValues();
1280 return Sched::RegPressure;
1282 for (unsigned i = 0; i != NumVals; ++i) {
1283 EVT VT = N->getValueType(i);
1284 if (VT == MVT::Glue || VT == MVT::Other)
1286 if (VT.isFloatingPoint() || VT.isVector())
1290 if (!N->isMachineOpcode())
1291 return Sched::RegPressure;
1293 // Load are scheduled for latency even if there instruction itinerary
1294 // is not available.
1295 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
1296 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1298 if (MCID.getNumDefs() == 0)
1299 return Sched::RegPressure;
1300 if (!Itins->isEmpty() &&
1301 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
1304 return Sched::RegPressure;
1307 //===----------------------------------------------------------------------===//
1309 //===----------------------------------------------------------------------===//
1311 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
1312 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
1314 default: llvm_unreachable("Unknown condition code!");
1315 case ISD::SETNE: return ARMCC::NE;
1316 case ISD::SETEQ: return ARMCC::EQ;
1317 case ISD::SETGT: return ARMCC::GT;
1318 case ISD::SETGE: return ARMCC::GE;
1319 case ISD::SETLT: return ARMCC::LT;
1320 case ISD::SETLE: return ARMCC::LE;
1321 case ISD::SETUGT: return ARMCC::HI;
1322 case ISD::SETUGE: return ARMCC::HS;
1323 case ISD::SETULT: return ARMCC::LO;
1324 case ISD::SETULE: return ARMCC::LS;
1328 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
1329 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
1330 ARMCC::CondCodes &CondCode2) {
1331 CondCode2 = ARMCC::AL;
1333 default: llvm_unreachable("Unknown FP condition!");
1335 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
1337 case ISD::SETOGT: CondCode = ARMCC::GT; break;
1339 case ISD::SETOGE: CondCode = ARMCC::GE; break;
1340 case ISD::SETOLT: CondCode = ARMCC::MI; break;
1341 case ISD::SETOLE: CondCode = ARMCC::LS; break;
1342 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
1343 case ISD::SETO: CondCode = ARMCC::VC; break;
1344 case ISD::SETUO: CondCode = ARMCC::VS; break;
1345 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
1346 case ISD::SETUGT: CondCode = ARMCC::HI; break;
1347 case ISD::SETUGE: CondCode = ARMCC::PL; break;
1349 case ISD::SETULT: CondCode = ARMCC::LT; break;
1351 case ISD::SETULE: CondCode = ARMCC::LE; break;
1353 case ISD::SETUNE: CondCode = ARMCC::NE; break;
1357 //===----------------------------------------------------------------------===//
1358 // Calling Convention Implementation
1359 //===----------------------------------------------------------------------===//
1361 #include "ARMGenCallingConv.inc"
1363 /// getEffectiveCallingConv - Get the effective calling convention, taking into
1364 /// account presence of floating point hardware and calling convention
1365 /// limitations, such as support for variadic functions.
1367 ARMTargetLowering::getEffectiveCallingConv(CallingConv::ID CC,
1368 bool isVarArg) const {
1371 llvm_unreachable("Unsupported calling convention");
1372 case CallingConv::ARM_AAPCS:
1373 case CallingConv::ARM_APCS:
1374 case CallingConv::GHC:
1376 case CallingConv::ARM_AAPCS_VFP:
1377 return isVarArg ? CallingConv::ARM_AAPCS : CallingConv::ARM_AAPCS_VFP;
1378 case CallingConv::C:
1379 if (!Subtarget->isAAPCS_ABI())
1380 return CallingConv::ARM_APCS;
1381 else if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() &&
1382 getTargetMachine().Options.FloatABIType == FloatABI::Hard &&
1384 return CallingConv::ARM_AAPCS_VFP;
1386 return CallingConv::ARM_AAPCS;
1387 case CallingConv::Fast:
1388 case CallingConv::CXX_FAST_TLS:
1389 if (!Subtarget->isAAPCS_ABI()) {
1390 if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() && !isVarArg)
1391 return CallingConv::Fast;
1392 return CallingConv::ARM_APCS;
1393 } else if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() && !isVarArg)
1394 return CallingConv::ARM_AAPCS_VFP;
1396 return CallingConv::ARM_AAPCS;
1400 /// CCAssignFnForNode - Selects the correct CCAssignFn for the given
1401 /// CallingConvention.
1402 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
1404 bool isVarArg) const {
1405 switch (getEffectiveCallingConv(CC, isVarArg)) {
1407 llvm_unreachable("Unsupported calling convention");
1408 case CallingConv::ARM_APCS:
1409 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1410 case CallingConv::ARM_AAPCS:
1411 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1412 case CallingConv::ARM_AAPCS_VFP:
1413 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1414 case CallingConv::Fast:
1415 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1416 case CallingConv::GHC:
1417 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC);
1421 /// LowerCallResult - Lower the result values of a call into the
1422 /// appropriate copies out of appropriate physical registers.
1424 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1425 CallingConv::ID CallConv, bool isVarArg,
1426 const SmallVectorImpl<ISD::InputArg> &Ins,
1427 SDLoc dl, SelectionDAG &DAG,
1428 SmallVectorImpl<SDValue> &InVals,
1429 bool isThisReturn, SDValue ThisVal) const {
1431 // Assign locations to each value returned by this call.
1432 SmallVector<CCValAssign, 16> RVLocs;
1433 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1434 *DAG.getContext(), Call);
1435 CCInfo.AnalyzeCallResult(Ins,
1436 CCAssignFnForNode(CallConv, /* Return*/ true,
1439 // Copy all of the result registers out of their specified physreg.
1440 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1441 CCValAssign VA = RVLocs[i];
1443 // Pass 'this' value directly from the argument to return value, to avoid
1444 // reg unit interference
1445 if (i == 0 && isThisReturn) {
1446 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&
1447 "unexpected return calling convention register assignment");
1448 InVals.push_back(ThisVal);
1453 if (VA.needsCustom()) {
1454 // Handle f64 or half of a v2f64.
1455 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1457 Chain = Lo.getValue(1);
1458 InFlag = Lo.getValue(2);
1459 VA = RVLocs[++i]; // skip ahead to next loc
1460 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1462 Chain = Hi.getValue(1);
1463 InFlag = Hi.getValue(2);
1464 if (!Subtarget->isLittle())
1466 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1468 if (VA.getLocVT() == MVT::v2f64) {
1469 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1470 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1471 DAG.getConstant(0, dl, MVT::i32));
1473 VA = RVLocs[++i]; // skip ahead to next loc
1474 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1475 Chain = Lo.getValue(1);
1476 InFlag = Lo.getValue(2);
1477 VA = RVLocs[++i]; // skip ahead to next loc
1478 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1479 Chain = Hi.getValue(1);
1480 InFlag = Hi.getValue(2);
1481 if (!Subtarget->isLittle())
1483 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1484 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1485 DAG.getConstant(1, dl, MVT::i32));
1488 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1490 Chain = Val.getValue(1);
1491 InFlag = Val.getValue(2);
1494 switch (VA.getLocInfo()) {
1495 default: llvm_unreachable("Unknown loc info!");
1496 case CCValAssign::Full: break;
1497 case CCValAssign::BCvt:
1498 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1502 InVals.push_back(Val);
1508 /// LowerMemOpCallTo - Store the argument to the stack.
1510 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
1511 SDValue StackPtr, SDValue Arg,
1512 SDLoc dl, SelectionDAG &DAG,
1513 const CCValAssign &VA,
1514 ISD::ArgFlagsTy Flags) const {
1515 unsigned LocMemOffset = VA.getLocMemOffset();
1516 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
1517 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
1519 return DAG.getStore(
1520 Chain, dl, Arg, PtrOff,
1521 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset),
1525 void ARMTargetLowering::PassF64ArgInRegs(SDLoc dl, SelectionDAG &DAG,
1526 SDValue Chain, SDValue &Arg,
1527 RegsToPassVector &RegsToPass,
1528 CCValAssign &VA, CCValAssign &NextVA,
1530 SmallVectorImpl<SDValue> &MemOpChains,
1531 ISD::ArgFlagsTy Flags) const {
1533 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1534 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1535 unsigned id = Subtarget->isLittle() ? 0 : 1;
1536 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(id)));
1538 if (NextVA.isRegLoc())
1539 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1-id)));
1541 assert(NextVA.isMemLoc());
1542 if (!StackPtr.getNode())
1543 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP,
1544 getPointerTy(DAG.getDataLayout()));
1546 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1-id),
1552 /// LowerCall - Lowering a call into a callseq_start <-
1553 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1556 ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1557 SmallVectorImpl<SDValue> &InVals) const {
1558 SelectionDAG &DAG = CLI.DAG;
1560 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1561 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1562 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1563 SDValue Chain = CLI.Chain;
1564 SDValue Callee = CLI.Callee;
1565 bool &isTailCall = CLI.IsTailCall;
1566 CallingConv::ID CallConv = CLI.CallConv;
1567 bool doesNotRet = CLI.DoesNotReturn;
1568 bool isVarArg = CLI.IsVarArg;
1570 MachineFunction &MF = DAG.getMachineFunction();
1571 bool isStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1572 bool isThisReturn = false;
1573 bool isSibCall = false;
1574 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
1576 // Disable tail calls if they're not supported.
1577 if (!Subtarget->supportsTailCall() || Attr.getValueAsString() == "true")
1581 // Check if it's really possible to do a tail call.
1582 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1583 isVarArg, isStructRet, MF.getFunction()->hasStructRetAttr(),
1584 Outs, OutVals, Ins, DAG);
1585 if (!isTailCall && CLI.CS && CLI.CS->isMustTailCall())
1586 report_fatal_error("failed to perform tail call elimination on a call "
1587 "site marked musttail");
1588 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1589 // detected sibcalls.
1596 // Analyze operands of the call, assigning locations to each operand.
1597 SmallVector<CCValAssign, 16> ArgLocs;
1598 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1599 *DAG.getContext(), Call);
1600 CCInfo.AnalyzeCallOperands(Outs,
1601 CCAssignFnForNode(CallConv, /* Return*/ false,
1604 // Get a count of how many bytes are to be pushed on the stack.
1605 unsigned NumBytes = CCInfo.getNextStackOffset();
1607 // For tail calls, memory operands are available in our caller's stack.
1611 // Adjust the stack pointer for the new arguments...
1612 // These operations are automatically eliminated by the prolog/epilog pass
1614 Chain = DAG.getCALLSEQ_START(Chain,
1615 DAG.getIntPtrConstant(NumBytes, dl, true), dl);
1618 DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy(DAG.getDataLayout()));
1620 RegsToPassVector RegsToPass;
1621 SmallVector<SDValue, 8> MemOpChains;
1623 // Walk the register/memloc assignments, inserting copies/loads. In the case
1624 // of tail call optimization, arguments are handled later.
1625 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1627 ++i, ++realArgIdx) {
1628 CCValAssign &VA = ArgLocs[i];
1629 SDValue Arg = OutVals[realArgIdx];
1630 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1631 bool isByVal = Flags.isByVal();
1633 // Promote the value if needed.
1634 switch (VA.getLocInfo()) {
1635 default: llvm_unreachable("Unknown loc info!");
1636 case CCValAssign::Full: break;
1637 case CCValAssign::SExt:
1638 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1640 case CCValAssign::ZExt:
1641 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1643 case CCValAssign::AExt:
1644 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1646 case CCValAssign::BCvt:
1647 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1651 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1652 if (VA.needsCustom()) {
1653 if (VA.getLocVT() == MVT::v2f64) {
1654 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1655 DAG.getConstant(0, dl, MVT::i32));
1656 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1657 DAG.getConstant(1, dl, MVT::i32));
1659 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1660 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1662 VA = ArgLocs[++i]; // skip ahead to next loc
1663 if (VA.isRegLoc()) {
1664 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1665 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1667 assert(VA.isMemLoc());
1669 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1670 dl, DAG, VA, Flags));
1673 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1674 StackPtr, MemOpChains, Flags);
1676 } else if (VA.isRegLoc()) {
1677 if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i32) {
1678 assert(VA.getLocVT() == MVT::i32 &&
1679 "unexpected calling convention register assignment");
1680 assert(!Ins.empty() && Ins[0].VT == MVT::i32 &&
1681 "unexpected use of 'returned'");
1682 isThisReturn = true;
1684 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1685 } else if (isByVal) {
1686 assert(VA.isMemLoc());
1687 unsigned offset = 0;
1689 // True if this byval aggregate will be split between registers
1691 unsigned ByValArgsCount = CCInfo.getInRegsParamsCount();
1692 unsigned CurByValIdx = CCInfo.getInRegsParamsProcessed();
1694 if (CurByValIdx < ByValArgsCount) {
1696 unsigned RegBegin, RegEnd;
1697 CCInfo.getInRegsParamInfo(CurByValIdx, RegBegin, RegEnd);
1700 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
1702 for (i = 0, j = RegBegin; j < RegEnd; i++, j++) {
1703 SDValue Const = DAG.getConstant(4*i, dl, MVT::i32);
1704 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
1705 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
1706 MachinePointerInfo(),
1707 false, false, false,
1708 DAG.InferPtrAlignment(AddArg));
1709 MemOpChains.push_back(Load.getValue(1));
1710 RegsToPass.push_back(std::make_pair(j, Load));
1713 // If parameter size outsides register area, "offset" value
1714 // helps us to calculate stack slot for remained part properly.
1715 offset = RegEnd - RegBegin;
1717 CCInfo.nextInRegsParam();
1720 if (Flags.getByValSize() > 4*offset) {
1721 auto PtrVT = getPointerTy(DAG.getDataLayout());
1722 unsigned LocMemOffset = VA.getLocMemOffset();
1723 SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
1724 SDValue Dst = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, StkPtrOff);
1725 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset, dl);
1726 SDValue Src = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, SrcOffset);
1727 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset, dl,
1729 SDValue AlignNode = DAG.getConstant(Flags.getByValAlign(), dl,
1732 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
1733 SDValue Ops[] = { Chain, Dst, Src, SizeNode, AlignNode};
1734 MemOpChains.push_back(DAG.getNode(ARMISD::COPY_STRUCT_BYVAL, dl, VTs,
1737 } else if (!isSibCall) {
1738 assert(VA.isMemLoc());
1740 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1741 dl, DAG, VA, Flags));
1745 if (!MemOpChains.empty())
1746 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
1748 // Build a sequence of copy-to-reg nodes chained together with token chain
1749 // and flag operands which copy the outgoing args into the appropriate regs.
1751 // Tail call byval lowering might overwrite argument registers so in case of
1752 // tail call optimization the copies to registers are lowered later.
1754 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1755 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1756 RegsToPass[i].second, InFlag);
1757 InFlag = Chain.getValue(1);
1760 // For tail calls lower the arguments to the 'real' stack slot.
1762 // Force all the incoming stack arguments to be loaded from the stack
1763 // before any new outgoing arguments are stored to the stack, because the
1764 // outgoing stack slots may alias the incoming argument stack slots, and
1765 // the alias isn't otherwise explicit. This is slightly more conservative
1766 // than necessary, because it means that each store effectively depends
1767 // on every argument instead of just those arguments it would clobber.
1769 // Do not flag preceding copytoreg stuff together with the following stuff.
1771 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1772 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1773 RegsToPass[i].second, InFlag);
1774 InFlag = Chain.getValue(1);
1779 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1780 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1781 // node so that legalize doesn't hack it.
1782 bool isDirect = false;
1783 bool isARMFunc = false;
1784 bool isLocalARMFunc = false;
1785 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1786 auto PtrVt = getPointerTy(DAG.getDataLayout());
1788 if (Subtarget->genLongCalls()) {
1789 assert((Subtarget->isTargetWindows() ||
1790 getTargetMachine().getRelocationModel() == Reloc::Static) &&
1791 "long-calls with non-static relocation model!");
1792 // Handle a global address or an external symbol. If it's not one of
1793 // those, the target's already in a register, so we don't need to do
1795 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1796 const GlobalValue *GV = G->getGlobal();
1797 // Create a constant pool entry for the callee address
1798 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1799 ARMConstantPoolValue *CPV =
1800 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0);
1802 // Get the address of the callee into a register
1803 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4);
1804 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1805 Callee = DAG.getLoad(
1806 PtrVt, dl, DAG.getEntryNode(), CPAddr,
1807 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
1809 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1810 const char *Sym = S->getSymbol();
1812 // Create a constant pool entry for the callee address
1813 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1814 ARMConstantPoolValue *CPV =
1815 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
1816 ARMPCLabelIndex, 0);
1817 // Get the address of the callee into a register
1818 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4);
1819 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1820 Callee = DAG.getLoad(
1821 PtrVt, dl, DAG.getEntryNode(), CPAddr,
1822 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
1825 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1826 const GlobalValue *GV = G->getGlobal();
1828 bool isDef = GV->isStrongDefinitionForLinker();
1829 bool isStub = (!isDef && Subtarget->isTargetMachO()) &&
1830 getTargetMachine().getRelocationModel() != Reloc::Static;
1831 isARMFunc = !Subtarget->isThumb() || (isStub && !Subtarget->isMClass());
1832 // ARM call to a local ARM function is predicable.
1833 isLocalARMFunc = !Subtarget->isThumb() && (isDef || !ARMInterworking);
1834 // tBX takes a register source operand.
1835 if (isStub && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1836 assert(Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?");
1837 Callee = DAG.getNode(
1838 ARMISD::WrapperPIC, dl, PtrVt,
1839 DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, ARMII::MO_NONLAZY));
1840 Callee = DAG.getLoad(PtrVt, dl, DAG.getEntryNode(), Callee,
1841 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
1842 false, false, true, 0);
1843 } else if (Subtarget->isTargetCOFF()) {
1844 assert(Subtarget->isTargetWindows() &&
1845 "Windows is the only supported COFF target");
1846 unsigned TargetFlags = GV->hasDLLImportStorageClass()
1847 ? ARMII::MO_DLLIMPORT
1848 : ARMII::MO_NO_FLAG;
1850 DAG.getTargetGlobalAddress(GV, dl, PtrVt, /*Offset=*/0, TargetFlags);
1851 if (GV->hasDLLImportStorageClass())
1853 DAG.getLoad(PtrVt, dl, DAG.getEntryNode(),
1854 DAG.getNode(ARMISD::Wrapper, dl, PtrVt, Callee),
1855 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
1856 false, false, false, 0);
1858 // On ELF targets for PIC code, direct calls should go through the PLT
1859 unsigned OpFlags = 0;
1860 if (Subtarget->isTargetELF() &&
1861 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1862 OpFlags = ARMII::MO_PLT;
1863 Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, OpFlags);
1865 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1867 bool isStub = Subtarget->isTargetMachO() &&
1868 getTargetMachine().getRelocationModel() != Reloc::Static;
1869 isARMFunc = !Subtarget->isThumb() || (isStub && !Subtarget->isMClass());
1870 // tBX takes a register source operand.
1871 const char *Sym = S->getSymbol();
1872 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1873 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1874 ARMConstantPoolValue *CPV =
1875 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
1876 ARMPCLabelIndex, 4);
1877 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4);
1878 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1879 Callee = DAG.getLoad(
1880 PtrVt, dl, DAG.getEntryNode(), CPAddr,
1881 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
1883 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
1884 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVt, Callee, PICLabel);
1886 unsigned OpFlags = 0;
1887 // On ELF targets for PIC code, direct calls should go through the PLT
1888 if (Subtarget->isTargetELF() &&
1889 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1890 OpFlags = ARMII::MO_PLT;
1891 Callee = DAG.getTargetExternalSymbol(Sym, PtrVt, OpFlags);
1895 // FIXME: handle tail calls differently.
1897 if (Subtarget->isThumb()) {
1898 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1899 CallOpc = ARMISD::CALL_NOLINK;
1901 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1903 if (!isDirect && !Subtarget->hasV5TOps())
1904 CallOpc = ARMISD::CALL_NOLINK;
1905 else if (doesNotRet && isDirect && Subtarget->hasRAS() &&
1906 // Emit regular call when code size is the priority
1907 !MF.getFunction()->optForMinSize())
1908 // "mov lr, pc; b _foo" to avoid confusing the RSP
1909 CallOpc = ARMISD::CALL_NOLINK;
1911 CallOpc = isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL;
1914 std::vector<SDValue> Ops;
1915 Ops.push_back(Chain);
1916 Ops.push_back(Callee);
1918 // Add argument registers to the end of the list so that they are known live
1920 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1921 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1922 RegsToPass[i].second.getValueType()));
1924 // Add a register mask operand representing the call-preserved registers.
1926 const uint32_t *Mask;
1927 const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo();
1929 // For 'this' returns, use the R0-preserving mask if applicable
1930 Mask = ARI->getThisReturnPreservedMask(MF, CallConv);
1932 // Set isThisReturn to false if the calling convention is not one that
1933 // allows 'returned' to be modeled in this way, so LowerCallResult does
1934 // not try to pass 'this' straight through
1935 isThisReturn = false;
1936 Mask = ARI->getCallPreservedMask(MF, CallConv);
1939 Mask = ARI->getCallPreservedMask(MF, CallConv);
1941 assert(Mask && "Missing call preserved mask for calling convention");
1942 Ops.push_back(DAG.getRegisterMask(Mask));
1945 if (InFlag.getNode())
1946 Ops.push_back(InFlag);
1948 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1950 MF.getFrameInfo()->setHasTailCall();
1951 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, Ops);
1954 // Returns a chain and a flag for retval copy to use.
1955 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
1956 InFlag = Chain.getValue(1);
1958 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
1959 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
1961 InFlag = Chain.getValue(1);
1963 // Handle result values, copying them out of physregs into vregs that we
1965 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
1966 InVals, isThisReturn,
1967 isThisReturn ? OutVals[0] : SDValue());
1970 /// HandleByVal - Every parameter *after* a byval parameter is passed
1971 /// on the stack. Remember the next parameter register to allocate,
1972 /// and then confiscate the rest of the parameter registers to insure
1974 void ARMTargetLowering::HandleByVal(CCState *State, unsigned &Size,
1975 unsigned Align) const {
1976 assert((State->getCallOrPrologue() == Prologue ||
1977 State->getCallOrPrologue() == Call) &&
1978 "unhandled ParmContext");
1980 // Byval (as with any stack) slots are always at least 4 byte aligned.
1981 Align = std::max(Align, 4U);
1983 unsigned Reg = State->AllocateReg(GPRArgRegs);
1987 unsigned AlignInRegs = Align / 4;
1988 unsigned Waste = (ARM::R4 - Reg) % AlignInRegs;
1989 for (unsigned i = 0; i < Waste; ++i)
1990 Reg = State->AllocateReg(GPRArgRegs);
1995 unsigned Excess = 4 * (ARM::R4 - Reg);
1997 // Special case when NSAA != SP and parameter size greater than size of
1998 // all remained GPR regs. In that case we can't split parameter, we must
1999 // send it to stack. We also must set NCRN to R4, so waste all
2000 // remained registers.
2001 const unsigned NSAAOffset = State->getNextStackOffset();
2002 if (NSAAOffset != 0 && Size > Excess) {
2003 while (State->AllocateReg(GPRArgRegs))
2008 // First register for byval parameter is the first register that wasn't
2009 // allocated before this method call, so it would be "reg".
2010 // If parameter is small enough to be saved in range [reg, r4), then
2011 // the end (first after last) register would be reg + param-size-in-regs,
2012 // else parameter would be splitted between registers and stack,
2013 // end register would be r4 in this case.
2014 unsigned ByValRegBegin = Reg;
2015 unsigned ByValRegEnd = std::min<unsigned>(Reg + Size / 4, ARM::R4);
2016 State->addInRegsParamInfo(ByValRegBegin, ByValRegEnd);
2017 // Note, first register is allocated in the beginning of function already,
2018 // allocate remained amount of registers we need.
2019 for (unsigned i = Reg + 1; i != ByValRegEnd; ++i)
2020 State->AllocateReg(GPRArgRegs);
2021 // A byval parameter that is split between registers and memory needs its
2022 // size truncated here.
2023 // In the case where the entire structure fits in registers, we set the
2024 // size in memory to zero.
2025 Size = std::max<int>(Size - Excess, 0);
2028 /// MatchingStackOffset - Return true if the given stack call argument is
2029 /// already available in the same position (relatively) of the caller's
2030 /// incoming argument stack.
2032 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
2033 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2034 const TargetInstrInfo *TII) {
2035 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2037 if (Arg.getOpcode() == ISD::CopyFromReg) {
2038 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2039 if (!TargetRegisterInfo::isVirtualRegister(VR))
2041 MachineInstr *Def = MRI->getVRegDef(VR);
2044 if (!Flags.isByVal()) {
2045 if (!TII->isLoadFromStackSlot(Def, FI))
2050 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2051 if (Flags.isByVal())
2052 // ByVal argument is passed in as a pointer but it's now being
2053 // dereferenced. e.g.
2054 // define @foo(%struct.X* %A) {
2055 // tail call @bar(%struct.X* byval %A)
2058 SDValue Ptr = Ld->getBasePtr();
2059 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2062 FI = FINode->getIndex();
2066 assert(FI != INT_MAX);
2067 if (!MFI->isFixedObjectIndex(FI))
2069 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2072 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2073 /// for tail call optimization. Targets which want to do tail call
2074 /// optimization should implement this function.
2076 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2077 CallingConv::ID CalleeCC,
2079 bool isCalleeStructRet,
2080 bool isCallerStructRet,
2081 const SmallVectorImpl<ISD::OutputArg> &Outs,
2082 const SmallVectorImpl<SDValue> &OutVals,
2083 const SmallVectorImpl<ISD::InputArg> &Ins,
2084 SelectionDAG& DAG) const {
2085 const Function *CallerF = DAG.getMachineFunction().getFunction();
2086 CallingConv::ID CallerCC = CallerF->getCallingConv();
2087 bool CCMatch = CallerCC == CalleeCC;
2089 assert(Subtarget->supportsTailCall());
2091 // Look for obvious safe cases to perform tail call optimization that do not
2092 // require ABI changes. This is what gcc calls sibcall.
2094 // Do not sibcall optimize vararg calls unless the call site is not passing
2096 if (isVarArg && !Outs.empty())
2099 // Exception-handling functions need a special set of instructions to indicate
2100 // a return to the hardware. Tail-calling another function would probably
2102 if (CallerF->hasFnAttribute("interrupt"))
2105 // Also avoid sibcall optimization if either caller or callee uses struct
2106 // return semantics.
2107 if (isCalleeStructRet || isCallerStructRet)
2110 // Externally-defined functions with weak linkage should not be
2111 // tail-called on ARM when the OS does not support dynamic
2112 // pre-emption of symbols, as the AAELF spec requires normal calls
2113 // to undefined weak functions to be replaced with a NOP or jump to the
2114 // next instruction. The behaviour of branch instructions in this
2115 // situation (as used for tail calls) is implementation-defined, so we
2116 // cannot rely on the linker replacing the tail call with a return.
2117 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2118 const GlobalValue *GV = G->getGlobal();
2119 const Triple &TT = getTargetMachine().getTargetTriple();
2120 if (GV->hasExternalWeakLinkage() &&
2121 (!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
2125 // If the calling conventions do not match, then we'd better make sure the
2126 // results are returned in the same way as what the caller expects.
2128 SmallVector<CCValAssign, 16> RVLocs1;
2129 ARMCCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
2130 *DAG.getContext(), Call);
2131 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
2133 SmallVector<CCValAssign, 16> RVLocs2;
2134 ARMCCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
2135 *DAG.getContext(), Call);
2136 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
2138 if (RVLocs1.size() != RVLocs2.size())
2140 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2141 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2143 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2145 if (RVLocs1[i].isRegLoc()) {
2146 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2149 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2155 // If Caller's vararg or byval argument has been split between registers and
2156 // stack, do not perform tail call, since part of the argument is in caller's
2158 const ARMFunctionInfo *AFI_Caller = DAG.getMachineFunction().
2159 getInfo<ARMFunctionInfo>();
2160 if (AFI_Caller->getArgRegsSaveSize())
2163 // If the callee takes no arguments then go on to check the results of the
2165 if (!Outs.empty()) {
2166 // Check if stack adjustment is needed. For now, do not do this if any
2167 // argument is passed on the stack.
2168 SmallVector<CCValAssign, 16> ArgLocs;
2169 ARMCCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2170 *DAG.getContext(), Call);
2171 CCInfo.AnalyzeCallOperands(Outs,
2172 CCAssignFnForNode(CalleeCC, false, isVarArg));
2173 if (CCInfo.getNextStackOffset()) {
2174 MachineFunction &MF = DAG.getMachineFunction();
2176 // Check if the arguments are already laid out in the right way as
2177 // the caller's fixed stack objects.
2178 MachineFrameInfo *MFI = MF.getFrameInfo();
2179 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2180 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
2181 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
2183 ++i, ++realArgIdx) {
2184 CCValAssign &VA = ArgLocs[i];
2185 EVT RegVT = VA.getLocVT();
2186 SDValue Arg = OutVals[realArgIdx];
2187 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2188 if (VA.getLocInfo() == CCValAssign::Indirect)
2190 if (VA.needsCustom()) {
2191 // f64 and vector types are split into multiple registers or
2192 // register/stack-slot combinations. The types will not match
2193 // the registers; give up on memory f64 refs until we figure
2194 // out what to do about this.
2197 if (!ArgLocs[++i].isRegLoc())
2199 if (RegVT == MVT::v2f64) {
2200 if (!ArgLocs[++i].isRegLoc())
2202 if (!ArgLocs[++i].isRegLoc())
2205 } else if (!VA.isRegLoc()) {
2206 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2218 ARMTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
2219 MachineFunction &MF, bool isVarArg,
2220 const SmallVectorImpl<ISD::OutputArg> &Outs,
2221 LLVMContext &Context) const {
2222 SmallVector<CCValAssign, 16> RVLocs;
2223 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2224 return CCInfo.CheckReturn(Outs, CCAssignFnForNode(CallConv, /*Return=*/true,
2228 static SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
2229 SDLoc DL, SelectionDAG &DAG) {
2230 const MachineFunction &MF = DAG.getMachineFunction();
2231 const Function *F = MF.getFunction();
2233 StringRef IntKind = F->getFnAttribute("interrupt").getValueAsString();
2235 // See ARM ARM v7 B1.8.3. On exception entry LR is set to a possibly offset
2236 // version of the "preferred return address". These offsets affect the return
2237 // instruction if this is a return from PL1 without hypervisor extensions.
2238 // IRQ/FIQ: +4 "subs pc, lr, #4"
2239 // SWI: 0 "subs pc, lr, #0"
2240 // ABORT: +4 "subs pc, lr, #4"
2241 // UNDEF: +4/+2 "subs pc, lr, #0"
2242 // UNDEF varies depending on where the exception came from ARM or Thumb
2243 // mode. Alongside GCC, we throw our hands up in disgust and pretend it's 0.
2246 if (IntKind == "" || IntKind == "IRQ" || IntKind == "FIQ" ||
2249 else if (IntKind == "SWI" || IntKind == "UNDEF")
2252 report_fatal_error("Unsupported interrupt attribute. If present, value "
2253 "must be one of: IRQ, FIQ, SWI, ABORT or UNDEF");
2255 RetOps.insert(RetOps.begin() + 1,
2256 DAG.getConstant(LROffset, DL, MVT::i32, false));
2258 return DAG.getNode(ARMISD::INTRET_FLAG, DL, MVT::Other, RetOps);
2262 ARMTargetLowering::LowerReturn(SDValue Chain,
2263 CallingConv::ID CallConv, bool isVarArg,
2264 const SmallVectorImpl<ISD::OutputArg> &Outs,
2265 const SmallVectorImpl<SDValue> &OutVals,
2266 SDLoc dl, SelectionDAG &DAG) const {
2268 // CCValAssign - represent the assignment of the return value to a location.
2269 SmallVector<CCValAssign, 16> RVLocs;
2271 // CCState - Info about the registers and stack slots.
2272 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2273 *DAG.getContext(), Call);
2275 // Analyze outgoing return values.
2276 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
2280 SmallVector<SDValue, 4> RetOps;
2281 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2282 bool isLittleEndian = Subtarget->isLittle();
2284 MachineFunction &MF = DAG.getMachineFunction();
2285 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2286 AFI->setReturnRegsCount(RVLocs.size());
2288 // Copy the result values into the output registers.
2289 for (unsigned i = 0, realRVLocIdx = 0;
2291 ++i, ++realRVLocIdx) {
2292 CCValAssign &VA = RVLocs[i];
2293 assert(VA.isRegLoc() && "Can only return in registers!");
2295 SDValue Arg = OutVals[realRVLocIdx];
2297 switch (VA.getLocInfo()) {
2298 default: llvm_unreachable("Unknown loc info!");
2299 case CCValAssign::Full: break;
2300 case CCValAssign::BCvt:
2301 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2305 if (VA.needsCustom()) {
2306 if (VA.getLocVT() == MVT::v2f64) {
2307 // Extract the first half and return it in two registers.
2308 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2309 DAG.getConstant(0, dl, MVT::i32));
2310 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
2311 DAG.getVTList(MVT::i32, MVT::i32), Half);
2313 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2314 HalfGPRs.getValue(isLittleEndian ? 0 : 1),
2316 Flag = Chain.getValue(1);
2317 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2318 VA = RVLocs[++i]; // skip ahead to next loc
2319 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2320 HalfGPRs.getValue(isLittleEndian ? 1 : 0),
2322 Flag = Chain.getValue(1);
2323 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2324 VA = RVLocs[++i]; // skip ahead to next loc
2326 // Extract the 2nd half and fall through to handle it as an f64 value.
2327 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2328 DAG.getConstant(1, dl, MVT::i32));
2330 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
2332 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
2333 DAG.getVTList(MVT::i32, MVT::i32), Arg);
2334 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2335 fmrrd.getValue(isLittleEndian ? 0 : 1),
2337 Flag = Chain.getValue(1);
2338 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2339 VA = RVLocs[++i]; // skip ahead to next loc
2340 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2341 fmrrd.getValue(isLittleEndian ? 1 : 0),
2344 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
2346 // Guarantee that all emitted copies are
2347 // stuck together, avoiding something bad.
2348 Flag = Chain.getValue(1);
2349 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2352 // Update chain and glue.
2355 RetOps.push_back(Flag);
2357 // CPUs which aren't M-class use a special sequence to return from
2358 // exceptions (roughly, any instruction setting pc and cpsr simultaneously,
2359 // though we use "subs pc, lr, #N").
2361 // M-class CPUs actually use a normal return sequence with a special
2362 // (hardware-provided) value in LR, so the normal code path works.
2363 if (DAG.getMachineFunction().getFunction()->hasFnAttribute("interrupt") &&
2364 !Subtarget->isMClass()) {
2365 if (Subtarget->isThumb1Only())
2366 report_fatal_error("interrupt attribute is not supported in Thumb1");
2367 return LowerInterruptReturn(RetOps, dl, DAG);
2370 return DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, RetOps);
2373 bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2374 if (N->getNumValues() != 1)
2376 if (!N->hasNUsesOfValue(1, 0))
2379 SDValue TCChain = Chain;
2380 SDNode *Copy = *N->use_begin();
2381 if (Copy->getOpcode() == ISD::CopyToReg) {
2382 // If the copy has a glue operand, we conservatively assume it isn't safe to
2383 // perform a tail call.
2384 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2386 TCChain = Copy->getOperand(0);
2387 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) {
2388 SDNode *VMov = Copy;
2389 // f64 returned in a pair of GPRs.
2390 SmallPtrSet<SDNode*, 2> Copies;
2391 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2393 if (UI->getOpcode() != ISD::CopyToReg)
2397 if (Copies.size() > 2)
2400 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2402 SDValue UseChain = UI->getOperand(0);
2403 if (Copies.count(UseChain.getNode()))
2407 // We are at the top of this chain.
2408 // If the copy has a glue operand, we conservatively assume it
2409 // isn't safe to perform a tail call.
2410 if (UI->getOperand(UI->getNumOperands()-1).getValueType() == MVT::Glue)
2416 } else if (Copy->getOpcode() == ISD::BITCAST) {
2417 // f32 returned in a single GPR.
2418 if (!Copy->hasOneUse())
2420 Copy = *Copy->use_begin();
2421 if (Copy->getOpcode() != ISD::CopyToReg || !Copy->hasNUsesOfValue(1, 0))
2423 // If the copy has a glue operand, we conservatively assume it isn't safe to
2424 // perform a tail call.
2425 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2427 TCChain = Copy->getOperand(0);
2432 bool HasRet = false;
2433 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2435 if (UI->getOpcode() != ARMISD::RET_FLAG &&
2436 UI->getOpcode() != ARMISD::INTRET_FLAG)
2448 bool ARMTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2449 if (!Subtarget->supportsTailCall())
2453 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2454 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2460 // Trying to write a 64 bit value so need to split into two 32 bit values first,
2461 // and pass the lower and high parts through.
2462 static SDValue LowerWRITE_REGISTER(SDValue Op, SelectionDAG &DAG) {
2464 SDValue WriteValue = Op->getOperand(2);
2466 // This function is only supposed to be called for i64 type argument.
2467 assert(WriteValue.getValueType() == MVT::i64
2468 && "LowerWRITE_REGISTER called for non-i64 type argument.");
2470 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
2471 DAG.getConstant(0, DL, MVT::i32));
2472 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
2473 DAG.getConstant(1, DL, MVT::i32));
2474 SDValue Ops[] = { Op->getOperand(0), Op->getOperand(1), Lo, Hi };
2475 return DAG.getNode(ISD::WRITE_REGISTER, DL, MVT::Other, Ops);
2478 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
2479 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
2480 // one of the above mentioned nodes. It has to be wrapped because otherwise
2481 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
2482 // be used to form addressing mode. These wrapped nodes will be selected
2484 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
2485 EVT PtrVT = Op.getValueType();
2486 // FIXME there is no actual debug info here
2488 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2490 if (CP->isMachineConstantPoolEntry())
2491 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
2492 CP->getAlignment());
2494 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
2495 CP->getAlignment());
2496 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
2499 unsigned ARMTargetLowering::getJumpTableEncoding() const {
2500 return MachineJumpTableInfo::EK_Inline;
2503 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
2504 SelectionDAG &DAG) const {
2505 MachineFunction &MF = DAG.getMachineFunction();
2506 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2507 unsigned ARMPCLabelIndex = 0;
2509 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2510 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
2511 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2513 if (RelocM == Reloc::Static) {
2514 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
2516 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2517 ARMPCLabelIndex = AFI->createPICLabelUId();
2518 ARMConstantPoolValue *CPV =
2519 ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex,
2520 ARMCP::CPBlockAddress, PCAdj);
2521 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2523 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
2525 DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
2526 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
2527 false, false, false, 0);
2528 if (RelocM == Reloc::Static)
2530 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, DL, MVT::i32);
2531 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
2534 /// \brief Convert a TLS address reference into the correct sequence of loads
2535 /// and calls to compute the variable's address for Darwin, and return an
2536 /// SDValue containing the final node.
2538 /// Darwin only has one TLS scheme which must be capable of dealing with the
2539 /// fully general situation, in the worst case. This means:
2540 /// + "extern __thread" declaration.
2541 /// + Defined in a possibly unknown dynamic library.
2543 /// The general system is that each __thread variable has a [3 x i32] descriptor
2544 /// which contains information used by the runtime to calculate the address. The
2545 /// only part of this the compiler needs to know about is the first word, which
2546 /// contains a function pointer that must be called with the address of the
2547 /// entire descriptor in "r0".
2549 /// Since this descriptor may be in a different unit, in general access must
2550 /// proceed along the usual ARM rules. A common sequence to produce is:
2552 /// movw rT1, :lower16:_var$non_lazy_ptr
2553 /// movt rT1, :upper16:_var$non_lazy_ptr
2557 /// [...address now in r0...]
2559 ARMTargetLowering::LowerGlobalTLSAddressDarwin(SDValue Op,
2560 SelectionDAG &DAG) const {
2561 assert(Subtarget->isTargetDarwin() && "TLS only supported on Darwin");
2564 // First step is to get the address of the actua global symbol. This is where
2565 // the TLS descriptor lives.
2566 SDValue DescAddr = LowerGlobalAddressDarwin(Op, DAG);
2568 // The first entry in the descriptor is a function pointer that we must call
2569 // to obtain the address of the variable.
2570 SDValue Chain = DAG.getEntryNode();
2571 SDValue FuncTLVGet =
2572 DAG.getLoad(MVT::i32, DL, Chain, DescAddr,
2573 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
2574 false, true, true, 4);
2575 Chain = FuncTLVGet.getValue(1);
2577 MachineFunction &F = DAG.getMachineFunction();
2578 MachineFrameInfo *MFI = F.getFrameInfo();
2579 MFI->setAdjustsStack(true);
2581 // TLS calls preserve all registers except those that absolutely must be
2582 // trashed: R0 (it takes an argument), LR (it's a call) and CPSR (let's not be
2585 getTargetMachine().getSubtargetImpl(*F.getFunction())->getRegisterInfo();
2586 auto ARI = static_cast<const ARMRegisterInfo *>(TRI);
2587 const uint32_t *Mask = ARI->getTLSCallPreservedMask(DAG.getMachineFunction());
2589 // Finally, we can make the call. This is just a degenerate version of a
2590 // normal AArch64 call node: r0 takes the address of the descriptor, and
2591 // returns the address of the variable in this thread.
2592 Chain = DAG.getCopyToReg(Chain, DL, ARM::R0, DescAddr, SDValue());
2594 DAG.getNode(ARMISD::CALL, DL, DAG.getVTList(MVT::Other, MVT::Glue),
2595 Chain, FuncTLVGet, DAG.getRegister(ARM::R0, MVT::i32),
2596 DAG.getRegisterMask(Mask), Chain.getValue(1));
2597 return DAG.getCopyFromReg(Chain, DL, ARM::R0, MVT::i32, Chain.getValue(1));
2600 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
2602 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
2603 SelectionDAG &DAG) const {
2605 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2606 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2607 MachineFunction &MF = DAG.getMachineFunction();
2608 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2609 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2610 ARMConstantPoolValue *CPV =
2611 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2612 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
2613 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2614 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
2616 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
2617 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
2618 false, false, false, 0);
2619 SDValue Chain = Argument.getValue(1);
2621 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2622 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
2624 // call __tls_get_addr.
2627 Entry.Node = Argument;
2628 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
2629 Args.push_back(Entry);
2631 // FIXME: is there useful debug info available here?
2632 TargetLowering::CallLoweringInfo CLI(DAG);
2633 CLI.setDebugLoc(dl).setChain(Chain)
2634 .setCallee(CallingConv::C, Type::getInt32Ty(*DAG.getContext()),
2635 DAG.getExternalSymbol("__tls_get_addr", PtrVT), std::move(Args),
2638 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2639 return CallResult.first;
2642 // Lower ISD::GlobalTLSAddress using the "initial exec" or
2643 // "local exec" model.
2645 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
2647 TLSModel::Model model) const {
2648 const GlobalValue *GV = GA->getGlobal();
2651 SDValue Chain = DAG.getEntryNode();
2652 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2653 // Get the Thread Pointer
2654 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2656 if (model == TLSModel::InitialExec) {
2657 MachineFunction &MF = DAG.getMachineFunction();
2658 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2659 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2660 // Initial exec model.
2661 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2662 ARMConstantPoolValue *CPV =
2663 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2664 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF,
2666 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2667 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2668 Offset = DAG.getLoad(
2669 PtrVT, dl, Chain, Offset,
2670 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
2672 Chain = Offset.getValue(1);
2674 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2675 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
2677 Offset = DAG.getLoad(
2678 PtrVT, dl, Chain, Offset,
2679 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
2683 assert(model == TLSModel::LocalExec);
2684 ARMConstantPoolValue *CPV =
2685 ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF);
2686 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2687 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2688 Offset = DAG.getLoad(
2689 PtrVT, dl, Chain, Offset,
2690 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
2694 // The address of the thread local variable is the add of the thread
2695 // pointer with the offset of the variable.
2696 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
2700 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
2701 if (Subtarget->isTargetDarwin())
2702 return LowerGlobalTLSAddressDarwin(Op, DAG);
2704 // TODO: implement the "local dynamic" model
2705 assert(Subtarget->isTargetELF() && "Only ELF implemented here");
2706 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2707 if (DAG.getTarget().Options.EmulatedTLS)
2708 return LowerToTLSEmulatedModel(GA, DAG);
2710 TLSModel::Model model = getTargetMachine().getTLSModel(GA->getGlobal());
2713 case TLSModel::GeneralDynamic:
2714 case TLSModel::LocalDynamic:
2715 return LowerToTLSGeneralDynamicModel(GA, DAG);
2716 case TLSModel::InitialExec:
2717 case TLSModel::LocalExec:
2718 return LowerToTLSExecModels(GA, DAG, model);
2720 llvm_unreachable("bogus TLS model");
2723 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
2724 SelectionDAG &DAG) const {
2725 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2727 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2728 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2730 !(GV->hasHiddenVisibility() || GV->hasLocalLinkage());
2732 MachineFunction &MF = DAG.getMachineFunction();
2733 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2734 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2735 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2737 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2738 ARMConstantPoolValue *CPV = ARMConstantPoolConstant::Create(
2739 GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj,
2740 UseGOT_PREL ? ARMCP::GOT_PREL : ARMCP::no_modifier,
2741 /*AddCurrentAddress=*/UseGOT_PREL);
2742 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2743 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2744 SDValue Result = DAG.getLoad(
2745 PtrVT, dl, DAG.getEntryNode(), CPAddr,
2746 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
2748 SDValue Chain = Result.getValue(1);
2749 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2750 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2752 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
2753 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
2754 false, false, false, 0);
2758 // If we have T2 ops, we can materialize the address directly via movt/movw
2759 // pair. This is always cheaper.
2760 if (Subtarget->useMovt(DAG.getMachineFunction())) {
2762 // FIXME: Once remat is capable of dealing with instructions with register
2763 // operands, expand this into two nodes.
2764 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2765 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2767 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
2768 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2770 PtrVT, dl, DAG.getEntryNode(), CPAddr,
2771 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
2776 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
2777 SelectionDAG &DAG) const {
2778 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2780 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2781 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2783 if (Subtarget->useMovt(DAG.getMachineFunction()))
2786 // FIXME: Once remat is capable of dealing with instructions with register
2787 // operands, expand this into multiple nodes
2789 RelocM == Reloc::PIC_ ? ARMISD::WrapperPIC : ARMISD::Wrapper;
2791 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_NONLAZY);
2792 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT, G);
2794 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
2795 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
2796 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
2797 false, false, false, 0);
2801 SDValue ARMTargetLowering::LowerGlobalAddressWindows(SDValue Op,
2802 SelectionDAG &DAG) const {
2803 assert(Subtarget->isTargetWindows() && "non-Windows COFF is not supported");
2804 assert(Subtarget->useMovt(DAG.getMachineFunction()) &&
2805 "Windows on ARM expects to use movw/movt");
2807 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2808 const ARMII::TOF TargetFlags =
2809 (GV->hasDLLImportStorageClass() ? ARMII::MO_DLLIMPORT : ARMII::MO_NO_FLAG);
2810 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2816 // FIXME: Once remat is capable of dealing with instructions with register
2817 // operands, expand this into two nodes.
2818 Result = DAG.getNode(ARMISD::Wrapper, DL, PtrVT,
2819 DAG.getTargetGlobalAddress(GV, DL, PtrVT, /*Offset=*/0,
2821 if (GV->hasDLLImportStorageClass())
2822 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
2823 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
2824 false, false, false, 0);
2829 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
2831 SDValue Val = DAG.getConstant(0, dl, MVT::i32);
2832 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl,
2833 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
2834 Op.getOperand(1), Val);
2838 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
2840 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
2841 Op.getOperand(1), DAG.getConstant(0, dl, MVT::i32));
2844 SDValue ARMTargetLowering::LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op,
2845 SelectionDAG &DAG) const {
2847 return DAG.getNode(ARMISD::EH_SJLJ_SETUP_DISPATCH, dl, MVT::Other,
2852 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
2853 const ARMSubtarget *Subtarget) const {
2854 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2857 default: return SDValue(); // Don't custom lower most intrinsics.
2858 case Intrinsic::arm_rbit: {
2859 assert(Op.getOperand(1).getValueType() == MVT::i32 &&
2860 "RBIT intrinsic must have i32 type!");
2861 return DAG.getNode(ISD::BITREVERSE, dl, MVT::i32, Op.getOperand(1));
2863 case Intrinsic::arm_thread_pointer: {
2864 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2865 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2867 case Intrinsic::eh_sjlj_lsda: {
2868 MachineFunction &MF = DAG.getMachineFunction();
2869 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2870 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2871 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2872 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2874 unsigned PCAdj = (RelocM != Reloc::PIC_)
2875 ? 0 : (Subtarget->isThumb() ? 4 : 8);
2876 ARMConstantPoolValue *CPV =
2877 ARMConstantPoolConstant::Create(MF.getFunction(), ARMPCLabelIndex,
2878 ARMCP::CPLSDA, PCAdj);
2879 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2880 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2881 SDValue Result = DAG.getLoad(
2882 PtrVT, dl, DAG.getEntryNode(), CPAddr,
2883 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
2886 if (RelocM == Reloc::PIC_) {
2887 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2888 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2892 case Intrinsic::arm_neon_vmulls:
2893 case Intrinsic::arm_neon_vmullu: {
2894 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
2895 ? ARMISD::VMULLs : ARMISD::VMULLu;
2896 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
2897 Op.getOperand(1), Op.getOperand(2));
2899 case Intrinsic::arm_neon_vminnm:
2900 case Intrinsic::arm_neon_vmaxnm: {
2901 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminnm)
2902 ? ISD::FMINNUM : ISD::FMAXNUM;
2903 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
2904 Op.getOperand(1), Op.getOperand(2));
2906 case Intrinsic::arm_neon_vminu:
2907 case Intrinsic::arm_neon_vmaxu: {
2908 if (Op.getValueType().isFloatingPoint())
2910 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminu)
2911 ? ISD::UMIN : ISD::UMAX;
2912 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
2913 Op.getOperand(1), Op.getOperand(2));
2915 case Intrinsic::arm_neon_vmins:
2916 case Intrinsic::arm_neon_vmaxs: {
2917 // v{min,max}s is overloaded between signed integers and floats.
2918 if (!Op.getValueType().isFloatingPoint()) {
2919 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
2920 ? ISD::SMIN : ISD::SMAX;
2921 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
2922 Op.getOperand(1), Op.getOperand(2));
2924 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
2925 ? ISD::FMINNAN : ISD::FMAXNAN;
2926 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
2927 Op.getOperand(1), Op.getOperand(2));
2932 static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
2933 const ARMSubtarget *Subtarget) {
2934 // FIXME: handle "fence singlethread" more efficiently.
2936 if (!Subtarget->hasDataBarrier()) {
2937 // Some ARMv6 cpus can support data barriers with an mcr instruction.
2938 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
2940 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&
2941 "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!");
2942 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2943 DAG.getConstant(0, dl, MVT::i32));
2946 ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1));
2947 AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue());
2948 ARM_MB::MemBOpt Domain = ARM_MB::ISH;
2949 if (Subtarget->isMClass()) {
2950 // Only a full system barrier exists in the M-class architectures.
2951 Domain = ARM_MB::SY;
2952 } else if (Subtarget->isSwift() && Ord == Release) {
2953 // Swift happens to implement ISHST barriers in a way that's compatible with
2954 // Release semantics but weaker than ISH so we'd be fools not to use
2955 // it. Beware: other processors probably don't!
2956 Domain = ARM_MB::ISHST;
2959 return DAG.getNode(ISD::INTRINSIC_VOID, dl, MVT::Other, Op.getOperand(0),
2960 DAG.getConstant(Intrinsic::arm_dmb, dl, MVT::i32),
2961 DAG.getConstant(Domain, dl, MVT::i32));
2964 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
2965 const ARMSubtarget *Subtarget) {
2966 // ARM pre v5TE and Thumb1 does not have preload instructions.
2967 if (!(Subtarget->isThumb2() ||
2968 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
2969 // Just preserve the chain.
2970 return Op.getOperand(0);
2973 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
2975 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
2976 // ARMv7 with MP extension has PLDW.
2977 return Op.getOperand(0);
2979 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
2980 if (Subtarget->isThumb()) {
2982 isRead = ~isRead & 1;
2983 isData = ~isData & 1;
2986 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
2987 Op.getOperand(1), DAG.getConstant(isRead, dl, MVT::i32),
2988 DAG.getConstant(isData, dl, MVT::i32));
2991 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
2992 MachineFunction &MF = DAG.getMachineFunction();
2993 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
2995 // vastart just stores the address of the VarArgsFrameIndex slot into the
2996 // memory location argument.
2998 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
2999 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3000 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
3001 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
3002 MachinePointerInfo(SV), false, false, 0);
3006 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
3007 SDValue &Root, SelectionDAG &DAG,
3009 MachineFunction &MF = DAG.getMachineFunction();
3010 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3012 const TargetRegisterClass *RC;
3013 if (AFI->isThumb1OnlyFunction())
3014 RC = &ARM::tGPRRegClass;
3016 RC = &ARM::GPRRegClass;
3018 // Transform the arguments stored in physical registers into virtual ones.
3019 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3020 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
3023 if (NextVA.isMemLoc()) {
3024 MachineFrameInfo *MFI = MF.getFrameInfo();
3025 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
3027 // Create load node to retrieve arguments from the stack.
3028 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
3029 ArgValue2 = DAG.getLoad(
3030 MVT::i32, dl, Root, FIN,
3031 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), false,
3034 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
3035 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
3037 if (!Subtarget->isLittle())
3038 std::swap (ArgValue, ArgValue2);
3039 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
3042 // The remaining GPRs hold either the beginning of variable-argument
3043 // data, or the beginning of an aggregate passed by value (usually
3044 // byval). Either way, we allocate stack slots adjacent to the data
3045 // provided by our caller, and store the unallocated registers there.
3046 // If this is a variadic function, the va_list pointer will begin with
3047 // these values; otherwise, this reassembles a (byval) structure that
3048 // was split between registers and memory.
3049 // Return: The frame index registers were stored into.
3051 ARMTargetLowering::StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
3052 SDLoc dl, SDValue &Chain,
3053 const Value *OrigArg,
3054 unsigned InRegsParamRecordIdx,
3056 unsigned ArgSize) const {
3057 // Currently, two use-cases possible:
3058 // Case #1. Non-var-args function, and we meet first byval parameter.
3059 // Setup first unallocated register as first byval register;
3060 // eat all remained registers
3061 // (these two actions are performed by HandleByVal method).
3062 // Then, here, we initialize stack frame with
3063 // "store-reg" instructions.
3064 // Case #2. Var-args function, that doesn't contain byval parameters.
3065 // The same: eat all remained unallocated registers,
3066 // initialize stack frame.
3068 MachineFunction &MF = DAG.getMachineFunction();
3069 MachineFrameInfo *MFI = MF.getFrameInfo();
3070 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3071 unsigned RBegin, REnd;
3072 if (InRegsParamRecordIdx < CCInfo.getInRegsParamsCount()) {
3073 CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd);
3075 unsigned RBeginIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
3076 RBegin = RBeginIdx == 4 ? (unsigned)ARM::R4 : GPRArgRegs[RBeginIdx];
3081 ArgOffset = -4 * (ARM::R4 - RBegin);
3083 auto PtrVT = getPointerTy(DAG.getDataLayout());
3084 int FrameIndex = MFI->CreateFixedObject(ArgSize, ArgOffset, false);
3085 SDValue FIN = DAG.getFrameIndex(FrameIndex, PtrVT);
3087 SmallVector<SDValue, 4> MemOps;
3088 const TargetRegisterClass *RC =
3089 AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
3091 for (unsigned Reg = RBegin, i = 0; Reg < REnd; ++Reg, ++i) {
3092 unsigned VReg = MF.addLiveIn(Reg, RC);
3093 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3095 DAG.getStore(Val.getValue(1), dl, Val, FIN,
3096 MachinePointerInfo(OrigArg, 4 * i), false, false, 0);
3097 MemOps.push_back(Store);
3098 FIN = DAG.getNode(ISD::ADD, dl, PtrVT, FIN, DAG.getConstant(4, dl, PtrVT));
3101 if (!MemOps.empty())
3102 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3106 // Setup stack frame, the va_list pointer will start from.
3108 ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
3109 SDLoc dl, SDValue &Chain,
3111 unsigned TotalArgRegsSaveSize,
3112 bool ForceMutable) const {
3113 MachineFunction &MF = DAG.getMachineFunction();
3114 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3116 // Try to store any remaining integer argument regs
3117 // to their spots on the stack so that they may be loaded by deferencing
3118 // the result of va_next.
3119 // If there is no regs to be stored, just point address after last
3120 // argument passed via stack.
3121 int FrameIndex = StoreByValRegs(CCInfo, DAG, dl, Chain, nullptr,
3122 CCInfo.getInRegsParamsCount(),
3123 CCInfo.getNextStackOffset(), 4);
3124 AFI->setVarArgsFrameIndex(FrameIndex);
3128 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
3129 CallingConv::ID CallConv, bool isVarArg,
3130 const SmallVectorImpl<ISD::InputArg>
3132 SDLoc dl, SelectionDAG &DAG,
3133 SmallVectorImpl<SDValue> &InVals)
3135 MachineFunction &MF = DAG.getMachineFunction();
3136 MachineFrameInfo *MFI = MF.getFrameInfo();
3138 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3140 // Assign locations to all of the incoming arguments.
3141 SmallVector<CCValAssign, 16> ArgLocs;
3142 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
3143 *DAG.getContext(), Prologue);
3144 CCInfo.AnalyzeFormalArguments(Ins,
3145 CCAssignFnForNode(CallConv, /* Return*/ false,
3148 SmallVector<SDValue, 16> ArgValues;
3150 Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin();
3151 unsigned CurArgIdx = 0;
3153 // Initially ArgRegsSaveSize is zero.
3154 // Then we increase this value each time we meet byval parameter.
3155 // We also increase this value in case of varargs function.
3156 AFI->setArgRegsSaveSize(0);
3158 // Calculate the amount of stack space that we need to allocate to store
3159 // byval and variadic arguments that are passed in registers.
3160 // We need to know this before we allocate the first byval or variadic
3161 // argument, as they will be allocated a stack slot below the CFA (Canonical
3162 // Frame Address, the stack pointer at entry to the function).
3163 unsigned ArgRegBegin = ARM::R4;
3164 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3165 if (CCInfo.getInRegsParamsProcessed() >= CCInfo.getInRegsParamsCount())
3168 CCValAssign &VA = ArgLocs[i];
3169 unsigned Index = VA.getValNo();
3170 ISD::ArgFlagsTy Flags = Ins[Index].Flags;
3171 if (!Flags.isByVal())
3174 assert(VA.isMemLoc() && "unexpected byval pointer in reg");
3175 unsigned RBegin, REnd;
3176 CCInfo.getInRegsParamInfo(CCInfo.getInRegsParamsProcessed(), RBegin, REnd);
3177 ArgRegBegin = std::min(ArgRegBegin, RBegin);
3179 CCInfo.nextInRegsParam();
3181 CCInfo.rewindByValRegsInfo();
3183 int lastInsIndex = -1;
3184 if (isVarArg && MFI->hasVAStart()) {
3185 unsigned RegIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
3186 if (RegIdx != array_lengthof(GPRArgRegs))
3187 ArgRegBegin = std::min(ArgRegBegin, (unsigned)GPRArgRegs[RegIdx]);
3190 unsigned TotalArgRegsSaveSize = 4 * (ARM::R4 - ArgRegBegin);
3191 AFI->setArgRegsSaveSize(TotalArgRegsSaveSize);
3192 auto PtrVT = getPointerTy(DAG.getDataLayout());
3194 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3195 CCValAssign &VA = ArgLocs[i];
3196 if (Ins[VA.getValNo()].isOrigArg()) {
3197 std::advance(CurOrigArg,
3198 Ins[VA.getValNo()].getOrigArgIndex() - CurArgIdx);
3199 CurArgIdx = Ins[VA.getValNo()].getOrigArgIndex();
3201 // Arguments stored in registers.
3202 if (VA.isRegLoc()) {
3203 EVT RegVT = VA.getLocVT();
3205 if (VA.needsCustom()) {
3206 // f64 and vector types are split up into multiple registers or
3207 // combinations of registers and stack slots.
3208 if (VA.getLocVT() == MVT::v2f64) {
3209 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
3211 VA = ArgLocs[++i]; // skip ahead to next loc
3213 if (VA.isMemLoc()) {
3214 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
3215 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3216 ArgValue2 = DAG.getLoad(
3217 MVT::f64, dl, Chain, FIN,
3218 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3219 false, false, false, 0);
3221 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
3224 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
3225 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
3226 ArgValue, ArgValue1,
3227 DAG.getIntPtrConstant(0, dl));
3228 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
3229 ArgValue, ArgValue2,
3230 DAG.getIntPtrConstant(1, dl));
3232 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
3235 const TargetRegisterClass *RC;
3237 if (RegVT == MVT::f32)
3238 RC = &ARM::SPRRegClass;
3239 else if (RegVT == MVT::f64)
3240 RC = &ARM::DPRRegClass;
3241 else if (RegVT == MVT::v2f64)
3242 RC = &ARM::QPRRegClass;
3243 else if (RegVT == MVT::i32)
3244 RC = AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass
3245 : &ARM::GPRRegClass;
3247 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
3249 // Transform the arguments in physical registers into virtual ones.
3250 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3251 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
3254 // If this is an 8 or 16-bit value, it is really passed promoted
3255 // to 32 bits. Insert an assert[sz]ext to capture this, then
3256 // truncate to the right size.
3257 switch (VA.getLocInfo()) {
3258 default: llvm_unreachable("Unknown loc info!");
3259 case CCValAssign::Full: break;
3260 case CCValAssign::BCvt:
3261 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
3263 case CCValAssign::SExt:
3264 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
3265 DAG.getValueType(VA.getValVT()));
3266 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3268 case CCValAssign::ZExt:
3269 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
3270 DAG.getValueType(VA.getValVT()));
3271 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3275 InVals.push_back(ArgValue);
3277 } else { // VA.isRegLoc()
3280 assert(VA.isMemLoc());
3281 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
3283 int index = VA.getValNo();
3285 // Some Ins[] entries become multiple ArgLoc[] entries.
3286 // Process them only once.
3287 if (index != lastInsIndex)
3289 ISD::ArgFlagsTy Flags = Ins[index].Flags;
3290 // FIXME: For now, all byval parameter objects are marked mutable.
3291 // This can be changed with more analysis.
3292 // In case of tail call optimization mark all arguments mutable.
3293 // Since they could be overwritten by lowering of arguments in case of
3295 if (Flags.isByVal()) {
3296 assert(Ins[index].isOrigArg() &&
3297 "Byval arguments cannot be implicit");
3298 unsigned CurByValIndex = CCInfo.getInRegsParamsProcessed();
3300 int FrameIndex = StoreByValRegs(
3301 CCInfo, DAG, dl, Chain, &*CurOrigArg, CurByValIndex,
3302 VA.getLocMemOffset(), Flags.getByValSize());
3303 InVals.push_back(DAG.getFrameIndex(FrameIndex, PtrVT));
3304 CCInfo.nextInRegsParam();
3306 unsigned FIOffset = VA.getLocMemOffset();
3307 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
3310 // Create load nodes to retrieve arguments from the stack.
3311 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3312 InVals.push_back(DAG.getLoad(
3313 VA.getValVT(), dl, Chain, FIN,
3314 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3315 false, false, false, 0));
3317 lastInsIndex = index;
3323 if (isVarArg && MFI->hasVAStart())
3324 VarArgStyleRegisters(CCInfo, DAG, dl, Chain,
3325 CCInfo.getNextStackOffset(),
3326 TotalArgRegsSaveSize);
3328 AFI->setArgumentStackSize(CCInfo.getNextStackOffset());
3333 /// isFloatingPointZero - Return true if this is +0.0.
3334 static bool isFloatingPointZero(SDValue Op) {
3335 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
3336 return CFP->getValueAPF().isPosZero();
3337 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
3338 // Maybe this has already been legalized into the constant pool?
3339 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
3340 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
3341 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
3342 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
3343 return CFP->getValueAPF().isPosZero();
3345 } else if (Op->getOpcode() == ISD::BITCAST &&
3346 Op->getValueType(0) == MVT::f64) {
3347 // Handle (ISD::BITCAST (ARMISD::VMOVIMM (ISD::TargetConstant 0)) MVT::f64)
3348 // created by LowerConstantFP().
3349 SDValue BitcastOp = Op->getOperand(0);
3350 if (BitcastOp->getOpcode() == ARMISD::VMOVIMM &&
3351 isNullConstant(BitcastOp->getOperand(0)))
3357 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
3358 /// the given operands.
3360 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
3361 SDValue &ARMcc, SelectionDAG &DAG,
3363 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
3364 unsigned C = RHSC->getZExtValue();
3365 if (!isLegalICmpImmediate(C)) {
3366 // Constant does not fit, try adjusting it by one?
3371 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
3372 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
3373 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
3378 if (C != 0 && isLegalICmpImmediate(C-1)) {
3379 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
3380 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
3385 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
3386 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
3387 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
3392 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
3393 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
3394 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
3401 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3402 ARMISD::NodeType CompareType;
3405 CompareType = ARMISD::CMP;
3410 CompareType = ARMISD::CMPZ;
3413 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
3414 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
3417 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
3419 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
3421 assert(!Subtarget->isFPOnlySP() || RHS.getValueType() != MVT::f64);
3423 if (!isFloatingPointZero(RHS))
3424 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS);
3426 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS);
3427 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
3430 /// duplicateCmp - Glue values can have only one use, so this function
3431 /// duplicates a comparison node.
3433 ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
3434 unsigned Opc = Cmp.getOpcode();
3436 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
3437 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
3439 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation");
3440 Cmp = Cmp.getOperand(0);
3441 Opc = Cmp.getOpcode();
3442 if (Opc == ARMISD::CMPFP)
3443 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
3445 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT");
3446 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0));
3448 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
3451 std::pair<SDValue, SDValue>
3452 ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG,
3453 SDValue &ARMcc) const {
3454 assert(Op.getValueType() == MVT::i32 && "Unsupported value type");
3456 SDValue Value, OverflowCmp;
3457 SDValue LHS = Op.getOperand(0);
3458 SDValue RHS = Op.getOperand(1);
3461 // FIXME: We are currently always generating CMPs because we don't support
3462 // generating CMN through the backend. This is not as good as the natural
3463 // CMP case because it causes a register dependency and cannot be folded
3466 switch (Op.getOpcode()) {
3468 llvm_unreachable("Unknown overflow instruction!");
3470 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
3471 Value = DAG.getNode(ISD::ADD, dl, Op.getValueType(), LHS, RHS);
3472 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
3475 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
3476 Value = DAG.getNode(ISD::ADD, dl, Op.getValueType(), LHS, RHS);
3477 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
3480 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
3481 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
3482 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
3485 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
3486 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
3487 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
3491 return std::make_pair(Value, OverflowCmp);
3496 ARMTargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
3497 // Let legalize expand this if it isn't a legal type yet.
3498 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
3501 SDValue Value, OverflowCmp;
3503 std::tie(Value, OverflowCmp) = getARMXALUOOp(Op, DAG, ARMcc);
3504 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3506 // We use 0 and 1 as false and true values.
3507 SDValue TVal = DAG.getConstant(1, dl, MVT::i32);
3508 SDValue FVal = DAG.getConstant(0, dl, MVT::i32);
3509 EVT VT = Op.getValueType();
3511 SDValue Overflow = DAG.getNode(ARMISD::CMOV, dl, VT, TVal, FVal,
3512 ARMcc, CCR, OverflowCmp);
3514 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
3515 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
3519 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
3520 SDValue Cond = Op.getOperand(0);
3521 SDValue SelectTrue = Op.getOperand(1);
3522 SDValue SelectFalse = Op.getOperand(2);
3524 unsigned Opc = Cond.getOpcode();
3526 if (Cond.getResNo() == 1 &&
3527 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3528 Opc == ISD::USUBO)) {
3529 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
3532 SDValue Value, OverflowCmp;
3534 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
3535 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3536 EVT VT = Op.getValueType();
3538 return getCMOV(dl, VT, SelectTrue, SelectFalse, ARMcc, CCR,
3544 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
3545 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
3547 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
3548 const ConstantSDNode *CMOVTrue =
3549 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
3550 const ConstantSDNode *CMOVFalse =
3551 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
3553 if (CMOVTrue && CMOVFalse) {
3554 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
3555 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
3559 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
3561 False = SelectFalse;
3562 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
3567 if (True.getNode() && False.getNode()) {
3568 EVT VT = Op.getValueType();
3569 SDValue ARMcc = Cond.getOperand(2);
3570 SDValue CCR = Cond.getOperand(3);
3571 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
3572 assert(True.getValueType() == VT);
3573 return getCMOV(dl, VT, True, False, ARMcc, CCR, Cmp, DAG);
3578 // ARM's BooleanContents value is UndefinedBooleanContent. Mask out the
3579 // undefined bits before doing a full-word comparison with zero.
3580 Cond = DAG.getNode(ISD::AND, dl, Cond.getValueType(), Cond,
3581 DAG.getConstant(1, dl, Cond.getValueType()));
3583 return DAG.getSelectCC(dl, Cond,
3584 DAG.getConstant(0, dl, Cond.getValueType()),
3585 SelectTrue, SelectFalse, ISD::SETNE);
3588 static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
3589 bool &swpCmpOps, bool &swpVselOps) {
3590 // Start by selecting the GE condition code for opcodes that return true for
3592 if (CC == ISD::SETUGE || CC == ISD::SETOGE || CC == ISD::SETOLE ||
3594 CondCode = ARMCC::GE;
3596 // and GT for opcodes that return false for 'equality'.
3597 else if (CC == ISD::SETUGT || CC == ISD::SETOGT || CC == ISD::SETOLT ||
3599 CondCode = ARMCC::GT;
3601 // Since we are constrained to GE/GT, if the opcode contains 'less', we need
3602 // to swap the compare operands.
3603 if (CC == ISD::SETOLE || CC == ISD::SETULE || CC == ISD::SETOLT ||
3607 // Both GT and GE are ordered comparisons, and return false for 'unordered'.
3608 // If we have an unordered opcode, we need to swap the operands to the VSEL
3609 // instruction (effectively negating the condition).
3611 // This also has the effect of swapping which one of 'less' or 'greater'
3612 // returns true, so we also swap the compare operands. It also switches
3613 // whether we return true for 'equality', so we compensate by picking the
3614 // opposite condition code to our original choice.
3615 if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE ||
3616 CC == ISD::SETUGT) {
3617 swpCmpOps = !swpCmpOps;
3618 swpVselOps = !swpVselOps;
3619 CondCode = CondCode == ARMCC::GT ? ARMCC::GE : ARMCC::GT;
3622 // 'ordered' is 'anything but unordered', so use the VS condition code and
3623 // swap the VSEL operands.
3624 if (CC == ISD::SETO) {
3625 CondCode = ARMCC::VS;
3629 // 'unordered or not equal' is 'anything but equal', so use the EQ condition
3630 // code and swap the VSEL operands.
3631 if (CC == ISD::SETUNE) {
3632 CondCode = ARMCC::EQ;
3637 SDValue ARMTargetLowering::getCMOV(SDLoc dl, EVT VT, SDValue FalseVal,
3638 SDValue TrueVal, SDValue ARMcc, SDValue CCR,
3639 SDValue Cmp, SelectionDAG &DAG) const {
3640 if (Subtarget->isFPOnlySP() && VT == MVT::f64) {
3641 FalseVal = DAG.getNode(ARMISD::VMOVRRD, dl,
3642 DAG.getVTList(MVT::i32, MVT::i32), FalseVal);
3643 TrueVal = DAG.getNode(ARMISD::VMOVRRD, dl,
3644 DAG.getVTList(MVT::i32, MVT::i32), TrueVal);
3646 SDValue TrueLow = TrueVal.getValue(0);
3647 SDValue TrueHigh = TrueVal.getValue(1);
3648 SDValue FalseLow = FalseVal.getValue(0);
3649 SDValue FalseHigh = FalseVal.getValue(1);
3651 SDValue Low = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseLow, TrueLow,
3653 SDValue High = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseHigh, TrueHigh,
3654 ARMcc, CCR, duplicateCmp(Cmp, DAG));
3656 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Low, High);
3658 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,
3663 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
3664 EVT VT = Op.getValueType();
3665 SDValue LHS = Op.getOperand(0);
3666 SDValue RHS = Op.getOperand(1);
3667 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3668 SDValue TrueVal = Op.getOperand(2);
3669 SDValue FalseVal = Op.getOperand(3);
3672 if (Subtarget->isFPOnlySP() && LHS.getValueType() == MVT::f64) {
3673 DAG.getTargetLoweringInfo().softenSetCCOperands(DAG, MVT::f64, LHS, RHS, CC,
3676 // If softenSetCCOperands only returned one value, we should compare it to
3678 if (!RHS.getNode()) {
3679 RHS = DAG.getConstant(0, dl, LHS.getValueType());
3684 if (LHS.getValueType() == MVT::i32) {
3685 // Try to generate VSEL on ARMv8.
3686 // The VSEL instruction can't use all the usual ARM condition
3687 // codes: it only has two bits to select the condition code, so it's
3688 // constrained to use only GE, GT, VS and EQ.
3690 // To implement all the various ISD::SETXXX opcodes, we sometimes need to
3691 // swap the operands of the previous compare instruction (effectively
3692 // inverting the compare condition, swapping 'less' and 'greater') and
3693 // sometimes need to swap the operands to the VSEL (which inverts the
3694 // condition in the sense of firing whenever the previous condition didn't)
3695 if (Subtarget->hasFPARMv8() && (TrueVal.getValueType() == MVT::f32 ||
3696 TrueVal.getValueType() == MVT::f64)) {
3697 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3698 if (CondCode == ARMCC::LT || CondCode == ARMCC::LE ||
3699 CondCode == ARMCC::VC || CondCode == ARMCC::NE) {
3700 CC = ISD::getSetCCInverse(CC, true);
3701 std::swap(TrueVal, FalseVal);
3706 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3707 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3708 return getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
3711 ARMCC::CondCodes CondCode, CondCode2;
3712 FPCCToARMCC(CC, CondCode, CondCode2);
3714 // Try to generate VMAXNM/VMINNM on ARMv8.
3715 if (Subtarget->hasFPARMv8() && (TrueVal.getValueType() == MVT::f32 ||
3716 TrueVal.getValueType() == MVT::f64)) {
3717 bool swpCmpOps = false;
3718 bool swpVselOps = false;
3719 checkVSELConstraints(CC, CondCode, swpCmpOps, swpVselOps);
3721 if (CondCode == ARMCC::GT || CondCode == ARMCC::GE ||
3722 CondCode == ARMCC::VS || CondCode == ARMCC::EQ) {
3724 std::swap(LHS, RHS);
3726 std::swap(TrueVal, FalseVal);
3730 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
3731 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
3732 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3733 SDValue Result = getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
3734 if (CondCode2 != ARMCC::AL) {
3735 SDValue ARMcc2 = DAG.getConstant(CondCode2, dl, MVT::i32);
3736 // FIXME: Needs another CMP because flag can have but one use.
3737 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
3738 Result = getCMOV(dl, VT, Result, TrueVal, ARMcc2, CCR, Cmp2, DAG);
3743 /// canChangeToInt - Given the fp compare operand, return true if it is suitable
3744 /// to morph to an integer compare sequence.
3745 static bool canChangeToInt(SDValue Op, bool &SeenZero,
3746 const ARMSubtarget *Subtarget) {
3747 SDNode *N = Op.getNode();
3748 if (!N->hasOneUse())
3749 // Otherwise it requires moving the value from fp to integer registers.
3751 if (!N->getNumValues())
3753 EVT VT = Op.getValueType();
3754 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
3755 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
3756 // vmrs are very slow, e.g. cortex-a8.
3759 if (isFloatingPointZero(Op)) {
3763 return ISD::isNormalLoad(N);
3766 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
3767 if (isFloatingPointZero(Op))
3768 return DAG.getConstant(0, SDLoc(Op), MVT::i32);
3770 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
3771 return DAG.getLoad(MVT::i32, SDLoc(Op),
3772 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(),
3773 Ld->isVolatile(), Ld->isNonTemporal(),
3774 Ld->isInvariant(), Ld->getAlignment());
3776 llvm_unreachable("Unknown VFP cmp argument!");
3779 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
3780 SDValue &RetVal1, SDValue &RetVal2) {
3783 if (isFloatingPointZero(Op)) {
3784 RetVal1 = DAG.getConstant(0, dl, MVT::i32);
3785 RetVal2 = DAG.getConstant(0, dl, MVT::i32);
3789 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
3790 SDValue Ptr = Ld->getBasePtr();
3791 RetVal1 = DAG.getLoad(MVT::i32, dl,
3792 Ld->getChain(), Ptr,
3793 Ld->getPointerInfo(),
3794 Ld->isVolatile(), Ld->isNonTemporal(),
3795 Ld->isInvariant(), Ld->getAlignment());
3797 EVT PtrType = Ptr.getValueType();
3798 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
3799 SDValue NewPtr = DAG.getNode(ISD::ADD, dl,
3800 PtrType, Ptr, DAG.getConstant(4, dl, PtrType));
3801 RetVal2 = DAG.getLoad(MVT::i32, dl,
3802 Ld->getChain(), NewPtr,
3803 Ld->getPointerInfo().getWithOffset(4),
3804 Ld->isVolatile(), Ld->isNonTemporal(),
3805 Ld->isInvariant(), NewAlign);
3809 llvm_unreachable("Unknown VFP cmp argument!");
3812 /// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
3813 /// f32 and even f64 comparisons to integer ones.
3815 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
3816 SDValue Chain = Op.getOperand(0);
3817 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3818 SDValue LHS = Op.getOperand(2);
3819 SDValue RHS = Op.getOperand(3);
3820 SDValue Dest = Op.getOperand(4);
3823 bool LHSSeenZero = false;
3824 bool LHSOk = canChangeToInt(LHS, LHSSeenZero, Subtarget);
3825 bool RHSSeenZero = false;
3826 bool RHSOk = canChangeToInt(RHS, RHSSeenZero, Subtarget);
3827 if (LHSOk && RHSOk && (LHSSeenZero || RHSSeenZero)) {
3828 // If unsafe fp math optimization is enabled and there are no other uses of
3829 // the CMP operands, and the condition code is EQ or NE, we can optimize it
3830 // to an integer comparison.
3831 if (CC == ISD::SETOEQ)
3833 else if (CC == ISD::SETUNE)
3836 SDValue Mask = DAG.getConstant(0x7fffffff, dl, MVT::i32);
3838 if (LHS.getValueType() == MVT::f32) {
3839 LHS = DAG.getNode(ISD::AND, dl, MVT::i32,
3840 bitcastf32Toi32(LHS, DAG), Mask);
3841 RHS = DAG.getNode(ISD::AND, dl, MVT::i32,
3842 bitcastf32Toi32(RHS, DAG), Mask);
3843 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3844 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3845 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
3846 Chain, Dest, ARMcc, CCR, Cmp);
3851 expandf64Toi32(LHS, DAG, LHS1, LHS2);
3852 expandf64Toi32(RHS, DAG, RHS1, RHS2);
3853 LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask);
3854 RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask);
3855 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3856 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
3857 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
3858 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
3859 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops);
3865 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
3866 SDValue Chain = Op.getOperand(0);
3867 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3868 SDValue LHS = Op.getOperand(2);
3869 SDValue RHS = Op.getOperand(3);
3870 SDValue Dest = Op.getOperand(4);
3873 if (Subtarget->isFPOnlySP() && LHS.getValueType() == MVT::f64) {
3874 DAG.getTargetLoweringInfo().softenSetCCOperands(DAG, MVT::f64, LHS, RHS, CC,
3877 // If softenSetCCOperands only returned one value, we should compare it to
3879 if (!RHS.getNode()) {
3880 RHS = DAG.getConstant(0, dl, LHS.getValueType());
3885 if (LHS.getValueType() == MVT::i32) {
3887 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3888 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3889 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
3890 Chain, Dest, ARMcc, CCR, Cmp);
3893 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3895 if (getTargetMachine().Options.UnsafeFPMath &&
3896 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
3897 CC == ISD::SETNE || CC == ISD::SETUNE)) {
3898 SDValue Result = OptimizeVFPBrcond(Op, DAG);
3899 if (Result.getNode())
3903 ARMCC::CondCodes CondCode, CondCode2;
3904 FPCCToARMCC(CC, CondCode, CondCode2);
3906 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
3907 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
3908 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3909 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
3910 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
3911 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
3912 if (CondCode2 != ARMCC::AL) {
3913 ARMcc = DAG.getConstant(CondCode2, dl, MVT::i32);
3914 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
3915 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
3920 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
3921 SDValue Chain = Op.getOperand(0);
3922 SDValue Table = Op.getOperand(1);
3923 SDValue Index = Op.getOperand(2);
3926 EVT PTy = getPointerTy(DAG.getDataLayout());
3927 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
3928 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
3929 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI);
3930 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, dl, PTy));
3931 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
3932 if (Subtarget->isThumb2()) {
3933 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
3934 // which does another jump to the destination. This also makes it easier
3935 // to translate it to TBB / TBH later.
3936 // FIXME: This might not work if the function is extremely large.
3937 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
3938 Addr, Op.getOperand(2), JTI);
3940 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
3942 DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
3943 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()),
3944 false, false, false, 0);
3945 Chain = Addr.getValue(1);
3946 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
3947 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
3950 DAG.getLoad(PTy, dl, Chain, Addr,
3951 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()),
3952 false, false, false, 0);
3953 Chain = Addr.getValue(1);
3954 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
3958 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
3959 EVT VT = Op.getValueType();
3962 if (Op.getValueType().getVectorElementType() == MVT::i32) {
3963 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32)
3965 return DAG.UnrollVectorOp(Op.getNode());
3968 assert(Op.getOperand(0).getValueType() == MVT::v4f32 &&
3969 "Invalid type for custom lowering!");
3970 if (VT != MVT::v4i16)
3971 return DAG.UnrollVectorOp(Op.getNode());
3973 Op = DAG.getNode(Op.getOpcode(), dl, MVT::v4i32, Op.getOperand(0));
3974 return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
3977 SDValue ARMTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const {
3978 EVT VT = Op.getValueType();
3980 return LowerVectorFP_TO_INT(Op, DAG);
3981 if (Subtarget->isFPOnlySP() && Op.getOperand(0).getValueType() == MVT::f64) {
3983 if (Op.getOpcode() == ISD::FP_TO_SINT)
3984 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(),
3987 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(),
3989 return makeLibCall(DAG, LC, Op.getValueType(), Op.getOperand(0),
3990 /*isSigned*/ false, SDLoc(Op)).first;
3996 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
3997 EVT VT = Op.getValueType();
4000 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) {
4001 if (VT.getVectorElementType() == MVT::f32)
4003 return DAG.UnrollVectorOp(Op.getNode());
4006 assert(Op.getOperand(0).getValueType() == MVT::v4i16 &&
4007 "Invalid type for custom lowering!");
4008 if (VT != MVT::v4f32)
4009 return DAG.UnrollVectorOp(Op.getNode());
4013 switch (Op.getOpcode()) {
4014 default: llvm_unreachable("Invalid opcode!");
4015 case ISD::SINT_TO_FP:
4016 CastOpc = ISD::SIGN_EXTEND;
4017 Opc = ISD::SINT_TO_FP;
4019 case ISD::UINT_TO_FP:
4020 CastOpc = ISD::ZERO_EXTEND;
4021 Opc = ISD::UINT_TO_FP;
4025 Op = DAG.getNode(CastOpc, dl, MVT::v4i32, Op.getOperand(0));
4026 return DAG.getNode(Opc, dl, VT, Op);
4029 SDValue ARMTargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const {
4030 EVT VT = Op.getValueType();
4032 return LowerVectorINT_TO_FP(Op, DAG);
4033 if (Subtarget->isFPOnlySP() && Op.getValueType() == MVT::f64) {
4035 if (Op.getOpcode() == ISD::SINT_TO_FP)
4036 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(),
4039 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(),
4041 return makeLibCall(DAG, LC, Op.getValueType(), Op.getOperand(0),
4042 /*isSigned*/ false, SDLoc(Op)).first;
4048 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
4049 // Implement fcopysign with a fabs and a conditional fneg.
4050 SDValue Tmp0 = Op.getOperand(0);
4051 SDValue Tmp1 = Op.getOperand(1);
4053 EVT VT = Op.getValueType();
4054 EVT SrcVT = Tmp1.getValueType();
4055 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
4056 Tmp0.getOpcode() == ARMISD::VMOVDRR;
4057 bool UseNEON = !InGPR && Subtarget->hasNEON();
4060 // Use VBSL to copy the sign bit.
4061 unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80);
4062 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
4063 DAG.getTargetConstant(EncodedVal, dl, MVT::i32));
4064 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
4066 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT,
4067 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
4068 DAG.getConstant(32, dl, MVT::i32));
4069 else /*if (VT == MVT::f32)*/
4070 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
4071 if (SrcVT == MVT::f32) {
4072 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
4074 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT,
4075 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
4076 DAG.getConstant(32, dl, MVT::i32));
4077 } else if (VT == MVT::f32)
4078 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64,
4079 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
4080 DAG.getConstant(32, dl, MVT::i32));
4081 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
4082 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
4084 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff),
4086 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
4087 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
4088 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
4090 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
4091 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
4092 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
4093 if (VT == MVT::f32) {
4094 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
4095 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
4096 DAG.getConstant(0, dl, MVT::i32));
4098 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
4104 // Bitcast operand 1 to i32.
4105 if (SrcVT == MVT::f64)
4106 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
4108 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
4110 // Or in the signbit with integer operations.
4111 SDValue Mask1 = DAG.getConstant(0x80000000, dl, MVT::i32);
4112 SDValue Mask2 = DAG.getConstant(0x7fffffff, dl, MVT::i32);
4113 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
4114 if (VT == MVT::f32) {
4115 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
4116 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
4117 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4118 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
4121 // f64: Or the high part with signbit and then combine two parts.
4122 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
4124 SDValue Lo = Tmp0.getValue(0);
4125 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
4126 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
4127 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
4130 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
4131 MachineFunction &MF = DAG.getMachineFunction();
4132 MachineFrameInfo *MFI = MF.getFrameInfo();
4133 MFI->setReturnAddressIsTaken(true);
4135 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
4138 EVT VT = Op.getValueType();
4140 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4142 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
4143 SDValue Offset = DAG.getConstant(4, dl, MVT::i32);
4144 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
4145 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
4146 MachinePointerInfo(), false, false, false, 0);
4149 // Return LR, which contains the return address. Mark it an implicit live-in.
4150 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
4151 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
4154 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
4155 const ARMBaseRegisterInfo &ARI =
4156 *static_cast<const ARMBaseRegisterInfo*>(RegInfo);
4157 MachineFunction &MF = DAG.getMachineFunction();
4158 MachineFrameInfo *MFI = MF.getFrameInfo();
4159 MFI->setFrameAddressIsTaken(true);
4161 EVT VT = Op.getValueType();
4162 SDLoc dl(Op); // FIXME probably not meaningful
4163 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4164 unsigned FrameReg = ARI.getFrameRegister(MF);
4165 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
4167 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
4168 MachinePointerInfo(),
4169 false, false, false, 0);
4173 // FIXME? Maybe this could be a TableGen attribute on some registers and
4174 // this table could be generated automatically from RegInfo.
4175 unsigned ARMTargetLowering::getRegisterByName(const char* RegName, EVT VT,
4176 SelectionDAG &DAG) const {
4177 unsigned Reg = StringSwitch<unsigned>(RegName)
4178 .Case("sp", ARM::SP)
4182 report_fatal_error(Twine("Invalid register name \""
4183 + StringRef(RegName) + "\"."));
4186 // Result is 64 bit value so split into two 32 bit values and return as a
4188 static void ExpandREAD_REGISTER(SDNode *N, SmallVectorImpl<SDValue> &Results,
4189 SelectionDAG &DAG) {
4192 // This function is only supposed to be called for i64 type destination.
4193 assert(N->getValueType(0) == MVT::i64
4194 && "ExpandREAD_REGISTER called for non-i64 type result.");
4196 SDValue Read = DAG.getNode(ISD::READ_REGISTER, DL,
4197 DAG.getVTList(MVT::i32, MVT::i32, MVT::Other),
4201 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Read.getValue(0),
4203 Results.push_back(Read.getOperand(0));
4206 /// \p BC is a bitcast that is about to be turned into a VMOVDRR.
4207 /// When \p DstVT, the destination type of \p BC, is on the vector
4208 /// register bank and the source of bitcast, \p Op, operates on the same bank,
4209 /// it might be possible to combine them, such that everything stays on the
4210 /// vector register bank.
4211 /// \p return The node that would replace \p BT, if the combine
4213 static SDValue CombineVMOVDRRCandidateWithVecOp(const SDNode *BC,
4214 SelectionDAG &DAG) {
4215 SDValue Op = BC->getOperand(0);
4216 EVT DstVT = BC->getValueType(0);
4218 // The only vector instruction that can produce a scalar (remember,
4219 // since the bitcast was about to be turned into VMOVDRR, the source
4220 // type is i64) from a vector is EXTRACT_VECTOR_ELT.
4221 // Moreover, we can do this combine only if there is one use.
4222 // Finally, if the destination type is not a vector, there is not
4223 // much point on forcing everything on the vector bank.
4224 if (!DstVT.isVector() || Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
4228 // If the index is not constant, we will introduce an additional
4229 // multiply that will stick.
4230 // Give up in that case.
4231 ConstantSDNode *Index = dyn_cast<ConstantSDNode>(Op.getOperand(1));
4234 unsigned DstNumElt = DstVT.getVectorNumElements();
4236 // Compute the new index.
4237 const APInt &APIntIndex = Index->getAPIntValue();
4238 APInt NewIndex(APIntIndex.getBitWidth(), DstNumElt);
4239 NewIndex *= APIntIndex;
4240 // Check if the new constant index fits into i32.
4241 if (NewIndex.getBitWidth() > 32)
4244 // vMTy bitcast(i64 extractelt vNi64 src, i32 index) ->
4245 // vMTy extractsubvector vNxMTy (bitcast vNi64 src), i32 index*M)
4247 SDValue ExtractSrc = Op.getOperand(0);
4248 EVT VecVT = EVT::getVectorVT(
4249 *DAG.getContext(), DstVT.getScalarType(),
4250 ExtractSrc.getValueType().getVectorNumElements() * DstNumElt);
4251 SDValue BitCast = DAG.getNode(ISD::BITCAST, dl, VecVT, ExtractSrc);
4252 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DstVT, BitCast,
4253 DAG.getConstant(NewIndex.getZExtValue(), dl, MVT::i32));
4256 /// ExpandBITCAST - If the target supports VFP, this function is called to
4257 /// expand a bit convert where either the source or destination type is i64 to
4258 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
4259 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
4260 /// vectors), since the legalizer won't know what to do with that.
4261 static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) {
4262 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4264 SDValue Op = N->getOperand(0);
4266 // This function is only supposed to be called for i64 types, either as the
4267 // source or destination of the bit convert.
4268 EVT SrcVT = Op.getValueType();
4269 EVT DstVT = N->getValueType(0);
4270 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
4271 "ExpandBITCAST called for non-i64 type");
4273 // Turn i64->f64 into VMOVDRR.
4274 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
4275 // Do not force values to GPRs (this is what VMOVDRR does for the inputs)
4276 // if we can combine the bitcast with its source.
4277 if (SDValue Val = CombineVMOVDRRCandidateWithVecOp(N, DAG))
4280 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
4281 DAG.getConstant(0, dl, MVT::i32));
4282 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
4283 DAG.getConstant(1, dl, MVT::i32));
4284 return DAG.getNode(ISD::BITCAST, dl, DstVT,
4285 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
4288 // Turn f64->i64 into VMOVRRD.
4289 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
4291 if (DAG.getDataLayout().isBigEndian() && SrcVT.isVector() &&
4292 SrcVT.getVectorNumElements() > 1)
4293 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
4294 DAG.getVTList(MVT::i32, MVT::i32),
4295 DAG.getNode(ARMISD::VREV64, dl, SrcVT, Op));
4297 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
4298 DAG.getVTList(MVT::i32, MVT::i32), Op);
4299 // Merge the pieces into a single i64 value.
4300 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
4306 /// getZeroVector - Returns a vector of specified type with all zero elements.
4307 /// Zero vectors are used to represent vector negation and in those cases
4308 /// will be implemented with the NEON VNEG instruction. However, VNEG does
4309 /// not support i64 elements, so sometimes the zero vectors will need to be
4310 /// explicitly constructed. Regardless, use a canonical VMOV to create the
4312 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, SDLoc dl) {
4313 assert(VT.isVector() && "Expected a vector type");
4314 // The canonical modified immediate encoding of a zero vector is....0!
4315 SDValue EncodedVal = DAG.getTargetConstant(0, dl, MVT::i32);
4316 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
4317 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
4318 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
4321 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
4322 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
4323 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
4324 SelectionDAG &DAG) const {
4325 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4326 EVT VT = Op.getValueType();
4327 unsigned VTBits = VT.getSizeInBits();
4329 SDValue ShOpLo = Op.getOperand(0);
4330 SDValue ShOpHi = Op.getOperand(1);
4331 SDValue ShAmt = Op.getOperand(2);
4333 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
4335 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
4337 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
4338 DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
4339 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
4340 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
4341 DAG.getConstant(VTBits, dl, MVT::i32));
4342 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
4343 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4344 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
4346 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4347 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
4348 ISD::SETGE, ARMcc, DAG, dl);
4349 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
4350 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
4353 SDValue Ops[2] = { Lo, Hi };
4354 return DAG.getMergeValues(Ops, dl);
4357 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
4358 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
4359 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
4360 SelectionDAG &DAG) const {
4361 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4362 EVT VT = Op.getValueType();
4363 unsigned VTBits = VT.getSizeInBits();
4365 SDValue ShOpLo = Op.getOperand(0);
4366 SDValue ShOpHi = Op.getOperand(1);
4367 SDValue ShAmt = Op.getOperand(2);
4370 assert(Op.getOpcode() == ISD::SHL_PARTS);
4371 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
4372 DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
4373 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
4374 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
4375 DAG.getConstant(VTBits, dl, MVT::i32));
4376 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
4377 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
4379 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4380 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4381 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
4382 ISD::SETGE, ARMcc, DAG, dl);
4383 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
4384 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
4387 SDValue Ops[2] = { Lo, Hi };
4388 return DAG.getMergeValues(Ops, dl);
4391 SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
4392 SelectionDAG &DAG) const {
4393 // The rounding mode is in bits 23:22 of the FPSCR.
4394 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
4395 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
4396 // so that the shift + and get folded into a bitfield extract.
4398 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
4399 DAG.getConstant(Intrinsic::arm_get_fpscr, dl,
4401 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
4402 DAG.getConstant(1U << 22, dl, MVT::i32));
4403 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
4404 DAG.getConstant(22, dl, MVT::i32));
4405 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
4406 DAG.getConstant(3, dl, MVT::i32));
4409 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
4410 const ARMSubtarget *ST) {
4412 EVT VT = N->getValueType(0);
4413 if (VT.isVector()) {
4414 assert(ST->hasNEON());
4416 // Compute the least significant set bit: LSB = X & -X
4417 SDValue X = N->getOperand(0);
4418 SDValue NX = DAG.getNode(ISD::SUB, dl, VT, getZeroVector(VT, DAG, dl), X);
4419 SDValue LSB = DAG.getNode(ISD::AND, dl, VT, X, NX);
4421 EVT ElemTy = VT.getVectorElementType();
4423 if (ElemTy == MVT::i8) {
4424 // Compute with: cttz(x) = ctpop(lsb - 1)
4425 SDValue One = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
4426 DAG.getTargetConstant(1, dl, ElemTy));
4427 SDValue Bits = DAG.getNode(ISD::SUB, dl, VT, LSB, One);
4428 return DAG.getNode(ISD::CTPOP, dl, VT, Bits);
4431 if ((ElemTy == MVT::i16 || ElemTy == MVT::i32) &&
4432 (N->getOpcode() == ISD::CTTZ_ZERO_UNDEF)) {
4433 // Compute with: cttz(x) = (width - 1) - ctlz(lsb), if x != 0
4434 unsigned NumBits = ElemTy.getSizeInBits();
4435 SDValue WidthMinus1 =
4436 DAG.getNode(ARMISD::VMOVIMM, dl, VT,
4437 DAG.getTargetConstant(NumBits - 1, dl, ElemTy));
4438 SDValue CTLZ = DAG.getNode(ISD::CTLZ, dl, VT, LSB);
4439 return DAG.getNode(ISD::SUB, dl, VT, WidthMinus1, CTLZ);
4442 // Compute with: cttz(x) = ctpop(lsb - 1)
4444 // Since we can only compute the number of bits in a byte with vcnt.8, we
4445 // have to gather the result with pairwise addition (vpaddl) for i16, i32,
4450 if (ElemTy == MVT::i64) {
4451 // Load constant 0xffff'ffff'ffff'ffff to register.
4452 SDValue FF = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
4453 DAG.getTargetConstant(0x1eff, dl, MVT::i32));
4454 Bits = DAG.getNode(ISD::ADD, dl, VT, LSB, FF);
4456 SDValue One = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
4457 DAG.getTargetConstant(1, dl, ElemTy));
4458 Bits = DAG.getNode(ISD::SUB, dl, VT, LSB, One);
4461 // Count #bits with vcnt.8.
4462 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8;
4463 SDValue BitsVT8 = DAG.getNode(ISD::BITCAST, dl, VT8Bit, Bits);
4464 SDValue Cnt8 = DAG.getNode(ISD::CTPOP, dl, VT8Bit, BitsVT8);
4466 // Gather the #bits with vpaddl (pairwise add.)
4467 EVT VT16Bit = VT.is64BitVector() ? MVT::v4i16 : MVT::v8i16;
4468 SDValue Cnt16 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT16Bit,
4469 DAG.getTargetConstant(Intrinsic::arm_neon_vpaddlu, dl, MVT::i32),
4471 if (ElemTy == MVT::i16)
4474 EVT VT32Bit = VT.is64BitVector() ? MVT::v2i32 : MVT::v4i32;
4475 SDValue Cnt32 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT32Bit,
4476 DAG.getTargetConstant(Intrinsic::arm_neon_vpaddlu, dl, MVT::i32),
4478 if (ElemTy == MVT::i32)
4481 assert(ElemTy == MVT::i64);
4482 SDValue Cnt64 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
4483 DAG.getTargetConstant(Intrinsic::arm_neon_vpaddlu, dl, MVT::i32),
4488 if (!ST->hasV6T2Ops())
4491 SDValue rbit = DAG.getNode(ISD::BITREVERSE, dl, VT, N->getOperand(0));
4492 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
4495 /// getCTPOP16BitCounts - Returns a v8i8/v16i8 vector containing the bit-count
4496 /// for each 16-bit element from operand, repeated. The basic idea is to
4497 /// leverage vcnt to get the 8-bit counts, gather and add the results.
4499 /// Trace for v4i16:
4500 /// input = [v0 v1 v2 v3 ] (vi 16-bit element)
4501 /// cast: N0 = [w0 w1 w2 w3 w4 w5 w6 w7] (v0 = [w0 w1], wi 8-bit element)
4502 /// vcnt: N1 = [b0 b1 b2 b3 b4 b5 b6 b7] (bi = bit-count of 8-bit element wi)
4503 /// vrev: N2 = [b1 b0 b3 b2 b5 b4 b7 b6]
4504 /// [b0 b1 b2 b3 b4 b5 b6 b7]
4505 /// +[b1 b0 b3 b2 b5 b4 b7 b6]
4506 /// N3=N1+N2 = [k0 k0 k1 k1 k2 k2 k3 k3] (k0 = b0+b1 = bit-count of 16-bit v0,
4507 /// vuzp: = [k0 k1 k2 k3 k0 k1 k2 k3] each ki is 8-bits)
4508 static SDValue getCTPOP16BitCounts(SDNode *N, SelectionDAG &DAG) {
4509 EVT VT = N->getValueType(0);
4512 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8;
4513 SDValue N0 = DAG.getNode(ISD::BITCAST, DL, VT8Bit, N->getOperand(0));
4514 SDValue N1 = DAG.getNode(ISD::CTPOP, DL, VT8Bit, N0);
4515 SDValue N2 = DAG.getNode(ARMISD::VREV16, DL, VT8Bit, N1);
4516 SDValue N3 = DAG.getNode(ISD::ADD, DL, VT8Bit, N1, N2);
4517 return DAG.getNode(ARMISD::VUZP, DL, VT8Bit, N3, N3);
4520 /// lowerCTPOP16BitElements - Returns a v4i16/v8i16 vector containing the
4521 /// bit-count for each 16-bit element from the operand. We need slightly
4522 /// different sequencing for v4i16 and v8i16 to stay within NEON's available
4523 /// 64/128-bit registers.
4525 /// Trace for v4i16:
4526 /// input = [v0 v1 v2 v3 ] (vi 16-bit element)
4527 /// v8i8: BitCounts = [k0 k1 k2 k3 k0 k1 k2 k3 ] (ki is the bit-count of vi)
4528 /// v8i16:Extended = [k0 k1 k2 k3 k0 k1 k2 k3 ]
4529 /// v4i16:Extracted = [k0 k1 k2 k3 ]
4530 static SDValue lowerCTPOP16BitElements(SDNode *N, SelectionDAG &DAG) {
4531 EVT VT = N->getValueType(0);
4534 SDValue BitCounts = getCTPOP16BitCounts(N, DAG);
4535 if (VT.is64BitVector()) {
4536 SDValue Extended = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v8i16, BitCounts);
4537 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, Extended,
4538 DAG.getIntPtrConstant(0, DL));
4540 SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v8i8,
4541 BitCounts, DAG.getIntPtrConstant(0, DL));
4542 return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v8i16, Extracted);
4546 /// lowerCTPOP32BitElements - Returns a v2i32/v4i32 vector containing the
4547 /// bit-count for each 32-bit element from the operand. The idea here is
4548 /// to split the vector into 16-bit elements, leverage the 16-bit count
4549 /// routine, and then combine the results.
4551 /// Trace for v2i32 (v4i32 similar with Extracted/Extended exchanged):
4552 /// input = [v0 v1 ] (vi: 32-bit elements)
4553 /// Bitcast = [w0 w1 w2 w3 ] (wi: 16-bit elements, v0 = [w0 w1])
4554 /// Counts16 = [k0 k1 k2 k3 ] (ki: 16-bit elements, bit-count of wi)
4555 /// vrev: N0 = [k1 k0 k3 k2 ]
4557 /// N1 =+[k1 k0 k3 k2 ]
4559 /// N2 =+[k1 k3 k0 k2 ]
4561 /// Extended =+[k1 k3 k0 k2 ]
4563 /// Extracted=+[k1 k3 ]
4565 static SDValue lowerCTPOP32BitElements(SDNode *N, SelectionDAG &DAG) {
4566 EVT VT = N->getValueType(0);
4569 EVT VT16Bit = VT.is64BitVector() ? MVT::v4i16 : MVT::v8i16;
4571 SDValue Bitcast = DAG.getNode(ISD::BITCAST, DL, VT16Bit, N->getOperand(0));
4572 SDValue Counts16 = lowerCTPOP16BitElements(Bitcast.getNode(), DAG);
4573 SDValue N0 = DAG.getNode(ARMISD::VREV32, DL, VT16Bit, Counts16);
4574 SDValue N1 = DAG.getNode(ISD::ADD, DL, VT16Bit, Counts16, N0);
4575 SDValue N2 = DAG.getNode(ARMISD::VUZP, DL, VT16Bit, N1, N1);
4577 if (VT.is64BitVector()) {
4578 SDValue Extended = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v4i32, N2);
4579 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i32, Extended,
4580 DAG.getIntPtrConstant(0, DL));
4582 SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, N2,
4583 DAG.getIntPtrConstant(0, DL));
4584 return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v4i32, Extracted);
4588 static SDValue LowerCTPOP(SDNode *N, SelectionDAG &DAG,
4589 const ARMSubtarget *ST) {
4590 EVT VT = N->getValueType(0);
4592 assert(ST->hasNEON() && "Custom ctpop lowering requires NEON.");
4593 assert((VT == MVT::v2i32 || VT == MVT::v4i32 ||
4594 VT == MVT::v4i16 || VT == MVT::v8i16) &&
4595 "Unexpected type for custom ctpop lowering");
4597 if (VT.getVectorElementType() == MVT::i32)
4598 return lowerCTPOP32BitElements(N, DAG);
4600 return lowerCTPOP16BitElements(N, DAG);
4603 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
4604 const ARMSubtarget *ST) {
4605 EVT VT = N->getValueType(0);
4611 // Lower vector shifts on NEON to use VSHL.
4612 assert(ST->hasNEON() && "unexpected vector shift");
4614 // Left shifts translate directly to the vshiftu intrinsic.
4615 if (N->getOpcode() == ISD::SHL)
4616 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
4617 DAG.getConstant(Intrinsic::arm_neon_vshiftu, dl,
4619 N->getOperand(0), N->getOperand(1));
4621 assert((N->getOpcode() == ISD::SRA ||
4622 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
4624 // NEON uses the same intrinsics for both left and right shifts. For
4625 // right shifts, the shift amounts are negative, so negate the vector of
4627 EVT ShiftVT = N->getOperand(1).getValueType();
4628 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
4629 getZeroVector(ShiftVT, DAG, dl),
4631 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
4632 Intrinsic::arm_neon_vshifts :
4633 Intrinsic::arm_neon_vshiftu);
4634 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
4635 DAG.getConstant(vshiftInt, dl, MVT::i32),
4636 N->getOperand(0), NegatedCount);
4639 static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
4640 const ARMSubtarget *ST) {
4641 EVT VT = N->getValueType(0);
4644 // We can get here for a node like i32 = ISD::SHL i32, i64
4648 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
4649 "Unknown shift to lower!");
4651 // We only lower SRA, SRL of 1 here, all others use generic lowering.
4652 if (!isOneConstant(N->getOperand(1)))
4655 // If we are in thumb mode, we don't have RRX.
4656 if (ST->isThumb1Only()) return SDValue();
4658 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
4659 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
4660 DAG.getConstant(0, dl, MVT::i32));
4661 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
4662 DAG.getConstant(1, dl, MVT::i32));
4664 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
4665 // captures the result into a carry flag.
4666 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
4667 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), Hi);
4669 // The low part is an ARMISD::RRX operand, which shifts the carry in.
4670 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
4672 // Merge the pieces into a single i64 value.
4673 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
4676 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
4677 SDValue TmpOp0, TmpOp1;
4678 bool Invert = false;
4682 SDValue Op0 = Op.getOperand(0);
4683 SDValue Op1 = Op.getOperand(1);
4684 SDValue CC = Op.getOperand(2);
4685 EVT CmpVT = Op0.getValueType().changeVectorElementTypeToInteger();
4686 EVT VT = Op.getValueType();
4687 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
4690 if (CmpVT.getVectorElementType() == MVT::i64)
4691 // 64-bit comparisons are not legal. We've marked SETCC as non-Custom,
4692 // but it's possible that our operands are 64-bit but our result is 32-bit.
4693 // Bail in this case.
4696 if (Op1.getValueType().isFloatingPoint()) {
4697 switch (SetCCOpcode) {
4698 default: llvm_unreachable("Illegal FP comparison");
4700 case ISD::SETNE: Invert = true; // Fallthrough
4702 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
4704 case ISD::SETLT: Swap = true; // Fallthrough
4706 case ISD::SETGT: Opc = ARMISD::VCGT; break;
4708 case ISD::SETLE: Swap = true; // Fallthrough
4710 case ISD::SETGE: Opc = ARMISD::VCGE; break;
4711 case ISD::SETUGE: Swap = true; // Fallthrough
4712 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
4713 case ISD::SETUGT: Swap = true; // Fallthrough
4714 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
4715 case ISD::SETUEQ: Invert = true; // Fallthrough
4717 // Expand this to (OLT | OGT).
4721 Op0 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp1, TmpOp0);
4722 Op1 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp0, TmpOp1);
4724 case ISD::SETUO: Invert = true; // Fallthrough
4726 // Expand this to (OLT | OGE).
4730 Op0 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp1, TmpOp0);
4731 Op1 = DAG.getNode(ARMISD::VCGE, dl, CmpVT, TmpOp0, TmpOp1);
4735 // Integer comparisons.
4736 switch (SetCCOpcode) {
4737 default: llvm_unreachable("Illegal integer comparison");
4738 case ISD::SETNE: Invert = true;
4739 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
4740 case ISD::SETLT: Swap = true;
4741 case ISD::SETGT: Opc = ARMISD::VCGT; break;
4742 case ISD::SETLE: Swap = true;
4743 case ISD::SETGE: Opc = ARMISD::VCGE; break;
4744 case ISD::SETULT: Swap = true;
4745 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
4746 case ISD::SETULE: Swap = true;
4747 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
4750 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
4751 if (Opc == ARMISD::VCEQ) {
4754 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
4756 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
4759 // Ignore bitconvert.
4760 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST)
4761 AndOp = AndOp.getOperand(0);
4763 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
4765 Op0 = DAG.getNode(ISD::BITCAST, dl, CmpVT, AndOp.getOperand(0));
4766 Op1 = DAG.getNode(ISD::BITCAST, dl, CmpVT, AndOp.getOperand(1));
4773 std::swap(Op0, Op1);
4775 // If one of the operands is a constant vector zero, attempt to fold the
4776 // comparison to a specialized compare-against-zero form.
4778 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
4780 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) {
4781 if (Opc == ARMISD::VCGE)
4782 Opc = ARMISD::VCLEZ;
4783 else if (Opc == ARMISD::VCGT)
4784 Opc = ARMISD::VCLTZ;
4789 if (SingleOp.getNode()) {
4792 Result = DAG.getNode(ARMISD::VCEQZ, dl, CmpVT, SingleOp); break;
4794 Result = DAG.getNode(ARMISD::VCGEZ, dl, CmpVT, SingleOp); break;
4796 Result = DAG.getNode(ARMISD::VCLEZ, dl, CmpVT, SingleOp); break;
4798 Result = DAG.getNode(ARMISD::VCGTZ, dl, CmpVT, SingleOp); break;
4800 Result = DAG.getNode(ARMISD::VCLTZ, dl, CmpVT, SingleOp); break;
4802 Result = DAG.getNode(Opc, dl, CmpVT, Op0, Op1);
4805 Result = DAG.getNode(Opc, dl, CmpVT, Op0, Op1);
4808 Result = DAG.getSExtOrTrunc(Result, dl, VT);
4811 Result = DAG.getNOT(dl, Result, VT);
4816 /// isNEONModifiedImm - Check if the specified splat value corresponds to a
4817 /// valid vector constant for a NEON instruction with a "modified immediate"
4818 /// operand (e.g., VMOV). If so, return the encoded value.
4819 static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
4820 unsigned SplatBitSize, SelectionDAG &DAG,
4821 SDLoc dl, EVT &VT, bool is128Bits,
4822 NEONModImmType type) {
4823 unsigned OpCmode, Imm;
4825 // SplatBitSize is set to the smallest size that splats the vector, so a
4826 // zero vector will always have SplatBitSize == 8. However, NEON modified
4827 // immediate instructions others than VMOV do not support the 8-bit encoding
4828 // of a zero vector, and the default encoding of zero is supposed to be the
4833 switch (SplatBitSize) {
4835 if (type != VMOVModImm)
4837 // Any 1-byte value is OK. Op=0, Cmode=1110.
4838 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
4841 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
4845 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
4846 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
4847 if ((SplatBits & ~0xff) == 0) {
4848 // Value = 0x00nn: Op=x, Cmode=100x.
4853 if ((SplatBits & ~0xff00) == 0) {
4854 // Value = 0xnn00: Op=x, Cmode=101x.
4856 Imm = SplatBits >> 8;
4862 // NEON's 32-bit VMOV supports splat values where:
4863 // * only one byte is nonzero, or
4864 // * the least significant byte is 0xff and the second byte is nonzero, or
4865 // * the least significant 2 bytes are 0xff and the third is nonzero.
4866 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
4867 if ((SplatBits & ~0xff) == 0) {
4868 // Value = 0x000000nn: Op=x, Cmode=000x.
4873 if ((SplatBits & ~0xff00) == 0) {
4874 // Value = 0x0000nn00: Op=x, Cmode=001x.
4876 Imm = SplatBits >> 8;
4879 if ((SplatBits & ~0xff0000) == 0) {
4880 // Value = 0x00nn0000: Op=x, Cmode=010x.
4882 Imm = SplatBits >> 16;
4885 if ((SplatBits & ~0xff000000) == 0) {
4886 // Value = 0xnn000000: Op=x, Cmode=011x.
4888 Imm = SplatBits >> 24;
4892 // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC
4893 if (type == OtherModImm) return SDValue();
4895 if ((SplatBits & ~0xffff) == 0 &&
4896 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
4897 // Value = 0x0000nnff: Op=x, Cmode=1100.
4899 Imm = SplatBits >> 8;
4903 if ((SplatBits & ~0xffffff) == 0 &&
4904 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
4905 // Value = 0x00nnffff: Op=x, Cmode=1101.
4907 Imm = SplatBits >> 16;
4911 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
4912 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
4913 // VMOV.I32. A (very) minor optimization would be to replicate the value
4914 // and fall through here to test for a valid 64-bit splat. But, then the
4915 // caller would also need to check and handle the change in size.
4919 if (type != VMOVModImm)
4921 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
4922 uint64_t BitMask = 0xff;
4924 unsigned ImmMask = 1;
4926 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
4927 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
4930 } else if ((SplatBits & BitMask) != 0) {
4937 if (DAG.getDataLayout().isBigEndian())
4938 // swap higher and lower 32 bit word
4939 Imm = ((Imm & 0xf) << 4) | ((Imm & 0xf0) >> 4);
4941 // Op=1, Cmode=1110.
4943 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
4948 llvm_unreachable("unexpected size for isNEONModifiedImm");
4951 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
4952 return DAG.getTargetConstant(EncodedVal, dl, MVT::i32);
4955 SDValue ARMTargetLowering::LowerConstantFP(SDValue Op, SelectionDAG &DAG,
4956 const ARMSubtarget *ST) const {
4960 bool IsDouble = Op.getValueType() == MVT::f64;
4961 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Op);
4963 // Use the default (constant pool) lowering for double constants when we have
4965 if (IsDouble && Subtarget->isFPOnlySP())
4968 // Try splatting with a VMOV.f32...
4969 APFloat FPVal = CFP->getValueAPF();
4970 int ImmVal = IsDouble ? ARM_AM::getFP64Imm(FPVal) : ARM_AM::getFP32Imm(FPVal);
4973 if (IsDouble || !ST->useNEONForSinglePrecisionFP()) {
4974 // We have code in place to select a valid ConstantFP already, no need to
4979 // It's a float and we are trying to use NEON operations where
4980 // possible. Lower it to a splat followed by an extract.
4982 SDValue NewVal = DAG.getTargetConstant(ImmVal, DL, MVT::i32);
4983 SDValue VecConstant = DAG.getNode(ARMISD::VMOVFPIMM, DL, MVT::v2f32,
4985 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecConstant,
4986 DAG.getConstant(0, DL, MVT::i32));
4989 // The rest of our options are NEON only, make sure that's allowed before
4991 if (!ST->hasNEON() || (!IsDouble && !ST->useNEONForSinglePrecisionFP()))
4995 uint64_t iVal = FPVal.bitcastToAPInt().getZExtValue();
4997 // It wouldn't really be worth bothering for doubles except for one very
4998 // important value, which does happen to match: 0.0. So make sure we don't do
5000 if (IsDouble && (iVal & 0xffffffff) != (iVal >> 32))
5003 // Try a VMOV.i32 (FIXME: i8, i16, or i64 could work too).
5004 SDValue NewVal = isNEONModifiedImm(iVal & 0xffffffffU, 0, 32, DAG, SDLoc(Op),
5005 VMovVT, false, VMOVModImm);
5006 if (NewVal != SDValue()) {
5008 SDValue VecConstant = DAG.getNode(ARMISD::VMOVIMM, DL, VMovVT,
5011 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant);
5013 // It's a float: cast and extract a vector element.
5014 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32,
5016 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant,
5017 DAG.getConstant(0, DL, MVT::i32));
5020 // Finally, try a VMVN.i32
5021 NewVal = isNEONModifiedImm(~iVal & 0xffffffffU, 0, 32, DAG, SDLoc(Op), VMovVT,
5023 if (NewVal != SDValue()) {
5025 SDValue VecConstant = DAG.getNode(ARMISD::VMVNIMM, DL, VMovVT, NewVal);
5028 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant);
5030 // It's a float: cast and extract a vector element.
5031 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32,
5033 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant,
5034 DAG.getConstant(0, DL, MVT::i32));
5040 // check if an VEXT instruction can handle the shuffle mask when the
5041 // vector sources of the shuffle are the same.
5042 static bool isSingletonVEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
5043 unsigned NumElts = VT.getVectorNumElements();
5045 // Assume that the first shuffle index is not UNDEF. Fail if it is.
5051 // If this is a VEXT shuffle, the immediate value is the index of the first
5052 // element. The other shuffle indices must be the successive elements after
5054 unsigned ExpectedElt = Imm;
5055 for (unsigned i = 1; i < NumElts; ++i) {
5056 // Increment the expected index. If it wraps around, just follow it
5057 // back to index zero and keep going.
5059 if (ExpectedElt == NumElts)
5062 if (M[i] < 0) continue; // ignore UNDEF indices
5063 if (ExpectedElt != static_cast<unsigned>(M[i]))
5071 static bool isVEXTMask(ArrayRef<int> M, EVT VT,
5072 bool &ReverseVEXT, unsigned &Imm) {
5073 unsigned NumElts = VT.getVectorNumElements();
5074 ReverseVEXT = false;
5076 // Assume that the first shuffle index is not UNDEF. Fail if it is.
5082 // If this is a VEXT shuffle, the immediate value is the index of the first
5083 // element. The other shuffle indices must be the successive elements after
5085 unsigned ExpectedElt = Imm;
5086 for (unsigned i = 1; i < NumElts; ++i) {
5087 // Increment the expected index. If it wraps around, it may still be
5088 // a VEXT but the source vectors must be swapped.
5090 if (ExpectedElt == NumElts * 2) {
5095 if (M[i] < 0) continue; // ignore UNDEF indices
5096 if (ExpectedElt != static_cast<unsigned>(M[i]))
5100 // Adjust the index value if the source operands will be swapped.
5107 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
5108 /// instruction with the specified blocksize. (The order of the elements
5109 /// within each block of the vector is reversed.)
5110 static bool isVREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
5111 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
5112 "Only possible block sizes for VREV are: 16, 32, 64");
5114 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
5118 unsigned NumElts = VT.getVectorNumElements();
5119 unsigned BlockElts = M[0] + 1;
5120 // If the first shuffle index is UNDEF, be optimistic.
5122 BlockElts = BlockSize / EltSz;
5124 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
5127 for (unsigned i = 0; i < NumElts; ++i) {
5128 if (M[i] < 0) continue; // ignore UNDEF indices
5129 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
5136 static bool isVTBLMask(ArrayRef<int> M, EVT VT) {
5137 // We can handle <8 x i8> vector shuffles. If the index in the mask is out of
5138 // range, then 0 is placed into the resulting vector. So pretty much any mask
5139 // of 8 elements can work here.
5140 return VT == MVT::v8i8 && M.size() == 8;
5143 // Checks whether the shuffle mask represents a vector transpose (VTRN) by
5144 // checking that pairs of elements in the shuffle mask represent the same index
5145 // in each vector, incrementing the expected index by 2 at each step.
5146 // e.g. For v1,v2 of type v4i32 a valid shuffle mask is: [0, 4, 2, 6]
5147 // v1={a,b,c,d} => x=shufflevector v1, v2 shufflemask => x={a,e,c,g}
5149 // WhichResult gives the offset for each element in the mask based on which
5150 // of the two results it belongs to.
5152 // The transpose can be represented either as:
5153 // result1 = shufflevector v1, v2, result1_shuffle_mask
5154 // result2 = shufflevector v1, v2, result2_shuffle_mask
5155 // where v1/v2 and the shuffle masks have the same number of elements
5156 // (here WhichResult (see below) indicates which result is being checked)
5159 // results = shufflevector v1, v2, shuffle_mask
5160 // where both results are returned in one vector and the shuffle mask has twice
5161 // as many elements as v1/v2 (here WhichResult will always be 0 if true) here we
5162 // want to check the low half and high half of the shuffle mask as if it were
5164 static bool isVTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5165 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
5169 unsigned NumElts = VT.getVectorNumElements();
5170 if (M.size() != NumElts && M.size() != NumElts*2)
5173 // If the mask is twice as long as the input vector then we need to check the
5174 // upper and lower parts of the mask with a matching value for WhichResult
5175 // FIXME: A mask with only even values will be rejected in case the first
5176 // element is undefined, e.g. [-1, 4, 2, 6] will be rejected, because only
5177 // M[0] is used to determine WhichResult
5178 for (unsigned i = 0; i < M.size(); i += NumElts) {
5179 if (M.size() == NumElts * 2)
5180 WhichResult = i / NumElts;
5182 WhichResult = M[i] == 0 ? 0 : 1;
5183 for (unsigned j = 0; j < NumElts; j += 2) {
5184 if ((M[i+j] >= 0 && (unsigned) M[i+j] != j + WhichResult) ||
5185 (M[i+j+1] >= 0 && (unsigned) M[i+j+1] != j + NumElts + WhichResult))
5190 if (M.size() == NumElts*2)
5196 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
5197 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
5198 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
5199 static bool isVTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
5200 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
5204 unsigned NumElts = VT.getVectorNumElements();
5205 if (M.size() != NumElts && M.size() != NumElts*2)
5208 for (unsigned i = 0; i < M.size(); i += NumElts) {
5209 if (M.size() == NumElts * 2)
5210 WhichResult = i / NumElts;
5212 WhichResult = M[i] == 0 ? 0 : 1;
5213 for (unsigned j = 0; j < NumElts; j += 2) {
5214 if ((M[i+j] >= 0 && (unsigned) M[i+j] != j + WhichResult) ||
5215 (M[i+j+1] >= 0 && (unsigned) M[i+j+1] != j + WhichResult))
5220 if (M.size() == NumElts*2)
5226 // Checks whether the shuffle mask represents a vector unzip (VUZP) by checking
5227 // that the mask elements are either all even and in steps of size 2 or all odd
5228 // and in steps of size 2.
5229 // e.g. For v1,v2 of type v4i32 a valid shuffle mask is: [0, 2, 4, 6]
5230 // v1={a,b,c,d} => x=shufflevector v1, v2 shufflemask => x={a,c,e,g}
5232 // Requires similar checks to that of isVTRNMask with
5233 // respect the how results are returned.
5234 static bool isVUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5235 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
5239 unsigned NumElts = VT.getVectorNumElements();
5240 if (M.size() != NumElts && M.size() != NumElts*2)
5243 for (unsigned i = 0; i < M.size(); i += NumElts) {
5244 WhichResult = M[i] == 0 ? 0 : 1;
5245 for (unsigned j = 0; j < NumElts; ++j) {
5246 if (M[i+j] >= 0 && (unsigned) M[i+j] != 2 * j + WhichResult)
5251 if (M.size() == NumElts*2)
5254 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
5255 if (VT.is64BitVector() && EltSz == 32)
5261 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
5262 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
5263 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
5264 static bool isVUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
5265 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
5269 unsigned NumElts = VT.getVectorNumElements();
5270 if (M.size() != NumElts && M.size() != NumElts*2)
5273 unsigned Half = NumElts / 2;
5274 for (unsigned i = 0; i < M.size(); i += NumElts) {
5275 WhichResult = M[i] == 0 ? 0 : 1;
5276 for (unsigned j = 0; j < NumElts; j += Half) {
5277 unsigned Idx = WhichResult;
5278 for (unsigned k = 0; k < Half; ++k) {
5279 int MIdx = M[i + j + k];
5280 if (MIdx >= 0 && (unsigned) MIdx != Idx)
5287 if (M.size() == NumElts*2)
5290 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
5291 if (VT.is64BitVector() && EltSz == 32)
5297 // Checks whether the shuffle mask represents a vector zip (VZIP) by checking
5298 // that pairs of elements of the shufflemask represent the same index in each
5299 // vector incrementing sequentially through the vectors.
5300 // e.g. For v1,v2 of type v4i32 a valid shuffle mask is: [0, 4, 1, 5]
5301 // v1={a,b,c,d} => x=shufflevector v1, v2 shufflemask => x={a,e,b,f}
5303 // Requires similar checks to that of isVTRNMask with respect the how results
5305 static bool isVZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5306 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
5310 unsigned NumElts = VT.getVectorNumElements();
5311 if (M.size() != NumElts && M.size() != NumElts*2)
5314 for (unsigned i = 0; i < M.size(); i += NumElts) {
5315 WhichResult = M[i] == 0 ? 0 : 1;
5316 unsigned Idx = WhichResult * NumElts / 2;
5317 for (unsigned j = 0; j < NumElts; j += 2) {
5318 if ((M[i+j] >= 0 && (unsigned) M[i+j] != Idx) ||
5319 (M[i+j+1] >= 0 && (unsigned) M[i+j+1] != Idx + NumElts))
5325 if (M.size() == NumElts*2)
5328 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
5329 if (VT.is64BitVector() && EltSz == 32)
5335 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
5336 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
5337 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
5338 static bool isVZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
5339 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
5343 unsigned NumElts = VT.getVectorNumElements();
5344 if (M.size() != NumElts && M.size() != NumElts*2)
5347 for (unsigned i = 0; i < M.size(); i += NumElts) {
5348 WhichResult = M[i] == 0 ? 0 : 1;
5349 unsigned Idx = WhichResult * NumElts / 2;
5350 for (unsigned j = 0; j < NumElts; j += 2) {
5351 if ((M[i+j] >= 0 && (unsigned) M[i+j] != Idx) ||
5352 (M[i+j+1] >= 0 && (unsigned) M[i+j+1] != Idx))
5358 if (M.size() == NumElts*2)
5361 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
5362 if (VT.is64BitVector() && EltSz == 32)
5368 /// Check if \p ShuffleMask is a NEON two-result shuffle (VZIP, VUZP, VTRN),
5369 /// and return the corresponding ARMISD opcode if it is, or 0 if it isn't.
5370 static unsigned isNEONTwoResultShuffleMask(ArrayRef<int> ShuffleMask, EVT VT,
5371 unsigned &WhichResult,
5374 if (isVTRNMask(ShuffleMask, VT, WhichResult))
5375 return ARMISD::VTRN;
5376 if (isVUZPMask(ShuffleMask, VT, WhichResult))
5377 return ARMISD::VUZP;
5378 if (isVZIPMask(ShuffleMask, VT, WhichResult))
5379 return ARMISD::VZIP;
5382 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
5383 return ARMISD::VTRN;
5384 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
5385 return ARMISD::VUZP;
5386 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
5387 return ARMISD::VZIP;
5392 /// \return true if this is a reverse operation on an vector.
5393 static bool isReverseMask(ArrayRef<int> M, EVT VT) {
5394 unsigned NumElts = VT.getVectorNumElements();
5395 // Make sure the mask has the right size.
5396 if (NumElts != M.size())
5399 // Look for <15, ..., 3, -1, 1, 0>.
5400 for (unsigned i = 0; i != NumElts; ++i)
5401 if (M[i] >= 0 && M[i] != (int) (NumElts - 1 - i))
5407 // If N is an integer constant that can be moved into a register in one
5408 // instruction, return an SDValue of such a constant (will become a MOV
5409 // instruction). Otherwise return null.
5410 static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG,
5411 const ARMSubtarget *ST, SDLoc dl) {
5413 if (!isa<ConstantSDNode>(N))
5415 Val = cast<ConstantSDNode>(N)->getZExtValue();
5417 if (ST->isThumb1Only()) {
5418 if (Val <= 255 || ~Val <= 255)
5419 return DAG.getConstant(Val, dl, MVT::i32);
5421 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1)
5422 return DAG.getConstant(Val, dl, MVT::i32);
5427 // If this is a case we can't handle, return null and let the default
5428 // expansion code take care of it.
5429 SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
5430 const ARMSubtarget *ST) const {
5431 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
5433 EVT VT = Op.getValueType();
5435 APInt SplatBits, SplatUndef;
5436 unsigned SplatBitSize;
5438 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5439 if (SplatBitSize <= 64) {
5440 // Check if an immediate VMOV works.
5442 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
5443 SplatUndef.getZExtValue(), SplatBitSize,
5444 DAG, dl, VmovVT, VT.is128BitVector(),
5446 if (Val.getNode()) {
5447 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
5448 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
5451 // Try an immediate VMVN.
5452 uint64_t NegatedImm = (~SplatBits).getZExtValue();
5453 Val = isNEONModifiedImm(NegatedImm,
5454 SplatUndef.getZExtValue(), SplatBitSize,
5455 DAG, dl, VmovVT, VT.is128BitVector(),
5457 if (Val.getNode()) {
5458 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
5459 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
5462 // Use vmov.f32 to materialize other v2f32 and v4f32 splats.
5463 if ((VT == MVT::v2f32 || VT == MVT::v4f32) && SplatBitSize == 32) {
5464 int ImmVal = ARM_AM::getFP32Imm(SplatBits);
5466 SDValue Val = DAG.getTargetConstant(ImmVal, dl, MVT::i32);
5467 return DAG.getNode(ARMISD::VMOVFPIMM, dl, VT, Val);
5473 // Scan through the operands to see if only one value is used.
5475 // As an optimisation, even if more than one value is used it may be more
5476 // profitable to splat with one value then change some lanes.
5478 // Heuristically we decide to do this if the vector has a "dominant" value,
5479 // defined as splatted to more than half of the lanes.
5480 unsigned NumElts = VT.getVectorNumElements();
5481 bool isOnlyLowElement = true;
5482 bool usesOnlyOneValue = true;
5483 bool hasDominantValue = false;
5484 bool isConstant = true;
5486 // Map of the number of times a particular SDValue appears in the
5488 DenseMap<SDValue, unsigned> ValueCounts;
5490 for (unsigned i = 0; i < NumElts; ++i) {
5491 SDValue V = Op.getOperand(i);
5492 if (V.getOpcode() == ISD::UNDEF)
5495 isOnlyLowElement = false;
5496 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
5499 ValueCounts.insert(std::make_pair(V, 0));
5500 unsigned &Count = ValueCounts[V];
5502 // Is this value dominant? (takes up more than half of the lanes)
5503 if (++Count > (NumElts / 2)) {
5504 hasDominantValue = true;
5508 if (ValueCounts.size() != 1)
5509 usesOnlyOneValue = false;
5510 if (!Value.getNode() && ValueCounts.size() > 0)
5511 Value = ValueCounts.begin()->first;
5513 if (ValueCounts.size() == 0)
5514 return DAG.getUNDEF(VT);
5516 // Loads are better lowered with insert_vector_elt/ARMISD::BUILD_VECTOR.
5517 // Keep going if we are hitting this case.
5518 if (isOnlyLowElement && !ISD::isNormalLoad(Value.getNode()))
5519 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
5521 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5523 // Use VDUP for non-constant splats. For f32 constant splats, reduce to
5524 // i32 and try again.
5525 if (hasDominantValue && EltSize <= 32) {
5529 // If we are VDUPing a value that comes directly from a vector, that will
5530 // cause an unnecessary move to and from a GPR, where instead we could
5531 // just use VDUPLANE. We can only do this if the lane being extracted
5532 // is at a constant index, as the VDUP from lane instructions only have
5533 // constant-index forms.
5534 ConstantSDNode *constIndex;
5535 if (Value->getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5536 (constIndex = dyn_cast<ConstantSDNode>(Value->getOperand(1)))) {
5537 // We need to create a new undef vector to use for the VDUPLANE if the
5538 // size of the vector from which we get the value is different than the
5539 // size of the vector that we need to create. We will insert the element
5540 // such that the register coalescer will remove unnecessary copies.
5541 if (VT != Value->getOperand(0).getValueType()) {
5542 unsigned index = constIndex->getAPIntValue().getLimitedValue() %
5543 VT.getVectorNumElements();
5544 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT,
5545 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DAG.getUNDEF(VT),
5546 Value, DAG.getConstant(index, dl, MVT::i32)),
5547 DAG.getConstant(index, dl, MVT::i32));
5549 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT,
5550 Value->getOperand(0), Value->getOperand(1));
5552 N = DAG.getNode(ARMISD::VDUP, dl, VT, Value);
5554 if (!usesOnlyOneValue) {
5555 // The dominant value was splatted as 'N', but we now have to insert
5556 // all differing elements.
5557 for (unsigned I = 0; I < NumElts; ++I) {
5558 if (Op.getOperand(I) == Value)
5560 SmallVector<SDValue, 3> Ops;
5562 Ops.push_back(Op.getOperand(I));
5563 Ops.push_back(DAG.getConstant(I, dl, MVT::i32));
5564 N = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Ops);
5569 if (VT.getVectorElementType().isFloatingPoint()) {
5570 SmallVector<SDValue, 8> Ops;
5571 for (unsigned i = 0; i < NumElts; ++i)
5572 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32,
5574 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
5575 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
5576 Val = LowerBUILD_VECTOR(Val, DAG, ST);
5578 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5580 if (usesOnlyOneValue) {
5581 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
5582 if (isConstant && Val.getNode())
5583 return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
5587 // If all elements are constants and the case above didn't get hit, fall back
5588 // to the default expansion, which will generate a load from the constant
5593 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
5595 SDValue shuffle = ReconstructShuffle(Op, DAG);
5596 if (shuffle != SDValue())
5600 // Vectors with 32- or 64-bit elements can be built by directly assigning
5601 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
5602 // will be legalized.
5603 if (EltSize >= 32) {
5604 // Do the expansion with floating-point types, since that is what the VFP
5605 // registers are defined to use, and since i64 is not legal.
5606 EVT EltVT = EVT::getFloatingPointVT(EltSize);
5607 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
5608 SmallVector<SDValue, 8> Ops;
5609 for (unsigned i = 0; i < NumElts; ++i)
5610 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i)));
5611 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops);
5612 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5615 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
5616 // know the default expansion would otherwise fall back on something even
5617 // worse. For a vector with one or two non-undef values, that's
5618 // scalar_to_vector for the elements followed by a shuffle (provided the
5619 // shuffle is valid for the target) and materialization element by element
5620 // on the stack followed by a load for everything else.
5621 if (!isConstant && !usesOnlyOneValue) {
5622 SDValue Vec = DAG.getUNDEF(VT);
5623 for (unsigned i = 0 ; i < NumElts; ++i) {
5624 SDValue V = Op.getOperand(i);
5625 if (V.getOpcode() == ISD::UNDEF)
5627 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i32);
5628 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
5636 // Gather data to see if the operation can be modelled as a
5637 // shuffle in combination with VEXTs.
5638 SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
5639 SelectionDAG &DAG) const {
5640 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
5642 EVT VT = Op.getValueType();
5643 unsigned NumElts = VT.getVectorNumElements();
5645 struct ShuffleSourceInfo {
5650 // We may insert some combination of BITCASTs and VEXT nodes to force Vec to
5651 // be compatible with the shuffle we intend to construct. As a result
5652 // ShuffleVec will be some sliding window into the original Vec.
5655 // Code should guarantee that element i in Vec starts at element "WindowBase
5656 // + i * WindowScale in ShuffleVec".
5660 bool operator ==(SDValue OtherVec) { return Vec == OtherVec; }
5661 ShuffleSourceInfo(SDValue Vec)
5662 : Vec(Vec), MinElt(UINT_MAX), MaxElt(0), ShuffleVec(Vec), WindowBase(0),
5666 // First gather all vectors used as an immediate source for this BUILD_VECTOR
5668 SmallVector<ShuffleSourceInfo, 2> Sources;
5669 for (unsigned i = 0; i < NumElts; ++i) {
5670 SDValue V = Op.getOperand(i);
5671 if (V.getOpcode() == ISD::UNDEF)
5673 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
5674 // A shuffle can only come from building a vector from various
5675 // elements of other vectors.
5677 } else if (!isa<ConstantSDNode>(V.getOperand(1))) {
5678 // Furthermore, shuffles require a constant mask, whereas extractelts
5679 // accept variable indices.
5683 // Add this element source to the list if it's not already there.
5684 SDValue SourceVec = V.getOperand(0);
5685 auto Source = std::find(Sources.begin(), Sources.end(), SourceVec);
5686 if (Source == Sources.end())
5687 Source = Sources.insert(Sources.end(), ShuffleSourceInfo(SourceVec));
5689 // Update the minimum and maximum lane number seen.
5690 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
5691 Source->MinElt = std::min(Source->MinElt, EltNo);
5692 Source->MaxElt = std::max(Source->MaxElt, EltNo);
5695 // Currently only do something sane when at most two source vectors
5697 if (Sources.size() > 2)
5700 // Find out the smallest element size among result and two sources, and use
5701 // it as element size to build the shuffle_vector.
5702 EVT SmallestEltTy = VT.getVectorElementType();
5703 for (auto &Source : Sources) {
5704 EVT SrcEltTy = Source.Vec.getValueType().getVectorElementType();
5705 if (SrcEltTy.bitsLT(SmallestEltTy))
5706 SmallestEltTy = SrcEltTy;
5708 unsigned ResMultiplier =
5709 VT.getVectorElementType().getSizeInBits() / SmallestEltTy.getSizeInBits();
5710 NumElts = VT.getSizeInBits() / SmallestEltTy.getSizeInBits();
5711 EVT ShuffleVT = EVT::getVectorVT(*DAG.getContext(), SmallestEltTy, NumElts);
5713 // If the source vector is too wide or too narrow, we may nevertheless be able
5714 // to construct a compatible shuffle either by concatenating it with UNDEF or
5715 // extracting a suitable range of elements.
5716 for (auto &Src : Sources) {
5717 EVT SrcVT = Src.ShuffleVec.getValueType();
5719 if (SrcVT.getSizeInBits() == VT.getSizeInBits())
5722 // This stage of the search produces a source with the same element type as
5723 // the original, but with a total width matching the BUILD_VECTOR output.
5724 EVT EltVT = SrcVT.getVectorElementType();
5725 unsigned NumSrcElts = VT.getSizeInBits() / EltVT.getSizeInBits();
5726 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts);
5728 if (SrcVT.getSizeInBits() < VT.getSizeInBits()) {
5729 if (2 * SrcVT.getSizeInBits() != VT.getSizeInBits())
5731 // We can pad out the smaller vector for free, so if it's part of a
5734 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec,
5735 DAG.getUNDEF(Src.ShuffleVec.getValueType()));
5739 if (SrcVT.getSizeInBits() != 2 * VT.getSizeInBits())
5742 if (Src.MaxElt - Src.MinElt >= NumSrcElts) {
5743 // Span too large for a VEXT to cope
5747 if (Src.MinElt >= NumSrcElts) {
5748 // The extraction can just take the second half
5750 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
5751 DAG.getConstant(NumSrcElts, dl, MVT::i32));
5752 Src.WindowBase = -NumSrcElts;
5753 } else if (Src.MaxElt < NumSrcElts) {
5754 // The extraction can just take the first half
5756 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
5757 DAG.getConstant(0, dl, MVT::i32));
5759 // An actual VEXT is needed
5761 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
5762 DAG.getConstant(0, dl, MVT::i32));
5764 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
5765 DAG.getConstant(NumSrcElts, dl, MVT::i32));
5767 Src.ShuffleVec = DAG.getNode(ARMISD::VEXT, dl, DestVT, VEXTSrc1,
5769 DAG.getConstant(Src.MinElt, dl, MVT::i32));
5770 Src.WindowBase = -Src.MinElt;
5774 // Another possible incompatibility occurs from the vector element types. We
5775 // can fix this by bitcasting the source vectors to the same type we intend
5777 for (auto &Src : Sources) {
5778 EVT SrcEltTy = Src.ShuffleVec.getValueType().getVectorElementType();
5779 if (SrcEltTy == SmallestEltTy)
5781 assert(ShuffleVT.getVectorElementType() == SmallestEltTy);
5782 Src.ShuffleVec = DAG.getNode(ISD::BITCAST, dl, ShuffleVT, Src.ShuffleVec);
5783 Src.WindowScale = SrcEltTy.getSizeInBits() / SmallestEltTy.getSizeInBits();
5784 Src.WindowBase *= Src.WindowScale;
5787 // Final sanity check before we try to actually produce a shuffle.
5789 for (auto Src : Sources)
5790 assert(Src.ShuffleVec.getValueType() == ShuffleVT);
5793 // The stars all align, our next step is to produce the mask for the shuffle.
5794 SmallVector<int, 8> Mask(ShuffleVT.getVectorNumElements(), -1);
5795 int BitsPerShuffleLane = ShuffleVT.getVectorElementType().getSizeInBits();
5796 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
5797 SDValue Entry = Op.getOperand(i);
5798 if (Entry.getOpcode() == ISD::UNDEF)
5801 auto Src = std::find(Sources.begin(), Sources.end(), Entry.getOperand(0));
5802 int EltNo = cast<ConstantSDNode>(Entry.getOperand(1))->getSExtValue();
5804 // EXTRACT_VECTOR_ELT performs an implicit any_ext; BUILD_VECTOR an implicit
5805 // trunc. So only std::min(SrcBits, DestBits) actually get defined in this
5807 EVT OrigEltTy = Entry.getOperand(0).getValueType().getVectorElementType();
5808 int BitsDefined = std::min(OrigEltTy.getSizeInBits(),
5809 VT.getVectorElementType().getSizeInBits());
5810 int LanesDefined = BitsDefined / BitsPerShuffleLane;
5812 // This source is expected to fill ResMultiplier lanes of the final shuffle,
5813 // starting at the appropriate offset.
5814 int *LaneMask = &Mask[i * ResMultiplier];
5816 int ExtractBase = EltNo * Src->WindowScale + Src->WindowBase;
5817 ExtractBase += NumElts * (Src - Sources.begin());
5818 for (int j = 0; j < LanesDefined; ++j)
5819 LaneMask[j] = ExtractBase + j;
5822 // Final check before we try to produce nonsense...
5823 if (!isShuffleMaskLegal(Mask, ShuffleVT))
5826 // We can't handle more than two sources. This should have already
5827 // been checked before this point.
5828 assert(Sources.size() <= 2 && "Too many sources!");
5830 SDValue ShuffleOps[] = { DAG.getUNDEF(ShuffleVT), DAG.getUNDEF(ShuffleVT) };
5831 for (unsigned i = 0; i < Sources.size(); ++i)
5832 ShuffleOps[i] = Sources[i].ShuffleVec;
5834 SDValue Shuffle = DAG.getVectorShuffle(ShuffleVT, dl, ShuffleOps[0],
5835 ShuffleOps[1], &Mask[0]);
5836 return DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
5839 /// isShuffleMaskLegal - Targets can use this to indicate that they only
5840 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
5841 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
5842 /// are assumed to be legal.
5844 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
5846 if (VT.getVectorNumElements() == 4 &&
5847 (VT.is128BitVector() || VT.is64BitVector())) {
5848 unsigned PFIndexes[4];
5849 for (unsigned i = 0; i != 4; ++i) {
5853 PFIndexes[i] = M[i];
5856 // Compute the index in the perfect shuffle table.
5857 unsigned PFTableIndex =
5858 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5859 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5860 unsigned Cost = (PFEntry >> 30);
5866 bool ReverseVEXT, isV_UNDEF;
5867 unsigned Imm, WhichResult;
5869 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5870 return (EltSize >= 32 ||
5871 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
5872 isVREVMask(M, VT, 64) ||
5873 isVREVMask(M, VT, 32) ||
5874 isVREVMask(M, VT, 16) ||
5875 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
5876 isVTBLMask(M, VT) ||
5877 isNEONTwoResultShuffleMask(M, VT, WhichResult, isV_UNDEF) ||
5878 ((VT == MVT::v8i16 || VT == MVT::v16i8) && isReverseMask(M, VT)));
5881 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5882 /// the specified operations to build the shuffle.
5883 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5884 SDValue RHS, SelectionDAG &DAG,
5886 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5887 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5888 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5891 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5900 OP_VUZPL, // VUZP, left result
5901 OP_VUZPR, // VUZP, right result
5902 OP_VZIPL, // VZIP, left result
5903 OP_VZIPR, // VZIP, right result
5904 OP_VTRNL, // VTRN, left result
5905 OP_VTRNR // VTRN, right result
5908 if (OpNum == OP_COPY) {
5909 if (LHSID == (1*9+2)*9+3) return LHS;
5910 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5914 SDValue OpLHS, OpRHS;
5915 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5916 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5917 EVT VT = OpLHS.getValueType();
5920 default: llvm_unreachable("Unknown shuffle opcode!");
5922 // VREV divides the vector in half and swaps within the half.
5923 if (VT.getVectorElementType() == MVT::i32 ||
5924 VT.getVectorElementType() == MVT::f32)
5925 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
5926 // vrev <4 x i16> -> VREV32
5927 if (VT.getVectorElementType() == MVT::i16)
5928 return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS);
5929 // vrev <4 x i8> -> VREV16
5930 assert(VT.getVectorElementType() == MVT::i8);
5931 return DAG.getNode(ARMISD::VREV16, dl, VT, OpLHS);
5936 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
5937 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, dl, MVT::i32));
5941 return DAG.getNode(ARMISD::VEXT, dl, VT,
5943 DAG.getConstant(OpNum - OP_VEXT1 + 1, dl, MVT::i32));
5946 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
5947 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
5950 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
5951 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
5954 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
5955 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
5959 static SDValue LowerVECTOR_SHUFFLEv8i8(SDValue Op,
5960 ArrayRef<int> ShuffleMask,
5961 SelectionDAG &DAG) {
5962 // Check to see if we can use the VTBL instruction.
5963 SDValue V1 = Op.getOperand(0);
5964 SDValue V2 = Op.getOperand(1);
5967 SmallVector<SDValue, 8> VTBLMask;
5968 for (ArrayRef<int>::iterator
5969 I = ShuffleMask.begin(), E = ShuffleMask.end(); I != E; ++I)
5970 VTBLMask.push_back(DAG.getConstant(*I, DL, MVT::i32));
5972 if (V2.getNode()->getOpcode() == ISD::UNDEF)
5973 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1,
5974 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, VTBLMask));
5976 return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2,
5977 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, VTBLMask));
5980 static SDValue LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(SDValue Op,
5981 SelectionDAG &DAG) {
5983 SDValue OpLHS = Op.getOperand(0);
5984 EVT VT = OpLHS.getValueType();
5986 assert((VT == MVT::v8i16 || VT == MVT::v16i8) &&
5987 "Expect an v8i16/v16i8 type");
5988 OpLHS = DAG.getNode(ARMISD::VREV64, DL, VT, OpLHS);
5989 // For a v16i8 type: After the VREV, we have got <8, ...15, 8, ..., 0>. Now,
5990 // extract the first 8 bytes into the top double word and the last 8 bytes
5991 // into the bottom double word. The v8i16 case is similar.
5992 unsigned ExtractNum = (VT == MVT::v16i8) ? 8 : 4;
5993 return DAG.getNode(ARMISD::VEXT, DL, VT, OpLHS, OpLHS,
5994 DAG.getConstant(ExtractNum, DL, MVT::i32));
5997 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
5998 SDValue V1 = Op.getOperand(0);
5999 SDValue V2 = Op.getOperand(1);
6001 EVT VT = Op.getValueType();
6002 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
6004 // Convert shuffles that are directly supported on NEON to target-specific
6005 // DAG nodes, instead of keeping them as shuffles and matching them again
6006 // during code selection. This is more efficient and avoids the possibility
6007 // of inconsistencies between legalization and selection.
6008 // FIXME: floating-point vectors should be canonicalized to integer vectors
6009 // of the same time so that they get CSEd properly.
6010 ArrayRef<int> ShuffleMask = SVN->getMask();
6012 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
6013 if (EltSize <= 32) {
6014 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
6015 int Lane = SVN->getSplatIndex();
6016 // If this is undef splat, generate it via "just" vdup, if possible.
6017 if (Lane == -1) Lane = 0;
6019 // Test if V1 is a SCALAR_TO_VECTOR.
6020 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
6021 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
6023 // Test if V1 is a BUILD_VECTOR which is equivalent to a SCALAR_TO_VECTOR
6024 // (and probably will turn into a SCALAR_TO_VECTOR once legalization
6026 if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
6027 !isa<ConstantSDNode>(V1.getOperand(0))) {
6028 bool IsScalarToVector = true;
6029 for (unsigned i = 1, e = V1.getNumOperands(); i != e; ++i)
6030 if (V1.getOperand(i).getOpcode() != ISD::UNDEF) {
6031 IsScalarToVector = false;
6034 if (IsScalarToVector)
6035 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
6037 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
6038 DAG.getConstant(Lane, dl, MVT::i32));
6043 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
6046 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
6047 DAG.getConstant(Imm, dl, MVT::i32));
6050 if (isVREVMask(ShuffleMask, VT, 64))
6051 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
6052 if (isVREVMask(ShuffleMask, VT, 32))
6053 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
6054 if (isVREVMask(ShuffleMask, VT, 16))
6055 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
6057 if (V2->getOpcode() == ISD::UNDEF &&
6058 isSingletonVEXTMask(ShuffleMask, VT, Imm)) {
6059 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V1,
6060 DAG.getConstant(Imm, dl, MVT::i32));
6063 // Check for Neon shuffles that modify both input vectors in place.
6064 // If both results are used, i.e., if there are two shuffles with the same
6065 // source operands and with masks corresponding to both results of one of
6066 // these operations, DAG memoization will ensure that a single node is
6067 // used for both shuffles.
6068 unsigned WhichResult;
6070 if (unsigned ShuffleOpc = isNEONTwoResultShuffleMask(
6071 ShuffleMask, VT, WhichResult, isV_UNDEF)) {
6074 return DAG.getNode(ShuffleOpc, dl, DAG.getVTList(VT, VT), V1, V2)
6075 .getValue(WhichResult);
6078 // Also check for these shuffles through CONCAT_VECTORS: we canonicalize
6079 // shuffles that produce a result larger than their operands with:
6080 // shuffle(concat(v1, undef), concat(v2, undef))
6082 // shuffle(concat(v1, v2), undef)
6083 // because we can access quad vectors (see PerformVECTOR_SHUFFLECombine).
6085 // This is useful in the general case, but there are special cases where
6086 // native shuffles produce larger results: the two-result ops.
6088 // Look through the concat when lowering them:
6089 // shuffle(concat(v1, v2), undef)
6091 // concat(VZIP(v1, v2):0, :1)
6093 if (V1->getOpcode() == ISD::CONCAT_VECTORS &&
6094 V2->getOpcode() == ISD::UNDEF) {
6095 SDValue SubV1 = V1->getOperand(0);
6096 SDValue SubV2 = V1->getOperand(1);
6097 EVT SubVT = SubV1.getValueType();
6099 // We expect these to have been canonicalized to -1.
6100 assert(std::all_of(ShuffleMask.begin(), ShuffleMask.end(), [&](int i) {
6101 return i < (int)VT.getVectorNumElements();
6102 }) && "Unexpected shuffle index into UNDEF operand!");
6104 if (unsigned ShuffleOpc = isNEONTwoResultShuffleMask(
6105 ShuffleMask, SubVT, WhichResult, isV_UNDEF)) {
6108 assert((WhichResult == 0) &&
6109 "In-place shuffle of concat can only have one result!");
6110 SDValue Res = DAG.getNode(ShuffleOpc, dl, DAG.getVTList(SubVT, SubVT),
6112 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Res.getValue(0),
6118 // If the shuffle is not directly supported and it has 4 elements, use
6119 // the PerfectShuffle-generated table to synthesize it from other shuffles.
6120 unsigned NumElts = VT.getVectorNumElements();
6122 unsigned PFIndexes[4];
6123 for (unsigned i = 0; i != 4; ++i) {
6124 if (ShuffleMask[i] < 0)
6127 PFIndexes[i] = ShuffleMask[i];
6130 // Compute the index in the perfect shuffle table.
6131 unsigned PFTableIndex =
6132 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
6133 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
6134 unsigned Cost = (PFEntry >> 30);
6137 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
6140 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
6141 if (EltSize >= 32) {
6142 // Do the expansion with floating-point types, since that is what the VFP
6143 // registers are defined to use, and since i64 is not legal.
6144 EVT EltVT = EVT::getFloatingPointVT(EltSize);
6145 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
6146 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1);
6147 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2);
6148 SmallVector<SDValue, 8> Ops;
6149 for (unsigned i = 0; i < NumElts; ++i) {
6150 if (ShuffleMask[i] < 0)
6151 Ops.push_back(DAG.getUNDEF(EltVT));
6153 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
6154 ShuffleMask[i] < (int)NumElts ? V1 : V2,
6155 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
6158 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops);
6159 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
6162 if ((VT == MVT::v8i16 || VT == MVT::v16i8) && isReverseMask(ShuffleMask, VT))
6163 return LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(Op, DAG);
6165 if (VT == MVT::v8i8) {
6166 SDValue NewOp = LowerVECTOR_SHUFFLEv8i8(Op, ShuffleMask, DAG);
6167 if (NewOp.getNode())
6174 static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
6175 // INSERT_VECTOR_ELT is legal only for immediate indexes.
6176 SDValue Lane = Op.getOperand(2);
6177 if (!isa<ConstantSDNode>(Lane))
6183 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
6184 // EXTRACT_VECTOR_ELT is legal only for immediate indexes.
6185 SDValue Lane = Op.getOperand(1);
6186 if (!isa<ConstantSDNode>(Lane))
6189 SDValue Vec = Op.getOperand(0);
6190 if (Op.getValueType() == MVT::i32 &&
6191 Vec.getValueType().getVectorElementType().getSizeInBits() < 32) {
6193 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
6199 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6200 // The only time a CONCAT_VECTORS operation can have legal types is when
6201 // two 64-bit vectors are concatenated to a 128-bit vector.
6202 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
6203 "unexpected CONCAT_VECTORS");
6205 SDValue Val = DAG.getUNDEF(MVT::v2f64);
6206 SDValue Op0 = Op.getOperand(0);
6207 SDValue Op1 = Op.getOperand(1);
6208 if (Op0.getOpcode() != ISD::UNDEF)
6209 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
6210 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0),
6211 DAG.getIntPtrConstant(0, dl));
6212 if (Op1.getOpcode() != ISD::UNDEF)
6213 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
6214 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1),
6215 DAG.getIntPtrConstant(1, dl));
6216 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val);
6219 /// isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each
6220 /// element has been zero/sign-extended, depending on the isSigned parameter,
6221 /// from an integer type half its size.
6222 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
6224 // A v2i64 BUILD_VECTOR will have been legalized to a BITCAST from v4i32.
6225 EVT VT = N->getValueType(0);
6226 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) {
6227 SDNode *BVN = N->getOperand(0).getNode();
6228 if (BVN->getValueType(0) != MVT::v4i32 ||
6229 BVN->getOpcode() != ISD::BUILD_VECTOR)
6231 unsigned LoElt = DAG.getDataLayout().isBigEndian() ? 1 : 0;
6232 unsigned HiElt = 1 - LoElt;
6233 ConstantSDNode *Lo0 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt));
6234 ConstantSDNode *Hi0 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt));
6235 ConstantSDNode *Lo1 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt+2));
6236 ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2));
6237 if (!Lo0 || !Hi0 || !Lo1 || !Hi1)
6240 if (Hi0->getSExtValue() == Lo0->getSExtValue() >> 32 &&
6241 Hi1->getSExtValue() == Lo1->getSExtValue() >> 32)
6244 if (Hi0->isNullValue() && Hi1->isNullValue())
6250 if (N->getOpcode() != ISD::BUILD_VECTOR)
6253 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
6254 SDNode *Elt = N->getOperand(i).getNode();
6255 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
6256 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
6257 unsigned HalfSize = EltSize / 2;
6259 if (!isIntN(HalfSize, C->getSExtValue()))
6262 if (!isUIntN(HalfSize, C->getZExtValue()))
6273 /// isSignExtended - Check if a node is a vector value that is sign-extended
6274 /// or a constant BUILD_VECTOR with sign-extended elements.
6275 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
6276 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N))
6278 if (isExtendedBUILD_VECTOR(N, DAG, true))
6283 /// isZeroExtended - Check if a node is a vector value that is zero-extended
6284 /// or a constant BUILD_VECTOR with zero-extended elements.
6285 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
6286 if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N))
6288 if (isExtendedBUILD_VECTOR(N, DAG, false))
6293 static EVT getExtensionTo64Bits(const EVT &OrigVT) {
6294 if (OrigVT.getSizeInBits() >= 64)
6297 assert(OrigVT.isSimple() && "Expecting a simple value type");
6299 MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy;
6300 switch (OrigSimpleTy) {
6301 default: llvm_unreachable("Unexpected Vector Type");
6310 /// AddRequiredExtensionForVMULL - Add a sign/zero extension to extend the total
6311 /// value size to 64 bits. We need a 64-bit D register as an operand to VMULL.
6312 /// We insert the required extension here to get the vector to fill a D register.
6313 static SDValue AddRequiredExtensionForVMULL(SDValue N, SelectionDAG &DAG,
6316 unsigned ExtOpcode) {
6317 // The vector originally had a size of OrigTy. It was then extended to ExtTy.
6318 // We expect the ExtTy to be 128-bits total. If the OrigTy is less than
6319 // 64-bits we need to insert a new extension so that it will be 64-bits.
6320 assert(ExtTy.is128BitVector() && "Unexpected extension size");
6321 if (OrigTy.getSizeInBits() >= 64)
6324 // Must extend size to at least 64 bits to be used as an operand for VMULL.
6325 EVT NewVT = getExtensionTo64Bits(OrigTy);
6327 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N);
6330 /// SkipLoadExtensionForVMULL - return a load of the original vector size that
6331 /// does not do any sign/zero extension. If the original vector is less
6332 /// than 64 bits, an appropriate extension will be added after the load to
6333 /// reach a total size of 64 bits. We have to add the extension separately
6334 /// because ARM does not have a sign/zero extending load for vectors.
6335 static SDValue SkipLoadExtensionForVMULL(LoadSDNode *LD, SelectionDAG& DAG) {
6336 EVT ExtendedTy = getExtensionTo64Bits(LD->getMemoryVT());
6338 // The load already has the right type.
6339 if (ExtendedTy == LD->getMemoryVT())
6340 return DAG.getLoad(LD->getMemoryVT(), SDLoc(LD), LD->getChain(),
6341 LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(),
6342 LD->isNonTemporal(), LD->isInvariant(),
6343 LD->getAlignment());
6345 // We need to create a zextload/sextload. We cannot just create a load
6346 // followed by a zext/zext node because LowerMUL is also run during normal
6347 // operation legalization where we can't create illegal types.
6348 return DAG.getExtLoad(LD->getExtensionType(), SDLoc(LD), ExtendedTy,
6349 LD->getChain(), LD->getBasePtr(), LD->getPointerInfo(),
6350 LD->getMemoryVT(), LD->isVolatile(), LD->isInvariant(),
6351 LD->isNonTemporal(), LD->getAlignment());
6354 /// SkipExtensionForVMULL - For a node that is a SIGN_EXTEND, ZERO_EXTEND,
6355 /// extending load, or BUILD_VECTOR with extended elements, return the
6356 /// unextended value. The unextended vector should be 64 bits so that it can
6357 /// be used as an operand to a VMULL instruction. If the original vector size
6358 /// before extension is less than 64 bits we add a an extension to resize
6359 /// the vector to 64 bits.
6360 static SDValue SkipExtensionForVMULL(SDNode *N, SelectionDAG &DAG) {
6361 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
6362 return AddRequiredExtensionForVMULL(N->getOperand(0), DAG,
6363 N->getOperand(0)->getValueType(0),
6367 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
6368 return SkipLoadExtensionForVMULL(LD, DAG);
6370 // Otherwise, the value must be a BUILD_VECTOR. For v2i64, it will
6371 // have been legalized as a BITCAST from v4i32.
6372 if (N->getOpcode() == ISD::BITCAST) {
6373 SDNode *BVN = N->getOperand(0).getNode();
6374 assert(BVN->getOpcode() == ISD::BUILD_VECTOR &&
6375 BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR");
6376 unsigned LowElt = DAG.getDataLayout().isBigEndian() ? 1 : 0;
6377 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), MVT::v2i32,
6378 BVN->getOperand(LowElt), BVN->getOperand(LowElt+2));
6380 // Construct a new BUILD_VECTOR with elements truncated to half the size.
6381 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
6382 EVT VT = N->getValueType(0);
6383 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
6384 unsigned NumElts = VT.getVectorNumElements();
6385 MVT TruncVT = MVT::getIntegerVT(EltSize);
6386 SmallVector<SDValue, 8> Ops;
6388 for (unsigned i = 0; i != NumElts; ++i) {
6389 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
6390 const APInt &CInt = C->getAPIntValue();
6391 // Element types smaller than 32 bits are not legal, so use i32 elements.
6392 // The values are implicitly truncated so sext vs. zext doesn't matter.
6393 Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), dl, MVT::i32));
6395 return DAG.getNode(ISD::BUILD_VECTOR, dl,
6396 MVT::getVectorVT(TruncVT, NumElts), Ops);
6399 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
6400 unsigned Opcode = N->getOpcode();
6401 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
6402 SDNode *N0 = N->getOperand(0).getNode();
6403 SDNode *N1 = N->getOperand(1).getNode();
6404 return N0->hasOneUse() && N1->hasOneUse() &&
6405 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
6410 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
6411 unsigned Opcode = N->getOpcode();
6412 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
6413 SDNode *N0 = N->getOperand(0).getNode();
6414 SDNode *N1 = N->getOperand(1).getNode();
6415 return N0->hasOneUse() && N1->hasOneUse() &&
6416 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
6421 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
6422 // Multiplications are only custom-lowered for 128-bit vectors so that
6423 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
6424 EVT VT = Op.getValueType();
6425 assert(VT.is128BitVector() && VT.isInteger() &&
6426 "unexpected type for custom-lowering ISD::MUL");
6427 SDNode *N0 = Op.getOperand(0).getNode();
6428 SDNode *N1 = Op.getOperand(1).getNode();
6429 unsigned NewOpc = 0;
6431 bool isN0SExt = isSignExtended(N0, DAG);
6432 bool isN1SExt = isSignExtended(N1, DAG);
6433 if (isN0SExt && isN1SExt)
6434 NewOpc = ARMISD::VMULLs;
6436 bool isN0ZExt = isZeroExtended(N0, DAG);
6437 bool isN1ZExt = isZeroExtended(N1, DAG);
6438 if (isN0ZExt && isN1ZExt)
6439 NewOpc = ARMISD::VMULLu;
6440 else if (isN1SExt || isN1ZExt) {
6441 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
6442 // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
6443 if (isN1SExt && isAddSubSExt(N0, DAG)) {
6444 NewOpc = ARMISD::VMULLs;
6446 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
6447 NewOpc = ARMISD::VMULLu;
6449 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
6451 NewOpc = ARMISD::VMULLu;
6457 if (VT == MVT::v2i64)
6458 // Fall through to expand this. It is not legal.
6461 // Other vector multiplications are legal.
6466 // Legalize to a VMULL instruction.
6469 SDValue Op1 = SkipExtensionForVMULL(N1, DAG);
6471 Op0 = SkipExtensionForVMULL(N0, DAG);
6472 assert(Op0.getValueType().is64BitVector() &&
6473 Op1.getValueType().is64BitVector() &&
6474 "unexpected types for extended operands to VMULL");
6475 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
6478 // Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during
6479 // isel lowering to take advantage of no-stall back to back vmul + vmla.
6486 SDValue N00 = SkipExtensionForVMULL(N0->getOperand(0).getNode(), DAG);
6487 SDValue N01 = SkipExtensionForVMULL(N0->getOperand(1).getNode(), DAG);
6488 EVT Op1VT = Op1.getValueType();
6489 return DAG.getNode(N0->getOpcode(), DL, VT,
6490 DAG.getNode(NewOpc, DL, VT,
6491 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
6492 DAG.getNode(NewOpc, DL, VT,
6493 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
6497 LowerSDIV_v4i8(SDValue X, SDValue Y, SDLoc dl, SelectionDAG &DAG) {
6498 // TODO: Should this propagate fast-math-flags?
6501 // float4 xf = vcvt_f32_s32(vmovl_s16(a.lo));
6502 // float4 yf = vcvt_f32_s32(vmovl_s16(b.lo));
6503 X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X);
6504 Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y);
6505 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X);
6506 Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y);
6507 // Get reciprocal estimate.
6508 // float4 recip = vrecpeq_f32(yf);
6509 Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6510 DAG.getConstant(Intrinsic::arm_neon_vrecpe, dl, MVT::i32),
6512 // Because char has a smaller range than uchar, we can actually get away
6513 // without any newton steps. This requires that we use a weird bias
6514 // of 0xb000, however (again, this has been exhaustively tested).
6515 // float4 result = as_float4(as_int4(xf*recip) + 0xb000);
6516 X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y);
6517 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X);
6518 Y = DAG.getConstant(0xb000, dl, MVT::i32);
6519 Y = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Y, Y, Y, Y);
6520 X = DAG.getNode(ISD::ADD, dl, MVT::v4i32, X, Y);
6521 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X);
6522 // Convert back to short.
6523 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X);
6524 X = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, X);
6529 LowerSDIV_v4i16(SDValue N0, SDValue N1, SDLoc dl, SelectionDAG &DAG) {
6530 // TODO: Should this propagate fast-math-flags?
6533 // Convert to float.
6534 // float4 yf = vcvt_f32_s32(vmovl_s16(y));
6535 // float4 xf = vcvt_f32_s32(vmovl_s16(x));
6536 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0);
6537 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1);
6538 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
6539 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
6541 // Use reciprocal estimate and one refinement step.
6542 // float4 recip = vrecpeq_f32(yf);
6543 // recip *= vrecpsq_f32(yf, recip);
6544 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6545 DAG.getConstant(Intrinsic::arm_neon_vrecpe, dl, MVT::i32),
6547 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6548 DAG.getConstant(Intrinsic::arm_neon_vrecps, dl, MVT::i32),
6550 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
6551 // Because short has a smaller range than ushort, we can actually get away
6552 // with only a single newton step. This requires that we use a weird bias
6553 // of 89, however (again, this has been exhaustively tested).
6554 // float4 result = as_float4(as_int4(xf*recip) + 0x89);
6555 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
6556 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
6557 N1 = DAG.getConstant(0x89, dl, MVT::i32);
6558 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
6559 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
6560 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
6561 // Convert back to integer and return.
6562 // return vmovn_s32(vcvt_s32_f32(result));
6563 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
6564 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
6568 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
6569 EVT VT = Op.getValueType();
6570 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
6571 "unexpected type for custom-lowering ISD::SDIV");
6574 SDValue N0 = Op.getOperand(0);
6575 SDValue N1 = Op.getOperand(1);
6578 if (VT == MVT::v8i8) {
6579 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0);
6580 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1);
6582 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
6583 DAG.getIntPtrConstant(4, dl));
6584 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
6585 DAG.getIntPtrConstant(4, dl));
6586 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
6587 DAG.getIntPtrConstant(0, dl));
6588 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
6589 DAG.getIntPtrConstant(0, dl));
6591 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16
6592 N2 = LowerSDIV_v4i8(N2, N3, dl, DAG); // v4i16
6594 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
6595 N0 = LowerCONCAT_VECTORS(N0, DAG);
6597 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0);
6600 return LowerSDIV_v4i16(N0, N1, dl, DAG);
6603 static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG) {
6604 // TODO: Should this propagate fast-math-flags?
6605 EVT VT = Op.getValueType();
6606 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
6607 "unexpected type for custom-lowering ISD::UDIV");
6610 SDValue N0 = Op.getOperand(0);
6611 SDValue N1 = Op.getOperand(1);
6614 if (VT == MVT::v8i8) {
6615 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0);
6616 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1);
6618 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
6619 DAG.getIntPtrConstant(4, dl));
6620 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
6621 DAG.getIntPtrConstant(4, dl));
6622 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
6623 DAG.getIntPtrConstant(0, dl));
6624 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
6625 DAG.getIntPtrConstant(0, dl));
6627 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16
6628 N2 = LowerSDIV_v4i16(N2, N3, dl, DAG); // v4i16
6630 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
6631 N0 = LowerCONCAT_VECTORS(N0, DAG);
6633 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8,
6634 DAG.getConstant(Intrinsic::arm_neon_vqmovnsu, dl,
6640 // v4i16 sdiv ... Convert to float.
6641 // float4 yf = vcvt_f32_s32(vmovl_u16(y));
6642 // float4 xf = vcvt_f32_s32(vmovl_u16(x));
6643 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0);
6644 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1);
6645 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
6646 SDValue BN1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
6648 // Use reciprocal estimate and two refinement steps.
6649 // float4 recip = vrecpeq_f32(yf);
6650 // recip *= vrecpsq_f32(yf, recip);
6651 // recip *= vrecpsq_f32(yf, recip);
6652 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6653 DAG.getConstant(Intrinsic::arm_neon_vrecpe, dl, MVT::i32),
6655 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6656 DAG.getConstant(Intrinsic::arm_neon_vrecps, dl, MVT::i32),
6658 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
6659 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6660 DAG.getConstant(Intrinsic::arm_neon_vrecps, dl, MVT::i32),
6662 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
6663 // Simply multiplying by the reciprocal estimate can leave us a few ulps
6664 // too low, so we add 2 ulps (exhaustive testing shows that this is enough,
6665 // and that it will never cause us to return an answer too large).
6666 // float4 result = as_float4(as_int4(xf*recip) + 2);
6667 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
6668 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
6669 N1 = DAG.getConstant(2, dl, MVT::i32);
6670 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
6671 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
6672 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
6673 // Convert back to integer and return.
6674 // return vmovn_u32(vcvt_s32_f32(result));
6675 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
6676 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
6680 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
6681 EVT VT = Op.getNode()->getValueType(0);
6682 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
6685 bool ExtraOp = false;
6686 switch (Op.getOpcode()) {
6687 default: llvm_unreachable("Invalid code");
6688 case ISD::ADDC: Opc = ARMISD::ADDC; break;
6689 case ISD::ADDE: Opc = ARMISD::ADDE; ExtraOp = true; break;
6690 case ISD::SUBC: Opc = ARMISD::SUBC; break;
6691 case ISD::SUBE: Opc = ARMISD::SUBE; ExtraOp = true; break;
6695 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
6697 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
6698 Op.getOperand(1), Op.getOperand(2));
6701 SDValue ARMTargetLowering::LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const {
6702 assert(Subtarget->isTargetDarwin());
6704 // For iOS, we want to call an alternative entry point: __sincos_stret,
6705 // return values are passed via sret.
6707 SDValue Arg = Op.getOperand(0);
6708 EVT ArgVT = Arg.getValueType();
6709 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
6710 auto PtrVT = getPointerTy(DAG.getDataLayout());
6712 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6713 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6715 // Pair of floats / doubles used to pass the result.
6716 Type *RetTy = StructType::get(ArgTy, ArgTy, nullptr);
6717 auto &DL = DAG.getDataLayout();
6720 bool ShouldUseSRet = Subtarget->isAPCS_ABI();
6722 if (ShouldUseSRet) {
6723 // Create stack object for sret.
6724 const uint64_t ByteSize = DL.getTypeAllocSize(RetTy);
6725 const unsigned StackAlign = DL.getPrefTypeAlignment(RetTy);
6726 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign, false);
6727 SRet = DAG.getFrameIndex(FrameIdx, TLI.getPointerTy(DL));
6731 Entry.Ty = RetTy->getPointerTo();
6732 Entry.isSExt = false;
6733 Entry.isZExt = false;
6734 Entry.isSRet = true;
6735 Args.push_back(Entry);
6736 RetTy = Type::getVoidTy(*DAG.getContext());
6742 Entry.isSExt = false;
6743 Entry.isZExt = false;
6744 Args.push_back(Entry);
6746 const char *LibcallName =
6747 (ArgVT == MVT::f64) ? "__sincos_stret" : "__sincosf_stret";
6749 (ArgVT == MVT::f64) ? RTLIB::SINCOS_F64 : RTLIB::SINCOS_F32;
6750 CallingConv::ID CC = getLibcallCallingConv(LC);
6751 SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy(DL));
6753 TargetLowering::CallLoweringInfo CLI(DAG);
6755 .setChain(DAG.getEntryNode())
6756 .setCallee(CC, RetTy, Callee, std::move(Args), 0)
6757 .setDiscardResult(ShouldUseSRet);
6758 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
6761 return CallResult.first;
6763 SDValue LoadSin = DAG.getLoad(ArgVT, dl, CallResult.second, SRet,
6764 MachinePointerInfo(), false, false, false, 0);
6766 // Address of cos field.
6767 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, SRet,
6768 DAG.getIntPtrConstant(ArgVT.getStoreSize(), dl));
6769 SDValue LoadCos = DAG.getLoad(ArgVT, dl, LoadSin.getValue(1), Add,
6770 MachinePointerInfo(), false, false, false, 0);
6772 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
6773 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys,
6774 LoadSin.getValue(0), LoadCos.getValue(0));
6777 SDValue ARMTargetLowering::LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG,
6779 SDValue &Chain) const {
6780 EVT VT = Op.getValueType();
6781 assert((VT == MVT::i32 || VT == MVT::i64) &&
6782 "unexpected type for custom lowering DIV");
6785 const auto &DL = DAG.getDataLayout();
6786 const auto &TLI = DAG.getTargetLoweringInfo();
6788 const char *Name = nullptr;
6790 Name = (VT == MVT::i32) ? "__rt_sdiv" : "__rt_sdiv64";
6792 Name = (VT == MVT::i32) ? "__rt_udiv" : "__rt_udiv64";
6794 SDValue ES = DAG.getExternalSymbol(Name, TLI.getPointerTy(DL));
6796 ARMTargetLowering::ArgListTy Args;
6798 for (auto AI : {1, 0}) {
6800 Arg.Node = Op.getOperand(AI);
6801 Arg.Ty = Arg.Node.getValueType().getTypeForEVT(*DAG.getContext());
6802 Args.push_back(Arg);
6805 CallLoweringInfo CLI(DAG);
6808 .setCallee(CallingConv::ARM_AAPCS_VFP, VT.getTypeForEVT(*DAG.getContext()),
6809 ES, std::move(Args), 0);
6811 return LowerCallTo(CLI).first;
6814 SDValue ARMTargetLowering::LowerDIV_Windows(SDValue Op, SelectionDAG &DAG,
6815 bool Signed) const {
6816 assert(Op.getValueType() == MVT::i32 &&
6817 "unexpected type for custom lowering DIV");
6820 SDValue DBZCHK = DAG.getNode(ARMISD::WIN__DBZCHK, dl, MVT::Other,
6821 DAG.getEntryNode(), Op.getOperand(1));
6823 return LowerWindowsDIVLibCall(Op, DAG, Signed, DBZCHK);
6826 void ARMTargetLowering::ExpandDIV_Windows(
6827 SDValue Op, SelectionDAG &DAG, bool Signed,
6828 SmallVectorImpl<SDValue> &Results) const {
6829 const auto &DL = DAG.getDataLayout();
6830 const auto &TLI = DAG.getTargetLoweringInfo();
6832 assert(Op.getValueType() == MVT::i64 &&
6833 "unexpected type for custom lowering DIV");
6836 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op.getOperand(1),
6837 DAG.getConstant(0, dl, MVT::i32));
6838 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op.getOperand(1),
6839 DAG.getConstant(1, dl, MVT::i32));
6840 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i32, Lo, Hi);
6843 DAG.getNode(ARMISD::WIN__DBZCHK, dl, MVT::Other, DAG.getEntryNode(), Or);
6845 SDValue Result = LowerWindowsDIVLibCall(Op, DAG, Signed, DBZCHK);
6847 SDValue Lower = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Result);
6848 SDValue Upper = DAG.getNode(ISD::SRL, dl, MVT::i64, Result,
6849 DAG.getConstant(32, dl, TLI.getPointerTy(DL)));
6850 Upper = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Upper);
6852 Results.push_back(Lower);
6853 Results.push_back(Upper);
6856 static SDValue LowerAtomicLoadStore(SDValue Op, SelectionDAG &DAG) {
6857 // Monotonic load/store is legal for all targets
6858 if (cast<AtomicSDNode>(Op)->getOrdering() <= Monotonic)
6861 // Acquire/Release load/store is not legal for targets without a
6862 // dmb or equivalent available.
6866 static void ReplaceREADCYCLECOUNTER(SDNode *N,
6867 SmallVectorImpl<SDValue> &Results,
6869 const ARMSubtarget *Subtarget) {
6871 // Under Power Management extensions, the cycle-count is:
6872 // mrc p15, #0, <Rt>, c9, c13, #0
6873 SDValue Ops[] = { N->getOperand(0), // Chain
6874 DAG.getConstant(Intrinsic::arm_mrc, DL, MVT::i32),
6875 DAG.getConstant(15, DL, MVT::i32),
6876 DAG.getConstant(0, DL, MVT::i32),
6877 DAG.getConstant(9, DL, MVT::i32),
6878 DAG.getConstant(13, DL, MVT::i32),
6879 DAG.getConstant(0, DL, MVT::i32)
6882 SDValue Cycles32 = DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL,
6883 DAG.getVTList(MVT::i32, MVT::Other), Ops);
6884 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Cycles32,
6885 DAG.getConstant(0, DL, MVT::i32)));
6886 Results.push_back(Cycles32.getValue(1));
6889 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6890 switch (Op.getOpcode()) {
6891 default: llvm_unreachable("Don't know how to custom lower this!");
6892 case ISD::WRITE_REGISTER: return LowerWRITE_REGISTER(Op, DAG);
6893 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6894 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
6895 case ISD::GlobalAddress:
6896 switch (Subtarget->getTargetTriple().getObjectFormat()) {
6897 default: llvm_unreachable("unknown object format");
6899 return LowerGlobalAddressWindows(Op, DAG);
6901 return LowerGlobalAddressELF(Op, DAG);
6903 return LowerGlobalAddressDarwin(Op, DAG);
6905 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6906 case ISD::SELECT: return LowerSELECT(Op, DAG);
6907 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
6908 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
6909 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
6910 case ISD::VASTART: return LowerVASTART(Op, DAG);
6911 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG, Subtarget);
6912 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget);
6913 case ISD::SINT_TO_FP:
6914 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
6915 case ISD::FP_TO_SINT:
6916 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
6917 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
6918 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6919 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6920 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
6921 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
6922 case ISD::EH_SJLJ_SETUP_DISPATCH: return LowerEH_SJLJ_SETUP_DISPATCH(Op, DAG);
6923 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
6925 case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG);
6928 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
6929 case ISD::SREM: return LowerREM(Op.getNode(), DAG);
6930 case ISD::UREM: return LowerREM(Op.getNode(), DAG);
6931 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
6932 case ISD::SRL_PARTS:
6933 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
6935 case ISD::CTTZ_ZERO_UNDEF: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
6936 case ISD::CTPOP: return LowerCTPOP(Op.getNode(), DAG, Subtarget);
6937 case ISD::SETCC: return LowerVSETCC(Op, DAG);
6938 case ISD::ConstantFP: return LowerConstantFP(Op, DAG, Subtarget);
6939 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
6940 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6941 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
6942 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
6943 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
6944 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6945 case ISD::MUL: return LowerMUL(Op, DAG);
6946 case ISD::SDIV: return LowerSDIV(Op, DAG);
6947 case ISD::UDIV: return LowerUDIV(Op, DAG);
6951 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
6956 return LowerXALUO(Op, DAG);
6957 case ISD::ATOMIC_LOAD:
6958 case ISD::ATOMIC_STORE: return LowerAtomicLoadStore(Op, DAG);
6959 case ISD::FSINCOS: return LowerFSINCOS(Op, DAG);
6961 case ISD::UDIVREM: return LowerDivRem(Op, DAG);
6962 case ISD::DYNAMIC_STACKALLOC:
6963 if (Subtarget->getTargetTriple().isWindowsItaniumEnvironment())
6964 return LowerDYNAMIC_STACKALLOC(Op, DAG);
6965 llvm_unreachable("Don't know how to custom lower this!");
6966 case ISD::FP_ROUND: return LowerFP_ROUND(Op, DAG);
6967 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
6968 case ARMISD::WIN__DBZCHK: return SDValue();
6972 /// ReplaceNodeResults - Replace the results of node with an illegal result
6973 /// type with new values built out of custom code.
6974 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
6975 SmallVectorImpl<SDValue> &Results,
6976 SelectionDAG &DAG) const {
6978 switch (N->getOpcode()) {
6980 llvm_unreachable("Don't know how to custom expand this!");
6981 case ISD::READ_REGISTER:
6982 ExpandREAD_REGISTER(N, Results, DAG);
6985 Res = ExpandBITCAST(N, DAG);
6989 Res = Expand64BitShift(N, DAG, Subtarget);
6993 Res = LowerREM(N, DAG);
6995 case ISD::READCYCLECOUNTER:
6996 ReplaceREADCYCLECOUNTER(N, Results, DAG, Subtarget);
7000 assert(Subtarget->isTargetWindows() && "can only expand DIV on Windows");
7001 return ExpandDIV_Windows(SDValue(N, 0), DAG, N->getOpcode() == ISD::SDIV,
7005 Results.push_back(Res);
7008 //===----------------------------------------------------------------------===//
7009 // ARM Scheduler Hooks
7010 //===----------------------------------------------------------------------===//
7012 /// SetupEntryBlockForSjLj - Insert code into the entry block that creates and
7013 /// registers the function context.
7014 void ARMTargetLowering::
7015 SetupEntryBlockForSjLj(MachineInstr *MI, MachineBasicBlock *MBB,
7016 MachineBasicBlock *DispatchBB, int FI) const {
7017 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
7018 DebugLoc dl = MI->getDebugLoc();
7019 MachineFunction *MF = MBB->getParent();
7020 MachineRegisterInfo *MRI = &MF->getRegInfo();
7021 MachineConstantPool *MCP = MF->getConstantPool();
7022 ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>();
7023 const Function *F = MF->getFunction();
7025 bool isThumb = Subtarget->isThumb();
7026 bool isThumb2 = Subtarget->isThumb2();
7028 unsigned PCLabelId = AFI->createPICLabelUId();
7029 unsigned PCAdj = (isThumb || isThumb2) ? 4 : 8;
7030 ARMConstantPoolValue *CPV =
7031 ARMConstantPoolMBB::Create(F->getContext(), DispatchBB, PCLabelId, PCAdj);
7032 unsigned CPI = MCP->getConstantPoolIndex(CPV, 4);
7034 const TargetRegisterClass *TRC = isThumb ? &ARM::tGPRRegClass
7035 : &ARM::GPRRegClass;
7037 // Grab constant pool and fixed stack memory operands.
7038 MachineMemOperand *CPMMO =
7039 MF->getMachineMemOperand(MachinePointerInfo::getConstantPool(*MF),
7040 MachineMemOperand::MOLoad, 4, 4);
7042 MachineMemOperand *FIMMOSt =
7043 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(*MF, FI),
7044 MachineMemOperand::MOStore, 4, 4);
7046 // Load the address of the dispatch MBB into the jump buffer.
7048 // Incoming value: jbuf
7049 // ldr.n r5, LCPI1_1
7052 // str r5, [$jbuf, #+4] ; &jbuf[1]
7053 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
7054 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2LDRpci), NewVReg1)
7055 .addConstantPoolIndex(CPI)
7056 .addMemOperand(CPMMO));
7057 // Set the low bit because of thumb mode.
7058 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
7060 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2ORRri), NewVReg2)
7061 .addReg(NewVReg1, RegState::Kill)
7063 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
7064 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg3)
7065 .addReg(NewVReg2, RegState::Kill)
7067 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2STRi12))
7068 .addReg(NewVReg3, RegState::Kill)
7070 .addImm(36) // &jbuf[1] :: pc
7071 .addMemOperand(FIMMOSt));
7072 } else if (isThumb) {
7073 // Incoming value: jbuf
7074 // ldr.n r1, LCPI1_4
7078 // add r2, $jbuf, #+4 ; &jbuf[1]
7080 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
7081 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tLDRpci), NewVReg1)
7082 .addConstantPoolIndex(CPI)
7083 .addMemOperand(CPMMO));
7084 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
7085 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg2)
7086 .addReg(NewVReg1, RegState::Kill)
7088 // Set the low bit because of thumb mode.
7089 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
7090 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tMOVi8), NewVReg3)
7091 .addReg(ARM::CPSR, RegState::Define)
7093 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
7094 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tORR), NewVReg4)
7095 .addReg(ARM::CPSR, RegState::Define)
7096 .addReg(NewVReg2, RegState::Kill)
7097 .addReg(NewVReg3, RegState::Kill));
7098 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
7099 BuildMI(*MBB, MI, dl, TII->get(ARM::tADDframe), NewVReg5)
7101 .addImm(36); // &jbuf[1] :: pc
7102 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tSTRi))
7103 .addReg(NewVReg4, RegState::Kill)
7104 .addReg(NewVReg5, RegState::Kill)
7106 .addMemOperand(FIMMOSt));
7108 // Incoming value: jbuf
7111 // str r1, [$jbuf, #+4] ; &jbuf[1]
7112 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
7113 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::LDRi12), NewVReg1)
7114 .addConstantPoolIndex(CPI)
7116 .addMemOperand(CPMMO));
7117 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
7118 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::PICADD), NewVReg2)
7119 .addReg(NewVReg1, RegState::Kill)
7120 .addImm(PCLabelId));
7121 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::STRi12))
7122 .addReg(NewVReg2, RegState::Kill)
7124 .addImm(36) // &jbuf[1] :: pc
7125 .addMemOperand(FIMMOSt));
7129 void ARMTargetLowering::EmitSjLjDispatchBlock(MachineInstr *MI,
7130 MachineBasicBlock *MBB) const {
7131 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
7132 DebugLoc dl = MI->getDebugLoc();
7133 MachineFunction *MF = MBB->getParent();
7134 MachineRegisterInfo *MRI = &MF->getRegInfo();
7135 MachineFrameInfo *MFI = MF->getFrameInfo();
7136 int FI = MFI->getFunctionContextIndex();
7138 const TargetRegisterClass *TRC = Subtarget->isThumb() ? &ARM::tGPRRegClass
7139 : &ARM::GPRnopcRegClass;
7141 // Get a mapping of the call site numbers to all of the landing pads they're
7143 DenseMap<unsigned, SmallVector<MachineBasicBlock*, 2> > CallSiteNumToLPad;
7144 unsigned MaxCSNum = 0;
7145 MachineModuleInfo &MMI = MF->getMMI();
7146 for (MachineFunction::iterator BB = MF->begin(), E = MF->end(); BB != E;
7148 if (!BB->isEHPad()) continue;
7150 // FIXME: We should assert that the EH_LABEL is the first MI in the landing
7152 for (MachineBasicBlock::iterator
7153 II = BB->begin(), IE = BB->end(); II != IE; ++II) {
7154 if (!II->isEHLabel()) continue;
7156 MCSymbol *Sym = II->getOperand(0).getMCSymbol();
7157 if (!MMI.hasCallSiteLandingPad(Sym)) continue;
7159 SmallVectorImpl<unsigned> &CallSiteIdxs = MMI.getCallSiteLandingPad(Sym);
7160 for (SmallVectorImpl<unsigned>::iterator
7161 CSI = CallSiteIdxs.begin(), CSE = CallSiteIdxs.end();
7162 CSI != CSE; ++CSI) {
7163 CallSiteNumToLPad[*CSI].push_back(&*BB);
7164 MaxCSNum = std::max(MaxCSNum, *CSI);
7170 // Get an ordered list of the machine basic blocks for the jump table.
7171 std::vector<MachineBasicBlock*> LPadList;
7172 SmallPtrSet<MachineBasicBlock*, 64> InvokeBBs;
7173 LPadList.reserve(CallSiteNumToLPad.size());
7174 for (unsigned I = 1; I <= MaxCSNum; ++I) {
7175 SmallVectorImpl<MachineBasicBlock*> &MBBList = CallSiteNumToLPad[I];
7176 for (SmallVectorImpl<MachineBasicBlock*>::iterator
7177 II = MBBList.begin(), IE = MBBList.end(); II != IE; ++II) {
7178 LPadList.push_back(*II);
7179 InvokeBBs.insert((*II)->pred_begin(), (*II)->pred_end());
7183 assert(!LPadList.empty() &&
7184 "No landing pad destinations for the dispatch jump table!");
7186 // Create the jump table and associated information.
7187 MachineJumpTableInfo *JTI =
7188 MF->getOrCreateJumpTableInfo(MachineJumpTableInfo::EK_Inline);
7189 unsigned MJTI = JTI->createJumpTableIndex(LPadList);
7190 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
7192 // Create the MBBs for the dispatch code.
7194 // Shove the dispatch's address into the return slot in the function context.
7195 MachineBasicBlock *DispatchBB = MF->CreateMachineBasicBlock();
7196 DispatchBB->setIsEHPad();
7198 MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock();
7199 unsigned trap_opcode;
7200 if (Subtarget->isThumb())
7201 trap_opcode = ARM::tTRAP;
7203 trap_opcode = Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP;
7205 BuildMI(TrapBB, dl, TII->get(trap_opcode));
7206 DispatchBB->addSuccessor(TrapBB);
7208 MachineBasicBlock *DispContBB = MF->CreateMachineBasicBlock();
7209 DispatchBB->addSuccessor(DispContBB);
7212 MF->insert(MF->end(), DispatchBB);
7213 MF->insert(MF->end(), DispContBB);
7214 MF->insert(MF->end(), TrapBB);
7216 // Insert code into the entry block that creates and registers the function
7218 SetupEntryBlockForSjLj(MI, MBB, DispatchBB, FI);
7220 MachineMemOperand *FIMMOLd = MF->getMachineMemOperand(
7221 MachinePointerInfo::getFixedStack(*MF, FI),
7222 MachineMemOperand::MOLoad | MachineMemOperand::MOVolatile, 4, 4);
7224 MachineInstrBuilder MIB;
7225 MIB = BuildMI(DispatchBB, dl, TII->get(ARM::Int_eh_sjlj_dispatchsetup));
7227 const ARMBaseInstrInfo *AII = static_cast<const ARMBaseInstrInfo*>(TII);
7228 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
7230 // Add a register mask with no preserved registers. This results in all
7231 // registers being marked as clobbered.
7232 MIB.addRegMask(RI.getNoPreservedMask());
7234 unsigned NumLPads = LPadList.size();
7235 if (Subtarget->isThumb2()) {
7236 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
7237 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2LDRi12), NewVReg1)
7240 .addMemOperand(FIMMOLd));
7242 if (NumLPads < 256) {
7243 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPri))
7245 .addImm(LPadList.size()));
7247 unsigned VReg1 = MRI->createVirtualRegister(TRC);
7248 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVi16), VReg1)
7249 .addImm(NumLPads & 0xFFFF));
7251 unsigned VReg2 = VReg1;
7252 if ((NumLPads & 0xFFFF0000) != 0) {
7253 VReg2 = MRI->createVirtualRegister(TRC);
7254 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVTi16), VReg2)
7256 .addImm(NumLPads >> 16));
7259 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPrr))
7264 BuildMI(DispatchBB, dl, TII->get(ARM::t2Bcc))
7269 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
7270 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::t2LEApcrelJT),NewVReg3)
7271 .addJumpTableIndex(MJTI));
7273 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
7276 BuildMI(DispContBB, dl, TII->get(ARM::t2ADDrs), NewVReg4)
7277 .addReg(NewVReg3, RegState::Kill)
7279 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))));
7281 BuildMI(DispContBB, dl, TII->get(ARM::t2BR_JT))
7282 .addReg(NewVReg4, RegState::Kill)
7284 .addJumpTableIndex(MJTI);
7285 } else if (Subtarget->isThumb()) {
7286 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
7287 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRspi), NewVReg1)
7290 .addMemOperand(FIMMOLd));
7292 if (NumLPads < 256) {
7293 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPi8))
7297 MachineConstantPool *ConstantPool = MF->getConstantPool();
7298 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
7299 const Constant *C = ConstantInt::get(Int32Ty, NumLPads);
7301 // MachineConstantPool wants an explicit alignment.
7302 unsigned Align = MF->getDataLayout().getPrefTypeAlignment(Int32Ty);
7304 Align = MF->getDataLayout().getTypeAllocSize(C->getType());
7305 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
7307 unsigned VReg1 = MRI->createVirtualRegister(TRC);
7308 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRpci))
7309 .addReg(VReg1, RegState::Define)
7310 .addConstantPoolIndex(Idx));
7311 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPr))
7316 BuildMI(DispatchBB, dl, TII->get(ARM::tBcc))
7321 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
7322 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLSLri), NewVReg2)
7323 .addReg(ARM::CPSR, RegState::Define)
7327 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
7328 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLEApcrelJT), NewVReg3)
7329 .addJumpTableIndex(MJTI));
7331 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
7332 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg4)
7333 .addReg(ARM::CPSR, RegState::Define)
7334 .addReg(NewVReg2, RegState::Kill)
7337 MachineMemOperand *JTMMOLd = MF->getMachineMemOperand(
7338 MachinePointerInfo::getJumpTable(*MF), MachineMemOperand::MOLoad, 4, 4);
7340 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
7341 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLDRi), NewVReg5)
7342 .addReg(NewVReg4, RegState::Kill)
7344 .addMemOperand(JTMMOLd));
7346 unsigned NewVReg6 = NewVReg5;
7347 if (RelocM == Reloc::PIC_) {
7348 NewVReg6 = MRI->createVirtualRegister(TRC);
7349 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg6)
7350 .addReg(ARM::CPSR, RegState::Define)
7351 .addReg(NewVReg5, RegState::Kill)
7355 BuildMI(DispContBB, dl, TII->get(ARM::tBR_JTr))
7356 .addReg(NewVReg6, RegState::Kill)
7357 .addJumpTableIndex(MJTI);
7359 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
7360 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRi12), NewVReg1)
7363 .addMemOperand(FIMMOLd));
7365 if (NumLPads < 256) {
7366 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPri))
7369 } else if (Subtarget->hasV6T2Ops() && isUInt<16>(NumLPads)) {
7370 unsigned VReg1 = MRI->createVirtualRegister(TRC);
7371 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVi16), VReg1)
7372 .addImm(NumLPads & 0xFFFF));
7374 unsigned VReg2 = VReg1;
7375 if ((NumLPads & 0xFFFF0000) != 0) {
7376 VReg2 = MRI->createVirtualRegister(TRC);
7377 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVTi16), VReg2)
7379 .addImm(NumLPads >> 16));
7382 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
7386 MachineConstantPool *ConstantPool = MF->getConstantPool();
7387 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
7388 const Constant *C = ConstantInt::get(Int32Ty, NumLPads);
7390 // MachineConstantPool wants an explicit alignment.
7391 unsigned Align = MF->getDataLayout().getPrefTypeAlignment(Int32Ty);
7393 Align = MF->getDataLayout().getTypeAllocSize(C->getType());
7394 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
7396 unsigned VReg1 = MRI->createVirtualRegister(TRC);
7397 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRcp))
7398 .addReg(VReg1, RegState::Define)
7399 .addConstantPoolIndex(Idx)
7401 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
7403 .addReg(VReg1, RegState::Kill));
7406 BuildMI(DispatchBB, dl, TII->get(ARM::Bcc))
7411 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
7413 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::MOVsi), NewVReg3)
7415 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))));
7416 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
7417 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::LEApcrelJT), NewVReg4)
7418 .addJumpTableIndex(MJTI));
7420 MachineMemOperand *JTMMOLd = MF->getMachineMemOperand(
7421 MachinePointerInfo::getJumpTable(*MF), MachineMemOperand::MOLoad, 4, 4);
7422 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
7424 BuildMI(DispContBB, dl, TII->get(ARM::LDRrs), NewVReg5)
7425 .addReg(NewVReg3, RegState::Kill)
7428 .addMemOperand(JTMMOLd));
7430 if (RelocM == Reloc::PIC_) {
7431 BuildMI(DispContBB, dl, TII->get(ARM::BR_JTadd))
7432 .addReg(NewVReg5, RegState::Kill)
7434 .addJumpTableIndex(MJTI);
7436 BuildMI(DispContBB, dl, TII->get(ARM::BR_JTr))
7437 .addReg(NewVReg5, RegState::Kill)
7438 .addJumpTableIndex(MJTI);
7442 // Add the jump table entries as successors to the MBB.
7443 SmallPtrSet<MachineBasicBlock*, 8> SeenMBBs;
7444 for (std::vector<MachineBasicBlock*>::iterator
7445 I = LPadList.begin(), E = LPadList.end(); I != E; ++I) {
7446 MachineBasicBlock *CurMBB = *I;
7447 if (SeenMBBs.insert(CurMBB).second)
7448 DispContBB->addSuccessor(CurMBB);
7451 // N.B. the order the invoke BBs are processed in doesn't matter here.
7452 const MCPhysReg *SavedRegs = RI.getCalleeSavedRegs(MF);
7453 SmallVector<MachineBasicBlock*, 64> MBBLPads;
7454 for (MachineBasicBlock *BB : InvokeBBs) {
7456 // Remove the landing pad successor from the invoke block and replace it
7457 // with the new dispatch block.
7458 SmallVector<MachineBasicBlock*, 4> Successors(BB->succ_begin(),
7460 while (!Successors.empty()) {
7461 MachineBasicBlock *SMBB = Successors.pop_back_val();
7462 if (SMBB->isEHPad()) {
7463 BB->removeSuccessor(SMBB);
7464 MBBLPads.push_back(SMBB);
7468 BB->addSuccessor(DispatchBB, BranchProbability::getZero());
7469 BB->normalizeSuccProbs();
7471 // Find the invoke call and mark all of the callee-saved registers as
7472 // 'implicit defined' so that they're spilled. This prevents code from
7473 // moving instructions to before the EH block, where they will never be
7475 for (MachineBasicBlock::reverse_iterator
7476 II = BB->rbegin(), IE = BB->rend(); II != IE; ++II) {
7477 if (!II->isCall()) continue;
7479 DenseMap<unsigned, bool> DefRegs;
7480 for (MachineInstr::mop_iterator
7481 OI = II->operands_begin(), OE = II->operands_end();
7483 if (!OI->isReg()) continue;
7484 DefRegs[OI->getReg()] = true;
7487 MachineInstrBuilder MIB(*MF, &*II);
7489 for (unsigned i = 0; SavedRegs[i] != 0; ++i) {
7490 unsigned Reg = SavedRegs[i];
7491 if (Subtarget->isThumb2() &&
7492 !ARM::tGPRRegClass.contains(Reg) &&
7493 !ARM::hGPRRegClass.contains(Reg))
7495 if (Subtarget->isThumb1Only() && !ARM::tGPRRegClass.contains(Reg))
7497 if (!Subtarget->isThumb() && !ARM::GPRRegClass.contains(Reg))
7500 MIB.addReg(Reg, RegState::ImplicitDefine | RegState::Dead);
7507 // Mark all former landing pads as non-landing pads. The dispatch is the only
7509 for (SmallVectorImpl<MachineBasicBlock*>::iterator
7510 I = MBBLPads.begin(), E = MBBLPads.end(); I != E; ++I)
7511 (*I)->setIsEHPad(false);
7513 // The instruction is gone now.
7514 MI->eraseFromParent();
7518 MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
7519 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
7520 E = MBB->succ_end(); I != E; ++I)
7523 llvm_unreachable("Expecting a BB with two successors!");
7526 /// Return the load opcode for a given load size. If load size >= 8,
7527 /// neon opcode will be returned.
7528 static unsigned getLdOpcode(unsigned LdSize, bool IsThumb1, bool IsThumb2) {
7530 return LdSize == 16 ? ARM::VLD1q32wb_fixed
7531 : LdSize == 8 ? ARM::VLD1d32wb_fixed : 0;
7533 return LdSize == 4 ? ARM::tLDRi
7534 : LdSize == 2 ? ARM::tLDRHi
7535 : LdSize == 1 ? ARM::tLDRBi : 0;
7537 return LdSize == 4 ? ARM::t2LDR_POST
7538 : LdSize == 2 ? ARM::t2LDRH_POST
7539 : LdSize == 1 ? ARM::t2LDRB_POST : 0;
7540 return LdSize == 4 ? ARM::LDR_POST_IMM
7541 : LdSize == 2 ? ARM::LDRH_POST
7542 : LdSize == 1 ? ARM::LDRB_POST_IMM : 0;
7545 /// Return the store opcode for a given store size. If store size >= 8,
7546 /// neon opcode will be returned.
7547 static unsigned getStOpcode(unsigned StSize, bool IsThumb1, bool IsThumb2) {
7549 return StSize == 16 ? ARM::VST1q32wb_fixed
7550 : StSize == 8 ? ARM::VST1d32wb_fixed : 0;
7552 return StSize == 4 ? ARM::tSTRi
7553 : StSize == 2 ? ARM::tSTRHi
7554 : StSize == 1 ? ARM::tSTRBi : 0;
7556 return StSize == 4 ? ARM::t2STR_POST
7557 : StSize == 2 ? ARM::t2STRH_POST
7558 : StSize == 1 ? ARM::t2STRB_POST : 0;
7559 return StSize == 4 ? ARM::STR_POST_IMM
7560 : StSize == 2 ? ARM::STRH_POST
7561 : StSize == 1 ? ARM::STRB_POST_IMM : 0;
7564 /// Emit a post-increment load operation with given size. The instructions
7565 /// will be added to BB at Pos.
7566 static void emitPostLd(MachineBasicBlock *BB, MachineInstr *Pos,
7567 const TargetInstrInfo *TII, DebugLoc dl,
7568 unsigned LdSize, unsigned Data, unsigned AddrIn,
7569 unsigned AddrOut, bool IsThumb1, bool IsThumb2) {
7570 unsigned LdOpc = getLdOpcode(LdSize, IsThumb1, IsThumb2);
7571 assert(LdOpc != 0 && "Should have a load opcode");
7573 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
7574 .addReg(AddrOut, RegState::Define).addReg(AddrIn)
7576 } else if (IsThumb1) {
7577 // load + update AddrIn
7578 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
7579 .addReg(AddrIn).addImm(0));
7580 MachineInstrBuilder MIB =
7581 BuildMI(*BB, Pos, dl, TII->get(ARM::tADDi8), AddrOut);
7582 MIB = AddDefaultT1CC(MIB);
7583 MIB.addReg(AddrIn).addImm(LdSize);
7584 AddDefaultPred(MIB);
7585 } else if (IsThumb2) {
7586 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
7587 .addReg(AddrOut, RegState::Define).addReg(AddrIn)
7590 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
7591 .addReg(AddrOut, RegState::Define).addReg(AddrIn)
7592 .addReg(0).addImm(LdSize));
7596 /// Emit a post-increment store operation with given size. The instructions
7597 /// will be added to BB at Pos.
7598 static void emitPostSt(MachineBasicBlock *BB, MachineInstr *Pos,
7599 const TargetInstrInfo *TII, DebugLoc dl,
7600 unsigned StSize, unsigned Data, unsigned AddrIn,
7601 unsigned AddrOut, bool IsThumb1, bool IsThumb2) {
7602 unsigned StOpc = getStOpcode(StSize, IsThumb1, IsThumb2);
7603 assert(StOpc != 0 && "Should have a store opcode");
7605 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
7606 .addReg(AddrIn).addImm(0).addReg(Data));
7607 } else if (IsThumb1) {
7608 // store + update AddrIn
7609 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc)).addReg(Data)
7610 .addReg(AddrIn).addImm(0));
7611 MachineInstrBuilder MIB =
7612 BuildMI(*BB, Pos, dl, TII->get(ARM::tADDi8), AddrOut);
7613 MIB = AddDefaultT1CC(MIB);
7614 MIB.addReg(AddrIn).addImm(StSize);
7615 AddDefaultPred(MIB);
7616 } else if (IsThumb2) {
7617 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
7618 .addReg(Data).addReg(AddrIn).addImm(StSize));
7620 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
7621 .addReg(Data).addReg(AddrIn).addReg(0)
7627 ARMTargetLowering::EmitStructByval(MachineInstr *MI,
7628 MachineBasicBlock *BB) const {
7629 // This pseudo instruction has 3 operands: dst, src, size
7630 // We expand it to a loop if size > Subtarget->getMaxInlineSizeThreshold().
7631 // Otherwise, we will generate unrolled scalar copies.
7632 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
7633 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7634 MachineFunction::iterator It = ++BB->getIterator();
7636 unsigned dest = MI->getOperand(0).getReg();
7637 unsigned src = MI->getOperand(1).getReg();
7638 unsigned SizeVal = MI->getOperand(2).getImm();
7639 unsigned Align = MI->getOperand(3).getImm();
7640 DebugLoc dl = MI->getDebugLoc();
7642 MachineFunction *MF = BB->getParent();
7643 MachineRegisterInfo &MRI = MF->getRegInfo();
7644 unsigned UnitSize = 0;
7645 const TargetRegisterClass *TRC = nullptr;
7646 const TargetRegisterClass *VecTRC = nullptr;
7648 bool IsThumb1 = Subtarget->isThumb1Only();
7649 bool IsThumb2 = Subtarget->isThumb2();
7653 } else if (Align & 2) {
7656 // Check whether we can use NEON instructions.
7657 if (!MF->getFunction()->hasFnAttribute(Attribute::NoImplicitFloat) &&
7658 Subtarget->hasNEON()) {
7659 if ((Align % 16 == 0) && SizeVal >= 16)
7661 else if ((Align % 8 == 0) && SizeVal >= 8)
7664 // Can't use NEON instructions.
7669 // Select the correct opcode and register class for unit size load/store
7670 bool IsNeon = UnitSize >= 8;
7671 TRC = (IsThumb1 || IsThumb2) ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
7673 VecTRC = UnitSize == 16 ? &ARM::DPairRegClass
7674 : UnitSize == 8 ? &ARM::DPRRegClass
7677 unsigned BytesLeft = SizeVal % UnitSize;
7678 unsigned LoopSize = SizeVal - BytesLeft;
7680 if (SizeVal <= Subtarget->getMaxInlineSizeThreshold()) {
7681 // Use LDR and STR to copy.
7682 // [scratch, srcOut] = LDR_POST(srcIn, UnitSize)
7683 // [destOut] = STR_POST(scratch, destIn, UnitSize)
7684 unsigned srcIn = src;
7685 unsigned destIn = dest;
7686 for (unsigned i = 0; i < LoopSize; i+=UnitSize) {
7687 unsigned srcOut = MRI.createVirtualRegister(TRC);
7688 unsigned destOut = MRI.createVirtualRegister(TRC);
7689 unsigned scratch = MRI.createVirtualRegister(IsNeon ? VecTRC : TRC);
7690 emitPostLd(BB, MI, TII, dl, UnitSize, scratch, srcIn, srcOut,
7691 IsThumb1, IsThumb2);
7692 emitPostSt(BB, MI, TII, dl, UnitSize, scratch, destIn, destOut,
7693 IsThumb1, IsThumb2);
7698 // Handle the leftover bytes with LDRB and STRB.
7699 // [scratch, srcOut] = LDRB_POST(srcIn, 1)
7700 // [destOut] = STRB_POST(scratch, destIn, 1)
7701 for (unsigned i = 0; i < BytesLeft; i++) {
7702 unsigned srcOut = MRI.createVirtualRegister(TRC);
7703 unsigned destOut = MRI.createVirtualRegister(TRC);
7704 unsigned scratch = MRI.createVirtualRegister(TRC);
7705 emitPostLd(BB, MI, TII, dl, 1, scratch, srcIn, srcOut,
7706 IsThumb1, IsThumb2);
7707 emitPostSt(BB, MI, TII, dl, 1, scratch, destIn, destOut,
7708 IsThumb1, IsThumb2);
7712 MI->eraseFromParent(); // The instruction is gone now.
7716 // Expand the pseudo op to a loop.
7719 // movw varEnd, # --> with thumb2
7721 // ldrcp varEnd, idx --> without thumb2
7722 // fallthrough --> loopMBB
7724 // PHI varPhi, varEnd, varLoop
7725 // PHI srcPhi, src, srcLoop
7726 // PHI destPhi, dst, destLoop
7727 // [scratch, srcLoop] = LDR_POST(srcPhi, UnitSize)
7728 // [destLoop] = STR_POST(scratch, destPhi, UnitSize)
7729 // subs varLoop, varPhi, #UnitSize
7731 // fallthrough --> exitMBB
7733 // epilogue to handle left-over bytes
7734 // [scratch, srcOut] = LDRB_POST(srcLoop, 1)
7735 // [destOut] = STRB_POST(scratch, destLoop, 1)
7736 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
7737 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
7738 MF->insert(It, loopMBB);
7739 MF->insert(It, exitMBB);
7741 // Transfer the remainder of BB and its successor edges to exitMBB.
7742 exitMBB->splice(exitMBB->begin(), BB,
7743 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7744 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7746 // Load an immediate to varEnd.
7747 unsigned varEnd = MRI.createVirtualRegister(TRC);
7748 if (Subtarget->useMovt(*MF)) {
7749 unsigned Vtmp = varEnd;
7750 if ((LoopSize & 0xFFFF0000) != 0)
7751 Vtmp = MRI.createVirtualRegister(TRC);
7752 AddDefaultPred(BuildMI(BB, dl,
7753 TII->get(IsThumb2 ? ARM::t2MOVi16 : ARM::MOVi16),
7754 Vtmp).addImm(LoopSize & 0xFFFF));
7756 if ((LoopSize & 0xFFFF0000) != 0)
7757 AddDefaultPred(BuildMI(BB, dl,
7758 TII->get(IsThumb2 ? ARM::t2MOVTi16 : ARM::MOVTi16),
7761 .addImm(LoopSize >> 16));
7763 MachineConstantPool *ConstantPool = MF->getConstantPool();
7764 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
7765 const Constant *C = ConstantInt::get(Int32Ty, LoopSize);
7767 // MachineConstantPool wants an explicit alignment.
7768 unsigned Align = MF->getDataLayout().getPrefTypeAlignment(Int32Ty);
7770 Align = MF->getDataLayout().getTypeAllocSize(C->getType());
7771 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
7774 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(ARM::tLDRpci)).addReg(
7775 varEnd, RegState::Define).addConstantPoolIndex(Idx));
7777 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(ARM::LDRcp)).addReg(
7778 varEnd, RegState::Define).addConstantPoolIndex(Idx).addImm(0));
7780 BB->addSuccessor(loopMBB);
7782 // Generate the loop body:
7783 // varPhi = PHI(varLoop, varEnd)
7784 // srcPhi = PHI(srcLoop, src)
7785 // destPhi = PHI(destLoop, dst)
7786 MachineBasicBlock *entryBB = BB;
7788 unsigned varLoop = MRI.createVirtualRegister(TRC);
7789 unsigned varPhi = MRI.createVirtualRegister(TRC);
7790 unsigned srcLoop = MRI.createVirtualRegister(TRC);
7791 unsigned srcPhi = MRI.createVirtualRegister(TRC);
7792 unsigned destLoop = MRI.createVirtualRegister(TRC);
7793 unsigned destPhi = MRI.createVirtualRegister(TRC);
7795 BuildMI(*BB, BB->begin(), dl, TII->get(ARM::PHI), varPhi)
7796 .addReg(varLoop).addMBB(loopMBB)
7797 .addReg(varEnd).addMBB(entryBB);
7798 BuildMI(BB, dl, TII->get(ARM::PHI), srcPhi)
7799 .addReg(srcLoop).addMBB(loopMBB)
7800 .addReg(src).addMBB(entryBB);
7801 BuildMI(BB, dl, TII->get(ARM::PHI), destPhi)
7802 .addReg(destLoop).addMBB(loopMBB)
7803 .addReg(dest).addMBB(entryBB);
7805 // [scratch, srcLoop] = LDR_POST(srcPhi, UnitSize)
7806 // [destLoop] = STR_POST(scratch, destPhi, UnitSiz)
7807 unsigned scratch = MRI.createVirtualRegister(IsNeon ? VecTRC : TRC);
7808 emitPostLd(BB, BB->end(), TII, dl, UnitSize, scratch, srcPhi, srcLoop,
7809 IsThumb1, IsThumb2);
7810 emitPostSt(BB, BB->end(), TII, dl, UnitSize, scratch, destPhi, destLoop,
7811 IsThumb1, IsThumb2);
7813 // Decrement loop variable by UnitSize.
7815 MachineInstrBuilder MIB =
7816 BuildMI(*BB, BB->end(), dl, TII->get(ARM::tSUBi8), varLoop);
7817 MIB = AddDefaultT1CC(MIB);
7818 MIB.addReg(varPhi).addImm(UnitSize);
7819 AddDefaultPred(MIB);
7821 MachineInstrBuilder MIB =
7822 BuildMI(*BB, BB->end(), dl,
7823 TII->get(IsThumb2 ? ARM::t2SUBri : ARM::SUBri), varLoop);
7824 AddDefaultCC(AddDefaultPred(MIB.addReg(varPhi).addImm(UnitSize)));
7825 MIB->getOperand(5).setReg(ARM::CPSR);
7826 MIB->getOperand(5).setIsDef(true);
7828 BuildMI(*BB, BB->end(), dl,
7829 TII->get(IsThumb1 ? ARM::tBcc : IsThumb2 ? ARM::t2Bcc : ARM::Bcc))
7830 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
7832 // loopMBB can loop back to loopMBB or fall through to exitMBB.
7833 BB->addSuccessor(loopMBB);
7834 BB->addSuccessor(exitMBB);
7836 // Add epilogue to handle BytesLeft.
7838 MachineInstr *StartOfExit = exitMBB->begin();
7840 // [scratch, srcOut] = LDRB_POST(srcLoop, 1)
7841 // [destOut] = STRB_POST(scratch, destLoop, 1)
7842 unsigned srcIn = srcLoop;
7843 unsigned destIn = destLoop;
7844 for (unsigned i = 0; i < BytesLeft; i++) {
7845 unsigned srcOut = MRI.createVirtualRegister(TRC);
7846 unsigned destOut = MRI.createVirtualRegister(TRC);
7847 unsigned scratch = MRI.createVirtualRegister(TRC);
7848 emitPostLd(BB, StartOfExit, TII, dl, 1, scratch, srcIn, srcOut,
7849 IsThumb1, IsThumb2);
7850 emitPostSt(BB, StartOfExit, TII, dl, 1, scratch, destIn, destOut,
7851 IsThumb1, IsThumb2);
7856 MI->eraseFromParent(); // The instruction is gone now.
7861 ARMTargetLowering::EmitLowered__chkstk(MachineInstr *MI,
7862 MachineBasicBlock *MBB) const {
7863 const TargetMachine &TM = getTargetMachine();
7864 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
7865 DebugLoc DL = MI->getDebugLoc();
7867 assert(Subtarget->isTargetWindows() &&
7868 "__chkstk is only supported on Windows");
7869 assert(Subtarget->isThumb2() && "Windows on ARM requires Thumb-2 mode");
7871 // __chkstk takes the number of words to allocate on the stack in R4, and
7872 // returns the stack adjustment in number of bytes in R4. This will not
7873 // clober any other registers (other than the obvious lr).
7875 // Although, technically, IP should be considered a register which may be
7876 // clobbered, the call itself will not touch it. Windows on ARM is a pure
7877 // thumb-2 environment, so there is no interworking required. As a result, we
7878 // do not expect a veneer to be emitted by the linker, clobbering IP.
7880 // Each module receives its own copy of __chkstk, so no import thunk is
7881 // required, again, ensuring that IP is not clobbered.
7883 // Finally, although some linkers may theoretically provide a trampoline for
7884 // out of range calls (which is quite common due to a 32M range limitation of
7885 // branches for Thumb), we can generate the long-call version via
7886 // -mcmodel=large, alleviating the need for the trampoline which may clobber
7889 switch (TM.getCodeModel()) {
7890 case CodeModel::Small:
7891 case CodeModel::Medium:
7892 case CodeModel::Default:
7893 case CodeModel::Kernel:
7894 BuildMI(*MBB, MI, DL, TII.get(ARM::tBL))
7895 .addImm((unsigned)ARMCC::AL).addReg(0)
7896 .addExternalSymbol("__chkstk")
7897 .addReg(ARM::R4, RegState::Implicit | RegState::Kill)
7898 .addReg(ARM::R4, RegState::Implicit | RegState::Define)
7899 .addReg(ARM::R12, RegState::Implicit | RegState::Define | RegState::Dead);
7901 case CodeModel::Large:
7902 case CodeModel::JITDefault: {
7903 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
7904 unsigned Reg = MRI.createVirtualRegister(&ARM::rGPRRegClass);
7906 BuildMI(*MBB, MI, DL, TII.get(ARM::t2MOVi32imm), Reg)
7907 .addExternalSymbol("__chkstk");
7908 BuildMI(*MBB, MI, DL, TII.get(ARM::tBLXr))
7909 .addImm((unsigned)ARMCC::AL).addReg(0)
7910 .addReg(Reg, RegState::Kill)
7911 .addReg(ARM::R4, RegState::Implicit | RegState::Kill)
7912 .addReg(ARM::R4, RegState::Implicit | RegState::Define)
7913 .addReg(ARM::R12, RegState::Implicit | RegState::Define | RegState::Dead);
7918 AddDefaultCC(AddDefaultPred(BuildMI(*MBB, MI, DL, TII.get(ARM::t2SUBrr),
7920 .addReg(ARM::SP).addReg(ARM::R4)));
7922 MI->eraseFromParent();
7927 ARMTargetLowering::EmitLowered__dbzchk(MachineInstr *MI,
7928 MachineBasicBlock *MBB) const {
7929 DebugLoc DL = MI->getDebugLoc();
7930 MachineFunction *MF = MBB->getParent();
7931 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
7933 MachineBasicBlock *ContBB = MF->CreateMachineBasicBlock();
7934 MF->push_back(ContBB);
7935 ContBB->splice(ContBB->begin(), MBB,
7936 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
7937 MBB->addSuccessor(ContBB);
7939 MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock();
7940 MF->push_back(TrapBB);
7941 BuildMI(TrapBB, DL, TII->get(ARM::t2UDF)).addImm(249);
7942 MBB->addSuccessor(TrapBB);
7944 BuildMI(*MBB, MI, DL, TII->get(ARM::tCBZ))
7945 .addReg(MI->getOperand(0).getReg())
7948 MI->eraseFromParent();
7953 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
7954 MachineBasicBlock *BB) const {
7955 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
7956 DebugLoc dl = MI->getDebugLoc();
7957 bool isThumb2 = Subtarget->isThumb2();
7958 switch (MI->getOpcode()) {
7961 llvm_unreachable("Unexpected instr type to insert");
7963 // The Thumb2 pre-indexed stores have the same MI operands, they just
7964 // define them differently in the .td files from the isel patterns, so
7965 // they need pseudos.
7966 case ARM::t2STR_preidx:
7967 MI->setDesc(TII->get(ARM::t2STR_PRE));
7969 case ARM::t2STRB_preidx:
7970 MI->setDesc(TII->get(ARM::t2STRB_PRE));
7972 case ARM::t2STRH_preidx:
7973 MI->setDesc(TII->get(ARM::t2STRH_PRE));
7976 case ARM::STRi_preidx:
7977 case ARM::STRBi_preidx: {
7978 unsigned NewOpc = MI->getOpcode() == ARM::STRi_preidx ?
7979 ARM::STR_PRE_IMM : ARM::STRB_PRE_IMM;
7980 // Decode the offset.
7981 unsigned Offset = MI->getOperand(4).getImm();
7982 bool isSub = ARM_AM::getAM2Op(Offset) == ARM_AM::sub;
7983 Offset = ARM_AM::getAM2Offset(Offset);
7987 MachineMemOperand *MMO = *MI->memoperands_begin();
7988 BuildMI(*BB, MI, dl, TII->get(NewOpc))
7989 .addOperand(MI->getOperand(0)) // Rn_wb
7990 .addOperand(MI->getOperand(1)) // Rt
7991 .addOperand(MI->getOperand(2)) // Rn
7992 .addImm(Offset) // offset (skip GPR==zero_reg)
7993 .addOperand(MI->getOperand(5)) // pred
7994 .addOperand(MI->getOperand(6))
7995 .addMemOperand(MMO);
7996 MI->eraseFromParent();
7999 case ARM::STRr_preidx:
8000 case ARM::STRBr_preidx:
8001 case ARM::STRH_preidx: {
8003 switch (MI->getOpcode()) {
8004 default: llvm_unreachable("unexpected opcode!");
8005 case ARM::STRr_preidx: NewOpc = ARM::STR_PRE_REG; break;
8006 case ARM::STRBr_preidx: NewOpc = ARM::STRB_PRE_REG; break;
8007 case ARM::STRH_preidx: NewOpc = ARM::STRH_PRE; break;
8009 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc));
8010 for (unsigned i = 0; i < MI->getNumOperands(); ++i)
8011 MIB.addOperand(MI->getOperand(i));
8012 MI->eraseFromParent();
8016 case ARM::tMOVCCr_pseudo: {
8017 // To "insert" a SELECT_CC instruction, we actually have to insert the
8018 // diamond control-flow pattern. The incoming instruction knows the
8019 // destination vreg to set, the condition code register to branch on, the
8020 // true/false values to select between, and a branch opcode to use.
8021 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8022 MachineFunction::iterator It = ++BB->getIterator();
8027 // cmpTY ccX, r1, r2
8029 // fallthrough --> copy0MBB
8030 MachineBasicBlock *thisMBB = BB;
8031 MachineFunction *F = BB->getParent();
8032 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
8033 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
8034 F->insert(It, copy0MBB);
8035 F->insert(It, sinkMBB);
8037 // Transfer the remainder of BB and its successor edges to sinkMBB.
8038 sinkMBB->splice(sinkMBB->begin(), BB,
8039 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8040 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
8042 BB->addSuccessor(copy0MBB);
8043 BB->addSuccessor(sinkMBB);
8045 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
8046 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
8049 // %FalseValue = ...
8050 // # fallthrough to sinkMBB
8053 // Update machine-CFG edges
8054 BB->addSuccessor(sinkMBB);
8057 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
8060 BuildMI(*BB, BB->begin(), dl,
8061 TII->get(ARM::PHI), MI->getOperand(0).getReg())
8062 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
8063 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
8065 MI->eraseFromParent(); // The pseudo instruction is gone now.
8070 case ARM::BCCZi64: {
8071 // If there is an unconditional branch to the other successor, remove it.
8072 BB->erase(std::next(MachineBasicBlock::iterator(MI)), BB->end());
8074 // Compare both parts that make up the double comparison separately for
8076 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
8078 unsigned LHS1 = MI->getOperand(1).getReg();
8079 unsigned LHS2 = MI->getOperand(2).getReg();
8081 AddDefaultPred(BuildMI(BB, dl,
8082 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
8083 .addReg(LHS1).addImm(0));
8084 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
8085 .addReg(LHS2).addImm(0)
8086 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
8088 unsigned RHS1 = MI->getOperand(3).getReg();
8089 unsigned RHS2 = MI->getOperand(4).getReg();
8090 AddDefaultPred(BuildMI(BB, dl,
8091 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
8092 .addReg(LHS1).addReg(RHS1));
8093 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
8094 .addReg(LHS2).addReg(RHS2)
8095 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
8098 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB();
8099 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
8100 if (MI->getOperand(0).getImm() == ARMCC::NE)
8101 std::swap(destMBB, exitMBB);
8103 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
8104 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
8106 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2B)).addMBB(exitMBB));
8108 BuildMI(BB, dl, TII->get(ARM::B)) .addMBB(exitMBB);
8110 MI->eraseFromParent(); // The pseudo instruction is gone now.
8114 case ARM::Int_eh_sjlj_setjmp:
8115 case ARM::Int_eh_sjlj_setjmp_nofp:
8116 case ARM::tInt_eh_sjlj_setjmp:
8117 case ARM::t2Int_eh_sjlj_setjmp:
8118 case ARM::t2Int_eh_sjlj_setjmp_nofp:
8121 case ARM::Int_eh_sjlj_setup_dispatch:
8122 EmitSjLjDispatchBlock(MI, BB);
8127 // To insert an ABS instruction, we have to insert the
8128 // diamond control-flow pattern. The incoming instruction knows the
8129 // source vreg to test against 0, the destination vreg to set,
8130 // the condition code register to branch on, the
8131 // true/false values to select between, and a branch opcode to use.
8136 // BCC (branch to SinkBB if V0 >= 0)
8137 // RSBBB: V3 = RSBri V2, 0 (compute ABS if V2 < 0)
8138 // SinkBB: V1 = PHI(V2, V3)
8139 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8140 MachineFunction::iterator BBI = ++BB->getIterator();
8141 MachineFunction *Fn = BB->getParent();
8142 MachineBasicBlock *RSBBB = Fn->CreateMachineBasicBlock(LLVM_BB);
8143 MachineBasicBlock *SinkBB = Fn->CreateMachineBasicBlock(LLVM_BB);
8144 Fn->insert(BBI, RSBBB);
8145 Fn->insert(BBI, SinkBB);
8147 unsigned int ABSSrcReg = MI->getOperand(1).getReg();
8148 unsigned int ABSDstReg = MI->getOperand(0).getReg();
8149 bool ABSSrcKIll = MI->getOperand(1).isKill();
8150 bool isThumb2 = Subtarget->isThumb2();
8151 MachineRegisterInfo &MRI = Fn->getRegInfo();
8152 // In Thumb mode S must not be specified if source register is the SP or
8153 // PC and if destination register is the SP, so restrict register class
8154 unsigned NewRsbDstReg =
8155 MRI.createVirtualRegister(isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass);
8157 // Transfer the remainder of BB and its successor edges to sinkMBB.
8158 SinkBB->splice(SinkBB->begin(), BB,
8159 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8160 SinkBB->transferSuccessorsAndUpdatePHIs(BB);
8162 BB->addSuccessor(RSBBB);
8163 BB->addSuccessor(SinkBB);
8165 // fall through to SinkMBB
8166 RSBBB->addSuccessor(SinkBB);
8168 // insert a cmp at the end of BB
8169 AddDefaultPred(BuildMI(BB, dl,
8170 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
8171 .addReg(ABSSrcReg).addImm(0));
8173 // insert a bcc with opposite CC to ARMCC::MI at the end of BB
8175 TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)).addMBB(SinkBB)
8176 .addImm(ARMCC::getOppositeCondition(ARMCC::MI)).addReg(ARM::CPSR);
8178 // insert rsbri in RSBBB
8179 // Note: BCC and rsbri will be converted into predicated rsbmi
8180 // by if-conversion pass
8181 BuildMI(*RSBBB, RSBBB->begin(), dl,
8182 TII->get(isThumb2 ? ARM::t2RSBri : ARM::RSBri), NewRsbDstReg)
8183 .addReg(ABSSrcReg, ABSSrcKIll ? RegState::Kill : 0)
8184 .addImm(0).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
8186 // insert PHI in SinkBB,
8187 // reuse ABSDstReg to not change uses of ABS instruction
8188 BuildMI(*SinkBB, SinkBB->begin(), dl,
8189 TII->get(ARM::PHI), ABSDstReg)
8190 .addReg(NewRsbDstReg).addMBB(RSBBB)
8191 .addReg(ABSSrcReg).addMBB(BB);
8193 // remove ABS instruction
8194 MI->eraseFromParent();
8196 // return last added BB
8199 case ARM::COPY_STRUCT_BYVAL_I32:
8201 return EmitStructByval(MI, BB);
8202 case ARM::WIN__CHKSTK:
8203 return EmitLowered__chkstk(MI, BB);
8204 case ARM::WIN__DBZCHK:
8205 return EmitLowered__dbzchk(MI, BB);
8209 /// \brief Attaches vregs to MEMCPY that it will use as scratch registers
8210 /// when it is expanded into LDM/STM. This is done as a post-isel lowering
8211 /// instead of as a custom inserter because we need the use list from the SDNode.
8212 static void attachMEMCPYScratchRegs(const ARMSubtarget *Subtarget,
8213 MachineInstr *MI, const SDNode *Node) {
8214 bool isThumb1 = Subtarget->isThumb1Only();
8216 DebugLoc DL = MI->getDebugLoc();
8217 MachineFunction *MF = MI->getParent()->getParent();
8218 MachineRegisterInfo &MRI = MF->getRegInfo();
8219 MachineInstrBuilder MIB(*MF, MI);
8221 // If the new dst/src is unused mark it as dead.
8222 if (!Node->hasAnyUseOfValue(0)) {
8223 MI->getOperand(0).setIsDead(true);
8225 if (!Node->hasAnyUseOfValue(1)) {
8226 MI->getOperand(1).setIsDead(true);
8229 // The MEMCPY both defines and kills the scratch registers.
8230 for (unsigned I = 0; I != MI->getOperand(4).getImm(); ++I) {
8231 unsigned TmpReg = MRI.createVirtualRegister(isThumb1 ? &ARM::tGPRRegClass
8232 : &ARM::GPRRegClass);
8233 MIB.addReg(TmpReg, RegState::Define|RegState::Dead);
8237 void ARMTargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
8238 SDNode *Node) const {
8239 if (MI->getOpcode() == ARM::MEMCPY) {
8240 attachMEMCPYScratchRegs(Subtarget, MI, Node);
8244 const MCInstrDesc *MCID = &MI->getDesc();
8245 // Adjust potentially 's' setting instructions after isel, i.e. ADC, SBC, RSB,
8246 // RSC. Coming out of isel, they have an implicit CPSR def, but the optional
8247 // operand is still set to noreg. If needed, set the optional operand's
8248 // register to CPSR, and remove the redundant implicit def.
8250 // e.g. ADCS (..., CPSR<imp-def>) -> ADC (... opt:CPSR<def>).
8252 // Rename pseudo opcodes.
8253 unsigned NewOpc = convertAddSubFlagsOpcode(MI->getOpcode());
8255 const ARMBaseInstrInfo *TII = Subtarget->getInstrInfo();
8256 MCID = &TII->get(NewOpc);
8258 assert(MCID->getNumOperands() == MI->getDesc().getNumOperands() + 1 &&
8259 "converted opcode should be the same except for cc_out");
8263 // Add the optional cc_out operand
8264 MI->addOperand(MachineOperand::CreateReg(0, /*isDef=*/true));
8266 unsigned ccOutIdx = MCID->getNumOperands() - 1;
8268 // Any ARM instruction that sets the 's' bit should specify an optional
8269 // "cc_out" operand in the last operand position.
8270 if (!MI->hasOptionalDef() || !MCID->OpInfo[ccOutIdx].isOptionalDef()) {
8271 assert(!NewOpc && "Optional cc_out operand required");
8274 // Look for an implicit def of CPSR added by MachineInstr ctor. Remove it
8275 // since we already have an optional CPSR def.
8276 bool definesCPSR = false;
8277 bool deadCPSR = false;
8278 for (unsigned i = MCID->getNumOperands(), e = MI->getNumOperands();
8280 const MachineOperand &MO = MI->getOperand(i);
8281 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) {
8285 MI->RemoveOperand(i);
8290 assert(!NewOpc && "Optional cc_out operand required");
8293 assert(deadCPSR == !Node->hasAnyUseOfValue(1) && "inconsistent dead flag");
8295 assert(!MI->getOperand(ccOutIdx).getReg() &&
8296 "expect uninitialized optional cc_out operand");
8300 // If this instruction was defined with an optional CPSR def and its dag node
8301 // had a live implicit CPSR def, then activate the optional CPSR def.
8302 MachineOperand &MO = MI->getOperand(ccOutIdx);
8303 MO.setReg(ARM::CPSR);
8307 //===----------------------------------------------------------------------===//
8308 // ARM Optimization Hooks
8309 //===----------------------------------------------------------------------===//
8311 // Helper function that checks if N is a null or all ones constant.
8312 static inline bool isZeroOrAllOnes(SDValue N, bool AllOnes) {
8313 return AllOnes ? isAllOnesConstant(N) : isNullConstant(N);
8316 // Return true if N is conditionally 0 or all ones.
8317 // Detects these expressions where cc is an i1 value:
8319 // (select cc 0, y) [AllOnes=0]
8320 // (select cc y, 0) [AllOnes=0]
8321 // (zext cc) [AllOnes=0]
8322 // (sext cc) [AllOnes=0/1]
8323 // (select cc -1, y) [AllOnes=1]
8324 // (select cc y, -1) [AllOnes=1]
8326 // Invert is set when N is the null/all ones constant when CC is false.
8327 // OtherOp is set to the alternative value of N.
8328 static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes,
8329 SDValue &CC, bool &Invert,
8331 SelectionDAG &DAG) {
8332 switch (N->getOpcode()) {
8333 default: return false;
8335 CC = N->getOperand(0);
8336 SDValue N1 = N->getOperand(1);
8337 SDValue N2 = N->getOperand(2);
8338 if (isZeroOrAllOnes(N1, AllOnes)) {
8343 if (isZeroOrAllOnes(N2, AllOnes)) {
8350 case ISD::ZERO_EXTEND:
8351 // (zext cc) can never be the all ones value.
8355 case ISD::SIGN_EXTEND: {
8357 EVT VT = N->getValueType(0);
8358 CC = N->getOperand(0);
8359 if (CC.getValueType() != MVT::i1)
8363 // When looking for an AllOnes constant, N is an sext, and the 'other'
8365 OtherOp = DAG.getConstant(0, dl, VT);
8366 else if (N->getOpcode() == ISD::ZERO_EXTEND)
8367 // When looking for a 0 constant, N can be zext or sext.
8368 OtherOp = DAG.getConstant(1, dl, VT);
8370 OtherOp = DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), dl,
8377 // Combine a constant select operand into its use:
8379 // (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
8380 // (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
8381 // (and (select cc, -1, c), x) -> (select cc, x, (and, x, c)) [AllOnes=1]
8382 // (or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
8383 // (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
8385 // The transform is rejected if the select doesn't have a constant operand that
8386 // is null, or all ones when AllOnes is set.
8388 // Also recognize sext/zext from i1:
8390 // (add (zext cc), x) -> (select cc (add x, 1), x)
8391 // (add (sext cc), x) -> (select cc (add x, -1), x)
8393 // These transformations eventually create predicated instructions.
8395 // @param N The node to transform.
8396 // @param Slct The N operand that is a select.
8397 // @param OtherOp The other N operand (x above).
8398 // @param DCI Context.
8399 // @param AllOnes Require the select constant to be all ones instead of null.
8400 // @returns The new node, or SDValue() on failure.
8402 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
8403 TargetLowering::DAGCombinerInfo &DCI,
8404 bool AllOnes = false) {
8405 SelectionDAG &DAG = DCI.DAG;
8406 EVT VT = N->getValueType(0);
8407 SDValue NonConstantVal;
8410 if (!isConditionalZeroOrAllOnes(Slct.getNode(), AllOnes, CCOp, SwapSelectOps,
8411 NonConstantVal, DAG))
8414 // Slct is now know to be the desired identity constant when CC is true.
8415 SDValue TrueVal = OtherOp;
8416 SDValue FalseVal = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
8417 OtherOp, NonConstantVal);
8418 // Unless SwapSelectOps says CC should be false.
8420 std::swap(TrueVal, FalseVal);
8422 return DAG.getNode(ISD::SELECT, SDLoc(N), VT,
8423 CCOp, TrueVal, FalseVal);
8426 // Attempt combineSelectAndUse on each operand of a commutative operator N.
8428 SDValue combineSelectAndUseCommutative(SDNode *N, bool AllOnes,
8429 TargetLowering::DAGCombinerInfo &DCI) {
8430 SDValue N0 = N->getOperand(0);
8431 SDValue N1 = N->getOperand(1);
8432 if (N0.getNode()->hasOneUse()) {
8433 SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes);
8434 if (Result.getNode())
8437 if (N1.getNode()->hasOneUse()) {
8438 SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes);
8439 if (Result.getNode())
8445 // AddCombineToVPADDL- For pair-wise add on neon, use the vpaddl instruction
8446 // (only after legalization).
8447 static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1,
8448 TargetLowering::DAGCombinerInfo &DCI,
8449 const ARMSubtarget *Subtarget) {
8451 // Only perform optimization if after legalize, and if NEON is available. We
8452 // also expected both operands to be BUILD_VECTORs.
8453 if (DCI.isBeforeLegalize() || !Subtarget->hasNEON()
8454 || N0.getOpcode() != ISD::BUILD_VECTOR
8455 || N1.getOpcode() != ISD::BUILD_VECTOR)
8458 // Check output type since VPADDL operand elements can only be 8, 16, or 32.
8459 EVT VT = N->getValueType(0);
8460 if (!VT.isInteger() || VT.getVectorElementType() == MVT::i64)
8463 // Check that the vector operands are of the right form.
8464 // N0 and N1 are BUILD_VECTOR nodes with N number of EXTRACT_VECTOR
8465 // operands, where N is the size of the formed vector.
8466 // Each EXTRACT_VECTOR should have the same input vector and odd or even
8467 // index such that we have a pair wise add pattern.
8469 // Grab the vector that all EXTRACT_VECTOR nodes should be referencing.
8470 if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
8472 SDValue Vec = N0->getOperand(0)->getOperand(0);
8473 SDNode *V = Vec.getNode();
8474 unsigned nextIndex = 0;
8476 // For each operands to the ADD which are BUILD_VECTORs,
8477 // check to see if each of their operands are an EXTRACT_VECTOR with
8478 // the same vector and appropriate index.
8479 for (unsigned i = 0, e = N0->getNumOperands(); i != e; ++i) {
8480 if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT
8481 && N1->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
8483 SDValue ExtVec0 = N0->getOperand(i);
8484 SDValue ExtVec1 = N1->getOperand(i);
8486 // First operand is the vector, verify its the same.
8487 if (V != ExtVec0->getOperand(0).getNode() ||
8488 V != ExtVec1->getOperand(0).getNode())
8491 // Second is the constant, verify its correct.
8492 ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(ExtVec0->getOperand(1));
8493 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(ExtVec1->getOperand(1));
8495 // For the constant, we want to see all the even or all the odd.
8496 if (!C0 || !C1 || C0->getZExtValue() != nextIndex
8497 || C1->getZExtValue() != nextIndex+1)
8506 // Create VPADDL node.
8507 SelectionDAG &DAG = DCI.DAG;
8508 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8512 // Build operand list.
8513 SmallVector<SDValue, 8> Ops;
8514 Ops.push_back(DAG.getConstant(Intrinsic::arm_neon_vpaddls, dl,
8515 TLI.getPointerTy(DAG.getDataLayout())));
8517 // Input is the vector.
8520 // Get widened type and narrowed type.
8522 unsigned numElem = VT.getVectorNumElements();
8524 EVT inputLaneType = Vec.getValueType().getVectorElementType();
8525 switch (inputLaneType.getSimpleVT().SimpleTy) {
8526 case MVT::i8: widenType = MVT::getVectorVT(MVT::i16, numElem); break;
8527 case MVT::i16: widenType = MVT::getVectorVT(MVT::i32, numElem); break;
8528 case MVT::i32: widenType = MVT::getVectorVT(MVT::i64, numElem); break;
8530 llvm_unreachable("Invalid vector element type for padd optimization.");
8533 SDValue tmp = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, widenType, Ops);
8534 unsigned ExtOp = VT.bitsGT(tmp.getValueType()) ? ISD::ANY_EXTEND : ISD::TRUNCATE;
8535 return DAG.getNode(ExtOp, dl, VT, tmp);
8538 static SDValue findMUL_LOHI(SDValue V) {
8539 if (V->getOpcode() == ISD::UMUL_LOHI ||
8540 V->getOpcode() == ISD::SMUL_LOHI)
8545 static SDValue AddCombineTo64bitMLAL(SDNode *AddcNode,
8546 TargetLowering::DAGCombinerInfo &DCI,
8547 const ARMSubtarget *Subtarget) {
8549 if (Subtarget->isThumb1Only()) return SDValue();
8551 // Only perform the checks after legalize when the pattern is available.
8552 if (DCI.isBeforeLegalize()) return SDValue();
8554 // Look for multiply add opportunities.
8555 // The pattern is a ISD::UMUL_LOHI followed by two add nodes, where
8556 // each add nodes consumes a value from ISD::UMUL_LOHI and there is
8557 // a glue link from the first add to the second add.
8558 // If we find this pattern, we can replace the U/SMUL_LOHI, ADDC, and ADDE by
8559 // a S/UMLAL instruction.
8562 // / \ [no multiline comment]
8568 assert(AddcNode->getOpcode() == ISD::ADDC && "Expect an ADDC");
8569 SDValue AddcOp0 = AddcNode->getOperand(0);
8570 SDValue AddcOp1 = AddcNode->getOperand(1);
8572 // Check if the two operands are from the same mul_lohi node.
8573 if (AddcOp0.getNode() == AddcOp1.getNode())
8576 assert(AddcNode->getNumValues() == 2 &&
8577 AddcNode->getValueType(0) == MVT::i32 &&
8578 "Expect ADDC with two result values. First: i32");
8580 // Check that we have a glued ADDC node.
8581 if (AddcNode->getValueType(1) != MVT::Glue)
8584 // Check that the ADDC adds the low result of the S/UMUL_LOHI.
8585 if (AddcOp0->getOpcode() != ISD::UMUL_LOHI &&
8586 AddcOp0->getOpcode() != ISD::SMUL_LOHI &&
8587 AddcOp1->getOpcode() != ISD::UMUL_LOHI &&
8588 AddcOp1->getOpcode() != ISD::SMUL_LOHI)
8591 // Look for the glued ADDE.
8592 SDNode* AddeNode = AddcNode->getGluedUser();
8596 // Make sure it is really an ADDE.
8597 if (AddeNode->getOpcode() != ISD::ADDE)
8600 assert(AddeNode->getNumOperands() == 3 &&
8601 AddeNode->getOperand(2).getValueType() == MVT::Glue &&
8602 "ADDE node has the wrong inputs");
8604 // Check for the triangle shape.
8605 SDValue AddeOp0 = AddeNode->getOperand(0);
8606 SDValue AddeOp1 = AddeNode->getOperand(1);
8608 // Make sure that the ADDE operands are not coming from the same node.
8609 if (AddeOp0.getNode() == AddeOp1.getNode())
8612 // Find the MUL_LOHI node walking up ADDE's operands.
8613 bool IsLeftOperandMUL = false;
8614 SDValue MULOp = findMUL_LOHI(AddeOp0);
8615 if (MULOp == SDValue())
8616 MULOp = findMUL_LOHI(AddeOp1);
8618 IsLeftOperandMUL = true;
8619 if (MULOp == SDValue())
8622 // Figure out the right opcode.
8623 unsigned Opc = MULOp->getOpcode();
8624 unsigned FinalOpc = (Opc == ISD::SMUL_LOHI) ? ARMISD::SMLAL : ARMISD::UMLAL;
8626 // Figure out the high and low input values to the MLAL node.
8627 SDValue* HiAdd = nullptr;
8628 SDValue* LoMul = nullptr;
8629 SDValue* LowAdd = nullptr;
8631 // Ensure that ADDE is from high result of ISD::SMUL_LOHI.
8632 if ((AddeOp0 != MULOp.getValue(1)) && (AddeOp1 != MULOp.getValue(1)))
8635 if (IsLeftOperandMUL)
8641 // Ensure that LoMul and LowAdd are taken from correct ISD::SMUL_LOHI node
8642 // whose low result is fed to the ADDC we are checking.
8644 if (AddcOp0 == MULOp.getValue(0)) {
8648 if (AddcOp1 == MULOp.getValue(0)) {
8656 // Create the merged node.
8657 SelectionDAG &DAG = DCI.DAG;
8659 // Build operand list.
8660 SmallVector<SDValue, 8> Ops;
8661 Ops.push_back(LoMul->getOperand(0));
8662 Ops.push_back(LoMul->getOperand(1));
8663 Ops.push_back(*LowAdd);
8664 Ops.push_back(*HiAdd);
8666 SDValue MLALNode = DAG.getNode(FinalOpc, SDLoc(AddcNode),
8667 DAG.getVTList(MVT::i32, MVT::i32), Ops);
8669 // Replace the ADDs' nodes uses by the MLA node's values.
8670 SDValue HiMLALResult(MLALNode.getNode(), 1);
8671 DAG.ReplaceAllUsesOfValueWith(SDValue(AddeNode, 0), HiMLALResult);
8673 SDValue LoMLALResult(MLALNode.getNode(), 0);
8674 DAG.ReplaceAllUsesOfValueWith(SDValue(AddcNode, 0), LoMLALResult);
8676 // Return original node to notify the driver to stop replacing.
8677 SDValue resNode(AddcNode, 0);
8681 /// PerformADDCCombine - Target-specific dag combine transform from
8682 /// ISD::ADDC, ISD::ADDE, and ISD::MUL_LOHI to MLAL.
8683 static SDValue PerformADDCCombine(SDNode *N,
8684 TargetLowering::DAGCombinerInfo &DCI,
8685 const ARMSubtarget *Subtarget) {
8687 return AddCombineTo64bitMLAL(N, DCI, Subtarget);
8691 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
8692 /// operands N0 and N1. This is a helper for PerformADDCombine that is
8693 /// called with the default operands, and if that fails, with commuted
8695 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
8696 TargetLowering::DAGCombinerInfo &DCI,
8697 const ARMSubtarget *Subtarget){
8699 // Attempt to create vpaddl for this add.
8700 SDValue Result = AddCombineToVPADDL(N, N0, N1, DCI, Subtarget);
8701 if (Result.getNode())
8704 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
8705 if (N0.getNode()->hasOneUse()) {
8706 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
8707 if (Result.getNode()) return Result;
8712 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
8714 static SDValue PerformADDCombine(SDNode *N,
8715 TargetLowering::DAGCombinerInfo &DCI,
8716 const ARMSubtarget *Subtarget) {
8717 SDValue N0 = N->getOperand(0);
8718 SDValue N1 = N->getOperand(1);
8720 // First try with the default operand order.
8721 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget);
8722 if (Result.getNode())
8725 // If that didn't work, try again with the operands commuted.
8726 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget);
8729 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
8731 static SDValue PerformSUBCombine(SDNode *N,
8732 TargetLowering::DAGCombinerInfo &DCI) {
8733 SDValue N0 = N->getOperand(0);
8734 SDValue N1 = N->getOperand(1);
8736 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
8737 if (N1.getNode()->hasOneUse()) {
8738 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
8739 if (Result.getNode()) return Result;
8745 /// PerformVMULCombine
8746 /// Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the
8747 /// special multiplier accumulator forwarding.
8753 // However, for (A + B) * (A + B),
8760 static SDValue PerformVMULCombine(SDNode *N,
8761 TargetLowering::DAGCombinerInfo &DCI,
8762 const ARMSubtarget *Subtarget) {
8763 if (!Subtarget->hasVMLxForwarding())
8766 SelectionDAG &DAG = DCI.DAG;
8767 SDValue N0 = N->getOperand(0);
8768 SDValue N1 = N->getOperand(1);
8769 unsigned Opcode = N0.getOpcode();
8770 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
8771 Opcode != ISD::FADD && Opcode != ISD::FSUB) {
8772 Opcode = N1.getOpcode();
8773 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
8774 Opcode != ISD::FADD && Opcode != ISD::FSUB)
8782 EVT VT = N->getValueType(0);
8784 SDValue N00 = N0->getOperand(0);
8785 SDValue N01 = N0->getOperand(1);
8786 return DAG.getNode(Opcode, DL, VT,
8787 DAG.getNode(ISD::MUL, DL, VT, N00, N1),
8788 DAG.getNode(ISD::MUL, DL, VT, N01, N1));
8791 static SDValue PerformMULCombine(SDNode *N,
8792 TargetLowering::DAGCombinerInfo &DCI,
8793 const ARMSubtarget *Subtarget) {
8794 SelectionDAG &DAG = DCI.DAG;
8796 if (Subtarget->isThumb1Only())
8799 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
8802 EVT VT = N->getValueType(0);
8803 if (VT.is64BitVector() || VT.is128BitVector())
8804 return PerformVMULCombine(N, DCI, Subtarget);
8808 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
8812 int64_t MulAmt = C->getSExtValue();
8813 unsigned ShiftAmt = countTrailingZeros<uint64_t>(MulAmt);
8815 ShiftAmt = ShiftAmt & (32 - 1);
8816 SDValue V = N->getOperand(0);
8820 MulAmt >>= ShiftAmt;
8823 if (isPowerOf2_32(MulAmt - 1)) {
8824 // (mul x, 2^N + 1) => (add (shl x, N), x)
8825 Res = DAG.getNode(ISD::ADD, DL, VT,
8827 DAG.getNode(ISD::SHL, DL, VT,
8829 DAG.getConstant(Log2_32(MulAmt - 1), DL,
8831 } else if (isPowerOf2_32(MulAmt + 1)) {
8832 // (mul x, 2^N - 1) => (sub (shl x, N), x)
8833 Res = DAG.getNode(ISD::SUB, DL, VT,
8834 DAG.getNode(ISD::SHL, DL, VT,
8836 DAG.getConstant(Log2_32(MulAmt + 1), DL,
8842 uint64_t MulAmtAbs = -MulAmt;
8843 if (isPowerOf2_32(MulAmtAbs + 1)) {
8844 // (mul x, -(2^N - 1)) => (sub x, (shl x, N))
8845 Res = DAG.getNode(ISD::SUB, DL, VT,
8847 DAG.getNode(ISD::SHL, DL, VT,
8849 DAG.getConstant(Log2_32(MulAmtAbs + 1), DL,
8851 } else if (isPowerOf2_32(MulAmtAbs - 1)) {
8852 // (mul x, -(2^N + 1)) => - (add (shl x, N), x)
8853 Res = DAG.getNode(ISD::ADD, DL, VT,
8855 DAG.getNode(ISD::SHL, DL, VT,
8857 DAG.getConstant(Log2_32(MulAmtAbs - 1), DL,
8859 Res = DAG.getNode(ISD::SUB, DL, VT,
8860 DAG.getConstant(0, DL, MVT::i32), Res);
8867 Res = DAG.getNode(ISD::SHL, DL, VT,
8868 Res, DAG.getConstant(ShiftAmt, DL, MVT::i32));
8870 // Do not add new nodes to DAG combiner worklist.
8871 DCI.CombineTo(N, Res, false);
8875 static SDValue PerformANDCombine(SDNode *N,
8876 TargetLowering::DAGCombinerInfo &DCI,
8877 const ARMSubtarget *Subtarget) {
8879 // Attempt to use immediate-form VBIC
8880 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
8882 EVT VT = N->getValueType(0);
8883 SelectionDAG &DAG = DCI.DAG;
8885 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
8888 APInt SplatBits, SplatUndef;
8889 unsigned SplatBitSize;
8892 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
8893 if (SplatBitSize <= 64) {
8895 SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(),
8896 SplatUndef.getZExtValue(), SplatBitSize,
8897 DAG, dl, VbicVT, VT.is128BitVector(),
8899 if (Val.getNode()) {
8901 DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0));
8902 SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val);
8903 return DAG.getNode(ISD::BITCAST, dl, VT, Vbic);
8908 if (!Subtarget->isThumb1Only()) {
8909 // fold (and (select cc, -1, c), x) -> (select cc, x, (and, x, c))
8910 SDValue Result = combineSelectAndUseCommutative(N, true, DCI);
8911 if (Result.getNode())
8918 /// PerformORCombine - Target-specific dag combine xforms for ISD::OR
8919 static SDValue PerformORCombine(SDNode *N,
8920 TargetLowering::DAGCombinerInfo &DCI,
8921 const ARMSubtarget *Subtarget) {
8922 // Attempt to use immediate-form VORR
8923 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
8925 EVT VT = N->getValueType(0);
8926 SelectionDAG &DAG = DCI.DAG;
8928 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
8931 APInt SplatBits, SplatUndef;
8932 unsigned SplatBitSize;
8934 if (BVN && Subtarget->hasNEON() &&
8935 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
8936 if (SplatBitSize <= 64) {
8938 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
8939 SplatUndef.getZExtValue(), SplatBitSize,
8940 DAG, dl, VorrVT, VT.is128BitVector(),
8942 if (Val.getNode()) {
8944 DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0));
8945 SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val);
8946 return DAG.getNode(ISD::BITCAST, dl, VT, Vorr);
8951 if (!Subtarget->isThumb1Only()) {
8952 // fold (or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
8953 SDValue Result = combineSelectAndUseCommutative(N, false, DCI);
8954 if (Result.getNode())
8958 // The code below optimizes (or (and X, Y), Z).
8959 // The AND operand needs to have a single user to make these optimizations
8961 SDValue N0 = N->getOperand(0);
8962 if (N0.getOpcode() != ISD::AND || !N0.hasOneUse())
8964 SDValue N1 = N->getOperand(1);
8966 // (or (and B, A), (and C, ~A)) => (VBSL A, B, C) when A is a constant.
8967 if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() &&
8968 DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
8970 unsigned SplatBitSize;
8973 APInt SplatBits0, SplatBits1;
8974 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1));
8975 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(1));
8976 // Ensure that the second operand of both ands are constants
8977 if (BVN0 && BVN0->isConstantSplat(SplatBits0, SplatUndef, SplatBitSize,
8978 HasAnyUndefs) && !HasAnyUndefs) {
8979 if (BVN1 && BVN1->isConstantSplat(SplatBits1, SplatUndef, SplatBitSize,
8980 HasAnyUndefs) && !HasAnyUndefs) {
8981 // Ensure that the bit width of the constants are the same and that
8982 // the splat arguments are logical inverses as per the pattern we
8983 // are trying to simplify.
8984 if (SplatBits0.getBitWidth() == SplatBits1.getBitWidth() &&
8985 SplatBits0 == ~SplatBits1) {
8986 // Canonicalize the vector type to make instruction selection
8988 EVT CanonicalVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
8989 SDValue Result = DAG.getNode(ARMISD::VBSL, dl, CanonicalVT,
8993 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
8999 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when
9002 // BFI is only available on V6T2+
9003 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops())
9007 // 1) or (and A, mask), val => ARMbfi A, val, mask
9008 // iff (val & mask) == val
9010 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
9011 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2)
9012 // && mask == ~mask2
9013 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2)
9014 // && ~mask == mask2
9015 // (i.e., copy a bitfield value into another bitfield of the same width)
9020 SDValue N00 = N0.getOperand(0);
9022 // The value and the mask need to be constants so we can verify this is
9023 // actually a bitfield set. If the mask is 0xffff, we can do better
9024 // via a movt instruction, so don't use BFI in that case.
9025 SDValue MaskOp = N0.getOperand(1);
9026 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(MaskOp);
9029 unsigned Mask = MaskC->getZExtValue();
9033 // Case (1): or (and A, mask), val => ARMbfi A, val, mask
9034 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
9036 unsigned Val = N1C->getZExtValue();
9037 if ((Val & ~Mask) != Val)
9040 if (ARM::isBitFieldInvertedMask(Mask)) {
9041 Val >>= countTrailingZeros(~Mask);
9043 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00,
9044 DAG.getConstant(Val, DL, MVT::i32),
9045 DAG.getConstant(Mask, DL, MVT::i32));
9047 // Do not add new nodes to DAG combiner worklist.
9048 DCI.CombineTo(N, Res, false);
9051 } else if (N1.getOpcode() == ISD::AND) {
9052 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
9053 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
9056 unsigned Mask2 = N11C->getZExtValue();
9058 // Mask and ~Mask2 (or reverse) must be equivalent for the BFI pattern
9060 if (ARM::isBitFieldInvertedMask(Mask) &&
9062 // The pack halfword instruction works better for masks that fit it,
9063 // so use that when it's available.
9064 if (Subtarget->hasT2ExtractPack() &&
9065 (Mask == 0xffff || Mask == 0xffff0000))
9068 unsigned amt = countTrailingZeros(Mask2);
9069 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
9070 DAG.getConstant(amt, DL, MVT::i32));
9071 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res,
9072 DAG.getConstant(Mask, DL, MVT::i32));
9073 // Do not add new nodes to DAG combiner worklist.
9074 DCI.CombineTo(N, Res, false);
9076 } else if (ARM::isBitFieldInvertedMask(~Mask) &&
9078 // The pack halfword instruction works better for masks that fit it,
9079 // so use that when it's available.
9080 if (Subtarget->hasT2ExtractPack() &&
9081 (Mask2 == 0xffff || Mask2 == 0xffff0000))
9084 unsigned lsb = countTrailingZeros(Mask);
9085 Res = DAG.getNode(ISD::SRL, DL, VT, N00,
9086 DAG.getConstant(lsb, DL, MVT::i32));
9087 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
9088 DAG.getConstant(Mask2, DL, MVT::i32));
9089 // Do not add new nodes to DAG combiner worklist.
9090 DCI.CombineTo(N, Res, false);
9095 if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) &&
9096 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) &&
9097 ARM::isBitFieldInvertedMask(~Mask)) {
9098 // Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask
9099 // where lsb(mask) == #shamt and masked bits of B are known zero.
9100 SDValue ShAmt = N00.getOperand(1);
9101 unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue();
9102 unsigned LSB = countTrailingZeros(Mask);
9106 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0),
9107 DAG.getConstant(~Mask, DL, MVT::i32));
9109 // Do not add new nodes to DAG combiner worklist.
9110 DCI.CombineTo(N, Res, false);
9116 static SDValue PerformXORCombine(SDNode *N,
9117 TargetLowering::DAGCombinerInfo &DCI,
9118 const ARMSubtarget *Subtarget) {
9119 EVT VT = N->getValueType(0);
9120 SelectionDAG &DAG = DCI.DAG;
9122 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
9125 if (!Subtarget->isThumb1Only()) {
9126 // fold (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
9127 SDValue Result = combineSelectAndUseCommutative(N, false, DCI);
9128 if (Result.getNode())
9135 // ParseBFI - given a BFI instruction in N, extract the "from" value (Rn) and return it,
9136 // and fill in FromMask and ToMask with (consecutive) bits in "from" to be extracted and
9137 // their position in "to" (Rd).
9138 static SDValue ParseBFI(SDNode *N, APInt &ToMask, APInt &FromMask) {
9139 assert(N->getOpcode() == ARMISD::BFI);
9141 SDValue From = N->getOperand(1);
9142 ToMask = ~cast<ConstantSDNode>(N->getOperand(2))->getAPIntValue();
9143 FromMask = APInt::getLowBitsSet(ToMask.getBitWidth(), ToMask.countPopulation());
9145 // If the Base came from a SHR #C, we can deduce that it is really testing bit
9146 // #C in the base of the SHR.
9147 if (From->getOpcode() == ISD::SRL &&
9148 isa<ConstantSDNode>(From->getOperand(1))) {
9149 APInt Shift = cast<ConstantSDNode>(From->getOperand(1))->getAPIntValue();
9150 assert(Shift.getLimitedValue() < 32 && "Shift too large!");
9151 FromMask <<= Shift.getLimitedValue(31);
9152 From = From->getOperand(0);
9158 // If A and B contain one contiguous set of bits, does A | B == A . B?
9160 // Neither A nor B must be zero.
9161 static bool BitsProperlyConcatenate(const APInt &A, const APInt &B) {
9162 unsigned LastActiveBitInA = A.countTrailingZeros();
9163 unsigned FirstActiveBitInB = B.getBitWidth() - B.countLeadingZeros() - 1;
9164 return LastActiveBitInA - 1 == FirstActiveBitInB;
9167 static SDValue FindBFIToCombineWith(SDNode *N) {
9168 // We have a BFI in N. Follow a possible chain of BFIs and find a BFI it can combine with,
9170 APInt ToMask, FromMask;
9171 SDValue From = ParseBFI(N, ToMask, FromMask);
9172 SDValue To = N->getOperand(0);
9174 // Now check for a compatible BFI to merge with. We can pass through BFIs that
9175 // aren't compatible, but not if they set the same bit in their destination as
9176 // we do (or that of any BFI we're going to combine with).
9178 APInt CombinedToMask = ToMask;
9179 while (V.getOpcode() == ARMISD::BFI) {
9180 APInt NewToMask, NewFromMask;
9181 SDValue NewFrom = ParseBFI(V.getNode(), NewToMask, NewFromMask);
9182 if (NewFrom != From) {
9183 // This BFI has a different base. Keep going.
9184 CombinedToMask |= NewToMask;
9185 V = V.getOperand(0);
9189 // Do the written bits conflict with any we've seen so far?
9190 if ((NewToMask & CombinedToMask).getBoolValue())
9191 // Conflicting bits - bail out because going further is unsafe.
9194 // Are the new bits contiguous when combined with the old bits?
9195 if (BitsProperlyConcatenate(ToMask, NewToMask) &&
9196 BitsProperlyConcatenate(FromMask, NewFromMask))
9198 if (BitsProperlyConcatenate(NewToMask, ToMask) &&
9199 BitsProperlyConcatenate(NewFromMask, FromMask))
9202 // We've seen a write to some bits, so track it.
9203 CombinedToMask |= NewToMask;
9205 V = V.getOperand(0);
9211 static SDValue PerformBFICombine(SDNode *N,
9212 TargetLowering::DAGCombinerInfo &DCI) {
9213 SDValue N1 = N->getOperand(1);
9214 if (N1.getOpcode() == ISD::AND) {
9215 // (bfi A, (and B, Mask1), Mask2) -> (bfi A, B, Mask2) iff
9216 // the bits being cleared by the AND are not demanded by the BFI.
9217 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
9220 unsigned InvMask = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
9221 unsigned LSB = countTrailingZeros(~InvMask);
9222 unsigned Width = (32 - countLeadingZeros(~InvMask)) - LSB;
9224 static_cast<unsigned>(std::numeric_limits<unsigned>::digits) &&
9225 "undefined behavior");
9226 unsigned Mask = (1u << Width) - 1;
9227 unsigned Mask2 = N11C->getZExtValue();
9228 if ((Mask & (~Mask2)) == 0)
9229 return DCI.DAG.getNode(ARMISD::BFI, SDLoc(N), N->getValueType(0),
9230 N->getOperand(0), N1.getOperand(0),
9232 } else if (N->getOperand(0).getOpcode() == ARMISD::BFI) {
9233 // We have a BFI of a BFI. Walk up the BFI chain to see how long it goes.
9234 // Keep track of any consecutive bits set that all come from the same base
9235 // value. We can combine these together into a single BFI.
9236 SDValue CombineBFI = FindBFIToCombineWith(N);
9237 if (CombineBFI == SDValue())
9240 // We've found a BFI.
9241 APInt ToMask1, FromMask1;
9242 SDValue From1 = ParseBFI(N, ToMask1, FromMask1);
9244 APInt ToMask2, FromMask2;
9245 SDValue From2 = ParseBFI(CombineBFI.getNode(), ToMask2, FromMask2);
9246 assert(From1 == From2);
9249 // First, unlink CombineBFI.
9250 DCI.DAG.ReplaceAllUsesWith(CombineBFI, CombineBFI.getOperand(0));
9251 // Then create a new BFI, combining the two together.
9252 APInt NewFromMask = FromMask1 | FromMask2;
9253 APInt NewToMask = ToMask1 | ToMask2;
9255 EVT VT = N->getValueType(0);
9258 if (NewFromMask[0] == 0)
9259 From1 = DCI.DAG.getNode(
9260 ISD::SRL, dl, VT, From1,
9261 DCI.DAG.getConstant(NewFromMask.countTrailingZeros(), dl, VT));
9262 return DCI.DAG.getNode(ARMISD::BFI, dl, VT, N->getOperand(0), From1,
9263 DCI.DAG.getConstant(~NewToMask, dl, VT));
9268 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
9269 /// ARMISD::VMOVRRD.
9270 static SDValue PerformVMOVRRDCombine(SDNode *N,
9271 TargetLowering::DAGCombinerInfo &DCI,
9272 const ARMSubtarget *Subtarget) {
9273 // vmovrrd(vmovdrr x, y) -> x,y
9274 SDValue InDouble = N->getOperand(0);
9275 if (InDouble.getOpcode() == ARMISD::VMOVDRR && !Subtarget->isFPOnlySP())
9276 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
9278 // vmovrrd(load f64) -> (load i32), (load i32)
9279 SDNode *InNode = InDouble.getNode();
9280 if (ISD::isNormalLoad(InNode) && InNode->hasOneUse() &&
9281 InNode->getValueType(0) == MVT::f64 &&
9282 InNode->getOperand(1).getOpcode() == ISD::FrameIndex &&
9283 !cast<LoadSDNode>(InNode)->isVolatile()) {
9284 // TODO: Should this be done for non-FrameIndex operands?
9285 LoadSDNode *LD = cast<LoadSDNode>(InNode);
9287 SelectionDAG &DAG = DCI.DAG;
9289 SDValue BasePtr = LD->getBasePtr();
9290 SDValue NewLD1 = DAG.getLoad(MVT::i32, DL, LD->getChain(), BasePtr,
9291 LD->getPointerInfo(), LD->isVolatile(),
9292 LD->isNonTemporal(), LD->isInvariant(),
9293 LD->getAlignment());
9295 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
9296 DAG.getConstant(4, DL, MVT::i32));
9297 SDValue NewLD2 = DAG.getLoad(MVT::i32, DL, NewLD1.getValue(1), OffsetPtr,
9298 LD->getPointerInfo(), LD->isVolatile(),
9299 LD->isNonTemporal(), LD->isInvariant(),
9300 std::min(4U, LD->getAlignment() / 2));
9302 DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), NewLD2.getValue(1));
9303 if (DCI.DAG.getDataLayout().isBigEndian())
9304 std::swap (NewLD1, NewLD2);
9305 SDValue Result = DCI.CombineTo(N, NewLD1, NewLD2);
9312 /// PerformVMOVDRRCombine - Target-specific dag combine xforms for
9313 /// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands.
9314 static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) {
9315 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X)
9316 SDValue Op0 = N->getOperand(0);
9317 SDValue Op1 = N->getOperand(1);
9318 if (Op0.getOpcode() == ISD::BITCAST)
9319 Op0 = Op0.getOperand(0);
9320 if (Op1.getOpcode() == ISD::BITCAST)
9321 Op1 = Op1.getOperand(0);
9322 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
9323 Op0.getNode() == Op1.getNode() &&
9324 Op0.getResNo() == 0 && Op1.getResNo() == 1)
9325 return DAG.getNode(ISD::BITCAST, SDLoc(N),
9326 N->getValueType(0), Op0.getOperand(0));
9330 /// hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node
9331 /// are normal, non-volatile loads. If so, it is profitable to bitcast an
9332 /// i64 vector to have f64 elements, since the value can then be loaded
9333 /// directly into a VFP register.
9334 static bool hasNormalLoadOperand(SDNode *N) {
9335 unsigned NumElts = N->getValueType(0).getVectorNumElements();
9336 for (unsigned i = 0; i < NumElts; ++i) {
9337 SDNode *Elt = N->getOperand(i).getNode();
9338 if (ISD::isNormalLoad(Elt) && !cast<LoadSDNode>(Elt)->isVolatile())
9344 /// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for
9345 /// ISD::BUILD_VECTOR.
9346 static SDValue PerformBUILD_VECTORCombine(SDNode *N,
9347 TargetLowering::DAGCombinerInfo &DCI,
9348 const ARMSubtarget *Subtarget) {
9349 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X):
9350 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value
9351 // into a pair of GPRs, which is fine when the value is used as a scalar,
9352 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD.
9353 SelectionDAG &DAG = DCI.DAG;
9354 if (N->getNumOperands() == 2) {
9355 SDValue RV = PerformVMOVDRRCombine(N, DAG);
9360 // Load i64 elements as f64 values so that type legalization does not split
9361 // them up into i32 values.
9362 EVT VT = N->getValueType(0);
9363 if (VT.getVectorElementType() != MVT::i64 || !hasNormalLoadOperand(N))
9366 SmallVector<SDValue, 8> Ops;
9367 unsigned NumElts = VT.getVectorNumElements();
9368 for (unsigned i = 0; i < NumElts; ++i) {
9369 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(i));
9371 // Make the DAGCombiner fold the bitcast.
9372 DCI.AddToWorklist(V.getNode());
9374 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, NumElts);
9375 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, FloatVT, Ops);
9376 return DAG.getNode(ISD::BITCAST, dl, VT, BV);
9379 /// \brief Target-specific dag combine xforms for ARMISD::BUILD_VECTOR.
9381 PerformARMBUILD_VECTORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
9382 // ARMISD::BUILD_VECTOR is introduced when legalizing ISD::BUILD_VECTOR.
9383 // At that time, we may have inserted bitcasts from integer to float.
9384 // If these bitcasts have survived DAGCombine, change the lowering of this
9385 // BUILD_VECTOR in something more vector friendly, i.e., that does not
9386 // force to use floating point types.
9388 // Make sure we can change the type of the vector.
9389 // This is possible iff:
9390 // 1. The vector is only used in a bitcast to a integer type. I.e.,
9391 // 1.1. Vector is used only once.
9392 // 1.2. Use is a bit convert to an integer type.
9393 // 2. The size of its operands are 32-bits (64-bits are not legal).
9394 EVT VT = N->getValueType(0);
9395 EVT EltVT = VT.getVectorElementType();
9397 // Check 1.1. and 2.
9398 if (EltVT.getSizeInBits() != 32 || !N->hasOneUse())
9401 // By construction, the input type must be float.
9402 assert(EltVT == MVT::f32 && "Unexpected type!");
9405 SDNode *Use = *N->use_begin();
9406 if (Use->getOpcode() != ISD::BITCAST ||
9407 Use->getValueType(0).isFloatingPoint())
9410 // Check profitability.
9411 // Model is, if more than half of the relevant operands are bitcast from
9412 // i32, turn the build_vector into a sequence of insert_vector_elt.
9413 // Relevant operands are everything that is not statically
9414 // (i.e., at compile time) bitcasted.
9415 unsigned NumOfBitCastedElts = 0;
9416 unsigned NumElts = VT.getVectorNumElements();
9417 unsigned NumOfRelevantElts = NumElts;
9418 for (unsigned Idx = 0; Idx < NumElts; ++Idx) {
9419 SDValue Elt = N->getOperand(Idx);
9420 if (Elt->getOpcode() == ISD::BITCAST) {
9421 // Assume only bit cast to i32 will go away.
9422 if (Elt->getOperand(0).getValueType() == MVT::i32)
9423 ++NumOfBitCastedElts;
9424 } else if (Elt.getOpcode() == ISD::UNDEF || isa<ConstantSDNode>(Elt))
9425 // Constants are statically casted, thus do not count them as
9426 // relevant operands.
9427 --NumOfRelevantElts;
9430 // Check if more than half of the elements require a non-free bitcast.
9431 if (NumOfBitCastedElts <= NumOfRelevantElts / 2)
9434 SelectionDAG &DAG = DCI.DAG;
9435 // Create the new vector type.
9436 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
9437 // Check if the type is legal.
9438 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9439 if (!TLI.isTypeLegal(VecVT))
9443 // ARMISD::BUILD_VECTOR E1, E2, ..., EN.
9444 // => BITCAST INSERT_VECTOR_ELT
9445 // (INSERT_VECTOR_ELT (...), (BITCAST EN-1), N-1),
9447 SDValue Vec = DAG.getUNDEF(VecVT);
9449 for (unsigned Idx = 0 ; Idx < NumElts; ++Idx) {
9450 SDValue V = N->getOperand(Idx);
9451 if (V.getOpcode() == ISD::UNDEF)
9453 if (V.getOpcode() == ISD::BITCAST &&
9454 V->getOperand(0).getValueType() == MVT::i32)
9455 // Fold obvious case.
9456 V = V.getOperand(0);
9458 V = DAG.getNode(ISD::BITCAST, SDLoc(V), MVT::i32, V);
9459 // Make the DAGCombiner fold the bitcasts.
9460 DCI.AddToWorklist(V.getNode());
9462 SDValue LaneIdx = DAG.getConstant(Idx, dl, MVT::i32);
9463 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecVT, Vec, V, LaneIdx);
9465 Vec = DAG.getNode(ISD::BITCAST, dl, VT, Vec);
9466 // Make the DAGCombiner fold the bitcasts.
9467 DCI.AddToWorklist(Vec.getNode());
9471 /// PerformInsertEltCombine - Target-specific dag combine xforms for
9472 /// ISD::INSERT_VECTOR_ELT.
9473 static SDValue PerformInsertEltCombine(SDNode *N,
9474 TargetLowering::DAGCombinerInfo &DCI) {
9475 // Bitcast an i64 load inserted into a vector to f64.
9476 // Otherwise, the i64 value will be legalized to a pair of i32 values.
9477 EVT VT = N->getValueType(0);
9478 SDNode *Elt = N->getOperand(1).getNode();
9479 if (VT.getVectorElementType() != MVT::i64 ||
9480 !ISD::isNormalLoad(Elt) || cast<LoadSDNode>(Elt)->isVolatile())
9483 SelectionDAG &DAG = DCI.DAG;
9485 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
9486 VT.getVectorNumElements());
9487 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, N->getOperand(0));
9488 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(1));
9489 // Make the DAGCombiner fold the bitcasts.
9490 DCI.AddToWorklist(Vec.getNode());
9491 DCI.AddToWorklist(V.getNode());
9492 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT,
9493 Vec, V, N->getOperand(2));
9494 return DAG.getNode(ISD::BITCAST, dl, VT, InsElt);
9497 /// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for
9498 /// ISD::VECTOR_SHUFFLE.
9499 static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) {
9500 // The LLVM shufflevector instruction does not require the shuffle mask
9501 // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does
9502 // have that requirement. When translating to ISD::VECTOR_SHUFFLE, if the
9503 // operands do not match the mask length, they are extended by concatenating
9504 // them with undef vectors. That is probably the right thing for other
9505 // targets, but for NEON it is better to concatenate two double-register
9506 // size vector operands into a single quad-register size vector. Do that
9507 // transformation here:
9508 // shuffle(concat(v1, undef), concat(v2, undef)) ->
9509 // shuffle(concat(v1, v2), undef)
9510 SDValue Op0 = N->getOperand(0);
9511 SDValue Op1 = N->getOperand(1);
9512 if (Op0.getOpcode() != ISD::CONCAT_VECTORS ||
9513 Op1.getOpcode() != ISD::CONCAT_VECTORS ||
9514 Op0.getNumOperands() != 2 ||
9515 Op1.getNumOperands() != 2)
9517 SDValue Concat0Op1 = Op0.getOperand(1);
9518 SDValue Concat1Op1 = Op1.getOperand(1);
9519 if (Concat0Op1.getOpcode() != ISD::UNDEF ||
9520 Concat1Op1.getOpcode() != ISD::UNDEF)
9522 // Skip the transformation if any of the types are illegal.
9523 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9524 EVT VT = N->getValueType(0);
9525 if (!TLI.isTypeLegal(VT) ||
9526 !TLI.isTypeLegal(Concat0Op1.getValueType()) ||
9527 !TLI.isTypeLegal(Concat1Op1.getValueType()))
9530 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT,
9531 Op0.getOperand(0), Op1.getOperand(0));
9532 // Translate the shuffle mask.
9533 SmallVector<int, 16> NewMask;
9534 unsigned NumElts = VT.getVectorNumElements();
9535 unsigned HalfElts = NumElts/2;
9536 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
9537 for (unsigned n = 0; n < NumElts; ++n) {
9538 int MaskElt = SVN->getMaskElt(n);
9540 if (MaskElt < (int)HalfElts)
9542 else if (MaskElt >= (int)NumElts && MaskElt < (int)(NumElts + HalfElts))
9543 NewElt = HalfElts + MaskElt - NumElts;
9544 NewMask.push_back(NewElt);
9546 return DAG.getVectorShuffle(VT, SDLoc(N), NewConcat,
9547 DAG.getUNDEF(VT), NewMask.data());
9550 /// CombineBaseUpdate - Target-specific DAG combine function for VLDDUP,
9551 /// NEON load/store intrinsics, and generic vector load/stores, to merge
9552 /// base address updates.
9553 /// For generic load/stores, the memory type is assumed to be a vector.
9554 /// The caller is assumed to have checked legality.
9555 static SDValue CombineBaseUpdate(SDNode *N,
9556 TargetLowering::DAGCombinerInfo &DCI) {
9557 SelectionDAG &DAG = DCI.DAG;
9558 const bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID ||
9559 N->getOpcode() == ISD::INTRINSIC_W_CHAIN);
9560 const bool isStore = N->getOpcode() == ISD::STORE;
9561 const unsigned AddrOpIdx = ((isIntrinsic || isStore) ? 2 : 1);
9562 SDValue Addr = N->getOperand(AddrOpIdx);
9563 MemSDNode *MemN = cast<MemSDNode>(N);
9566 // Search for a use of the address operand that is an increment.
9567 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
9568 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
9570 if (User->getOpcode() != ISD::ADD ||
9571 UI.getUse().getResNo() != Addr.getResNo())
9574 // Check that the add is independent of the load/store. Otherwise, folding
9575 // it would create a cycle.
9576 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
9579 // Find the new opcode for the updating load/store.
9580 bool isLoadOp = true;
9581 bool isLaneOp = false;
9582 unsigned NewOpc = 0;
9583 unsigned NumVecs = 0;
9585 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
9587 default: llvm_unreachable("unexpected intrinsic for Neon base update");
9588 case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD;
9590 case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD;
9592 case Intrinsic::arm_neon_vld3: NewOpc = ARMISD::VLD3_UPD;
9594 case Intrinsic::arm_neon_vld4: NewOpc = ARMISD::VLD4_UPD;
9596 case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD;
9597 NumVecs = 2; isLaneOp = true; break;
9598 case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD;
9599 NumVecs = 3; isLaneOp = true; break;
9600 case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD;
9601 NumVecs = 4; isLaneOp = true; break;
9602 case Intrinsic::arm_neon_vst1: NewOpc = ARMISD::VST1_UPD;
9603 NumVecs = 1; isLoadOp = false; break;
9604 case Intrinsic::arm_neon_vst2: NewOpc = ARMISD::VST2_UPD;
9605 NumVecs = 2; isLoadOp = false; break;
9606 case Intrinsic::arm_neon_vst3: NewOpc = ARMISD::VST3_UPD;
9607 NumVecs = 3; isLoadOp = false; break;
9608 case Intrinsic::arm_neon_vst4: NewOpc = ARMISD::VST4_UPD;
9609 NumVecs = 4; isLoadOp = false; break;
9610 case Intrinsic::arm_neon_vst2lane: NewOpc = ARMISD::VST2LN_UPD;
9611 NumVecs = 2; isLoadOp = false; isLaneOp = true; break;
9612 case Intrinsic::arm_neon_vst3lane: NewOpc = ARMISD::VST3LN_UPD;
9613 NumVecs = 3; isLoadOp = false; isLaneOp = true; break;
9614 case Intrinsic::arm_neon_vst4lane: NewOpc = ARMISD::VST4LN_UPD;
9615 NumVecs = 4; isLoadOp = false; isLaneOp = true; break;
9619 switch (N->getOpcode()) {
9620 default: llvm_unreachable("unexpected opcode for Neon base update");
9621 case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break;
9622 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break;
9623 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break;
9624 case ISD::LOAD: NewOpc = ARMISD::VLD1_UPD;
9625 NumVecs = 1; isLaneOp = false; break;
9626 case ISD::STORE: NewOpc = ARMISD::VST1_UPD;
9627 NumVecs = 1; isLaneOp = false; isLoadOp = false; break;
9631 // Find the size of memory referenced by the load/store.
9634 VecTy = N->getValueType(0);
9635 } else if (isIntrinsic) {
9636 VecTy = N->getOperand(AddrOpIdx+1).getValueType();
9638 assert(isStore && "Node has to be a load, a store, or an intrinsic!");
9639 VecTy = N->getOperand(1).getValueType();
9642 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
9644 NumBytes /= VecTy.getVectorNumElements();
9646 // If the increment is a constant, it must match the memory ref size.
9647 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
9648 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
9649 uint64_t IncVal = CInc->getZExtValue();
9650 if (IncVal != NumBytes)
9652 } else if (NumBytes >= 3 * 16) {
9653 // VLD3/4 and VST3/4 for 128-bit vectors are implemented with two
9654 // separate instructions that make it harder to use a non-constant update.
9658 // OK, we found an ADD we can fold into the base update.
9659 // Now, create a _UPD node, taking care of not breaking alignment.
9661 EVT AlignedVecTy = VecTy;
9662 unsigned Alignment = MemN->getAlignment();
9664 // If this is a less-than-standard-aligned load/store, change the type to
9665 // match the standard alignment.
9666 // The alignment is overlooked when selecting _UPD variants; and it's
9667 // easier to introduce bitcasts here than fix that.
9668 // There are 3 ways to get to this base-update combine:
9669 // - intrinsics: they are assumed to be properly aligned (to the standard
9670 // alignment of the memory type), so we don't need to do anything.
9671 // - ARMISD::VLDx nodes: they are only generated from the aforementioned
9672 // intrinsics, so, likewise, there's nothing to do.
9673 // - generic load/store instructions: the alignment is specified as an
9674 // explicit operand, rather than implicitly as the standard alignment
9675 // of the memory type (like the intrisics). We need to change the
9676 // memory type to match the explicit alignment. That way, we don't
9677 // generate non-standard-aligned ARMISD::VLDx nodes.
9678 if (isa<LSBaseSDNode>(N)) {
9681 if (Alignment < VecTy.getScalarSizeInBits() / 8) {
9682 MVT EltTy = MVT::getIntegerVT(Alignment * 8);
9683 assert(NumVecs == 1 && "Unexpected multi-element generic load/store.");
9684 assert(!isLaneOp && "Unexpected generic load/store lane.");
9685 unsigned NumElts = NumBytes / (EltTy.getSizeInBits() / 8);
9686 AlignedVecTy = MVT::getVectorVT(EltTy, NumElts);
9688 // Don't set an explicit alignment on regular load/stores that we want
9689 // to transform to VLD/VST 1_UPD nodes.
9690 // This matches the behavior of regular load/stores, which only get an
9691 // explicit alignment if the MMO alignment is larger than the standard
9692 // alignment of the memory type.
9693 // Intrinsics, however, always get an explicit alignment, set to the
9694 // alignment of the MMO.
9698 // Create the new updating load/store node.
9699 // First, create an SDVTList for the new updating node's results.
9701 unsigned NumResultVecs = (isLoadOp ? NumVecs : 0);
9703 for (n = 0; n < NumResultVecs; ++n)
9704 Tys[n] = AlignedVecTy;
9705 Tys[n++] = MVT::i32;
9706 Tys[n] = MVT::Other;
9707 SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumResultVecs+2));
9709 // Then, gather the new node's operands.
9710 SmallVector<SDValue, 8> Ops;
9711 Ops.push_back(N->getOperand(0)); // incoming chain
9712 Ops.push_back(N->getOperand(AddrOpIdx));
9715 if (StoreSDNode *StN = dyn_cast<StoreSDNode>(N)) {
9716 // Try to match the intrinsic's signature
9717 Ops.push_back(StN->getValue());
9719 // Loads (and of course intrinsics) match the intrinsics' signature,
9720 // so just add all but the alignment operand.
9721 for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands() - 1; ++i)
9722 Ops.push_back(N->getOperand(i));
9725 // For all node types, the alignment operand is always the last one.
9726 Ops.push_back(DAG.getConstant(Alignment, dl, MVT::i32));
9728 // If this is a non-standard-aligned STORE, the penultimate operand is the
9729 // stored value. Bitcast it to the aligned type.
9730 if (AlignedVecTy != VecTy && N->getOpcode() == ISD::STORE) {
9731 SDValue &StVal = Ops[Ops.size()-2];
9732 StVal = DAG.getNode(ISD::BITCAST, dl, AlignedVecTy, StVal);
9735 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, dl, SDTys,
9737 MemN->getMemOperand());
9740 SmallVector<SDValue, 5> NewResults;
9741 for (unsigned i = 0; i < NumResultVecs; ++i)
9742 NewResults.push_back(SDValue(UpdN.getNode(), i));
9744 // If this is an non-standard-aligned LOAD, the first result is the loaded
9745 // value. Bitcast it to the expected result type.
9746 if (AlignedVecTy != VecTy && N->getOpcode() == ISD::LOAD) {
9747 SDValue &LdVal = NewResults[0];
9748 LdVal = DAG.getNode(ISD::BITCAST, dl, VecTy, LdVal);
9751 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs+1)); // chain
9752 DCI.CombineTo(N, NewResults);
9753 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
9760 static SDValue PerformVLDCombine(SDNode *N,
9761 TargetLowering::DAGCombinerInfo &DCI) {
9762 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
9765 return CombineBaseUpdate(N, DCI);
9768 /// CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a
9769 /// vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic
9770 /// are also VDUPLANEs. If so, combine them to a vldN-dup operation and
9772 static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
9773 SelectionDAG &DAG = DCI.DAG;
9774 EVT VT = N->getValueType(0);
9775 // vldN-dup instructions only support 64-bit vectors for N > 1.
9776 if (!VT.is64BitVector())
9779 // Check if the VDUPLANE operand is a vldN-dup intrinsic.
9780 SDNode *VLD = N->getOperand(0).getNode();
9781 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN)
9783 unsigned NumVecs = 0;
9784 unsigned NewOpc = 0;
9785 unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue();
9786 if (IntNo == Intrinsic::arm_neon_vld2lane) {
9788 NewOpc = ARMISD::VLD2DUP;
9789 } else if (IntNo == Intrinsic::arm_neon_vld3lane) {
9791 NewOpc = ARMISD::VLD3DUP;
9792 } else if (IntNo == Intrinsic::arm_neon_vld4lane) {
9794 NewOpc = ARMISD::VLD4DUP;
9799 // First check that all the vldN-lane uses are VDUPLANEs and that the lane
9800 // numbers match the load.
9801 unsigned VLDLaneNo =
9802 cast<ConstantSDNode>(VLD->getOperand(NumVecs+3))->getZExtValue();
9803 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
9805 // Ignore uses of the chain result.
9806 if (UI.getUse().getResNo() == NumVecs)
9809 if (User->getOpcode() != ARMISD::VDUPLANE ||
9810 VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue())
9814 // Create the vldN-dup node.
9817 for (n = 0; n < NumVecs; ++n)
9819 Tys[n] = MVT::Other;
9820 SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumVecs+1));
9821 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) };
9822 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD);
9823 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, SDLoc(VLD), SDTys,
9824 Ops, VLDMemInt->getMemoryVT(),
9825 VLDMemInt->getMemOperand());
9828 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
9830 unsigned ResNo = UI.getUse().getResNo();
9831 // Ignore uses of the chain result.
9832 if (ResNo == NumVecs)
9835 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo));
9838 // Now the vldN-lane intrinsic is dead except for its chain result.
9839 // Update uses of the chain.
9840 std::vector<SDValue> VLDDupResults;
9841 for (unsigned n = 0; n < NumVecs; ++n)
9842 VLDDupResults.push_back(SDValue(VLDDup.getNode(), n));
9843 VLDDupResults.push_back(SDValue(VLDDup.getNode(), NumVecs));
9844 DCI.CombineTo(VLD, VLDDupResults);
9849 /// PerformVDUPLANECombine - Target-specific dag combine xforms for
9850 /// ARMISD::VDUPLANE.
9851 static SDValue PerformVDUPLANECombine(SDNode *N,
9852 TargetLowering::DAGCombinerInfo &DCI) {
9853 SDValue Op = N->getOperand(0);
9855 // If the source is a vldN-lane (N > 1) intrinsic, and all the other uses
9856 // of that intrinsic are also VDUPLANEs, combine them to a vldN-dup operation.
9857 if (CombineVLDDUP(N, DCI))
9858 return SDValue(N, 0);
9860 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
9861 // redundant. Ignore bit_converts for now; element sizes are checked below.
9862 while (Op.getOpcode() == ISD::BITCAST)
9863 Op = Op.getOperand(0);
9864 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
9867 // Make sure the VMOV element size is not bigger than the VDUPLANE elements.
9868 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits();
9869 // The canonical VMOV for a zero vector uses a 32-bit element size.
9870 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9872 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
9874 EVT VT = N->getValueType(0);
9875 if (EltSize > VT.getVectorElementType().getSizeInBits())
9878 return DCI.DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
9881 static SDValue PerformLOADCombine(SDNode *N,
9882 TargetLowering::DAGCombinerInfo &DCI) {
9883 EVT VT = N->getValueType(0);
9885 // If this is a legal vector load, try to combine it into a VLD1_UPD.
9886 if (ISD::isNormalLoad(N) && VT.isVector() &&
9887 DCI.DAG.getTargetLoweringInfo().isTypeLegal(VT))
9888 return CombineBaseUpdate(N, DCI);
9893 /// PerformSTORECombine - Target-specific dag combine xforms for
9895 static SDValue PerformSTORECombine(SDNode *N,
9896 TargetLowering::DAGCombinerInfo &DCI) {
9897 StoreSDNode *St = cast<StoreSDNode>(N);
9898 if (St->isVolatile())
9901 // Optimize trunc store (of multiple scalars) to shuffle and store. First,
9902 // pack all of the elements in one place. Next, store to memory in fewer
9904 SDValue StVal = St->getValue();
9905 EVT VT = StVal.getValueType();
9906 if (St->isTruncatingStore() && VT.isVector()) {
9907 SelectionDAG &DAG = DCI.DAG;
9908 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9909 EVT StVT = St->getMemoryVT();
9910 unsigned NumElems = VT.getVectorNumElements();
9911 assert(StVT != VT && "Cannot truncate to the same type");
9912 unsigned FromEltSz = VT.getVectorElementType().getSizeInBits();
9913 unsigned ToEltSz = StVT.getVectorElementType().getSizeInBits();
9915 // From, To sizes and ElemCount must be pow of two
9916 if (!isPowerOf2_32(NumElems * FromEltSz * ToEltSz)) return SDValue();
9918 // We are going to use the original vector elt for storing.
9919 // Accumulated smaller vector elements must be a multiple of the store size.
9920 if (0 != (NumElems * FromEltSz) % ToEltSz) return SDValue();
9922 unsigned SizeRatio = FromEltSz / ToEltSz;
9923 assert(SizeRatio * NumElems * ToEltSz == VT.getSizeInBits());
9925 // Create a type on which we perform the shuffle.
9926 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), StVT.getScalarType(),
9927 NumElems*SizeRatio);
9928 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
9931 SDValue WideVec = DAG.getNode(ISD::BITCAST, DL, WideVecVT, StVal);
9932 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
9933 for (unsigned i = 0; i < NumElems; ++i)
9934 ShuffleVec[i] = DAG.getDataLayout().isBigEndian()
9935 ? (i + 1) * SizeRatio - 1
9938 // Can't shuffle using an illegal type.
9939 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
9941 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, DL, WideVec,
9942 DAG.getUNDEF(WideVec.getValueType()),
9944 // At this point all of the data is stored at the bottom of the
9945 // register. We now need to save it to mem.
9947 // Find the largest store unit
9948 MVT StoreType = MVT::i8;
9949 for (MVT Tp : MVT::integer_valuetypes()) {
9950 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToEltSz)
9953 // Didn't find a legal store type.
9954 if (!TLI.isTypeLegal(StoreType))
9957 // Bitcast the original vector into a vector of store-size units
9958 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
9959 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
9960 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
9961 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, DL, StoreVecVT, Shuff);
9962 SmallVector<SDValue, 8> Chains;
9963 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits() / 8, DL,
9964 TLI.getPointerTy(DAG.getDataLayout()));
9965 SDValue BasePtr = St->getBasePtr();
9967 // Perform one or more big stores into memory.
9968 unsigned E = (ToEltSz*NumElems)/StoreType.getSizeInBits();
9969 for (unsigned I = 0; I < E; I++) {
9970 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
9971 StoreType, ShuffWide,
9972 DAG.getIntPtrConstant(I, DL));
9973 SDValue Ch = DAG.getStore(St->getChain(), DL, SubVec, BasePtr,
9974 St->getPointerInfo(), St->isVolatile(),
9975 St->isNonTemporal(), St->getAlignment());
9976 BasePtr = DAG.getNode(ISD::ADD, DL, BasePtr.getValueType(), BasePtr,
9978 Chains.push_back(Ch);
9980 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
9983 if (!ISD::isNormalStore(St))
9986 // Split a store of a VMOVDRR into two integer stores to avoid mixing NEON and
9987 // ARM stores of arguments in the same cache line.
9988 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR &&
9989 StVal.getNode()->hasOneUse()) {
9990 SelectionDAG &DAG = DCI.DAG;
9991 bool isBigEndian = DAG.getDataLayout().isBigEndian();
9993 SDValue BasePtr = St->getBasePtr();
9994 SDValue NewST1 = DAG.getStore(St->getChain(), DL,
9995 StVal.getNode()->getOperand(isBigEndian ? 1 : 0 ),
9996 BasePtr, St->getPointerInfo(), St->isVolatile(),
9997 St->isNonTemporal(), St->getAlignment());
9999 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
10000 DAG.getConstant(4, DL, MVT::i32));
10001 return DAG.getStore(NewST1.getValue(0), DL,
10002 StVal.getNode()->getOperand(isBigEndian ? 0 : 1),
10003 OffsetPtr, St->getPointerInfo(), St->isVolatile(),
10004 St->isNonTemporal(),
10005 std::min(4U, St->getAlignment() / 2));
10008 if (StVal.getValueType() == MVT::i64 &&
10009 StVal.getNode()->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
10011 // Bitcast an i64 store extracted from a vector to f64.
10012 // Otherwise, the i64 value will be legalized to a pair of i32 values.
10013 SelectionDAG &DAG = DCI.DAG;
10015 SDValue IntVec = StVal.getOperand(0);
10016 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
10017 IntVec.getValueType().getVectorNumElements());
10018 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec);
10019 SDValue ExtElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
10020 Vec, StVal.getOperand(1));
10022 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt);
10023 // Make the DAGCombiner fold the bitcasts.
10024 DCI.AddToWorklist(Vec.getNode());
10025 DCI.AddToWorklist(ExtElt.getNode());
10026 DCI.AddToWorklist(V.getNode());
10027 return DAG.getStore(St->getChain(), dl, V, St->getBasePtr(),
10028 St->getPointerInfo(), St->isVolatile(),
10029 St->isNonTemporal(), St->getAlignment(),
10033 // If this is a legal vector store, try to combine it into a VST1_UPD.
10034 if (ISD::isNormalStore(N) && VT.isVector() &&
10035 DCI.DAG.getTargetLoweringInfo().isTypeLegal(VT))
10036 return CombineBaseUpdate(N, DCI);
10041 /// PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD)
10042 /// can replace combinations of VMUL and VCVT (floating-point to integer)
10043 /// when the VMUL has a constant operand that is a power of 2.
10045 /// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
10046 /// vmul.f32 d16, d17, d16
10047 /// vcvt.s32.f32 d16, d16
10049 /// vcvt.s32.f32 d16, d16, #3
10050 static SDValue PerformVCVTCombine(SDNode *N, SelectionDAG &DAG,
10051 const ARMSubtarget *Subtarget) {
10052 if (!Subtarget->hasNEON())
10055 SDValue Op = N->getOperand(0);
10056 if (!Op.getValueType().isVector() || Op.getOpcode() != ISD::FMUL)
10059 SDValue ConstVec = Op->getOperand(1);
10060 if (!isa<BuildVectorSDNode>(ConstVec))
10063 MVT FloatTy = Op.getSimpleValueType().getVectorElementType();
10064 uint32_t FloatBits = FloatTy.getSizeInBits();
10065 MVT IntTy = N->getSimpleValueType(0).getVectorElementType();
10066 uint32_t IntBits = IntTy.getSizeInBits();
10067 unsigned NumLanes = Op.getValueType().getVectorNumElements();
10068 if (FloatBits != 32 || IntBits > 32 || NumLanes > 4) {
10069 // These instructions only exist converting from f32 to i32. We can handle
10070 // smaller integers by generating an extra truncate, but larger ones would
10071 // be lossy. We also can't handle more then 4 lanes, since these intructions
10072 // only support v2i32/v4i32 types.
10076 BitVector UndefElements;
10077 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(ConstVec);
10078 int32_t C = BV->getConstantFPSplatPow2ToLog2Int(&UndefElements, 33);
10079 if (C == -1 || C == 0 || C > 32)
10083 bool isSigned = N->getOpcode() == ISD::FP_TO_SINT;
10084 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfp2fxs :
10085 Intrinsic::arm_neon_vcvtfp2fxu;
10086 SDValue FixConv = DAG.getNode(
10087 ISD::INTRINSIC_WO_CHAIN, dl, NumLanes == 2 ? MVT::v2i32 : MVT::v4i32,
10088 DAG.getConstant(IntrinsicOpcode, dl, MVT::i32), Op->getOperand(0),
10089 DAG.getConstant(C, dl, MVT::i32));
10091 if (IntBits < FloatBits)
10092 FixConv = DAG.getNode(ISD::TRUNCATE, dl, N->getValueType(0), FixConv);
10097 /// PerformVDIVCombine - VCVT (fixed-point to floating-point, Advanced SIMD)
10098 /// can replace combinations of VCVT (integer to floating-point) and VDIV
10099 /// when the VDIV has a constant operand that is a power of 2.
10101 /// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
10102 /// vcvt.f32.s32 d16, d16
10103 /// vdiv.f32 d16, d17, d16
10105 /// vcvt.f32.s32 d16, d16, #3
10106 static SDValue PerformVDIVCombine(SDNode *N, SelectionDAG &DAG,
10107 const ARMSubtarget *Subtarget) {
10108 if (!Subtarget->hasNEON())
10111 SDValue Op = N->getOperand(0);
10112 unsigned OpOpcode = Op.getNode()->getOpcode();
10113 if (!N->getValueType(0).isVector() ||
10114 (OpOpcode != ISD::SINT_TO_FP && OpOpcode != ISD::UINT_TO_FP))
10117 SDValue ConstVec = N->getOperand(1);
10118 if (!isa<BuildVectorSDNode>(ConstVec))
10121 MVT FloatTy = N->getSimpleValueType(0).getVectorElementType();
10122 uint32_t FloatBits = FloatTy.getSizeInBits();
10123 MVT IntTy = Op.getOperand(0).getSimpleValueType().getVectorElementType();
10124 uint32_t IntBits = IntTy.getSizeInBits();
10125 unsigned NumLanes = Op.getValueType().getVectorNumElements();
10126 if (FloatBits != 32 || IntBits > 32 || NumLanes > 4) {
10127 // These instructions only exist converting from i32 to f32. We can handle
10128 // smaller integers by generating an extra extend, but larger ones would
10129 // be lossy. We also can't handle more then 4 lanes, since these intructions
10130 // only support v2i32/v4i32 types.
10134 BitVector UndefElements;
10135 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(ConstVec);
10136 int32_t C = BV->getConstantFPSplatPow2ToLog2Int(&UndefElements, 33);
10137 if (C == -1 || C == 0 || C > 32)
10141 bool isSigned = OpOpcode == ISD::SINT_TO_FP;
10142 SDValue ConvInput = Op.getOperand(0);
10143 if (IntBits < FloatBits)
10144 ConvInput = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
10145 dl, NumLanes == 2 ? MVT::v2i32 : MVT::v4i32,
10148 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfxs2fp :
10149 Intrinsic::arm_neon_vcvtfxu2fp;
10150 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl,
10152 DAG.getConstant(IntrinsicOpcode, dl, MVT::i32),
10153 ConvInput, DAG.getConstant(C, dl, MVT::i32));
10156 /// Getvshiftimm - Check if this is a valid build_vector for the immediate
10157 /// operand of a vector shift operation, where all the elements of the
10158 /// build_vector must have the same constant integer value.
10159 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
10160 // Ignore bit_converts.
10161 while (Op.getOpcode() == ISD::BITCAST)
10162 Op = Op.getOperand(0);
10163 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
10164 APInt SplatBits, SplatUndef;
10165 unsigned SplatBitSize;
10167 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
10168 HasAnyUndefs, ElementBits) ||
10169 SplatBitSize > ElementBits)
10171 Cnt = SplatBits.getSExtValue();
10175 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
10176 /// operand of a vector shift left operation. That value must be in the range:
10177 /// 0 <= Value < ElementBits for a left shift; or
10178 /// 0 <= Value <= ElementBits for a long left shift.
10179 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
10180 assert(VT.isVector() && "vector shift count is not a vector type");
10181 int64_t ElementBits = VT.getVectorElementType().getSizeInBits();
10182 if (! getVShiftImm(Op, ElementBits, Cnt))
10184 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
10187 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
10188 /// operand of a vector shift right operation. For a shift opcode, the value
10189 /// is positive, but for an intrinsic the value count must be negative. The
10190 /// absolute value must be in the range:
10191 /// 1 <= |Value| <= ElementBits for a right shift; or
10192 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
10193 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
10195 assert(VT.isVector() && "vector shift count is not a vector type");
10196 int64_t ElementBits = VT.getVectorElementType().getSizeInBits();
10197 if (! getVShiftImm(Op, ElementBits, Cnt))
10200 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
10201 if (Cnt >= -(isNarrow ? ElementBits/2 : ElementBits) && Cnt <= -1) {
10208 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
10209 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
10210 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
10213 // Don't do anything for most intrinsics.
10216 // Vector shifts: check for immediate versions and lower them.
10217 // Note: This is done during DAG combining instead of DAG legalizing because
10218 // the build_vectors for 64-bit vector element shift counts are generally
10219 // not legal, and it is hard to see their values after they get legalized to
10220 // loads from a constant pool.
10221 case Intrinsic::arm_neon_vshifts:
10222 case Intrinsic::arm_neon_vshiftu:
10223 case Intrinsic::arm_neon_vrshifts:
10224 case Intrinsic::arm_neon_vrshiftu:
10225 case Intrinsic::arm_neon_vrshiftn:
10226 case Intrinsic::arm_neon_vqshifts:
10227 case Intrinsic::arm_neon_vqshiftu:
10228 case Intrinsic::arm_neon_vqshiftsu:
10229 case Intrinsic::arm_neon_vqshiftns:
10230 case Intrinsic::arm_neon_vqshiftnu:
10231 case Intrinsic::arm_neon_vqshiftnsu:
10232 case Intrinsic::arm_neon_vqrshiftns:
10233 case Intrinsic::arm_neon_vqrshiftnu:
10234 case Intrinsic::arm_neon_vqrshiftnsu: {
10235 EVT VT = N->getOperand(1).getValueType();
10237 unsigned VShiftOpc = 0;
10240 case Intrinsic::arm_neon_vshifts:
10241 case Intrinsic::arm_neon_vshiftu:
10242 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
10243 VShiftOpc = ARMISD::VSHL;
10246 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
10247 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
10248 ARMISD::VSHRs : ARMISD::VSHRu);
10253 case Intrinsic::arm_neon_vrshifts:
10254 case Intrinsic::arm_neon_vrshiftu:
10255 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
10259 case Intrinsic::arm_neon_vqshifts:
10260 case Intrinsic::arm_neon_vqshiftu:
10261 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
10265 case Intrinsic::arm_neon_vqshiftsu:
10266 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
10268 llvm_unreachable("invalid shift count for vqshlu intrinsic");
10270 case Intrinsic::arm_neon_vrshiftn:
10271 case Intrinsic::arm_neon_vqshiftns:
10272 case Intrinsic::arm_neon_vqshiftnu:
10273 case Intrinsic::arm_neon_vqshiftnsu:
10274 case Intrinsic::arm_neon_vqrshiftns:
10275 case Intrinsic::arm_neon_vqrshiftnu:
10276 case Intrinsic::arm_neon_vqrshiftnsu:
10277 // Narrowing shifts require an immediate right shift.
10278 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
10280 llvm_unreachable("invalid shift count for narrowing vector shift "
10284 llvm_unreachable("unhandled vector shift");
10288 case Intrinsic::arm_neon_vshifts:
10289 case Intrinsic::arm_neon_vshiftu:
10290 // Opcode already set above.
10292 case Intrinsic::arm_neon_vrshifts:
10293 VShiftOpc = ARMISD::VRSHRs; break;
10294 case Intrinsic::arm_neon_vrshiftu:
10295 VShiftOpc = ARMISD::VRSHRu; break;
10296 case Intrinsic::arm_neon_vrshiftn:
10297 VShiftOpc = ARMISD::VRSHRN; break;
10298 case Intrinsic::arm_neon_vqshifts:
10299 VShiftOpc = ARMISD::VQSHLs; break;
10300 case Intrinsic::arm_neon_vqshiftu:
10301 VShiftOpc = ARMISD::VQSHLu; break;
10302 case Intrinsic::arm_neon_vqshiftsu:
10303 VShiftOpc = ARMISD::VQSHLsu; break;
10304 case Intrinsic::arm_neon_vqshiftns:
10305 VShiftOpc = ARMISD::VQSHRNs; break;
10306 case Intrinsic::arm_neon_vqshiftnu:
10307 VShiftOpc = ARMISD::VQSHRNu; break;
10308 case Intrinsic::arm_neon_vqshiftnsu:
10309 VShiftOpc = ARMISD::VQSHRNsu; break;
10310 case Intrinsic::arm_neon_vqrshiftns:
10311 VShiftOpc = ARMISD::VQRSHRNs; break;
10312 case Intrinsic::arm_neon_vqrshiftnu:
10313 VShiftOpc = ARMISD::VQRSHRNu; break;
10314 case Intrinsic::arm_neon_vqrshiftnsu:
10315 VShiftOpc = ARMISD::VQRSHRNsu; break;
10319 return DAG.getNode(VShiftOpc, dl, N->getValueType(0),
10320 N->getOperand(1), DAG.getConstant(Cnt, dl, MVT::i32));
10323 case Intrinsic::arm_neon_vshiftins: {
10324 EVT VT = N->getOperand(1).getValueType();
10326 unsigned VShiftOpc = 0;
10328 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
10329 VShiftOpc = ARMISD::VSLI;
10330 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
10331 VShiftOpc = ARMISD::VSRI;
10333 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
10337 return DAG.getNode(VShiftOpc, dl, N->getValueType(0),
10338 N->getOperand(1), N->getOperand(2),
10339 DAG.getConstant(Cnt, dl, MVT::i32));
10342 case Intrinsic::arm_neon_vqrshifts:
10343 case Intrinsic::arm_neon_vqrshiftu:
10344 // No immediate versions of these to check for.
10351 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
10352 /// lowers them. As with the vector shift intrinsics, this is done during DAG
10353 /// combining instead of DAG legalizing because the build_vectors for 64-bit
10354 /// vector element shift counts are generally not legal, and it is hard to see
10355 /// their values after they get legalized to loads from a constant pool.
10356 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
10357 const ARMSubtarget *ST) {
10358 EVT VT = N->getValueType(0);
10359 if (N->getOpcode() == ISD::SRL && VT == MVT::i32 && ST->hasV6Ops()) {
10360 // Canonicalize (srl (bswap x), 16) to (rotr (bswap x), 16) if the high
10361 // 16-bits of x is zero. This optimizes rev + lsr 16 to rev16.
10362 SDValue N1 = N->getOperand(1);
10363 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
10364 SDValue N0 = N->getOperand(0);
10365 if (C->getZExtValue() == 16 && N0.getOpcode() == ISD::BSWAP &&
10366 DAG.MaskedValueIsZero(N0.getOperand(0),
10367 APInt::getHighBitsSet(32, 16)))
10368 return DAG.getNode(ISD::ROTR, SDLoc(N), VT, N0, N1);
10372 // Nothing to be done for scalar shifts.
10373 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10374 if (!VT.isVector() || !TLI.isTypeLegal(VT))
10377 assert(ST->hasNEON() && "unexpected vector shift");
10380 switch (N->getOpcode()) {
10381 default: llvm_unreachable("unexpected shift opcode");
10384 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt)) {
10386 return DAG.getNode(ARMISD::VSHL, dl, VT, N->getOperand(0),
10387 DAG.getConstant(Cnt, dl, MVT::i32));
10393 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
10394 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
10395 ARMISD::VSHRs : ARMISD::VSHRu);
10397 return DAG.getNode(VShiftOpc, dl, VT, N->getOperand(0),
10398 DAG.getConstant(Cnt, dl, MVT::i32));
10404 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
10405 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
10406 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
10407 const ARMSubtarget *ST) {
10408 SDValue N0 = N->getOperand(0);
10410 // Check for sign- and zero-extensions of vector extract operations of 8-
10411 // and 16-bit vector elements. NEON supports these directly. They are
10412 // handled during DAG combining because type legalization will promote them
10413 // to 32-bit types and it is messy to recognize the operations after that.
10414 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
10415 SDValue Vec = N0.getOperand(0);
10416 SDValue Lane = N0.getOperand(1);
10417 EVT VT = N->getValueType(0);
10418 EVT EltVT = N0.getValueType();
10419 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10421 if (VT == MVT::i32 &&
10422 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
10423 TLI.isTypeLegal(Vec.getValueType()) &&
10424 isa<ConstantSDNode>(Lane)) {
10427 switch (N->getOpcode()) {
10428 default: llvm_unreachable("unexpected opcode");
10429 case ISD::SIGN_EXTEND:
10430 Opc = ARMISD::VGETLANEs;
10432 case ISD::ZERO_EXTEND:
10433 case ISD::ANY_EXTEND:
10434 Opc = ARMISD::VGETLANEu;
10437 return DAG.getNode(Opc, SDLoc(N), VT, Vec, Lane);
10444 static void computeKnownBits(SelectionDAG &DAG, SDValue Op, APInt &KnownZero,
10446 if (Op.getOpcode() == ARMISD::BFI) {
10447 // Conservatively, we can recurse down the first operand
10448 // and just mask out all affected bits.
10449 computeKnownBits(DAG, Op.getOperand(0), KnownZero, KnownOne);
10451 // The operand to BFI is already a mask suitable for removing the bits it
10453 ConstantSDNode *CI = cast<ConstantSDNode>(Op.getOperand(2));
10454 APInt Mask = CI->getAPIntValue();
10459 if (Op.getOpcode() == ARMISD::CMOV) {
10460 APInt KZ2(KnownZero.getBitWidth(), 0);
10461 APInt KO2(KnownOne.getBitWidth(), 0);
10462 computeKnownBits(DAG, Op.getOperand(1), KnownZero, KnownOne);
10463 computeKnownBits(DAG, Op.getOperand(2), KZ2, KO2);
10469 return DAG.computeKnownBits(Op, KnownZero, KnownOne);
10472 SDValue ARMTargetLowering::PerformCMOVToBFICombine(SDNode *CMOV, SelectionDAG &DAG) const {
10473 // If we have a CMOV, OR and AND combination such as:
10478 // * CN is a single bit;
10479 // * All bits covered by CM are known zero in y
10481 // Then we can convert this into a sequence of BFI instructions. This will
10482 // always be a win if CM is a single bit, will always be no worse than the
10483 // TST&OR sequence if CM is two bits, and for thumb will be no worse if CM is
10484 // three bits (due to the extra IT instruction).
10486 SDValue Op0 = CMOV->getOperand(0);
10487 SDValue Op1 = CMOV->getOperand(1);
10488 auto CCNode = cast<ConstantSDNode>(CMOV->getOperand(2));
10489 auto CC = CCNode->getAPIntValue().getLimitedValue();
10490 SDValue CmpZ = CMOV->getOperand(4);
10492 // The compare must be against zero.
10493 if (!isNullConstant(CmpZ->getOperand(1)))
10496 assert(CmpZ->getOpcode() == ARMISD::CMPZ);
10497 SDValue And = CmpZ->getOperand(0);
10498 if (And->getOpcode() != ISD::AND)
10500 ConstantSDNode *AndC = dyn_cast<ConstantSDNode>(And->getOperand(1));
10501 if (!AndC || !AndC->getAPIntValue().isPowerOf2())
10503 SDValue X = And->getOperand(0);
10505 if (CC == ARMCC::EQ) {
10506 // We're performing an "equal to zero" compare. Swap the operands so we
10507 // canonicalize on a "not equal to zero" compare.
10508 std::swap(Op0, Op1);
10510 assert(CC == ARMCC::NE && "How can a CMPZ node not be EQ or NE?");
10513 if (Op1->getOpcode() != ISD::OR)
10516 ConstantSDNode *OrC = dyn_cast<ConstantSDNode>(Op1->getOperand(1));
10519 SDValue Y = Op1->getOperand(0);
10524 // Now, is it profitable to continue?
10525 APInt OrCI = OrC->getAPIntValue();
10526 unsigned Heuristic = Subtarget->isThumb() ? 3 : 2;
10527 if (OrCI.countPopulation() > Heuristic)
10530 // Lastly, can we determine that the bits defined by OrCI
10532 APInt KnownZero, KnownOne;
10533 computeKnownBits(DAG, Y, KnownZero, KnownOne);
10534 if ((OrCI & KnownZero) != OrCI)
10537 // OK, we can do the combine.
10540 EVT VT = X.getValueType();
10541 unsigned BitInX = AndC->getAPIntValue().logBase2();
10544 // We must shift X first.
10545 X = DAG.getNode(ISD::SRL, dl, VT, X,
10546 DAG.getConstant(BitInX, dl, VT));
10549 for (unsigned BitInY = 0, NumActiveBits = OrCI.getActiveBits();
10550 BitInY < NumActiveBits; ++BitInY) {
10551 if (OrCI[BitInY] == 0)
10553 APInt Mask(VT.getSizeInBits(), 0);
10554 Mask.setBit(BitInY);
10555 V = DAG.getNode(ARMISD::BFI, dl, VT, V, X,
10556 // Confusingly, the operand is an *inverted* mask.
10557 DAG.getConstant(~Mask, dl, VT));
10563 /// PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV.
10565 ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const {
10566 SDValue Cmp = N->getOperand(4);
10567 if (Cmp.getOpcode() != ARMISD::CMPZ)
10568 // Only looking at EQ and NE cases.
10571 EVT VT = N->getValueType(0);
10573 SDValue LHS = Cmp.getOperand(0);
10574 SDValue RHS = Cmp.getOperand(1);
10575 SDValue FalseVal = N->getOperand(0);
10576 SDValue TrueVal = N->getOperand(1);
10577 SDValue ARMcc = N->getOperand(2);
10578 ARMCC::CondCodes CC =
10579 (ARMCC::CondCodes)cast<ConstantSDNode>(ARMcc)->getZExtValue();
10581 // BFI is only available on V6T2+.
10582 if (!Subtarget->isThumb1Only() && Subtarget->hasV6T2Ops()) {
10583 SDValue R = PerformCMOVToBFICombine(N, DAG);
10604 /// FIXME: Turn this into a target neutral optimization?
10606 if (CC == ARMCC::NE && FalseVal == RHS && FalseVal != LHS) {
10607 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, TrueVal, ARMcc,
10608 N->getOperand(3), Cmp);
10609 } else if (CC == ARMCC::EQ && TrueVal == RHS) {
10611 SDValue NewCmp = getARMCmp(LHS, RHS, ISD::SETNE, ARMcc, DAG, dl);
10612 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, FalseVal, ARMcc,
10613 N->getOperand(3), NewCmp);
10616 if (Res.getNode()) {
10617 APInt KnownZero, KnownOne;
10618 DAG.computeKnownBits(SDValue(N,0), KnownZero, KnownOne);
10619 // Capture demanded bits information that would be otherwise lost.
10620 if (KnownZero == 0xfffffffe)
10621 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
10622 DAG.getValueType(MVT::i1));
10623 else if (KnownZero == 0xffffff00)
10624 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
10625 DAG.getValueType(MVT::i8));
10626 else if (KnownZero == 0xffff0000)
10627 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
10628 DAG.getValueType(MVT::i16));
10634 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
10635 DAGCombinerInfo &DCI) const {
10636 switch (N->getOpcode()) {
10638 case ISD::ADDC: return PerformADDCCombine(N, DCI, Subtarget);
10639 case ISD::ADD: return PerformADDCombine(N, DCI, Subtarget);
10640 case ISD::SUB: return PerformSUBCombine(N, DCI);
10641 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
10642 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
10643 case ISD::XOR: return PerformXORCombine(N, DCI, Subtarget);
10644 case ISD::AND: return PerformANDCombine(N, DCI, Subtarget);
10645 case ARMISD::BFI: return PerformBFICombine(N, DCI);
10646 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI, Subtarget);
10647 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
10648 case ISD::STORE: return PerformSTORECombine(N, DCI);
10649 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI, Subtarget);
10650 case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI);
10651 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
10652 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
10653 case ISD::FP_TO_SINT:
10654 case ISD::FP_TO_UINT:
10655 return PerformVCVTCombine(N, DCI.DAG, Subtarget);
10657 return PerformVDIVCombine(N, DCI.DAG, Subtarget);
10658 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
10661 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
10662 case ISD::SIGN_EXTEND:
10663 case ISD::ZERO_EXTEND:
10664 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
10665 case ARMISD::CMOV: return PerformCMOVCombine(N, DCI.DAG);
10666 case ISD::LOAD: return PerformLOADCombine(N, DCI);
10667 case ARMISD::VLD2DUP:
10668 case ARMISD::VLD3DUP:
10669 case ARMISD::VLD4DUP:
10670 return PerformVLDCombine(N, DCI);
10671 case ARMISD::BUILD_VECTOR:
10672 return PerformARMBUILD_VECTORCombine(N, DCI);
10673 case ISD::INTRINSIC_VOID:
10674 case ISD::INTRINSIC_W_CHAIN:
10675 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
10676 case Intrinsic::arm_neon_vld1:
10677 case Intrinsic::arm_neon_vld2:
10678 case Intrinsic::arm_neon_vld3:
10679 case Intrinsic::arm_neon_vld4:
10680 case Intrinsic::arm_neon_vld2lane:
10681 case Intrinsic::arm_neon_vld3lane:
10682 case Intrinsic::arm_neon_vld4lane:
10683 case Intrinsic::arm_neon_vst1:
10684 case Intrinsic::arm_neon_vst2:
10685 case Intrinsic::arm_neon_vst3:
10686 case Intrinsic::arm_neon_vst4:
10687 case Intrinsic::arm_neon_vst2lane:
10688 case Intrinsic::arm_neon_vst3lane:
10689 case Intrinsic::arm_neon_vst4lane:
10690 return PerformVLDCombine(N, DCI);
10698 bool ARMTargetLowering::isDesirableToTransformToIntegerOp(unsigned Opc,
10700 return (VT == MVT::f32) && (Opc == ISD::LOAD || Opc == ISD::STORE);
10703 bool ARMTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
10706 bool *Fast) const {
10707 // The AllowsUnaliged flag models the SCTLR.A setting in ARM cpus
10708 bool AllowsUnaligned = Subtarget->allowsUnalignedMem();
10710 switch (VT.getSimpleVT().SimpleTy) {
10716 // Unaligned access can use (for example) LRDB, LRDH, LDR
10717 if (AllowsUnaligned) {
10719 *Fast = Subtarget->hasV7Ops();
10726 // For any little-endian targets with neon, we can support unaligned ld/st
10727 // of D and Q (e.g. {D0,D1}) registers by using vld1.i8/vst1.i8.
10728 // A big-endian target may also explicitly support unaligned accesses
10729 if (Subtarget->hasNEON() && (AllowsUnaligned || Subtarget->isLittle())) {
10739 static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign,
10740 unsigned AlignCheck) {
10741 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) &&
10742 (DstAlign == 0 || DstAlign % AlignCheck == 0));
10745 EVT ARMTargetLowering::getOptimalMemOpType(uint64_t Size,
10746 unsigned DstAlign, unsigned SrcAlign,
10747 bool IsMemset, bool ZeroMemset,
10749 MachineFunction &MF) const {
10750 const Function *F = MF.getFunction();
10752 // See if we can use NEON instructions for this...
10753 if ((!IsMemset || ZeroMemset) && Subtarget->hasNEON() &&
10754 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
10757 (memOpAlign(SrcAlign, DstAlign, 16) ||
10758 (allowsMisalignedMemoryAccesses(MVT::v2f64, 0, 1, &Fast) && Fast))) {
10760 } else if (Size >= 8 &&
10761 (memOpAlign(SrcAlign, DstAlign, 8) ||
10762 (allowsMisalignedMemoryAccesses(MVT::f64, 0, 1, &Fast) &&
10768 // Lowering to i32/i16 if the size permits.
10771 else if (Size >= 2)
10774 // Let the target-independent logic figure it out.
10778 bool ARMTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
10779 if (Val.getOpcode() != ISD::LOAD)
10782 EVT VT1 = Val.getValueType();
10783 if (!VT1.isSimple() || !VT1.isInteger() ||
10784 !VT2.isSimple() || !VT2.isInteger())
10787 switch (VT1.getSimpleVT().SimpleTy) {
10792 // 8-bit and 16-bit loads implicitly zero-extend to 32-bits.
10799 bool ARMTargetLowering::isVectorLoadExtDesirable(SDValue ExtVal) const {
10800 EVT VT = ExtVal.getValueType();
10802 if (!isTypeLegal(VT))
10805 // Don't create a loadext if we can fold the extension into a wide/long
10807 // If there's more than one user instruction, the loadext is desirable no
10808 // matter what. There can be two uses by the same instruction.
10809 if (ExtVal->use_empty() ||
10810 !ExtVal->use_begin()->isOnlyUserOf(ExtVal.getNode()))
10813 SDNode *U = *ExtVal->use_begin();
10814 if ((U->getOpcode() == ISD::ADD || U->getOpcode() == ISD::SUB ||
10815 U->getOpcode() == ISD::SHL || U->getOpcode() == ARMISD::VSHL))
10821 bool ARMTargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
10822 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
10825 if (!isTypeLegal(EVT::getEVT(Ty1)))
10828 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
10830 // Assuming the caller doesn't have a zeroext or signext return parameter,
10831 // truncation all the way down to i1 is valid.
10836 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
10840 unsigned Scale = 1;
10841 switch (VT.getSimpleVT().SimpleTy) {
10842 default: return false;
10857 if ((V & (Scale - 1)) != 0)
10860 return V == (V & ((1LL << 5) - 1));
10863 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
10864 const ARMSubtarget *Subtarget) {
10865 bool isNeg = false;
10871 switch (VT.getSimpleVT().SimpleTy) {
10872 default: return false;
10877 // + imm12 or - imm8
10879 return V == (V & ((1LL << 8) - 1));
10880 return V == (V & ((1LL << 12) - 1));
10883 // Same as ARM mode. FIXME: NEON?
10884 if (!Subtarget->hasVFP2())
10889 return V == (V & ((1LL << 8) - 1));
10893 /// isLegalAddressImmediate - Return true if the integer value can be used
10894 /// as the offset of the target addressing mode for load / store of the
10896 static bool isLegalAddressImmediate(int64_t V, EVT VT,
10897 const ARMSubtarget *Subtarget) {
10901 if (!VT.isSimple())
10904 if (Subtarget->isThumb1Only())
10905 return isLegalT1AddressImmediate(V, VT);
10906 else if (Subtarget->isThumb2())
10907 return isLegalT2AddressImmediate(V, VT, Subtarget);
10912 switch (VT.getSimpleVT().SimpleTy) {
10913 default: return false;
10918 return V == (V & ((1LL << 12) - 1));
10921 return V == (V & ((1LL << 8) - 1));
10924 if (!Subtarget->hasVFP2()) // FIXME: NEON?
10929 return V == (V & ((1LL << 8) - 1));
10933 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
10935 int Scale = AM.Scale;
10939 switch (VT.getSimpleVT().SimpleTy) {
10940 default: return false;
10948 Scale = Scale & ~1;
10949 return Scale == 2 || Scale == 4 || Scale == 8;
10952 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
10956 // Note, we allow "void" uses (basically, uses that aren't loads or
10957 // stores), because arm allows folding a scale into many arithmetic
10958 // operations. This should be made more precise and revisited later.
10960 // Allow r << imm, but the imm has to be a multiple of two.
10961 if (Scale & 1) return false;
10962 return isPowerOf2_32(Scale);
10966 /// isLegalAddressingMode - Return true if the addressing mode represented
10967 /// by AM is legal for this target, for a load/store of the specified type.
10968 bool ARMTargetLowering::isLegalAddressingMode(const DataLayout &DL,
10969 const AddrMode &AM, Type *Ty,
10970 unsigned AS) const {
10971 EVT VT = getValueType(DL, Ty, true);
10972 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
10975 // Can never fold addr of global into load/store.
10979 switch (AM.Scale) {
10980 case 0: // no scale reg, must be "r+i" or "r", or "i".
10983 if (Subtarget->isThumb1Only())
10987 // ARM doesn't support any R+R*scale+imm addr modes.
10991 if (!VT.isSimple())
10994 if (Subtarget->isThumb2())
10995 return isLegalT2ScaledAddressingMode(AM, VT);
10997 int Scale = AM.Scale;
10998 switch (VT.getSimpleVT().SimpleTy) {
10999 default: return false;
11003 if (Scale < 0) Scale = -Scale;
11007 return isPowerOf2_32(Scale & ~1);
11011 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
11016 // Note, we allow "void" uses (basically, uses that aren't loads or
11017 // stores), because arm allows folding a scale into many arithmetic
11018 // operations. This should be made more precise and revisited later.
11020 // Allow r << imm, but the imm has to be a multiple of two.
11021 if (Scale & 1) return false;
11022 return isPowerOf2_32(Scale);
11028 /// isLegalICmpImmediate - Return true if the specified immediate is legal
11029 /// icmp immediate, that is the target has icmp instructions which can compare
11030 /// a register against the immediate without having to materialize the
11031 /// immediate into a register.
11032 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
11033 // Thumb2 and ARM modes can use cmn for negative immediates.
11034 if (!Subtarget->isThumb())
11035 return ARM_AM::getSOImmVal(std::abs(Imm)) != -1;
11036 if (Subtarget->isThumb2())
11037 return ARM_AM::getT2SOImmVal(std::abs(Imm)) != -1;
11038 // Thumb1 doesn't have cmn, and only 8-bit immediates.
11039 return Imm >= 0 && Imm <= 255;
11042 /// isLegalAddImmediate - Return true if the specified immediate is a legal add
11043 /// *or sub* immediate, that is the target has add or sub instructions which can
11044 /// add a register with the immediate without having to materialize the
11045 /// immediate into a register.
11046 bool ARMTargetLowering::isLegalAddImmediate(int64_t Imm) const {
11047 // Same encoding for add/sub, just flip the sign.
11048 int64_t AbsImm = std::abs(Imm);
11049 if (!Subtarget->isThumb())
11050 return ARM_AM::getSOImmVal(AbsImm) != -1;
11051 if (Subtarget->isThumb2())
11052 return ARM_AM::getT2SOImmVal(AbsImm) != -1;
11053 // Thumb1 only has 8-bit unsigned immediate.
11054 return AbsImm >= 0 && AbsImm <= 255;
11057 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
11058 bool isSEXTLoad, SDValue &Base,
11059 SDValue &Offset, bool &isInc,
11060 SelectionDAG &DAG) {
11061 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
11064 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
11065 // AddressingMode 3
11066 Base = Ptr->getOperand(0);
11067 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
11068 int RHSC = (int)RHS->getZExtValue();
11069 if (RHSC < 0 && RHSC > -256) {
11070 assert(Ptr->getOpcode() == ISD::ADD);
11072 Offset = DAG.getConstant(-RHSC, SDLoc(Ptr), RHS->getValueType(0));
11076 isInc = (Ptr->getOpcode() == ISD::ADD);
11077 Offset = Ptr->getOperand(1);
11079 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
11080 // AddressingMode 2
11081 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
11082 int RHSC = (int)RHS->getZExtValue();
11083 if (RHSC < 0 && RHSC > -0x1000) {
11084 assert(Ptr->getOpcode() == ISD::ADD);
11086 Offset = DAG.getConstant(-RHSC, SDLoc(Ptr), RHS->getValueType(0));
11087 Base = Ptr->getOperand(0);
11092 if (Ptr->getOpcode() == ISD::ADD) {
11094 ARM_AM::ShiftOpc ShOpcVal=
11095 ARM_AM::getShiftOpcForNode(Ptr->getOperand(0).getOpcode());
11096 if (ShOpcVal != ARM_AM::no_shift) {
11097 Base = Ptr->getOperand(1);
11098 Offset = Ptr->getOperand(0);
11100 Base = Ptr->getOperand(0);
11101 Offset = Ptr->getOperand(1);
11106 isInc = (Ptr->getOpcode() == ISD::ADD);
11107 Base = Ptr->getOperand(0);
11108 Offset = Ptr->getOperand(1);
11112 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
11116 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
11117 bool isSEXTLoad, SDValue &Base,
11118 SDValue &Offset, bool &isInc,
11119 SelectionDAG &DAG) {
11120 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
11123 Base = Ptr->getOperand(0);
11124 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
11125 int RHSC = (int)RHS->getZExtValue();
11126 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
11127 assert(Ptr->getOpcode() == ISD::ADD);
11129 Offset = DAG.getConstant(-RHSC, SDLoc(Ptr), RHS->getValueType(0));
11131 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
11132 isInc = Ptr->getOpcode() == ISD::ADD;
11133 Offset = DAG.getConstant(RHSC, SDLoc(Ptr), RHS->getValueType(0));
11141 /// getPreIndexedAddressParts - returns true by value, base pointer and
11142 /// offset pointer and addressing mode by reference if the node's address
11143 /// can be legally represented as pre-indexed load / store address.
11145 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
11147 ISD::MemIndexedMode &AM,
11148 SelectionDAG &DAG) const {
11149 if (Subtarget->isThumb1Only())
11154 bool isSEXTLoad = false;
11155 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
11156 Ptr = LD->getBasePtr();
11157 VT = LD->getMemoryVT();
11158 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
11159 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
11160 Ptr = ST->getBasePtr();
11161 VT = ST->getMemoryVT();
11166 bool isLegal = false;
11167 if (Subtarget->isThumb2())
11168 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
11169 Offset, isInc, DAG);
11171 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
11172 Offset, isInc, DAG);
11176 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
11180 /// getPostIndexedAddressParts - returns true by value, base pointer and
11181 /// offset pointer and addressing mode by reference if this node can be
11182 /// combined with a load / store to form a post-indexed load / store.
11183 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
11186 ISD::MemIndexedMode &AM,
11187 SelectionDAG &DAG) const {
11188 if (Subtarget->isThumb1Only())
11193 bool isSEXTLoad = false;
11194 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
11195 VT = LD->getMemoryVT();
11196 Ptr = LD->getBasePtr();
11197 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
11198 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
11199 VT = ST->getMemoryVT();
11200 Ptr = ST->getBasePtr();
11205 bool isLegal = false;
11206 if (Subtarget->isThumb2())
11207 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
11210 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
11216 // Swap base ptr and offset to catch more post-index load / store when
11217 // it's legal. In Thumb2 mode, offset must be an immediate.
11218 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
11219 !Subtarget->isThumb2())
11220 std::swap(Base, Offset);
11222 // Post-indexed load / store update the base pointer.
11227 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
11231 void ARMTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
11234 const SelectionDAG &DAG,
11235 unsigned Depth) const {
11236 unsigned BitWidth = KnownOne.getBitWidth();
11237 KnownZero = KnownOne = APInt(BitWidth, 0);
11238 switch (Op.getOpcode()) {
11244 // These nodes' second result is a boolean
11245 if (Op.getResNo() == 0)
11247 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
11249 case ARMISD::CMOV: {
11250 // Bits are known zero/one if known on the LHS and RHS.
11251 DAG.computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1);
11252 if (KnownZero == 0 && KnownOne == 0) return;
11254 APInt KnownZeroRHS, KnownOneRHS;
11255 DAG.computeKnownBits(Op.getOperand(1), KnownZeroRHS, KnownOneRHS, Depth+1);
11256 KnownZero &= KnownZeroRHS;
11257 KnownOne &= KnownOneRHS;
11260 case ISD::INTRINSIC_W_CHAIN: {
11261 ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
11262 Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
11265 case Intrinsic::arm_ldaex:
11266 case Intrinsic::arm_ldrex: {
11267 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();
11268 unsigned MemBits = VT.getScalarType().getSizeInBits();
11269 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
11277 //===----------------------------------------------------------------------===//
11278 // ARM Inline Assembly Support
11279 //===----------------------------------------------------------------------===//
11281 bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const {
11282 // Looking for "rev" which is V6+.
11283 if (!Subtarget->hasV6Ops())
11286 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
11287 std::string AsmStr = IA->getAsmString();
11288 SmallVector<StringRef, 4> AsmPieces;
11289 SplitString(AsmStr, AsmPieces, ";\n");
11291 switch (AsmPieces.size()) {
11292 default: return false;
11294 AsmStr = AsmPieces[0];
11296 SplitString(AsmStr, AsmPieces, " \t,");
11299 if (AsmPieces.size() == 3 &&
11300 AsmPieces[0] == "rev" && AsmPieces[1] == "$0" && AsmPieces[2] == "$1" &&
11301 IA->getConstraintString().compare(0, 4, "=l,l") == 0) {
11302 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
11303 if (Ty && Ty->getBitWidth() == 32)
11304 return IntrinsicLowering::LowerToByteSwap(CI);
11312 /// getConstraintType - Given a constraint letter, return the type of
11313 /// constraint it is for this target.
11314 ARMTargetLowering::ConstraintType
11315 ARMTargetLowering::getConstraintType(StringRef Constraint) const {
11316 if (Constraint.size() == 1) {
11317 switch (Constraint[0]) {
11319 case 'l': return C_RegisterClass;
11320 case 'w': return C_RegisterClass;
11321 case 'h': return C_RegisterClass;
11322 case 'x': return C_RegisterClass;
11323 case 't': return C_RegisterClass;
11324 case 'j': return C_Other; // Constant for movw.
11325 // An address with a single base register. Due to the way we
11326 // currently handle addresses it is the same as an 'r' memory constraint.
11327 case 'Q': return C_Memory;
11329 } else if (Constraint.size() == 2) {
11330 switch (Constraint[0]) {
11332 // All 'U+' constraints are addresses.
11333 case 'U': return C_Memory;
11336 return TargetLowering::getConstraintType(Constraint);
11339 /// Examine constraint type and operand type and determine a weight value.
11340 /// This object must already have been set up with the operand type
11341 /// and the current alternative constraint selected.
11342 TargetLowering::ConstraintWeight
11343 ARMTargetLowering::getSingleConstraintMatchWeight(
11344 AsmOperandInfo &info, const char *constraint) const {
11345 ConstraintWeight weight = CW_Invalid;
11346 Value *CallOperandVal = info.CallOperandVal;
11347 // If we don't have a value, we can't do a match,
11348 // but allow it at the lowest weight.
11349 if (!CallOperandVal)
11351 Type *type = CallOperandVal->getType();
11352 // Look at the constraint type.
11353 switch (*constraint) {
11355 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
11358 if (type->isIntegerTy()) {
11359 if (Subtarget->isThumb())
11360 weight = CW_SpecificReg;
11362 weight = CW_Register;
11366 if (type->isFloatingPointTy())
11367 weight = CW_Register;
11373 typedef std::pair<unsigned, const TargetRegisterClass*> RCPair;
11374 RCPair ARMTargetLowering::getRegForInlineAsmConstraint(
11375 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
11376 if (Constraint.size() == 1) {
11377 // GCC ARM Constraint Letters
11378 switch (Constraint[0]) {
11379 case 'l': // Low regs or general regs.
11380 if (Subtarget->isThumb())
11381 return RCPair(0U, &ARM::tGPRRegClass);
11382 return RCPair(0U, &ARM::GPRRegClass);
11383 case 'h': // High regs or no regs.
11384 if (Subtarget->isThumb())
11385 return RCPair(0U, &ARM::hGPRRegClass);
11388 if (Subtarget->isThumb1Only())
11389 return RCPair(0U, &ARM::tGPRRegClass);
11390 return RCPair(0U, &ARM::GPRRegClass);
11392 if (VT == MVT::Other)
11394 if (VT == MVT::f32)
11395 return RCPair(0U, &ARM::SPRRegClass);
11396 if (VT.getSizeInBits() == 64)
11397 return RCPair(0U, &ARM::DPRRegClass);
11398 if (VT.getSizeInBits() == 128)
11399 return RCPair(0U, &ARM::QPRRegClass);
11402 if (VT == MVT::Other)
11404 if (VT == MVT::f32)
11405 return RCPair(0U, &ARM::SPR_8RegClass);
11406 if (VT.getSizeInBits() == 64)
11407 return RCPair(0U, &ARM::DPR_8RegClass);
11408 if (VT.getSizeInBits() == 128)
11409 return RCPair(0U, &ARM::QPR_8RegClass);
11412 if (VT == MVT::f32)
11413 return RCPair(0U, &ARM::SPRRegClass);
11417 if (StringRef("{cc}").equals_lower(Constraint))
11418 return std::make_pair(unsigned(ARM::CPSR), &ARM::CCRRegClass);
11420 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
11423 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
11424 /// vector. If it is invalid, don't add anything to Ops.
11425 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
11426 std::string &Constraint,
11427 std::vector<SDValue>&Ops,
11428 SelectionDAG &DAG) const {
11431 // Currently only support length 1 constraints.
11432 if (Constraint.length() != 1) return;
11434 char ConstraintLetter = Constraint[0];
11435 switch (ConstraintLetter) {
11438 case 'I': case 'J': case 'K': case 'L':
11439 case 'M': case 'N': case 'O':
11440 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
11444 int64_t CVal64 = C->getSExtValue();
11445 int CVal = (int) CVal64;
11446 // None of these constraints allow values larger than 32 bits. Check
11447 // that the value fits in an int.
11448 if (CVal != CVal64)
11451 switch (ConstraintLetter) {
11453 // Constant suitable for movw, must be between 0 and
11455 if (Subtarget->hasV6T2Ops())
11456 if (CVal >= 0 && CVal <= 65535)
11460 if (Subtarget->isThumb1Only()) {
11461 // This must be a constant between 0 and 255, for ADD
11463 if (CVal >= 0 && CVal <= 255)
11465 } else if (Subtarget->isThumb2()) {
11466 // A constant that can be used as an immediate value in a
11467 // data-processing instruction.
11468 if (ARM_AM::getT2SOImmVal(CVal) != -1)
11471 // A constant that can be used as an immediate value in a
11472 // data-processing instruction.
11473 if (ARM_AM::getSOImmVal(CVal) != -1)
11479 if (Subtarget->isThumb1Only()) {
11480 // This must be a constant between -255 and -1, for negated ADD
11481 // immediates. This can be used in GCC with an "n" modifier that
11482 // prints the negated value, for use with SUB instructions. It is
11483 // not useful otherwise but is implemented for compatibility.
11484 if (CVal >= -255 && CVal <= -1)
11487 // This must be a constant between -4095 and 4095. It is not clear
11488 // what this constraint is intended for. Implemented for
11489 // compatibility with GCC.
11490 if (CVal >= -4095 && CVal <= 4095)
11496 if (Subtarget->isThumb1Only()) {
11497 // A 32-bit value where only one byte has a nonzero value. Exclude
11498 // zero to match GCC. This constraint is used by GCC internally for
11499 // constants that can be loaded with a move/shift combination.
11500 // It is not useful otherwise but is implemented for compatibility.
11501 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
11503 } else if (Subtarget->isThumb2()) {
11504 // A constant whose bitwise inverse can be used as an immediate
11505 // value in a data-processing instruction. This can be used in GCC
11506 // with a "B" modifier that prints the inverted value, for use with
11507 // BIC and MVN instructions. It is not useful otherwise but is
11508 // implemented for compatibility.
11509 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
11512 // A constant whose bitwise inverse can be used as an immediate
11513 // value in a data-processing instruction. This can be used in GCC
11514 // with a "B" modifier that prints the inverted value, for use with
11515 // BIC and MVN instructions. It is not useful otherwise but is
11516 // implemented for compatibility.
11517 if (ARM_AM::getSOImmVal(~CVal) != -1)
11523 if (Subtarget->isThumb1Only()) {
11524 // This must be a constant between -7 and 7,
11525 // for 3-operand ADD/SUB immediate instructions.
11526 if (CVal >= -7 && CVal < 7)
11528 } else if (Subtarget->isThumb2()) {
11529 // A constant whose negation can be used as an immediate value in a
11530 // data-processing instruction. This can be used in GCC with an "n"
11531 // modifier that prints the negated value, for use with SUB
11532 // instructions. It is not useful otherwise but is implemented for
11534 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
11537 // A constant whose negation can be used as an immediate value in a
11538 // data-processing instruction. This can be used in GCC with an "n"
11539 // modifier that prints the negated value, for use with SUB
11540 // instructions. It is not useful otherwise but is implemented for
11542 if (ARM_AM::getSOImmVal(-CVal) != -1)
11548 if (Subtarget->isThumb1Only()) {
11549 // This must be a multiple of 4 between 0 and 1020, for
11550 // ADD sp + immediate.
11551 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
11554 // A power of two or a constant between 0 and 32. This is used in
11555 // GCC for the shift amount on shifted register operands, but it is
11556 // useful in general for any shift amounts.
11557 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
11563 if (Subtarget->isThumb()) { // FIXME thumb2
11564 // This must be a constant between 0 and 31, for shift amounts.
11565 if (CVal >= 0 && CVal <= 31)
11571 if (Subtarget->isThumb()) { // FIXME thumb2
11572 // This must be a multiple of 4 between -508 and 508, for
11573 // ADD/SUB sp = sp + immediate.
11574 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
11579 Result = DAG.getTargetConstant(CVal, SDLoc(Op), Op.getValueType());
11583 if (Result.getNode()) {
11584 Ops.push_back(Result);
11587 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
11590 static RTLIB::Libcall getDivRemLibcall(
11591 const SDNode *N, MVT::SimpleValueType SVT) {
11592 assert((N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD::UDIVREM ||
11593 N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM) &&
11594 "Unhandled Opcode in getDivRemLibcall");
11595 bool isSigned = N->getOpcode() == ISD::SDIVREM ||
11596 N->getOpcode() == ISD::SREM;
11599 default: llvm_unreachable("Unexpected request for libcall!");
11600 case MVT::i8: LC = isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
11601 case MVT::i16: LC = isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
11602 case MVT::i32: LC = isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
11603 case MVT::i64: LC = isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
11608 static TargetLowering::ArgListTy getDivRemArgList(
11609 const SDNode *N, LLVMContext *Context) {
11610 assert((N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD::UDIVREM ||
11611 N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM) &&
11612 "Unhandled Opcode in getDivRemArgList");
11613 bool isSigned = N->getOpcode() == ISD::SDIVREM ||
11614 N->getOpcode() == ISD::SREM;
11615 TargetLowering::ArgListTy Args;
11616 TargetLowering::ArgListEntry Entry;
11617 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
11618 EVT ArgVT = N->getOperand(i).getValueType();
11619 Type *ArgTy = ArgVT.getTypeForEVT(*Context);
11620 Entry.Node = N->getOperand(i);
11622 Entry.isSExt = isSigned;
11623 Entry.isZExt = !isSigned;
11624 Args.push_back(Entry);
11629 SDValue ARMTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const {
11630 assert((Subtarget->isTargetAEABI() || Subtarget->isTargetAndroid()) &&
11631 "Register-based DivRem lowering only");
11632 unsigned Opcode = Op->getOpcode();
11633 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
11634 "Invalid opcode for Div/Rem lowering");
11635 bool isSigned = (Opcode == ISD::SDIVREM);
11636 EVT VT = Op->getValueType(0);
11637 Type *Ty = VT.getTypeForEVT(*DAG.getContext());
11639 RTLIB::Libcall LC = getDivRemLibcall(Op.getNode(),
11640 VT.getSimpleVT().SimpleTy);
11641 SDValue InChain = DAG.getEntryNode();
11643 TargetLowering::ArgListTy Args = getDivRemArgList(Op.getNode(),
11646 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
11647 getPointerTy(DAG.getDataLayout()));
11649 Type *RetTy = (Type*)StructType::get(Ty, Ty, nullptr);
11652 TargetLowering::CallLoweringInfo CLI(DAG);
11653 CLI.setDebugLoc(dl).setChain(InChain)
11654 .setCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
11655 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
11657 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
11658 return CallInfo.first;
11661 // Lowers REM using divmod helpers
11662 // see RTABI section 4.2/4.3
11663 SDValue ARMTargetLowering::LowerREM(SDNode *N, SelectionDAG &DAG) const {
11664 // Build return types (div and rem)
11665 std::vector<Type*> RetTyParams;
11666 Type *RetTyElement;
11668 switch (N->getValueType(0).getSimpleVT().SimpleTy) {
11669 default: llvm_unreachable("Unexpected request for libcall!");
11670 case MVT::i8: RetTyElement = Type::getInt8Ty(*DAG.getContext()); break;
11671 case MVT::i16: RetTyElement = Type::getInt16Ty(*DAG.getContext()); break;
11672 case MVT::i32: RetTyElement = Type::getInt32Ty(*DAG.getContext()); break;
11673 case MVT::i64: RetTyElement = Type::getInt64Ty(*DAG.getContext()); break;
11676 RetTyParams.push_back(RetTyElement);
11677 RetTyParams.push_back(RetTyElement);
11678 ArrayRef<Type*> ret = ArrayRef<Type*>(RetTyParams);
11679 Type *RetTy = StructType::get(*DAG.getContext(), ret);
11681 RTLIB::Libcall LC = getDivRemLibcall(N, N->getValueType(0).getSimpleVT().
11683 SDValue InChain = DAG.getEntryNode();
11684 TargetLowering::ArgListTy Args = getDivRemArgList(N, DAG.getContext());
11685 bool isSigned = N->getOpcode() == ISD::SREM;
11686 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
11687 getPointerTy(DAG.getDataLayout()));
11690 CallLoweringInfo CLI(DAG);
11691 CLI.setChain(InChain)
11692 .setCallee(CallingConv::ARM_AAPCS, RetTy, Callee, std::move(Args), 0)
11693 .setSExtResult(isSigned).setZExtResult(!isSigned).setDebugLoc(SDLoc(N));
11694 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
11696 // Return second (rem) result operand (first contains div)
11697 SDNode *ResNode = CallResult.first.getNode();
11698 assert(ResNode->getNumOperands() == 2 && "divmod should return two operands");
11699 return ResNode->getOperand(1);
11703 ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const {
11704 assert(Subtarget->isTargetWindows() && "unsupported target platform");
11708 SDValue Chain = Op.getOperand(0);
11709 SDValue Size = Op.getOperand(1);
11711 SDValue Words = DAG.getNode(ISD::SRL, DL, MVT::i32, Size,
11712 DAG.getConstant(2, DL, MVT::i32));
11715 Chain = DAG.getCopyToReg(Chain, DL, ARM::R4, Words, Flag);
11716 Flag = Chain.getValue(1);
11718 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11719 Chain = DAG.getNode(ARMISD::WIN__CHKSTK, DL, NodeTys, Chain, Flag);
11721 SDValue NewSP = DAG.getCopyFromReg(Chain, DL, ARM::SP, MVT::i32);
11722 Chain = NewSP.getValue(1);
11724 SDValue Ops[2] = { NewSP, Chain };
11725 return DAG.getMergeValues(Ops, DL);
11728 SDValue ARMTargetLowering::LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const {
11729 assert(Op.getValueType() == MVT::f64 && Subtarget->isFPOnlySP() &&
11730 "Unexpected type for custom-lowering FP_EXTEND");
11733 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType());
11735 SDValue SrcVal = Op.getOperand(0);
11736 return makeLibCall(DAG, LC, Op.getValueType(), SrcVal, /*isSigned*/ false,
11740 SDValue ARMTargetLowering::LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const {
11741 assert(Op.getOperand(0).getValueType() == MVT::f64 &&
11742 Subtarget->isFPOnlySP() &&
11743 "Unexpected type for custom-lowering FP_ROUND");
11746 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
11748 SDValue SrcVal = Op.getOperand(0);
11749 return makeLibCall(DAG, LC, Op.getValueType(), SrcVal, /*isSigned*/ false,
11754 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
11755 // The ARM target isn't yet aware of offsets.
11759 bool ARM::isBitFieldInvertedMask(unsigned v) {
11760 if (v == 0xffffffff)
11763 // there can be 1's on either or both "outsides", all the "inside"
11764 // bits must be 0's
11765 return isShiftedMask_32(~v);
11768 /// isFPImmLegal - Returns true if the target can instruction select the
11769 /// specified FP immediate natively. If false, the legalizer will
11770 /// materialize the FP immediate as a load from a constant pool.
11771 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
11772 if (!Subtarget->hasVFP3())
11774 if (VT == MVT::f32)
11775 return ARM_AM::getFP32Imm(Imm) != -1;
11776 if (VT == MVT::f64 && !Subtarget->isFPOnlySP())
11777 return ARM_AM::getFP64Imm(Imm) != -1;
11781 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
11782 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
11783 /// specified in the intrinsic calls.
11784 bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
11786 unsigned Intrinsic) const {
11787 switch (Intrinsic) {
11788 case Intrinsic::arm_neon_vld1:
11789 case Intrinsic::arm_neon_vld2:
11790 case Intrinsic::arm_neon_vld3:
11791 case Intrinsic::arm_neon_vld4:
11792 case Intrinsic::arm_neon_vld2lane:
11793 case Intrinsic::arm_neon_vld3lane:
11794 case Intrinsic::arm_neon_vld4lane: {
11795 Info.opc = ISD::INTRINSIC_W_CHAIN;
11796 // Conservatively set memVT to the entire set of vectors loaded.
11797 auto &DL = I.getCalledFunction()->getParent()->getDataLayout();
11798 uint64_t NumElts = DL.getTypeSizeInBits(I.getType()) / 64;
11799 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
11800 Info.ptrVal = I.getArgOperand(0);
11802 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
11803 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
11804 Info.vol = false; // volatile loads with NEON intrinsics not supported
11805 Info.readMem = true;
11806 Info.writeMem = false;
11809 case Intrinsic::arm_neon_vst1:
11810 case Intrinsic::arm_neon_vst2:
11811 case Intrinsic::arm_neon_vst3:
11812 case Intrinsic::arm_neon_vst4:
11813 case Intrinsic::arm_neon_vst2lane:
11814 case Intrinsic::arm_neon_vst3lane:
11815 case Intrinsic::arm_neon_vst4lane: {
11816 Info.opc = ISD::INTRINSIC_VOID;
11817 // Conservatively set memVT to the entire set of vectors stored.
11818 auto &DL = I.getCalledFunction()->getParent()->getDataLayout();
11819 unsigned NumElts = 0;
11820 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
11821 Type *ArgTy = I.getArgOperand(ArgI)->getType();
11822 if (!ArgTy->isVectorTy())
11824 NumElts += DL.getTypeSizeInBits(ArgTy) / 64;
11826 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
11827 Info.ptrVal = I.getArgOperand(0);
11829 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
11830 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
11831 Info.vol = false; // volatile stores with NEON intrinsics not supported
11832 Info.readMem = false;
11833 Info.writeMem = true;
11836 case Intrinsic::arm_ldaex:
11837 case Intrinsic::arm_ldrex: {
11838 auto &DL = I.getCalledFunction()->getParent()->getDataLayout();
11839 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
11840 Info.opc = ISD::INTRINSIC_W_CHAIN;
11841 Info.memVT = MVT::getVT(PtrTy->getElementType());
11842 Info.ptrVal = I.getArgOperand(0);
11844 Info.align = DL.getABITypeAlignment(PtrTy->getElementType());
11846 Info.readMem = true;
11847 Info.writeMem = false;
11850 case Intrinsic::arm_stlex:
11851 case Intrinsic::arm_strex: {
11852 auto &DL = I.getCalledFunction()->getParent()->getDataLayout();
11853 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
11854 Info.opc = ISD::INTRINSIC_W_CHAIN;
11855 Info.memVT = MVT::getVT(PtrTy->getElementType());
11856 Info.ptrVal = I.getArgOperand(1);
11858 Info.align = DL.getABITypeAlignment(PtrTy->getElementType());
11860 Info.readMem = false;
11861 Info.writeMem = true;
11864 case Intrinsic::arm_stlexd:
11865 case Intrinsic::arm_strexd: {
11866 Info.opc = ISD::INTRINSIC_W_CHAIN;
11867 Info.memVT = MVT::i64;
11868 Info.ptrVal = I.getArgOperand(2);
11872 Info.readMem = false;
11873 Info.writeMem = true;
11876 case Intrinsic::arm_ldaexd:
11877 case Intrinsic::arm_ldrexd: {
11878 Info.opc = ISD::INTRINSIC_W_CHAIN;
11879 Info.memVT = MVT::i64;
11880 Info.ptrVal = I.getArgOperand(0);
11884 Info.readMem = true;
11885 Info.writeMem = false;
11895 /// \brief Returns true if it is beneficial to convert a load of a constant
11896 /// to just the constant itself.
11897 bool ARMTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
11899 assert(Ty->isIntegerTy());
11901 unsigned Bits = Ty->getPrimitiveSizeInBits();
11902 if (Bits == 0 || Bits > 32)
11907 Instruction* ARMTargetLowering::makeDMB(IRBuilder<> &Builder,
11908 ARM_MB::MemBOpt Domain) const {
11909 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
11911 // First, if the target has no DMB, see what fallback we can use.
11912 if (!Subtarget->hasDataBarrier()) {
11913 // Some ARMv6 cpus can support data barriers with an mcr instruction.
11914 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
11916 if (Subtarget->hasV6Ops() && !Subtarget->isThumb()) {
11917 Function *MCR = llvm::Intrinsic::getDeclaration(M, Intrinsic::arm_mcr);
11918 Value* args[6] = {Builder.getInt32(15), Builder.getInt32(0),
11919 Builder.getInt32(0), Builder.getInt32(7),
11920 Builder.getInt32(10), Builder.getInt32(5)};
11921 return Builder.CreateCall(MCR, args);
11923 // Instead of using barriers, atomic accesses on these subtargets use
11925 llvm_unreachable("makeDMB on a target so old that it has no barriers");
11928 Function *DMB = llvm::Intrinsic::getDeclaration(M, Intrinsic::arm_dmb);
11929 // Only a full system barrier exists in the M-class architectures.
11930 Domain = Subtarget->isMClass() ? ARM_MB::SY : Domain;
11931 Constant *CDomain = Builder.getInt32(Domain);
11932 return Builder.CreateCall(DMB, CDomain);
11936 // Based on http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
11937 Instruction* ARMTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
11938 AtomicOrdering Ord, bool IsStore,
11939 bool IsLoad) const {
11940 if (!getInsertFencesForAtomic())
11946 llvm_unreachable("Invalid fence: unordered/non-atomic");
11949 return nullptr; // Nothing to do
11950 case SequentiallyConsistent:
11952 return nullptr; // Nothing to do
11955 case AcquireRelease:
11956 if (Subtarget->isSwift())
11957 return makeDMB(Builder, ARM_MB::ISHST);
11958 // FIXME: add a comment with a link to documentation justifying this.
11960 return makeDMB(Builder, ARM_MB::ISH);
11962 llvm_unreachable("Unknown fence ordering in emitLeadingFence");
11965 Instruction* ARMTargetLowering::emitTrailingFence(IRBuilder<> &Builder,
11966 AtomicOrdering Ord, bool IsStore,
11967 bool IsLoad) const {
11968 if (!getInsertFencesForAtomic())
11974 llvm_unreachable("Invalid fence: unordered/not-atomic");
11977 return nullptr; // Nothing to do
11979 case AcquireRelease:
11980 case SequentiallyConsistent:
11981 return makeDMB(Builder, ARM_MB::ISH);
11983 llvm_unreachable("Unknown fence ordering in emitTrailingFence");
11986 // Loads and stores less than 64-bits are already atomic; ones above that
11987 // are doomed anyway, so defer to the default libcall and blame the OS when
11988 // things go wrong. Cortex M doesn't have ldrexd/strexd though, so don't emit
11989 // anything for those.
11990 bool ARMTargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
11991 unsigned Size = SI->getValueOperand()->getType()->getPrimitiveSizeInBits();
11992 return (Size == 64) && !Subtarget->isMClass();
11995 // Loads and stores less than 64-bits are already atomic; ones above that
11996 // are doomed anyway, so defer to the default libcall and blame the OS when
11997 // things go wrong. Cortex M doesn't have ldrexd/strexd though, so don't emit
11998 // anything for those.
11999 // FIXME: ldrd and strd are atomic if the CPU has LPAE (e.g. A15 has that
12000 // guarantee, see DDI0406C ARM architecture reference manual,
12001 // sections A8.8.72-74 LDRD)
12002 TargetLowering::AtomicExpansionKind
12003 ARMTargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
12004 unsigned Size = LI->getType()->getPrimitiveSizeInBits();
12005 return ((Size == 64) && !Subtarget->isMClass()) ? AtomicExpansionKind::LLOnly
12006 : AtomicExpansionKind::None;
12009 // For the real atomic operations, we have ldrex/strex up to 32 bits,
12010 // and up to 64 bits on the non-M profiles
12011 TargetLowering::AtomicExpansionKind
12012 ARMTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
12013 unsigned Size = AI->getType()->getPrimitiveSizeInBits();
12014 return (Size <= (Subtarget->isMClass() ? 32U : 64U))
12015 ? AtomicExpansionKind::LLSC
12016 : AtomicExpansionKind::None;
12019 bool ARMTargetLowering::shouldExpandAtomicCmpXchgInIR(
12020 AtomicCmpXchgInst *AI) const {
12024 // This has so far only been implemented for MachO.
12025 bool ARMTargetLowering::useLoadStackGuardNode() const {
12026 return Subtarget->isTargetMachO();
12029 bool ARMTargetLowering::canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
12030 unsigned &Cost) const {
12031 // If we do not have NEON, vector types are not natively supported.
12032 if (!Subtarget->hasNEON())
12035 // Floating point values and vector values map to the same register file.
12036 // Therefore, although we could do a store extract of a vector type, this is
12037 // better to leave at float as we have more freedom in the addressing mode for
12039 if (VectorTy->isFPOrFPVectorTy())
12042 // If the index is unknown at compile time, this is very expensive to lower
12043 // and it is not possible to combine the store with the extract.
12044 if (!isa<ConstantInt>(Idx))
12047 assert(VectorTy->isVectorTy() && "VectorTy is not a vector type");
12048 unsigned BitWidth = cast<VectorType>(VectorTy)->getBitWidth();
12049 // We can do a store + vector extract on any vector that fits perfectly in a D
12051 if (BitWidth == 64 || BitWidth == 128) {
12058 bool ARMTargetLowering::isCheapToSpeculateCttz() const {
12059 return Subtarget->hasV6T2Ops();
12062 bool ARMTargetLowering::isCheapToSpeculateCtlz() const {
12063 return Subtarget->hasV6T2Ops();
12066 Value *ARMTargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
12067 AtomicOrdering Ord) const {
12068 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
12069 Type *ValTy = cast<PointerType>(Addr->getType())->getElementType();
12070 bool IsAcquire = isAtLeastAcquire(Ord);
12072 // Since i64 isn't legal and intrinsics don't get type-lowered, the ldrexd
12073 // intrinsic must return {i32, i32} and we have to recombine them into a
12074 // single i64 here.
12075 if (ValTy->getPrimitiveSizeInBits() == 64) {
12076 Intrinsic::ID Int =
12077 IsAcquire ? Intrinsic::arm_ldaexd : Intrinsic::arm_ldrexd;
12078 Function *Ldrex = llvm::Intrinsic::getDeclaration(M, Int);
12080 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
12081 Value *LoHi = Builder.CreateCall(Ldrex, Addr, "lohi");
12083 Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo");
12084 Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi");
12085 if (!Subtarget->isLittle())
12086 std::swap (Lo, Hi);
12087 Lo = Builder.CreateZExt(Lo, ValTy, "lo64");
12088 Hi = Builder.CreateZExt(Hi, ValTy, "hi64");
12089 return Builder.CreateOr(
12090 Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 32)), "val64");
12093 Type *Tys[] = { Addr->getType() };
12094 Intrinsic::ID Int = IsAcquire ? Intrinsic::arm_ldaex : Intrinsic::arm_ldrex;
12095 Function *Ldrex = llvm::Intrinsic::getDeclaration(M, Int, Tys);
12097 return Builder.CreateTruncOrBitCast(
12098 Builder.CreateCall(Ldrex, Addr),
12099 cast<PointerType>(Addr->getType())->getElementType());
12102 void ARMTargetLowering::emitAtomicCmpXchgNoStoreLLBalance(
12103 IRBuilder<> &Builder) const {
12104 if (!Subtarget->hasV7Ops())
12106 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
12107 Builder.CreateCall(llvm::Intrinsic::getDeclaration(M, Intrinsic::arm_clrex));
12110 Value *ARMTargetLowering::emitStoreConditional(IRBuilder<> &Builder, Value *Val,
12112 AtomicOrdering Ord) const {
12113 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
12114 bool IsRelease = isAtLeastRelease(Ord);
12116 // Since the intrinsics must have legal type, the i64 intrinsics take two
12117 // parameters: "i32, i32". We must marshal Val into the appropriate form
12118 // before the call.
12119 if (Val->getType()->getPrimitiveSizeInBits() == 64) {
12120 Intrinsic::ID Int =
12121 IsRelease ? Intrinsic::arm_stlexd : Intrinsic::arm_strexd;
12122 Function *Strex = Intrinsic::getDeclaration(M, Int);
12123 Type *Int32Ty = Type::getInt32Ty(M->getContext());
12125 Value *Lo = Builder.CreateTrunc(Val, Int32Ty, "lo");
12126 Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 32), Int32Ty, "hi");
12127 if (!Subtarget->isLittle())
12128 std::swap (Lo, Hi);
12129 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
12130 return Builder.CreateCall(Strex, {Lo, Hi, Addr});
12133 Intrinsic::ID Int = IsRelease ? Intrinsic::arm_stlex : Intrinsic::arm_strex;
12134 Type *Tys[] = { Addr->getType() };
12135 Function *Strex = Intrinsic::getDeclaration(M, Int, Tys);
12137 return Builder.CreateCall(
12138 Strex, {Builder.CreateZExtOrBitCast(
12139 Val, Strex->getFunctionType()->getParamType(0)),
12143 /// \brief Lower an interleaved load into a vldN intrinsic.
12145 /// E.g. Lower an interleaved load (Factor = 2):
12146 /// %wide.vec = load <8 x i32>, <8 x i32>* %ptr, align 4
12147 /// %v0 = shuffle %wide.vec, undef, <0, 2, 4, 6> ; Extract even elements
12148 /// %v1 = shuffle %wide.vec, undef, <1, 3, 5, 7> ; Extract odd elements
12151 /// %vld2 = { <4 x i32>, <4 x i32> } call llvm.arm.neon.vld2(%ptr, 4)
12152 /// %vec0 = extractelement { <4 x i32>, <4 x i32> } %vld2, i32 0
12153 /// %vec1 = extractelement { <4 x i32>, <4 x i32> } %vld2, i32 1
12154 bool ARMTargetLowering::lowerInterleavedLoad(
12155 LoadInst *LI, ArrayRef<ShuffleVectorInst *> Shuffles,
12156 ArrayRef<unsigned> Indices, unsigned Factor) const {
12157 assert(Factor >= 2 && Factor <= getMaxSupportedInterleaveFactor() &&
12158 "Invalid interleave factor");
12159 assert(!Shuffles.empty() && "Empty shufflevector input");
12160 assert(Shuffles.size() == Indices.size() &&
12161 "Unmatched number of shufflevectors and indices");
12163 VectorType *VecTy = Shuffles[0]->getType();
12164 Type *EltTy = VecTy->getVectorElementType();
12166 const DataLayout &DL = LI->getModule()->getDataLayout();
12167 unsigned VecSize = DL.getTypeSizeInBits(VecTy);
12168 bool EltIs64Bits = DL.getTypeSizeInBits(EltTy) == 64;
12170 // Skip if we do not have NEON and skip illegal vector types and vector types
12171 // with i64/f64 elements (vldN doesn't support i64/f64 elements).
12172 if (!Subtarget->hasNEON() || (VecSize != 64 && VecSize != 128) || EltIs64Bits)
12175 // A pointer vector can not be the return type of the ldN intrinsics. Need to
12176 // load integer vectors first and then convert to pointer vectors.
12177 if (EltTy->isPointerTy())
12179 VectorType::get(DL.getIntPtrType(EltTy), VecTy->getVectorNumElements());
12181 static const Intrinsic::ID LoadInts[3] = {Intrinsic::arm_neon_vld2,
12182 Intrinsic::arm_neon_vld3,
12183 Intrinsic::arm_neon_vld4};
12185 IRBuilder<> Builder(LI);
12186 SmallVector<Value *, 2> Ops;
12188 Type *Int8Ptr = Builder.getInt8PtrTy(LI->getPointerAddressSpace());
12189 Ops.push_back(Builder.CreateBitCast(LI->getPointerOperand(), Int8Ptr));
12190 Ops.push_back(Builder.getInt32(LI->getAlignment()));
12192 Type *Tys[] = { VecTy, Int8Ptr };
12193 Function *VldnFunc =
12194 Intrinsic::getDeclaration(LI->getModule(), LoadInts[Factor - 2], Tys);
12195 CallInst *VldN = Builder.CreateCall(VldnFunc, Ops, "vldN");
12197 // Replace uses of each shufflevector with the corresponding vector loaded
12199 for (unsigned i = 0; i < Shuffles.size(); i++) {
12200 ShuffleVectorInst *SV = Shuffles[i];
12201 unsigned Index = Indices[i];
12203 Value *SubVec = Builder.CreateExtractValue(VldN, Index);
12205 // Convert the integer vector to pointer vector if the element is pointer.
12206 if (EltTy->isPointerTy())
12207 SubVec = Builder.CreateIntToPtr(SubVec, SV->getType());
12209 SV->replaceAllUsesWith(SubVec);
12215 /// \brief Get a mask consisting of sequential integers starting from \p Start.
12217 /// I.e. <Start, Start + 1, ..., Start + NumElts - 1>
12218 static Constant *getSequentialMask(IRBuilder<> &Builder, unsigned Start,
12219 unsigned NumElts) {
12220 SmallVector<Constant *, 16> Mask;
12221 for (unsigned i = 0; i < NumElts; i++)
12222 Mask.push_back(Builder.getInt32(Start + i));
12224 return ConstantVector::get(Mask);
12227 /// \brief Lower an interleaved store into a vstN intrinsic.
12229 /// E.g. Lower an interleaved store (Factor = 3):
12230 /// %i.vec = shuffle <8 x i32> %v0, <8 x i32> %v1,
12231 /// <0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11>
12232 /// store <12 x i32> %i.vec, <12 x i32>* %ptr, align 4
12235 /// %sub.v0 = shuffle <8 x i32> %v0, <8 x i32> v1, <0, 1, 2, 3>
12236 /// %sub.v1 = shuffle <8 x i32> %v0, <8 x i32> v1, <4, 5, 6, 7>
12237 /// %sub.v2 = shuffle <8 x i32> %v0, <8 x i32> v1, <8, 9, 10, 11>
12238 /// call void llvm.arm.neon.vst3(%ptr, %sub.v0, %sub.v1, %sub.v2, 4)
12240 /// Note that the new shufflevectors will be removed and we'll only generate one
12241 /// vst3 instruction in CodeGen.
12242 bool ARMTargetLowering::lowerInterleavedStore(StoreInst *SI,
12243 ShuffleVectorInst *SVI,
12244 unsigned Factor) const {
12245 assert(Factor >= 2 && Factor <= getMaxSupportedInterleaveFactor() &&
12246 "Invalid interleave factor");
12248 VectorType *VecTy = SVI->getType();
12249 assert(VecTy->getVectorNumElements() % Factor == 0 &&
12250 "Invalid interleaved store");
12252 unsigned NumSubElts = VecTy->getVectorNumElements() / Factor;
12253 Type *EltTy = VecTy->getVectorElementType();
12254 VectorType *SubVecTy = VectorType::get(EltTy, NumSubElts);
12256 const DataLayout &DL = SI->getModule()->getDataLayout();
12257 unsigned SubVecSize = DL.getTypeSizeInBits(SubVecTy);
12258 bool EltIs64Bits = DL.getTypeSizeInBits(EltTy) == 64;
12260 // Skip if we do not have NEON and skip illegal vector types and vector types
12261 // with i64/f64 elements (vstN doesn't support i64/f64 elements).
12262 if (!Subtarget->hasNEON() || (SubVecSize != 64 && SubVecSize != 128) ||
12266 Value *Op0 = SVI->getOperand(0);
12267 Value *Op1 = SVI->getOperand(1);
12268 IRBuilder<> Builder(SI);
12270 // StN intrinsics don't support pointer vectors as arguments. Convert pointer
12271 // vectors to integer vectors.
12272 if (EltTy->isPointerTy()) {
12273 Type *IntTy = DL.getIntPtrType(EltTy);
12275 // Convert to the corresponding integer vector.
12277 VectorType::get(IntTy, Op0->getType()->getVectorNumElements());
12278 Op0 = Builder.CreatePtrToInt(Op0, IntVecTy);
12279 Op1 = Builder.CreatePtrToInt(Op1, IntVecTy);
12281 SubVecTy = VectorType::get(IntTy, NumSubElts);
12284 static const Intrinsic::ID StoreInts[3] = {Intrinsic::arm_neon_vst2,
12285 Intrinsic::arm_neon_vst3,
12286 Intrinsic::arm_neon_vst4};
12287 SmallVector<Value *, 6> Ops;
12289 Type *Int8Ptr = Builder.getInt8PtrTy(SI->getPointerAddressSpace());
12290 Ops.push_back(Builder.CreateBitCast(SI->getPointerOperand(), Int8Ptr));
12292 Type *Tys[] = { Int8Ptr, SubVecTy };
12293 Function *VstNFunc = Intrinsic::getDeclaration(
12294 SI->getModule(), StoreInts[Factor - 2], Tys);
12296 // Split the shufflevector operands into sub vectors for the new vstN call.
12297 for (unsigned i = 0; i < Factor; i++)
12298 Ops.push_back(Builder.CreateShuffleVector(
12299 Op0, Op1, getSequentialMask(Builder, NumSubElts * i, NumSubElts)));
12301 Ops.push_back(Builder.getInt32(SI->getAlignment()));
12302 Builder.CreateCall(VstNFunc, Ops);
12314 static bool isHomogeneousAggregate(Type *Ty, HABaseType &Base,
12315 uint64_t &Members) {
12316 if (auto *ST = dyn_cast<StructType>(Ty)) {
12317 for (unsigned i = 0; i < ST->getNumElements(); ++i) {
12318 uint64_t SubMembers = 0;
12319 if (!isHomogeneousAggregate(ST->getElementType(i), Base, SubMembers))
12321 Members += SubMembers;
12323 } else if (auto *AT = dyn_cast<ArrayType>(Ty)) {
12324 uint64_t SubMembers = 0;
12325 if (!isHomogeneousAggregate(AT->getElementType(), Base, SubMembers))
12327 Members += SubMembers * AT->getNumElements();
12328 } else if (Ty->isFloatTy()) {
12329 if (Base != HA_UNKNOWN && Base != HA_FLOAT)
12333 } else if (Ty->isDoubleTy()) {
12334 if (Base != HA_UNKNOWN && Base != HA_DOUBLE)
12338 } else if (auto *VT = dyn_cast<VectorType>(Ty)) {
12345 return VT->getBitWidth() == 64;
12347 return VT->getBitWidth() == 128;
12349 switch (VT->getBitWidth()) {
12362 return (Members > 0 && Members <= 4);
12365 /// \brief Return true if a type is an AAPCS-VFP homogeneous aggregate or one of
12366 /// [N x i32] or [N x i64]. This allows front-ends to skip emitting padding when
12367 /// passing according to AAPCS rules.
12368 bool ARMTargetLowering::functionArgumentNeedsConsecutiveRegisters(
12369 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const {
12370 if (getEffectiveCallingConv(CallConv, isVarArg) !=
12371 CallingConv::ARM_AAPCS_VFP)
12374 HABaseType Base = HA_UNKNOWN;
12375 uint64_t Members = 0;
12376 bool IsHA = isHomogeneousAggregate(Ty, Base, Members);
12377 DEBUG(dbgs() << "isHA: " << IsHA << " "; Ty->dump());
12379 bool IsIntArray = Ty->isArrayTy() && Ty->getArrayElementType()->isIntegerTy();
12380 return IsHA || IsIntArray;
12383 unsigned ARMTargetLowering::getExceptionPointerRegister(
12384 const Constant *PersonalityFn) const {
12385 // Platforms which do not use SjLj EH may return values in these registers
12386 // via the personality function.
12387 return Subtarget->useSjLjEH() ? ARM::NoRegister : ARM::R0;
12390 unsigned ARMTargetLowering::getExceptionSelectorRegister(
12391 const Constant *PersonalityFn) const {
12392 // Platforms which do not use SjLj EH may return values in these registers
12393 // via the personality function.
12394 return Subtarget->useSjLjEH() ? ARM::NoRegister : ARM::R1;