1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "arm-isel"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMISelLowering.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMPerfectShuffle.h"
22 #include "ARMRegisterInfo.h"
23 #include "ARMSubtarget.h"
24 #include "ARMTargetMachine.h"
25 #include "ARMTargetObjectFile.h"
26 #include "llvm/CallingConv.h"
27 #include "llvm/Constants.h"
28 #include "llvm/Function.h"
29 #include "llvm/GlobalValue.h"
30 #include "llvm/Instruction.h"
31 #include "llvm/Intrinsics.h"
32 #include "llvm/Type.h"
33 #include "llvm/CodeGen/CallingConvLower.h"
34 #include "llvm/CodeGen/MachineBasicBlock.h"
35 #include "llvm/CodeGen/MachineFrameInfo.h"
36 #include "llvm/CodeGen/MachineFunction.h"
37 #include "llvm/CodeGen/MachineInstrBuilder.h"
38 #include "llvm/CodeGen/MachineRegisterInfo.h"
39 #include "llvm/CodeGen/PseudoSourceValue.h"
40 #include "llvm/CodeGen/SelectionDAG.h"
41 #include "llvm/MC/MCSectionMachO.h"
42 #include "llvm/Target/TargetOptions.h"
43 #include "llvm/ADT/VectorExtras.h"
44 #include "llvm/ADT/Statistic.h"
45 #include "llvm/Support/CommandLine.h"
46 #include "llvm/Support/ErrorHandling.h"
47 #include "llvm/Support/MathExtras.h"
48 #include "llvm/Support/raw_ostream.h"
52 STATISTIC(NumTailCalls, "Number of tail calls");
54 // This option should go away when tail calls fully work.
56 EnableARMTailCalls("arm-tail-calls", cl::Hidden,
57 cl::desc("Generate tail calls (TEMPORARY OPTION)."),
61 EnableARMLongCalls("arm-long-calls", cl::Hidden,
62 cl::desc("Generate calls via indirect call instructions"),
66 ARMInterworking("arm-interworking", cl::Hidden,
67 cl::desc("Enable / disable ARM interworking (for debugging only)"),
71 EnableARMCodePlacement("arm-code-placement", cl::Hidden,
72 cl::desc("Enable code placement pass for ARM"),
75 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
76 CCValAssign::LocInfo &LocInfo,
77 ISD::ArgFlagsTy &ArgFlags,
79 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
80 CCValAssign::LocInfo &LocInfo,
81 ISD::ArgFlagsTy &ArgFlags,
83 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
84 CCValAssign::LocInfo &LocInfo,
85 ISD::ArgFlagsTy &ArgFlags,
87 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
88 CCValAssign::LocInfo &LocInfo,
89 ISD::ArgFlagsTy &ArgFlags,
92 void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
93 EVT PromotedBitwiseVT) {
94 if (VT != PromotedLdStVT) {
95 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
96 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
97 PromotedLdStVT.getSimpleVT());
99 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
100 AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
101 PromotedLdStVT.getSimpleVT());
104 EVT ElemTy = VT.getVectorElementType();
105 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
106 setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
107 if (ElemTy == MVT::i8 || ElemTy == MVT::i16)
108 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
109 if (ElemTy != MVT::i32) {
110 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
111 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand);
112 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand);
113 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand);
115 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
116 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
117 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
118 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Expand);
119 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
120 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
121 if (VT.isInteger()) {
122 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
123 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
124 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
127 // Promote all bit-wise operations.
128 if (VT.isInteger() && VT != PromotedBitwiseVT) {
129 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
130 AddPromotedToType (ISD::AND, VT.getSimpleVT(),
131 PromotedBitwiseVT.getSimpleVT());
132 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
133 AddPromotedToType (ISD::OR, VT.getSimpleVT(),
134 PromotedBitwiseVT.getSimpleVT());
135 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
136 AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
137 PromotedBitwiseVT.getSimpleVT());
140 // Neon does not support vector divide/remainder operations.
141 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
142 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
143 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand);
144 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
145 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
146 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
149 void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
150 addRegisterClass(VT, ARM::DPRRegisterClass);
151 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
154 void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
155 addRegisterClass(VT, ARM::QPRRegisterClass);
156 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
159 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
160 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
161 return new TargetLoweringObjectFileMachO();
163 return new ARMElfTargetObjectFile();
166 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
167 : TargetLowering(TM, createTLOF(TM)) {
168 Subtarget = &TM.getSubtarget<ARMSubtarget>();
170 if (Subtarget->isTargetDarwin()) {
171 // Uses VFP for Thumb libfuncs if available.
172 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
173 // Single-precision floating-point arithmetic.
174 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
175 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
176 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
177 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
179 // Double-precision floating-point arithmetic.
180 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
181 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
182 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
183 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
185 // Single-precision comparisons.
186 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
187 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
188 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
189 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
190 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
191 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
192 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
193 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
195 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
196 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
197 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
198 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
199 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
200 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
201 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
202 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
204 // Double-precision comparisons.
205 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
206 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
207 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
208 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
209 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
210 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
211 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
212 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
214 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
215 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
216 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
217 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
218 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
219 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
220 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
221 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
223 // Floating-point to integer conversions.
224 // i64 conversions are done via library routines even when generating VFP
225 // instructions, so use the same ones.
226 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
227 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
228 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
229 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
231 // Conversions between floating types.
232 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
233 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
235 // Integer to floating-point conversions.
236 // i64 conversions are done via library routines even when generating VFP
237 // instructions, so use the same ones.
238 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
239 // e.g., __floatunsidf vs. __floatunssidfvfp.
240 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
241 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
242 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
243 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
247 // These libcalls are not available in 32-bit.
248 setLibcallName(RTLIB::SHL_I128, 0);
249 setLibcallName(RTLIB::SRL_I128, 0);
250 setLibcallName(RTLIB::SRA_I128, 0);
252 // Libcalls should use the AAPCS base standard ABI, even if hard float
253 // is in effect, as per the ARM RTABI specification, section 4.1.2.
254 if (Subtarget->isAAPCS_ABI()) {
255 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
256 setLibcallCallingConv(static_cast<RTLIB::Libcall>(i),
257 CallingConv::ARM_AAPCS);
261 if (Subtarget->isThumb1Only())
262 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
264 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
265 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
266 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
267 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
269 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
272 if (Subtarget->hasNEON()) {
273 addDRTypeForNEON(MVT::v2f32);
274 addDRTypeForNEON(MVT::v8i8);
275 addDRTypeForNEON(MVT::v4i16);
276 addDRTypeForNEON(MVT::v2i32);
277 addDRTypeForNEON(MVT::v1i64);
279 addQRTypeForNEON(MVT::v4f32);
280 addQRTypeForNEON(MVT::v2f64);
281 addQRTypeForNEON(MVT::v16i8);
282 addQRTypeForNEON(MVT::v8i16);
283 addQRTypeForNEON(MVT::v4i32);
284 addQRTypeForNEON(MVT::v2i64);
286 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
287 // neither Neon nor VFP support any arithmetic operations on it.
288 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
289 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
290 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
291 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
292 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
293 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
294 setOperationAction(ISD::VSETCC, MVT::v2f64, Expand);
295 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
296 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
297 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
298 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
299 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
300 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
301 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
302 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
303 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
304 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
305 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
306 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
307 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
308 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
309 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
310 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
311 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
313 // Neon does not support some operations on v1i64 and v2i64 types.
314 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
315 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
316 setOperationAction(ISD::VSETCC, MVT::v1i64, Expand);
317 setOperationAction(ISD::VSETCC, MVT::v2i64, Expand);
319 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
320 setTargetDAGCombine(ISD::SHL);
321 setTargetDAGCombine(ISD::SRL);
322 setTargetDAGCombine(ISD::SRA);
323 setTargetDAGCombine(ISD::SIGN_EXTEND);
324 setTargetDAGCombine(ISD::ZERO_EXTEND);
325 setTargetDAGCombine(ISD::ANY_EXTEND);
326 setTargetDAGCombine(ISD::SELECT_CC);
329 computeRegisterProperties();
331 // ARM does not have f32 extending load.
332 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
334 // ARM does not have i1 sign extending load.
335 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
337 // ARM supports all 4 flavors of integer indexed load / store.
338 if (!Subtarget->isThumb1Only()) {
339 for (unsigned im = (unsigned)ISD::PRE_INC;
340 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
341 setIndexedLoadAction(im, MVT::i1, Legal);
342 setIndexedLoadAction(im, MVT::i8, Legal);
343 setIndexedLoadAction(im, MVT::i16, Legal);
344 setIndexedLoadAction(im, MVT::i32, Legal);
345 setIndexedStoreAction(im, MVT::i1, Legal);
346 setIndexedStoreAction(im, MVT::i8, Legal);
347 setIndexedStoreAction(im, MVT::i16, Legal);
348 setIndexedStoreAction(im, MVT::i32, Legal);
352 // i64 operation support.
353 if (Subtarget->isThumb1Only()) {
354 setOperationAction(ISD::MUL, MVT::i64, Expand);
355 setOperationAction(ISD::MULHU, MVT::i32, Expand);
356 setOperationAction(ISD::MULHS, MVT::i32, Expand);
357 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
358 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
360 setOperationAction(ISD::MUL, MVT::i64, Expand);
361 setOperationAction(ISD::MULHU, MVT::i32, Expand);
362 if (!Subtarget->hasV6Ops())
363 setOperationAction(ISD::MULHS, MVT::i32, Expand);
365 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
366 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
367 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
368 setOperationAction(ISD::SRL, MVT::i64, Custom);
369 setOperationAction(ISD::SRA, MVT::i64, Custom);
371 // ARM does not have ROTL.
372 setOperationAction(ISD::ROTL, MVT::i32, Expand);
373 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
374 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
375 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
376 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
378 // Only ARMv6 has BSWAP.
379 if (!Subtarget->hasV6Ops())
380 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
382 // These are expanded into libcalls.
383 if (!Subtarget->hasDivide()) {
384 // v7M has a hardware divider
385 setOperationAction(ISD::SDIV, MVT::i32, Expand);
386 setOperationAction(ISD::UDIV, MVT::i32, Expand);
388 setOperationAction(ISD::SREM, MVT::i32, Expand);
389 setOperationAction(ISD::UREM, MVT::i32, Expand);
390 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
391 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
393 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
394 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
395 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
396 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
397 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
399 setOperationAction(ISD::TRAP, MVT::Other, Legal);
401 // Use the default implementation.
402 setOperationAction(ISD::VASTART, MVT::Other, Custom);
403 setOperationAction(ISD::VAARG, MVT::Other, Expand);
404 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
405 setOperationAction(ISD::VAEND, MVT::Other, Expand);
406 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
407 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
408 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
409 // FIXME: Shouldn't need this, since no register is used, but the legalizer
410 // doesn't yet know how to not do that for SjLj.
411 setExceptionSelectorRegister(ARM::R0);
412 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
413 // Handle atomics directly for ARMv[67] (except for Thumb1), otherwise
414 // use the default expansion.
415 bool canHandleAtomics =
416 (Subtarget->hasV7Ops() ||
417 (Subtarget->hasV6Ops() && !Subtarget->isThumb1Only()));
418 if (canHandleAtomics) {
419 // membarrier needs custom lowering; the rest are legal and handled
421 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
423 // Set them all for expansion, which will force libcalls.
424 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
425 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Expand);
426 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Expand);
427 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
428 setOperationAction(ISD::ATOMIC_SWAP, MVT::i8, Expand);
429 setOperationAction(ISD::ATOMIC_SWAP, MVT::i16, Expand);
430 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
431 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i8, Expand);
432 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i16, Expand);
433 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
434 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Expand);
435 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Expand);
436 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
437 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i8, Expand);
438 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i16, Expand);
439 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
440 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i8, Expand);
441 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i16, Expand);
442 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
443 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i8, Expand);
444 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i16, Expand);
445 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
446 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i8, Expand);
447 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i16, Expand);
448 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
449 // Since the libcalls include locking, fold in the fences
450 setShouldFoldAtomicFences(true);
452 // 64-bit versions are always libcalls (for now)
453 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Expand);
454 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Expand);
455 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Expand);
456 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Expand);
457 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Expand);
458 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Expand);
459 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Expand);
460 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Expand);
462 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
463 if (!Subtarget->hasV6Ops()) {
464 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
465 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
467 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
469 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only())
470 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
471 // iff target supports vfp2.
472 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
474 // We want to custom lower some of our intrinsics.
475 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
476 if (Subtarget->isTargetDarwin()) {
477 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
478 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
481 setOperationAction(ISD::SETCC, MVT::i32, Expand);
482 setOperationAction(ISD::SETCC, MVT::f32, Expand);
483 setOperationAction(ISD::SETCC, MVT::f64, Expand);
484 setOperationAction(ISD::SELECT, MVT::i32, Expand);
485 setOperationAction(ISD::SELECT, MVT::f32, Expand);
486 setOperationAction(ISD::SELECT, MVT::f64, Expand);
487 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
488 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
489 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
491 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
492 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
493 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
494 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
495 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
497 // We don't support sin/cos/fmod/copysign/pow
498 setOperationAction(ISD::FSIN, MVT::f64, Expand);
499 setOperationAction(ISD::FSIN, MVT::f32, Expand);
500 setOperationAction(ISD::FCOS, MVT::f32, Expand);
501 setOperationAction(ISD::FCOS, MVT::f64, Expand);
502 setOperationAction(ISD::FREM, MVT::f64, Expand);
503 setOperationAction(ISD::FREM, MVT::f32, Expand);
504 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
505 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
506 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
508 setOperationAction(ISD::FPOW, MVT::f64, Expand);
509 setOperationAction(ISD::FPOW, MVT::f32, Expand);
511 // Various VFP goodness
512 if (!UseSoftFloat && !Subtarget->isThumb1Only()) {
513 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
514 if (Subtarget->hasVFP2()) {
515 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
516 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
517 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
518 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
520 // Special handling for half-precision FP.
521 if (!Subtarget->hasFP16()) {
522 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
523 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand);
527 // We have target-specific dag combine patterns for the following nodes:
528 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
529 setTargetDAGCombine(ISD::ADD);
530 setTargetDAGCombine(ISD::SUB);
531 setTargetDAGCombine(ISD::MUL);
533 if (Subtarget->hasV6T2Ops())
534 setTargetDAGCombine(ISD::OR);
536 setStackPointerRegisterToSaveRestore(ARM::SP);
538 if (UseSoftFloat || Subtarget->isThumb1Only() || !Subtarget->hasVFP2())
539 setSchedulingPreference(Sched::RegPressure);
541 setSchedulingPreference(Sched::Hybrid);
543 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
545 // On ARM arguments smaller than 4 bytes are extended, so all arguments
546 // are at least 4 bytes aligned.
547 setMinStackArgumentAlignment(4);
549 if (EnableARMCodePlacement)
550 benefitFromCodePlacementOpt = true;
553 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
556 case ARMISD::Wrapper: return "ARMISD::Wrapper";
557 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
558 case ARMISD::CALL: return "ARMISD::CALL";
559 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
560 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
561 case ARMISD::tCALL: return "ARMISD::tCALL";
562 case ARMISD::BRCOND: return "ARMISD::BRCOND";
563 case ARMISD::BR_JT: return "ARMISD::BR_JT";
564 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
565 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
566 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
567 case ARMISD::CMP: return "ARMISD::CMP";
568 case ARMISD::CMPZ: return "ARMISD::CMPZ";
569 case ARMISD::CMPFP: return "ARMISD::CMPFP";
570 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
571 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
572 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
573 case ARMISD::CMOV: return "ARMISD::CMOV";
574 case ARMISD::CNEG: return "ARMISD::CNEG";
576 case ARMISD::RBIT: return "ARMISD::RBIT";
578 case ARMISD::FTOSI: return "ARMISD::FTOSI";
579 case ARMISD::FTOUI: return "ARMISD::FTOUI";
580 case ARMISD::SITOF: return "ARMISD::SITOF";
581 case ARMISD::UITOF: return "ARMISD::UITOF";
583 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
584 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
585 case ARMISD::RRX: return "ARMISD::RRX";
587 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
588 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
590 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
591 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
593 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
595 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
597 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
599 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER";
600 case ARMISD::SYNCBARRIER: return "ARMISD::SYNCBARRIER";
602 case ARMISD::VCEQ: return "ARMISD::VCEQ";
603 case ARMISD::VCGE: return "ARMISD::VCGE";
604 case ARMISD::VCGEU: return "ARMISD::VCGEU";
605 case ARMISD::VCGT: return "ARMISD::VCGT";
606 case ARMISD::VCGTU: return "ARMISD::VCGTU";
607 case ARMISD::VTST: return "ARMISD::VTST";
609 case ARMISD::VSHL: return "ARMISD::VSHL";
610 case ARMISD::VSHRs: return "ARMISD::VSHRs";
611 case ARMISD::VSHRu: return "ARMISD::VSHRu";
612 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
613 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
614 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
615 case ARMISD::VSHRN: return "ARMISD::VSHRN";
616 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
617 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
618 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
619 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
620 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
621 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
622 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
623 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
624 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
625 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
626 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
627 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
628 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
629 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
630 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
631 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
632 case ARMISD::VDUP: return "ARMISD::VDUP";
633 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
634 case ARMISD::VEXT: return "ARMISD::VEXT";
635 case ARMISD::VREV64: return "ARMISD::VREV64";
636 case ARMISD::VREV32: return "ARMISD::VREV32";
637 case ARMISD::VREV16: return "ARMISD::VREV16";
638 case ARMISD::VZIP: return "ARMISD::VZIP";
639 case ARMISD::VUZP: return "ARMISD::VUZP";
640 case ARMISD::VTRN: return "ARMISD::VTRN";
641 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
642 case ARMISD::FMAX: return "ARMISD::FMAX";
643 case ARMISD::FMIN: return "ARMISD::FMIN";
647 /// getRegClassFor - Return the register class that should be used for the
648 /// specified value type.
649 TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const {
650 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
651 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
652 // load / store 4 to 8 consecutive D registers.
653 if (Subtarget->hasNEON()) {
654 if (VT == MVT::v4i64)
655 return ARM::QQPRRegisterClass;
656 else if (VT == MVT::v8i64)
657 return ARM::QQQQPRRegisterClass;
659 return TargetLowering::getRegClassFor(VT);
662 /// getFunctionAlignment - Return the Log2 alignment of this function.
663 unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
664 return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 1 : 2;
667 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
668 unsigned NumVals = N->getNumValues();
670 return Sched::RegPressure;
672 for (unsigned i = 0; i != NumVals; ++i) {
673 EVT VT = N->getValueType(i);
674 if (VT.isFloatingPoint() || VT.isVector())
675 return Sched::Latency;
678 if (!N->isMachineOpcode())
679 return Sched::RegPressure;
681 // Load are scheduled for latency even if there instruction itinerary
683 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
684 const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
686 return Sched::Latency;
688 const InstrItineraryData &Itins = getTargetMachine().getInstrItineraryData();
689 if (!Itins.isEmpty() && Itins.getStageLatency(TID.getSchedClass()) > 2)
690 return Sched::Latency;
691 return Sched::RegPressure;
694 //===----------------------------------------------------------------------===//
696 //===----------------------------------------------------------------------===//
698 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
699 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
701 default: llvm_unreachable("Unknown condition code!");
702 case ISD::SETNE: return ARMCC::NE;
703 case ISD::SETEQ: return ARMCC::EQ;
704 case ISD::SETGT: return ARMCC::GT;
705 case ISD::SETGE: return ARMCC::GE;
706 case ISD::SETLT: return ARMCC::LT;
707 case ISD::SETLE: return ARMCC::LE;
708 case ISD::SETUGT: return ARMCC::HI;
709 case ISD::SETUGE: return ARMCC::HS;
710 case ISD::SETULT: return ARMCC::LO;
711 case ISD::SETULE: return ARMCC::LS;
715 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
716 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
717 ARMCC::CondCodes &CondCode2) {
718 CondCode2 = ARMCC::AL;
720 default: llvm_unreachable("Unknown FP condition!");
722 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
724 case ISD::SETOGT: CondCode = ARMCC::GT; break;
726 case ISD::SETOGE: CondCode = ARMCC::GE; break;
727 case ISD::SETOLT: CondCode = ARMCC::MI; break;
728 case ISD::SETOLE: CondCode = ARMCC::LS; break;
729 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
730 case ISD::SETO: CondCode = ARMCC::VC; break;
731 case ISD::SETUO: CondCode = ARMCC::VS; break;
732 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
733 case ISD::SETUGT: CondCode = ARMCC::HI; break;
734 case ISD::SETUGE: CondCode = ARMCC::PL; break;
736 case ISD::SETULT: CondCode = ARMCC::LT; break;
738 case ISD::SETULE: CondCode = ARMCC::LE; break;
740 case ISD::SETUNE: CondCode = ARMCC::NE; break;
744 //===----------------------------------------------------------------------===//
745 // Calling Convention Implementation
746 //===----------------------------------------------------------------------===//
748 #include "ARMGenCallingConv.inc"
750 // APCS f64 is in register pairs, possibly split to stack
751 static bool f64AssignAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
752 CCValAssign::LocInfo &LocInfo,
753 CCState &State, bool CanFail) {
754 static const unsigned RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
756 // Try to get the first register.
757 if (unsigned Reg = State.AllocateReg(RegList, 4))
758 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
760 // For the 2nd half of a v2f64, do not fail.
764 // Put the whole thing on the stack.
765 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
766 State.AllocateStack(8, 4),
771 // Try to get the second register.
772 if (unsigned Reg = State.AllocateReg(RegList, 4))
773 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
775 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
776 State.AllocateStack(4, 4),
781 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
782 CCValAssign::LocInfo &LocInfo,
783 ISD::ArgFlagsTy &ArgFlags,
785 if (!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
787 if (LocVT == MVT::v2f64 &&
788 !f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
790 return true; // we handled it
793 // AAPCS f64 is in aligned register pairs
794 static bool f64AssignAAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
795 CCValAssign::LocInfo &LocInfo,
796 CCState &State, bool CanFail) {
797 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
798 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
800 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
802 // For the 2nd half of a v2f64, do not just fail.
806 // Put the whole thing on the stack.
807 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
808 State.AllocateStack(8, 8),
814 for (i = 0; i < 2; ++i)
815 if (HiRegList[i] == Reg)
818 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
819 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
824 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
825 CCValAssign::LocInfo &LocInfo,
826 ISD::ArgFlagsTy &ArgFlags,
828 if (!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
830 if (LocVT == MVT::v2f64 &&
831 !f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
833 return true; // we handled it
836 static bool f64RetAssign(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
837 CCValAssign::LocInfo &LocInfo, CCState &State) {
838 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
839 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
841 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
843 return false; // we didn't handle it
846 for (i = 0; i < 2; ++i)
847 if (HiRegList[i] == Reg)
850 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
851 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
856 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
857 CCValAssign::LocInfo &LocInfo,
858 ISD::ArgFlagsTy &ArgFlags,
860 if (!f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
862 if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
864 return true; // we handled it
867 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
868 CCValAssign::LocInfo &LocInfo,
869 ISD::ArgFlagsTy &ArgFlags,
871 return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags,
875 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
876 /// given CallingConvention value.
877 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
879 bool isVarArg) const {
882 llvm_unreachable("Unsupported calling convention");
884 case CallingConv::Fast:
885 // Use target triple & subtarget features to do actual dispatch.
886 if (Subtarget->isAAPCS_ABI()) {
887 if (Subtarget->hasVFP2() &&
888 FloatABIType == FloatABI::Hard && !isVarArg)
889 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
891 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
893 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
894 case CallingConv::ARM_AAPCS_VFP:
895 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
896 case CallingConv::ARM_AAPCS:
897 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
898 case CallingConv::ARM_APCS:
899 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
903 /// LowerCallResult - Lower the result values of a call into the
904 /// appropriate copies out of appropriate physical registers.
906 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
907 CallingConv::ID CallConv, bool isVarArg,
908 const SmallVectorImpl<ISD::InputArg> &Ins,
909 DebugLoc dl, SelectionDAG &DAG,
910 SmallVectorImpl<SDValue> &InVals) const {
912 // Assign locations to each value returned by this call.
913 SmallVector<CCValAssign, 16> RVLocs;
914 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
915 RVLocs, *DAG.getContext());
916 CCInfo.AnalyzeCallResult(Ins,
917 CCAssignFnForNode(CallConv, /* Return*/ true,
920 // Copy all of the result registers out of their specified physreg.
921 for (unsigned i = 0; i != RVLocs.size(); ++i) {
922 CCValAssign VA = RVLocs[i];
925 if (VA.needsCustom()) {
926 // Handle f64 or half of a v2f64.
927 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
929 Chain = Lo.getValue(1);
930 InFlag = Lo.getValue(2);
931 VA = RVLocs[++i]; // skip ahead to next loc
932 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
934 Chain = Hi.getValue(1);
935 InFlag = Hi.getValue(2);
936 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
938 if (VA.getLocVT() == MVT::v2f64) {
939 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
940 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
941 DAG.getConstant(0, MVT::i32));
943 VA = RVLocs[++i]; // skip ahead to next loc
944 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
945 Chain = Lo.getValue(1);
946 InFlag = Lo.getValue(2);
947 VA = RVLocs[++i]; // skip ahead to next loc
948 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
949 Chain = Hi.getValue(1);
950 InFlag = Hi.getValue(2);
951 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
952 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
953 DAG.getConstant(1, MVT::i32));
956 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
958 Chain = Val.getValue(1);
959 InFlag = Val.getValue(2);
962 switch (VA.getLocInfo()) {
963 default: llvm_unreachable("Unknown loc info!");
964 case CCValAssign::Full: break;
965 case CCValAssign::BCvt:
966 Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val);
970 InVals.push_back(Val);
976 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
977 /// by "Src" to address "Dst" of size "Size". Alignment information is
978 /// specified by the specific parameter attribute. The copy will be passed as
979 /// a byval function parameter.
980 /// Sometimes what we are copying is the end of a larger object, the part that
981 /// does not fit in registers.
983 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
984 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
986 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
987 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
988 /*isVolatile=*/false, /*AlwaysInline=*/false,
992 /// LowerMemOpCallTo - Store the argument to the stack.
994 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
995 SDValue StackPtr, SDValue Arg,
996 DebugLoc dl, SelectionDAG &DAG,
997 const CCValAssign &VA,
998 ISD::ArgFlagsTy Flags) const {
999 unsigned LocMemOffset = VA.getLocMemOffset();
1000 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1001 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1002 if (Flags.isByVal()) {
1003 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1005 return DAG.getStore(Chain, dl, Arg, PtrOff,
1006 PseudoSourceValue::getStack(), LocMemOffset,
1010 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
1011 SDValue Chain, SDValue &Arg,
1012 RegsToPassVector &RegsToPass,
1013 CCValAssign &VA, CCValAssign &NextVA,
1015 SmallVector<SDValue, 8> &MemOpChains,
1016 ISD::ArgFlagsTy Flags) const {
1018 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1019 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1020 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
1022 if (NextVA.isRegLoc())
1023 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
1025 assert(NextVA.isMemLoc());
1026 if (StackPtr.getNode() == 0)
1027 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1029 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
1035 /// LowerCall - Lowering a call into a callseq_start <-
1036 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1039 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1040 CallingConv::ID CallConv, bool isVarArg,
1042 const SmallVectorImpl<ISD::OutputArg> &Outs,
1043 const SmallVectorImpl<SDValue> &OutVals,
1044 const SmallVectorImpl<ISD::InputArg> &Ins,
1045 DebugLoc dl, SelectionDAG &DAG,
1046 SmallVectorImpl<SDValue> &InVals) const {
1047 MachineFunction &MF = DAG.getMachineFunction();
1048 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1049 bool IsSibCall = false;
1050 // Temporarily disable tail calls so things don't break.
1051 if (!EnableARMTailCalls)
1054 // Check if it's really possible to do a tail call.
1055 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1056 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1057 Outs, OutVals, Ins, DAG);
1058 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1059 // detected sibcalls.
1066 // Analyze operands of the call, assigning locations to each operand.
1067 SmallVector<CCValAssign, 16> ArgLocs;
1068 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1070 CCInfo.AnalyzeCallOperands(Outs,
1071 CCAssignFnForNode(CallConv, /* Return*/ false,
1074 // Get a count of how many bytes are to be pushed on the stack.
1075 unsigned NumBytes = CCInfo.getNextStackOffset();
1077 // For tail calls, memory operands are available in our caller's stack.
1081 // Adjust the stack pointer for the new arguments...
1082 // These operations are automatically eliminated by the prolog/epilog pass
1084 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1086 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1088 RegsToPassVector RegsToPass;
1089 SmallVector<SDValue, 8> MemOpChains;
1091 // Walk the register/memloc assignments, inserting copies/loads. In the case
1092 // of tail call optimization, arguments are handled later.
1093 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1095 ++i, ++realArgIdx) {
1096 CCValAssign &VA = ArgLocs[i];
1097 SDValue Arg = OutVals[realArgIdx];
1098 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1100 // Promote the value if needed.
1101 switch (VA.getLocInfo()) {
1102 default: llvm_unreachable("Unknown loc info!");
1103 case CCValAssign::Full: break;
1104 case CCValAssign::SExt:
1105 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1107 case CCValAssign::ZExt:
1108 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1110 case CCValAssign::AExt:
1111 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1113 case CCValAssign::BCvt:
1114 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1118 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1119 if (VA.needsCustom()) {
1120 if (VA.getLocVT() == MVT::v2f64) {
1121 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1122 DAG.getConstant(0, MVT::i32));
1123 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1124 DAG.getConstant(1, MVT::i32));
1126 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1127 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1129 VA = ArgLocs[++i]; // skip ahead to next loc
1130 if (VA.isRegLoc()) {
1131 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1132 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1134 assert(VA.isMemLoc());
1136 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1137 dl, DAG, VA, Flags));
1140 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1141 StackPtr, MemOpChains, Flags);
1143 } else if (VA.isRegLoc()) {
1144 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1145 } else if (!IsSibCall) {
1146 assert(VA.isMemLoc());
1148 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1149 dl, DAG, VA, Flags));
1153 if (!MemOpChains.empty())
1154 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1155 &MemOpChains[0], MemOpChains.size());
1157 // Build a sequence of copy-to-reg nodes chained together with token chain
1158 // and flag operands which copy the outgoing args into the appropriate regs.
1160 // Tail call byval lowering might overwrite argument registers so in case of
1161 // tail call optimization the copies to registers are lowered later.
1163 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1164 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1165 RegsToPass[i].second, InFlag);
1166 InFlag = Chain.getValue(1);
1169 // For tail calls lower the arguments to the 'real' stack slot.
1171 // Force all the incoming stack arguments to be loaded from the stack
1172 // before any new outgoing arguments are stored to the stack, because the
1173 // outgoing stack slots may alias the incoming argument stack slots, and
1174 // the alias isn't otherwise explicit. This is slightly more conservative
1175 // than necessary, because it means that each store effectively depends
1176 // on every argument instead of just those arguments it would clobber.
1178 // Do not flag preceeding copytoreg stuff together with the following stuff.
1180 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1181 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1182 RegsToPass[i].second, InFlag);
1183 InFlag = Chain.getValue(1);
1188 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1189 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1190 // node so that legalize doesn't hack it.
1191 bool isDirect = false;
1192 bool isARMFunc = false;
1193 bool isLocalARMFunc = false;
1194 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1196 if (EnableARMLongCalls) {
1197 assert (getTargetMachine().getRelocationModel() == Reloc::Static
1198 && "long-calls with non-static relocation model!");
1199 // Handle a global address or an external symbol. If it's not one of
1200 // those, the target's already in a register, so we don't need to do
1202 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1203 const GlobalValue *GV = G->getGlobal();
1204 // Create a constant pool entry for the callee address
1205 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1206 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1209 // Get the address of the callee into a register
1210 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1211 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1212 Callee = DAG.getLoad(getPointerTy(), dl,
1213 DAG.getEntryNode(), CPAddr,
1214 PseudoSourceValue::getConstantPool(), 0,
1216 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1217 const char *Sym = S->getSymbol();
1219 // Create a constant pool entry for the callee address
1220 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1221 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1222 Sym, ARMPCLabelIndex, 0);
1223 // Get the address of the callee into a register
1224 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1225 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1226 Callee = DAG.getLoad(getPointerTy(), dl,
1227 DAG.getEntryNode(), CPAddr,
1228 PseudoSourceValue::getConstantPool(), 0,
1231 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1232 const GlobalValue *GV = G->getGlobal();
1234 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1235 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
1236 getTargetMachine().getRelocationModel() != Reloc::Static;
1237 isARMFunc = !Subtarget->isThumb() || isStub;
1238 // ARM call to a local ARM function is predicable.
1239 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
1240 // tBX takes a register source operand.
1241 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1242 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1243 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1246 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1247 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1248 Callee = DAG.getLoad(getPointerTy(), dl,
1249 DAG.getEntryNode(), CPAddr,
1250 PseudoSourceValue::getConstantPool(), 0,
1252 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1253 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1254 getPointerTy(), Callee, PICLabel);
1256 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy());
1257 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1259 bool isStub = Subtarget->isTargetDarwin() &&
1260 getTargetMachine().getRelocationModel() != Reloc::Static;
1261 isARMFunc = !Subtarget->isThumb() || isStub;
1262 // tBX takes a register source operand.
1263 const char *Sym = S->getSymbol();
1264 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1265 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1266 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1267 Sym, ARMPCLabelIndex, 4);
1268 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1269 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1270 Callee = DAG.getLoad(getPointerTy(), dl,
1271 DAG.getEntryNode(), CPAddr,
1272 PseudoSourceValue::getConstantPool(), 0,
1274 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1275 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1276 getPointerTy(), Callee, PICLabel);
1278 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
1281 // FIXME: handle tail calls differently.
1283 if (Subtarget->isThumb()) {
1284 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1285 CallOpc = ARMISD::CALL_NOLINK;
1287 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1289 CallOpc = (isDirect || Subtarget->hasV5TOps())
1290 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
1291 : ARMISD::CALL_NOLINK;
1294 std::vector<SDValue> Ops;
1295 Ops.push_back(Chain);
1296 Ops.push_back(Callee);
1298 // Add argument registers to the end of the list so that they are known live
1300 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1301 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1302 RegsToPass[i].second.getValueType()));
1304 if (InFlag.getNode())
1305 Ops.push_back(InFlag);
1307 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1309 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
1311 // Returns a chain and a flag for retval copy to use.
1312 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
1313 InFlag = Chain.getValue(1);
1315 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1316 DAG.getIntPtrConstant(0, true), InFlag);
1318 InFlag = Chain.getValue(1);
1320 // Handle result values, copying them out of physregs into vregs that we
1322 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1326 /// MatchingStackOffset - Return true if the given stack call argument is
1327 /// already available in the same position (relatively) of the caller's
1328 /// incoming argument stack.
1330 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1331 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1332 const ARMInstrInfo *TII) {
1333 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
1335 if (Arg.getOpcode() == ISD::CopyFromReg) {
1336 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
1337 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR))
1339 MachineInstr *Def = MRI->getVRegDef(VR);
1342 if (!Flags.isByVal()) {
1343 if (!TII->isLoadFromStackSlot(Def, FI))
1348 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
1349 if (Flags.isByVal())
1350 // ByVal argument is passed in as a pointer but it's now being
1351 // dereferenced. e.g.
1352 // define @foo(%struct.X* %A) {
1353 // tail call @bar(%struct.X* byval %A)
1356 SDValue Ptr = Ld->getBasePtr();
1357 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
1360 FI = FINode->getIndex();
1364 assert(FI != INT_MAX);
1365 if (!MFI->isFixedObjectIndex(FI))
1367 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
1370 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1371 /// for tail call optimization. Targets which want to do tail call
1372 /// optimization should implement this function.
1374 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1375 CallingConv::ID CalleeCC,
1377 bool isCalleeStructRet,
1378 bool isCallerStructRet,
1379 const SmallVectorImpl<ISD::OutputArg> &Outs,
1380 const SmallVectorImpl<SDValue> &OutVals,
1381 const SmallVectorImpl<ISD::InputArg> &Ins,
1382 SelectionDAG& DAG) const {
1383 const Function *CallerF = DAG.getMachineFunction().getFunction();
1384 CallingConv::ID CallerCC = CallerF->getCallingConv();
1385 bool CCMatch = CallerCC == CalleeCC;
1387 // Look for obvious safe cases to perform tail call optimization that do not
1388 // require ABI changes. This is what gcc calls sibcall.
1390 // Do not sibcall optimize vararg calls unless the call site is not passing
1392 if (isVarArg && !Outs.empty())
1395 // Also avoid sibcall optimization if either caller or callee uses struct
1396 // return semantics.
1397 if (isCalleeStructRet || isCallerStructRet)
1400 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
1401 // emitEpilogue is not ready for them.
1402 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
1403 // LR. This means if we need to reload LR, it takes an extra instructions,
1404 // which outweighs the value of the tail call; but here we don't know yet
1405 // whether LR is going to be used. Probably the right approach is to
1406 // generate the tail call here and turn it back into CALL/RET in
1407 // emitEpilogue if LR is used.
1408 if (Subtarget->isThumb1Only())
1411 // For the moment, we can only do this to functions defined in this
1412 // compilation, or to indirect calls. A Thumb B to an ARM function,
1413 // or vice versa, is not easily fixed up in the linker unlike BL.
1414 // (We could do this by loading the address of the callee into a register;
1415 // that is an extra instruction over the direct call and burns a register
1416 // as well, so is not likely to be a win.)
1418 // It might be safe to remove this restriction on non-Darwin.
1420 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
1421 // but we need to make sure there are enough registers; the only valid
1422 // registers are the 4 used for parameters. We don't currently do this
1424 if (isa<ExternalSymbolSDNode>(Callee))
1427 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1428 const GlobalValue *GV = G->getGlobal();
1429 if (GV->isDeclaration() || GV->isWeakForLinker())
1433 // If the calling conventions do not match, then we'd better make sure the
1434 // results are returned in the same way as what the caller expects.
1436 SmallVector<CCValAssign, 16> RVLocs1;
1437 CCState CCInfo1(CalleeCC, false, getTargetMachine(),
1438 RVLocs1, *DAG.getContext());
1439 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
1441 SmallVector<CCValAssign, 16> RVLocs2;
1442 CCState CCInfo2(CallerCC, false, getTargetMachine(),
1443 RVLocs2, *DAG.getContext());
1444 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
1446 if (RVLocs1.size() != RVLocs2.size())
1448 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
1449 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
1451 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
1453 if (RVLocs1[i].isRegLoc()) {
1454 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
1457 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
1463 // If the callee takes no arguments then go on to check the results of the
1465 if (!Outs.empty()) {
1466 // Check if stack adjustment is needed. For now, do not do this if any
1467 // argument is passed on the stack.
1468 SmallVector<CCValAssign, 16> ArgLocs;
1469 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
1470 ArgLocs, *DAG.getContext());
1471 CCInfo.AnalyzeCallOperands(Outs,
1472 CCAssignFnForNode(CalleeCC, false, isVarArg));
1473 if (CCInfo.getNextStackOffset()) {
1474 MachineFunction &MF = DAG.getMachineFunction();
1476 // Check if the arguments are already laid out in the right way as
1477 // the caller's fixed stack objects.
1478 MachineFrameInfo *MFI = MF.getFrameInfo();
1479 const MachineRegisterInfo *MRI = &MF.getRegInfo();
1480 const ARMInstrInfo *TII =
1481 ((ARMTargetMachine&)getTargetMachine()).getInstrInfo();
1482 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1484 ++i, ++realArgIdx) {
1485 CCValAssign &VA = ArgLocs[i];
1486 EVT RegVT = VA.getLocVT();
1487 SDValue Arg = OutVals[realArgIdx];
1488 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1489 if (VA.getLocInfo() == CCValAssign::Indirect)
1491 if (VA.needsCustom()) {
1492 // f64 and vector types are split into multiple registers or
1493 // register/stack-slot combinations. The types will not match
1494 // the registers; give up on memory f64 refs until we figure
1495 // out what to do about this.
1498 if (!ArgLocs[++i].isRegLoc())
1500 if (RegVT == MVT::v2f64) {
1501 if (!ArgLocs[++i].isRegLoc())
1503 if (!ArgLocs[++i].isRegLoc())
1506 } else if (!VA.isRegLoc()) {
1507 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
1519 ARMTargetLowering::LowerReturn(SDValue Chain,
1520 CallingConv::ID CallConv, bool isVarArg,
1521 const SmallVectorImpl<ISD::OutputArg> &Outs,
1522 const SmallVectorImpl<SDValue> &OutVals,
1523 DebugLoc dl, SelectionDAG &DAG) const {
1525 // CCValAssign - represent the assignment of the return value to a location.
1526 SmallVector<CCValAssign, 16> RVLocs;
1528 // CCState - Info about the registers and stack slots.
1529 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
1532 // Analyze outgoing return values.
1533 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1536 // If this is the first return lowered for this function, add
1537 // the regs to the liveout set for the function.
1538 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1539 for (unsigned i = 0; i != RVLocs.size(); ++i)
1540 if (RVLocs[i].isRegLoc())
1541 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1546 // Copy the result values into the output registers.
1547 for (unsigned i = 0, realRVLocIdx = 0;
1549 ++i, ++realRVLocIdx) {
1550 CCValAssign &VA = RVLocs[i];
1551 assert(VA.isRegLoc() && "Can only return in registers!");
1553 SDValue Arg = OutVals[realRVLocIdx];
1555 switch (VA.getLocInfo()) {
1556 default: llvm_unreachable("Unknown loc info!");
1557 case CCValAssign::Full: break;
1558 case CCValAssign::BCvt:
1559 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1563 if (VA.needsCustom()) {
1564 if (VA.getLocVT() == MVT::v2f64) {
1565 // Extract the first half and return it in two registers.
1566 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1567 DAG.getConstant(0, MVT::i32));
1568 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
1569 DAG.getVTList(MVT::i32, MVT::i32), Half);
1571 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1572 Flag = Chain.getValue(1);
1573 VA = RVLocs[++i]; // skip ahead to next loc
1574 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1575 HalfGPRs.getValue(1), Flag);
1576 Flag = Chain.getValue(1);
1577 VA = RVLocs[++i]; // skip ahead to next loc
1579 // Extract the 2nd half and fall through to handle it as an f64 value.
1580 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1581 DAG.getConstant(1, MVT::i32));
1583 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1585 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1586 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1587 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1588 Flag = Chain.getValue(1);
1589 VA = RVLocs[++i]; // skip ahead to next loc
1590 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1593 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1595 // Guarantee that all emitted copies are
1596 // stuck together, avoiding something bad.
1597 Flag = Chain.getValue(1);
1602 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1604 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1609 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1610 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1611 // one of the above mentioned nodes. It has to be wrapped because otherwise
1612 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1613 // be used to form addressing mode. These wrapped nodes will be selected
1615 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1616 EVT PtrVT = Op.getValueType();
1617 // FIXME there is no actual debug info here
1618 DebugLoc dl = Op.getDebugLoc();
1619 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1621 if (CP->isMachineConstantPoolEntry())
1622 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1623 CP->getAlignment());
1625 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1626 CP->getAlignment());
1627 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1630 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
1631 SelectionDAG &DAG) const {
1632 MachineFunction &MF = DAG.getMachineFunction();
1633 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1634 unsigned ARMPCLabelIndex = 0;
1635 DebugLoc DL = Op.getDebugLoc();
1636 EVT PtrVT = getPointerTy();
1637 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1638 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1640 if (RelocM == Reloc::Static) {
1641 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
1643 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1644 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1645 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(BA, ARMPCLabelIndex,
1646 ARMCP::CPBlockAddress,
1648 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1650 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
1651 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
1652 PseudoSourceValue::getConstantPool(), 0,
1654 if (RelocM == Reloc::Static)
1656 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1657 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
1660 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
1662 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1663 SelectionDAG &DAG) const {
1664 DebugLoc dl = GA->getDebugLoc();
1665 EVT PtrVT = getPointerTy();
1666 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1667 MachineFunction &MF = DAG.getMachineFunction();
1668 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1669 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1670 ARMConstantPoolValue *CPV =
1671 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1672 ARMCP::CPValue, PCAdj, "tlsgd", true);
1673 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1674 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
1675 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
1676 PseudoSourceValue::getConstantPool(), 0,
1678 SDValue Chain = Argument.getValue(1);
1680 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1681 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
1683 // call __tls_get_addr.
1686 Entry.Node = Argument;
1687 Entry.Ty = (const Type *) Type::getInt32Ty(*DAG.getContext());
1688 Args.push_back(Entry);
1689 // FIXME: is there useful debug info available here?
1690 std::pair<SDValue, SDValue> CallResult =
1691 LowerCallTo(Chain, (const Type *) Type::getInt32Ty(*DAG.getContext()),
1692 false, false, false, false,
1693 0, CallingConv::C, false, /*isReturnValueUsed=*/true,
1694 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
1695 return CallResult.first;
1698 // Lower ISD::GlobalTLSAddress using the "initial exec" or
1699 // "local exec" model.
1701 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
1702 SelectionDAG &DAG) const {
1703 const GlobalValue *GV = GA->getGlobal();
1704 DebugLoc dl = GA->getDebugLoc();
1706 SDValue Chain = DAG.getEntryNode();
1707 EVT PtrVT = getPointerTy();
1708 // Get the Thread Pointer
1709 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1711 if (GV->isDeclaration()) {
1712 MachineFunction &MF = DAG.getMachineFunction();
1713 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1714 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1715 // Initial exec model.
1716 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1717 ARMConstantPoolValue *CPV =
1718 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1719 ARMCP::CPValue, PCAdj, "gottpoff", true);
1720 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1721 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1722 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1723 PseudoSourceValue::getConstantPool(), 0,
1725 Chain = Offset.getValue(1);
1727 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1728 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
1730 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1731 PseudoSourceValue::getConstantPool(), 0,
1735 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, "tpoff");
1736 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1737 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1738 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1739 PseudoSourceValue::getConstantPool(), 0,
1743 // The address of the thread local variable is the add of the thread
1744 // pointer with the offset of the variable.
1745 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
1749 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
1750 // TODO: implement the "local dynamic" model
1751 assert(Subtarget->isTargetELF() &&
1752 "TLS not implemented for non-ELF targets");
1753 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1754 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
1755 // otherwise use the "Local Exec" TLS Model
1756 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
1757 return LowerToTLSGeneralDynamicModel(GA, DAG);
1759 return LowerToTLSExecModels(GA, DAG);
1762 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
1763 SelectionDAG &DAG) const {
1764 EVT PtrVT = getPointerTy();
1765 DebugLoc dl = Op.getDebugLoc();
1766 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1767 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1768 if (RelocM == Reloc::PIC_) {
1769 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
1770 ARMConstantPoolValue *CPV =
1771 new ARMConstantPoolValue(GV, UseGOTOFF ? "GOTOFF" : "GOT");
1772 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1773 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1774 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1776 PseudoSourceValue::getConstantPool(), 0,
1778 SDValue Chain = Result.getValue(1);
1779 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1780 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
1782 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
1783 PseudoSourceValue::getGOT(), 0,
1787 // If we have T2 ops, we can materialize the address directly via movt/movw
1788 // pair. This is always cheaper.
1789 if (Subtarget->useMovt()) {
1790 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
1791 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
1793 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1794 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1795 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1796 PseudoSourceValue::getConstantPool(), 0,
1802 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
1803 SelectionDAG &DAG) const {
1804 MachineFunction &MF = DAG.getMachineFunction();
1805 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1806 unsigned ARMPCLabelIndex = 0;
1807 EVT PtrVT = getPointerTy();
1808 DebugLoc dl = Op.getDebugLoc();
1809 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1810 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1812 if (RelocM == Reloc::Static)
1813 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1815 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1816 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8);
1817 ARMConstantPoolValue *CPV =
1818 new ARMConstantPoolValue(GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj);
1819 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1821 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1823 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1824 PseudoSourceValue::getConstantPool(), 0,
1826 SDValue Chain = Result.getValue(1);
1828 if (RelocM == Reloc::PIC_) {
1829 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1830 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1833 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
1834 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
1835 PseudoSourceValue::getGOT(), 0,
1841 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
1842 SelectionDAG &DAG) const {
1843 assert(Subtarget->isTargetELF() &&
1844 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
1845 MachineFunction &MF = DAG.getMachineFunction();
1846 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1847 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1848 EVT PtrVT = getPointerTy();
1849 DebugLoc dl = Op.getDebugLoc();
1850 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1851 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1852 "_GLOBAL_OFFSET_TABLE_",
1853 ARMPCLabelIndex, PCAdj);
1854 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1855 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1856 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1857 PseudoSourceValue::getConstantPool(), 0,
1859 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1860 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1864 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
1865 DebugLoc dl = Op.getDebugLoc();
1866 SDValue Val = DAG.getConstant(0, MVT::i32);
1867 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(0),
1868 Op.getOperand(1), Val);
1872 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
1873 DebugLoc dl = Op.getDebugLoc();
1874 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
1875 Op.getOperand(1), DAG.getConstant(0, MVT::i32));
1879 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
1880 const ARMSubtarget *Subtarget) const {
1881 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1882 DebugLoc dl = Op.getDebugLoc();
1884 default: return SDValue(); // Don't custom lower most intrinsics.
1885 case Intrinsic::arm_thread_pointer: {
1886 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1887 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1889 case Intrinsic::eh_sjlj_lsda: {
1890 MachineFunction &MF = DAG.getMachineFunction();
1891 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1892 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1893 EVT PtrVT = getPointerTy();
1894 DebugLoc dl = Op.getDebugLoc();
1895 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1897 unsigned PCAdj = (RelocM != Reloc::PIC_)
1898 ? 0 : (Subtarget->isThumb() ? 4 : 8);
1899 ARMConstantPoolValue *CPV =
1900 new ARMConstantPoolValue(MF.getFunction(), ARMPCLabelIndex,
1901 ARMCP::CPLSDA, PCAdj);
1902 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1903 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1905 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1906 PseudoSourceValue::getConstantPool(), 0,
1909 if (RelocM == Reloc::PIC_) {
1910 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1911 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1918 static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG,
1919 const ARMSubtarget *Subtarget) {
1920 DebugLoc dl = Op.getDebugLoc();
1921 SDValue Op5 = Op.getOperand(5);
1922 unsigned isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue();
1923 // v6 and v7 can both handle barriers directly, but need handled a bit
1924 // differently. Thumb1 and pre-v6 ARM mode use a libcall instead and should
1926 unsigned Opc = isDeviceBarrier ? ARMISD::SYNCBARRIER : ARMISD::MEMBARRIER;
1927 if (Subtarget->hasV7Ops())
1928 return DAG.getNode(Opc, dl, MVT::Other, Op.getOperand(0));
1929 else if (Subtarget->hasV6Ops() && !Subtarget->isThumb1Only())
1930 return DAG.getNode(Opc, dl, MVT::Other, Op.getOperand(0),
1931 DAG.getConstant(0, MVT::i32));
1932 assert(0 && "Unexpected ISD::MEMBARRIER encountered. Should be libcall!");
1936 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
1937 MachineFunction &MF = DAG.getMachineFunction();
1938 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
1940 // vastart just stores the address of the VarArgsFrameIndex slot into the
1941 // memory location argument.
1942 DebugLoc dl = Op.getDebugLoc();
1943 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1944 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1945 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1946 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0,
1951 ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
1952 SelectionDAG &DAG) const {
1953 SDNode *Node = Op.getNode();
1954 DebugLoc dl = Node->getDebugLoc();
1955 EVT VT = Node->getValueType(0);
1956 SDValue Chain = Op.getOperand(0);
1957 SDValue Size = Op.getOperand(1);
1958 SDValue Align = Op.getOperand(2);
1960 // Chain the dynamic stack allocation so that it doesn't modify the stack
1961 // pointer when other instructions are using the stack.
1962 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1964 unsigned AlignVal = cast<ConstantSDNode>(Align)->getZExtValue();
1965 unsigned StackAlign = getTargetMachine().getFrameInfo()->getStackAlignment();
1966 if (AlignVal > StackAlign)
1967 // Do this now since selection pass cannot introduce new target
1968 // independent node.
1969 Align = DAG.getConstant(-(uint64_t)AlignVal, VT);
1971 // In Thumb1 mode, there isn't a "sub r, sp, r" instruction, we will end up
1972 // using a "add r, sp, r" instead. Negate the size now so we don't have to
1973 // do even more horrible hack later.
1974 MachineFunction &MF = DAG.getMachineFunction();
1975 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1976 if (AFI->isThumb1OnlyFunction()) {
1978 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Size);
1980 uint32_t Val = C->getZExtValue();
1981 if (Val <= 508 && ((Val & 3) == 0))
1985 Size = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, VT), Size);
1988 SDVTList VTList = DAG.getVTList(VT, MVT::Other);
1989 SDValue Ops1[] = { Chain, Size, Align };
1990 SDValue Res = DAG.getNode(ARMISD::DYN_ALLOC, dl, VTList, Ops1, 3);
1991 Chain = Res.getValue(1);
1992 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1993 DAG.getIntPtrConstant(0, true), SDValue());
1994 SDValue Ops2[] = { Res, Chain };
1995 return DAG.getMergeValues(Ops2, 2, dl);
1999 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
2000 SDValue &Root, SelectionDAG &DAG,
2001 DebugLoc dl) const {
2002 MachineFunction &MF = DAG.getMachineFunction();
2003 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2005 TargetRegisterClass *RC;
2006 if (AFI->isThumb1OnlyFunction())
2007 RC = ARM::tGPRRegisterClass;
2009 RC = ARM::GPRRegisterClass;
2011 // Transform the arguments stored in physical registers into virtual ones.
2012 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2013 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2016 if (NextVA.isMemLoc()) {
2017 MachineFrameInfo *MFI = MF.getFrameInfo();
2018 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
2020 // Create load node to retrieve arguments from the stack.
2021 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2022 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
2023 PseudoSourceValue::getFixedStack(FI), 0,
2026 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2027 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2030 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
2034 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
2035 CallingConv::ID CallConv, bool isVarArg,
2036 const SmallVectorImpl<ISD::InputArg>
2038 DebugLoc dl, SelectionDAG &DAG,
2039 SmallVectorImpl<SDValue> &InVals)
2042 MachineFunction &MF = DAG.getMachineFunction();
2043 MachineFrameInfo *MFI = MF.getFrameInfo();
2045 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2047 // Assign locations to all of the incoming arguments.
2048 SmallVector<CCValAssign, 16> ArgLocs;
2049 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
2051 CCInfo.AnalyzeFormalArguments(Ins,
2052 CCAssignFnForNode(CallConv, /* Return*/ false,
2055 SmallVector<SDValue, 16> ArgValues;
2057 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2058 CCValAssign &VA = ArgLocs[i];
2060 // Arguments stored in registers.
2061 if (VA.isRegLoc()) {
2062 EVT RegVT = VA.getLocVT();
2065 if (VA.needsCustom()) {
2066 // f64 and vector types are split up into multiple registers or
2067 // combinations of registers and stack slots.
2068 if (VA.getLocVT() == MVT::v2f64) {
2069 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
2071 VA = ArgLocs[++i]; // skip ahead to next loc
2073 if (VA.isMemLoc()) {
2074 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
2075 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2076 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
2077 PseudoSourceValue::getFixedStack(FI), 0,
2080 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
2083 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2084 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2085 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
2086 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2087 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
2089 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
2092 TargetRegisterClass *RC;
2094 if (RegVT == MVT::f32)
2095 RC = ARM::SPRRegisterClass;
2096 else if (RegVT == MVT::f64)
2097 RC = ARM::DPRRegisterClass;
2098 else if (RegVT == MVT::v2f64)
2099 RC = ARM::QPRRegisterClass;
2100 else if (RegVT == MVT::i32)
2101 RC = (AFI->isThumb1OnlyFunction() ?
2102 ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
2104 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2106 // Transform the arguments in physical registers into virtual ones.
2107 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2108 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2111 // If this is an 8 or 16-bit value, it is really passed promoted
2112 // to 32 bits. Insert an assert[sz]ext to capture this, then
2113 // truncate to the right size.
2114 switch (VA.getLocInfo()) {
2115 default: llvm_unreachable("Unknown loc info!");
2116 case CCValAssign::Full: break;
2117 case CCValAssign::BCvt:
2118 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
2120 case CCValAssign::SExt:
2121 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2122 DAG.getValueType(VA.getValVT()));
2123 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2125 case CCValAssign::ZExt:
2126 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2127 DAG.getValueType(VA.getValVT()));
2128 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2132 InVals.push_back(ArgValue);
2134 } else { // VA.isRegLoc()
2137 assert(VA.isMemLoc());
2138 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
2140 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
2141 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(), true);
2143 // Create load nodes to retrieve arguments from the stack.
2144 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2145 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2146 PseudoSourceValue::getFixedStack(FI), 0,
2153 static const unsigned GPRArgRegs[] = {
2154 ARM::R0, ARM::R1, ARM::R2, ARM::R3
2157 unsigned NumGPRs = CCInfo.getFirstUnallocated
2158 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
2160 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
2161 unsigned VARegSize = (4 - NumGPRs) * 4;
2162 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
2163 unsigned ArgOffset = CCInfo.getNextStackOffset();
2164 if (VARegSaveSize) {
2165 // If this function is vararg, store any remaining integer argument regs
2166 // to their spots on the stack so that they may be loaded by deferencing
2167 // the result of va_next.
2168 AFI->setVarArgsRegSaveSize(VARegSaveSize);
2169 AFI->setVarArgsFrameIndex(
2170 MFI->CreateFixedObject(VARegSaveSize,
2171 ArgOffset + VARegSaveSize - VARegSize,
2173 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(),
2176 SmallVector<SDValue, 4> MemOps;
2177 for (; NumGPRs < 4; ++NumGPRs) {
2178 TargetRegisterClass *RC;
2179 if (AFI->isThumb1OnlyFunction())
2180 RC = ARM::tGPRRegisterClass;
2182 RC = ARM::GPRRegisterClass;
2184 unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
2185 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2187 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2188 PseudoSourceValue::getFixedStack(AFI->getVarArgsFrameIndex()),
2189 0, false, false, 0);
2190 MemOps.push_back(Store);
2191 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
2192 DAG.getConstant(4, getPointerTy()));
2194 if (!MemOps.empty())
2195 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2196 &MemOps[0], MemOps.size());
2198 // This will point to the next argument passed via stack.
2199 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset, true));
2205 /// isFloatingPointZero - Return true if this is +0.0.
2206 static bool isFloatingPointZero(SDValue Op) {
2207 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
2208 return CFP->getValueAPF().isPosZero();
2209 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
2210 // Maybe this has already been legalized into the constant pool?
2211 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
2212 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
2213 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
2214 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
2215 return CFP->getValueAPF().isPosZero();
2221 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
2222 /// the given operands.
2224 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2225 SDValue &ARMcc, SelectionDAG &DAG,
2226 DebugLoc dl) const {
2227 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
2228 unsigned C = RHSC->getZExtValue();
2229 if (!isLegalICmpImmediate(C)) {
2230 // Constant does not fit, try adjusting it by one?
2235 if (isLegalICmpImmediate(C-1)) {
2236 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
2237 RHS = DAG.getConstant(C-1, MVT::i32);
2242 if (C > 0 && isLegalICmpImmediate(C-1)) {
2243 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
2244 RHS = DAG.getConstant(C-1, MVT::i32);
2249 if (isLegalICmpImmediate(C+1)) {
2250 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
2251 RHS = DAG.getConstant(C+1, MVT::i32);
2256 if (C < 0xffffffff && isLegalICmpImmediate(C+1)) {
2257 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2258 RHS = DAG.getConstant(C+1, MVT::i32);
2265 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2266 ARMISD::NodeType CompareType;
2269 CompareType = ARMISD::CMP;
2274 CompareType = ARMISD::CMPZ;
2277 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2278 return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS);
2281 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
2283 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
2284 DebugLoc dl) const {
2286 if (!isFloatingPointZero(RHS))
2287 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS);
2289 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS);
2290 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp);
2293 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
2294 EVT VT = Op.getValueType();
2295 SDValue LHS = Op.getOperand(0);
2296 SDValue RHS = Op.getOperand(1);
2297 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2298 SDValue TrueVal = Op.getOperand(2);
2299 SDValue FalseVal = Op.getOperand(3);
2300 DebugLoc dl = Op.getDebugLoc();
2302 if (LHS.getValueType() == MVT::i32) {
2304 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2305 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2306 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,Cmp);
2309 ARMCC::CondCodes CondCode, CondCode2;
2310 FPCCToARMCC(CC, CondCode, CondCode2);
2312 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2313 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2314 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2315 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
2317 if (CondCode2 != ARMCC::AL) {
2318 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32);
2319 // FIXME: Needs another CMP because flag can have but one use.
2320 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
2321 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
2322 Result, TrueVal, ARMcc2, CCR, Cmp2);
2327 /// canChangeToInt - Given the fp compare operand, return true if it is suitable
2328 /// to morph to an integer compare sequence.
2329 static bool canChangeToInt(SDValue Op, bool &SeenZero,
2330 const ARMSubtarget *Subtarget) {
2331 SDNode *N = Op.getNode();
2332 if (!N->hasOneUse())
2333 // Otherwise it requires moving the value from fp to integer registers.
2335 if (!N->getNumValues())
2337 EVT VT = Op.getValueType();
2338 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
2339 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
2340 // vmrs are very slow, e.g. cortex-a8.
2343 if (isFloatingPointZero(Op)) {
2347 return ISD::isNormalLoad(N);
2350 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
2351 if (isFloatingPointZero(Op))
2352 return DAG.getConstant(0, MVT::i32);
2354 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
2355 return DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2356 Ld->getChain(), Ld->getBasePtr(),
2357 Ld->getSrcValue(), Ld->getSrcValueOffset(),
2358 Ld->isVolatile(), Ld->isNonTemporal(),
2359 Ld->getAlignment());
2361 llvm_unreachable("Unknown VFP cmp argument!");
2364 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
2365 SDValue &RetVal1, SDValue &RetVal2) {
2366 if (isFloatingPointZero(Op)) {
2367 RetVal1 = DAG.getConstant(0, MVT::i32);
2368 RetVal2 = DAG.getConstant(0, MVT::i32);
2372 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
2373 SDValue Ptr = Ld->getBasePtr();
2374 RetVal1 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2375 Ld->getChain(), Ptr,
2376 Ld->getSrcValue(), Ld->getSrcValueOffset(),
2377 Ld->isVolatile(), Ld->isNonTemporal(),
2378 Ld->getAlignment());
2380 EVT PtrType = Ptr.getValueType();
2381 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
2382 SDValue NewPtr = DAG.getNode(ISD::ADD, Op.getDebugLoc(),
2383 PtrType, Ptr, DAG.getConstant(4, PtrType));
2384 RetVal2 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2385 Ld->getChain(), NewPtr,
2386 Ld->getSrcValue(), Ld->getSrcValueOffset() + 4,
2387 Ld->isVolatile(), Ld->isNonTemporal(),
2392 llvm_unreachable("Unknown VFP cmp argument!");
2395 /// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
2396 /// f32 and even f64 comparisons to integer ones.
2398 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
2399 SDValue Chain = Op.getOperand(0);
2400 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2401 SDValue LHS = Op.getOperand(2);
2402 SDValue RHS = Op.getOperand(3);
2403 SDValue Dest = Op.getOperand(4);
2404 DebugLoc dl = Op.getDebugLoc();
2406 bool SeenZero = false;
2407 if (canChangeToInt(LHS, SeenZero, Subtarget) &&
2408 canChangeToInt(RHS, SeenZero, Subtarget) &&
2409 // If one of the operand is zero, it's safe to ignore the NaN case since
2410 // we only care about equality comparisons.
2411 (SeenZero || (DAG.isKnownNeverNaN(LHS) && DAG.isKnownNeverNaN(RHS)))) {
2412 // If unsafe fp math optimization is enabled and there are no othter uses of
2413 // the CMP operands, and the condition code is EQ oe NE, we can optimize it
2414 // to an integer comparison.
2415 if (CC == ISD::SETOEQ)
2417 else if (CC == ISD::SETUNE)
2421 if (LHS.getValueType() == MVT::f32) {
2422 LHS = bitcastf32Toi32(LHS, DAG);
2423 RHS = bitcastf32Toi32(RHS, DAG);
2424 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2425 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2426 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2427 Chain, Dest, ARMcc, CCR, Cmp);
2432 expandf64Toi32(LHS, DAG, LHS1, LHS2);
2433 expandf64Toi32(RHS, DAG, RHS1, RHS2);
2434 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2435 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2436 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
2437 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
2438 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7);
2444 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2445 SDValue Chain = Op.getOperand(0);
2446 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2447 SDValue LHS = Op.getOperand(2);
2448 SDValue RHS = Op.getOperand(3);
2449 SDValue Dest = Op.getOperand(4);
2450 DebugLoc dl = Op.getDebugLoc();
2452 if (LHS.getValueType() == MVT::i32) {
2454 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2455 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2456 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2457 Chain, Dest, ARMcc, CCR, Cmp);
2460 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
2463 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
2464 CC == ISD::SETNE || CC == ISD::SETUNE)) {
2465 SDValue Result = OptimizeVFPBrcond(Op, DAG);
2466 if (Result.getNode())
2470 ARMCC::CondCodes CondCode, CondCode2;
2471 FPCCToARMCC(CC, CondCode, CondCode2);
2473 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2474 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2475 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2476 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
2477 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
2478 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2479 if (CondCode2 != ARMCC::AL) {
2480 ARMcc = DAG.getConstant(CondCode2, MVT::i32);
2481 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
2482 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2487 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
2488 SDValue Chain = Op.getOperand(0);
2489 SDValue Table = Op.getOperand(1);
2490 SDValue Index = Op.getOperand(2);
2491 DebugLoc dl = Op.getDebugLoc();
2493 EVT PTy = getPointerTy();
2494 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
2495 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
2496 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
2497 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
2498 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
2499 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
2500 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2501 if (Subtarget->isThumb2()) {
2502 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
2503 // which does another jump to the destination. This also makes it easier
2504 // to translate it to TBB / TBH later.
2505 // FIXME: This might not work if the function is extremely large.
2506 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
2507 Addr, Op.getOperand(2), JTI, UId);
2509 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2510 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
2511 PseudoSourceValue::getJumpTable(), 0,
2513 Chain = Addr.getValue(1);
2514 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
2515 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2517 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
2518 PseudoSourceValue::getJumpTable(), 0, false, false, 0);
2519 Chain = Addr.getValue(1);
2520 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2524 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
2525 DebugLoc dl = Op.getDebugLoc();
2528 switch (Op.getOpcode()) {
2530 assert(0 && "Invalid opcode!");
2531 case ISD::FP_TO_SINT:
2532 Opc = ARMISD::FTOSI;
2534 case ISD::FP_TO_UINT:
2535 Opc = ARMISD::FTOUI;
2538 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
2539 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
2542 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
2543 EVT VT = Op.getValueType();
2544 DebugLoc dl = Op.getDebugLoc();
2547 switch (Op.getOpcode()) {
2549 assert(0 && "Invalid opcode!");
2550 case ISD::SINT_TO_FP:
2551 Opc = ARMISD::SITOF;
2553 case ISD::UINT_TO_FP:
2554 Opc = ARMISD::UITOF;
2558 Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
2559 return DAG.getNode(Opc, dl, VT, Op);
2562 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
2563 // Implement fcopysign with a fabs and a conditional fneg.
2564 SDValue Tmp0 = Op.getOperand(0);
2565 SDValue Tmp1 = Op.getOperand(1);
2566 DebugLoc dl = Op.getDebugLoc();
2567 EVT VT = Op.getValueType();
2568 EVT SrcVT = Tmp1.getValueType();
2569 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
2570 SDValue ARMcc = DAG.getConstant(ARMCC::LT, MVT::i32);
2571 SDValue FP0 = DAG.getConstantFP(0.0, SrcVT);
2572 SDValue Cmp = getVFPCmp(Tmp1, FP0, DAG, dl);
2573 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2574 return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMcc, CCR, Cmp);
2577 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
2578 MachineFunction &MF = DAG.getMachineFunction();
2579 MachineFrameInfo *MFI = MF.getFrameInfo();
2580 MFI->setReturnAddressIsTaken(true);
2582 EVT VT = Op.getValueType();
2583 DebugLoc dl = Op.getDebugLoc();
2584 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2586 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
2587 SDValue Offset = DAG.getConstant(4, MVT::i32);
2588 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
2589 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
2590 NULL, 0, false, false, 0);
2593 // Return LR, which contains the return address. Mark it an implicit live-in.
2594 unsigned Reg = MF.addLiveIn(ARM::LR, ARM::GPRRegisterClass);
2595 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
2598 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2599 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2600 MFI->setFrameAddressIsTaken(true);
2602 EVT VT = Op.getValueType();
2603 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
2604 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2605 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
2606 ? ARM::R7 : ARM::R11;
2607 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
2609 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0,
2614 /// ExpandBIT_CONVERT - If the target supports VFP, this function is called to
2615 /// expand a bit convert where either the source or destination type is i64 to
2616 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
2617 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
2618 /// vectors), since the legalizer won't know what to do with that.
2619 static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
2620 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2621 DebugLoc dl = N->getDebugLoc();
2622 SDValue Op = N->getOperand(0);
2624 // This function is only supposed to be called for i64 types, either as the
2625 // source or destination of the bit convert.
2626 EVT SrcVT = Op.getValueType();
2627 EVT DstVT = N->getValueType(0);
2628 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
2629 "ExpandBIT_CONVERT called for non-i64 type");
2631 // Turn i64->f64 into VMOVDRR.
2632 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
2633 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2634 DAG.getConstant(0, MVT::i32));
2635 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2636 DAG.getConstant(1, MVT::i32));
2637 return DAG.getNode(ISD::BIT_CONVERT, dl, DstVT,
2638 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
2641 // Turn f64->i64 into VMOVRRD.
2642 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
2643 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
2644 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
2645 // Merge the pieces into a single i64 value.
2646 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
2652 /// getZeroVector - Returns a vector of specified type with all zero elements.
2653 /// Zero vectors are used to represent vector negation and in those cases
2654 /// will be implemented with the NEON VNEG instruction. However, VNEG does
2655 /// not support i64 elements, so sometimes the zero vectors will need to be
2656 /// explicitly constructed. Regardless, use a canonical VMOV to create the
2658 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2659 assert(VT.isVector() && "Expected a vector type");
2660 // The canonical modified immediate encoding of a zero vector is....0!
2661 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32);
2662 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
2663 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
2664 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov);
2667 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
2668 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2669 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
2670 SelectionDAG &DAG) const {
2671 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2672 EVT VT = Op.getValueType();
2673 unsigned VTBits = VT.getSizeInBits();
2674 DebugLoc dl = Op.getDebugLoc();
2675 SDValue ShOpLo = Op.getOperand(0);
2676 SDValue ShOpHi = Op.getOperand(1);
2677 SDValue ShAmt = Op.getOperand(2);
2679 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
2681 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
2683 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2684 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2685 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
2686 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2687 DAG.getConstant(VTBits, MVT::i32));
2688 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
2689 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2690 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
2692 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2693 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
2695 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
2696 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
2699 SDValue Ops[2] = { Lo, Hi };
2700 return DAG.getMergeValues(Ops, 2, dl);
2703 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
2704 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2705 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
2706 SelectionDAG &DAG) const {
2707 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2708 EVT VT = Op.getValueType();
2709 unsigned VTBits = VT.getSizeInBits();
2710 DebugLoc dl = Op.getDebugLoc();
2711 SDValue ShOpLo = Op.getOperand(0);
2712 SDValue ShOpHi = Op.getOperand(1);
2713 SDValue ShAmt = Op.getOperand(2);
2716 assert(Op.getOpcode() == ISD::SHL_PARTS);
2717 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2718 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2719 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
2720 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2721 DAG.getConstant(VTBits, MVT::i32));
2722 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
2723 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
2725 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2726 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2727 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
2729 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
2730 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
2733 SDValue Ops[2] = { Lo, Hi };
2734 return DAG.getMergeValues(Ops, 2, dl);
2737 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
2738 const ARMSubtarget *ST) {
2739 EVT VT = N->getValueType(0);
2740 DebugLoc dl = N->getDebugLoc();
2742 if (!ST->hasV6T2Ops())
2745 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
2746 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
2749 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
2750 const ARMSubtarget *ST) {
2751 EVT VT = N->getValueType(0);
2752 DebugLoc dl = N->getDebugLoc();
2754 // Lower vector shifts on NEON to use VSHL.
2755 if (VT.isVector()) {
2756 assert(ST->hasNEON() && "unexpected vector shift");
2758 // Left shifts translate directly to the vshiftu intrinsic.
2759 if (N->getOpcode() == ISD::SHL)
2760 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2761 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
2762 N->getOperand(0), N->getOperand(1));
2764 assert((N->getOpcode() == ISD::SRA ||
2765 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
2767 // NEON uses the same intrinsics for both left and right shifts. For
2768 // right shifts, the shift amounts are negative, so negate the vector of
2770 EVT ShiftVT = N->getOperand(1).getValueType();
2771 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
2772 getZeroVector(ShiftVT, DAG, dl),
2774 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
2775 Intrinsic::arm_neon_vshifts :
2776 Intrinsic::arm_neon_vshiftu);
2777 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2778 DAG.getConstant(vshiftInt, MVT::i32),
2779 N->getOperand(0), NegatedCount);
2782 // We can get here for a node like i32 = ISD::SHL i32, i64
2786 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
2787 "Unknown shift to lower!");
2789 // We only lower SRA, SRL of 1 here, all others use generic lowering.
2790 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
2791 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
2794 // If we are in thumb mode, we don't have RRX.
2795 if (ST->isThumb1Only()) return SDValue();
2797 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
2798 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2799 DAG.getConstant(0, MVT::i32));
2800 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2801 DAG.getConstant(1, MVT::i32));
2803 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
2804 // captures the result into a carry flag.
2805 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
2806 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
2808 // The low part is an ARMISD::RRX operand, which shifts the carry in.
2809 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
2811 // Merge the pieces into a single i64 value.
2812 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
2815 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
2816 SDValue TmpOp0, TmpOp1;
2817 bool Invert = false;
2821 SDValue Op0 = Op.getOperand(0);
2822 SDValue Op1 = Op.getOperand(1);
2823 SDValue CC = Op.getOperand(2);
2824 EVT VT = Op.getValueType();
2825 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
2826 DebugLoc dl = Op.getDebugLoc();
2828 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
2829 switch (SetCCOpcode) {
2830 default: llvm_unreachable("Illegal FP comparison"); break;
2832 case ISD::SETNE: Invert = true; // Fallthrough
2834 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2836 case ISD::SETLT: Swap = true; // Fallthrough
2838 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2840 case ISD::SETLE: Swap = true; // Fallthrough
2842 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2843 case ISD::SETUGE: Swap = true; // Fallthrough
2844 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
2845 case ISD::SETUGT: Swap = true; // Fallthrough
2846 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
2847 case ISD::SETUEQ: Invert = true; // Fallthrough
2849 // Expand this to (OLT | OGT).
2853 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2854 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
2856 case ISD::SETUO: Invert = true; // Fallthrough
2858 // Expand this to (OLT | OGE).
2862 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2863 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
2867 // Integer comparisons.
2868 switch (SetCCOpcode) {
2869 default: llvm_unreachable("Illegal integer comparison"); break;
2870 case ISD::SETNE: Invert = true;
2871 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2872 case ISD::SETLT: Swap = true;
2873 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2874 case ISD::SETLE: Swap = true;
2875 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2876 case ISD::SETULT: Swap = true;
2877 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
2878 case ISD::SETULE: Swap = true;
2879 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
2882 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
2883 if (Opc == ARMISD::VCEQ) {
2886 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
2888 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
2891 // Ignore bitconvert.
2892 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BIT_CONVERT)
2893 AndOp = AndOp.getOperand(0);
2895 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
2897 Op0 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(0));
2898 Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(1));
2905 std::swap(Op0, Op1);
2907 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
2910 Result = DAG.getNOT(dl, Result, VT);
2915 /// isNEONModifiedImm - Check if the specified splat value corresponds to a
2916 /// valid vector constant for a NEON instruction with a "modified immediate"
2917 /// operand (e.g., VMOV). If so, return the encoded value.
2918 static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
2919 unsigned SplatBitSize, SelectionDAG &DAG,
2920 EVT &VT, bool is128Bits, bool isVMOV) {
2921 unsigned OpCmode, Imm;
2923 // SplatBitSize is set to the smallest size that splats the vector, so a
2924 // zero vector will always have SplatBitSize == 8. However, NEON modified
2925 // immediate instructions others than VMOV do not support the 8-bit encoding
2926 // of a zero vector, and the default encoding of zero is supposed to be the
2931 switch (SplatBitSize) {
2935 // Any 1-byte value is OK. Op=0, Cmode=1110.
2936 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
2939 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
2943 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
2944 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
2945 if ((SplatBits & ~0xff) == 0) {
2946 // Value = 0x00nn: Op=x, Cmode=100x.
2951 if ((SplatBits & ~0xff00) == 0) {
2952 // Value = 0xnn00: Op=x, Cmode=101x.
2954 Imm = SplatBits >> 8;
2960 // NEON's 32-bit VMOV supports splat values where:
2961 // * only one byte is nonzero, or
2962 // * the least significant byte is 0xff and the second byte is nonzero, or
2963 // * the least significant 2 bytes are 0xff and the third is nonzero.
2964 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
2965 if ((SplatBits & ~0xff) == 0) {
2966 // Value = 0x000000nn: Op=x, Cmode=000x.
2971 if ((SplatBits & ~0xff00) == 0) {
2972 // Value = 0x0000nn00: Op=x, Cmode=001x.
2974 Imm = SplatBits >> 8;
2977 if ((SplatBits & ~0xff0000) == 0) {
2978 // Value = 0x00nn0000: Op=x, Cmode=010x.
2980 Imm = SplatBits >> 16;
2983 if ((SplatBits & ~0xff000000) == 0) {
2984 // Value = 0xnn000000: Op=x, Cmode=011x.
2986 Imm = SplatBits >> 24;
2990 if ((SplatBits & ~0xffff) == 0 &&
2991 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
2992 // Value = 0x0000nnff: Op=x, Cmode=1100.
2994 Imm = SplatBits >> 8;
2999 if ((SplatBits & ~0xffffff) == 0 &&
3000 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
3001 // Value = 0x00nnffff: Op=x, Cmode=1101.
3003 Imm = SplatBits >> 16;
3004 SplatBits |= 0xffff;
3008 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
3009 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
3010 // VMOV.I32. A (very) minor optimization would be to replicate the value
3011 // and fall through here to test for a valid 64-bit splat. But, then the
3012 // caller would also need to check and handle the change in size.
3018 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
3019 uint64_t BitMask = 0xff;
3021 unsigned ImmMask = 1;
3023 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
3024 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
3027 } else if ((SplatBits & BitMask) != 0) {
3033 // Op=1, Cmode=1110.
3036 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
3041 llvm_unreachable("unexpected size for isNEONModifiedImm");
3045 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
3046 return DAG.getTargetConstant(EncodedVal, MVT::i32);
3049 static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT,
3050 bool &ReverseVEXT, unsigned &Imm) {
3051 unsigned NumElts = VT.getVectorNumElements();
3052 ReverseVEXT = false;
3055 // If this is a VEXT shuffle, the immediate value is the index of the first
3056 // element. The other shuffle indices must be the successive elements after
3058 unsigned ExpectedElt = Imm;
3059 for (unsigned i = 1; i < NumElts; ++i) {
3060 // Increment the expected index. If it wraps around, it may still be
3061 // a VEXT but the source vectors must be swapped.
3063 if (ExpectedElt == NumElts * 2) {
3068 if (ExpectedElt != static_cast<unsigned>(M[i]))
3072 // Adjust the index value if the source operands will be swapped.
3079 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
3080 /// instruction with the specified blocksize. (The order of the elements
3081 /// within each block of the vector is reversed.)
3082 static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT,
3083 unsigned BlockSize) {
3084 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
3085 "Only possible block sizes for VREV are: 16, 32, 64");
3087 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3091 unsigned NumElts = VT.getVectorNumElements();
3092 unsigned BlockElts = M[0] + 1;
3094 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
3097 for (unsigned i = 0; i < NumElts; ++i) {
3098 if ((unsigned) M[i] !=
3099 (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
3106 static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT,
3107 unsigned &WhichResult) {
3108 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3112 unsigned NumElts = VT.getVectorNumElements();
3113 WhichResult = (M[0] == 0 ? 0 : 1);
3114 for (unsigned i = 0; i < NumElts; i += 2) {
3115 if ((unsigned) M[i] != i + WhichResult ||
3116 (unsigned) M[i+1] != i + NumElts + WhichResult)
3122 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
3123 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3124 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
3125 static bool isVTRN_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3126 unsigned &WhichResult) {
3127 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3131 unsigned NumElts = VT.getVectorNumElements();
3132 WhichResult = (M[0] == 0 ? 0 : 1);
3133 for (unsigned i = 0; i < NumElts; i += 2) {
3134 if ((unsigned) M[i] != i + WhichResult ||
3135 (unsigned) M[i+1] != i + WhichResult)
3141 static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT,
3142 unsigned &WhichResult) {
3143 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3147 unsigned NumElts = VT.getVectorNumElements();
3148 WhichResult = (M[0] == 0 ? 0 : 1);
3149 for (unsigned i = 0; i != NumElts; ++i) {
3150 if ((unsigned) M[i] != 2 * i + WhichResult)
3154 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3155 if (VT.is64BitVector() && EltSz == 32)
3161 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
3162 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3163 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
3164 static bool isVUZP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3165 unsigned &WhichResult) {
3166 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3170 unsigned Half = VT.getVectorNumElements() / 2;
3171 WhichResult = (M[0] == 0 ? 0 : 1);
3172 for (unsigned j = 0; j != 2; ++j) {
3173 unsigned Idx = WhichResult;
3174 for (unsigned i = 0; i != Half; ++i) {
3175 if ((unsigned) M[i + j * Half] != Idx)
3181 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3182 if (VT.is64BitVector() && EltSz == 32)
3188 static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT,
3189 unsigned &WhichResult) {
3190 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3194 unsigned NumElts = VT.getVectorNumElements();
3195 WhichResult = (M[0] == 0 ? 0 : 1);
3196 unsigned Idx = WhichResult * NumElts / 2;
3197 for (unsigned i = 0; i != NumElts; i += 2) {
3198 if ((unsigned) M[i] != Idx ||
3199 (unsigned) M[i+1] != Idx + NumElts)
3204 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3205 if (VT.is64BitVector() && EltSz == 32)
3211 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
3212 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3213 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
3214 static bool isVZIP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3215 unsigned &WhichResult) {
3216 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3220 unsigned NumElts = VT.getVectorNumElements();
3221 WhichResult = (M[0] == 0 ? 0 : 1);
3222 unsigned Idx = WhichResult * NumElts / 2;
3223 for (unsigned i = 0; i != NumElts; i += 2) {
3224 if ((unsigned) M[i] != Idx ||
3225 (unsigned) M[i+1] != Idx)
3230 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3231 if (VT.is64BitVector() && EltSz == 32)
3237 // If this is a case we can't handle, return null and let the default
3238 // expansion code take care of it.
3239 static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3240 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
3241 DebugLoc dl = Op.getDebugLoc();
3242 EVT VT = Op.getValueType();
3244 APInt SplatBits, SplatUndef;
3245 unsigned SplatBitSize;
3247 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
3248 if (SplatBitSize <= 64) {
3249 // Check if an immediate VMOV works.
3251 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
3252 SplatUndef.getZExtValue(), SplatBitSize,
3253 DAG, VmovVT, VT.is128BitVector(), true);
3254 if (Val.getNode()) {
3255 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
3256 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov);
3259 // Try an immediate VMVN.
3260 uint64_t NegatedImm = (SplatBits.getZExtValue() ^
3261 ((1LL << SplatBitSize) - 1));
3262 Val = isNEONModifiedImm(NegatedImm,
3263 SplatUndef.getZExtValue(), SplatBitSize,
3264 DAG, VmovVT, VT.is128BitVector(), false);
3265 if (Val.getNode()) {
3266 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
3267 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov);
3272 // Scan through the operands to see if only one value is used.
3273 unsigned NumElts = VT.getVectorNumElements();
3274 bool isOnlyLowElement = true;
3275 bool usesOnlyOneValue = true;
3276 bool isConstant = true;
3278 for (unsigned i = 0; i < NumElts; ++i) {
3279 SDValue V = Op.getOperand(i);
3280 if (V.getOpcode() == ISD::UNDEF)
3283 isOnlyLowElement = false;
3284 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
3287 if (!Value.getNode())
3289 else if (V != Value)
3290 usesOnlyOneValue = false;
3293 if (!Value.getNode())
3294 return DAG.getUNDEF(VT);
3296 if (isOnlyLowElement)
3297 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
3299 // If all elements are constants, fall back to the default expansion, which
3300 // will generate a load from the constant pool.
3304 // Use VDUP for non-constant splats.
3305 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3306 if (usesOnlyOneValue && EltSize <= 32)
3307 return DAG.getNode(ARMISD::VDUP, dl, VT, Value);
3309 // Vectors with 32- or 64-bit elements can be built by directly assigning
3310 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
3311 // will be legalized.
3312 if (EltSize >= 32) {
3313 // Do the expansion with floating-point types, since that is what the VFP
3314 // registers are defined to use, and since i64 is not legal.
3315 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3316 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3317 SmallVector<SDValue, 8> Ops;
3318 for (unsigned i = 0; i < NumElts; ++i)
3319 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, EltVT, Op.getOperand(i)));
3320 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
3321 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val);
3327 /// isShuffleMaskLegal - Targets can use this to indicate that they only
3328 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
3329 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
3330 /// are assumed to be legal.
3332 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
3334 if (VT.getVectorNumElements() == 4 &&
3335 (VT.is128BitVector() || VT.is64BitVector())) {
3336 unsigned PFIndexes[4];
3337 for (unsigned i = 0; i != 4; ++i) {
3341 PFIndexes[i] = M[i];
3344 // Compute the index in the perfect shuffle table.
3345 unsigned PFTableIndex =
3346 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3347 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3348 unsigned Cost = (PFEntry >> 30);
3355 unsigned Imm, WhichResult;
3357 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3358 return (EltSize >= 32 ||
3359 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
3360 isVREVMask(M, VT, 64) ||
3361 isVREVMask(M, VT, 32) ||
3362 isVREVMask(M, VT, 16) ||
3363 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
3364 isVTRNMask(M, VT, WhichResult) ||
3365 isVUZPMask(M, VT, WhichResult) ||
3366 isVZIPMask(M, VT, WhichResult) ||
3367 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
3368 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
3369 isVZIP_v_undef_Mask(M, VT, WhichResult));
3372 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
3373 /// the specified operations to build the shuffle.
3374 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
3375 SDValue RHS, SelectionDAG &DAG,
3377 unsigned OpNum = (PFEntry >> 26) & 0x0F;
3378 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
3379 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
3382 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
3391 OP_VUZPL, // VUZP, left result
3392 OP_VUZPR, // VUZP, right result
3393 OP_VZIPL, // VZIP, left result
3394 OP_VZIPR, // VZIP, right result
3395 OP_VTRNL, // VTRN, left result
3396 OP_VTRNR // VTRN, right result
3399 if (OpNum == OP_COPY) {
3400 if (LHSID == (1*9+2)*9+3) return LHS;
3401 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
3405 SDValue OpLHS, OpRHS;
3406 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
3407 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
3408 EVT VT = OpLHS.getValueType();
3411 default: llvm_unreachable("Unknown shuffle opcode!");
3413 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
3418 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
3419 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
3423 return DAG.getNode(ARMISD::VEXT, dl, VT,
3425 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
3428 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3429 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
3432 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3433 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
3436 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3437 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
3441 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
3442 SDValue V1 = Op.getOperand(0);
3443 SDValue V2 = Op.getOperand(1);
3444 DebugLoc dl = Op.getDebugLoc();
3445 EVT VT = Op.getValueType();
3446 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
3447 SmallVector<int, 8> ShuffleMask;
3449 // Convert shuffles that are directly supported on NEON to target-specific
3450 // DAG nodes, instead of keeping them as shuffles and matching them again
3451 // during code selection. This is more efficient and avoids the possibility
3452 // of inconsistencies between legalization and selection.
3453 // FIXME: floating-point vectors should be canonicalized to integer vectors
3454 // of the same time so that they get CSEd properly.
3455 SVN->getMask(ShuffleMask);
3457 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3458 if (EltSize <= 32) {
3459 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
3460 int Lane = SVN->getSplatIndex();
3461 // If this is undef splat, generate it via "just" vdup, if possible.
3462 if (Lane == -1) Lane = 0;
3464 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
3465 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
3467 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
3468 DAG.getConstant(Lane, MVT::i32));
3473 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
3476 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
3477 DAG.getConstant(Imm, MVT::i32));
3480 if (isVREVMask(ShuffleMask, VT, 64))
3481 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
3482 if (isVREVMask(ShuffleMask, VT, 32))
3483 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
3484 if (isVREVMask(ShuffleMask, VT, 16))
3485 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
3487 // Check for Neon shuffles that modify both input vectors in place.
3488 // If both results are used, i.e., if there are two shuffles with the same
3489 // source operands and with masks corresponding to both results of one of
3490 // these operations, DAG memoization will ensure that a single node is
3491 // used for both shuffles.
3492 unsigned WhichResult;
3493 if (isVTRNMask(ShuffleMask, VT, WhichResult))
3494 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3495 V1, V2).getValue(WhichResult);
3496 if (isVUZPMask(ShuffleMask, VT, WhichResult))
3497 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3498 V1, V2).getValue(WhichResult);
3499 if (isVZIPMask(ShuffleMask, VT, WhichResult))
3500 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3501 V1, V2).getValue(WhichResult);
3503 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
3504 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3505 V1, V1).getValue(WhichResult);
3506 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
3507 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3508 V1, V1).getValue(WhichResult);
3509 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
3510 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3511 V1, V1).getValue(WhichResult);
3514 // If the shuffle is not directly supported and it has 4 elements, use
3515 // the PerfectShuffle-generated table to synthesize it from other shuffles.
3516 unsigned NumElts = VT.getVectorNumElements();
3518 unsigned PFIndexes[4];
3519 for (unsigned i = 0; i != 4; ++i) {
3520 if (ShuffleMask[i] < 0)
3523 PFIndexes[i] = ShuffleMask[i];
3526 // Compute the index in the perfect shuffle table.
3527 unsigned PFTableIndex =
3528 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3529 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3530 unsigned Cost = (PFEntry >> 30);
3533 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
3536 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
3537 if (EltSize >= 32) {
3538 // Do the expansion with floating-point types, since that is what the VFP
3539 // registers are defined to use, and since i64 is not legal.
3540 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3541 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3542 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, V1);
3543 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, V2);
3544 SmallVector<SDValue, 8> Ops;
3545 for (unsigned i = 0; i < NumElts; ++i) {
3546 if (ShuffleMask[i] < 0)
3547 Ops.push_back(DAG.getUNDEF(EltVT));
3549 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3550 ShuffleMask[i] < (int)NumElts ? V1 : V2,
3551 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
3554 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
3555 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val);
3561 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
3562 EVT VT = Op.getValueType();
3563 DebugLoc dl = Op.getDebugLoc();
3564 SDValue Vec = Op.getOperand(0);
3565 SDValue Lane = Op.getOperand(1);
3566 assert(VT == MVT::i32 &&
3567 Vec.getValueType().getVectorElementType().getSizeInBits() < 32 &&
3568 "unexpected type for custom-lowering vector extract");
3569 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
3572 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
3573 // The only time a CONCAT_VECTORS operation can have legal types is when
3574 // two 64-bit vectors are concatenated to a 128-bit vector.
3575 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
3576 "unexpected CONCAT_VECTORS");
3577 DebugLoc dl = Op.getDebugLoc();
3578 SDValue Val = DAG.getUNDEF(MVT::v2f64);
3579 SDValue Op0 = Op.getOperand(0);
3580 SDValue Op1 = Op.getOperand(1);
3581 if (Op0.getOpcode() != ISD::UNDEF)
3582 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
3583 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op0),
3584 DAG.getIntPtrConstant(0));
3585 if (Op1.getOpcode() != ISD::UNDEF)
3586 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
3587 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op1),
3588 DAG.getIntPtrConstant(1));
3589 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Val);
3592 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
3593 switch (Op.getOpcode()) {
3594 default: llvm_unreachable("Don't know how to custom lower this!");
3595 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3596 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
3597 case ISD::GlobalAddress:
3598 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
3599 LowerGlobalAddressELF(Op, DAG);
3600 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
3601 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
3602 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
3603 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
3604 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
3605 case ISD::VASTART: return LowerVASTART(Op, DAG);
3606 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget);
3607 case ISD::SINT_TO_FP:
3608 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
3609 case ISD::FP_TO_SINT:
3610 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
3611 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
3612 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
3613 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
3614 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
3615 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
3616 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
3617 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
3619 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(Op.getNode(), DAG);
3622 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
3623 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
3624 case ISD::SRL_PARTS:
3625 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
3626 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
3627 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
3628 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
3629 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
3630 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
3631 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
3636 /// ReplaceNodeResults - Replace the results of node with an illegal result
3637 /// type with new values built out of custom code.
3638 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
3639 SmallVectorImpl<SDValue>&Results,
3640 SelectionDAG &DAG) const {
3642 switch (N->getOpcode()) {
3644 llvm_unreachable("Don't know how to custom expand this!");
3646 case ISD::BIT_CONVERT:
3647 Res = ExpandBIT_CONVERT(N, DAG);
3651 Res = LowerShift(N, DAG, Subtarget);
3655 Results.push_back(Res);
3658 //===----------------------------------------------------------------------===//
3659 // ARM Scheduler Hooks
3660 //===----------------------------------------------------------------------===//
3663 ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
3664 MachineBasicBlock *BB,
3665 unsigned Size) const {
3666 unsigned dest = MI->getOperand(0).getReg();
3667 unsigned ptr = MI->getOperand(1).getReg();
3668 unsigned oldval = MI->getOperand(2).getReg();
3669 unsigned newval = MI->getOperand(3).getReg();
3670 unsigned scratch = BB->getParent()->getRegInfo()
3671 .createVirtualRegister(ARM::GPRRegisterClass);
3672 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3673 DebugLoc dl = MI->getDebugLoc();
3674 bool isThumb2 = Subtarget->isThumb2();
3676 unsigned ldrOpc, strOpc;
3678 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
3680 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
3681 strOpc = isThumb2 ? ARM::t2LDREXB : ARM::STREXB;
3684 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
3685 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
3688 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
3689 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
3693 MachineFunction *MF = BB->getParent();
3694 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3695 MachineFunction::iterator It = BB;
3696 ++It; // insert the new blocks after the current block
3698 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
3699 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
3700 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3701 MF->insert(It, loop1MBB);
3702 MF->insert(It, loop2MBB);
3703 MF->insert(It, exitMBB);
3705 // Transfer the remainder of BB and its successor edges to exitMBB.
3706 exitMBB->splice(exitMBB->begin(), BB,
3707 llvm::next(MachineBasicBlock::iterator(MI)),
3709 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
3713 // fallthrough --> loop1MBB
3714 BB->addSuccessor(loop1MBB);
3717 // ldrex dest, [ptr]
3721 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
3722 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
3723 .addReg(dest).addReg(oldval));
3724 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3725 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
3726 BB->addSuccessor(loop2MBB);
3727 BB->addSuccessor(exitMBB);
3730 // strex scratch, newval, [ptr]
3734 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval)
3736 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
3737 .addReg(scratch).addImm(0));
3738 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3739 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
3740 BB->addSuccessor(loop1MBB);
3741 BB->addSuccessor(exitMBB);
3747 MI->eraseFromParent(); // The instruction is gone now.
3753 ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
3754 unsigned Size, unsigned BinOpcode) const {
3755 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
3756 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3758 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3759 MachineFunction *MF = BB->getParent();
3760 MachineFunction::iterator It = BB;
3763 unsigned dest = MI->getOperand(0).getReg();
3764 unsigned ptr = MI->getOperand(1).getReg();
3765 unsigned incr = MI->getOperand(2).getReg();
3766 DebugLoc dl = MI->getDebugLoc();
3768 bool isThumb2 = Subtarget->isThumb2();
3769 unsigned ldrOpc, strOpc;
3771 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
3773 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
3774 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
3777 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
3778 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
3781 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
3782 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
3786 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3787 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3788 MF->insert(It, loopMBB);
3789 MF->insert(It, exitMBB);
3791 // Transfer the remainder of BB and its successor edges to exitMBB.
3792 exitMBB->splice(exitMBB->begin(), BB,
3793 llvm::next(MachineBasicBlock::iterator(MI)),
3795 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
3797 MachineRegisterInfo &RegInfo = MF->getRegInfo();
3798 unsigned scratch = RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
3799 unsigned scratch2 = (!BinOpcode) ? incr :
3800 RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
3804 // fallthrough --> loopMBB
3805 BB->addSuccessor(loopMBB);
3809 // <binop> scratch2, dest, incr
3810 // strex scratch, scratch2, ptr
3813 // fallthrough --> exitMBB
3815 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
3817 // operand order needs to go the other way for NAND
3818 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr)
3819 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
3820 addReg(incr).addReg(dest)).addReg(0);
3822 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
3823 addReg(dest).addReg(incr)).addReg(0);
3826 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2)
3828 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
3829 .addReg(scratch).addImm(0));
3830 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3831 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
3833 BB->addSuccessor(loopMBB);
3834 BB->addSuccessor(exitMBB);
3840 MI->eraseFromParent(); // The instruction is gone now.
3846 MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
3847 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
3848 E = MBB->succ_end(); I != E; ++I)
3851 llvm_unreachable("Expecting a BB with two successors!");
3855 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
3856 MachineBasicBlock *BB) const {
3857 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3858 DebugLoc dl = MI->getDebugLoc();
3859 bool isThumb2 = Subtarget->isThumb2();
3860 switch (MI->getOpcode()) {
3863 llvm_unreachable("Unexpected instr type to insert");
3865 case ARM::ATOMIC_LOAD_ADD_I8:
3866 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
3867 case ARM::ATOMIC_LOAD_ADD_I16:
3868 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
3869 case ARM::ATOMIC_LOAD_ADD_I32:
3870 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
3872 case ARM::ATOMIC_LOAD_AND_I8:
3873 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
3874 case ARM::ATOMIC_LOAD_AND_I16:
3875 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
3876 case ARM::ATOMIC_LOAD_AND_I32:
3877 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
3879 case ARM::ATOMIC_LOAD_OR_I8:
3880 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
3881 case ARM::ATOMIC_LOAD_OR_I16:
3882 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
3883 case ARM::ATOMIC_LOAD_OR_I32:
3884 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
3886 case ARM::ATOMIC_LOAD_XOR_I8:
3887 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
3888 case ARM::ATOMIC_LOAD_XOR_I16:
3889 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
3890 case ARM::ATOMIC_LOAD_XOR_I32:
3891 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
3893 case ARM::ATOMIC_LOAD_NAND_I8:
3894 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
3895 case ARM::ATOMIC_LOAD_NAND_I16:
3896 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
3897 case ARM::ATOMIC_LOAD_NAND_I32:
3898 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
3900 case ARM::ATOMIC_LOAD_SUB_I8:
3901 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
3902 case ARM::ATOMIC_LOAD_SUB_I16:
3903 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
3904 case ARM::ATOMIC_LOAD_SUB_I32:
3905 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
3907 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0);
3908 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0);
3909 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0);
3911 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1);
3912 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
3913 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
3915 case ARM::tMOVCCr_pseudo: {
3916 // To "insert" a SELECT_CC instruction, we actually have to insert the
3917 // diamond control-flow pattern. The incoming instruction knows the
3918 // destination vreg to set, the condition code register to branch on, the
3919 // true/false values to select between, and a branch opcode to use.
3920 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3921 MachineFunction::iterator It = BB;
3927 // cmpTY ccX, r1, r2
3929 // fallthrough --> copy0MBB
3930 MachineBasicBlock *thisMBB = BB;
3931 MachineFunction *F = BB->getParent();
3932 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
3933 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
3934 F->insert(It, copy0MBB);
3935 F->insert(It, sinkMBB);
3937 // Transfer the remainder of BB and its successor edges to sinkMBB.
3938 sinkMBB->splice(sinkMBB->begin(), BB,
3939 llvm::next(MachineBasicBlock::iterator(MI)),
3941 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
3943 BB->addSuccessor(copy0MBB);
3944 BB->addSuccessor(sinkMBB);
3946 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
3947 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
3950 // %FalseValue = ...
3951 // # fallthrough to sinkMBB
3954 // Update machine-CFG edges
3955 BB->addSuccessor(sinkMBB);
3958 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
3961 BuildMI(*BB, BB->begin(), dl,
3962 TII->get(ARM::PHI), MI->getOperand(0).getReg())
3963 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
3964 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
3966 MI->eraseFromParent(); // The pseudo instruction is gone now.
3971 case ARM::BCCZi64: {
3972 // Compare both parts that make up the double comparison separately for
3974 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
3976 unsigned LHS1 = MI->getOperand(1).getReg();
3977 unsigned LHS2 = MI->getOperand(2).getReg();
3979 AddDefaultPred(BuildMI(BB, dl,
3980 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
3981 .addReg(LHS1).addImm(0));
3982 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
3983 .addReg(LHS2).addImm(0)
3984 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
3986 unsigned RHS1 = MI->getOperand(3).getReg();
3987 unsigned RHS2 = MI->getOperand(4).getReg();
3988 AddDefaultPred(BuildMI(BB, dl,
3989 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
3990 .addReg(LHS1).addReg(RHS1));
3991 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
3992 .addReg(LHS2).addReg(RHS2)
3993 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
3996 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB();
3997 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
3998 if (MI->getOperand(0).getImm() == ARMCC::NE)
3999 std::swap(destMBB, exitMBB);
4001 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4002 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
4003 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2B : ARM::B))
4006 MI->eraseFromParent(); // The pseudo instruction is gone now.
4013 case ARM::t2SUBrSPi_:
4014 case ARM::t2SUBrSPi12_:
4015 case ARM::t2SUBrSPs_: {
4016 MachineFunction *MF = BB->getParent();
4017 unsigned DstReg = MI->getOperand(0).getReg();
4018 unsigned SrcReg = MI->getOperand(1).getReg();
4019 bool DstIsDead = MI->getOperand(0).isDead();
4020 bool SrcIsKill = MI->getOperand(1).isKill();
4022 if (SrcReg != ARM::SP) {
4023 // Copy the source to SP from virtual register.
4024 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(SrcReg);
4025 unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
4026 ? ARM::tMOVtgpr2gpr : ARM::tMOVgpr2gpr;
4027 BuildMI(*BB, MI, dl, TII->get(CopyOpc), ARM::SP)
4028 .addReg(SrcReg, getKillRegState(SrcIsKill));
4032 bool NeedPred = false, NeedCC = false, NeedOp3 = false;
4033 switch (MI->getOpcode()) {
4035 llvm_unreachable("Unexpected pseudo instruction!");
4041 OpOpc = ARM::tADDspr;
4044 OpOpc = ARM::tSUBspi;
4046 case ARM::t2SUBrSPi_:
4047 OpOpc = ARM::t2SUBrSPi;
4048 NeedPred = true; NeedCC = true;
4050 case ARM::t2SUBrSPi12_:
4051 OpOpc = ARM::t2SUBrSPi12;
4054 case ARM::t2SUBrSPs_:
4055 OpOpc = ARM::t2SUBrSPs;
4056 NeedPred = true; NeedCC = true; NeedOp3 = true;
4059 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(OpOpc), ARM::SP);
4060 if (OpOpc == ARM::tAND)
4061 AddDefaultT1CC(MIB);
4062 MIB.addReg(ARM::SP);
4063 MIB.addOperand(MI->getOperand(2));
4065 MIB.addOperand(MI->getOperand(3));
4067 AddDefaultPred(MIB);
4071 // Copy the result from SP to virtual register.
4072 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(DstReg);
4073 unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
4074 ? ARM::tMOVgpr2tgpr : ARM::tMOVgpr2gpr;
4075 BuildMI(*BB, MI, dl, TII->get(CopyOpc))
4076 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead))
4078 MI->eraseFromParent(); // The pseudo instruction is gone now.
4084 //===----------------------------------------------------------------------===//
4085 // ARM Optimization Hooks
4086 //===----------------------------------------------------------------------===//
4089 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
4090 TargetLowering::DAGCombinerInfo &DCI) {
4091 SelectionDAG &DAG = DCI.DAG;
4092 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4093 EVT VT = N->getValueType(0);
4094 unsigned Opc = N->getOpcode();
4095 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
4096 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
4097 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
4098 ISD::CondCode CC = ISD::SETCC_INVALID;
4101 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
4103 SDValue CCOp = Slct.getOperand(0);
4104 if (CCOp.getOpcode() == ISD::SETCC)
4105 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
4108 bool DoXform = false;
4110 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
4113 if (LHS.getOpcode() == ISD::Constant &&
4114 cast<ConstantSDNode>(LHS)->isNullValue()) {
4116 } else if (CC != ISD::SETCC_INVALID &&
4117 RHS.getOpcode() == ISD::Constant &&
4118 cast<ConstantSDNode>(RHS)->isNullValue()) {
4119 std::swap(LHS, RHS);
4120 SDValue Op0 = Slct.getOperand(0);
4121 EVT OpVT = isSlctCC ? Op0.getValueType() :
4122 Op0.getOperand(0).getValueType();
4123 bool isInt = OpVT.isInteger();
4124 CC = ISD::getSetCCInverse(CC, isInt);
4126 if (!TLI.isCondCodeLegal(CC, OpVT))
4127 return SDValue(); // Inverse operator isn't legal.
4134 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
4136 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
4137 Slct.getOperand(0), Slct.getOperand(1), CC);
4138 SDValue CCOp = Slct.getOperand(0);
4140 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
4141 CCOp.getOperand(0), CCOp.getOperand(1), CC);
4142 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
4143 CCOp, OtherOp, Result);
4148 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
4149 static SDValue PerformADDCombine(SDNode *N,
4150 TargetLowering::DAGCombinerInfo &DCI) {
4151 // added by evan in r37685 with no testcase.
4152 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
4154 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
4155 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
4156 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
4157 if (Result.getNode()) return Result;
4159 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
4160 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
4161 if (Result.getNode()) return Result;
4167 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
4168 static SDValue PerformSUBCombine(SDNode *N,
4169 TargetLowering::DAGCombinerInfo &DCI) {
4170 // added by evan in r37685 with no testcase.
4171 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
4173 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
4174 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
4175 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
4176 if (Result.getNode()) return Result;
4182 static SDValue PerformMULCombine(SDNode *N,
4183 TargetLowering::DAGCombinerInfo &DCI,
4184 const ARMSubtarget *Subtarget) {
4185 SelectionDAG &DAG = DCI.DAG;
4187 if (Subtarget->isThumb1Only())
4190 if (DAG.getMachineFunction().
4191 getFunction()->hasFnAttr(Attribute::OptimizeForSize))
4194 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
4197 EVT VT = N->getValueType(0);
4201 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
4205 uint64_t MulAmt = C->getZExtValue();
4206 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt);
4207 ShiftAmt = ShiftAmt & (32 - 1);
4208 SDValue V = N->getOperand(0);
4209 DebugLoc DL = N->getDebugLoc();
4212 MulAmt >>= ShiftAmt;
4213 if (isPowerOf2_32(MulAmt - 1)) {
4214 // (mul x, 2^N + 1) => (add (shl x, N), x)
4215 Res = DAG.getNode(ISD::ADD, DL, VT,
4216 V, DAG.getNode(ISD::SHL, DL, VT,
4217 V, DAG.getConstant(Log2_32(MulAmt-1),
4219 } else if (isPowerOf2_32(MulAmt + 1)) {
4220 // (mul x, 2^N - 1) => (sub (shl x, N), x)
4221 Res = DAG.getNode(ISD::SUB, DL, VT,
4222 DAG.getNode(ISD::SHL, DL, VT,
4223 V, DAG.getConstant(Log2_32(MulAmt+1),
4230 Res = DAG.getNode(ISD::SHL, DL, VT, Res,
4231 DAG.getConstant(ShiftAmt, MVT::i32));
4233 // Do not add new nodes to DAG combiner worklist.
4234 DCI.CombineTo(N, Res, false);
4238 /// PerformORCombine - Target-specific dag combine xforms for ISD::OR
4239 static SDValue PerformORCombine(SDNode *N,
4240 TargetLowering::DAGCombinerInfo &DCI,
4241 const ARMSubtarget *Subtarget) {
4242 // BFI is only available on V6T2+
4243 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops())
4246 SelectionDAG &DAG = DCI.DAG;
4247 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
4248 // or (and A, mask), val => ARMbfi A, val, mask
4249 // iff (val & mask) == val
4250 if (N0->getOpcode() != ISD::AND)
4253 EVT VT = N->getValueType(0);
4257 // The value and the mask need to be constants so we can verify this is
4258 // actually a bitfield set. If the mask is 0xffff, we can do better
4259 // via a movt instruction, so don't use BFI in that case.
4260 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
4263 unsigned Mask = C->getZExtValue();
4266 C = dyn_cast<ConstantSDNode>(N1);
4269 unsigned Val = C->getZExtValue();
4270 if (!ARM::isBitFieldInvertedMask(Mask) || (Val & ~Mask) != Val)
4272 Val >>= CountTrailingZeros_32(~Mask);
4274 DebugLoc DL = N->getDebugLoc();
4275 SDValue Res = DAG.getNode(ARMISD::BFI, DL, VT, N0.getOperand(0),
4276 DAG.getConstant(Val, MVT::i32),
4277 DAG.getConstant(Mask, MVT::i32));
4279 // Do not add new nodes to DAG combiner worklist.
4280 DCI.CombineTo(N, Res, false);
4285 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
4286 /// ARMISD::VMOVRRD.
4287 static SDValue PerformVMOVRRDCombine(SDNode *N,
4288 TargetLowering::DAGCombinerInfo &DCI) {
4289 // fmrrd(fmdrr x, y) -> x,y
4290 SDValue InDouble = N->getOperand(0);
4291 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
4292 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
4296 /// PerformVDUPLANECombine - Target-specific dag combine xforms for
4297 /// ARMISD::VDUPLANE.
4298 static SDValue PerformVDUPLANECombine(SDNode *N,
4299 TargetLowering::DAGCombinerInfo &DCI) {
4300 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
4302 SDValue Op = N->getOperand(0);
4303 EVT VT = N->getValueType(0);
4305 // Ignore bit_converts.
4306 while (Op.getOpcode() == ISD::BIT_CONVERT)
4307 Op = Op.getOperand(0);
4308 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
4311 // Make sure the VMOV element size is not bigger than the VDUPLANE elements.
4312 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits();
4313 // The canonical VMOV for a zero vector uses a 32-bit element size.
4314 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4316 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
4318 if (EltSize > VT.getVectorElementType().getSizeInBits())
4321 SDValue Res = DCI.DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
4322 return DCI.CombineTo(N, Res, false);
4325 /// getVShiftImm - Check if this is a valid build_vector for the immediate
4326 /// operand of a vector shift operation, where all the elements of the
4327 /// build_vector must have the same constant integer value.
4328 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
4329 // Ignore bit_converts.
4330 while (Op.getOpcode() == ISD::BIT_CONVERT)
4331 Op = Op.getOperand(0);
4332 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
4333 APInt SplatBits, SplatUndef;
4334 unsigned SplatBitSize;
4336 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
4337 HasAnyUndefs, ElementBits) ||
4338 SplatBitSize > ElementBits)
4340 Cnt = SplatBits.getSExtValue();
4344 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
4345 /// operand of a vector shift left operation. That value must be in the range:
4346 /// 0 <= Value < ElementBits for a left shift; or
4347 /// 0 <= Value <= ElementBits for a long left shift.
4348 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
4349 assert(VT.isVector() && "vector shift count is not a vector type");
4350 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
4351 if (! getVShiftImm(Op, ElementBits, Cnt))
4353 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
4356 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
4357 /// operand of a vector shift right operation. For a shift opcode, the value
4358 /// is positive, but for an intrinsic the value count must be negative. The
4359 /// absolute value must be in the range:
4360 /// 1 <= |Value| <= ElementBits for a right shift; or
4361 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
4362 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
4364 assert(VT.isVector() && "vector shift count is not a vector type");
4365 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
4366 if (! getVShiftImm(Op, ElementBits, Cnt))
4370 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
4373 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
4374 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
4375 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
4378 // Don't do anything for most intrinsics.
4381 // Vector shifts: check for immediate versions and lower them.
4382 // Note: This is done during DAG combining instead of DAG legalizing because
4383 // the build_vectors for 64-bit vector element shift counts are generally
4384 // not legal, and it is hard to see their values after they get legalized to
4385 // loads from a constant pool.
4386 case Intrinsic::arm_neon_vshifts:
4387 case Intrinsic::arm_neon_vshiftu:
4388 case Intrinsic::arm_neon_vshiftls:
4389 case Intrinsic::arm_neon_vshiftlu:
4390 case Intrinsic::arm_neon_vshiftn:
4391 case Intrinsic::arm_neon_vrshifts:
4392 case Intrinsic::arm_neon_vrshiftu:
4393 case Intrinsic::arm_neon_vrshiftn:
4394 case Intrinsic::arm_neon_vqshifts:
4395 case Intrinsic::arm_neon_vqshiftu:
4396 case Intrinsic::arm_neon_vqshiftsu:
4397 case Intrinsic::arm_neon_vqshiftns:
4398 case Intrinsic::arm_neon_vqshiftnu:
4399 case Intrinsic::arm_neon_vqshiftnsu:
4400 case Intrinsic::arm_neon_vqrshiftns:
4401 case Intrinsic::arm_neon_vqrshiftnu:
4402 case Intrinsic::arm_neon_vqrshiftnsu: {
4403 EVT VT = N->getOperand(1).getValueType();
4405 unsigned VShiftOpc = 0;
4408 case Intrinsic::arm_neon_vshifts:
4409 case Intrinsic::arm_neon_vshiftu:
4410 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
4411 VShiftOpc = ARMISD::VSHL;
4414 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
4415 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
4416 ARMISD::VSHRs : ARMISD::VSHRu);
4421 case Intrinsic::arm_neon_vshiftls:
4422 case Intrinsic::arm_neon_vshiftlu:
4423 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
4425 llvm_unreachable("invalid shift count for vshll intrinsic");
4427 case Intrinsic::arm_neon_vrshifts:
4428 case Intrinsic::arm_neon_vrshiftu:
4429 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
4433 case Intrinsic::arm_neon_vqshifts:
4434 case Intrinsic::arm_neon_vqshiftu:
4435 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
4439 case Intrinsic::arm_neon_vqshiftsu:
4440 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
4442 llvm_unreachable("invalid shift count for vqshlu intrinsic");
4444 case Intrinsic::arm_neon_vshiftn:
4445 case Intrinsic::arm_neon_vrshiftn:
4446 case Intrinsic::arm_neon_vqshiftns:
4447 case Intrinsic::arm_neon_vqshiftnu:
4448 case Intrinsic::arm_neon_vqshiftnsu:
4449 case Intrinsic::arm_neon_vqrshiftns:
4450 case Intrinsic::arm_neon_vqrshiftnu:
4451 case Intrinsic::arm_neon_vqrshiftnsu:
4452 // Narrowing shifts require an immediate right shift.
4453 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
4455 llvm_unreachable("invalid shift count for narrowing vector shift "
4459 llvm_unreachable("unhandled vector shift");
4463 case Intrinsic::arm_neon_vshifts:
4464 case Intrinsic::arm_neon_vshiftu:
4465 // Opcode already set above.
4467 case Intrinsic::arm_neon_vshiftls:
4468 case Intrinsic::arm_neon_vshiftlu:
4469 if (Cnt == VT.getVectorElementType().getSizeInBits())
4470 VShiftOpc = ARMISD::VSHLLi;
4472 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
4473 ARMISD::VSHLLs : ARMISD::VSHLLu);
4475 case Intrinsic::arm_neon_vshiftn:
4476 VShiftOpc = ARMISD::VSHRN; break;
4477 case Intrinsic::arm_neon_vrshifts:
4478 VShiftOpc = ARMISD::VRSHRs; break;
4479 case Intrinsic::arm_neon_vrshiftu:
4480 VShiftOpc = ARMISD::VRSHRu; break;
4481 case Intrinsic::arm_neon_vrshiftn:
4482 VShiftOpc = ARMISD::VRSHRN; break;
4483 case Intrinsic::arm_neon_vqshifts:
4484 VShiftOpc = ARMISD::VQSHLs; break;
4485 case Intrinsic::arm_neon_vqshiftu:
4486 VShiftOpc = ARMISD::VQSHLu; break;
4487 case Intrinsic::arm_neon_vqshiftsu:
4488 VShiftOpc = ARMISD::VQSHLsu; break;
4489 case Intrinsic::arm_neon_vqshiftns:
4490 VShiftOpc = ARMISD::VQSHRNs; break;
4491 case Intrinsic::arm_neon_vqshiftnu:
4492 VShiftOpc = ARMISD::VQSHRNu; break;
4493 case Intrinsic::arm_neon_vqshiftnsu:
4494 VShiftOpc = ARMISD::VQSHRNsu; break;
4495 case Intrinsic::arm_neon_vqrshiftns:
4496 VShiftOpc = ARMISD::VQRSHRNs; break;
4497 case Intrinsic::arm_neon_vqrshiftnu:
4498 VShiftOpc = ARMISD::VQRSHRNu; break;
4499 case Intrinsic::arm_neon_vqrshiftnsu:
4500 VShiftOpc = ARMISD::VQRSHRNsu; break;
4503 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
4504 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
4507 case Intrinsic::arm_neon_vshiftins: {
4508 EVT VT = N->getOperand(1).getValueType();
4510 unsigned VShiftOpc = 0;
4512 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
4513 VShiftOpc = ARMISD::VSLI;
4514 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
4515 VShiftOpc = ARMISD::VSRI;
4517 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
4520 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
4521 N->getOperand(1), N->getOperand(2),
4522 DAG.getConstant(Cnt, MVT::i32));
4525 case Intrinsic::arm_neon_vqrshifts:
4526 case Intrinsic::arm_neon_vqrshiftu:
4527 // No immediate versions of these to check for.
4534 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
4535 /// lowers them. As with the vector shift intrinsics, this is done during DAG
4536 /// combining instead of DAG legalizing because the build_vectors for 64-bit
4537 /// vector element shift counts are generally not legal, and it is hard to see
4538 /// their values after they get legalized to loads from a constant pool.
4539 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
4540 const ARMSubtarget *ST) {
4541 EVT VT = N->getValueType(0);
4543 // Nothing to be done for scalar shifts.
4544 if (! VT.isVector())
4547 assert(ST->hasNEON() && "unexpected vector shift");
4550 switch (N->getOpcode()) {
4551 default: llvm_unreachable("unexpected shift opcode");
4554 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
4555 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
4556 DAG.getConstant(Cnt, MVT::i32));
4561 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
4562 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
4563 ARMISD::VSHRs : ARMISD::VSHRu);
4564 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
4565 DAG.getConstant(Cnt, MVT::i32));
4571 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
4572 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
4573 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
4574 const ARMSubtarget *ST) {
4575 SDValue N0 = N->getOperand(0);
4577 // Check for sign- and zero-extensions of vector extract operations of 8-
4578 // and 16-bit vector elements. NEON supports these directly. They are
4579 // handled during DAG combining because type legalization will promote them
4580 // to 32-bit types and it is messy to recognize the operations after that.
4581 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
4582 SDValue Vec = N0.getOperand(0);
4583 SDValue Lane = N0.getOperand(1);
4584 EVT VT = N->getValueType(0);
4585 EVT EltVT = N0.getValueType();
4586 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4588 if (VT == MVT::i32 &&
4589 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
4590 TLI.isTypeLegal(Vec.getValueType())) {
4593 switch (N->getOpcode()) {
4594 default: llvm_unreachable("unexpected opcode");
4595 case ISD::SIGN_EXTEND:
4596 Opc = ARMISD::VGETLANEs;
4598 case ISD::ZERO_EXTEND:
4599 case ISD::ANY_EXTEND:
4600 Opc = ARMISD::VGETLANEu;
4603 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
4610 /// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
4611 /// to match f32 max/min patterns to use NEON vmax/vmin instructions.
4612 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
4613 const ARMSubtarget *ST) {
4614 // If the target supports NEON, try to use vmax/vmin instructions for f32
4615 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set,
4616 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
4617 // a NaN; only do the transformation when it matches that behavior.
4619 // For now only do this when using NEON for FP operations; if using VFP, it
4620 // is not obvious that the benefit outweighs the cost of switching to the
4622 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
4623 N->getValueType(0) != MVT::f32)
4626 SDValue CondLHS = N->getOperand(0);
4627 SDValue CondRHS = N->getOperand(1);
4628 SDValue LHS = N->getOperand(2);
4629 SDValue RHS = N->getOperand(3);
4630 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
4632 unsigned Opcode = 0;
4634 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
4635 IsReversed = false; // x CC y ? x : y
4636 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
4637 IsReversed = true ; // x CC y ? y : x
4651 // If LHS is NaN, an ordered comparison will be false and the result will
4652 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
4653 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
4654 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
4655 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
4657 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
4658 // will return -0, so vmin can only be used for unsafe math or if one of
4659 // the operands is known to be nonzero.
4660 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
4662 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
4664 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
4673 // If LHS is NaN, an ordered comparison will be false and the result will
4674 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
4675 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
4676 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
4677 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
4679 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
4680 // will return +0, so vmax can only be used for unsafe math or if one of
4681 // the operands is known to be nonzero.
4682 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
4684 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
4686 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
4692 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS);
4695 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
4696 DAGCombinerInfo &DCI) const {
4697 switch (N->getOpcode()) {
4699 case ISD::ADD: return PerformADDCombine(N, DCI);
4700 case ISD::SUB: return PerformSUBCombine(N, DCI);
4701 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
4702 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
4703 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
4704 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
4705 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
4708 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
4709 case ISD::SIGN_EXTEND:
4710 case ISD::ZERO_EXTEND:
4711 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
4712 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
4717 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
4718 if (!Subtarget->hasV6Ops())
4719 // Pre-v6 does not support unaligned mem access.
4722 // v6+ may or may not support unaligned mem access depending on the system
4724 // FIXME: This is pretty conservative. Should we provide cmdline option to
4725 // control the behaviour?
4726 if (!Subtarget->isTargetDarwin())
4729 switch (VT.getSimpleVT().SimpleTy) {
4736 // FIXME: VLD1 etc with standard alignment is legal.
4740 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
4745 switch (VT.getSimpleVT().SimpleTy) {
4746 default: return false;
4761 if ((V & (Scale - 1)) != 0)
4764 return V == (V & ((1LL << 5) - 1));
4767 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
4768 const ARMSubtarget *Subtarget) {
4775 switch (VT.getSimpleVT().SimpleTy) {
4776 default: return false;
4781 // + imm12 or - imm8
4783 return V == (V & ((1LL << 8) - 1));
4784 return V == (V & ((1LL << 12) - 1));
4787 // Same as ARM mode. FIXME: NEON?
4788 if (!Subtarget->hasVFP2())
4793 return V == (V & ((1LL << 8) - 1));
4797 /// isLegalAddressImmediate - Return true if the integer value can be used
4798 /// as the offset of the target addressing mode for load / store of the
4800 static bool isLegalAddressImmediate(int64_t V, EVT VT,
4801 const ARMSubtarget *Subtarget) {
4808 if (Subtarget->isThumb1Only())
4809 return isLegalT1AddressImmediate(V, VT);
4810 else if (Subtarget->isThumb2())
4811 return isLegalT2AddressImmediate(V, VT, Subtarget);
4816 switch (VT.getSimpleVT().SimpleTy) {
4817 default: return false;
4822 return V == (V & ((1LL << 12) - 1));
4825 return V == (V & ((1LL << 8) - 1));
4828 if (!Subtarget->hasVFP2()) // FIXME: NEON?
4833 return V == (V & ((1LL << 8) - 1));
4837 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
4839 int Scale = AM.Scale;
4843 switch (VT.getSimpleVT().SimpleTy) {
4844 default: return false;
4853 return Scale == 2 || Scale == 4 || Scale == 8;
4856 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
4860 // Note, we allow "void" uses (basically, uses that aren't loads or
4861 // stores), because arm allows folding a scale into many arithmetic
4862 // operations. This should be made more precise and revisited later.
4864 // Allow r << imm, but the imm has to be a multiple of two.
4865 if (Scale & 1) return false;
4866 return isPowerOf2_32(Scale);
4870 /// isLegalAddressingMode - Return true if the addressing mode represented
4871 /// by AM is legal for this target, for a load/store of the specified type.
4872 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
4873 const Type *Ty) const {
4874 EVT VT = getValueType(Ty, true);
4875 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
4878 // Can never fold addr of global into load/store.
4883 case 0: // no scale reg, must be "r+i" or "r", or "i".
4886 if (Subtarget->isThumb1Only())
4890 // ARM doesn't support any R+R*scale+imm addr modes.
4897 if (Subtarget->isThumb2())
4898 return isLegalT2ScaledAddressingMode(AM, VT);
4900 int Scale = AM.Scale;
4901 switch (VT.getSimpleVT().SimpleTy) {
4902 default: return false;
4906 if (Scale < 0) Scale = -Scale;
4910 return isPowerOf2_32(Scale & ~1);
4914 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
4919 // Note, we allow "void" uses (basically, uses that aren't loads or
4920 // stores), because arm allows folding a scale into many arithmetic
4921 // operations. This should be made more precise and revisited later.
4923 // Allow r << imm, but the imm has to be a multiple of two.
4924 if (Scale & 1) return false;
4925 return isPowerOf2_32(Scale);
4932 /// isLegalICmpImmediate - Return true if the specified immediate is legal
4933 /// icmp immediate, that is the target has icmp instructions which can compare
4934 /// a register against the immediate without having to materialize the
4935 /// immediate into a register.
4936 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
4937 if (!Subtarget->isThumb())
4938 return ARM_AM::getSOImmVal(Imm) != -1;
4939 if (Subtarget->isThumb2())
4940 return ARM_AM::getT2SOImmVal(Imm) != -1;
4941 return Imm >= 0 && Imm <= 255;
4944 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
4945 bool isSEXTLoad, SDValue &Base,
4946 SDValue &Offset, bool &isInc,
4947 SelectionDAG &DAG) {
4948 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
4951 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
4953 Base = Ptr->getOperand(0);
4954 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
4955 int RHSC = (int)RHS->getZExtValue();
4956 if (RHSC < 0 && RHSC > -256) {
4957 assert(Ptr->getOpcode() == ISD::ADD);
4959 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
4963 isInc = (Ptr->getOpcode() == ISD::ADD);
4964 Offset = Ptr->getOperand(1);
4966 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
4968 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
4969 int RHSC = (int)RHS->getZExtValue();
4970 if (RHSC < 0 && RHSC > -0x1000) {
4971 assert(Ptr->getOpcode() == ISD::ADD);
4973 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
4974 Base = Ptr->getOperand(0);
4979 if (Ptr->getOpcode() == ISD::ADD) {
4981 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
4982 if (ShOpcVal != ARM_AM::no_shift) {
4983 Base = Ptr->getOperand(1);
4984 Offset = Ptr->getOperand(0);
4986 Base = Ptr->getOperand(0);
4987 Offset = Ptr->getOperand(1);
4992 isInc = (Ptr->getOpcode() == ISD::ADD);
4993 Base = Ptr->getOperand(0);
4994 Offset = Ptr->getOperand(1);
4998 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
5002 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
5003 bool isSEXTLoad, SDValue &Base,
5004 SDValue &Offset, bool &isInc,
5005 SelectionDAG &DAG) {
5006 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
5009 Base = Ptr->getOperand(0);
5010 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
5011 int RHSC = (int)RHS->getZExtValue();
5012 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
5013 assert(Ptr->getOpcode() == ISD::ADD);
5015 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
5017 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
5018 isInc = Ptr->getOpcode() == ISD::ADD;
5019 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
5027 /// getPreIndexedAddressParts - returns true by value, base pointer and
5028 /// offset pointer and addressing mode by reference if the node's address
5029 /// can be legally represented as pre-indexed load / store address.
5031 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
5033 ISD::MemIndexedMode &AM,
5034 SelectionDAG &DAG) const {
5035 if (Subtarget->isThumb1Only())
5040 bool isSEXTLoad = false;
5041 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5042 Ptr = LD->getBasePtr();
5043 VT = LD->getMemoryVT();
5044 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
5045 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5046 Ptr = ST->getBasePtr();
5047 VT = ST->getMemoryVT();
5052 bool isLegal = false;
5053 if (Subtarget->isThumb2())
5054 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
5055 Offset, isInc, DAG);
5057 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
5058 Offset, isInc, DAG);
5062 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
5066 /// getPostIndexedAddressParts - returns true by value, base pointer and
5067 /// offset pointer and addressing mode by reference if this node can be
5068 /// combined with a load / store to form a post-indexed load / store.
5069 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
5072 ISD::MemIndexedMode &AM,
5073 SelectionDAG &DAG) const {
5074 if (Subtarget->isThumb1Only())
5079 bool isSEXTLoad = false;
5080 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5081 VT = LD->getMemoryVT();
5082 Ptr = LD->getBasePtr();
5083 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
5084 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5085 VT = ST->getMemoryVT();
5086 Ptr = ST->getBasePtr();
5091 bool isLegal = false;
5092 if (Subtarget->isThumb2())
5093 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
5096 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
5102 // Swap base ptr and offset to catch more post-index load / store when
5103 // it's legal. In Thumb2 mode, offset must be an immediate.
5104 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
5105 !Subtarget->isThumb2())
5106 std::swap(Base, Offset);
5108 // Post-indexed load / store update the base pointer.
5113 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
5117 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
5121 const SelectionDAG &DAG,
5122 unsigned Depth) const {
5123 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
5124 switch (Op.getOpcode()) {
5126 case ARMISD::CMOV: {
5127 // Bits are known zero/one if known on the LHS and RHS.
5128 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
5129 if (KnownZero == 0 && KnownOne == 0) return;
5131 APInt KnownZeroRHS, KnownOneRHS;
5132 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
5133 KnownZeroRHS, KnownOneRHS, Depth+1);
5134 KnownZero &= KnownZeroRHS;
5135 KnownOne &= KnownOneRHS;
5141 //===----------------------------------------------------------------------===//
5142 // ARM Inline Assembly Support
5143 //===----------------------------------------------------------------------===//
5145 /// getConstraintType - Given a constraint letter, return the type of
5146 /// constraint it is for this target.
5147 ARMTargetLowering::ConstraintType
5148 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
5149 if (Constraint.size() == 1) {
5150 switch (Constraint[0]) {
5152 case 'l': return C_RegisterClass;
5153 case 'w': return C_RegisterClass;
5156 return TargetLowering::getConstraintType(Constraint);
5159 std::pair<unsigned, const TargetRegisterClass*>
5160 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
5162 if (Constraint.size() == 1) {
5163 // GCC ARM Constraint Letters
5164 switch (Constraint[0]) {
5166 if (Subtarget->isThumb())
5167 return std::make_pair(0U, ARM::tGPRRegisterClass);
5169 return std::make_pair(0U, ARM::GPRRegisterClass);
5171 return std::make_pair(0U, ARM::GPRRegisterClass);
5174 return std::make_pair(0U, ARM::SPRRegisterClass);
5175 if (VT.getSizeInBits() == 64)
5176 return std::make_pair(0U, ARM::DPRRegisterClass);
5177 if (VT.getSizeInBits() == 128)
5178 return std::make_pair(0U, ARM::QPRRegisterClass);
5182 if (StringRef("{cc}").equals_lower(Constraint))
5183 return std::make_pair(unsigned(ARM::CPSR), ARM::CCRRegisterClass);
5185 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
5188 std::vector<unsigned> ARMTargetLowering::
5189 getRegClassForInlineAsmConstraint(const std::string &Constraint,
5191 if (Constraint.size() != 1)
5192 return std::vector<unsigned>();
5194 switch (Constraint[0]) { // GCC ARM Constraint Letters
5197 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
5198 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
5201 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
5202 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
5203 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
5204 ARM::R12, ARM::LR, 0);
5207 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
5208 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
5209 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
5210 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
5211 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
5212 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
5213 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
5214 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
5215 if (VT.getSizeInBits() == 64)
5216 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
5217 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
5218 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
5219 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
5220 if (VT.getSizeInBits() == 128)
5221 return make_vector<unsigned>(ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
5222 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 0);
5226 return std::vector<unsigned>();
5229 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
5230 /// vector. If it is invalid, don't add anything to Ops.
5231 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
5233 std::vector<SDValue>&Ops,
5234 SelectionDAG &DAG) const {
5235 SDValue Result(0, 0);
5237 switch (Constraint) {
5239 case 'I': case 'J': case 'K': case 'L':
5240 case 'M': case 'N': case 'O':
5241 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
5245 int64_t CVal64 = C->getSExtValue();
5246 int CVal = (int) CVal64;
5247 // None of these constraints allow values larger than 32 bits. Check
5248 // that the value fits in an int.
5252 switch (Constraint) {
5254 if (Subtarget->isThumb1Only()) {
5255 // This must be a constant between 0 and 255, for ADD
5257 if (CVal >= 0 && CVal <= 255)
5259 } else if (Subtarget->isThumb2()) {
5260 // A constant that can be used as an immediate value in a
5261 // data-processing instruction.
5262 if (ARM_AM::getT2SOImmVal(CVal) != -1)
5265 // A constant that can be used as an immediate value in a
5266 // data-processing instruction.
5267 if (ARM_AM::getSOImmVal(CVal) != -1)
5273 if (Subtarget->isThumb()) { // FIXME thumb2
5274 // This must be a constant between -255 and -1, for negated ADD
5275 // immediates. This can be used in GCC with an "n" modifier that
5276 // prints the negated value, for use with SUB instructions. It is
5277 // not useful otherwise but is implemented for compatibility.
5278 if (CVal >= -255 && CVal <= -1)
5281 // This must be a constant between -4095 and 4095. It is not clear
5282 // what this constraint is intended for. Implemented for
5283 // compatibility with GCC.
5284 if (CVal >= -4095 && CVal <= 4095)
5290 if (Subtarget->isThumb1Only()) {
5291 // A 32-bit value where only one byte has a nonzero value. Exclude
5292 // zero to match GCC. This constraint is used by GCC internally for
5293 // constants that can be loaded with a move/shift combination.
5294 // It is not useful otherwise but is implemented for compatibility.
5295 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
5297 } else if (Subtarget->isThumb2()) {
5298 // A constant whose bitwise inverse can be used as an immediate
5299 // value in a data-processing instruction. This can be used in GCC
5300 // with a "B" modifier that prints the inverted value, for use with
5301 // BIC and MVN instructions. It is not useful otherwise but is
5302 // implemented for compatibility.
5303 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
5306 // A constant whose bitwise inverse can be used as an immediate
5307 // value in a data-processing instruction. This can be used in GCC
5308 // with a "B" modifier that prints the inverted value, for use with
5309 // BIC and MVN instructions. It is not useful otherwise but is
5310 // implemented for compatibility.
5311 if (ARM_AM::getSOImmVal(~CVal) != -1)
5317 if (Subtarget->isThumb1Only()) {
5318 // This must be a constant between -7 and 7,
5319 // for 3-operand ADD/SUB immediate instructions.
5320 if (CVal >= -7 && CVal < 7)
5322 } else if (Subtarget->isThumb2()) {
5323 // A constant whose negation can be used as an immediate value in a
5324 // data-processing instruction. This can be used in GCC with an "n"
5325 // modifier that prints the negated value, for use with SUB
5326 // instructions. It is not useful otherwise but is implemented for
5328 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
5331 // A constant whose negation can be used as an immediate value in a
5332 // data-processing instruction. This can be used in GCC with an "n"
5333 // modifier that prints the negated value, for use with SUB
5334 // instructions. It is not useful otherwise but is implemented for
5336 if (ARM_AM::getSOImmVal(-CVal) != -1)
5342 if (Subtarget->isThumb()) { // FIXME thumb2
5343 // This must be a multiple of 4 between 0 and 1020, for
5344 // ADD sp + immediate.
5345 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
5348 // A power of two or a constant between 0 and 32. This is used in
5349 // GCC for the shift amount on shifted register operands, but it is
5350 // useful in general for any shift amounts.
5351 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
5357 if (Subtarget->isThumb()) { // FIXME thumb2
5358 // This must be a constant between 0 and 31, for shift amounts.
5359 if (CVal >= 0 && CVal <= 31)
5365 if (Subtarget->isThumb()) { // FIXME thumb2
5366 // This must be a multiple of 4 between -508 and 508, for
5367 // ADD/SUB sp = sp + immediate.
5368 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
5373 Result = DAG.getTargetConstant(CVal, Op.getValueType());
5377 if (Result.getNode()) {
5378 Ops.push_back(Result);
5381 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
5385 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
5386 // The ARM target isn't yet aware of offsets.
5390 int ARM::getVFPf32Imm(const APFloat &FPImm) {
5391 APInt Imm = FPImm.bitcastToAPInt();
5392 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
5393 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127
5394 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits
5396 // We can handle 4 bits of mantissa.
5397 // mantissa = (16+UInt(e:f:g:h))/16.
5398 if (Mantissa & 0x7ffff)
5401 if ((Mantissa & 0xf) != Mantissa)
5404 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
5405 if (Exp < -3 || Exp > 4)
5407 Exp = ((Exp+3) & 0x7) ^ 4;
5409 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
5412 int ARM::getVFPf64Imm(const APFloat &FPImm) {
5413 APInt Imm = FPImm.bitcastToAPInt();
5414 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
5415 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
5416 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffLL;
5418 // We can handle 4 bits of mantissa.
5419 // mantissa = (16+UInt(e:f:g:h))/16.
5420 if (Mantissa & 0xffffffffffffLL)
5423 if ((Mantissa & 0xf) != Mantissa)
5426 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
5427 if (Exp < -3 || Exp > 4)
5429 Exp = ((Exp+3) & 0x7) ^ 4;
5431 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
5434 bool ARM::isBitFieldInvertedMask(unsigned v) {
5435 if (v == 0xffffffff)
5437 // there can be 1's on either or both "outsides", all the "inside"
5439 unsigned int lsb = 0, msb = 31;
5440 while (v & (1 << msb)) --msb;
5441 while (v & (1 << lsb)) ++lsb;
5442 for (unsigned int i = lsb; i <= msb; ++i) {
5449 /// isFPImmLegal - Returns true if the target can instruction select the
5450 /// specified FP immediate natively. If false, the legalizer will
5451 /// materialize the FP immediate as a load from a constant pool.
5452 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
5453 if (!Subtarget->hasVFP3())
5456 return ARM::getVFPf32Imm(Imm) != -1;
5458 return ARM::getVFPf64Imm(Imm) != -1;