1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "ARMAddressingModes.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMISelLowering.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMPerfectShuffle.h"
21 #include "ARMRegisterInfo.h"
22 #include "ARMSubtarget.h"
23 #include "ARMTargetMachine.h"
24 #include "ARMTargetObjectFile.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/Constants.h"
27 #include "llvm/Function.h"
28 #include "llvm/GlobalValue.h"
29 #include "llvm/Instruction.h"
30 #include "llvm/Intrinsics.h"
31 #include "llvm/Type.h"
32 #include "llvm/CodeGen/CallingConvLower.h"
33 #include "llvm/CodeGen/MachineBasicBlock.h"
34 #include "llvm/CodeGen/MachineFrameInfo.h"
35 #include "llvm/CodeGen/MachineFunction.h"
36 #include "llvm/CodeGen/MachineInstrBuilder.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/PseudoSourceValue.h"
39 #include "llvm/CodeGen/SelectionDAG.h"
40 #include "llvm/Target/TargetOptions.h"
41 #include "llvm/ADT/VectorExtras.h"
42 #include "llvm/Support/CommandLine.h"
43 #include "llvm/Support/ErrorHandling.h"
44 #include "llvm/Support/MathExtras.h"
45 #include "llvm/Support/raw_ostream.h"
49 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
50 CCValAssign::LocInfo &LocInfo,
51 ISD::ArgFlagsTy &ArgFlags,
53 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
54 CCValAssign::LocInfo &LocInfo,
55 ISD::ArgFlagsTy &ArgFlags,
57 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
58 CCValAssign::LocInfo &LocInfo,
59 ISD::ArgFlagsTy &ArgFlags,
61 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
62 CCValAssign::LocInfo &LocInfo,
63 ISD::ArgFlagsTy &ArgFlags,
66 void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
67 EVT PromotedBitwiseVT) {
68 if (VT != PromotedLdStVT) {
69 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
70 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
71 PromotedLdStVT.getSimpleVT());
73 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
74 AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
75 PromotedLdStVT.getSimpleVT());
78 EVT ElemTy = VT.getVectorElementType();
79 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
80 setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
81 if (ElemTy == MVT::i8 || ElemTy == MVT::i16)
82 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
83 if (ElemTy != MVT::i32) {
84 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
85 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand);
86 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand);
87 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand);
89 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
90 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
91 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Custom);
92 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Expand);
94 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
95 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
96 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
99 // Promote all bit-wise operations.
100 if (VT.isInteger() && VT != PromotedBitwiseVT) {
101 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
102 AddPromotedToType (ISD::AND, VT.getSimpleVT(),
103 PromotedBitwiseVT.getSimpleVT());
104 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
105 AddPromotedToType (ISD::OR, VT.getSimpleVT(),
106 PromotedBitwiseVT.getSimpleVT());
107 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
108 AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
109 PromotedBitwiseVT.getSimpleVT());
112 // Neon does not support vector divide/remainder operations.
113 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
114 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
115 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand);
116 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
117 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
118 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
121 void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
122 addRegisterClass(VT, ARM::DPRRegisterClass);
123 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
126 void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
127 addRegisterClass(VT, ARM::QPRRegisterClass);
128 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
131 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
132 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
133 return new TargetLoweringObjectFileMachO();
134 return new ARMElfTargetObjectFile();
137 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
138 : TargetLowering(TM, createTLOF(TM)) {
139 Subtarget = &TM.getSubtarget<ARMSubtarget>();
141 if (Subtarget->isTargetDarwin()) {
142 // Uses VFP for Thumb libfuncs if available.
143 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
144 // Single-precision floating-point arithmetic.
145 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
146 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
147 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
148 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
150 // Double-precision floating-point arithmetic.
151 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
152 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
153 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
154 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
156 // Single-precision comparisons.
157 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
158 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
159 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
160 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
161 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
162 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
163 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
164 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
166 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
167 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
168 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
169 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
170 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
171 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
172 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
173 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
175 // Double-precision comparisons.
176 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
177 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
178 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
179 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
180 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
181 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
182 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
183 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
185 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
186 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
187 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
188 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
189 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
190 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
191 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
192 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
194 // Floating-point to integer conversions.
195 // i64 conversions are done via library routines even when generating VFP
196 // instructions, so use the same ones.
197 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
198 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
199 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
200 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
202 // Conversions between floating types.
203 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
204 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
206 // Integer to floating-point conversions.
207 // i64 conversions are done via library routines even when generating VFP
208 // instructions, so use the same ones.
209 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
210 // e.g., __floatunsidf vs. __floatunssidfvfp.
211 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
212 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
213 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
214 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
218 // These libcalls are not available in 32-bit.
219 setLibcallName(RTLIB::SHL_I128, 0);
220 setLibcallName(RTLIB::SRL_I128, 0);
221 setLibcallName(RTLIB::SRA_I128, 0);
223 // Libcalls should use the AAPCS base standard ABI, even if hard float
224 // is in effect, as per the ARM RTABI specification, section 4.1.2.
225 if (Subtarget->isAAPCS_ABI()) {
226 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
227 setLibcallCallingConv(static_cast<RTLIB::Libcall>(i),
228 CallingConv::ARM_AAPCS);
232 if (Subtarget->isThumb1Only())
233 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
235 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
236 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
237 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
238 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
240 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
243 if (Subtarget->hasNEON()) {
244 addDRTypeForNEON(MVT::v2f32);
245 addDRTypeForNEON(MVT::v8i8);
246 addDRTypeForNEON(MVT::v4i16);
247 addDRTypeForNEON(MVT::v2i32);
248 addDRTypeForNEON(MVT::v1i64);
250 addQRTypeForNEON(MVT::v4f32);
251 addQRTypeForNEON(MVT::v2f64);
252 addQRTypeForNEON(MVT::v16i8);
253 addQRTypeForNEON(MVT::v8i16);
254 addQRTypeForNEON(MVT::v4i32);
255 addQRTypeForNEON(MVT::v2i64);
257 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
258 // neither Neon nor VFP support any arithmetic operations on it.
259 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
260 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
261 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
262 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
263 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
264 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
265 setOperationAction(ISD::VSETCC, MVT::v2f64, Expand);
266 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
267 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
268 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
269 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
270 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
271 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
272 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
273 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
274 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
275 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
276 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
277 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
278 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
279 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
280 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
281 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
282 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
284 // Neon does not support some operations on v1i64 and v2i64 types.
285 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
286 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
287 setOperationAction(ISD::VSETCC, MVT::v1i64, Expand);
288 setOperationAction(ISD::VSETCC, MVT::v2i64, Expand);
290 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
291 setTargetDAGCombine(ISD::SHL);
292 setTargetDAGCombine(ISD::SRL);
293 setTargetDAGCombine(ISD::SRA);
294 setTargetDAGCombine(ISD::SIGN_EXTEND);
295 setTargetDAGCombine(ISD::ZERO_EXTEND);
296 setTargetDAGCombine(ISD::ANY_EXTEND);
299 computeRegisterProperties();
301 // ARM does not have f32 extending load.
302 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
304 // ARM does not have i1 sign extending load.
305 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
307 // ARM supports all 4 flavors of integer indexed load / store.
308 if (!Subtarget->isThumb1Only()) {
309 for (unsigned im = (unsigned)ISD::PRE_INC;
310 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
311 setIndexedLoadAction(im, MVT::i1, Legal);
312 setIndexedLoadAction(im, MVT::i8, Legal);
313 setIndexedLoadAction(im, MVT::i16, Legal);
314 setIndexedLoadAction(im, MVT::i32, Legal);
315 setIndexedStoreAction(im, MVT::i1, Legal);
316 setIndexedStoreAction(im, MVT::i8, Legal);
317 setIndexedStoreAction(im, MVT::i16, Legal);
318 setIndexedStoreAction(im, MVT::i32, Legal);
322 // i64 operation support.
323 if (Subtarget->isThumb1Only()) {
324 setOperationAction(ISD::MUL, MVT::i64, Expand);
325 setOperationAction(ISD::MULHU, MVT::i32, Expand);
326 setOperationAction(ISD::MULHS, MVT::i32, Expand);
327 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
328 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
330 setOperationAction(ISD::MUL, MVT::i64, Expand);
331 setOperationAction(ISD::MULHU, MVT::i32, Expand);
332 if (!Subtarget->hasV6Ops())
333 setOperationAction(ISD::MULHS, MVT::i32, Expand);
335 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
336 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
337 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
338 setOperationAction(ISD::SRL, MVT::i64, Custom);
339 setOperationAction(ISD::SRA, MVT::i64, Custom);
341 // ARM does not have ROTL.
342 setOperationAction(ISD::ROTL, MVT::i32, Expand);
343 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
344 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
345 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
346 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
348 // Only ARMv6 has BSWAP.
349 if (!Subtarget->hasV6Ops())
350 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
352 // These are expanded into libcalls.
353 setOperationAction(ISD::SDIV, MVT::i32, Expand);
354 setOperationAction(ISD::UDIV, MVT::i32, Expand);
355 setOperationAction(ISD::SREM, MVT::i32, Expand);
356 setOperationAction(ISD::UREM, MVT::i32, Expand);
357 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
358 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
360 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
361 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
362 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
363 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
364 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
366 // Use the default implementation.
367 setOperationAction(ISD::VASTART, MVT::Other, Custom);
368 setOperationAction(ISD::VAARG, MVT::Other, Expand);
369 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
370 setOperationAction(ISD::VAEND, MVT::Other, Expand);
371 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
372 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
373 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
374 // FIXME: Shouldn't need this, since no register is used, but the legalizer
375 // doesn't yet know how to not do that for SjLj.
376 setExceptionSelectorRegister(ARM::R0);
377 if (Subtarget->isThumb())
378 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
380 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
381 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
383 if (!Subtarget->hasV6Ops() && !Subtarget->isThumb2()) {
384 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
385 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
387 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
389 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only())
390 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
391 // iff target supports vfp2.
392 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
394 // We want to custom lower some of our intrinsics.
395 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
397 setOperationAction(ISD::SETCC, MVT::i32, Expand);
398 setOperationAction(ISD::SETCC, MVT::f32, Expand);
399 setOperationAction(ISD::SETCC, MVT::f64, Expand);
400 setOperationAction(ISD::SELECT, MVT::i32, Expand);
401 setOperationAction(ISD::SELECT, MVT::f32, Expand);
402 setOperationAction(ISD::SELECT, MVT::f64, Expand);
403 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
404 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
405 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
407 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
408 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
409 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
410 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
411 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
413 // We don't support sin/cos/fmod/copysign/pow
414 setOperationAction(ISD::FSIN, MVT::f64, Expand);
415 setOperationAction(ISD::FSIN, MVT::f32, Expand);
416 setOperationAction(ISD::FCOS, MVT::f32, Expand);
417 setOperationAction(ISD::FCOS, MVT::f64, Expand);
418 setOperationAction(ISD::FREM, MVT::f64, Expand);
419 setOperationAction(ISD::FREM, MVT::f32, Expand);
420 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
421 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
422 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
424 setOperationAction(ISD::FPOW, MVT::f64, Expand);
425 setOperationAction(ISD::FPOW, MVT::f32, Expand);
427 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
428 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
429 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
430 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
431 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
432 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
435 // We have target-specific dag combine patterns for the following nodes:
436 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
437 setTargetDAGCombine(ISD::ADD);
438 setTargetDAGCombine(ISD::SUB);
440 setStackPointerRegisterToSaveRestore(ARM::SP);
441 setSchedulingPreference(SchedulingForRegPressure);
443 // FIXME: If-converter should use instruction latency to determine
444 // profitability rather than relying on fixed limits.
445 if (Subtarget->getCPUString() == "generic") {
446 // Generic (and overly aggressive) if-conversion limits.
447 setIfCvtBlockSizeLimit(10);
448 setIfCvtDupBlockSizeLimit(2);
449 } else if (Subtarget->hasV6Ops()) {
450 setIfCvtBlockSizeLimit(2);
451 setIfCvtDupBlockSizeLimit(1);
453 setIfCvtBlockSizeLimit(3);
454 setIfCvtDupBlockSizeLimit(2);
457 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
458 // Do not enable CodePlacementOpt for now: it currently runs after the
459 // ARMConstantIslandPass and messes up branch relaxation and placement
460 // of constant islands.
461 // benefitFromCodePlacementOpt = true;
464 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
467 case ARMISD::Wrapper: return "ARMISD::Wrapper";
468 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
469 case ARMISD::CALL: return "ARMISD::CALL";
470 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
471 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
472 case ARMISD::tCALL: return "ARMISD::tCALL";
473 case ARMISD::BRCOND: return "ARMISD::BRCOND";
474 case ARMISD::BR_JT: return "ARMISD::BR_JT";
475 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
476 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
477 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
478 case ARMISD::CMP: return "ARMISD::CMP";
479 case ARMISD::CMPZ: return "ARMISD::CMPZ";
480 case ARMISD::CMPFP: return "ARMISD::CMPFP";
481 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
482 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
483 case ARMISD::CMOV: return "ARMISD::CMOV";
484 case ARMISD::CNEG: return "ARMISD::CNEG";
486 case ARMISD::RBIT: return "ARMISD::RBIT";
488 case ARMISD::FTOSI: return "ARMISD::FTOSI";
489 case ARMISD::FTOUI: return "ARMISD::FTOUI";
490 case ARMISD::SITOF: return "ARMISD::SITOF";
491 case ARMISD::UITOF: return "ARMISD::UITOF";
493 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
494 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
495 case ARMISD::RRX: return "ARMISD::RRX";
497 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
498 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
500 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
501 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
503 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
505 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
507 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER";
508 case ARMISD::SYNCBARRIER: return "ARMISD::SYNCBARRIER";
510 case ARMISD::VCEQ: return "ARMISD::VCEQ";
511 case ARMISD::VCGE: return "ARMISD::VCGE";
512 case ARMISD::VCGEU: return "ARMISD::VCGEU";
513 case ARMISD::VCGT: return "ARMISD::VCGT";
514 case ARMISD::VCGTU: return "ARMISD::VCGTU";
515 case ARMISD::VTST: return "ARMISD::VTST";
517 case ARMISD::VSHL: return "ARMISD::VSHL";
518 case ARMISD::VSHRs: return "ARMISD::VSHRs";
519 case ARMISD::VSHRu: return "ARMISD::VSHRu";
520 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
521 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
522 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
523 case ARMISD::VSHRN: return "ARMISD::VSHRN";
524 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
525 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
526 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
527 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
528 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
529 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
530 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
531 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
532 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
533 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
534 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
535 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
536 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
537 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
538 case ARMISD::VDUP: return "ARMISD::VDUP";
539 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
540 case ARMISD::VEXT: return "ARMISD::VEXT";
541 case ARMISD::VREV64: return "ARMISD::VREV64";
542 case ARMISD::VREV32: return "ARMISD::VREV32";
543 case ARMISD::VREV16: return "ARMISD::VREV16";
544 case ARMISD::VZIP: return "ARMISD::VZIP";
545 case ARMISD::VUZP: return "ARMISD::VUZP";
546 case ARMISD::VTRN: return "ARMISD::VTRN";
550 /// getFunctionAlignment - Return the Log2 alignment of this function.
551 unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
552 return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 0 : 1;
555 //===----------------------------------------------------------------------===//
557 //===----------------------------------------------------------------------===//
559 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
560 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
562 default: llvm_unreachable("Unknown condition code!");
563 case ISD::SETNE: return ARMCC::NE;
564 case ISD::SETEQ: return ARMCC::EQ;
565 case ISD::SETGT: return ARMCC::GT;
566 case ISD::SETGE: return ARMCC::GE;
567 case ISD::SETLT: return ARMCC::LT;
568 case ISD::SETLE: return ARMCC::LE;
569 case ISD::SETUGT: return ARMCC::HI;
570 case ISD::SETUGE: return ARMCC::HS;
571 case ISD::SETULT: return ARMCC::LO;
572 case ISD::SETULE: return ARMCC::LS;
576 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
577 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
578 ARMCC::CondCodes &CondCode2) {
579 CondCode2 = ARMCC::AL;
581 default: llvm_unreachable("Unknown FP condition!");
583 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
585 case ISD::SETOGT: CondCode = ARMCC::GT; break;
587 case ISD::SETOGE: CondCode = ARMCC::GE; break;
588 case ISD::SETOLT: CondCode = ARMCC::MI; break;
589 case ISD::SETOLE: CondCode = ARMCC::LS; break;
590 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
591 case ISD::SETO: CondCode = ARMCC::VC; break;
592 case ISD::SETUO: CondCode = ARMCC::VS; break;
593 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
594 case ISD::SETUGT: CondCode = ARMCC::HI; break;
595 case ISD::SETUGE: CondCode = ARMCC::PL; break;
597 case ISD::SETULT: CondCode = ARMCC::LT; break;
599 case ISD::SETULE: CondCode = ARMCC::LE; break;
601 case ISD::SETUNE: CondCode = ARMCC::NE; break;
605 //===----------------------------------------------------------------------===//
606 // Calling Convention Implementation
607 //===----------------------------------------------------------------------===//
609 #include "ARMGenCallingConv.inc"
611 // APCS f64 is in register pairs, possibly split to stack
612 static bool f64AssignAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
613 CCValAssign::LocInfo &LocInfo,
614 CCState &State, bool CanFail) {
615 static const unsigned RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
617 // Try to get the first register.
618 if (unsigned Reg = State.AllocateReg(RegList, 4))
619 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
621 // For the 2nd half of a v2f64, do not fail.
625 // Put the whole thing on the stack.
626 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
627 State.AllocateStack(8, 4),
632 // Try to get the second register.
633 if (unsigned Reg = State.AllocateReg(RegList, 4))
634 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
636 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
637 State.AllocateStack(4, 4),
642 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
643 CCValAssign::LocInfo &LocInfo,
644 ISD::ArgFlagsTy &ArgFlags,
646 if (!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
648 if (LocVT == MVT::v2f64 &&
649 !f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
651 return true; // we handled it
654 // AAPCS f64 is in aligned register pairs
655 static bool f64AssignAAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
656 CCValAssign::LocInfo &LocInfo,
657 CCState &State, bool CanFail) {
658 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
659 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
661 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
663 // For the 2nd half of a v2f64, do not just fail.
667 // Put the whole thing on the stack.
668 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
669 State.AllocateStack(8, 8),
675 for (i = 0; i < 2; ++i)
676 if (HiRegList[i] == Reg)
679 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
680 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
685 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
686 CCValAssign::LocInfo &LocInfo,
687 ISD::ArgFlagsTy &ArgFlags,
689 if (!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
691 if (LocVT == MVT::v2f64 &&
692 !f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
694 return true; // we handled it
697 static bool f64RetAssign(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
698 CCValAssign::LocInfo &LocInfo, CCState &State) {
699 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
700 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
702 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
704 return false; // we didn't handle it
707 for (i = 0; i < 2; ++i)
708 if (HiRegList[i] == Reg)
711 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
712 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
717 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
718 CCValAssign::LocInfo &LocInfo,
719 ISD::ArgFlagsTy &ArgFlags,
721 if (!f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
723 if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
725 return true; // we handled it
728 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
729 CCValAssign::LocInfo &LocInfo,
730 ISD::ArgFlagsTy &ArgFlags,
732 return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags,
736 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
737 /// given CallingConvention value.
738 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
740 bool isVarArg) const {
743 llvm_unreachable("Unsupported calling convention");
745 case CallingConv::Fast:
746 // Use target triple & subtarget features to do actual dispatch.
747 if (Subtarget->isAAPCS_ABI()) {
748 if (Subtarget->hasVFP2() &&
749 FloatABIType == FloatABI::Hard && !isVarArg)
750 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
752 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
754 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
755 case CallingConv::ARM_AAPCS_VFP:
756 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
757 case CallingConv::ARM_AAPCS:
758 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
759 case CallingConv::ARM_APCS:
760 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
764 /// LowerCallResult - Lower the result values of a call into the
765 /// appropriate copies out of appropriate physical registers.
767 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
768 CallingConv::ID CallConv, bool isVarArg,
769 const SmallVectorImpl<ISD::InputArg> &Ins,
770 DebugLoc dl, SelectionDAG &DAG,
771 SmallVectorImpl<SDValue> &InVals) {
773 // Assign locations to each value returned by this call.
774 SmallVector<CCValAssign, 16> RVLocs;
775 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
776 RVLocs, *DAG.getContext());
777 CCInfo.AnalyzeCallResult(Ins,
778 CCAssignFnForNode(CallConv, /* Return*/ true,
781 // Copy all of the result registers out of their specified physreg.
782 for (unsigned i = 0; i != RVLocs.size(); ++i) {
783 CCValAssign VA = RVLocs[i];
786 if (VA.needsCustom()) {
787 // Handle f64 or half of a v2f64.
788 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
790 Chain = Lo.getValue(1);
791 InFlag = Lo.getValue(2);
792 VA = RVLocs[++i]; // skip ahead to next loc
793 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
795 Chain = Hi.getValue(1);
796 InFlag = Hi.getValue(2);
797 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
799 if (VA.getLocVT() == MVT::v2f64) {
800 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
801 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
802 DAG.getConstant(0, MVT::i32));
804 VA = RVLocs[++i]; // skip ahead to next loc
805 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
806 Chain = Lo.getValue(1);
807 InFlag = Lo.getValue(2);
808 VA = RVLocs[++i]; // skip ahead to next loc
809 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
810 Chain = Hi.getValue(1);
811 InFlag = Hi.getValue(2);
812 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
813 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
814 DAG.getConstant(1, MVT::i32));
817 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
819 Chain = Val.getValue(1);
820 InFlag = Val.getValue(2);
823 switch (VA.getLocInfo()) {
824 default: llvm_unreachable("Unknown loc info!");
825 case CCValAssign::Full: break;
826 case CCValAssign::BCvt:
827 Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val);
831 InVals.push_back(Val);
837 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
838 /// by "Src" to address "Dst" of size "Size". Alignment information is
839 /// specified by the specific parameter attribute. The copy will be passed as
840 /// a byval function parameter.
841 /// Sometimes what we are copying is the end of a larger object, the part that
842 /// does not fit in registers.
844 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
845 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
847 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
848 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
849 /*AlwaysInline=*/false, NULL, 0, NULL, 0);
852 /// LowerMemOpCallTo - Store the argument to the stack.
854 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
855 SDValue StackPtr, SDValue Arg,
856 DebugLoc dl, SelectionDAG &DAG,
857 const CCValAssign &VA,
858 ISD::ArgFlagsTy Flags) {
859 unsigned LocMemOffset = VA.getLocMemOffset();
860 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
861 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
862 if (Flags.isByVal()) {
863 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
865 return DAG.getStore(Chain, dl, Arg, PtrOff,
866 PseudoSourceValue::getStack(), LocMemOffset);
869 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
870 SDValue Chain, SDValue &Arg,
871 RegsToPassVector &RegsToPass,
872 CCValAssign &VA, CCValAssign &NextVA,
874 SmallVector<SDValue, 8> &MemOpChains,
875 ISD::ArgFlagsTy Flags) {
877 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
878 DAG.getVTList(MVT::i32, MVT::i32), Arg);
879 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
881 if (NextVA.isRegLoc())
882 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
884 assert(NextVA.isMemLoc());
885 if (StackPtr.getNode() == 0)
886 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
888 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
894 /// LowerCall - Lowering a call into a callseq_start <-
895 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
898 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
899 CallingConv::ID CallConv, bool isVarArg,
901 const SmallVectorImpl<ISD::OutputArg> &Outs,
902 const SmallVectorImpl<ISD::InputArg> &Ins,
903 DebugLoc dl, SelectionDAG &DAG,
904 SmallVectorImpl<SDValue> &InVals) {
905 // ARM target does not yet support tail call optimization.
908 // Analyze operands of the call, assigning locations to each operand.
909 SmallVector<CCValAssign, 16> ArgLocs;
910 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
912 CCInfo.AnalyzeCallOperands(Outs,
913 CCAssignFnForNode(CallConv, /* Return*/ false,
916 // Get a count of how many bytes are to be pushed on the stack.
917 unsigned NumBytes = CCInfo.getNextStackOffset();
919 // Adjust the stack pointer for the new arguments...
920 // These operations are automatically eliminated by the prolog/epilog pass
921 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
923 SDValue StackPtr = DAG.getRegister(ARM::SP, MVT::i32);
925 RegsToPassVector RegsToPass;
926 SmallVector<SDValue, 8> MemOpChains;
928 // Walk the register/memloc assignments, inserting copies/loads. In the case
929 // of tail call optimization, arguments are handled later.
930 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
933 CCValAssign &VA = ArgLocs[i];
934 SDValue Arg = Outs[realArgIdx].Val;
935 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
937 // Promote the value if needed.
938 switch (VA.getLocInfo()) {
939 default: llvm_unreachable("Unknown loc info!");
940 case CCValAssign::Full: break;
941 case CCValAssign::SExt:
942 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
944 case CCValAssign::ZExt:
945 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
947 case CCValAssign::AExt:
948 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
950 case CCValAssign::BCvt:
951 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
955 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
956 if (VA.needsCustom()) {
957 if (VA.getLocVT() == MVT::v2f64) {
958 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
959 DAG.getConstant(0, MVT::i32));
960 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
961 DAG.getConstant(1, MVT::i32));
963 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
964 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
966 VA = ArgLocs[++i]; // skip ahead to next loc
968 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
969 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
971 assert(VA.isMemLoc());
972 if (StackPtr.getNode() == 0)
973 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
975 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
976 dl, DAG, VA, Flags));
979 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
980 StackPtr, MemOpChains, Flags);
982 } else if (VA.isRegLoc()) {
983 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
985 assert(VA.isMemLoc());
986 if (StackPtr.getNode() == 0)
987 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
989 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
990 dl, DAG, VA, Flags));
994 if (!MemOpChains.empty())
995 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
996 &MemOpChains[0], MemOpChains.size());
998 // Build a sequence of copy-to-reg nodes chained together with token chain
999 // and flag operands which copy the outgoing args into the appropriate regs.
1001 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1002 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1003 RegsToPass[i].second, InFlag);
1004 InFlag = Chain.getValue(1);
1007 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1008 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1009 // node so that legalize doesn't hack it.
1010 bool isDirect = false;
1011 bool isARMFunc = false;
1012 bool isLocalARMFunc = false;
1013 MachineFunction &MF = DAG.getMachineFunction();
1014 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1015 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1016 GlobalValue *GV = G->getGlobal();
1018 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1019 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
1020 getTargetMachine().getRelocationModel() != Reloc::Static;
1021 isARMFunc = !Subtarget->isThumb() || isStub;
1022 // ARM call to a local ARM function is predicable.
1023 isLocalARMFunc = !Subtarget->isThumb() && !isExt;
1024 // tBX takes a register source operand.
1025 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1026 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1027 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1030 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1031 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1032 Callee = DAG.getLoad(getPointerTy(), dl,
1033 DAG.getEntryNode(), CPAddr,
1034 PseudoSourceValue::getConstantPool(), 0);
1035 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1036 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1037 getPointerTy(), Callee, PICLabel);
1039 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy());
1040 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1042 bool isStub = Subtarget->isTargetDarwin() &&
1043 getTargetMachine().getRelocationModel() != Reloc::Static;
1044 isARMFunc = !Subtarget->isThumb() || isStub;
1045 // tBX takes a register source operand.
1046 const char *Sym = S->getSymbol();
1047 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1048 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1049 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1050 Sym, ARMPCLabelIndex, 4);
1051 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1052 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1053 Callee = DAG.getLoad(getPointerTy(), dl,
1054 DAG.getEntryNode(), CPAddr,
1055 PseudoSourceValue::getConstantPool(), 0);
1056 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1057 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1058 getPointerTy(), Callee, PICLabel);
1060 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
1063 // FIXME: handle tail calls differently.
1065 if (Subtarget->isThumb()) {
1066 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1067 CallOpc = ARMISD::CALL_NOLINK;
1069 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1071 CallOpc = (isDirect || Subtarget->hasV5TOps())
1072 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
1073 : ARMISD::CALL_NOLINK;
1075 if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb1Only()) {
1076 // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK
1077 Chain = DAG.getCopyToReg(Chain, dl, ARM::LR, DAG.getUNDEF(MVT::i32),InFlag);
1078 InFlag = Chain.getValue(1);
1081 std::vector<SDValue> Ops;
1082 Ops.push_back(Chain);
1083 Ops.push_back(Callee);
1085 // Add argument registers to the end of the list so that they are known live
1087 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1088 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1089 RegsToPass[i].second.getValueType()));
1091 if (InFlag.getNode())
1092 Ops.push_back(InFlag);
1093 // Returns a chain and a flag for retval copy to use.
1094 Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(MVT::Other, MVT::Flag),
1095 &Ops[0], Ops.size());
1096 InFlag = Chain.getValue(1);
1098 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1099 DAG.getIntPtrConstant(0, true), InFlag);
1101 InFlag = Chain.getValue(1);
1103 // Handle result values, copying them out of physregs into vregs that we
1105 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1110 ARMTargetLowering::LowerReturn(SDValue Chain,
1111 CallingConv::ID CallConv, bool isVarArg,
1112 const SmallVectorImpl<ISD::OutputArg> &Outs,
1113 DebugLoc dl, SelectionDAG &DAG) {
1115 // CCValAssign - represent the assignment of the return value to a location.
1116 SmallVector<CCValAssign, 16> RVLocs;
1118 // CCState - Info about the registers and stack slots.
1119 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
1122 // Analyze outgoing return values.
1123 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1126 // If this is the first return lowered for this function, add
1127 // the regs to the liveout set for the function.
1128 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1129 for (unsigned i = 0; i != RVLocs.size(); ++i)
1130 if (RVLocs[i].isRegLoc())
1131 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1136 // Copy the result values into the output registers.
1137 for (unsigned i = 0, realRVLocIdx = 0;
1139 ++i, ++realRVLocIdx) {
1140 CCValAssign &VA = RVLocs[i];
1141 assert(VA.isRegLoc() && "Can only return in registers!");
1143 SDValue Arg = Outs[realRVLocIdx].Val;
1145 switch (VA.getLocInfo()) {
1146 default: llvm_unreachable("Unknown loc info!");
1147 case CCValAssign::Full: break;
1148 case CCValAssign::BCvt:
1149 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1153 if (VA.needsCustom()) {
1154 if (VA.getLocVT() == MVT::v2f64) {
1155 // Extract the first half and return it in two registers.
1156 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1157 DAG.getConstant(0, MVT::i32));
1158 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
1159 DAG.getVTList(MVT::i32, MVT::i32), Half);
1161 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1162 Flag = Chain.getValue(1);
1163 VA = RVLocs[++i]; // skip ahead to next loc
1164 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1165 HalfGPRs.getValue(1), Flag);
1166 Flag = Chain.getValue(1);
1167 VA = RVLocs[++i]; // skip ahead to next loc
1169 // Extract the 2nd half and fall through to handle it as an f64 value.
1170 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1171 DAG.getConstant(1, MVT::i32));
1173 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1175 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1176 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1177 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1178 Flag = Chain.getValue(1);
1179 VA = RVLocs[++i]; // skip ahead to next loc
1180 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1183 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1185 // Guarantee that all emitted copies are
1186 // stuck together, avoiding something bad.
1187 Flag = Chain.getValue(1);
1192 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1194 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1199 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1200 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1201 // one of the above mentioned nodes. It has to be wrapped because otherwise
1202 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1203 // be used to form addressing mode. These wrapped nodes will be selected
1205 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1206 EVT PtrVT = Op.getValueType();
1207 // FIXME there is no actual debug info here
1208 DebugLoc dl = Op.getDebugLoc();
1209 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1211 if (CP->isMachineConstantPoolEntry())
1212 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1213 CP->getAlignment());
1215 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1216 CP->getAlignment());
1217 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1220 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) {
1221 MachineFunction &MF = DAG.getMachineFunction();
1222 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1223 unsigned ARMPCLabelIndex = 0;
1224 DebugLoc DL = Op.getDebugLoc();
1225 EVT PtrVT = getPointerTy();
1226 BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1227 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1229 if (RelocM == Reloc::Static) {
1230 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
1232 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1233 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1234 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(BA, ARMPCLabelIndex,
1235 ARMCP::CPBlockAddress,
1237 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1239 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
1240 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
1241 PseudoSourceValue::getConstantPool(), 0);
1242 if (RelocM == Reloc::Static)
1244 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1245 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
1248 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
1250 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1251 SelectionDAG &DAG) {
1252 DebugLoc dl = GA->getDebugLoc();
1253 EVT PtrVT = getPointerTy();
1254 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1255 MachineFunction &MF = DAG.getMachineFunction();
1256 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1257 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1258 ARMConstantPoolValue *CPV =
1259 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1260 ARMCP::CPValue, PCAdj, "tlsgd", true);
1261 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1262 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
1263 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
1264 PseudoSourceValue::getConstantPool(), 0);
1265 SDValue Chain = Argument.getValue(1);
1267 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1268 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
1270 // call __tls_get_addr.
1273 Entry.Node = Argument;
1274 Entry.Ty = (const Type *) Type::getInt32Ty(*DAG.getContext());
1275 Args.push_back(Entry);
1276 // FIXME: is there useful debug info available here?
1277 std::pair<SDValue, SDValue> CallResult =
1278 LowerCallTo(Chain, (const Type *) Type::getInt32Ty(*DAG.getContext()),
1279 false, false, false, false,
1280 0, CallingConv::C, false, /*isReturnValueUsed=*/true,
1281 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl,
1282 DAG.GetOrdering(Chain.getNode()));
1283 return CallResult.first;
1286 // Lower ISD::GlobalTLSAddress using the "initial exec" or
1287 // "local exec" model.
1289 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
1290 SelectionDAG &DAG) {
1291 GlobalValue *GV = GA->getGlobal();
1292 DebugLoc dl = GA->getDebugLoc();
1294 SDValue Chain = DAG.getEntryNode();
1295 EVT PtrVT = getPointerTy();
1296 // Get the Thread Pointer
1297 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1299 if (GV->isDeclaration()) {
1300 MachineFunction &MF = DAG.getMachineFunction();
1301 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1302 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1303 // Initial exec model.
1304 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1305 ARMConstantPoolValue *CPV =
1306 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1307 ARMCP::CPValue, PCAdj, "gottpoff", true);
1308 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1309 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1310 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1311 PseudoSourceValue::getConstantPool(), 0);
1312 Chain = Offset.getValue(1);
1314 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1315 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
1317 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1318 PseudoSourceValue::getConstantPool(), 0);
1321 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, "tpoff");
1322 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1323 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1324 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1325 PseudoSourceValue::getConstantPool(), 0);
1328 // The address of the thread local variable is the add of the thread
1329 // pointer with the offset of the variable.
1330 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
1334 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
1335 // TODO: implement the "local dynamic" model
1336 assert(Subtarget->isTargetELF() &&
1337 "TLS not implemented for non-ELF targets");
1338 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1339 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
1340 // otherwise use the "Local Exec" TLS Model
1341 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
1342 return LowerToTLSGeneralDynamicModel(GA, DAG);
1344 return LowerToTLSExecModels(GA, DAG);
1347 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
1348 SelectionDAG &DAG) {
1349 EVT PtrVT = getPointerTy();
1350 DebugLoc dl = Op.getDebugLoc();
1351 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1352 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1353 if (RelocM == Reloc::PIC_) {
1354 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
1355 ARMConstantPoolValue *CPV =
1356 new ARMConstantPoolValue(GV, UseGOTOFF ? "GOTOFF" : "GOT");
1357 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1358 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1359 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1361 PseudoSourceValue::getConstantPool(), 0);
1362 SDValue Chain = Result.getValue(1);
1363 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1364 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
1366 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
1367 PseudoSourceValue::getGOT(), 0);
1370 // If we have T2 ops, we can materialize the address directly via movt/movw
1371 // pair. This is always cheaper.
1372 if (Subtarget->useMovt()) {
1373 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
1374 DAG.getTargetGlobalAddress(GV, PtrVT));
1376 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1377 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1378 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1379 PseudoSourceValue::getConstantPool(), 0);
1384 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
1385 SelectionDAG &DAG) {
1386 MachineFunction &MF = DAG.getMachineFunction();
1387 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1388 unsigned ARMPCLabelIndex = 0;
1389 EVT PtrVT = getPointerTy();
1390 DebugLoc dl = Op.getDebugLoc();
1391 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1392 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1394 if (RelocM == Reloc::Static)
1395 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1397 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1398 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8);
1399 ARMConstantPoolValue *CPV =
1400 new ARMConstantPoolValue(GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj);
1401 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1403 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1405 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1406 PseudoSourceValue::getConstantPool(), 0);
1407 SDValue Chain = Result.getValue(1);
1409 if (RelocM == Reloc::PIC_) {
1410 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1411 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1414 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
1415 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
1416 PseudoSourceValue::getGOT(), 0);
1421 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
1423 assert(Subtarget->isTargetELF() &&
1424 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
1425 MachineFunction &MF = DAG.getMachineFunction();
1426 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1427 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1428 EVT PtrVT = getPointerTy();
1429 DebugLoc dl = Op.getDebugLoc();
1430 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1431 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1432 "_GLOBAL_OFFSET_TABLE_",
1433 ARMPCLabelIndex, PCAdj);
1434 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1435 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1436 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1437 PseudoSourceValue::getConstantPool(), 0);
1438 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1439 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1443 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
1444 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1445 DebugLoc dl = Op.getDebugLoc();
1447 default: return SDValue(); // Don't custom lower most intrinsics.
1448 case Intrinsic::arm_thread_pointer: {
1449 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1450 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1452 case Intrinsic::eh_sjlj_lsda: {
1453 MachineFunction &MF = DAG.getMachineFunction();
1454 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1455 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1456 EVT PtrVT = getPointerTy();
1457 DebugLoc dl = Op.getDebugLoc();
1458 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1460 unsigned PCAdj = (RelocM != Reloc::PIC_)
1461 ? 0 : (Subtarget->isThumb() ? 4 : 8);
1462 ARMConstantPoolValue *CPV =
1463 new ARMConstantPoolValue(MF.getFunction(), ARMPCLabelIndex,
1464 ARMCP::CPLSDA, PCAdj);
1465 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1466 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1468 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1469 PseudoSourceValue::getConstantPool(), 0);
1470 SDValue Chain = Result.getValue(1);
1472 if (RelocM == Reloc::PIC_) {
1473 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1474 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1478 case Intrinsic::eh_sjlj_setjmp:
1479 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(1));
1483 static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG,
1484 const ARMSubtarget *Subtarget) {
1485 DebugLoc dl = Op.getDebugLoc();
1486 SDValue Op5 = Op.getOperand(5);
1488 unsigned isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue();
1489 if (isDeviceBarrier) {
1490 if (Subtarget->hasV7Ops())
1491 Res = DAG.getNode(ARMISD::SYNCBARRIER, dl, MVT::Other, Op.getOperand(0));
1493 Res = DAG.getNode(ARMISD::SYNCBARRIER, dl, MVT::Other, Op.getOperand(0),
1494 DAG.getConstant(0, MVT::i32));
1496 if (Subtarget->hasV7Ops())
1497 Res = DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
1499 Res = DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
1500 DAG.getConstant(0, MVT::i32));
1505 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
1506 unsigned VarArgsFrameIndex) {
1507 // vastart just stores the address of the VarArgsFrameIndex slot into the
1508 // memory location argument.
1509 DebugLoc dl = Op.getDebugLoc();
1510 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1511 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1512 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1513 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
1517 ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) {
1518 SDNode *Node = Op.getNode();
1519 DebugLoc dl = Node->getDebugLoc();
1520 EVT VT = Node->getValueType(0);
1521 SDValue Chain = Op.getOperand(0);
1522 SDValue Size = Op.getOperand(1);
1523 SDValue Align = Op.getOperand(2);
1525 // Chain the dynamic stack allocation so that it doesn't modify the stack
1526 // pointer when other instructions are using the stack.
1527 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1529 unsigned AlignVal = cast<ConstantSDNode>(Align)->getZExtValue();
1530 unsigned StackAlign = getTargetMachine().getFrameInfo()->getStackAlignment();
1531 if (AlignVal > StackAlign)
1532 // Do this now since selection pass cannot introduce new target
1533 // independent node.
1534 Align = DAG.getConstant(-(uint64_t)AlignVal, VT);
1536 // In Thumb1 mode, there isn't a "sub r, sp, r" instruction, we will end up
1537 // using a "add r, sp, r" instead. Negate the size now so we don't have to
1538 // do even more horrible hack later.
1539 MachineFunction &MF = DAG.getMachineFunction();
1540 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1541 if (AFI->isThumb1OnlyFunction()) {
1543 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Size);
1545 uint32_t Val = C->getZExtValue();
1546 if (Val <= 508 && ((Val & 3) == 0))
1550 Size = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, VT), Size);
1553 SDVTList VTList = DAG.getVTList(VT, MVT::Other);
1554 SDValue Ops1[] = { Chain, Size, Align };
1555 SDValue Res = DAG.getNode(ARMISD::DYN_ALLOC, dl, VTList, Ops1, 3);
1556 Chain = Res.getValue(1);
1557 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1558 DAG.getIntPtrConstant(0, true), SDValue());
1559 SDValue Ops2[] = { Res, Chain };
1560 return DAG.getMergeValues(Ops2, 2, dl);
1564 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
1565 SDValue &Root, SelectionDAG &DAG,
1567 MachineFunction &MF = DAG.getMachineFunction();
1568 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1570 TargetRegisterClass *RC;
1571 if (AFI->isThumb1OnlyFunction())
1572 RC = ARM::tGPRRegisterClass;
1574 RC = ARM::GPRRegisterClass;
1576 // Transform the arguments stored in physical registers into virtual ones.
1577 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1578 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
1581 if (NextVA.isMemLoc()) {
1582 unsigned ArgSize = NextVA.getLocVT().getSizeInBits()/8;
1583 MachineFrameInfo *MFI = MF.getFrameInfo();
1584 int FI = MFI->CreateFixedObject(ArgSize, NextVA.getLocMemOffset(),
1587 // Create load node to retrieve arguments from the stack.
1588 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1589 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
1590 PseudoSourceValue::getFixedStack(FI), 0);
1592 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
1593 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
1596 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
1600 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
1601 CallingConv::ID CallConv, bool isVarArg,
1602 const SmallVectorImpl<ISD::InputArg>
1604 DebugLoc dl, SelectionDAG &DAG,
1605 SmallVectorImpl<SDValue> &InVals) {
1607 MachineFunction &MF = DAG.getMachineFunction();
1608 MachineFrameInfo *MFI = MF.getFrameInfo();
1610 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1612 // Assign locations to all of the incoming arguments.
1613 SmallVector<CCValAssign, 16> ArgLocs;
1614 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1616 CCInfo.AnalyzeFormalArguments(Ins,
1617 CCAssignFnForNode(CallConv, /* Return*/ false,
1620 SmallVector<SDValue, 16> ArgValues;
1622 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1623 CCValAssign &VA = ArgLocs[i];
1625 // Arguments stored in registers.
1626 if (VA.isRegLoc()) {
1627 EVT RegVT = VA.getLocVT();
1630 if (VA.needsCustom()) {
1631 // f64 and vector types are split up into multiple registers or
1632 // combinations of registers and stack slots.
1635 if (VA.getLocVT() == MVT::v2f64) {
1636 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
1638 VA = ArgLocs[++i]; // skip ahead to next loc
1639 SDValue ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
1641 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1642 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
1643 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
1644 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
1645 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
1647 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
1650 TargetRegisterClass *RC;
1652 if (RegVT == MVT::f32)
1653 RC = ARM::SPRRegisterClass;
1654 else if (RegVT == MVT::f64)
1655 RC = ARM::DPRRegisterClass;
1656 else if (RegVT == MVT::v2f64)
1657 RC = ARM::QPRRegisterClass;
1658 else if (RegVT == MVT::i32)
1659 RC = (AFI->isThumb1OnlyFunction() ?
1660 ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
1662 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
1664 // Transform the arguments in physical registers into virtual ones.
1665 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1666 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1669 // If this is an 8 or 16-bit value, it is really passed promoted
1670 // to 32 bits. Insert an assert[sz]ext to capture this, then
1671 // truncate to the right size.
1672 switch (VA.getLocInfo()) {
1673 default: llvm_unreachable("Unknown loc info!");
1674 case CCValAssign::Full: break;
1675 case CCValAssign::BCvt:
1676 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1678 case CCValAssign::SExt:
1679 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1680 DAG.getValueType(VA.getValVT()));
1681 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1683 case CCValAssign::ZExt:
1684 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1685 DAG.getValueType(VA.getValVT()));
1686 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1690 InVals.push_back(ArgValue);
1692 } else { // VA.isRegLoc()
1695 assert(VA.isMemLoc());
1696 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
1698 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
1699 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
1702 // Create load nodes to retrieve arguments from the stack.
1703 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1704 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
1705 PseudoSourceValue::getFixedStack(FI), 0));
1711 static const unsigned GPRArgRegs[] = {
1712 ARM::R0, ARM::R1, ARM::R2, ARM::R3
1715 unsigned NumGPRs = CCInfo.getFirstUnallocated
1716 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
1718 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1719 unsigned VARegSize = (4 - NumGPRs) * 4;
1720 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
1721 unsigned ArgOffset = CCInfo.getNextStackOffset();
1722 if (VARegSaveSize) {
1723 // If this function is vararg, store any remaining integer argument regs
1724 // to their spots on the stack so that they may be loaded by deferencing
1725 // the result of va_next.
1726 AFI->setVarArgsRegSaveSize(VARegSaveSize);
1727 VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset +
1728 VARegSaveSize - VARegSize,
1730 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
1732 SmallVector<SDValue, 4> MemOps;
1733 for (; NumGPRs < 4; ++NumGPRs) {
1734 TargetRegisterClass *RC;
1735 if (AFI->isThumb1OnlyFunction())
1736 RC = ARM::tGPRRegisterClass;
1738 RC = ARM::GPRRegisterClass;
1740 unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
1741 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
1742 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
1743 PseudoSourceValue::getFixedStack(VarArgsFrameIndex), 0);
1744 MemOps.push_back(Store);
1745 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
1746 DAG.getConstant(4, getPointerTy()));
1748 if (!MemOps.empty())
1749 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1750 &MemOps[0], MemOps.size());
1752 // This will point to the next argument passed via stack.
1753 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset, true, false);
1759 /// isFloatingPointZero - Return true if this is +0.0.
1760 static bool isFloatingPointZero(SDValue Op) {
1761 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1762 return CFP->getValueAPF().isPosZero();
1763 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1764 // Maybe this has already been legalized into the constant pool?
1765 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
1766 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
1767 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
1768 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1769 return CFP->getValueAPF().isPosZero();
1775 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
1776 /// the given operands.
1778 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1779 SDValue &ARMCC, SelectionDAG &DAG, DebugLoc dl) {
1780 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1781 unsigned C = RHSC->getZExtValue();
1782 if (!isLegalICmpImmediate(C)) {
1783 // Constant does not fit, try adjusting it by one?
1788 if (isLegalICmpImmediate(C-1)) {
1789 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1790 RHS = DAG.getConstant(C-1, MVT::i32);
1795 if (C > 0 && isLegalICmpImmediate(C-1)) {
1796 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1797 RHS = DAG.getConstant(C-1, MVT::i32);
1802 if (isLegalICmpImmediate(C+1)) {
1803 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1804 RHS = DAG.getConstant(C+1, MVT::i32);
1809 if (C < 0xffffffff && isLegalICmpImmediate(C+1)) {
1810 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1811 RHS = DAG.getConstant(C+1, MVT::i32);
1818 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
1819 ARMISD::NodeType CompareType;
1822 CompareType = ARMISD::CMP;
1827 CompareType = ARMISD::CMPZ;
1830 ARMCC = DAG.getConstant(CondCode, MVT::i32);
1831 return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS);
1834 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
1835 static SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
1838 if (!isFloatingPointZero(RHS))
1839 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS);
1841 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS);
1842 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp);
1845 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
1846 EVT VT = Op.getValueType();
1847 SDValue LHS = Op.getOperand(0);
1848 SDValue RHS = Op.getOperand(1);
1849 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1850 SDValue TrueVal = Op.getOperand(2);
1851 SDValue FalseVal = Op.getOperand(3);
1852 DebugLoc dl = Op.getDebugLoc();
1854 if (LHS.getValueType() == MVT::i32) {
1856 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1857 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, dl);
1858 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC, CCR,Cmp);
1861 ARMCC::CondCodes CondCode, CondCode2;
1862 FPCCToARMCC(CC, CondCode, CondCode2);
1864 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
1865 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1866 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
1867 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
1869 if (CondCode2 != ARMCC::AL) {
1870 SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
1871 // FIXME: Needs another CMP because flag can have but one use.
1872 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
1873 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
1874 Result, TrueVal, ARMCC2, CCR, Cmp2);
1879 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
1880 SDValue Chain = Op.getOperand(0);
1881 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1882 SDValue LHS = Op.getOperand(2);
1883 SDValue RHS = Op.getOperand(3);
1884 SDValue Dest = Op.getOperand(4);
1885 DebugLoc dl = Op.getDebugLoc();
1887 if (LHS.getValueType() == MVT::i32) {
1889 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1890 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, dl);
1891 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
1892 Chain, Dest, ARMCC, CCR,Cmp);
1895 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
1896 ARMCC::CondCodes CondCode, CondCode2;
1897 FPCCToARMCC(CC, CondCode, CondCode2);
1899 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
1900 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
1901 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1902 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
1903 SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp };
1904 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
1905 if (CondCode2 != ARMCC::AL) {
1906 ARMCC = DAG.getConstant(CondCode2, MVT::i32);
1907 SDValue Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) };
1908 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
1913 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) {
1914 SDValue Chain = Op.getOperand(0);
1915 SDValue Table = Op.getOperand(1);
1916 SDValue Index = Op.getOperand(2);
1917 DebugLoc dl = Op.getDebugLoc();
1919 EVT PTy = getPointerTy();
1920 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
1921 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
1922 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
1923 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
1924 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
1925 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
1926 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
1927 if (Subtarget->isThumb2()) {
1928 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
1929 // which does another jump to the destination. This also makes it easier
1930 // to translate it to TBB / TBH later.
1931 // FIXME: This might not work if the function is extremely large.
1932 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
1933 Addr, Op.getOperand(2), JTI, UId);
1935 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1936 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
1937 PseudoSourceValue::getJumpTable(), 0);
1938 Chain = Addr.getValue(1);
1939 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
1940 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
1942 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
1943 PseudoSourceValue::getJumpTable(), 0);
1944 Chain = Addr.getValue(1);
1945 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
1949 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1950 DebugLoc dl = Op.getDebugLoc();
1952 Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI;
1953 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
1954 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
1957 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1958 EVT VT = Op.getValueType();
1959 DebugLoc dl = Op.getDebugLoc();
1961 Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF;
1963 Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
1964 return DAG.getNode(Opc, dl, VT, Op);
1967 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
1968 // Implement fcopysign with a fabs and a conditional fneg.
1969 SDValue Tmp0 = Op.getOperand(0);
1970 SDValue Tmp1 = Op.getOperand(1);
1971 DebugLoc dl = Op.getDebugLoc();
1972 EVT VT = Op.getValueType();
1973 EVT SrcVT = Tmp1.getValueType();
1974 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
1975 SDValue Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG, dl);
1976 SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
1977 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1978 return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp);
1981 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
1982 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1983 MFI->setFrameAddressIsTaken(true);
1984 EVT VT = Op.getValueType();
1985 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
1986 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1987 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
1988 ? ARM::R7 : ARM::R11;
1989 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
1991 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0);
1996 ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
1998 SDValue Dst, SDValue Src,
1999 SDValue Size, unsigned Align,
2001 const Value *DstSV, uint64_t DstSVOff,
2002 const Value *SrcSV, uint64_t SrcSVOff){
2003 // Do repeated 4-byte loads and stores. To be improved.
2004 // This requires 4-byte alignment.
2005 if ((Align & 3) != 0)
2007 // This requires the copy size to be a constant, preferrably
2008 // within a subtarget-specific limit.
2009 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
2012 uint64_t SizeVal = ConstantSize->getZExtValue();
2013 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
2016 unsigned BytesLeft = SizeVal & 3;
2017 unsigned NumMemOps = SizeVal >> 2;
2018 unsigned EmittedNumMemOps = 0;
2020 unsigned VTSize = 4;
2022 const unsigned MAX_LOADS_IN_LDM = 6;
2023 SDValue TFOps[MAX_LOADS_IN_LDM];
2024 SDValue Loads[MAX_LOADS_IN_LDM];
2025 uint64_t SrcOff = 0, DstOff = 0;
2027 // Emit up to MAX_LOADS_IN_LDM loads, then a TokenFactor barrier, then the
2028 // same number of stores. The loads and stores will get combined into
2029 // ldm/stm later on.
2030 while (EmittedNumMemOps < NumMemOps) {
2032 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
2033 Loads[i] = DAG.getLoad(VT, dl, Chain,
2034 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
2035 DAG.getConstant(SrcOff, MVT::i32)),
2036 SrcSV, SrcSVOff + SrcOff);
2037 TFOps[i] = Loads[i].getValue(1);
2040 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
2043 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
2044 TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
2045 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
2046 DAG.getConstant(DstOff, MVT::i32)),
2047 DstSV, DstSVOff + DstOff);
2050 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
2052 EmittedNumMemOps += i;
2058 // Issue loads / stores for the trailing (1 - 3) bytes.
2059 unsigned BytesLeftSave = BytesLeft;
2062 if (BytesLeft >= 2) {
2070 Loads[i] = DAG.getLoad(VT, dl, Chain,
2071 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
2072 DAG.getConstant(SrcOff, MVT::i32)),
2073 SrcSV, SrcSVOff + SrcOff);
2074 TFOps[i] = Loads[i].getValue(1);
2077 BytesLeft -= VTSize;
2079 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
2082 BytesLeft = BytesLeftSave;
2084 if (BytesLeft >= 2) {
2092 TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
2093 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
2094 DAG.getConstant(DstOff, MVT::i32)),
2095 DstSV, DstSVOff + DstOff);
2098 BytesLeft -= VTSize;
2100 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
2103 static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
2104 SDValue Op = N->getOperand(0);
2105 DebugLoc dl = N->getDebugLoc();
2106 if (N->getValueType(0) == MVT::f64) {
2107 // Turn i64->f64 into VMOVDRR.
2108 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2109 DAG.getConstant(0, MVT::i32));
2110 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2111 DAG.getConstant(1, MVT::i32));
2112 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
2115 // Turn f64->i64 into VMOVRRD.
2116 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
2117 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
2119 // Merge the pieces into a single i64 value.
2120 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
2123 /// getZeroVector - Returns a vector of specified type with all zero elements.
2125 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2126 assert(VT.isVector() && "Expected a vector type");
2128 // Zero vectors are used to represent vector negation and in those cases
2129 // will be implemented with the NEON VNEG instruction. However, VNEG does
2130 // not support i64 elements, so sometimes the zero vectors will need to be
2131 // explicitly constructed. For those cases, and potentially other uses in
2132 // the future, always build zero vectors as <16 x i8> or <8 x i8> bitcasted
2133 // to their dest type. This ensures they get CSE'd.
2135 SDValue Cst = DAG.getTargetConstant(0, MVT::i8);
2136 SmallVector<SDValue, 8> Ops;
2139 if (VT.getSizeInBits() == 64) {
2140 Ops.assign(8, Cst); TVT = MVT::v8i8;
2142 Ops.assign(16, Cst); TVT = MVT::v16i8;
2144 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, TVT, &Ops[0], Ops.size());
2146 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2149 /// getOnesVector - Returns a vector of specified type with all bits set.
2151 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2152 assert(VT.isVector() && "Expected a vector type");
2154 // Always build ones vectors as <16 x i8> or <8 x i8> bitcasted to their
2155 // dest type. This ensures they get CSE'd.
2157 SDValue Cst = DAG.getTargetConstant(0xFF, MVT::i8);
2158 SmallVector<SDValue, 8> Ops;
2161 if (VT.getSizeInBits() == 64) {
2162 Ops.assign(8, Cst); TVT = MVT::v8i8;
2164 Ops.assign(16, Cst); TVT = MVT::v16i8;
2166 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, TVT, &Ops[0], Ops.size());
2168 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2171 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
2172 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2173 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) {
2174 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2175 EVT VT = Op.getValueType();
2176 unsigned VTBits = VT.getSizeInBits();
2177 DebugLoc dl = Op.getDebugLoc();
2178 SDValue ShOpLo = Op.getOperand(0);
2179 SDValue ShOpHi = Op.getOperand(1);
2180 SDValue ShAmt = Op.getOperand(2);
2182 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
2184 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
2186 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2187 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2188 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
2189 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2190 DAG.getConstant(VTBits, MVT::i32));
2191 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
2192 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2193 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
2195 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2196 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
2198 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
2199 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC,
2202 SDValue Ops[2] = { Lo, Hi };
2203 return DAG.getMergeValues(Ops, 2, dl);
2206 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
2207 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2208 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) {
2209 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2210 EVT VT = Op.getValueType();
2211 unsigned VTBits = VT.getSizeInBits();
2212 DebugLoc dl = Op.getDebugLoc();
2213 SDValue ShOpLo = Op.getOperand(0);
2214 SDValue ShOpHi = Op.getOperand(1);
2215 SDValue ShAmt = Op.getOperand(2);
2218 assert(Op.getOpcode() == ISD::SHL_PARTS);
2219 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2220 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2221 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
2222 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2223 DAG.getConstant(VTBits, MVT::i32));
2224 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
2225 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
2227 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2228 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2229 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
2231 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
2232 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMCC,
2235 SDValue Ops[2] = { Lo, Hi };
2236 return DAG.getMergeValues(Ops, 2, dl);
2239 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
2240 const ARMSubtarget *ST) {
2241 EVT VT = N->getValueType(0);
2242 DebugLoc dl = N->getDebugLoc();
2244 if (!ST->hasV6T2Ops())
2247 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
2248 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
2251 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
2252 const ARMSubtarget *ST) {
2253 EVT VT = N->getValueType(0);
2254 DebugLoc dl = N->getDebugLoc();
2256 // Lower vector shifts on NEON to use VSHL.
2257 if (VT.isVector()) {
2258 assert(ST->hasNEON() && "unexpected vector shift");
2260 // Left shifts translate directly to the vshiftu intrinsic.
2261 if (N->getOpcode() == ISD::SHL)
2262 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2263 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
2264 N->getOperand(0), N->getOperand(1));
2266 assert((N->getOpcode() == ISD::SRA ||
2267 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
2269 // NEON uses the same intrinsics for both left and right shifts. For
2270 // right shifts, the shift amounts are negative, so negate the vector of
2272 EVT ShiftVT = N->getOperand(1).getValueType();
2273 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
2274 getZeroVector(ShiftVT, DAG, dl),
2276 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
2277 Intrinsic::arm_neon_vshifts :
2278 Intrinsic::arm_neon_vshiftu);
2279 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2280 DAG.getConstant(vshiftInt, MVT::i32),
2281 N->getOperand(0), NegatedCount);
2284 // We can get here for a node like i32 = ISD::SHL i32, i64
2288 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
2289 "Unknown shift to lower!");
2291 // We only lower SRA, SRL of 1 here, all others use generic lowering.
2292 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
2293 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
2296 // If we are in thumb mode, we don't have RRX.
2297 if (ST->isThumb1Only()) return SDValue();
2299 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
2300 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2301 DAG.getConstant(0, MVT::i32));
2302 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2303 DAG.getConstant(1, MVT::i32));
2305 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
2306 // captures the result into a carry flag.
2307 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
2308 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
2310 // The low part is an ARMISD::RRX operand, which shifts the carry in.
2311 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
2313 // Merge the pieces into a single i64 value.
2314 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
2317 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
2318 SDValue TmpOp0, TmpOp1;
2319 bool Invert = false;
2323 SDValue Op0 = Op.getOperand(0);
2324 SDValue Op1 = Op.getOperand(1);
2325 SDValue CC = Op.getOperand(2);
2326 EVT VT = Op.getValueType();
2327 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
2328 DebugLoc dl = Op.getDebugLoc();
2330 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
2331 switch (SetCCOpcode) {
2332 default: llvm_unreachable("Illegal FP comparison"); break;
2334 case ISD::SETNE: Invert = true; // Fallthrough
2336 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2338 case ISD::SETLT: Swap = true; // Fallthrough
2340 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2342 case ISD::SETLE: Swap = true; // Fallthrough
2344 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2345 case ISD::SETUGE: Swap = true; // Fallthrough
2346 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
2347 case ISD::SETUGT: Swap = true; // Fallthrough
2348 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
2349 case ISD::SETUEQ: Invert = true; // Fallthrough
2351 // Expand this to (OLT | OGT).
2355 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2356 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
2358 case ISD::SETUO: Invert = true; // Fallthrough
2360 // Expand this to (OLT | OGE).
2364 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2365 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
2369 // Integer comparisons.
2370 switch (SetCCOpcode) {
2371 default: llvm_unreachable("Illegal integer comparison"); break;
2372 case ISD::SETNE: Invert = true;
2373 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2374 case ISD::SETLT: Swap = true;
2375 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2376 case ISD::SETLE: Swap = true;
2377 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2378 case ISD::SETULT: Swap = true;
2379 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
2380 case ISD::SETULE: Swap = true;
2381 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
2384 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
2385 if (Opc == ARMISD::VCEQ) {
2388 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
2390 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
2393 // Ignore bitconvert.
2394 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BIT_CONVERT)
2395 AndOp = AndOp.getOperand(0);
2397 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
2399 Op0 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(0));
2400 Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(1));
2407 std::swap(Op0, Op1);
2409 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
2412 Result = DAG.getNOT(dl, Result, VT);
2417 /// isVMOVSplat - Check if the specified splat value corresponds to an immediate
2418 /// VMOV instruction, and if so, return the constant being splatted.
2419 static SDValue isVMOVSplat(uint64_t SplatBits, uint64_t SplatUndef,
2420 unsigned SplatBitSize, SelectionDAG &DAG) {
2421 switch (SplatBitSize) {
2423 // Any 1-byte value is OK.
2424 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
2425 return DAG.getTargetConstant(SplatBits, MVT::i8);
2428 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
2429 if ((SplatBits & ~0xff) == 0 ||
2430 (SplatBits & ~0xff00) == 0)
2431 return DAG.getTargetConstant(SplatBits, MVT::i16);
2435 // NEON's 32-bit VMOV supports splat values where:
2436 // * only one byte is nonzero, or
2437 // * the least significant byte is 0xff and the second byte is nonzero, or
2438 // * the least significant 2 bytes are 0xff and the third is nonzero.
2439 if ((SplatBits & ~0xff) == 0 ||
2440 (SplatBits & ~0xff00) == 0 ||
2441 (SplatBits & ~0xff0000) == 0 ||
2442 (SplatBits & ~0xff000000) == 0)
2443 return DAG.getTargetConstant(SplatBits, MVT::i32);
2445 if ((SplatBits & ~0xffff) == 0 &&
2446 ((SplatBits | SplatUndef) & 0xff) == 0xff)
2447 return DAG.getTargetConstant(SplatBits | 0xff, MVT::i32);
2449 if ((SplatBits & ~0xffffff) == 0 &&
2450 ((SplatBits | SplatUndef) & 0xffff) == 0xffff)
2451 return DAG.getTargetConstant(SplatBits | 0xffff, MVT::i32);
2453 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
2454 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
2455 // VMOV.I32. A (very) minor optimization would be to replicate the value
2456 // and fall through here to test for a valid 64-bit splat. But, then the
2457 // caller would also need to check and handle the change in size.
2461 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
2462 uint64_t BitMask = 0xff;
2464 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
2465 if (((SplatBits | SplatUndef) & BitMask) == BitMask)
2467 else if ((SplatBits & BitMask) != 0)
2471 return DAG.getTargetConstant(Val, MVT::i64);
2475 llvm_unreachable("unexpected size for isVMOVSplat");
2482 /// getVMOVImm - If this is a build_vector of constants which can be
2483 /// formed by using a VMOV instruction of the specified element size,
2484 /// return the constant being splatted. The ByteSize field indicates the
2485 /// number of bytes of each element [1248].
2486 SDValue ARM::getVMOVImm(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
2487 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N);
2488 APInt SplatBits, SplatUndef;
2489 unsigned SplatBitSize;
2491 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
2492 HasAnyUndefs, ByteSize * 8))
2495 if (SplatBitSize > ByteSize * 8)
2498 return isVMOVSplat(SplatBits.getZExtValue(), SplatUndef.getZExtValue(),
2502 static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT,
2503 bool &ReverseVEXT, unsigned &Imm) {
2504 unsigned NumElts = VT.getVectorNumElements();
2505 ReverseVEXT = false;
2508 // If this is a VEXT shuffle, the immediate value is the index of the first
2509 // element. The other shuffle indices must be the successive elements after
2511 unsigned ExpectedElt = Imm;
2512 for (unsigned i = 1; i < NumElts; ++i) {
2513 // Increment the expected index. If it wraps around, it may still be
2514 // a VEXT but the source vectors must be swapped.
2516 if (ExpectedElt == NumElts * 2) {
2521 if (ExpectedElt != static_cast<unsigned>(M[i]))
2525 // Adjust the index value if the source operands will be swapped.
2532 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
2533 /// instruction with the specified blocksize. (The order of the elements
2534 /// within each block of the vector is reversed.)
2535 static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT,
2536 unsigned BlockSize) {
2537 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
2538 "Only possible block sizes for VREV are: 16, 32, 64");
2540 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2544 unsigned NumElts = VT.getVectorNumElements();
2545 unsigned BlockElts = M[0] + 1;
2547 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
2550 for (unsigned i = 0; i < NumElts; ++i) {
2551 if ((unsigned) M[i] !=
2552 (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
2559 static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT,
2560 unsigned &WhichResult) {
2561 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2565 unsigned NumElts = VT.getVectorNumElements();
2566 WhichResult = (M[0] == 0 ? 0 : 1);
2567 for (unsigned i = 0; i < NumElts; i += 2) {
2568 if ((unsigned) M[i] != i + WhichResult ||
2569 (unsigned) M[i+1] != i + NumElts + WhichResult)
2575 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
2576 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
2577 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
2578 static bool isVTRN_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
2579 unsigned &WhichResult) {
2580 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2584 unsigned NumElts = VT.getVectorNumElements();
2585 WhichResult = (M[0] == 0 ? 0 : 1);
2586 for (unsigned i = 0; i < NumElts; i += 2) {
2587 if ((unsigned) M[i] != i + WhichResult ||
2588 (unsigned) M[i+1] != i + WhichResult)
2594 static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT,
2595 unsigned &WhichResult) {
2596 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2600 unsigned NumElts = VT.getVectorNumElements();
2601 WhichResult = (M[0] == 0 ? 0 : 1);
2602 for (unsigned i = 0; i != NumElts; ++i) {
2603 if ((unsigned) M[i] != 2 * i + WhichResult)
2607 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
2608 if (VT.is64BitVector() && EltSz == 32)
2614 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
2615 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
2616 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
2617 static bool isVUZP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
2618 unsigned &WhichResult) {
2619 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2623 unsigned Half = VT.getVectorNumElements() / 2;
2624 WhichResult = (M[0] == 0 ? 0 : 1);
2625 for (unsigned j = 0; j != 2; ++j) {
2626 unsigned Idx = WhichResult;
2627 for (unsigned i = 0; i != Half; ++i) {
2628 if ((unsigned) M[i + j * Half] != Idx)
2634 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
2635 if (VT.is64BitVector() && EltSz == 32)
2641 static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT,
2642 unsigned &WhichResult) {
2643 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2647 unsigned NumElts = VT.getVectorNumElements();
2648 WhichResult = (M[0] == 0 ? 0 : 1);
2649 unsigned Idx = WhichResult * NumElts / 2;
2650 for (unsigned i = 0; i != NumElts; i += 2) {
2651 if ((unsigned) M[i] != Idx ||
2652 (unsigned) M[i+1] != Idx + NumElts)
2657 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
2658 if (VT.is64BitVector() && EltSz == 32)
2664 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
2665 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
2666 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
2667 static bool isVZIP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
2668 unsigned &WhichResult) {
2669 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2673 unsigned NumElts = VT.getVectorNumElements();
2674 WhichResult = (M[0] == 0 ? 0 : 1);
2675 unsigned Idx = WhichResult * NumElts / 2;
2676 for (unsigned i = 0; i != NumElts; i += 2) {
2677 if ((unsigned) M[i] != Idx ||
2678 (unsigned) M[i+1] != Idx)
2683 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
2684 if (VT.is64BitVector() && EltSz == 32)
2691 static SDValue BuildSplat(SDValue Val, EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2692 // Canonicalize all-zeros and all-ones vectors.
2693 ConstantSDNode *ConstVal = cast<ConstantSDNode>(Val.getNode());
2694 if (ConstVal->isNullValue())
2695 return getZeroVector(VT, DAG, dl);
2696 if (ConstVal->isAllOnesValue())
2697 return getOnesVector(VT, DAG, dl);
2700 if (VT.is64BitVector()) {
2701 switch (Val.getValueType().getSizeInBits()) {
2702 case 8: CanonicalVT = MVT::v8i8; break;
2703 case 16: CanonicalVT = MVT::v4i16; break;
2704 case 32: CanonicalVT = MVT::v2i32; break;
2705 case 64: CanonicalVT = MVT::v1i64; break;
2706 default: llvm_unreachable("unexpected splat element type"); break;
2709 assert(VT.is128BitVector() && "unknown splat vector size");
2710 switch (Val.getValueType().getSizeInBits()) {
2711 case 8: CanonicalVT = MVT::v16i8; break;
2712 case 16: CanonicalVT = MVT::v8i16; break;
2713 case 32: CanonicalVT = MVT::v4i32; break;
2714 case 64: CanonicalVT = MVT::v2i64; break;
2715 default: llvm_unreachable("unexpected splat element type"); break;
2719 // Build a canonical splat for this value.
2720 SmallVector<SDValue, 8> Ops;
2721 Ops.assign(CanonicalVT.getVectorNumElements(), Val);
2722 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, &Ops[0],
2724 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Res);
2727 // If this is a case we can't handle, return null and let the default
2728 // expansion code take care of it.
2729 static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
2730 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
2731 DebugLoc dl = Op.getDebugLoc();
2732 EVT VT = Op.getValueType();
2734 APInt SplatBits, SplatUndef;
2735 unsigned SplatBitSize;
2737 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
2738 if (SplatBitSize <= 64) {
2739 SDValue Val = isVMOVSplat(SplatBits.getZExtValue(),
2740 SplatUndef.getZExtValue(), SplatBitSize, DAG);
2742 return BuildSplat(Val, VT, DAG, dl);
2746 // If there are only 2 elements in a 128-bit vector, insert them into an
2747 // undef vector. This handles the common case for 128-bit vector argument
2748 // passing, where the insertions should be translated to subreg accesses
2749 // with no real instructions.
2750 if (VT.is128BitVector() && Op.getNumOperands() == 2) {
2751 SDValue Val = DAG.getUNDEF(VT);
2752 SDValue Op0 = Op.getOperand(0);
2753 SDValue Op1 = Op.getOperand(1);
2754 if (Op0.getOpcode() != ISD::UNDEF)
2755 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, Op0,
2756 DAG.getIntPtrConstant(0));
2757 if (Op1.getOpcode() != ISD::UNDEF)
2758 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, Op1,
2759 DAG.getIntPtrConstant(1));
2766 /// isShuffleMaskLegal - Targets can use this to indicate that they only
2767 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
2768 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
2769 /// are assumed to be legal.
2771 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
2773 if (VT.getVectorNumElements() == 4 &&
2774 (VT.is128BitVector() || VT.is64BitVector())) {
2775 unsigned PFIndexes[4];
2776 for (unsigned i = 0; i != 4; ++i) {
2780 PFIndexes[i] = M[i];
2783 // Compute the index in the perfect shuffle table.
2784 unsigned PFTableIndex =
2785 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
2786 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
2787 unsigned Cost = (PFEntry >> 30);
2794 unsigned Imm, WhichResult;
2796 return (ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
2797 isVREVMask(M, VT, 64) ||
2798 isVREVMask(M, VT, 32) ||
2799 isVREVMask(M, VT, 16) ||
2800 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
2801 isVTRNMask(M, VT, WhichResult) ||
2802 isVUZPMask(M, VT, WhichResult) ||
2803 isVZIPMask(M, VT, WhichResult) ||
2804 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
2805 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
2806 isVZIP_v_undef_Mask(M, VT, WhichResult));
2809 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
2810 /// the specified operations to build the shuffle.
2811 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
2812 SDValue RHS, SelectionDAG &DAG,
2814 unsigned OpNum = (PFEntry >> 26) & 0x0F;
2815 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
2816 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
2819 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
2828 OP_VUZPL, // VUZP, left result
2829 OP_VUZPR, // VUZP, right result
2830 OP_VZIPL, // VZIP, left result
2831 OP_VZIPR, // VZIP, right result
2832 OP_VTRNL, // VTRN, left result
2833 OP_VTRNR // VTRN, right result
2836 if (OpNum == OP_COPY) {
2837 if (LHSID == (1*9+2)*9+3) return LHS;
2838 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
2842 SDValue OpLHS, OpRHS;
2843 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
2844 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
2845 EVT VT = OpLHS.getValueType();
2848 default: llvm_unreachable("Unknown shuffle opcode!");
2850 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
2855 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
2856 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
2860 return DAG.getNode(ARMISD::VEXT, dl, VT,
2862 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
2865 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
2866 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
2869 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
2870 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
2873 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
2874 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
2878 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
2879 SDValue V1 = Op.getOperand(0);
2880 SDValue V2 = Op.getOperand(1);
2881 DebugLoc dl = Op.getDebugLoc();
2882 EVT VT = Op.getValueType();
2883 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
2884 SmallVector<int, 8> ShuffleMask;
2886 // Convert shuffles that are directly supported on NEON to target-specific
2887 // DAG nodes, instead of keeping them as shuffles and matching them again
2888 // during code selection. This is more efficient and avoids the possibility
2889 // of inconsistencies between legalization and selection.
2890 // FIXME: floating-point vectors should be canonicalized to integer vectors
2891 // of the same time so that they get CSEd properly.
2892 SVN->getMask(ShuffleMask);
2894 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
2895 int Lane = SVN->getSplatIndex();
2896 // If this is undef splat, generate it via "just" vdup, if possible.
2897 if (Lane == -1) Lane = 0;
2899 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
2900 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
2902 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
2903 DAG.getConstant(Lane, MVT::i32));
2908 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
2911 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
2912 DAG.getConstant(Imm, MVT::i32));
2915 if (isVREVMask(ShuffleMask, VT, 64))
2916 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
2917 if (isVREVMask(ShuffleMask, VT, 32))
2918 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
2919 if (isVREVMask(ShuffleMask, VT, 16))
2920 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
2922 // Check for Neon shuffles that modify both input vectors in place.
2923 // If both results are used, i.e., if there are two shuffles with the same
2924 // source operands and with masks corresponding to both results of one of
2925 // these operations, DAG memoization will ensure that a single node is
2926 // used for both shuffles.
2927 unsigned WhichResult;
2928 if (isVTRNMask(ShuffleMask, VT, WhichResult))
2929 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
2930 V1, V2).getValue(WhichResult);
2931 if (isVUZPMask(ShuffleMask, VT, WhichResult))
2932 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
2933 V1, V2).getValue(WhichResult);
2934 if (isVZIPMask(ShuffleMask, VT, WhichResult))
2935 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
2936 V1, V2).getValue(WhichResult);
2938 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
2939 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
2940 V1, V1).getValue(WhichResult);
2941 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
2942 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
2943 V1, V1).getValue(WhichResult);
2944 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
2945 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
2946 V1, V1).getValue(WhichResult);
2948 // If the shuffle is not directly supported and it has 4 elements, use
2949 // the PerfectShuffle-generated table to synthesize it from other shuffles.
2950 if (VT.getVectorNumElements() == 4 &&
2951 (VT.is128BitVector() || VT.is64BitVector())) {
2952 unsigned PFIndexes[4];
2953 for (unsigned i = 0; i != 4; ++i) {
2954 if (ShuffleMask[i] < 0)
2957 PFIndexes[i] = ShuffleMask[i];
2960 // Compute the index in the perfect shuffle table.
2961 unsigned PFTableIndex =
2962 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
2964 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
2965 unsigned Cost = (PFEntry >> 30);
2968 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
2974 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
2975 EVT VT = Op.getValueType();
2976 DebugLoc dl = Op.getDebugLoc();
2977 SDValue Vec = Op.getOperand(0);
2978 SDValue Lane = Op.getOperand(1);
2979 assert(VT == MVT::i32 &&
2980 Vec.getValueType().getVectorElementType().getSizeInBits() < 32 &&
2981 "unexpected type for custom-lowering vector extract");
2982 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
2985 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
2986 // The only time a CONCAT_VECTORS operation can have legal types is when
2987 // two 64-bit vectors are concatenated to a 128-bit vector.
2988 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
2989 "unexpected CONCAT_VECTORS");
2990 DebugLoc dl = Op.getDebugLoc();
2991 SDValue Val = DAG.getUNDEF(MVT::v2f64);
2992 SDValue Op0 = Op.getOperand(0);
2993 SDValue Op1 = Op.getOperand(1);
2994 if (Op0.getOpcode() != ISD::UNDEF)
2995 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
2996 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op0),
2997 DAG.getIntPtrConstant(0));
2998 if (Op1.getOpcode() != ISD::UNDEF)
2999 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
3000 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op1),
3001 DAG.getIntPtrConstant(1));
3002 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Val);
3005 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
3006 switch (Op.getOpcode()) {
3007 default: llvm_unreachable("Don't know how to custom lower this!");
3008 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3009 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
3010 case ISD::GlobalAddress:
3011 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
3012 LowerGlobalAddressELF(Op, DAG);
3013 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
3014 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
3015 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
3016 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
3017 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
3018 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex);
3019 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget);
3020 case ISD::SINT_TO_FP:
3021 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
3022 case ISD::FP_TO_SINT:
3023 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
3024 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
3025 case ISD::RETURNADDR: break;
3026 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
3027 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
3028 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
3029 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(Op.getNode(), DAG);
3032 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
3033 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
3034 case ISD::SRL_PARTS:
3035 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
3036 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
3037 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
3038 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
3039 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
3040 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
3041 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
3046 /// ReplaceNodeResults - Replace the results of node with an illegal result
3047 /// type with new values built out of custom code.
3048 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
3049 SmallVectorImpl<SDValue>&Results,
3050 SelectionDAG &DAG) {
3051 switch (N->getOpcode()) {
3053 llvm_unreachable("Don't know how to custom expand this!");
3055 case ISD::BIT_CONVERT:
3056 Results.push_back(ExpandBIT_CONVERT(N, DAG));
3060 SDValue Res = LowerShift(N, DAG, Subtarget);
3062 Results.push_back(Res);
3068 //===----------------------------------------------------------------------===//
3069 // ARM Scheduler Hooks
3070 //===----------------------------------------------------------------------===//
3073 ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
3074 MachineBasicBlock *BB,
3075 unsigned Size) const {
3076 unsigned dest = MI->getOperand(0).getReg();
3077 unsigned ptr = MI->getOperand(1).getReg();
3078 unsigned oldval = MI->getOperand(2).getReg();
3079 unsigned newval = MI->getOperand(3).getReg();
3080 unsigned scratch = BB->getParent()->getRegInfo()
3081 .createVirtualRegister(ARM::GPRRegisterClass);
3082 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3083 DebugLoc dl = MI->getDebugLoc();
3084 bool isThumb2 = Subtarget->isThumb2();
3086 unsigned ldrOpc, strOpc;
3088 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
3090 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
3091 strOpc = isThumb2 ? ARM::t2LDREXB : ARM::STREXB;
3094 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
3095 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
3098 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
3099 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
3103 MachineFunction *MF = BB->getParent();
3104 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3105 MachineFunction::iterator It = BB;
3106 ++It; // insert the new blocks after the current block
3108 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
3109 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
3110 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3111 MF->insert(It, loop1MBB);
3112 MF->insert(It, loop2MBB);
3113 MF->insert(It, exitMBB);
3114 exitMBB->transferSuccessors(BB);
3118 // fallthrough --> loop1MBB
3119 BB->addSuccessor(loop1MBB);
3122 // ldrex dest, [ptr]
3126 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
3127 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
3128 .addReg(dest).addReg(oldval));
3129 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3130 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
3131 BB->addSuccessor(loop2MBB);
3132 BB->addSuccessor(exitMBB);
3135 // strex scratch, newval, [ptr]
3139 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval)
3141 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
3142 .addReg(scratch).addImm(0));
3143 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3144 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
3145 BB->addSuccessor(loop1MBB);
3146 BB->addSuccessor(exitMBB);
3152 MF->DeleteMachineInstr(MI); // The instruction is gone now.
3158 ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
3159 unsigned Size, unsigned BinOpcode) const {
3160 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
3161 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3163 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3164 MachineFunction *MF = BB->getParent();
3165 MachineFunction::iterator It = BB;
3168 unsigned dest = MI->getOperand(0).getReg();
3169 unsigned ptr = MI->getOperand(1).getReg();
3170 unsigned incr = MI->getOperand(2).getReg();
3171 DebugLoc dl = MI->getDebugLoc();
3173 bool isThumb2 = Subtarget->isThumb2();
3174 unsigned ldrOpc, strOpc;
3176 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
3178 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
3179 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
3182 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
3183 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
3186 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
3187 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
3191 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3192 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3193 MF->insert(It, loopMBB);
3194 MF->insert(It, exitMBB);
3195 exitMBB->transferSuccessors(BB);
3197 MachineRegisterInfo &RegInfo = MF->getRegInfo();
3198 unsigned scratch = RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
3199 unsigned scratch2 = (!BinOpcode) ? incr :
3200 RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
3204 // fallthrough --> loopMBB
3205 BB->addSuccessor(loopMBB);
3209 // <binop> scratch2, dest, incr
3210 // strex scratch, scratch2, ptr
3213 // fallthrough --> exitMBB
3215 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
3217 // operand order needs to go the other way for NAND
3218 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr)
3219 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
3220 addReg(incr).addReg(dest)).addReg(0);
3222 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
3223 addReg(dest).addReg(incr)).addReg(0);
3226 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2)
3228 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
3229 .addReg(scratch).addImm(0));
3230 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3231 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
3233 BB->addSuccessor(loopMBB);
3234 BB->addSuccessor(exitMBB);
3240 MF->DeleteMachineInstr(MI); // The instruction is gone now.
3246 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
3247 MachineBasicBlock *BB,
3248 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
3249 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3250 DebugLoc dl = MI->getDebugLoc();
3251 bool isThumb2 = Subtarget->isThumb2();
3252 switch (MI->getOpcode()) {
3255 llvm_unreachable("Unexpected instr type to insert");
3257 case ARM::ATOMIC_LOAD_ADD_I8:
3258 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
3259 case ARM::ATOMIC_LOAD_ADD_I16:
3260 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
3261 case ARM::ATOMIC_LOAD_ADD_I32:
3262 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
3264 case ARM::ATOMIC_LOAD_AND_I8:
3265 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
3266 case ARM::ATOMIC_LOAD_AND_I16:
3267 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
3268 case ARM::ATOMIC_LOAD_AND_I32:
3269 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
3271 case ARM::ATOMIC_LOAD_OR_I8:
3272 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
3273 case ARM::ATOMIC_LOAD_OR_I16:
3274 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
3275 case ARM::ATOMIC_LOAD_OR_I32:
3276 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
3278 case ARM::ATOMIC_LOAD_XOR_I8:
3279 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
3280 case ARM::ATOMIC_LOAD_XOR_I16:
3281 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
3282 case ARM::ATOMIC_LOAD_XOR_I32:
3283 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
3285 case ARM::ATOMIC_LOAD_NAND_I8:
3286 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
3287 case ARM::ATOMIC_LOAD_NAND_I16:
3288 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
3289 case ARM::ATOMIC_LOAD_NAND_I32:
3290 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
3292 case ARM::ATOMIC_LOAD_SUB_I8:
3293 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
3294 case ARM::ATOMIC_LOAD_SUB_I16:
3295 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
3296 case ARM::ATOMIC_LOAD_SUB_I32:
3297 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
3299 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0);
3300 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0);
3301 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0);
3303 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1);
3304 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
3305 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
3307 case ARM::tMOVCCr_pseudo: {
3308 // To "insert" a SELECT_CC instruction, we actually have to insert the
3309 // diamond control-flow pattern. The incoming instruction knows the
3310 // destination vreg to set, the condition code register to branch on, the
3311 // true/false values to select between, and a branch opcode to use.
3312 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3313 MachineFunction::iterator It = BB;
3319 // cmpTY ccX, r1, r2
3321 // fallthrough --> copy0MBB
3322 MachineBasicBlock *thisMBB = BB;
3323 MachineFunction *F = BB->getParent();
3324 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
3325 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
3326 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
3327 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
3328 F->insert(It, copy0MBB);
3329 F->insert(It, sinkMBB);
3330 // Update machine-CFG edges by first adding all successors of the current
3331 // block to the new block which will contain the Phi node for the select.
3332 // Also inform sdisel of the edge changes.
3333 for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
3334 E = BB->succ_end(); I != E; ++I) {
3335 EM->insert(std::make_pair(*I, sinkMBB));
3336 sinkMBB->addSuccessor(*I);
3338 // Next, remove all successors of the current block, and add the true
3339 // and fallthrough blocks as its successors.
3340 while (!BB->succ_empty())
3341 BB->removeSuccessor(BB->succ_begin());
3342 BB->addSuccessor(copy0MBB);
3343 BB->addSuccessor(sinkMBB);
3346 // %FalseValue = ...
3347 // # fallthrough to sinkMBB
3350 // Update machine-CFG edges
3351 BB->addSuccessor(sinkMBB);
3354 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
3357 BuildMI(BB, dl, TII->get(ARM::PHI), MI->getOperand(0).getReg())
3358 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
3359 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
3361 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
3368 case ARM::t2SUBrSPi_:
3369 case ARM::t2SUBrSPi12_:
3370 case ARM::t2SUBrSPs_: {
3371 MachineFunction *MF = BB->getParent();
3372 unsigned DstReg = MI->getOperand(0).getReg();
3373 unsigned SrcReg = MI->getOperand(1).getReg();
3374 bool DstIsDead = MI->getOperand(0).isDead();
3375 bool SrcIsKill = MI->getOperand(1).isKill();
3377 if (SrcReg != ARM::SP) {
3378 // Copy the source to SP from virtual register.
3379 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(SrcReg);
3380 unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
3381 ? ARM::tMOVtgpr2gpr : ARM::tMOVgpr2gpr;
3382 BuildMI(BB, dl, TII->get(CopyOpc), ARM::SP)
3383 .addReg(SrcReg, getKillRegState(SrcIsKill));
3387 bool NeedPred = false, NeedCC = false, NeedOp3 = false;
3388 switch (MI->getOpcode()) {
3390 llvm_unreachable("Unexpected pseudo instruction!");
3396 OpOpc = ARM::tADDspr;
3399 OpOpc = ARM::tSUBspi;
3401 case ARM::t2SUBrSPi_:
3402 OpOpc = ARM::t2SUBrSPi;
3403 NeedPred = true; NeedCC = true;
3405 case ARM::t2SUBrSPi12_:
3406 OpOpc = ARM::t2SUBrSPi12;
3409 case ARM::t2SUBrSPs_:
3410 OpOpc = ARM::t2SUBrSPs;
3411 NeedPred = true; NeedCC = true; NeedOp3 = true;
3414 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(OpOpc), ARM::SP);
3415 if (OpOpc == ARM::tAND)
3416 AddDefaultT1CC(MIB);
3417 MIB.addReg(ARM::SP);
3418 MIB.addOperand(MI->getOperand(2));
3420 MIB.addOperand(MI->getOperand(3));
3422 AddDefaultPred(MIB);
3426 // Copy the result from SP to virtual register.
3427 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(DstReg);
3428 unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
3429 ? ARM::tMOVgpr2tgpr : ARM::tMOVgpr2gpr;
3430 BuildMI(BB, dl, TII->get(CopyOpc))
3431 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead))
3433 MF->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
3439 //===----------------------------------------------------------------------===//
3440 // ARM Optimization Hooks
3441 //===----------------------------------------------------------------------===//
3444 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
3445 TargetLowering::DAGCombinerInfo &DCI) {
3446 SelectionDAG &DAG = DCI.DAG;
3447 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3448 EVT VT = N->getValueType(0);
3449 unsigned Opc = N->getOpcode();
3450 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
3451 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
3452 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
3453 ISD::CondCode CC = ISD::SETCC_INVALID;
3456 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
3458 SDValue CCOp = Slct.getOperand(0);
3459 if (CCOp.getOpcode() == ISD::SETCC)
3460 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
3463 bool DoXform = false;
3465 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
3468 if (LHS.getOpcode() == ISD::Constant &&
3469 cast<ConstantSDNode>(LHS)->isNullValue()) {
3471 } else if (CC != ISD::SETCC_INVALID &&
3472 RHS.getOpcode() == ISD::Constant &&
3473 cast<ConstantSDNode>(RHS)->isNullValue()) {
3474 std::swap(LHS, RHS);
3475 SDValue Op0 = Slct.getOperand(0);
3476 EVT OpVT = isSlctCC ? Op0.getValueType() :
3477 Op0.getOperand(0).getValueType();
3478 bool isInt = OpVT.isInteger();
3479 CC = ISD::getSetCCInverse(CC, isInt);
3481 if (!TLI.isCondCodeLegal(CC, OpVT))
3482 return SDValue(); // Inverse operator isn't legal.
3489 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
3491 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
3492 Slct.getOperand(0), Slct.getOperand(1), CC);
3493 SDValue CCOp = Slct.getOperand(0);
3495 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
3496 CCOp.getOperand(0), CCOp.getOperand(1), CC);
3497 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
3498 CCOp, OtherOp, Result);
3503 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
3504 static SDValue PerformADDCombine(SDNode *N,
3505 TargetLowering::DAGCombinerInfo &DCI) {
3506 // added by evan in r37685 with no testcase.
3507 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
3509 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
3510 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
3511 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
3512 if (Result.getNode()) return Result;
3514 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
3515 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
3516 if (Result.getNode()) return Result;
3522 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
3523 static SDValue PerformSUBCombine(SDNode *N,
3524 TargetLowering::DAGCombinerInfo &DCI) {
3525 // added by evan in r37685 with no testcase.
3526 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
3528 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
3529 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
3530 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
3531 if (Result.getNode()) return Result;
3537 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
3538 /// ARMISD::VMOVRRD.
3539 static SDValue PerformVMOVRRDCombine(SDNode *N,
3540 TargetLowering::DAGCombinerInfo &DCI) {
3541 // fmrrd(fmdrr x, y) -> x,y
3542 SDValue InDouble = N->getOperand(0);
3543 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
3544 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
3548 /// getVShiftImm - Check if this is a valid build_vector for the immediate
3549 /// operand of a vector shift operation, where all the elements of the
3550 /// build_vector must have the same constant integer value.
3551 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
3552 // Ignore bit_converts.
3553 while (Op.getOpcode() == ISD::BIT_CONVERT)
3554 Op = Op.getOperand(0);
3555 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
3556 APInt SplatBits, SplatUndef;
3557 unsigned SplatBitSize;
3559 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
3560 HasAnyUndefs, ElementBits) ||
3561 SplatBitSize > ElementBits)
3563 Cnt = SplatBits.getSExtValue();
3567 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
3568 /// operand of a vector shift left operation. That value must be in the range:
3569 /// 0 <= Value < ElementBits for a left shift; or
3570 /// 0 <= Value <= ElementBits for a long left shift.
3571 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
3572 assert(VT.isVector() && "vector shift count is not a vector type");
3573 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
3574 if (! getVShiftImm(Op, ElementBits, Cnt))
3576 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
3579 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
3580 /// operand of a vector shift right operation. For a shift opcode, the value
3581 /// is positive, but for an intrinsic the value count must be negative. The
3582 /// absolute value must be in the range:
3583 /// 1 <= |Value| <= ElementBits for a right shift; or
3584 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
3585 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
3587 assert(VT.isVector() && "vector shift count is not a vector type");
3588 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
3589 if (! getVShiftImm(Op, ElementBits, Cnt))
3593 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
3596 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
3597 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
3598 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
3601 // Don't do anything for most intrinsics.
3604 // Vector shifts: check for immediate versions and lower them.
3605 // Note: This is done during DAG combining instead of DAG legalizing because
3606 // the build_vectors for 64-bit vector element shift counts are generally
3607 // not legal, and it is hard to see their values after they get legalized to
3608 // loads from a constant pool.
3609 case Intrinsic::arm_neon_vshifts:
3610 case Intrinsic::arm_neon_vshiftu:
3611 case Intrinsic::arm_neon_vshiftls:
3612 case Intrinsic::arm_neon_vshiftlu:
3613 case Intrinsic::arm_neon_vshiftn:
3614 case Intrinsic::arm_neon_vrshifts:
3615 case Intrinsic::arm_neon_vrshiftu:
3616 case Intrinsic::arm_neon_vrshiftn:
3617 case Intrinsic::arm_neon_vqshifts:
3618 case Intrinsic::arm_neon_vqshiftu:
3619 case Intrinsic::arm_neon_vqshiftsu:
3620 case Intrinsic::arm_neon_vqshiftns:
3621 case Intrinsic::arm_neon_vqshiftnu:
3622 case Intrinsic::arm_neon_vqshiftnsu:
3623 case Intrinsic::arm_neon_vqrshiftns:
3624 case Intrinsic::arm_neon_vqrshiftnu:
3625 case Intrinsic::arm_neon_vqrshiftnsu: {
3626 EVT VT = N->getOperand(1).getValueType();
3628 unsigned VShiftOpc = 0;
3631 case Intrinsic::arm_neon_vshifts:
3632 case Intrinsic::arm_neon_vshiftu:
3633 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
3634 VShiftOpc = ARMISD::VSHL;
3637 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
3638 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
3639 ARMISD::VSHRs : ARMISD::VSHRu);
3644 case Intrinsic::arm_neon_vshiftls:
3645 case Intrinsic::arm_neon_vshiftlu:
3646 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
3648 llvm_unreachable("invalid shift count for vshll intrinsic");
3650 case Intrinsic::arm_neon_vrshifts:
3651 case Intrinsic::arm_neon_vrshiftu:
3652 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
3656 case Intrinsic::arm_neon_vqshifts:
3657 case Intrinsic::arm_neon_vqshiftu:
3658 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
3662 case Intrinsic::arm_neon_vqshiftsu:
3663 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
3665 llvm_unreachable("invalid shift count for vqshlu intrinsic");
3667 case Intrinsic::arm_neon_vshiftn:
3668 case Intrinsic::arm_neon_vrshiftn:
3669 case Intrinsic::arm_neon_vqshiftns:
3670 case Intrinsic::arm_neon_vqshiftnu:
3671 case Intrinsic::arm_neon_vqshiftnsu:
3672 case Intrinsic::arm_neon_vqrshiftns:
3673 case Intrinsic::arm_neon_vqrshiftnu:
3674 case Intrinsic::arm_neon_vqrshiftnsu:
3675 // Narrowing shifts require an immediate right shift.
3676 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
3678 llvm_unreachable("invalid shift count for narrowing vector shift intrinsic");
3681 llvm_unreachable("unhandled vector shift");
3685 case Intrinsic::arm_neon_vshifts:
3686 case Intrinsic::arm_neon_vshiftu:
3687 // Opcode already set above.
3689 case Intrinsic::arm_neon_vshiftls:
3690 case Intrinsic::arm_neon_vshiftlu:
3691 if (Cnt == VT.getVectorElementType().getSizeInBits())
3692 VShiftOpc = ARMISD::VSHLLi;
3694 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
3695 ARMISD::VSHLLs : ARMISD::VSHLLu);
3697 case Intrinsic::arm_neon_vshiftn:
3698 VShiftOpc = ARMISD::VSHRN; break;
3699 case Intrinsic::arm_neon_vrshifts:
3700 VShiftOpc = ARMISD::VRSHRs; break;
3701 case Intrinsic::arm_neon_vrshiftu:
3702 VShiftOpc = ARMISD::VRSHRu; break;
3703 case Intrinsic::arm_neon_vrshiftn:
3704 VShiftOpc = ARMISD::VRSHRN; break;
3705 case Intrinsic::arm_neon_vqshifts:
3706 VShiftOpc = ARMISD::VQSHLs; break;
3707 case Intrinsic::arm_neon_vqshiftu:
3708 VShiftOpc = ARMISD::VQSHLu; break;
3709 case Intrinsic::arm_neon_vqshiftsu:
3710 VShiftOpc = ARMISD::VQSHLsu; break;
3711 case Intrinsic::arm_neon_vqshiftns:
3712 VShiftOpc = ARMISD::VQSHRNs; break;
3713 case Intrinsic::arm_neon_vqshiftnu:
3714 VShiftOpc = ARMISD::VQSHRNu; break;
3715 case Intrinsic::arm_neon_vqshiftnsu:
3716 VShiftOpc = ARMISD::VQSHRNsu; break;
3717 case Intrinsic::arm_neon_vqrshiftns:
3718 VShiftOpc = ARMISD::VQRSHRNs; break;
3719 case Intrinsic::arm_neon_vqrshiftnu:
3720 VShiftOpc = ARMISD::VQRSHRNu; break;
3721 case Intrinsic::arm_neon_vqrshiftnsu:
3722 VShiftOpc = ARMISD::VQRSHRNsu; break;
3725 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
3726 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
3729 case Intrinsic::arm_neon_vshiftins: {
3730 EVT VT = N->getOperand(1).getValueType();
3732 unsigned VShiftOpc = 0;
3734 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
3735 VShiftOpc = ARMISD::VSLI;
3736 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
3737 VShiftOpc = ARMISD::VSRI;
3739 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
3742 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
3743 N->getOperand(1), N->getOperand(2),
3744 DAG.getConstant(Cnt, MVT::i32));
3747 case Intrinsic::arm_neon_vqrshifts:
3748 case Intrinsic::arm_neon_vqrshiftu:
3749 // No immediate versions of these to check for.
3756 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
3757 /// lowers them. As with the vector shift intrinsics, this is done during DAG
3758 /// combining instead of DAG legalizing because the build_vectors for 64-bit
3759 /// vector element shift counts are generally not legal, and it is hard to see
3760 /// their values after they get legalized to loads from a constant pool.
3761 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
3762 const ARMSubtarget *ST) {
3763 EVT VT = N->getValueType(0);
3765 // Nothing to be done for scalar shifts.
3766 if (! VT.isVector())
3769 assert(ST->hasNEON() && "unexpected vector shift");
3772 switch (N->getOpcode()) {
3773 default: llvm_unreachable("unexpected shift opcode");
3776 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
3777 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
3778 DAG.getConstant(Cnt, MVT::i32));
3783 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
3784 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
3785 ARMISD::VSHRs : ARMISD::VSHRu);
3786 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
3787 DAG.getConstant(Cnt, MVT::i32));
3793 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
3794 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
3795 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
3796 const ARMSubtarget *ST) {
3797 SDValue N0 = N->getOperand(0);
3799 // Check for sign- and zero-extensions of vector extract operations of 8-
3800 // and 16-bit vector elements. NEON supports these directly. They are
3801 // handled during DAG combining because type legalization will promote them
3802 // to 32-bit types and it is messy to recognize the operations after that.
3803 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
3804 SDValue Vec = N0.getOperand(0);
3805 SDValue Lane = N0.getOperand(1);
3806 EVT VT = N->getValueType(0);
3807 EVT EltVT = N0.getValueType();
3808 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3810 if (VT == MVT::i32 &&
3811 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
3812 TLI.isTypeLegal(Vec.getValueType())) {
3815 switch (N->getOpcode()) {
3816 default: llvm_unreachable("unexpected opcode");
3817 case ISD::SIGN_EXTEND:
3818 Opc = ARMISD::VGETLANEs;
3820 case ISD::ZERO_EXTEND:
3821 case ISD::ANY_EXTEND:
3822 Opc = ARMISD::VGETLANEu;
3825 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
3832 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
3833 DAGCombinerInfo &DCI) const {
3834 switch (N->getOpcode()) {
3836 case ISD::ADD: return PerformADDCombine(N, DCI);
3837 case ISD::SUB: return PerformSUBCombine(N, DCI);
3838 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
3839 case ISD::INTRINSIC_WO_CHAIN:
3840 return PerformIntrinsicCombine(N, DCI.DAG);
3844 return PerformShiftCombine(N, DCI.DAG, Subtarget);
3845 case ISD::SIGN_EXTEND:
3846 case ISD::ZERO_EXTEND:
3847 case ISD::ANY_EXTEND:
3848 return PerformExtendCombine(N, DCI.DAG, Subtarget);
3853 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
3854 if (!Subtarget->hasV6Ops())
3855 // Pre-v6 does not support unaligned mem access.
3857 else if (!Subtarget->hasV6Ops()) {
3858 // v6 may or may not support unaligned mem access.
3859 if (!Subtarget->isTargetDarwin())
3863 switch (VT.getSimpleVT().SimpleTy) {
3870 // FIXME: VLD1 etc with standard alignment is legal.
3874 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
3879 switch (VT.getSimpleVT().SimpleTy) {
3880 default: return false;
3895 if ((V & (Scale - 1)) != 0)
3898 return V == (V & ((1LL << 5) - 1));
3901 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
3902 const ARMSubtarget *Subtarget) {
3909 switch (VT.getSimpleVT().SimpleTy) {
3910 default: return false;
3915 // + imm12 or - imm8
3917 return V == (V & ((1LL << 8) - 1));
3918 return V == (V & ((1LL << 12) - 1));
3921 // Same as ARM mode. FIXME: NEON?
3922 if (!Subtarget->hasVFP2())
3927 return V == (V & ((1LL << 8) - 1));
3931 /// isLegalAddressImmediate - Return true if the integer value can be used
3932 /// as the offset of the target addressing mode for load / store of the
3934 static bool isLegalAddressImmediate(int64_t V, EVT VT,
3935 const ARMSubtarget *Subtarget) {
3942 if (Subtarget->isThumb1Only())
3943 return isLegalT1AddressImmediate(V, VT);
3944 else if (Subtarget->isThumb2())
3945 return isLegalT2AddressImmediate(V, VT, Subtarget);
3950 switch (VT.getSimpleVT().SimpleTy) {
3951 default: return false;
3956 return V == (V & ((1LL << 12) - 1));
3959 return V == (V & ((1LL << 8) - 1));
3962 if (!Subtarget->hasVFP2()) // FIXME: NEON?
3967 return V == (V & ((1LL << 8) - 1));
3971 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
3973 int Scale = AM.Scale;
3977 switch (VT.getSimpleVT().SimpleTy) {
3978 default: return false;
3987 return Scale == 2 || Scale == 4 || Scale == 8;
3990 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
3994 // Note, we allow "void" uses (basically, uses that aren't loads or
3995 // stores), because arm allows folding a scale into many arithmetic
3996 // operations. This should be made more precise and revisited later.
3998 // Allow r << imm, but the imm has to be a multiple of two.
3999 if (Scale & 1) return false;
4000 return isPowerOf2_32(Scale);
4004 /// isLegalAddressingMode - Return true if the addressing mode represented
4005 /// by AM is legal for this target, for a load/store of the specified type.
4006 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
4007 const Type *Ty) const {
4008 EVT VT = getValueType(Ty, true);
4009 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
4012 // Can never fold addr of global into load/store.
4017 case 0: // no scale reg, must be "r+i" or "r", or "i".
4020 if (Subtarget->isThumb1Only())
4024 // ARM doesn't support any R+R*scale+imm addr modes.
4031 if (Subtarget->isThumb2())
4032 return isLegalT2ScaledAddressingMode(AM, VT);
4034 int Scale = AM.Scale;
4035 switch (VT.getSimpleVT().SimpleTy) {
4036 default: return false;
4040 if (Scale < 0) Scale = -Scale;
4044 return isPowerOf2_32(Scale & ~1);
4048 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
4053 // Note, we allow "void" uses (basically, uses that aren't loads or
4054 // stores), because arm allows folding a scale into many arithmetic
4055 // operations. This should be made more precise and revisited later.
4057 // Allow r << imm, but the imm has to be a multiple of two.
4058 if (Scale & 1) return false;
4059 return isPowerOf2_32(Scale);
4066 /// isLegalICmpImmediate - Return true if the specified immediate is legal
4067 /// icmp immediate, that is the target has icmp instructions which can compare
4068 /// a register against the immediate without having to materialize the
4069 /// immediate into a register.
4070 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
4071 if (!Subtarget->isThumb())
4072 return ARM_AM::getSOImmVal(Imm) != -1;
4073 if (Subtarget->isThumb2())
4074 return ARM_AM::getT2SOImmVal(Imm) != -1;
4075 return Imm >= 0 && Imm <= 255;
4078 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
4079 bool isSEXTLoad, SDValue &Base,
4080 SDValue &Offset, bool &isInc,
4081 SelectionDAG &DAG) {
4082 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
4085 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
4087 Base = Ptr->getOperand(0);
4088 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
4089 int RHSC = (int)RHS->getZExtValue();
4090 if (RHSC < 0 && RHSC > -256) {
4091 assert(Ptr->getOpcode() == ISD::ADD);
4093 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
4097 isInc = (Ptr->getOpcode() == ISD::ADD);
4098 Offset = Ptr->getOperand(1);
4100 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
4102 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
4103 int RHSC = (int)RHS->getZExtValue();
4104 if (RHSC < 0 && RHSC > -0x1000) {
4105 assert(Ptr->getOpcode() == ISD::ADD);
4107 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
4108 Base = Ptr->getOperand(0);
4113 if (Ptr->getOpcode() == ISD::ADD) {
4115 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
4116 if (ShOpcVal != ARM_AM::no_shift) {
4117 Base = Ptr->getOperand(1);
4118 Offset = Ptr->getOperand(0);
4120 Base = Ptr->getOperand(0);
4121 Offset = Ptr->getOperand(1);
4126 isInc = (Ptr->getOpcode() == ISD::ADD);
4127 Base = Ptr->getOperand(0);
4128 Offset = Ptr->getOperand(1);
4132 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
4136 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
4137 bool isSEXTLoad, SDValue &Base,
4138 SDValue &Offset, bool &isInc,
4139 SelectionDAG &DAG) {
4140 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
4143 Base = Ptr->getOperand(0);
4144 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
4145 int RHSC = (int)RHS->getZExtValue();
4146 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
4147 assert(Ptr->getOpcode() == ISD::ADD);
4149 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
4151 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
4152 isInc = Ptr->getOpcode() == ISD::ADD;
4153 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
4161 /// getPreIndexedAddressParts - returns true by value, base pointer and
4162 /// offset pointer and addressing mode by reference if the node's address
4163 /// can be legally represented as pre-indexed load / store address.
4165 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
4167 ISD::MemIndexedMode &AM,
4168 SelectionDAG &DAG) const {
4169 if (Subtarget->isThumb1Only())
4174 bool isSEXTLoad = false;
4175 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4176 Ptr = LD->getBasePtr();
4177 VT = LD->getMemoryVT();
4178 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
4179 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4180 Ptr = ST->getBasePtr();
4181 VT = ST->getMemoryVT();
4186 bool isLegal = false;
4187 if (Subtarget->isThumb2())
4188 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
4189 Offset, isInc, DAG);
4191 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
4192 Offset, isInc, DAG);
4196 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
4200 /// getPostIndexedAddressParts - returns true by value, base pointer and
4201 /// offset pointer and addressing mode by reference if this node can be
4202 /// combined with a load / store to form a post-indexed load / store.
4203 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
4206 ISD::MemIndexedMode &AM,
4207 SelectionDAG &DAG) const {
4208 if (Subtarget->isThumb1Only())
4213 bool isSEXTLoad = false;
4214 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4215 VT = LD->getMemoryVT();
4216 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
4217 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4218 VT = ST->getMemoryVT();
4223 bool isLegal = false;
4224 if (Subtarget->isThumb2())
4225 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
4228 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
4233 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
4237 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
4241 const SelectionDAG &DAG,
4242 unsigned Depth) const {
4243 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
4244 switch (Op.getOpcode()) {
4246 case ARMISD::CMOV: {
4247 // Bits are known zero/one if known on the LHS and RHS.
4248 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
4249 if (KnownZero == 0 && KnownOne == 0) return;
4251 APInt KnownZeroRHS, KnownOneRHS;
4252 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
4253 KnownZeroRHS, KnownOneRHS, Depth+1);
4254 KnownZero &= KnownZeroRHS;
4255 KnownOne &= KnownOneRHS;
4261 //===----------------------------------------------------------------------===//
4262 // ARM Inline Assembly Support
4263 //===----------------------------------------------------------------------===//
4265 /// getConstraintType - Given a constraint letter, return the type of
4266 /// constraint it is for this target.
4267 ARMTargetLowering::ConstraintType
4268 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
4269 if (Constraint.size() == 1) {
4270 switch (Constraint[0]) {
4272 case 'l': return C_RegisterClass;
4273 case 'w': return C_RegisterClass;
4276 return TargetLowering::getConstraintType(Constraint);
4279 std::pair<unsigned, const TargetRegisterClass*>
4280 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
4282 if (Constraint.size() == 1) {
4283 // GCC ARM Constraint Letters
4284 switch (Constraint[0]) {
4286 if (Subtarget->isThumb())
4287 return std::make_pair(0U, ARM::tGPRRegisterClass);
4289 return std::make_pair(0U, ARM::GPRRegisterClass);
4291 return std::make_pair(0U, ARM::GPRRegisterClass);
4294 return std::make_pair(0U, ARM::SPRRegisterClass);
4295 if (VT.getSizeInBits() == 64)
4296 return std::make_pair(0U, ARM::DPRRegisterClass);
4297 if (VT.getSizeInBits() == 128)
4298 return std::make_pair(0U, ARM::QPRRegisterClass);
4302 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
4305 std::vector<unsigned> ARMTargetLowering::
4306 getRegClassForInlineAsmConstraint(const std::string &Constraint,
4308 if (Constraint.size() != 1)
4309 return std::vector<unsigned>();
4311 switch (Constraint[0]) { // GCC ARM Constraint Letters
4314 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
4315 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
4318 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
4319 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
4320 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
4321 ARM::R12, ARM::LR, 0);
4324 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
4325 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
4326 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
4327 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
4328 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
4329 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
4330 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
4331 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
4332 if (VT.getSizeInBits() == 64)
4333 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
4334 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
4335 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
4336 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
4337 if (VT.getSizeInBits() == 128)
4338 return make_vector<unsigned>(ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
4339 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 0);
4343 return std::vector<unsigned>();
4346 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
4347 /// vector. If it is invalid, don't add anything to Ops.
4348 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
4351 std::vector<SDValue>&Ops,
4352 SelectionDAG &DAG) const {
4353 SDValue Result(0, 0);
4355 switch (Constraint) {
4357 case 'I': case 'J': case 'K': case 'L':
4358 case 'M': case 'N': case 'O':
4359 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
4363 int64_t CVal64 = C->getSExtValue();
4364 int CVal = (int) CVal64;
4365 // None of these constraints allow values larger than 32 bits. Check
4366 // that the value fits in an int.
4370 switch (Constraint) {
4372 if (Subtarget->isThumb1Only()) {
4373 // This must be a constant between 0 and 255, for ADD
4375 if (CVal >= 0 && CVal <= 255)
4377 } else if (Subtarget->isThumb2()) {
4378 // A constant that can be used as an immediate value in a
4379 // data-processing instruction.
4380 if (ARM_AM::getT2SOImmVal(CVal) != -1)
4383 // A constant that can be used as an immediate value in a
4384 // data-processing instruction.
4385 if (ARM_AM::getSOImmVal(CVal) != -1)
4391 if (Subtarget->isThumb()) { // FIXME thumb2
4392 // This must be a constant between -255 and -1, for negated ADD
4393 // immediates. This can be used in GCC with an "n" modifier that
4394 // prints the negated value, for use with SUB instructions. It is
4395 // not useful otherwise but is implemented for compatibility.
4396 if (CVal >= -255 && CVal <= -1)
4399 // This must be a constant between -4095 and 4095. It is not clear
4400 // what this constraint is intended for. Implemented for
4401 // compatibility with GCC.
4402 if (CVal >= -4095 && CVal <= 4095)
4408 if (Subtarget->isThumb1Only()) {
4409 // A 32-bit value where only one byte has a nonzero value. Exclude
4410 // zero to match GCC. This constraint is used by GCC internally for
4411 // constants that can be loaded with a move/shift combination.
4412 // It is not useful otherwise but is implemented for compatibility.
4413 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
4415 } else if (Subtarget->isThumb2()) {
4416 // A constant whose bitwise inverse can be used as an immediate
4417 // value in a data-processing instruction. This can be used in GCC
4418 // with a "B" modifier that prints the inverted value, for use with
4419 // BIC and MVN instructions. It is not useful otherwise but is
4420 // implemented for compatibility.
4421 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
4424 // A constant whose bitwise inverse can be used as an immediate
4425 // value in a data-processing instruction. This can be used in GCC
4426 // with a "B" modifier that prints the inverted value, for use with
4427 // BIC and MVN instructions. It is not useful otherwise but is
4428 // implemented for compatibility.
4429 if (ARM_AM::getSOImmVal(~CVal) != -1)
4435 if (Subtarget->isThumb1Only()) {
4436 // This must be a constant between -7 and 7,
4437 // for 3-operand ADD/SUB immediate instructions.
4438 if (CVal >= -7 && CVal < 7)
4440 } else if (Subtarget->isThumb2()) {
4441 // A constant whose negation can be used as an immediate value in a
4442 // data-processing instruction. This can be used in GCC with an "n"
4443 // modifier that prints the negated value, for use with SUB
4444 // instructions. It is not useful otherwise but is implemented for
4446 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
4449 // A constant whose negation can be used as an immediate value in a
4450 // data-processing instruction. This can be used in GCC with an "n"
4451 // modifier that prints the negated value, for use with SUB
4452 // instructions. It is not useful otherwise but is implemented for
4454 if (ARM_AM::getSOImmVal(-CVal) != -1)
4460 if (Subtarget->isThumb()) { // FIXME thumb2
4461 // This must be a multiple of 4 between 0 and 1020, for
4462 // ADD sp + immediate.
4463 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
4466 // A power of two or a constant between 0 and 32. This is used in
4467 // GCC for the shift amount on shifted register operands, but it is
4468 // useful in general for any shift amounts.
4469 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
4475 if (Subtarget->isThumb()) { // FIXME thumb2
4476 // This must be a constant between 0 and 31, for shift amounts.
4477 if (CVal >= 0 && CVal <= 31)
4483 if (Subtarget->isThumb()) { // FIXME thumb2
4484 // This must be a multiple of 4 between -508 and 508, for
4485 // ADD/SUB sp = sp + immediate.
4486 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
4491 Result = DAG.getTargetConstant(CVal, Op.getValueType());
4495 if (Result.getNode()) {
4496 Ops.push_back(Result);
4499 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,
4504 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
4505 // The ARM target isn't yet aware of offsets.
4509 int ARM::getVFPf32Imm(const APFloat &FPImm) {
4510 APInt Imm = FPImm.bitcastToAPInt();
4511 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
4512 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127
4513 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits
4515 // We can handle 4 bits of mantissa.
4516 // mantissa = (16+UInt(e:f:g:h))/16.
4517 if (Mantissa & 0x7ffff)
4520 if ((Mantissa & 0xf) != Mantissa)
4523 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
4524 if (Exp < -3 || Exp > 4)
4526 Exp = ((Exp+3) & 0x7) ^ 4;
4528 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
4531 int ARM::getVFPf64Imm(const APFloat &FPImm) {
4532 APInt Imm = FPImm.bitcastToAPInt();
4533 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
4534 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
4535 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffLL;
4537 // We can handle 4 bits of mantissa.
4538 // mantissa = (16+UInt(e:f:g:h))/16.
4539 if (Mantissa & 0xffffffffffffLL)
4542 if ((Mantissa & 0xf) != Mantissa)
4545 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
4546 if (Exp < -3 || Exp > 4)
4548 Exp = ((Exp+3) & 0x7) ^ 4;
4550 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
4553 /// isFPImmLegal - Returns true if the target can instruction select the
4554 /// specified FP immediate natively. If false, the legalizer will
4555 /// materialize the FP immediate as a load from a constant pool.
4556 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4557 if (!Subtarget->hasVFP3())
4560 return ARM::getVFPf32Imm(Imm) != -1;
4562 return ARM::getVFPf64Imm(Imm) != -1;