1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "arm-isel"
17 #include "ARMAddressingModes.h"
18 #include "ARMCallingConv.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMISelLowering.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMPerfectShuffle.h"
23 #include "ARMRegisterInfo.h"
24 #include "ARMSubtarget.h"
25 #include "ARMTargetMachine.h"
26 #include "ARMTargetObjectFile.h"
27 #include "llvm/CallingConv.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Function.h"
30 #include "llvm/GlobalValue.h"
31 #include "llvm/Instruction.h"
32 #include "llvm/Instructions.h"
33 #include "llvm/Intrinsics.h"
34 #include "llvm/Type.h"
35 #include "llvm/CodeGen/CallingConvLower.h"
36 #include "llvm/CodeGen/MachineBasicBlock.h"
37 #include "llvm/CodeGen/MachineFrameInfo.h"
38 #include "llvm/CodeGen/MachineFunction.h"
39 #include "llvm/CodeGen/MachineInstrBuilder.h"
40 #include "llvm/CodeGen/MachineRegisterInfo.h"
41 #include "llvm/CodeGen/PseudoSourceValue.h"
42 #include "llvm/CodeGen/SelectionDAG.h"
43 #include "llvm/MC/MCSectionMachO.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/ADT/VectorExtras.h"
46 #include "llvm/ADT/Statistic.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Support/raw_ostream.h"
54 STATISTIC(NumTailCalls, "Number of tail calls");
56 // This option should go away when tail calls fully work.
58 EnableARMTailCalls("arm-tail-calls", cl::Hidden,
59 cl::desc("Generate tail calls (TEMPORARY OPTION)."),
63 EnableARMLongCalls("arm-long-calls", cl::Hidden,
64 cl::desc("Generate calls via indirect call instructions"),
68 ARMInterworking("arm-interworking", cl::Hidden,
69 cl::desc("Enable / disable ARM interworking (for debugging only)"),
72 void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
73 EVT PromotedBitwiseVT) {
74 if (VT != PromotedLdStVT) {
75 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
76 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
77 PromotedLdStVT.getSimpleVT());
79 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
80 AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
81 PromotedLdStVT.getSimpleVT());
84 EVT ElemTy = VT.getVectorElementType();
85 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
86 setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
87 if (ElemTy == MVT::i8 || ElemTy == MVT::i16)
88 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
89 if (ElemTy != MVT::i32) {
90 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
91 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand);
92 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand);
93 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand);
95 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
96 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
97 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
98 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Expand);
99 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
100 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
101 if (VT.isInteger()) {
102 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
103 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
104 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
105 setLoadExtAction(ISD::SEXTLOAD, VT.getSimpleVT(), Expand);
106 setLoadExtAction(ISD::ZEXTLOAD, VT.getSimpleVT(), Expand);
107 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
108 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
109 setTruncStoreAction(VT.getSimpleVT(),
110 (MVT::SimpleValueType)InnerVT, Expand);
112 setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand);
114 // Promote all bit-wise operations.
115 if (VT.isInteger() && VT != PromotedBitwiseVT) {
116 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
117 AddPromotedToType (ISD::AND, VT.getSimpleVT(),
118 PromotedBitwiseVT.getSimpleVT());
119 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
120 AddPromotedToType (ISD::OR, VT.getSimpleVT(),
121 PromotedBitwiseVT.getSimpleVT());
122 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
123 AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
124 PromotedBitwiseVT.getSimpleVT());
127 // Neon does not support vector divide/remainder operations.
128 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
129 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
130 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand);
131 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
132 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
133 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
136 void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
137 addRegisterClass(VT, ARM::DPRRegisterClass);
138 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
141 void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
142 addRegisterClass(VT, ARM::QPRRegisterClass);
143 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
146 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
147 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
148 return new TargetLoweringObjectFileMachO();
150 return new ARMElfTargetObjectFile();
153 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
154 : TargetLowering(TM, createTLOF(TM)) {
155 Subtarget = &TM.getSubtarget<ARMSubtarget>();
156 RegInfo = TM.getRegisterInfo();
157 Itins = TM.getInstrItineraryData();
159 if (Subtarget->isTargetDarwin()) {
160 // Uses VFP for Thumb libfuncs if available.
161 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
162 // Single-precision floating-point arithmetic.
163 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
164 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
165 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
166 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
168 // Double-precision floating-point arithmetic.
169 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
170 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
171 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
172 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
174 // Single-precision comparisons.
175 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
176 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
177 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
178 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
179 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
180 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
181 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
182 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
184 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
185 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
186 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
187 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
188 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
189 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
190 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
191 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
193 // Double-precision comparisons.
194 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
195 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
196 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
197 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
198 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
199 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
200 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
201 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
203 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
204 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
205 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
206 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
207 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
208 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
209 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
210 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
212 // Floating-point to integer conversions.
213 // i64 conversions are done via library routines even when generating VFP
214 // instructions, so use the same ones.
215 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
216 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
217 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
218 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
220 // Conversions between floating types.
221 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
222 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
224 // Integer to floating-point conversions.
225 // i64 conversions are done via library routines even when generating VFP
226 // instructions, so use the same ones.
227 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
228 // e.g., __floatunsidf vs. __floatunssidfvfp.
229 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
230 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
231 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
232 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
236 // These libcalls are not available in 32-bit.
237 setLibcallName(RTLIB::SHL_I128, 0);
238 setLibcallName(RTLIB::SRL_I128, 0);
239 setLibcallName(RTLIB::SRA_I128, 0);
241 if (Subtarget->isAAPCS_ABI()) {
242 // Double-precision floating-point arithmetic helper functions
243 // RTABI chapter 4.1.2, Table 2
244 setLibcallName(RTLIB::ADD_F64, "__aeabi_dadd");
245 setLibcallName(RTLIB::DIV_F64, "__aeabi_ddiv");
246 setLibcallName(RTLIB::MUL_F64, "__aeabi_dmul");
247 setLibcallName(RTLIB::SUB_F64, "__aeabi_dsub");
248 setLibcallCallingConv(RTLIB::ADD_F64, CallingConv::ARM_AAPCS);
249 setLibcallCallingConv(RTLIB::DIV_F64, CallingConv::ARM_AAPCS);
250 setLibcallCallingConv(RTLIB::MUL_F64, CallingConv::ARM_AAPCS);
251 setLibcallCallingConv(RTLIB::SUB_F64, CallingConv::ARM_AAPCS);
253 // Double-precision floating-point comparison helper functions
254 // RTABI chapter 4.1.2, Table 3
255 setLibcallName(RTLIB::OEQ_F64, "__aeabi_dcmpeq");
256 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
257 setLibcallName(RTLIB::UNE_F64, "__aeabi_dcmpeq");
258 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETEQ);
259 setLibcallName(RTLIB::OLT_F64, "__aeabi_dcmplt");
260 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
261 setLibcallName(RTLIB::OLE_F64, "__aeabi_dcmple");
262 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
263 setLibcallName(RTLIB::OGE_F64, "__aeabi_dcmpge");
264 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
265 setLibcallName(RTLIB::OGT_F64, "__aeabi_dcmpgt");
266 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
267 setLibcallName(RTLIB::UO_F64, "__aeabi_dcmpun");
268 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
269 setLibcallName(RTLIB::O_F64, "__aeabi_dcmpun");
270 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
271 setLibcallCallingConv(RTLIB::OEQ_F64, CallingConv::ARM_AAPCS);
272 setLibcallCallingConv(RTLIB::UNE_F64, CallingConv::ARM_AAPCS);
273 setLibcallCallingConv(RTLIB::OLT_F64, CallingConv::ARM_AAPCS);
274 setLibcallCallingConv(RTLIB::OLE_F64, CallingConv::ARM_AAPCS);
275 setLibcallCallingConv(RTLIB::OGE_F64, CallingConv::ARM_AAPCS);
276 setLibcallCallingConv(RTLIB::OGT_F64, CallingConv::ARM_AAPCS);
277 setLibcallCallingConv(RTLIB::UO_F64, CallingConv::ARM_AAPCS);
278 setLibcallCallingConv(RTLIB::O_F64, CallingConv::ARM_AAPCS);
280 // Single-precision floating-point arithmetic helper functions
281 // RTABI chapter 4.1.2, Table 4
282 setLibcallName(RTLIB::ADD_F32, "__aeabi_fadd");
283 setLibcallName(RTLIB::DIV_F32, "__aeabi_fdiv");
284 setLibcallName(RTLIB::MUL_F32, "__aeabi_fmul");
285 setLibcallName(RTLIB::SUB_F32, "__aeabi_fsub");
286 setLibcallCallingConv(RTLIB::ADD_F32, CallingConv::ARM_AAPCS);
287 setLibcallCallingConv(RTLIB::DIV_F32, CallingConv::ARM_AAPCS);
288 setLibcallCallingConv(RTLIB::MUL_F32, CallingConv::ARM_AAPCS);
289 setLibcallCallingConv(RTLIB::SUB_F32, CallingConv::ARM_AAPCS);
291 // Single-precision floating-point comparison helper functions
292 // RTABI chapter 4.1.2, Table 5
293 setLibcallName(RTLIB::OEQ_F32, "__aeabi_fcmpeq");
294 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
295 setLibcallName(RTLIB::UNE_F32, "__aeabi_fcmpeq");
296 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETEQ);
297 setLibcallName(RTLIB::OLT_F32, "__aeabi_fcmplt");
298 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
299 setLibcallName(RTLIB::OLE_F32, "__aeabi_fcmple");
300 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
301 setLibcallName(RTLIB::OGE_F32, "__aeabi_fcmpge");
302 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
303 setLibcallName(RTLIB::OGT_F32, "__aeabi_fcmpgt");
304 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
305 setLibcallName(RTLIB::UO_F32, "__aeabi_fcmpun");
306 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
307 setLibcallName(RTLIB::O_F32, "__aeabi_fcmpun");
308 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
309 setLibcallCallingConv(RTLIB::OEQ_F32, CallingConv::ARM_AAPCS);
310 setLibcallCallingConv(RTLIB::UNE_F32, CallingConv::ARM_AAPCS);
311 setLibcallCallingConv(RTLIB::OLT_F32, CallingConv::ARM_AAPCS);
312 setLibcallCallingConv(RTLIB::OLE_F32, CallingConv::ARM_AAPCS);
313 setLibcallCallingConv(RTLIB::OGE_F32, CallingConv::ARM_AAPCS);
314 setLibcallCallingConv(RTLIB::OGT_F32, CallingConv::ARM_AAPCS);
315 setLibcallCallingConv(RTLIB::UO_F32, CallingConv::ARM_AAPCS);
316 setLibcallCallingConv(RTLIB::O_F32, CallingConv::ARM_AAPCS);
318 // Floating-point to integer conversions.
319 // RTABI chapter 4.1.2, Table 6
320 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz");
321 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz");
322 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz");
323 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz");
324 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz");
325 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz");
326 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz");
327 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz");
328 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I32, CallingConv::ARM_AAPCS);
329 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I32, CallingConv::ARM_AAPCS);
330 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I64, CallingConv::ARM_AAPCS);
331 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::ARM_AAPCS);
332 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I32, CallingConv::ARM_AAPCS);
333 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I32, CallingConv::ARM_AAPCS);
334 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I64, CallingConv::ARM_AAPCS);
335 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::ARM_AAPCS);
337 // Conversions between floating types.
338 // RTABI chapter 4.1.2, Table 7
339 setLibcallName(RTLIB::FPROUND_F64_F32, "__aeabi_d2f");
340 setLibcallName(RTLIB::FPEXT_F32_F64, "__aeabi_f2d");
341 setLibcallCallingConv(RTLIB::FPROUND_F64_F32, CallingConv::ARM_AAPCS);
342 setLibcallCallingConv(RTLIB::FPEXT_F32_F64, CallingConv::ARM_AAPCS);
344 // Integer to floating-point conversions.
345 // RTABI chapter 4.1.2, Table 8
346 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d");
347 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d");
348 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d");
349 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d");
350 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f");
351 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f");
352 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f");
353 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f");
354 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
355 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
356 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
357 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
358 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
359 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
360 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
361 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
363 // Long long helper functions
364 // RTABI chapter 4.2, Table 9
365 setLibcallName(RTLIB::MUL_I64, "__aeabi_lmul");
366 setLibcallName(RTLIB::SDIV_I64, "__aeabi_ldivmod");
367 setLibcallName(RTLIB::UDIV_I64, "__aeabi_uldivmod");
368 setLibcallName(RTLIB::SHL_I64, "__aeabi_llsl");
369 setLibcallName(RTLIB::SRL_I64, "__aeabi_llsr");
370 setLibcallName(RTLIB::SRA_I64, "__aeabi_lasr");
371 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::ARM_AAPCS);
372 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::ARM_AAPCS);
373 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::ARM_AAPCS);
374 setLibcallCallingConv(RTLIB::SHL_I64, CallingConv::ARM_AAPCS);
375 setLibcallCallingConv(RTLIB::SRL_I64, CallingConv::ARM_AAPCS);
376 setLibcallCallingConv(RTLIB::SRA_I64, CallingConv::ARM_AAPCS);
378 // Integer division functions
379 // RTABI chapter 4.3.1
380 setLibcallName(RTLIB::SDIV_I8, "__aeabi_idiv");
381 setLibcallName(RTLIB::SDIV_I16, "__aeabi_idiv");
382 setLibcallName(RTLIB::SDIV_I32, "__aeabi_idiv");
383 setLibcallName(RTLIB::UDIV_I8, "__aeabi_uidiv");
384 setLibcallName(RTLIB::UDIV_I16, "__aeabi_uidiv");
385 setLibcallName(RTLIB::UDIV_I32, "__aeabi_uidiv");
386 setLibcallCallingConv(RTLIB::SDIV_I8, CallingConv::ARM_AAPCS);
387 setLibcallCallingConv(RTLIB::SDIV_I16, CallingConv::ARM_AAPCS);
388 setLibcallCallingConv(RTLIB::SDIV_I32, CallingConv::ARM_AAPCS);
389 setLibcallCallingConv(RTLIB::UDIV_I8, CallingConv::ARM_AAPCS);
390 setLibcallCallingConv(RTLIB::UDIV_I16, CallingConv::ARM_AAPCS);
391 setLibcallCallingConv(RTLIB::UDIV_I32, CallingConv::ARM_AAPCS);
394 if (Subtarget->isThumb1Only())
395 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
397 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
398 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
399 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
400 if (!Subtarget->isFPOnlySP())
401 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
403 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
406 if (Subtarget->hasNEON()) {
407 addDRTypeForNEON(MVT::v2f32);
408 addDRTypeForNEON(MVT::v8i8);
409 addDRTypeForNEON(MVT::v4i16);
410 addDRTypeForNEON(MVT::v2i32);
411 addDRTypeForNEON(MVT::v1i64);
413 addQRTypeForNEON(MVT::v4f32);
414 addQRTypeForNEON(MVT::v2f64);
415 addQRTypeForNEON(MVT::v16i8);
416 addQRTypeForNEON(MVT::v8i16);
417 addQRTypeForNEON(MVT::v4i32);
418 addQRTypeForNEON(MVT::v2i64);
420 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
421 // neither Neon nor VFP support any arithmetic operations on it.
422 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
423 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
424 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
425 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
426 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
427 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
428 setOperationAction(ISD::VSETCC, MVT::v2f64, Expand);
429 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
430 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
431 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
432 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
433 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
434 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
435 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
436 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
437 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
438 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
439 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
440 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
441 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
442 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
443 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
444 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
445 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
447 setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand);
449 // Neon does not support some operations on v1i64 and v2i64 types.
450 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
451 // Custom handling for some quad-vector types to detect VMULL.
452 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
453 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
454 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
455 setOperationAction(ISD::VSETCC, MVT::v1i64, Expand);
456 setOperationAction(ISD::VSETCC, MVT::v2i64, Expand);
458 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
459 setTargetDAGCombine(ISD::SHL);
460 setTargetDAGCombine(ISD::SRL);
461 setTargetDAGCombine(ISD::SRA);
462 setTargetDAGCombine(ISD::SIGN_EXTEND);
463 setTargetDAGCombine(ISD::ZERO_EXTEND);
464 setTargetDAGCombine(ISD::ANY_EXTEND);
465 setTargetDAGCombine(ISD::SELECT_CC);
466 setTargetDAGCombine(ISD::BUILD_VECTOR);
467 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
470 computeRegisterProperties();
472 // ARM does not have f32 extending load.
473 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
475 // ARM does not have i1 sign extending load.
476 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
478 // ARM supports all 4 flavors of integer indexed load / store.
479 if (!Subtarget->isThumb1Only()) {
480 for (unsigned im = (unsigned)ISD::PRE_INC;
481 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
482 setIndexedLoadAction(im, MVT::i1, Legal);
483 setIndexedLoadAction(im, MVT::i8, Legal);
484 setIndexedLoadAction(im, MVT::i16, Legal);
485 setIndexedLoadAction(im, MVT::i32, Legal);
486 setIndexedStoreAction(im, MVT::i1, Legal);
487 setIndexedStoreAction(im, MVT::i8, Legal);
488 setIndexedStoreAction(im, MVT::i16, Legal);
489 setIndexedStoreAction(im, MVT::i32, Legal);
493 // i64 operation support.
494 if (Subtarget->isThumb1Only()) {
495 setOperationAction(ISD::MUL, MVT::i64, Expand);
496 setOperationAction(ISD::MULHU, MVT::i32, Expand);
497 setOperationAction(ISD::MULHS, MVT::i32, Expand);
498 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
499 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
501 setOperationAction(ISD::MUL, MVT::i64, Expand);
502 setOperationAction(ISD::MULHU, MVT::i32, Expand);
503 if (!Subtarget->hasV6Ops())
504 setOperationAction(ISD::MULHS, MVT::i32, Expand);
506 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
507 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
508 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
509 setOperationAction(ISD::SRL, MVT::i64, Custom);
510 setOperationAction(ISD::SRA, MVT::i64, Custom);
512 // ARM does not have ROTL.
513 setOperationAction(ISD::ROTL, MVT::i32, Expand);
514 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
515 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
516 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
517 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
519 // Only ARMv6 has BSWAP.
520 if (!Subtarget->hasV6Ops())
521 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
523 // These are expanded into libcalls.
524 if (!Subtarget->hasDivide()) {
525 // v7M has a hardware divider
526 setOperationAction(ISD::SDIV, MVT::i32, Expand);
527 setOperationAction(ISD::UDIV, MVT::i32, Expand);
529 setOperationAction(ISD::SREM, MVT::i32, Expand);
530 setOperationAction(ISD::UREM, MVT::i32, Expand);
531 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
532 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
534 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
535 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
536 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
537 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
538 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
540 setOperationAction(ISD::TRAP, MVT::Other, Legal);
542 // Use the default implementation.
543 setOperationAction(ISD::VASTART, MVT::Other, Custom);
544 setOperationAction(ISD::VAARG, MVT::Other, Expand);
545 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
546 setOperationAction(ISD::VAEND, MVT::Other, Expand);
547 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
548 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
549 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
550 // FIXME: Shouldn't need this, since no register is used, but the legalizer
551 // doesn't yet know how to not do that for SjLj.
552 setExceptionSelectorRegister(ARM::R0);
553 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
554 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
555 // the default expansion.
556 if (Subtarget->hasDataBarrier() ||
557 (Subtarget->hasV6Ops() && !Subtarget->isThumb1Only())) {
558 // membarrier needs custom lowering; the rest are legal and handled
560 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
562 // Set them all for expansion, which will force libcalls.
563 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
564 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Expand);
565 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Expand);
566 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
567 setOperationAction(ISD::ATOMIC_SWAP, MVT::i8, Expand);
568 setOperationAction(ISD::ATOMIC_SWAP, MVT::i16, Expand);
569 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
570 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i8, Expand);
571 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i16, Expand);
572 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
573 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Expand);
574 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Expand);
575 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
576 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i8, Expand);
577 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i16, Expand);
578 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
579 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i8, Expand);
580 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i16, Expand);
581 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
582 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i8, Expand);
583 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i16, Expand);
584 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
585 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i8, Expand);
586 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i16, Expand);
587 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
588 // Since the libcalls include locking, fold in the fences
589 setShouldFoldAtomicFences(true);
591 // 64-bit versions are always libcalls (for now)
592 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Expand);
593 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Expand);
594 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Expand);
595 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Expand);
596 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Expand);
597 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Expand);
598 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Expand);
599 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Expand);
601 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
602 if (!Subtarget->hasV6Ops()) {
603 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
604 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
606 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
608 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
609 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
610 // iff target supports vfp2.
611 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
612 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
615 // We want to custom lower some of our intrinsics.
616 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
617 if (Subtarget->isTargetDarwin()) {
618 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
619 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
620 setOperationAction(ISD::EH_SJLJ_DISPATCHSETUP, MVT::Other, Custom);
623 setOperationAction(ISD::SETCC, MVT::i32, Expand);
624 setOperationAction(ISD::SETCC, MVT::f32, Expand);
625 setOperationAction(ISD::SETCC, MVT::f64, Expand);
626 setOperationAction(ISD::SELECT, MVT::i32, Custom);
627 setOperationAction(ISD::SELECT, MVT::f32, Custom);
628 setOperationAction(ISD::SELECT, MVT::f64, Custom);
629 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
630 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
631 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
633 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
634 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
635 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
636 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
637 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
639 // We don't support sin/cos/fmod/copysign/pow
640 setOperationAction(ISD::FSIN, MVT::f64, Expand);
641 setOperationAction(ISD::FSIN, MVT::f32, Expand);
642 setOperationAction(ISD::FCOS, MVT::f32, Expand);
643 setOperationAction(ISD::FCOS, MVT::f64, Expand);
644 setOperationAction(ISD::FREM, MVT::f64, Expand);
645 setOperationAction(ISD::FREM, MVT::f32, Expand);
646 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
647 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
648 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
650 setOperationAction(ISD::FPOW, MVT::f64, Expand);
651 setOperationAction(ISD::FPOW, MVT::f32, Expand);
653 // Various VFP goodness
654 if (!UseSoftFloat && !Subtarget->isThumb1Only()) {
655 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
656 if (Subtarget->hasVFP2()) {
657 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
658 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
659 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
660 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
662 // Special handling for half-precision FP.
663 if (!Subtarget->hasFP16()) {
664 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
665 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand);
669 // We have target-specific dag combine patterns for the following nodes:
670 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
671 setTargetDAGCombine(ISD::ADD);
672 setTargetDAGCombine(ISD::SUB);
673 setTargetDAGCombine(ISD::MUL);
675 if (Subtarget->hasV6T2Ops())
676 setTargetDAGCombine(ISD::OR);
678 setStackPointerRegisterToSaveRestore(ARM::SP);
680 if (UseSoftFloat || Subtarget->isThumb1Only() || !Subtarget->hasVFP2())
681 setSchedulingPreference(Sched::RegPressure);
683 setSchedulingPreference(Sched::Hybrid);
685 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
687 // On ARM arguments smaller than 4 bytes are extended, so all arguments
688 // are at least 4 bytes aligned.
689 setMinStackArgumentAlignment(4);
691 benefitFromCodePlacementOpt = true;
694 std::pair<const TargetRegisterClass*, uint8_t>
695 ARMTargetLowering::findRepresentativeClass(EVT VT) const{
696 const TargetRegisterClass *RRC = 0;
698 switch (VT.getSimpleVT().SimpleTy) {
700 return TargetLowering::findRepresentativeClass(VT);
701 // Use DPR as representative register class for all floating point
702 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
703 // the cost is 1 for both f32 and f64.
704 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
705 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
706 RRC = ARM::DPRRegisterClass;
708 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
709 case MVT::v4f32: case MVT::v2f64:
710 RRC = ARM::DPRRegisterClass;
714 RRC = ARM::DPRRegisterClass;
718 RRC = ARM::DPRRegisterClass;
722 return std::make_pair(RRC, Cost);
725 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
728 case ARMISD::Wrapper: return "ARMISD::Wrapper";
729 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
730 case ARMISD::CALL: return "ARMISD::CALL";
731 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
732 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
733 case ARMISD::tCALL: return "ARMISD::tCALL";
734 case ARMISD::BRCOND: return "ARMISD::BRCOND";
735 case ARMISD::BR_JT: return "ARMISD::BR_JT";
736 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
737 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
738 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
739 case ARMISD::CMP: return "ARMISD::CMP";
740 case ARMISD::CMPZ: return "ARMISD::CMPZ";
741 case ARMISD::CMPFP: return "ARMISD::CMPFP";
742 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
743 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
744 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
745 case ARMISD::CMOV: return "ARMISD::CMOV";
746 case ARMISD::CNEG: return "ARMISD::CNEG";
748 case ARMISD::RBIT: return "ARMISD::RBIT";
750 case ARMISD::FTOSI: return "ARMISD::FTOSI";
751 case ARMISD::FTOUI: return "ARMISD::FTOUI";
752 case ARMISD::SITOF: return "ARMISD::SITOF";
753 case ARMISD::UITOF: return "ARMISD::UITOF";
755 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
756 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
757 case ARMISD::RRX: return "ARMISD::RRX";
759 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
760 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
762 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
763 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
764 case ARMISD::EH_SJLJ_DISPATCHSETUP:return "ARMISD::EH_SJLJ_DISPATCHSETUP";
766 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
768 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
770 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
772 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER";
773 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
775 case ARMISD::VCEQ: return "ARMISD::VCEQ";
776 case ARMISD::VCGE: return "ARMISD::VCGE";
777 case ARMISD::VCGEU: return "ARMISD::VCGEU";
778 case ARMISD::VCGT: return "ARMISD::VCGT";
779 case ARMISD::VCGTU: return "ARMISD::VCGTU";
780 case ARMISD::VTST: return "ARMISD::VTST";
782 case ARMISD::VSHL: return "ARMISD::VSHL";
783 case ARMISD::VSHRs: return "ARMISD::VSHRs";
784 case ARMISD::VSHRu: return "ARMISD::VSHRu";
785 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
786 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
787 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
788 case ARMISD::VSHRN: return "ARMISD::VSHRN";
789 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
790 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
791 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
792 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
793 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
794 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
795 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
796 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
797 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
798 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
799 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
800 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
801 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
802 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
803 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
804 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
805 case ARMISD::VDUP: return "ARMISD::VDUP";
806 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
807 case ARMISD::VEXT: return "ARMISD::VEXT";
808 case ARMISD::VREV64: return "ARMISD::VREV64";
809 case ARMISD::VREV32: return "ARMISD::VREV32";
810 case ARMISD::VREV16: return "ARMISD::VREV16";
811 case ARMISD::VZIP: return "ARMISD::VZIP";
812 case ARMISD::VUZP: return "ARMISD::VUZP";
813 case ARMISD::VTRN: return "ARMISD::VTRN";
814 case ARMISD::VMULLs: return "ARMISD::VMULLs";
815 case ARMISD::VMULLu: return "ARMISD::VMULLu";
816 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
817 case ARMISD::FMAX: return "ARMISD::FMAX";
818 case ARMISD::FMIN: return "ARMISD::FMIN";
819 case ARMISD::BFI: return "ARMISD::BFI";
823 /// getRegClassFor - Return the register class that should be used for the
824 /// specified value type.
825 TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const {
826 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
827 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
828 // load / store 4 to 8 consecutive D registers.
829 if (Subtarget->hasNEON()) {
830 if (VT == MVT::v4i64)
831 return ARM::QQPRRegisterClass;
832 else if (VT == MVT::v8i64)
833 return ARM::QQQQPRRegisterClass;
835 return TargetLowering::getRegClassFor(VT);
838 // Create a fast isel object.
840 ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
841 return ARM::createFastISel(funcInfo);
844 /// getFunctionAlignment - Return the Log2 alignment of this function.
845 unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
846 return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 1 : 2;
849 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
850 /// be used for loads / stores from the global.
851 unsigned ARMTargetLowering::getMaximalGlobalOffset() const {
852 return (Subtarget->isThumb1Only() ? 127 : 4095);
855 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
856 unsigned NumVals = N->getNumValues();
858 return Sched::RegPressure;
860 for (unsigned i = 0; i != NumVals; ++i) {
861 EVT VT = N->getValueType(i);
862 if (VT == MVT::Flag || VT == MVT::Other)
864 if (VT.isFloatingPoint() || VT.isVector())
865 return Sched::Latency;
868 if (!N->isMachineOpcode())
869 return Sched::RegPressure;
871 // Load are scheduled for latency even if there instruction itinerary
873 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
874 const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
876 if (TID.getNumDefs() == 0)
877 return Sched::RegPressure;
878 if (!Itins->isEmpty() &&
879 Itins->getOperandCycle(TID.getSchedClass(), 0) > 2)
880 return Sched::Latency;
882 return Sched::RegPressure;
886 ARMTargetLowering::getRegPressureLimit(const TargetRegisterClass *RC,
887 MachineFunction &MF) const {
888 switch (RC->getID()) {
891 case ARM::tGPRRegClassID:
892 return RegInfo->hasFP(MF) ? 4 : 5;
893 case ARM::GPRRegClassID: {
894 unsigned FP = RegInfo->hasFP(MF) ? 1 : 0;
895 return 10 - FP - (Subtarget->isR9Reserved() ? 1 : 0);
897 case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
898 case ARM::DPRRegClassID:
903 //===----------------------------------------------------------------------===//
905 //===----------------------------------------------------------------------===//
907 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
908 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
910 default: llvm_unreachable("Unknown condition code!");
911 case ISD::SETNE: return ARMCC::NE;
912 case ISD::SETEQ: return ARMCC::EQ;
913 case ISD::SETGT: return ARMCC::GT;
914 case ISD::SETGE: return ARMCC::GE;
915 case ISD::SETLT: return ARMCC::LT;
916 case ISD::SETLE: return ARMCC::LE;
917 case ISD::SETUGT: return ARMCC::HI;
918 case ISD::SETUGE: return ARMCC::HS;
919 case ISD::SETULT: return ARMCC::LO;
920 case ISD::SETULE: return ARMCC::LS;
924 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
925 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
926 ARMCC::CondCodes &CondCode2) {
927 CondCode2 = ARMCC::AL;
929 default: llvm_unreachable("Unknown FP condition!");
931 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
933 case ISD::SETOGT: CondCode = ARMCC::GT; break;
935 case ISD::SETOGE: CondCode = ARMCC::GE; break;
936 case ISD::SETOLT: CondCode = ARMCC::MI; break;
937 case ISD::SETOLE: CondCode = ARMCC::LS; break;
938 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
939 case ISD::SETO: CondCode = ARMCC::VC; break;
940 case ISD::SETUO: CondCode = ARMCC::VS; break;
941 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
942 case ISD::SETUGT: CondCode = ARMCC::HI; break;
943 case ISD::SETUGE: CondCode = ARMCC::PL; break;
945 case ISD::SETULT: CondCode = ARMCC::LT; break;
947 case ISD::SETULE: CondCode = ARMCC::LE; break;
949 case ISD::SETUNE: CondCode = ARMCC::NE; break;
953 //===----------------------------------------------------------------------===//
954 // Calling Convention Implementation
955 //===----------------------------------------------------------------------===//
957 #include "ARMGenCallingConv.inc"
959 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
960 /// given CallingConvention value.
961 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
963 bool isVarArg) const {
966 llvm_unreachable("Unsupported calling convention");
967 case CallingConv::Fast:
968 if (Subtarget->hasVFP2() && !isVarArg) {
969 if (!Subtarget->isAAPCS_ABI())
970 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
971 // For AAPCS ABI targets, just use VFP variant of the calling convention.
972 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
975 case CallingConv::C: {
976 // Use target triple & subtarget features to do actual dispatch.
977 if (!Subtarget->isAAPCS_ABI())
978 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
979 else if (Subtarget->hasVFP2() &&
980 FloatABIType == FloatABI::Hard && !isVarArg)
981 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
982 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
984 case CallingConv::ARM_AAPCS_VFP:
985 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
986 case CallingConv::ARM_AAPCS:
987 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
988 case CallingConv::ARM_APCS:
989 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
993 /// LowerCallResult - Lower the result values of a call into the
994 /// appropriate copies out of appropriate physical registers.
996 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
997 CallingConv::ID CallConv, bool isVarArg,
998 const SmallVectorImpl<ISD::InputArg> &Ins,
999 DebugLoc dl, SelectionDAG &DAG,
1000 SmallVectorImpl<SDValue> &InVals) const {
1002 // Assign locations to each value returned by this call.
1003 SmallVector<CCValAssign, 16> RVLocs;
1004 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1005 RVLocs, *DAG.getContext());
1006 CCInfo.AnalyzeCallResult(Ins,
1007 CCAssignFnForNode(CallConv, /* Return*/ true,
1010 // Copy all of the result registers out of their specified physreg.
1011 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1012 CCValAssign VA = RVLocs[i];
1015 if (VA.needsCustom()) {
1016 // Handle f64 or half of a v2f64.
1017 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1019 Chain = Lo.getValue(1);
1020 InFlag = Lo.getValue(2);
1021 VA = RVLocs[++i]; // skip ahead to next loc
1022 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1024 Chain = Hi.getValue(1);
1025 InFlag = Hi.getValue(2);
1026 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1028 if (VA.getLocVT() == MVT::v2f64) {
1029 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1030 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1031 DAG.getConstant(0, MVT::i32));
1033 VA = RVLocs[++i]; // skip ahead to next loc
1034 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1035 Chain = Lo.getValue(1);
1036 InFlag = Lo.getValue(2);
1037 VA = RVLocs[++i]; // skip ahead to next loc
1038 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1039 Chain = Hi.getValue(1);
1040 InFlag = Hi.getValue(2);
1041 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1042 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1043 DAG.getConstant(1, MVT::i32));
1046 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1048 Chain = Val.getValue(1);
1049 InFlag = Val.getValue(2);
1052 switch (VA.getLocInfo()) {
1053 default: llvm_unreachable("Unknown loc info!");
1054 case CCValAssign::Full: break;
1055 case CCValAssign::BCvt:
1056 Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val);
1060 InVals.push_back(Val);
1066 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1067 /// by "Src" to address "Dst" of size "Size". Alignment information is
1068 /// specified by the specific parameter attribute. The copy will be passed as
1069 /// a byval function parameter.
1070 /// Sometimes what we are copying is the end of a larger object, the part that
1071 /// does not fit in registers.
1073 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1074 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1076 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1077 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1078 /*isVolatile=*/false, /*AlwaysInline=*/false,
1079 MachinePointerInfo(0), MachinePointerInfo(0));
1082 /// LowerMemOpCallTo - Store the argument to the stack.
1084 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
1085 SDValue StackPtr, SDValue Arg,
1086 DebugLoc dl, SelectionDAG &DAG,
1087 const CCValAssign &VA,
1088 ISD::ArgFlagsTy Flags) const {
1089 unsigned LocMemOffset = VA.getLocMemOffset();
1090 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1091 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1092 if (Flags.isByVal())
1093 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1095 return DAG.getStore(Chain, dl, Arg, PtrOff,
1096 MachinePointerInfo::getStack(LocMemOffset),
1100 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
1101 SDValue Chain, SDValue &Arg,
1102 RegsToPassVector &RegsToPass,
1103 CCValAssign &VA, CCValAssign &NextVA,
1105 SmallVector<SDValue, 8> &MemOpChains,
1106 ISD::ArgFlagsTy Flags) const {
1108 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1109 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1110 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
1112 if (NextVA.isRegLoc())
1113 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
1115 assert(NextVA.isMemLoc());
1116 if (StackPtr.getNode() == 0)
1117 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1119 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
1125 /// LowerCall - Lowering a call into a callseq_start <-
1126 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1129 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1130 CallingConv::ID CallConv, bool isVarArg,
1132 const SmallVectorImpl<ISD::OutputArg> &Outs,
1133 const SmallVectorImpl<SDValue> &OutVals,
1134 const SmallVectorImpl<ISD::InputArg> &Ins,
1135 DebugLoc dl, SelectionDAG &DAG,
1136 SmallVectorImpl<SDValue> &InVals) const {
1137 MachineFunction &MF = DAG.getMachineFunction();
1138 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1139 bool IsSibCall = false;
1140 // Temporarily disable tail calls so things don't break.
1141 if (!EnableARMTailCalls)
1144 // Check if it's really possible to do a tail call.
1145 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1146 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1147 Outs, OutVals, Ins, DAG);
1148 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1149 // detected sibcalls.
1156 // Analyze operands of the call, assigning locations to each operand.
1157 SmallVector<CCValAssign, 16> ArgLocs;
1158 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1160 CCInfo.AnalyzeCallOperands(Outs,
1161 CCAssignFnForNode(CallConv, /* Return*/ false,
1164 // Get a count of how many bytes are to be pushed on the stack.
1165 unsigned NumBytes = CCInfo.getNextStackOffset();
1167 // For tail calls, memory operands are available in our caller's stack.
1171 // Adjust the stack pointer for the new arguments...
1172 // These operations are automatically eliminated by the prolog/epilog pass
1174 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1176 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1178 RegsToPassVector RegsToPass;
1179 SmallVector<SDValue, 8> MemOpChains;
1181 // Walk the register/memloc assignments, inserting copies/loads. In the case
1182 // of tail call optimization, arguments are handled later.
1183 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1185 ++i, ++realArgIdx) {
1186 CCValAssign &VA = ArgLocs[i];
1187 SDValue Arg = OutVals[realArgIdx];
1188 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1190 // Promote the value if needed.
1191 switch (VA.getLocInfo()) {
1192 default: llvm_unreachable("Unknown loc info!");
1193 case CCValAssign::Full: break;
1194 case CCValAssign::SExt:
1195 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1197 case CCValAssign::ZExt:
1198 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1200 case CCValAssign::AExt:
1201 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1203 case CCValAssign::BCvt:
1204 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1208 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1209 if (VA.needsCustom()) {
1210 if (VA.getLocVT() == MVT::v2f64) {
1211 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1212 DAG.getConstant(0, MVT::i32));
1213 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1214 DAG.getConstant(1, MVT::i32));
1216 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1217 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1219 VA = ArgLocs[++i]; // skip ahead to next loc
1220 if (VA.isRegLoc()) {
1221 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1222 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1224 assert(VA.isMemLoc());
1226 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1227 dl, DAG, VA, Flags));
1230 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1231 StackPtr, MemOpChains, Flags);
1233 } else if (VA.isRegLoc()) {
1234 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1235 } else if (!IsSibCall) {
1236 assert(VA.isMemLoc());
1238 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1239 dl, DAG, VA, Flags));
1243 if (!MemOpChains.empty())
1244 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1245 &MemOpChains[0], MemOpChains.size());
1247 // Build a sequence of copy-to-reg nodes chained together with token chain
1248 // and flag operands which copy the outgoing args into the appropriate regs.
1250 // Tail call byval lowering might overwrite argument registers so in case of
1251 // tail call optimization the copies to registers are lowered later.
1253 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1254 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1255 RegsToPass[i].second, InFlag);
1256 InFlag = Chain.getValue(1);
1259 // For tail calls lower the arguments to the 'real' stack slot.
1261 // Force all the incoming stack arguments to be loaded from the stack
1262 // before any new outgoing arguments are stored to the stack, because the
1263 // outgoing stack slots may alias the incoming argument stack slots, and
1264 // the alias isn't otherwise explicit. This is slightly more conservative
1265 // than necessary, because it means that each store effectively depends
1266 // on every argument instead of just those arguments it would clobber.
1268 // Do not flag preceeding copytoreg stuff together with the following stuff.
1270 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1271 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1272 RegsToPass[i].second, InFlag);
1273 InFlag = Chain.getValue(1);
1278 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1279 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1280 // node so that legalize doesn't hack it.
1281 bool isDirect = false;
1282 bool isARMFunc = false;
1283 bool isLocalARMFunc = false;
1284 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1286 if (EnableARMLongCalls) {
1287 assert (getTargetMachine().getRelocationModel() == Reloc::Static
1288 && "long-calls with non-static relocation model!");
1289 // Handle a global address or an external symbol. If it's not one of
1290 // those, the target's already in a register, so we don't need to do
1292 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1293 const GlobalValue *GV = G->getGlobal();
1294 // Create a constant pool entry for the callee address
1295 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1296 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1299 // Get the address of the callee into a register
1300 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1301 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1302 Callee = DAG.getLoad(getPointerTy(), dl,
1303 DAG.getEntryNode(), CPAddr,
1304 MachinePointerInfo::getConstantPool(),
1306 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1307 const char *Sym = S->getSymbol();
1309 // Create a constant pool entry for the callee address
1310 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1311 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1312 Sym, ARMPCLabelIndex, 0);
1313 // Get the address of the callee into a register
1314 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1315 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1316 Callee = DAG.getLoad(getPointerTy(), dl,
1317 DAG.getEntryNode(), CPAddr,
1318 MachinePointerInfo::getConstantPool(),
1321 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1322 const GlobalValue *GV = G->getGlobal();
1324 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1325 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
1326 getTargetMachine().getRelocationModel() != Reloc::Static;
1327 isARMFunc = !Subtarget->isThumb() || isStub;
1328 // ARM call to a local ARM function is predicable.
1329 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
1330 // tBX takes a register source operand.
1331 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1332 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1333 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1336 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1337 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1338 Callee = DAG.getLoad(getPointerTy(), dl,
1339 DAG.getEntryNode(), CPAddr,
1340 MachinePointerInfo::getConstantPool(),
1342 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1343 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1344 getPointerTy(), Callee, PICLabel);
1346 // On ELF targets for PIC code, direct calls should go through the PLT
1347 unsigned OpFlags = 0;
1348 if (Subtarget->isTargetELF() &&
1349 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1350 OpFlags = ARMII::MO_PLT;
1351 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
1353 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1355 bool isStub = Subtarget->isTargetDarwin() &&
1356 getTargetMachine().getRelocationModel() != Reloc::Static;
1357 isARMFunc = !Subtarget->isThumb() || isStub;
1358 // tBX takes a register source operand.
1359 const char *Sym = S->getSymbol();
1360 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1361 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1362 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1363 Sym, ARMPCLabelIndex, 4);
1364 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1365 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1366 Callee = DAG.getLoad(getPointerTy(), dl,
1367 DAG.getEntryNode(), CPAddr,
1368 MachinePointerInfo::getConstantPool(),
1370 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1371 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1372 getPointerTy(), Callee, PICLabel);
1374 unsigned OpFlags = 0;
1375 // On ELF targets for PIC code, direct calls should go through the PLT
1376 if (Subtarget->isTargetELF() &&
1377 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1378 OpFlags = ARMII::MO_PLT;
1379 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags);
1383 // FIXME: handle tail calls differently.
1385 if (Subtarget->isThumb()) {
1386 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1387 CallOpc = ARMISD::CALL_NOLINK;
1389 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1391 CallOpc = (isDirect || Subtarget->hasV5TOps())
1392 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
1393 : ARMISD::CALL_NOLINK;
1396 std::vector<SDValue> Ops;
1397 Ops.push_back(Chain);
1398 Ops.push_back(Callee);
1400 // Add argument registers to the end of the list so that they are known live
1402 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1403 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1404 RegsToPass[i].second.getValueType()));
1406 if (InFlag.getNode())
1407 Ops.push_back(InFlag);
1409 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1411 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
1413 // Returns a chain and a flag for retval copy to use.
1414 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
1415 InFlag = Chain.getValue(1);
1417 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1418 DAG.getIntPtrConstant(0, true), InFlag);
1420 InFlag = Chain.getValue(1);
1422 // Handle result values, copying them out of physregs into vregs that we
1424 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1428 /// MatchingStackOffset - Return true if the given stack call argument is
1429 /// already available in the same position (relatively) of the caller's
1430 /// incoming argument stack.
1432 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1433 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1434 const ARMInstrInfo *TII) {
1435 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
1437 if (Arg.getOpcode() == ISD::CopyFromReg) {
1438 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
1439 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR))
1441 MachineInstr *Def = MRI->getVRegDef(VR);
1444 if (!Flags.isByVal()) {
1445 if (!TII->isLoadFromStackSlot(Def, FI))
1450 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
1451 if (Flags.isByVal())
1452 // ByVal argument is passed in as a pointer but it's now being
1453 // dereferenced. e.g.
1454 // define @foo(%struct.X* %A) {
1455 // tail call @bar(%struct.X* byval %A)
1458 SDValue Ptr = Ld->getBasePtr();
1459 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
1462 FI = FINode->getIndex();
1466 assert(FI != INT_MAX);
1467 if (!MFI->isFixedObjectIndex(FI))
1469 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
1472 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1473 /// for tail call optimization. Targets which want to do tail call
1474 /// optimization should implement this function.
1476 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1477 CallingConv::ID CalleeCC,
1479 bool isCalleeStructRet,
1480 bool isCallerStructRet,
1481 const SmallVectorImpl<ISD::OutputArg> &Outs,
1482 const SmallVectorImpl<SDValue> &OutVals,
1483 const SmallVectorImpl<ISD::InputArg> &Ins,
1484 SelectionDAG& DAG) const {
1485 const Function *CallerF = DAG.getMachineFunction().getFunction();
1486 CallingConv::ID CallerCC = CallerF->getCallingConv();
1487 bool CCMatch = CallerCC == CalleeCC;
1489 // Look for obvious safe cases to perform tail call optimization that do not
1490 // require ABI changes. This is what gcc calls sibcall.
1492 // Do not sibcall optimize vararg calls unless the call site is not passing
1494 if (isVarArg && !Outs.empty())
1497 // Also avoid sibcall optimization if either caller or callee uses struct
1498 // return semantics.
1499 if (isCalleeStructRet || isCallerStructRet)
1502 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
1503 // emitEpilogue is not ready for them.
1504 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
1505 // LR. This means if we need to reload LR, it takes an extra instructions,
1506 // which outweighs the value of the tail call; but here we don't know yet
1507 // whether LR is going to be used. Probably the right approach is to
1508 // generate the tail call here and turn it back into CALL/RET in
1509 // emitEpilogue if LR is used.
1510 if (Subtarget->isThumb1Only())
1513 // For the moment, we can only do this to functions defined in this
1514 // compilation, or to indirect calls. A Thumb B to an ARM function,
1515 // or vice versa, is not easily fixed up in the linker unlike BL.
1516 // (We could do this by loading the address of the callee into a register;
1517 // that is an extra instruction over the direct call and burns a register
1518 // as well, so is not likely to be a win.)
1520 // It might be safe to remove this restriction on non-Darwin.
1522 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
1523 // but we need to make sure there are enough registers; the only valid
1524 // registers are the 4 used for parameters. We don't currently do this
1526 if (isa<ExternalSymbolSDNode>(Callee))
1529 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1530 const GlobalValue *GV = G->getGlobal();
1531 if (GV->isDeclaration() || GV->isWeakForLinker())
1535 // If the calling conventions do not match, then we'd better make sure the
1536 // results are returned in the same way as what the caller expects.
1538 SmallVector<CCValAssign, 16> RVLocs1;
1539 CCState CCInfo1(CalleeCC, false, getTargetMachine(),
1540 RVLocs1, *DAG.getContext());
1541 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
1543 SmallVector<CCValAssign, 16> RVLocs2;
1544 CCState CCInfo2(CallerCC, false, getTargetMachine(),
1545 RVLocs2, *DAG.getContext());
1546 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
1548 if (RVLocs1.size() != RVLocs2.size())
1550 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
1551 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
1553 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
1555 if (RVLocs1[i].isRegLoc()) {
1556 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
1559 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
1565 // If the callee takes no arguments then go on to check the results of the
1567 if (!Outs.empty()) {
1568 // Check if stack adjustment is needed. For now, do not do this if any
1569 // argument is passed on the stack.
1570 SmallVector<CCValAssign, 16> ArgLocs;
1571 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
1572 ArgLocs, *DAG.getContext());
1573 CCInfo.AnalyzeCallOperands(Outs,
1574 CCAssignFnForNode(CalleeCC, false, isVarArg));
1575 if (CCInfo.getNextStackOffset()) {
1576 MachineFunction &MF = DAG.getMachineFunction();
1578 // Check if the arguments are already laid out in the right way as
1579 // the caller's fixed stack objects.
1580 MachineFrameInfo *MFI = MF.getFrameInfo();
1581 const MachineRegisterInfo *MRI = &MF.getRegInfo();
1582 const ARMInstrInfo *TII =
1583 ((ARMTargetMachine&)getTargetMachine()).getInstrInfo();
1584 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1586 ++i, ++realArgIdx) {
1587 CCValAssign &VA = ArgLocs[i];
1588 EVT RegVT = VA.getLocVT();
1589 SDValue Arg = OutVals[realArgIdx];
1590 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1591 if (VA.getLocInfo() == CCValAssign::Indirect)
1593 if (VA.needsCustom()) {
1594 // f64 and vector types are split into multiple registers or
1595 // register/stack-slot combinations. The types will not match
1596 // the registers; give up on memory f64 refs until we figure
1597 // out what to do about this.
1600 if (!ArgLocs[++i].isRegLoc())
1602 if (RegVT == MVT::v2f64) {
1603 if (!ArgLocs[++i].isRegLoc())
1605 if (!ArgLocs[++i].isRegLoc())
1608 } else if (!VA.isRegLoc()) {
1609 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
1621 ARMTargetLowering::LowerReturn(SDValue Chain,
1622 CallingConv::ID CallConv, bool isVarArg,
1623 const SmallVectorImpl<ISD::OutputArg> &Outs,
1624 const SmallVectorImpl<SDValue> &OutVals,
1625 DebugLoc dl, SelectionDAG &DAG) const {
1627 // CCValAssign - represent the assignment of the return value to a location.
1628 SmallVector<CCValAssign, 16> RVLocs;
1630 // CCState - Info about the registers and stack slots.
1631 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
1634 // Analyze outgoing return values.
1635 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1638 // If this is the first return lowered for this function, add
1639 // the regs to the liveout set for the function.
1640 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1641 for (unsigned i = 0; i != RVLocs.size(); ++i)
1642 if (RVLocs[i].isRegLoc())
1643 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1648 // Copy the result values into the output registers.
1649 for (unsigned i = 0, realRVLocIdx = 0;
1651 ++i, ++realRVLocIdx) {
1652 CCValAssign &VA = RVLocs[i];
1653 assert(VA.isRegLoc() && "Can only return in registers!");
1655 SDValue Arg = OutVals[realRVLocIdx];
1657 switch (VA.getLocInfo()) {
1658 default: llvm_unreachable("Unknown loc info!");
1659 case CCValAssign::Full: break;
1660 case CCValAssign::BCvt:
1661 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1665 if (VA.needsCustom()) {
1666 if (VA.getLocVT() == MVT::v2f64) {
1667 // Extract the first half and return it in two registers.
1668 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1669 DAG.getConstant(0, MVT::i32));
1670 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
1671 DAG.getVTList(MVT::i32, MVT::i32), Half);
1673 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1674 Flag = Chain.getValue(1);
1675 VA = RVLocs[++i]; // skip ahead to next loc
1676 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1677 HalfGPRs.getValue(1), Flag);
1678 Flag = Chain.getValue(1);
1679 VA = RVLocs[++i]; // skip ahead to next loc
1681 // Extract the 2nd half and fall through to handle it as an f64 value.
1682 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1683 DAG.getConstant(1, MVT::i32));
1685 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1687 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1688 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1689 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1690 Flag = Chain.getValue(1);
1691 VA = RVLocs[++i]; // skip ahead to next loc
1692 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1695 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1697 // Guarantee that all emitted copies are
1698 // stuck together, avoiding something bad.
1699 Flag = Chain.getValue(1);
1704 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1706 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1711 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1712 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1713 // one of the above mentioned nodes. It has to be wrapped because otherwise
1714 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1715 // be used to form addressing mode. These wrapped nodes will be selected
1717 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1718 EVT PtrVT = Op.getValueType();
1719 // FIXME there is no actual debug info here
1720 DebugLoc dl = Op.getDebugLoc();
1721 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1723 if (CP->isMachineConstantPoolEntry())
1724 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1725 CP->getAlignment());
1727 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1728 CP->getAlignment());
1729 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1732 unsigned ARMTargetLowering::getJumpTableEncoding() const {
1733 return MachineJumpTableInfo::EK_Inline;
1736 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
1737 SelectionDAG &DAG) const {
1738 MachineFunction &MF = DAG.getMachineFunction();
1739 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1740 unsigned ARMPCLabelIndex = 0;
1741 DebugLoc DL = Op.getDebugLoc();
1742 EVT PtrVT = getPointerTy();
1743 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1744 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1746 if (RelocM == Reloc::Static) {
1747 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
1749 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1750 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1751 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(BA, ARMPCLabelIndex,
1752 ARMCP::CPBlockAddress,
1754 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1756 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
1757 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
1758 MachinePointerInfo::getConstantPool(),
1760 if (RelocM == Reloc::Static)
1762 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1763 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
1766 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
1768 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1769 SelectionDAG &DAG) const {
1770 DebugLoc dl = GA->getDebugLoc();
1771 EVT PtrVT = getPointerTy();
1772 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1773 MachineFunction &MF = DAG.getMachineFunction();
1774 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1775 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1776 ARMConstantPoolValue *CPV =
1777 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1778 ARMCP::CPValue, PCAdj, "tlsgd", true);
1779 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1780 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
1781 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
1782 MachinePointerInfo::getConstantPool(),
1784 SDValue Chain = Argument.getValue(1);
1786 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1787 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
1789 // call __tls_get_addr.
1792 Entry.Node = Argument;
1793 Entry.Ty = (const Type *) Type::getInt32Ty(*DAG.getContext());
1794 Args.push_back(Entry);
1795 // FIXME: is there useful debug info available here?
1796 std::pair<SDValue, SDValue> CallResult =
1797 LowerCallTo(Chain, (const Type *) Type::getInt32Ty(*DAG.getContext()),
1798 false, false, false, false,
1799 0, CallingConv::C, false, /*isReturnValueUsed=*/true,
1800 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
1801 return CallResult.first;
1804 // Lower ISD::GlobalTLSAddress using the "initial exec" or
1805 // "local exec" model.
1807 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
1808 SelectionDAG &DAG) const {
1809 const GlobalValue *GV = GA->getGlobal();
1810 DebugLoc dl = GA->getDebugLoc();
1812 SDValue Chain = DAG.getEntryNode();
1813 EVT PtrVT = getPointerTy();
1814 // Get the Thread Pointer
1815 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1817 if (GV->isDeclaration()) {
1818 MachineFunction &MF = DAG.getMachineFunction();
1819 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1820 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1821 // Initial exec model.
1822 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1823 ARMConstantPoolValue *CPV =
1824 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1825 ARMCP::CPValue, PCAdj, "gottpoff", true);
1826 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1827 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1828 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1829 MachinePointerInfo::getConstantPool(),
1831 Chain = Offset.getValue(1);
1833 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1834 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
1836 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1837 MachinePointerInfo::getConstantPool(),
1841 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, "tpoff");
1842 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1843 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1844 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1845 MachinePointerInfo::getConstantPool(),
1849 // The address of the thread local variable is the add of the thread
1850 // pointer with the offset of the variable.
1851 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
1855 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
1856 // TODO: implement the "local dynamic" model
1857 assert(Subtarget->isTargetELF() &&
1858 "TLS not implemented for non-ELF targets");
1859 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1860 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
1861 // otherwise use the "Local Exec" TLS Model
1862 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
1863 return LowerToTLSGeneralDynamicModel(GA, DAG);
1865 return LowerToTLSExecModels(GA, DAG);
1868 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
1869 SelectionDAG &DAG) const {
1870 EVT PtrVT = getPointerTy();
1871 DebugLoc dl = Op.getDebugLoc();
1872 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1873 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1874 if (RelocM == Reloc::PIC_) {
1875 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
1876 ARMConstantPoolValue *CPV =
1877 new ARMConstantPoolValue(GV, UseGOTOFF ? "GOTOFF" : "GOT");
1878 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1879 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1880 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1882 MachinePointerInfo::getConstantPool(),
1884 SDValue Chain = Result.getValue(1);
1885 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1886 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
1888 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
1889 MachinePointerInfo::getGOT(), false, false, 0);
1892 // If we have T2 ops, we can materialize the address directly via movt/movw
1893 // pair. This is always cheaper.
1894 if (Subtarget->useMovt()) {
1895 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
1896 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
1898 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1899 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1900 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1901 MachinePointerInfo::getConstantPool(),
1907 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
1908 SelectionDAG &DAG) const {
1909 MachineFunction &MF = DAG.getMachineFunction();
1910 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1911 unsigned ARMPCLabelIndex = 0;
1912 EVT PtrVT = getPointerTy();
1913 DebugLoc dl = Op.getDebugLoc();
1914 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1915 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1917 if (RelocM == Reloc::Static)
1918 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1920 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1921 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8);
1922 ARMConstantPoolValue *CPV =
1923 new ARMConstantPoolValue(GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj);
1924 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1926 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1928 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1929 MachinePointerInfo::getConstantPool(),
1931 SDValue Chain = Result.getValue(1);
1933 if (RelocM == Reloc::PIC_) {
1934 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1935 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1938 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
1939 Result = DAG.getLoad(PtrVT, dl, Chain, Result, MachinePointerInfo::getGOT(),
1945 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
1946 SelectionDAG &DAG) const {
1947 assert(Subtarget->isTargetELF() &&
1948 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
1949 MachineFunction &MF = DAG.getMachineFunction();
1950 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1951 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1952 EVT PtrVT = getPointerTy();
1953 DebugLoc dl = Op.getDebugLoc();
1954 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1955 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1956 "_GLOBAL_OFFSET_TABLE_",
1957 ARMPCLabelIndex, PCAdj);
1958 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1959 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1960 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1961 MachinePointerInfo::getConstantPool(),
1963 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1964 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1968 ARMTargetLowering::LowerEH_SJLJ_DISPATCHSETUP(SDValue Op, SelectionDAG &DAG)
1970 DebugLoc dl = Op.getDebugLoc();
1971 return DAG.getNode(ARMISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other,
1972 Op.getOperand(0), Op.getOperand(1));
1976 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
1977 DebugLoc dl = Op.getDebugLoc();
1978 SDValue Val = DAG.getConstant(0, MVT::i32);
1979 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(0),
1980 Op.getOperand(1), Val);
1984 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
1985 DebugLoc dl = Op.getDebugLoc();
1986 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
1987 Op.getOperand(1), DAG.getConstant(0, MVT::i32));
1991 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
1992 const ARMSubtarget *Subtarget) const {
1993 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1994 DebugLoc dl = Op.getDebugLoc();
1996 default: return SDValue(); // Don't custom lower most intrinsics.
1997 case Intrinsic::arm_thread_pointer: {
1998 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1999 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2001 case Intrinsic::eh_sjlj_lsda: {
2002 MachineFunction &MF = DAG.getMachineFunction();
2003 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2004 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
2005 EVT PtrVT = getPointerTy();
2006 DebugLoc dl = Op.getDebugLoc();
2007 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2009 unsigned PCAdj = (RelocM != Reloc::PIC_)
2010 ? 0 : (Subtarget->isThumb() ? 4 : 8);
2011 ARMConstantPoolValue *CPV =
2012 new ARMConstantPoolValue(MF.getFunction(), ARMPCLabelIndex,
2013 ARMCP::CPLSDA, PCAdj);
2014 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2015 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2017 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2018 MachinePointerInfo::getConstantPool(),
2021 if (RelocM == Reloc::PIC_) {
2022 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2023 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2030 static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG,
2031 const ARMSubtarget *Subtarget) {
2032 DebugLoc dl = Op.getDebugLoc();
2033 if (!Subtarget->hasDataBarrier()) {
2034 // Some ARMv6 cpus can support data barriers with an mcr instruction.
2035 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
2037 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb1Only() &&
2038 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!");
2039 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2040 DAG.getConstant(0, MVT::i32));
2043 SDValue Op5 = Op.getOperand(5);
2044 bool isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue() != 0;
2045 unsigned isLL = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
2046 unsigned isLS = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
2047 bool isOnlyStoreBarrier = (isLL == 0 && isLS == 0);
2049 ARM_MB::MemBOpt DMBOpt;
2050 if (isDeviceBarrier)
2051 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ST : ARM_MB::SY;
2053 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ISHST : ARM_MB::ISH;
2054 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
2055 DAG.getConstant(DMBOpt, MVT::i32));
2058 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
2059 MachineFunction &MF = DAG.getMachineFunction();
2060 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
2062 // vastart just stores the address of the VarArgsFrameIndex slot into the
2063 // memory location argument.
2064 DebugLoc dl = Op.getDebugLoc();
2065 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2066 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2067 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2068 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2069 MachinePointerInfo(SV), false, false, 0);
2073 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
2074 SDValue &Root, SelectionDAG &DAG,
2075 DebugLoc dl) const {
2076 MachineFunction &MF = DAG.getMachineFunction();
2077 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2079 TargetRegisterClass *RC;
2080 if (AFI->isThumb1OnlyFunction())
2081 RC = ARM::tGPRRegisterClass;
2083 RC = ARM::GPRRegisterClass;
2085 // Transform the arguments stored in physical registers into virtual ones.
2086 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2087 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2090 if (NextVA.isMemLoc()) {
2091 MachineFrameInfo *MFI = MF.getFrameInfo();
2092 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
2094 // Create load node to retrieve arguments from the stack.
2095 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2096 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
2097 MachinePointerInfo::getFixedStack(FI),
2100 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2101 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2104 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
2108 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
2109 CallingConv::ID CallConv, bool isVarArg,
2110 const SmallVectorImpl<ISD::InputArg>
2112 DebugLoc dl, SelectionDAG &DAG,
2113 SmallVectorImpl<SDValue> &InVals)
2116 MachineFunction &MF = DAG.getMachineFunction();
2117 MachineFrameInfo *MFI = MF.getFrameInfo();
2119 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2121 // Assign locations to all of the incoming arguments.
2122 SmallVector<CCValAssign, 16> ArgLocs;
2123 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
2125 CCInfo.AnalyzeFormalArguments(Ins,
2126 CCAssignFnForNode(CallConv, /* Return*/ false,
2129 SmallVector<SDValue, 16> ArgValues;
2131 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2132 CCValAssign &VA = ArgLocs[i];
2134 // Arguments stored in registers.
2135 if (VA.isRegLoc()) {
2136 EVT RegVT = VA.getLocVT();
2139 if (VA.needsCustom()) {
2140 // f64 and vector types are split up into multiple registers or
2141 // combinations of registers and stack slots.
2142 if (VA.getLocVT() == MVT::v2f64) {
2143 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
2145 VA = ArgLocs[++i]; // skip ahead to next loc
2147 if (VA.isMemLoc()) {
2148 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
2149 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2150 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
2151 MachinePointerInfo::getFixedStack(FI),
2154 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
2157 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2158 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2159 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
2160 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2161 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
2163 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
2166 TargetRegisterClass *RC;
2168 if (RegVT == MVT::f32)
2169 RC = ARM::SPRRegisterClass;
2170 else if (RegVT == MVT::f64)
2171 RC = ARM::DPRRegisterClass;
2172 else if (RegVT == MVT::v2f64)
2173 RC = ARM::QPRRegisterClass;
2174 else if (RegVT == MVT::i32)
2175 RC = (AFI->isThumb1OnlyFunction() ?
2176 ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
2178 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2180 // Transform the arguments in physical registers into virtual ones.
2181 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2182 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2185 // If this is an 8 or 16-bit value, it is really passed promoted
2186 // to 32 bits. Insert an assert[sz]ext to capture this, then
2187 // truncate to the right size.
2188 switch (VA.getLocInfo()) {
2189 default: llvm_unreachable("Unknown loc info!");
2190 case CCValAssign::Full: break;
2191 case CCValAssign::BCvt:
2192 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
2194 case CCValAssign::SExt:
2195 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2196 DAG.getValueType(VA.getValVT()));
2197 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2199 case CCValAssign::ZExt:
2200 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2201 DAG.getValueType(VA.getValVT()));
2202 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2206 InVals.push_back(ArgValue);
2208 } else { // VA.isRegLoc()
2211 assert(VA.isMemLoc());
2212 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
2214 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
2215 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(), true);
2217 // Create load nodes to retrieve arguments from the stack.
2218 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2219 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2220 MachinePointerInfo::getFixedStack(FI),
2227 static const unsigned GPRArgRegs[] = {
2228 ARM::R0, ARM::R1, ARM::R2, ARM::R3
2231 unsigned NumGPRs = CCInfo.getFirstUnallocated
2232 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
2234 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
2235 unsigned VARegSize = (4 - NumGPRs) * 4;
2236 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
2237 unsigned ArgOffset = CCInfo.getNextStackOffset();
2238 if (VARegSaveSize) {
2239 // If this function is vararg, store any remaining integer argument regs
2240 // to their spots on the stack so that they may be loaded by deferencing
2241 // the result of va_next.
2242 AFI->setVarArgsRegSaveSize(VARegSaveSize);
2243 AFI->setVarArgsFrameIndex(
2244 MFI->CreateFixedObject(VARegSaveSize,
2245 ArgOffset + VARegSaveSize - VARegSize,
2247 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(),
2250 SmallVector<SDValue, 4> MemOps;
2251 for (; NumGPRs < 4; ++NumGPRs) {
2252 TargetRegisterClass *RC;
2253 if (AFI->isThumb1OnlyFunction())
2254 RC = ARM::tGPRRegisterClass;
2256 RC = ARM::GPRRegisterClass;
2258 unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
2259 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2261 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2262 MachinePointerInfo::getFixedStack(AFI->getVarArgsFrameIndex()),
2264 MemOps.push_back(Store);
2265 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
2266 DAG.getConstant(4, getPointerTy()));
2268 if (!MemOps.empty())
2269 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2270 &MemOps[0], MemOps.size());
2272 // This will point to the next argument passed via stack.
2273 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset, true));
2279 /// isFloatingPointZero - Return true if this is +0.0.
2280 static bool isFloatingPointZero(SDValue Op) {
2281 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
2282 return CFP->getValueAPF().isPosZero();
2283 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
2284 // Maybe this has already been legalized into the constant pool?
2285 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
2286 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
2287 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
2288 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
2289 return CFP->getValueAPF().isPosZero();
2295 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
2296 /// the given operands.
2298 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2299 SDValue &ARMcc, SelectionDAG &DAG,
2300 DebugLoc dl) const {
2301 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
2302 unsigned C = RHSC->getZExtValue();
2303 if (!isLegalICmpImmediate(C)) {
2304 // Constant does not fit, try adjusting it by one?
2309 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
2310 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
2311 RHS = DAG.getConstant(C-1, MVT::i32);
2316 if (C != 0 && isLegalICmpImmediate(C-1)) {
2317 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
2318 RHS = DAG.getConstant(C-1, MVT::i32);
2323 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
2324 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
2325 RHS = DAG.getConstant(C+1, MVT::i32);
2330 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
2331 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2332 RHS = DAG.getConstant(C+1, MVT::i32);
2339 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2340 ARMISD::NodeType CompareType;
2343 CompareType = ARMISD::CMP;
2348 CompareType = ARMISD::CMPZ;
2351 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2352 return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS);
2355 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
2357 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
2358 DebugLoc dl) const {
2360 if (!isFloatingPointZero(RHS))
2361 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS);
2363 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS);
2364 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp);
2367 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2368 SDValue Cond = Op.getOperand(0);
2369 SDValue SelectTrue = Op.getOperand(1);
2370 SDValue SelectFalse = Op.getOperand(2);
2371 DebugLoc dl = Op.getDebugLoc();
2375 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
2376 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
2378 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
2379 const ConstantSDNode *CMOVTrue =
2380 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
2381 const ConstantSDNode *CMOVFalse =
2382 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
2384 if (CMOVTrue && CMOVFalse) {
2385 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
2386 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
2390 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
2392 False = SelectFalse;
2393 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
2398 if (True.getNode() && False.getNode()) {
2399 EVT VT = Cond.getValueType();
2400 SDValue ARMcc = Cond.getOperand(2);
2401 SDValue CCR = Cond.getOperand(3);
2402 SDValue Cmp = Cond.getOperand(4);
2403 return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp);
2408 return DAG.getSelectCC(dl, Cond,
2409 DAG.getConstant(0, Cond.getValueType()),
2410 SelectTrue, SelectFalse, ISD::SETNE);
2413 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
2414 EVT VT = Op.getValueType();
2415 SDValue LHS = Op.getOperand(0);
2416 SDValue RHS = Op.getOperand(1);
2417 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2418 SDValue TrueVal = Op.getOperand(2);
2419 SDValue FalseVal = Op.getOperand(3);
2420 DebugLoc dl = Op.getDebugLoc();
2422 if (LHS.getValueType() == MVT::i32) {
2424 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2425 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2426 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,Cmp);
2429 ARMCC::CondCodes CondCode, CondCode2;
2430 FPCCToARMCC(CC, CondCode, CondCode2);
2432 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2433 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2434 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2435 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
2437 if (CondCode2 != ARMCC::AL) {
2438 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32);
2439 // FIXME: Needs another CMP because flag can have but one use.
2440 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
2441 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
2442 Result, TrueVal, ARMcc2, CCR, Cmp2);
2447 /// canChangeToInt - Given the fp compare operand, return true if it is suitable
2448 /// to morph to an integer compare sequence.
2449 static bool canChangeToInt(SDValue Op, bool &SeenZero,
2450 const ARMSubtarget *Subtarget) {
2451 SDNode *N = Op.getNode();
2452 if (!N->hasOneUse())
2453 // Otherwise it requires moving the value from fp to integer registers.
2455 if (!N->getNumValues())
2457 EVT VT = Op.getValueType();
2458 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
2459 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
2460 // vmrs are very slow, e.g. cortex-a8.
2463 if (isFloatingPointZero(Op)) {
2467 return ISD::isNormalLoad(N);
2470 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
2471 if (isFloatingPointZero(Op))
2472 return DAG.getConstant(0, MVT::i32);
2474 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
2475 return DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2476 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(),
2477 Ld->isVolatile(), Ld->isNonTemporal(),
2478 Ld->getAlignment());
2480 llvm_unreachable("Unknown VFP cmp argument!");
2483 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
2484 SDValue &RetVal1, SDValue &RetVal2) {
2485 if (isFloatingPointZero(Op)) {
2486 RetVal1 = DAG.getConstant(0, MVT::i32);
2487 RetVal2 = DAG.getConstant(0, MVT::i32);
2491 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
2492 SDValue Ptr = Ld->getBasePtr();
2493 RetVal1 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2494 Ld->getChain(), Ptr,
2495 Ld->getPointerInfo(),
2496 Ld->isVolatile(), Ld->isNonTemporal(),
2497 Ld->getAlignment());
2499 EVT PtrType = Ptr.getValueType();
2500 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
2501 SDValue NewPtr = DAG.getNode(ISD::ADD, Op.getDebugLoc(),
2502 PtrType, Ptr, DAG.getConstant(4, PtrType));
2503 RetVal2 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2504 Ld->getChain(), NewPtr,
2505 Ld->getPointerInfo().getWithOffset(4),
2506 Ld->isVolatile(), Ld->isNonTemporal(),
2511 llvm_unreachable("Unknown VFP cmp argument!");
2514 /// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
2515 /// f32 and even f64 comparisons to integer ones.
2517 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
2518 SDValue Chain = Op.getOperand(0);
2519 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2520 SDValue LHS = Op.getOperand(2);
2521 SDValue RHS = Op.getOperand(3);
2522 SDValue Dest = Op.getOperand(4);
2523 DebugLoc dl = Op.getDebugLoc();
2525 bool SeenZero = false;
2526 if (canChangeToInt(LHS, SeenZero, Subtarget) &&
2527 canChangeToInt(RHS, SeenZero, Subtarget) &&
2528 // If one of the operand is zero, it's safe to ignore the NaN case since
2529 // we only care about equality comparisons.
2530 (SeenZero || (DAG.isKnownNeverNaN(LHS) && DAG.isKnownNeverNaN(RHS)))) {
2531 // If unsafe fp math optimization is enabled and there are no othter uses of
2532 // the CMP operands, and the condition code is EQ oe NE, we can optimize it
2533 // to an integer comparison.
2534 if (CC == ISD::SETOEQ)
2536 else if (CC == ISD::SETUNE)
2540 if (LHS.getValueType() == MVT::f32) {
2541 LHS = bitcastf32Toi32(LHS, DAG);
2542 RHS = bitcastf32Toi32(RHS, DAG);
2543 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2544 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2545 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2546 Chain, Dest, ARMcc, CCR, Cmp);
2551 expandf64Toi32(LHS, DAG, LHS1, LHS2);
2552 expandf64Toi32(RHS, DAG, RHS1, RHS2);
2553 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2554 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2555 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
2556 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
2557 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7);
2563 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2564 SDValue Chain = Op.getOperand(0);
2565 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2566 SDValue LHS = Op.getOperand(2);
2567 SDValue RHS = Op.getOperand(3);
2568 SDValue Dest = Op.getOperand(4);
2569 DebugLoc dl = Op.getDebugLoc();
2571 if (LHS.getValueType() == MVT::i32) {
2573 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2574 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2575 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2576 Chain, Dest, ARMcc, CCR, Cmp);
2579 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
2582 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
2583 CC == ISD::SETNE || CC == ISD::SETUNE)) {
2584 SDValue Result = OptimizeVFPBrcond(Op, DAG);
2585 if (Result.getNode())
2589 ARMCC::CondCodes CondCode, CondCode2;
2590 FPCCToARMCC(CC, CondCode, CondCode2);
2592 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2593 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2594 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2595 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
2596 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
2597 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2598 if (CondCode2 != ARMCC::AL) {
2599 ARMcc = DAG.getConstant(CondCode2, MVT::i32);
2600 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
2601 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2606 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
2607 SDValue Chain = Op.getOperand(0);
2608 SDValue Table = Op.getOperand(1);
2609 SDValue Index = Op.getOperand(2);
2610 DebugLoc dl = Op.getDebugLoc();
2612 EVT PTy = getPointerTy();
2613 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
2614 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
2615 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
2616 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
2617 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
2618 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
2619 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2620 if (Subtarget->isThumb2()) {
2621 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
2622 // which does another jump to the destination. This also makes it easier
2623 // to translate it to TBB / TBH later.
2624 // FIXME: This might not work if the function is extremely large.
2625 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
2626 Addr, Op.getOperand(2), JTI, UId);
2628 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2629 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
2630 MachinePointerInfo::getJumpTable(),
2632 Chain = Addr.getValue(1);
2633 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
2634 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2636 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
2637 MachinePointerInfo::getJumpTable(), false, false, 0);
2638 Chain = Addr.getValue(1);
2639 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2643 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
2644 DebugLoc dl = Op.getDebugLoc();
2647 switch (Op.getOpcode()) {
2649 assert(0 && "Invalid opcode!");
2650 case ISD::FP_TO_SINT:
2651 Opc = ARMISD::FTOSI;
2653 case ISD::FP_TO_UINT:
2654 Opc = ARMISD::FTOUI;
2657 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
2658 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
2661 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
2662 EVT VT = Op.getValueType();
2663 DebugLoc dl = Op.getDebugLoc();
2666 switch (Op.getOpcode()) {
2668 assert(0 && "Invalid opcode!");
2669 case ISD::SINT_TO_FP:
2670 Opc = ARMISD::SITOF;
2672 case ISD::UINT_TO_FP:
2673 Opc = ARMISD::UITOF;
2677 Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
2678 return DAG.getNode(Opc, dl, VT, Op);
2681 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
2682 // Implement fcopysign with a fabs and a conditional fneg.
2683 SDValue Tmp0 = Op.getOperand(0);
2684 SDValue Tmp1 = Op.getOperand(1);
2685 DebugLoc dl = Op.getDebugLoc();
2686 EVT VT = Op.getValueType();
2687 EVT SrcVT = Tmp1.getValueType();
2688 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
2689 SDValue ARMcc = DAG.getConstant(ARMCC::LT, MVT::i32);
2690 SDValue FP0 = DAG.getConstantFP(0.0, SrcVT);
2691 SDValue Cmp = getVFPCmp(Tmp1, FP0, DAG, dl);
2692 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2693 return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMcc, CCR, Cmp);
2696 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
2697 MachineFunction &MF = DAG.getMachineFunction();
2698 MachineFrameInfo *MFI = MF.getFrameInfo();
2699 MFI->setReturnAddressIsTaken(true);
2701 EVT VT = Op.getValueType();
2702 DebugLoc dl = Op.getDebugLoc();
2703 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2705 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
2706 SDValue Offset = DAG.getConstant(4, MVT::i32);
2707 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
2708 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
2709 MachinePointerInfo(), false, false, 0);
2712 // Return LR, which contains the return address. Mark it an implicit live-in.
2713 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
2714 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
2717 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2718 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2719 MFI->setFrameAddressIsTaken(true);
2721 EVT VT = Op.getValueType();
2722 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
2723 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2724 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
2725 ? ARM::R7 : ARM::R11;
2726 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
2728 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
2729 MachinePointerInfo(),
2734 /// ExpandBIT_CONVERT - If the target supports VFP, this function is called to
2735 /// expand a bit convert where either the source or destination type is i64 to
2736 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
2737 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
2738 /// vectors), since the legalizer won't know what to do with that.
2739 static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
2740 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2741 DebugLoc dl = N->getDebugLoc();
2742 SDValue Op = N->getOperand(0);
2744 // This function is only supposed to be called for i64 types, either as the
2745 // source or destination of the bit convert.
2746 EVT SrcVT = Op.getValueType();
2747 EVT DstVT = N->getValueType(0);
2748 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
2749 "ExpandBIT_CONVERT called for non-i64 type");
2751 // Turn i64->f64 into VMOVDRR.
2752 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
2753 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2754 DAG.getConstant(0, MVT::i32));
2755 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2756 DAG.getConstant(1, MVT::i32));
2757 return DAG.getNode(ISD::BIT_CONVERT, dl, DstVT,
2758 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
2761 // Turn f64->i64 into VMOVRRD.
2762 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
2763 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
2764 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
2765 // Merge the pieces into a single i64 value.
2766 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
2772 /// getZeroVector - Returns a vector of specified type with all zero elements.
2773 /// Zero vectors are used to represent vector negation and in those cases
2774 /// will be implemented with the NEON VNEG instruction. However, VNEG does
2775 /// not support i64 elements, so sometimes the zero vectors will need to be
2776 /// explicitly constructed. Regardless, use a canonical VMOV to create the
2778 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2779 assert(VT.isVector() && "Expected a vector type");
2780 // The canonical modified immediate encoding of a zero vector is....0!
2781 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32);
2782 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
2783 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
2784 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov);
2787 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
2788 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2789 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
2790 SelectionDAG &DAG) const {
2791 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2792 EVT VT = Op.getValueType();
2793 unsigned VTBits = VT.getSizeInBits();
2794 DebugLoc dl = Op.getDebugLoc();
2795 SDValue ShOpLo = Op.getOperand(0);
2796 SDValue ShOpHi = Op.getOperand(1);
2797 SDValue ShAmt = Op.getOperand(2);
2799 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
2801 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
2803 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2804 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2805 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
2806 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2807 DAG.getConstant(VTBits, MVT::i32));
2808 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
2809 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2810 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
2812 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2813 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
2815 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
2816 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
2819 SDValue Ops[2] = { Lo, Hi };
2820 return DAG.getMergeValues(Ops, 2, dl);
2823 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
2824 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2825 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
2826 SelectionDAG &DAG) const {
2827 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2828 EVT VT = Op.getValueType();
2829 unsigned VTBits = VT.getSizeInBits();
2830 DebugLoc dl = Op.getDebugLoc();
2831 SDValue ShOpLo = Op.getOperand(0);
2832 SDValue ShOpHi = Op.getOperand(1);
2833 SDValue ShAmt = Op.getOperand(2);
2836 assert(Op.getOpcode() == ISD::SHL_PARTS);
2837 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2838 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2839 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
2840 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2841 DAG.getConstant(VTBits, MVT::i32));
2842 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
2843 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
2845 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2846 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2847 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
2849 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
2850 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
2853 SDValue Ops[2] = { Lo, Hi };
2854 return DAG.getMergeValues(Ops, 2, dl);
2857 SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
2858 SelectionDAG &DAG) const {
2859 // The rounding mode is in bits 23:22 of the FPSCR.
2860 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
2861 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
2862 // so that the shift + and get folded into a bitfield extract.
2863 DebugLoc dl = Op.getDebugLoc();
2864 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
2865 DAG.getConstant(Intrinsic::arm_get_fpscr,
2867 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
2868 DAG.getConstant(1U << 22, MVT::i32));
2869 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
2870 DAG.getConstant(22, MVT::i32));
2871 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
2872 DAG.getConstant(3, MVT::i32));
2875 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
2876 const ARMSubtarget *ST) {
2877 EVT VT = N->getValueType(0);
2878 DebugLoc dl = N->getDebugLoc();
2880 if (!ST->hasV6T2Ops())
2883 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
2884 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
2887 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
2888 const ARMSubtarget *ST) {
2889 EVT VT = N->getValueType(0);
2890 DebugLoc dl = N->getDebugLoc();
2892 // Lower vector shifts on NEON to use VSHL.
2893 if (VT.isVector()) {
2894 assert(ST->hasNEON() && "unexpected vector shift");
2896 // Left shifts translate directly to the vshiftu intrinsic.
2897 if (N->getOpcode() == ISD::SHL)
2898 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2899 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
2900 N->getOperand(0), N->getOperand(1));
2902 assert((N->getOpcode() == ISD::SRA ||
2903 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
2905 // NEON uses the same intrinsics for both left and right shifts. For
2906 // right shifts, the shift amounts are negative, so negate the vector of
2908 EVT ShiftVT = N->getOperand(1).getValueType();
2909 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
2910 getZeroVector(ShiftVT, DAG, dl),
2912 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
2913 Intrinsic::arm_neon_vshifts :
2914 Intrinsic::arm_neon_vshiftu);
2915 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2916 DAG.getConstant(vshiftInt, MVT::i32),
2917 N->getOperand(0), NegatedCount);
2920 // We can get here for a node like i32 = ISD::SHL i32, i64
2924 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
2925 "Unknown shift to lower!");
2927 // We only lower SRA, SRL of 1 here, all others use generic lowering.
2928 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
2929 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
2932 // If we are in thumb mode, we don't have RRX.
2933 if (ST->isThumb1Only()) return SDValue();
2935 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
2936 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2937 DAG.getConstant(0, MVT::i32));
2938 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2939 DAG.getConstant(1, MVT::i32));
2941 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
2942 // captures the result into a carry flag.
2943 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
2944 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
2946 // The low part is an ARMISD::RRX operand, which shifts the carry in.
2947 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
2949 // Merge the pieces into a single i64 value.
2950 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
2953 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
2954 SDValue TmpOp0, TmpOp1;
2955 bool Invert = false;
2959 SDValue Op0 = Op.getOperand(0);
2960 SDValue Op1 = Op.getOperand(1);
2961 SDValue CC = Op.getOperand(2);
2962 EVT VT = Op.getValueType();
2963 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
2964 DebugLoc dl = Op.getDebugLoc();
2966 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
2967 switch (SetCCOpcode) {
2968 default: llvm_unreachable("Illegal FP comparison"); break;
2970 case ISD::SETNE: Invert = true; // Fallthrough
2972 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2974 case ISD::SETLT: Swap = true; // Fallthrough
2976 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2978 case ISD::SETLE: Swap = true; // Fallthrough
2980 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2981 case ISD::SETUGE: Swap = true; // Fallthrough
2982 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
2983 case ISD::SETUGT: Swap = true; // Fallthrough
2984 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
2985 case ISD::SETUEQ: Invert = true; // Fallthrough
2987 // Expand this to (OLT | OGT).
2991 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2992 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
2994 case ISD::SETUO: Invert = true; // Fallthrough
2996 // Expand this to (OLT | OGE).
3000 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3001 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
3005 // Integer comparisons.
3006 switch (SetCCOpcode) {
3007 default: llvm_unreachable("Illegal integer comparison"); break;
3008 case ISD::SETNE: Invert = true;
3009 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3010 case ISD::SETLT: Swap = true;
3011 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3012 case ISD::SETLE: Swap = true;
3013 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3014 case ISD::SETULT: Swap = true;
3015 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
3016 case ISD::SETULE: Swap = true;
3017 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
3020 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
3021 if (Opc == ARMISD::VCEQ) {
3024 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
3026 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
3029 // Ignore bitconvert.
3030 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BIT_CONVERT)
3031 AndOp = AndOp.getOperand(0);
3033 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
3035 Op0 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(0));
3036 Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(1));
3043 std::swap(Op0, Op1);
3045 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3048 Result = DAG.getNOT(dl, Result, VT);
3053 /// isNEONModifiedImm - Check if the specified splat value corresponds to a
3054 /// valid vector constant for a NEON instruction with a "modified immediate"
3055 /// operand (e.g., VMOV). If so, return the encoded value.
3056 static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
3057 unsigned SplatBitSize, SelectionDAG &DAG,
3058 EVT &VT, bool is128Bits, bool isVMOV) {
3059 unsigned OpCmode, Imm;
3061 // SplatBitSize is set to the smallest size that splats the vector, so a
3062 // zero vector will always have SplatBitSize == 8. However, NEON modified
3063 // immediate instructions others than VMOV do not support the 8-bit encoding
3064 // of a zero vector, and the default encoding of zero is supposed to be the
3069 switch (SplatBitSize) {
3073 // Any 1-byte value is OK. Op=0, Cmode=1110.
3074 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
3077 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
3081 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
3082 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
3083 if ((SplatBits & ~0xff) == 0) {
3084 // Value = 0x00nn: Op=x, Cmode=100x.
3089 if ((SplatBits & ~0xff00) == 0) {
3090 // Value = 0xnn00: Op=x, Cmode=101x.
3092 Imm = SplatBits >> 8;
3098 // NEON's 32-bit VMOV supports splat values where:
3099 // * only one byte is nonzero, or
3100 // * the least significant byte is 0xff and the second byte is nonzero, or
3101 // * the least significant 2 bytes are 0xff and the third is nonzero.
3102 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
3103 if ((SplatBits & ~0xff) == 0) {
3104 // Value = 0x000000nn: Op=x, Cmode=000x.
3109 if ((SplatBits & ~0xff00) == 0) {
3110 // Value = 0x0000nn00: Op=x, Cmode=001x.
3112 Imm = SplatBits >> 8;
3115 if ((SplatBits & ~0xff0000) == 0) {
3116 // Value = 0x00nn0000: Op=x, Cmode=010x.
3118 Imm = SplatBits >> 16;
3121 if ((SplatBits & ~0xff000000) == 0) {
3122 // Value = 0xnn000000: Op=x, Cmode=011x.
3124 Imm = SplatBits >> 24;
3128 if ((SplatBits & ~0xffff) == 0 &&
3129 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
3130 // Value = 0x0000nnff: Op=x, Cmode=1100.
3132 Imm = SplatBits >> 8;
3137 if ((SplatBits & ~0xffffff) == 0 &&
3138 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
3139 // Value = 0x00nnffff: Op=x, Cmode=1101.
3141 Imm = SplatBits >> 16;
3142 SplatBits |= 0xffff;
3146 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
3147 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
3148 // VMOV.I32. A (very) minor optimization would be to replicate the value
3149 // and fall through here to test for a valid 64-bit splat. But, then the
3150 // caller would also need to check and handle the change in size.
3156 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
3157 uint64_t BitMask = 0xff;
3159 unsigned ImmMask = 1;
3161 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
3162 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
3165 } else if ((SplatBits & BitMask) != 0) {
3171 // Op=1, Cmode=1110.
3174 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
3179 llvm_unreachable("unexpected size for isNEONModifiedImm");
3183 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
3184 return DAG.getTargetConstant(EncodedVal, MVT::i32);
3187 static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT,
3188 bool &ReverseVEXT, unsigned &Imm) {
3189 unsigned NumElts = VT.getVectorNumElements();
3190 ReverseVEXT = false;
3192 // Assume that the first shuffle index is not UNDEF. Fail if it is.
3198 // If this is a VEXT shuffle, the immediate value is the index of the first
3199 // element. The other shuffle indices must be the successive elements after
3201 unsigned ExpectedElt = Imm;
3202 for (unsigned i = 1; i < NumElts; ++i) {
3203 // Increment the expected index. If it wraps around, it may still be
3204 // a VEXT but the source vectors must be swapped.
3206 if (ExpectedElt == NumElts * 2) {
3211 if (M[i] < 0) continue; // ignore UNDEF indices
3212 if (ExpectedElt != static_cast<unsigned>(M[i]))
3216 // Adjust the index value if the source operands will be swapped.
3223 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
3224 /// instruction with the specified blocksize. (The order of the elements
3225 /// within each block of the vector is reversed.)
3226 static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT,
3227 unsigned BlockSize) {
3228 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
3229 "Only possible block sizes for VREV are: 16, 32, 64");
3231 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3235 unsigned NumElts = VT.getVectorNumElements();
3236 unsigned BlockElts = M[0] + 1;
3237 // If the first shuffle index is UNDEF, be optimistic.
3239 BlockElts = BlockSize / EltSz;
3241 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
3244 for (unsigned i = 0; i < NumElts; ++i) {
3245 if (M[i] < 0) continue; // ignore UNDEF indices
3246 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
3253 static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT,
3254 unsigned &WhichResult) {
3255 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3259 unsigned NumElts = VT.getVectorNumElements();
3260 WhichResult = (M[0] == 0 ? 0 : 1);
3261 for (unsigned i = 0; i < NumElts; i += 2) {
3262 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3263 (M[i+1] >= 0 && (unsigned) M[i+1] != i + NumElts + WhichResult))
3269 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
3270 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3271 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
3272 static bool isVTRN_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3273 unsigned &WhichResult) {
3274 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3278 unsigned NumElts = VT.getVectorNumElements();
3279 WhichResult = (M[0] == 0 ? 0 : 1);
3280 for (unsigned i = 0; i < NumElts; i += 2) {
3281 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3282 (M[i+1] >= 0 && (unsigned) M[i+1] != i + WhichResult))
3288 static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT,
3289 unsigned &WhichResult) {
3290 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3294 unsigned NumElts = VT.getVectorNumElements();
3295 WhichResult = (M[0] == 0 ? 0 : 1);
3296 for (unsigned i = 0; i != NumElts; ++i) {
3297 if (M[i] < 0) continue; // ignore UNDEF indices
3298 if ((unsigned) M[i] != 2 * i + WhichResult)
3302 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3303 if (VT.is64BitVector() && EltSz == 32)
3309 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
3310 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3311 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
3312 static bool isVUZP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3313 unsigned &WhichResult) {
3314 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3318 unsigned Half = VT.getVectorNumElements() / 2;
3319 WhichResult = (M[0] == 0 ? 0 : 1);
3320 for (unsigned j = 0; j != 2; ++j) {
3321 unsigned Idx = WhichResult;
3322 for (unsigned i = 0; i != Half; ++i) {
3323 int MIdx = M[i + j * Half];
3324 if (MIdx >= 0 && (unsigned) MIdx != Idx)
3330 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3331 if (VT.is64BitVector() && EltSz == 32)
3337 static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT,
3338 unsigned &WhichResult) {
3339 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3343 unsigned NumElts = VT.getVectorNumElements();
3344 WhichResult = (M[0] == 0 ? 0 : 1);
3345 unsigned Idx = WhichResult * NumElts / 2;
3346 for (unsigned i = 0; i != NumElts; i += 2) {
3347 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3348 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts))
3353 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3354 if (VT.is64BitVector() && EltSz == 32)
3360 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
3361 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3362 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
3363 static bool isVZIP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3364 unsigned &WhichResult) {
3365 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3369 unsigned NumElts = VT.getVectorNumElements();
3370 WhichResult = (M[0] == 0 ? 0 : 1);
3371 unsigned Idx = WhichResult * NumElts / 2;
3372 for (unsigned i = 0; i != NumElts; i += 2) {
3373 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3374 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx))
3379 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3380 if (VT.is64BitVector() && EltSz == 32)
3386 // If N is an integer constant that can be moved into a register in one
3387 // instruction, return an SDValue of such a constant (will become a MOV
3388 // instruction). Otherwise return null.
3389 static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG,
3390 const ARMSubtarget *ST, DebugLoc dl) {
3392 if (!isa<ConstantSDNode>(N))
3394 Val = cast<ConstantSDNode>(N)->getZExtValue();
3396 if (ST->isThumb1Only()) {
3397 if (Val <= 255 || ~Val <= 255)
3398 return DAG.getConstant(Val, MVT::i32);
3400 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1)
3401 return DAG.getConstant(Val, MVT::i32);
3406 // If this is a case we can't handle, return null and let the default
3407 // expansion code take care of it.
3408 static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
3409 const ARMSubtarget *ST) {
3410 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
3411 DebugLoc dl = Op.getDebugLoc();
3412 EVT VT = Op.getValueType();
3414 APInt SplatBits, SplatUndef;
3415 unsigned SplatBitSize;
3417 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
3418 if (SplatBitSize <= 64) {
3419 // Check if an immediate VMOV works.
3421 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
3422 SplatUndef.getZExtValue(), SplatBitSize,
3423 DAG, VmovVT, VT.is128BitVector(), true);
3424 if (Val.getNode()) {
3425 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
3426 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov);
3429 // Try an immediate VMVN.
3430 uint64_t NegatedImm = (SplatBits.getZExtValue() ^
3431 ((1LL << SplatBitSize) - 1));
3432 Val = isNEONModifiedImm(NegatedImm,
3433 SplatUndef.getZExtValue(), SplatBitSize,
3434 DAG, VmovVT, VT.is128BitVector(), false);
3435 if (Val.getNode()) {
3436 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
3437 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov);
3442 // Scan through the operands to see if only one value is used.
3443 unsigned NumElts = VT.getVectorNumElements();
3444 bool isOnlyLowElement = true;
3445 bool usesOnlyOneValue = true;
3446 bool isConstant = true;
3448 for (unsigned i = 0; i < NumElts; ++i) {
3449 SDValue V = Op.getOperand(i);
3450 if (V.getOpcode() == ISD::UNDEF)
3453 isOnlyLowElement = false;
3454 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
3457 if (!Value.getNode())
3459 else if (V != Value)
3460 usesOnlyOneValue = false;
3463 if (!Value.getNode())
3464 return DAG.getUNDEF(VT);
3466 if (isOnlyLowElement)
3467 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
3469 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3471 // Use VDUP for non-constant splats. For f32 constant splats, reduce to
3472 // i32 and try again.
3473 if (usesOnlyOneValue && EltSize <= 32) {
3475 return DAG.getNode(ARMISD::VDUP, dl, VT, Value);
3476 if (VT.getVectorElementType().isFloatingPoint()) {
3477 SmallVector<SDValue, 8> Ops;
3478 for (unsigned i = 0; i < NumElts; ++i)
3479 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32,
3481 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &Ops[0],
3483 Val = LowerBUILD_VECTOR(Val, DAG, ST);
3485 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val);
3487 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
3489 return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
3492 // If all elements are constants and the case above didn't get hit, fall back
3493 // to the default expansion, which will generate a load from the constant
3498 // Vectors with 32- or 64-bit elements can be built by directly assigning
3499 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
3500 // will be legalized.
3501 if (EltSize >= 32) {
3502 // Do the expansion with floating-point types, since that is what the VFP
3503 // registers are defined to use, and since i64 is not legal.
3504 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3505 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3506 SmallVector<SDValue, 8> Ops;
3507 for (unsigned i = 0; i < NumElts; ++i)
3508 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, EltVT, Op.getOperand(i)));
3509 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
3510 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val);
3516 /// isShuffleMaskLegal - Targets can use this to indicate that they only
3517 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
3518 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
3519 /// are assumed to be legal.
3521 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
3523 if (VT.getVectorNumElements() == 4 &&
3524 (VT.is128BitVector() || VT.is64BitVector())) {
3525 unsigned PFIndexes[4];
3526 for (unsigned i = 0; i != 4; ++i) {
3530 PFIndexes[i] = M[i];
3533 // Compute the index in the perfect shuffle table.
3534 unsigned PFTableIndex =
3535 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3536 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3537 unsigned Cost = (PFEntry >> 30);
3544 unsigned Imm, WhichResult;
3546 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3547 return (EltSize >= 32 ||
3548 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
3549 isVREVMask(M, VT, 64) ||
3550 isVREVMask(M, VT, 32) ||
3551 isVREVMask(M, VT, 16) ||
3552 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
3553 isVTRNMask(M, VT, WhichResult) ||
3554 isVUZPMask(M, VT, WhichResult) ||
3555 isVZIPMask(M, VT, WhichResult) ||
3556 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
3557 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
3558 isVZIP_v_undef_Mask(M, VT, WhichResult));
3561 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
3562 /// the specified operations to build the shuffle.
3563 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
3564 SDValue RHS, SelectionDAG &DAG,
3566 unsigned OpNum = (PFEntry >> 26) & 0x0F;
3567 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
3568 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
3571 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
3580 OP_VUZPL, // VUZP, left result
3581 OP_VUZPR, // VUZP, right result
3582 OP_VZIPL, // VZIP, left result
3583 OP_VZIPR, // VZIP, right result
3584 OP_VTRNL, // VTRN, left result
3585 OP_VTRNR // VTRN, right result
3588 if (OpNum == OP_COPY) {
3589 if (LHSID == (1*9+2)*9+3) return LHS;
3590 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
3594 SDValue OpLHS, OpRHS;
3595 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
3596 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
3597 EVT VT = OpLHS.getValueType();
3600 default: llvm_unreachable("Unknown shuffle opcode!");
3602 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
3607 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
3608 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
3612 return DAG.getNode(ARMISD::VEXT, dl, VT,
3614 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
3617 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3618 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
3621 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3622 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
3625 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3626 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
3630 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
3631 SDValue V1 = Op.getOperand(0);
3632 SDValue V2 = Op.getOperand(1);
3633 DebugLoc dl = Op.getDebugLoc();
3634 EVT VT = Op.getValueType();
3635 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
3636 SmallVector<int, 8> ShuffleMask;
3638 // Convert shuffles that are directly supported on NEON to target-specific
3639 // DAG nodes, instead of keeping them as shuffles and matching them again
3640 // during code selection. This is more efficient and avoids the possibility
3641 // of inconsistencies between legalization and selection.
3642 // FIXME: floating-point vectors should be canonicalized to integer vectors
3643 // of the same time so that they get CSEd properly.
3644 SVN->getMask(ShuffleMask);
3646 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3647 if (EltSize <= 32) {
3648 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
3649 int Lane = SVN->getSplatIndex();
3650 // If this is undef splat, generate it via "just" vdup, if possible.
3651 if (Lane == -1) Lane = 0;
3653 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
3654 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
3656 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
3657 DAG.getConstant(Lane, MVT::i32));
3662 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
3665 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
3666 DAG.getConstant(Imm, MVT::i32));
3669 if (isVREVMask(ShuffleMask, VT, 64))
3670 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
3671 if (isVREVMask(ShuffleMask, VT, 32))
3672 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
3673 if (isVREVMask(ShuffleMask, VT, 16))
3674 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
3676 // Check for Neon shuffles that modify both input vectors in place.
3677 // If both results are used, i.e., if there are two shuffles with the same
3678 // source operands and with masks corresponding to both results of one of
3679 // these operations, DAG memoization will ensure that a single node is
3680 // used for both shuffles.
3681 unsigned WhichResult;
3682 if (isVTRNMask(ShuffleMask, VT, WhichResult))
3683 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3684 V1, V2).getValue(WhichResult);
3685 if (isVUZPMask(ShuffleMask, VT, WhichResult))
3686 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3687 V1, V2).getValue(WhichResult);
3688 if (isVZIPMask(ShuffleMask, VT, WhichResult))
3689 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3690 V1, V2).getValue(WhichResult);
3692 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
3693 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3694 V1, V1).getValue(WhichResult);
3695 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
3696 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3697 V1, V1).getValue(WhichResult);
3698 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
3699 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3700 V1, V1).getValue(WhichResult);
3703 // If the shuffle is not directly supported and it has 4 elements, use
3704 // the PerfectShuffle-generated table to synthesize it from other shuffles.
3705 unsigned NumElts = VT.getVectorNumElements();
3707 unsigned PFIndexes[4];
3708 for (unsigned i = 0; i != 4; ++i) {
3709 if (ShuffleMask[i] < 0)
3712 PFIndexes[i] = ShuffleMask[i];
3715 // Compute the index in the perfect shuffle table.
3716 unsigned PFTableIndex =
3717 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3718 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3719 unsigned Cost = (PFEntry >> 30);
3722 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
3725 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
3726 if (EltSize >= 32) {
3727 // Do the expansion with floating-point types, since that is what the VFP
3728 // registers are defined to use, and since i64 is not legal.
3729 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3730 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3731 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, V1);
3732 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, V2);
3733 SmallVector<SDValue, 8> Ops;
3734 for (unsigned i = 0; i < NumElts; ++i) {
3735 if (ShuffleMask[i] < 0)
3736 Ops.push_back(DAG.getUNDEF(EltVT));
3738 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3739 ShuffleMask[i] < (int)NumElts ? V1 : V2,
3740 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
3743 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
3744 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val);
3750 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
3751 EVT VT = Op.getValueType();
3752 DebugLoc dl = Op.getDebugLoc();
3753 SDValue Vec = Op.getOperand(0);
3754 SDValue Lane = Op.getOperand(1);
3755 assert(VT == MVT::i32 &&
3756 Vec.getValueType().getVectorElementType().getSizeInBits() < 32 &&
3757 "unexpected type for custom-lowering vector extract");
3758 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
3761 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
3762 // The only time a CONCAT_VECTORS operation can have legal types is when
3763 // two 64-bit vectors are concatenated to a 128-bit vector.
3764 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
3765 "unexpected CONCAT_VECTORS");
3766 DebugLoc dl = Op.getDebugLoc();
3767 SDValue Val = DAG.getUNDEF(MVT::v2f64);
3768 SDValue Op0 = Op.getOperand(0);
3769 SDValue Op1 = Op.getOperand(1);
3770 if (Op0.getOpcode() != ISD::UNDEF)
3771 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
3772 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op0),
3773 DAG.getIntPtrConstant(0));
3774 if (Op1.getOpcode() != ISD::UNDEF)
3775 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
3776 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op1),
3777 DAG.getIntPtrConstant(1));
3778 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Val);
3781 /// SkipExtension - For a node that is either a SIGN_EXTEND, ZERO_EXTEND, or
3782 /// an extending load, return the unextended value.
3783 static SDValue SkipExtension(SDNode *N, SelectionDAG &DAG) {
3784 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
3785 return N->getOperand(0);
3786 LoadSDNode *LD = cast<LoadSDNode>(N);
3787 return DAG.getLoad(LD->getMemoryVT(), N->getDebugLoc(), LD->getChain(),
3788 LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(),
3789 LD->isNonTemporal(), LD->getAlignment());
3792 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
3793 // Multiplications are only custom-lowered for 128-bit vectors so that
3794 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
3795 EVT VT = Op.getValueType();
3796 assert(VT.is128BitVector() && "unexpected type for custom-lowering ISD::MUL");
3797 SDNode *N0 = Op.getOperand(0).getNode();
3798 SDNode *N1 = Op.getOperand(1).getNode();
3799 unsigned NewOpc = 0;
3800 if ((N0->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N0)) &&
3801 (N1->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N1))) {
3802 NewOpc = ARMISD::VMULLs;
3803 } else if ((N0->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N0)) &&
3804 (N1->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N1))) {
3805 NewOpc = ARMISD::VMULLu;
3806 } else if (VT.getSimpleVT().SimpleTy == MVT::v2i64) {
3807 // Fall through to expand this. It is not legal.
3810 // Other vector multiplications are legal.
3814 // Legalize to a VMULL instruction.
3815 DebugLoc DL = Op.getDebugLoc();
3816 SDValue Op0 = SkipExtension(N0, DAG);
3817 SDValue Op1 = SkipExtension(N1, DAG);
3819 assert(Op0.getValueType().is64BitVector() &&
3820 Op1.getValueType().is64BitVector() &&
3821 "unexpected types for extended operands to VMULL");
3822 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
3825 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
3826 switch (Op.getOpcode()) {
3827 default: llvm_unreachable("Don't know how to custom lower this!");
3828 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3829 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
3830 case ISD::GlobalAddress:
3831 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
3832 LowerGlobalAddressELF(Op, DAG);
3833 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
3834 case ISD::SELECT: return LowerSELECT(Op, DAG);
3835 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
3836 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
3837 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
3838 case ISD::VASTART: return LowerVASTART(Op, DAG);
3839 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget);
3840 case ISD::SINT_TO_FP:
3841 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
3842 case ISD::FP_TO_SINT:
3843 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
3844 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
3845 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
3846 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
3847 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
3848 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
3849 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
3850 case ISD::EH_SJLJ_DISPATCHSETUP: return LowerEH_SJLJ_DISPATCHSETUP(Op, DAG);
3851 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
3853 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(Op.getNode(), DAG);
3856 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
3857 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
3858 case ISD::SRL_PARTS:
3859 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
3860 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
3861 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
3862 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
3863 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
3864 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
3865 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
3866 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
3867 case ISD::MUL: return LowerMUL(Op, DAG);
3872 /// ReplaceNodeResults - Replace the results of node with an illegal result
3873 /// type with new values built out of custom code.
3874 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
3875 SmallVectorImpl<SDValue>&Results,
3876 SelectionDAG &DAG) const {
3878 switch (N->getOpcode()) {
3880 llvm_unreachable("Don't know how to custom expand this!");
3882 case ISD::BIT_CONVERT:
3883 Res = ExpandBIT_CONVERT(N, DAG);
3887 Res = LowerShift(N, DAG, Subtarget);
3891 Results.push_back(Res);
3894 //===----------------------------------------------------------------------===//
3895 // ARM Scheduler Hooks
3896 //===----------------------------------------------------------------------===//
3899 ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
3900 MachineBasicBlock *BB,
3901 unsigned Size) const {
3902 unsigned dest = MI->getOperand(0).getReg();
3903 unsigned ptr = MI->getOperand(1).getReg();
3904 unsigned oldval = MI->getOperand(2).getReg();
3905 unsigned newval = MI->getOperand(3).getReg();
3906 unsigned scratch = BB->getParent()->getRegInfo()
3907 .createVirtualRegister(ARM::GPRRegisterClass);
3908 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3909 DebugLoc dl = MI->getDebugLoc();
3910 bool isThumb2 = Subtarget->isThumb2();
3912 unsigned ldrOpc, strOpc;
3914 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
3916 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
3917 strOpc = isThumb2 ? ARM::t2LDREXB : ARM::STREXB;
3920 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
3921 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
3924 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
3925 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
3929 MachineFunction *MF = BB->getParent();
3930 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3931 MachineFunction::iterator It = BB;
3932 ++It; // insert the new blocks after the current block
3934 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
3935 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
3936 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3937 MF->insert(It, loop1MBB);
3938 MF->insert(It, loop2MBB);
3939 MF->insert(It, exitMBB);
3941 // Transfer the remainder of BB and its successor edges to exitMBB.
3942 exitMBB->splice(exitMBB->begin(), BB,
3943 llvm::next(MachineBasicBlock::iterator(MI)),
3945 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
3949 // fallthrough --> loop1MBB
3950 BB->addSuccessor(loop1MBB);
3953 // ldrex dest, [ptr]
3957 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
3958 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
3959 .addReg(dest).addReg(oldval));
3960 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3961 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
3962 BB->addSuccessor(loop2MBB);
3963 BB->addSuccessor(exitMBB);
3966 // strex scratch, newval, [ptr]
3970 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval)
3972 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
3973 .addReg(scratch).addImm(0));
3974 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3975 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
3976 BB->addSuccessor(loop1MBB);
3977 BB->addSuccessor(exitMBB);
3983 MI->eraseFromParent(); // The instruction is gone now.
3989 ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
3990 unsigned Size, unsigned BinOpcode) const {
3991 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
3992 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3994 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3995 MachineFunction *MF = BB->getParent();
3996 MachineFunction::iterator It = BB;
3999 unsigned dest = MI->getOperand(0).getReg();
4000 unsigned ptr = MI->getOperand(1).getReg();
4001 unsigned incr = MI->getOperand(2).getReg();
4002 DebugLoc dl = MI->getDebugLoc();
4004 bool isThumb2 = Subtarget->isThumb2();
4005 unsigned ldrOpc, strOpc;
4007 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
4009 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
4010 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
4013 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
4014 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
4017 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
4018 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
4022 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
4023 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
4024 MF->insert(It, loopMBB);
4025 MF->insert(It, exitMBB);
4027 // Transfer the remainder of BB and its successor edges to exitMBB.
4028 exitMBB->splice(exitMBB->begin(), BB,
4029 llvm::next(MachineBasicBlock::iterator(MI)),
4031 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4033 MachineRegisterInfo &RegInfo = MF->getRegInfo();
4034 unsigned scratch = RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
4035 unsigned scratch2 = (!BinOpcode) ? incr :
4036 RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
4040 // fallthrough --> loopMBB
4041 BB->addSuccessor(loopMBB);
4045 // <binop> scratch2, dest, incr
4046 // strex scratch, scratch2, ptr
4049 // fallthrough --> exitMBB
4051 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
4053 // operand order needs to go the other way for NAND
4054 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr)
4055 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
4056 addReg(incr).addReg(dest)).addReg(0);
4058 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
4059 addReg(dest).addReg(incr)).addReg(0);
4062 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2)
4064 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4065 .addReg(scratch).addImm(0));
4066 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4067 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
4069 BB->addSuccessor(loopMBB);
4070 BB->addSuccessor(exitMBB);
4076 MI->eraseFromParent(); // The instruction is gone now.
4082 MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
4083 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
4084 E = MBB->succ_end(); I != E; ++I)
4087 llvm_unreachable("Expecting a BB with two successors!");
4091 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4092 MachineBasicBlock *BB) const {
4093 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4094 DebugLoc dl = MI->getDebugLoc();
4095 bool isThumb2 = Subtarget->isThumb2();
4096 switch (MI->getOpcode()) {
4099 llvm_unreachable("Unexpected instr type to insert");
4101 case ARM::ATOMIC_LOAD_ADD_I8:
4102 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
4103 case ARM::ATOMIC_LOAD_ADD_I16:
4104 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
4105 case ARM::ATOMIC_LOAD_ADD_I32:
4106 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
4108 case ARM::ATOMIC_LOAD_AND_I8:
4109 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
4110 case ARM::ATOMIC_LOAD_AND_I16:
4111 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
4112 case ARM::ATOMIC_LOAD_AND_I32:
4113 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
4115 case ARM::ATOMIC_LOAD_OR_I8:
4116 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
4117 case ARM::ATOMIC_LOAD_OR_I16:
4118 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
4119 case ARM::ATOMIC_LOAD_OR_I32:
4120 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
4122 case ARM::ATOMIC_LOAD_XOR_I8:
4123 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
4124 case ARM::ATOMIC_LOAD_XOR_I16:
4125 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
4126 case ARM::ATOMIC_LOAD_XOR_I32:
4127 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
4129 case ARM::ATOMIC_LOAD_NAND_I8:
4130 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
4131 case ARM::ATOMIC_LOAD_NAND_I16:
4132 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
4133 case ARM::ATOMIC_LOAD_NAND_I32:
4134 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
4136 case ARM::ATOMIC_LOAD_SUB_I8:
4137 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
4138 case ARM::ATOMIC_LOAD_SUB_I16:
4139 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
4140 case ARM::ATOMIC_LOAD_SUB_I32:
4141 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
4143 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0);
4144 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0);
4145 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0);
4147 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1);
4148 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
4149 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
4151 case ARM::tMOVCCr_pseudo: {
4152 // To "insert" a SELECT_CC instruction, we actually have to insert the
4153 // diamond control-flow pattern. The incoming instruction knows the
4154 // destination vreg to set, the condition code register to branch on, the
4155 // true/false values to select between, and a branch opcode to use.
4156 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4157 MachineFunction::iterator It = BB;
4163 // cmpTY ccX, r1, r2
4165 // fallthrough --> copy0MBB
4166 MachineBasicBlock *thisMBB = BB;
4167 MachineFunction *F = BB->getParent();
4168 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4169 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
4170 F->insert(It, copy0MBB);
4171 F->insert(It, sinkMBB);
4173 // Transfer the remainder of BB and its successor edges to sinkMBB.
4174 sinkMBB->splice(sinkMBB->begin(), BB,
4175 llvm::next(MachineBasicBlock::iterator(MI)),
4177 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
4179 BB->addSuccessor(copy0MBB);
4180 BB->addSuccessor(sinkMBB);
4182 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
4183 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
4186 // %FalseValue = ...
4187 // # fallthrough to sinkMBB
4190 // Update machine-CFG edges
4191 BB->addSuccessor(sinkMBB);
4194 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
4197 BuildMI(*BB, BB->begin(), dl,
4198 TII->get(ARM::PHI), MI->getOperand(0).getReg())
4199 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
4200 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
4202 MI->eraseFromParent(); // The pseudo instruction is gone now.
4207 case ARM::BCCZi64: {
4208 // Compare both parts that make up the double comparison separately for
4210 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
4212 unsigned LHS1 = MI->getOperand(1).getReg();
4213 unsigned LHS2 = MI->getOperand(2).getReg();
4215 AddDefaultPred(BuildMI(BB, dl,
4216 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4217 .addReg(LHS1).addImm(0));
4218 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4219 .addReg(LHS2).addImm(0)
4220 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
4222 unsigned RHS1 = MI->getOperand(3).getReg();
4223 unsigned RHS2 = MI->getOperand(4).getReg();
4224 AddDefaultPred(BuildMI(BB, dl,
4225 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
4226 .addReg(LHS1).addReg(RHS1));
4227 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
4228 .addReg(LHS2).addReg(RHS2)
4229 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
4232 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB();
4233 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
4234 if (MI->getOperand(0).getImm() == ARMCC::NE)
4235 std::swap(destMBB, exitMBB);
4237 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4238 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
4239 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2B : ARM::B))
4242 MI->eraseFromParent(); // The pseudo instruction is gone now.
4248 //===----------------------------------------------------------------------===//
4249 // ARM Optimization Hooks
4250 //===----------------------------------------------------------------------===//
4253 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
4254 TargetLowering::DAGCombinerInfo &DCI) {
4255 SelectionDAG &DAG = DCI.DAG;
4256 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4257 EVT VT = N->getValueType(0);
4258 unsigned Opc = N->getOpcode();
4259 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
4260 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
4261 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
4262 ISD::CondCode CC = ISD::SETCC_INVALID;
4265 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
4267 SDValue CCOp = Slct.getOperand(0);
4268 if (CCOp.getOpcode() == ISD::SETCC)
4269 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
4272 bool DoXform = false;
4274 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
4277 if (LHS.getOpcode() == ISD::Constant &&
4278 cast<ConstantSDNode>(LHS)->isNullValue()) {
4280 } else if (CC != ISD::SETCC_INVALID &&
4281 RHS.getOpcode() == ISD::Constant &&
4282 cast<ConstantSDNode>(RHS)->isNullValue()) {
4283 std::swap(LHS, RHS);
4284 SDValue Op0 = Slct.getOperand(0);
4285 EVT OpVT = isSlctCC ? Op0.getValueType() :
4286 Op0.getOperand(0).getValueType();
4287 bool isInt = OpVT.isInteger();
4288 CC = ISD::getSetCCInverse(CC, isInt);
4290 if (!TLI.isCondCodeLegal(CC, OpVT))
4291 return SDValue(); // Inverse operator isn't legal.
4298 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
4300 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
4301 Slct.getOperand(0), Slct.getOperand(1), CC);
4302 SDValue CCOp = Slct.getOperand(0);
4304 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
4305 CCOp.getOperand(0), CCOp.getOperand(1), CC);
4306 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
4307 CCOp, OtherOp, Result);
4312 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
4313 /// operands N0 and N1. This is a helper for PerformADDCombine that is
4314 /// called with the default operands, and if that fails, with commuted
4316 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
4317 TargetLowering::DAGCombinerInfo &DCI) {
4318 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
4319 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
4320 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
4321 if (Result.getNode()) return Result;
4326 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
4328 static SDValue PerformADDCombine(SDNode *N,
4329 TargetLowering::DAGCombinerInfo &DCI) {
4330 SDValue N0 = N->getOperand(0);
4331 SDValue N1 = N->getOperand(1);
4333 // First try with the default operand order.
4334 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI);
4335 if (Result.getNode())
4338 // If that didn't work, try again with the operands commuted.
4339 return PerformADDCombineWithOperands(N, N1, N0, DCI);
4342 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
4344 static SDValue PerformSUBCombine(SDNode *N,
4345 TargetLowering::DAGCombinerInfo &DCI) {
4346 SDValue N0 = N->getOperand(0);
4347 SDValue N1 = N->getOperand(1);
4349 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
4350 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
4351 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
4352 if (Result.getNode()) return Result;
4358 static SDValue PerformMULCombine(SDNode *N,
4359 TargetLowering::DAGCombinerInfo &DCI,
4360 const ARMSubtarget *Subtarget) {
4361 SelectionDAG &DAG = DCI.DAG;
4363 if (Subtarget->isThumb1Only())
4366 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
4369 EVT VT = N->getValueType(0);
4373 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
4377 uint64_t MulAmt = C->getZExtValue();
4378 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt);
4379 ShiftAmt = ShiftAmt & (32 - 1);
4380 SDValue V = N->getOperand(0);
4381 DebugLoc DL = N->getDebugLoc();
4384 MulAmt >>= ShiftAmt;
4385 if (isPowerOf2_32(MulAmt - 1)) {
4386 // (mul x, 2^N + 1) => (add (shl x, N), x)
4387 Res = DAG.getNode(ISD::ADD, DL, VT,
4388 V, DAG.getNode(ISD::SHL, DL, VT,
4389 V, DAG.getConstant(Log2_32(MulAmt-1),
4391 } else if (isPowerOf2_32(MulAmt + 1)) {
4392 // (mul x, 2^N - 1) => (sub (shl x, N), x)
4393 Res = DAG.getNode(ISD::SUB, DL, VT,
4394 DAG.getNode(ISD::SHL, DL, VT,
4395 V, DAG.getConstant(Log2_32(MulAmt+1),
4402 Res = DAG.getNode(ISD::SHL, DL, VT, Res,
4403 DAG.getConstant(ShiftAmt, MVT::i32));
4405 // Do not add new nodes to DAG combiner worklist.
4406 DCI.CombineTo(N, Res, false);
4410 /// PerformORCombine - Target-specific dag combine xforms for ISD::OR
4411 static SDValue PerformORCombine(SDNode *N,
4412 TargetLowering::DAGCombinerInfo &DCI,
4413 const ARMSubtarget *Subtarget) {
4414 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when
4417 // BFI is only available on V6T2+
4418 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops())
4421 SelectionDAG &DAG = DCI.DAG;
4422 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
4423 DebugLoc DL = N->getDebugLoc();
4424 // 1) or (and A, mask), val => ARMbfi A, val, mask
4425 // iff (val & mask) == val
4427 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
4428 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2)
4429 // && CountPopulation_32(mask) == CountPopulation_32(~mask2)
4430 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2)
4431 // && CountPopulation_32(mask) == CountPopulation_32(~mask2)
4432 // (i.e., copy a bitfield value into another bitfield of the same width)
4433 if (N0.getOpcode() != ISD::AND)
4436 EVT VT = N->getValueType(0);
4441 // The value and the mask need to be constants so we can verify this is
4442 // actually a bitfield set. If the mask is 0xffff, we can do better
4443 // via a movt instruction, so don't use BFI in that case.
4444 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
4447 unsigned Mask = C->getZExtValue();
4451 // Case (1): or (and A, mask), val => ARMbfi A, val, mask
4452 if ((C = dyn_cast<ConstantSDNode>(N1))) {
4453 unsigned Val = C->getZExtValue();
4454 if (!ARM::isBitFieldInvertedMask(Mask) || (Val & ~Mask) != Val)
4456 Val >>= CountTrailingZeros_32(~Mask);
4458 Res = DAG.getNode(ARMISD::BFI, DL, VT, N0.getOperand(0),
4459 DAG.getConstant(Val, MVT::i32),
4460 DAG.getConstant(Mask, MVT::i32));
4462 // Do not add new nodes to DAG combiner worklist.
4463 DCI.CombineTo(N, Res, false);
4464 } else if (N1.getOpcode() == ISD::AND) {
4465 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
4466 C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
4469 unsigned Mask2 = C->getZExtValue();
4471 if (ARM::isBitFieldInvertedMask(Mask) &&
4472 ARM::isBitFieldInvertedMask(~Mask2) &&
4473 (CountPopulation_32(Mask) == CountPopulation_32(~Mask2))) {
4474 // The pack halfword instruction works better for masks that fit it,
4475 // so use that when it's available.
4476 if (Subtarget->hasT2ExtractPack() &&
4477 (Mask == 0xffff || Mask == 0xffff0000))
4480 unsigned lsb = CountTrailingZeros_32(Mask2);
4481 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
4482 DAG.getConstant(lsb, MVT::i32));
4483 Res = DAG.getNode(ARMISD::BFI, DL, VT, N0.getOperand(0), Res,
4484 DAG.getConstant(Mask, MVT::i32));
4485 // Do not add new nodes to DAG combiner worklist.
4486 DCI.CombineTo(N, Res, false);
4487 } else if (ARM::isBitFieldInvertedMask(~Mask) &&
4488 ARM::isBitFieldInvertedMask(Mask2) &&
4489 (CountPopulation_32(~Mask) == CountPopulation_32(Mask2))) {
4490 // The pack halfword instruction works better for masks that fit it,
4491 // so use that when it's available.
4492 if (Subtarget->hasT2ExtractPack() &&
4493 (Mask2 == 0xffff || Mask2 == 0xffff0000))
4496 unsigned lsb = CountTrailingZeros_32(Mask);
4497 Res = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0),
4498 DAG.getConstant(lsb, MVT::i32));
4499 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
4500 DAG.getConstant(Mask2, MVT::i32));
4501 // Do not add new nodes to DAG combiner worklist.
4502 DCI.CombineTo(N, Res, false);
4509 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
4510 /// ARMISD::VMOVRRD.
4511 static SDValue PerformVMOVRRDCombine(SDNode *N,
4512 TargetLowering::DAGCombinerInfo &DCI) {
4513 // vmovrrd(vmovdrr x, y) -> x,y
4514 SDValue InDouble = N->getOperand(0);
4515 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
4516 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
4520 /// PerformVMOVDRRCombine - Target-specific dag combine xforms for
4521 /// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands.
4522 static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) {
4523 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X)
4524 SDValue Op0 = N->getOperand(0);
4525 SDValue Op1 = N->getOperand(1);
4526 if (Op0.getOpcode() == ISD::BIT_CONVERT)
4527 Op0 = Op0.getOperand(0);
4528 if (Op1.getOpcode() == ISD::BIT_CONVERT)
4529 Op1 = Op1.getOperand(0);
4530 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
4531 Op0.getNode() == Op1.getNode() &&
4532 Op0.getResNo() == 0 && Op1.getResNo() == 1)
4533 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
4534 N->getValueType(0), Op0.getOperand(0));
4538 /// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for
4539 /// ISD::BUILD_VECTOR.
4540 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG) {
4541 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X):
4542 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value
4543 // into a pair of GPRs, which is fine when the value is used as a scalar,
4544 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD.
4545 if (N->getNumOperands() == 2)
4546 return PerformVMOVDRRCombine(N, DAG);
4551 /// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for
4552 /// ISD::VECTOR_SHUFFLE.
4553 static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) {
4554 // The LLVM shufflevector instruction does not require the shuffle mask
4555 // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does
4556 // have that requirement. When translating to ISD::VECTOR_SHUFFLE, if the
4557 // operands do not match the mask length, they are extended by concatenating
4558 // them with undef vectors. That is probably the right thing for other
4559 // targets, but for NEON it is better to concatenate two double-register
4560 // size vector operands into a single quad-register size vector. Do that
4561 // transformation here:
4562 // shuffle(concat(v1, undef), concat(v2, undef)) ->
4563 // shuffle(concat(v1, v2), undef)
4564 SDValue Op0 = N->getOperand(0);
4565 SDValue Op1 = N->getOperand(1);
4566 if (Op0.getOpcode() != ISD::CONCAT_VECTORS ||
4567 Op1.getOpcode() != ISD::CONCAT_VECTORS ||
4568 Op0.getNumOperands() != 2 ||
4569 Op1.getNumOperands() != 2)
4571 SDValue Concat0Op1 = Op0.getOperand(1);
4572 SDValue Concat1Op1 = Op1.getOperand(1);
4573 if (Concat0Op1.getOpcode() != ISD::UNDEF ||
4574 Concat1Op1.getOpcode() != ISD::UNDEF)
4576 // Skip the transformation if any of the types are illegal.
4577 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4578 EVT VT = N->getValueType(0);
4579 if (!TLI.isTypeLegal(VT) ||
4580 !TLI.isTypeLegal(Concat0Op1.getValueType()) ||
4581 !TLI.isTypeLegal(Concat1Op1.getValueType()))
4584 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT,
4585 Op0.getOperand(0), Op1.getOperand(0));
4586 // Translate the shuffle mask.
4587 SmallVector<int, 16> NewMask;
4588 unsigned NumElts = VT.getVectorNumElements();
4589 unsigned HalfElts = NumElts/2;
4590 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
4591 for (unsigned n = 0; n < NumElts; ++n) {
4592 int MaskElt = SVN->getMaskElt(n);
4594 if (MaskElt < (int)HalfElts)
4596 else if (MaskElt >= (int)NumElts && MaskElt < (int)(NumElts + HalfElts))
4597 NewElt = HalfElts + MaskElt - NumElts;
4598 NewMask.push_back(NewElt);
4600 return DAG.getVectorShuffle(VT, N->getDebugLoc(), NewConcat,
4601 DAG.getUNDEF(VT), NewMask.data());
4604 /// PerformVDUPLANECombine - Target-specific dag combine xforms for
4605 /// ARMISD::VDUPLANE.
4606 static SDValue PerformVDUPLANECombine(SDNode *N, SelectionDAG &DAG) {
4607 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
4609 SDValue Op = N->getOperand(0);
4610 EVT VT = N->getValueType(0);
4612 // Ignore bit_converts.
4613 while (Op.getOpcode() == ISD::BIT_CONVERT)
4614 Op = Op.getOperand(0);
4615 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
4618 // Make sure the VMOV element size is not bigger than the VDUPLANE elements.
4619 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits();
4620 // The canonical VMOV for a zero vector uses a 32-bit element size.
4621 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4623 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
4625 if (EltSize > VT.getVectorElementType().getSizeInBits())
4628 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
4631 /// getVShiftImm - Check if this is a valid build_vector for the immediate
4632 /// operand of a vector shift operation, where all the elements of the
4633 /// build_vector must have the same constant integer value.
4634 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
4635 // Ignore bit_converts.
4636 while (Op.getOpcode() == ISD::BIT_CONVERT)
4637 Op = Op.getOperand(0);
4638 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
4639 APInt SplatBits, SplatUndef;
4640 unsigned SplatBitSize;
4642 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
4643 HasAnyUndefs, ElementBits) ||
4644 SplatBitSize > ElementBits)
4646 Cnt = SplatBits.getSExtValue();
4650 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
4651 /// operand of a vector shift left operation. That value must be in the range:
4652 /// 0 <= Value < ElementBits for a left shift; or
4653 /// 0 <= Value <= ElementBits for a long left shift.
4654 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
4655 assert(VT.isVector() && "vector shift count is not a vector type");
4656 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
4657 if (! getVShiftImm(Op, ElementBits, Cnt))
4659 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
4662 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
4663 /// operand of a vector shift right operation. For a shift opcode, the value
4664 /// is positive, but for an intrinsic the value count must be negative. The
4665 /// absolute value must be in the range:
4666 /// 1 <= |Value| <= ElementBits for a right shift; or
4667 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
4668 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
4670 assert(VT.isVector() && "vector shift count is not a vector type");
4671 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
4672 if (! getVShiftImm(Op, ElementBits, Cnt))
4676 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
4679 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
4680 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
4681 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
4684 // Don't do anything for most intrinsics.
4687 // Vector shifts: check for immediate versions and lower them.
4688 // Note: This is done during DAG combining instead of DAG legalizing because
4689 // the build_vectors for 64-bit vector element shift counts are generally
4690 // not legal, and it is hard to see their values after they get legalized to
4691 // loads from a constant pool.
4692 case Intrinsic::arm_neon_vshifts:
4693 case Intrinsic::arm_neon_vshiftu:
4694 case Intrinsic::arm_neon_vshiftls:
4695 case Intrinsic::arm_neon_vshiftlu:
4696 case Intrinsic::arm_neon_vshiftn:
4697 case Intrinsic::arm_neon_vrshifts:
4698 case Intrinsic::arm_neon_vrshiftu:
4699 case Intrinsic::arm_neon_vrshiftn:
4700 case Intrinsic::arm_neon_vqshifts:
4701 case Intrinsic::arm_neon_vqshiftu:
4702 case Intrinsic::arm_neon_vqshiftsu:
4703 case Intrinsic::arm_neon_vqshiftns:
4704 case Intrinsic::arm_neon_vqshiftnu:
4705 case Intrinsic::arm_neon_vqshiftnsu:
4706 case Intrinsic::arm_neon_vqrshiftns:
4707 case Intrinsic::arm_neon_vqrshiftnu:
4708 case Intrinsic::arm_neon_vqrshiftnsu: {
4709 EVT VT = N->getOperand(1).getValueType();
4711 unsigned VShiftOpc = 0;
4714 case Intrinsic::arm_neon_vshifts:
4715 case Intrinsic::arm_neon_vshiftu:
4716 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
4717 VShiftOpc = ARMISD::VSHL;
4720 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
4721 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
4722 ARMISD::VSHRs : ARMISD::VSHRu);
4727 case Intrinsic::arm_neon_vshiftls:
4728 case Intrinsic::arm_neon_vshiftlu:
4729 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
4731 llvm_unreachable("invalid shift count for vshll intrinsic");
4733 case Intrinsic::arm_neon_vrshifts:
4734 case Intrinsic::arm_neon_vrshiftu:
4735 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
4739 case Intrinsic::arm_neon_vqshifts:
4740 case Intrinsic::arm_neon_vqshiftu:
4741 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
4745 case Intrinsic::arm_neon_vqshiftsu:
4746 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
4748 llvm_unreachable("invalid shift count for vqshlu intrinsic");
4750 case Intrinsic::arm_neon_vshiftn:
4751 case Intrinsic::arm_neon_vrshiftn:
4752 case Intrinsic::arm_neon_vqshiftns:
4753 case Intrinsic::arm_neon_vqshiftnu:
4754 case Intrinsic::arm_neon_vqshiftnsu:
4755 case Intrinsic::arm_neon_vqrshiftns:
4756 case Intrinsic::arm_neon_vqrshiftnu:
4757 case Intrinsic::arm_neon_vqrshiftnsu:
4758 // Narrowing shifts require an immediate right shift.
4759 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
4761 llvm_unreachable("invalid shift count for narrowing vector shift "
4765 llvm_unreachable("unhandled vector shift");
4769 case Intrinsic::arm_neon_vshifts:
4770 case Intrinsic::arm_neon_vshiftu:
4771 // Opcode already set above.
4773 case Intrinsic::arm_neon_vshiftls:
4774 case Intrinsic::arm_neon_vshiftlu:
4775 if (Cnt == VT.getVectorElementType().getSizeInBits())
4776 VShiftOpc = ARMISD::VSHLLi;
4778 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
4779 ARMISD::VSHLLs : ARMISD::VSHLLu);
4781 case Intrinsic::arm_neon_vshiftn:
4782 VShiftOpc = ARMISD::VSHRN; break;
4783 case Intrinsic::arm_neon_vrshifts:
4784 VShiftOpc = ARMISD::VRSHRs; break;
4785 case Intrinsic::arm_neon_vrshiftu:
4786 VShiftOpc = ARMISD::VRSHRu; break;
4787 case Intrinsic::arm_neon_vrshiftn:
4788 VShiftOpc = ARMISD::VRSHRN; break;
4789 case Intrinsic::arm_neon_vqshifts:
4790 VShiftOpc = ARMISD::VQSHLs; break;
4791 case Intrinsic::arm_neon_vqshiftu:
4792 VShiftOpc = ARMISD::VQSHLu; break;
4793 case Intrinsic::arm_neon_vqshiftsu:
4794 VShiftOpc = ARMISD::VQSHLsu; break;
4795 case Intrinsic::arm_neon_vqshiftns:
4796 VShiftOpc = ARMISD::VQSHRNs; break;
4797 case Intrinsic::arm_neon_vqshiftnu:
4798 VShiftOpc = ARMISD::VQSHRNu; break;
4799 case Intrinsic::arm_neon_vqshiftnsu:
4800 VShiftOpc = ARMISD::VQSHRNsu; break;
4801 case Intrinsic::arm_neon_vqrshiftns:
4802 VShiftOpc = ARMISD::VQRSHRNs; break;
4803 case Intrinsic::arm_neon_vqrshiftnu:
4804 VShiftOpc = ARMISD::VQRSHRNu; break;
4805 case Intrinsic::arm_neon_vqrshiftnsu:
4806 VShiftOpc = ARMISD::VQRSHRNsu; break;
4809 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
4810 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
4813 case Intrinsic::arm_neon_vshiftins: {
4814 EVT VT = N->getOperand(1).getValueType();
4816 unsigned VShiftOpc = 0;
4818 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
4819 VShiftOpc = ARMISD::VSLI;
4820 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
4821 VShiftOpc = ARMISD::VSRI;
4823 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
4826 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
4827 N->getOperand(1), N->getOperand(2),
4828 DAG.getConstant(Cnt, MVT::i32));
4831 case Intrinsic::arm_neon_vqrshifts:
4832 case Intrinsic::arm_neon_vqrshiftu:
4833 // No immediate versions of these to check for.
4840 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
4841 /// lowers them. As with the vector shift intrinsics, this is done during DAG
4842 /// combining instead of DAG legalizing because the build_vectors for 64-bit
4843 /// vector element shift counts are generally not legal, and it is hard to see
4844 /// their values after they get legalized to loads from a constant pool.
4845 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
4846 const ARMSubtarget *ST) {
4847 EVT VT = N->getValueType(0);
4849 // Nothing to be done for scalar shifts.
4850 if (! VT.isVector())
4853 assert(ST->hasNEON() && "unexpected vector shift");
4856 switch (N->getOpcode()) {
4857 default: llvm_unreachable("unexpected shift opcode");
4860 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
4861 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
4862 DAG.getConstant(Cnt, MVT::i32));
4867 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
4868 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
4869 ARMISD::VSHRs : ARMISD::VSHRu);
4870 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
4871 DAG.getConstant(Cnt, MVT::i32));
4877 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
4878 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
4879 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
4880 const ARMSubtarget *ST) {
4881 SDValue N0 = N->getOperand(0);
4883 // Check for sign- and zero-extensions of vector extract operations of 8-
4884 // and 16-bit vector elements. NEON supports these directly. They are
4885 // handled during DAG combining because type legalization will promote them
4886 // to 32-bit types and it is messy to recognize the operations after that.
4887 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
4888 SDValue Vec = N0.getOperand(0);
4889 SDValue Lane = N0.getOperand(1);
4890 EVT VT = N->getValueType(0);
4891 EVT EltVT = N0.getValueType();
4892 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4894 if (VT == MVT::i32 &&
4895 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
4896 TLI.isTypeLegal(Vec.getValueType())) {
4899 switch (N->getOpcode()) {
4900 default: llvm_unreachable("unexpected opcode");
4901 case ISD::SIGN_EXTEND:
4902 Opc = ARMISD::VGETLANEs;
4904 case ISD::ZERO_EXTEND:
4905 case ISD::ANY_EXTEND:
4906 Opc = ARMISD::VGETLANEu;
4909 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
4916 /// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
4917 /// to match f32 max/min patterns to use NEON vmax/vmin instructions.
4918 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
4919 const ARMSubtarget *ST) {
4920 // If the target supports NEON, try to use vmax/vmin instructions for f32
4921 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set,
4922 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
4923 // a NaN; only do the transformation when it matches that behavior.
4925 // For now only do this when using NEON for FP operations; if using VFP, it
4926 // is not obvious that the benefit outweighs the cost of switching to the
4928 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
4929 N->getValueType(0) != MVT::f32)
4932 SDValue CondLHS = N->getOperand(0);
4933 SDValue CondRHS = N->getOperand(1);
4934 SDValue LHS = N->getOperand(2);
4935 SDValue RHS = N->getOperand(3);
4936 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
4938 unsigned Opcode = 0;
4940 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
4941 IsReversed = false; // x CC y ? x : y
4942 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
4943 IsReversed = true ; // x CC y ? y : x
4957 // If LHS is NaN, an ordered comparison will be false and the result will
4958 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
4959 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
4960 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
4961 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
4963 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
4964 // will return -0, so vmin can only be used for unsafe math or if one of
4965 // the operands is known to be nonzero.
4966 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
4968 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
4970 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
4979 // If LHS is NaN, an ordered comparison will be false and the result will
4980 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
4981 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
4982 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
4983 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
4985 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
4986 // will return +0, so vmax can only be used for unsafe math or if one of
4987 // the operands is known to be nonzero.
4988 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
4990 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
4992 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
4998 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS);
5001 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
5002 DAGCombinerInfo &DCI) const {
5003 switch (N->getOpcode()) {
5005 case ISD::ADD: return PerformADDCombine(N, DCI);
5006 case ISD::SUB: return PerformSUBCombine(N, DCI);
5007 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
5008 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
5009 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
5010 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
5011 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI.DAG);
5012 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
5013 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI.DAG);
5014 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
5017 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
5018 case ISD::SIGN_EXTEND:
5019 case ISD::ZERO_EXTEND:
5020 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
5021 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
5026 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
5027 if (!Subtarget->allowsUnalignedMem())
5030 switch (VT.getSimpleVT().SimpleTy) {
5037 // FIXME: VLD1 etc with standard alignment is legal.
5041 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
5046 switch (VT.getSimpleVT().SimpleTy) {
5047 default: return false;
5062 if ((V & (Scale - 1)) != 0)
5065 return V == (V & ((1LL << 5) - 1));
5068 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
5069 const ARMSubtarget *Subtarget) {
5076 switch (VT.getSimpleVT().SimpleTy) {
5077 default: return false;
5082 // + imm12 or - imm8
5084 return V == (V & ((1LL << 8) - 1));
5085 return V == (V & ((1LL << 12) - 1));
5088 // Same as ARM mode. FIXME: NEON?
5089 if (!Subtarget->hasVFP2())
5094 return V == (V & ((1LL << 8) - 1));
5098 /// isLegalAddressImmediate - Return true if the integer value can be used
5099 /// as the offset of the target addressing mode for load / store of the
5101 static bool isLegalAddressImmediate(int64_t V, EVT VT,
5102 const ARMSubtarget *Subtarget) {
5109 if (Subtarget->isThumb1Only())
5110 return isLegalT1AddressImmediate(V, VT);
5111 else if (Subtarget->isThumb2())
5112 return isLegalT2AddressImmediate(V, VT, Subtarget);
5117 switch (VT.getSimpleVT().SimpleTy) {
5118 default: return false;
5123 return V == (V & ((1LL << 12) - 1));
5126 return V == (V & ((1LL << 8) - 1));
5129 if (!Subtarget->hasVFP2()) // FIXME: NEON?
5134 return V == (V & ((1LL << 8) - 1));
5138 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
5140 int Scale = AM.Scale;
5144 switch (VT.getSimpleVT().SimpleTy) {
5145 default: return false;
5154 return Scale == 2 || Scale == 4 || Scale == 8;
5157 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
5161 // Note, we allow "void" uses (basically, uses that aren't loads or
5162 // stores), because arm allows folding a scale into many arithmetic
5163 // operations. This should be made more precise and revisited later.
5165 // Allow r << imm, but the imm has to be a multiple of two.
5166 if (Scale & 1) return false;
5167 return isPowerOf2_32(Scale);
5171 /// isLegalAddressingMode - Return true if the addressing mode represented
5172 /// by AM is legal for this target, for a load/store of the specified type.
5173 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
5174 const Type *Ty) const {
5175 EVT VT = getValueType(Ty, true);
5176 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
5179 // Can never fold addr of global into load/store.
5184 case 0: // no scale reg, must be "r+i" or "r", or "i".
5187 if (Subtarget->isThumb1Only())
5191 // ARM doesn't support any R+R*scale+imm addr modes.
5198 if (Subtarget->isThumb2())
5199 return isLegalT2ScaledAddressingMode(AM, VT);
5201 int Scale = AM.Scale;
5202 switch (VT.getSimpleVT().SimpleTy) {
5203 default: return false;
5207 if (Scale < 0) Scale = -Scale;
5211 return isPowerOf2_32(Scale & ~1);
5215 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
5220 // Note, we allow "void" uses (basically, uses that aren't loads or
5221 // stores), because arm allows folding a scale into many arithmetic
5222 // operations. This should be made more precise and revisited later.
5224 // Allow r << imm, but the imm has to be a multiple of two.
5225 if (Scale & 1) return false;
5226 return isPowerOf2_32(Scale);
5233 /// isLegalICmpImmediate - Return true if the specified immediate is legal
5234 /// icmp immediate, that is the target has icmp instructions which can compare
5235 /// a register against the immediate without having to materialize the
5236 /// immediate into a register.
5237 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
5238 if (!Subtarget->isThumb())
5239 return ARM_AM::getSOImmVal(Imm) != -1;
5240 if (Subtarget->isThumb2())
5241 return ARM_AM::getT2SOImmVal(Imm) != -1;
5242 return Imm >= 0 && Imm <= 255;
5245 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
5246 bool isSEXTLoad, SDValue &Base,
5247 SDValue &Offset, bool &isInc,
5248 SelectionDAG &DAG) {
5249 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
5252 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
5254 Base = Ptr->getOperand(0);
5255 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
5256 int RHSC = (int)RHS->getZExtValue();
5257 if (RHSC < 0 && RHSC > -256) {
5258 assert(Ptr->getOpcode() == ISD::ADD);
5260 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
5264 isInc = (Ptr->getOpcode() == ISD::ADD);
5265 Offset = Ptr->getOperand(1);
5267 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
5269 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
5270 int RHSC = (int)RHS->getZExtValue();
5271 if (RHSC < 0 && RHSC > -0x1000) {
5272 assert(Ptr->getOpcode() == ISD::ADD);
5274 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
5275 Base = Ptr->getOperand(0);
5280 if (Ptr->getOpcode() == ISD::ADD) {
5282 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
5283 if (ShOpcVal != ARM_AM::no_shift) {
5284 Base = Ptr->getOperand(1);
5285 Offset = Ptr->getOperand(0);
5287 Base = Ptr->getOperand(0);
5288 Offset = Ptr->getOperand(1);
5293 isInc = (Ptr->getOpcode() == ISD::ADD);
5294 Base = Ptr->getOperand(0);
5295 Offset = Ptr->getOperand(1);
5299 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
5303 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
5304 bool isSEXTLoad, SDValue &Base,
5305 SDValue &Offset, bool &isInc,
5306 SelectionDAG &DAG) {
5307 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
5310 Base = Ptr->getOperand(0);
5311 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
5312 int RHSC = (int)RHS->getZExtValue();
5313 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
5314 assert(Ptr->getOpcode() == ISD::ADD);
5316 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
5318 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
5319 isInc = Ptr->getOpcode() == ISD::ADD;
5320 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
5328 /// getPreIndexedAddressParts - returns true by value, base pointer and
5329 /// offset pointer and addressing mode by reference if the node's address
5330 /// can be legally represented as pre-indexed load / store address.
5332 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
5334 ISD::MemIndexedMode &AM,
5335 SelectionDAG &DAG) const {
5336 if (Subtarget->isThumb1Only())
5341 bool isSEXTLoad = false;
5342 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5343 Ptr = LD->getBasePtr();
5344 VT = LD->getMemoryVT();
5345 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
5346 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5347 Ptr = ST->getBasePtr();
5348 VT = ST->getMemoryVT();
5353 bool isLegal = false;
5354 if (Subtarget->isThumb2())
5355 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
5356 Offset, isInc, DAG);
5358 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
5359 Offset, isInc, DAG);
5363 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
5367 /// getPostIndexedAddressParts - returns true by value, base pointer and
5368 /// offset pointer and addressing mode by reference if this node can be
5369 /// combined with a load / store to form a post-indexed load / store.
5370 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
5373 ISD::MemIndexedMode &AM,
5374 SelectionDAG &DAG) const {
5375 if (Subtarget->isThumb1Only())
5380 bool isSEXTLoad = false;
5381 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5382 VT = LD->getMemoryVT();
5383 Ptr = LD->getBasePtr();
5384 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
5385 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5386 VT = ST->getMemoryVT();
5387 Ptr = ST->getBasePtr();
5392 bool isLegal = false;
5393 if (Subtarget->isThumb2())
5394 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
5397 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
5403 // Swap base ptr and offset to catch more post-index load / store when
5404 // it's legal. In Thumb2 mode, offset must be an immediate.
5405 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
5406 !Subtarget->isThumb2())
5407 std::swap(Base, Offset);
5409 // Post-indexed load / store update the base pointer.
5414 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
5418 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
5422 const SelectionDAG &DAG,
5423 unsigned Depth) const {
5424 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
5425 switch (Op.getOpcode()) {
5427 case ARMISD::CMOV: {
5428 // Bits are known zero/one if known on the LHS and RHS.
5429 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
5430 if (KnownZero == 0 && KnownOne == 0) return;
5432 APInt KnownZeroRHS, KnownOneRHS;
5433 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
5434 KnownZeroRHS, KnownOneRHS, Depth+1);
5435 KnownZero &= KnownZeroRHS;
5436 KnownOne &= KnownOneRHS;
5442 //===----------------------------------------------------------------------===//
5443 // ARM Inline Assembly Support
5444 //===----------------------------------------------------------------------===//
5446 /// getConstraintType - Given a constraint letter, return the type of
5447 /// constraint it is for this target.
5448 ARMTargetLowering::ConstraintType
5449 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
5450 if (Constraint.size() == 1) {
5451 switch (Constraint[0]) {
5453 case 'l': return C_RegisterClass;
5454 case 'w': return C_RegisterClass;
5457 return TargetLowering::getConstraintType(Constraint);
5460 /// Examine constraint type and operand type and determine a weight value.
5461 /// This object must already have been set up with the operand type
5462 /// and the current alternative constraint selected.
5463 TargetLowering::ConstraintWeight
5464 ARMTargetLowering::getSingleConstraintMatchWeight(
5465 AsmOperandInfo &info, const char *constraint) const {
5466 ConstraintWeight weight = CW_Invalid;
5467 Value *CallOperandVal = info.CallOperandVal;
5468 // If we don't have a value, we can't do a match,
5469 // but allow it at the lowest weight.
5470 if (CallOperandVal == NULL)
5472 const Type *type = CallOperandVal->getType();
5473 // Look at the constraint type.
5474 switch (*constraint) {
5476 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
5479 if (type->isIntegerTy()) {
5480 if (Subtarget->isThumb())
5481 weight = CW_SpecificReg;
5483 weight = CW_Register;
5487 if (type->isFloatingPointTy())
5488 weight = CW_Register;
5494 std::pair<unsigned, const TargetRegisterClass*>
5495 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
5497 if (Constraint.size() == 1) {
5498 // GCC ARM Constraint Letters
5499 switch (Constraint[0]) {
5501 if (Subtarget->isThumb())
5502 return std::make_pair(0U, ARM::tGPRRegisterClass);
5504 return std::make_pair(0U, ARM::GPRRegisterClass);
5506 return std::make_pair(0U, ARM::GPRRegisterClass);
5509 return std::make_pair(0U, ARM::SPRRegisterClass);
5510 if (VT.getSizeInBits() == 64)
5511 return std::make_pair(0U, ARM::DPRRegisterClass);
5512 if (VT.getSizeInBits() == 128)
5513 return std::make_pair(0U, ARM::QPRRegisterClass);
5517 if (StringRef("{cc}").equals_lower(Constraint))
5518 return std::make_pair(unsigned(ARM::CPSR), ARM::CCRRegisterClass);
5520 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
5523 std::vector<unsigned> ARMTargetLowering::
5524 getRegClassForInlineAsmConstraint(const std::string &Constraint,
5526 if (Constraint.size() != 1)
5527 return std::vector<unsigned>();
5529 switch (Constraint[0]) { // GCC ARM Constraint Letters
5532 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
5533 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
5536 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
5537 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
5538 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
5539 ARM::R12, ARM::LR, 0);
5542 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
5543 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
5544 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
5545 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
5546 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
5547 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
5548 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
5549 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
5550 if (VT.getSizeInBits() == 64)
5551 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
5552 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
5553 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
5554 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
5555 if (VT.getSizeInBits() == 128)
5556 return make_vector<unsigned>(ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
5557 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 0);
5561 return std::vector<unsigned>();
5564 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
5565 /// vector. If it is invalid, don't add anything to Ops.
5566 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
5568 std::vector<SDValue>&Ops,
5569 SelectionDAG &DAG) const {
5570 SDValue Result(0, 0);
5572 switch (Constraint) {
5574 case 'I': case 'J': case 'K': case 'L':
5575 case 'M': case 'N': case 'O':
5576 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
5580 int64_t CVal64 = C->getSExtValue();
5581 int CVal = (int) CVal64;
5582 // None of these constraints allow values larger than 32 bits. Check
5583 // that the value fits in an int.
5587 switch (Constraint) {
5589 if (Subtarget->isThumb1Only()) {
5590 // This must be a constant between 0 and 255, for ADD
5592 if (CVal >= 0 && CVal <= 255)
5594 } else if (Subtarget->isThumb2()) {
5595 // A constant that can be used as an immediate value in a
5596 // data-processing instruction.
5597 if (ARM_AM::getT2SOImmVal(CVal) != -1)
5600 // A constant that can be used as an immediate value in a
5601 // data-processing instruction.
5602 if (ARM_AM::getSOImmVal(CVal) != -1)
5608 if (Subtarget->isThumb()) { // FIXME thumb2
5609 // This must be a constant between -255 and -1, for negated ADD
5610 // immediates. This can be used in GCC with an "n" modifier that
5611 // prints the negated value, for use with SUB instructions. It is
5612 // not useful otherwise but is implemented for compatibility.
5613 if (CVal >= -255 && CVal <= -1)
5616 // This must be a constant between -4095 and 4095. It is not clear
5617 // what this constraint is intended for. Implemented for
5618 // compatibility with GCC.
5619 if (CVal >= -4095 && CVal <= 4095)
5625 if (Subtarget->isThumb1Only()) {
5626 // A 32-bit value where only one byte has a nonzero value. Exclude
5627 // zero to match GCC. This constraint is used by GCC internally for
5628 // constants that can be loaded with a move/shift combination.
5629 // It is not useful otherwise but is implemented for compatibility.
5630 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
5632 } else if (Subtarget->isThumb2()) {
5633 // A constant whose bitwise inverse can be used as an immediate
5634 // value in a data-processing instruction. This can be used in GCC
5635 // with a "B" modifier that prints the inverted value, for use with
5636 // BIC and MVN instructions. It is not useful otherwise but is
5637 // implemented for compatibility.
5638 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
5641 // A constant whose bitwise inverse can be used as an immediate
5642 // value in a data-processing instruction. This can be used in GCC
5643 // with a "B" modifier that prints the inverted value, for use with
5644 // BIC and MVN instructions. It is not useful otherwise but is
5645 // implemented for compatibility.
5646 if (ARM_AM::getSOImmVal(~CVal) != -1)
5652 if (Subtarget->isThumb1Only()) {
5653 // This must be a constant between -7 and 7,
5654 // for 3-operand ADD/SUB immediate instructions.
5655 if (CVal >= -7 && CVal < 7)
5657 } else if (Subtarget->isThumb2()) {
5658 // A constant whose negation can be used as an immediate value in a
5659 // data-processing instruction. This can be used in GCC with an "n"
5660 // modifier that prints the negated value, for use with SUB
5661 // instructions. It is not useful otherwise but is implemented for
5663 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
5666 // A constant whose negation can be used as an immediate value in a
5667 // data-processing instruction. This can be used in GCC with an "n"
5668 // modifier that prints the negated value, for use with SUB
5669 // instructions. It is not useful otherwise but is implemented for
5671 if (ARM_AM::getSOImmVal(-CVal) != -1)
5677 if (Subtarget->isThumb()) { // FIXME thumb2
5678 // This must be a multiple of 4 between 0 and 1020, for
5679 // ADD sp + immediate.
5680 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
5683 // A power of two or a constant between 0 and 32. This is used in
5684 // GCC for the shift amount on shifted register operands, but it is
5685 // useful in general for any shift amounts.
5686 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
5692 if (Subtarget->isThumb()) { // FIXME thumb2
5693 // This must be a constant between 0 and 31, for shift amounts.
5694 if (CVal >= 0 && CVal <= 31)
5700 if (Subtarget->isThumb()) { // FIXME thumb2
5701 // This must be a multiple of 4 between -508 and 508, for
5702 // ADD/SUB sp = sp + immediate.
5703 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
5708 Result = DAG.getTargetConstant(CVal, Op.getValueType());
5712 if (Result.getNode()) {
5713 Ops.push_back(Result);
5716 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
5720 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
5721 // The ARM target isn't yet aware of offsets.
5725 int ARM::getVFPf32Imm(const APFloat &FPImm) {
5726 APInt Imm = FPImm.bitcastToAPInt();
5727 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
5728 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127
5729 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits
5731 // We can handle 4 bits of mantissa.
5732 // mantissa = (16+UInt(e:f:g:h))/16.
5733 if (Mantissa & 0x7ffff)
5736 if ((Mantissa & 0xf) != Mantissa)
5739 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
5740 if (Exp < -3 || Exp > 4)
5742 Exp = ((Exp+3) & 0x7) ^ 4;
5744 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
5747 int ARM::getVFPf64Imm(const APFloat &FPImm) {
5748 APInt Imm = FPImm.bitcastToAPInt();
5749 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
5750 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
5751 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffLL;
5753 // We can handle 4 bits of mantissa.
5754 // mantissa = (16+UInt(e:f:g:h))/16.
5755 if (Mantissa & 0xffffffffffffLL)
5758 if ((Mantissa & 0xf) != Mantissa)
5761 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
5762 if (Exp < -3 || Exp > 4)
5764 Exp = ((Exp+3) & 0x7) ^ 4;
5766 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
5769 bool ARM::isBitFieldInvertedMask(unsigned v) {
5770 if (v == 0xffffffff)
5772 // there can be 1's on either or both "outsides", all the "inside"
5774 unsigned int lsb = 0, msb = 31;
5775 while (v & (1 << msb)) --msb;
5776 while (v & (1 << lsb)) ++lsb;
5777 for (unsigned int i = lsb; i <= msb; ++i) {
5784 /// isFPImmLegal - Returns true if the target can instruction select the
5785 /// specified FP immediate natively. If false, the legalizer will
5786 /// materialize the FP immediate as a load from a constant pool.
5787 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
5788 if (!Subtarget->hasVFP3())
5791 return ARM::getVFPf32Imm(Imm) != -1;
5793 return ARM::getVFPf64Imm(Imm) != -1;
5797 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
5798 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
5799 /// specified in the intrinsic calls.
5800 bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
5802 unsigned Intrinsic) const {
5803 switch (Intrinsic) {
5804 case Intrinsic::arm_neon_vld1:
5805 case Intrinsic::arm_neon_vld2:
5806 case Intrinsic::arm_neon_vld3:
5807 case Intrinsic::arm_neon_vld4:
5808 case Intrinsic::arm_neon_vld2lane:
5809 case Intrinsic::arm_neon_vld3lane:
5810 case Intrinsic::arm_neon_vld4lane: {
5811 Info.opc = ISD::INTRINSIC_W_CHAIN;
5812 // Conservatively set memVT to the entire set of vectors loaded.
5813 uint64_t NumElts = getTargetData()->getTypeAllocSize(I.getType()) / 8;
5814 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
5815 Info.ptrVal = I.getArgOperand(0);
5817 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
5818 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
5819 Info.vol = false; // volatile loads with NEON intrinsics not supported
5820 Info.readMem = true;
5821 Info.writeMem = false;
5824 case Intrinsic::arm_neon_vst1:
5825 case Intrinsic::arm_neon_vst2:
5826 case Intrinsic::arm_neon_vst3:
5827 case Intrinsic::arm_neon_vst4:
5828 case Intrinsic::arm_neon_vst2lane:
5829 case Intrinsic::arm_neon_vst3lane:
5830 case Intrinsic::arm_neon_vst4lane: {
5831 Info.opc = ISD::INTRINSIC_VOID;
5832 // Conservatively set memVT to the entire set of vectors stored.
5833 unsigned NumElts = 0;
5834 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
5835 const Type *ArgTy = I.getArgOperand(ArgI)->getType();
5836 if (!ArgTy->isVectorTy())
5838 NumElts += getTargetData()->getTypeAllocSize(ArgTy) / 8;
5840 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
5841 Info.ptrVal = I.getArgOperand(0);
5843 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
5844 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
5845 Info.vol = false; // volatile stores with NEON intrinsics not supported
5846 Info.readMem = false;
5847 Info.writeMem = true;