1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "ARMAddressingModes.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMISelLowering.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMPerfectShuffle.h"
21 #include "ARMRegisterInfo.h"
22 #include "ARMSubtarget.h"
23 #include "ARMTargetMachine.h"
24 #include "ARMTargetObjectFile.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/Constants.h"
27 #include "llvm/Function.h"
28 #include "llvm/GlobalValue.h"
29 #include "llvm/Instruction.h"
30 #include "llvm/Intrinsics.h"
31 #include "llvm/Type.h"
32 #include "llvm/CodeGen/CallingConvLower.h"
33 #include "llvm/CodeGen/MachineBasicBlock.h"
34 #include "llvm/CodeGen/MachineFrameInfo.h"
35 #include "llvm/CodeGen/MachineFunction.h"
36 #include "llvm/CodeGen/MachineInstrBuilder.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/PseudoSourceValue.h"
39 #include "llvm/CodeGen/SelectionDAG.h"
40 #include "llvm/Target/TargetOptions.h"
41 #include "llvm/ADT/VectorExtras.h"
42 #include "llvm/Support/ErrorHandling.h"
43 #include "llvm/Support/MathExtras.h"
47 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
48 CCValAssign::LocInfo &LocInfo,
49 ISD::ArgFlagsTy &ArgFlags,
51 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
52 CCValAssign::LocInfo &LocInfo,
53 ISD::ArgFlagsTy &ArgFlags,
55 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
56 CCValAssign::LocInfo &LocInfo,
57 ISD::ArgFlagsTy &ArgFlags,
59 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
60 CCValAssign::LocInfo &LocInfo,
61 ISD::ArgFlagsTy &ArgFlags,
64 void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
65 EVT PromotedBitwiseVT) {
66 if (VT != PromotedLdStVT) {
67 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
68 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
69 PromotedLdStVT.getSimpleVT());
71 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
72 AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
73 PromotedLdStVT.getSimpleVT());
76 EVT ElemTy = VT.getVectorElementType();
77 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
78 setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
79 if (ElemTy == MVT::i8 || ElemTy == MVT::i16)
80 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
81 if (ElemTy != MVT::i32) {
82 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
83 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand);
84 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand);
85 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand);
87 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
88 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
89 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Custom);
90 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Expand);
92 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
93 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
94 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
97 // Promote all bit-wise operations.
98 if (VT.isInteger() && VT != PromotedBitwiseVT) {
99 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
100 AddPromotedToType (ISD::AND, VT.getSimpleVT(),
101 PromotedBitwiseVT.getSimpleVT());
102 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
103 AddPromotedToType (ISD::OR, VT.getSimpleVT(),
104 PromotedBitwiseVT.getSimpleVT());
105 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
106 AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
107 PromotedBitwiseVT.getSimpleVT());
110 // Neon does not support vector divide/remainder operations.
111 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
112 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
113 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand);
114 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
115 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
116 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
119 void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
120 addRegisterClass(VT, ARM::DPRRegisterClass);
121 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
124 void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
125 addRegisterClass(VT, ARM::QPRRegisterClass);
126 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
129 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
130 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
131 return new TargetLoweringObjectFileMachO();
132 return new ARMElfTargetObjectFile();
135 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
136 : TargetLowering(TM, createTLOF(TM)) {
137 Subtarget = &TM.getSubtarget<ARMSubtarget>();
139 if (Subtarget->isTargetDarwin()) {
140 // Uses VFP for Thumb libfuncs if available.
141 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
142 // Single-precision floating-point arithmetic.
143 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
144 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
145 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
146 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
148 // Double-precision floating-point arithmetic.
149 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
150 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
151 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
152 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
154 // Single-precision comparisons.
155 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
156 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
157 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
158 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
159 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
160 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
161 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
162 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
164 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
165 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
166 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
167 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
168 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
169 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
170 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
171 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
173 // Double-precision comparisons.
174 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
175 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
176 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
177 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
178 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
179 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
180 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
181 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
183 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
184 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
185 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
186 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
187 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
188 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
189 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
190 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
192 // Floating-point to integer conversions.
193 // i64 conversions are done via library routines even when generating VFP
194 // instructions, so use the same ones.
195 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
196 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
197 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
198 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
200 // Conversions between floating types.
201 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
202 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
204 // Integer to floating-point conversions.
205 // i64 conversions are done via library routines even when generating VFP
206 // instructions, so use the same ones.
207 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
208 // e.g., __floatunsidf vs. __floatunssidfvfp.
209 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
210 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
211 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
212 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
216 // These libcalls are not available in 32-bit.
217 setLibcallName(RTLIB::SHL_I128, 0);
218 setLibcallName(RTLIB::SRL_I128, 0);
219 setLibcallName(RTLIB::SRA_I128, 0);
221 // Libcalls should use the AAPCS base standard ABI, even if hard float
222 // is in effect, as per the ARM RTABI specification, section 4.1.2.
223 if (Subtarget->isAAPCS_ABI()) {
224 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
225 setLibcallCallingConv(static_cast<RTLIB::Libcall>(i),
226 CallingConv::ARM_AAPCS);
230 if (Subtarget->isThumb1Only())
231 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
233 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
234 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
235 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
236 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
238 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
241 if (Subtarget->hasNEON()) {
242 addDRTypeForNEON(MVT::v2f32);
243 addDRTypeForNEON(MVT::v8i8);
244 addDRTypeForNEON(MVT::v4i16);
245 addDRTypeForNEON(MVT::v2i32);
246 addDRTypeForNEON(MVT::v1i64);
248 addQRTypeForNEON(MVT::v4f32);
249 addQRTypeForNEON(MVT::v2f64);
250 addQRTypeForNEON(MVT::v16i8);
251 addQRTypeForNEON(MVT::v8i16);
252 addQRTypeForNEON(MVT::v4i32);
253 addQRTypeForNEON(MVT::v2i64);
255 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
256 // neither Neon nor VFP support any arithmetic operations on it.
257 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
258 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
259 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
260 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
261 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
262 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
263 setOperationAction(ISD::VSETCC, MVT::v2f64, Expand);
264 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
265 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
266 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
267 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
268 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
269 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
270 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
271 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
272 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
273 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
274 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
275 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
276 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
277 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
278 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
279 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
280 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
282 // Neon does not support some operations on v1i64 and v2i64 types.
283 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
284 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
285 setOperationAction(ISD::VSETCC, MVT::v1i64, Expand);
286 setOperationAction(ISD::VSETCC, MVT::v2i64, Expand);
288 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
289 setTargetDAGCombine(ISD::SHL);
290 setTargetDAGCombine(ISD::SRL);
291 setTargetDAGCombine(ISD::SRA);
292 setTargetDAGCombine(ISD::SIGN_EXTEND);
293 setTargetDAGCombine(ISD::ZERO_EXTEND);
294 setTargetDAGCombine(ISD::ANY_EXTEND);
297 computeRegisterProperties();
299 // ARM does not have f32 extending load.
300 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
302 // ARM does not have i1 sign extending load.
303 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
305 // ARM supports all 4 flavors of integer indexed load / store.
306 if (!Subtarget->isThumb1Only()) {
307 for (unsigned im = (unsigned)ISD::PRE_INC;
308 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
309 setIndexedLoadAction(im, MVT::i1, Legal);
310 setIndexedLoadAction(im, MVT::i8, Legal);
311 setIndexedLoadAction(im, MVT::i16, Legal);
312 setIndexedLoadAction(im, MVT::i32, Legal);
313 setIndexedStoreAction(im, MVT::i1, Legal);
314 setIndexedStoreAction(im, MVT::i8, Legal);
315 setIndexedStoreAction(im, MVT::i16, Legal);
316 setIndexedStoreAction(im, MVT::i32, Legal);
320 // i64 operation support.
321 if (Subtarget->isThumb1Only()) {
322 setOperationAction(ISD::MUL, MVT::i64, Expand);
323 setOperationAction(ISD::MULHU, MVT::i32, Expand);
324 setOperationAction(ISD::MULHS, MVT::i32, Expand);
325 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
326 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
328 setOperationAction(ISD::MUL, MVT::i64, Expand);
329 setOperationAction(ISD::MULHU, MVT::i32, Expand);
330 if (!Subtarget->hasV6Ops())
331 setOperationAction(ISD::MULHS, MVT::i32, Expand);
333 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
334 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
335 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
336 setOperationAction(ISD::SRL, MVT::i64, Custom);
337 setOperationAction(ISD::SRA, MVT::i64, Custom);
339 // ARM does not have ROTL.
340 setOperationAction(ISD::ROTL, MVT::i32, Expand);
341 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
342 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
343 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
344 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
346 // Only ARMv6 has BSWAP.
347 if (!Subtarget->hasV6Ops())
348 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
350 // These are expanded into libcalls.
351 setOperationAction(ISD::SDIV, MVT::i32, Expand);
352 setOperationAction(ISD::UDIV, MVT::i32, Expand);
353 setOperationAction(ISD::SREM, MVT::i32, Expand);
354 setOperationAction(ISD::UREM, MVT::i32, Expand);
355 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
356 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
358 // Support label based line numbers.
359 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
361 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
362 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
363 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
364 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
365 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
367 // Use the default implementation.
368 setOperationAction(ISD::VASTART, MVT::Other, Custom);
369 setOperationAction(ISD::VAARG, MVT::Other, Expand);
370 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
371 setOperationAction(ISD::VAEND, MVT::Other, Expand);
372 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
373 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
374 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
375 // FIXME: Shouldn't need this, since no register is used, but the legalizer
376 // doesn't yet know how to not do that for SjLj.
377 setExceptionSelectorRegister(ARM::R0);
378 if (Subtarget->isThumb())
379 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
381 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
382 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
384 if (!Subtarget->hasV6Ops() && !Subtarget->isThumb2()) {
385 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
386 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
388 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
390 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only())
391 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR iff target supports vfp2.
392 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
394 // We want to custom lower some of our intrinsics.
395 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
397 setOperationAction(ISD::SETCC, MVT::i32, Expand);
398 setOperationAction(ISD::SETCC, MVT::f32, Expand);
399 setOperationAction(ISD::SETCC, MVT::f64, Expand);
400 setOperationAction(ISD::SELECT, MVT::i32, Expand);
401 setOperationAction(ISD::SELECT, MVT::f32, Expand);
402 setOperationAction(ISD::SELECT, MVT::f64, Expand);
403 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
404 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
405 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
407 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
408 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
409 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
410 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
411 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
413 // We don't support sin/cos/fmod/copysign/pow
414 setOperationAction(ISD::FSIN, MVT::f64, Expand);
415 setOperationAction(ISD::FSIN, MVT::f32, Expand);
416 setOperationAction(ISD::FCOS, MVT::f32, Expand);
417 setOperationAction(ISD::FCOS, MVT::f64, Expand);
418 setOperationAction(ISD::FREM, MVT::f64, Expand);
419 setOperationAction(ISD::FREM, MVT::f32, Expand);
420 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
421 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
422 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
424 setOperationAction(ISD::FPOW, MVT::f64, Expand);
425 setOperationAction(ISD::FPOW, MVT::f32, Expand);
427 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
428 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
429 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
430 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
431 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
432 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
435 // We have target-specific dag combine patterns for the following nodes:
436 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
437 setTargetDAGCombine(ISD::ADD);
438 setTargetDAGCombine(ISD::SUB);
440 setStackPointerRegisterToSaveRestore(ARM::SP);
441 setSchedulingPreference(SchedulingForRegPressure);
443 // FIXME: If-converter should use instruction latency to determine
444 // profitability rather than relying on fixed limits.
445 if (Subtarget->getCPUString() == "generic") {
446 // Generic (and overly aggressive) if-conversion limits.
447 setIfCvtBlockSizeLimit(10);
448 setIfCvtDupBlockSizeLimit(2);
449 } else if (Subtarget->hasV6Ops()) {
450 setIfCvtBlockSizeLimit(2);
451 setIfCvtDupBlockSizeLimit(1);
453 setIfCvtBlockSizeLimit(3);
454 setIfCvtDupBlockSizeLimit(2);
457 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
458 // Do not enable CodePlacementOpt for now: it currently runs after the
459 // ARMConstantIslandPass and messes up branch relaxation and placement
460 // of constant islands.
461 // benefitFromCodePlacementOpt = true;
464 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
467 case ARMISD::Wrapper: return "ARMISD::Wrapper";
468 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
469 case ARMISD::CALL: return "ARMISD::CALL";
470 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
471 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
472 case ARMISD::tCALL: return "ARMISD::tCALL";
473 case ARMISD::BRCOND: return "ARMISD::BRCOND";
474 case ARMISD::BR_JT: return "ARMISD::BR_JT";
475 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
476 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
477 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
478 case ARMISD::CMP: return "ARMISD::CMP";
479 case ARMISD::CMPZ: return "ARMISD::CMPZ";
480 case ARMISD::CMPFP: return "ARMISD::CMPFP";
481 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
482 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
483 case ARMISD::CMOV: return "ARMISD::CMOV";
484 case ARMISD::CNEG: return "ARMISD::CNEG";
486 case ARMISD::FTOSI: return "ARMISD::FTOSI";
487 case ARMISD::FTOUI: return "ARMISD::FTOUI";
488 case ARMISD::SITOF: return "ARMISD::SITOF";
489 case ARMISD::UITOF: return "ARMISD::UITOF";
491 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
492 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
493 case ARMISD::RRX: return "ARMISD::RRX";
495 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
496 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
498 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
499 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
501 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
503 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
505 case ARMISD::VCEQ: return "ARMISD::VCEQ";
506 case ARMISD::VCGE: return "ARMISD::VCGE";
507 case ARMISD::VCGEU: return "ARMISD::VCGEU";
508 case ARMISD::VCGT: return "ARMISD::VCGT";
509 case ARMISD::VCGTU: return "ARMISD::VCGTU";
510 case ARMISD::VTST: return "ARMISD::VTST";
512 case ARMISD::VSHL: return "ARMISD::VSHL";
513 case ARMISD::VSHRs: return "ARMISD::VSHRs";
514 case ARMISD::VSHRu: return "ARMISD::VSHRu";
515 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
516 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
517 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
518 case ARMISD::VSHRN: return "ARMISD::VSHRN";
519 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
520 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
521 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
522 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
523 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
524 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
525 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
526 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
527 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
528 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
529 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
530 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
531 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
532 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
533 case ARMISD::VDUP: return "ARMISD::VDUP";
534 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
535 case ARMISD::VEXT: return "ARMISD::VEXT";
536 case ARMISD::VREV64: return "ARMISD::VREV64";
537 case ARMISD::VREV32: return "ARMISD::VREV32";
538 case ARMISD::VREV16: return "ARMISD::VREV16";
539 case ARMISD::VZIP: return "ARMISD::VZIP";
540 case ARMISD::VUZP: return "ARMISD::VUZP";
541 case ARMISD::VTRN: return "ARMISD::VTRN";
545 /// getFunctionAlignment - Return the Log2 alignment of this function.
546 unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
547 return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 0 : 1;
550 //===----------------------------------------------------------------------===//
552 //===----------------------------------------------------------------------===//
554 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
555 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
557 default: llvm_unreachable("Unknown condition code!");
558 case ISD::SETNE: return ARMCC::NE;
559 case ISD::SETEQ: return ARMCC::EQ;
560 case ISD::SETGT: return ARMCC::GT;
561 case ISD::SETGE: return ARMCC::GE;
562 case ISD::SETLT: return ARMCC::LT;
563 case ISD::SETLE: return ARMCC::LE;
564 case ISD::SETUGT: return ARMCC::HI;
565 case ISD::SETUGE: return ARMCC::HS;
566 case ISD::SETULT: return ARMCC::LO;
567 case ISD::SETULE: return ARMCC::LS;
571 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
572 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
573 ARMCC::CondCodes &CondCode2) {
574 CondCode2 = ARMCC::AL;
576 default: llvm_unreachable("Unknown FP condition!");
578 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
580 case ISD::SETOGT: CondCode = ARMCC::GT; break;
582 case ISD::SETOGE: CondCode = ARMCC::GE; break;
583 case ISD::SETOLT: CondCode = ARMCC::MI; break;
584 case ISD::SETOLE: CondCode = ARMCC::LS; break;
585 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
586 case ISD::SETO: CondCode = ARMCC::VC; break;
587 case ISD::SETUO: CondCode = ARMCC::VS; break;
588 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
589 case ISD::SETUGT: CondCode = ARMCC::HI; break;
590 case ISD::SETUGE: CondCode = ARMCC::PL; break;
592 case ISD::SETULT: CondCode = ARMCC::LT; break;
594 case ISD::SETULE: CondCode = ARMCC::LE; break;
596 case ISD::SETUNE: CondCode = ARMCC::NE; break;
600 //===----------------------------------------------------------------------===//
601 // Calling Convention Implementation
602 //===----------------------------------------------------------------------===//
604 #include "ARMGenCallingConv.inc"
606 // APCS f64 is in register pairs, possibly split to stack
607 static bool f64AssignAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
608 CCValAssign::LocInfo &LocInfo,
609 CCState &State, bool CanFail) {
610 static const unsigned RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
612 // Try to get the first register.
613 if (unsigned Reg = State.AllocateReg(RegList, 4))
614 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
616 // For the 2nd half of a v2f64, do not fail.
620 // Put the whole thing on the stack.
621 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
622 State.AllocateStack(8, 4),
627 // Try to get the second register.
628 if (unsigned Reg = State.AllocateReg(RegList, 4))
629 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
631 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
632 State.AllocateStack(4, 4),
637 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
638 CCValAssign::LocInfo &LocInfo,
639 ISD::ArgFlagsTy &ArgFlags,
641 if (!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
643 if (LocVT == MVT::v2f64 &&
644 !f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
646 return true; // we handled it
649 // AAPCS f64 is in aligned register pairs
650 static bool f64AssignAAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
651 CCValAssign::LocInfo &LocInfo,
652 CCState &State, bool CanFail) {
653 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
654 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
656 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
658 // For the 2nd half of a v2f64, do not just fail.
662 // Put the whole thing on the stack.
663 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
664 State.AllocateStack(8, 8),
670 for (i = 0; i < 2; ++i)
671 if (HiRegList[i] == Reg)
674 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
675 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
680 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
681 CCValAssign::LocInfo &LocInfo,
682 ISD::ArgFlagsTy &ArgFlags,
684 if (!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
686 if (LocVT == MVT::v2f64 &&
687 !f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
689 return true; // we handled it
692 static bool f64RetAssign(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
693 CCValAssign::LocInfo &LocInfo, CCState &State) {
694 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
695 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
697 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
699 return false; // we didn't handle it
702 for (i = 0; i < 2; ++i)
703 if (HiRegList[i] == Reg)
706 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
707 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
712 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
713 CCValAssign::LocInfo &LocInfo,
714 ISD::ArgFlagsTy &ArgFlags,
716 if (!f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
718 if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
720 return true; // we handled it
723 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
724 CCValAssign::LocInfo &LocInfo,
725 ISD::ArgFlagsTy &ArgFlags,
727 return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags,
731 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
732 /// given CallingConvention value.
733 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
735 bool isVarArg) const {
738 llvm_unreachable("Unsupported calling convention");
740 case CallingConv::Fast:
741 // Use target triple & subtarget features to do actual dispatch.
742 if (Subtarget->isAAPCS_ABI()) {
743 if (Subtarget->hasVFP2() &&
744 FloatABIType == FloatABI::Hard && !isVarArg)
745 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
747 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
749 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
750 case CallingConv::ARM_AAPCS_VFP:
751 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
752 case CallingConv::ARM_AAPCS:
753 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
754 case CallingConv::ARM_APCS:
755 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
759 /// LowerCallResult - Lower the result values of a call into the
760 /// appropriate copies out of appropriate physical registers.
762 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
763 CallingConv::ID CallConv, bool isVarArg,
764 const SmallVectorImpl<ISD::InputArg> &Ins,
765 DebugLoc dl, SelectionDAG &DAG,
766 SmallVectorImpl<SDValue> &InVals) {
768 // Assign locations to each value returned by this call.
769 SmallVector<CCValAssign, 16> RVLocs;
770 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
771 RVLocs, *DAG.getContext());
772 CCInfo.AnalyzeCallResult(Ins,
773 CCAssignFnForNode(CallConv, /* Return*/ true,
776 // Copy all of the result registers out of their specified physreg.
777 for (unsigned i = 0; i != RVLocs.size(); ++i) {
778 CCValAssign VA = RVLocs[i];
781 if (VA.needsCustom()) {
782 // Handle f64 or half of a v2f64.
783 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
785 Chain = Lo.getValue(1);
786 InFlag = Lo.getValue(2);
787 VA = RVLocs[++i]; // skip ahead to next loc
788 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
790 Chain = Hi.getValue(1);
791 InFlag = Hi.getValue(2);
792 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
794 if (VA.getLocVT() == MVT::v2f64) {
795 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
796 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
797 DAG.getConstant(0, MVT::i32));
799 VA = RVLocs[++i]; // skip ahead to next loc
800 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
801 Chain = Lo.getValue(1);
802 InFlag = Lo.getValue(2);
803 VA = RVLocs[++i]; // skip ahead to next loc
804 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
805 Chain = Hi.getValue(1);
806 InFlag = Hi.getValue(2);
807 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
808 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
809 DAG.getConstant(1, MVT::i32));
812 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
814 Chain = Val.getValue(1);
815 InFlag = Val.getValue(2);
818 switch (VA.getLocInfo()) {
819 default: llvm_unreachable("Unknown loc info!");
820 case CCValAssign::Full: break;
821 case CCValAssign::BCvt:
822 Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val);
826 InVals.push_back(Val);
832 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
833 /// by "Src" to address "Dst" of size "Size". Alignment information is
834 /// specified by the specific parameter attribute. The copy will be passed as
835 /// a byval function parameter.
836 /// Sometimes what we are copying is the end of a larger object, the part that
837 /// does not fit in registers.
839 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
840 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
842 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
843 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
844 /*AlwaysInline=*/false, NULL, 0, NULL, 0);
847 /// LowerMemOpCallTo - Store the argument to the stack.
849 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
850 SDValue StackPtr, SDValue Arg,
851 DebugLoc dl, SelectionDAG &DAG,
852 const CCValAssign &VA,
853 ISD::ArgFlagsTy Flags) {
854 unsigned LocMemOffset = VA.getLocMemOffset();
855 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
856 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
857 if (Flags.isByVal()) {
858 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
860 return DAG.getStore(Chain, dl, Arg, PtrOff,
861 PseudoSourceValue::getStack(), LocMemOffset);
864 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
865 SDValue Chain, SDValue &Arg,
866 RegsToPassVector &RegsToPass,
867 CCValAssign &VA, CCValAssign &NextVA,
869 SmallVector<SDValue, 8> &MemOpChains,
870 ISD::ArgFlagsTy Flags) {
872 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
873 DAG.getVTList(MVT::i32, MVT::i32), Arg);
874 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
876 if (NextVA.isRegLoc())
877 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
879 assert(NextVA.isMemLoc());
880 if (StackPtr.getNode() == 0)
881 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
883 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
889 /// LowerCall - Lowering a call into a callseq_start <-
890 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
893 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
894 CallingConv::ID CallConv, bool isVarArg,
896 const SmallVectorImpl<ISD::OutputArg> &Outs,
897 const SmallVectorImpl<ISD::InputArg> &Ins,
898 DebugLoc dl, SelectionDAG &DAG,
899 SmallVectorImpl<SDValue> &InVals) {
901 // Analyze operands of the call, assigning locations to each operand.
902 SmallVector<CCValAssign, 16> ArgLocs;
903 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
905 CCInfo.AnalyzeCallOperands(Outs,
906 CCAssignFnForNode(CallConv, /* Return*/ false,
909 // Get a count of how many bytes are to be pushed on the stack.
910 unsigned NumBytes = CCInfo.getNextStackOffset();
912 // Adjust the stack pointer for the new arguments...
913 // These operations are automatically eliminated by the prolog/epilog pass
914 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
916 SDValue StackPtr = DAG.getRegister(ARM::SP, MVT::i32);
918 RegsToPassVector RegsToPass;
919 SmallVector<SDValue, 8> MemOpChains;
921 // Walk the register/memloc assignments, inserting copies/loads. In the case
922 // of tail call optimization, arguments are handled later.
923 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
926 CCValAssign &VA = ArgLocs[i];
927 SDValue Arg = Outs[realArgIdx].Val;
928 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
930 // Promote the value if needed.
931 switch (VA.getLocInfo()) {
932 default: llvm_unreachable("Unknown loc info!");
933 case CCValAssign::Full: break;
934 case CCValAssign::SExt:
935 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
937 case CCValAssign::ZExt:
938 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
940 case CCValAssign::AExt:
941 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
943 case CCValAssign::BCvt:
944 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
948 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
949 if (VA.needsCustom()) {
950 if (VA.getLocVT() == MVT::v2f64) {
951 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
952 DAG.getConstant(0, MVT::i32));
953 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
954 DAG.getConstant(1, MVT::i32));
956 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
957 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
959 VA = ArgLocs[++i]; // skip ahead to next loc
961 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
962 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
964 assert(VA.isMemLoc());
965 if (StackPtr.getNode() == 0)
966 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
968 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
969 dl, DAG, VA, Flags));
972 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
973 StackPtr, MemOpChains, Flags);
975 } else if (VA.isRegLoc()) {
976 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
978 assert(VA.isMemLoc());
979 if (StackPtr.getNode() == 0)
980 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
982 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
983 dl, DAG, VA, Flags));
987 if (!MemOpChains.empty())
988 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
989 &MemOpChains[0], MemOpChains.size());
991 // Build a sequence of copy-to-reg nodes chained together with token chain
992 // and flag operands which copy the outgoing args into the appropriate regs.
994 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
995 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
996 RegsToPass[i].second, InFlag);
997 InFlag = Chain.getValue(1);
1000 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1001 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1002 // node so that legalize doesn't hack it.
1003 bool isDirect = false;
1004 bool isARMFunc = false;
1005 bool isLocalARMFunc = false;
1006 MachineFunction &MF = DAG.getMachineFunction();
1007 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1008 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1009 GlobalValue *GV = G->getGlobal();
1011 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1012 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
1013 getTargetMachine().getRelocationModel() != Reloc::Static;
1014 isARMFunc = !Subtarget->isThumb() || isStub;
1015 // ARM call to a local ARM function is predicable.
1016 isLocalARMFunc = !Subtarget->isThumb() && !isExt;
1017 // tBX takes a register source operand.
1018 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1019 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1020 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1023 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1024 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1025 Callee = DAG.getLoad(getPointerTy(), dl,
1026 DAG.getEntryNode(), CPAddr,
1027 PseudoSourceValue::getConstantPool(), 0);
1028 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1029 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1030 getPointerTy(), Callee, PICLabel);
1032 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy());
1033 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1035 bool isStub = Subtarget->isTargetDarwin() &&
1036 getTargetMachine().getRelocationModel() != Reloc::Static;
1037 isARMFunc = !Subtarget->isThumb() || isStub;
1038 // tBX takes a register source operand.
1039 const char *Sym = S->getSymbol();
1040 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1041 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1042 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1043 Sym, ARMPCLabelIndex, 4);
1044 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1045 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1046 Callee = DAG.getLoad(getPointerTy(), dl,
1047 DAG.getEntryNode(), CPAddr,
1048 PseudoSourceValue::getConstantPool(), 0);
1049 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1050 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1051 getPointerTy(), Callee, PICLabel);
1053 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
1056 // FIXME: handle tail calls differently.
1058 if (Subtarget->isThumb()) {
1059 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1060 CallOpc = ARMISD::CALL_NOLINK;
1062 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1064 CallOpc = (isDirect || Subtarget->hasV5TOps())
1065 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
1066 : ARMISD::CALL_NOLINK;
1068 if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb1Only()) {
1069 // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK
1070 Chain = DAG.getCopyToReg(Chain, dl, ARM::LR, DAG.getUNDEF(MVT::i32),InFlag);
1071 InFlag = Chain.getValue(1);
1074 std::vector<SDValue> Ops;
1075 Ops.push_back(Chain);
1076 Ops.push_back(Callee);
1078 // Add argument registers to the end of the list so that they are known live
1080 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1081 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1082 RegsToPass[i].second.getValueType()));
1084 if (InFlag.getNode())
1085 Ops.push_back(InFlag);
1086 // Returns a chain and a flag for retval copy to use.
1087 Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(MVT::Other, MVT::Flag),
1088 &Ops[0], Ops.size());
1089 InFlag = Chain.getValue(1);
1091 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1092 DAG.getIntPtrConstant(0, true), InFlag);
1094 InFlag = Chain.getValue(1);
1096 // Handle result values, copying them out of physregs into vregs that we
1098 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1103 ARMTargetLowering::LowerReturn(SDValue Chain,
1104 CallingConv::ID CallConv, bool isVarArg,
1105 const SmallVectorImpl<ISD::OutputArg> &Outs,
1106 DebugLoc dl, SelectionDAG &DAG) {
1108 // CCValAssign - represent the assignment of the return value to a location.
1109 SmallVector<CCValAssign, 16> RVLocs;
1111 // CCState - Info about the registers and stack slots.
1112 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
1115 // Analyze outgoing return values.
1116 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1119 // If this is the first return lowered for this function, add
1120 // the regs to the liveout set for the function.
1121 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1122 for (unsigned i = 0; i != RVLocs.size(); ++i)
1123 if (RVLocs[i].isRegLoc())
1124 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1129 // Copy the result values into the output registers.
1130 for (unsigned i = 0, realRVLocIdx = 0;
1132 ++i, ++realRVLocIdx) {
1133 CCValAssign &VA = RVLocs[i];
1134 assert(VA.isRegLoc() && "Can only return in registers!");
1136 SDValue Arg = Outs[realRVLocIdx].Val;
1138 switch (VA.getLocInfo()) {
1139 default: llvm_unreachable("Unknown loc info!");
1140 case CCValAssign::Full: break;
1141 case CCValAssign::BCvt:
1142 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1146 if (VA.needsCustom()) {
1147 if (VA.getLocVT() == MVT::v2f64) {
1148 // Extract the first half and return it in two registers.
1149 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1150 DAG.getConstant(0, MVT::i32));
1151 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
1152 DAG.getVTList(MVT::i32, MVT::i32), Half);
1154 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1155 Flag = Chain.getValue(1);
1156 VA = RVLocs[++i]; // skip ahead to next loc
1157 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1158 HalfGPRs.getValue(1), Flag);
1159 Flag = Chain.getValue(1);
1160 VA = RVLocs[++i]; // skip ahead to next loc
1162 // Extract the 2nd half and fall through to handle it as an f64 value.
1163 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1164 DAG.getConstant(1, MVT::i32));
1166 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1168 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1169 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1170 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1171 Flag = Chain.getValue(1);
1172 VA = RVLocs[++i]; // skip ahead to next loc
1173 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1176 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1178 // Guarantee that all emitted copies are
1179 // stuck together, avoiding something bad.
1180 Flag = Chain.getValue(1);
1185 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1187 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1192 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1193 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1194 // one of the above mentioned nodes. It has to be wrapped because otherwise
1195 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1196 // be used to form addressing mode. These wrapped nodes will be selected
1198 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1199 EVT PtrVT = Op.getValueType();
1200 // FIXME there is no actual debug info here
1201 DebugLoc dl = Op.getDebugLoc();
1202 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1204 if (CP->isMachineConstantPoolEntry())
1205 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1206 CP->getAlignment());
1208 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1209 CP->getAlignment());
1210 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1213 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) {
1214 MachineFunction &MF = DAG.getMachineFunction();
1215 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1216 unsigned ARMPCLabelIndex = 0;
1217 DebugLoc DL = Op.getDebugLoc();
1218 EVT PtrVT = getPointerTy();
1219 BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1220 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1222 if (RelocM == Reloc::Static) {
1223 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
1225 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1226 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1227 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(BA, ARMPCLabelIndex,
1228 ARMCP::CPBlockAddress,
1230 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1232 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
1233 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
1234 PseudoSourceValue::getConstantPool(), 0);
1235 if (RelocM == Reloc::Static)
1237 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1238 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
1241 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
1243 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1244 SelectionDAG &DAG) {
1245 DebugLoc dl = GA->getDebugLoc();
1246 EVT PtrVT = getPointerTy();
1247 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1248 MachineFunction &MF = DAG.getMachineFunction();
1249 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1250 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1251 ARMConstantPoolValue *CPV =
1252 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1253 ARMCP::CPValue, PCAdj, "tlsgd", true);
1254 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1255 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
1256 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
1257 PseudoSourceValue::getConstantPool(), 0);
1258 SDValue Chain = Argument.getValue(1);
1260 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1261 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
1263 // call __tls_get_addr.
1266 Entry.Node = Argument;
1267 Entry.Ty = (const Type *) Type::getInt32Ty(*DAG.getContext());
1268 Args.push_back(Entry);
1269 // FIXME: is there useful debug info available here?
1270 std::pair<SDValue, SDValue> CallResult =
1271 LowerCallTo(Chain, (const Type *) Type::getInt32Ty(*DAG.getContext()),
1272 false, false, false, false,
1273 0, CallingConv::C, false, /*isReturnValueUsed=*/true,
1274 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
1275 return CallResult.first;
1278 // Lower ISD::GlobalTLSAddress using the "initial exec" or
1279 // "local exec" model.
1281 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
1282 SelectionDAG &DAG) {
1283 GlobalValue *GV = GA->getGlobal();
1284 DebugLoc dl = GA->getDebugLoc();
1286 SDValue Chain = DAG.getEntryNode();
1287 EVT PtrVT = getPointerTy();
1288 // Get the Thread Pointer
1289 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1291 if (GV->isDeclaration()) {
1292 MachineFunction &MF = DAG.getMachineFunction();
1293 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1294 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1295 // Initial exec model.
1296 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1297 ARMConstantPoolValue *CPV =
1298 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1299 ARMCP::CPValue, PCAdj, "gottpoff", true);
1300 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1301 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1302 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1303 PseudoSourceValue::getConstantPool(), 0);
1304 Chain = Offset.getValue(1);
1306 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1307 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
1309 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1310 PseudoSourceValue::getConstantPool(), 0);
1313 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, "tpoff");
1314 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1315 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1316 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1317 PseudoSourceValue::getConstantPool(), 0);
1320 // The address of the thread local variable is the add of the thread
1321 // pointer with the offset of the variable.
1322 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
1326 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
1327 // TODO: implement the "local dynamic" model
1328 assert(Subtarget->isTargetELF() &&
1329 "TLS not implemented for non-ELF targets");
1330 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1331 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
1332 // otherwise use the "Local Exec" TLS Model
1333 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
1334 return LowerToTLSGeneralDynamicModel(GA, DAG);
1336 return LowerToTLSExecModels(GA, DAG);
1339 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
1340 SelectionDAG &DAG) {
1341 EVT PtrVT = getPointerTy();
1342 DebugLoc dl = Op.getDebugLoc();
1343 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1344 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1345 if (RelocM == Reloc::PIC_) {
1346 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
1347 ARMConstantPoolValue *CPV =
1348 new ARMConstantPoolValue(GV, UseGOTOFF ? "GOTOFF" : "GOT");
1349 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1350 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1351 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1353 PseudoSourceValue::getConstantPool(), 0);
1354 SDValue Chain = Result.getValue(1);
1355 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1356 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
1358 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
1359 PseudoSourceValue::getGOT(), 0);
1362 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1363 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1364 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1365 PseudoSourceValue::getConstantPool(), 0);
1369 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
1370 SelectionDAG &DAG) {
1371 MachineFunction &MF = DAG.getMachineFunction();
1372 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1373 unsigned ARMPCLabelIndex = 0;
1374 EVT PtrVT = getPointerTy();
1375 DebugLoc dl = Op.getDebugLoc();
1376 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1377 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1379 if (RelocM == Reloc::Static)
1380 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1382 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1383 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8);
1384 ARMConstantPoolValue *CPV =
1385 new ARMConstantPoolValue(GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj);
1386 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1388 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1390 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1391 PseudoSourceValue::getConstantPool(), 0);
1392 SDValue Chain = Result.getValue(1);
1394 if (RelocM == Reloc::PIC_) {
1395 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1396 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1399 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
1400 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
1401 PseudoSourceValue::getGOT(), 0);
1406 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
1408 assert(Subtarget->isTargetELF() &&
1409 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
1410 MachineFunction &MF = DAG.getMachineFunction();
1411 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1412 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1413 EVT PtrVT = getPointerTy();
1414 DebugLoc dl = Op.getDebugLoc();
1415 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1416 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1417 "_GLOBAL_OFFSET_TABLE_",
1418 ARMPCLabelIndex, PCAdj);
1419 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1420 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1421 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1422 PseudoSourceValue::getConstantPool(), 0);
1423 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1424 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1428 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
1429 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1430 DebugLoc dl = Op.getDebugLoc();
1432 default: return SDValue(); // Don't custom lower most intrinsics.
1433 case Intrinsic::arm_thread_pointer: {
1434 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1435 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1437 case Intrinsic::eh_sjlj_lsda: {
1438 MachineFunction &MF = DAG.getMachineFunction();
1439 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1440 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1441 EVT PtrVT = getPointerTy();
1442 DebugLoc dl = Op.getDebugLoc();
1443 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1445 unsigned PCAdj = (RelocM != Reloc::PIC_)
1446 ? 0 : (Subtarget->isThumb() ? 4 : 8);
1447 ARMConstantPoolValue *CPV =
1448 new ARMConstantPoolValue(MF.getFunction(), ARMPCLabelIndex,
1449 ARMCP::CPLSDA, PCAdj);
1450 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1451 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1453 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1454 PseudoSourceValue::getConstantPool(), 0);
1455 SDValue Chain = Result.getValue(1);
1457 if (RelocM == Reloc::PIC_) {
1458 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1459 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1463 case Intrinsic::eh_sjlj_setjmp:
1464 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(1));
1468 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
1469 unsigned VarArgsFrameIndex) {
1470 // vastart just stores the address of the VarArgsFrameIndex slot into the
1471 // memory location argument.
1472 DebugLoc dl = Op.getDebugLoc();
1473 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1474 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1475 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1476 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
1480 ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) {
1481 SDNode *Node = Op.getNode();
1482 DebugLoc dl = Node->getDebugLoc();
1483 EVT VT = Node->getValueType(0);
1484 SDValue Chain = Op.getOperand(0);
1485 SDValue Size = Op.getOperand(1);
1486 SDValue Align = Op.getOperand(2);
1488 // Chain the dynamic stack allocation so that it doesn't modify the stack
1489 // pointer when other instructions are using the stack.
1490 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1492 unsigned AlignVal = cast<ConstantSDNode>(Align)->getZExtValue();
1493 unsigned StackAlign = getTargetMachine().getFrameInfo()->getStackAlignment();
1494 if (AlignVal > StackAlign)
1495 // Do this now since selection pass cannot introduce new target
1496 // independent node.
1497 Align = DAG.getConstant(-(uint64_t)AlignVal, VT);
1499 // In Thumb1 mode, there isn't a "sub r, sp, r" instruction, we will end up
1500 // using a "add r, sp, r" instead. Negate the size now so we don't have to
1501 // do even more horrible hack later.
1502 MachineFunction &MF = DAG.getMachineFunction();
1503 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1504 if (AFI->isThumb1OnlyFunction()) {
1506 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Size);
1508 uint32_t Val = C->getZExtValue();
1509 if (Val <= 508 && ((Val & 3) == 0))
1513 Size = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, VT), Size);
1516 SDVTList VTList = DAG.getVTList(VT, MVT::Other);
1517 SDValue Ops1[] = { Chain, Size, Align };
1518 SDValue Res = DAG.getNode(ARMISD::DYN_ALLOC, dl, VTList, Ops1, 3);
1519 Chain = Res.getValue(1);
1520 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1521 DAG.getIntPtrConstant(0, true), SDValue());
1522 SDValue Ops2[] = { Res, Chain };
1523 return DAG.getMergeValues(Ops2, 2, dl);
1527 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
1528 SDValue &Root, SelectionDAG &DAG,
1530 MachineFunction &MF = DAG.getMachineFunction();
1531 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1533 TargetRegisterClass *RC;
1534 if (AFI->isThumb1OnlyFunction())
1535 RC = ARM::tGPRRegisterClass;
1537 RC = ARM::GPRRegisterClass;
1539 // Transform the arguments stored in physical registers into virtual ones.
1540 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1541 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
1544 if (NextVA.isMemLoc()) {
1545 unsigned ArgSize = NextVA.getLocVT().getSizeInBits()/8;
1546 MachineFrameInfo *MFI = MF.getFrameInfo();
1547 int FI = MFI->CreateFixedObject(ArgSize, NextVA.getLocMemOffset(),
1550 // Create load node to retrieve arguments from the stack.
1551 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1552 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
1553 PseudoSourceValue::getFixedStack(FI), 0);
1555 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
1556 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
1559 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
1563 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
1564 CallingConv::ID CallConv, bool isVarArg,
1565 const SmallVectorImpl<ISD::InputArg>
1567 DebugLoc dl, SelectionDAG &DAG,
1568 SmallVectorImpl<SDValue> &InVals) {
1570 MachineFunction &MF = DAG.getMachineFunction();
1571 MachineFrameInfo *MFI = MF.getFrameInfo();
1573 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1575 // Assign locations to all of the incoming arguments.
1576 SmallVector<CCValAssign, 16> ArgLocs;
1577 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1579 CCInfo.AnalyzeFormalArguments(Ins,
1580 CCAssignFnForNode(CallConv, /* Return*/ false,
1583 SmallVector<SDValue, 16> ArgValues;
1585 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1586 CCValAssign &VA = ArgLocs[i];
1588 // Arguments stored in registers.
1589 if (VA.isRegLoc()) {
1590 EVT RegVT = VA.getLocVT();
1593 if (VA.needsCustom()) {
1594 // f64 and vector types are split up into multiple registers or
1595 // combinations of registers and stack slots.
1598 if (VA.getLocVT() == MVT::v2f64) {
1599 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
1601 VA = ArgLocs[++i]; // skip ahead to next loc
1602 SDValue ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
1604 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1605 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
1606 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
1607 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
1608 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
1610 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
1613 TargetRegisterClass *RC;
1615 if (RegVT == MVT::f32)
1616 RC = ARM::SPRRegisterClass;
1617 else if (RegVT == MVT::f64)
1618 RC = ARM::DPRRegisterClass;
1619 else if (RegVT == MVT::v2f64)
1620 RC = ARM::QPRRegisterClass;
1621 else if (RegVT == MVT::i32)
1622 RC = (AFI->isThumb1OnlyFunction() ?
1623 ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
1625 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
1627 // Transform the arguments in physical registers into virtual ones.
1628 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1629 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1632 // If this is an 8 or 16-bit value, it is really passed promoted
1633 // to 32 bits. Insert an assert[sz]ext to capture this, then
1634 // truncate to the right size.
1635 switch (VA.getLocInfo()) {
1636 default: llvm_unreachable("Unknown loc info!");
1637 case CCValAssign::Full: break;
1638 case CCValAssign::BCvt:
1639 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1641 case CCValAssign::SExt:
1642 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1643 DAG.getValueType(VA.getValVT()));
1644 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1646 case CCValAssign::ZExt:
1647 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1648 DAG.getValueType(VA.getValVT()));
1649 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1653 InVals.push_back(ArgValue);
1655 } else { // VA.isRegLoc()
1658 assert(VA.isMemLoc());
1659 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
1661 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
1662 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
1665 // Create load nodes to retrieve arguments from the stack.
1666 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1667 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
1668 PseudoSourceValue::getFixedStack(FI), 0));
1674 static const unsigned GPRArgRegs[] = {
1675 ARM::R0, ARM::R1, ARM::R2, ARM::R3
1678 unsigned NumGPRs = CCInfo.getFirstUnallocated
1679 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
1681 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1682 unsigned VARegSize = (4 - NumGPRs) * 4;
1683 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
1684 unsigned ArgOffset = CCInfo.getNextStackOffset();
1685 if (VARegSaveSize) {
1686 // If this function is vararg, store any remaining integer argument regs
1687 // to their spots on the stack so that they may be loaded by deferencing
1688 // the result of va_next.
1689 AFI->setVarArgsRegSaveSize(VARegSaveSize);
1690 VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset +
1691 VARegSaveSize - VARegSize,
1693 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
1695 SmallVector<SDValue, 4> MemOps;
1696 for (; NumGPRs < 4; ++NumGPRs) {
1697 TargetRegisterClass *RC;
1698 if (AFI->isThumb1OnlyFunction())
1699 RC = ARM::tGPRRegisterClass;
1701 RC = ARM::GPRRegisterClass;
1703 unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
1704 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
1705 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
1706 PseudoSourceValue::getFixedStack(VarArgsFrameIndex), 0);
1707 MemOps.push_back(Store);
1708 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
1709 DAG.getConstant(4, getPointerTy()));
1711 if (!MemOps.empty())
1712 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1713 &MemOps[0], MemOps.size());
1715 // This will point to the next argument passed via stack.
1716 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset, true, false);
1722 /// isFloatingPointZero - Return true if this is +0.0.
1723 static bool isFloatingPointZero(SDValue Op) {
1724 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1725 return CFP->getValueAPF().isPosZero();
1726 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1727 // Maybe this has already been legalized into the constant pool?
1728 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
1729 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
1730 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
1731 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1732 return CFP->getValueAPF().isPosZero();
1738 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
1739 /// the given operands.
1741 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1742 SDValue &ARMCC, SelectionDAG &DAG, DebugLoc dl) {
1743 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1744 unsigned C = RHSC->getZExtValue();
1745 if (!isLegalICmpImmediate(C)) {
1746 // Constant does not fit, try adjusting it by one?
1751 if (isLegalICmpImmediate(C-1)) {
1752 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1753 RHS = DAG.getConstant(C-1, MVT::i32);
1758 if (C > 0 && isLegalICmpImmediate(C-1)) {
1759 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1760 RHS = DAG.getConstant(C-1, MVT::i32);
1765 if (isLegalICmpImmediate(C+1)) {
1766 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1767 RHS = DAG.getConstant(C+1, MVT::i32);
1772 if (C < 0xffffffff && isLegalICmpImmediate(C+1)) {
1773 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1774 RHS = DAG.getConstant(C+1, MVT::i32);
1781 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
1782 ARMISD::NodeType CompareType;
1785 CompareType = ARMISD::CMP;
1790 CompareType = ARMISD::CMPZ;
1793 ARMCC = DAG.getConstant(CondCode, MVT::i32);
1794 return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS);
1797 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
1798 static SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
1801 if (!isFloatingPointZero(RHS))
1802 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS);
1804 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS);
1805 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp);
1808 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
1809 EVT VT = Op.getValueType();
1810 SDValue LHS = Op.getOperand(0);
1811 SDValue RHS = Op.getOperand(1);
1812 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1813 SDValue TrueVal = Op.getOperand(2);
1814 SDValue FalseVal = Op.getOperand(3);
1815 DebugLoc dl = Op.getDebugLoc();
1817 if (LHS.getValueType() == MVT::i32) {
1819 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1820 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, dl);
1821 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC, CCR,Cmp);
1824 ARMCC::CondCodes CondCode, CondCode2;
1825 FPCCToARMCC(CC, CondCode, CondCode2);
1827 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
1828 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1829 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
1830 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
1832 if (CondCode2 != ARMCC::AL) {
1833 SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
1834 // FIXME: Needs another CMP because flag can have but one use.
1835 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
1836 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
1837 Result, TrueVal, ARMCC2, CCR, Cmp2);
1842 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
1843 SDValue Chain = Op.getOperand(0);
1844 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1845 SDValue LHS = Op.getOperand(2);
1846 SDValue RHS = Op.getOperand(3);
1847 SDValue Dest = Op.getOperand(4);
1848 DebugLoc dl = Op.getDebugLoc();
1850 if (LHS.getValueType() == MVT::i32) {
1852 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1853 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, dl);
1854 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
1855 Chain, Dest, ARMCC, CCR,Cmp);
1858 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
1859 ARMCC::CondCodes CondCode, CondCode2;
1860 FPCCToARMCC(CC, CondCode, CondCode2);
1862 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
1863 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
1864 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1865 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
1866 SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp };
1867 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
1868 if (CondCode2 != ARMCC::AL) {
1869 ARMCC = DAG.getConstant(CondCode2, MVT::i32);
1870 SDValue Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) };
1871 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
1876 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) {
1877 SDValue Chain = Op.getOperand(0);
1878 SDValue Table = Op.getOperand(1);
1879 SDValue Index = Op.getOperand(2);
1880 DebugLoc dl = Op.getDebugLoc();
1882 EVT PTy = getPointerTy();
1883 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
1884 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
1885 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
1886 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
1887 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
1888 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
1889 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
1890 if (Subtarget->isThumb2()) {
1891 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
1892 // which does another jump to the destination. This also makes it easier
1893 // to translate it to TBB / TBH later.
1894 // FIXME: This might not work if the function is extremely large.
1895 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
1896 Addr, Op.getOperand(2), JTI, UId);
1898 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1899 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
1900 PseudoSourceValue::getJumpTable(), 0);
1901 Chain = Addr.getValue(1);
1902 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
1903 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
1905 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
1906 PseudoSourceValue::getJumpTable(), 0);
1907 Chain = Addr.getValue(1);
1908 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
1912 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1913 DebugLoc dl = Op.getDebugLoc();
1915 Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI;
1916 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
1917 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
1920 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1921 EVT VT = Op.getValueType();
1922 DebugLoc dl = Op.getDebugLoc();
1924 Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF;
1926 Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
1927 return DAG.getNode(Opc, dl, VT, Op);
1930 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
1931 // Implement fcopysign with a fabs and a conditional fneg.
1932 SDValue Tmp0 = Op.getOperand(0);
1933 SDValue Tmp1 = Op.getOperand(1);
1934 DebugLoc dl = Op.getDebugLoc();
1935 EVT VT = Op.getValueType();
1936 EVT SrcVT = Tmp1.getValueType();
1937 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
1938 SDValue Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG, dl);
1939 SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
1940 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1941 return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp);
1944 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
1945 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1946 MFI->setFrameAddressIsTaken(true);
1947 EVT VT = Op.getValueType();
1948 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
1949 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1950 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
1951 ? ARM::R7 : ARM::R11;
1952 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
1954 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0);
1959 ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
1961 SDValue Dst, SDValue Src,
1962 SDValue Size, unsigned Align,
1964 const Value *DstSV, uint64_t DstSVOff,
1965 const Value *SrcSV, uint64_t SrcSVOff){
1966 // Do repeated 4-byte loads and stores. To be improved.
1967 // This requires 4-byte alignment.
1968 if ((Align & 3) != 0)
1970 // This requires the copy size to be a constant, preferrably
1971 // within a subtarget-specific limit.
1972 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
1975 uint64_t SizeVal = ConstantSize->getZExtValue();
1976 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
1979 unsigned BytesLeft = SizeVal & 3;
1980 unsigned NumMemOps = SizeVal >> 2;
1981 unsigned EmittedNumMemOps = 0;
1983 unsigned VTSize = 4;
1985 const unsigned MAX_LOADS_IN_LDM = 6;
1986 SDValue TFOps[MAX_LOADS_IN_LDM];
1987 SDValue Loads[MAX_LOADS_IN_LDM];
1988 uint64_t SrcOff = 0, DstOff = 0;
1990 // Emit up to MAX_LOADS_IN_LDM loads, then a TokenFactor barrier, then the
1991 // same number of stores. The loads and stores will get combined into
1992 // ldm/stm later on.
1993 while (EmittedNumMemOps < NumMemOps) {
1995 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
1996 Loads[i] = DAG.getLoad(VT, dl, Chain,
1997 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
1998 DAG.getConstant(SrcOff, MVT::i32)),
1999 SrcSV, SrcSVOff + SrcOff);
2000 TFOps[i] = Loads[i].getValue(1);
2003 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
2006 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
2007 TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
2008 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
2009 DAG.getConstant(DstOff, MVT::i32)),
2010 DstSV, DstSVOff + DstOff);
2013 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
2015 EmittedNumMemOps += i;
2021 // Issue loads / stores for the trailing (1 - 3) bytes.
2022 unsigned BytesLeftSave = BytesLeft;
2025 if (BytesLeft >= 2) {
2033 Loads[i] = DAG.getLoad(VT, dl, Chain,
2034 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
2035 DAG.getConstant(SrcOff, MVT::i32)),
2036 SrcSV, SrcSVOff + SrcOff);
2037 TFOps[i] = Loads[i].getValue(1);
2040 BytesLeft -= VTSize;
2042 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
2045 BytesLeft = BytesLeftSave;
2047 if (BytesLeft >= 2) {
2055 TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
2056 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
2057 DAG.getConstant(DstOff, MVT::i32)),
2058 DstSV, DstSVOff + DstOff);
2061 BytesLeft -= VTSize;
2063 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
2066 static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
2067 SDValue Op = N->getOperand(0);
2068 DebugLoc dl = N->getDebugLoc();
2069 if (N->getValueType(0) == MVT::f64) {
2070 // Turn i64->f64 into VMOVDRR.
2071 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2072 DAG.getConstant(0, MVT::i32));
2073 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2074 DAG.getConstant(1, MVT::i32));
2075 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
2078 // Turn f64->i64 into VMOVRRD.
2079 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
2080 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
2082 // Merge the pieces into a single i64 value.
2083 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
2086 /// getZeroVector - Returns a vector of specified type with all zero elements.
2088 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2089 assert(VT.isVector() && "Expected a vector type");
2091 // Zero vectors are used to represent vector negation and in those cases
2092 // will be implemented with the NEON VNEG instruction. However, VNEG does
2093 // not support i64 elements, so sometimes the zero vectors will need to be
2094 // explicitly constructed. For those cases, and potentially other uses in
2095 // the future, always build zero vectors as <16 x i8> or <8 x i8> bitcasted
2096 // to their dest type. This ensures they get CSE'd.
2098 SDValue Cst = DAG.getTargetConstant(0, MVT::i8);
2099 SmallVector<SDValue, 8> Ops;
2102 if (VT.getSizeInBits() == 64) {
2103 Ops.assign(8, Cst); TVT = MVT::v8i8;
2105 Ops.assign(16, Cst); TVT = MVT::v16i8;
2107 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, TVT, &Ops[0], Ops.size());
2109 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2112 /// getOnesVector - Returns a vector of specified type with all bits set.
2114 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2115 assert(VT.isVector() && "Expected a vector type");
2117 // Always build ones vectors as <16 x i8> or <8 x i8> bitcasted to their
2118 // dest type. This ensures they get CSE'd.
2120 SDValue Cst = DAG.getTargetConstant(0xFF, MVT::i8);
2121 SmallVector<SDValue, 8> Ops;
2124 if (VT.getSizeInBits() == 64) {
2125 Ops.assign(8, Cst); TVT = MVT::v8i8;
2127 Ops.assign(16, Cst); TVT = MVT::v16i8;
2129 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, TVT, &Ops[0], Ops.size());
2131 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2134 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
2135 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2136 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) {
2137 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2138 EVT VT = Op.getValueType();
2139 unsigned VTBits = VT.getSizeInBits();
2140 DebugLoc dl = Op.getDebugLoc();
2141 SDValue ShOpLo = Op.getOperand(0);
2142 SDValue ShOpHi = Op.getOperand(1);
2143 SDValue ShAmt = Op.getOperand(2);
2145 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
2147 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
2149 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2150 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2151 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
2152 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2153 DAG.getConstant(VTBits, MVT::i32));
2154 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
2155 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2156 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
2158 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2159 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
2161 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
2162 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC,
2165 SDValue Ops[2] = { Lo, Hi };
2166 return DAG.getMergeValues(Ops, 2, dl);
2169 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
2170 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2171 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) {
2172 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2173 EVT VT = Op.getValueType();
2174 unsigned VTBits = VT.getSizeInBits();
2175 DebugLoc dl = Op.getDebugLoc();
2176 SDValue ShOpLo = Op.getOperand(0);
2177 SDValue ShOpHi = Op.getOperand(1);
2178 SDValue ShAmt = Op.getOperand(2);
2181 assert(Op.getOpcode() == ISD::SHL_PARTS);
2182 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2183 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2184 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
2185 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2186 DAG.getConstant(VTBits, MVT::i32));
2187 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
2188 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
2190 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2191 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2192 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
2194 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
2195 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMCC,
2198 SDValue Ops[2] = { Lo, Hi };
2199 return DAG.getMergeValues(Ops, 2, dl);
2202 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
2203 const ARMSubtarget *ST) {
2204 EVT VT = N->getValueType(0);
2205 DebugLoc dl = N->getDebugLoc();
2207 // Lower vector shifts on NEON to use VSHL.
2208 if (VT.isVector()) {
2209 assert(ST->hasNEON() && "unexpected vector shift");
2211 // Left shifts translate directly to the vshiftu intrinsic.
2212 if (N->getOpcode() == ISD::SHL)
2213 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2214 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
2215 N->getOperand(0), N->getOperand(1));
2217 assert((N->getOpcode() == ISD::SRA ||
2218 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
2220 // NEON uses the same intrinsics for both left and right shifts. For
2221 // right shifts, the shift amounts are negative, so negate the vector of
2223 EVT ShiftVT = N->getOperand(1).getValueType();
2224 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
2225 getZeroVector(ShiftVT, DAG, dl),
2227 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
2228 Intrinsic::arm_neon_vshifts :
2229 Intrinsic::arm_neon_vshiftu);
2230 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2231 DAG.getConstant(vshiftInt, MVT::i32),
2232 N->getOperand(0), NegatedCount);
2235 // We can get here for a node like i32 = ISD::SHL i32, i64
2239 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
2240 "Unknown shift to lower!");
2242 // We only lower SRA, SRL of 1 here, all others use generic lowering.
2243 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
2244 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
2247 // If we are in thumb mode, we don't have RRX.
2248 if (ST->isThumb1Only()) return SDValue();
2250 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
2251 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2252 DAG.getConstant(0, MVT::i32));
2253 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2254 DAG.getConstant(1, MVT::i32));
2256 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
2257 // captures the result into a carry flag.
2258 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
2259 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
2261 // The low part is an ARMISD::RRX operand, which shifts the carry in.
2262 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
2264 // Merge the pieces into a single i64 value.
2265 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
2268 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
2269 SDValue TmpOp0, TmpOp1;
2270 bool Invert = false;
2274 SDValue Op0 = Op.getOperand(0);
2275 SDValue Op1 = Op.getOperand(1);
2276 SDValue CC = Op.getOperand(2);
2277 EVT VT = Op.getValueType();
2278 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
2279 DebugLoc dl = Op.getDebugLoc();
2281 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
2282 switch (SetCCOpcode) {
2283 default: llvm_unreachable("Illegal FP comparison"); break;
2285 case ISD::SETNE: Invert = true; // Fallthrough
2287 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2289 case ISD::SETLT: Swap = true; // Fallthrough
2291 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2293 case ISD::SETLE: Swap = true; // Fallthrough
2295 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2296 case ISD::SETUGE: Swap = true; // Fallthrough
2297 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
2298 case ISD::SETUGT: Swap = true; // Fallthrough
2299 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
2300 case ISD::SETUEQ: Invert = true; // Fallthrough
2302 // Expand this to (OLT | OGT).
2306 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2307 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
2309 case ISD::SETUO: Invert = true; // Fallthrough
2311 // Expand this to (OLT | OGE).
2315 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2316 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
2320 // Integer comparisons.
2321 switch (SetCCOpcode) {
2322 default: llvm_unreachable("Illegal integer comparison"); break;
2323 case ISD::SETNE: Invert = true;
2324 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2325 case ISD::SETLT: Swap = true;
2326 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2327 case ISD::SETLE: Swap = true;
2328 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2329 case ISD::SETULT: Swap = true;
2330 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
2331 case ISD::SETULE: Swap = true;
2332 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
2335 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
2336 if (Opc == ARMISD::VCEQ) {
2339 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
2341 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
2344 // Ignore bitconvert.
2345 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BIT_CONVERT)
2346 AndOp = AndOp.getOperand(0);
2348 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
2350 Op0 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(0));
2351 Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(1));
2358 std::swap(Op0, Op1);
2360 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
2363 Result = DAG.getNOT(dl, Result, VT);
2368 /// isVMOVSplat - Check if the specified splat value corresponds to an immediate
2369 /// VMOV instruction, and if so, return the constant being splatted.
2370 static SDValue isVMOVSplat(uint64_t SplatBits, uint64_t SplatUndef,
2371 unsigned SplatBitSize, SelectionDAG &DAG) {
2372 switch (SplatBitSize) {
2374 // Any 1-byte value is OK.
2375 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
2376 return DAG.getTargetConstant(SplatBits, MVT::i8);
2379 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
2380 if ((SplatBits & ~0xff) == 0 ||
2381 (SplatBits & ~0xff00) == 0)
2382 return DAG.getTargetConstant(SplatBits, MVT::i16);
2386 // NEON's 32-bit VMOV supports splat values where:
2387 // * only one byte is nonzero, or
2388 // * the least significant byte is 0xff and the second byte is nonzero, or
2389 // * the least significant 2 bytes are 0xff and the third is nonzero.
2390 if ((SplatBits & ~0xff) == 0 ||
2391 (SplatBits & ~0xff00) == 0 ||
2392 (SplatBits & ~0xff0000) == 0 ||
2393 (SplatBits & ~0xff000000) == 0)
2394 return DAG.getTargetConstant(SplatBits, MVT::i32);
2396 if ((SplatBits & ~0xffff) == 0 &&
2397 ((SplatBits | SplatUndef) & 0xff) == 0xff)
2398 return DAG.getTargetConstant(SplatBits | 0xff, MVT::i32);
2400 if ((SplatBits & ~0xffffff) == 0 &&
2401 ((SplatBits | SplatUndef) & 0xffff) == 0xffff)
2402 return DAG.getTargetConstant(SplatBits | 0xffff, MVT::i32);
2404 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
2405 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
2406 // VMOV.I32. A (very) minor optimization would be to replicate the value
2407 // and fall through here to test for a valid 64-bit splat. But, then the
2408 // caller would also need to check and handle the change in size.
2412 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
2413 uint64_t BitMask = 0xff;
2415 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
2416 if (((SplatBits | SplatUndef) & BitMask) == BitMask)
2418 else if ((SplatBits & BitMask) != 0)
2422 return DAG.getTargetConstant(Val, MVT::i64);
2426 llvm_unreachable("unexpected size for isVMOVSplat");
2433 /// getVMOVImm - If this is a build_vector of constants which can be
2434 /// formed by using a VMOV instruction of the specified element size,
2435 /// return the constant being splatted. The ByteSize field indicates the
2436 /// number of bytes of each element [1248].
2437 SDValue ARM::getVMOVImm(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
2438 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N);
2439 APInt SplatBits, SplatUndef;
2440 unsigned SplatBitSize;
2442 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
2443 HasAnyUndefs, ByteSize * 8))
2446 if (SplatBitSize > ByteSize * 8)
2449 return isVMOVSplat(SplatBits.getZExtValue(), SplatUndef.getZExtValue(),
2453 static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT,
2454 bool &ReverseVEXT, unsigned &Imm) {
2455 unsigned NumElts = VT.getVectorNumElements();
2456 ReverseVEXT = false;
2459 // If this is a VEXT shuffle, the immediate value is the index of the first
2460 // element. The other shuffle indices must be the successive elements after
2462 unsigned ExpectedElt = Imm;
2463 for (unsigned i = 1; i < NumElts; ++i) {
2464 // Increment the expected index. If it wraps around, it may still be
2465 // a VEXT but the source vectors must be swapped.
2467 if (ExpectedElt == NumElts * 2) {
2472 if (ExpectedElt != static_cast<unsigned>(M[i]))
2476 // Adjust the index value if the source operands will be swapped.
2483 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
2484 /// instruction with the specified blocksize. (The order of the elements
2485 /// within each block of the vector is reversed.)
2486 static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT,
2487 unsigned BlockSize) {
2488 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
2489 "Only possible block sizes for VREV are: 16, 32, 64");
2491 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2495 unsigned NumElts = VT.getVectorNumElements();
2496 unsigned BlockElts = M[0] + 1;
2498 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
2501 for (unsigned i = 0; i < NumElts; ++i) {
2502 if ((unsigned) M[i] !=
2503 (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
2510 static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT,
2511 unsigned &WhichResult) {
2512 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2516 unsigned NumElts = VT.getVectorNumElements();
2517 WhichResult = (M[0] == 0 ? 0 : 1);
2518 for (unsigned i = 0; i < NumElts; i += 2) {
2519 if ((unsigned) M[i] != i + WhichResult ||
2520 (unsigned) M[i+1] != i + NumElts + WhichResult)
2526 static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT,
2527 unsigned &WhichResult) {
2528 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2532 unsigned NumElts = VT.getVectorNumElements();
2533 WhichResult = (M[0] == 0 ? 0 : 1);
2534 for (unsigned i = 0; i != NumElts; ++i) {
2535 if ((unsigned) M[i] != 2 * i + WhichResult)
2539 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
2540 if (VT.is64BitVector() && EltSz == 32)
2546 static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT,
2547 unsigned &WhichResult) {
2548 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2552 unsigned NumElts = VT.getVectorNumElements();
2553 WhichResult = (M[0] == 0 ? 0 : 1);
2554 unsigned Idx = WhichResult * NumElts / 2;
2555 for (unsigned i = 0; i != NumElts; i += 2) {
2556 if ((unsigned) M[i] != Idx ||
2557 (unsigned) M[i+1] != Idx + NumElts)
2562 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
2563 if (VT.is64BitVector() && EltSz == 32)
2569 static SDValue BuildSplat(SDValue Val, EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2570 // Canonicalize all-zeros and all-ones vectors.
2571 ConstantSDNode *ConstVal = cast<ConstantSDNode>(Val.getNode());
2572 if (ConstVal->isNullValue())
2573 return getZeroVector(VT, DAG, dl);
2574 if (ConstVal->isAllOnesValue())
2575 return getOnesVector(VT, DAG, dl);
2578 if (VT.is64BitVector()) {
2579 switch (Val.getValueType().getSizeInBits()) {
2580 case 8: CanonicalVT = MVT::v8i8; break;
2581 case 16: CanonicalVT = MVT::v4i16; break;
2582 case 32: CanonicalVT = MVT::v2i32; break;
2583 case 64: CanonicalVT = MVT::v1i64; break;
2584 default: llvm_unreachable("unexpected splat element type"); break;
2587 assert(VT.is128BitVector() && "unknown splat vector size");
2588 switch (Val.getValueType().getSizeInBits()) {
2589 case 8: CanonicalVT = MVT::v16i8; break;
2590 case 16: CanonicalVT = MVT::v8i16; break;
2591 case 32: CanonicalVT = MVT::v4i32; break;
2592 case 64: CanonicalVT = MVT::v2i64; break;
2593 default: llvm_unreachable("unexpected splat element type"); break;
2597 // Build a canonical splat for this value.
2598 SmallVector<SDValue, 8> Ops;
2599 Ops.assign(CanonicalVT.getVectorNumElements(), Val);
2600 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, &Ops[0],
2602 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Res);
2605 // If this is a case we can't handle, return null and let the default
2606 // expansion code take care of it.
2607 static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
2608 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
2609 DebugLoc dl = Op.getDebugLoc();
2610 EVT VT = Op.getValueType();
2612 APInt SplatBits, SplatUndef;
2613 unsigned SplatBitSize;
2615 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
2616 if (SplatBitSize <= 64) {
2617 SDValue Val = isVMOVSplat(SplatBits.getZExtValue(),
2618 SplatUndef.getZExtValue(), SplatBitSize, DAG);
2620 return BuildSplat(Val, VT, DAG, dl);
2624 // If there are only 2 elements in a 128-bit vector, insert them into an
2625 // undef vector. This handles the common case for 128-bit vector argument
2626 // passing, where the insertions should be translated to subreg accesses
2627 // with no real instructions.
2628 if (VT.is128BitVector() && Op.getNumOperands() == 2) {
2629 SDValue Val = DAG.getUNDEF(VT);
2630 SDValue Op0 = Op.getOperand(0);
2631 SDValue Op1 = Op.getOperand(1);
2632 if (Op0.getOpcode() != ISD::UNDEF)
2633 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, Op0,
2634 DAG.getIntPtrConstant(0));
2635 if (Op1.getOpcode() != ISD::UNDEF)
2636 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, Op1,
2637 DAG.getIntPtrConstant(1));
2644 /// isShuffleMaskLegal - Targets can use this to indicate that they only
2645 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
2646 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
2647 /// are assumed to be legal.
2649 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
2651 if (VT.getVectorNumElements() == 4 &&
2652 (VT.is128BitVector() || VT.is64BitVector())) {
2653 unsigned PFIndexes[4];
2654 for (unsigned i = 0; i != 4; ++i) {
2658 PFIndexes[i] = M[i];
2661 // Compute the index in the perfect shuffle table.
2662 unsigned PFTableIndex =
2663 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
2664 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
2665 unsigned Cost = (PFEntry >> 30);
2672 unsigned Imm, WhichResult;
2674 return (ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
2675 isVREVMask(M, VT, 64) ||
2676 isVREVMask(M, VT, 32) ||
2677 isVREVMask(M, VT, 16) ||
2678 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
2679 isVTRNMask(M, VT, WhichResult) ||
2680 isVUZPMask(M, VT, WhichResult) ||
2681 isVZIPMask(M, VT, WhichResult));
2684 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
2685 /// the specified operations to build the shuffle.
2686 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
2687 SDValue RHS, SelectionDAG &DAG,
2689 unsigned OpNum = (PFEntry >> 26) & 0x0F;
2690 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
2691 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
2694 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
2703 OP_VUZPL, // VUZP, left result
2704 OP_VUZPR, // VUZP, right result
2705 OP_VZIPL, // VZIP, left result
2706 OP_VZIPR, // VZIP, right result
2707 OP_VTRNL, // VTRN, left result
2708 OP_VTRNR // VTRN, right result
2711 if (OpNum == OP_COPY) {
2712 if (LHSID == (1*9+2)*9+3) return LHS;
2713 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
2717 SDValue OpLHS, OpRHS;
2718 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
2719 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
2720 EVT VT = OpLHS.getValueType();
2723 default: llvm_unreachable("Unknown shuffle opcode!");
2725 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
2730 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
2731 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
2735 return DAG.getNode(ARMISD::VEXT, dl, VT,
2737 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
2740 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
2741 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
2744 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
2745 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
2748 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
2749 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
2753 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
2754 SDValue V1 = Op.getOperand(0);
2755 SDValue V2 = Op.getOperand(1);
2756 DebugLoc dl = Op.getDebugLoc();
2757 EVT VT = Op.getValueType();
2758 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
2759 SmallVector<int, 8> ShuffleMask;
2761 // Convert shuffles that are directly supported on NEON to target-specific
2762 // DAG nodes, instead of keeping them as shuffles and matching them again
2763 // during code selection. This is more efficient and avoids the possibility
2764 // of inconsistencies between legalization and selection.
2765 // FIXME: floating-point vectors should be canonicalized to integer vectors
2766 // of the same time so that they get CSEd properly.
2767 SVN->getMask(ShuffleMask);
2769 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
2770 int Lane = SVN->getSplatIndex();
2771 // If this is undef splat, generate it via "just" vdup, if possible.
2772 if (Lane == -1) Lane = 0;
2774 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
2775 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
2777 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
2778 DAG.getConstant(Lane, MVT::i32));
2783 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
2786 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
2787 DAG.getConstant(Imm, MVT::i32));
2790 if (isVREVMask(ShuffleMask, VT, 64))
2791 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
2792 if (isVREVMask(ShuffleMask, VT, 32))
2793 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
2794 if (isVREVMask(ShuffleMask, VT, 16))
2795 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
2797 // Check for Neon shuffles that modify both input vectors in place.
2798 // If both results are used, i.e., if there are two shuffles with the same
2799 // source operands and with masks corresponding to both results of one of
2800 // these operations, DAG memoization will ensure that a single node is
2801 // used for both shuffles.
2802 unsigned WhichResult;
2803 if (isVTRNMask(ShuffleMask, VT, WhichResult))
2804 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
2805 V1, V2).getValue(WhichResult);
2806 if (isVUZPMask(ShuffleMask, VT, WhichResult))
2807 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
2808 V1, V2).getValue(WhichResult);
2809 if (isVZIPMask(ShuffleMask, VT, WhichResult))
2810 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
2811 V1, V2).getValue(WhichResult);
2813 // If the shuffle is not directly supported and it has 4 elements, use
2814 // the PerfectShuffle-generated table to synthesize it from other shuffles.
2815 if (VT.getVectorNumElements() == 4 &&
2816 (VT.is128BitVector() || VT.is64BitVector())) {
2817 unsigned PFIndexes[4];
2818 for (unsigned i = 0; i != 4; ++i) {
2819 if (ShuffleMask[i] < 0)
2822 PFIndexes[i] = ShuffleMask[i];
2825 // Compute the index in the perfect shuffle table.
2826 unsigned PFTableIndex =
2827 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
2829 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
2830 unsigned Cost = (PFEntry >> 30);
2833 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
2839 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
2840 EVT VT = Op.getValueType();
2841 DebugLoc dl = Op.getDebugLoc();
2842 SDValue Vec = Op.getOperand(0);
2843 SDValue Lane = Op.getOperand(1);
2844 assert(VT == MVT::i32 &&
2845 Vec.getValueType().getVectorElementType().getSizeInBits() < 32 &&
2846 "unexpected type for custom-lowering vector extract");
2847 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
2850 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
2851 // The only time a CONCAT_VECTORS operation can have legal types is when
2852 // two 64-bit vectors are concatenated to a 128-bit vector.
2853 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
2854 "unexpected CONCAT_VECTORS");
2855 DebugLoc dl = Op.getDebugLoc();
2856 SDValue Val = DAG.getUNDEF(MVT::v2f64);
2857 SDValue Op0 = Op.getOperand(0);
2858 SDValue Op1 = Op.getOperand(1);
2859 if (Op0.getOpcode() != ISD::UNDEF)
2860 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
2861 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op0),
2862 DAG.getIntPtrConstant(0));
2863 if (Op1.getOpcode() != ISD::UNDEF)
2864 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
2865 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op1),
2866 DAG.getIntPtrConstant(1));
2867 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Val);
2870 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
2871 switch (Op.getOpcode()) {
2872 default: llvm_unreachable("Don't know how to custom lower this!");
2873 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2874 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
2875 case ISD::GlobalAddress:
2876 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
2877 LowerGlobalAddressELF(Op, DAG);
2878 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
2879 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
2880 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
2881 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
2882 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
2883 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex);
2884 case ISD::SINT_TO_FP:
2885 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
2886 case ISD::FP_TO_SINT:
2887 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
2888 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
2889 case ISD::RETURNADDR: break;
2890 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
2891 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
2892 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2893 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(Op.getNode(), DAG);
2896 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
2897 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
2898 case ISD::SRL_PARTS:
2899 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
2900 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
2901 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
2902 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
2903 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
2904 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
2909 /// ReplaceNodeResults - Replace the results of node with an illegal result
2910 /// type with new values built out of custom code.
2911 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
2912 SmallVectorImpl<SDValue>&Results,
2913 SelectionDAG &DAG) {
2914 switch (N->getOpcode()) {
2916 llvm_unreachable("Don't know how to custom expand this!");
2918 case ISD::BIT_CONVERT:
2919 Results.push_back(ExpandBIT_CONVERT(N, DAG));
2923 SDValue Res = LowerShift(N, DAG, Subtarget);
2925 Results.push_back(Res);
2931 //===----------------------------------------------------------------------===//
2932 // ARM Scheduler Hooks
2933 //===----------------------------------------------------------------------===//
2936 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
2937 MachineBasicBlock *BB,
2938 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
2939 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2940 DebugLoc dl = MI->getDebugLoc();
2941 switch (MI->getOpcode()) {
2943 llvm_unreachable("Unexpected instr type to insert");
2944 case ARM::tMOVCCr_pseudo: {
2945 // To "insert" a SELECT_CC instruction, we actually have to insert the
2946 // diamond control-flow pattern. The incoming instruction knows the
2947 // destination vreg to set, the condition code register to branch on, the
2948 // true/false values to select between, and a branch opcode to use.
2949 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2950 MachineFunction::iterator It = BB;
2956 // cmpTY ccX, r1, r2
2958 // fallthrough --> copy0MBB
2959 MachineBasicBlock *thisMBB = BB;
2960 MachineFunction *F = BB->getParent();
2961 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
2962 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
2963 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
2964 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
2965 F->insert(It, copy0MBB);
2966 F->insert(It, sinkMBB);
2967 // Update machine-CFG edges by first adding all successors of the current
2968 // block to the new block which will contain the Phi node for the select.
2969 // Also inform sdisel of the edge changes.
2970 for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
2971 E = BB->succ_end(); I != E; ++I) {
2972 EM->insert(std::make_pair(*I, sinkMBB));
2973 sinkMBB->addSuccessor(*I);
2975 // Next, remove all successors of the current block, and add the true
2976 // and fallthrough blocks as its successors.
2977 while (!BB->succ_empty())
2978 BB->removeSuccessor(BB->succ_begin());
2979 BB->addSuccessor(copy0MBB);
2980 BB->addSuccessor(sinkMBB);
2983 // %FalseValue = ...
2984 // # fallthrough to sinkMBB
2987 // Update machine-CFG edges
2988 BB->addSuccessor(sinkMBB);
2991 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
2994 BuildMI(BB, dl, TII->get(ARM::PHI), MI->getOperand(0).getReg())
2995 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
2996 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
2998 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
3005 case ARM::t2SUBrSPi_:
3006 case ARM::t2SUBrSPi12_:
3007 case ARM::t2SUBrSPs_: {
3008 MachineFunction *MF = BB->getParent();
3009 unsigned DstReg = MI->getOperand(0).getReg();
3010 unsigned SrcReg = MI->getOperand(1).getReg();
3011 bool DstIsDead = MI->getOperand(0).isDead();
3012 bool SrcIsKill = MI->getOperand(1).isKill();
3014 if (SrcReg != ARM::SP) {
3015 // Copy the source to SP from virtual register.
3016 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(SrcReg);
3017 unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
3018 ? ARM::tMOVtgpr2gpr : ARM::tMOVgpr2gpr;
3019 BuildMI(BB, dl, TII->get(CopyOpc), ARM::SP)
3020 .addReg(SrcReg, getKillRegState(SrcIsKill));
3024 bool NeedPred = false, NeedCC = false, NeedOp3 = false;
3025 switch (MI->getOpcode()) {
3027 llvm_unreachable("Unexpected pseudo instruction!");
3033 OpOpc = ARM::tADDspr;
3036 OpOpc = ARM::tSUBspi;
3038 case ARM::t2SUBrSPi_:
3039 OpOpc = ARM::t2SUBrSPi;
3040 NeedPred = true; NeedCC = true;
3042 case ARM::t2SUBrSPi12_:
3043 OpOpc = ARM::t2SUBrSPi12;
3046 case ARM::t2SUBrSPs_:
3047 OpOpc = ARM::t2SUBrSPs;
3048 NeedPred = true; NeedCC = true; NeedOp3 = true;
3051 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(OpOpc), ARM::SP);
3052 if (OpOpc == ARM::tAND)
3053 AddDefaultT1CC(MIB);
3054 MIB.addReg(ARM::SP);
3055 MIB.addOperand(MI->getOperand(2));
3057 MIB.addOperand(MI->getOperand(3));
3059 AddDefaultPred(MIB);
3063 // Copy the result from SP to virtual register.
3064 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(DstReg);
3065 unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
3066 ? ARM::tMOVgpr2tgpr : ARM::tMOVgpr2gpr;
3067 BuildMI(BB, dl, TII->get(CopyOpc))
3068 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead))
3070 MF->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
3076 //===----------------------------------------------------------------------===//
3077 // ARM Optimization Hooks
3078 //===----------------------------------------------------------------------===//
3081 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
3082 TargetLowering::DAGCombinerInfo &DCI) {
3083 SelectionDAG &DAG = DCI.DAG;
3084 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3085 EVT VT = N->getValueType(0);
3086 unsigned Opc = N->getOpcode();
3087 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
3088 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
3089 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
3090 ISD::CondCode CC = ISD::SETCC_INVALID;
3093 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
3095 SDValue CCOp = Slct.getOperand(0);
3096 if (CCOp.getOpcode() == ISD::SETCC)
3097 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
3100 bool DoXform = false;
3102 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
3105 if (LHS.getOpcode() == ISD::Constant &&
3106 cast<ConstantSDNode>(LHS)->isNullValue()) {
3108 } else if (CC != ISD::SETCC_INVALID &&
3109 RHS.getOpcode() == ISD::Constant &&
3110 cast<ConstantSDNode>(RHS)->isNullValue()) {
3111 std::swap(LHS, RHS);
3112 SDValue Op0 = Slct.getOperand(0);
3113 EVT OpVT = isSlctCC ? Op0.getValueType() :
3114 Op0.getOperand(0).getValueType();
3115 bool isInt = OpVT.isInteger();
3116 CC = ISD::getSetCCInverse(CC, isInt);
3118 if (!TLI.isCondCodeLegal(CC, OpVT))
3119 return SDValue(); // Inverse operator isn't legal.
3126 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
3128 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
3129 Slct.getOperand(0), Slct.getOperand(1), CC);
3130 SDValue CCOp = Slct.getOperand(0);
3132 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
3133 CCOp.getOperand(0), CCOp.getOperand(1), CC);
3134 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
3135 CCOp, OtherOp, Result);
3140 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
3141 static SDValue PerformADDCombine(SDNode *N,
3142 TargetLowering::DAGCombinerInfo &DCI) {
3143 // added by evan in r37685 with no testcase.
3144 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
3146 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
3147 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
3148 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
3149 if (Result.getNode()) return Result;
3151 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
3152 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
3153 if (Result.getNode()) return Result;
3159 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
3160 static SDValue PerformSUBCombine(SDNode *N,
3161 TargetLowering::DAGCombinerInfo &DCI) {
3162 // added by evan in r37685 with no testcase.
3163 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
3165 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
3166 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
3167 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
3168 if (Result.getNode()) return Result;
3174 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for ARMISD::VMOVRRD.
3175 static SDValue PerformVMOVRRDCombine(SDNode *N,
3176 TargetLowering::DAGCombinerInfo &DCI) {
3177 // fmrrd(fmdrr x, y) -> x,y
3178 SDValue InDouble = N->getOperand(0);
3179 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
3180 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
3184 /// getVShiftImm - Check if this is a valid build_vector for the immediate
3185 /// operand of a vector shift operation, where all the elements of the
3186 /// build_vector must have the same constant integer value.
3187 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
3188 // Ignore bit_converts.
3189 while (Op.getOpcode() == ISD::BIT_CONVERT)
3190 Op = Op.getOperand(0);
3191 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
3192 APInt SplatBits, SplatUndef;
3193 unsigned SplatBitSize;
3195 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
3196 HasAnyUndefs, ElementBits) ||
3197 SplatBitSize > ElementBits)
3199 Cnt = SplatBits.getSExtValue();
3203 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
3204 /// operand of a vector shift left operation. That value must be in the range:
3205 /// 0 <= Value < ElementBits for a left shift; or
3206 /// 0 <= Value <= ElementBits for a long left shift.
3207 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
3208 assert(VT.isVector() && "vector shift count is not a vector type");
3209 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
3210 if (! getVShiftImm(Op, ElementBits, Cnt))
3212 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
3215 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
3216 /// operand of a vector shift right operation. For a shift opcode, the value
3217 /// is positive, but for an intrinsic the value count must be negative. The
3218 /// absolute value must be in the range:
3219 /// 1 <= |Value| <= ElementBits for a right shift; or
3220 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
3221 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
3223 assert(VT.isVector() && "vector shift count is not a vector type");
3224 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
3225 if (! getVShiftImm(Op, ElementBits, Cnt))
3229 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
3232 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
3233 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
3234 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
3237 // Don't do anything for most intrinsics.
3240 // Vector shifts: check for immediate versions and lower them.
3241 // Note: This is done during DAG combining instead of DAG legalizing because
3242 // the build_vectors for 64-bit vector element shift counts are generally
3243 // not legal, and it is hard to see their values after they get legalized to
3244 // loads from a constant pool.
3245 case Intrinsic::arm_neon_vshifts:
3246 case Intrinsic::arm_neon_vshiftu:
3247 case Intrinsic::arm_neon_vshiftls:
3248 case Intrinsic::arm_neon_vshiftlu:
3249 case Intrinsic::arm_neon_vshiftn:
3250 case Intrinsic::arm_neon_vrshifts:
3251 case Intrinsic::arm_neon_vrshiftu:
3252 case Intrinsic::arm_neon_vrshiftn:
3253 case Intrinsic::arm_neon_vqshifts:
3254 case Intrinsic::arm_neon_vqshiftu:
3255 case Intrinsic::arm_neon_vqshiftsu:
3256 case Intrinsic::arm_neon_vqshiftns:
3257 case Intrinsic::arm_neon_vqshiftnu:
3258 case Intrinsic::arm_neon_vqshiftnsu:
3259 case Intrinsic::arm_neon_vqrshiftns:
3260 case Intrinsic::arm_neon_vqrshiftnu:
3261 case Intrinsic::arm_neon_vqrshiftnsu: {
3262 EVT VT = N->getOperand(1).getValueType();
3264 unsigned VShiftOpc = 0;
3267 case Intrinsic::arm_neon_vshifts:
3268 case Intrinsic::arm_neon_vshiftu:
3269 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
3270 VShiftOpc = ARMISD::VSHL;
3273 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
3274 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
3275 ARMISD::VSHRs : ARMISD::VSHRu);
3280 case Intrinsic::arm_neon_vshiftls:
3281 case Intrinsic::arm_neon_vshiftlu:
3282 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
3284 llvm_unreachable("invalid shift count for vshll intrinsic");
3286 case Intrinsic::arm_neon_vrshifts:
3287 case Intrinsic::arm_neon_vrshiftu:
3288 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
3292 case Intrinsic::arm_neon_vqshifts:
3293 case Intrinsic::arm_neon_vqshiftu:
3294 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
3298 case Intrinsic::arm_neon_vqshiftsu:
3299 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
3301 llvm_unreachable("invalid shift count for vqshlu intrinsic");
3303 case Intrinsic::arm_neon_vshiftn:
3304 case Intrinsic::arm_neon_vrshiftn:
3305 case Intrinsic::arm_neon_vqshiftns:
3306 case Intrinsic::arm_neon_vqshiftnu:
3307 case Intrinsic::arm_neon_vqshiftnsu:
3308 case Intrinsic::arm_neon_vqrshiftns:
3309 case Intrinsic::arm_neon_vqrshiftnu:
3310 case Intrinsic::arm_neon_vqrshiftnsu:
3311 // Narrowing shifts require an immediate right shift.
3312 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
3314 llvm_unreachable("invalid shift count for narrowing vector shift intrinsic");
3317 llvm_unreachable("unhandled vector shift");
3321 case Intrinsic::arm_neon_vshifts:
3322 case Intrinsic::arm_neon_vshiftu:
3323 // Opcode already set above.
3325 case Intrinsic::arm_neon_vshiftls:
3326 case Intrinsic::arm_neon_vshiftlu:
3327 if (Cnt == VT.getVectorElementType().getSizeInBits())
3328 VShiftOpc = ARMISD::VSHLLi;
3330 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
3331 ARMISD::VSHLLs : ARMISD::VSHLLu);
3333 case Intrinsic::arm_neon_vshiftn:
3334 VShiftOpc = ARMISD::VSHRN; break;
3335 case Intrinsic::arm_neon_vrshifts:
3336 VShiftOpc = ARMISD::VRSHRs; break;
3337 case Intrinsic::arm_neon_vrshiftu:
3338 VShiftOpc = ARMISD::VRSHRu; break;
3339 case Intrinsic::arm_neon_vrshiftn:
3340 VShiftOpc = ARMISD::VRSHRN; break;
3341 case Intrinsic::arm_neon_vqshifts:
3342 VShiftOpc = ARMISD::VQSHLs; break;
3343 case Intrinsic::arm_neon_vqshiftu:
3344 VShiftOpc = ARMISD::VQSHLu; break;
3345 case Intrinsic::arm_neon_vqshiftsu:
3346 VShiftOpc = ARMISD::VQSHLsu; break;
3347 case Intrinsic::arm_neon_vqshiftns:
3348 VShiftOpc = ARMISD::VQSHRNs; break;
3349 case Intrinsic::arm_neon_vqshiftnu:
3350 VShiftOpc = ARMISD::VQSHRNu; break;
3351 case Intrinsic::arm_neon_vqshiftnsu:
3352 VShiftOpc = ARMISD::VQSHRNsu; break;
3353 case Intrinsic::arm_neon_vqrshiftns:
3354 VShiftOpc = ARMISD::VQRSHRNs; break;
3355 case Intrinsic::arm_neon_vqrshiftnu:
3356 VShiftOpc = ARMISD::VQRSHRNu; break;
3357 case Intrinsic::arm_neon_vqrshiftnsu:
3358 VShiftOpc = ARMISD::VQRSHRNsu; break;
3361 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
3362 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
3365 case Intrinsic::arm_neon_vshiftins: {
3366 EVT VT = N->getOperand(1).getValueType();
3368 unsigned VShiftOpc = 0;
3370 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
3371 VShiftOpc = ARMISD::VSLI;
3372 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
3373 VShiftOpc = ARMISD::VSRI;
3375 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
3378 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
3379 N->getOperand(1), N->getOperand(2),
3380 DAG.getConstant(Cnt, MVT::i32));
3383 case Intrinsic::arm_neon_vqrshifts:
3384 case Intrinsic::arm_neon_vqrshiftu:
3385 // No immediate versions of these to check for.
3392 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
3393 /// lowers them. As with the vector shift intrinsics, this is done during DAG
3394 /// combining instead of DAG legalizing because the build_vectors for 64-bit
3395 /// vector element shift counts are generally not legal, and it is hard to see
3396 /// their values after they get legalized to loads from a constant pool.
3397 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
3398 const ARMSubtarget *ST) {
3399 EVT VT = N->getValueType(0);
3401 // Nothing to be done for scalar shifts.
3402 if (! VT.isVector())
3405 assert(ST->hasNEON() && "unexpected vector shift");
3408 switch (N->getOpcode()) {
3409 default: llvm_unreachable("unexpected shift opcode");
3412 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
3413 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
3414 DAG.getConstant(Cnt, MVT::i32));
3419 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
3420 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
3421 ARMISD::VSHRs : ARMISD::VSHRu);
3422 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
3423 DAG.getConstant(Cnt, MVT::i32));
3429 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
3430 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
3431 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
3432 const ARMSubtarget *ST) {
3433 SDValue N0 = N->getOperand(0);
3435 // Check for sign- and zero-extensions of vector extract operations of 8-
3436 // and 16-bit vector elements. NEON supports these directly. They are
3437 // handled during DAG combining because type legalization will promote them
3438 // to 32-bit types and it is messy to recognize the operations after that.
3439 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
3440 SDValue Vec = N0.getOperand(0);
3441 SDValue Lane = N0.getOperand(1);
3442 EVT VT = N->getValueType(0);
3443 EVT EltVT = N0.getValueType();
3444 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3446 if (VT == MVT::i32 &&
3447 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
3448 TLI.isTypeLegal(Vec.getValueType())) {
3451 switch (N->getOpcode()) {
3452 default: llvm_unreachable("unexpected opcode");
3453 case ISD::SIGN_EXTEND:
3454 Opc = ARMISD::VGETLANEs;
3456 case ISD::ZERO_EXTEND:
3457 case ISD::ANY_EXTEND:
3458 Opc = ARMISD::VGETLANEu;
3461 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
3468 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
3469 DAGCombinerInfo &DCI) const {
3470 switch (N->getOpcode()) {
3472 case ISD::ADD: return PerformADDCombine(N, DCI);
3473 case ISD::SUB: return PerformSUBCombine(N, DCI);
3474 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
3475 case ISD::INTRINSIC_WO_CHAIN:
3476 return PerformIntrinsicCombine(N, DCI.DAG);
3480 return PerformShiftCombine(N, DCI.DAG, Subtarget);
3481 case ISD::SIGN_EXTEND:
3482 case ISD::ZERO_EXTEND:
3483 case ISD::ANY_EXTEND:
3484 return PerformExtendCombine(N, DCI.DAG, Subtarget);
3489 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
3490 if (!Subtarget->hasV6Ops())
3491 // Pre-v6 does not support unaligned mem access.
3493 else if (!Subtarget->hasV6Ops()) {
3494 // v6 may or may not support unaligned mem access.
3495 if (!Subtarget->isTargetDarwin())
3499 switch (VT.getSimpleVT().SimpleTy) {
3506 // FIXME: VLD1 etc with standard alignment is legal.
3510 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
3515 switch (VT.getSimpleVT().SimpleTy) {
3516 default: return false;
3531 if ((V & (Scale - 1)) != 0)
3534 return V == (V & ((1LL << 5) - 1));
3537 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
3538 const ARMSubtarget *Subtarget) {
3545 switch (VT.getSimpleVT().SimpleTy) {
3546 default: return false;
3551 // + imm12 or - imm8
3553 return V == (V & ((1LL << 8) - 1));
3554 return V == (V & ((1LL << 12) - 1));
3557 // Same as ARM mode. FIXME: NEON?
3558 if (!Subtarget->hasVFP2())
3563 return V == (V & ((1LL << 8) - 1));
3567 /// isLegalAddressImmediate - Return true if the integer value can be used
3568 /// as the offset of the target addressing mode for load / store of the
3570 static bool isLegalAddressImmediate(int64_t V, EVT VT,
3571 const ARMSubtarget *Subtarget) {
3578 if (Subtarget->isThumb1Only())
3579 return isLegalT1AddressImmediate(V, VT);
3580 else if (Subtarget->isThumb2())
3581 return isLegalT2AddressImmediate(V, VT, Subtarget);
3586 switch (VT.getSimpleVT().SimpleTy) {
3587 default: return false;
3592 return V == (V & ((1LL << 12) - 1));
3595 return V == (V & ((1LL << 8) - 1));
3598 if (!Subtarget->hasVFP2()) // FIXME: NEON?
3603 return V == (V & ((1LL << 8) - 1));
3607 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
3609 int Scale = AM.Scale;
3613 switch (VT.getSimpleVT().SimpleTy) {
3614 default: return false;
3623 return Scale == 2 || Scale == 4 || Scale == 8;
3626 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
3630 // Note, we allow "void" uses (basically, uses that aren't loads or
3631 // stores), because arm allows folding a scale into many arithmetic
3632 // operations. This should be made more precise and revisited later.
3634 // Allow r << imm, but the imm has to be a multiple of two.
3635 if (Scale & 1) return false;
3636 return isPowerOf2_32(Scale);
3640 /// isLegalAddressingMode - Return true if the addressing mode represented
3641 /// by AM is legal for this target, for a load/store of the specified type.
3642 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
3643 const Type *Ty) const {
3644 EVT VT = getValueType(Ty, true);
3645 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
3648 // Can never fold addr of global into load/store.
3653 case 0: // no scale reg, must be "r+i" or "r", or "i".
3656 if (Subtarget->isThumb1Only())
3660 // ARM doesn't support any R+R*scale+imm addr modes.
3667 if (Subtarget->isThumb2())
3668 return isLegalT2ScaledAddressingMode(AM, VT);
3670 int Scale = AM.Scale;
3671 switch (VT.getSimpleVT().SimpleTy) {
3672 default: return false;
3676 if (Scale < 0) Scale = -Scale;
3680 return isPowerOf2_32(Scale & ~1);
3684 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
3689 // Note, we allow "void" uses (basically, uses that aren't loads or
3690 // stores), because arm allows folding a scale into many arithmetic
3691 // operations. This should be made more precise and revisited later.
3693 // Allow r << imm, but the imm has to be a multiple of two.
3694 if (Scale & 1) return false;
3695 return isPowerOf2_32(Scale);
3702 /// isLegalICmpImmediate - Return true if the specified immediate is legal
3703 /// icmp immediate, that is the target has icmp instructions which can compare
3704 /// a register against the immediate without having to materialize the
3705 /// immediate into a register.
3706 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
3707 if (!Subtarget->isThumb())
3708 return ARM_AM::getSOImmVal(Imm) != -1;
3709 if (Subtarget->isThumb2())
3710 return ARM_AM::getT2SOImmVal(Imm) != -1;
3711 return Imm >= 0 && Imm <= 255;
3714 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
3715 bool isSEXTLoad, SDValue &Base,
3716 SDValue &Offset, bool &isInc,
3717 SelectionDAG &DAG) {
3718 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
3721 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
3723 Base = Ptr->getOperand(0);
3724 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
3725 int RHSC = (int)RHS->getZExtValue();
3726 if (RHSC < 0 && RHSC > -256) {
3727 assert(Ptr->getOpcode() == ISD::ADD);
3729 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
3733 isInc = (Ptr->getOpcode() == ISD::ADD);
3734 Offset = Ptr->getOperand(1);
3736 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
3738 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
3739 int RHSC = (int)RHS->getZExtValue();
3740 if (RHSC < 0 && RHSC > -0x1000) {
3741 assert(Ptr->getOpcode() == ISD::ADD);
3743 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
3744 Base = Ptr->getOperand(0);
3749 if (Ptr->getOpcode() == ISD::ADD) {
3751 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
3752 if (ShOpcVal != ARM_AM::no_shift) {
3753 Base = Ptr->getOperand(1);
3754 Offset = Ptr->getOperand(0);
3756 Base = Ptr->getOperand(0);
3757 Offset = Ptr->getOperand(1);
3762 isInc = (Ptr->getOpcode() == ISD::ADD);
3763 Base = Ptr->getOperand(0);
3764 Offset = Ptr->getOperand(1);
3768 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
3772 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
3773 bool isSEXTLoad, SDValue &Base,
3774 SDValue &Offset, bool &isInc,
3775 SelectionDAG &DAG) {
3776 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
3779 Base = Ptr->getOperand(0);
3780 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
3781 int RHSC = (int)RHS->getZExtValue();
3782 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
3783 assert(Ptr->getOpcode() == ISD::ADD);
3785 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
3787 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
3788 isInc = Ptr->getOpcode() == ISD::ADD;
3789 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
3797 /// getPreIndexedAddressParts - returns true by value, base pointer and
3798 /// offset pointer and addressing mode by reference if the node's address
3799 /// can be legally represented as pre-indexed load / store address.
3801 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
3803 ISD::MemIndexedMode &AM,
3804 SelectionDAG &DAG) const {
3805 if (Subtarget->isThumb1Only())
3810 bool isSEXTLoad = false;
3811 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3812 Ptr = LD->getBasePtr();
3813 VT = LD->getMemoryVT();
3814 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
3815 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3816 Ptr = ST->getBasePtr();
3817 VT = ST->getMemoryVT();
3822 bool isLegal = false;
3823 if (Subtarget->isThumb2())
3824 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
3825 Offset, isInc, DAG);
3827 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
3828 Offset, isInc, DAG);
3832 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
3836 /// getPostIndexedAddressParts - returns true by value, base pointer and
3837 /// offset pointer and addressing mode by reference if this node can be
3838 /// combined with a load / store to form a post-indexed load / store.
3839 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
3842 ISD::MemIndexedMode &AM,
3843 SelectionDAG &DAG) const {
3844 if (Subtarget->isThumb1Only())
3849 bool isSEXTLoad = false;
3850 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3851 VT = LD->getMemoryVT();
3852 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
3853 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3854 VT = ST->getMemoryVT();
3859 bool isLegal = false;
3860 if (Subtarget->isThumb2())
3861 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
3864 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
3869 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
3873 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
3877 const SelectionDAG &DAG,
3878 unsigned Depth) const {
3879 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
3880 switch (Op.getOpcode()) {
3882 case ARMISD::CMOV: {
3883 // Bits are known zero/one if known on the LHS and RHS.
3884 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
3885 if (KnownZero == 0 && KnownOne == 0) return;
3887 APInt KnownZeroRHS, KnownOneRHS;
3888 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
3889 KnownZeroRHS, KnownOneRHS, Depth+1);
3890 KnownZero &= KnownZeroRHS;
3891 KnownOne &= KnownOneRHS;
3897 //===----------------------------------------------------------------------===//
3898 // ARM Inline Assembly Support
3899 //===----------------------------------------------------------------------===//
3901 /// getConstraintType - Given a constraint letter, return the type of
3902 /// constraint it is for this target.
3903 ARMTargetLowering::ConstraintType
3904 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
3905 if (Constraint.size() == 1) {
3906 switch (Constraint[0]) {
3908 case 'l': return C_RegisterClass;
3909 case 'w': return C_RegisterClass;
3912 return TargetLowering::getConstraintType(Constraint);
3915 std::pair<unsigned, const TargetRegisterClass*>
3916 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
3918 if (Constraint.size() == 1) {
3919 // GCC RS6000 Constraint Letters
3920 switch (Constraint[0]) {
3922 if (Subtarget->isThumb1Only())
3923 return std::make_pair(0U, ARM::tGPRRegisterClass);
3925 return std::make_pair(0U, ARM::GPRRegisterClass);
3927 return std::make_pair(0U, ARM::GPRRegisterClass);
3930 return std::make_pair(0U, ARM::SPRRegisterClass);
3932 return std::make_pair(0U, ARM::DPRRegisterClass);
3936 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3939 std::vector<unsigned> ARMTargetLowering::
3940 getRegClassForInlineAsmConstraint(const std::string &Constraint,
3942 if (Constraint.size() != 1)
3943 return std::vector<unsigned>();
3945 switch (Constraint[0]) { // GCC ARM Constraint Letters
3948 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
3949 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
3952 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
3953 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
3954 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
3955 ARM::R12, ARM::LR, 0);
3958 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
3959 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
3960 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
3961 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
3962 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
3963 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
3964 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
3965 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
3967 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
3968 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
3969 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
3970 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
3974 return std::vector<unsigned>();
3977 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3978 /// vector. If it is invalid, don't add anything to Ops.
3979 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
3982 std::vector<SDValue>&Ops,
3983 SelectionDAG &DAG) const {
3984 SDValue Result(0, 0);
3986 switch (Constraint) {
3988 case 'I': case 'J': case 'K': case 'L':
3989 case 'M': case 'N': case 'O':
3990 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3994 int64_t CVal64 = C->getSExtValue();
3995 int CVal = (int) CVal64;
3996 // None of these constraints allow values larger than 32 bits. Check
3997 // that the value fits in an int.
4001 switch (Constraint) {
4003 if (Subtarget->isThumb1Only()) {
4004 // This must be a constant between 0 and 255, for ADD
4006 if (CVal >= 0 && CVal <= 255)
4008 } else if (Subtarget->isThumb2()) {
4009 // A constant that can be used as an immediate value in a
4010 // data-processing instruction.
4011 if (ARM_AM::getT2SOImmVal(CVal) != -1)
4014 // A constant that can be used as an immediate value in a
4015 // data-processing instruction.
4016 if (ARM_AM::getSOImmVal(CVal) != -1)
4022 if (Subtarget->isThumb()) { // FIXME thumb2
4023 // This must be a constant between -255 and -1, for negated ADD
4024 // immediates. This can be used in GCC with an "n" modifier that
4025 // prints the negated value, for use with SUB instructions. It is
4026 // not useful otherwise but is implemented for compatibility.
4027 if (CVal >= -255 && CVal <= -1)
4030 // This must be a constant between -4095 and 4095. It is not clear
4031 // what this constraint is intended for. Implemented for
4032 // compatibility with GCC.
4033 if (CVal >= -4095 && CVal <= 4095)
4039 if (Subtarget->isThumb1Only()) {
4040 // A 32-bit value where only one byte has a nonzero value. Exclude
4041 // zero to match GCC. This constraint is used by GCC internally for
4042 // constants that can be loaded with a move/shift combination.
4043 // It is not useful otherwise but is implemented for compatibility.
4044 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
4046 } else if (Subtarget->isThumb2()) {
4047 // A constant whose bitwise inverse can be used as an immediate
4048 // value in a data-processing instruction. This can be used in GCC
4049 // with a "B" modifier that prints the inverted value, for use with
4050 // BIC and MVN instructions. It is not useful otherwise but is
4051 // implemented for compatibility.
4052 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
4055 // A constant whose bitwise inverse can be used as an immediate
4056 // value in a data-processing instruction. This can be used in GCC
4057 // with a "B" modifier that prints the inverted value, for use with
4058 // BIC and MVN instructions. It is not useful otherwise but is
4059 // implemented for compatibility.
4060 if (ARM_AM::getSOImmVal(~CVal) != -1)
4066 if (Subtarget->isThumb1Only()) {
4067 // This must be a constant between -7 and 7,
4068 // for 3-operand ADD/SUB immediate instructions.
4069 if (CVal >= -7 && CVal < 7)
4071 } else if (Subtarget->isThumb2()) {
4072 // A constant whose negation can be used as an immediate value in a
4073 // data-processing instruction. This can be used in GCC with an "n"
4074 // modifier that prints the negated value, for use with SUB
4075 // instructions. It is not useful otherwise but is implemented for
4077 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
4080 // A constant whose negation can be used as an immediate value in a
4081 // data-processing instruction. This can be used in GCC with an "n"
4082 // modifier that prints the negated value, for use with SUB
4083 // instructions. It is not useful otherwise but is implemented for
4085 if (ARM_AM::getSOImmVal(-CVal) != -1)
4091 if (Subtarget->isThumb()) { // FIXME thumb2
4092 // This must be a multiple of 4 between 0 and 1020, for
4093 // ADD sp + immediate.
4094 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
4097 // A power of two or a constant between 0 and 32. This is used in
4098 // GCC for the shift amount on shifted register operands, but it is
4099 // useful in general for any shift amounts.
4100 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
4106 if (Subtarget->isThumb()) { // FIXME thumb2
4107 // This must be a constant between 0 and 31, for shift amounts.
4108 if (CVal >= 0 && CVal <= 31)
4114 if (Subtarget->isThumb()) { // FIXME thumb2
4115 // This must be a multiple of 4 between -508 and 508, for
4116 // ADD/SUB sp = sp + immediate.
4117 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
4122 Result = DAG.getTargetConstant(CVal, Op.getValueType());
4126 if (Result.getNode()) {
4127 Ops.push_back(Result);
4130 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,
4135 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
4136 // The ARM target isn't yet aware of offsets.
4140 int ARM::getVFPf32Imm(const APFloat &FPImm) {
4141 APInt Imm = FPImm.bitcastToAPInt();
4142 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
4143 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127
4144 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits
4146 // We can handle 4 bits of mantissa.
4147 // mantissa = (16+UInt(e:f:g:h))/16.
4148 if (Mantissa & 0x7ffff)
4151 if ((Mantissa & 0xf) != Mantissa)
4154 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
4155 if (Exp < -3 || Exp > 4)
4157 Exp = ((Exp+3) & 0x7) ^ 4;
4159 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
4162 int ARM::getVFPf64Imm(const APFloat &FPImm) {
4163 APInt Imm = FPImm.bitcastToAPInt();
4164 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
4165 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
4166 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffLL;
4168 // We can handle 4 bits of mantissa.
4169 // mantissa = (16+UInt(e:f:g:h))/16.
4170 if (Mantissa & 0xffffffffffffLL)
4173 if ((Mantissa & 0xf) != Mantissa)
4176 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
4177 if (Exp < -3 || Exp > 4)
4179 Exp = ((Exp+3) & 0x7) ^ 4;
4181 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
4184 /// isFPImmLegal - Returns true if the target can instruction select the
4185 /// specified FP immediate natively. If false, the legalizer will
4186 /// materialize the FP immediate as a load from a constant pool.
4187 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
4188 if (!Subtarget->hasVFP3())
4191 return ARM::getVFPf32Imm(Imm) != -1;
4193 return ARM::getVFPf64Imm(Imm) != -1;