1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "ARMISelLowering.h"
16 #include "ARMCallingConv.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMPerfectShuffle.h"
20 #include "ARMSubtarget.h"
21 #include "ARMTargetMachine.h"
22 #include "ARMTargetObjectFile.h"
23 #include "MCTargetDesc/ARMAddressingModes.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/CodeGen/CallingConvLower.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineBasicBlock.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SelectionDAG.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalValue.h"
41 #include "llvm/IR/IRBuilder.h"
42 #include "llvm/IR/Instruction.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/IntrinsicInst.h"
45 #include "llvm/IR/Intrinsics.h"
46 #include "llvm/IR/Type.h"
47 #include "llvm/MC/MCSectionMachO.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Support/raw_ostream.h"
53 #include "llvm/Target/TargetOptions.h"
57 #define DEBUG_TYPE "arm-isel"
59 STATISTIC(NumTailCalls, "Number of tail calls");
60 STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt");
61 STATISTIC(NumLoopByVals, "Number of loops generated for byval arguments");
64 ARMInterworking("arm-interworking", cl::Hidden,
65 cl::desc("Enable / disable ARM interworking (for debugging only)"),
69 class ARMCCState : public CCState {
71 ARMCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
72 SmallVectorImpl<CCValAssign> &locs, LLVMContext &C,
74 : CCState(CC, isVarArg, MF, locs, C) {
75 assert(((PC == Call) || (PC == Prologue)) &&
76 "ARMCCState users must specify whether their context is call"
77 "or prologue generation.");
83 // The APCS parameter registers.
84 static const MCPhysReg GPRArgRegs[] = {
85 ARM::R0, ARM::R1, ARM::R2, ARM::R3
88 void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT,
89 MVT PromotedBitwiseVT) {
90 if (VT != PromotedLdStVT) {
91 setOperationAction(ISD::LOAD, VT, Promote);
92 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
94 setOperationAction(ISD::STORE, VT, Promote);
95 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
98 MVT ElemTy = VT.getVectorElementType();
99 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
100 setOperationAction(ISD::SETCC, VT, Custom);
101 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
102 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
103 if (ElemTy == MVT::i32) {
104 setOperationAction(ISD::SINT_TO_FP, VT, Custom);
105 setOperationAction(ISD::UINT_TO_FP, VT, Custom);
106 setOperationAction(ISD::FP_TO_SINT, VT, Custom);
107 setOperationAction(ISD::FP_TO_UINT, VT, Custom);
109 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
110 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
111 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
112 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
114 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
115 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
116 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
117 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
118 setOperationAction(ISD::SELECT, VT, Expand);
119 setOperationAction(ISD::SELECT_CC, VT, Expand);
120 setOperationAction(ISD::VSELECT, VT, Expand);
121 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
122 if (VT.isInteger()) {
123 setOperationAction(ISD::SHL, VT, Custom);
124 setOperationAction(ISD::SRA, VT, Custom);
125 setOperationAction(ISD::SRL, VT, Custom);
128 // Promote all bit-wise operations.
129 if (VT.isInteger() && VT != PromotedBitwiseVT) {
130 setOperationAction(ISD::AND, VT, Promote);
131 AddPromotedToType (ISD::AND, VT, PromotedBitwiseVT);
132 setOperationAction(ISD::OR, VT, Promote);
133 AddPromotedToType (ISD::OR, VT, PromotedBitwiseVT);
134 setOperationAction(ISD::XOR, VT, Promote);
135 AddPromotedToType (ISD::XOR, VT, PromotedBitwiseVT);
138 // Neon does not support vector divide/remainder operations.
139 setOperationAction(ISD::SDIV, VT, Expand);
140 setOperationAction(ISD::UDIV, VT, Expand);
141 setOperationAction(ISD::FDIV, VT, Expand);
142 setOperationAction(ISD::SREM, VT, Expand);
143 setOperationAction(ISD::UREM, VT, Expand);
144 setOperationAction(ISD::FREM, VT, Expand);
146 if (VT.isInteger()) {
147 setOperationAction(ISD::SABSDIFF, VT, Legal);
148 setOperationAction(ISD::UABSDIFF, VT, Legal);
150 if (!VT.isFloatingPoint() &&
151 VT != MVT::v2i64 && VT != MVT::v1i64)
152 for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
153 setOperationAction(Opcode, VT, Legal);
157 void ARMTargetLowering::addDRTypeForNEON(MVT VT) {
158 addRegisterClass(VT, &ARM::DPRRegClass);
159 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
162 void ARMTargetLowering::addQRTypeForNEON(MVT VT) {
163 addRegisterClass(VT, &ARM::DPairRegClass);
164 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
167 ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
168 const ARMSubtarget &STI)
169 : TargetLowering(TM), Subtarget(&STI) {
170 RegInfo = Subtarget->getRegisterInfo();
171 Itins = Subtarget->getInstrItineraryData();
173 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
175 if (Subtarget->isTargetMachO()) {
176 // Uses VFP for Thumb libfuncs if available.
177 if (Subtarget->isThumb() && Subtarget->hasVFP2() &&
178 Subtarget->hasARMOps() && !Subtarget->useSoftFloat()) {
179 static const struct {
180 const RTLIB::Libcall Op;
181 const char * const Name;
182 const ISD::CondCode Cond;
184 // Single-precision floating-point arithmetic.
185 { RTLIB::ADD_F32, "__addsf3vfp", ISD::SETCC_INVALID },
186 { RTLIB::SUB_F32, "__subsf3vfp", ISD::SETCC_INVALID },
187 { RTLIB::MUL_F32, "__mulsf3vfp", ISD::SETCC_INVALID },
188 { RTLIB::DIV_F32, "__divsf3vfp", ISD::SETCC_INVALID },
190 // Double-precision floating-point arithmetic.
191 { RTLIB::ADD_F64, "__adddf3vfp", ISD::SETCC_INVALID },
192 { RTLIB::SUB_F64, "__subdf3vfp", ISD::SETCC_INVALID },
193 { RTLIB::MUL_F64, "__muldf3vfp", ISD::SETCC_INVALID },
194 { RTLIB::DIV_F64, "__divdf3vfp", ISD::SETCC_INVALID },
196 // Single-precision comparisons.
197 { RTLIB::OEQ_F32, "__eqsf2vfp", ISD::SETNE },
198 { RTLIB::UNE_F32, "__nesf2vfp", ISD::SETNE },
199 { RTLIB::OLT_F32, "__ltsf2vfp", ISD::SETNE },
200 { RTLIB::OLE_F32, "__lesf2vfp", ISD::SETNE },
201 { RTLIB::OGE_F32, "__gesf2vfp", ISD::SETNE },
202 { RTLIB::OGT_F32, "__gtsf2vfp", ISD::SETNE },
203 { RTLIB::UO_F32, "__unordsf2vfp", ISD::SETNE },
204 { RTLIB::O_F32, "__unordsf2vfp", ISD::SETEQ },
206 // Double-precision comparisons.
207 { RTLIB::OEQ_F64, "__eqdf2vfp", ISD::SETNE },
208 { RTLIB::UNE_F64, "__nedf2vfp", ISD::SETNE },
209 { RTLIB::OLT_F64, "__ltdf2vfp", ISD::SETNE },
210 { RTLIB::OLE_F64, "__ledf2vfp", ISD::SETNE },
211 { RTLIB::OGE_F64, "__gedf2vfp", ISD::SETNE },
212 { RTLIB::OGT_F64, "__gtdf2vfp", ISD::SETNE },
213 { RTLIB::UO_F64, "__unorddf2vfp", ISD::SETNE },
214 { RTLIB::O_F64, "__unorddf2vfp", ISD::SETEQ },
216 // Floating-point to integer conversions.
217 // i64 conversions are done via library routines even when generating VFP
218 // instructions, so use the same ones.
219 { RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp", ISD::SETCC_INVALID },
220 { RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp", ISD::SETCC_INVALID },
221 { RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp", ISD::SETCC_INVALID },
222 { RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp", ISD::SETCC_INVALID },
224 // Conversions between floating types.
225 { RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp", ISD::SETCC_INVALID },
226 { RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp", ISD::SETCC_INVALID },
228 // Integer to floating-point conversions.
229 // i64 conversions are done via library routines even when generating VFP
230 // instructions, so use the same ones.
231 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
232 // e.g., __floatunsidf vs. __floatunssidfvfp.
233 { RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp", ISD::SETCC_INVALID },
234 { RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp", ISD::SETCC_INVALID },
235 { RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp", ISD::SETCC_INVALID },
236 { RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp", ISD::SETCC_INVALID },
239 for (const auto &LC : LibraryCalls) {
240 setLibcallName(LC.Op, LC.Name);
241 if (LC.Cond != ISD::SETCC_INVALID)
242 setCmpLibcallCC(LC.Op, LC.Cond);
247 // These libcalls are not available in 32-bit.
248 setLibcallName(RTLIB::SHL_I128, nullptr);
249 setLibcallName(RTLIB::SRL_I128, nullptr);
250 setLibcallName(RTLIB::SRA_I128, nullptr);
252 if (Subtarget->isAAPCS_ABI() && !Subtarget->isTargetMachO() &&
253 !Subtarget->isTargetWindows()) {
254 static const struct {
255 const RTLIB::Libcall Op;
256 const char * const Name;
257 const CallingConv::ID CC;
258 const ISD::CondCode Cond;
260 // Double-precision floating-point arithmetic helper functions
261 // RTABI chapter 4.1.2, Table 2
262 { RTLIB::ADD_F64, "__aeabi_dadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
263 { RTLIB::DIV_F64, "__aeabi_ddiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
264 { RTLIB::MUL_F64, "__aeabi_dmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
265 { RTLIB::SUB_F64, "__aeabi_dsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
267 // Double-precision floating-point comparison helper functions
268 // RTABI chapter 4.1.2, Table 3
269 { RTLIB::OEQ_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
270 { RTLIB::UNE_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
271 { RTLIB::OLT_F64, "__aeabi_dcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
272 { RTLIB::OLE_F64, "__aeabi_dcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
273 { RTLIB::OGE_F64, "__aeabi_dcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
274 { RTLIB::OGT_F64, "__aeabi_dcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
275 { RTLIB::UO_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
276 { RTLIB::O_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ },
278 // Single-precision floating-point arithmetic helper functions
279 // RTABI chapter 4.1.2, Table 4
280 { RTLIB::ADD_F32, "__aeabi_fadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
281 { RTLIB::DIV_F32, "__aeabi_fdiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
282 { RTLIB::MUL_F32, "__aeabi_fmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
283 { RTLIB::SUB_F32, "__aeabi_fsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
285 // Single-precision floating-point comparison helper functions
286 // RTABI chapter 4.1.2, Table 5
287 { RTLIB::OEQ_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
288 { RTLIB::UNE_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
289 { RTLIB::OLT_F32, "__aeabi_fcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
290 { RTLIB::OLE_F32, "__aeabi_fcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
291 { RTLIB::OGE_F32, "__aeabi_fcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
292 { RTLIB::OGT_F32, "__aeabi_fcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
293 { RTLIB::UO_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
294 { RTLIB::O_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ },
296 // Floating-point to integer conversions.
297 // RTABI chapter 4.1.2, Table 6
298 { RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
299 { RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
300 { RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
301 { RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
302 { RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
303 { RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
304 { RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
305 { RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
307 // Conversions between floating types.
308 // RTABI chapter 4.1.2, Table 7
309 { RTLIB::FPROUND_F64_F32, "__aeabi_d2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
310 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
311 { RTLIB::FPEXT_F32_F64, "__aeabi_f2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
313 // Integer to floating-point conversions.
314 // RTABI chapter 4.1.2, Table 8
315 { RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
316 { RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
317 { RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
318 { RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
319 { RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
320 { RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
321 { RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
322 { RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
324 // Long long helper functions
325 // RTABI chapter 4.2, Table 9
326 { RTLIB::MUL_I64, "__aeabi_lmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
327 { RTLIB::SHL_I64, "__aeabi_llsl", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
328 { RTLIB::SRL_I64, "__aeabi_llsr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
329 { RTLIB::SRA_I64, "__aeabi_lasr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
331 // Integer division functions
332 // RTABI chapter 4.3.1
333 { RTLIB::SDIV_I8, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
334 { RTLIB::SDIV_I16, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
335 { RTLIB::SDIV_I32, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
336 { RTLIB::SDIV_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
337 { RTLIB::UDIV_I8, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
338 { RTLIB::UDIV_I16, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
339 { RTLIB::UDIV_I32, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
340 { RTLIB::UDIV_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
343 // RTABI chapter 4.3.4
344 { RTLIB::MEMCPY, "__aeabi_memcpy", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
345 { RTLIB::MEMMOVE, "__aeabi_memmove", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
346 { RTLIB::MEMSET, "__aeabi_memset", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
349 for (const auto &LC : LibraryCalls) {
350 setLibcallName(LC.Op, LC.Name);
351 setLibcallCallingConv(LC.Op, LC.CC);
352 if (LC.Cond != ISD::SETCC_INVALID)
353 setCmpLibcallCC(LC.Op, LC.Cond);
357 if (Subtarget->isTargetWindows()) {
358 static const struct {
359 const RTLIB::Libcall Op;
360 const char * const Name;
361 const CallingConv::ID CC;
363 { RTLIB::FPTOSINT_F32_I64, "__stoi64", CallingConv::ARM_AAPCS_VFP },
364 { RTLIB::FPTOSINT_F64_I64, "__dtoi64", CallingConv::ARM_AAPCS_VFP },
365 { RTLIB::FPTOUINT_F32_I64, "__stou64", CallingConv::ARM_AAPCS_VFP },
366 { RTLIB::FPTOUINT_F64_I64, "__dtou64", CallingConv::ARM_AAPCS_VFP },
367 { RTLIB::SINTTOFP_I64_F32, "__i64tos", CallingConv::ARM_AAPCS_VFP },
368 { RTLIB::SINTTOFP_I64_F64, "__i64tod", CallingConv::ARM_AAPCS_VFP },
369 { RTLIB::UINTTOFP_I64_F32, "__u64tos", CallingConv::ARM_AAPCS_VFP },
370 { RTLIB::UINTTOFP_I64_F64, "__u64tod", CallingConv::ARM_AAPCS_VFP },
372 { RTLIB::SDIV_I32, "__rt_sdiv", CallingConv::ARM_AAPCS_VFP },
373 { RTLIB::UDIV_I32, "__rt_udiv", CallingConv::ARM_AAPCS_VFP },
374 { RTLIB::SDIV_I64, "__rt_sdiv64", CallingConv::ARM_AAPCS_VFP },
375 { RTLIB::UDIV_I64, "__rt_udiv64", CallingConv::ARM_AAPCS_VFP },
378 for (const auto &LC : LibraryCalls) {
379 setLibcallName(LC.Op, LC.Name);
380 setLibcallCallingConv(LC.Op, LC.CC);
384 // Use divmod compiler-rt calls for iOS 5.0 and later.
385 if (Subtarget->getTargetTriple().isiOS() &&
386 !Subtarget->getTargetTriple().isOSVersionLT(5, 0)) {
387 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
388 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
391 // The half <-> float conversion functions are always soft-float, but are
392 // needed for some targets which use a hard-float calling convention by
394 if (Subtarget->isAAPCS_ABI()) {
395 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_AAPCS);
396 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_AAPCS);
397 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_AAPCS);
399 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_APCS);
400 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_APCS);
401 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_APCS);
404 if (Subtarget->isThumb1Only())
405 addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
407 addRegisterClass(MVT::i32, &ARM::GPRRegClass);
408 if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2() &&
409 !Subtarget->isThumb1Only()) {
410 addRegisterClass(MVT::f32, &ARM::SPRRegClass);
411 addRegisterClass(MVT::f64, &ARM::DPRRegClass);
414 for (MVT VT : MVT::vector_valuetypes()) {
415 for (MVT InnerVT : MVT::vector_valuetypes()) {
416 setTruncStoreAction(VT, InnerVT, Expand);
417 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
418 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
419 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
422 setOperationAction(ISD::MULHS, VT, Expand);
423 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
424 setOperationAction(ISD::MULHU, VT, Expand);
425 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
427 setOperationAction(ISD::BSWAP, VT, Expand);
430 setOperationAction(ISD::ConstantFP, MVT::f32, Custom);
431 setOperationAction(ISD::ConstantFP, MVT::f64, Custom);
433 setOperationAction(ISD::READ_REGISTER, MVT::i64, Custom);
434 setOperationAction(ISD::WRITE_REGISTER, MVT::i64, Custom);
436 if (Subtarget->hasNEON()) {
437 addDRTypeForNEON(MVT::v2f32);
438 addDRTypeForNEON(MVT::v8i8);
439 addDRTypeForNEON(MVT::v4i16);
440 addDRTypeForNEON(MVT::v2i32);
441 addDRTypeForNEON(MVT::v1i64);
443 addQRTypeForNEON(MVT::v4f32);
444 addQRTypeForNEON(MVT::v2f64);
445 addQRTypeForNEON(MVT::v16i8);
446 addQRTypeForNEON(MVT::v8i16);
447 addQRTypeForNEON(MVT::v4i32);
448 addQRTypeForNEON(MVT::v2i64);
450 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
451 // neither Neon nor VFP support any arithmetic operations on it.
452 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
453 // supported for v4f32.
454 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
455 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
456 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
457 // FIXME: Code duplication: FDIV and FREM are expanded always, see
458 // ARMTargetLowering::addTypeForNEON method for details.
459 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
460 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
461 // FIXME: Create unittest.
462 // In another words, find a way when "copysign" appears in DAG with vector
464 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
465 // FIXME: Code duplication: SETCC has custom operation action, see
466 // ARMTargetLowering::addTypeForNEON method for details.
467 setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
468 // FIXME: Create unittest for FNEG and for FABS.
469 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
470 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
471 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
472 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
473 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
474 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
475 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
476 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
477 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
478 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
479 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
480 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
481 // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR.
482 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
483 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
484 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
485 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
486 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
487 setOperationAction(ISD::FMA, MVT::v2f64, Expand);
489 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
490 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
491 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
492 setOperationAction(ISD::FPOWI, MVT::v4f32, Expand);
493 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
494 setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
495 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
496 setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
497 setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
498 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
499 setOperationAction(ISD::FCEIL, MVT::v4f32, Expand);
500 setOperationAction(ISD::FTRUNC, MVT::v4f32, Expand);
501 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
502 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
503 setOperationAction(ISD::FFLOOR, MVT::v4f32, Expand);
505 // Mark v2f32 intrinsics.
506 setOperationAction(ISD::FSQRT, MVT::v2f32, Expand);
507 setOperationAction(ISD::FSIN, MVT::v2f32, Expand);
508 setOperationAction(ISD::FCOS, MVT::v2f32, Expand);
509 setOperationAction(ISD::FPOWI, MVT::v2f32, Expand);
510 setOperationAction(ISD::FPOW, MVT::v2f32, Expand);
511 setOperationAction(ISD::FLOG, MVT::v2f32, Expand);
512 setOperationAction(ISD::FLOG2, MVT::v2f32, Expand);
513 setOperationAction(ISD::FLOG10, MVT::v2f32, Expand);
514 setOperationAction(ISD::FEXP, MVT::v2f32, Expand);
515 setOperationAction(ISD::FEXP2, MVT::v2f32, Expand);
516 setOperationAction(ISD::FCEIL, MVT::v2f32, Expand);
517 setOperationAction(ISD::FTRUNC, MVT::v2f32, Expand);
518 setOperationAction(ISD::FRINT, MVT::v2f32, Expand);
519 setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Expand);
520 setOperationAction(ISD::FFLOOR, MVT::v2f32, Expand);
522 // Neon does not support some operations on v1i64 and v2i64 types.
523 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
524 // Custom handling for some quad-vector types to detect VMULL.
525 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
526 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
527 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
528 // Custom handling for some vector types to avoid expensive expansions
529 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
530 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
531 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
532 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
533 setOperationAction(ISD::SETCC, MVT::v1i64, Expand);
534 setOperationAction(ISD::SETCC, MVT::v2i64, Expand);
535 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
536 // a destination type that is wider than the source, and nor does
537 // it have a FP_TO_[SU]INT instruction with a narrower destination than
539 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
540 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
541 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
542 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
544 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
545 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand);
547 // NEON does not have single instruction CTPOP for vectors with element
548 // types wider than 8-bits. However, custom lowering can leverage the
549 // v8i8/v16i8 vcnt instruction.
550 setOperationAction(ISD::CTPOP, MVT::v2i32, Custom);
551 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
552 setOperationAction(ISD::CTPOP, MVT::v4i16, Custom);
553 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
555 // NEON does not have single instruction CTTZ for vectors.
556 setOperationAction(ISD::CTTZ, MVT::v8i8, Custom);
557 setOperationAction(ISD::CTTZ, MVT::v4i16, Custom);
558 setOperationAction(ISD::CTTZ, MVT::v2i32, Custom);
559 setOperationAction(ISD::CTTZ, MVT::v1i64, Custom);
561 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
562 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
563 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
564 setOperationAction(ISD::CTTZ, MVT::v2i64, Custom);
566 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i8, Custom);
567 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i16, Custom);
568 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i32, Custom);
569 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v1i64, Custom);
571 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
572 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
573 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
574 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
576 // NEON only has FMA instructions as of VFP4.
577 if (!Subtarget->hasVFP4()) {
578 setOperationAction(ISD::FMA, MVT::v2f32, Expand);
579 setOperationAction(ISD::FMA, MVT::v4f32, Expand);
582 setTargetDAGCombine(ISD::INTRINSIC_VOID);
583 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
584 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
585 setTargetDAGCombine(ISD::SHL);
586 setTargetDAGCombine(ISD::SRL);
587 setTargetDAGCombine(ISD::SRA);
588 setTargetDAGCombine(ISD::SIGN_EXTEND);
589 setTargetDAGCombine(ISD::ZERO_EXTEND);
590 setTargetDAGCombine(ISD::ANY_EXTEND);
591 setTargetDAGCombine(ISD::BUILD_VECTOR);
592 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
593 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
594 setTargetDAGCombine(ISD::STORE);
595 setTargetDAGCombine(ISD::FP_TO_SINT);
596 setTargetDAGCombine(ISD::FP_TO_UINT);
597 setTargetDAGCombine(ISD::FDIV);
598 setTargetDAGCombine(ISD::LOAD);
600 // It is legal to extload from v4i8 to v4i16 or v4i32.
601 for (MVT Ty : {MVT::v8i8, MVT::v4i8, MVT::v2i8, MVT::v4i16, MVT::v2i16,
603 for (MVT VT : MVT::integer_vector_valuetypes()) {
604 setLoadExtAction(ISD::EXTLOAD, VT, Ty, Legal);
605 setLoadExtAction(ISD::ZEXTLOAD, VT, Ty, Legal);
606 setLoadExtAction(ISD::SEXTLOAD, VT, Ty, Legal);
611 // ARM and Thumb2 support UMLAL/SMLAL.
612 if (!Subtarget->isThumb1Only())
613 setTargetDAGCombine(ISD::ADDC);
615 if (Subtarget->isFPOnlySP()) {
616 // When targeting a floating-point unit with only single-precision
617 // operations, f64 is legal for the few double-precision instructions which
618 // are present However, no double-precision operations other than moves,
619 // loads and stores are provided by the hardware.
620 setOperationAction(ISD::FADD, MVT::f64, Expand);
621 setOperationAction(ISD::FSUB, MVT::f64, Expand);
622 setOperationAction(ISD::FMUL, MVT::f64, Expand);
623 setOperationAction(ISD::FMA, MVT::f64, Expand);
624 setOperationAction(ISD::FDIV, MVT::f64, Expand);
625 setOperationAction(ISD::FREM, MVT::f64, Expand);
626 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
627 setOperationAction(ISD::FGETSIGN, MVT::f64, Expand);
628 setOperationAction(ISD::FNEG, MVT::f64, Expand);
629 setOperationAction(ISD::FABS, MVT::f64, Expand);
630 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
631 setOperationAction(ISD::FSIN, MVT::f64, Expand);
632 setOperationAction(ISD::FCOS, MVT::f64, Expand);
633 setOperationAction(ISD::FPOWI, MVT::f64, Expand);
634 setOperationAction(ISD::FPOW, MVT::f64, Expand);
635 setOperationAction(ISD::FLOG, MVT::f64, Expand);
636 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
637 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
638 setOperationAction(ISD::FEXP, MVT::f64, Expand);
639 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
640 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
641 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
642 setOperationAction(ISD::FRINT, MVT::f64, Expand);
643 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
644 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
645 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
646 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
647 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
648 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
649 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Custom);
650 setOperationAction(ISD::FP_TO_UINT, MVT::f64, Custom);
651 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
652 setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom);
655 computeRegisterProperties(Subtarget->getRegisterInfo());
657 // ARM does not have floating-point extending loads.
658 for (MVT VT : MVT::fp_valuetypes()) {
659 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
660 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
663 // ... or truncating stores
664 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
665 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
666 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
668 // ARM does not have i1 sign extending load.
669 for (MVT VT : MVT::integer_valuetypes())
670 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
672 // ARM supports all 4 flavors of integer indexed load / store.
673 if (!Subtarget->isThumb1Only()) {
674 for (unsigned im = (unsigned)ISD::PRE_INC;
675 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
676 setIndexedLoadAction(im, MVT::i1, Legal);
677 setIndexedLoadAction(im, MVT::i8, Legal);
678 setIndexedLoadAction(im, MVT::i16, Legal);
679 setIndexedLoadAction(im, MVT::i32, Legal);
680 setIndexedStoreAction(im, MVT::i1, Legal);
681 setIndexedStoreAction(im, MVT::i8, Legal);
682 setIndexedStoreAction(im, MVT::i16, Legal);
683 setIndexedStoreAction(im, MVT::i32, Legal);
687 setOperationAction(ISD::SADDO, MVT::i32, Custom);
688 setOperationAction(ISD::UADDO, MVT::i32, Custom);
689 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
690 setOperationAction(ISD::USUBO, MVT::i32, Custom);
692 // i64 operation support.
693 setOperationAction(ISD::MUL, MVT::i64, Expand);
694 setOperationAction(ISD::MULHU, MVT::i32, Expand);
695 if (Subtarget->isThumb1Only()) {
696 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
697 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
699 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
700 || (Subtarget->isThumb2() && !Subtarget->hasThumb2DSP()))
701 setOperationAction(ISD::MULHS, MVT::i32, Expand);
703 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
704 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
705 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
706 setOperationAction(ISD::SRL, MVT::i64, Custom);
707 setOperationAction(ISD::SRA, MVT::i64, Custom);
709 if (!Subtarget->isThumb1Only()) {
710 // FIXME: We should do this for Thumb1 as well.
711 setOperationAction(ISD::ADDC, MVT::i32, Custom);
712 setOperationAction(ISD::ADDE, MVT::i32, Custom);
713 setOperationAction(ISD::SUBC, MVT::i32, Custom);
714 setOperationAction(ISD::SUBE, MVT::i32, Custom);
717 // ARM does not have ROTL.
718 setOperationAction(ISD::ROTL, MVT::i32, Expand);
719 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
720 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
721 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
722 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
724 // These just redirect to CTTZ and CTLZ on ARM.
725 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i32 , Expand);
726 setOperationAction(ISD::CTLZ_ZERO_UNDEF , MVT::i32 , Expand);
728 // @llvm.readcyclecounter requires the Performance Monitors extension.
729 // Default to the 0 expansion on unsupported platforms.
730 // FIXME: Technically there are older ARM CPUs that have
731 // implementation-specific ways of obtaining this information.
732 if (Subtarget->hasPerfMon())
733 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
735 // Only ARMv6 has BSWAP.
736 if (!Subtarget->hasV6Ops())
737 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
739 if (!(Subtarget->hasDivide() && Subtarget->isThumb2()) &&
740 !(Subtarget->hasDivideInARMMode() && !Subtarget->isThumb())) {
741 // These are expanded into libcalls if the cpu doesn't have HW divider.
742 setOperationAction(ISD::SDIV, MVT::i32, Expand);
743 setOperationAction(ISD::UDIV, MVT::i32, Expand);
746 setOperationAction(ISD::SREM, MVT::i32, Expand);
747 setOperationAction(ISD::UREM, MVT::i32, Expand);
748 // Register based DivRem for AEABI (RTABI 4.2)
749 if (Subtarget->isTargetAEABI() || Subtarget->isTargetAndroid()) {
750 setOperationAction(ISD::SREM, MVT::i64, Custom);
751 setOperationAction(ISD::UREM, MVT::i64, Custom);
753 setLibcallName(RTLIB::SDIVREM_I8, "__aeabi_idivmod");
754 setLibcallName(RTLIB::SDIVREM_I16, "__aeabi_idivmod");
755 setLibcallName(RTLIB::SDIVREM_I32, "__aeabi_idivmod");
756 setLibcallName(RTLIB::SDIVREM_I64, "__aeabi_ldivmod");
757 setLibcallName(RTLIB::UDIVREM_I8, "__aeabi_uidivmod");
758 setLibcallName(RTLIB::UDIVREM_I16, "__aeabi_uidivmod");
759 setLibcallName(RTLIB::UDIVREM_I32, "__aeabi_uidivmod");
760 setLibcallName(RTLIB::UDIVREM_I64, "__aeabi_uldivmod");
762 setLibcallCallingConv(RTLIB::SDIVREM_I8, CallingConv::ARM_AAPCS);
763 setLibcallCallingConv(RTLIB::SDIVREM_I16, CallingConv::ARM_AAPCS);
764 setLibcallCallingConv(RTLIB::SDIVREM_I32, CallingConv::ARM_AAPCS);
765 setLibcallCallingConv(RTLIB::SDIVREM_I64, CallingConv::ARM_AAPCS);
766 setLibcallCallingConv(RTLIB::UDIVREM_I8, CallingConv::ARM_AAPCS);
767 setLibcallCallingConv(RTLIB::UDIVREM_I16, CallingConv::ARM_AAPCS);
768 setLibcallCallingConv(RTLIB::UDIVREM_I32, CallingConv::ARM_AAPCS);
769 setLibcallCallingConv(RTLIB::UDIVREM_I64, CallingConv::ARM_AAPCS);
771 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
772 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
774 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
775 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
778 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
779 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
780 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
781 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
782 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
784 setOperationAction(ISD::TRAP, MVT::Other, Legal);
786 // Use the default implementation.
787 setOperationAction(ISD::VASTART, MVT::Other, Custom);
788 setOperationAction(ISD::VAARG, MVT::Other, Expand);
789 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
790 setOperationAction(ISD::VAEND, MVT::Other, Expand);
791 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
792 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
794 if (!Subtarget->isTargetMachO()) {
795 // Non-MachO platforms may return values in these registers via the
796 // personality function.
797 setExceptionPointerRegister(ARM::R0);
798 setExceptionSelectorRegister(ARM::R1);
801 if (Subtarget->getTargetTriple().isWindowsItaniumEnvironment())
802 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
804 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
806 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
807 // the default expansion. If we are targeting a single threaded system,
808 // then set them all for expand so we can lower them later into their
810 if (TM.Options.ThreadModel == ThreadModel::Single)
811 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
812 else if (Subtarget->hasAnyDataBarrier() && !Subtarget->isThumb1Only()) {
813 // ATOMIC_FENCE needs custom lowering; the others should have been expanded
814 // to ldrex/strex loops already.
815 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
817 // On v8, we have particularly efficient implementations of atomic fences
818 // if they can be combined with nearby atomic loads and stores.
819 if (!Subtarget->hasV8Ops()) {
820 // Automatically insert fences (dmb ish) around ATOMIC_SWAP etc.
821 setInsertFencesForAtomic(true);
824 // If there's anything we can use as a barrier, go through custom lowering
826 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other,
827 Subtarget->hasAnyDataBarrier() ? Custom : Expand);
829 // Set them all for expansion, which will force libcalls.
830 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
831 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
832 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
833 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
834 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
835 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
836 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
837 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
838 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
839 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
840 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
841 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
842 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the
843 // Unordered/Monotonic case.
844 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
845 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
848 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
850 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
851 if (!Subtarget->hasV6Ops()) {
852 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
853 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
855 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
857 if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2() &&
858 !Subtarget->isThumb1Only()) {
859 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
860 // iff target supports vfp2.
861 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
862 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
865 // We want to custom lower some of our intrinsics.
866 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
867 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
868 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
869 setOperationAction(ISD::EH_SJLJ_SETUP_DISPATCH, MVT::Other, Custom);
870 if (Subtarget->isTargetDarwin())
871 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
873 setOperationAction(ISD::SETCC, MVT::i32, Expand);
874 setOperationAction(ISD::SETCC, MVT::f32, Expand);
875 setOperationAction(ISD::SETCC, MVT::f64, Expand);
876 setOperationAction(ISD::SELECT, MVT::i32, Custom);
877 setOperationAction(ISD::SELECT, MVT::f32, Custom);
878 setOperationAction(ISD::SELECT, MVT::f64, Custom);
879 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
880 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
881 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
883 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
884 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
885 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
886 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
887 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
889 // We don't support sin/cos/fmod/copysign/pow
890 setOperationAction(ISD::FSIN, MVT::f64, Expand);
891 setOperationAction(ISD::FSIN, MVT::f32, Expand);
892 setOperationAction(ISD::FCOS, MVT::f32, Expand);
893 setOperationAction(ISD::FCOS, MVT::f64, Expand);
894 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
895 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
896 setOperationAction(ISD::FREM, MVT::f64, Expand);
897 setOperationAction(ISD::FREM, MVT::f32, Expand);
898 if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2() &&
899 !Subtarget->isThumb1Only()) {
900 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
901 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
903 setOperationAction(ISD::FPOW, MVT::f64, Expand);
904 setOperationAction(ISD::FPOW, MVT::f32, Expand);
906 if (!Subtarget->hasVFP4()) {
907 setOperationAction(ISD::FMA, MVT::f64, Expand);
908 setOperationAction(ISD::FMA, MVT::f32, Expand);
911 // Various VFP goodness
912 if (!Subtarget->useSoftFloat() && !Subtarget->isThumb1Only()) {
913 // FP-ARMv8 adds f64 <-> f16 conversion. Before that it should be expanded.
914 if (!Subtarget->hasFPARMv8() || Subtarget->isFPOnlySP()) {
915 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
916 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
919 // fp16 is a special v7 extension that adds f16 <-> f32 conversions.
920 if (!Subtarget->hasFP16()) {
921 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
922 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
926 // Combine sin / cos into one node or libcall if possible.
927 if (Subtarget->hasSinCos()) {
928 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
929 setLibcallName(RTLIB::SINCOS_F64, "sincos");
930 if (Subtarget->getTargetTriple().isiOS()) {
931 // For iOS, we don't want to the normal expansion of a libcall to
932 // sincos. We want to issue a libcall to __sincos_stret.
933 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
934 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
938 // FP-ARMv8 implements a lot of rounding-like FP operations.
939 if (Subtarget->hasFPARMv8()) {
940 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
941 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
942 setOperationAction(ISD::FROUND, MVT::f32, Legal);
943 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
944 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
945 setOperationAction(ISD::FRINT, MVT::f32, Legal);
946 setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
947 setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
948 setOperationAction(ISD::FMINNUM, MVT::v2f32, Legal);
949 setOperationAction(ISD::FMAXNUM, MVT::v2f32, Legal);
950 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
951 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
953 if (!Subtarget->isFPOnlySP()) {
954 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
955 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
956 setOperationAction(ISD::FROUND, MVT::f64, Legal);
957 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
958 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
959 setOperationAction(ISD::FRINT, MVT::f64, Legal);
960 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
961 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
965 if (Subtarget->hasNEON()) {
966 // vmin and vmax aren't available in a scalar form, so we use
967 // a NEON instruction with an undef lane instead.
968 setOperationAction(ISD::FMINNAN, MVT::f32, Legal);
969 setOperationAction(ISD::FMAXNAN, MVT::f32, Legal);
970 setOperationAction(ISD::FMINNAN, MVT::v2f32, Legal);
971 setOperationAction(ISD::FMAXNAN, MVT::v2f32, Legal);
972 setOperationAction(ISD::FMINNAN, MVT::v4f32, Legal);
973 setOperationAction(ISD::FMAXNAN, MVT::v4f32, Legal);
976 // We have target-specific dag combine patterns for the following nodes:
977 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
978 setTargetDAGCombine(ISD::ADD);
979 setTargetDAGCombine(ISD::SUB);
980 setTargetDAGCombine(ISD::MUL);
981 setTargetDAGCombine(ISD::AND);
982 setTargetDAGCombine(ISD::OR);
983 setTargetDAGCombine(ISD::XOR);
985 if (Subtarget->hasV6Ops())
986 setTargetDAGCombine(ISD::SRL);
988 setStackPointerRegisterToSaveRestore(ARM::SP);
990 if (Subtarget->useSoftFloat() || Subtarget->isThumb1Only() ||
991 !Subtarget->hasVFP2())
992 setSchedulingPreference(Sched::RegPressure);
994 setSchedulingPreference(Sched::Hybrid);
996 //// temporary - rewrite interface to use type
997 MaxStoresPerMemset = 8;
998 MaxStoresPerMemsetOptSize = 4;
999 MaxStoresPerMemcpy = 4; // For @llvm.memcpy -> sequence of stores
1000 MaxStoresPerMemcpyOptSize = 2;
1001 MaxStoresPerMemmove = 4; // For @llvm.memmove -> sequence of stores
1002 MaxStoresPerMemmoveOptSize = 2;
1004 // On ARM arguments smaller than 4 bytes are extended, so all arguments
1005 // are at least 4 bytes aligned.
1006 setMinStackArgumentAlignment(4);
1008 // Prefer likely predicted branches to selects on out-of-order cores.
1009 PredictableSelectIsExpensive = Subtarget->isLikeA9();
1011 setMinFunctionAlignment(Subtarget->isThumb() ? 1 : 2);
1014 bool ARMTargetLowering::useSoftFloat() const {
1015 return Subtarget->useSoftFloat();
1018 // FIXME: It might make sense to define the representative register class as the
1019 // nearest super-register that has a non-null superset. For example, DPR_VFP2 is
1020 // a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
1021 // SPR's representative would be DPR_VFP2. This should work well if register
1022 // pressure tracking were modified such that a register use would increment the
1023 // pressure of the register class's representative and all of it's super
1024 // classes' representatives transitively. We have not implemented this because
1025 // of the difficulty prior to coalescing of modeling operand register classes
1026 // due to the common occurrence of cross class copies and subregister insertions
1028 std::pair<const TargetRegisterClass *, uint8_t>
1029 ARMTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
1031 const TargetRegisterClass *RRC = nullptr;
1033 switch (VT.SimpleTy) {
1035 return TargetLowering::findRepresentativeClass(TRI, VT);
1036 // Use DPR as representative register class for all floating point
1037 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
1038 // the cost is 1 for both f32 and f64.
1039 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
1040 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
1041 RRC = &ARM::DPRRegClass;
1042 // When NEON is used for SP, only half of the register file is available
1043 // because operations that define both SP and DP results will be constrained
1044 // to the VFP2 class (D0-D15). We currently model this constraint prior to
1045 // coalescing by double-counting the SP regs. See the FIXME above.
1046 if (Subtarget->useNEONForSinglePrecisionFP())
1049 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1050 case MVT::v4f32: case MVT::v2f64:
1051 RRC = &ARM::DPRRegClass;
1055 RRC = &ARM::DPRRegClass;
1059 RRC = &ARM::DPRRegClass;
1063 return std::make_pair(RRC, Cost);
1066 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
1067 switch ((ARMISD::NodeType)Opcode) {
1068 case ARMISD::FIRST_NUMBER: break;
1069 case ARMISD::Wrapper: return "ARMISD::Wrapper";
1070 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
1071 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
1072 case ARMISD::COPY_STRUCT_BYVAL: return "ARMISD::COPY_STRUCT_BYVAL";
1073 case ARMISD::CALL: return "ARMISD::CALL";
1074 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
1075 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
1076 case ARMISD::tCALL: return "ARMISD::tCALL";
1077 case ARMISD::BRCOND: return "ARMISD::BRCOND";
1078 case ARMISD::BR_JT: return "ARMISD::BR_JT";
1079 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
1080 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
1081 case ARMISD::INTRET_FLAG: return "ARMISD::INTRET_FLAG";
1082 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
1083 case ARMISD::CMP: return "ARMISD::CMP";
1084 case ARMISD::CMN: return "ARMISD::CMN";
1085 case ARMISD::CMPZ: return "ARMISD::CMPZ";
1086 case ARMISD::CMPFP: return "ARMISD::CMPFP";
1087 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
1088 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
1089 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
1091 case ARMISD::CMOV: return "ARMISD::CMOV";
1093 case ARMISD::RBIT: return "ARMISD::RBIT";
1095 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
1096 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
1097 case ARMISD::RRX: return "ARMISD::RRX";
1099 case ARMISD::ADDC: return "ARMISD::ADDC";
1100 case ARMISD::ADDE: return "ARMISD::ADDE";
1101 case ARMISD::SUBC: return "ARMISD::SUBC";
1102 case ARMISD::SUBE: return "ARMISD::SUBE";
1104 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
1105 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
1107 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
1108 case ARMISD::EH_SJLJ_LONGJMP: return "ARMISD::EH_SJLJ_LONGJMP";
1109 case ARMISD::EH_SJLJ_SETUP_DISPATCH: return "ARMISD::EH_SJLJ_SETUP_DISPATCH";
1111 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
1113 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
1115 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
1117 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
1119 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
1121 case ARMISD::WIN__CHKSTK: return "ARMISD:::WIN__CHKSTK";
1123 case ARMISD::VCEQ: return "ARMISD::VCEQ";
1124 case ARMISD::VCEQZ: return "ARMISD::VCEQZ";
1125 case ARMISD::VCGE: return "ARMISD::VCGE";
1126 case ARMISD::VCGEZ: return "ARMISD::VCGEZ";
1127 case ARMISD::VCLEZ: return "ARMISD::VCLEZ";
1128 case ARMISD::VCGEU: return "ARMISD::VCGEU";
1129 case ARMISD::VCGT: return "ARMISD::VCGT";
1130 case ARMISD::VCGTZ: return "ARMISD::VCGTZ";
1131 case ARMISD::VCLTZ: return "ARMISD::VCLTZ";
1132 case ARMISD::VCGTU: return "ARMISD::VCGTU";
1133 case ARMISD::VTST: return "ARMISD::VTST";
1135 case ARMISD::VSHL: return "ARMISD::VSHL";
1136 case ARMISD::VSHRs: return "ARMISD::VSHRs";
1137 case ARMISD::VSHRu: return "ARMISD::VSHRu";
1138 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
1139 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
1140 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
1141 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
1142 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
1143 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
1144 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
1145 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
1146 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
1147 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
1148 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
1149 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
1150 case ARMISD::VSLI: return "ARMISD::VSLI";
1151 case ARMISD::VSRI: return "ARMISD::VSRI";
1152 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
1153 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
1154 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
1155 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
1156 case ARMISD::VMOVFPIMM: return "ARMISD::VMOVFPIMM";
1157 case ARMISD::VDUP: return "ARMISD::VDUP";
1158 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
1159 case ARMISD::VEXT: return "ARMISD::VEXT";
1160 case ARMISD::VREV64: return "ARMISD::VREV64";
1161 case ARMISD::VREV32: return "ARMISD::VREV32";
1162 case ARMISD::VREV16: return "ARMISD::VREV16";
1163 case ARMISD::VZIP: return "ARMISD::VZIP";
1164 case ARMISD::VUZP: return "ARMISD::VUZP";
1165 case ARMISD::VTRN: return "ARMISD::VTRN";
1166 case ARMISD::VTBL1: return "ARMISD::VTBL1";
1167 case ARMISD::VTBL2: return "ARMISD::VTBL2";
1168 case ARMISD::VMULLs: return "ARMISD::VMULLs";
1169 case ARMISD::VMULLu: return "ARMISD::VMULLu";
1170 case ARMISD::UMLAL: return "ARMISD::UMLAL";
1171 case ARMISD::SMLAL: return "ARMISD::SMLAL";
1172 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
1173 case ARMISD::BFI: return "ARMISD::BFI";
1174 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
1175 case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
1176 case ARMISD::VBSL: return "ARMISD::VBSL";
1177 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
1178 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
1179 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
1180 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD";
1181 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD";
1182 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD";
1183 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD";
1184 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD";
1185 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD";
1186 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD";
1187 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD";
1188 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD";
1189 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD";
1190 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD";
1191 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD";
1192 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD";
1193 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD";
1194 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD";
1195 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD";
1196 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD";
1201 EVT ARMTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1204 return getPointerTy(DL);
1205 return VT.changeVectorElementTypeToInteger();
1208 /// getRegClassFor - Return the register class that should be used for the
1209 /// specified value type.
1210 const TargetRegisterClass *ARMTargetLowering::getRegClassFor(MVT VT) const {
1211 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
1212 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
1213 // load / store 4 to 8 consecutive D registers.
1214 if (Subtarget->hasNEON()) {
1215 if (VT == MVT::v4i64)
1216 return &ARM::QQPRRegClass;
1217 if (VT == MVT::v8i64)
1218 return &ARM::QQQQPRRegClass;
1220 return TargetLowering::getRegClassFor(VT);
1223 // memcpy, and other memory intrinsics, typically tries to use LDM/STM if the
1224 // source/dest is aligned and the copy size is large enough. We therefore want
1225 // to align such objects passed to memory intrinsics.
1226 bool ARMTargetLowering::shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
1227 unsigned &PrefAlign) const {
1228 if (!isa<MemIntrinsic>(CI))
1231 // On ARM11 onwards (excluding M class) 8-byte aligned LDM is typically 1
1232 // cycle faster than 4-byte aligned LDM.
1233 PrefAlign = (Subtarget->hasV6Ops() && !Subtarget->isMClass() ? 8 : 4);
1237 // Create a fast isel object.
1239 ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
1240 const TargetLibraryInfo *libInfo) const {
1241 return ARM::createFastISel(funcInfo, libInfo);
1244 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
1245 unsigned NumVals = N->getNumValues();
1247 return Sched::RegPressure;
1249 for (unsigned i = 0; i != NumVals; ++i) {
1250 EVT VT = N->getValueType(i);
1251 if (VT == MVT::Glue || VT == MVT::Other)
1253 if (VT.isFloatingPoint() || VT.isVector())
1257 if (!N->isMachineOpcode())
1258 return Sched::RegPressure;
1260 // Load are scheduled for latency even if there instruction itinerary
1261 // is not available.
1262 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
1263 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1265 if (MCID.getNumDefs() == 0)
1266 return Sched::RegPressure;
1267 if (!Itins->isEmpty() &&
1268 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
1271 return Sched::RegPressure;
1274 //===----------------------------------------------------------------------===//
1276 //===----------------------------------------------------------------------===//
1278 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
1279 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
1281 default: llvm_unreachable("Unknown condition code!");
1282 case ISD::SETNE: return ARMCC::NE;
1283 case ISD::SETEQ: return ARMCC::EQ;
1284 case ISD::SETGT: return ARMCC::GT;
1285 case ISD::SETGE: return ARMCC::GE;
1286 case ISD::SETLT: return ARMCC::LT;
1287 case ISD::SETLE: return ARMCC::LE;
1288 case ISD::SETUGT: return ARMCC::HI;
1289 case ISD::SETUGE: return ARMCC::HS;
1290 case ISD::SETULT: return ARMCC::LO;
1291 case ISD::SETULE: return ARMCC::LS;
1295 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
1296 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
1297 ARMCC::CondCodes &CondCode2) {
1298 CondCode2 = ARMCC::AL;
1300 default: llvm_unreachable("Unknown FP condition!");
1302 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
1304 case ISD::SETOGT: CondCode = ARMCC::GT; break;
1306 case ISD::SETOGE: CondCode = ARMCC::GE; break;
1307 case ISD::SETOLT: CondCode = ARMCC::MI; break;
1308 case ISD::SETOLE: CondCode = ARMCC::LS; break;
1309 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
1310 case ISD::SETO: CondCode = ARMCC::VC; break;
1311 case ISD::SETUO: CondCode = ARMCC::VS; break;
1312 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
1313 case ISD::SETUGT: CondCode = ARMCC::HI; break;
1314 case ISD::SETUGE: CondCode = ARMCC::PL; break;
1316 case ISD::SETULT: CondCode = ARMCC::LT; break;
1318 case ISD::SETULE: CondCode = ARMCC::LE; break;
1320 case ISD::SETUNE: CondCode = ARMCC::NE; break;
1324 //===----------------------------------------------------------------------===//
1325 // Calling Convention Implementation
1326 //===----------------------------------------------------------------------===//
1328 #include "ARMGenCallingConv.inc"
1330 /// getEffectiveCallingConv - Get the effective calling convention, taking into
1331 /// account presence of floating point hardware and calling convention
1332 /// limitations, such as support for variadic functions.
1334 ARMTargetLowering::getEffectiveCallingConv(CallingConv::ID CC,
1335 bool isVarArg) const {
1338 llvm_unreachable("Unsupported calling convention");
1339 case CallingConv::ARM_AAPCS:
1340 case CallingConv::ARM_APCS:
1341 case CallingConv::GHC:
1343 case CallingConv::ARM_AAPCS_VFP:
1344 return isVarArg ? CallingConv::ARM_AAPCS : CallingConv::ARM_AAPCS_VFP;
1345 case CallingConv::C:
1346 if (!Subtarget->isAAPCS_ABI())
1347 return CallingConv::ARM_APCS;
1348 else if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() &&
1349 getTargetMachine().Options.FloatABIType == FloatABI::Hard &&
1351 return CallingConv::ARM_AAPCS_VFP;
1353 return CallingConv::ARM_AAPCS;
1354 case CallingConv::Fast:
1355 if (!Subtarget->isAAPCS_ABI()) {
1356 if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() && !isVarArg)
1357 return CallingConv::Fast;
1358 return CallingConv::ARM_APCS;
1359 } else if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() && !isVarArg)
1360 return CallingConv::ARM_AAPCS_VFP;
1362 return CallingConv::ARM_AAPCS;
1366 /// CCAssignFnForNode - Selects the correct CCAssignFn for the given
1367 /// CallingConvention.
1368 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
1370 bool isVarArg) const {
1371 switch (getEffectiveCallingConv(CC, isVarArg)) {
1373 llvm_unreachable("Unsupported calling convention");
1374 case CallingConv::ARM_APCS:
1375 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1376 case CallingConv::ARM_AAPCS:
1377 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1378 case CallingConv::ARM_AAPCS_VFP:
1379 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1380 case CallingConv::Fast:
1381 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1382 case CallingConv::GHC:
1383 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC);
1387 /// LowerCallResult - Lower the result values of a call into the
1388 /// appropriate copies out of appropriate physical registers.
1390 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1391 CallingConv::ID CallConv, bool isVarArg,
1392 const SmallVectorImpl<ISD::InputArg> &Ins,
1393 SDLoc dl, SelectionDAG &DAG,
1394 SmallVectorImpl<SDValue> &InVals,
1395 bool isThisReturn, SDValue ThisVal) const {
1397 // Assign locations to each value returned by this call.
1398 SmallVector<CCValAssign, 16> RVLocs;
1399 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1400 *DAG.getContext(), Call);
1401 CCInfo.AnalyzeCallResult(Ins,
1402 CCAssignFnForNode(CallConv, /* Return*/ true,
1405 // Copy all of the result registers out of their specified physreg.
1406 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1407 CCValAssign VA = RVLocs[i];
1409 // Pass 'this' value directly from the argument to return value, to avoid
1410 // reg unit interference
1411 if (i == 0 && isThisReturn) {
1412 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&
1413 "unexpected return calling convention register assignment");
1414 InVals.push_back(ThisVal);
1419 if (VA.needsCustom()) {
1420 // Handle f64 or half of a v2f64.
1421 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1423 Chain = Lo.getValue(1);
1424 InFlag = Lo.getValue(2);
1425 VA = RVLocs[++i]; // skip ahead to next loc
1426 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1428 Chain = Hi.getValue(1);
1429 InFlag = Hi.getValue(2);
1430 if (!Subtarget->isLittle())
1432 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1434 if (VA.getLocVT() == MVT::v2f64) {
1435 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1436 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1437 DAG.getConstant(0, dl, MVT::i32));
1439 VA = RVLocs[++i]; // skip ahead to next loc
1440 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1441 Chain = Lo.getValue(1);
1442 InFlag = Lo.getValue(2);
1443 VA = RVLocs[++i]; // skip ahead to next loc
1444 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1445 Chain = Hi.getValue(1);
1446 InFlag = Hi.getValue(2);
1447 if (!Subtarget->isLittle())
1449 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1450 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1451 DAG.getConstant(1, dl, MVT::i32));
1454 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1456 Chain = Val.getValue(1);
1457 InFlag = Val.getValue(2);
1460 switch (VA.getLocInfo()) {
1461 default: llvm_unreachable("Unknown loc info!");
1462 case CCValAssign::Full: break;
1463 case CCValAssign::BCvt:
1464 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1468 InVals.push_back(Val);
1474 /// LowerMemOpCallTo - Store the argument to the stack.
1476 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
1477 SDValue StackPtr, SDValue Arg,
1478 SDLoc dl, SelectionDAG &DAG,
1479 const CCValAssign &VA,
1480 ISD::ArgFlagsTy Flags) const {
1481 unsigned LocMemOffset = VA.getLocMemOffset();
1482 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
1483 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
1485 return DAG.getStore(
1486 Chain, dl, Arg, PtrOff,
1487 MachinePointerInfo::getStack(DAG.getMachineFunction(), LocMemOffset),
1491 void ARMTargetLowering::PassF64ArgInRegs(SDLoc dl, SelectionDAG &DAG,
1492 SDValue Chain, SDValue &Arg,
1493 RegsToPassVector &RegsToPass,
1494 CCValAssign &VA, CCValAssign &NextVA,
1496 SmallVectorImpl<SDValue> &MemOpChains,
1497 ISD::ArgFlagsTy Flags) const {
1499 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1500 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1501 unsigned id = Subtarget->isLittle() ? 0 : 1;
1502 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(id)));
1504 if (NextVA.isRegLoc())
1505 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1-id)));
1507 assert(NextVA.isMemLoc());
1508 if (!StackPtr.getNode())
1509 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP,
1510 getPointerTy(DAG.getDataLayout()));
1512 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1-id),
1518 /// LowerCall - Lowering a call into a callseq_start <-
1519 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1522 ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1523 SmallVectorImpl<SDValue> &InVals) const {
1524 SelectionDAG &DAG = CLI.DAG;
1526 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1527 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1528 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1529 SDValue Chain = CLI.Chain;
1530 SDValue Callee = CLI.Callee;
1531 bool &isTailCall = CLI.IsTailCall;
1532 CallingConv::ID CallConv = CLI.CallConv;
1533 bool doesNotRet = CLI.DoesNotReturn;
1534 bool isVarArg = CLI.IsVarArg;
1536 MachineFunction &MF = DAG.getMachineFunction();
1537 bool isStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1538 bool isThisReturn = false;
1539 bool isSibCall = false;
1540 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
1542 // Disable tail calls if they're not supported.
1543 if (!Subtarget->supportsTailCall() || Attr.getValueAsString() == "true")
1547 // Check if it's really possible to do a tail call.
1548 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1549 isVarArg, isStructRet, MF.getFunction()->hasStructRetAttr(),
1550 Outs, OutVals, Ins, DAG);
1551 if (!isTailCall && CLI.CS && CLI.CS->isMustTailCall())
1552 report_fatal_error("failed to perform tail call elimination on a call "
1553 "site marked musttail");
1554 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1555 // detected sibcalls.
1562 // Analyze operands of the call, assigning locations to each operand.
1563 SmallVector<CCValAssign, 16> ArgLocs;
1564 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1565 *DAG.getContext(), Call);
1566 CCInfo.AnalyzeCallOperands(Outs,
1567 CCAssignFnForNode(CallConv, /* Return*/ false,
1570 // Get a count of how many bytes are to be pushed on the stack.
1571 unsigned NumBytes = CCInfo.getNextStackOffset();
1573 // For tail calls, memory operands are available in our caller's stack.
1577 // Adjust the stack pointer for the new arguments...
1578 // These operations are automatically eliminated by the prolog/epilog pass
1580 Chain = DAG.getCALLSEQ_START(Chain,
1581 DAG.getIntPtrConstant(NumBytes, dl, true), dl);
1584 DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy(DAG.getDataLayout()));
1586 RegsToPassVector RegsToPass;
1587 SmallVector<SDValue, 8> MemOpChains;
1589 // Walk the register/memloc assignments, inserting copies/loads. In the case
1590 // of tail call optimization, arguments are handled later.
1591 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1593 ++i, ++realArgIdx) {
1594 CCValAssign &VA = ArgLocs[i];
1595 SDValue Arg = OutVals[realArgIdx];
1596 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1597 bool isByVal = Flags.isByVal();
1599 // Promote the value if needed.
1600 switch (VA.getLocInfo()) {
1601 default: llvm_unreachable("Unknown loc info!");
1602 case CCValAssign::Full: break;
1603 case CCValAssign::SExt:
1604 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1606 case CCValAssign::ZExt:
1607 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1609 case CCValAssign::AExt:
1610 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1612 case CCValAssign::BCvt:
1613 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1617 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1618 if (VA.needsCustom()) {
1619 if (VA.getLocVT() == MVT::v2f64) {
1620 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1621 DAG.getConstant(0, dl, MVT::i32));
1622 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1623 DAG.getConstant(1, dl, MVT::i32));
1625 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1626 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1628 VA = ArgLocs[++i]; // skip ahead to next loc
1629 if (VA.isRegLoc()) {
1630 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1631 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1633 assert(VA.isMemLoc());
1635 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1636 dl, DAG, VA, Flags));
1639 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1640 StackPtr, MemOpChains, Flags);
1642 } else if (VA.isRegLoc()) {
1643 if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i32) {
1644 assert(VA.getLocVT() == MVT::i32 &&
1645 "unexpected calling convention register assignment");
1646 assert(!Ins.empty() && Ins[0].VT == MVT::i32 &&
1647 "unexpected use of 'returned'");
1648 isThisReturn = true;
1650 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1651 } else if (isByVal) {
1652 assert(VA.isMemLoc());
1653 unsigned offset = 0;
1655 // True if this byval aggregate will be split between registers
1657 unsigned ByValArgsCount = CCInfo.getInRegsParamsCount();
1658 unsigned CurByValIdx = CCInfo.getInRegsParamsProcessed();
1660 if (CurByValIdx < ByValArgsCount) {
1662 unsigned RegBegin, RegEnd;
1663 CCInfo.getInRegsParamInfo(CurByValIdx, RegBegin, RegEnd);
1666 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
1668 for (i = 0, j = RegBegin; j < RegEnd; i++, j++) {
1669 SDValue Const = DAG.getConstant(4*i, dl, MVT::i32);
1670 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
1671 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
1672 MachinePointerInfo(),
1673 false, false, false,
1674 DAG.InferPtrAlignment(AddArg));
1675 MemOpChains.push_back(Load.getValue(1));
1676 RegsToPass.push_back(std::make_pair(j, Load));
1679 // If parameter size outsides register area, "offset" value
1680 // helps us to calculate stack slot for remained part properly.
1681 offset = RegEnd - RegBegin;
1683 CCInfo.nextInRegsParam();
1686 if (Flags.getByValSize() > 4*offset) {
1687 auto PtrVT = getPointerTy(DAG.getDataLayout());
1688 unsigned LocMemOffset = VA.getLocMemOffset();
1689 SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
1690 SDValue Dst = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, StkPtrOff);
1691 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset, dl);
1692 SDValue Src = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, SrcOffset);
1693 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset, dl,
1695 SDValue AlignNode = DAG.getConstant(Flags.getByValAlign(), dl,
1698 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
1699 SDValue Ops[] = { Chain, Dst, Src, SizeNode, AlignNode};
1700 MemOpChains.push_back(DAG.getNode(ARMISD::COPY_STRUCT_BYVAL, dl, VTs,
1703 } else if (!isSibCall) {
1704 assert(VA.isMemLoc());
1706 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1707 dl, DAG, VA, Flags));
1711 if (!MemOpChains.empty())
1712 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
1714 // Build a sequence of copy-to-reg nodes chained together with token chain
1715 // and flag operands which copy the outgoing args into the appropriate regs.
1717 // Tail call byval lowering might overwrite argument registers so in case of
1718 // tail call optimization the copies to registers are lowered later.
1720 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1721 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1722 RegsToPass[i].second, InFlag);
1723 InFlag = Chain.getValue(1);
1726 // For tail calls lower the arguments to the 'real' stack slot.
1728 // Force all the incoming stack arguments to be loaded from the stack
1729 // before any new outgoing arguments are stored to the stack, because the
1730 // outgoing stack slots may alias the incoming argument stack slots, and
1731 // the alias isn't otherwise explicit. This is slightly more conservative
1732 // than necessary, because it means that each store effectively depends
1733 // on every argument instead of just those arguments it would clobber.
1735 // Do not flag preceding copytoreg stuff together with the following stuff.
1737 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1738 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1739 RegsToPass[i].second, InFlag);
1740 InFlag = Chain.getValue(1);
1745 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1746 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1747 // node so that legalize doesn't hack it.
1748 bool isDirect = false;
1749 bool isARMFunc = false;
1750 bool isLocalARMFunc = false;
1751 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1752 auto PtrVt = getPointerTy(DAG.getDataLayout());
1754 if (Subtarget->genLongCalls()) {
1755 assert((Subtarget->isTargetWindows() ||
1756 getTargetMachine().getRelocationModel() == Reloc::Static) &&
1757 "long-calls with non-static relocation model!");
1758 // Handle a global address or an external symbol. If it's not one of
1759 // those, the target's already in a register, so we don't need to do
1761 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1762 const GlobalValue *GV = G->getGlobal();
1763 // Create a constant pool entry for the callee address
1764 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1765 ARMConstantPoolValue *CPV =
1766 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0);
1768 // Get the address of the callee into a register
1769 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4);
1770 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1771 Callee = DAG.getLoad(
1772 PtrVt, dl, DAG.getEntryNode(), CPAddr,
1773 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
1775 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1776 const char *Sym = S->getSymbol();
1778 // Create a constant pool entry for the callee address
1779 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1780 ARMConstantPoolValue *CPV =
1781 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
1782 ARMPCLabelIndex, 0);
1783 // Get the address of the callee into a register
1784 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4);
1785 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1786 Callee = DAG.getLoad(
1787 PtrVt, dl, DAG.getEntryNode(), CPAddr,
1788 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
1791 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1792 const GlobalValue *GV = G->getGlobal();
1794 bool isDef = GV->isStrongDefinitionForLinker();
1795 bool isStub = (!isDef && Subtarget->isTargetMachO()) &&
1796 getTargetMachine().getRelocationModel() != Reloc::Static;
1797 isARMFunc = !Subtarget->isThumb() || (isStub && !Subtarget->isMClass());
1798 // ARM call to a local ARM function is predicable.
1799 isLocalARMFunc = !Subtarget->isThumb() && (isDef || !ARMInterworking);
1800 // tBX takes a register source operand.
1801 if (isStub && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1802 assert(Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?");
1803 Callee = DAG.getNode(
1804 ARMISD::WrapperPIC, dl, PtrVt,
1805 DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, ARMII::MO_NONLAZY));
1806 Callee = DAG.getLoad(PtrVt, dl, DAG.getEntryNode(), Callee,
1807 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
1808 false, false, true, 0);
1809 } else if (Subtarget->isTargetCOFF()) {
1810 assert(Subtarget->isTargetWindows() &&
1811 "Windows is the only supported COFF target");
1812 unsigned TargetFlags = GV->hasDLLImportStorageClass()
1813 ? ARMII::MO_DLLIMPORT
1814 : ARMII::MO_NO_FLAG;
1816 DAG.getTargetGlobalAddress(GV, dl, PtrVt, /*Offset=*/0, TargetFlags);
1817 if (GV->hasDLLImportStorageClass())
1819 DAG.getLoad(PtrVt, dl, DAG.getEntryNode(),
1820 DAG.getNode(ARMISD::Wrapper, dl, PtrVt, Callee),
1821 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
1822 false, false, false, 0);
1824 // On ELF targets for PIC code, direct calls should go through the PLT
1825 unsigned OpFlags = 0;
1826 if (Subtarget->isTargetELF() &&
1827 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1828 OpFlags = ARMII::MO_PLT;
1829 Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, OpFlags);
1831 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1833 bool isStub = Subtarget->isTargetMachO() &&
1834 getTargetMachine().getRelocationModel() != Reloc::Static;
1835 isARMFunc = !Subtarget->isThumb() || (isStub && !Subtarget->isMClass());
1836 // tBX takes a register source operand.
1837 const char *Sym = S->getSymbol();
1838 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1839 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1840 ARMConstantPoolValue *CPV =
1841 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
1842 ARMPCLabelIndex, 4);
1843 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4);
1844 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1845 Callee = DAG.getLoad(
1846 PtrVt, dl, DAG.getEntryNode(), CPAddr,
1847 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
1849 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
1850 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVt, Callee, PICLabel);
1852 unsigned OpFlags = 0;
1853 // On ELF targets for PIC code, direct calls should go through the PLT
1854 if (Subtarget->isTargetELF() &&
1855 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1856 OpFlags = ARMII::MO_PLT;
1857 Callee = DAG.getTargetExternalSymbol(Sym, PtrVt, OpFlags);
1861 // FIXME: handle tail calls differently.
1863 if (Subtarget->isThumb()) {
1864 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1865 CallOpc = ARMISD::CALL_NOLINK;
1867 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1869 if (!isDirect && !Subtarget->hasV5TOps())
1870 CallOpc = ARMISD::CALL_NOLINK;
1871 else if (doesNotRet && isDirect && Subtarget->hasRAS() &&
1872 // Emit regular call when code size is the priority
1873 !MF.getFunction()->optForMinSize())
1874 // "mov lr, pc; b _foo" to avoid confusing the RSP
1875 CallOpc = ARMISD::CALL_NOLINK;
1877 CallOpc = isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL;
1880 std::vector<SDValue> Ops;
1881 Ops.push_back(Chain);
1882 Ops.push_back(Callee);
1884 // Add argument registers to the end of the list so that they are known live
1886 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1887 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1888 RegsToPass[i].second.getValueType()));
1890 // Add a register mask operand representing the call-preserved registers.
1892 const uint32_t *Mask;
1893 const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo();
1895 // For 'this' returns, use the R0-preserving mask if applicable
1896 Mask = ARI->getThisReturnPreservedMask(MF, CallConv);
1898 // Set isThisReturn to false if the calling convention is not one that
1899 // allows 'returned' to be modeled in this way, so LowerCallResult does
1900 // not try to pass 'this' straight through
1901 isThisReturn = false;
1902 Mask = ARI->getCallPreservedMask(MF, CallConv);
1905 Mask = ARI->getCallPreservedMask(MF, CallConv);
1907 assert(Mask && "Missing call preserved mask for calling convention");
1908 Ops.push_back(DAG.getRegisterMask(Mask));
1911 if (InFlag.getNode())
1912 Ops.push_back(InFlag);
1914 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1916 MF.getFrameInfo()->setHasTailCall();
1917 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, Ops);
1920 // Returns a chain and a flag for retval copy to use.
1921 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
1922 InFlag = Chain.getValue(1);
1924 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
1925 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
1927 InFlag = Chain.getValue(1);
1929 // Handle result values, copying them out of physregs into vregs that we
1931 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
1932 InVals, isThisReturn,
1933 isThisReturn ? OutVals[0] : SDValue());
1936 /// HandleByVal - Every parameter *after* a byval parameter is passed
1937 /// on the stack. Remember the next parameter register to allocate,
1938 /// and then confiscate the rest of the parameter registers to insure
1940 void ARMTargetLowering::HandleByVal(CCState *State, unsigned &Size,
1941 unsigned Align) const {
1942 assert((State->getCallOrPrologue() == Prologue ||
1943 State->getCallOrPrologue() == Call) &&
1944 "unhandled ParmContext");
1946 // Byval (as with any stack) slots are always at least 4 byte aligned.
1947 Align = std::max(Align, 4U);
1949 unsigned Reg = State->AllocateReg(GPRArgRegs);
1953 unsigned AlignInRegs = Align / 4;
1954 unsigned Waste = (ARM::R4 - Reg) % AlignInRegs;
1955 for (unsigned i = 0; i < Waste; ++i)
1956 Reg = State->AllocateReg(GPRArgRegs);
1961 unsigned Excess = 4 * (ARM::R4 - Reg);
1963 // Special case when NSAA != SP and parameter size greater than size of
1964 // all remained GPR regs. In that case we can't split parameter, we must
1965 // send it to stack. We also must set NCRN to R4, so waste all
1966 // remained registers.
1967 const unsigned NSAAOffset = State->getNextStackOffset();
1968 if (NSAAOffset != 0 && Size > Excess) {
1969 while (State->AllocateReg(GPRArgRegs))
1974 // First register for byval parameter is the first register that wasn't
1975 // allocated before this method call, so it would be "reg".
1976 // If parameter is small enough to be saved in range [reg, r4), then
1977 // the end (first after last) register would be reg + param-size-in-regs,
1978 // else parameter would be splitted between registers and stack,
1979 // end register would be r4 in this case.
1980 unsigned ByValRegBegin = Reg;
1981 unsigned ByValRegEnd = std::min<unsigned>(Reg + Size / 4, ARM::R4);
1982 State->addInRegsParamInfo(ByValRegBegin, ByValRegEnd);
1983 // Note, first register is allocated in the beginning of function already,
1984 // allocate remained amount of registers we need.
1985 for (unsigned i = Reg + 1; i != ByValRegEnd; ++i)
1986 State->AllocateReg(GPRArgRegs);
1987 // A byval parameter that is split between registers and memory needs its
1988 // size truncated here.
1989 // In the case where the entire structure fits in registers, we set the
1990 // size in memory to zero.
1991 Size = std::max<int>(Size - Excess, 0);
1994 /// MatchingStackOffset - Return true if the given stack call argument is
1995 /// already available in the same position (relatively) of the caller's
1996 /// incoming argument stack.
1998 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1999 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
2000 const TargetInstrInfo *TII) {
2001 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
2003 if (Arg.getOpcode() == ISD::CopyFromReg) {
2004 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
2005 if (!TargetRegisterInfo::isVirtualRegister(VR))
2007 MachineInstr *Def = MRI->getVRegDef(VR);
2010 if (!Flags.isByVal()) {
2011 if (!TII->isLoadFromStackSlot(Def, FI))
2016 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
2017 if (Flags.isByVal())
2018 // ByVal argument is passed in as a pointer but it's now being
2019 // dereferenced. e.g.
2020 // define @foo(%struct.X* %A) {
2021 // tail call @bar(%struct.X* byval %A)
2024 SDValue Ptr = Ld->getBasePtr();
2025 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
2028 FI = FINode->getIndex();
2032 assert(FI != INT_MAX);
2033 if (!MFI->isFixedObjectIndex(FI))
2035 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2038 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2039 /// for tail call optimization. Targets which want to do tail call
2040 /// optimization should implement this function.
2042 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2043 CallingConv::ID CalleeCC,
2045 bool isCalleeStructRet,
2046 bool isCallerStructRet,
2047 const SmallVectorImpl<ISD::OutputArg> &Outs,
2048 const SmallVectorImpl<SDValue> &OutVals,
2049 const SmallVectorImpl<ISD::InputArg> &Ins,
2050 SelectionDAG& DAG) const {
2051 const Function *CallerF = DAG.getMachineFunction().getFunction();
2052 CallingConv::ID CallerCC = CallerF->getCallingConv();
2053 bool CCMatch = CallerCC == CalleeCC;
2055 // Look for obvious safe cases to perform tail call optimization that do not
2056 // require ABI changes. This is what gcc calls sibcall.
2058 // Do not sibcall optimize vararg calls unless the call site is not passing
2060 if (isVarArg && !Outs.empty())
2063 // Exception-handling functions need a special set of instructions to indicate
2064 // a return to the hardware. Tail-calling another function would probably
2066 if (CallerF->hasFnAttribute("interrupt"))
2069 // Also avoid sibcall optimization if either caller or callee uses struct
2070 // return semantics.
2071 if (isCalleeStructRet || isCallerStructRet)
2074 // FIXME: Completely disable sibcall for Thumb1 since ThumbRegisterInfo::
2075 // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
2076 // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
2077 // support in the assembler and linker to be used. This would need to be
2078 // fixed to fully support tail calls in Thumb1.
2080 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
2081 // LR. This means if we need to reload LR, it takes an extra instructions,
2082 // which outweighs the value of the tail call; but here we don't know yet
2083 // whether LR is going to be used. Probably the right approach is to
2084 // generate the tail call here and turn it back into CALL/RET in
2085 // emitEpilogue if LR is used.
2087 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
2088 // but we need to make sure there are enough registers; the only valid
2089 // registers are the 4 used for parameters. We don't currently do this
2091 if (Subtarget->isThumb1Only())
2094 // Externally-defined functions with weak linkage should not be
2095 // tail-called on ARM when the OS does not support dynamic
2096 // pre-emption of symbols, as the AAELF spec requires normal calls
2097 // to undefined weak functions to be replaced with a NOP or jump to the
2098 // next instruction. The behaviour of branch instructions in this
2099 // situation (as used for tail calls) is implementation-defined, so we
2100 // cannot rely on the linker replacing the tail call with a return.
2101 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2102 const GlobalValue *GV = G->getGlobal();
2103 const Triple &TT = getTargetMachine().getTargetTriple();
2104 if (GV->hasExternalWeakLinkage() &&
2105 (!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
2109 // If the calling conventions do not match, then we'd better make sure the
2110 // results are returned in the same way as what the caller expects.
2112 SmallVector<CCValAssign, 16> RVLocs1;
2113 ARMCCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
2114 *DAG.getContext(), Call);
2115 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
2117 SmallVector<CCValAssign, 16> RVLocs2;
2118 ARMCCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
2119 *DAG.getContext(), Call);
2120 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
2122 if (RVLocs1.size() != RVLocs2.size())
2124 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2125 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2127 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2129 if (RVLocs1[i].isRegLoc()) {
2130 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2133 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2139 // If Caller's vararg or byval argument has been split between registers and
2140 // stack, do not perform tail call, since part of the argument is in caller's
2142 const ARMFunctionInfo *AFI_Caller = DAG.getMachineFunction().
2143 getInfo<ARMFunctionInfo>();
2144 if (AFI_Caller->getArgRegsSaveSize())
2147 // If the callee takes no arguments then go on to check the results of the
2149 if (!Outs.empty()) {
2150 // Check if stack adjustment is needed. For now, do not do this if any
2151 // argument is passed on the stack.
2152 SmallVector<CCValAssign, 16> ArgLocs;
2153 ARMCCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2154 *DAG.getContext(), Call);
2155 CCInfo.AnalyzeCallOperands(Outs,
2156 CCAssignFnForNode(CalleeCC, false, isVarArg));
2157 if (CCInfo.getNextStackOffset()) {
2158 MachineFunction &MF = DAG.getMachineFunction();
2160 // Check if the arguments are already laid out in the right way as
2161 // the caller's fixed stack objects.
2162 MachineFrameInfo *MFI = MF.getFrameInfo();
2163 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2164 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
2165 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
2167 ++i, ++realArgIdx) {
2168 CCValAssign &VA = ArgLocs[i];
2169 EVT RegVT = VA.getLocVT();
2170 SDValue Arg = OutVals[realArgIdx];
2171 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2172 if (VA.getLocInfo() == CCValAssign::Indirect)
2174 if (VA.needsCustom()) {
2175 // f64 and vector types are split into multiple registers or
2176 // register/stack-slot combinations. The types will not match
2177 // the registers; give up on memory f64 refs until we figure
2178 // out what to do about this.
2181 if (!ArgLocs[++i].isRegLoc())
2183 if (RegVT == MVT::v2f64) {
2184 if (!ArgLocs[++i].isRegLoc())
2186 if (!ArgLocs[++i].isRegLoc())
2189 } else if (!VA.isRegLoc()) {
2190 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2202 ARMTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
2203 MachineFunction &MF, bool isVarArg,
2204 const SmallVectorImpl<ISD::OutputArg> &Outs,
2205 LLVMContext &Context) const {
2206 SmallVector<CCValAssign, 16> RVLocs;
2207 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2208 return CCInfo.CheckReturn(Outs, CCAssignFnForNode(CallConv, /*Return=*/true,
2212 static SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
2213 SDLoc DL, SelectionDAG &DAG) {
2214 const MachineFunction &MF = DAG.getMachineFunction();
2215 const Function *F = MF.getFunction();
2217 StringRef IntKind = F->getFnAttribute("interrupt").getValueAsString();
2219 // See ARM ARM v7 B1.8.3. On exception entry LR is set to a possibly offset
2220 // version of the "preferred return address". These offsets affect the return
2221 // instruction if this is a return from PL1 without hypervisor extensions.
2222 // IRQ/FIQ: +4 "subs pc, lr, #4"
2223 // SWI: 0 "subs pc, lr, #0"
2224 // ABORT: +4 "subs pc, lr, #4"
2225 // UNDEF: +4/+2 "subs pc, lr, #0"
2226 // UNDEF varies depending on where the exception came from ARM or Thumb
2227 // mode. Alongside GCC, we throw our hands up in disgust and pretend it's 0.
2230 if (IntKind == "" || IntKind == "IRQ" || IntKind == "FIQ" ||
2233 else if (IntKind == "SWI" || IntKind == "UNDEF")
2236 report_fatal_error("Unsupported interrupt attribute. If present, value "
2237 "must be one of: IRQ, FIQ, SWI, ABORT or UNDEF");
2239 RetOps.insert(RetOps.begin() + 1,
2240 DAG.getConstant(LROffset, DL, MVT::i32, false));
2242 return DAG.getNode(ARMISD::INTRET_FLAG, DL, MVT::Other, RetOps);
2246 ARMTargetLowering::LowerReturn(SDValue Chain,
2247 CallingConv::ID CallConv, bool isVarArg,
2248 const SmallVectorImpl<ISD::OutputArg> &Outs,
2249 const SmallVectorImpl<SDValue> &OutVals,
2250 SDLoc dl, SelectionDAG &DAG) const {
2252 // CCValAssign - represent the assignment of the return value to a location.
2253 SmallVector<CCValAssign, 16> RVLocs;
2255 // CCState - Info about the registers and stack slots.
2256 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2257 *DAG.getContext(), Call);
2259 // Analyze outgoing return values.
2260 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
2264 SmallVector<SDValue, 4> RetOps;
2265 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2266 bool isLittleEndian = Subtarget->isLittle();
2268 MachineFunction &MF = DAG.getMachineFunction();
2269 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2270 AFI->setReturnRegsCount(RVLocs.size());
2272 // Copy the result values into the output registers.
2273 for (unsigned i = 0, realRVLocIdx = 0;
2275 ++i, ++realRVLocIdx) {
2276 CCValAssign &VA = RVLocs[i];
2277 assert(VA.isRegLoc() && "Can only return in registers!");
2279 SDValue Arg = OutVals[realRVLocIdx];
2281 switch (VA.getLocInfo()) {
2282 default: llvm_unreachable("Unknown loc info!");
2283 case CCValAssign::Full: break;
2284 case CCValAssign::BCvt:
2285 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2289 if (VA.needsCustom()) {
2290 if (VA.getLocVT() == MVT::v2f64) {
2291 // Extract the first half and return it in two registers.
2292 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2293 DAG.getConstant(0, dl, MVT::i32));
2294 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
2295 DAG.getVTList(MVT::i32, MVT::i32), Half);
2297 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2298 HalfGPRs.getValue(isLittleEndian ? 0 : 1),
2300 Flag = Chain.getValue(1);
2301 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2302 VA = RVLocs[++i]; // skip ahead to next loc
2303 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2304 HalfGPRs.getValue(isLittleEndian ? 1 : 0),
2306 Flag = Chain.getValue(1);
2307 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2308 VA = RVLocs[++i]; // skip ahead to next loc
2310 // Extract the 2nd half and fall through to handle it as an f64 value.
2311 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2312 DAG.getConstant(1, dl, MVT::i32));
2314 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
2316 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
2317 DAG.getVTList(MVT::i32, MVT::i32), Arg);
2318 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2319 fmrrd.getValue(isLittleEndian ? 0 : 1),
2321 Flag = Chain.getValue(1);
2322 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2323 VA = RVLocs[++i]; // skip ahead to next loc
2324 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2325 fmrrd.getValue(isLittleEndian ? 1 : 0),
2328 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
2330 // Guarantee that all emitted copies are
2331 // stuck together, avoiding something bad.
2332 Flag = Chain.getValue(1);
2333 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2336 // Update chain and glue.
2339 RetOps.push_back(Flag);
2341 // CPUs which aren't M-class use a special sequence to return from
2342 // exceptions (roughly, any instruction setting pc and cpsr simultaneously,
2343 // though we use "subs pc, lr, #N").
2345 // M-class CPUs actually use a normal return sequence with a special
2346 // (hardware-provided) value in LR, so the normal code path works.
2347 if (DAG.getMachineFunction().getFunction()->hasFnAttribute("interrupt") &&
2348 !Subtarget->isMClass()) {
2349 if (Subtarget->isThumb1Only())
2350 report_fatal_error("interrupt attribute is not supported in Thumb1");
2351 return LowerInterruptReturn(RetOps, dl, DAG);
2354 return DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, RetOps);
2357 bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2358 if (N->getNumValues() != 1)
2360 if (!N->hasNUsesOfValue(1, 0))
2363 SDValue TCChain = Chain;
2364 SDNode *Copy = *N->use_begin();
2365 if (Copy->getOpcode() == ISD::CopyToReg) {
2366 // If the copy has a glue operand, we conservatively assume it isn't safe to
2367 // perform a tail call.
2368 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2370 TCChain = Copy->getOperand(0);
2371 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) {
2372 SDNode *VMov = Copy;
2373 // f64 returned in a pair of GPRs.
2374 SmallPtrSet<SDNode*, 2> Copies;
2375 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2377 if (UI->getOpcode() != ISD::CopyToReg)
2381 if (Copies.size() > 2)
2384 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2386 SDValue UseChain = UI->getOperand(0);
2387 if (Copies.count(UseChain.getNode()))
2391 // We are at the top of this chain.
2392 // If the copy has a glue operand, we conservatively assume it
2393 // isn't safe to perform a tail call.
2394 if (UI->getOperand(UI->getNumOperands()-1).getValueType() == MVT::Glue)
2400 } else if (Copy->getOpcode() == ISD::BITCAST) {
2401 // f32 returned in a single GPR.
2402 if (!Copy->hasOneUse())
2404 Copy = *Copy->use_begin();
2405 if (Copy->getOpcode() != ISD::CopyToReg || !Copy->hasNUsesOfValue(1, 0))
2407 // If the copy has a glue operand, we conservatively assume it isn't safe to
2408 // perform a tail call.
2409 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2411 TCChain = Copy->getOperand(0);
2416 bool HasRet = false;
2417 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2419 if (UI->getOpcode() != ARMISD::RET_FLAG &&
2420 UI->getOpcode() != ARMISD::INTRET_FLAG)
2432 bool ARMTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2433 if (!Subtarget->supportsTailCall())
2437 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2438 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2441 return !Subtarget->isThumb1Only();
2444 // Trying to write a 64 bit value so need to split into two 32 bit values first,
2445 // and pass the lower and high parts through.
2446 static SDValue LowerWRITE_REGISTER(SDValue Op, SelectionDAG &DAG) {
2448 SDValue WriteValue = Op->getOperand(2);
2450 // This function is only supposed to be called for i64 type argument.
2451 assert(WriteValue.getValueType() == MVT::i64
2452 && "LowerWRITE_REGISTER called for non-i64 type argument.");
2454 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
2455 DAG.getConstant(0, DL, MVT::i32));
2456 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
2457 DAG.getConstant(1, DL, MVT::i32));
2458 SDValue Ops[] = { Op->getOperand(0), Op->getOperand(1), Lo, Hi };
2459 return DAG.getNode(ISD::WRITE_REGISTER, DL, MVT::Other, Ops);
2462 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
2463 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
2464 // one of the above mentioned nodes. It has to be wrapped because otherwise
2465 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
2466 // be used to form addressing mode. These wrapped nodes will be selected
2468 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
2469 EVT PtrVT = Op.getValueType();
2470 // FIXME there is no actual debug info here
2472 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2474 if (CP->isMachineConstantPoolEntry())
2475 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
2476 CP->getAlignment());
2478 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
2479 CP->getAlignment());
2480 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
2483 unsigned ARMTargetLowering::getJumpTableEncoding() const {
2484 return MachineJumpTableInfo::EK_Inline;
2487 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
2488 SelectionDAG &DAG) const {
2489 MachineFunction &MF = DAG.getMachineFunction();
2490 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2491 unsigned ARMPCLabelIndex = 0;
2493 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2494 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
2495 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2497 if (RelocM == Reloc::Static) {
2498 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
2500 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2501 ARMPCLabelIndex = AFI->createPICLabelUId();
2502 ARMConstantPoolValue *CPV =
2503 ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex,
2504 ARMCP::CPBlockAddress, PCAdj);
2505 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2507 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
2509 DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
2510 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
2511 false, false, false, 0);
2512 if (RelocM == Reloc::Static)
2514 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, DL, MVT::i32);
2515 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
2518 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
2520 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
2521 SelectionDAG &DAG) const {
2523 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2524 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2525 MachineFunction &MF = DAG.getMachineFunction();
2526 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2527 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2528 ARMConstantPoolValue *CPV =
2529 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2530 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
2531 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2532 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
2534 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
2535 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
2536 false, false, false, 0);
2537 SDValue Chain = Argument.getValue(1);
2539 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2540 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
2542 // call __tls_get_addr.
2545 Entry.Node = Argument;
2546 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
2547 Args.push_back(Entry);
2549 // FIXME: is there useful debug info available here?
2550 TargetLowering::CallLoweringInfo CLI(DAG);
2551 CLI.setDebugLoc(dl).setChain(Chain)
2552 .setCallee(CallingConv::C, Type::getInt32Ty(*DAG.getContext()),
2553 DAG.getExternalSymbol("__tls_get_addr", PtrVT), std::move(Args),
2556 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2557 return CallResult.first;
2560 // Lower ISD::GlobalTLSAddress using the "initial exec" or
2561 // "local exec" model.
2563 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
2565 TLSModel::Model model) const {
2566 const GlobalValue *GV = GA->getGlobal();
2569 SDValue Chain = DAG.getEntryNode();
2570 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2571 // Get the Thread Pointer
2572 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2574 if (model == TLSModel::InitialExec) {
2575 MachineFunction &MF = DAG.getMachineFunction();
2576 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2577 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2578 // Initial exec model.
2579 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2580 ARMConstantPoolValue *CPV =
2581 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2582 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF,
2584 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2585 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2586 Offset = DAG.getLoad(
2587 PtrVT, dl, Chain, Offset,
2588 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
2590 Chain = Offset.getValue(1);
2592 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2593 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
2595 Offset = DAG.getLoad(
2596 PtrVT, dl, Chain, Offset,
2597 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
2601 assert(model == TLSModel::LocalExec);
2602 ARMConstantPoolValue *CPV =
2603 ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF);
2604 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2605 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2606 Offset = DAG.getLoad(
2607 PtrVT, dl, Chain, Offset,
2608 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
2612 // The address of the thread local variable is the add of the thread
2613 // pointer with the offset of the variable.
2614 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
2618 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
2619 // TODO: implement the "local dynamic" model
2620 assert(Subtarget->isTargetELF() &&
2621 "TLS not implemented for non-ELF targets");
2622 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2623 if (DAG.getTarget().Options.EmulatedTLS)
2624 return LowerToTLSEmulatedModel(GA, DAG);
2626 TLSModel::Model model = getTargetMachine().getTLSModel(GA->getGlobal());
2629 case TLSModel::GeneralDynamic:
2630 case TLSModel::LocalDynamic:
2631 return LowerToTLSGeneralDynamicModel(GA, DAG);
2632 case TLSModel::InitialExec:
2633 case TLSModel::LocalExec:
2634 return LowerToTLSExecModels(GA, DAG, model);
2636 llvm_unreachable("bogus TLS model");
2639 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
2640 SelectionDAG &DAG) const {
2641 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2643 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2644 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2645 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
2646 ARMConstantPoolValue *CPV =
2647 ARMConstantPoolConstant::Create(GV,
2648 UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
2649 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2650 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2651 SDValue Result = DAG.getLoad(
2652 PtrVT, dl, DAG.getEntryNode(), CPAddr,
2653 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
2655 SDValue Chain = Result.getValue(1);
2656 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
2657 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
2659 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
2660 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
2661 false, false, false, 0);
2665 // If we have T2 ops, we can materialize the address directly via movt/movw
2666 // pair. This is always cheaper.
2667 if (Subtarget->useMovt(DAG.getMachineFunction())) {
2669 // FIXME: Once remat is capable of dealing with instructions with register
2670 // operands, expand this into two nodes.
2671 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2672 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2674 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
2675 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2677 PtrVT, dl, DAG.getEntryNode(), CPAddr,
2678 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
2683 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
2684 SelectionDAG &DAG) const {
2685 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2687 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2688 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2690 if (Subtarget->useMovt(DAG.getMachineFunction()))
2693 // FIXME: Once remat is capable of dealing with instructions with register
2694 // operands, expand this into multiple nodes
2696 RelocM == Reloc::PIC_ ? ARMISD::WrapperPIC : ARMISD::Wrapper;
2698 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_NONLAZY);
2699 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT, G);
2701 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
2702 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
2703 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
2704 false, false, false, 0);
2708 SDValue ARMTargetLowering::LowerGlobalAddressWindows(SDValue Op,
2709 SelectionDAG &DAG) const {
2710 assert(Subtarget->isTargetWindows() && "non-Windows COFF is not supported");
2711 assert(Subtarget->useMovt(DAG.getMachineFunction()) &&
2712 "Windows on ARM expects to use movw/movt");
2714 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2715 const ARMII::TOF TargetFlags =
2716 (GV->hasDLLImportStorageClass() ? ARMII::MO_DLLIMPORT : ARMII::MO_NO_FLAG);
2717 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2723 // FIXME: Once remat is capable of dealing with instructions with register
2724 // operands, expand this into two nodes.
2725 Result = DAG.getNode(ARMISD::Wrapper, DL, PtrVT,
2726 DAG.getTargetGlobalAddress(GV, DL, PtrVT, /*Offset=*/0,
2728 if (GV->hasDLLImportStorageClass())
2729 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
2730 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
2731 false, false, false, 0);
2735 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
2736 SelectionDAG &DAG) const {
2737 assert(Subtarget->isTargetELF() &&
2738 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
2739 MachineFunction &MF = DAG.getMachineFunction();
2740 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2741 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2742 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2744 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2745 ARMConstantPoolValue *CPV =
2746 ARMConstantPoolSymbol::Create(*DAG.getContext(), "_GLOBAL_OFFSET_TABLE_",
2747 ARMPCLabelIndex, PCAdj);
2748 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2749 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2751 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2752 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()),
2753 false, false, false, 0);
2754 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2755 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2759 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
2761 SDValue Val = DAG.getConstant(0, dl, MVT::i32);
2762 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl,
2763 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
2764 Op.getOperand(1), Val);
2768 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
2770 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
2771 Op.getOperand(1), DAG.getConstant(0, dl, MVT::i32));
2774 SDValue ARMTargetLowering::LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op,
2775 SelectionDAG &DAG) const {
2777 return DAG.getNode(ARMISD::EH_SJLJ_SETUP_DISPATCH, dl, MVT::Other,
2782 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
2783 const ARMSubtarget *Subtarget) const {
2784 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2787 default: return SDValue(); // Don't custom lower most intrinsics.
2788 case Intrinsic::arm_rbit: {
2789 assert(Op.getOperand(1).getValueType() == MVT::i32 &&
2790 "RBIT intrinsic must have i32 type!");
2791 return DAG.getNode(ARMISD::RBIT, dl, MVT::i32, Op.getOperand(1));
2793 case Intrinsic::arm_thread_pointer: {
2794 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2795 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2797 case Intrinsic::eh_sjlj_lsda: {
2798 MachineFunction &MF = DAG.getMachineFunction();
2799 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2800 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2801 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2802 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2804 unsigned PCAdj = (RelocM != Reloc::PIC_)
2805 ? 0 : (Subtarget->isThumb() ? 4 : 8);
2806 ARMConstantPoolValue *CPV =
2807 ARMConstantPoolConstant::Create(MF.getFunction(), ARMPCLabelIndex,
2808 ARMCP::CPLSDA, PCAdj);
2809 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2810 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2811 SDValue Result = DAG.getLoad(
2812 PtrVT, dl, DAG.getEntryNode(), CPAddr,
2813 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
2816 if (RelocM == Reloc::PIC_) {
2817 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2818 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2822 case Intrinsic::arm_neon_vmulls:
2823 case Intrinsic::arm_neon_vmullu: {
2824 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
2825 ? ARMISD::VMULLs : ARMISD::VMULLu;
2826 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
2827 Op.getOperand(1), Op.getOperand(2));
2829 case Intrinsic::arm_neon_vminnm:
2830 case Intrinsic::arm_neon_vmaxnm: {
2831 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminnm)
2832 ? ISD::FMINNUM : ISD::FMAXNUM;
2833 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
2834 Op.getOperand(1), Op.getOperand(2));
2836 case Intrinsic::arm_neon_vminu:
2837 case Intrinsic::arm_neon_vmaxu: {
2838 if (Op.getValueType().isFloatingPoint())
2840 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vminu)
2841 ? ISD::UMIN : ISD::UMAX;
2842 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
2843 Op.getOperand(1), Op.getOperand(2));
2845 case Intrinsic::arm_neon_vmins:
2846 case Intrinsic::arm_neon_vmaxs: {
2847 // v{min,max}s is overloaded between signed integers and floats.
2848 if (!Op.getValueType().isFloatingPoint()) {
2849 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
2850 ? ISD::SMIN : ISD::SMAX;
2851 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
2852 Op.getOperand(1), Op.getOperand(2));
2854 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmins)
2855 ? ISD::FMINNAN : ISD::FMAXNAN;
2856 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
2857 Op.getOperand(1), Op.getOperand(2));
2862 static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
2863 const ARMSubtarget *Subtarget) {
2864 // FIXME: handle "fence singlethread" more efficiently.
2866 if (!Subtarget->hasDataBarrier()) {
2867 // Some ARMv6 cpus can support data barriers with an mcr instruction.
2868 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
2870 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&
2871 "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!");
2872 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2873 DAG.getConstant(0, dl, MVT::i32));
2876 ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1));
2877 AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue());
2878 ARM_MB::MemBOpt Domain = ARM_MB::ISH;
2879 if (Subtarget->isMClass()) {
2880 // Only a full system barrier exists in the M-class architectures.
2881 Domain = ARM_MB::SY;
2882 } else if (Subtarget->isSwift() && Ord == Release) {
2883 // Swift happens to implement ISHST barriers in a way that's compatible with
2884 // Release semantics but weaker than ISH so we'd be fools not to use
2885 // it. Beware: other processors probably don't!
2886 Domain = ARM_MB::ISHST;
2889 return DAG.getNode(ISD::INTRINSIC_VOID, dl, MVT::Other, Op.getOperand(0),
2890 DAG.getConstant(Intrinsic::arm_dmb, dl, MVT::i32),
2891 DAG.getConstant(Domain, dl, MVT::i32));
2894 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
2895 const ARMSubtarget *Subtarget) {
2896 // ARM pre v5TE and Thumb1 does not have preload instructions.
2897 if (!(Subtarget->isThumb2() ||
2898 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
2899 // Just preserve the chain.
2900 return Op.getOperand(0);
2903 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
2905 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
2906 // ARMv7 with MP extension has PLDW.
2907 return Op.getOperand(0);
2909 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
2910 if (Subtarget->isThumb()) {
2912 isRead = ~isRead & 1;
2913 isData = ~isData & 1;
2916 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
2917 Op.getOperand(1), DAG.getConstant(isRead, dl, MVT::i32),
2918 DAG.getConstant(isData, dl, MVT::i32));
2921 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
2922 MachineFunction &MF = DAG.getMachineFunction();
2923 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
2925 // vastart just stores the address of the VarArgsFrameIndex slot into the
2926 // memory location argument.
2928 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
2929 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2930 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2931 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2932 MachinePointerInfo(SV), false, false, 0);
2936 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
2937 SDValue &Root, SelectionDAG &DAG,
2939 MachineFunction &MF = DAG.getMachineFunction();
2940 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2942 const TargetRegisterClass *RC;
2943 if (AFI->isThumb1OnlyFunction())
2944 RC = &ARM::tGPRRegClass;
2946 RC = &ARM::GPRRegClass;
2948 // Transform the arguments stored in physical registers into virtual ones.
2949 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2950 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2953 if (NextVA.isMemLoc()) {
2954 MachineFrameInfo *MFI = MF.getFrameInfo();
2955 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
2957 // Create load node to retrieve arguments from the stack.
2958 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2959 ArgValue2 = DAG.getLoad(
2960 MVT::i32, dl, Root, FIN,
2961 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), false,
2964 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2965 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2967 if (!Subtarget->isLittle())
2968 std::swap (ArgValue, ArgValue2);
2969 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
2972 // The remaining GPRs hold either the beginning of variable-argument
2973 // data, or the beginning of an aggregate passed by value (usually
2974 // byval). Either way, we allocate stack slots adjacent to the data
2975 // provided by our caller, and store the unallocated registers there.
2976 // If this is a variadic function, the va_list pointer will begin with
2977 // these values; otherwise, this reassembles a (byval) structure that
2978 // was split between registers and memory.
2979 // Return: The frame index registers were stored into.
2981 ARMTargetLowering::StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
2982 SDLoc dl, SDValue &Chain,
2983 const Value *OrigArg,
2984 unsigned InRegsParamRecordIdx,
2986 unsigned ArgSize) const {
2987 // Currently, two use-cases possible:
2988 // Case #1. Non-var-args function, and we meet first byval parameter.
2989 // Setup first unallocated register as first byval register;
2990 // eat all remained registers
2991 // (these two actions are performed by HandleByVal method).
2992 // Then, here, we initialize stack frame with
2993 // "store-reg" instructions.
2994 // Case #2. Var-args function, that doesn't contain byval parameters.
2995 // The same: eat all remained unallocated registers,
2996 // initialize stack frame.
2998 MachineFunction &MF = DAG.getMachineFunction();
2999 MachineFrameInfo *MFI = MF.getFrameInfo();
3000 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3001 unsigned RBegin, REnd;
3002 if (InRegsParamRecordIdx < CCInfo.getInRegsParamsCount()) {
3003 CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd);
3005 unsigned RBeginIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
3006 RBegin = RBeginIdx == 4 ? (unsigned)ARM::R4 : GPRArgRegs[RBeginIdx];
3011 ArgOffset = -4 * (ARM::R4 - RBegin);
3013 auto PtrVT = getPointerTy(DAG.getDataLayout());
3014 int FrameIndex = MFI->CreateFixedObject(ArgSize, ArgOffset, false);
3015 SDValue FIN = DAG.getFrameIndex(FrameIndex, PtrVT);
3017 SmallVector<SDValue, 4> MemOps;
3018 const TargetRegisterClass *RC =
3019 AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
3021 for (unsigned Reg = RBegin, i = 0; Reg < REnd; ++Reg, ++i) {
3022 unsigned VReg = MF.addLiveIn(Reg, RC);
3023 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3025 DAG.getStore(Val.getValue(1), dl, Val, FIN,
3026 MachinePointerInfo(OrigArg, 4 * i), false, false, 0);
3027 MemOps.push_back(Store);
3028 FIN = DAG.getNode(ISD::ADD, dl, PtrVT, FIN, DAG.getConstant(4, dl, PtrVT));
3031 if (!MemOps.empty())
3032 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3036 // Setup stack frame, the va_list pointer will start from.
3038 ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
3039 SDLoc dl, SDValue &Chain,
3041 unsigned TotalArgRegsSaveSize,
3042 bool ForceMutable) const {
3043 MachineFunction &MF = DAG.getMachineFunction();
3044 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3046 // Try to store any remaining integer argument regs
3047 // to their spots on the stack so that they may be loaded by deferencing
3048 // the result of va_next.
3049 // If there is no regs to be stored, just point address after last
3050 // argument passed via stack.
3051 int FrameIndex = StoreByValRegs(CCInfo, DAG, dl, Chain, nullptr,
3052 CCInfo.getInRegsParamsCount(),
3053 CCInfo.getNextStackOffset(), 4);
3054 AFI->setVarArgsFrameIndex(FrameIndex);
3058 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
3059 CallingConv::ID CallConv, bool isVarArg,
3060 const SmallVectorImpl<ISD::InputArg>
3062 SDLoc dl, SelectionDAG &DAG,
3063 SmallVectorImpl<SDValue> &InVals)
3065 MachineFunction &MF = DAG.getMachineFunction();
3066 MachineFrameInfo *MFI = MF.getFrameInfo();
3068 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
3070 // Assign locations to all of the incoming arguments.
3071 SmallVector<CCValAssign, 16> ArgLocs;
3072 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
3073 *DAG.getContext(), Prologue);
3074 CCInfo.AnalyzeFormalArguments(Ins,
3075 CCAssignFnForNode(CallConv, /* Return*/ false,
3078 SmallVector<SDValue, 16> ArgValues;
3080 Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin();
3081 unsigned CurArgIdx = 0;
3083 // Initially ArgRegsSaveSize is zero.
3084 // Then we increase this value each time we meet byval parameter.
3085 // We also increase this value in case of varargs function.
3086 AFI->setArgRegsSaveSize(0);
3088 // Calculate the amount of stack space that we need to allocate to store
3089 // byval and variadic arguments that are passed in registers.
3090 // We need to know this before we allocate the first byval or variadic
3091 // argument, as they will be allocated a stack slot below the CFA (Canonical
3092 // Frame Address, the stack pointer at entry to the function).
3093 unsigned ArgRegBegin = ARM::R4;
3094 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3095 if (CCInfo.getInRegsParamsProcessed() >= CCInfo.getInRegsParamsCount())
3098 CCValAssign &VA = ArgLocs[i];
3099 unsigned Index = VA.getValNo();
3100 ISD::ArgFlagsTy Flags = Ins[Index].Flags;
3101 if (!Flags.isByVal())
3104 assert(VA.isMemLoc() && "unexpected byval pointer in reg");
3105 unsigned RBegin, REnd;
3106 CCInfo.getInRegsParamInfo(CCInfo.getInRegsParamsProcessed(), RBegin, REnd);
3107 ArgRegBegin = std::min(ArgRegBegin, RBegin);
3109 CCInfo.nextInRegsParam();
3111 CCInfo.rewindByValRegsInfo();
3113 int lastInsIndex = -1;
3114 if (isVarArg && MFI->hasVAStart()) {
3115 unsigned RegIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
3116 if (RegIdx != array_lengthof(GPRArgRegs))
3117 ArgRegBegin = std::min(ArgRegBegin, (unsigned)GPRArgRegs[RegIdx]);
3120 unsigned TotalArgRegsSaveSize = 4 * (ARM::R4 - ArgRegBegin);
3121 AFI->setArgRegsSaveSize(TotalArgRegsSaveSize);
3122 auto PtrVT = getPointerTy(DAG.getDataLayout());
3124 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3125 CCValAssign &VA = ArgLocs[i];
3126 if (Ins[VA.getValNo()].isOrigArg()) {
3127 std::advance(CurOrigArg,
3128 Ins[VA.getValNo()].getOrigArgIndex() - CurArgIdx);
3129 CurArgIdx = Ins[VA.getValNo()].getOrigArgIndex();
3131 // Arguments stored in registers.
3132 if (VA.isRegLoc()) {
3133 EVT RegVT = VA.getLocVT();
3135 if (VA.needsCustom()) {
3136 // f64 and vector types are split up into multiple registers or
3137 // combinations of registers and stack slots.
3138 if (VA.getLocVT() == MVT::v2f64) {
3139 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
3141 VA = ArgLocs[++i]; // skip ahead to next loc
3143 if (VA.isMemLoc()) {
3144 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
3145 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3146 ArgValue2 = DAG.getLoad(
3147 MVT::f64, dl, Chain, FIN,
3148 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3149 false, false, false, 0);
3151 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
3154 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
3155 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
3156 ArgValue, ArgValue1,
3157 DAG.getIntPtrConstant(0, dl));
3158 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
3159 ArgValue, ArgValue2,
3160 DAG.getIntPtrConstant(1, dl));
3162 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
3165 const TargetRegisterClass *RC;
3167 if (RegVT == MVT::f32)
3168 RC = &ARM::SPRRegClass;
3169 else if (RegVT == MVT::f64)
3170 RC = &ARM::DPRRegClass;
3171 else if (RegVT == MVT::v2f64)
3172 RC = &ARM::QPRRegClass;
3173 else if (RegVT == MVT::i32)
3174 RC = AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass
3175 : &ARM::GPRRegClass;
3177 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
3179 // Transform the arguments in physical registers into virtual ones.
3180 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3181 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
3184 // If this is an 8 or 16-bit value, it is really passed promoted
3185 // to 32 bits. Insert an assert[sz]ext to capture this, then
3186 // truncate to the right size.
3187 switch (VA.getLocInfo()) {
3188 default: llvm_unreachable("Unknown loc info!");
3189 case CCValAssign::Full: break;
3190 case CCValAssign::BCvt:
3191 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
3193 case CCValAssign::SExt:
3194 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
3195 DAG.getValueType(VA.getValVT()));
3196 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3198 case CCValAssign::ZExt:
3199 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
3200 DAG.getValueType(VA.getValVT()));
3201 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3205 InVals.push_back(ArgValue);
3207 } else { // VA.isRegLoc()
3210 assert(VA.isMemLoc());
3211 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
3213 int index = VA.getValNo();
3215 // Some Ins[] entries become multiple ArgLoc[] entries.
3216 // Process them only once.
3217 if (index != lastInsIndex)
3219 ISD::ArgFlagsTy Flags = Ins[index].Flags;
3220 // FIXME: For now, all byval parameter objects are marked mutable.
3221 // This can be changed with more analysis.
3222 // In case of tail call optimization mark all arguments mutable.
3223 // Since they could be overwritten by lowering of arguments in case of
3225 if (Flags.isByVal()) {
3226 assert(Ins[index].isOrigArg() &&
3227 "Byval arguments cannot be implicit");
3228 unsigned CurByValIndex = CCInfo.getInRegsParamsProcessed();
3230 int FrameIndex = StoreByValRegs(CCInfo, DAG, dl, Chain, CurOrigArg,
3231 CurByValIndex, VA.getLocMemOffset(),
3232 Flags.getByValSize());
3233 InVals.push_back(DAG.getFrameIndex(FrameIndex, PtrVT));
3234 CCInfo.nextInRegsParam();
3236 unsigned FIOffset = VA.getLocMemOffset();
3237 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
3240 // Create load nodes to retrieve arguments from the stack.
3241 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3242 InVals.push_back(DAG.getLoad(
3243 VA.getValVT(), dl, Chain, FIN,
3244 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI),
3245 false, false, false, 0));
3247 lastInsIndex = index;
3253 if (isVarArg && MFI->hasVAStart())
3254 VarArgStyleRegisters(CCInfo, DAG, dl, Chain,
3255 CCInfo.getNextStackOffset(),
3256 TotalArgRegsSaveSize);
3258 AFI->setArgumentStackSize(CCInfo.getNextStackOffset());
3263 /// isFloatingPointZero - Return true if this is +0.0.
3264 static bool isFloatingPointZero(SDValue Op) {
3265 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
3266 return CFP->getValueAPF().isPosZero();
3267 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
3268 // Maybe this has already been legalized into the constant pool?
3269 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
3270 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
3271 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
3272 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
3273 return CFP->getValueAPF().isPosZero();
3275 } else if (Op->getOpcode() == ISD::BITCAST &&
3276 Op->getValueType(0) == MVT::f64) {
3277 // Handle (ISD::BITCAST (ARMISD::VMOVIMM (ISD::TargetConstant 0)) MVT::f64)
3278 // created by LowerConstantFP().
3279 SDValue BitcastOp = Op->getOperand(0);
3280 if (BitcastOp->getOpcode() == ARMISD::VMOVIMM) {
3281 SDValue MoveOp = BitcastOp->getOperand(0);
3282 if (MoveOp->getOpcode() == ISD::TargetConstant &&
3283 cast<ConstantSDNode>(MoveOp)->getZExtValue() == 0) {
3291 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
3292 /// the given operands.
3294 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
3295 SDValue &ARMcc, SelectionDAG &DAG,
3297 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
3298 unsigned C = RHSC->getZExtValue();
3299 if (!isLegalICmpImmediate(C)) {
3300 // Constant does not fit, try adjusting it by one?
3305 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
3306 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
3307 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
3312 if (C != 0 && isLegalICmpImmediate(C-1)) {
3313 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
3314 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
3319 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
3320 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
3321 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
3326 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
3327 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
3328 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
3335 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3336 ARMISD::NodeType CompareType;
3339 CompareType = ARMISD::CMP;
3344 CompareType = ARMISD::CMPZ;
3347 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
3348 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
3351 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
3353 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
3355 assert(!Subtarget->isFPOnlySP() || RHS.getValueType() != MVT::f64);
3357 if (!isFloatingPointZero(RHS))
3358 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS);
3360 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS);
3361 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
3364 /// duplicateCmp - Glue values can have only one use, so this function
3365 /// duplicates a comparison node.
3367 ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
3368 unsigned Opc = Cmp.getOpcode();
3370 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
3371 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
3373 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation");
3374 Cmp = Cmp.getOperand(0);
3375 Opc = Cmp.getOpcode();
3376 if (Opc == ARMISD::CMPFP)
3377 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
3379 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT");
3380 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0));
3382 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
3385 std::pair<SDValue, SDValue>
3386 ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG,
3387 SDValue &ARMcc) const {
3388 assert(Op.getValueType() == MVT::i32 && "Unsupported value type");
3390 SDValue Value, OverflowCmp;
3391 SDValue LHS = Op.getOperand(0);
3392 SDValue RHS = Op.getOperand(1);
3395 // FIXME: We are currently always generating CMPs because we don't support
3396 // generating CMN through the backend. This is not as good as the natural
3397 // CMP case because it causes a register dependency and cannot be folded
3400 switch (Op.getOpcode()) {
3402 llvm_unreachable("Unknown overflow instruction!");
3404 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
3405 Value = DAG.getNode(ISD::ADD, dl, Op.getValueType(), LHS, RHS);
3406 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
3409 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
3410 Value = DAG.getNode(ISD::ADD, dl, Op.getValueType(), LHS, RHS);
3411 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
3414 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
3415 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
3416 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
3419 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
3420 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
3421 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
3425 return std::make_pair(Value, OverflowCmp);
3430 ARMTargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
3431 // Let legalize expand this if it isn't a legal type yet.
3432 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
3435 SDValue Value, OverflowCmp;
3437 std::tie(Value, OverflowCmp) = getARMXALUOOp(Op, DAG, ARMcc);
3438 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3440 // We use 0 and 1 as false and true values.
3441 SDValue TVal = DAG.getConstant(1, dl, MVT::i32);
3442 SDValue FVal = DAG.getConstant(0, dl, MVT::i32);
3443 EVT VT = Op.getValueType();
3445 SDValue Overflow = DAG.getNode(ARMISD::CMOV, dl, VT, TVal, FVal,
3446 ARMcc, CCR, OverflowCmp);
3448 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
3449 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
3453 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
3454 SDValue Cond = Op.getOperand(0);
3455 SDValue SelectTrue = Op.getOperand(1);
3456 SDValue SelectFalse = Op.getOperand(2);
3458 unsigned Opc = Cond.getOpcode();
3460 if (Cond.getResNo() == 1 &&
3461 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3462 Opc == ISD::USUBO)) {
3463 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
3466 SDValue Value, OverflowCmp;
3468 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
3469 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3470 EVT VT = Op.getValueType();
3472 return getCMOV(dl, VT, SelectTrue, SelectFalse, ARMcc, CCR,
3478 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
3479 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
3481 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
3482 const ConstantSDNode *CMOVTrue =
3483 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
3484 const ConstantSDNode *CMOVFalse =
3485 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
3487 if (CMOVTrue && CMOVFalse) {
3488 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
3489 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
3493 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
3495 False = SelectFalse;
3496 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
3501 if (True.getNode() && False.getNode()) {
3502 EVT VT = Op.getValueType();
3503 SDValue ARMcc = Cond.getOperand(2);
3504 SDValue CCR = Cond.getOperand(3);
3505 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
3506 assert(True.getValueType() == VT);
3507 return getCMOV(dl, VT, True, False, ARMcc, CCR, Cmp, DAG);
3512 // ARM's BooleanContents value is UndefinedBooleanContent. Mask out the
3513 // undefined bits before doing a full-word comparison with zero.
3514 Cond = DAG.getNode(ISD::AND, dl, Cond.getValueType(), Cond,
3515 DAG.getConstant(1, dl, Cond.getValueType()));
3517 return DAG.getSelectCC(dl, Cond,
3518 DAG.getConstant(0, dl, Cond.getValueType()),
3519 SelectTrue, SelectFalse, ISD::SETNE);
3522 static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
3523 bool &swpCmpOps, bool &swpVselOps) {
3524 // Start by selecting the GE condition code for opcodes that return true for
3526 if (CC == ISD::SETUGE || CC == ISD::SETOGE || CC == ISD::SETOLE ||
3528 CondCode = ARMCC::GE;
3530 // and GT for opcodes that return false for 'equality'.
3531 else if (CC == ISD::SETUGT || CC == ISD::SETOGT || CC == ISD::SETOLT ||
3533 CondCode = ARMCC::GT;
3535 // Since we are constrained to GE/GT, if the opcode contains 'less', we need
3536 // to swap the compare operands.
3537 if (CC == ISD::SETOLE || CC == ISD::SETULE || CC == ISD::SETOLT ||
3541 // Both GT and GE are ordered comparisons, and return false for 'unordered'.
3542 // If we have an unordered opcode, we need to swap the operands to the VSEL
3543 // instruction (effectively negating the condition).
3545 // This also has the effect of swapping which one of 'less' or 'greater'
3546 // returns true, so we also swap the compare operands. It also switches
3547 // whether we return true for 'equality', so we compensate by picking the
3548 // opposite condition code to our original choice.
3549 if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE ||
3550 CC == ISD::SETUGT) {
3551 swpCmpOps = !swpCmpOps;
3552 swpVselOps = !swpVselOps;
3553 CondCode = CondCode == ARMCC::GT ? ARMCC::GE : ARMCC::GT;
3556 // 'ordered' is 'anything but unordered', so use the VS condition code and
3557 // swap the VSEL operands.
3558 if (CC == ISD::SETO) {
3559 CondCode = ARMCC::VS;
3563 // 'unordered or not equal' is 'anything but equal', so use the EQ condition
3564 // code and swap the VSEL operands.
3565 if (CC == ISD::SETUNE) {
3566 CondCode = ARMCC::EQ;
3571 SDValue ARMTargetLowering::getCMOV(SDLoc dl, EVT VT, SDValue FalseVal,
3572 SDValue TrueVal, SDValue ARMcc, SDValue CCR,
3573 SDValue Cmp, SelectionDAG &DAG) const {
3574 if (Subtarget->isFPOnlySP() && VT == MVT::f64) {
3575 FalseVal = DAG.getNode(ARMISD::VMOVRRD, dl,
3576 DAG.getVTList(MVT::i32, MVT::i32), FalseVal);
3577 TrueVal = DAG.getNode(ARMISD::VMOVRRD, dl,
3578 DAG.getVTList(MVT::i32, MVT::i32), TrueVal);
3580 SDValue TrueLow = TrueVal.getValue(0);
3581 SDValue TrueHigh = TrueVal.getValue(1);
3582 SDValue FalseLow = FalseVal.getValue(0);
3583 SDValue FalseHigh = FalseVal.getValue(1);
3585 SDValue Low = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseLow, TrueLow,
3587 SDValue High = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseHigh, TrueHigh,
3588 ARMcc, CCR, duplicateCmp(Cmp, DAG));
3590 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Low, High);
3592 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,
3597 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
3598 EVT VT = Op.getValueType();
3599 SDValue LHS = Op.getOperand(0);
3600 SDValue RHS = Op.getOperand(1);
3601 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3602 SDValue TrueVal = Op.getOperand(2);
3603 SDValue FalseVal = Op.getOperand(3);
3606 if (Subtarget->isFPOnlySP() && LHS.getValueType() == MVT::f64) {
3607 DAG.getTargetLoweringInfo().softenSetCCOperands(DAG, MVT::f64, LHS, RHS, CC,
3610 // If softenSetCCOperands only returned one value, we should compare it to
3612 if (!RHS.getNode()) {
3613 RHS = DAG.getConstant(0, dl, LHS.getValueType());
3618 if (LHS.getValueType() == MVT::i32) {
3619 // Try to generate VSEL on ARMv8.
3620 // The VSEL instruction can't use all the usual ARM condition
3621 // codes: it only has two bits to select the condition code, so it's
3622 // constrained to use only GE, GT, VS and EQ.
3624 // To implement all the various ISD::SETXXX opcodes, we sometimes need to
3625 // swap the operands of the previous compare instruction (effectively
3626 // inverting the compare condition, swapping 'less' and 'greater') and
3627 // sometimes need to swap the operands to the VSEL (which inverts the
3628 // condition in the sense of firing whenever the previous condition didn't)
3629 if (Subtarget->hasFPARMv8() && (TrueVal.getValueType() == MVT::f32 ||
3630 TrueVal.getValueType() == MVT::f64)) {
3631 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3632 if (CondCode == ARMCC::LT || CondCode == ARMCC::LE ||
3633 CondCode == ARMCC::VC || CondCode == ARMCC::NE) {
3634 CC = ISD::getSetCCInverse(CC, true);
3635 std::swap(TrueVal, FalseVal);
3640 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3641 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3642 return getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
3645 ARMCC::CondCodes CondCode, CondCode2;
3646 FPCCToARMCC(CC, CondCode, CondCode2);
3648 // Try to generate VMAXNM/VMINNM on ARMv8.
3649 if (Subtarget->hasFPARMv8() && (TrueVal.getValueType() == MVT::f32 ||
3650 TrueVal.getValueType() == MVT::f64)) {
3651 bool swpCmpOps = false;
3652 bool swpVselOps = false;
3653 checkVSELConstraints(CC, CondCode, swpCmpOps, swpVselOps);
3655 if (CondCode == ARMCC::GT || CondCode == ARMCC::GE ||
3656 CondCode == ARMCC::VS || CondCode == ARMCC::EQ) {
3658 std::swap(LHS, RHS);
3660 std::swap(TrueVal, FalseVal);
3664 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
3665 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
3666 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3667 SDValue Result = getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
3668 if (CondCode2 != ARMCC::AL) {
3669 SDValue ARMcc2 = DAG.getConstant(CondCode2, dl, MVT::i32);
3670 // FIXME: Needs another CMP because flag can have but one use.
3671 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
3672 Result = getCMOV(dl, VT, Result, TrueVal, ARMcc2, CCR, Cmp2, DAG);
3677 /// canChangeToInt - Given the fp compare operand, return true if it is suitable
3678 /// to morph to an integer compare sequence.
3679 static bool canChangeToInt(SDValue Op, bool &SeenZero,
3680 const ARMSubtarget *Subtarget) {
3681 SDNode *N = Op.getNode();
3682 if (!N->hasOneUse())
3683 // Otherwise it requires moving the value from fp to integer registers.
3685 if (!N->getNumValues())
3687 EVT VT = Op.getValueType();
3688 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
3689 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
3690 // vmrs are very slow, e.g. cortex-a8.
3693 if (isFloatingPointZero(Op)) {
3697 return ISD::isNormalLoad(N);
3700 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
3701 if (isFloatingPointZero(Op))
3702 return DAG.getConstant(0, SDLoc(Op), MVT::i32);
3704 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
3705 return DAG.getLoad(MVT::i32, SDLoc(Op),
3706 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(),
3707 Ld->isVolatile(), Ld->isNonTemporal(),
3708 Ld->isInvariant(), Ld->getAlignment());
3710 llvm_unreachable("Unknown VFP cmp argument!");
3713 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
3714 SDValue &RetVal1, SDValue &RetVal2) {
3717 if (isFloatingPointZero(Op)) {
3718 RetVal1 = DAG.getConstant(0, dl, MVT::i32);
3719 RetVal2 = DAG.getConstant(0, dl, MVT::i32);
3723 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
3724 SDValue Ptr = Ld->getBasePtr();
3725 RetVal1 = DAG.getLoad(MVT::i32, dl,
3726 Ld->getChain(), Ptr,
3727 Ld->getPointerInfo(),
3728 Ld->isVolatile(), Ld->isNonTemporal(),
3729 Ld->isInvariant(), Ld->getAlignment());
3731 EVT PtrType = Ptr.getValueType();
3732 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
3733 SDValue NewPtr = DAG.getNode(ISD::ADD, dl,
3734 PtrType, Ptr, DAG.getConstant(4, dl, PtrType));
3735 RetVal2 = DAG.getLoad(MVT::i32, dl,
3736 Ld->getChain(), NewPtr,
3737 Ld->getPointerInfo().getWithOffset(4),
3738 Ld->isVolatile(), Ld->isNonTemporal(),
3739 Ld->isInvariant(), NewAlign);
3743 llvm_unreachable("Unknown VFP cmp argument!");
3746 /// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
3747 /// f32 and even f64 comparisons to integer ones.
3749 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
3750 SDValue Chain = Op.getOperand(0);
3751 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3752 SDValue LHS = Op.getOperand(2);
3753 SDValue RHS = Op.getOperand(3);
3754 SDValue Dest = Op.getOperand(4);
3757 bool LHSSeenZero = false;
3758 bool LHSOk = canChangeToInt(LHS, LHSSeenZero, Subtarget);
3759 bool RHSSeenZero = false;
3760 bool RHSOk = canChangeToInt(RHS, RHSSeenZero, Subtarget);
3761 if (LHSOk && RHSOk && (LHSSeenZero || RHSSeenZero)) {
3762 // If unsafe fp math optimization is enabled and there are no other uses of
3763 // the CMP operands, and the condition code is EQ or NE, we can optimize it
3764 // to an integer comparison.
3765 if (CC == ISD::SETOEQ)
3767 else if (CC == ISD::SETUNE)
3770 SDValue Mask = DAG.getConstant(0x7fffffff, dl, MVT::i32);
3772 if (LHS.getValueType() == MVT::f32) {
3773 LHS = DAG.getNode(ISD::AND, dl, MVT::i32,
3774 bitcastf32Toi32(LHS, DAG), Mask);
3775 RHS = DAG.getNode(ISD::AND, dl, MVT::i32,
3776 bitcastf32Toi32(RHS, DAG), Mask);
3777 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3778 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3779 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
3780 Chain, Dest, ARMcc, CCR, Cmp);
3785 expandf64Toi32(LHS, DAG, LHS1, LHS2);
3786 expandf64Toi32(RHS, DAG, RHS1, RHS2);
3787 LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask);
3788 RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask);
3789 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3790 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
3791 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
3792 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
3793 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops);
3799 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
3800 SDValue Chain = Op.getOperand(0);
3801 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3802 SDValue LHS = Op.getOperand(2);
3803 SDValue RHS = Op.getOperand(3);
3804 SDValue Dest = Op.getOperand(4);
3807 if (Subtarget->isFPOnlySP() && LHS.getValueType() == MVT::f64) {
3808 DAG.getTargetLoweringInfo().softenSetCCOperands(DAG, MVT::f64, LHS, RHS, CC,
3811 // If softenSetCCOperands only returned one value, we should compare it to
3813 if (!RHS.getNode()) {
3814 RHS = DAG.getConstant(0, dl, LHS.getValueType());
3819 if (LHS.getValueType() == MVT::i32) {
3821 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3822 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3823 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
3824 Chain, Dest, ARMcc, CCR, Cmp);
3827 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3829 if (getTargetMachine().Options.UnsafeFPMath &&
3830 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
3831 CC == ISD::SETNE || CC == ISD::SETUNE)) {
3832 SDValue Result = OptimizeVFPBrcond(Op, DAG);
3833 if (Result.getNode())
3837 ARMCC::CondCodes CondCode, CondCode2;
3838 FPCCToARMCC(CC, CondCode, CondCode2);
3840 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
3841 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
3842 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3843 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
3844 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
3845 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
3846 if (CondCode2 != ARMCC::AL) {
3847 ARMcc = DAG.getConstant(CondCode2, dl, MVT::i32);
3848 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
3849 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
3854 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
3855 SDValue Chain = Op.getOperand(0);
3856 SDValue Table = Op.getOperand(1);
3857 SDValue Index = Op.getOperand(2);
3860 EVT PTy = getPointerTy(DAG.getDataLayout());
3861 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
3862 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
3863 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI);
3864 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, dl, PTy));
3865 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
3866 if (Subtarget->isThumb2()) {
3867 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
3868 // which does another jump to the destination. This also makes it easier
3869 // to translate it to TBB / TBH later.
3870 // FIXME: This might not work if the function is extremely large.
3871 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
3872 Addr, Op.getOperand(2), JTI);
3874 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
3876 DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
3877 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()),
3878 false, false, false, 0);
3879 Chain = Addr.getValue(1);
3880 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
3881 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
3884 DAG.getLoad(PTy, dl, Chain, Addr,
3885 MachinePointerInfo::getJumpTable(DAG.getMachineFunction()),
3886 false, false, false, 0);
3887 Chain = Addr.getValue(1);
3888 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
3892 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
3893 EVT VT = Op.getValueType();
3896 if (Op.getValueType().getVectorElementType() == MVT::i32) {
3897 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32)
3899 return DAG.UnrollVectorOp(Op.getNode());
3902 assert(Op.getOperand(0).getValueType() == MVT::v4f32 &&
3903 "Invalid type for custom lowering!");
3904 if (VT != MVT::v4i16)
3905 return DAG.UnrollVectorOp(Op.getNode());
3907 Op = DAG.getNode(Op.getOpcode(), dl, MVT::v4i32, Op.getOperand(0));
3908 return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
3911 SDValue ARMTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const {
3912 EVT VT = Op.getValueType();
3914 return LowerVectorFP_TO_INT(Op, DAG);
3915 if (Subtarget->isFPOnlySP() && Op.getOperand(0).getValueType() == MVT::f64) {
3917 if (Op.getOpcode() == ISD::FP_TO_SINT)
3918 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(),
3921 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(),
3923 return makeLibCall(DAG, LC, Op.getValueType(), &Op.getOperand(0), 1,
3924 /*isSigned*/ false, SDLoc(Op)).first;
3930 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
3931 EVT VT = Op.getValueType();
3934 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) {
3935 if (VT.getVectorElementType() == MVT::f32)
3937 return DAG.UnrollVectorOp(Op.getNode());
3940 assert(Op.getOperand(0).getValueType() == MVT::v4i16 &&
3941 "Invalid type for custom lowering!");
3942 if (VT != MVT::v4f32)
3943 return DAG.UnrollVectorOp(Op.getNode());
3947 switch (Op.getOpcode()) {
3948 default: llvm_unreachable("Invalid opcode!");
3949 case ISD::SINT_TO_FP:
3950 CastOpc = ISD::SIGN_EXTEND;
3951 Opc = ISD::SINT_TO_FP;
3953 case ISD::UINT_TO_FP:
3954 CastOpc = ISD::ZERO_EXTEND;
3955 Opc = ISD::UINT_TO_FP;
3959 Op = DAG.getNode(CastOpc, dl, MVT::v4i32, Op.getOperand(0));
3960 return DAG.getNode(Opc, dl, VT, Op);
3963 SDValue ARMTargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const {
3964 EVT VT = Op.getValueType();
3966 return LowerVectorINT_TO_FP(Op, DAG);
3967 if (Subtarget->isFPOnlySP() && Op.getValueType() == MVT::f64) {
3969 if (Op.getOpcode() == ISD::SINT_TO_FP)
3970 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(),
3973 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(),
3975 return makeLibCall(DAG, LC, Op.getValueType(), &Op.getOperand(0), 1,
3976 /*isSigned*/ false, SDLoc(Op)).first;
3982 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
3983 // Implement fcopysign with a fabs and a conditional fneg.
3984 SDValue Tmp0 = Op.getOperand(0);
3985 SDValue Tmp1 = Op.getOperand(1);
3987 EVT VT = Op.getValueType();
3988 EVT SrcVT = Tmp1.getValueType();
3989 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
3990 Tmp0.getOpcode() == ARMISD::VMOVDRR;
3991 bool UseNEON = !InGPR && Subtarget->hasNEON();
3994 // Use VBSL to copy the sign bit.
3995 unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80);
3996 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
3997 DAG.getTargetConstant(EncodedVal, dl, MVT::i32));
3998 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
4000 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT,
4001 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
4002 DAG.getConstant(32, dl, MVT::i32));
4003 else /*if (VT == MVT::f32)*/
4004 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
4005 if (SrcVT == MVT::f32) {
4006 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
4008 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT,
4009 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
4010 DAG.getConstant(32, dl, MVT::i32));
4011 } else if (VT == MVT::f32)
4012 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64,
4013 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
4014 DAG.getConstant(32, dl, MVT::i32));
4015 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
4016 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
4018 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff),
4020 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
4021 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
4022 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
4024 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
4025 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
4026 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
4027 if (VT == MVT::f32) {
4028 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
4029 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
4030 DAG.getConstant(0, dl, MVT::i32));
4032 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
4038 // Bitcast operand 1 to i32.
4039 if (SrcVT == MVT::f64)
4040 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
4042 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
4044 // Or in the signbit with integer operations.
4045 SDValue Mask1 = DAG.getConstant(0x80000000, dl, MVT::i32);
4046 SDValue Mask2 = DAG.getConstant(0x7fffffff, dl, MVT::i32);
4047 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
4048 if (VT == MVT::f32) {
4049 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
4050 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
4051 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4052 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
4055 // f64: Or the high part with signbit and then combine two parts.
4056 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
4058 SDValue Lo = Tmp0.getValue(0);
4059 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
4060 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
4061 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
4064 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
4065 MachineFunction &MF = DAG.getMachineFunction();
4066 MachineFrameInfo *MFI = MF.getFrameInfo();
4067 MFI->setReturnAddressIsTaken(true);
4069 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
4072 EVT VT = Op.getValueType();
4074 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4076 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
4077 SDValue Offset = DAG.getConstant(4, dl, MVT::i32);
4078 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
4079 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
4080 MachinePointerInfo(), false, false, false, 0);
4083 // Return LR, which contains the return address. Mark it an implicit live-in.
4084 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
4085 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
4088 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
4089 const ARMBaseRegisterInfo &ARI =
4090 *static_cast<const ARMBaseRegisterInfo*>(RegInfo);
4091 MachineFunction &MF = DAG.getMachineFunction();
4092 MachineFrameInfo *MFI = MF.getFrameInfo();
4093 MFI->setFrameAddressIsTaken(true);
4095 EVT VT = Op.getValueType();
4096 SDLoc dl(Op); // FIXME probably not meaningful
4097 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4098 unsigned FrameReg = ARI.getFrameRegister(MF);
4099 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
4101 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
4102 MachinePointerInfo(),
4103 false, false, false, 0);
4107 // FIXME? Maybe this could be a TableGen attribute on some registers and
4108 // this table could be generated automatically from RegInfo.
4109 unsigned ARMTargetLowering::getRegisterByName(const char* RegName, EVT VT,
4110 SelectionDAG &DAG) const {
4111 unsigned Reg = StringSwitch<unsigned>(RegName)
4112 .Case("sp", ARM::SP)
4116 report_fatal_error(Twine("Invalid register name \""
4117 + StringRef(RegName) + "\"."));
4120 // Result is 64 bit value so split into two 32 bit values and return as a
4122 static void ExpandREAD_REGISTER(SDNode *N, SmallVectorImpl<SDValue> &Results,
4123 SelectionDAG &DAG) {
4126 // This function is only supposed to be called for i64 type destination.
4127 assert(N->getValueType(0) == MVT::i64
4128 && "ExpandREAD_REGISTER called for non-i64 type result.");
4130 SDValue Read = DAG.getNode(ISD::READ_REGISTER, DL,
4131 DAG.getVTList(MVT::i32, MVT::i32, MVT::Other),
4135 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Read.getValue(0),
4137 Results.push_back(Read.getOperand(0));
4140 /// ExpandBITCAST - If the target supports VFP, this function is called to
4141 /// expand a bit convert where either the source or destination type is i64 to
4142 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
4143 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
4144 /// vectors), since the legalizer won't know what to do with that.
4145 static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) {
4146 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4148 SDValue Op = N->getOperand(0);
4150 // This function is only supposed to be called for i64 types, either as the
4151 // source or destination of the bit convert.
4152 EVT SrcVT = Op.getValueType();
4153 EVT DstVT = N->getValueType(0);
4154 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
4155 "ExpandBITCAST called for non-i64 type");
4157 // Turn i64->f64 into VMOVDRR.
4158 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
4159 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
4160 DAG.getConstant(0, dl, MVT::i32));
4161 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
4162 DAG.getConstant(1, dl, MVT::i32));
4163 return DAG.getNode(ISD::BITCAST, dl, DstVT,
4164 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
4167 // Turn f64->i64 into VMOVRRD.
4168 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
4170 if (DAG.getDataLayout().isBigEndian() && SrcVT.isVector() &&
4171 SrcVT.getVectorNumElements() > 1)
4172 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
4173 DAG.getVTList(MVT::i32, MVT::i32),
4174 DAG.getNode(ARMISD::VREV64, dl, SrcVT, Op));
4176 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
4177 DAG.getVTList(MVT::i32, MVT::i32), Op);
4178 // Merge the pieces into a single i64 value.
4179 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
4185 /// getZeroVector - Returns a vector of specified type with all zero elements.
4186 /// Zero vectors are used to represent vector negation and in those cases
4187 /// will be implemented with the NEON VNEG instruction. However, VNEG does
4188 /// not support i64 elements, so sometimes the zero vectors will need to be
4189 /// explicitly constructed. Regardless, use a canonical VMOV to create the
4191 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, SDLoc dl) {
4192 assert(VT.isVector() && "Expected a vector type");
4193 // The canonical modified immediate encoding of a zero vector is....0!
4194 SDValue EncodedVal = DAG.getTargetConstant(0, dl, MVT::i32);
4195 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
4196 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
4197 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
4200 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
4201 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
4202 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
4203 SelectionDAG &DAG) const {
4204 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4205 EVT VT = Op.getValueType();
4206 unsigned VTBits = VT.getSizeInBits();
4208 SDValue ShOpLo = Op.getOperand(0);
4209 SDValue ShOpHi = Op.getOperand(1);
4210 SDValue ShAmt = Op.getOperand(2);
4212 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
4214 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
4216 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
4217 DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
4218 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
4219 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
4220 DAG.getConstant(VTBits, dl, MVT::i32));
4221 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
4222 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4223 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
4225 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4226 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
4227 ISD::SETGE, ARMcc, DAG, dl);
4228 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
4229 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
4232 SDValue Ops[2] = { Lo, Hi };
4233 return DAG.getMergeValues(Ops, dl);
4236 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
4237 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
4238 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
4239 SelectionDAG &DAG) const {
4240 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4241 EVT VT = Op.getValueType();
4242 unsigned VTBits = VT.getSizeInBits();
4244 SDValue ShOpLo = Op.getOperand(0);
4245 SDValue ShOpHi = Op.getOperand(1);
4246 SDValue ShAmt = Op.getOperand(2);
4249 assert(Op.getOpcode() == ISD::SHL_PARTS);
4250 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
4251 DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
4252 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
4253 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
4254 DAG.getConstant(VTBits, dl, MVT::i32));
4255 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
4256 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
4258 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4259 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4260 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
4261 ISD::SETGE, ARMcc, DAG, dl);
4262 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
4263 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
4266 SDValue Ops[2] = { Lo, Hi };
4267 return DAG.getMergeValues(Ops, dl);
4270 SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
4271 SelectionDAG &DAG) const {
4272 // The rounding mode is in bits 23:22 of the FPSCR.
4273 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
4274 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
4275 // so that the shift + and get folded into a bitfield extract.
4277 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
4278 DAG.getConstant(Intrinsic::arm_get_fpscr, dl,
4280 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
4281 DAG.getConstant(1U << 22, dl, MVT::i32));
4282 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
4283 DAG.getConstant(22, dl, MVT::i32));
4284 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
4285 DAG.getConstant(3, dl, MVT::i32));
4288 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
4289 const ARMSubtarget *ST) {
4291 EVT VT = N->getValueType(0);
4292 if (VT.isVector()) {
4293 assert(ST->hasNEON());
4295 // Compute the least significant set bit: LSB = X & -X
4296 SDValue X = N->getOperand(0);
4297 SDValue NX = DAG.getNode(ISD::SUB, dl, VT, getZeroVector(VT, DAG, dl), X);
4298 SDValue LSB = DAG.getNode(ISD::AND, dl, VT, X, NX);
4300 EVT ElemTy = VT.getVectorElementType();
4302 if (ElemTy == MVT::i8) {
4303 // Compute with: cttz(x) = ctpop(lsb - 1)
4304 SDValue One = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
4305 DAG.getTargetConstant(1, dl, ElemTy));
4306 SDValue Bits = DAG.getNode(ISD::SUB, dl, VT, LSB, One);
4307 return DAG.getNode(ISD::CTPOP, dl, VT, Bits);
4310 if ((ElemTy == MVT::i16 || ElemTy == MVT::i32) &&
4311 (N->getOpcode() == ISD::CTTZ_ZERO_UNDEF)) {
4312 // Compute with: cttz(x) = (width - 1) - ctlz(lsb), if x != 0
4313 unsigned NumBits = ElemTy.getSizeInBits();
4314 SDValue WidthMinus1 =
4315 DAG.getNode(ARMISD::VMOVIMM, dl, VT,
4316 DAG.getTargetConstant(NumBits - 1, dl, ElemTy));
4317 SDValue CTLZ = DAG.getNode(ISD::CTLZ, dl, VT, LSB);
4318 return DAG.getNode(ISD::SUB, dl, VT, WidthMinus1, CTLZ);
4321 // Compute with: cttz(x) = ctpop(lsb - 1)
4323 // Since we can only compute the number of bits in a byte with vcnt.8, we
4324 // have to gather the result with pairwise addition (vpaddl) for i16, i32,
4329 if (ElemTy == MVT::i64) {
4330 // Load constant 0xffff'ffff'ffff'ffff to register.
4331 SDValue FF = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
4332 DAG.getTargetConstant(0x1eff, dl, MVT::i32));
4333 Bits = DAG.getNode(ISD::ADD, dl, VT, LSB, FF);
4335 SDValue One = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
4336 DAG.getTargetConstant(1, dl, ElemTy));
4337 Bits = DAG.getNode(ISD::SUB, dl, VT, LSB, One);
4340 // Count #bits with vcnt.8.
4341 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8;
4342 SDValue BitsVT8 = DAG.getNode(ISD::BITCAST, dl, VT8Bit, Bits);
4343 SDValue Cnt8 = DAG.getNode(ISD::CTPOP, dl, VT8Bit, BitsVT8);
4345 // Gather the #bits with vpaddl (pairwise add.)
4346 EVT VT16Bit = VT.is64BitVector() ? MVT::v4i16 : MVT::v8i16;
4347 SDValue Cnt16 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT16Bit,
4348 DAG.getTargetConstant(Intrinsic::arm_neon_vpaddlu, dl, MVT::i32),
4350 if (ElemTy == MVT::i16)
4353 EVT VT32Bit = VT.is64BitVector() ? MVT::v2i32 : MVT::v4i32;
4354 SDValue Cnt32 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT32Bit,
4355 DAG.getTargetConstant(Intrinsic::arm_neon_vpaddlu, dl, MVT::i32),
4357 if (ElemTy == MVT::i32)
4360 assert(ElemTy == MVT::i64);
4361 SDValue Cnt64 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
4362 DAG.getTargetConstant(Intrinsic::arm_neon_vpaddlu, dl, MVT::i32),
4367 if (!ST->hasV6T2Ops())
4370 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
4371 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
4374 /// getCTPOP16BitCounts - Returns a v8i8/v16i8 vector containing the bit-count
4375 /// for each 16-bit element from operand, repeated. The basic idea is to
4376 /// leverage vcnt to get the 8-bit counts, gather and add the results.
4378 /// Trace for v4i16:
4379 /// input = [v0 v1 v2 v3 ] (vi 16-bit element)
4380 /// cast: N0 = [w0 w1 w2 w3 w4 w5 w6 w7] (v0 = [w0 w1], wi 8-bit element)
4381 /// vcnt: N1 = [b0 b1 b2 b3 b4 b5 b6 b7] (bi = bit-count of 8-bit element wi)
4382 /// vrev: N2 = [b1 b0 b3 b2 b5 b4 b7 b6]
4383 /// [b0 b1 b2 b3 b4 b5 b6 b7]
4384 /// +[b1 b0 b3 b2 b5 b4 b7 b6]
4385 /// N3=N1+N2 = [k0 k0 k1 k1 k2 k2 k3 k3] (k0 = b0+b1 = bit-count of 16-bit v0,
4386 /// vuzp: = [k0 k1 k2 k3 k0 k1 k2 k3] each ki is 8-bits)
4387 static SDValue getCTPOP16BitCounts(SDNode *N, SelectionDAG &DAG) {
4388 EVT VT = N->getValueType(0);
4391 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8;
4392 SDValue N0 = DAG.getNode(ISD::BITCAST, DL, VT8Bit, N->getOperand(0));
4393 SDValue N1 = DAG.getNode(ISD::CTPOP, DL, VT8Bit, N0);
4394 SDValue N2 = DAG.getNode(ARMISD::VREV16, DL, VT8Bit, N1);
4395 SDValue N3 = DAG.getNode(ISD::ADD, DL, VT8Bit, N1, N2);
4396 return DAG.getNode(ARMISD::VUZP, DL, VT8Bit, N3, N3);
4399 /// lowerCTPOP16BitElements - Returns a v4i16/v8i16 vector containing the
4400 /// bit-count for each 16-bit element from the operand. We need slightly
4401 /// different sequencing for v4i16 and v8i16 to stay within NEON's available
4402 /// 64/128-bit registers.
4404 /// Trace for v4i16:
4405 /// input = [v0 v1 v2 v3 ] (vi 16-bit element)
4406 /// v8i8: BitCounts = [k0 k1 k2 k3 k0 k1 k2 k3 ] (ki is the bit-count of vi)
4407 /// v8i16:Extended = [k0 k1 k2 k3 k0 k1 k2 k3 ]
4408 /// v4i16:Extracted = [k0 k1 k2 k3 ]
4409 static SDValue lowerCTPOP16BitElements(SDNode *N, SelectionDAG &DAG) {
4410 EVT VT = N->getValueType(0);
4413 SDValue BitCounts = getCTPOP16BitCounts(N, DAG);
4414 if (VT.is64BitVector()) {
4415 SDValue Extended = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v8i16, BitCounts);
4416 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, Extended,
4417 DAG.getIntPtrConstant(0, DL));
4419 SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v8i8,
4420 BitCounts, DAG.getIntPtrConstant(0, DL));
4421 return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v8i16, Extracted);
4425 /// lowerCTPOP32BitElements - Returns a v2i32/v4i32 vector containing the
4426 /// bit-count for each 32-bit element from the operand. The idea here is
4427 /// to split the vector into 16-bit elements, leverage the 16-bit count
4428 /// routine, and then combine the results.
4430 /// Trace for v2i32 (v4i32 similar with Extracted/Extended exchanged):
4431 /// input = [v0 v1 ] (vi: 32-bit elements)
4432 /// Bitcast = [w0 w1 w2 w3 ] (wi: 16-bit elements, v0 = [w0 w1])
4433 /// Counts16 = [k0 k1 k2 k3 ] (ki: 16-bit elements, bit-count of wi)
4434 /// vrev: N0 = [k1 k0 k3 k2 ]
4436 /// N1 =+[k1 k0 k3 k2 ]
4438 /// N2 =+[k1 k3 k0 k2 ]
4440 /// Extended =+[k1 k3 k0 k2 ]
4442 /// Extracted=+[k1 k3 ]
4444 static SDValue lowerCTPOP32BitElements(SDNode *N, SelectionDAG &DAG) {
4445 EVT VT = N->getValueType(0);
4448 EVT VT16Bit = VT.is64BitVector() ? MVT::v4i16 : MVT::v8i16;
4450 SDValue Bitcast = DAG.getNode(ISD::BITCAST, DL, VT16Bit, N->getOperand(0));
4451 SDValue Counts16 = lowerCTPOP16BitElements(Bitcast.getNode(), DAG);
4452 SDValue N0 = DAG.getNode(ARMISD::VREV32, DL, VT16Bit, Counts16);
4453 SDValue N1 = DAG.getNode(ISD::ADD, DL, VT16Bit, Counts16, N0);
4454 SDValue N2 = DAG.getNode(ARMISD::VUZP, DL, VT16Bit, N1, N1);
4456 if (VT.is64BitVector()) {
4457 SDValue Extended = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v4i32, N2);
4458 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i32, Extended,
4459 DAG.getIntPtrConstant(0, DL));
4461 SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, N2,
4462 DAG.getIntPtrConstant(0, DL));
4463 return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v4i32, Extracted);
4467 static SDValue LowerCTPOP(SDNode *N, SelectionDAG &DAG,
4468 const ARMSubtarget *ST) {
4469 EVT VT = N->getValueType(0);
4471 assert(ST->hasNEON() && "Custom ctpop lowering requires NEON.");
4472 assert((VT == MVT::v2i32 || VT == MVT::v4i32 ||
4473 VT == MVT::v4i16 || VT == MVT::v8i16) &&
4474 "Unexpected type for custom ctpop lowering");
4476 if (VT.getVectorElementType() == MVT::i32)
4477 return lowerCTPOP32BitElements(N, DAG);
4479 return lowerCTPOP16BitElements(N, DAG);
4482 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
4483 const ARMSubtarget *ST) {
4484 EVT VT = N->getValueType(0);
4490 // Lower vector shifts on NEON to use VSHL.
4491 assert(ST->hasNEON() && "unexpected vector shift");
4493 // Left shifts translate directly to the vshiftu intrinsic.
4494 if (N->getOpcode() == ISD::SHL)
4495 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
4496 DAG.getConstant(Intrinsic::arm_neon_vshiftu, dl,
4498 N->getOperand(0), N->getOperand(1));
4500 assert((N->getOpcode() == ISD::SRA ||
4501 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
4503 // NEON uses the same intrinsics for both left and right shifts. For
4504 // right shifts, the shift amounts are negative, so negate the vector of
4506 EVT ShiftVT = N->getOperand(1).getValueType();
4507 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
4508 getZeroVector(ShiftVT, DAG, dl),
4510 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
4511 Intrinsic::arm_neon_vshifts :
4512 Intrinsic::arm_neon_vshiftu);
4513 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
4514 DAG.getConstant(vshiftInt, dl, MVT::i32),
4515 N->getOperand(0), NegatedCount);
4518 static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
4519 const ARMSubtarget *ST) {
4520 EVT VT = N->getValueType(0);
4523 // We can get here for a node like i32 = ISD::SHL i32, i64
4527 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
4528 "Unknown shift to lower!");
4530 // We only lower SRA, SRL of 1 here, all others use generic lowering.
4531 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
4532 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
4535 // If we are in thumb mode, we don't have RRX.
4536 if (ST->isThumb1Only()) return SDValue();
4538 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
4539 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
4540 DAG.getConstant(0, dl, MVT::i32));
4541 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
4542 DAG.getConstant(1, dl, MVT::i32));
4544 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
4545 // captures the result into a carry flag.
4546 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
4547 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), Hi);
4549 // The low part is an ARMISD::RRX operand, which shifts the carry in.
4550 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
4552 // Merge the pieces into a single i64 value.
4553 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
4556 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
4557 SDValue TmpOp0, TmpOp1;
4558 bool Invert = false;
4562 SDValue Op0 = Op.getOperand(0);
4563 SDValue Op1 = Op.getOperand(1);
4564 SDValue CC = Op.getOperand(2);
4565 EVT CmpVT = Op0.getValueType().changeVectorElementTypeToInteger();
4566 EVT VT = Op.getValueType();
4567 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
4570 if (CmpVT.getVectorElementType() == MVT::i64)
4571 // 64-bit comparisons are not legal. We've marked SETCC as non-Custom,
4572 // but it's possible that our operands are 64-bit but our result is 32-bit.
4573 // Bail in this case.
4576 if (Op1.getValueType().isFloatingPoint()) {
4577 switch (SetCCOpcode) {
4578 default: llvm_unreachable("Illegal FP comparison");
4580 case ISD::SETNE: Invert = true; // Fallthrough
4582 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
4584 case ISD::SETLT: Swap = true; // Fallthrough
4586 case ISD::SETGT: Opc = ARMISD::VCGT; break;
4588 case ISD::SETLE: Swap = true; // Fallthrough
4590 case ISD::SETGE: Opc = ARMISD::VCGE; break;
4591 case ISD::SETUGE: Swap = true; // Fallthrough
4592 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
4593 case ISD::SETUGT: Swap = true; // Fallthrough
4594 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
4595 case ISD::SETUEQ: Invert = true; // Fallthrough
4597 // Expand this to (OLT | OGT).
4601 Op0 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp1, TmpOp0);
4602 Op1 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp0, TmpOp1);
4604 case ISD::SETUO: Invert = true; // Fallthrough
4606 // Expand this to (OLT | OGE).
4610 Op0 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp1, TmpOp0);
4611 Op1 = DAG.getNode(ARMISD::VCGE, dl, CmpVT, TmpOp0, TmpOp1);
4615 // Integer comparisons.
4616 switch (SetCCOpcode) {
4617 default: llvm_unreachable("Illegal integer comparison");
4618 case ISD::SETNE: Invert = true;
4619 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
4620 case ISD::SETLT: Swap = true;
4621 case ISD::SETGT: Opc = ARMISD::VCGT; break;
4622 case ISD::SETLE: Swap = true;
4623 case ISD::SETGE: Opc = ARMISD::VCGE; break;
4624 case ISD::SETULT: Swap = true;
4625 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
4626 case ISD::SETULE: Swap = true;
4627 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
4630 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
4631 if (Opc == ARMISD::VCEQ) {
4634 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
4636 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
4639 // Ignore bitconvert.
4640 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST)
4641 AndOp = AndOp.getOperand(0);
4643 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
4645 Op0 = DAG.getNode(ISD::BITCAST, dl, CmpVT, AndOp.getOperand(0));
4646 Op1 = DAG.getNode(ISD::BITCAST, dl, CmpVT, AndOp.getOperand(1));
4653 std::swap(Op0, Op1);
4655 // If one of the operands is a constant vector zero, attempt to fold the
4656 // comparison to a specialized compare-against-zero form.
4658 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
4660 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) {
4661 if (Opc == ARMISD::VCGE)
4662 Opc = ARMISD::VCLEZ;
4663 else if (Opc == ARMISD::VCGT)
4664 Opc = ARMISD::VCLTZ;
4669 if (SingleOp.getNode()) {
4672 Result = DAG.getNode(ARMISD::VCEQZ, dl, CmpVT, SingleOp); break;
4674 Result = DAG.getNode(ARMISD::VCGEZ, dl, CmpVT, SingleOp); break;
4676 Result = DAG.getNode(ARMISD::VCLEZ, dl, CmpVT, SingleOp); break;
4678 Result = DAG.getNode(ARMISD::VCGTZ, dl, CmpVT, SingleOp); break;
4680 Result = DAG.getNode(ARMISD::VCLTZ, dl, CmpVT, SingleOp); break;
4682 Result = DAG.getNode(Opc, dl, CmpVT, Op0, Op1);
4685 Result = DAG.getNode(Opc, dl, CmpVT, Op0, Op1);
4688 Result = DAG.getSExtOrTrunc(Result, dl, VT);
4691 Result = DAG.getNOT(dl, Result, VT);
4696 /// isNEONModifiedImm - Check if the specified splat value corresponds to a
4697 /// valid vector constant for a NEON instruction with a "modified immediate"
4698 /// operand (e.g., VMOV). If so, return the encoded value.
4699 static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
4700 unsigned SplatBitSize, SelectionDAG &DAG,
4701 SDLoc dl, EVT &VT, bool is128Bits,
4702 NEONModImmType type) {
4703 unsigned OpCmode, Imm;
4705 // SplatBitSize is set to the smallest size that splats the vector, so a
4706 // zero vector will always have SplatBitSize == 8. However, NEON modified
4707 // immediate instructions others than VMOV do not support the 8-bit encoding
4708 // of a zero vector, and the default encoding of zero is supposed to be the
4713 switch (SplatBitSize) {
4715 if (type != VMOVModImm)
4717 // Any 1-byte value is OK. Op=0, Cmode=1110.
4718 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
4721 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
4725 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
4726 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
4727 if ((SplatBits & ~0xff) == 0) {
4728 // Value = 0x00nn: Op=x, Cmode=100x.
4733 if ((SplatBits & ~0xff00) == 0) {
4734 // Value = 0xnn00: Op=x, Cmode=101x.
4736 Imm = SplatBits >> 8;
4742 // NEON's 32-bit VMOV supports splat values where:
4743 // * only one byte is nonzero, or
4744 // * the least significant byte is 0xff and the second byte is nonzero, or
4745 // * the least significant 2 bytes are 0xff and the third is nonzero.
4746 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
4747 if ((SplatBits & ~0xff) == 0) {
4748 // Value = 0x000000nn: Op=x, Cmode=000x.
4753 if ((SplatBits & ~0xff00) == 0) {
4754 // Value = 0x0000nn00: Op=x, Cmode=001x.
4756 Imm = SplatBits >> 8;
4759 if ((SplatBits & ~0xff0000) == 0) {
4760 // Value = 0x00nn0000: Op=x, Cmode=010x.
4762 Imm = SplatBits >> 16;
4765 if ((SplatBits & ~0xff000000) == 0) {
4766 // Value = 0xnn000000: Op=x, Cmode=011x.
4768 Imm = SplatBits >> 24;
4772 // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC
4773 if (type == OtherModImm) return SDValue();
4775 if ((SplatBits & ~0xffff) == 0 &&
4776 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
4777 // Value = 0x0000nnff: Op=x, Cmode=1100.
4779 Imm = SplatBits >> 8;
4783 if ((SplatBits & ~0xffffff) == 0 &&
4784 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
4785 // Value = 0x00nnffff: Op=x, Cmode=1101.
4787 Imm = SplatBits >> 16;
4791 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
4792 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
4793 // VMOV.I32. A (very) minor optimization would be to replicate the value
4794 // and fall through here to test for a valid 64-bit splat. But, then the
4795 // caller would also need to check and handle the change in size.
4799 if (type != VMOVModImm)
4801 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
4802 uint64_t BitMask = 0xff;
4804 unsigned ImmMask = 1;
4806 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
4807 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
4810 } else if ((SplatBits & BitMask) != 0) {
4817 if (DAG.getDataLayout().isBigEndian())
4818 // swap higher and lower 32 bit word
4819 Imm = ((Imm & 0xf) << 4) | ((Imm & 0xf0) >> 4);
4821 // Op=1, Cmode=1110.
4823 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
4828 llvm_unreachable("unexpected size for isNEONModifiedImm");
4831 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
4832 return DAG.getTargetConstant(EncodedVal, dl, MVT::i32);
4835 SDValue ARMTargetLowering::LowerConstantFP(SDValue Op, SelectionDAG &DAG,
4836 const ARMSubtarget *ST) const {
4840 bool IsDouble = Op.getValueType() == MVT::f64;
4841 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Op);
4843 // Use the default (constant pool) lowering for double constants when we have
4845 if (IsDouble && Subtarget->isFPOnlySP())
4848 // Try splatting with a VMOV.f32...
4849 APFloat FPVal = CFP->getValueAPF();
4850 int ImmVal = IsDouble ? ARM_AM::getFP64Imm(FPVal) : ARM_AM::getFP32Imm(FPVal);
4853 if (IsDouble || !ST->useNEONForSinglePrecisionFP()) {
4854 // We have code in place to select a valid ConstantFP already, no need to
4859 // It's a float and we are trying to use NEON operations where
4860 // possible. Lower it to a splat followed by an extract.
4862 SDValue NewVal = DAG.getTargetConstant(ImmVal, DL, MVT::i32);
4863 SDValue VecConstant = DAG.getNode(ARMISD::VMOVFPIMM, DL, MVT::v2f32,
4865 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecConstant,
4866 DAG.getConstant(0, DL, MVT::i32));
4869 // The rest of our options are NEON only, make sure that's allowed before
4871 if (!ST->hasNEON() || (!IsDouble && !ST->useNEONForSinglePrecisionFP()))
4875 uint64_t iVal = FPVal.bitcastToAPInt().getZExtValue();
4877 // It wouldn't really be worth bothering for doubles except for one very
4878 // important value, which does happen to match: 0.0. So make sure we don't do
4880 if (IsDouble && (iVal & 0xffffffff) != (iVal >> 32))
4883 // Try a VMOV.i32 (FIXME: i8, i16, or i64 could work too).
4884 SDValue NewVal = isNEONModifiedImm(iVal & 0xffffffffU, 0, 32, DAG, SDLoc(Op),
4885 VMovVT, false, VMOVModImm);
4886 if (NewVal != SDValue()) {
4888 SDValue VecConstant = DAG.getNode(ARMISD::VMOVIMM, DL, VMovVT,
4891 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant);
4893 // It's a float: cast and extract a vector element.
4894 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32,
4896 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant,
4897 DAG.getConstant(0, DL, MVT::i32));
4900 // Finally, try a VMVN.i32
4901 NewVal = isNEONModifiedImm(~iVal & 0xffffffffU, 0, 32, DAG, SDLoc(Op), VMovVT,
4903 if (NewVal != SDValue()) {
4905 SDValue VecConstant = DAG.getNode(ARMISD::VMVNIMM, DL, VMovVT, NewVal);
4908 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant);
4910 // It's a float: cast and extract a vector element.
4911 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32,
4913 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant,
4914 DAG.getConstant(0, DL, MVT::i32));
4920 // check if an VEXT instruction can handle the shuffle mask when the
4921 // vector sources of the shuffle are the same.
4922 static bool isSingletonVEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
4923 unsigned NumElts = VT.getVectorNumElements();
4925 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4931 // If this is a VEXT shuffle, the immediate value is the index of the first
4932 // element. The other shuffle indices must be the successive elements after
4934 unsigned ExpectedElt = Imm;
4935 for (unsigned i = 1; i < NumElts; ++i) {
4936 // Increment the expected index. If it wraps around, just follow it
4937 // back to index zero and keep going.
4939 if (ExpectedElt == NumElts)
4942 if (M[i] < 0) continue; // ignore UNDEF indices
4943 if (ExpectedElt != static_cast<unsigned>(M[i]))
4951 static bool isVEXTMask(ArrayRef<int> M, EVT VT,
4952 bool &ReverseVEXT, unsigned &Imm) {
4953 unsigned NumElts = VT.getVectorNumElements();
4954 ReverseVEXT = false;
4956 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4962 // If this is a VEXT shuffle, the immediate value is the index of the first
4963 // element. The other shuffle indices must be the successive elements after
4965 unsigned ExpectedElt = Imm;
4966 for (unsigned i = 1; i < NumElts; ++i) {
4967 // Increment the expected index. If it wraps around, it may still be
4968 // a VEXT but the source vectors must be swapped.
4970 if (ExpectedElt == NumElts * 2) {
4975 if (M[i] < 0) continue; // ignore UNDEF indices
4976 if (ExpectedElt != static_cast<unsigned>(M[i]))
4980 // Adjust the index value if the source operands will be swapped.
4987 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
4988 /// instruction with the specified blocksize. (The order of the elements
4989 /// within each block of the vector is reversed.)
4990 static bool isVREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
4991 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
4992 "Only possible block sizes for VREV are: 16, 32, 64");
4994 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4998 unsigned NumElts = VT.getVectorNumElements();
4999 unsigned BlockElts = M[0] + 1;
5000 // If the first shuffle index is UNDEF, be optimistic.
5002 BlockElts = BlockSize / EltSz;
5004 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
5007 for (unsigned i = 0; i < NumElts; ++i) {
5008 if (M[i] < 0) continue; // ignore UNDEF indices
5009 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
5016 static bool isVTBLMask(ArrayRef<int> M, EVT VT) {
5017 // We can handle <8 x i8> vector shuffles. If the index in the mask is out of
5018 // range, then 0 is placed into the resulting vector. So pretty much any mask
5019 // of 8 elements can work here.
5020 return VT == MVT::v8i8 && M.size() == 8;
5023 // Checks whether the shuffle mask represents a vector transpose (VTRN) by
5024 // checking that pairs of elements in the shuffle mask represent the same index
5025 // in each vector, incrementing the expected index by 2 at each step.
5026 // e.g. For v1,v2 of type v4i32 a valid shuffle mask is: [0, 4, 2, 6]
5027 // v1={a,b,c,d} => x=shufflevector v1, v2 shufflemask => x={a,e,c,g}
5029 // WhichResult gives the offset for each element in the mask based on which
5030 // of the two results it belongs to.
5032 // The transpose can be represented either as:
5033 // result1 = shufflevector v1, v2, result1_shuffle_mask
5034 // result2 = shufflevector v1, v2, result2_shuffle_mask
5035 // where v1/v2 and the shuffle masks have the same number of elements
5036 // (here WhichResult (see below) indicates which result is being checked)
5039 // results = shufflevector v1, v2, shuffle_mask
5040 // where both results are returned in one vector and the shuffle mask has twice
5041 // as many elements as v1/v2 (here WhichResult will always be 0 if true) here we
5042 // want to check the low half and high half of the shuffle mask as if it were
5044 static bool isVTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5045 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
5049 unsigned NumElts = VT.getVectorNumElements();
5050 if (M.size() != NumElts && M.size() != NumElts*2)
5053 // If the mask is twice as long as the input vector then we need to check the
5054 // upper and lower parts of the mask with a matching value for WhichResult
5055 // FIXME: A mask with only even values will be rejected in case the first
5056 // element is undefined, e.g. [-1, 4, 2, 6] will be rejected, because only
5057 // M[0] is used to determine WhichResult
5058 for (unsigned i = 0; i < M.size(); i += NumElts) {
5059 if (M.size() == NumElts * 2)
5060 WhichResult = i / NumElts;
5062 WhichResult = M[i] == 0 ? 0 : 1;
5063 for (unsigned j = 0; j < NumElts; j += 2) {
5064 if ((M[i+j] >= 0 && (unsigned) M[i+j] != j + WhichResult) ||
5065 (M[i+j+1] >= 0 && (unsigned) M[i+j+1] != j + NumElts + WhichResult))
5070 if (M.size() == NumElts*2)
5076 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
5077 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
5078 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
5079 static bool isVTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
5080 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
5084 unsigned NumElts = VT.getVectorNumElements();
5085 if (M.size() != NumElts && M.size() != NumElts*2)
5088 for (unsigned i = 0; i < M.size(); i += NumElts) {
5089 if (M.size() == NumElts * 2)
5090 WhichResult = i / NumElts;
5092 WhichResult = M[i] == 0 ? 0 : 1;
5093 for (unsigned j = 0; j < NumElts; j += 2) {
5094 if ((M[i+j] >= 0 && (unsigned) M[i+j] != j + WhichResult) ||
5095 (M[i+j+1] >= 0 && (unsigned) M[i+j+1] != j + WhichResult))
5100 if (M.size() == NumElts*2)
5106 // Checks whether the shuffle mask represents a vector unzip (VUZP) by checking
5107 // that the mask elements are either all even and in steps of size 2 or all odd
5108 // and in steps of size 2.
5109 // e.g. For v1,v2 of type v4i32 a valid shuffle mask is: [0, 2, 4, 6]
5110 // v1={a,b,c,d} => x=shufflevector v1, v2 shufflemask => x={a,c,e,g}
5112 // Requires similar checks to that of isVTRNMask with
5113 // respect the how results are returned.
5114 static bool isVUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5115 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
5119 unsigned NumElts = VT.getVectorNumElements();
5120 if (M.size() != NumElts && M.size() != NumElts*2)
5123 for (unsigned i = 0; i < M.size(); i += NumElts) {
5124 WhichResult = M[i] == 0 ? 0 : 1;
5125 for (unsigned j = 0; j < NumElts; ++j) {
5126 if (M[i+j] >= 0 && (unsigned) M[i+j] != 2 * j + WhichResult)
5131 if (M.size() == NumElts*2)
5134 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
5135 if (VT.is64BitVector() && EltSz == 32)
5141 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
5142 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
5143 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
5144 static bool isVUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
5145 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
5149 unsigned NumElts = VT.getVectorNumElements();
5150 if (M.size() != NumElts && M.size() != NumElts*2)
5153 unsigned Half = NumElts / 2;
5154 for (unsigned i = 0; i < M.size(); i += NumElts) {
5155 WhichResult = M[i] == 0 ? 0 : 1;
5156 for (unsigned j = 0; j < NumElts; j += Half) {
5157 unsigned Idx = WhichResult;
5158 for (unsigned k = 0; k < Half; ++k) {
5159 int MIdx = M[i + j + k];
5160 if (MIdx >= 0 && (unsigned) MIdx != Idx)
5167 if (M.size() == NumElts*2)
5170 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
5171 if (VT.is64BitVector() && EltSz == 32)
5177 // Checks whether the shuffle mask represents a vector zip (VZIP) by checking
5178 // that pairs of elements of the shufflemask represent the same index in each
5179 // vector incrementing sequentially through the vectors.
5180 // e.g. For v1,v2 of type v4i32 a valid shuffle mask is: [0, 4, 1, 5]
5181 // v1={a,b,c,d} => x=shufflevector v1, v2 shufflemask => x={a,e,b,f}
5183 // Requires similar checks to that of isVTRNMask with respect the how results
5185 static bool isVZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5186 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
5190 unsigned NumElts = VT.getVectorNumElements();
5191 if (M.size() != NumElts && M.size() != NumElts*2)
5194 for (unsigned i = 0; i < M.size(); i += NumElts) {
5195 WhichResult = M[i] == 0 ? 0 : 1;
5196 unsigned Idx = WhichResult * NumElts / 2;
5197 for (unsigned j = 0; j < NumElts; j += 2) {
5198 if ((M[i+j] >= 0 && (unsigned) M[i+j] != Idx) ||
5199 (M[i+j+1] >= 0 && (unsigned) M[i+j+1] != Idx + NumElts))
5205 if (M.size() == NumElts*2)
5208 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
5209 if (VT.is64BitVector() && EltSz == 32)
5215 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
5216 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
5217 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
5218 static bool isVZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
5219 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
5223 unsigned NumElts = VT.getVectorNumElements();
5224 if (M.size() != NumElts && M.size() != NumElts*2)
5227 for (unsigned i = 0; i < M.size(); i += NumElts) {
5228 WhichResult = M[i] == 0 ? 0 : 1;
5229 unsigned Idx = WhichResult * NumElts / 2;
5230 for (unsigned j = 0; j < NumElts; j += 2) {
5231 if ((M[i+j] >= 0 && (unsigned) M[i+j] != Idx) ||
5232 (M[i+j+1] >= 0 && (unsigned) M[i+j+1] != Idx))
5238 if (M.size() == NumElts*2)
5241 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
5242 if (VT.is64BitVector() && EltSz == 32)
5248 /// Check if \p ShuffleMask is a NEON two-result shuffle (VZIP, VUZP, VTRN),
5249 /// and return the corresponding ARMISD opcode if it is, or 0 if it isn't.
5250 static unsigned isNEONTwoResultShuffleMask(ArrayRef<int> ShuffleMask, EVT VT,
5251 unsigned &WhichResult,
5254 if (isVTRNMask(ShuffleMask, VT, WhichResult))
5255 return ARMISD::VTRN;
5256 if (isVUZPMask(ShuffleMask, VT, WhichResult))
5257 return ARMISD::VUZP;
5258 if (isVZIPMask(ShuffleMask, VT, WhichResult))
5259 return ARMISD::VZIP;
5262 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
5263 return ARMISD::VTRN;
5264 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
5265 return ARMISD::VUZP;
5266 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
5267 return ARMISD::VZIP;
5272 /// \return true if this is a reverse operation on an vector.
5273 static bool isReverseMask(ArrayRef<int> M, EVT VT) {
5274 unsigned NumElts = VT.getVectorNumElements();
5275 // Make sure the mask has the right size.
5276 if (NumElts != M.size())
5279 // Look for <15, ..., 3, -1, 1, 0>.
5280 for (unsigned i = 0; i != NumElts; ++i)
5281 if (M[i] >= 0 && M[i] != (int) (NumElts - 1 - i))
5287 // If N is an integer constant that can be moved into a register in one
5288 // instruction, return an SDValue of such a constant (will become a MOV
5289 // instruction). Otherwise return null.
5290 static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG,
5291 const ARMSubtarget *ST, SDLoc dl) {
5293 if (!isa<ConstantSDNode>(N))
5295 Val = cast<ConstantSDNode>(N)->getZExtValue();
5297 if (ST->isThumb1Only()) {
5298 if (Val <= 255 || ~Val <= 255)
5299 return DAG.getConstant(Val, dl, MVT::i32);
5301 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1)
5302 return DAG.getConstant(Val, dl, MVT::i32);
5307 // If this is a case we can't handle, return null and let the default
5308 // expansion code take care of it.
5309 SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
5310 const ARMSubtarget *ST) const {
5311 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
5313 EVT VT = Op.getValueType();
5315 APInt SplatBits, SplatUndef;
5316 unsigned SplatBitSize;
5318 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5319 if (SplatBitSize <= 64) {
5320 // Check if an immediate VMOV works.
5322 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
5323 SplatUndef.getZExtValue(), SplatBitSize,
5324 DAG, dl, VmovVT, VT.is128BitVector(),
5326 if (Val.getNode()) {
5327 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
5328 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
5331 // Try an immediate VMVN.
5332 uint64_t NegatedImm = (~SplatBits).getZExtValue();
5333 Val = isNEONModifiedImm(NegatedImm,
5334 SplatUndef.getZExtValue(), SplatBitSize,
5335 DAG, dl, VmovVT, VT.is128BitVector(),
5337 if (Val.getNode()) {
5338 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
5339 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
5342 // Use vmov.f32 to materialize other v2f32 and v4f32 splats.
5343 if ((VT == MVT::v2f32 || VT == MVT::v4f32) && SplatBitSize == 32) {
5344 int ImmVal = ARM_AM::getFP32Imm(SplatBits);
5346 SDValue Val = DAG.getTargetConstant(ImmVal, dl, MVT::i32);
5347 return DAG.getNode(ARMISD::VMOVFPIMM, dl, VT, Val);
5353 // Scan through the operands to see if only one value is used.
5355 // As an optimisation, even if more than one value is used it may be more
5356 // profitable to splat with one value then change some lanes.
5358 // Heuristically we decide to do this if the vector has a "dominant" value,
5359 // defined as splatted to more than half of the lanes.
5360 unsigned NumElts = VT.getVectorNumElements();
5361 bool isOnlyLowElement = true;
5362 bool usesOnlyOneValue = true;
5363 bool hasDominantValue = false;
5364 bool isConstant = true;
5366 // Map of the number of times a particular SDValue appears in the
5368 DenseMap<SDValue, unsigned> ValueCounts;
5370 for (unsigned i = 0; i < NumElts; ++i) {
5371 SDValue V = Op.getOperand(i);
5372 if (V.getOpcode() == ISD::UNDEF)
5375 isOnlyLowElement = false;
5376 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
5379 ValueCounts.insert(std::make_pair(V, 0));
5380 unsigned &Count = ValueCounts[V];
5382 // Is this value dominant? (takes up more than half of the lanes)
5383 if (++Count > (NumElts / 2)) {
5384 hasDominantValue = true;
5388 if (ValueCounts.size() != 1)
5389 usesOnlyOneValue = false;
5390 if (!Value.getNode() && ValueCounts.size() > 0)
5391 Value = ValueCounts.begin()->first;
5393 if (ValueCounts.size() == 0)
5394 return DAG.getUNDEF(VT);
5396 // Loads are better lowered with insert_vector_elt/ARMISD::BUILD_VECTOR.
5397 // Keep going if we are hitting this case.
5398 if (isOnlyLowElement && !ISD::isNormalLoad(Value.getNode()))
5399 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
5401 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5403 // Use VDUP for non-constant splats. For f32 constant splats, reduce to
5404 // i32 and try again.
5405 if (hasDominantValue && EltSize <= 32) {
5409 // If we are VDUPing a value that comes directly from a vector, that will
5410 // cause an unnecessary move to and from a GPR, where instead we could
5411 // just use VDUPLANE. We can only do this if the lane being extracted
5412 // is at a constant index, as the VDUP from lane instructions only have
5413 // constant-index forms.
5414 if (Value->getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5415 isa<ConstantSDNode>(Value->getOperand(1))) {
5416 // We need to create a new undef vector to use for the VDUPLANE if the
5417 // size of the vector from which we get the value is different than the
5418 // size of the vector that we need to create. We will insert the element
5419 // such that the register coalescer will remove unnecessary copies.
5420 if (VT != Value->getOperand(0).getValueType()) {
5421 ConstantSDNode *constIndex;
5422 constIndex = dyn_cast<ConstantSDNode>(Value->getOperand(1));
5423 assert(constIndex && "The index is not a constant!");
5424 unsigned index = constIndex->getAPIntValue().getLimitedValue() %
5425 VT.getVectorNumElements();
5426 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT,
5427 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DAG.getUNDEF(VT),
5428 Value, DAG.getConstant(index, dl, MVT::i32)),
5429 DAG.getConstant(index, dl, MVT::i32));
5431 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT,
5432 Value->getOperand(0), Value->getOperand(1));
5434 N = DAG.getNode(ARMISD::VDUP, dl, VT, Value);
5436 if (!usesOnlyOneValue) {
5437 // The dominant value was splatted as 'N', but we now have to insert
5438 // all differing elements.
5439 for (unsigned I = 0; I < NumElts; ++I) {
5440 if (Op.getOperand(I) == Value)
5442 SmallVector<SDValue, 3> Ops;
5444 Ops.push_back(Op.getOperand(I));
5445 Ops.push_back(DAG.getConstant(I, dl, MVT::i32));
5446 N = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Ops);
5451 if (VT.getVectorElementType().isFloatingPoint()) {
5452 SmallVector<SDValue, 8> Ops;
5453 for (unsigned i = 0; i < NumElts; ++i)
5454 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32,
5456 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
5457 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
5458 Val = LowerBUILD_VECTOR(Val, DAG, ST);
5460 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5462 if (usesOnlyOneValue) {
5463 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
5464 if (isConstant && Val.getNode())
5465 return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
5469 // If all elements are constants and the case above didn't get hit, fall back
5470 // to the default expansion, which will generate a load from the constant
5475 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
5477 SDValue shuffle = ReconstructShuffle(Op, DAG);
5478 if (shuffle != SDValue())
5482 // Vectors with 32- or 64-bit elements can be built by directly assigning
5483 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
5484 // will be legalized.
5485 if (EltSize >= 32) {
5486 // Do the expansion with floating-point types, since that is what the VFP
5487 // registers are defined to use, and since i64 is not legal.
5488 EVT EltVT = EVT::getFloatingPointVT(EltSize);
5489 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
5490 SmallVector<SDValue, 8> Ops;
5491 for (unsigned i = 0; i < NumElts; ++i)
5492 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i)));
5493 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops);
5494 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5497 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
5498 // know the default expansion would otherwise fall back on something even
5499 // worse. For a vector with one or two non-undef values, that's
5500 // scalar_to_vector for the elements followed by a shuffle (provided the
5501 // shuffle is valid for the target) and materialization element by element
5502 // on the stack followed by a load for everything else.
5503 if (!isConstant && !usesOnlyOneValue) {
5504 SDValue Vec = DAG.getUNDEF(VT);
5505 for (unsigned i = 0 ; i < NumElts; ++i) {
5506 SDValue V = Op.getOperand(i);
5507 if (V.getOpcode() == ISD::UNDEF)
5509 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i32);
5510 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
5518 // Gather data to see if the operation can be modelled as a
5519 // shuffle in combination with VEXTs.
5520 SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
5521 SelectionDAG &DAG) const {
5522 assert(Op.getOpcode() == ISD::BUILD_VECTOR && "Unknown opcode!");
5524 EVT VT = Op.getValueType();
5525 unsigned NumElts = VT.getVectorNumElements();
5527 struct ShuffleSourceInfo {
5532 // We may insert some combination of BITCASTs and VEXT nodes to force Vec to
5533 // be compatible with the shuffle we intend to construct. As a result
5534 // ShuffleVec will be some sliding window into the original Vec.
5537 // Code should guarantee that element i in Vec starts at element "WindowBase
5538 // + i * WindowScale in ShuffleVec".
5542 bool operator ==(SDValue OtherVec) { return Vec == OtherVec; }
5543 ShuffleSourceInfo(SDValue Vec)
5544 : Vec(Vec), MinElt(UINT_MAX), MaxElt(0), ShuffleVec(Vec), WindowBase(0),
5548 // First gather all vectors used as an immediate source for this BUILD_VECTOR
5550 SmallVector<ShuffleSourceInfo, 2> Sources;
5551 for (unsigned i = 0; i < NumElts; ++i) {
5552 SDValue V = Op.getOperand(i);
5553 if (V.getOpcode() == ISD::UNDEF)
5555 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
5556 // A shuffle can only come from building a vector from various
5557 // elements of other vectors.
5559 } else if (!isa<ConstantSDNode>(V.getOperand(1))) {
5560 // Furthermore, shuffles require a constant mask, whereas extractelts
5561 // accept variable indices.
5565 // Add this element source to the list if it's not already there.
5566 SDValue SourceVec = V.getOperand(0);
5567 auto Source = std::find(Sources.begin(), Sources.end(), SourceVec);
5568 if (Source == Sources.end())
5569 Source = Sources.insert(Sources.end(), ShuffleSourceInfo(SourceVec));
5571 // Update the minimum and maximum lane number seen.
5572 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
5573 Source->MinElt = std::min(Source->MinElt, EltNo);
5574 Source->MaxElt = std::max(Source->MaxElt, EltNo);
5577 // Currently only do something sane when at most two source vectors
5579 if (Sources.size() > 2)
5582 // Find out the smallest element size among result and two sources, and use
5583 // it as element size to build the shuffle_vector.
5584 EVT SmallestEltTy = VT.getVectorElementType();
5585 for (auto &Source : Sources) {
5586 EVT SrcEltTy = Source.Vec.getValueType().getVectorElementType();
5587 if (SrcEltTy.bitsLT(SmallestEltTy))
5588 SmallestEltTy = SrcEltTy;
5590 unsigned ResMultiplier =
5591 VT.getVectorElementType().getSizeInBits() / SmallestEltTy.getSizeInBits();
5592 NumElts = VT.getSizeInBits() / SmallestEltTy.getSizeInBits();
5593 EVT ShuffleVT = EVT::getVectorVT(*DAG.getContext(), SmallestEltTy, NumElts);
5595 // If the source vector is too wide or too narrow, we may nevertheless be able
5596 // to construct a compatible shuffle either by concatenating it with UNDEF or
5597 // extracting a suitable range of elements.
5598 for (auto &Src : Sources) {
5599 EVT SrcVT = Src.ShuffleVec.getValueType();
5601 if (SrcVT.getSizeInBits() == VT.getSizeInBits())
5604 // This stage of the search produces a source with the same element type as
5605 // the original, but with a total width matching the BUILD_VECTOR output.
5606 EVT EltVT = SrcVT.getVectorElementType();
5607 unsigned NumSrcElts = VT.getSizeInBits() / EltVT.getSizeInBits();
5608 EVT DestVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumSrcElts);
5610 if (SrcVT.getSizeInBits() < VT.getSizeInBits()) {
5611 if (2 * SrcVT.getSizeInBits() != VT.getSizeInBits())
5613 // We can pad out the smaller vector for free, so if it's part of a
5616 DAG.getNode(ISD::CONCAT_VECTORS, dl, DestVT, Src.ShuffleVec,
5617 DAG.getUNDEF(Src.ShuffleVec.getValueType()));
5621 if (SrcVT.getSizeInBits() != 2 * VT.getSizeInBits())
5624 if (Src.MaxElt - Src.MinElt >= NumSrcElts) {
5625 // Span too large for a VEXT to cope
5629 if (Src.MinElt >= NumSrcElts) {
5630 // The extraction can just take the second half
5632 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
5633 DAG.getConstant(NumSrcElts, dl, MVT::i32));
5634 Src.WindowBase = -NumSrcElts;
5635 } else if (Src.MaxElt < NumSrcElts) {
5636 // The extraction can just take the first half
5638 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
5639 DAG.getConstant(0, dl, MVT::i32));
5641 // An actual VEXT is needed
5643 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
5644 DAG.getConstant(0, dl, MVT::i32));
5646 DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, DestVT, Src.ShuffleVec,
5647 DAG.getConstant(NumSrcElts, dl, MVT::i32));
5649 Src.ShuffleVec = DAG.getNode(ARMISD::VEXT, dl, DestVT, VEXTSrc1,
5651 DAG.getConstant(Src.MinElt, dl, MVT::i32));
5652 Src.WindowBase = -Src.MinElt;
5656 // Another possible incompatibility occurs from the vector element types. We
5657 // can fix this by bitcasting the source vectors to the same type we intend
5659 for (auto &Src : Sources) {
5660 EVT SrcEltTy = Src.ShuffleVec.getValueType().getVectorElementType();
5661 if (SrcEltTy == SmallestEltTy)
5663 assert(ShuffleVT.getVectorElementType() == SmallestEltTy);
5664 Src.ShuffleVec = DAG.getNode(ISD::BITCAST, dl, ShuffleVT, Src.ShuffleVec);
5665 Src.WindowScale = SrcEltTy.getSizeInBits() / SmallestEltTy.getSizeInBits();
5666 Src.WindowBase *= Src.WindowScale;
5669 // Final sanity check before we try to actually produce a shuffle.
5671 for (auto Src : Sources)
5672 assert(Src.ShuffleVec.getValueType() == ShuffleVT);
5675 // The stars all align, our next step is to produce the mask for the shuffle.
5676 SmallVector<int, 8> Mask(ShuffleVT.getVectorNumElements(), -1);
5677 int BitsPerShuffleLane = ShuffleVT.getVectorElementType().getSizeInBits();
5678 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
5679 SDValue Entry = Op.getOperand(i);
5680 if (Entry.getOpcode() == ISD::UNDEF)
5683 auto Src = std::find(Sources.begin(), Sources.end(), Entry.getOperand(0));
5684 int EltNo = cast<ConstantSDNode>(Entry.getOperand(1))->getSExtValue();
5686 // EXTRACT_VECTOR_ELT performs an implicit any_ext; BUILD_VECTOR an implicit
5687 // trunc. So only std::min(SrcBits, DestBits) actually get defined in this
5689 EVT OrigEltTy = Entry.getOperand(0).getValueType().getVectorElementType();
5690 int BitsDefined = std::min(OrigEltTy.getSizeInBits(),
5691 VT.getVectorElementType().getSizeInBits());
5692 int LanesDefined = BitsDefined / BitsPerShuffleLane;
5694 // This source is expected to fill ResMultiplier lanes of the final shuffle,
5695 // starting at the appropriate offset.
5696 int *LaneMask = &Mask[i * ResMultiplier];
5698 int ExtractBase = EltNo * Src->WindowScale + Src->WindowBase;
5699 ExtractBase += NumElts * (Src - Sources.begin());
5700 for (int j = 0; j < LanesDefined; ++j)
5701 LaneMask[j] = ExtractBase + j;
5704 // Final check before we try to produce nonsense...
5705 if (!isShuffleMaskLegal(Mask, ShuffleVT))
5708 // We can't handle more than two sources. This should have already
5709 // been checked before this point.
5710 assert(Sources.size() <= 2 && "Too many sources!");
5712 SDValue ShuffleOps[] = { DAG.getUNDEF(ShuffleVT), DAG.getUNDEF(ShuffleVT) };
5713 for (unsigned i = 0; i < Sources.size(); ++i)
5714 ShuffleOps[i] = Sources[i].ShuffleVec;
5716 SDValue Shuffle = DAG.getVectorShuffle(ShuffleVT, dl, ShuffleOps[0],
5717 ShuffleOps[1], &Mask[0]);
5718 return DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);
5721 /// isShuffleMaskLegal - Targets can use this to indicate that they only
5722 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
5723 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
5724 /// are assumed to be legal.
5726 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
5728 if (VT.getVectorNumElements() == 4 &&
5729 (VT.is128BitVector() || VT.is64BitVector())) {
5730 unsigned PFIndexes[4];
5731 for (unsigned i = 0; i != 4; ++i) {
5735 PFIndexes[i] = M[i];
5738 // Compute the index in the perfect shuffle table.
5739 unsigned PFTableIndex =
5740 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5741 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5742 unsigned Cost = (PFEntry >> 30);
5748 bool ReverseVEXT, isV_UNDEF;
5749 unsigned Imm, WhichResult;
5751 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5752 return (EltSize >= 32 ||
5753 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
5754 isVREVMask(M, VT, 64) ||
5755 isVREVMask(M, VT, 32) ||
5756 isVREVMask(M, VT, 16) ||
5757 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
5758 isVTBLMask(M, VT) ||
5759 isNEONTwoResultShuffleMask(M, VT, WhichResult, isV_UNDEF) ||
5760 ((VT == MVT::v8i16 || VT == MVT::v16i8) && isReverseMask(M, VT)));
5763 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5764 /// the specified operations to build the shuffle.
5765 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5766 SDValue RHS, SelectionDAG &DAG,
5768 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5769 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5770 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5773 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5782 OP_VUZPL, // VUZP, left result
5783 OP_VUZPR, // VUZP, right result
5784 OP_VZIPL, // VZIP, left result
5785 OP_VZIPR, // VZIP, right result
5786 OP_VTRNL, // VTRN, left result
5787 OP_VTRNR // VTRN, right result
5790 if (OpNum == OP_COPY) {
5791 if (LHSID == (1*9+2)*9+3) return LHS;
5792 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5796 SDValue OpLHS, OpRHS;
5797 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5798 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5799 EVT VT = OpLHS.getValueType();
5802 default: llvm_unreachable("Unknown shuffle opcode!");
5804 // VREV divides the vector in half and swaps within the half.
5805 if (VT.getVectorElementType() == MVT::i32 ||
5806 VT.getVectorElementType() == MVT::f32)
5807 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
5808 // vrev <4 x i16> -> VREV32
5809 if (VT.getVectorElementType() == MVT::i16)
5810 return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS);
5811 // vrev <4 x i8> -> VREV16
5812 assert(VT.getVectorElementType() == MVT::i8);
5813 return DAG.getNode(ARMISD::VREV16, dl, VT, OpLHS);
5818 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
5819 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, dl, MVT::i32));
5823 return DAG.getNode(ARMISD::VEXT, dl, VT,
5825 DAG.getConstant(OpNum - OP_VEXT1 + 1, dl, MVT::i32));
5828 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
5829 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
5832 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
5833 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
5836 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
5837 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
5841 static SDValue LowerVECTOR_SHUFFLEv8i8(SDValue Op,
5842 ArrayRef<int> ShuffleMask,
5843 SelectionDAG &DAG) {
5844 // Check to see if we can use the VTBL instruction.
5845 SDValue V1 = Op.getOperand(0);
5846 SDValue V2 = Op.getOperand(1);
5849 SmallVector<SDValue, 8> VTBLMask;
5850 for (ArrayRef<int>::iterator
5851 I = ShuffleMask.begin(), E = ShuffleMask.end(); I != E; ++I)
5852 VTBLMask.push_back(DAG.getConstant(*I, DL, MVT::i32));
5854 if (V2.getNode()->getOpcode() == ISD::UNDEF)
5855 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1,
5856 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, VTBLMask));
5858 return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2,
5859 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, VTBLMask));
5862 static SDValue LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(SDValue Op,
5863 SelectionDAG &DAG) {
5865 SDValue OpLHS = Op.getOperand(0);
5866 EVT VT = OpLHS.getValueType();
5868 assert((VT == MVT::v8i16 || VT == MVT::v16i8) &&
5869 "Expect an v8i16/v16i8 type");
5870 OpLHS = DAG.getNode(ARMISD::VREV64, DL, VT, OpLHS);
5871 // For a v16i8 type: After the VREV, we have got <8, ...15, 8, ..., 0>. Now,
5872 // extract the first 8 bytes into the top double word and the last 8 bytes
5873 // into the bottom double word. The v8i16 case is similar.
5874 unsigned ExtractNum = (VT == MVT::v16i8) ? 8 : 4;
5875 return DAG.getNode(ARMISD::VEXT, DL, VT, OpLHS, OpLHS,
5876 DAG.getConstant(ExtractNum, DL, MVT::i32));
5879 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
5880 SDValue V1 = Op.getOperand(0);
5881 SDValue V2 = Op.getOperand(1);
5883 EVT VT = Op.getValueType();
5884 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
5886 // Convert shuffles that are directly supported on NEON to target-specific
5887 // DAG nodes, instead of keeping them as shuffles and matching them again
5888 // during code selection. This is more efficient and avoids the possibility
5889 // of inconsistencies between legalization and selection.
5890 // FIXME: floating-point vectors should be canonicalized to integer vectors
5891 // of the same time so that they get CSEd properly.
5892 ArrayRef<int> ShuffleMask = SVN->getMask();
5894 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5895 if (EltSize <= 32) {
5896 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
5897 int Lane = SVN->getSplatIndex();
5898 // If this is undef splat, generate it via "just" vdup, if possible.
5899 if (Lane == -1) Lane = 0;
5901 // Test if V1 is a SCALAR_TO_VECTOR.
5902 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5903 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
5905 // Test if V1 is a BUILD_VECTOR which is equivalent to a SCALAR_TO_VECTOR
5906 // (and probably will turn into a SCALAR_TO_VECTOR once legalization
5908 if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
5909 !isa<ConstantSDNode>(V1.getOperand(0))) {
5910 bool IsScalarToVector = true;
5911 for (unsigned i = 1, e = V1.getNumOperands(); i != e; ++i)
5912 if (V1.getOperand(i).getOpcode() != ISD::UNDEF) {
5913 IsScalarToVector = false;
5916 if (IsScalarToVector)
5917 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
5919 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
5920 DAG.getConstant(Lane, dl, MVT::i32));
5925 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
5928 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
5929 DAG.getConstant(Imm, dl, MVT::i32));
5932 if (isVREVMask(ShuffleMask, VT, 64))
5933 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
5934 if (isVREVMask(ShuffleMask, VT, 32))
5935 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
5936 if (isVREVMask(ShuffleMask, VT, 16))
5937 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
5939 if (V2->getOpcode() == ISD::UNDEF &&
5940 isSingletonVEXTMask(ShuffleMask, VT, Imm)) {
5941 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V1,
5942 DAG.getConstant(Imm, dl, MVT::i32));
5945 // Check for Neon shuffles that modify both input vectors in place.
5946 // If both results are used, i.e., if there are two shuffles with the same
5947 // source operands and with masks corresponding to both results of one of
5948 // these operations, DAG memoization will ensure that a single node is
5949 // used for both shuffles.
5950 unsigned WhichResult;
5952 if (unsigned ShuffleOpc = isNEONTwoResultShuffleMask(
5953 ShuffleMask, VT, WhichResult, isV_UNDEF)) {
5956 return DAG.getNode(ShuffleOpc, dl, DAG.getVTList(VT, VT), V1, V2)
5957 .getValue(WhichResult);
5960 // Also check for these shuffles through CONCAT_VECTORS: we canonicalize
5961 // shuffles that produce a result larger than their operands with:
5962 // shuffle(concat(v1, undef), concat(v2, undef))
5964 // shuffle(concat(v1, v2), undef)
5965 // because we can access quad vectors (see PerformVECTOR_SHUFFLECombine).
5967 // This is useful in the general case, but there are special cases where
5968 // native shuffles produce larger results: the two-result ops.
5970 // Look through the concat when lowering them:
5971 // shuffle(concat(v1, v2), undef)
5973 // concat(VZIP(v1, v2):0, :1)
5975 if (V1->getOpcode() == ISD::CONCAT_VECTORS &&
5976 V2->getOpcode() == ISD::UNDEF) {
5977 SDValue SubV1 = V1->getOperand(0);
5978 SDValue SubV2 = V1->getOperand(1);
5979 EVT SubVT = SubV1.getValueType();
5981 // We expect these to have been canonicalized to -1.
5982 assert(std::all_of(ShuffleMask.begin(), ShuffleMask.end(), [&](int i) {
5983 return i < (int)VT.getVectorNumElements();
5984 }) && "Unexpected shuffle index into UNDEF operand!");
5986 if (unsigned ShuffleOpc = isNEONTwoResultShuffleMask(
5987 ShuffleMask, SubVT, WhichResult, isV_UNDEF)) {
5990 assert((WhichResult == 0) &&
5991 "In-place shuffle of concat can only have one result!");
5992 SDValue Res = DAG.getNode(ShuffleOpc, dl, DAG.getVTList(SubVT, SubVT),
5994 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Res.getValue(0),
6000 // If the shuffle is not directly supported and it has 4 elements, use
6001 // the PerfectShuffle-generated table to synthesize it from other shuffles.
6002 unsigned NumElts = VT.getVectorNumElements();
6004 unsigned PFIndexes[4];
6005 for (unsigned i = 0; i != 4; ++i) {
6006 if (ShuffleMask[i] < 0)
6009 PFIndexes[i] = ShuffleMask[i];
6012 // Compute the index in the perfect shuffle table.
6013 unsigned PFTableIndex =
6014 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
6015 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
6016 unsigned Cost = (PFEntry >> 30);
6019 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
6022 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
6023 if (EltSize >= 32) {
6024 // Do the expansion with floating-point types, since that is what the VFP
6025 // registers are defined to use, and since i64 is not legal.
6026 EVT EltVT = EVT::getFloatingPointVT(EltSize);
6027 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
6028 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1);
6029 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2);
6030 SmallVector<SDValue, 8> Ops;
6031 for (unsigned i = 0; i < NumElts; ++i) {
6032 if (ShuffleMask[i] < 0)
6033 Ops.push_back(DAG.getUNDEF(EltVT));
6035 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
6036 ShuffleMask[i] < (int)NumElts ? V1 : V2,
6037 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
6040 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops);
6041 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
6044 if ((VT == MVT::v8i16 || VT == MVT::v16i8) && isReverseMask(ShuffleMask, VT))
6045 return LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(Op, DAG);
6047 if (VT == MVT::v8i8) {
6048 SDValue NewOp = LowerVECTOR_SHUFFLEv8i8(Op, ShuffleMask, DAG);
6049 if (NewOp.getNode())
6056 static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
6057 // INSERT_VECTOR_ELT is legal only for immediate indexes.
6058 SDValue Lane = Op.getOperand(2);
6059 if (!isa<ConstantSDNode>(Lane))
6065 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
6066 // EXTRACT_VECTOR_ELT is legal only for immediate indexes.
6067 SDValue Lane = Op.getOperand(1);
6068 if (!isa<ConstantSDNode>(Lane))
6071 SDValue Vec = Op.getOperand(0);
6072 if (Op.getValueType() == MVT::i32 &&
6073 Vec.getValueType().getVectorElementType().getSizeInBits() < 32) {
6075 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
6081 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6082 // The only time a CONCAT_VECTORS operation can have legal types is when
6083 // two 64-bit vectors are concatenated to a 128-bit vector.
6084 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
6085 "unexpected CONCAT_VECTORS");
6087 SDValue Val = DAG.getUNDEF(MVT::v2f64);
6088 SDValue Op0 = Op.getOperand(0);
6089 SDValue Op1 = Op.getOperand(1);
6090 if (Op0.getOpcode() != ISD::UNDEF)
6091 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
6092 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0),
6093 DAG.getIntPtrConstant(0, dl));
6094 if (Op1.getOpcode() != ISD::UNDEF)
6095 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
6096 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1),
6097 DAG.getIntPtrConstant(1, dl));
6098 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val);
6101 /// isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each
6102 /// element has been zero/sign-extended, depending on the isSigned parameter,
6103 /// from an integer type half its size.
6104 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
6106 // A v2i64 BUILD_VECTOR will have been legalized to a BITCAST from v4i32.
6107 EVT VT = N->getValueType(0);
6108 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) {
6109 SDNode *BVN = N->getOperand(0).getNode();
6110 if (BVN->getValueType(0) != MVT::v4i32 ||
6111 BVN->getOpcode() != ISD::BUILD_VECTOR)
6113 unsigned LoElt = DAG.getDataLayout().isBigEndian() ? 1 : 0;
6114 unsigned HiElt = 1 - LoElt;
6115 ConstantSDNode *Lo0 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt));
6116 ConstantSDNode *Hi0 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt));
6117 ConstantSDNode *Lo1 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt+2));
6118 ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2));
6119 if (!Lo0 || !Hi0 || !Lo1 || !Hi1)
6122 if (Hi0->getSExtValue() == Lo0->getSExtValue() >> 32 &&
6123 Hi1->getSExtValue() == Lo1->getSExtValue() >> 32)
6126 if (Hi0->isNullValue() && Hi1->isNullValue())
6132 if (N->getOpcode() != ISD::BUILD_VECTOR)
6135 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
6136 SDNode *Elt = N->getOperand(i).getNode();
6137 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
6138 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
6139 unsigned HalfSize = EltSize / 2;
6141 if (!isIntN(HalfSize, C->getSExtValue()))
6144 if (!isUIntN(HalfSize, C->getZExtValue()))
6155 /// isSignExtended - Check if a node is a vector value that is sign-extended
6156 /// or a constant BUILD_VECTOR with sign-extended elements.
6157 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
6158 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N))
6160 if (isExtendedBUILD_VECTOR(N, DAG, true))
6165 /// isZeroExtended - Check if a node is a vector value that is zero-extended
6166 /// or a constant BUILD_VECTOR with zero-extended elements.
6167 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
6168 if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N))
6170 if (isExtendedBUILD_VECTOR(N, DAG, false))
6175 static EVT getExtensionTo64Bits(const EVT &OrigVT) {
6176 if (OrigVT.getSizeInBits() >= 64)
6179 assert(OrigVT.isSimple() && "Expecting a simple value type");
6181 MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy;
6182 switch (OrigSimpleTy) {
6183 default: llvm_unreachable("Unexpected Vector Type");
6192 /// AddRequiredExtensionForVMULL - Add a sign/zero extension to extend the total
6193 /// value size to 64 bits. We need a 64-bit D register as an operand to VMULL.
6194 /// We insert the required extension here to get the vector to fill a D register.
6195 static SDValue AddRequiredExtensionForVMULL(SDValue N, SelectionDAG &DAG,
6198 unsigned ExtOpcode) {
6199 // The vector originally had a size of OrigTy. It was then extended to ExtTy.
6200 // We expect the ExtTy to be 128-bits total. If the OrigTy is less than
6201 // 64-bits we need to insert a new extension so that it will be 64-bits.
6202 assert(ExtTy.is128BitVector() && "Unexpected extension size");
6203 if (OrigTy.getSizeInBits() >= 64)
6206 // Must extend size to at least 64 bits to be used as an operand for VMULL.
6207 EVT NewVT = getExtensionTo64Bits(OrigTy);
6209 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N);
6212 /// SkipLoadExtensionForVMULL - return a load of the original vector size that
6213 /// does not do any sign/zero extension. If the original vector is less
6214 /// than 64 bits, an appropriate extension will be added after the load to
6215 /// reach a total size of 64 bits. We have to add the extension separately
6216 /// because ARM does not have a sign/zero extending load for vectors.
6217 static SDValue SkipLoadExtensionForVMULL(LoadSDNode *LD, SelectionDAG& DAG) {
6218 EVT ExtendedTy = getExtensionTo64Bits(LD->getMemoryVT());
6220 // The load already has the right type.
6221 if (ExtendedTy == LD->getMemoryVT())
6222 return DAG.getLoad(LD->getMemoryVT(), SDLoc(LD), LD->getChain(),
6223 LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(),
6224 LD->isNonTemporal(), LD->isInvariant(),
6225 LD->getAlignment());
6227 // We need to create a zextload/sextload. We cannot just create a load
6228 // followed by a zext/zext node because LowerMUL is also run during normal
6229 // operation legalization where we can't create illegal types.
6230 return DAG.getExtLoad(LD->getExtensionType(), SDLoc(LD), ExtendedTy,
6231 LD->getChain(), LD->getBasePtr(), LD->getPointerInfo(),
6232 LD->getMemoryVT(), LD->isVolatile(), LD->isInvariant(),
6233 LD->isNonTemporal(), LD->getAlignment());
6236 /// SkipExtensionForVMULL - For a node that is a SIGN_EXTEND, ZERO_EXTEND,
6237 /// extending load, or BUILD_VECTOR with extended elements, return the
6238 /// unextended value. The unextended vector should be 64 bits so that it can
6239 /// be used as an operand to a VMULL instruction. If the original vector size
6240 /// before extension is less than 64 bits we add a an extension to resize
6241 /// the vector to 64 bits.
6242 static SDValue SkipExtensionForVMULL(SDNode *N, SelectionDAG &DAG) {
6243 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
6244 return AddRequiredExtensionForVMULL(N->getOperand(0), DAG,
6245 N->getOperand(0)->getValueType(0),
6249 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
6250 return SkipLoadExtensionForVMULL(LD, DAG);
6252 // Otherwise, the value must be a BUILD_VECTOR. For v2i64, it will
6253 // have been legalized as a BITCAST from v4i32.
6254 if (N->getOpcode() == ISD::BITCAST) {
6255 SDNode *BVN = N->getOperand(0).getNode();
6256 assert(BVN->getOpcode() == ISD::BUILD_VECTOR &&
6257 BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR");
6258 unsigned LowElt = DAG.getDataLayout().isBigEndian() ? 1 : 0;
6259 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), MVT::v2i32,
6260 BVN->getOperand(LowElt), BVN->getOperand(LowElt+2));
6262 // Construct a new BUILD_VECTOR with elements truncated to half the size.
6263 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
6264 EVT VT = N->getValueType(0);
6265 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
6266 unsigned NumElts = VT.getVectorNumElements();
6267 MVT TruncVT = MVT::getIntegerVT(EltSize);
6268 SmallVector<SDValue, 8> Ops;
6270 for (unsigned i = 0; i != NumElts; ++i) {
6271 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
6272 const APInt &CInt = C->getAPIntValue();
6273 // Element types smaller than 32 bits are not legal, so use i32 elements.
6274 // The values are implicitly truncated so sext vs. zext doesn't matter.
6275 Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), dl, MVT::i32));
6277 return DAG.getNode(ISD::BUILD_VECTOR, dl,
6278 MVT::getVectorVT(TruncVT, NumElts), Ops);
6281 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
6282 unsigned Opcode = N->getOpcode();
6283 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
6284 SDNode *N0 = N->getOperand(0).getNode();
6285 SDNode *N1 = N->getOperand(1).getNode();
6286 return N0->hasOneUse() && N1->hasOneUse() &&
6287 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
6292 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
6293 unsigned Opcode = N->getOpcode();
6294 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
6295 SDNode *N0 = N->getOperand(0).getNode();
6296 SDNode *N1 = N->getOperand(1).getNode();
6297 return N0->hasOneUse() && N1->hasOneUse() &&
6298 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
6303 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
6304 // Multiplications are only custom-lowered for 128-bit vectors so that
6305 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
6306 EVT VT = Op.getValueType();
6307 assert(VT.is128BitVector() && VT.isInteger() &&
6308 "unexpected type for custom-lowering ISD::MUL");
6309 SDNode *N0 = Op.getOperand(0).getNode();
6310 SDNode *N1 = Op.getOperand(1).getNode();
6311 unsigned NewOpc = 0;
6313 bool isN0SExt = isSignExtended(N0, DAG);
6314 bool isN1SExt = isSignExtended(N1, DAG);
6315 if (isN0SExt && isN1SExt)
6316 NewOpc = ARMISD::VMULLs;
6318 bool isN0ZExt = isZeroExtended(N0, DAG);
6319 bool isN1ZExt = isZeroExtended(N1, DAG);
6320 if (isN0ZExt && isN1ZExt)
6321 NewOpc = ARMISD::VMULLu;
6322 else if (isN1SExt || isN1ZExt) {
6323 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
6324 // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
6325 if (isN1SExt && isAddSubSExt(N0, DAG)) {
6326 NewOpc = ARMISD::VMULLs;
6328 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
6329 NewOpc = ARMISD::VMULLu;
6331 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
6333 NewOpc = ARMISD::VMULLu;
6339 if (VT == MVT::v2i64)
6340 // Fall through to expand this. It is not legal.
6343 // Other vector multiplications are legal.
6348 // Legalize to a VMULL instruction.
6351 SDValue Op1 = SkipExtensionForVMULL(N1, DAG);
6353 Op0 = SkipExtensionForVMULL(N0, DAG);
6354 assert(Op0.getValueType().is64BitVector() &&
6355 Op1.getValueType().is64BitVector() &&
6356 "unexpected types for extended operands to VMULL");
6357 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
6360 // Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during
6361 // isel lowering to take advantage of no-stall back to back vmul + vmla.
6368 SDValue N00 = SkipExtensionForVMULL(N0->getOperand(0).getNode(), DAG);
6369 SDValue N01 = SkipExtensionForVMULL(N0->getOperand(1).getNode(), DAG);
6370 EVT Op1VT = Op1.getValueType();
6371 return DAG.getNode(N0->getOpcode(), DL, VT,
6372 DAG.getNode(NewOpc, DL, VT,
6373 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
6374 DAG.getNode(NewOpc, DL, VT,
6375 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
6379 LowerSDIV_v4i8(SDValue X, SDValue Y, SDLoc dl, SelectionDAG &DAG) {
6380 // TODO: Should this propagate fast-math-flags?
6383 // float4 xf = vcvt_f32_s32(vmovl_s16(a.lo));
6384 // float4 yf = vcvt_f32_s32(vmovl_s16(b.lo));
6385 X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X);
6386 Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y);
6387 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X);
6388 Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y);
6389 // Get reciprocal estimate.
6390 // float4 recip = vrecpeq_f32(yf);
6391 Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6392 DAG.getConstant(Intrinsic::arm_neon_vrecpe, dl, MVT::i32),
6394 // Because char has a smaller range than uchar, we can actually get away
6395 // without any newton steps. This requires that we use a weird bias
6396 // of 0xb000, however (again, this has been exhaustively tested).
6397 // float4 result = as_float4(as_int4(xf*recip) + 0xb000);
6398 X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y);
6399 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X);
6400 Y = DAG.getConstant(0xb000, dl, MVT::i32);
6401 Y = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Y, Y, Y, Y);
6402 X = DAG.getNode(ISD::ADD, dl, MVT::v4i32, X, Y);
6403 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X);
6404 // Convert back to short.
6405 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X);
6406 X = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, X);
6411 LowerSDIV_v4i16(SDValue N0, SDValue N1, SDLoc dl, SelectionDAG &DAG) {
6412 // TODO: Should this propagate fast-math-flags?
6415 // Convert to float.
6416 // float4 yf = vcvt_f32_s32(vmovl_s16(y));
6417 // float4 xf = vcvt_f32_s32(vmovl_s16(x));
6418 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0);
6419 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1);
6420 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
6421 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
6423 // Use reciprocal estimate and one refinement step.
6424 // float4 recip = vrecpeq_f32(yf);
6425 // recip *= vrecpsq_f32(yf, recip);
6426 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6427 DAG.getConstant(Intrinsic::arm_neon_vrecpe, dl, MVT::i32),
6429 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6430 DAG.getConstant(Intrinsic::arm_neon_vrecps, dl, MVT::i32),
6432 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
6433 // Because short has a smaller range than ushort, we can actually get away
6434 // with only a single newton step. This requires that we use a weird bias
6435 // of 89, however (again, this has been exhaustively tested).
6436 // float4 result = as_float4(as_int4(xf*recip) + 0x89);
6437 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
6438 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
6439 N1 = DAG.getConstant(0x89, dl, MVT::i32);
6440 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
6441 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
6442 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
6443 // Convert back to integer and return.
6444 // return vmovn_s32(vcvt_s32_f32(result));
6445 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
6446 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
6450 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
6451 EVT VT = Op.getValueType();
6452 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
6453 "unexpected type for custom-lowering ISD::SDIV");
6456 SDValue N0 = Op.getOperand(0);
6457 SDValue N1 = Op.getOperand(1);
6460 if (VT == MVT::v8i8) {
6461 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0);
6462 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1);
6464 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
6465 DAG.getIntPtrConstant(4, dl));
6466 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
6467 DAG.getIntPtrConstant(4, dl));
6468 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
6469 DAG.getIntPtrConstant(0, dl));
6470 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
6471 DAG.getIntPtrConstant(0, dl));
6473 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16
6474 N2 = LowerSDIV_v4i8(N2, N3, dl, DAG); // v4i16
6476 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
6477 N0 = LowerCONCAT_VECTORS(N0, DAG);
6479 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0);
6482 return LowerSDIV_v4i16(N0, N1, dl, DAG);
6485 static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG) {
6486 // TODO: Should this propagate fast-math-flags?
6487 EVT VT = Op.getValueType();
6488 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
6489 "unexpected type for custom-lowering ISD::UDIV");
6492 SDValue N0 = Op.getOperand(0);
6493 SDValue N1 = Op.getOperand(1);
6496 if (VT == MVT::v8i8) {
6497 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0);
6498 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1);
6500 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
6501 DAG.getIntPtrConstant(4, dl));
6502 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
6503 DAG.getIntPtrConstant(4, dl));
6504 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
6505 DAG.getIntPtrConstant(0, dl));
6506 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
6507 DAG.getIntPtrConstant(0, dl));
6509 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16
6510 N2 = LowerSDIV_v4i16(N2, N3, dl, DAG); // v4i16
6512 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
6513 N0 = LowerCONCAT_VECTORS(N0, DAG);
6515 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8,
6516 DAG.getConstant(Intrinsic::arm_neon_vqmovnsu, dl,
6522 // v4i16 sdiv ... Convert to float.
6523 // float4 yf = vcvt_f32_s32(vmovl_u16(y));
6524 // float4 xf = vcvt_f32_s32(vmovl_u16(x));
6525 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0);
6526 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1);
6527 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
6528 SDValue BN1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
6530 // Use reciprocal estimate and two refinement steps.
6531 // float4 recip = vrecpeq_f32(yf);
6532 // recip *= vrecpsq_f32(yf, recip);
6533 // recip *= vrecpsq_f32(yf, recip);
6534 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6535 DAG.getConstant(Intrinsic::arm_neon_vrecpe, dl, MVT::i32),
6537 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6538 DAG.getConstant(Intrinsic::arm_neon_vrecps, dl, MVT::i32),
6540 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
6541 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6542 DAG.getConstant(Intrinsic::arm_neon_vrecps, dl, MVT::i32),
6544 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
6545 // Simply multiplying by the reciprocal estimate can leave us a few ulps
6546 // too low, so we add 2 ulps (exhaustive testing shows that this is enough,
6547 // and that it will never cause us to return an answer too large).
6548 // float4 result = as_float4(as_int4(xf*recip) + 2);
6549 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
6550 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
6551 N1 = DAG.getConstant(2, dl, MVT::i32);
6552 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
6553 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
6554 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
6555 // Convert back to integer and return.
6556 // return vmovn_u32(vcvt_s32_f32(result));
6557 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
6558 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
6562 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
6563 EVT VT = Op.getNode()->getValueType(0);
6564 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
6567 bool ExtraOp = false;
6568 switch (Op.getOpcode()) {
6569 default: llvm_unreachable("Invalid code");
6570 case ISD::ADDC: Opc = ARMISD::ADDC; break;
6571 case ISD::ADDE: Opc = ARMISD::ADDE; ExtraOp = true; break;
6572 case ISD::SUBC: Opc = ARMISD::SUBC; break;
6573 case ISD::SUBE: Opc = ARMISD::SUBE; ExtraOp = true; break;
6577 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
6579 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
6580 Op.getOperand(1), Op.getOperand(2));
6583 SDValue ARMTargetLowering::LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const {
6584 assert(Subtarget->isTargetDarwin());
6586 // For iOS, we want to call an alternative entry point: __sincos_stret,
6587 // return values are passed via sret.
6589 SDValue Arg = Op.getOperand(0);
6590 EVT ArgVT = Arg.getValueType();
6591 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
6592 auto PtrVT = getPointerTy(DAG.getDataLayout());
6594 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6596 // Pair of floats / doubles used to pass the result.
6597 StructType *RetTy = StructType::get(ArgTy, ArgTy, nullptr);
6599 // Create stack object for sret.
6600 auto &DL = DAG.getDataLayout();
6601 const uint64_t ByteSize = DL.getTypeAllocSize(RetTy);
6602 const unsigned StackAlign = DL.getPrefTypeAlignment(RetTy);
6603 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign, false);
6604 SDValue SRet = DAG.getFrameIndex(FrameIdx, getPointerTy(DL));
6610 Entry.Ty = RetTy->getPointerTo();
6611 Entry.isSExt = false;
6612 Entry.isZExt = false;
6613 Entry.isSRet = true;
6614 Args.push_back(Entry);
6618 Entry.isSExt = false;
6619 Entry.isZExt = false;
6620 Args.push_back(Entry);
6622 const char *LibcallName =
6623 (ArgVT == MVT::f64) ? "__sincos_stret" : "__sincosf_stret";
6624 SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy(DL));
6626 TargetLowering::CallLoweringInfo CLI(DAG);
6627 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
6628 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()), Callee,
6630 .setDiscardResult();
6632 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
6634 SDValue LoadSin = DAG.getLoad(ArgVT, dl, CallResult.second, SRet,
6635 MachinePointerInfo(), false, false, false, 0);
6637 // Address of cos field.
6638 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, SRet,
6639 DAG.getIntPtrConstant(ArgVT.getStoreSize(), dl));
6640 SDValue LoadCos = DAG.getLoad(ArgVT, dl, LoadSin.getValue(1), Add,
6641 MachinePointerInfo(), false, false, false, 0);
6643 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
6644 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys,
6645 LoadSin.getValue(0), LoadCos.getValue(0));
6648 static SDValue LowerAtomicLoadStore(SDValue Op, SelectionDAG &DAG) {
6649 // Monotonic load/store is legal for all targets
6650 if (cast<AtomicSDNode>(Op)->getOrdering() <= Monotonic)
6653 // Acquire/Release load/store is not legal for targets without a
6654 // dmb or equivalent available.
6658 static void ReplaceREADCYCLECOUNTER(SDNode *N,
6659 SmallVectorImpl<SDValue> &Results,
6661 const ARMSubtarget *Subtarget) {
6663 // Under Power Management extensions, the cycle-count is:
6664 // mrc p15, #0, <Rt>, c9, c13, #0
6665 SDValue Ops[] = { N->getOperand(0), // Chain
6666 DAG.getConstant(Intrinsic::arm_mrc, DL, MVT::i32),
6667 DAG.getConstant(15, DL, MVT::i32),
6668 DAG.getConstant(0, DL, MVT::i32),
6669 DAG.getConstant(9, DL, MVT::i32),
6670 DAG.getConstant(13, DL, MVT::i32),
6671 DAG.getConstant(0, DL, MVT::i32)
6674 SDValue Cycles32 = DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL,
6675 DAG.getVTList(MVT::i32, MVT::Other), Ops);
6676 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Cycles32,
6677 DAG.getConstant(0, DL, MVT::i32)));
6678 Results.push_back(Cycles32.getValue(1));
6681 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6682 switch (Op.getOpcode()) {
6683 default: llvm_unreachable("Don't know how to custom lower this!");
6684 case ISD::WRITE_REGISTER: return LowerWRITE_REGISTER(Op, DAG);
6685 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6686 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
6687 case ISD::GlobalAddress:
6688 switch (Subtarget->getTargetTriple().getObjectFormat()) {
6689 default: llvm_unreachable("unknown object format");
6691 return LowerGlobalAddressWindows(Op, DAG);
6693 return LowerGlobalAddressELF(Op, DAG);
6695 return LowerGlobalAddressDarwin(Op, DAG);
6697 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6698 case ISD::SELECT: return LowerSELECT(Op, DAG);
6699 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
6700 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
6701 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
6702 case ISD::VASTART: return LowerVASTART(Op, DAG);
6703 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG, Subtarget);
6704 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget);
6705 case ISD::SINT_TO_FP:
6706 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
6707 case ISD::FP_TO_SINT:
6708 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
6709 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
6710 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6711 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6712 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
6713 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
6714 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
6715 case ISD::EH_SJLJ_SETUP_DISPATCH: return LowerEH_SJLJ_SETUP_DISPATCH(Op, DAG);
6716 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
6718 case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG);
6721 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
6722 case ISD::SREM: return LowerREM(Op.getNode(), DAG);
6723 case ISD::UREM: return LowerREM(Op.getNode(), DAG);
6724 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
6725 case ISD::SRL_PARTS:
6726 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
6728 case ISD::CTTZ_ZERO_UNDEF: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
6729 case ISD::CTPOP: return LowerCTPOP(Op.getNode(), DAG, Subtarget);
6730 case ISD::SETCC: return LowerVSETCC(Op, DAG);
6731 case ISD::ConstantFP: return LowerConstantFP(Op, DAG, Subtarget);
6732 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
6733 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6734 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
6735 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
6736 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
6737 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6738 case ISD::MUL: return LowerMUL(Op, DAG);
6739 case ISD::SDIV: return LowerSDIV(Op, DAG);
6740 case ISD::UDIV: return LowerUDIV(Op, DAG);
6744 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
6749 return LowerXALUO(Op, DAG);
6750 case ISD::ATOMIC_LOAD:
6751 case ISD::ATOMIC_STORE: return LowerAtomicLoadStore(Op, DAG);
6752 case ISD::FSINCOS: return LowerFSINCOS(Op, DAG);
6754 case ISD::UDIVREM: return LowerDivRem(Op, DAG);
6755 case ISD::DYNAMIC_STACKALLOC:
6756 if (Subtarget->getTargetTriple().isWindowsItaniumEnvironment())
6757 return LowerDYNAMIC_STACKALLOC(Op, DAG);
6758 llvm_unreachable("Don't know how to custom lower this!");
6759 case ISD::FP_ROUND: return LowerFP_ROUND(Op, DAG);
6760 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
6764 /// ReplaceNodeResults - Replace the results of node with an illegal result
6765 /// type with new values built out of custom code.
6766 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
6767 SmallVectorImpl<SDValue>&Results,
6768 SelectionDAG &DAG) const {
6770 switch (N->getOpcode()) {
6772 llvm_unreachable("Don't know how to custom expand this!");
6773 case ISD::READ_REGISTER:
6774 ExpandREAD_REGISTER(N, Results, DAG);
6777 Res = ExpandBITCAST(N, DAG);
6781 Res = Expand64BitShift(N, DAG, Subtarget);
6785 Res = LowerREM(N, DAG);
6787 case ISD::READCYCLECOUNTER:
6788 ReplaceREADCYCLECOUNTER(N, Results, DAG, Subtarget);
6792 Results.push_back(Res);
6795 //===----------------------------------------------------------------------===//
6796 // ARM Scheduler Hooks
6797 //===----------------------------------------------------------------------===//
6799 /// SetupEntryBlockForSjLj - Insert code into the entry block that creates and
6800 /// registers the function context.
6801 void ARMTargetLowering::
6802 SetupEntryBlockForSjLj(MachineInstr *MI, MachineBasicBlock *MBB,
6803 MachineBasicBlock *DispatchBB, int FI) const {
6804 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
6805 DebugLoc dl = MI->getDebugLoc();
6806 MachineFunction *MF = MBB->getParent();
6807 MachineRegisterInfo *MRI = &MF->getRegInfo();
6808 MachineConstantPool *MCP = MF->getConstantPool();
6809 ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>();
6810 const Function *F = MF->getFunction();
6812 bool isThumb = Subtarget->isThumb();
6813 bool isThumb2 = Subtarget->isThumb2();
6815 unsigned PCLabelId = AFI->createPICLabelUId();
6816 unsigned PCAdj = (isThumb || isThumb2) ? 4 : 8;
6817 ARMConstantPoolValue *CPV =
6818 ARMConstantPoolMBB::Create(F->getContext(), DispatchBB, PCLabelId, PCAdj);
6819 unsigned CPI = MCP->getConstantPoolIndex(CPV, 4);
6821 const TargetRegisterClass *TRC = isThumb ? &ARM::tGPRRegClass
6822 : &ARM::GPRRegClass;
6824 // Grab constant pool and fixed stack memory operands.
6825 MachineMemOperand *CPMMO =
6826 MF->getMachineMemOperand(MachinePointerInfo::getConstantPool(*MF),
6827 MachineMemOperand::MOLoad, 4, 4);
6829 MachineMemOperand *FIMMOSt =
6830 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(*MF, FI),
6831 MachineMemOperand::MOStore, 4, 4);
6833 // Load the address of the dispatch MBB into the jump buffer.
6835 // Incoming value: jbuf
6836 // ldr.n r5, LCPI1_1
6839 // str r5, [$jbuf, #+4] ; &jbuf[1]
6840 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6841 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2LDRpci), NewVReg1)
6842 .addConstantPoolIndex(CPI)
6843 .addMemOperand(CPMMO));
6844 // Set the low bit because of thumb mode.
6845 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6847 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2ORRri), NewVReg2)
6848 .addReg(NewVReg1, RegState::Kill)
6850 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6851 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg3)
6852 .addReg(NewVReg2, RegState::Kill)
6854 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2STRi12))
6855 .addReg(NewVReg3, RegState::Kill)
6857 .addImm(36) // &jbuf[1] :: pc
6858 .addMemOperand(FIMMOSt));
6859 } else if (isThumb) {
6860 // Incoming value: jbuf
6861 // ldr.n r1, LCPI1_4
6865 // add r2, $jbuf, #+4 ; &jbuf[1]
6867 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6868 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tLDRpci), NewVReg1)
6869 .addConstantPoolIndex(CPI)
6870 .addMemOperand(CPMMO));
6871 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6872 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg2)
6873 .addReg(NewVReg1, RegState::Kill)
6875 // Set the low bit because of thumb mode.
6876 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6877 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tMOVi8), NewVReg3)
6878 .addReg(ARM::CPSR, RegState::Define)
6880 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
6881 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tORR), NewVReg4)
6882 .addReg(ARM::CPSR, RegState::Define)
6883 .addReg(NewVReg2, RegState::Kill)
6884 .addReg(NewVReg3, RegState::Kill));
6885 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
6886 BuildMI(*MBB, MI, dl, TII->get(ARM::tADDframe), NewVReg5)
6888 .addImm(36); // &jbuf[1] :: pc
6889 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tSTRi))
6890 .addReg(NewVReg4, RegState::Kill)
6891 .addReg(NewVReg5, RegState::Kill)
6893 .addMemOperand(FIMMOSt));
6895 // Incoming value: jbuf
6898 // str r1, [$jbuf, #+4] ; &jbuf[1]
6899 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6900 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::LDRi12), NewVReg1)
6901 .addConstantPoolIndex(CPI)
6903 .addMemOperand(CPMMO));
6904 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6905 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::PICADD), NewVReg2)
6906 .addReg(NewVReg1, RegState::Kill)
6907 .addImm(PCLabelId));
6908 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::STRi12))
6909 .addReg(NewVReg2, RegState::Kill)
6911 .addImm(36) // &jbuf[1] :: pc
6912 .addMemOperand(FIMMOSt));
6916 void ARMTargetLowering::EmitSjLjDispatchBlock(MachineInstr *MI,
6917 MachineBasicBlock *MBB) const {
6918 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
6919 DebugLoc dl = MI->getDebugLoc();
6920 MachineFunction *MF = MBB->getParent();
6921 MachineRegisterInfo *MRI = &MF->getRegInfo();
6922 MachineFrameInfo *MFI = MF->getFrameInfo();
6923 int FI = MFI->getFunctionContextIndex();
6925 const TargetRegisterClass *TRC = Subtarget->isThumb() ? &ARM::tGPRRegClass
6926 : &ARM::GPRnopcRegClass;
6928 // Get a mapping of the call site numbers to all of the landing pads they're
6930 DenseMap<unsigned, SmallVector<MachineBasicBlock*, 2> > CallSiteNumToLPad;
6931 unsigned MaxCSNum = 0;
6932 MachineModuleInfo &MMI = MF->getMMI();
6933 for (MachineFunction::iterator BB = MF->begin(), E = MF->end(); BB != E;
6935 if (!BB->isEHPad()) continue;
6937 // FIXME: We should assert that the EH_LABEL is the first MI in the landing
6939 for (MachineBasicBlock::iterator
6940 II = BB->begin(), IE = BB->end(); II != IE; ++II) {
6941 if (!II->isEHLabel()) continue;
6943 MCSymbol *Sym = II->getOperand(0).getMCSymbol();
6944 if (!MMI.hasCallSiteLandingPad(Sym)) continue;
6946 SmallVectorImpl<unsigned> &CallSiteIdxs = MMI.getCallSiteLandingPad(Sym);
6947 for (SmallVectorImpl<unsigned>::iterator
6948 CSI = CallSiteIdxs.begin(), CSE = CallSiteIdxs.end();
6949 CSI != CSE; ++CSI) {
6950 CallSiteNumToLPad[*CSI].push_back(BB);
6951 MaxCSNum = std::max(MaxCSNum, *CSI);
6957 // Get an ordered list of the machine basic blocks for the jump table.
6958 std::vector<MachineBasicBlock*> LPadList;
6959 SmallPtrSet<MachineBasicBlock*, 64> InvokeBBs;
6960 LPadList.reserve(CallSiteNumToLPad.size());
6961 for (unsigned I = 1; I <= MaxCSNum; ++I) {
6962 SmallVectorImpl<MachineBasicBlock*> &MBBList = CallSiteNumToLPad[I];
6963 for (SmallVectorImpl<MachineBasicBlock*>::iterator
6964 II = MBBList.begin(), IE = MBBList.end(); II != IE; ++II) {
6965 LPadList.push_back(*II);
6966 InvokeBBs.insert((*II)->pred_begin(), (*II)->pred_end());
6970 assert(!LPadList.empty() &&
6971 "No landing pad destinations for the dispatch jump table!");
6973 // Create the jump table and associated information.
6974 MachineJumpTableInfo *JTI =
6975 MF->getOrCreateJumpTableInfo(MachineJumpTableInfo::EK_Inline);
6976 unsigned MJTI = JTI->createJumpTableIndex(LPadList);
6977 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
6979 // Create the MBBs for the dispatch code.
6981 // Shove the dispatch's address into the return slot in the function context.
6982 MachineBasicBlock *DispatchBB = MF->CreateMachineBasicBlock();
6983 DispatchBB->setIsEHPad();
6985 MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock();
6986 unsigned trap_opcode;
6987 if (Subtarget->isThumb())
6988 trap_opcode = ARM::tTRAP;
6990 trap_opcode = Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP;
6992 BuildMI(TrapBB, dl, TII->get(trap_opcode));
6993 DispatchBB->addSuccessor(TrapBB);
6995 MachineBasicBlock *DispContBB = MF->CreateMachineBasicBlock();
6996 DispatchBB->addSuccessor(DispContBB);
6999 MF->insert(MF->end(), DispatchBB);
7000 MF->insert(MF->end(), DispContBB);
7001 MF->insert(MF->end(), TrapBB);
7003 // Insert code into the entry block that creates and registers the function
7005 SetupEntryBlockForSjLj(MI, MBB, DispatchBB, FI);
7007 MachineMemOperand *FIMMOLd = MF->getMachineMemOperand(
7008 MachinePointerInfo::getFixedStack(*MF, FI),
7009 MachineMemOperand::MOLoad | MachineMemOperand::MOVolatile, 4, 4);
7011 MachineInstrBuilder MIB;
7012 MIB = BuildMI(DispatchBB, dl, TII->get(ARM::Int_eh_sjlj_dispatchsetup));
7014 const ARMBaseInstrInfo *AII = static_cast<const ARMBaseInstrInfo*>(TII);
7015 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
7017 // Add a register mask with no preserved registers. This results in all
7018 // registers being marked as clobbered.
7019 MIB.addRegMask(RI.getNoPreservedMask());
7021 unsigned NumLPads = LPadList.size();
7022 if (Subtarget->isThumb2()) {
7023 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
7024 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2LDRi12), NewVReg1)
7027 .addMemOperand(FIMMOLd));
7029 if (NumLPads < 256) {
7030 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPri))
7032 .addImm(LPadList.size()));
7034 unsigned VReg1 = MRI->createVirtualRegister(TRC);
7035 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVi16), VReg1)
7036 .addImm(NumLPads & 0xFFFF));
7038 unsigned VReg2 = VReg1;
7039 if ((NumLPads & 0xFFFF0000) != 0) {
7040 VReg2 = MRI->createVirtualRegister(TRC);
7041 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVTi16), VReg2)
7043 .addImm(NumLPads >> 16));
7046 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPrr))
7051 BuildMI(DispatchBB, dl, TII->get(ARM::t2Bcc))
7056 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
7057 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::t2LEApcrelJT),NewVReg3)
7058 .addJumpTableIndex(MJTI));
7060 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
7063 BuildMI(DispContBB, dl, TII->get(ARM::t2ADDrs), NewVReg4)
7064 .addReg(NewVReg3, RegState::Kill)
7066 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))));
7068 BuildMI(DispContBB, dl, TII->get(ARM::t2BR_JT))
7069 .addReg(NewVReg4, RegState::Kill)
7071 .addJumpTableIndex(MJTI);
7072 } else if (Subtarget->isThumb()) {
7073 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
7074 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRspi), NewVReg1)
7077 .addMemOperand(FIMMOLd));
7079 if (NumLPads < 256) {
7080 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPi8))
7084 MachineConstantPool *ConstantPool = MF->getConstantPool();
7085 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
7086 const Constant *C = ConstantInt::get(Int32Ty, NumLPads);
7088 // MachineConstantPool wants an explicit alignment.
7089 unsigned Align = MF->getDataLayout().getPrefTypeAlignment(Int32Ty);
7091 Align = MF->getDataLayout().getTypeAllocSize(C->getType());
7092 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
7094 unsigned VReg1 = MRI->createVirtualRegister(TRC);
7095 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRpci))
7096 .addReg(VReg1, RegState::Define)
7097 .addConstantPoolIndex(Idx));
7098 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPr))
7103 BuildMI(DispatchBB, dl, TII->get(ARM::tBcc))
7108 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
7109 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLSLri), NewVReg2)
7110 .addReg(ARM::CPSR, RegState::Define)
7114 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
7115 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLEApcrelJT), NewVReg3)
7116 .addJumpTableIndex(MJTI));
7118 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
7119 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg4)
7120 .addReg(ARM::CPSR, RegState::Define)
7121 .addReg(NewVReg2, RegState::Kill)
7124 MachineMemOperand *JTMMOLd = MF->getMachineMemOperand(
7125 MachinePointerInfo::getJumpTable(*MF), MachineMemOperand::MOLoad, 4, 4);
7127 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
7128 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLDRi), NewVReg5)
7129 .addReg(NewVReg4, RegState::Kill)
7131 .addMemOperand(JTMMOLd));
7133 unsigned NewVReg6 = NewVReg5;
7134 if (RelocM == Reloc::PIC_) {
7135 NewVReg6 = MRI->createVirtualRegister(TRC);
7136 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg6)
7137 .addReg(ARM::CPSR, RegState::Define)
7138 .addReg(NewVReg5, RegState::Kill)
7142 BuildMI(DispContBB, dl, TII->get(ARM::tBR_JTr))
7143 .addReg(NewVReg6, RegState::Kill)
7144 .addJumpTableIndex(MJTI);
7146 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
7147 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRi12), NewVReg1)
7150 .addMemOperand(FIMMOLd));
7152 if (NumLPads < 256) {
7153 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPri))
7156 } else if (Subtarget->hasV6T2Ops() && isUInt<16>(NumLPads)) {
7157 unsigned VReg1 = MRI->createVirtualRegister(TRC);
7158 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVi16), VReg1)
7159 .addImm(NumLPads & 0xFFFF));
7161 unsigned VReg2 = VReg1;
7162 if ((NumLPads & 0xFFFF0000) != 0) {
7163 VReg2 = MRI->createVirtualRegister(TRC);
7164 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVTi16), VReg2)
7166 .addImm(NumLPads >> 16));
7169 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
7173 MachineConstantPool *ConstantPool = MF->getConstantPool();
7174 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
7175 const Constant *C = ConstantInt::get(Int32Ty, NumLPads);
7177 // MachineConstantPool wants an explicit alignment.
7178 unsigned Align = MF->getDataLayout().getPrefTypeAlignment(Int32Ty);
7180 Align = MF->getDataLayout().getTypeAllocSize(C->getType());
7181 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
7183 unsigned VReg1 = MRI->createVirtualRegister(TRC);
7184 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRcp))
7185 .addReg(VReg1, RegState::Define)
7186 .addConstantPoolIndex(Idx)
7188 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
7190 .addReg(VReg1, RegState::Kill));
7193 BuildMI(DispatchBB, dl, TII->get(ARM::Bcc))
7198 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
7200 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::MOVsi), NewVReg3)
7202 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))));
7203 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
7204 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::LEApcrelJT), NewVReg4)
7205 .addJumpTableIndex(MJTI));
7207 MachineMemOperand *JTMMOLd = MF->getMachineMemOperand(
7208 MachinePointerInfo::getJumpTable(*MF), MachineMemOperand::MOLoad, 4, 4);
7209 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
7211 BuildMI(DispContBB, dl, TII->get(ARM::LDRrs), NewVReg5)
7212 .addReg(NewVReg3, RegState::Kill)
7215 .addMemOperand(JTMMOLd));
7217 if (RelocM == Reloc::PIC_) {
7218 BuildMI(DispContBB, dl, TII->get(ARM::BR_JTadd))
7219 .addReg(NewVReg5, RegState::Kill)
7221 .addJumpTableIndex(MJTI);
7223 BuildMI(DispContBB, dl, TII->get(ARM::BR_JTr))
7224 .addReg(NewVReg5, RegState::Kill)
7225 .addJumpTableIndex(MJTI);
7229 // Add the jump table entries as successors to the MBB.
7230 SmallPtrSet<MachineBasicBlock*, 8> SeenMBBs;
7231 for (std::vector<MachineBasicBlock*>::iterator
7232 I = LPadList.begin(), E = LPadList.end(); I != E; ++I) {
7233 MachineBasicBlock *CurMBB = *I;
7234 if (SeenMBBs.insert(CurMBB).second)
7235 DispContBB->addSuccessor(CurMBB);
7238 // N.B. the order the invoke BBs are processed in doesn't matter here.
7239 const MCPhysReg *SavedRegs = RI.getCalleeSavedRegs(MF);
7240 SmallVector<MachineBasicBlock*, 64> MBBLPads;
7241 for (MachineBasicBlock *BB : InvokeBBs) {
7243 // Remove the landing pad successor from the invoke block and replace it
7244 // with the new dispatch block.
7245 SmallVector<MachineBasicBlock*, 4> Successors(BB->succ_begin(),
7247 while (!Successors.empty()) {
7248 MachineBasicBlock *SMBB = Successors.pop_back_val();
7249 if (SMBB->isEHPad()) {
7250 BB->removeSuccessor(SMBB);
7251 MBBLPads.push_back(SMBB);
7255 BB->addSuccessor(DispatchBB);
7257 // Find the invoke call and mark all of the callee-saved registers as
7258 // 'implicit defined' so that they're spilled. This prevents code from
7259 // moving instructions to before the EH block, where they will never be
7261 for (MachineBasicBlock::reverse_iterator
7262 II = BB->rbegin(), IE = BB->rend(); II != IE; ++II) {
7263 if (!II->isCall()) continue;
7265 DenseMap<unsigned, bool> DefRegs;
7266 for (MachineInstr::mop_iterator
7267 OI = II->operands_begin(), OE = II->operands_end();
7269 if (!OI->isReg()) continue;
7270 DefRegs[OI->getReg()] = true;
7273 MachineInstrBuilder MIB(*MF, &*II);
7275 for (unsigned i = 0; SavedRegs[i] != 0; ++i) {
7276 unsigned Reg = SavedRegs[i];
7277 if (Subtarget->isThumb2() &&
7278 !ARM::tGPRRegClass.contains(Reg) &&
7279 !ARM::hGPRRegClass.contains(Reg))
7281 if (Subtarget->isThumb1Only() && !ARM::tGPRRegClass.contains(Reg))
7283 if (!Subtarget->isThumb() && !ARM::GPRRegClass.contains(Reg))
7286 MIB.addReg(Reg, RegState::ImplicitDefine | RegState::Dead);
7293 // Mark all former landing pads as non-landing pads. The dispatch is the only
7295 for (SmallVectorImpl<MachineBasicBlock*>::iterator
7296 I = MBBLPads.begin(), E = MBBLPads.end(); I != E; ++I)
7297 (*I)->setIsEHPad(false);
7299 // The instruction is gone now.
7300 MI->eraseFromParent();
7304 MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
7305 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
7306 E = MBB->succ_end(); I != E; ++I)
7309 llvm_unreachable("Expecting a BB with two successors!");
7312 /// Return the load opcode for a given load size. If load size >= 8,
7313 /// neon opcode will be returned.
7314 static unsigned getLdOpcode(unsigned LdSize, bool IsThumb1, bool IsThumb2) {
7316 return LdSize == 16 ? ARM::VLD1q32wb_fixed
7317 : LdSize == 8 ? ARM::VLD1d32wb_fixed : 0;
7319 return LdSize == 4 ? ARM::tLDRi
7320 : LdSize == 2 ? ARM::tLDRHi
7321 : LdSize == 1 ? ARM::tLDRBi : 0;
7323 return LdSize == 4 ? ARM::t2LDR_POST
7324 : LdSize == 2 ? ARM::t2LDRH_POST
7325 : LdSize == 1 ? ARM::t2LDRB_POST : 0;
7326 return LdSize == 4 ? ARM::LDR_POST_IMM
7327 : LdSize == 2 ? ARM::LDRH_POST
7328 : LdSize == 1 ? ARM::LDRB_POST_IMM : 0;
7331 /// Return the store opcode for a given store size. If store size >= 8,
7332 /// neon opcode will be returned.
7333 static unsigned getStOpcode(unsigned StSize, bool IsThumb1, bool IsThumb2) {
7335 return StSize == 16 ? ARM::VST1q32wb_fixed
7336 : StSize == 8 ? ARM::VST1d32wb_fixed : 0;
7338 return StSize == 4 ? ARM::tSTRi
7339 : StSize == 2 ? ARM::tSTRHi
7340 : StSize == 1 ? ARM::tSTRBi : 0;
7342 return StSize == 4 ? ARM::t2STR_POST
7343 : StSize == 2 ? ARM::t2STRH_POST
7344 : StSize == 1 ? ARM::t2STRB_POST : 0;
7345 return StSize == 4 ? ARM::STR_POST_IMM
7346 : StSize == 2 ? ARM::STRH_POST
7347 : StSize == 1 ? ARM::STRB_POST_IMM : 0;
7350 /// Emit a post-increment load operation with given size. The instructions
7351 /// will be added to BB at Pos.
7352 static void emitPostLd(MachineBasicBlock *BB, MachineInstr *Pos,
7353 const TargetInstrInfo *TII, DebugLoc dl,
7354 unsigned LdSize, unsigned Data, unsigned AddrIn,
7355 unsigned AddrOut, bool IsThumb1, bool IsThumb2) {
7356 unsigned LdOpc = getLdOpcode(LdSize, IsThumb1, IsThumb2);
7357 assert(LdOpc != 0 && "Should have a load opcode");
7359 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
7360 .addReg(AddrOut, RegState::Define).addReg(AddrIn)
7362 } else if (IsThumb1) {
7363 // load + update AddrIn
7364 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
7365 .addReg(AddrIn).addImm(0));
7366 MachineInstrBuilder MIB =
7367 BuildMI(*BB, Pos, dl, TII->get(ARM::tADDi8), AddrOut);
7368 MIB = AddDefaultT1CC(MIB);
7369 MIB.addReg(AddrIn).addImm(LdSize);
7370 AddDefaultPred(MIB);
7371 } else if (IsThumb2) {
7372 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
7373 .addReg(AddrOut, RegState::Define).addReg(AddrIn)
7376 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
7377 .addReg(AddrOut, RegState::Define).addReg(AddrIn)
7378 .addReg(0).addImm(LdSize));
7382 /// Emit a post-increment store operation with given size. The instructions
7383 /// will be added to BB at Pos.
7384 static void emitPostSt(MachineBasicBlock *BB, MachineInstr *Pos,
7385 const TargetInstrInfo *TII, DebugLoc dl,
7386 unsigned StSize, unsigned Data, unsigned AddrIn,
7387 unsigned AddrOut, bool IsThumb1, bool IsThumb2) {
7388 unsigned StOpc = getStOpcode(StSize, IsThumb1, IsThumb2);
7389 assert(StOpc != 0 && "Should have a store opcode");
7391 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
7392 .addReg(AddrIn).addImm(0).addReg(Data));
7393 } else if (IsThumb1) {
7394 // store + update AddrIn
7395 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc)).addReg(Data)
7396 .addReg(AddrIn).addImm(0));
7397 MachineInstrBuilder MIB =
7398 BuildMI(*BB, Pos, dl, TII->get(ARM::tADDi8), AddrOut);
7399 MIB = AddDefaultT1CC(MIB);
7400 MIB.addReg(AddrIn).addImm(StSize);
7401 AddDefaultPred(MIB);
7402 } else if (IsThumb2) {
7403 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
7404 .addReg(Data).addReg(AddrIn).addImm(StSize));
7406 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
7407 .addReg(Data).addReg(AddrIn).addReg(0)
7413 ARMTargetLowering::EmitStructByval(MachineInstr *MI,
7414 MachineBasicBlock *BB) const {
7415 // This pseudo instruction has 3 operands: dst, src, size
7416 // We expand it to a loop if size > Subtarget->getMaxInlineSizeThreshold().
7417 // Otherwise, we will generate unrolled scalar copies.
7418 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
7419 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7420 MachineFunction::iterator It = BB;
7423 unsigned dest = MI->getOperand(0).getReg();
7424 unsigned src = MI->getOperand(1).getReg();
7425 unsigned SizeVal = MI->getOperand(2).getImm();
7426 unsigned Align = MI->getOperand(3).getImm();
7427 DebugLoc dl = MI->getDebugLoc();
7429 MachineFunction *MF = BB->getParent();
7430 MachineRegisterInfo &MRI = MF->getRegInfo();
7431 unsigned UnitSize = 0;
7432 const TargetRegisterClass *TRC = nullptr;
7433 const TargetRegisterClass *VecTRC = nullptr;
7435 bool IsThumb1 = Subtarget->isThumb1Only();
7436 bool IsThumb2 = Subtarget->isThumb2();
7440 } else if (Align & 2) {
7443 // Check whether we can use NEON instructions.
7444 if (!MF->getFunction()->hasFnAttribute(Attribute::NoImplicitFloat) &&
7445 Subtarget->hasNEON()) {
7446 if ((Align % 16 == 0) && SizeVal >= 16)
7448 else if ((Align % 8 == 0) && SizeVal >= 8)
7451 // Can't use NEON instructions.
7456 // Select the correct opcode and register class for unit size load/store
7457 bool IsNeon = UnitSize >= 8;
7458 TRC = (IsThumb1 || IsThumb2) ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
7460 VecTRC = UnitSize == 16 ? &ARM::DPairRegClass
7461 : UnitSize == 8 ? &ARM::DPRRegClass
7464 unsigned BytesLeft = SizeVal % UnitSize;
7465 unsigned LoopSize = SizeVal - BytesLeft;
7467 if (SizeVal <= Subtarget->getMaxInlineSizeThreshold()) {
7468 // Use LDR and STR to copy.
7469 // [scratch, srcOut] = LDR_POST(srcIn, UnitSize)
7470 // [destOut] = STR_POST(scratch, destIn, UnitSize)
7471 unsigned srcIn = src;
7472 unsigned destIn = dest;
7473 for (unsigned i = 0; i < LoopSize; i+=UnitSize) {
7474 unsigned srcOut = MRI.createVirtualRegister(TRC);
7475 unsigned destOut = MRI.createVirtualRegister(TRC);
7476 unsigned scratch = MRI.createVirtualRegister(IsNeon ? VecTRC : TRC);
7477 emitPostLd(BB, MI, TII, dl, UnitSize, scratch, srcIn, srcOut,
7478 IsThumb1, IsThumb2);
7479 emitPostSt(BB, MI, TII, dl, UnitSize, scratch, destIn, destOut,
7480 IsThumb1, IsThumb2);
7485 // Handle the leftover bytes with LDRB and STRB.
7486 // [scratch, srcOut] = LDRB_POST(srcIn, 1)
7487 // [destOut] = STRB_POST(scratch, destIn, 1)
7488 for (unsigned i = 0; i < BytesLeft; i++) {
7489 unsigned srcOut = MRI.createVirtualRegister(TRC);
7490 unsigned destOut = MRI.createVirtualRegister(TRC);
7491 unsigned scratch = MRI.createVirtualRegister(TRC);
7492 emitPostLd(BB, MI, TII, dl, 1, scratch, srcIn, srcOut,
7493 IsThumb1, IsThumb2);
7494 emitPostSt(BB, MI, TII, dl, 1, scratch, destIn, destOut,
7495 IsThumb1, IsThumb2);
7499 MI->eraseFromParent(); // The instruction is gone now.
7503 // Expand the pseudo op to a loop.
7506 // movw varEnd, # --> with thumb2
7508 // ldrcp varEnd, idx --> without thumb2
7509 // fallthrough --> loopMBB
7511 // PHI varPhi, varEnd, varLoop
7512 // PHI srcPhi, src, srcLoop
7513 // PHI destPhi, dst, destLoop
7514 // [scratch, srcLoop] = LDR_POST(srcPhi, UnitSize)
7515 // [destLoop] = STR_POST(scratch, destPhi, UnitSize)
7516 // subs varLoop, varPhi, #UnitSize
7518 // fallthrough --> exitMBB
7520 // epilogue to handle left-over bytes
7521 // [scratch, srcOut] = LDRB_POST(srcLoop, 1)
7522 // [destOut] = STRB_POST(scratch, destLoop, 1)
7523 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
7524 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
7525 MF->insert(It, loopMBB);
7526 MF->insert(It, exitMBB);
7528 // Transfer the remainder of BB and its successor edges to exitMBB.
7529 exitMBB->splice(exitMBB->begin(), BB,
7530 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7531 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7533 // Load an immediate to varEnd.
7534 unsigned varEnd = MRI.createVirtualRegister(TRC);
7535 if (Subtarget->useMovt(*MF)) {
7536 unsigned Vtmp = varEnd;
7537 if ((LoopSize & 0xFFFF0000) != 0)
7538 Vtmp = MRI.createVirtualRegister(TRC);
7539 AddDefaultPred(BuildMI(BB, dl,
7540 TII->get(IsThumb2 ? ARM::t2MOVi16 : ARM::MOVi16),
7541 Vtmp).addImm(LoopSize & 0xFFFF));
7543 if ((LoopSize & 0xFFFF0000) != 0)
7544 AddDefaultPred(BuildMI(BB, dl,
7545 TII->get(IsThumb2 ? ARM::t2MOVTi16 : ARM::MOVTi16),
7548 .addImm(LoopSize >> 16));
7550 MachineConstantPool *ConstantPool = MF->getConstantPool();
7551 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
7552 const Constant *C = ConstantInt::get(Int32Ty, LoopSize);
7554 // MachineConstantPool wants an explicit alignment.
7555 unsigned Align = MF->getDataLayout().getPrefTypeAlignment(Int32Ty);
7557 Align = MF->getDataLayout().getTypeAllocSize(C->getType());
7558 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
7561 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(ARM::tLDRpci)).addReg(
7562 varEnd, RegState::Define).addConstantPoolIndex(Idx));
7564 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(ARM::LDRcp)).addReg(
7565 varEnd, RegState::Define).addConstantPoolIndex(Idx).addImm(0));
7567 BB->addSuccessor(loopMBB);
7569 // Generate the loop body:
7570 // varPhi = PHI(varLoop, varEnd)
7571 // srcPhi = PHI(srcLoop, src)
7572 // destPhi = PHI(destLoop, dst)
7573 MachineBasicBlock *entryBB = BB;
7575 unsigned varLoop = MRI.createVirtualRegister(TRC);
7576 unsigned varPhi = MRI.createVirtualRegister(TRC);
7577 unsigned srcLoop = MRI.createVirtualRegister(TRC);
7578 unsigned srcPhi = MRI.createVirtualRegister(TRC);
7579 unsigned destLoop = MRI.createVirtualRegister(TRC);
7580 unsigned destPhi = MRI.createVirtualRegister(TRC);
7582 BuildMI(*BB, BB->begin(), dl, TII->get(ARM::PHI), varPhi)
7583 .addReg(varLoop).addMBB(loopMBB)
7584 .addReg(varEnd).addMBB(entryBB);
7585 BuildMI(BB, dl, TII->get(ARM::PHI), srcPhi)
7586 .addReg(srcLoop).addMBB(loopMBB)
7587 .addReg(src).addMBB(entryBB);
7588 BuildMI(BB, dl, TII->get(ARM::PHI), destPhi)
7589 .addReg(destLoop).addMBB(loopMBB)
7590 .addReg(dest).addMBB(entryBB);
7592 // [scratch, srcLoop] = LDR_POST(srcPhi, UnitSize)
7593 // [destLoop] = STR_POST(scratch, destPhi, UnitSiz)
7594 unsigned scratch = MRI.createVirtualRegister(IsNeon ? VecTRC : TRC);
7595 emitPostLd(BB, BB->end(), TII, dl, UnitSize, scratch, srcPhi, srcLoop,
7596 IsThumb1, IsThumb2);
7597 emitPostSt(BB, BB->end(), TII, dl, UnitSize, scratch, destPhi, destLoop,
7598 IsThumb1, IsThumb2);
7600 // Decrement loop variable by UnitSize.
7602 MachineInstrBuilder MIB =
7603 BuildMI(*BB, BB->end(), dl, TII->get(ARM::tSUBi8), varLoop);
7604 MIB = AddDefaultT1CC(MIB);
7605 MIB.addReg(varPhi).addImm(UnitSize);
7606 AddDefaultPred(MIB);
7608 MachineInstrBuilder MIB =
7609 BuildMI(*BB, BB->end(), dl,
7610 TII->get(IsThumb2 ? ARM::t2SUBri : ARM::SUBri), varLoop);
7611 AddDefaultCC(AddDefaultPred(MIB.addReg(varPhi).addImm(UnitSize)));
7612 MIB->getOperand(5).setReg(ARM::CPSR);
7613 MIB->getOperand(5).setIsDef(true);
7615 BuildMI(*BB, BB->end(), dl,
7616 TII->get(IsThumb1 ? ARM::tBcc : IsThumb2 ? ARM::t2Bcc : ARM::Bcc))
7617 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
7619 // loopMBB can loop back to loopMBB or fall through to exitMBB.
7620 BB->addSuccessor(loopMBB);
7621 BB->addSuccessor(exitMBB);
7623 // Add epilogue to handle BytesLeft.
7625 MachineInstr *StartOfExit = exitMBB->begin();
7627 // [scratch, srcOut] = LDRB_POST(srcLoop, 1)
7628 // [destOut] = STRB_POST(scratch, destLoop, 1)
7629 unsigned srcIn = srcLoop;
7630 unsigned destIn = destLoop;
7631 for (unsigned i = 0; i < BytesLeft; i++) {
7632 unsigned srcOut = MRI.createVirtualRegister(TRC);
7633 unsigned destOut = MRI.createVirtualRegister(TRC);
7634 unsigned scratch = MRI.createVirtualRegister(TRC);
7635 emitPostLd(BB, StartOfExit, TII, dl, 1, scratch, srcIn, srcOut,
7636 IsThumb1, IsThumb2);
7637 emitPostSt(BB, StartOfExit, TII, dl, 1, scratch, destIn, destOut,
7638 IsThumb1, IsThumb2);
7643 MI->eraseFromParent(); // The instruction is gone now.
7648 ARMTargetLowering::EmitLowered__chkstk(MachineInstr *MI,
7649 MachineBasicBlock *MBB) const {
7650 const TargetMachine &TM = getTargetMachine();
7651 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
7652 DebugLoc DL = MI->getDebugLoc();
7654 assert(Subtarget->isTargetWindows() &&
7655 "__chkstk is only supported on Windows");
7656 assert(Subtarget->isThumb2() && "Windows on ARM requires Thumb-2 mode");
7658 // __chkstk takes the number of words to allocate on the stack in R4, and
7659 // returns the stack adjustment in number of bytes in R4. This will not
7660 // clober any other registers (other than the obvious lr).
7662 // Although, technically, IP should be considered a register which may be
7663 // clobbered, the call itself will not touch it. Windows on ARM is a pure
7664 // thumb-2 environment, so there is no interworking required. As a result, we
7665 // do not expect a veneer to be emitted by the linker, clobbering IP.
7667 // Each module receives its own copy of __chkstk, so no import thunk is
7668 // required, again, ensuring that IP is not clobbered.
7670 // Finally, although some linkers may theoretically provide a trampoline for
7671 // out of range calls (which is quite common due to a 32M range limitation of
7672 // branches for Thumb), we can generate the long-call version via
7673 // -mcmodel=large, alleviating the need for the trampoline which may clobber
7676 switch (TM.getCodeModel()) {
7677 case CodeModel::Small:
7678 case CodeModel::Medium:
7679 case CodeModel::Default:
7680 case CodeModel::Kernel:
7681 BuildMI(*MBB, MI, DL, TII.get(ARM::tBL))
7682 .addImm((unsigned)ARMCC::AL).addReg(0)
7683 .addExternalSymbol("__chkstk")
7684 .addReg(ARM::R4, RegState::Implicit | RegState::Kill)
7685 .addReg(ARM::R4, RegState::Implicit | RegState::Define)
7686 .addReg(ARM::R12, RegState::Implicit | RegState::Define | RegState::Dead);
7688 case CodeModel::Large:
7689 case CodeModel::JITDefault: {
7690 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
7691 unsigned Reg = MRI.createVirtualRegister(&ARM::rGPRRegClass);
7693 BuildMI(*MBB, MI, DL, TII.get(ARM::t2MOVi32imm), Reg)
7694 .addExternalSymbol("__chkstk");
7695 BuildMI(*MBB, MI, DL, TII.get(ARM::tBLXr))
7696 .addImm((unsigned)ARMCC::AL).addReg(0)
7697 .addReg(Reg, RegState::Kill)
7698 .addReg(ARM::R4, RegState::Implicit | RegState::Kill)
7699 .addReg(ARM::R4, RegState::Implicit | RegState::Define)
7700 .addReg(ARM::R12, RegState::Implicit | RegState::Define | RegState::Dead);
7705 AddDefaultCC(AddDefaultPred(BuildMI(*MBB, MI, DL, TII.get(ARM::t2SUBrr),
7707 .addReg(ARM::SP).addReg(ARM::R4)));
7709 MI->eraseFromParent();
7714 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
7715 MachineBasicBlock *BB) const {
7716 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
7717 DebugLoc dl = MI->getDebugLoc();
7718 bool isThumb2 = Subtarget->isThumb2();
7719 switch (MI->getOpcode()) {
7722 llvm_unreachable("Unexpected instr type to insert");
7724 // The Thumb2 pre-indexed stores have the same MI operands, they just
7725 // define them differently in the .td files from the isel patterns, so
7726 // they need pseudos.
7727 case ARM::t2STR_preidx:
7728 MI->setDesc(TII->get(ARM::t2STR_PRE));
7730 case ARM::t2STRB_preidx:
7731 MI->setDesc(TII->get(ARM::t2STRB_PRE));
7733 case ARM::t2STRH_preidx:
7734 MI->setDesc(TII->get(ARM::t2STRH_PRE));
7737 case ARM::STRi_preidx:
7738 case ARM::STRBi_preidx: {
7739 unsigned NewOpc = MI->getOpcode() == ARM::STRi_preidx ?
7740 ARM::STR_PRE_IMM : ARM::STRB_PRE_IMM;
7741 // Decode the offset.
7742 unsigned Offset = MI->getOperand(4).getImm();
7743 bool isSub = ARM_AM::getAM2Op(Offset) == ARM_AM::sub;
7744 Offset = ARM_AM::getAM2Offset(Offset);
7748 MachineMemOperand *MMO = *MI->memoperands_begin();
7749 BuildMI(*BB, MI, dl, TII->get(NewOpc))
7750 .addOperand(MI->getOperand(0)) // Rn_wb
7751 .addOperand(MI->getOperand(1)) // Rt
7752 .addOperand(MI->getOperand(2)) // Rn
7753 .addImm(Offset) // offset (skip GPR==zero_reg)
7754 .addOperand(MI->getOperand(5)) // pred
7755 .addOperand(MI->getOperand(6))
7756 .addMemOperand(MMO);
7757 MI->eraseFromParent();
7760 case ARM::STRr_preidx:
7761 case ARM::STRBr_preidx:
7762 case ARM::STRH_preidx: {
7764 switch (MI->getOpcode()) {
7765 default: llvm_unreachable("unexpected opcode!");
7766 case ARM::STRr_preidx: NewOpc = ARM::STR_PRE_REG; break;
7767 case ARM::STRBr_preidx: NewOpc = ARM::STRB_PRE_REG; break;
7768 case ARM::STRH_preidx: NewOpc = ARM::STRH_PRE; break;
7770 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc));
7771 for (unsigned i = 0; i < MI->getNumOperands(); ++i)
7772 MIB.addOperand(MI->getOperand(i));
7773 MI->eraseFromParent();
7777 case ARM::tMOVCCr_pseudo: {
7778 // To "insert" a SELECT_CC instruction, we actually have to insert the
7779 // diamond control-flow pattern. The incoming instruction knows the
7780 // destination vreg to set, the condition code register to branch on, the
7781 // true/false values to select between, and a branch opcode to use.
7782 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7783 MachineFunction::iterator It = BB;
7789 // cmpTY ccX, r1, r2
7791 // fallthrough --> copy0MBB
7792 MachineBasicBlock *thisMBB = BB;
7793 MachineFunction *F = BB->getParent();
7794 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7795 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7796 F->insert(It, copy0MBB);
7797 F->insert(It, sinkMBB);
7799 // Transfer the remainder of BB and its successor edges to sinkMBB.
7800 sinkMBB->splice(sinkMBB->begin(), BB,
7801 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7802 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
7804 BB->addSuccessor(copy0MBB);
7805 BB->addSuccessor(sinkMBB);
7807 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
7808 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
7811 // %FalseValue = ...
7812 // # fallthrough to sinkMBB
7815 // Update machine-CFG edges
7816 BB->addSuccessor(sinkMBB);
7819 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7822 BuildMI(*BB, BB->begin(), dl,
7823 TII->get(ARM::PHI), MI->getOperand(0).getReg())
7824 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
7825 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7827 MI->eraseFromParent(); // The pseudo instruction is gone now.
7832 case ARM::BCCZi64: {
7833 // If there is an unconditional branch to the other successor, remove it.
7834 BB->erase(std::next(MachineBasicBlock::iterator(MI)), BB->end());
7836 // Compare both parts that make up the double comparison separately for
7838 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
7840 unsigned LHS1 = MI->getOperand(1).getReg();
7841 unsigned LHS2 = MI->getOperand(2).getReg();
7843 AddDefaultPred(BuildMI(BB, dl,
7844 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
7845 .addReg(LHS1).addImm(0));
7846 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
7847 .addReg(LHS2).addImm(0)
7848 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
7850 unsigned RHS1 = MI->getOperand(3).getReg();
7851 unsigned RHS2 = MI->getOperand(4).getReg();
7852 AddDefaultPred(BuildMI(BB, dl,
7853 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
7854 .addReg(LHS1).addReg(RHS1));
7855 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
7856 .addReg(LHS2).addReg(RHS2)
7857 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
7860 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB();
7861 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
7862 if (MI->getOperand(0).getImm() == ARMCC::NE)
7863 std::swap(destMBB, exitMBB);
7865 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
7866 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
7868 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2B)).addMBB(exitMBB));
7870 BuildMI(BB, dl, TII->get(ARM::B)) .addMBB(exitMBB);
7872 MI->eraseFromParent(); // The pseudo instruction is gone now.
7876 case ARM::Int_eh_sjlj_setjmp:
7877 case ARM::Int_eh_sjlj_setjmp_nofp:
7878 case ARM::tInt_eh_sjlj_setjmp:
7879 case ARM::t2Int_eh_sjlj_setjmp:
7880 case ARM::t2Int_eh_sjlj_setjmp_nofp:
7883 case ARM::Int_eh_sjlj_setup_dispatch:
7884 EmitSjLjDispatchBlock(MI, BB);
7889 // To insert an ABS instruction, we have to insert the
7890 // diamond control-flow pattern. The incoming instruction knows the
7891 // source vreg to test against 0, the destination vreg to set,
7892 // the condition code register to branch on, the
7893 // true/false values to select between, and a branch opcode to use.
7898 // BCC (branch to SinkBB if V0 >= 0)
7899 // RSBBB: V3 = RSBri V2, 0 (compute ABS if V2 < 0)
7900 // SinkBB: V1 = PHI(V2, V3)
7901 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7902 MachineFunction::iterator BBI = BB;
7904 MachineFunction *Fn = BB->getParent();
7905 MachineBasicBlock *RSBBB = Fn->CreateMachineBasicBlock(LLVM_BB);
7906 MachineBasicBlock *SinkBB = Fn->CreateMachineBasicBlock(LLVM_BB);
7907 Fn->insert(BBI, RSBBB);
7908 Fn->insert(BBI, SinkBB);
7910 unsigned int ABSSrcReg = MI->getOperand(1).getReg();
7911 unsigned int ABSDstReg = MI->getOperand(0).getReg();
7912 bool ABSSrcKIll = MI->getOperand(1).isKill();
7913 bool isThumb2 = Subtarget->isThumb2();
7914 MachineRegisterInfo &MRI = Fn->getRegInfo();
7915 // In Thumb mode S must not be specified if source register is the SP or
7916 // PC and if destination register is the SP, so restrict register class
7917 unsigned NewRsbDstReg =
7918 MRI.createVirtualRegister(isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass);
7920 // Transfer the remainder of BB and its successor edges to sinkMBB.
7921 SinkBB->splice(SinkBB->begin(), BB,
7922 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7923 SinkBB->transferSuccessorsAndUpdatePHIs(BB);
7925 BB->addSuccessor(RSBBB);
7926 BB->addSuccessor(SinkBB);
7928 // fall through to SinkMBB
7929 RSBBB->addSuccessor(SinkBB);
7931 // insert a cmp at the end of BB
7932 AddDefaultPred(BuildMI(BB, dl,
7933 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
7934 .addReg(ABSSrcReg).addImm(0));
7936 // insert a bcc with opposite CC to ARMCC::MI at the end of BB
7938 TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)).addMBB(SinkBB)
7939 .addImm(ARMCC::getOppositeCondition(ARMCC::MI)).addReg(ARM::CPSR);
7941 // insert rsbri in RSBBB
7942 // Note: BCC and rsbri will be converted into predicated rsbmi
7943 // by if-conversion pass
7944 BuildMI(*RSBBB, RSBBB->begin(), dl,
7945 TII->get(isThumb2 ? ARM::t2RSBri : ARM::RSBri), NewRsbDstReg)
7946 .addReg(ABSSrcReg, ABSSrcKIll ? RegState::Kill : 0)
7947 .addImm(0).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
7949 // insert PHI in SinkBB,
7950 // reuse ABSDstReg to not change uses of ABS instruction
7951 BuildMI(*SinkBB, SinkBB->begin(), dl,
7952 TII->get(ARM::PHI), ABSDstReg)
7953 .addReg(NewRsbDstReg).addMBB(RSBBB)
7954 .addReg(ABSSrcReg).addMBB(BB);
7956 // remove ABS instruction
7957 MI->eraseFromParent();
7959 // return last added BB
7962 case ARM::COPY_STRUCT_BYVAL_I32:
7964 return EmitStructByval(MI, BB);
7965 case ARM::WIN__CHKSTK:
7966 return EmitLowered__chkstk(MI, BB);
7970 void ARMTargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
7971 SDNode *Node) const {
7972 const MCInstrDesc *MCID = &MI->getDesc();
7973 // Adjust potentially 's' setting instructions after isel, i.e. ADC, SBC, RSB,
7974 // RSC. Coming out of isel, they have an implicit CPSR def, but the optional
7975 // operand is still set to noreg. If needed, set the optional operand's
7976 // register to CPSR, and remove the redundant implicit def.
7978 // e.g. ADCS (..., CPSR<imp-def>) -> ADC (... opt:CPSR<def>).
7980 // Rename pseudo opcodes.
7981 unsigned NewOpc = convertAddSubFlagsOpcode(MI->getOpcode());
7983 const ARMBaseInstrInfo *TII = Subtarget->getInstrInfo();
7984 MCID = &TII->get(NewOpc);
7986 assert(MCID->getNumOperands() == MI->getDesc().getNumOperands() + 1 &&
7987 "converted opcode should be the same except for cc_out");
7991 // Add the optional cc_out operand
7992 MI->addOperand(MachineOperand::CreateReg(0, /*isDef=*/true));
7994 unsigned ccOutIdx = MCID->getNumOperands() - 1;
7996 // Any ARM instruction that sets the 's' bit should specify an optional
7997 // "cc_out" operand in the last operand position.
7998 if (!MI->hasOptionalDef() || !MCID->OpInfo[ccOutIdx].isOptionalDef()) {
7999 assert(!NewOpc && "Optional cc_out operand required");
8002 // Look for an implicit def of CPSR added by MachineInstr ctor. Remove it
8003 // since we already have an optional CPSR def.
8004 bool definesCPSR = false;
8005 bool deadCPSR = false;
8006 for (unsigned i = MCID->getNumOperands(), e = MI->getNumOperands();
8008 const MachineOperand &MO = MI->getOperand(i);
8009 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) {
8013 MI->RemoveOperand(i);
8018 assert(!NewOpc && "Optional cc_out operand required");
8021 assert(deadCPSR == !Node->hasAnyUseOfValue(1) && "inconsistent dead flag");
8023 assert(!MI->getOperand(ccOutIdx).getReg() &&
8024 "expect uninitialized optional cc_out operand");
8028 // If this instruction was defined with an optional CPSR def and its dag node
8029 // had a live implicit CPSR def, then activate the optional CPSR def.
8030 MachineOperand &MO = MI->getOperand(ccOutIdx);
8031 MO.setReg(ARM::CPSR);
8035 //===----------------------------------------------------------------------===//
8036 // ARM Optimization Hooks
8037 //===----------------------------------------------------------------------===//
8039 // Helper function that checks if N is a null or all ones constant.
8040 static inline bool isZeroOrAllOnes(SDValue N, bool AllOnes) {
8041 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
8044 return AllOnes ? C->isAllOnesValue() : C->isNullValue();
8047 // Return true if N is conditionally 0 or all ones.
8048 // Detects these expressions where cc is an i1 value:
8050 // (select cc 0, y) [AllOnes=0]
8051 // (select cc y, 0) [AllOnes=0]
8052 // (zext cc) [AllOnes=0]
8053 // (sext cc) [AllOnes=0/1]
8054 // (select cc -1, y) [AllOnes=1]
8055 // (select cc y, -1) [AllOnes=1]
8057 // Invert is set when N is the null/all ones constant when CC is false.
8058 // OtherOp is set to the alternative value of N.
8059 static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes,
8060 SDValue &CC, bool &Invert,
8062 SelectionDAG &DAG) {
8063 switch (N->getOpcode()) {
8064 default: return false;
8066 CC = N->getOperand(0);
8067 SDValue N1 = N->getOperand(1);
8068 SDValue N2 = N->getOperand(2);
8069 if (isZeroOrAllOnes(N1, AllOnes)) {
8074 if (isZeroOrAllOnes(N2, AllOnes)) {
8081 case ISD::ZERO_EXTEND:
8082 // (zext cc) can never be the all ones value.
8086 case ISD::SIGN_EXTEND: {
8088 EVT VT = N->getValueType(0);
8089 CC = N->getOperand(0);
8090 if (CC.getValueType() != MVT::i1)
8094 // When looking for an AllOnes constant, N is an sext, and the 'other'
8096 OtherOp = DAG.getConstant(0, dl, VT);
8097 else if (N->getOpcode() == ISD::ZERO_EXTEND)
8098 // When looking for a 0 constant, N can be zext or sext.
8099 OtherOp = DAG.getConstant(1, dl, VT);
8101 OtherOp = DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), dl,
8108 // Combine a constant select operand into its use:
8110 // (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
8111 // (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
8112 // (and (select cc, -1, c), x) -> (select cc, x, (and, x, c)) [AllOnes=1]
8113 // (or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
8114 // (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
8116 // The transform is rejected if the select doesn't have a constant operand that
8117 // is null, or all ones when AllOnes is set.
8119 // Also recognize sext/zext from i1:
8121 // (add (zext cc), x) -> (select cc (add x, 1), x)
8122 // (add (sext cc), x) -> (select cc (add x, -1), x)
8124 // These transformations eventually create predicated instructions.
8126 // @param N The node to transform.
8127 // @param Slct The N operand that is a select.
8128 // @param OtherOp The other N operand (x above).
8129 // @param DCI Context.
8130 // @param AllOnes Require the select constant to be all ones instead of null.
8131 // @returns The new node, or SDValue() on failure.
8133 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
8134 TargetLowering::DAGCombinerInfo &DCI,
8135 bool AllOnes = false) {
8136 SelectionDAG &DAG = DCI.DAG;
8137 EVT VT = N->getValueType(0);
8138 SDValue NonConstantVal;
8141 if (!isConditionalZeroOrAllOnes(Slct.getNode(), AllOnes, CCOp, SwapSelectOps,
8142 NonConstantVal, DAG))
8145 // Slct is now know to be the desired identity constant when CC is true.
8146 SDValue TrueVal = OtherOp;
8147 SDValue FalseVal = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
8148 OtherOp, NonConstantVal);
8149 // Unless SwapSelectOps says CC should be false.
8151 std::swap(TrueVal, FalseVal);
8153 return DAG.getNode(ISD::SELECT, SDLoc(N), VT,
8154 CCOp, TrueVal, FalseVal);
8157 // Attempt combineSelectAndUse on each operand of a commutative operator N.
8159 SDValue combineSelectAndUseCommutative(SDNode *N, bool AllOnes,
8160 TargetLowering::DAGCombinerInfo &DCI) {
8161 SDValue N0 = N->getOperand(0);
8162 SDValue N1 = N->getOperand(1);
8163 if (N0.getNode()->hasOneUse()) {
8164 SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes);
8165 if (Result.getNode())
8168 if (N1.getNode()->hasOneUse()) {
8169 SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes);
8170 if (Result.getNode())
8176 // AddCombineToVPADDL- For pair-wise add on neon, use the vpaddl instruction
8177 // (only after legalization).
8178 static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1,
8179 TargetLowering::DAGCombinerInfo &DCI,
8180 const ARMSubtarget *Subtarget) {
8182 // Only perform optimization if after legalize, and if NEON is available. We
8183 // also expected both operands to be BUILD_VECTORs.
8184 if (DCI.isBeforeLegalize() || !Subtarget->hasNEON()
8185 || N0.getOpcode() != ISD::BUILD_VECTOR
8186 || N1.getOpcode() != ISD::BUILD_VECTOR)
8189 // Check output type since VPADDL operand elements can only be 8, 16, or 32.
8190 EVT VT = N->getValueType(0);
8191 if (!VT.isInteger() || VT.getVectorElementType() == MVT::i64)
8194 // Check that the vector operands are of the right form.
8195 // N0 and N1 are BUILD_VECTOR nodes with N number of EXTRACT_VECTOR
8196 // operands, where N is the size of the formed vector.
8197 // Each EXTRACT_VECTOR should have the same input vector and odd or even
8198 // index such that we have a pair wise add pattern.
8200 // Grab the vector that all EXTRACT_VECTOR nodes should be referencing.
8201 if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
8203 SDValue Vec = N0->getOperand(0)->getOperand(0);
8204 SDNode *V = Vec.getNode();
8205 unsigned nextIndex = 0;
8207 // For each operands to the ADD which are BUILD_VECTORs,
8208 // check to see if each of their operands are an EXTRACT_VECTOR with
8209 // the same vector and appropriate index.
8210 for (unsigned i = 0, e = N0->getNumOperands(); i != e; ++i) {
8211 if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT
8212 && N1->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
8214 SDValue ExtVec0 = N0->getOperand(i);
8215 SDValue ExtVec1 = N1->getOperand(i);
8217 // First operand is the vector, verify its the same.
8218 if (V != ExtVec0->getOperand(0).getNode() ||
8219 V != ExtVec1->getOperand(0).getNode())
8222 // Second is the constant, verify its correct.
8223 ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(ExtVec0->getOperand(1));
8224 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(ExtVec1->getOperand(1));
8226 // For the constant, we want to see all the even or all the odd.
8227 if (!C0 || !C1 || C0->getZExtValue() != nextIndex
8228 || C1->getZExtValue() != nextIndex+1)
8237 // Create VPADDL node.
8238 SelectionDAG &DAG = DCI.DAG;
8239 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8243 // Build operand list.
8244 SmallVector<SDValue, 8> Ops;
8245 Ops.push_back(DAG.getConstant(Intrinsic::arm_neon_vpaddls, dl,
8246 TLI.getPointerTy(DAG.getDataLayout())));
8248 // Input is the vector.
8251 // Get widened type and narrowed type.
8253 unsigned numElem = VT.getVectorNumElements();
8255 EVT inputLaneType = Vec.getValueType().getVectorElementType();
8256 switch (inputLaneType.getSimpleVT().SimpleTy) {
8257 case MVT::i8: widenType = MVT::getVectorVT(MVT::i16, numElem); break;
8258 case MVT::i16: widenType = MVT::getVectorVT(MVT::i32, numElem); break;
8259 case MVT::i32: widenType = MVT::getVectorVT(MVT::i64, numElem); break;
8261 llvm_unreachable("Invalid vector element type for padd optimization.");
8264 SDValue tmp = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, widenType, Ops);
8265 unsigned ExtOp = VT.bitsGT(tmp.getValueType()) ? ISD::ANY_EXTEND : ISD::TRUNCATE;
8266 return DAG.getNode(ExtOp, dl, VT, tmp);
8269 static SDValue findMUL_LOHI(SDValue V) {
8270 if (V->getOpcode() == ISD::UMUL_LOHI ||
8271 V->getOpcode() == ISD::SMUL_LOHI)
8276 static SDValue AddCombineTo64bitMLAL(SDNode *AddcNode,
8277 TargetLowering::DAGCombinerInfo &DCI,
8278 const ARMSubtarget *Subtarget) {
8280 if (Subtarget->isThumb1Only()) return SDValue();
8282 // Only perform the checks after legalize when the pattern is available.
8283 if (DCI.isBeforeLegalize()) return SDValue();
8285 // Look for multiply add opportunities.
8286 // The pattern is a ISD::UMUL_LOHI followed by two add nodes, where
8287 // each add nodes consumes a value from ISD::UMUL_LOHI and there is
8288 // a glue link from the first add to the second add.
8289 // If we find this pattern, we can replace the U/SMUL_LOHI, ADDC, and ADDE by
8290 // a S/UMLAL instruction.
8293 // / \ [no multiline comment]
8299 assert(AddcNode->getOpcode() == ISD::ADDC && "Expect an ADDC");
8300 SDValue AddcOp0 = AddcNode->getOperand(0);
8301 SDValue AddcOp1 = AddcNode->getOperand(1);
8303 // Check if the two operands are from the same mul_lohi node.
8304 if (AddcOp0.getNode() == AddcOp1.getNode())
8307 assert(AddcNode->getNumValues() == 2 &&
8308 AddcNode->getValueType(0) == MVT::i32 &&
8309 "Expect ADDC with two result values. First: i32");
8311 // Check that we have a glued ADDC node.
8312 if (AddcNode->getValueType(1) != MVT::Glue)
8315 // Check that the ADDC adds the low result of the S/UMUL_LOHI.
8316 if (AddcOp0->getOpcode() != ISD::UMUL_LOHI &&
8317 AddcOp0->getOpcode() != ISD::SMUL_LOHI &&
8318 AddcOp1->getOpcode() != ISD::UMUL_LOHI &&
8319 AddcOp1->getOpcode() != ISD::SMUL_LOHI)
8322 // Look for the glued ADDE.
8323 SDNode* AddeNode = AddcNode->getGluedUser();
8327 // Make sure it is really an ADDE.
8328 if (AddeNode->getOpcode() != ISD::ADDE)
8331 assert(AddeNode->getNumOperands() == 3 &&
8332 AddeNode->getOperand(2).getValueType() == MVT::Glue &&
8333 "ADDE node has the wrong inputs");
8335 // Check for the triangle shape.
8336 SDValue AddeOp0 = AddeNode->getOperand(0);
8337 SDValue AddeOp1 = AddeNode->getOperand(1);
8339 // Make sure that the ADDE operands are not coming from the same node.
8340 if (AddeOp0.getNode() == AddeOp1.getNode())
8343 // Find the MUL_LOHI node walking up ADDE's operands.
8344 bool IsLeftOperandMUL = false;
8345 SDValue MULOp = findMUL_LOHI(AddeOp0);
8346 if (MULOp == SDValue())
8347 MULOp = findMUL_LOHI(AddeOp1);
8349 IsLeftOperandMUL = true;
8350 if (MULOp == SDValue())
8353 // Figure out the right opcode.
8354 unsigned Opc = MULOp->getOpcode();
8355 unsigned FinalOpc = (Opc == ISD::SMUL_LOHI) ? ARMISD::SMLAL : ARMISD::UMLAL;
8357 // Figure out the high and low input values to the MLAL node.
8358 SDValue* HiAdd = nullptr;
8359 SDValue* LoMul = nullptr;
8360 SDValue* LowAdd = nullptr;
8362 // Ensure that ADDE is from high result of ISD::SMUL_LOHI.
8363 if ((AddeOp0 != MULOp.getValue(1)) && (AddeOp1 != MULOp.getValue(1)))
8366 if (IsLeftOperandMUL)
8372 // Ensure that LoMul and LowAdd are taken from correct ISD::SMUL_LOHI node
8373 // whose low result is fed to the ADDC we are checking.
8375 if (AddcOp0 == MULOp.getValue(0)) {
8379 if (AddcOp1 == MULOp.getValue(0)) {
8387 // Create the merged node.
8388 SelectionDAG &DAG = DCI.DAG;
8390 // Build operand list.
8391 SmallVector<SDValue, 8> Ops;
8392 Ops.push_back(LoMul->getOperand(0));
8393 Ops.push_back(LoMul->getOperand(1));
8394 Ops.push_back(*LowAdd);
8395 Ops.push_back(*HiAdd);
8397 SDValue MLALNode = DAG.getNode(FinalOpc, SDLoc(AddcNode),
8398 DAG.getVTList(MVT::i32, MVT::i32), Ops);
8400 // Replace the ADDs' nodes uses by the MLA node's values.
8401 SDValue HiMLALResult(MLALNode.getNode(), 1);
8402 DAG.ReplaceAllUsesOfValueWith(SDValue(AddeNode, 0), HiMLALResult);
8404 SDValue LoMLALResult(MLALNode.getNode(), 0);
8405 DAG.ReplaceAllUsesOfValueWith(SDValue(AddcNode, 0), LoMLALResult);
8407 // Return original node to notify the driver to stop replacing.
8408 SDValue resNode(AddcNode, 0);
8412 /// PerformADDCCombine - Target-specific dag combine transform from
8413 /// ISD::ADDC, ISD::ADDE, and ISD::MUL_LOHI to MLAL.
8414 static SDValue PerformADDCCombine(SDNode *N,
8415 TargetLowering::DAGCombinerInfo &DCI,
8416 const ARMSubtarget *Subtarget) {
8418 return AddCombineTo64bitMLAL(N, DCI, Subtarget);
8422 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
8423 /// operands N0 and N1. This is a helper for PerformADDCombine that is
8424 /// called with the default operands, and if that fails, with commuted
8426 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
8427 TargetLowering::DAGCombinerInfo &DCI,
8428 const ARMSubtarget *Subtarget){
8430 // Attempt to create vpaddl for this add.
8431 SDValue Result = AddCombineToVPADDL(N, N0, N1, DCI, Subtarget);
8432 if (Result.getNode())
8435 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
8436 if (N0.getNode()->hasOneUse()) {
8437 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
8438 if (Result.getNode()) return Result;
8443 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
8445 static SDValue PerformADDCombine(SDNode *N,
8446 TargetLowering::DAGCombinerInfo &DCI,
8447 const ARMSubtarget *Subtarget) {
8448 SDValue N0 = N->getOperand(0);
8449 SDValue N1 = N->getOperand(1);
8451 // First try with the default operand order.
8452 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget);
8453 if (Result.getNode())
8456 // If that didn't work, try again with the operands commuted.
8457 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget);
8460 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
8462 static SDValue PerformSUBCombine(SDNode *N,
8463 TargetLowering::DAGCombinerInfo &DCI) {
8464 SDValue N0 = N->getOperand(0);
8465 SDValue N1 = N->getOperand(1);
8467 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
8468 if (N1.getNode()->hasOneUse()) {
8469 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
8470 if (Result.getNode()) return Result;
8476 /// PerformVMULCombine
8477 /// Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the
8478 /// special multiplier accumulator forwarding.
8484 // However, for (A + B) * (A + B),
8491 static SDValue PerformVMULCombine(SDNode *N,
8492 TargetLowering::DAGCombinerInfo &DCI,
8493 const ARMSubtarget *Subtarget) {
8494 if (!Subtarget->hasVMLxForwarding())
8497 SelectionDAG &DAG = DCI.DAG;
8498 SDValue N0 = N->getOperand(0);
8499 SDValue N1 = N->getOperand(1);
8500 unsigned Opcode = N0.getOpcode();
8501 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
8502 Opcode != ISD::FADD && Opcode != ISD::FSUB) {
8503 Opcode = N1.getOpcode();
8504 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
8505 Opcode != ISD::FADD && Opcode != ISD::FSUB)
8513 EVT VT = N->getValueType(0);
8515 SDValue N00 = N0->getOperand(0);
8516 SDValue N01 = N0->getOperand(1);
8517 return DAG.getNode(Opcode, DL, VT,
8518 DAG.getNode(ISD::MUL, DL, VT, N00, N1),
8519 DAG.getNode(ISD::MUL, DL, VT, N01, N1));
8522 static SDValue PerformMULCombine(SDNode *N,
8523 TargetLowering::DAGCombinerInfo &DCI,
8524 const ARMSubtarget *Subtarget) {
8525 SelectionDAG &DAG = DCI.DAG;
8527 if (Subtarget->isThumb1Only())
8530 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
8533 EVT VT = N->getValueType(0);
8534 if (VT.is64BitVector() || VT.is128BitVector())
8535 return PerformVMULCombine(N, DCI, Subtarget);
8539 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
8543 int64_t MulAmt = C->getSExtValue();
8544 unsigned ShiftAmt = countTrailingZeros<uint64_t>(MulAmt);
8546 ShiftAmt = ShiftAmt & (32 - 1);
8547 SDValue V = N->getOperand(0);
8551 MulAmt >>= ShiftAmt;
8554 if (isPowerOf2_32(MulAmt - 1)) {
8555 // (mul x, 2^N + 1) => (add (shl x, N), x)
8556 Res = DAG.getNode(ISD::ADD, DL, VT,
8558 DAG.getNode(ISD::SHL, DL, VT,
8560 DAG.getConstant(Log2_32(MulAmt - 1), DL,
8562 } else if (isPowerOf2_32(MulAmt + 1)) {
8563 // (mul x, 2^N - 1) => (sub (shl x, N), x)
8564 Res = DAG.getNode(ISD::SUB, DL, VT,
8565 DAG.getNode(ISD::SHL, DL, VT,
8567 DAG.getConstant(Log2_32(MulAmt + 1), DL,
8573 uint64_t MulAmtAbs = -MulAmt;
8574 if (isPowerOf2_32(MulAmtAbs + 1)) {
8575 // (mul x, -(2^N - 1)) => (sub x, (shl x, N))
8576 Res = DAG.getNode(ISD::SUB, DL, VT,
8578 DAG.getNode(ISD::SHL, DL, VT,
8580 DAG.getConstant(Log2_32(MulAmtAbs + 1), DL,
8582 } else if (isPowerOf2_32(MulAmtAbs - 1)) {
8583 // (mul x, -(2^N + 1)) => - (add (shl x, N), x)
8584 Res = DAG.getNode(ISD::ADD, DL, VT,
8586 DAG.getNode(ISD::SHL, DL, VT,
8588 DAG.getConstant(Log2_32(MulAmtAbs - 1), DL,
8590 Res = DAG.getNode(ISD::SUB, DL, VT,
8591 DAG.getConstant(0, DL, MVT::i32), Res);
8598 Res = DAG.getNode(ISD::SHL, DL, VT,
8599 Res, DAG.getConstant(ShiftAmt, DL, MVT::i32));
8601 // Do not add new nodes to DAG combiner worklist.
8602 DCI.CombineTo(N, Res, false);
8606 static SDValue PerformANDCombine(SDNode *N,
8607 TargetLowering::DAGCombinerInfo &DCI,
8608 const ARMSubtarget *Subtarget) {
8610 // Attempt to use immediate-form VBIC
8611 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
8613 EVT VT = N->getValueType(0);
8614 SelectionDAG &DAG = DCI.DAG;
8616 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
8619 APInt SplatBits, SplatUndef;
8620 unsigned SplatBitSize;
8623 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
8624 if (SplatBitSize <= 64) {
8626 SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(),
8627 SplatUndef.getZExtValue(), SplatBitSize,
8628 DAG, dl, VbicVT, VT.is128BitVector(),
8630 if (Val.getNode()) {
8632 DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0));
8633 SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val);
8634 return DAG.getNode(ISD::BITCAST, dl, VT, Vbic);
8639 if (!Subtarget->isThumb1Only()) {
8640 // fold (and (select cc, -1, c), x) -> (select cc, x, (and, x, c))
8641 SDValue Result = combineSelectAndUseCommutative(N, true, DCI);
8642 if (Result.getNode())
8649 /// PerformORCombine - Target-specific dag combine xforms for ISD::OR
8650 static SDValue PerformORCombine(SDNode *N,
8651 TargetLowering::DAGCombinerInfo &DCI,
8652 const ARMSubtarget *Subtarget) {
8653 // Attempt to use immediate-form VORR
8654 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
8656 EVT VT = N->getValueType(0);
8657 SelectionDAG &DAG = DCI.DAG;
8659 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
8662 APInt SplatBits, SplatUndef;
8663 unsigned SplatBitSize;
8665 if (BVN && Subtarget->hasNEON() &&
8666 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
8667 if (SplatBitSize <= 64) {
8669 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
8670 SplatUndef.getZExtValue(), SplatBitSize,
8671 DAG, dl, VorrVT, VT.is128BitVector(),
8673 if (Val.getNode()) {
8675 DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0));
8676 SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val);
8677 return DAG.getNode(ISD::BITCAST, dl, VT, Vorr);
8682 if (!Subtarget->isThumb1Only()) {
8683 // fold (or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
8684 SDValue Result = combineSelectAndUseCommutative(N, false, DCI);
8685 if (Result.getNode())
8689 // The code below optimizes (or (and X, Y), Z).
8690 // The AND operand needs to have a single user to make these optimizations
8692 SDValue N0 = N->getOperand(0);
8693 if (N0.getOpcode() != ISD::AND || !N0.hasOneUse())
8695 SDValue N1 = N->getOperand(1);
8697 // (or (and B, A), (and C, ~A)) => (VBSL A, B, C) when A is a constant.
8698 if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() &&
8699 DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
8701 unsigned SplatBitSize;
8704 APInt SplatBits0, SplatBits1;
8705 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1));
8706 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(1));
8707 // Ensure that the second operand of both ands are constants
8708 if (BVN0 && BVN0->isConstantSplat(SplatBits0, SplatUndef, SplatBitSize,
8709 HasAnyUndefs) && !HasAnyUndefs) {
8710 if (BVN1 && BVN1->isConstantSplat(SplatBits1, SplatUndef, SplatBitSize,
8711 HasAnyUndefs) && !HasAnyUndefs) {
8712 // Ensure that the bit width of the constants are the same and that
8713 // the splat arguments are logical inverses as per the pattern we
8714 // are trying to simplify.
8715 if (SplatBits0.getBitWidth() == SplatBits1.getBitWidth() &&
8716 SplatBits0 == ~SplatBits1) {
8717 // Canonicalize the vector type to make instruction selection
8719 EVT CanonicalVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
8720 SDValue Result = DAG.getNode(ARMISD::VBSL, dl, CanonicalVT,
8724 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
8730 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when
8733 // BFI is only available on V6T2+
8734 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops())
8738 // 1) or (and A, mask), val => ARMbfi A, val, mask
8739 // iff (val & mask) == val
8741 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
8742 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2)
8743 // && mask == ~mask2
8744 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2)
8745 // && ~mask == mask2
8746 // (i.e., copy a bitfield value into another bitfield of the same width)
8751 SDValue N00 = N0.getOperand(0);
8753 // The value and the mask need to be constants so we can verify this is
8754 // actually a bitfield set. If the mask is 0xffff, we can do better
8755 // via a movt instruction, so don't use BFI in that case.
8756 SDValue MaskOp = N0.getOperand(1);
8757 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(MaskOp);
8760 unsigned Mask = MaskC->getZExtValue();
8764 // Case (1): or (and A, mask), val => ARMbfi A, val, mask
8765 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
8767 unsigned Val = N1C->getZExtValue();
8768 if ((Val & ~Mask) != Val)
8771 if (ARM::isBitFieldInvertedMask(Mask)) {
8772 Val >>= countTrailingZeros(~Mask);
8774 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00,
8775 DAG.getConstant(Val, DL, MVT::i32),
8776 DAG.getConstant(Mask, DL, MVT::i32));
8778 // Do not add new nodes to DAG combiner worklist.
8779 DCI.CombineTo(N, Res, false);
8782 } else if (N1.getOpcode() == ISD::AND) {
8783 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
8784 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
8787 unsigned Mask2 = N11C->getZExtValue();
8789 // Mask and ~Mask2 (or reverse) must be equivalent for the BFI pattern
8791 if (ARM::isBitFieldInvertedMask(Mask) &&
8793 // The pack halfword instruction works better for masks that fit it,
8794 // so use that when it's available.
8795 if (Subtarget->hasT2ExtractPack() &&
8796 (Mask == 0xffff || Mask == 0xffff0000))
8799 unsigned amt = countTrailingZeros(Mask2);
8800 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
8801 DAG.getConstant(amt, DL, MVT::i32));
8802 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res,
8803 DAG.getConstant(Mask, DL, MVT::i32));
8804 // Do not add new nodes to DAG combiner worklist.
8805 DCI.CombineTo(N, Res, false);
8807 } else if (ARM::isBitFieldInvertedMask(~Mask) &&
8809 // The pack halfword instruction works better for masks that fit it,
8810 // so use that when it's available.
8811 if (Subtarget->hasT2ExtractPack() &&
8812 (Mask2 == 0xffff || Mask2 == 0xffff0000))
8815 unsigned lsb = countTrailingZeros(Mask);
8816 Res = DAG.getNode(ISD::SRL, DL, VT, N00,
8817 DAG.getConstant(lsb, DL, MVT::i32));
8818 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
8819 DAG.getConstant(Mask2, DL, MVT::i32));
8820 // Do not add new nodes to DAG combiner worklist.
8821 DCI.CombineTo(N, Res, false);
8826 if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) &&
8827 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) &&
8828 ARM::isBitFieldInvertedMask(~Mask)) {
8829 // Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask
8830 // where lsb(mask) == #shamt and masked bits of B are known zero.
8831 SDValue ShAmt = N00.getOperand(1);
8832 unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue();
8833 unsigned LSB = countTrailingZeros(Mask);
8837 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0),
8838 DAG.getConstant(~Mask, DL, MVT::i32));
8840 // Do not add new nodes to DAG combiner worklist.
8841 DCI.CombineTo(N, Res, false);
8847 static SDValue PerformXORCombine(SDNode *N,
8848 TargetLowering::DAGCombinerInfo &DCI,
8849 const ARMSubtarget *Subtarget) {
8850 EVT VT = N->getValueType(0);
8851 SelectionDAG &DAG = DCI.DAG;
8853 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
8856 if (!Subtarget->isThumb1Only()) {
8857 // fold (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
8858 SDValue Result = combineSelectAndUseCommutative(N, false, DCI);
8859 if (Result.getNode())
8866 /// PerformBFICombine - (bfi A, (and B, Mask1), Mask2) -> (bfi A, B, Mask2) iff
8867 /// the bits being cleared by the AND are not demanded by the BFI.
8868 static SDValue PerformBFICombine(SDNode *N,
8869 TargetLowering::DAGCombinerInfo &DCI) {
8870 SDValue N1 = N->getOperand(1);
8871 if (N1.getOpcode() == ISD::AND) {
8872 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
8875 unsigned InvMask = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
8876 unsigned LSB = countTrailingZeros(~InvMask);
8877 unsigned Width = (32 - countLeadingZeros(~InvMask)) - LSB;
8879 static_cast<unsigned>(std::numeric_limits<unsigned>::digits) &&
8880 "undefined behavior");
8881 unsigned Mask = (1u << Width) - 1;
8882 unsigned Mask2 = N11C->getZExtValue();
8883 if ((Mask & (~Mask2)) == 0)
8884 return DCI.DAG.getNode(ARMISD::BFI, SDLoc(N), N->getValueType(0),
8885 N->getOperand(0), N1.getOperand(0),
8891 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
8892 /// ARMISD::VMOVRRD.
8893 static SDValue PerformVMOVRRDCombine(SDNode *N,
8894 TargetLowering::DAGCombinerInfo &DCI,
8895 const ARMSubtarget *Subtarget) {
8896 // vmovrrd(vmovdrr x, y) -> x,y
8897 SDValue InDouble = N->getOperand(0);
8898 if (InDouble.getOpcode() == ARMISD::VMOVDRR && !Subtarget->isFPOnlySP())
8899 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
8901 // vmovrrd(load f64) -> (load i32), (load i32)
8902 SDNode *InNode = InDouble.getNode();
8903 if (ISD::isNormalLoad(InNode) && InNode->hasOneUse() &&
8904 InNode->getValueType(0) == MVT::f64 &&
8905 InNode->getOperand(1).getOpcode() == ISD::FrameIndex &&
8906 !cast<LoadSDNode>(InNode)->isVolatile()) {
8907 // TODO: Should this be done for non-FrameIndex operands?
8908 LoadSDNode *LD = cast<LoadSDNode>(InNode);
8910 SelectionDAG &DAG = DCI.DAG;
8912 SDValue BasePtr = LD->getBasePtr();
8913 SDValue NewLD1 = DAG.getLoad(MVT::i32, DL, LD->getChain(), BasePtr,
8914 LD->getPointerInfo(), LD->isVolatile(),
8915 LD->isNonTemporal(), LD->isInvariant(),
8916 LD->getAlignment());
8918 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
8919 DAG.getConstant(4, DL, MVT::i32));
8920 SDValue NewLD2 = DAG.getLoad(MVT::i32, DL, NewLD1.getValue(1), OffsetPtr,
8921 LD->getPointerInfo(), LD->isVolatile(),
8922 LD->isNonTemporal(), LD->isInvariant(),
8923 std::min(4U, LD->getAlignment() / 2));
8925 DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), NewLD2.getValue(1));
8926 if (DCI.DAG.getDataLayout().isBigEndian())
8927 std::swap (NewLD1, NewLD2);
8928 SDValue Result = DCI.CombineTo(N, NewLD1, NewLD2);
8935 /// PerformVMOVDRRCombine - Target-specific dag combine xforms for
8936 /// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands.
8937 static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) {
8938 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X)
8939 SDValue Op0 = N->getOperand(0);
8940 SDValue Op1 = N->getOperand(1);
8941 if (Op0.getOpcode() == ISD::BITCAST)
8942 Op0 = Op0.getOperand(0);
8943 if (Op1.getOpcode() == ISD::BITCAST)
8944 Op1 = Op1.getOperand(0);
8945 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
8946 Op0.getNode() == Op1.getNode() &&
8947 Op0.getResNo() == 0 && Op1.getResNo() == 1)
8948 return DAG.getNode(ISD::BITCAST, SDLoc(N),
8949 N->getValueType(0), Op0.getOperand(0));
8953 /// hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node
8954 /// are normal, non-volatile loads. If so, it is profitable to bitcast an
8955 /// i64 vector to have f64 elements, since the value can then be loaded
8956 /// directly into a VFP register.
8957 static bool hasNormalLoadOperand(SDNode *N) {
8958 unsigned NumElts = N->getValueType(0).getVectorNumElements();
8959 for (unsigned i = 0; i < NumElts; ++i) {
8960 SDNode *Elt = N->getOperand(i).getNode();
8961 if (ISD::isNormalLoad(Elt) && !cast<LoadSDNode>(Elt)->isVolatile())
8967 /// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for
8968 /// ISD::BUILD_VECTOR.
8969 static SDValue PerformBUILD_VECTORCombine(SDNode *N,
8970 TargetLowering::DAGCombinerInfo &DCI,
8971 const ARMSubtarget *Subtarget) {
8972 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X):
8973 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value
8974 // into a pair of GPRs, which is fine when the value is used as a scalar,
8975 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD.
8976 SelectionDAG &DAG = DCI.DAG;
8977 if (N->getNumOperands() == 2) {
8978 SDValue RV = PerformVMOVDRRCombine(N, DAG);
8983 // Load i64 elements as f64 values so that type legalization does not split
8984 // them up into i32 values.
8985 EVT VT = N->getValueType(0);
8986 if (VT.getVectorElementType() != MVT::i64 || !hasNormalLoadOperand(N))
8989 SmallVector<SDValue, 8> Ops;
8990 unsigned NumElts = VT.getVectorNumElements();
8991 for (unsigned i = 0; i < NumElts; ++i) {
8992 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(i));
8994 // Make the DAGCombiner fold the bitcast.
8995 DCI.AddToWorklist(V.getNode());
8997 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, NumElts);
8998 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, FloatVT, Ops);
8999 return DAG.getNode(ISD::BITCAST, dl, VT, BV);
9002 /// \brief Target-specific dag combine xforms for ARMISD::BUILD_VECTOR.
9004 PerformARMBUILD_VECTORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
9005 // ARMISD::BUILD_VECTOR is introduced when legalizing ISD::BUILD_VECTOR.
9006 // At that time, we may have inserted bitcasts from integer to float.
9007 // If these bitcasts have survived DAGCombine, change the lowering of this
9008 // BUILD_VECTOR in something more vector friendly, i.e., that does not
9009 // force to use floating point types.
9011 // Make sure we can change the type of the vector.
9012 // This is possible iff:
9013 // 1. The vector is only used in a bitcast to a integer type. I.e.,
9014 // 1.1. Vector is used only once.
9015 // 1.2. Use is a bit convert to an integer type.
9016 // 2. The size of its operands are 32-bits (64-bits are not legal).
9017 EVT VT = N->getValueType(0);
9018 EVT EltVT = VT.getVectorElementType();
9020 // Check 1.1. and 2.
9021 if (EltVT.getSizeInBits() != 32 || !N->hasOneUse())
9024 // By construction, the input type must be float.
9025 assert(EltVT == MVT::f32 && "Unexpected type!");
9028 SDNode *Use = *N->use_begin();
9029 if (Use->getOpcode() != ISD::BITCAST ||
9030 Use->getValueType(0).isFloatingPoint())
9033 // Check profitability.
9034 // Model is, if more than half of the relevant operands are bitcast from
9035 // i32, turn the build_vector into a sequence of insert_vector_elt.
9036 // Relevant operands are everything that is not statically
9037 // (i.e., at compile time) bitcasted.
9038 unsigned NumOfBitCastedElts = 0;
9039 unsigned NumElts = VT.getVectorNumElements();
9040 unsigned NumOfRelevantElts = NumElts;
9041 for (unsigned Idx = 0; Idx < NumElts; ++Idx) {
9042 SDValue Elt = N->getOperand(Idx);
9043 if (Elt->getOpcode() == ISD::BITCAST) {
9044 // Assume only bit cast to i32 will go away.
9045 if (Elt->getOperand(0).getValueType() == MVT::i32)
9046 ++NumOfBitCastedElts;
9047 } else if (Elt.getOpcode() == ISD::UNDEF || isa<ConstantSDNode>(Elt))
9048 // Constants are statically casted, thus do not count them as
9049 // relevant operands.
9050 --NumOfRelevantElts;
9053 // Check if more than half of the elements require a non-free bitcast.
9054 if (NumOfBitCastedElts <= NumOfRelevantElts / 2)
9057 SelectionDAG &DAG = DCI.DAG;
9058 // Create the new vector type.
9059 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
9060 // Check if the type is legal.
9061 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9062 if (!TLI.isTypeLegal(VecVT))
9066 // ARMISD::BUILD_VECTOR E1, E2, ..., EN.
9067 // => BITCAST INSERT_VECTOR_ELT
9068 // (INSERT_VECTOR_ELT (...), (BITCAST EN-1), N-1),
9070 SDValue Vec = DAG.getUNDEF(VecVT);
9072 for (unsigned Idx = 0 ; Idx < NumElts; ++Idx) {
9073 SDValue V = N->getOperand(Idx);
9074 if (V.getOpcode() == ISD::UNDEF)
9076 if (V.getOpcode() == ISD::BITCAST &&
9077 V->getOperand(0).getValueType() == MVT::i32)
9078 // Fold obvious case.
9079 V = V.getOperand(0);
9081 V = DAG.getNode(ISD::BITCAST, SDLoc(V), MVT::i32, V);
9082 // Make the DAGCombiner fold the bitcasts.
9083 DCI.AddToWorklist(V.getNode());
9085 SDValue LaneIdx = DAG.getConstant(Idx, dl, MVT::i32);
9086 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecVT, Vec, V, LaneIdx);
9088 Vec = DAG.getNode(ISD::BITCAST, dl, VT, Vec);
9089 // Make the DAGCombiner fold the bitcasts.
9090 DCI.AddToWorklist(Vec.getNode());
9094 /// PerformInsertEltCombine - Target-specific dag combine xforms for
9095 /// ISD::INSERT_VECTOR_ELT.
9096 static SDValue PerformInsertEltCombine(SDNode *N,
9097 TargetLowering::DAGCombinerInfo &DCI) {
9098 // Bitcast an i64 load inserted into a vector to f64.
9099 // Otherwise, the i64 value will be legalized to a pair of i32 values.
9100 EVT VT = N->getValueType(0);
9101 SDNode *Elt = N->getOperand(1).getNode();
9102 if (VT.getVectorElementType() != MVT::i64 ||
9103 !ISD::isNormalLoad(Elt) || cast<LoadSDNode>(Elt)->isVolatile())
9106 SelectionDAG &DAG = DCI.DAG;
9108 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
9109 VT.getVectorNumElements());
9110 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, N->getOperand(0));
9111 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(1));
9112 // Make the DAGCombiner fold the bitcasts.
9113 DCI.AddToWorklist(Vec.getNode());
9114 DCI.AddToWorklist(V.getNode());
9115 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT,
9116 Vec, V, N->getOperand(2));
9117 return DAG.getNode(ISD::BITCAST, dl, VT, InsElt);
9120 /// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for
9121 /// ISD::VECTOR_SHUFFLE.
9122 static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) {
9123 // The LLVM shufflevector instruction does not require the shuffle mask
9124 // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does
9125 // have that requirement. When translating to ISD::VECTOR_SHUFFLE, if the
9126 // operands do not match the mask length, they are extended by concatenating
9127 // them with undef vectors. That is probably the right thing for other
9128 // targets, but for NEON it is better to concatenate two double-register
9129 // size vector operands into a single quad-register size vector. Do that
9130 // transformation here:
9131 // shuffle(concat(v1, undef), concat(v2, undef)) ->
9132 // shuffle(concat(v1, v2), undef)
9133 SDValue Op0 = N->getOperand(0);
9134 SDValue Op1 = N->getOperand(1);
9135 if (Op0.getOpcode() != ISD::CONCAT_VECTORS ||
9136 Op1.getOpcode() != ISD::CONCAT_VECTORS ||
9137 Op0.getNumOperands() != 2 ||
9138 Op1.getNumOperands() != 2)
9140 SDValue Concat0Op1 = Op0.getOperand(1);
9141 SDValue Concat1Op1 = Op1.getOperand(1);
9142 if (Concat0Op1.getOpcode() != ISD::UNDEF ||
9143 Concat1Op1.getOpcode() != ISD::UNDEF)
9145 // Skip the transformation if any of the types are illegal.
9146 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9147 EVT VT = N->getValueType(0);
9148 if (!TLI.isTypeLegal(VT) ||
9149 !TLI.isTypeLegal(Concat0Op1.getValueType()) ||
9150 !TLI.isTypeLegal(Concat1Op1.getValueType()))
9153 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT,
9154 Op0.getOperand(0), Op1.getOperand(0));
9155 // Translate the shuffle mask.
9156 SmallVector<int, 16> NewMask;
9157 unsigned NumElts = VT.getVectorNumElements();
9158 unsigned HalfElts = NumElts/2;
9159 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
9160 for (unsigned n = 0; n < NumElts; ++n) {
9161 int MaskElt = SVN->getMaskElt(n);
9163 if (MaskElt < (int)HalfElts)
9165 else if (MaskElt >= (int)NumElts && MaskElt < (int)(NumElts + HalfElts))
9166 NewElt = HalfElts + MaskElt - NumElts;
9167 NewMask.push_back(NewElt);
9169 return DAG.getVectorShuffle(VT, SDLoc(N), NewConcat,
9170 DAG.getUNDEF(VT), NewMask.data());
9173 /// CombineBaseUpdate - Target-specific DAG combine function for VLDDUP,
9174 /// NEON load/store intrinsics, and generic vector load/stores, to merge
9175 /// base address updates.
9176 /// For generic load/stores, the memory type is assumed to be a vector.
9177 /// The caller is assumed to have checked legality.
9178 static SDValue CombineBaseUpdate(SDNode *N,
9179 TargetLowering::DAGCombinerInfo &DCI) {
9180 SelectionDAG &DAG = DCI.DAG;
9181 const bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID ||
9182 N->getOpcode() == ISD::INTRINSIC_W_CHAIN);
9183 const bool isStore = N->getOpcode() == ISD::STORE;
9184 const unsigned AddrOpIdx = ((isIntrinsic || isStore) ? 2 : 1);
9185 SDValue Addr = N->getOperand(AddrOpIdx);
9186 MemSDNode *MemN = cast<MemSDNode>(N);
9189 // Search for a use of the address operand that is an increment.
9190 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
9191 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
9193 if (User->getOpcode() != ISD::ADD ||
9194 UI.getUse().getResNo() != Addr.getResNo())
9197 // Check that the add is independent of the load/store. Otherwise, folding
9198 // it would create a cycle.
9199 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
9202 // Find the new opcode for the updating load/store.
9203 bool isLoadOp = true;
9204 bool isLaneOp = false;
9205 unsigned NewOpc = 0;
9206 unsigned NumVecs = 0;
9208 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
9210 default: llvm_unreachable("unexpected intrinsic for Neon base update");
9211 case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD;
9213 case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD;
9215 case Intrinsic::arm_neon_vld3: NewOpc = ARMISD::VLD3_UPD;
9217 case Intrinsic::arm_neon_vld4: NewOpc = ARMISD::VLD4_UPD;
9219 case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD;
9220 NumVecs = 2; isLaneOp = true; break;
9221 case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD;
9222 NumVecs = 3; isLaneOp = true; break;
9223 case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD;
9224 NumVecs = 4; isLaneOp = true; break;
9225 case Intrinsic::arm_neon_vst1: NewOpc = ARMISD::VST1_UPD;
9226 NumVecs = 1; isLoadOp = false; break;
9227 case Intrinsic::arm_neon_vst2: NewOpc = ARMISD::VST2_UPD;
9228 NumVecs = 2; isLoadOp = false; break;
9229 case Intrinsic::arm_neon_vst3: NewOpc = ARMISD::VST3_UPD;
9230 NumVecs = 3; isLoadOp = false; break;
9231 case Intrinsic::arm_neon_vst4: NewOpc = ARMISD::VST4_UPD;
9232 NumVecs = 4; isLoadOp = false; break;
9233 case Intrinsic::arm_neon_vst2lane: NewOpc = ARMISD::VST2LN_UPD;
9234 NumVecs = 2; isLoadOp = false; isLaneOp = true; break;
9235 case Intrinsic::arm_neon_vst3lane: NewOpc = ARMISD::VST3LN_UPD;
9236 NumVecs = 3; isLoadOp = false; isLaneOp = true; break;
9237 case Intrinsic::arm_neon_vst4lane: NewOpc = ARMISD::VST4LN_UPD;
9238 NumVecs = 4; isLoadOp = false; isLaneOp = true; break;
9242 switch (N->getOpcode()) {
9243 default: llvm_unreachable("unexpected opcode for Neon base update");
9244 case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break;
9245 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break;
9246 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break;
9247 case ISD::LOAD: NewOpc = ARMISD::VLD1_UPD;
9248 NumVecs = 1; isLaneOp = false; break;
9249 case ISD::STORE: NewOpc = ARMISD::VST1_UPD;
9250 NumVecs = 1; isLaneOp = false; isLoadOp = false; break;
9254 // Find the size of memory referenced by the load/store.
9257 VecTy = N->getValueType(0);
9258 } else if (isIntrinsic) {
9259 VecTy = N->getOperand(AddrOpIdx+1).getValueType();
9261 assert(isStore && "Node has to be a load, a store, or an intrinsic!");
9262 VecTy = N->getOperand(1).getValueType();
9265 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
9267 NumBytes /= VecTy.getVectorNumElements();
9269 // If the increment is a constant, it must match the memory ref size.
9270 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
9271 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
9272 uint64_t IncVal = CInc->getZExtValue();
9273 if (IncVal != NumBytes)
9275 } else if (NumBytes >= 3 * 16) {
9276 // VLD3/4 and VST3/4 for 128-bit vectors are implemented with two
9277 // separate instructions that make it harder to use a non-constant update.
9281 // OK, we found an ADD we can fold into the base update.
9282 // Now, create a _UPD node, taking care of not breaking alignment.
9284 EVT AlignedVecTy = VecTy;
9285 unsigned Alignment = MemN->getAlignment();
9287 // If this is a less-than-standard-aligned load/store, change the type to
9288 // match the standard alignment.
9289 // The alignment is overlooked when selecting _UPD variants; and it's
9290 // easier to introduce bitcasts here than fix that.
9291 // There are 3 ways to get to this base-update combine:
9292 // - intrinsics: they are assumed to be properly aligned (to the standard
9293 // alignment of the memory type), so we don't need to do anything.
9294 // - ARMISD::VLDx nodes: they are only generated from the aforementioned
9295 // intrinsics, so, likewise, there's nothing to do.
9296 // - generic load/store instructions: the alignment is specified as an
9297 // explicit operand, rather than implicitly as the standard alignment
9298 // of the memory type (like the intrisics). We need to change the
9299 // memory type to match the explicit alignment. That way, we don't
9300 // generate non-standard-aligned ARMISD::VLDx nodes.
9301 if (isa<LSBaseSDNode>(N)) {
9304 if (Alignment < VecTy.getScalarSizeInBits() / 8) {
9305 MVT EltTy = MVT::getIntegerVT(Alignment * 8);
9306 assert(NumVecs == 1 && "Unexpected multi-element generic load/store.");
9307 assert(!isLaneOp && "Unexpected generic load/store lane.");
9308 unsigned NumElts = NumBytes / (EltTy.getSizeInBits() / 8);
9309 AlignedVecTy = MVT::getVectorVT(EltTy, NumElts);
9311 // Don't set an explicit alignment on regular load/stores that we want
9312 // to transform to VLD/VST 1_UPD nodes.
9313 // This matches the behavior of regular load/stores, which only get an
9314 // explicit alignment if the MMO alignment is larger than the standard
9315 // alignment of the memory type.
9316 // Intrinsics, however, always get an explicit alignment, set to the
9317 // alignment of the MMO.
9321 // Create the new updating load/store node.
9322 // First, create an SDVTList for the new updating node's results.
9324 unsigned NumResultVecs = (isLoadOp ? NumVecs : 0);
9326 for (n = 0; n < NumResultVecs; ++n)
9327 Tys[n] = AlignedVecTy;
9328 Tys[n++] = MVT::i32;
9329 Tys[n] = MVT::Other;
9330 SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumResultVecs+2));
9332 // Then, gather the new node's operands.
9333 SmallVector<SDValue, 8> Ops;
9334 Ops.push_back(N->getOperand(0)); // incoming chain
9335 Ops.push_back(N->getOperand(AddrOpIdx));
9338 if (StoreSDNode *StN = dyn_cast<StoreSDNode>(N)) {
9339 // Try to match the intrinsic's signature
9340 Ops.push_back(StN->getValue());
9342 // Loads (and of course intrinsics) match the intrinsics' signature,
9343 // so just add all but the alignment operand.
9344 for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands() - 1; ++i)
9345 Ops.push_back(N->getOperand(i));
9348 // For all node types, the alignment operand is always the last one.
9349 Ops.push_back(DAG.getConstant(Alignment, dl, MVT::i32));
9351 // If this is a non-standard-aligned STORE, the penultimate operand is the
9352 // stored value. Bitcast it to the aligned type.
9353 if (AlignedVecTy != VecTy && N->getOpcode() == ISD::STORE) {
9354 SDValue &StVal = Ops[Ops.size()-2];
9355 StVal = DAG.getNode(ISD::BITCAST, dl, AlignedVecTy, StVal);
9358 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, dl, SDTys,
9360 MemN->getMemOperand());
9363 SmallVector<SDValue, 5> NewResults;
9364 for (unsigned i = 0; i < NumResultVecs; ++i)
9365 NewResults.push_back(SDValue(UpdN.getNode(), i));
9367 // If this is an non-standard-aligned LOAD, the first result is the loaded
9368 // value. Bitcast it to the expected result type.
9369 if (AlignedVecTy != VecTy && N->getOpcode() == ISD::LOAD) {
9370 SDValue &LdVal = NewResults[0];
9371 LdVal = DAG.getNode(ISD::BITCAST, dl, VecTy, LdVal);
9374 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs+1)); // chain
9375 DCI.CombineTo(N, NewResults);
9376 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
9383 static SDValue PerformVLDCombine(SDNode *N,
9384 TargetLowering::DAGCombinerInfo &DCI) {
9385 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
9388 return CombineBaseUpdate(N, DCI);
9391 /// CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a
9392 /// vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic
9393 /// are also VDUPLANEs. If so, combine them to a vldN-dup operation and
9395 static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
9396 SelectionDAG &DAG = DCI.DAG;
9397 EVT VT = N->getValueType(0);
9398 // vldN-dup instructions only support 64-bit vectors for N > 1.
9399 if (!VT.is64BitVector())
9402 // Check if the VDUPLANE operand is a vldN-dup intrinsic.
9403 SDNode *VLD = N->getOperand(0).getNode();
9404 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN)
9406 unsigned NumVecs = 0;
9407 unsigned NewOpc = 0;
9408 unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue();
9409 if (IntNo == Intrinsic::arm_neon_vld2lane) {
9411 NewOpc = ARMISD::VLD2DUP;
9412 } else if (IntNo == Intrinsic::arm_neon_vld3lane) {
9414 NewOpc = ARMISD::VLD3DUP;
9415 } else if (IntNo == Intrinsic::arm_neon_vld4lane) {
9417 NewOpc = ARMISD::VLD4DUP;
9422 // First check that all the vldN-lane uses are VDUPLANEs and that the lane
9423 // numbers match the load.
9424 unsigned VLDLaneNo =
9425 cast<ConstantSDNode>(VLD->getOperand(NumVecs+3))->getZExtValue();
9426 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
9428 // Ignore uses of the chain result.
9429 if (UI.getUse().getResNo() == NumVecs)
9432 if (User->getOpcode() != ARMISD::VDUPLANE ||
9433 VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue())
9437 // Create the vldN-dup node.
9440 for (n = 0; n < NumVecs; ++n)
9442 Tys[n] = MVT::Other;
9443 SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumVecs+1));
9444 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) };
9445 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD);
9446 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, SDLoc(VLD), SDTys,
9447 Ops, VLDMemInt->getMemoryVT(),
9448 VLDMemInt->getMemOperand());
9451 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
9453 unsigned ResNo = UI.getUse().getResNo();
9454 // Ignore uses of the chain result.
9455 if (ResNo == NumVecs)
9458 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo));
9461 // Now the vldN-lane intrinsic is dead except for its chain result.
9462 // Update uses of the chain.
9463 std::vector<SDValue> VLDDupResults;
9464 for (unsigned n = 0; n < NumVecs; ++n)
9465 VLDDupResults.push_back(SDValue(VLDDup.getNode(), n));
9466 VLDDupResults.push_back(SDValue(VLDDup.getNode(), NumVecs));
9467 DCI.CombineTo(VLD, VLDDupResults);
9472 /// PerformVDUPLANECombine - Target-specific dag combine xforms for
9473 /// ARMISD::VDUPLANE.
9474 static SDValue PerformVDUPLANECombine(SDNode *N,
9475 TargetLowering::DAGCombinerInfo &DCI) {
9476 SDValue Op = N->getOperand(0);
9478 // If the source is a vldN-lane (N > 1) intrinsic, and all the other uses
9479 // of that intrinsic are also VDUPLANEs, combine them to a vldN-dup operation.
9480 if (CombineVLDDUP(N, DCI))
9481 return SDValue(N, 0);
9483 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
9484 // redundant. Ignore bit_converts for now; element sizes are checked below.
9485 while (Op.getOpcode() == ISD::BITCAST)
9486 Op = Op.getOperand(0);
9487 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
9490 // Make sure the VMOV element size is not bigger than the VDUPLANE elements.
9491 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits();
9492 // The canonical VMOV for a zero vector uses a 32-bit element size.
9493 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9495 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
9497 EVT VT = N->getValueType(0);
9498 if (EltSize > VT.getVectorElementType().getSizeInBits())
9501 return DCI.DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
9504 static SDValue PerformLOADCombine(SDNode *N,
9505 TargetLowering::DAGCombinerInfo &DCI) {
9506 EVT VT = N->getValueType(0);
9508 // If this is a legal vector load, try to combine it into a VLD1_UPD.
9509 if (ISD::isNormalLoad(N) && VT.isVector() &&
9510 DCI.DAG.getTargetLoweringInfo().isTypeLegal(VT))
9511 return CombineBaseUpdate(N, DCI);
9516 /// PerformSTORECombine - Target-specific dag combine xforms for
9518 static SDValue PerformSTORECombine(SDNode *N,
9519 TargetLowering::DAGCombinerInfo &DCI) {
9520 StoreSDNode *St = cast<StoreSDNode>(N);
9521 if (St->isVolatile())
9524 // Optimize trunc store (of multiple scalars) to shuffle and store. First,
9525 // pack all of the elements in one place. Next, store to memory in fewer
9527 SDValue StVal = St->getValue();
9528 EVT VT = StVal.getValueType();
9529 if (St->isTruncatingStore() && VT.isVector()) {
9530 SelectionDAG &DAG = DCI.DAG;
9531 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9532 EVT StVT = St->getMemoryVT();
9533 unsigned NumElems = VT.getVectorNumElements();
9534 assert(StVT != VT && "Cannot truncate to the same type");
9535 unsigned FromEltSz = VT.getVectorElementType().getSizeInBits();
9536 unsigned ToEltSz = StVT.getVectorElementType().getSizeInBits();
9538 // From, To sizes and ElemCount must be pow of two
9539 if (!isPowerOf2_32(NumElems * FromEltSz * ToEltSz)) return SDValue();
9541 // We are going to use the original vector elt for storing.
9542 // Accumulated smaller vector elements must be a multiple of the store size.
9543 if (0 != (NumElems * FromEltSz) % ToEltSz) return SDValue();
9545 unsigned SizeRatio = FromEltSz / ToEltSz;
9546 assert(SizeRatio * NumElems * ToEltSz == VT.getSizeInBits());
9548 // Create a type on which we perform the shuffle.
9549 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), StVT.getScalarType(),
9550 NumElems*SizeRatio);
9551 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
9554 SDValue WideVec = DAG.getNode(ISD::BITCAST, DL, WideVecVT, StVal);
9555 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
9556 for (unsigned i = 0; i < NumElems; ++i)
9557 ShuffleVec[i] = DAG.getDataLayout().isBigEndian()
9558 ? (i + 1) * SizeRatio - 1
9561 // Can't shuffle using an illegal type.
9562 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
9564 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, DL, WideVec,
9565 DAG.getUNDEF(WideVec.getValueType()),
9567 // At this point all of the data is stored at the bottom of the
9568 // register. We now need to save it to mem.
9570 // Find the largest store unit
9571 MVT StoreType = MVT::i8;
9572 for (MVT Tp : MVT::integer_valuetypes()) {
9573 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToEltSz)
9576 // Didn't find a legal store type.
9577 if (!TLI.isTypeLegal(StoreType))
9580 // Bitcast the original vector into a vector of store-size units
9581 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
9582 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
9583 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
9584 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, DL, StoreVecVT, Shuff);
9585 SmallVector<SDValue, 8> Chains;
9586 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits() / 8, DL,
9587 TLI.getPointerTy(DAG.getDataLayout()));
9588 SDValue BasePtr = St->getBasePtr();
9590 // Perform one or more big stores into memory.
9591 unsigned E = (ToEltSz*NumElems)/StoreType.getSizeInBits();
9592 for (unsigned I = 0; I < E; I++) {
9593 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
9594 StoreType, ShuffWide,
9595 DAG.getIntPtrConstant(I, DL));
9596 SDValue Ch = DAG.getStore(St->getChain(), DL, SubVec, BasePtr,
9597 St->getPointerInfo(), St->isVolatile(),
9598 St->isNonTemporal(), St->getAlignment());
9599 BasePtr = DAG.getNode(ISD::ADD, DL, BasePtr.getValueType(), BasePtr,
9601 Chains.push_back(Ch);
9603 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
9606 if (!ISD::isNormalStore(St))
9609 // Split a store of a VMOVDRR into two integer stores to avoid mixing NEON and
9610 // ARM stores of arguments in the same cache line.
9611 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR &&
9612 StVal.getNode()->hasOneUse()) {
9613 SelectionDAG &DAG = DCI.DAG;
9614 bool isBigEndian = DAG.getDataLayout().isBigEndian();
9616 SDValue BasePtr = St->getBasePtr();
9617 SDValue NewST1 = DAG.getStore(St->getChain(), DL,
9618 StVal.getNode()->getOperand(isBigEndian ? 1 : 0 ),
9619 BasePtr, St->getPointerInfo(), St->isVolatile(),
9620 St->isNonTemporal(), St->getAlignment());
9622 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
9623 DAG.getConstant(4, DL, MVT::i32));
9624 return DAG.getStore(NewST1.getValue(0), DL,
9625 StVal.getNode()->getOperand(isBigEndian ? 0 : 1),
9626 OffsetPtr, St->getPointerInfo(), St->isVolatile(),
9627 St->isNonTemporal(),
9628 std::min(4U, St->getAlignment() / 2));
9631 if (StVal.getValueType() == MVT::i64 &&
9632 StVal.getNode()->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
9634 // Bitcast an i64 store extracted from a vector to f64.
9635 // Otherwise, the i64 value will be legalized to a pair of i32 values.
9636 SelectionDAG &DAG = DCI.DAG;
9638 SDValue IntVec = StVal.getOperand(0);
9639 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
9640 IntVec.getValueType().getVectorNumElements());
9641 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec);
9642 SDValue ExtElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
9643 Vec, StVal.getOperand(1));
9645 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt);
9646 // Make the DAGCombiner fold the bitcasts.
9647 DCI.AddToWorklist(Vec.getNode());
9648 DCI.AddToWorklist(ExtElt.getNode());
9649 DCI.AddToWorklist(V.getNode());
9650 return DAG.getStore(St->getChain(), dl, V, St->getBasePtr(),
9651 St->getPointerInfo(), St->isVolatile(),
9652 St->isNonTemporal(), St->getAlignment(),
9656 // If this is a legal vector store, try to combine it into a VST1_UPD.
9657 if (ISD::isNormalStore(N) && VT.isVector() &&
9658 DCI.DAG.getTargetLoweringInfo().isTypeLegal(VT))
9659 return CombineBaseUpdate(N, DCI);
9664 // isConstVecPow2 - Return true if each vector element is a power of 2, all
9665 // elements are the same constant, C, and Log2(C) ranges from 1 to 32.
9666 static bool isConstVecPow2(SDValue ConstVec, bool isSigned, uint64_t &C)
9670 for (unsigned I = 0, E = ConstVec.getValueType().getVectorNumElements();
9672 ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(ConstVec.getOperand(I));
9677 APFloat APF = C->getValueAPF();
9678 if (APF.convertToInteger(&cN, 64, isSigned, APFloat::rmTowardZero, &isExact)
9679 != APFloat::opOK || !isExact)
9682 c0 = (I == 0) ? cN : c0;
9683 if (!isPowerOf2_64(cN) || c0 != cN || Log2_64(c0) < 1 || Log2_64(c0) > 32)
9690 /// PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD)
9691 /// can replace combinations of VMUL and VCVT (floating-point to integer)
9692 /// when the VMUL has a constant operand that is a power of 2.
9694 /// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
9695 /// vmul.f32 d16, d17, d16
9696 /// vcvt.s32.f32 d16, d16
9698 /// vcvt.s32.f32 d16, d16, #3
9699 static SDValue PerformVCVTCombine(SDNode *N,
9700 TargetLowering::DAGCombinerInfo &DCI,
9701 const ARMSubtarget *Subtarget) {
9702 SelectionDAG &DAG = DCI.DAG;
9703 SDValue Op = N->getOperand(0);
9705 if (!Subtarget->hasNEON() || !Op.getValueType().isVector() ||
9706 Op.getOpcode() != ISD::FMUL)
9710 SDValue N0 = Op->getOperand(0);
9711 SDValue ConstVec = Op->getOperand(1);
9712 bool isSigned = N->getOpcode() == ISD::FP_TO_SINT;
9714 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
9715 !isConstVecPow2(ConstVec, isSigned, C))
9718 MVT FloatTy = Op.getSimpleValueType().getVectorElementType();
9719 MVT IntTy = N->getSimpleValueType(0).getVectorElementType();
9720 unsigned NumLanes = Op.getValueType().getVectorNumElements();
9721 if (FloatTy.getSizeInBits() != 32 || IntTy.getSizeInBits() > 32 ||
9723 // These instructions only exist converting from f32 to i32. We can handle
9724 // smaller integers by generating an extra truncate, but larger ones would
9725 // be lossy. We also can't handle more then 4 lanes, since these intructions
9726 // only support v2i32/v4i32 types.
9731 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfp2fxs :
9732 Intrinsic::arm_neon_vcvtfp2fxu;
9733 SDValue FixConv = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl,
9734 NumLanes == 2 ? MVT::v2i32 : MVT::v4i32,
9735 DAG.getConstant(IntrinsicOpcode, dl, MVT::i32),
9737 DAG.getConstant(Log2_64(C), dl, MVT::i32));
9739 if (IntTy.getSizeInBits() < FloatTy.getSizeInBits())
9740 FixConv = DAG.getNode(ISD::TRUNCATE, dl, N->getValueType(0), FixConv);
9745 /// PerformVDIVCombine - VCVT (fixed-point to floating-point, Advanced SIMD)
9746 /// can replace combinations of VCVT (integer to floating-point) and VDIV
9747 /// when the VDIV has a constant operand that is a power of 2.
9749 /// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
9750 /// vcvt.f32.s32 d16, d16
9751 /// vdiv.f32 d16, d17, d16
9753 /// vcvt.f32.s32 d16, d16, #3
9754 static SDValue PerformVDIVCombine(SDNode *N,
9755 TargetLowering::DAGCombinerInfo &DCI,
9756 const ARMSubtarget *Subtarget) {
9757 SelectionDAG &DAG = DCI.DAG;
9758 SDValue Op = N->getOperand(0);
9759 unsigned OpOpcode = Op.getNode()->getOpcode();
9761 if (!Subtarget->hasNEON() || !N->getValueType(0).isVector() ||
9762 (OpOpcode != ISD::SINT_TO_FP && OpOpcode != ISD::UINT_TO_FP))
9766 SDValue ConstVec = N->getOperand(1);
9767 bool isSigned = OpOpcode == ISD::SINT_TO_FP;
9769 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
9770 !isConstVecPow2(ConstVec, isSigned, C))
9773 MVT FloatTy = N->getSimpleValueType(0).getVectorElementType();
9774 MVT IntTy = Op.getOperand(0).getSimpleValueType().getVectorElementType();
9775 if (FloatTy.getSizeInBits() != 32 || IntTy.getSizeInBits() > 32) {
9776 // These instructions only exist converting from i32 to f32. We can handle
9777 // smaller integers by generating an extra extend, but larger ones would
9783 SDValue ConvInput = Op.getOperand(0);
9784 unsigned NumLanes = Op.getValueType().getVectorNumElements();
9785 if (IntTy.getSizeInBits() < FloatTy.getSizeInBits())
9786 ConvInput = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
9787 dl, NumLanes == 2 ? MVT::v2i32 : MVT::v4i32,
9790 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfxs2fp :
9791 Intrinsic::arm_neon_vcvtfxu2fp;
9792 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl,
9794 DAG.getConstant(IntrinsicOpcode, dl, MVT::i32),
9795 ConvInput, DAG.getConstant(Log2_64(C), dl, MVT::i32));
9798 /// Getvshiftimm - Check if this is a valid build_vector for the immediate
9799 /// operand of a vector shift operation, where all the elements of the
9800 /// build_vector must have the same constant integer value.
9801 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
9802 // Ignore bit_converts.
9803 while (Op.getOpcode() == ISD::BITCAST)
9804 Op = Op.getOperand(0);
9805 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
9806 APInt SplatBits, SplatUndef;
9807 unsigned SplatBitSize;
9809 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
9810 HasAnyUndefs, ElementBits) ||
9811 SplatBitSize > ElementBits)
9813 Cnt = SplatBits.getSExtValue();
9817 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
9818 /// operand of a vector shift left operation. That value must be in the range:
9819 /// 0 <= Value < ElementBits for a left shift; or
9820 /// 0 <= Value <= ElementBits for a long left shift.
9821 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
9822 assert(VT.isVector() && "vector shift count is not a vector type");
9823 int64_t ElementBits = VT.getVectorElementType().getSizeInBits();
9824 if (! getVShiftImm(Op, ElementBits, Cnt))
9826 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
9829 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
9830 /// operand of a vector shift right operation. For a shift opcode, the value
9831 /// is positive, but for an intrinsic the value count must be negative. The
9832 /// absolute value must be in the range:
9833 /// 1 <= |Value| <= ElementBits for a right shift; or
9834 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
9835 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
9837 assert(VT.isVector() && "vector shift count is not a vector type");
9838 int64_t ElementBits = VT.getVectorElementType().getSizeInBits();
9839 if (! getVShiftImm(Op, ElementBits, Cnt))
9842 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
9843 if (Cnt >= -(isNarrow ? ElementBits/2 : ElementBits) && Cnt <= -1) {
9850 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
9851 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
9852 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
9855 // Don't do anything for most intrinsics.
9858 case Intrinsic::arm_neon_vabds:
9859 if (!N->getValueType(0).isInteger())
9861 return DAG.getNode(ISD::SABSDIFF, SDLoc(N), N->getValueType(0),
9862 N->getOperand(1), N->getOperand(2));
9863 case Intrinsic::arm_neon_vabdu:
9864 return DAG.getNode(ISD::UABSDIFF, SDLoc(N), N->getValueType(0),
9865 N->getOperand(1), N->getOperand(2));
9867 // Vector shifts: check for immediate versions and lower them.
9868 // Note: This is done during DAG combining instead of DAG legalizing because
9869 // the build_vectors for 64-bit vector element shift counts are generally
9870 // not legal, and it is hard to see their values after they get legalized to
9871 // loads from a constant pool.
9872 case Intrinsic::arm_neon_vshifts:
9873 case Intrinsic::arm_neon_vshiftu:
9874 case Intrinsic::arm_neon_vrshifts:
9875 case Intrinsic::arm_neon_vrshiftu:
9876 case Intrinsic::arm_neon_vrshiftn:
9877 case Intrinsic::arm_neon_vqshifts:
9878 case Intrinsic::arm_neon_vqshiftu:
9879 case Intrinsic::arm_neon_vqshiftsu:
9880 case Intrinsic::arm_neon_vqshiftns:
9881 case Intrinsic::arm_neon_vqshiftnu:
9882 case Intrinsic::arm_neon_vqshiftnsu:
9883 case Intrinsic::arm_neon_vqrshiftns:
9884 case Intrinsic::arm_neon_vqrshiftnu:
9885 case Intrinsic::arm_neon_vqrshiftnsu: {
9886 EVT VT = N->getOperand(1).getValueType();
9888 unsigned VShiftOpc = 0;
9891 case Intrinsic::arm_neon_vshifts:
9892 case Intrinsic::arm_neon_vshiftu:
9893 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
9894 VShiftOpc = ARMISD::VSHL;
9897 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
9898 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
9899 ARMISD::VSHRs : ARMISD::VSHRu);
9904 case Intrinsic::arm_neon_vrshifts:
9905 case Intrinsic::arm_neon_vrshiftu:
9906 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
9910 case Intrinsic::arm_neon_vqshifts:
9911 case Intrinsic::arm_neon_vqshiftu:
9912 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
9916 case Intrinsic::arm_neon_vqshiftsu:
9917 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
9919 llvm_unreachable("invalid shift count for vqshlu intrinsic");
9921 case Intrinsic::arm_neon_vrshiftn:
9922 case Intrinsic::arm_neon_vqshiftns:
9923 case Intrinsic::arm_neon_vqshiftnu:
9924 case Intrinsic::arm_neon_vqshiftnsu:
9925 case Intrinsic::arm_neon_vqrshiftns:
9926 case Intrinsic::arm_neon_vqrshiftnu:
9927 case Intrinsic::arm_neon_vqrshiftnsu:
9928 // Narrowing shifts require an immediate right shift.
9929 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
9931 llvm_unreachable("invalid shift count for narrowing vector shift "
9935 llvm_unreachable("unhandled vector shift");
9939 case Intrinsic::arm_neon_vshifts:
9940 case Intrinsic::arm_neon_vshiftu:
9941 // Opcode already set above.
9943 case Intrinsic::arm_neon_vrshifts:
9944 VShiftOpc = ARMISD::VRSHRs; break;
9945 case Intrinsic::arm_neon_vrshiftu:
9946 VShiftOpc = ARMISD::VRSHRu; break;
9947 case Intrinsic::arm_neon_vrshiftn:
9948 VShiftOpc = ARMISD::VRSHRN; break;
9949 case Intrinsic::arm_neon_vqshifts:
9950 VShiftOpc = ARMISD::VQSHLs; break;
9951 case Intrinsic::arm_neon_vqshiftu:
9952 VShiftOpc = ARMISD::VQSHLu; break;
9953 case Intrinsic::arm_neon_vqshiftsu:
9954 VShiftOpc = ARMISD::VQSHLsu; break;
9955 case Intrinsic::arm_neon_vqshiftns:
9956 VShiftOpc = ARMISD::VQSHRNs; break;
9957 case Intrinsic::arm_neon_vqshiftnu:
9958 VShiftOpc = ARMISD::VQSHRNu; break;
9959 case Intrinsic::arm_neon_vqshiftnsu:
9960 VShiftOpc = ARMISD::VQSHRNsu; break;
9961 case Intrinsic::arm_neon_vqrshiftns:
9962 VShiftOpc = ARMISD::VQRSHRNs; break;
9963 case Intrinsic::arm_neon_vqrshiftnu:
9964 VShiftOpc = ARMISD::VQRSHRNu; break;
9965 case Intrinsic::arm_neon_vqrshiftnsu:
9966 VShiftOpc = ARMISD::VQRSHRNsu; break;
9970 return DAG.getNode(VShiftOpc, dl, N->getValueType(0),
9971 N->getOperand(1), DAG.getConstant(Cnt, dl, MVT::i32));
9974 case Intrinsic::arm_neon_vshiftins: {
9975 EVT VT = N->getOperand(1).getValueType();
9977 unsigned VShiftOpc = 0;
9979 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
9980 VShiftOpc = ARMISD::VSLI;
9981 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
9982 VShiftOpc = ARMISD::VSRI;
9984 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
9988 return DAG.getNode(VShiftOpc, dl, N->getValueType(0),
9989 N->getOperand(1), N->getOperand(2),
9990 DAG.getConstant(Cnt, dl, MVT::i32));
9993 case Intrinsic::arm_neon_vqrshifts:
9994 case Intrinsic::arm_neon_vqrshiftu:
9995 // No immediate versions of these to check for.
10002 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
10003 /// lowers them. As with the vector shift intrinsics, this is done during DAG
10004 /// combining instead of DAG legalizing because the build_vectors for 64-bit
10005 /// vector element shift counts are generally not legal, and it is hard to see
10006 /// their values after they get legalized to loads from a constant pool.
10007 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
10008 const ARMSubtarget *ST) {
10009 EVT VT = N->getValueType(0);
10010 if (N->getOpcode() == ISD::SRL && VT == MVT::i32 && ST->hasV6Ops()) {
10011 // Canonicalize (srl (bswap x), 16) to (rotr (bswap x), 16) if the high
10012 // 16-bits of x is zero. This optimizes rev + lsr 16 to rev16.
10013 SDValue N1 = N->getOperand(1);
10014 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
10015 SDValue N0 = N->getOperand(0);
10016 if (C->getZExtValue() == 16 && N0.getOpcode() == ISD::BSWAP &&
10017 DAG.MaskedValueIsZero(N0.getOperand(0),
10018 APInt::getHighBitsSet(32, 16)))
10019 return DAG.getNode(ISD::ROTR, SDLoc(N), VT, N0, N1);
10023 // Nothing to be done for scalar shifts.
10024 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10025 if (!VT.isVector() || !TLI.isTypeLegal(VT))
10028 assert(ST->hasNEON() && "unexpected vector shift");
10031 switch (N->getOpcode()) {
10032 default: llvm_unreachable("unexpected shift opcode");
10035 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt)) {
10037 return DAG.getNode(ARMISD::VSHL, dl, VT, N->getOperand(0),
10038 DAG.getConstant(Cnt, dl, MVT::i32));
10044 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
10045 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
10046 ARMISD::VSHRs : ARMISD::VSHRu);
10048 return DAG.getNode(VShiftOpc, dl, VT, N->getOperand(0),
10049 DAG.getConstant(Cnt, dl, MVT::i32));
10055 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
10056 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
10057 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
10058 const ARMSubtarget *ST) {
10059 SDValue N0 = N->getOperand(0);
10061 // Check for sign- and zero-extensions of vector extract operations of 8-
10062 // and 16-bit vector elements. NEON supports these directly. They are
10063 // handled during DAG combining because type legalization will promote them
10064 // to 32-bit types and it is messy to recognize the operations after that.
10065 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
10066 SDValue Vec = N0.getOperand(0);
10067 SDValue Lane = N0.getOperand(1);
10068 EVT VT = N->getValueType(0);
10069 EVT EltVT = N0.getValueType();
10070 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10072 if (VT == MVT::i32 &&
10073 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
10074 TLI.isTypeLegal(Vec.getValueType()) &&
10075 isa<ConstantSDNode>(Lane)) {
10078 switch (N->getOpcode()) {
10079 default: llvm_unreachable("unexpected opcode");
10080 case ISD::SIGN_EXTEND:
10081 Opc = ARMISD::VGETLANEs;
10083 case ISD::ZERO_EXTEND:
10084 case ISD::ANY_EXTEND:
10085 Opc = ARMISD::VGETLANEu;
10088 return DAG.getNode(Opc, SDLoc(N), VT, Vec, Lane);
10095 /// PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV.
10097 ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const {
10098 SDValue Cmp = N->getOperand(4);
10099 if (Cmp.getOpcode() != ARMISD::CMPZ)
10100 // Only looking at EQ and NE cases.
10103 EVT VT = N->getValueType(0);
10105 SDValue LHS = Cmp.getOperand(0);
10106 SDValue RHS = Cmp.getOperand(1);
10107 SDValue FalseVal = N->getOperand(0);
10108 SDValue TrueVal = N->getOperand(1);
10109 SDValue ARMcc = N->getOperand(2);
10110 ARMCC::CondCodes CC =
10111 (ARMCC::CondCodes)cast<ConstantSDNode>(ARMcc)->getZExtValue();
10129 /// FIXME: Turn this into a target neutral optimization?
10131 if (CC == ARMCC::NE && FalseVal == RHS && FalseVal != LHS) {
10132 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, TrueVal, ARMcc,
10133 N->getOperand(3), Cmp);
10134 } else if (CC == ARMCC::EQ && TrueVal == RHS) {
10136 SDValue NewCmp = getARMCmp(LHS, RHS, ISD::SETNE, ARMcc, DAG, dl);
10137 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, FalseVal, ARMcc,
10138 N->getOperand(3), NewCmp);
10141 if (Res.getNode()) {
10142 APInt KnownZero, KnownOne;
10143 DAG.computeKnownBits(SDValue(N,0), KnownZero, KnownOne);
10144 // Capture demanded bits information that would be otherwise lost.
10145 if (KnownZero == 0xfffffffe)
10146 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
10147 DAG.getValueType(MVT::i1));
10148 else if (KnownZero == 0xffffff00)
10149 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
10150 DAG.getValueType(MVT::i8));
10151 else if (KnownZero == 0xffff0000)
10152 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
10153 DAG.getValueType(MVT::i16));
10159 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
10160 DAGCombinerInfo &DCI) const {
10161 switch (N->getOpcode()) {
10163 case ISD::ADDC: return PerformADDCCombine(N, DCI, Subtarget);
10164 case ISD::ADD: return PerformADDCombine(N, DCI, Subtarget);
10165 case ISD::SUB: return PerformSUBCombine(N, DCI);
10166 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
10167 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
10168 case ISD::XOR: return PerformXORCombine(N, DCI, Subtarget);
10169 case ISD::AND: return PerformANDCombine(N, DCI, Subtarget);
10170 case ARMISD::BFI: return PerformBFICombine(N, DCI);
10171 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI, Subtarget);
10172 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
10173 case ISD::STORE: return PerformSTORECombine(N, DCI);
10174 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI, Subtarget);
10175 case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI);
10176 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
10177 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
10178 case ISD::FP_TO_SINT:
10179 case ISD::FP_TO_UINT: return PerformVCVTCombine(N, DCI, Subtarget);
10180 case ISD::FDIV: return PerformVDIVCombine(N, DCI, Subtarget);
10181 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
10184 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
10185 case ISD::SIGN_EXTEND:
10186 case ISD::ZERO_EXTEND:
10187 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
10188 case ARMISD::CMOV: return PerformCMOVCombine(N, DCI.DAG);
10189 case ISD::LOAD: return PerformLOADCombine(N, DCI);
10190 case ARMISD::VLD2DUP:
10191 case ARMISD::VLD3DUP:
10192 case ARMISD::VLD4DUP:
10193 return PerformVLDCombine(N, DCI);
10194 case ARMISD::BUILD_VECTOR:
10195 return PerformARMBUILD_VECTORCombine(N, DCI);
10196 case ISD::INTRINSIC_VOID:
10197 case ISD::INTRINSIC_W_CHAIN:
10198 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
10199 case Intrinsic::arm_neon_vld1:
10200 case Intrinsic::arm_neon_vld2:
10201 case Intrinsic::arm_neon_vld3:
10202 case Intrinsic::arm_neon_vld4:
10203 case Intrinsic::arm_neon_vld2lane:
10204 case Intrinsic::arm_neon_vld3lane:
10205 case Intrinsic::arm_neon_vld4lane:
10206 case Intrinsic::arm_neon_vst1:
10207 case Intrinsic::arm_neon_vst2:
10208 case Intrinsic::arm_neon_vst3:
10209 case Intrinsic::arm_neon_vst4:
10210 case Intrinsic::arm_neon_vst2lane:
10211 case Intrinsic::arm_neon_vst3lane:
10212 case Intrinsic::arm_neon_vst4lane:
10213 return PerformVLDCombine(N, DCI);
10221 bool ARMTargetLowering::isDesirableToTransformToIntegerOp(unsigned Opc,
10223 return (VT == MVT::f32) && (Opc == ISD::LOAD || Opc == ISD::STORE);
10226 bool ARMTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
10229 bool *Fast) const {
10230 // The AllowsUnaliged flag models the SCTLR.A setting in ARM cpus
10231 bool AllowsUnaligned = Subtarget->allowsUnalignedMem();
10233 switch (VT.getSimpleVT().SimpleTy) {
10239 // Unaligned access can use (for example) LRDB, LRDH, LDR
10240 if (AllowsUnaligned) {
10242 *Fast = Subtarget->hasV7Ops();
10249 // For any little-endian targets with neon, we can support unaligned ld/st
10250 // of D and Q (e.g. {D0,D1}) registers by using vld1.i8/vst1.i8.
10251 // A big-endian target may also explicitly support unaligned accesses
10252 if (Subtarget->hasNEON() && (AllowsUnaligned || Subtarget->isLittle())) {
10262 static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign,
10263 unsigned AlignCheck) {
10264 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) &&
10265 (DstAlign == 0 || DstAlign % AlignCheck == 0));
10268 EVT ARMTargetLowering::getOptimalMemOpType(uint64_t Size,
10269 unsigned DstAlign, unsigned SrcAlign,
10270 bool IsMemset, bool ZeroMemset,
10272 MachineFunction &MF) const {
10273 const Function *F = MF.getFunction();
10275 // See if we can use NEON instructions for this...
10276 if ((!IsMemset || ZeroMemset) && Subtarget->hasNEON() &&
10277 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
10280 (memOpAlign(SrcAlign, DstAlign, 16) ||
10281 (allowsMisalignedMemoryAccesses(MVT::v2f64, 0, 1, &Fast) && Fast))) {
10283 } else if (Size >= 8 &&
10284 (memOpAlign(SrcAlign, DstAlign, 8) ||
10285 (allowsMisalignedMemoryAccesses(MVT::f64, 0, 1, &Fast) &&
10291 // Lowering to i32/i16 if the size permits.
10294 else if (Size >= 2)
10297 // Let the target-independent logic figure it out.
10301 bool ARMTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
10302 if (Val.getOpcode() != ISD::LOAD)
10305 EVT VT1 = Val.getValueType();
10306 if (!VT1.isSimple() || !VT1.isInteger() ||
10307 !VT2.isSimple() || !VT2.isInteger())
10310 switch (VT1.getSimpleVT().SimpleTy) {
10315 // 8-bit and 16-bit loads implicitly zero-extend to 32-bits.
10322 bool ARMTargetLowering::isVectorLoadExtDesirable(SDValue ExtVal) const {
10323 EVT VT = ExtVal.getValueType();
10325 if (!isTypeLegal(VT))
10328 // Don't create a loadext if we can fold the extension into a wide/long
10330 // If there's more than one user instruction, the loadext is desirable no
10331 // matter what. There can be two uses by the same instruction.
10332 if (ExtVal->use_empty() ||
10333 !ExtVal->use_begin()->isOnlyUserOf(ExtVal.getNode()))
10336 SDNode *U = *ExtVal->use_begin();
10337 if ((U->getOpcode() == ISD::ADD || U->getOpcode() == ISD::SUB ||
10338 U->getOpcode() == ISD::SHL || U->getOpcode() == ARMISD::VSHL))
10344 bool ARMTargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
10345 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
10348 if (!isTypeLegal(EVT::getEVT(Ty1)))
10351 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
10353 // Assuming the caller doesn't have a zeroext or signext return parameter,
10354 // truncation all the way down to i1 is valid.
10359 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
10363 unsigned Scale = 1;
10364 switch (VT.getSimpleVT().SimpleTy) {
10365 default: return false;
10380 if ((V & (Scale - 1)) != 0)
10383 return V == (V & ((1LL << 5) - 1));
10386 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
10387 const ARMSubtarget *Subtarget) {
10388 bool isNeg = false;
10394 switch (VT.getSimpleVT().SimpleTy) {
10395 default: return false;
10400 // + imm12 or - imm8
10402 return V == (V & ((1LL << 8) - 1));
10403 return V == (V & ((1LL << 12) - 1));
10406 // Same as ARM mode. FIXME: NEON?
10407 if (!Subtarget->hasVFP2())
10412 return V == (V & ((1LL << 8) - 1));
10416 /// isLegalAddressImmediate - Return true if the integer value can be used
10417 /// as the offset of the target addressing mode for load / store of the
10419 static bool isLegalAddressImmediate(int64_t V, EVT VT,
10420 const ARMSubtarget *Subtarget) {
10424 if (!VT.isSimple())
10427 if (Subtarget->isThumb1Only())
10428 return isLegalT1AddressImmediate(V, VT);
10429 else if (Subtarget->isThumb2())
10430 return isLegalT2AddressImmediate(V, VT, Subtarget);
10435 switch (VT.getSimpleVT().SimpleTy) {
10436 default: return false;
10441 return V == (V & ((1LL << 12) - 1));
10444 return V == (V & ((1LL << 8) - 1));
10447 if (!Subtarget->hasVFP2()) // FIXME: NEON?
10452 return V == (V & ((1LL << 8) - 1));
10456 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
10458 int Scale = AM.Scale;
10462 switch (VT.getSimpleVT().SimpleTy) {
10463 default: return false;
10471 Scale = Scale & ~1;
10472 return Scale == 2 || Scale == 4 || Scale == 8;
10475 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
10479 // Note, we allow "void" uses (basically, uses that aren't loads or
10480 // stores), because arm allows folding a scale into many arithmetic
10481 // operations. This should be made more precise and revisited later.
10483 // Allow r << imm, but the imm has to be a multiple of two.
10484 if (Scale & 1) return false;
10485 return isPowerOf2_32(Scale);
10489 /// isLegalAddressingMode - Return true if the addressing mode represented
10490 /// by AM is legal for this target, for a load/store of the specified type.
10491 bool ARMTargetLowering::isLegalAddressingMode(const DataLayout &DL,
10492 const AddrMode &AM, Type *Ty,
10493 unsigned AS) const {
10494 EVT VT = getValueType(DL, Ty, true);
10495 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
10498 // Can never fold addr of global into load/store.
10502 switch (AM.Scale) {
10503 case 0: // no scale reg, must be "r+i" or "r", or "i".
10506 if (Subtarget->isThumb1Only())
10510 // ARM doesn't support any R+R*scale+imm addr modes.
10514 if (!VT.isSimple())
10517 if (Subtarget->isThumb2())
10518 return isLegalT2ScaledAddressingMode(AM, VT);
10520 int Scale = AM.Scale;
10521 switch (VT.getSimpleVT().SimpleTy) {
10522 default: return false;
10526 if (Scale < 0) Scale = -Scale;
10530 return isPowerOf2_32(Scale & ~1);
10534 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
10539 // Note, we allow "void" uses (basically, uses that aren't loads or
10540 // stores), because arm allows folding a scale into many arithmetic
10541 // operations. This should be made more precise and revisited later.
10543 // Allow r << imm, but the imm has to be a multiple of two.
10544 if (Scale & 1) return false;
10545 return isPowerOf2_32(Scale);
10551 /// isLegalICmpImmediate - Return true if the specified immediate is legal
10552 /// icmp immediate, that is the target has icmp instructions which can compare
10553 /// a register against the immediate without having to materialize the
10554 /// immediate into a register.
10555 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
10556 // Thumb2 and ARM modes can use cmn for negative immediates.
10557 if (!Subtarget->isThumb())
10558 return ARM_AM::getSOImmVal(std::abs(Imm)) != -1;
10559 if (Subtarget->isThumb2())
10560 return ARM_AM::getT2SOImmVal(std::abs(Imm)) != -1;
10561 // Thumb1 doesn't have cmn, and only 8-bit immediates.
10562 return Imm >= 0 && Imm <= 255;
10565 /// isLegalAddImmediate - Return true if the specified immediate is a legal add
10566 /// *or sub* immediate, that is the target has add or sub instructions which can
10567 /// add a register with the immediate without having to materialize the
10568 /// immediate into a register.
10569 bool ARMTargetLowering::isLegalAddImmediate(int64_t Imm) const {
10570 // Same encoding for add/sub, just flip the sign.
10571 int64_t AbsImm = std::abs(Imm);
10572 if (!Subtarget->isThumb())
10573 return ARM_AM::getSOImmVal(AbsImm) != -1;
10574 if (Subtarget->isThumb2())
10575 return ARM_AM::getT2SOImmVal(AbsImm) != -1;
10576 // Thumb1 only has 8-bit unsigned immediate.
10577 return AbsImm >= 0 && AbsImm <= 255;
10580 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
10581 bool isSEXTLoad, SDValue &Base,
10582 SDValue &Offset, bool &isInc,
10583 SelectionDAG &DAG) {
10584 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
10587 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
10588 // AddressingMode 3
10589 Base = Ptr->getOperand(0);
10590 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
10591 int RHSC = (int)RHS->getZExtValue();
10592 if (RHSC < 0 && RHSC > -256) {
10593 assert(Ptr->getOpcode() == ISD::ADD);
10595 Offset = DAG.getConstant(-RHSC, SDLoc(Ptr), RHS->getValueType(0));
10599 isInc = (Ptr->getOpcode() == ISD::ADD);
10600 Offset = Ptr->getOperand(1);
10602 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
10603 // AddressingMode 2
10604 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
10605 int RHSC = (int)RHS->getZExtValue();
10606 if (RHSC < 0 && RHSC > -0x1000) {
10607 assert(Ptr->getOpcode() == ISD::ADD);
10609 Offset = DAG.getConstant(-RHSC, SDLoc(Ptr), RHS->getValueType(0));
10610 Base = Ptr->getOperand(0);
10615 if (Ptr->getOpcode() == ISD::ADD) {
10617 ARM_AM::ShiftOpc ShOpcVal=
10618 ARM_AM::getShiftOpcForNode(Ptr->getOperand(0).getOpcode());
10619 if (ShOpcVal != ARM_AM::no_shift) {
10620 Base = Ptr->getOperand(1);
10621 Offset = Ptr->getOperand(0);
10623 Base = Ptr->getOperand(0);
10624 Offset = Ptr->getOperand(1);
10629 isInc = (Ptr->getOpcode() == ISD::ADD);
10630 Base = Ptr->getOperand(0);
10631 Offset = Ptr->getOperand(1);
10635 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
10639 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
10640 bool isSEXTLoad, SDValue &Base,
10641 SDValue &Offset, bool &isInc,
10642 SelectionDAG &DAG) {
10643 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
10646 Base = Ptr->getOperand(0);
10647 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
10648 int RHSC = (int)RHS->getZExtValue();
10649 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
10650 assert(Ptr->getOpcode() == ISD::ADD);
10652 Offset = DAG.getConstant(-RHSC, SDLoc(Ptr), RHS->getValueType(0));
10654 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
10655 isInc = Ptr->getOpcode() == ISD::ADD;
10656 Offset = DAG.getConstant(RHSC, SDLoc(Ptr), RHS->getValueType(0));
10664 /// getPreIndexedAddressParts - returns true by value, base pointer and
10665 /// offset pointer and addressing mode by reference if the node's address
10666 /// can be legally represented as pre-indexed load / store address.
10668 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
10670 ISD::MemIndexedMode &AM,
10671 SelectionDAG &DAG) const {
10672 if (Subtarget->isThumb1Only())
10677 bool isSEXTLoad = false;
10678 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
10679 Ptr = LD->getBasePtr();
10680 VT = LD->getMemoryVT();
10681 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
10682 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
10683 Ptr = ST->getBasePtr();
10684 VT = ST->getMemoryVT();
10689 bool isLegal = false;
10690 if (Subtarget->isThumb2())
10691 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
10692 Offset, isInc, DAG);
10694 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
10695 Offset, isInc, DAG);
10699 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
10703 /// getPostIndexedAddressParts - returns true by value, base pointer and
10704 /// offset pointer and addressing mode by reference if this node can be
10705 /// combined with a load / store to form a post-indexed load / store.
10706 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
10709 ISD::MemIndexedMode &AM,
10710 SelectionDAG &DAG) const {
10711 if (Subtarget->isThumb1Only())
10716 bool isSEXTLoad = false;
10717 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
10718 VT = LD->getMemoryVT();
10719 Ptr = LD->getBasePtr();
10720 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
10721 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
10722 VT = ST->getMemoryVT();
10723 Ptr = ST->getBasePtr();
10728 bool isLegal = false;
10729 if (Subtarget->isThumb2())
10730 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
10733 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
10739 // Swap base ptr and offset to catch more post-index load / store when
10740 // it's legal. In Thumb2 mode, offset must be an immediate.
10741 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
10742 !Subtarget->isThumb2())
10743 std::swap(Base, Offset);
10745 // Post-indexed load / store update the base pointer.
10750 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
10754 void ARMTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
10757 const SelectionDAG &DAG,
10758 unsigned Depth) const {
10759 unsigned BitWidth = KnownOne.getBitWidth();
10760 KnownZero = KnownOne = APInt(BitWidth, 0);
10761 switch (Op.getOpcode()) {
10767 // These nodes' second result is a boolean
10768 if (Op.getResNo() == 0)
10770 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
10772 case ARMISD::CMOV: {
10773 // Bits are known zero/one if known on the LHS and RHS.
10774 DAG.computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1);
10775 if (KnownZero == 0 && KnownOne == 0) return;
10777 APInt KnownZeroRHS, KnownOneRHS;
10778 DAG.computeKnownBits(Op.getOperand(1), KnownZeroRHS, KnownOneRHS, Depth+1);
10779 KnownZero &= KnownZeroRHS;
10780 KnownOne &= KnownOneRHS;
10783 case ISD::INTRINSIC_W_CHAIN: {
10784 ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
10785 Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
10788 case Intrinsic::arm_ldaex:
10789 case Intrinsic::arm_ldrex: {
10790 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();
10791 unsigned MemBits = VT.getScalarType().getSizeInBits();
10792 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
10800 //===----------------------------------------------------------------------===//
10801 // ARM Inline Assembly Support
10802 //===----------------------------------------------------------------------===//
10804 bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const {
10805 // Looking for "rev" which is V6+.
10806 if (!Subtarget->hasV6Ops())
10809 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
10810 std::string AsmStr = IA->getAsmString();
10811 SmallVector<StringRef, 4> AsmPieces;
10812 SplitString(AsmStr, AsmPieces, ";\n");
10814 switch (AsmPieces.size()) {
10815 default: return false;
10817 AsmStr = AsmPieces[0];
10819 SplitString(AsmStr, AsmPieces, " \t,");
10822 if (AsmPieces.size() == 3 &&
10823 AsmPieces[0] == "rev" && AsmPieces[1] == "$0" && AsmPieces[2] == "$1" &&
10824 IA->getConstraintString().compare(0, 4, "=l,l") == 0) {
10825 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
10826 if (Ty && Ty->getBitWidth() == 32)
10827 return IntrinsicLowering::LowerToByteSwap(CI);
10835 /// getConstraintType - Given a constraint letter, return the type of
10836 /// constraint it is for this target.
10837 ARMTargetLowering::ConstraintType
10838 ARMTargetLowering::getConstraintType(StringRef Constraint) const {
10839 if (Constraint.size() == 1) {
10840 switch (Constraint[0]) {
10842 case 'l': return C_RegisterClass;
10843 case 'w': return C_RegisterClass;
10844 case 'h': return C_RegisterClass;
10845 case 'x': return C_RegisterClass;
10846 case 't': return C_RegisterClass;
10847 case 'j': return C_Other; // Constant for movw.
10848 // An address with a single base register. Due to the way we
10849 // currently handle addresses it is the same as an 'r' memory constraint.
10850 case 'Q': return C_Memory;
10852 } else if (Constraint.size() == 2) {
10853 switch (Constraint[0]) {
10855 // All 'U+' constraints are addresses.
10856 case 'U': return C_Memory;
10859 return TargetLowering::getConstraintType(Constraint);
10862 /// Examine constraint type and operand type and determine a weight value.
10863 /// This object must already have been set up with the operand type
10864 /// and the current alternative constraint selected.
10865 TargetLowering::ConstraintWeight
10866 ARMTargetLowering::getSingleConstraintMatchWeight(
10867 AsmOperandInfo &info, const char *constraint) const {
10868 ConstraintWeight weight = CW_Invalid;
10869 Value *CallOperandVal = info.CallOperandVal;
10870 // If we don't have a value, we can't do a match,
10871 // but allow it at the lowest weight.
10872 if (!CallOperandVal)
10874 Type *type = CallOperandVal->getType();
10875 // Look at the constraint type.
10876 switch (*constraint) {
10878 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
10881 if (type->isIntegerTy()) {
10882 if (Subtarget->isThumb())
10883 weight = CW_SpecificReg;
10885 weight = CW_Register;
10889 if (type->isFloatingPointTy())
10890 weight = CW_Register;
10896 typedef std::pair<unsigned, const TargetRegisterClass*> RCPair;
10897 RCPair ARMTargetLowering::getRegForInlineAsmConstraint(
10898 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
10899 if (Constraint.size() == 1) {
10900 // GCC ARM Constraint Letters
10901 switch (Constraint[0]) {
10902 case 'l': // Low regs or general regs.
10903 if (Subtarget->isThumb())
10904 return RCPair(0U, &ARM::tGPRRegClass);
10905 return RCPair(0U, &ARM::GPRRegClass);
10906 case 'h': // High regs or no regs.
10907 if (Subtarget->isThumb())
10908 return RCPair(0U, &ARM::hGPRRegClass);
10911 if (Subtarget->isThumb1Only())
10912 return RCPair(0U, &ARM::tGPRRegClass);
10913 return RCPair(0U, &ARM::GPRRegClass);
10915 if (VT == MVT::Other)
10917 if (VT == MVT::f32)
10918 return RCPair(0U, &ARM::SPRRegClass);
10919 if (VT.getSizeInBits() == 64)
10920 return RCPair(0U, &ARM::DPRRegClass);
10921 if (VT.getSizeInBits() == 128)
10922 return RCPair(0U, &ARM::QPRRegClass);
10925 if (VT == MVT::Other)
10927 if (VT == MVT::f32)
10928 return RCPair(0U, &ARM::SPR_8RegClass);
10929 if (VT.getSizeInBits() == 64)
10930 return RCPair(0U, &ARM::DPR_8RegClass);
10931 if (VT.getSizeInBits() == 128)
10932 return RCPair(0U, &ARM::QPR_8RegClass);
10935 if (VT == MVT::f32)
10936 return RCPair(0U, &ARM::SPRRegClass);
10940 if (StringRef("{cc}").equals_lower(Constraint))
10941 return std::make_pair(unsigned(ARM::CPSR), &ARM::CCRRegClass);
10943 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
10946 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
10947 /// vector. If it is invalid, don't add anything to Ops.
10948 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
10949 std::string &Constraint,
10950 std::vector<SDValue>&Ops,
10951 SelectionDAG &DAG) const {
10954 // Currently only support length 1 constraints.
10955 if (Constraint.length() != 1) return;
10957 char ConstraintLetter = Constraint[0];
10958 switch (ConstraintLetter) {
10961 case 'I': case 'J': case 'K': case 'L':
10962 case 'M': case 'N': case 'O':
10963 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
10967 int64_t CVal64 = C->getSExtValue();
10968 int CVal = (int) CVal64;
10969 // None of these constraints allow values larger than 32 bits. Check
10970 // that the value fits in an int.
10971 if (CVal != CVal64)
10974 switch (ConstraintLetter) {
10976 // Constant suitable for movw, must be between 0 and
10978 if (Subtarget->hasV6T2Ops())
10979 if (CVal >= 0 && CVal <= 65535)
10983 if (Subtarget->isThumb1Only()) {
10984 // This must be a constant between 0 and 255, for ADD
10986 if (CVal >= 0 && CVal <= 255)
10988 } else if (Subtarget->isThumb2()) {
10989 // A constant that can be used as an immediate value in a
10990 // data-processing instruction.
10991 if (ARM_AM::getT2SOImmVal(CVal) != -1)
10994 // A constant that can be used as an immediate value in a
10995 // data-processing instruction.
10996 if (ARM_AM::getSOImmVal(CVal) != -1)
11002 if (Subtarget->isThumb()) { // FIXME thumb2
11003 // This must be a constant between -255 and -1, for negated ADD
11004 // immediates. This can be used in GCC with an "n" modifier that
11005 // prints the negated value, for use with SUB instructions. It is
11006 // not useful otherwise but is implemented for compatibility.
11007 if (CVal >= -255 && CVal <= -1)
11010 // This must be a constant between -4095 and 4095. It is not clear
11011 // what this constraint is intended for. Implemented for
11012 // compatibility with GCC.
11013 if (CVal >= -4095 && CVal <= 4095)
11019 if (Subtarget->isThumb1Only()) {
11020 // A 32-bit value where only one byte has a nonzero value. Exclude
11021 // zero to match GCC. This constraint is used by GCC internally for
11022 // constants that can be loaded with a move/shift combination.
11023 // It is not useful otherwise but is implemented for compatibility.
11024 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
11026 } else if (Subtarget->isThumb2()) {
11027 // A constant whose bitwise inverse can be used as an immediate
11028 // value in a data-processing instruction. This can be used in GCC
11029 // with a "B" modifier that prints the inverted value, for use with
11030 // BIC and MVN instructions. It is not useful otherwise but is
11031 // implemented for compatibility.
11032 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
11035 // A constant whose bitwise inverse can be used as an immediate
11036 // value in a data-processing instruction. This can be used in GCC
11037 // with a "B" modifier that prints the inverted value, for use with
11038 // BIC and MVN instructions. It is not useful otherwise but is
11039 // implemented for compatibility.
11040 if (ARM_AM::getSOImmVal(~CVal) != -1)
11046 if (Subtarget->isThumb1Only()) {
11047 // This must be a constant between -7 and 7,
11048 // for 3-operand ADD/SUB immediate instructions.
11049 if (CVal >= -7 && CVal < 7)
11051 } else if (Subtarget->isThumb2()) {
11052 // A constant whose negation can be used as an immediate value in a
11053 // data-processing instruction. This can be used in GCC with an "n"
11054 // modifier that prints the negated value, for use with SUB
11055 // instructions. It is not useful otherwise but is implemented for
11057 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
11060 // A constant whose negation can be used as an immediate value in a
11061 // data-processing instruction. This can be used in GCC with an "n"
11062 // modifier that prints the negated value, for use with SUB
11063 // instructions. It is not useful otherwise but is implemented for
11065 if (ARM_AM::getSOImmVal(-CVal) != -1)
11071 if (Subtarget->isThumb()) { // FIXME thumb2
11072 // This must be a multiple of 4 between 0 and 1020, for
11073 // ADD sp + immediate.
11074 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
11077 // A power of two or a constant between 0 and 32. This is used in
11078 // GCC for the shift amount on shifted register operands, but it is
11079 // useful in general for any shift amounts.
11080 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
11086 if (Subtarget->isThumb()) { // FIXME thumb2
11087 // This must be a constant between 0 and 31, for shift amounts.
11088 if (CVal >= 0 && CVal <= 31)
11094 if (Subtarget->isThumb()) { // FIXME thumb2
11095 // This must be a multiple of 4 between -508 and 508, for
11096 // ADD/SUB sp = sp + immediate.
11097 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
11102 Result = DAG.getTargetConstant(CVal, SDLoc(Op), Op.getValueType());
11106 if (Result.getNode()) {
11107 Ops.push_back(Result);
11110 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
11113 static RTLIB::Libcall getDivRemLibcall(
11114 const SDNode *N, MVT::SimpleValueType SVT) {
11115 assert((N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD::UDIVREM ||
11116 N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM) &&
11117 "Unhandled Opcode in getDivRemLibcall");
11118 bool isSigned = N->getOpcode() == ISD::SDIVREM ||
11119 N->getOpcode() == ISD::SREM;
11122 default: llvm_unreachable("Unexpected request for libcall!");
11123 case MVT::i8: LC = isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
11124 case MVT::i16: LC = isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
11125 case MVT::i32: LC = isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
11126 case MVT::i64: LC = isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
11131 static TargetLowering::ArgListTy getDivRemArgList(
11132 const SDNode *N, LLVMContext *Context) {
11133 assert((N->getOpcode() == ISD::SDIVREM || N->getOpcode() == ISD::UDIVREM ||
11134 N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM) &&
11135 "Unhandled Opcode in getDivRemArgList");
11136 bool isSigned = N->getOpcode() == ISD::SDIVREM ||
11137 N->getOpcode() == ISD::SREM;
11138 TargetLowering::ArgListTy Args;
11139 TargetLowering::ArgListEntry Entry;
11140 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
11141 EVT ArgVT = N->getOperand(i).getValueType();
11142 Type *ArgTy = ArgVT.getTypeForEVT(*Context);
11143 Entry.Node = N->getOperand(i);
11145 Entry.isSExt = isSigned;
11146 Entry.isZExt = !isSigned;
11147 Args.push_back(Entry);
11152 SDValue ARMTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const {
11153 assert((Subtarget->isTargetAEABI() || Subtarget->isTargetAndroid()) &&
11154 "Register-based DivRem lowering only");
11155 unsigned Opcode = Op->getOpcode();
11156 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
11157 "Invalid opcode for Div/Rem lowering");
11158 bool isSigned = (Opcode == ISD::SDIVREM);
11159 EVT VT = Op->getValueType(0);
11160 Type *Ty = VT.getTypeForEVT(*DAG.getContext());
11162 RTLIB::Libcall LC = getDivRemLibcall(Op.getNode(),
11163 VT.getSimpleVT().SimpleTy);
11164 SDValue InChain = DAG.getEntryNode();
11166 TargetLowering::ArgListTy Args = getDivRemArgList(Op.getNode(),
11169 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
11170 getPointerTy(DAG.getDataLayout()));
11172 Type *RetTy = (Type*)StructType::get(Ty, Ty, nullptr);
11175 TargetLowering::CallLoweringInfo CLI(DAG);
11176 CLI.setDebugLoc(dl).setChain(InChain)
11177 .setCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
11178 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
11180 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
11181 return CallInfo.first;
11184 // Lowers REM using divmod helpers
11185 // see RTABI section 4.2/4.3
11186 SDValue ARMTargetLowering::LowerREM(SDNode *N, SelectionDAG &DAG) const {
11187 // Build return types (div and rem)
11188 std::vector<Type*> RetTyParams;
11189 Type *RetTyElement;
11191 switch (N->getValueType(0).getSimpleVT().SimpleTy) {
11192 default: llvm_unreachable("Unexpected request for libcall!");
11193 case MVT::i8: RetTyElement = Type::getInt8Ty(*DAG.getContext()); break;
11194 case MVT::i16: RetTyElement = Type::getInt16Ty(*DAG.getContext()); break;
11195 case MVT::i32: RetTyElement = Type::getInt32Ty(*DAG.getContext()); break;
11196 case MVT::i64: RetTyElement = Type::getInt64Ty(*DAG.getContext()); break;
11199 RetTyParams.push_back(RetTyElement);
11200 RetTyParams.push_back(RetTyElement);
11201 ArrayRef<Type*> ret = ArrayRef<Type*>(RetTyParams);
11202 Type *RetTy = StructType::get(*DAG.getContext(), ret);
11204 RTLIB::Libcall LC = getDivRemLibcall(N, N->getValueType(0).getSimpleVT().
11206 SDValue InChain = DAG.getEntryNode();
11207 TargetLowering::ArgListTy Args = getDivRemArgList(N, DAG.getContext());
11208 bool isSigned = N->getOpcode() == ISD::SREM;
11209 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
11210 getPointerTy(DAG.getDataLayout()));
11213 CallLoweringInfo CLI(DAG);
11214 CLI.setChain(InChain)
11215 .setCallee(CallingConv::ARM_AAPCS, RetTy, Callee, std::move(Args), 0)
11216 .setSExtResult(isSigned).setZExtResult(!isSigned).setDebugLoc(SDLoc(N));
11217 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
11219 // Return second (rem) result operand (first contains div)
11220 SDNode *ResNode = CallResult.first.getNode();
11221 assert(ResNode->getNumOperands() == 2 && "divmod should return two operands");
11222 return ResNode->getOperand(1);
11226 ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const {
11227 assert(Subtarget->isTargetWindows() && "unsupported target platform");
11231 SDValue Chain = Op.getOperand(0);
11232 SDValue Size = Op.getOperand(1);
11234 SDValue Words = DAG.getNode(ISD::SRL, DL, MVT::i32, Size,
11235 DAG.getConstant(2, DL, MVT::i32));
11238 Chain = DAG.getCopyToReg(Chain, DL, ARM::R4, Words, Flag);
11239 Flag = Chain.getValue(1);
11241 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11242 Chain = DAG.getNode(ARMISD::WIN__CHKSTK, DL, NodeTys, Chain, Flag);
11244 SDValue NewSP = DAG.getCopyFromReg(Chain, DL, ARM::SP, MVT::i32);
11245 Chain = NewSP.getValue(1);
11247 SDValue Ops[2] = { NewSP, Chain };
11248 return DAG.getMergeValues(Ops, DL);
11251 SDValue ARMTargetLowering::LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const {
11252 assert(Op.getValueType() == MVT::f64 && Subtarget->isFPOnlySP() &&
11253 "Unexpected type for custom-lowering FP_EXTEND");
11256 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType());
11258 SDValue SrcVal = Op.getOperand(0);
11259 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
11260 /*isSigned*/ false, SDLoc(Op)).first;
11263 SDValue ARMTargetLowering::LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const {
11264 assert(Op.getOperand(0).getValueType() == MVT::f64 &&
11265 Subtarget->isFPOnlySP() &&
11266 "Unexpected type for custom-lowering FP_ROUND");
11269 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
11271 SDValue SrcVal = Op.getOperand(0);
11272 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
11273 /*isSigned*/ false, SDLoc(Op)).first;
11277 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
11278 // The ARM target isn't yet aware of offsets.
11282 bool ARM::isBitFieldInvertedMask(unsigned v) {
11283 if (v == 0xffffffff)
11286 // there can be 1's on either or both "outsides", all the "inside"
11287 // bits must be 0's
11288 return isShiftedMask_32(~v);
11291 /// isFPImmLegal - Returns true if the target can instruction select the
11292 /// specified FP immediate natively. If false, the legalizer will
11293 /// materialize the FP immediate as a load from a constant pool.
11294 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
11295 if (!Subtarget->hasVFP3())
11297 if (VT == MVT::f32)
11298 return ARM_AM::getFP32Imm(Imm) != -1;
11299 if (VT == MVT::f64 && !Subtarget->isFPOnlySP())
11300 return ARM_AM::getFP64Imm(Imm) != -1;
11304 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
11305 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
11306 /// specified in the intrinsic calls.
11307 bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
11309 unsigned Intrinsic) const {
11310 switch (Intrinsic) {
11311 case Intrinsic::arm_neon_vld1:
11312 case Intrinsic::arm_neon_vld2:
11313 case Intrinsic::arm_neon_vld3:
11314 case Intrinsic::arm_neon_vld4:
11315 case Intrinsic::arm_neon_vld2lane:
11316 case Intrinsic::arm_neon_vld3lane:
11317 case Intrinsic::arm_neon_vld4lane: {
11318 Info.opc = ISD::INTRINSIC_W_CHAIN;
11319 // Conservatively set memVT to the entire set of vectors loaded.
11320 auto &DL = I.getCalledFunction()->getParent()->getDataLayout();
11321 uint64_t NumElts = DL.getTypeAllocSize(I.getType()) / 8;
11322 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
11323 Info.ptrVal = I.getArgOperand(0);
11325 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
11326 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
11327 Info.vol = false; // volatile loads with NEON intrinsics not supported
11328 Info.readMem = true;
11329 Info.writeMem = false;
11332 case Intrinsic::arm_neon_vst1:
11333 case Intrinsic::arm_neon_vst2:
11334 case Intrinsic::arm_neon_vst3:
11335 case Intrinsic::arm_neon_vst4:
11336 case Intrinsic::arm_neon_vst2lane:
11337 case Intrinsic::arm_neon_vst3lane:
11338 case Intrinsic::arm_neon_vst4lane: {
11339 Info.opc = ISD::INTRINSIC_VOID;
11340 // Conservatively set memVT to the entire set of vectors stored.
11341 auto &DL = I.getCalledFunction()->getParent()->getDataLayout();
11342 unsigned NumElts = 0;
11343 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
11344 Type *ArgTy = I.getArgOperand(ArgI)->getType();
11345 if (!ArgTy->isVectorTy())
11347 NumElts += DL.getTypeAllocSize(ArgTy) / 8;
11349 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
11350 Info.ptrVal = I.getArgOperand(0);
11352 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
11353 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
11354 Info.vol = false; // volatile stores with NEON intrinsics not supported
11355 Info.readMem = false;
11356 Info.writeMem = true;
11359 case Intrinsic::arm_ldaex:
11360 case Intrinsic::arm_ldrex: {
11361 auto &DL = I.getCalledFunction()->getParent()->getDataLayout();
11362 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
11363 Info.opc = ISD::INTRINSIC_W_CHAIN;
11364 Info.memVT = MVT::getVT(PtrTy->getElementType());
11365 Info.ptrVal = I.getArgOperand(0);
11367 Info.align = DL.getABITypeAlignment(PtrTy->getElementType());
11369 Info.readMem = true;
11370 Info.writeMem = false;
11373 case Intrinsic::arm_stlex:
11374 case Intrinsic::arm_strex: {
11375 auto &DL = I.getCalledFunction()->getParent()->getDataLayout();
11376 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
11377 Info.opc = ISD::INTRINSIC_W_CHAIN;
11378 Info.memVT = MVT::getVT(PtrTy->getElementType());
11379 Info.ptrVal = I.getArgOperand(1);
11381 Info.align = DL.getABITypeAlignment(PtrTy->getElementType());
11383 Info.readMem = false;
11384 Info.writeMem = true;
11387 case Intrinsic::arm_stlexd:
11388 case Intrinsic::arm_strexd: {
11389 Info.opc = ISD::INTRINSIC_W_CHAIN;
11390 Info.memVT = MVT::i64;
11391 Info.ptrVal = I.getArgOperand(2);
11395 Info.readMem = false;
11396 Info.writeMem = true;
11399 case Intrinsic::arm_ldaexd:
11400 case Intrinsic::arm_ldrexd: {
11401 Info.opc = ISD::INTRINSIC_W_CHAIN;
11402 Info.memVT = MVT::i64;
11403 Info.ptrVal = I.getArgOperand(0);
11407 Info.readMem = true;
11408 Info.writeMem = false;
11418 /// \brief Returns true if it is beneficial to convert a load of a constant
11419 /// to just the constant itself.
11420 bool ARMTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
11422 assert(Ty->isIntegerTy());
11424 unsigned Bits = Ty->getPrimitiveSizeInBits();
11425 if (Bits == 0 || Bits > 32)
11430 Instruction* ARMTargetLowering::makeDMB(IRBuilder<> &Builder,
11431 ARM_MB::MemBOpt Domain) const {
11432 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
11434 // First, if the target has no DMB, see what fallback we can use.
11435 if (!Subtarget->hasDataBarrier()) {
11436 // Some ARMv6 cpus can support data barriers with an mcr instruction.
11437 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
11439 if (Subtarget->hasV6Ops() && !Subtarget->isThumb()) {
11440 Function *MCR = llvm::Intrinsic::getDeclaration(M, Intrinsic::arm_mcr);
11441 Value* args[6] = {Builder.getInt32(15), Builder.getInt32(0),
11442 Builder.getInt32(0), Builder.getInt32(7),
11443 Builder.getInt32(10), Builder.getInt32(5)};
11444 return Builder.CreateCall(MCR, args);
11446 // Instead of using barriers, atomic accesses on these subtargets use
11448 llvm_unreachable("makeDMB on a target so old that it has no barriers");
11451 Function *DMB = llvm::Intrinsic::getDeclaration(M, Intrinsic::arm_dmb);
11452 // Only a full system barrier exists in the M-class architectures.
11453 Domain = Subtarget->isMClass() ? ARM_MB::SY : Domain;
11454 Constant *CDomain = Builder.getInt32(Domain);
11455 return Builder.CreateCall(DMB, CDomain);
11459 // Based on http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
11460 Instruction* ARMTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
11461 AtomicOrdering Ord, bool IsStore,
11462 bool IsLoad) const {
11463 if (!getInsertFencesForAtomic())
11469 llvm_unreachable("Invalid fence: unordered/non-atomic");
11472 return nullptr; // Nothing to do
11473 case SequentiallyConsistent:
11475 return nullptr; // Nothing to do
11478 case AcquireRelease:
11479 if (Subtarget->isSwift())
11480 return makeDMB(Builder, ARM_MB::ISHST);
11481 // FIXME: add a comment with a link to documentation justifying this.
11483 return makeDMB(Builder, ARM_MB::ISH);
11485 llvm_unreachable("Unknown fence ordering in emitLeadingFence");
11488 Instruction* ARMTargetLowering::emitTrailingFence(IRBuilder<> &Builder,
11489 AtomicOrdering Ord, bool IsStore,
11490 bool IsLoad) const {
11491 if (!getInsertFencesForAtomic())
11497 llvm_unreachable("Invalid fence: unordered/not-atomic");
11500 return nullptr; // Nothing to do
11502 case AcquireRelease:
11503 case SequentiallyConsistent:
11504 return makeDMB(Builder, ARM_MB::ISH);
11506 llvm_unreachable("Unknown fence ordering in emitTrailingFence");
11509 // Loads and stores less than 64-bits are already atomic; ones above that
11510 // are doomed anyway, so defer to the default libcall and blame the OS when
11511 // things go wrong. Cortex M doesn't have ldrexd/strexd though, so don't emit
11512 // anything for those.
11513 bool ARMTargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
11514 unsigned Size = SI->getValueOperand()->getType()->getPrimitiveSizeInBits();
11515 return (Size == 64) && !Subtarget->isMClass();
11518 // Loads and stores less than 64-bits are already atomic; ones above that
11519 // are doomed anyway, so defer to the default libcall and blame the OS when
11520 // things go wrong. Cortex M doesn't have ldrexd/strexd though, so don't emit
11521 // anything for those.
11522 // FIXME: ldrd and strd are atomic if the CPU has LPAE (e.g. A15 has that
11523 // guarantee, see DDI0406C ARM architecture reference manual,
11524 // sections A8.8.72-74 LDRD)
11525 TargetLowering::AtomicExpansionKind
11526 ARMTargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
11527 unsigned Size = LI->getType()->getPrimitiveSizeInBits();
11528 return ((Size == 64) && !Subtarget->isMClass()) ? AtomicExpansionKind::LLSC
11529 : AtomicExpansionKind::None;
11532 // For the real atomic operations, we have ldrex/strex up to 32 bits,
11533 // and up to 64 bits on the non-M profiles
11534 TargetLowering::AtomicExpansionKind
11535 ARMTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
11536 unsigned Size = AI->getType()->getPrimitiveSizeInBits();
11537 return (Size <= (Subtarget->isMClass() ? 32U : 64U))
11538 ? AtomicExpansionKind::LLSC
11539 : AtomicExpansionKind::None;
11542 bool ARMTargetLowering::shouldExpandAtomicCmpXchgInIR(
11543 AtomicCmpXchgInst *AI) const {
11547 // This has so far only been implemented for MachO.
11548 bool ARMTargetLowering::useLoadStackGuardNode() const {
11549 return Subtarget->isTargetMachO();
11552 bool ARMTargetLowering::canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
11553 unsigned &Cost) const {
11554 // If we do not have NEON, vector types are not natively supported.
11555 if (!Subtarget->hasNEON())
11558 // Floating point values and vector values map to the same register file.
11559 // Therefore, although we could do a store extract of a vector type, this is
11560 // better to leave at float as we have more freedom in the addressing mode for
11562 if (VectorTy->isFPOrFPVectorTy())
11565 // If the index is unknown at compile time, this is very expensive to lower
11566 // and it is not possible to combine the store with the extract.
11567 if (!isa<ConstantInt>(Idx))
11570 assert(VectorTy->isVectorTy() && "VectorTy is not a vector type");
11571 unsigned BitWidth = cast<VectorType>(VectorTy)->getBitWidth();
11572 // We can do a store + vector extract on any vector that fits perfectly in a D
11574 if (BitWidth == 64 || BitWidth == 128) {
11581 Value *ARMTargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
11582 AtomicOrdering Ord) const {
11583 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
11584 Type *ValTy = cast<PointerType>(Addr->getType())->getElementType();
11585 bool IsAcquire = isAtLeastAcquire(Ord);
11587 // Since i64 isn't legal and intrinsics don't get type-lowered, the ldrexd
11588 // intrinsic must return {i32, i32} and we have to recombine them into a
11589 // single i64 here.
11590 if (ValTy->getPrimitiveSizeInBits() == 64) {
11591 Intrinsic::ID Int =
11592 IsAcquire ? Intrinsic::arm_ldaexd : Intrinsic::arm_ldrexd;
11593 Function *Ldrex = llvm::Intrinsic::getDeclaration(M, Int);
11595 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
11596 Value *LoHi = Builder.CreateCall(Ldrex, Addr, "lohi");
11598 Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo");
11599 Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi");
11600 if (!Subtarget->isLittle())
11601 std::swap (Lo, Hi);
11602 Lo = Builder.CreateZExt(Lo, ValTy, "lo64");
11603 Hi = Builder.CreateZExt(Hi, ValTy, "hi64");
11604 return Builder.CreateOr(
11605 Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 32)), "val64");
11608 Type *Tys[] = { Addr->getType() };
11609 Intrinsic::ID Int = IsAcquire ? Intrinsic::arm_ldaex : Intrinsic::arm_ldrex;
11610 Function *Ldrex = llvm::Intrinsic::getDeclaration(M, Int, Tys);
11612 return Builder.CreateTruncOrBitCast(
11613 Builder.CreateCall(Ldrex, Addr),
11614 cast<PointerType>(Addr->getType())->getElementType());
11617 void ARMTargetLowering::emitAtomicCmpXchgNoStoreLLBalance(
11618 IRBuilder<> &Builder) const {
11619 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
11620 Builder.CreateCall(llvm::Intrinsic::getDeclaration(M, Intrinsic::arm_clrex));
11623 Value *ARMTargetLowering::emitStoreConditional(IRBuilder<> &Builder, Value *Val,
11625 AtomicOrdering Ord) const {
11626 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
11627 bool IsRelease = isAtLeastRelease(Ord);
11629 // Since the intrinsics must have legal type, the i64 intrinsics take two
11630 // parameters: "i32, i32". We must marshal Val into the appropriate form
11631 // before the call.
11632 if (Val->getType()->getPrimitiveSizeInBits() == 64) {
11633 Intrinsic::ID Int =
11634 IsRelease ? Intrinsic::arm_stlexd : Intrinsic::arm_strexd;
11635 Function *Strex = Intrinsic::getDeclaration(M, Int);
11636 Type *Int32Ty = Type::getInt32Ty(M->getContext());
11638 Value *Lo = Builder.CreateTrunc(Val, Int32Ty, "lo");
11639 Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 32), Int32Ty, "hi");
11640 if (!Subtarget->isLittle())
11641 std::swap (Lo, Hi);
11642 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
11643 return Builder.CreateCall(Strex, {Lo, Hi, Addr});
11646 Intrinsic::ID Int = IsRelease ? Intrinsic::arm_stlex : Intrinsic::arm_strex;
11647 Type *Tys[] = { Addr->getType() };
11648 Function *Strex = Intrinsic::getDeclaration(M, Int, Tys);
11650 return Builder.CreateCall(
11651 Strex, {Builder.CreateZExtOrBitCast(
11652 Val, Strex->getFunctionType()->getParamType(0)),
11656 /// \brief Lower an interleaved load into a vldN intrinsic.
11658 /// E.g. Lower an interleaved load (Factor = 2):
11659 /// %wide.vec = load <8 x i32>, <8 x i32>* %ptr, align 4
11660 /// %v0 = shuffle %wide.vec, undef, <0, 2, 4, 6> ; Extract even elements
11661 /// %v1 = shuffle %wide.vec, undef, <1, 3, 5, 7> ; Extract odd elements
11664 /// %vld2 = { <4 x i32>, <4 x i32> } call llvm.arm.neon.vld2(%ptr, 4)
11665 /// %vec0 = extractelement { <4 x i32>, <4 x i32> } %vld2, i32 0
11666 /// %vec1 = extractelement { <4 x i32>, <4 x i32> } %vld2, i32 1
11667 bool ARMTargetLowering::lowerInterleavedLoad(
11668 LoadInst *LI, ArrayRef<ShuffleVectorInst *> Shuffles,
11669 ArrayRef<unsigned> Indices, unsigned Factor) const {
11670 assert(Factor >= 2 && Factor <= getMaxSupportedInterleaveFactor() &&
11671 "Invalid interleave factor");
11672 assert(!Shuffles.empty() && "Empty shufflevector input");
11673 assert(Shuffles.size() == Indices.size() &&
11674 "Unmatched number of shufflevectors and indices");
11676 VectorType *VecTy = Shuffles[0]->getType();
11677 Type *EltTy = VecTy->getVectorElementType();
11679 const DataLayout &DL = LI->getModule()->getDataLayout();
11680 unsigned VecSize = DL.getTypeAllocSizeInBits(VecTy);
11681 bool EltIs64Bits = DL.getTypeAllocSizeInBits(EltTy) == 64;
11683 // Skip illegal vector types and vector types of i64/f64 element (vldN doesn't
11684 // support i64/f64 element).
11685 if ((VecSize != 64 && VecSize != 128) || EltIs64Bits)
11688 // A pointer vector can not be the return type of the ldN intrinsics. Need to
11689 // load integer vectors first and then convert to pointer vectors.
11690 if (EltTy->isPointerTy())
11692 VectorType::get(DL.getIntPtrType(EltTy), VecTy->getVectorNumElements());
11694 static const Intrinsic::ID LoadInts[3] = {Intrinsic::arm_neon_vld2,
11695 Intrinsic::arm_neon_vld3,
11696 Intrinsic::arm_neon_vld4};
11698 Function *VldnFunc =
11699 Intrinsic::getDeclaration(LI->getModule(), LoadInts[Factor - 2], VecTy);
11701 IRBuilder<> Builder(LI);
11702 SmallVector<Value *, 2> Ops;
11704 Type *Int8Ptr = Builder.getInt8PtrTy(LI->getPointerAddressSpace());
11705 Ops.push_back(Builder.CreateBitCast(LI->getPointerOperand(), Int8Ptr));
11706 Ops.push_back(Builder.getInt32(LI->getAlignment()));
11708 CallInst *VldN = Builder.CreateCall(VldnFunc, Ops, "vldN");
11710 // Replace uses of each shufflevector with the corresponding vector loaded
11712 for (unsigned i = 0; i < Shuffles.size(); i++) {
11713 ShuffleVectorInst *SV = Shuffles[i];
11714 unsigned Index = Indices[i];
11716 Value *SubVec = Builder.CreateExtractValue(VldN, Index);
11718 // Convert the integer vector to pointer vector if the element is pointer.
11719 if (EltTy->isPointerTy())
11720 SubVec = Builder.CreateIntToPtr(SubVec, SV->getType());
11722 SV->replaceAllUsesWith(SubVec);
11728 /// \brief Get a mask consisting of sequential integers starting from \p Start.
11730 /// I.e. <Start, Start + 1, ..., Start + NumElts - 1>
11731 static Constant *getSequentialMask(IRBuilder<> &Builder, unsigned Start,
11732 unsigned NumElts) {
11733 SmallVector<Constant *, 16> Mask;
11734 for (unsigned i = 0; i < NumElts; i++)
11735 Mask.push_back(Builder.getInt32(Start + i));
11737 return ConstantVector::get(Mask);
11740 /// \brief Lower an interleaved store into a vstN intrinsic.
11742 /// E.g. Lower an interleaved store (Factor = 3):
11743 /// %i.vec = shuffle <8 x i32> %v0, <8 x i32> %v1,
11744 /// <0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11>
11745 /// store <12 x i32> %i.vec, <12 x i32>* %ptr, align 4
11748 /// %sub.v0 = shuffle <8 x i32> %v0, <8 x i32> v1, <0, 1, 2, 3>
11749 /// %sub.v1 = shuffle <8 x i32> %v0, <8 x i32> v1, <4, 5, 6, 7>
11750 /// %sub.v2 = shuffle <8 x i32> %v0, <8 x i32> v1, <8, 9, 10, 11>
11751 /// call void llvm.arm.neon.vst3(%ptr, %sub.v0, %sub.v1, %sub.v2, 4)
11753 /// Note that the new shufflevectors will be removed and we'll only generate one
11754 /// vst3 instruction in CodeGen.
11755 bool ARMTargetLowering::lowerInterleavedStore(StoreInst *SI,
11756 ShuffleVectorInst *SVI,
11757 unsigned Factor) const {
11758 assert(Factor >= 2 && Factor <= getMaxSupportedInterleaveFactor() &&
11759 "Invalid interleave factor");
11761 VectorType *VecTy = SVI->getType();
11762 assert(VecTy->getVectorNumElements() % Factor == 0 &&
11763 "Invalid interleaved store");
11765 unsigned NumSubElts = VecTy->getVectorNumElements() / Factor;
11766 Type *EltTy = VecTy->getVectorElementType();
11767 VectorType *SubVecTy = VectorType::get(EltTy, NumSubElts);
11769 const DataLayout &DL = SI->getModule()->getDataLayout();
11770 unsigned SubVecSize = DL.getTypeAllocSizeInBits(SubVecTy);
11771 bool EltIs64Bits = DL.getTypeAllocSizeInBits(EltTy) == 64;
11773 // Skip illegal sub vector types and vector types of i64/f64 element (vstN
11774 // doesn't support i64/f64 element).
11775 if ((SubVecSize != 64 && SubVecSize != 128) || EltIs64Bits)
11778 Value *Op0 = SVI->getOperand(0);
11779 Value *Op1 = SVI->getOperand(1);
11780 IRBuilder<> Builder(SI);
11782 // StN intrinsics don't support pointer vectors as arguments. Convert pointer
11783 // vectors to integer vectors.
11784 if (EltTy->isPointerTy()) {
11785 Type *IntTy = DL.getIntPtrType(EltTy);
11787 // Convert to the corresponding integer vector.
11789 VectorType::get(IntTy, Op0->getType()->getVectorNumElements());
11790 Op0 = Builder.CreatePtrToInt(Op0, IntVecTy);
11791 Op1 = Builder.CreatePtrToInt(Op1, IntVecTy);
11793 SubVecTy = VectorType::get(IntTy, NumSubElts);
11796 static Intrinsic::ID StoreInts[3] = {Intrinsic::arm_neon_vst2,
11797 Intrinsic::arm_neon_vst3,
11798 Intrinsic::arm_neon_vst4};
11799 Function *VstNFunc = Intrinsic::getDeclaration(
11800 SI->getModule(), StoreInts[Factor - 2], SubVecTy);
11802 SmallVector<Value *, 6> Ops;
11804 Type *Int8Ptr = Builder.getInt8PtrTy(SI->getPointerAddressSpace());
11805 Ops.push_back(Builder.CreateBitCast(SI->getPointerOperand(), Int8Ptr));
11807 // Split the shufflevector operands into sub vectors for the new vstN call.
11808 for (unsigned i = 0; i < Factor; i++)
11809 Ops.push_back(Builder.CreateShuffleVector(
11810 Op0, Op1, getSequentialMask(Builder, NumSubElts * i, NumSubElts)));
11812 Ops.push_back(Builder.getInt32(SI->getAlignment()));
11813 Builder.CreateCall(VstNFunc, Ops);
11825 static bool isHomogeneousAggregate(Type *Ty, HABaseType &Base,
11826 uint64_t &Members) {
11827 if (auto *ST = dyn_cast<StructType>(Ty)) {
11828 for (unsigned i = 0; i < ST->getNumElements(); ++i) {
11829 uint64_t SubMembers = 0;
11830 if (!isHomogeneousAggregate(ST->getElementType(i), Base, SubMembers))
11832 Members += SubMembers;
11834 } else if (auto *AT = dyn_cast<ArrayType>(Ty)) {
11835 uint64_t SubMembers = 0;
11836 if (!isHomogeneousAggregate(AT->getElementType(), Base, SubMembers))
11838 Members += SubMembers * AT->getNumElements();
11839 } else if (Ty->isFloatTy()) {
11840 if (Base != HA_UNKNOWN && Base != HA_FLOAT)
11844 } else if (Ty->isDoubleTy()) {
11845 if (Base != HA_UNKNOWN && Base != HA_DOUBLE)
11849 } else if (auto *VT = dyn_cast<VectorType>(Ty)) {
11856 return VT->getBitWidth() == 64;
11858 return VT->getBitWidth() == 128;
11860 switch (VT->getBitWidth()) {
11873 return (Members > 0 && Members <= 4);
11876 /// \brief Return true if a type is an AAPCS-VFP homogeneous aggregate or one of
11877 /// [N x i32] or [N x i64]. This allows front-ends to skip emitting padding when
11878 /// passing according to AAPCS rules.
11879 bool ARMTargetLowering::functionArgumentNeedsConsecutiveRegisters(
11880 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const {
11881 if (getEffectiveCallingConv(CallConv, isVarArg) !=
11882 CallingConv::ARM_AAPCS_VFP)
11885 HABaseType Base = HA_UNKNOWN;
11886 uint64_t Members = 0;
11887 bool IsHA = isHomogeneousAggregate(Ty, Base, Members);
11888 DEBUG(dbgs() << "isHA: " << IsHA << " "; Ty->dump());
11890 bool IsIntArray = Ty->isArrayTy() && Ty->getArrayElementType()->isIntegerTy();
11891 return IsHA || IsIntArray;