1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "ARMAddressingModes.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMISelLowering.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMRegisterInfo.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "ARMTargetObjectFile.h"
24 #include "llvm/CallingConv.h"
25 #include "llvm/Constants.h"
26 #include "llvm/Function.h"
27 #include "llvm/Instruction.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/GlobalValue.h"
30 #include "llvm/CodeGen/CallingConvLower.h"
31 #include "llvm/CodeGen/MachineBasicBlock.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/PseudoSourceValue.h"
37 #include "llvm/CodeGen/SelectionDAG.h"
38 #include "llvm/Target/TargetOptions.h"
39 #include "llvm/ADT/VectorExtras.h"
40 #include "llvm/Support/ErrorHandling.h"
41 #include "llvm/Support/MathExtras.h"
44 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
45 CCValAssign::LocInfo &LocInfo,
46 ISD::ArgFlagsTy &ArgFlags,
48 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
49 CCValAssign::LocInfo &LocInfo,
50 ISD::ArgFlagsTy &ArgFlags,
52 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
53 CCValAssign::LocInfo &LocInfo,
54 ISD::ArgFlagsTy &ArgFlags,
56 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
57 CCValAssign::LocInfo &LocInfo,
58 ISD::ArgFlagsTy &ArgFlags,
61 void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
62 EVT PromotedBitwiseVT) {
63 if (VT != PromotedLdStVT) {
64 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
65 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
66 PromotedLdStVT.getSimpleVT());
68 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
69 AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
70 PromotedLdStVT.getSimpleVT());
73 EVT ElemTy = VT.getVectorElementType();
74 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
75 setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
76 if (ElemTy == MVT::i8 || ElemTy == MVT::i16)
77 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
78 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
79 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
80 setOperationAction(ISD::SCALAR_TO_VECTOR, VT.getSimpleVT(), Custom);
81 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Custom);
83 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
84 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
85 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
88 // Promote all bit-wise operations.
89 if (VT.isInteger() && VT != PromotedBitwiseVT) {
90 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
91 AddPromotedToType (ISD::AND, VT.getSimpleVT(),
92 PromotedBitwiseVT.getSimpleVT());
93 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
94 AddPromotedToType (ISD::OR, VT.getSimpleVT(),
95 PromotedBitwiseVT.getSimpleVT());
96 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
97 AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
98 PromotedBitwiseVT.getSimpleVT());
102 void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
103 addRegisterClass(VT, ARM::DPRRegisterClass);
104 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
107 void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
108 addRegisterClass(VT, ARM::QPRRegisterClass);
109 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
112 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
113 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
114 return new TargetLoweringObjectFileMachO();
115 return new ARMElfTargetObjectFile();
118 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
119 : TargetLowering(TM, createTLOF(TM)), ARMPCLabelIndex(0) {
120 Subtarget = &TM.getSubtarget<ARMSubtarget>();
122 if (Subtarget->isTargetDarwin()) {
123 // Uses VFP for Thumb libfuncs if available.
124 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
125 // Single-precision floating-point arithmetic.
126 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
127 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
128 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
129 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
131 // Double-precision floating-point arithmetic.
132 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
133 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
134 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
135 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
137 // Single-precision comparisons.
138 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
139 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
140 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
141 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
142 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
143 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
144 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
145 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
147 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
148 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
149 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
150 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
151 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
152 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
153 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
154 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
156 // Double-precision comparisons.
157 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
158 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
159 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
160 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
161 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
162 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
163 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
164 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
166 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
167 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
168 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
169 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
170 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
171 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
172 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
173 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
175 // Floating-point to integer conversions.
176 // i64 conversions are done via library routines even when generating VFP
177 // instructions, so use the same ones.
178 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
179 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
180 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
181 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
183 // Conversions between floating types.
184 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
185 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
187 // Integer to floating-point conversions.
188 // i64 conversions are done via library routines even when generating VFP
189 // instructions, so use the same ones.
190 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
191 // e.g., __floatunsidf vs. __floatunssidfvfp.
192 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
193 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
194 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
195 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
199 // These libcalls are not available in 32-bit.
200 setLibcallName(RTLIB::SHL_I128, 0);
201 setLibcallName(RTLIB::SRL_I128, 0);
202 setLibcallName(RTLIB::SRA_I128, 0);
204 if (Subtarget->isThumb1Only())
205 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
207 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
208 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
209 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
210 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
212 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
215 if (Subtarget->hasNEON()) {
216 addDRTypeForNEON(MVT::v2f32);
217 addDRTypeForNEON(MVT::v8i8);
218 addDRTypeForNEON(MVT::v4i16);
219 addDRTypeForNEON(MVT::v2i32);
220 addDRTypeForNEON(MVT::v1i64);
222 addQRTypeForNEON(MVT::v4f32);
223 addQRTypeForNEON(MVT::v2f64);
224 addQRTypeForNEON(MVT::v16i8);
225 addQRTypeForNEON(MVT::v8i16);
226 addQRTypeForNEON(MVT::v4i32);
227 addQRTypeForNEON(MVT::v2i64);
229 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
230 setTargetDAGCombine(ISD::SHL);
231 setTargetDAGCombine(ISD::SRL);
232 setTargetDAGCombine(ISD::SRA);
233 setTargetDAGCombine(ISD::SIGN_EXTEND);
234 setTargetDAGCombine(ISD::ZERO_EXTEND);
235 setTargetDAGCombine(ISD::ANY_EXTEND);
238 computeRegisterProperties();
240 // ARM does not have f32 extending load.
241 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
243 // ARM does not have i1 sign extending load.
244 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
246 // ARM supports all 4 flavors of integer indexed load / store.
247 if (!Subtarget->isThumb1Only()) {
248 for (unsigned im = (unsigned)ISD::PRE_INC;
249 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
250 setIndexedLoadAction(im, MVT::i1, Legal);
251 setIndexedLoadAction(im, MVT::i8, Legal);
252 setIndexedLoadAction(im, MVT::i16, Legal);
253 setIndexedLoadAction(im, MVT::i32, Legal);
254 setIndexedStoreAction(im, MVT::i1, Legal);
255 setIndexedStoreAction(im, MVT::i8, Legal);
256 setIndexedStoreAction(im, MVT::i16, Legal);
257 setIndexedStoreAction(im, MVT::i32, Legal);
261 // i64 operation support.
262 if (Subtarget->isThumb1Only()) {
263 setOperationAction(ISD::MUL, MVT::i64, Expand);
264 setOperationAction(ISD::MULHU, MVT::i32, Expand);
265 setOperationAction(ISD::MULHS, MVT::i32, Expand);
266 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
267 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
269 setOperationAction(ISD::MUL, MVT::i64, Expand);
270 setOperationAction(ISD::MULHU, MVT::i32, Expand);
271 if (!Subtarget->hasV6Ops())
272 setOperationAction(ISD::MULHS, MVT::i32, Expand);
274 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
275 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
276 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
277 setOperationAction(ISD::SRL, MVT::i64, Custom);
278 setOperationAction(ISD::SRA, MVT::i64, Custom);
280 // ARM does not have ROTL.
281 setOperationAction(ISD::ROTL, MVT::i32, Expand);
282 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
283 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
284 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
285 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
287 // Only ARMv6 has BSWAP.
288 if (!Subtarget->hasV6Ops())
289 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
291 // These are expanded into libcalls.
292 setOperationAction(ISD::SDIV, MVT::i32, Expand);
293 setOperationAction(ISD::UDIV, MVT::i32, Expand);
294 setOperationAction(ISD::SREM, MVT::i32, Expand);
295 setOperationAction(ISD::UREM, MVT::i32, Expand);
296 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
297 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
299 // Support label based line numbers.
300 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
301 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
303 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
304 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
305 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
306 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
308 // Use the default implementation.
309 setOperationAction(ISD::VASTART, MVT::Other, Custom);
310 setOperationAction(ISD::VAARG, MVT::Other, Expand);
311 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
312 setOperationAction(ISD::VAEND, MVT::Other, Expand);
313 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
314 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
315 if (Subtarget->isThumb())
316 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
318 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
319 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
321 if (!Subtarget->hasV6Ops() && !Subtarget->isThumb2()) {
322 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
323 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
325 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
327 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only())
328 // Turn f64->i64 into FMRRD, i64 -> f64 to FMDRR iff target supports vfp2.
329 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
331 // We want to custom lower some of our intrinsics.
332 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
333 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
334 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
336 setOperationAction(ISD::SETCC, MVT::i32, Expand);
337 setOperationAction(ISD::SETCC, MVT::f32, Expand);
338 setOperationAction(ISD::SETCC, MVT::f64, Expand);
339 setOperationAction(ISD::SELECT, MVT::i32, Expand);
340 setOperationAction(ISD::SELECT, MVT::f32, Expand);
341 setOperationAction(ISD::SELECT, MVT::f64, Expand);
342 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
343 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
344 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
346 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
347 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
348 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
349 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
350 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
352 // We don't support sin/cos/fmod/copysign/pow
353 setOperationAction(ISD::FSIN, MVT::f64, Expand);
354 setOperationAction(ISD::FSIN, MVT::f32, Expand);
355 setOperationAction(ISD::FCOS, MVT::f32, Expand);
356 setOperationAction(ISD::FCOS, MVT::f64, Expand);
357 setOperationAction(ISD::FREM, MVT::f64, Expand);
358 setOperationAction(ISD::FREM, MVT::f32, Expand);
359 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
360 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
361 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
363 setOperationAction(ISD::FPOW, MVT::f64, Expand);
364 setOperationAction(ISD::FPOW, MVT::f32, Expand);
366 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
367 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
368 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
369 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
370 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
371 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
374 // We have target-specific dag combine patterns for the following nodes:
375 // ARMISD::FMRRD - No need to call setTargetDAGCombine
376 setTargetDAGCombine(ISD::ADD);
377 setTargetDAGCombine(ISD::SUB);
379 setStackPointerRegisterToSaveRestore(ARM::SP);
380 setSchedulingPreference(SchedulingForRegPressure);
381 setIfCvtBlockSizeLimit(Subtarget->isThumb() ? 0 : 10);
382 setIfCvtDupBlockSizeLimit(Subtarget->isThumb() ? 0 : 2);
384 if (!Subtarget->isThumb()) {
385 // Use branch latency information to determine if-conversion limits.
386 // FIXME: If-converter should use instruction latency of the branch being
387 // eliminated to compute the threshold. For ARMv6, the branch "latency"
388 // varies depending on whether it's dynamically or statically predicted
389 // and on whether the destination is in the prefetch buffer.
390 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
391 const InstrItineraryData &InstrItins = Subtarget->getInstrItineraryData();
392 unsigned Latency= InstrItins.getLatency(TII->get(ARM::Bcc).getSchedClass());
394 setIfCvtBlockSizeLimit(Latency-1);
396 setIfCvtDupBlockSizeLimit(Latency-2);
398 setIfCvtBlockSizeLimit(10);
399 setIfCvtDupBlockSizeLimit(2);
403 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
404 // Do not enable CodePlacementOpt for now: it currently runs after the
405 // ARMConstantIslandPass and messes up branch relaxation and placement
406 // of constant islands.
407 // benefitFromCodePlacementOpt = true;
410 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
413 case ARMISD::Wrapper: return "ARMISD::Wrapper";
414 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
415 case ARMISD::CALL: return "ARMISD::CALL";
416 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
417 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
418 case ARMISD::tCALL: return "ARMISD::tCALL";
419 case ARMISD::BRCOND: return "ARMISD::BRCOND";
420 case ARMISD::BR_JT: return "ARMISD::BR_JT";
421 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
422 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
423 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
424 case ARMISD::CMP: return "ARMISD::CMP";
425 case ARMISD::CMPZ: return "ARMISD::CMPZ";
426 case ARMISD::CMPFP: return "ARMISD::CMPFP";
427 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
428 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
429 case ARMISD::CMOV: return "ARMISD::CMOV";
430 case ARMISD::CNEG: return "ARMISD::CNEG";
432 case ARMISD::FTOSI: return "ARMISD::FTOSI";
433 case ARMISD::FTOUI: return "ARMISD::FTOUI";
434 case ARMISD::SITOF: return "ARMISD::SITOF";
435 case ARMISD::UITOF: return "ARMISD::UITOF";
437 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
438 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
439 case ARMISD::RRX: return "ARMISD::RRX";
441 case ARMISD::FMRRD: return "ARMISD::FMRRD";
442 case ARMISD::FMDRR: return "ARMISD::FMDRR";
444 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
446 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
448 case ARMISD::VCEQ: return "ARMISD::VCEQ";
449 case ARMISD::VCGE: return "ARMISD::VCGE";
450 case ARMISD::VCGEU: return "ARMISD::VCGEU";
451 case ARMISD::VCGT: return "ARMISD::VCGT";
452 case ARMISD::VCGTU: return "ARMISD::VCGTU";
453 case ARMISD::VTST: return "ARMISD::VTST";
455 case ARMISD::VSHL: return "ARMISD::VSHL";
456 case ARMISD::VSHRs: return "ARMISD::VSHRs";
457 case ARMISD::VSHRu: return "ARMISD::VSHRu";
458 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
459 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
460 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
461 case ARMISD::VSHRN: return "ARMISD::VSHRN";
462 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
463 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
464 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
465 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
466 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
467 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
468 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
469 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
470 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
471 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
472 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
473 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
474 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
475 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
476 case ARMISD::VDUPLANEQ: return "ARMISD::VDUPLANEQ";
477 case ARMISD::VLD2D: return "ARMISD::VLD2D";
478 case ARMISD::VLD3D: return "ARMISD::VLD3D";
479 case ARMISD::VLD4D: return "ARMISD::VLD4D";
480 case ARMISD::VST2D: return "ARMISD::VST2D";
481 case ARMISD::VST3D: return "ARMISD::VST3D";
482 case ARMISD::VST4D: return "ARMISD::VST4D";
486 /// getFunctionAlignment - Return the Log2 alignment of this function.
487 unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
488 return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 1 : 2;
491 //===----------------------------------------------------------------------===//
493 //===----------------------------------------------------------------------===//
495 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
496 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
498 default: llvm_unreachable("Unknown condition code!");
499 case ISD::SETNE: return ARMCC::NE;
500 case ISD::SETEQ: return ARMCC::EQ;
501 case ISD::SETGT: return ARMCC::GT;
502 case ISD::SETGE: return ARMCC::GE;
503 case ISD::SETLT: return ARMCC::LT;
504 case ISD::SETLE: return ARMCC::LE;
505 case ISD::SETUGT: return ARMCC::HI;
506 case ISD::SETUGE: return ARMCC::HS;
507 case ISD::SETULT: return ARMCC::LO;
508 case ISD::SETULE: return ARMCC::LS;
512 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. It
513 /// returns true if the operands should be inverted to form the proper
515 static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
516 ARMCC::CondCodes &CondCode2) {
518 CondCode2 = ARMCC::AL;
520 default: llvm_unreachable("Unknown FP condition!");
522 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
524 case ISD::SETOGT: CondCode = ARMCC::GT; break;
526 case ISD::SETOGE: CondCode = ARMCC::GE; break;
527 case ISD::SETOLT: CondCode = ARMCC::MI; break;
528 case ISD::SETOLE: CondCode = ARMCC::GT; Invert = true; break;
529 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
530 case ISD::SETO: CondCode = ARMCC::VC; break;
531 case ISD::SETUO: CondCode = ARMCC::VS; break;
532 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
533 case ISD::SETUGT: CondCode = ARMCC::HI; break;
534 case ISD::SETUGE: CondCode = ARMCC::PL; break;
536 case ISD::SETULT: CondCode = ARMCC::LT; break;
538 case ISD::SETULE: CondCode = ARMCC::LE; break;
540 case ISD::SETUNE: CondCode = ARMCC::NE; break;
545 //===----------------------------------------------------------------------===//
546 // Calling Convention Implementation
547 //===----------------------------------------------------------------------===//
549 #include "ARMGenCallingConv.inc"
551 // APCS f64 is in register pairs, possibly split to stack
552 static bool f64AssignAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
553 CCValAssign::LocInfo &LocInfo,
554 CCState &State, bool CanFail) {
555 static const unsigned RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
557 // Try to get the first register.
558 if (unsigned Reg = State.AllocateReg(RegList, 4))
559 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
561 // For the 2nd half of a v2f64, do not fail.
565 // Put the whole thing on the stack.
566 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
567 State.AllocateStack(8, 4),
572 // Try to get the second register.
573 if (unsigned Reg = State.AllocateReg(RegList, 4))
574 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
576 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
577 State.AllocateStack(4, 4),
582 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
583 CCValAssign::LocInfo &LocInfo,
584 ISD::ArgFlagsTy &ArgFlags,
586 if (!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
588 if (LocVT == MVT::v2f64 &&
589 !f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
591 return true; // we handled it
594 // AAPCS f64 is in aligned register pairs
595 static bool f64AssignAAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
596 CCValAssign::LocInfo &LocInfo,
597 CCState &State, bool CanFail) {
598 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
599 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
601 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
603 // For the 2nd half of a v2f64, do not just fail.
607 // Put the whole thing on the stack.
608 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
609 State.AllocateStack(8, 8),
615 for (i = 0; i < 2; ++i)
616 if (HiRegList[i] == Reg)
619 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
620 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
625 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
626 CCValAssign::LocInfo &LocInfo,
627 ISD::ArgFlagsTy &ArgFlags,
629 if (!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
631 if (LocVT == MVT::v2f64 &&
632 !f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
634 return true; // we handled it
637 static bool f64RetAssign(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
638 CCValAssign::LocInfo &LocInfo, CCState &State) {
639 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
640 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
642 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
644 return false; // we didn't handle it
647 for (i = 0; i < 2; ++i)
648 if (HiRegList[i] == Reg)
651 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
652 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
657 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
658 CCValAssign::LocInfo &LocInfo,
659 ISD::ArgFlagsTy &ArgFlags,
661 if (!f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
663 if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
665 return true; // we handled it
668 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
669 CCValAssign::LocInfo &LocInfo,
670 ISD::ArgFlagsTy &ArgFlags,
672 return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags,
676 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
677 /// given CallingConvention value.
678 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(unsigned CC,
680 bool isVarArg) const {
683 llvm_unreachable("Unsupported calling convention");
685 case CallingConv::Fast:
686 // Use target triple & subtarget features to do actual dispatch.
687 if (Subtarget->isAAPCS_ABI()) {
688 if (Subtarget->hasVFP2() &&
689 FloatABIType == FloatABI::Hard && !isVarArg)
690 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
692 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
694 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
695 case CallingConv::ARM_AAPCS_VFP:
696 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
697 case CallingConv::ARM_AAPCS:
698 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
699 case CallingConv::ARM_APCS:
700 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
704 /// LowerCallResult - Lower the result values of a call into the
705 /// appropriate copies out of appropriate physical registers.
707 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
708 unsigned CallConv, bool isVarArg,
709 const SmallVectorImpl<ISD::InputArg> &Ins,
710 DebugLoc dl, SelectionDAG &DAG,
711 SmallVectorImpl<SDValue> &InVals) {
713 // Assign locations to each value returned by this call.
714 SmallVector<CCValAssign, 16> RVLocs;
715 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
716 RVLocs, *DAG.getContext());
717 CCInfo.AnalyzeCallResult(Ins,
718 CCAssignFnForNode(CallConv, /* Return*/ true,
721 // Copy all of the result registers out of their specified physreg.
722 for (unsigned i = 0; i != RVLocs.size(); ++i) {
723 CCValAssign VA = RVLocs[i];
726 if (VA.needsCustom()) {
727 // Handle f64 or half of a v2f64.
728 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
730 Chain = Lo.getValue(1);
731 InFlag = Lo.getValue(2);
732 VA = RVLocs[++i]; // skip ahead to next loc
733 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
735 Chain = Hi.getValue(1);
736 InFlag = Hi.getValue(2);
737 Val = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
739 if (VA.getLocVT() == MVT::v2f64) {
740 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
741 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
742 DAG.getConstant(0, MVT::i32));
744 VA = RVLocs[++i]; // skip ahead to next loc
745 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
746 Chain = Lo.getValue(1);
747 InFlag = Lo.getValue(2);
748 VA = RVLocs[++i]; // skip ahead to next loc
749 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
750 Chain = Hi.getValue(1);
751 InFlag = Hi.getValue(2);
752 Val = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
753 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
754 DAG.getConstant(1, MVT::i32));
757 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
759 Chain = Val.getValue(1);
760 InFlag = Val.getValue(2);
763 switch (VA.getLocInfo()) {
764 default: llvm_unreachable("Unknown loc info!");
765 case CCValAssign::Full: break;
766 case CCValAssign::BCvt:
767 Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val);
771 InVals.push_back(Val);
777 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
778 /// by "Src" to address "Dst" of size "Size". Alignment information is
779 /// specified by the specific parameter attribute. The copy will be passed as
780 /// a byval function parameter.
781 /// Sometimes what we are copying is the end of a larger object, the part that
782 /// does not fit in registers.
784 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
785 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
787 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
788 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
789 /*AlwaysInline=*/false, NULL, 0, NULL, 0);
792 /// LowerMemOpCallTo - Store the argument to the stack.
794 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
795 SDValue StackPtr, SDValue Arg,
796 DebugLoc dl, SelectionDAG &DAG,
797 const CCValAssign &VA,
798 ISD::ArgFlagsTy Flags) {
799 unsigned LocMemOffset = VA.getLocMemOffset();
800 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
801 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
802 if (Flags.isByVal()) {
803 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
805 return DAG.getStore(Chain, dl, Arg, PtrOff,
806 PseudoSourceValue::getStack(), LocMemOffset);
809 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
810 SDValue Chain, SDValue &Arg,
811 RegsToPassVector &RegsToPass,
812 CCValAssign &VA, CCValAssign &NextVA,
814 SmallVector<SDValue, 8> &MemOpChains,
815 ISD::ArgFlagsTy Flags) {
817 SDValue fmrrd = DAG.getNode(ARMISD::FMRRD, dl,
818 DAG.getVTList(MVT::i32, MVT::i32), Arg);
819 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
821 if (NextVA.isRegLoc())
822 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
824 assert(NextVA.isMemLoc());
825 if (StackPtr.getNode() == 0)
826 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
828 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
834 /// LowerCall - Lowering a call into a callseq_start <-
835 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
838 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
839 unsigned CallConv, bool isVarArg,
841 const SmallVectorImpl<ISD::OutputArg> &Outs,
842 const SmallVectorImpl<ISD::InputArg> &Ins,
843 DebugLoc dl, SelectionDAG &DAG,
844 SmallVectorImpl<SDValue> &InVals) {
846 // Analyze operands of the call, assigning locations to each operand.
847 SmallVector<CCValAssign, 16> ArgLocs;
848 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
850 CCInfo.AnalyzeCallOperands(Outs,
851 CCAssignFnForNode(CallConv, /* Return*/ false,
854 // Get a count of how many bytes are to be pushed on the stack.
855 unsigned NumBytes = CCInfo.getNextStackOffset();
857 // Adjust the stack pointer for the new arguments...
858 // These operations are automatically eliminated by the prolog/epilog pass
859 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
861 SDValue StackPtr = DAG.getRegister(ARM::SP, MVT::i32);
863 RegsToPassVector RegsToPass;
864 SmallVector<SDValue, 8> MemOpChains;
866 // Walk the register/memloc assignments, inserting copies/loads. In the case
867 // of tail call optimization, arguments are handled later.
868 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
871 CCValAssign &VA = ArgLocs[i];
872 SDValue Arg = Outs[realArgIdx].Val;
873 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
875 // Promote the value if needed.
876 switch (VA.getLocInfo()) {
877 default: llvm_unreachable("Unknown loc info!");
878 case CCValAssign::Full: break;
879 case CCValAssign::SExt:
880 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
882 case CCValAssign::ZExt:
883 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
885 case CCValAssign::AExt:
886 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
888 case CCValAssign::BCvt:
889 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
893 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
894 if (VA.needsCustom()) {
895 if (VA.getLocVT() == MVT::v2f64) {
896 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
897 DAG.getConstant(0, MVT::i32));
898 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
899 DAG.getConstant(1, MVT::i32));
901 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
902 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
904 VA = ArgLocs[++i]; // skip ahead to next loc
906 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
907 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
909 assert(VA.isMemLoc());
910 if (StackPtr.getNode() == 0)
911 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
913 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
914 dl, DAG, VA, Flags));
917 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
918 StackPtr, MemOpChains, Flags);
920 } else if (VA.isRegLoc()) {
921 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
923 assert(VA.isMemLoc());
924 if (StackPtr.getNode() == 0)
925 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
927 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
928 dl, DAG, VA, Flags));
932 if (!MemOpChains.empty())
933 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
934 &MemOpChains[0], MemOpChains.size());
936 // Build a sequence of copy-to-reg nodes chained together with token chain
937 // and flag operands which copy the outgoing args into the appropriate regs.
939 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
940 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
941 RegsToPass[i].second, InFlag);
942 InFlag = Chain.getValue(1);
945 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
946 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
947 // node so that legalize doesn't hack it.
948 bool isDirect = false;
949 bool isARMFunc = false;
950 bool isLocalARMFunc = false;
951 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
952 GlobalValue *GV = G->getGlobal();
954 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
955 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
956 getTargetMachine().getRelocationModel() != Reloc::Static;
957 isARMFunc = !Subtarget->isThumb() || isStub;
958 // ARM call to a local ARM function is predicable.
959 isLocalARMFunc = !Subtarget->isThumb() && !isExt;
960 // tBX takes a register source operand.
961 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
962 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
964 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
965 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
966 Callee = DAG.getLoad(getPointerTy(), dl,
967 DAG.getEntryNode(), CPAddr, NULL, 0);
968 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
969 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
970 getPointerTy(), Callee, PICLabel);
972 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy());
973 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
975 bool isStub = Subtarget->isTargetDarwin() &&
976 getTargetMachine().getRelocationModel() != Reloc::Static;
977 isARMFunc = !Subtarget->isThumb() || isStub;
978 // tBX takes a register source operand.
979 const char *Sym = S->getSymbol();
980 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
981 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(Sym, ARMPCLabelIndex,
983 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
984 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
985 Callee = DAG.getLoad(getPointerTy(), dl,
986 DAG.getEntryNode(), CPAddr, NULL, 0);
987 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
988 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
989 getPointerTy(), Callee, PICLabel);
991 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
994 // FIXME: handle tail calls differently.
996 if (Subtarget->isThumb()) {
997 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
998 CallOpc = ARMISD::CALL_NOLINK;
1000 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1002 CallOpc = (isDirect || Subtarget->hasV5TOps())
1003 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
1004 : ARMISD::CALL_NOLINK;
1006 if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb1Only()) {
1007 // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK
1008 Chain = DAG.getCopyToReg(Chain, dl, ARM::LR, DAG.getUNDEF(MVT::i32),InFlag);
1009 InFlag = Chain.getValue(1);
1012 std::vector<SDValue> Ops;
1013 Ops.push_back(Chain);
1014 Ops.push_back(Callee);
1016 // Add argument registers to the end of the list so that they are known live
1018 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1019 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1020 RegsToPass[i].second.getValueType()));
1022 if (InFlag.getNode())
1023 Ops.push_back(InFlag);
1024 // Returns a chain and a flag for retval copy to use.
1025 Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(MVT::Other, MVT::Flag),
1026 &Ops[0], Ops.size());
1027 InFlag = Chain.getValue(1);
1029 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1030 DAG.getIntPtrConstant(0, true), InFlag);
1032 InFlag = Chain.getValue(1);
1034 // Handle result values, copying them out of physregs into vregs that we
1036 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1041 ARMTargetLowering::LowerReturn(SDValue Chain,
1042 unsigned CallConv, bool isVarArg,
1043 const SmallVectorImpl<ISD::OutputArg> &Outs,
1044 DebugLoc dl, SelectionDAG &DAG) {
1046 // CCValAssign - represent the assignment of the return value to a location.
1047 SmallVector<CCValAssign, 16> RVLocs;
1049 // CCState - Info about the registers and stack slots.
1050 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
1053 // Analyze outgoing return values.
1054 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1057 // If this is the first return lowered for this function, add
1058 // the regs to the liveout set for the function.
1059 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1060 for (unsigned i = 0; i != RVLocs.size(); ++i)
1061 if (RVLocs[i].isRegLoc())
1062 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1067 // Copy the result values into the output registers.
1068 for (unsigned i = 0, realRVLocIdx = 0;
1070 ++i, ++realRVLocIdx) {
1071 CCValAssign &VA = RVLocs[i];
1072 assert(VA.isRegLoc() && "Can only return in registers!");
1074 SDValue Arg = Outs[realRVLocIdx].Val;
1076 switch (VA.getLocInfo()) {
1077 default: llvm_unreachable("Unknown loc info!");
1078 case CCValAssign::Full: break;
1079 case CCValAssign::BCvt:
1080 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1084 if (VA.needsCustom()) {
1085 if (VA.getLocVT() == MVT::v2f64) {
1086 // Extract the first half and return it in two registers.
1087 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1088 DAG.getConstant(0, MVT::i32));
1089 SDValue HalfGPRs = DAG.getNode(ARMISD::FMRRD, dl,
1090 DAG.getVTList(MVT::i32, MVT::i32), Half);
1092 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1093 Flag = Chain.getValue(1);
1094 VA = RVLocs[++i]; // skip ahead to next loc
1095 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1096 HalfGPRs.getValue(1), Flag);
1097 Flag = Chain.getValue(1);
1098 VA = RVLocs[++i]; // skip ahead to next loc
1100 // Extract the 2nd half and fall through to handle it as an f64 value.
1101 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1102 DAG.getConstant(1, MVT::i32));
1104 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1106 SDValue fmrrd = DAG.getNode(ARMISD::FMRRD, dl,
1107 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1108 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1109 Flag = Chain.getValue(1);
1110 VA = RVLocs[++i]; // skip ahead to next loc
1111 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1114 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1116 // Guarantee that all emitted copies are
1117 // stuck together, avoiding something bad.
1118 Flag = Chain.getValue(1);
1123 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1125 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1130 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1131 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1132 // one of the above mentioned nodes. It has to be wrapped because otherwise
1133 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1134 // be used to form addressing mode. These wrapped nodes will be selected
1136 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1137 EVT PtrVT = Op.getValueType();
1138 // FIXME there is no actual debug info here
1139 DebugLoc dl = Op.getDebugLoc();
1140 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1142 if (CP->isMachineConstantPoolEntry())
1143 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1144 CP->getAlignment());
1146 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1147 CP->getAlignment());
1148 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1151 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
1153 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1154 SelectionDAG &DAG) {
1155 DebugLoc dl = GA->getDebugLoc();
1156 EVT PtrVT = getPointerTy();
1157 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1158 ARMConstantPoolValue *CPV =
1159 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
1160 PCAdj, "tlsgd", true);
1161 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1162 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
1163 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument, NULL, 0);
1164 SDValue Chain = Argument.getValue(1);
1166 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1167 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
1169 // call __tls_get_addr.
1172 Entry.Node = Argument;
1173 Entry.Ty = (const Type *) Type::Int32Ty;
1174 Args.push_back(Entry);
1175 // FIXME: is there useful debug info available here?
1176 std::pair<SDValue, SDValue> CallResult =
1177 LowerCallTo(Chain, (const Type *) Type::Int32Ty, false, false, false, false,
1178 0, CallingConv::C, false, /*isReturnValueUsed=*/true,
1179 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
1180 return CallResult.first;
1183 // Lower ISD::GlobalTLSAddress using the "initial exec" or
1184 // "local exec" model.
1186 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
1187 SelectionDAG &DAG) {
1188 GlobalValue *GV = GA->getGlobal();
1189 DebugLoc dl = GA->getDebugLoc();
1191 SDValue Chain = DAG.getEntryNode();
1192 EVT PtrVT = getPointerTy();
1193 // Get the Thread Pointer
1194 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1196 if (GV->isDeclaration()) {
1197 // initial exec model
1198 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1199 ARMConstantPoolValue *CPV =
1200 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
1201 PCAdj, "gottpoff", true);
1202 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1203 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1204 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
1205 Chain = Offset.getValue(1);
1207 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1208 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
1210 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
1213 ARMConstantPoolValue *CPV =
1214 new ARMConstantPoolValue(GV, ARMCP::CPValue, "tpoff");
1215 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1216 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1217 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
1220 // The address of the thread local variable is the add of the thread
1221 // pointer with the offset of the variable.
1222 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
1226 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
1227 // TODO: implement the "local dynamic" model
1228 assert(Subtarget->isTargetELF() &&
1229 "TLS not implemented for non-ELF targets");
1230 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1231 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
1232 // otherwise use the "Local Exec" TLS Model
1233 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
1234 return LowerToTLSGeneralDynamicModel(GA, DAG);
1236 return LowerToTLSExecModels(GA, DAG);
1239 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
1240 SelectionDAG &DAG) {
1241 EVT PtrVT = getPointerTy();
1242 DebugLoc dl = Op.getDebugLoc();
1243 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1244 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1245 if (RelocM == Reloc::PIC_) {
1246 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
1247 ARMConstantPoolValue *CPV =
1248 new ARMConstantPoolValue(GV, ARMCP::CPValue, UseGOTOFF ? "GOTOFF":"GOT");
1249 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1250 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1251 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1253 SDValue Chain = Result.getValue(1);
1254 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1255 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
1257 Result = DAG.getLoad(PtrVT, dl, Chain, Result, NULL, 0);
1260 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1261 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1262 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
1266 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol
1267 /// even in non-static mode.
1268 static bool GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model RelocM) {
1269 // If symbol visibility is hidden, the extra load is not needed if
1270 // the symbol is definitely defined in the current translation unit.
1271 bool isDecl = GV->isDeclaration() || GV->hasAvailableExternallyLinkage();
1272 if (GV->hasHiddenVisibility() && (!isDecl && !GV->hasCommonLinkage()))
1274 return RelocM != Reloc::Static && (isDecl || GV->isWeakForLinker());
1277 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
1278 SelectionDAG &DAG) {
1279 EVT PtrVT = getPointerTy();
1280 DebugLoc dl = Op.getDebugLoc();
1281 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1282 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1283 bool IsIndirect = GVIsIndirectSymbol(GV, RelocM);
1285 if (RelocM == Reloc::Static)
1286 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1288 unsigned PCAdj = (RelocM != Reloc::PIC_)
1289 ? 0 : (Subtarget->isThumb() ? 4 : 8);
1290 ARMCP::ARMCPKind Kind = IsIndirect ? ARMCP::CPNonLazyPtr
1292 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
1294 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1296 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1298 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
1299 SDValue Chain = Result.getValue(1);
1301 if (RelocM == Reloc::PIC_) {
1302 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1303 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1306 Result = DAG.getLoad(PtrVT, dl, Chain, Result, NULL, 0);
1311 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
1313 assert(Subtarget->isTargetELF() &&
1314 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
1315 EVT PtrVT = getPointerTy();
1316 DebugLoc dl = Op.getDebugLoc();
1317 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1318 ARMConstantPoolValue *CPV = new ARMConstantPoolValue("_GLOBAL_OFFSET_TABLE_",
1320 ARMCP::CPValue, PCAdj);
1321 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1322 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1323 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
1324 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1325 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1328 static SDValue LowerNeonVLDIntrinsic(SDValue Op, SelectionDAG &DAG,
1330 SDNode *Node = Op.getNode();
1331 EVT VT = Node->getValueType(0);
1332 DebugLoc dl = Op.getDebugLoc();
1334 if (!VT.is64BitVector())
1335 return SDValue(); // unimplemented
1337 SDValue Ops[] = { Node->getOperand(0),
1338 Node->getOperand(2) };
1339 return DAG.getNode(Opcode, dl, Node->getVTList(), Ops, 2);
1342 static SDValue LowerNeonVSTIntrinsic(SDValue Op, SelectionDAG &DAG,
1343 unsigned Opcode, unsigned NumVecs) {
1344 SDNode *Node = Op.getNode();
1345 EVT VT = Node->getOperand(3).getValueType();
1346 DebugLoc dl = Op.getDebugLoc();
1348 if (!VT.is64BitVector())
1349 return SDValue(); // unimplemented
1351 SmallVector<SDValue, 6> Ops;
1352 Ops.push_back(Node->getOperand(0));
1353 Ops.push_back(Node->getOperand(2));
1354 for (unsigned N = 0; N < NumVecs; ++N)
1355 Ops.push_back(Node->getOperand(N + 3));
1356 return DAG.getNode(Opcode, dl, MVT::Other, Ops.data(), Ops.size());
1360 ARMTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) {
1361 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1363 case Intrinsic::arm_neon_vld2:
1364 return LowerNeonVLDIntrinsic(Op, DAG, ARMISD::VLD2D);
1365 case Intrinsic::arm_neon_vld3:
1366 return LowerNeonVLDIntrinsic(Op, DAG, ARMISD::VLD3D);
1367 case Intrinsic::arm_neon_vld4:
1368 return LowerNeonVLDIntrinsic(Op, DAG, ARMISD::VLD4D);
1369 case Intrinsic::arm_neon_vst2:
1370 return LowerNeonVSTIntrinsic(Op, DAG, ARMISD::VST2D, 2);
1371 case Intrinsic::arm_neon_vst3:
1372 return LowerNeonVSTIntrinsic(Op, DAG, ARMISD::VST3D, 3);
1373 case Intrinsic::arm_neon_vst4:
1374 return LowerNeonVSTIntrinsic(Op, DAG, ARMISD::VST4D, 4);
1375 default: return SDValue(); // Don't custom lower most intrinsics.
1380 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
1381 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1382 DebugLoc dl = Op.getDebugLoc();
1384 default: return SDValue(); // Don't custom lower most intrinsics.
1385 case Intrinsic::arm_thread_pointer: {
1386 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1387 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1389 case Intrinsic::eh_sjlj_lsda: {
1390 // blah. horrible, horrible hack with the forced magic name.
1391 // really need to clean this up. It belongs in the target-independent
1392 // layer somehow that doesn't require the coupling with the asm
1394 MachineFunction &MF = DAG.getMachineFunction();
1395 EVT PtrVT = getPointerTy();
1396 DebugLoc dl = Op.getDebugLoc();
1397 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1399 unsigned PCAdj = (RelocM != Reloc::PIC_)
1400 ? 0 : (Subtarget->isThumb() ? 4 : 8);
1401 ARMCP::ARMCPKind Kind = ARMCP::CPValue;
1402 // Save off the LSDA name for the AsmPrinter to use when it's time
1403 // to emit the table
1404 std::string LSDAName = "L_lsda_";
1405 LSDAName += MF.getFunction()->getName();
1406 ARMConstantPoolValue *CPV =
1407 new ARMConstantPoolValue(LSDAName.c_str(), ARMPCLabelIndex, Kind, PCAdj);
1408 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1409 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1411 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
1412 SDValue Chain = Result.getValue(1);
1414 if (RelocM == Reloc::PIC_) {
1415 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1416 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1420 case Intrinsic::eh_sjlj_setjmp:
1421 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(1));
1425 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
1426 unsigned VarArgsFrameIndex) {
1427 // vastart just stores the address of the VarArgsFrameIndex slot into the
1428 // memory location argument.
1429 DebugLoc dl = Op.getDebugLoc();
1430 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1431 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1432 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1433 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
1437 ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) {
1438 SDNode *Node = Op.getNode();
1439 DebugLoc dl = Node->getDebugLoc();
1440 EVT VT = Node->getValueType(0);
1441 SDValue Chain = Op.getOperand(0);
1442 SDValue Size = Op.getOperand(1);
1443 SDValue Align = Op.getOperand(2);
1445 // Chain the dynamic stack allocation so that it doesn't modify the stack
1446 // pointer when other instructions are using the stack.
1447 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1449 unsigned AlignVal = cast<ConstantSDNode>(Align)->getZExtValue();
1450 unsigned StackAlign = getTargetMachine().getFrameInfo()->getStackAlignment();
1451 if (AlignVal > StackAlign)
1452 // Do this now since selection pass cannot introduce new target
1453 // independent node.
1454 Align = DAG.getConstant(-(uint64_t)AlignVal, VT);
1456 // In Thumb1 mode, there isn't a "sub r, sp, r" instruction, we will end up
1457 // using a "add r, sp, r" instead. Negate the size now so we don't have to
1458 // do even more horrible hack later.
1459 MachineFunction &MF = DAG.getMachineFunction();
1460 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1461 if (AFI->isThumb1OnlyFunction()) {
1463 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Size);
1465 uint32_t Val = C->getZExtValue();
1466 if (Val <= 508 && ((Val & 3) == 0))
1470 Size = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, VT), Size);
1473 SDVTList VTList = DAG.getVTList(VT, MVT::Other);
1474 SDValue Ops1[] = { Chain, Size, Align };
1475 SDValue Res = DAG.getNode(ARMISD::DYN_ALLOC, dl, VTList, Ops1, 3);
1476 Chain = Res.getValue(1);
1477 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1478 DAG.getIntPtrConstant(0, true), SDValue());
1479 SDValue Ops2[] = { Res, Chain };
1480 return DAG.getMergeValues(Ops2, 2, dl);
1484 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
1485 SDValue &Root, SelectionDAG &DAG,
1487 MachineFunction &MF = DAG.getMachineFunction();
1488 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1490 TargetRegisterClass *RC;
1491 if (AFI->isThumb1OnlyFunction())
1492 RC = ARM::tGPRRegisterClass;
1494 RC = ARM::GPRRegisterClass;
1496 // Transform the arguments stored in physical registers into virtual ones.
1497 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1498 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
1501 if (NextVA.isMemLoc()) {
1502 unsigned ArgSize = NextVA.getLocVT().getSizeInBits()/8;
1503 MachineFrameInfo *MFI = MF.getFrameInfo();
1504 int FI = MFI->CreateFixedObject(ArgSize, NextVA.getLocMemOffset());
1506 // Create load node to retrieve arguments from the stack.
1507 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1508 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN, NULL, 0);
1510 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
1511 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
1514 return DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, ArgValue, ArgValue2);
1518 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
1519 unsigned CallConv, bool isVarArg,
1520 const SmallVectorImpl<ISD::InputArg>
1522 DebugLoc dl, SelectionDAG &DAG,
1523 SmallVectorImpl<SDValue> &InVals) {
1525 MachineFunction &MF = DAG.getMachineFunction();
1526 MachineFrameInfo *MFI = MF.getFrameInfo();
1528 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1530 // Assign locations to all of the incoming arguments.
1531 SmallVector<CCValAssign, 16> ArgLocs;
1532 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1534 CCInfo.AnalyzeFormalArguments(Ins,
1535 CCAssignFnForNode(CallConv, /* Return*/ false,
1538 SmallVector<SDValue, 16> ArgValues;
1540 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1541 CCValAssign &VA = ArgLocs[i];
1543 // Arguments stored in registers.
1544 if (VA.isRegLoc()) {
1545 EVT RegVT = VA.getLocVT();
1548 if (VA.needsCustom()) {
1549 // f64 and vector types are split up into multiple registers or
1550 // combinations of registers and stack slots.
1553 if (VA.getLocVT() == MVT::v2f64) {
1554 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
1556 VA = ArgLocs[++i]; // skip ahead to next loc
1557 SDValue ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
1559 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1560 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
1561 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
1562 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
1563 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
1565 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
1568 TargetRegisterClass *RC;
1570 if (RegVT == MVT::f32)
1571 RC = ARM::SPRRegisterClass;
1572 else if (RegVT == MVT::f64)
1573 RC = ARM::DPRRegisterClass;
1574 else if (RegVT == MVT::v2f64)
1575 RC = ARM::QPRRegisterClass;
1576 else if (RegVT == MVT::i32)
1577 RC = (AFI->isThumb1OnlyFunction() ?
1578 ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
1580 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
1582 // Transform the arguments in physical registers into virtual ones.
1583 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1584 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1587 // If this is an 8 or 16-bit value, it is really passed promoted
1588 // to 32 bits. Insert an assert[sz]ext to capture this, then
1589 // truncate to the right size.
1590 switch (VA.getLocInfo()) {
1591 default: llvm_unreachable("Unknown loc info!");
1592 case CCValAssign::Full: break;
1593 case CCValAssign::BCvt:
1594 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1596 case CCValAssign::SExt:
1597 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1598 DAG.getValueType(VA.getValVT()));
1599 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1601 case CCValAssign::ZExt:
1602 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1603 DAG.getValueType(VA.getValVT()));
1604 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1608 InVals.push_back(ArgValue);
1610 } else { // VA.isRegLoc()
1613 assert(VA.isMemLoc());
1614 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
1616 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
1617 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset());
1619 // Create load nodes to retrieve arguments from the stack.
1620 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1621 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, NULL, 0));
1627 static const unsigned GPRArgRegs[] = {
1628 ARM::R0, ARM::R1, ARM::R2, ARM::R3
1631 unsigned NumGPRs = CCInfo.getFirstUnallocated
1632 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
1634 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1635 unsigned VARegSize = (4 - NumGPRs) * 4;
1636 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
1637 unsigned ArgOffset = 0;
1638 if (VARegSaveSize) {
1639 // If this function is vararg, store any remaining integer argument regs
1640 // to their spots on the stack so that they may be loaded by deferencing
1641 // the result of va_next.
1642 AFI->setVarArgsRegSaveSize(VARegSaveSize);
1643 ArgOffset = CCInfo.getNextStackOffset();
1644 VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset +
1645 VARegSaveSize - VARegSize);
1646 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
1648 SmallVector<SDValue, 4> MemOps;
1649 for (; NumGPRs < 4; ++NumGPRs) {
1650 TargetRegisterClass *RC;
1651 if (AFI->isThumb1OnlyFunction())
1652 RC = ARM::tGPRRegisterClass;
1654 RC = ARM::GPRRegisterClass;
1656 unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
1657 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
1658 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
1659 MemOps.push_back(Store);
1660 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
1661 DAG.getConstant(4, getPointerTy()));
1663 if (!MemOps.empty())
1664 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1665 &MemOps[0], MemOps.size());
1667 // This will point to the next argument passed via stack.
1668 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
1674 /// isFloatingPointZero - Return true if this is +0.0.
1675 static bool isFloatingPointZero(SDValue Op) {
1676 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1677 return CFP->getValueAPF().isPosZero();
1678 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1679 // Maybe this has already been legalized into the constant pool?
1680 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
1681 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
1682 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
1683 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1684 return CFP->getValueAPF().isPosZero();
1690 static bool isLegalCmpImmediate(unsigned C, bool isThumb1Only) {
1691 return ( isThumb1Only && (C & ~255U) == 0) ||
1692 (!isThumb1Only && ARM_AM::getSOImmVal(C) != -1);
1695 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
1696 /// the given operands.
1697 static SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1698 SDValue &ARMCC, SelectionDAG &DAG, bool isThumb1Only,
1700 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1701 unsigned C = RHSC->getZExtValue();
1702 if (!isLegalCmpImmediate(C, isThumb1Only)) {
1703 // Constant does not fit, try adjusting it by one?
1708 if (isLegalCmpImmediate(C-1, isThumb1Only)) {
1709 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1710 RHS = DAG.getConstant(C-1, MVT::i32);
1715 if (C > 0 && isLegalCmpImmediate(C-1, isThumb1Only)) {
1716 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1717 RHS = DAG.getConstant(C-1, MVT::i32);
1722 if (isLegalCmpImmediate(C+1, isThumb1Only)) {
1723 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1724 RHS = DAG.getConstant(C+1, MVT::i32);
1729 if (C < 0xffffffff && isLegalCmpImmediate(C+1, isThumb1Only)) {
1730 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1731 RHS = DAG.getConstant(C+1, MVT::i32);
1738 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
1739 ARMISD::NodeType CompareType;
1742 CompareType = ARMISD::CMP;
1747 CompareType = ARMISD::CMPZ;
1750 ARMCC = DAG.getConstant(CondCode, MVT::i32);
1751 return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS);
1754 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
1755 static SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
1758 if (!isFloatingPointZero(RHS))
1759 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS);
1761 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS);
1762 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp);
1765 static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
1766 const ARMSubtarget *ST) {
1767 EVT VT = Op.getValueType();
1768 SDValue LHS = Op.getOperand(0);
1769 SDValue RHS = Op.getOperand(1);
1770 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1771 SDValue TrueVal = Op.getOperand(2);
1772 SDValue FalseVal = Op.getOperand(3);
1773 DebugLoc dl = Op.getDebugLoc();
1775 if (LHS.getValueType() == MVT::i32) {
1777 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1778 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb1Only(), dl);
1779 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC, CCR,Cmp);
1782 ARMCC::CondCodes CondCode, CondCode2;
1783 if (FPCCToARMCC(CC, CondCode, CondCode2))
1784 std::swap(TrueVal, FalseVal);
1786 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
1787 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1788 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
1789 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
1791 if (CondCode2 != ARMCC::AL) {
1792 SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
1793 // FIXME: Needs another CMP because flag can have but one use.
1794 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
1795 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
1796 Result, TrueVal, ARMCC2, CCR, Cmp2);
1801 static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
1802 const ARMSubtarget *ST) {
1803 SDValue Chain = Op.getOperand(0);
1804 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1805 SDValue LHS = Op.getOperand(2);
1806 SDValue RHS = Op.getOperand(3);
1807 SDValue Dest = Op.getOperand(4);
1808 DebugLoc dl = Op.getDebugLoc();
1810 if (LHS.getValueType() == MVT::i32) {
1812 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1813 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb1Only(), dl);
1814 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
1815 Chain, Dest, ARMCC, CCR,Cmp);
1818 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
1819 ARMCC::CondCodes CondCode, CondCode2;
1820 if (FPCCToARMCC(CC, CondCode, CondCode2))
1821 // Swap the LHS/RHS of the comparison if needed.
1822 std::swap(LHS, RHS);
1824 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
1825 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
1826 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1827 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
1828 SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp };
1829 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
1830 if (CondCode2 != ARMCC::AL) {
1831 ARMCC = DAG.getConstant(CondCode2, MVT::i32);
1832 SDValue Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) };
1833 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
1838 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) {
1839 SDValue Chain = Op.getOperand(0);
1840 SDValue Table = Op.getOperand(1);
1841 SDValue Index = Op.getOperand(2);
1842 DebugLoc dl = Op.getDebugLoc();
1844 EVT PTy = getPointerTy();
1845 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
1846 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
1847 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
1848 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
1849 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
1850 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
1851 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
1852 if (Subtarget->isThumb2()) {
1853 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
1854 // which does another jump to the destination. This also makes it easier
1855 // to translate it to TBB / TBH later.
1856 // FIXME: This might not work if the function is extremely large.
1857 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
1858 Addr, Op.getOperand(2), JTI, UId);
1860 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1861 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr, NULL, 0);
1862 Chain = Addr.getValue(1);
1863 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
1864 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
1866 Addr = DAG.getLoad(PTy, dl, Chain, Addr, NULL, 0);
1867 Chain = Addr.getValue(1);
1868 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
1872 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1873 DebugLoc dl = Op.getDebugLoc();
1875 Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI;
1876 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
1877 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
1880 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1881 EVT VT = Op.getValueType();
1882 DebugLoc dl = Op.getDebugLoc();
1884 Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF;
1886 Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
1887 return DAG.getNode(Opc, dl, VT, Op);
1890 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
1891 // Implement fcopysign with a fabs and a conditional fneg.
1892 SDValue Tmp0 = Op.getOperand(0);
1893 SDValue Tmp1 = Op.getOperand(1);
1894 DebugLoc dl = Op.getDebugLoc();
1895 EVT VT = Op.getValueType();
1896 EVT SrcVT = Tmp1.getValueType();
1897 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
1898 SDValue Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG, dl);
1899 SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
1900 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1901 return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp);
1904 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
1905 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1906 MFI->setFrameAddressIsTaken(true);
1907 EVT VT = Op.getValueType();
1908 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
1909 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1910 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
1911 ? ARM::R7 : ARM::R11;
1912 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
1914 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0);
1919 ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
1921 SDValue Dst, SDValue Src,
1922 SDValue Size, unsigned Align,
1924 const Value *DstSV, uint64_t DstSVOff,
1925 const Value *SrcSV, uint64_t SrcSVOff){
1926 // Do repeated 4-byte loads and stores. To be improved.
1927 // This requires 4-byte alignment.
1928 if ((Align & 3) != 0)
1930 // This requires the copy size to be a constant, preferrably
1931 // within a subtarget-specific limit.
1932 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
1935 uint64_t SizeVal = ConstantSize->getZExtValue();
1936 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
1939 unsigned BytesLeft = SizeVal & 3;
1940 unsigned NumMemOps = SizeVal >> 2;
1941 unsigned EmittedNumMemOps = 0;
1943 unsigned VTSize = 4;
1945 const unsigned MAX_LOADS_IN_LDM = 6;
1946 SDValue TFOps[MAX_LOADS_IN_LDM];
1947 SDValue Loads[MAX_LOADS_IN_LDM];
1948 uint64_t SrcOff = 0, DstOff = 0;
1950 // Emit up to MAX_LOADS_IN_LDM loads, then a TokenFactor barrier, then the
1951 // same number of stores. The loads and stores will get combined into
1952 // ldm/stm later on.
1953 while (EmittedNumMemOps < NumMemOps) {
1955 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
1956 Loads[i] = DAG.getLoad(VT, dl, Chain,
1957 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
1958 DAG.getConstant(SrcOff, MVT::i32)),
1959 SrcSV, SrcSVOff + SrcOff);
1960 TFOps[i] = Loads[i].getValue(1);
1963 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
1966 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
1967 TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
1968 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
1969 DAG.getConstant(DstOff, MVT::i32)),
1970 DstSV, DstSVOff + DstOff);
1973 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
1975 EmittedNumMemOps += i;
1981 // Issue loads / stores for the trailing (1 - 3) bytes.
1982 unsigned BytesLeftSave = BytesLeft;
1985 if (BytesLeft >= 2) {
1993 Loads[i] = DAG.getLoad(VT, dl, Chain,
1994 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
1995 DAG.getConstant(SrcOff, MVT::i32)),
1996 SrcSV, SrcSVOff + SrcOff);
1997 TFOps[i] = Loads[i].getValue(1);
2000 BytesLeft -= VTSize;
2002 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
2005 BytesLeft = BytesLeftSave;
2007 if (BytesLeft >= 2) {
2015 TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
2016 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
2017 DAG.getConstant(DstOff, MVT::i32)),
2018 DstSV, DstSVOff + DstOff);
2021 BytesLeft -= VTSize;
2023 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
2026 static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
2027 SDValue Op = N->getOperand(0);
2028 DebugLoc dl = N->getDebugLoc();
2029 if (N->getValueType(0) == MVT::f64) {
2030 // Turn i64->f64 into FMDRR.
2031 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2032 DAG.getConstant(0, MVT::i32));
2033 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2034 DAG.getConstant(1, MVT::i32));
2035 return DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
2038 // Turn f64->i64 into FMRRD.
2039 SDValue Cvt = DAG.getNode(ARMISD::FMRRD, dl,
2040 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
2042 // Merge the pieces into a single i64 value.
2043 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
2046 /// getZeroVector - Returns a vector of specified type with all zero elements.
2048 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2049 assert(VT.isVector() && "Expected a vector type");
2051 // Zero vectors are used to represent vector negation and in those cases
2052 // will be implemented with the NEON VNEG instruction. However, VNEG does
2053 // not support i64 elements, so sometimes the zero vectors will need to be
2054 // explicitly constructed. For those cases, and potentially other uses in
2055 // the future, always build zero vectors as <4 x i32> or <2 x i32> bitcasted
2056 // to their dest type. This ensures they get CSE'd.
2058 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
2059 if (VT.getSizeInBits() == 64)
2060 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
2062 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
2064 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2067 /// getOnesVector - Returns a vector of specified type with all bits set.
2069 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2070 assert(VT.isVector() && "Expected a vector type");
2072 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2073 // type. This ensures they get CSE'd.
2075 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
2076 if (VT.getSizeInBits() == 64)
2077 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
2079 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
2081 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2084 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
2085 const ARMSubtarget *ST) {
2086 EVT VT = N->getValueType(0);
2087 DebugLoc dl = N->getDebugLoc();
2089 // Lower vector shifts on NEON to use VSHL.
2090 if (VT.isVector()) {
2091 assert(ST->hasNEON() && "unexpected vector shift");
2093 // Left shifts translate directly to the vshiftu intrinsic.
2094 if (N->getOpcode() == ISD::SHL)
2095 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2096 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
2097 N->getOperand(0), N->getOperand(1));
2099 assert((N->getOpcode() == ISD::SRA ||
2100 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
2102 // NEON uses the same intrinsics for both left and right shifts. For
2103 // right shifts, the shift amounts are negative, so negate the vector of
2105 EVT ShiftVT = N->getOperand(1).getValueType();
2106 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
2107 getZeroVector(ShiftVT, DAG, dl),
2109 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
2110 Intrinsic::arm_neon_vshifts :
2111 Intrinsic::arm_neon_vshiftu);
2112 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2113 DAG.getConstant(vshiftInt, MVT::i32),
2114 N->getOperand(0), NegatedCount);
2117 assert(VT == MVT::i64 &&
2118 (N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
2119 "Unknown shift to lower!");
2121 // We only lower SRA, SRL of 1 here, all others use generic lowering.
2122 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
2123 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
2126 // If we are in thumb mode, we don't have RRX.
2127 if (ST->isThumb1Only()) return SDValue();
2129 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
2130 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2131 DAG.getConstant(0, MVT::i32));
2132 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2133 DAG.getConstant(1, MVT::i32));
2135 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
2136 // captures the result into a carry flag.
2137 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
2138 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
2140 // The low part is an ARMISD::RRX operand, which shifts the carry in.
2141 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
2143 // Merge the pieces into a single i64 value.
2144 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
2147 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
2148 SDValue TmpOp0, TmpOp1;
2149 bool Invert = false;
2153 SDValue Op0 = Op.getOperand(0);
2154 SDValue Op1 = Op.getOperand(1);
2155 SDValue CC = Op.getOperand(2);
2156 EVT VT = Op.getValueType();
2157 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
2158 DebugLoc dl = Op.getDebugLoc();
2160 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
2161 switch (SetCCOpcode) {
2162 default: llvm_unreachable("Illegal FP comparison"); break;
2164 case ISD::SETNE: Invert = true; // Fallthrough
2166 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2168 case ISD::SETLT: Swap = true; // Fallthrough
2170 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2172 case ISD::SETLE: Swap = true; // Fallthrough
2174 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2175 case ISD::SETUGE: Swap = true; // Fallthrough
2176 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
2177 case ISD::SETUGT: Swap = true; // Fallthrough
2178 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
2179 case ISD::SETUEQ: Invert = true; // Fallthrough
2181 // Expand this to (OLT | OGT).
2185 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2186 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
2188 case ISD::SETUO: Invert = true; // Fallthrough
2190 // Expand this to (OLT | OGE).
2194 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2195 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
2199 // Integer comparisons.
2200 switch (SetCCOpcode) {
2201 default: llvm_unreachable("Illegal integer comparison"); break;
2202 case ISD::SETNE: Invert = true;
2203 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2204 case ISD::SETLT: Swap = true;
2205 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2206 case ISD::SETLE: Swap = true;
2207 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2208 case ISD::SETULT: Swap = true;
2209 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
2210 case ISD::SETULE: Swap = true;
2211 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
2214 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
2215 if (Opc == ARMISD::VCEQ) {
2218 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
2220 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
2223 // Ignore bitconvert.
2224 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BIT_CONVERT)
2225 AndOp = AndOp.getOperand(0);
2227 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
2229 Op0 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(0));
2230 Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(1));
2237 std::swap(Op0, Op1);
2239 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
2242 Result = DAG.getNOT(dl, Result, VT);
2247 /// isVMOVSplat - Check if the specified splat value corresponds to an immediate
2248 /// VMOV instruction, and if so, return the constant being splatted.
2249 static SDValue isVMOVSplat(uint64_t SplatBits, uint64_t SplatUndef,
2250 unsigned SplatBitSize, SelectionDAG &DAG) {
2251 switch (SplatBitSize) {
2253 // Any 1-byte value is OK.
2254 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
2255 return DAG.getTargetConstant(SplatBits, MVT::i8);
2258 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
2259 if ((SplatBits & ~0xff) == 0 ||
2260 (SplatBits & ~0xff00) == 0)
2261 return DAG.getTargetConstant(SplatBits, MVT::i16);
2265 // NEON's 32-bit VMOV supports splat values where:
2266 // * only one byte is nonzero, or
2267 // * the least significant byte is 0xff and the second byte is nonzero, or
2268 // * the least significant 2 bytes are 0xff and the third is nonzero.
2269 if ((SplatBits & ~0xff) == 0 ||
2270 (SplatBits & ~0xff00) == 0 ||
2271 (SplatBits & ~0xff0000) == 0 ||
2272 (SplatBits & ~0xff000000) == 0)
2273 return DAG.getTargetConstant(SplatBits, MVT::i32);
2275 if ((SplatBits & ~0xffff) == 0 &&
2276 ((SplatBits | SplatUndef) & 0xff) == 0xff)
2277 return DAG.getTargetConstant(SplatBits | 0xff, MVT::i32);
2279 if ((SplatBits & ~0xffffff) == 0 &&
2280 ((SplatBits | SplatUndef) & 0xffff) == 0xffff)
2281 return DAG.getTargetConstant(SplatBits | 0xffff, MVT::i32);
2283 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
2284 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
2285 // VMOV.I32. A (very) minor optimization would be to replicate the value
2286 // and fall through here to test for a valid 64-bit splat. But, then the
2287 // caller would also need to check and handle the change in size.
2291 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
2292 uint64_t BitMask = 0xff;
2294 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
2295 if (((SplatBits | SplatUndef) & BitMask) == BitMask)
2297 else if ((SplatBits & BitMask) != 0)
2301 return DAG.getTargetConstant(Val, MVT::i64);
2305 llvm_unreachable("unexpected size for isVMOVSplat");
2312 /// getVMOVImm - If this is a build_vector of constants which can be
2313 /// formed by using a VMOV instruction of the specified element size,
2314 /// return the constant being splatted. The ByteSize field indicates the
2315 /// number of bytes of each element [1248].
2316 SDValue ARM::getVMOVImm(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
2317 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N);
2318 APInt SplatBits, SplatUndef;
2319 unsigned SplatBitSize;
2321 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
2322 HasAnyUndefs, ByteSize * 8))
2325 if (SplatBitSize > ByteSize * 8)
2328 return isVMOVSplat(SplatBits.getZExtValue(), SplatUndef.getZExtValue(),
2332 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
2333 /// instruction with the specified blocksize. (The order of the elements
2334 /// within each block of the vector is reversed.)
2335 bool ARM::isVREVMask(ShuffleVectorSDNode *N, unsigned BlockSize) {
2336 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
2337 "Only possible block sizes for VREV are: 16, 32, 64");
2339 EVT VT = N->getValueType(0);
2340 unsigned NumElts = VT.getVectorNumElements();
2341 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2342 unsigned BlockElts = N->getMaskElt(0) + 1;
2344 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
2347 for (unsigned i = 0; i < NumElts; ++i) {
2348 if ((unsigned) N->getMaskElt(i) !=
2349 (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
2356 static SDValue BuildSplat(SDValue Val, EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2357 // Canonicalize all-zeros and all-ones vectors.
2358 ConstantSDNode *ConstVal = dyn_cast<ConstantSDNode>(Val.getNode());
2359 if (ConstVal->isNullValue())
2360 return getZeroVector(VT, DAG, dl);
2361 if (ConstVal->isAllOnesValue())
2362 return getOnesVector(VT, DAG, dl);
2365 if (VT.is64BitVector()) {
2366 switch (Val.getValueType().getSizeInBits()) {
2367 case 8: CanonicalVT = MVT::v8i8; break;
2368 case 16: CanonicalVT = MVT::v4i16; break;
2369 case 32: CanonicalVT = MVT::v2i32; break;
2370 case 64: CanonicalVT = MVT::v1i64; break;
2371 default: llvm_unreachable("unexpected splat element type"); break;
2374 assert(VT.is128BitVector() && "unknown splat vector size");
2375 switch (Val.getValueType().getSizeInBits()) {
2376 case 8: CanonicalVT = MVT::v16i8; break;
2377 case 16: CanonicalVT = MVT::v8i16; break;
2378 case 32: CanonicalVT = MVT::v4i32; break;
2379 case 64: CanonicalVT = MVT::v2i64; break;
2380 default: llvm_unreachable("unexpected splat element type"); break;
2384 // Build a canonical splat for this value.
2385 SmallVector<SDValue, 8> Ops;
2386 Ops.assign(CanonicalVT.getVectorNumElements(), Val);
2387 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, &Ops[0],
2389 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Res);
2392 // If this is a case we can't handle, return null and let the default
2393 // expansion code take care of it.
2394 static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
2395 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
2396 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
2397 DebugLoc dl = Op.getDebugLoc();
2398 EVT VT = Op.getValueType();
2400 APInt SplatBits, SplatUndef;
2401 unsigned SplatBitSize;
2403 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
2404 SDValue Val = isVMOVSplat(SplatBits.getZExtValue(),
2405 SplatUndef.getZExtValue(), SplatBitSize, DAG);
2407 return BuildSplat(Val, VT, DAG, dl);
2410 // If there are only 2 elements in a 128-bit vector, insert them into an
2411 // undef vector. This handles the common case for 128-bit vector argument
2412 // passing, where the insertions should be translated to subreg accesses
2413 // with no real instructions.
2414 if (VT.is128BitVector() && Op.getNumOperands() == 2) {
2415 SDValue Val = DAG.getUNDEF(VT);
2416 SDValue Op0 = Op.getOperand(0);
2417 SDValue Op1 = Op.getOperand(1);
2418 if (Op0.getOpcode() != ISD::UNDEF)
2419 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, Op0,
2420 DAG.getIntPtrConstant(0));
2421 if (Op1.getOpcode() != ISD::UNDEF)
2422 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, Op1,
2423 DAG.getIntPtrConstant(1));
2430 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
2434 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
2438 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
2439 EVT VT = Op.getValueType();
2440 DebugLoc dl = Op.getDebugLoc();
2441 assert((VT == MVT::i8 || VT == MVT::i16) &&
2442 "unexpected type for custom-lowering vector extract");
2443 SDValue Vec = Op.getOperand(0);
2444 SDValue Lane = Op.getOperand(1);
2445 Op = DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
2446 Op = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Op, DAG.getValueType(VT));
2447 return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
2450 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
2451 // The only time a CONCAT_VECTORS operation can have legal types is when
2452 // two 64-bit vectors are concatenated to a 128-bit vector.
2453 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
2454 "unexpected CONCAT_VECTORS");
2455 DebugLoc dl = Op.getDebugLoc();
2456 SDValue Val = DAG.getUNDEF(MVT::v2f64);
2457 SDValue Op0 = Op.getOperand(0);
2458 SDValue Op1 = Op.getOperand(1);
2459 if (Op0.getOpcode() != ISD::UNDEF)
2460 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
2461 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op0),
2462 DAG.getIntPtrConstant(0));
2463 if (Op1.getOpcode() != ISD::UNDEF)
2464 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
2465 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op1),
2466 DAG.getIntPtrConstant(1));
2467 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Val);
2470 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
2471 switch (Op.getOpcode()) {
2472 default: llvm_unreachable("Don't know how to custom lower this!");
2473 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2474 case ISD::GlobalAddress:
2475 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
2476 LowerGlobalAddressELF(Op, DAG);
2477 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
2478 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, Subtarget);
2479 case ISD::BR_CC: return LowerBR_CC(Op, DAG, Subtarget);
2480 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
2481 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
2482 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex);
2483 case ISD::SINT_TO_FP:
2484 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
2485 case ISD::FP_TO_SINT:
2486 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
2487 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
2488 case ISD::RETURNADDR: break;
2489 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
2490 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
2491 case ISD::INTRINSIC_VOID:
2492 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
2493 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2494 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(Op.getNode(), DAG);
2497 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
2498 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
2499 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
2500 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
2501 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
2502 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
2503 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
2508 /// ReplaceNodeResults - Replace the results of node with an illegal result
2509 /// type with new values built out of custom code.
2510 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
2511 SmallVectorImpl<SDValue>&Results,
2512 SelectionDAG &DAG) {
2513 switch (N->getOpcode()) {
2515 llvm_unreachable("Don't know how to custom expand this!");
2517 case ISD::BIT_CONVERT:
2518 Results.push_back(ExpandBIT_CONVERT(N, DAG));
2522 SDValue Res = LowerShift(N, DAG, Subtarget);
2524 Results.push_back(Res);
2530 //===----------------------------------------------------------------------===//
2531 // ARM Scheduler Hooks
2532 //===----------------------------------------------------------------------===//
2535 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
2536 MachineBasicBlock *BB) const {
2537 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2538 DebugLoc dl = MI->getDebugLoc();
2539 switch (MI->getOpcode()) {
2541 llvm_unreachable("Unexpected instr type to insert");
2542 case ARM::tMOVCCr: {
2543 // To "insert" a SELECT_CC instruction, we actually have to insert the
2544 // diamond control-flow pattern. The incoming instruction knows the
2545 // destination vreg to set, the condition code register to branch on, the
2546 // true/false values to select between, and a branch opcode to use.
2547 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2548 MachineFunction::iterator It = BB;
2554 // cmpTY ccX, r1, r2
2556 // fallthrough --> copy0MBB
2557 MachineBasicBlock *thisMBB = BB;
2558 MachineFunction *F = BB->getParent();
2559 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
2560 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
2561 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
2562 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
2563 F->insert(It, copy0MBB);
2564 F->insert(It, sinkMBB);
2565 // Update machine-CFG edges by first adding all successors of the current
2566 // block to the new block which will contain the Phi node for the select.
2567 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
2568 e = BB->succ_end(); i != e; ++i)
2569 sinkMBB->addSuccessor(*i);
2570 // Next, remove all successors of the current block, and add the true
2571 // and fallthrough blocks as its successors.
2572 while(!BB->succ_empty())
2573 BB->removeSuccessor(BB->succ_begin());
2574 BB->addSuccessor(copy0MBB);
2575 BB->addSuccessor(sinkMBB);
2578 // %FalseValue = ...
2579 // # fallthrough to sinkMBB
2582 // Update machine-CFG edges
2583 BB->addSuccessor(sinkMBB);
2586 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
2589 BuildMI(BB, dl, TII->get(ARM::PHI), MI->getOperand(0).getReg())
2590 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
2591 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
2593 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
2600 case ARM::t2SUBrSPi_:
2601 case ARM::t2SUBrSPi12_:
2602 case ARM::t2SUBrSPs_: {
2603 MachineFunction *MF = BB->getParent();
2604 unsigned DstReg = MI->getOperand(0).getReg();
2605 unsigned SrcReg = MI->getOperand(1).getReg();
2606 bool DstIsDead = MI->getOperand(0).isDead();
2607 bool SrcIsKill = MI->getOperand(1).isKill();
2609 if (SrcReg != ARM::SP) {
2610 // Copy the source to SP from virtual register.
2611 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(SrcReg);
2612 unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
2613 ? ARM::tMOVtgpr2gpr : ARM::tMOVgpr2gpr;
2614 BuildMI(BB, dl, TII->get(CopyOpc), ARM::SP)
2615 .addReg(SrcReg, getKillRegState(SrcIsKill));
2619 bool NeedPred = false, NeedCC = false, NeedOp3 = false;
2620 switch (MI->getOpcode()) {
2622 llvm_unreachable("Unexpected pseudo instruction!");
2628 OpOpc = ARM::tADDspr;
2631 OpOpc = ARM::tSUBspi;
2633 case ARM::t2SUBrSPi_:
2634 OpOpc = ARM::t2SUBrSPi;
2635 NeedPred = true; NeedCC = true;
2637 case ARM::t2SUBrSPi12_:
2638 OpOpc = ARM::t2SUBrSPi12;
2641 case ARM::t2SUBrSPs_:
2642 OpOpc = ARM::t2SUBrSPs;
2643 NeedPred = true; NeedCC = true; NeedOp3 = true;
2646 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(OpOpc), ARM::SP);
2647 if (OpOpc == ARM::tAND)
2648 AddDefaultT1CC(MIB);
2649 MIB.addReg(ARM::SP);
2650 MIB.addOperand(MI->getOperand(2));
2652 MIB.addOperand(MI->getOperand(3));
2654 AddDefaultPred(MIB);
2658 // Copy the result from SP to virtual register.
2659 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(DstReg);
2660 unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
2661 ? ARM::tMOVgpr2tgpr : ARM::tMOVgpr2gpr;
2662 BuildMI(BB, dl, TII->get(CopyOpc))
2663 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead))
2665 MF->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
2671 //===----------------------------------------------------------------------===//
2672 // ARM Optimization Hooks
2673 //===----------------------------------------------------------------------===//
2676 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
2677 TargetLowering::DAGCombinerInfo &DCI) {
2678 SelectionDAG &DAG = DCI.DAG;
2679 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2680 EVT VT = N->getValueType(0);
2681 unsigned Opc = N->getOpcode();
2682 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
2683 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
2684 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
2685 ISD::CondCode CC = ISD::SETCC_INVALID;
2688 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
2690 SDValue CCOp = Slct.getOperand(0);
2691 if (CCOp.getOpcode() == ISD::SETCC)
2692 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
2695 bool DoXform = false;
2697 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
2700 if (LHS.getOpcode() == ISD::Constant &&
2701 cast<ConstantSDNode>(LHS)->isNullValue()) {
2703 } else if (CC != ISD::SETCC_INVALID &&
2704 RHS.getOpcode() == ISD::Constant &&
2705 cast<ConstantSDNode>(RHS)->isNullValue()) {
2706 std::swap(LHS, RHS);
2707 SDValue Op0 = Slct.getOperand(0);
2708 EVT OpVT = isSlctCC ? Op0.getValueType() :
2709 Op0.getOperand(0).getValueType();
2710 bool isInt = OpVT.isInteger();
2711 CC = ISD::getSetCCInverse(CC, isInt);
2713 if (!TLI.isCondCodeLegal(CC, OpVT))
2714 return SDValue(); // Inverse operator isn't legal.
2721 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
2723 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
2724 Slct.getOperand(0), Slct.getOperand(1), CC);
2725 SDValue CCOp = Slct.getOperand(0);
2727 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
2728 CCOp.getOperand(0), CCOp.getOperand(1), CC);
2729 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
2730 CCOp, OtherOp, Result);
2735 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
2736 static SDValue PerformADDCombine(SDNode *N,
2737 TargetLowering::DAGCombinerInfo &DCI) {
2738 // added by evan in r37685 with no testcase.
2739 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2741 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
2742 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
2743 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
2744 if (Result.getNode()) return Result;
2746 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
2747 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
2748 if (Result.getNode()) return Result;
2754 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
2755 static SDValue PerformSUBCombine(SDNode *N,
2756 TargetLowering::DAGCombinerInfo &DCI) {
2757 // added by evan in r37685 with no testcase.
2758 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2760 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
2761 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
2762 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
2763 if (Result.getNode()) return Result;
2770 /// PerformFMRRDCombine - Target-specific dag combine xforms for ARMISD::FMRRD.
2771 static SDValue PerformFMRRDCombine(SDNode *N,
2772 TargetLowering::DAGCombinerInfo &DCI) {
2773 // fmrrd(fmdrr x, y) -> x,y
2774 SDValue InDouble = N->getOperand(0);
2775 if (InDouble.getOpcode() == ARMISD::FMDRR)
2776 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
2780 /// getVShiftImm - Check if this is a valid build_vector for the immediate
2781 /// operand of a vector shift operation, where all the elements of the
2782 /// build_vector must have the same constant integer value.
2783 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
2784 // Ignore bit_converts.
2785 while (Op.getOpcode() == ISD::BIT_CONVERT)
2786 Op = Op.getOperand(0);
2787 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
2788 APInt SplatBits, SplatUndef;
2789 unsigned SplatBitSize;
2791 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
2792 HasAnyUndefs, ElementBits) ||
2793 SplatBitSize > ElementBits)
2795 Cnt = SplatBits.getSExtValue();
2799 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
2800 /// operand of a vector shift left operation. That value must be in the range:
2801 /// 0 <= Value < ElementBits for a left shift; or
2802 /// 0 <= Value <= ElementBits for a long left shift.
2803 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
2804 assert(VT.isVector() && "vector shift count is not a vector type");
2805 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
2806 if (! getVShiftImm(Op, ElementBits, Cnt))
2808 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
2811 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
2812 /// operand of a vector shift right operation. For a shift opcode, the value
2813 /// is positive, but for an intrinsic the value count must be negative. The
2814 /// absolute value must be in the range:
2815 /// 1 <= |Value| <= ElementBits for a right shift; or
2816 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
2817 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
2819 assert(VT.isVector() && "vector shift count is not a vector type");
2820 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
2821 if (! getVShiftImm(Op, ElementBits, Cnt))
2825 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
2828 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
2829 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
2830 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
2833 // Don't do anything for most intrinsics.
2836 // Vector shifts: check for immediate versions and lower them.
2837 // Note: This is done during DAG combining instead of DAG legalizing because
2838 // the build_vectors for 64-bit vector element shift counts are generally
2839 // not legal, and it is hard to see their values after they get legalized to
2840 // loads from a constant pool.
2841 case Intrinsic::arm_neon_vshifts:
2842 case Intrinsic::arm_neon_vshiftu:
2843 case Intrinsic::arm_neon_vshiftls:
2844 case Intrinsic::arm_neon_vshiftlu:
2845 case Intrinsic::arm_neon_vshiftn:
2846 case Intrinsic::arm_neon_vrshifts:
2847 case Intrinsic::arm_neon_vrshiftu:
2848 case Intrinsic::arm_neon_vrshiftn:
2849 case Intrinsic::arm_neon_vqshifts:
2850 case Intrinsic::arm_neon_vqshiftu:
2851 case Intrinsic::arm_neon_vqshiftsu:
2852 case Intrinsic::arm_neon_vqshiftns:
2853 case Intrinsic::arm_neon_vqshiftnu:
2854 case Intrinsic::arm_neon_vqshiftnsu:
2855 case Intrinsic::arm_neon_vqrshiftns:
2856 case Intrinsic::arm_neon_vqrshiftnu:
2857 case Intrinsic::arm_neon_vqrshiftnsu: {
2858 EVT VT = N->getOperand(1).getValueType();
2860 unsigned VShiftOpc = 0;
2863 case Intrinsic::arm_neon_vshifts:
2864 case Intrinsic::arm_neon_vshiftu:
2865 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
2866 VShiftOpc = ARMISD::VSHL;
2869 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
2870 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
2871 ARMISD::VSHRs : ARMISD::VSHRu);
2876 case Intrinsic::arm_neon_vshiftls:
2877 case Intrinsic::arm_neon_vshiftlu:
2878 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
2880 llvm_unreachable("invalid shift count for vshll intrinsic");
2882 case Intrinsic::arm_neon_vrshifts:
2883 case Intrinsic::arm_neon_vrshiftu:
2884 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
2888 case Intrinsic::arm_neon_vqshifts:
2889 case Intrinsic::arm_neon_vqshiftu:
2890 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
2894 case Intrinsic::arm_neon_vqshiftsu:
2895 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
2897 llvm_unreachable("invalid shift count for vqshlu intrinsic");
2899 case Intrinsic::arm_neon_vshiftn:
2900 case Intrinsic::arm_neon_vrshiftn:
2901 case Intrinsic::arm_neon_vqshiftns:
2902 case Intrinsic::arm_neon_vqshiftnu:
2903 case Intrinsic::arm_neon_vqshiftnsu:
2904 case Intrinsic::arm_neon_vqrshiftns:
2905 case Intrinsic::arm_neon_vqrshiftnu:
2906 case Intrinsic::arm_neon_vqrshiftnsu:
2907 // Narrowing shifts require an immediate right shift.
2908 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
2910 llvm_unreachable("invalid shift count for narrowing vector shift intrinsic");
2913 llvm_unreachable("unhandled vector shift");
2917 case Intrinsic::arm_neon_vshifts:
2918 case Intrinsic::arm_neon_vshiftu:
2919 // Opcode already set above.
2921 case Intrinsic::arm_neon_vshiftls:
2922 case Intrinsic::arm_neon_vshiftlu:
2923 if (Cnt == VT.getVectorElementType().getSizeInBits())
2924 VShiftOpc = ARMISD::VSHLLi;
2926 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
2927 ARMISD::VSHLLs : ARMISD::VSHLLu);
2929 case Intrinsic::arm_neon_vshiftn:
2930 VShiftOpc = ARMISD::VSHRN; break;
2931 case Intrinsic::arm_neon_vrshifts:
2932 VShiftOpc = ARMISD::VRSHRs; break;
2933 case Intrinsic::arm_neon_vrshiftu:
2934 VShiftOpc = ARMISD::VRSHRu; break;
2935 case Intrinsic::arm_neon_vrshiftn:
2936 VShiftOpc = ARMISD::VRSHRN; break;
2937 case Intrinsic::arm_neon_vqshifts:
2938 VShiftOpc = ARMISD::VQSHLs; break;
2939 case Intrinsic::arm_neon_vqshiftu:
2940 VShiftOpc = ARMISD::VQSHLu; break;
2941 case Intrinsic::arm_neon_vqshiftsu:
2942 VShiftOpc = ARMISD::VQSHLsu; break;
2943 case Intrinsic::arm_neon_vqshiftns:
2944 VShiftOpc = ARMISD::VQSHRNs; break;
2945 case Intrinsic::arm_neon_vqshiftnu:
2946 VShiftOpc = ARMISD::VQSHRNu; break;
2947 case Intrinsic::arm_neon_vqshiftnsu:
2948 VShiftOpc = ARMISD::VQSHRNsu; break;
2949 case Intrinsic::arm_neon_vqrshiftns:
2950 VShiftOpc = ARMISD::VQRSHRNs; break;
2951 case Intrinsic::arm_neon_vqrshiftnu:
2952 VShiftOpc = ARMISD::VQRSHRNu; break;
2953 case Intrinsic::arm_neon_vqrshiftnsu:
2954 VShiftOpc = ARMISD::VQRSHRNsu; break;
2957 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
2958 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
2961 case Intrinsic::arm_neon_vshiftins: {
2962 EVT VT = N->getOperand(1).getValueType();
2964 unsigned VShiftOpc = 0;
2966 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
2967 VShiftOpc = ARMISD::VSLI;
2968 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
2969 VShiftOpc = ARMISD::VSRI;
2971 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
2974 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
2975 N->getOperand(1), N->getOperand(2),
2976 DAG.getConstant(Cnt, MVT::i32));
2979 case Intrinsic::arm_neon_vqrshifts:
2980 case Intrinsic::arm_neon_vqrshiftu:
2981 // No immediate versions of these to check for.
2988 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
2989 /// lowers them. As with the vector shift intrinsics, this is done during DAG
2990 /// combining instead of DAG legalizing because the build_vectors for 64-bit
2991 /// vector element shift counts are generally not legal, and it is hard to see
2992 /// their values after they get legalized to loads from a constant pool.
2993 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
2994 const ARMSubtarget *ST) {
2995 EVT VT = N->getValueType(0);
2997 // Nothing to be done for scalar shifts.
2998 if (! VT.isVector())
3001 assert(ST->hasNEON() && "unexpected vector shift");
3004 switch (N->getOpcode()) {
3005 default: llvm_unreachable("unexpected shift opcode");
3008 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
3009 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
3010 DAG.getConstant(Cnt, MVT::i32));
3015 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
3016 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
3017 ARMISD::VSHRs : ARMISD::VSHRu);
3018 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
3019 DAG.getConstant(Cnt, MVT::i32));
3025 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
3026 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
3027 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
3028 const ARMSubtarget *ST) {
3029 SDValue N0 = N->getOperand(0);
3031 // Check for sign- and zero-extensions of vector extract operations of 8-
3032 // and 16-bit vector elements. NEON supports these directly. They are
3033 // handled during DAG combining because type legalization will promote them
3034 // to 32-bit types and it is messy to recognize the operations after that.
3035 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
3036 SDValue Vec = N0.getOperand(0);
3037 SDValue Lane = N0.getOperand(1);
3038 EVT VT = N->getValueType(0);
3039 EVT EltVT = N0.getValueType();
3040 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3042 if (VT == MVT::i32 &&
3043 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
3044 TLI.isTypeLegal(Vec.getValueType())) {
3047 switch (N->getOpcode()) {
3048 default: llvm_unreachable("unexpected opcode");
3049 case ISD::SIGN_EXTEND:
3050 Opc = ARMISD::VGETLANEs;
3052 case ISD::ZERO_EXTEND:
3053 case ISD::ANY_EXTEND:
3054 Opc = ARMISD::VGETLANEu;
3057 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
3064 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
3065 DAGCombinerInfo &DCI) const {
3066 switch (N->getOpcode()) {
3068 case ISD::ADD: return PerformADDCombine(N, DCI);
3069 case ISD::SUB: return PerformSUBCombine(N, DCI);
3070 case ARMISD::FMRRD: return PerformFMRRDCombine(N, DCI);
3071 case ISD::INTRINSIC_WO_CHAIN:
3072 return PerformIntrinsicCombine(N, DCI.DAG);
3076 return PerformShiftCombine(N, DCI.DAG, Subtarget);
3077 case ISD::SIGN_EXTEND:
3078 case ISD::ZERO_EXTEND:
3079 case ISD::ANY_EXTEND:
3080 return PerformExtendCombine(N, DCI.DAG, Subtarget);
3085 /// isLegalAddressImmediate - Return true if the integer value can be used
3086 /// as the offset of the target addressing mode for load / store of the
3088 static bool isLegalAddressImmediate(int64_t V, EVT VT,
3089 const ARMSubtarget *Subtarget) {
3096 if (Subtarget->isThumb()) { // FIXME for thumb2
3101 switch (VT.getSimpleVT().SimpleTy) {
3102 default: return false;
3117 if ((V & (Scale - 1)) != 0)
3120 return V == (V & ((1LL << 5) - 1));
3125 switch (VT.getSimpleVT().SimpleTy) {
3126 default: return false;
3131 return V == (V & ((1LL << 12) - 1));
3134 return V == (V & ((1LL << 8) - 1));
3137 if (!Subtarget->hasVFP2())
3142 return V == (V & ((1LL << 8) - 1));
3146 /// isLegalAddressingMode - Return true if the addressing mode represented
3147 /// by AM is legal for this target, for a load/store of the specified type.
3148 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
3149 const Type *Ty) const {
3150 EVT VT = getValueType(Ty, true);
3151 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
3154 // Can never fold addr of global into load/store.
3159 case 0: // no scale reg, must be "r+i" or "r", or "i".
3162 if (Subtarget->isThumb()) // FIXME for thumb2
3166 // ARM doesn't support any R+R*scale+imm addr modes.
3173 int Scale = AM.Scale;
3174 switch (VT.getSimpleVT().SimpleTy) {
3175 default: return false;
3180 // This assumes i64 is legalized to a pair of i32. If not (i.e.
3181 // ldrd / strd are used, then its address mode is same as i16.
3183 if (Scale < 0) Scale = -Scale;
3187 return isPowerOf2_32(Scale & ~1);
3190 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
3195 // Note, we allow "void" uses (basically, uses that aren't loads or
3196 // stores), because arm allows folding a scale into many arithmetic
3197 // operations. This should be made more precise and revisited later.
3199 // Allow r << imm, but the imm has to be a multiple of two.
3200 if (AM.Scale & 1) return false;
3201 return isPowerOf2_32(AM.Scale);
3208 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
3209 bool isSEXTLoad, SDValue &Base,
3210 SDValue &Offset, bool &isInc,
3211 SelectionDAG &DAG) {
3212 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
3215 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
3217 Base = Ptr->getOperand(0);
3218 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
3219 int RHSC = (int)RHS->getZExtValue();
3220 if (RHSC < 0 && RHSC > -256) {
3221 assert(Ptr->getOpcode() == ISD::ADD);
3223 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
3227 isInc = (Ptr->getOpcode() == ISD::ADD);
3228 Offset = Ptr->getOperand(1);
3230 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
3232 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
3233 int RHSC = (int)RHS->getZExtValue();
3234 if (RHSC < 0 && RHSC > -0x1000) {
3235 assert(Ptr->getOpcode() == ISD::ADD);
3237 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
3238 Base = Ptr->getOperand(0);
3243 if (Ptr->getOpcode() == ISD::ADD) {
3245 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
3246 if (ShOpcVal != ARM_AM::no_shift) {
3247 Base = Ptr->getOperand(1);
3248 Offset = Ptr->getOperand(0);
3250 Base = Ptr->getOperand(0);
3251 Offset = Ptr->getOperand(1);
3256 isInc = (Ptr->getOpcode() == ISD::ADD);
3257 Base = Ptr->getOperand(0);
3258 Offset = Ptr->getOperand(1);
3262 // FIXME: Use FLDM / FSTM to emulate indexed FP load / store.
3266 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
3267 bool isSEXTLoad, SDValue &Base,
3268 SDValue &Offset, bool &isInc,
3269 SelectionDAG &DAG) {
3270 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
3273 Base = Ptr->getOperand(0);
3274 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
3275 int RHSC = (int)RHS->getZExtValue();
3276 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
3277 assert(Ptr->getOpcode() == ISD::ADD);
3279 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
3281 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
3282 isInc = Ptr->getOpcode() == ISD::ADD;
3283 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
3291 /// getPreIndexedAddressParts - returns true by value, base pointer and
3292 /// offset pointer and addressing mode by reference if the node's address
3293 /// can be legally represented as pre-indexed load / store address.
3295 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
3297 ISD::MemIndexedMode &AM,
3298 SelectionDAG &DAG) const {
3299 if (Subtarget->isThumb1Only())
3304 bool isSEXTLoad = false;
3305 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3306 Ptr = LD->getBasePtr();
3307 VT = LD->getMemoryVT();
3308 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
3309 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3310 Ptr = ST->getBasePtr();
3311 VT = ST->getMemoryVT();
3316 bool isLegal = false;
3317 if (Subtarget->isThumb() && Subtarget->hasThumb2())
3318 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
3319 Offset, isInc, DAG);
3321 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
3322 Offset, isInc, DAG);
3326 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
3330 /// getPostIndexedAddressParts - returns true by value, base pointer and
3331 /// offset pointer and addressing mode by reference if this node can be
3332 /// combined with a load / store to form a post-indexed load / store.
3333 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
3336 ISD::MemIndexedMode &AM,
3337 SelectionDAG &DAG) const {
3338 if (Subtarget->isThumb1Only())
3343 bool isSEXTLoad = false;
3344 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3345 VT = LD->getMemoryVT();
3346 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
3347 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3348 VT = ST->getMemoryVT();
3353 bool isLegal = false;
3354 if (Subtarget->isThumb() && Subtarget->hasThumb2())
3355 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
3358 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
3363 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
3367 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
3371 const SelectionDAG &DAG,
3372 unsigned Depth) const {
3373 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
3374 switch (Op.getOpcode()) {
3376 case ARMISD::CMOV: {
3377 // Bits are known zero/one if known on the LHS and RHS.
3378 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
3379 if (KnownZero == 0 && KnownOne == 0) return;
3381 APInt KnownZeroRHS, KnownOneRHS;
3382 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
3383 KnownZeroRHS, KnownOneRHS, Depth+1);
3384 KnownZero &= KnownZeroRHS;
3385 KnownOne &= KnownOneRHS;
3391 //===----------------------------------------------------------------------===//
3392 // ARM Inline Assembly Support
3393 //===----------------------------------------------------------------------===//
3395 /// getConstraintType - Given a constraint letter, return the type of
3396 /// constraint it is for this target.
3397 ARMTargetLowering::ConstraintType
3398 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
3399 if (Constraint.size() == 1) {
3400 switch (Constraint[0]) {
3402 case 'l': return C_RegisterClass;
3403 case 'w': return C_RegisterClass;
3406 return TargetLowering::getConstraintType(Constraint);
3409 std::pair<unsigned, const TargetRegisterClass*>
3410 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
3412 if (Constraint.size() == 1) {
3413 // GCC RS6000 Constraint Letters
3414 switch (Constraint[0]) {
3416 if (Subtarget->isThumb1Only())
3417 return std::make_pair(0U, ARM::tGPRRegisterClass);
3419 return std::make_pair(0U, ARM::GPRRegisterClass);
3421 return std::make_pair(0U, ARM::GPRRegisterClass);
3424 return std::make_pair(0U, ARM::SPRRegisterClass);
3426 return std::make_pair(0U, ARM::DPRRegisterClass);
3430 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3433 std::vector<unsigned> ARMTargetLowering::
3434 getRegClassForInlineAsmConstraint(const std::string &Constraint,
3436 if (Constraint.size() != 1)
3437 return std::vector<unsigned>();
3439 switch (Constraint[0]) { // GCC ARM Constraint Letters
3442 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
3443 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
3446 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
3447 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
3448 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
3449 ARM::R12, ARM::LR, 0);
3452 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
3453 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
3454 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
3455 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
3456 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
3457 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
3458 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
3459 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
3461 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
3462 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
3463 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
3464 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
3468 return std::vector<unsigned>();
3471 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3472 /// vector. If it is invalid, don't add anything to Ops.
3473 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
3476 std::vector<SDValue>&Ops,
3477 SelectionDAG &DAG) const {
3478 SDValue Result(0, 0);
3480 switch (Constraint) {
3482 case 'I': case 'J': case 'K': case 'L':
3483 case 'M': case 'N': case 'O':
3484 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3488 int64_t CVal64 = C->getSExtValue();
3489 int CVal = (int) CVal64;
3490 // None of these constraints allow values larger than 32 bits. Check
3491 // that the value fits in an int.
3495 switch (Constraint) {
3497 if (Subtarget->isThumb1Only()) {
3498 // This must be a constant between 0 and 255, for ADD
3500 if (CVal >= 0 && CVal <= 255)
3502 } else if (Subtarget->isThumb2()) {
3503 // A constant that can be used as an immediate value in a
3504 // data-processing instruction.
3505 if (ARM_AM::getT2SOImmVal(CVal) != -1)
3508 // A constant that can be used as an immediate value in a
3509 // data-processing instruction.
3510 if (ARM_AM::getSOImmVal(CVal) != -1)
3516 if (Subtarget->isThumb()) { // FIXME thumb2
3517 // This must be a constant between -255 and -1, for negated ADD
3518 // immediates. This can be used in GCC with an "n" modifier that
3519 // prints the negated value, for use with SUB instructions. It is
3520 // not useful otherwise but is implemented for compatibility.
3521 if (CVal >= -255 && CVal <= -1)
3524 // This must be a constant between -4095 and 4095. It is not clear
3525 // what this constraint is intended for. Implemented for
3526 // compatibility with GCC.
3527 if (CVal >= -4095 && CVal <= 4095)
3533 if (Subtarget->isThumb1Only()) {
3534 // A 32-bit value where only one byte has a nonzero value. Exclude
3535 // zero to match GCC. This constraint is used by GCC internally for
3536 // constants that can be loaded with a move/shift combination.
3537 // It is not useful otherwise but is implemented for compatibility.
3538 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
3540 } else if (Subtarget->isThumb2()) {
3541 // A constant whose bitwise inverse can be used as an immediate
3542 // value in a data-processing instruction. This can be used in GCC
3543 // with a "B" modifier that prints the inverted value, for use with
3544 // BIC and MVN instructions. It is not useful otherwise but is
3545 // implemented for compatibility.
3546 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
3549 // A constant whose bitwise inverse can be used as an immediate
3550 // value in a data-processing instruction. This can be used in GCC
3551 // with a "B" modifier that prints the inverted value, for use with
3552 // BIC and MVN instructions. It is not useful otherwise but is
3553 // implemented for compatibility.
3554 if (ARM_AM::getSOImmVal(~CVal) != -1)
3560 if (Subtarget->isThumb1Only()) {
3561 // This must be a constant between -7 and 7,
3562 // for 3-operand ADD/SUB immediate instructions.
3563 if (CVal >= -7 && CVal < 7)
3565 } else if (Subtarget->isThumb2()) {
3566 // A constant whose negation can be used as an immediate value in a
3567 // data-processing instruction. This can be used in GCC with an "n"
3568 // modifier that prints the negated value, for use with SUB
3569 // instructions. It is not useful otherwise but is implemented for
3571 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
3574 // A constant whose negation can be used as an immediate value in a
3575 // data-processing instruction. This can be used in GCC with an "n"
3576 // modifier that prints the negated value, for use with SUB
3577 // instructions. It is not useful otherwise but is implemented for
3579 if (ARM_AM::getSOImmVal(-CVal) != -1)
3585 if (Subtarget->isThumb()) { // FIXME thumb2
3586 // This must be a multiple of 4 between 0 and 1020, for
3587 // ADD sp + immediate.
3588 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
3591 // A power of two or a constant between 0 and 32. This is used in
3592 // GCC for the shift amount on shifted register operands, but it is
3593 // useful in general for any shift amounts.
3594 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
3600 if (Subtarget->isThumb()) { // FIXME thumb2
3601 // This must be a constant between 0 and 31, for shift amounts.
3602 if (CVal >= 0 && CVal <= 31)
3608 if (Subtarget->isThumb()) { // FIXME thumb2
3609 // This must be a multiple of 4 between -508 and 508, for
3610 // ADD/SUB sp = sp + immediate.
3611 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
3616 Result = DAG.getTargetConstant(CVal, Op.getValueType());
3620 if (Result.getNode()) {
3621 Ops.push_back(Result);
3624 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,