1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "ARMAddressingModes.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMISelLowering.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMRegisterInfo.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "ARMTargetObjectFile.h"
24 #include "llvm/CallingConv.h"
25 #include "llvm/Constants.h"
26 #include "llvm/Function.h"
27 #include "llvm/Instruction.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/GlobalValue.h"
30 #include "llvm/CodeGen/CallingConvLower.h"
31 #include "llvm/CodeGen/MachineBasicBlock.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/PseudoSourceValue.h"
37 #include "llvm/CodeGen/SelectionDAG.h"
38 #include "llvm/Target/TargetOptions.h"
39 #include "llvm/ADT/VectorExtras.h"
40 #include "llvm/Support/ErrorHandling.h"
41 #include "llvm/Support/MathExtras.h"
44 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
45 CCValAssign::LocInfo &LocInfo,
46 ISD::ArgFlagsTy &ArgFlags,
48 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
49 CCValAssign::LocInfo &LocInfo,
50 ISD::ArgFlagsTy &ArgFlags,
52 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
53 CCValAssign::LocInfo &LocInfo,
54 ISD::ArgFlagsTy &ArgFlags,
56 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
57 CCValAssign::LocInfo &LocInfo,
58 ISD::ArgFlagsTy &ArgFlags,
61 void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
62 EVT PromotedBitwiseVT) {
63 if (VT != PromotedLdStVT) {
64 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
65 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
66 PromotedLdStVT.getSimpleVT());
68 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
69 AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
70 PromotedLdStVT.getSimpleVT());
73 EVT ElemTy = VT.getVectorElementType();
74 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
75 setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
76 if (ElemTy == MVT::i8 || ElemTy == MVT::i16)
77 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
78 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
79 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
80 setOperationAction(ISD::SCALAR_TO_VECTOR, VT.getSimpleVT(), Custom);
81 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Custom);
83 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
84 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
85 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
88 // Promote all bit-wise operations.
89 if (VT.isInteger() && VT != PromotedBitwiseVT) {
90 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
91 AddPromotedToType (ISD::AND, VT.getSimpleVT(),
92 PromotedBitwiseVT.getSimpleVT());
93 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
94 AddPromotedToType (ISD::OR, VT.getSimpleVT(),
95 PromotedBitwiseVT.getSimpleVT());
96 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
97 AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
98 PromotedBitwiseVT.getSimpleVT());
102 void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
103 addRegisterClass(VT, ARM::DPRRegisterClass);
104 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
107 void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
108 addRegisterClass(VT, ARM::QPRRegisterClass);
109 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
112 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
113 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
114 return new TargetLoweringObjectFileMachO();
115 return new ARMElfTargetObjectFile();
118 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
119 : TargetLowering(TM, createTLOF(TM)), ARMPCLabelIndex(0) {
120 Subtarget = &TM.getSubtarget<ARMSubtarget>();
122 if (Subtarget->isTargetDarwin()) {
123 // Uses VFP for Thumb libfuncs if available.
124 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
125 // Single-precision floating-point arithmetic.
126 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
127 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
128 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
129 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
131 // Double-precision floating-point arithmetic.
132 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
133 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
134 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
135 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
137 // Single-precision comparisons.
138 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
139 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
140 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
141 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
142 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
143 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
144 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
145 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
147 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
148 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
149 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
150 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
151 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
152 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
153 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
154 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
156 // Double-precision comparisons.
157 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
158 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
159 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
160 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
161 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
162 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
163 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
164 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
166 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
167 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
168 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
169 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
170 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
171 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
172 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
173 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
175 // Floating-point to integer conversions.
176 // i64 conversions are done via library routines even when generating VFP
177 // instructions, so use the same ones.
178 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
179 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
180 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
181 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
183 // Conversions between floating types.
184 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
185 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
187 // Integer to floating-point conversions.
188 // i64 conversions are done via library routines even when generating VFP
189 // instructions, so use the same ones.
190 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
191 // e.g., __floatunsidf vs. __floatunssidfvfp.
192 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
193 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
194 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
195 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
199 // These libcalls are not available in 32-bit.
200 setLibcallName(RTLIB::SHL_I128, 0);
201 setLibcallName(RTLIB::SRL_I128, 0);
202 setLibcallName(RTLIB::SRA_I128, 0);
204 // Libcalls should use the AAPCS base standard ABI, even if hard float
205 // is in effect, as per the ARM RTABI specification, section 4.1.2.
206 if (Subtarget->isAAPCS_ABI()) {
207 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
208 setLibcallCallingConv(static_cast<RTLIB::Libcall>(i),
209 CallingConv::ARM_AAPCS);
213 if (Subtarget->isThumb1Only())
214 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
216 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
217 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
218 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
219 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
221 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
224 if (Subtarget->hasNEON()) {
225 addDRTypeForNEON(MVT::v2f32);
226 addDRTypeForNEON(MVT::v8i8);
227 addDRTypeForNEON(MVT::v4i16);
228 addDRTypeForNEON(MVT::v2i32);
229 addDRTypeForNEON(MVT::v1i64);
231 addQRTypeForNEON(MVT::v4f32);
232 addQRTypeForNEON(MVT::v2f64);
233 addQRTypeForNEON(MVT::v16i8);
234 addQRTypeForNEON(MVT::v8i16);
235 addQRTypeForNEON(MVT::v4i32);
236 addQRTypeForNEON(MVT::v2i64);
238 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
239 setTargetDAGCombine(ISD::SHL);
240 setTargetDAGCombine(ISD::SRL);
241 setTargetDAGCombine(ISD::SRA);
242 setTargetDAGCombine(ISD::SIGN_EXTEND);
243 setTargetDAGCombine(ISD::ZERO_EXTEND);
244 setTargetDAGCombine(ISD::ANY_EXTEND);
247 computeRegisterProperties();
249 // ARM does not have f32 extending load.
250 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
252 // ARM does not have i1 sign extending load.
253 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
255 // ARM supports all 4 flavors of integer indexed load / store.
256 if (!Subtarget->isThumb1Only()) {
257 for (unsigned im = (unsigned)ISD::PRE_INC;
258 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
259 setIndexedLoadAction(im, MVT::i1, Legal);
260 setIndexedLoadAction(im, MVT::i8, Legal);
261 setIndexedLoadAction(im, MVT::i16, Legal);
262 setIndexedLoadAction(im, MVT::i32, Legal);
263 setIndexedStoreAction(im, MVT::i1, Legal);
264 setIndexedStoreAction(im, MVT::i8, Legal);
265 setIndexedStoreAction(im, MVT::i16, Legal);
266 setIndexedStoreAction(im, MVT::i32, Legal);
270 // i64 operation support.
271 if (Subtarget->isThumb1Only()) {
272 setOperationAction(ISD::MUL, MVT::i64, Expand);
273 setOperationAction(ISD::MULHU, MVT::i32, Expand);
274 setOperationAction(ISD::MULHS, MVT::i32, Expand);
275 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
276 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
278 setOperationAction(ISD::MUL, MVT::i64, Expand);
279 setOperationAction(ISD::MULHU, MVT::i32, Expand);
280 if (!Subtarget->hasV6Ops())
281 setOperationAction(ISD::MULHS, MVT::i32, Expand);
283 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
284 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
285 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
286 setOperationAction(ISD::SRL, MVT::i64, Custom);
287 setOperationAction(ISD::SRA, MVT::i64, Custom);
289 // ARM does not have ROTL.
290 setOperationAction(ISD::ROTL, MVT::i32, Expand);
291 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
292 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
293 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
294 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
296 // Only ARMv6 has BSWAP.
297 if (!Subtarget->hasV6Ops())
298 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
300 // These are expanded into libcalls.
301 setOperationAction(ISD::SDIV, MVT::i32, Expand);
302 setOperationAction(ISD::UDIV, MVT::i32, Expand);
303 setOperationAction(ISD::SREM, MVT::i32, Expand);
304 setOperationAction(ISD::UREM, MVT::i32, Expand);
305 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
306 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
308 // Support label based line numbers.
309 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
310 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
312 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
313 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
314 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
315 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
317 // Use the default implementation.
318 setOperationAction(ISD::VASTART, MVT::Other, Custom);
319 setOperationAction(ISD::VAARG, MVT::Other, Expand);
320 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
321 setOperationAction(ISD::VAEND, MVT::Other, Expand);
322 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
323 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
324 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
325 // FIXME: Shouldn't need this, since no register is used, but the legalizer
326 // doesn't yet know how to not do that for SjLj.
327 setExceptionSelectorRegister(ARM::R0);
328 if (Subtarget->isThumb())
329 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
331 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
332 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
334 if (!Subtarget->hasV6Ops() && !Subtarget->isThumb2()) {
335 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
336 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
338 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
340 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only())
341 // Turn f64->i64 into FMRRD, i64 -> f64 to FMDRR iff target supports vfp2.
342 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
344 // We want to custom lower some of our intrinsics.
345 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
346 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
347 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
349 setOperationAction(ISD::SETCC, MVT::i32, Expand);
350 setOperationAction(ISD::SETCC, MVT::f32, Expand);
351 setOperationAction(ISD::SETCC, MVT::f64, Expand);
352 setOperationAction(ISD::SELECT, MVT::i32, Expand);
353 setOperationAction(ISD::SELECT, MVT::f32, Expand);
354 setOperationAction(ISD::SELECT, MVT::f64, Expand);
355 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
356 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
357 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
359 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
360 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
361 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
362 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
363 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
365 // We don't support sin/cos/fmod/copysign/pow
366 setOperationAction(ISD::FSIN, MVT::f64, Expand);
367 setOperationAction(ISD::FSIN, MVT::f32, Expand);
368 setOperationAction(ISD::FCOS, MVT::f32, Expand);
369 setOperationAction(ISD::FCOS, MVT::f64, Expand);
370 setOperationAction(ISD::FREM, MVT::f64, Expand);
371 setOperationAction(ISD::FREM, MVT::f32, Expand);
372 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
373 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
374 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
376 setOperationAction(ISD::FPOW, MVT::f64, Expand);
377 setOperationAction(ISD::FPOW, MVT::f32, Expand);
379 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
380 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
381 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
382 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
383 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
384 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
387 // We have target-specific dag combine patterns for the following nodes:
388 // ARMISD::FMRRD - No need to call setTargetDAGCombine
389 setTargetDAGCombine(ISD::ADD);
390 setTargetDAGCombine(ISD::SUB);
392 setStackPointerRegisterToSaveRestore(ARM::SP);
393 setSchedulingPreference(SchedulingForRegPressure);
394 setIfCvtBlockSizeLimit(Subtarget->isThumb() ? 0 : 10);
395 setIfCvtDupBlockSizeLimit(Subtarget->isThumb() ? 0 : 2);
397 if (!Subtarget->isThumb()) {
398 // Use branch latency information to determine if-conversion limits.
399 // FIXME: If-converter should use instruction latency of the branch being
400 // eliminated to compute the threshold. For ARMv6, the branch "latency"
401 // varies depending on whether it's dynamically or statically predicted
402 // and on whether the destination is in the prefetch buffer.
403 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
404 const InstrItineraryData &InstrItins = Subtarget->getInstrItineraryData();
405 unsigned Latency= InstrItins.getLatency(TII->get(ARM::Bcc).getSchedClass());
407 setIfCvtBlockSizeLimit(Latency-1);
409 setIfCvtDupBlockSizeLimit(Latency-2);
411 setIfCvtBlockSizeLimit(10);
412 setIfCvtDupBlockSizeLimit(2);
416 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
417 // Do not enable CodePlacementOpt for now: it currently runs after the
418 // ARMConstantIslandPass and messes up branch relaxation and placement
419 // of constant islands.
420 // benefitFromCodePlacementOpt = true;
423 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
426 case ARMISD::Wrapper: return "ARMISD::Wrapper";
427 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
428 case ARMISD::CALL: return "ARMISD::CALL";
429 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
430 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
431 case ARMISD::tCALL: return "ARMISD::tCALL";
432 case ARMISD::BRCOND: return "ARMISD::BRCOND";
433 case ARMISD::BR_JT: return "ARMISD::BR_JT";
434 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
435 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
436 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
437 case ARMISD::CMP: return "ARMISD::CMP";
438 case ARMISD::CMPZ: return "ARMISD::CMPZ";
439 case ARMISD::CMPFP: return "ARMISD::CMPFP";
440 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
441 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
442 case ARMISD::CMOV: return "ARMISD::CMOV";
443 case ARMISD::CNEG: return "ARMISD::CNEG";
445 case ARMISD::FTOSI: return "ARMISD::FTOSI";
446 case ARMISD::FTOUI: return "ARMISD::FTOUI";
447 case ARMISD::SITOF: return "ARMISD::SITOF";
448 case ARMISD::UITOF: return "ARMISD::UITOF";
450 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
451 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
452 case ARMISD::RRX: return "ARMISD::RRX";
454 case ARMISD::FMRRD: return "ARMISD::FMRRD";
455 case ARMISD::FMDRR: return "ARMISD::FMDRR";
457 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
459 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
461 case ARMISD::VCEQ: return "ARMISD::VCEQ";
462 case ARMISD::VCGE: return "ARMISD::VCGE";
463 case ARMISD::VCGEU: return "ARMISD::VCGEU";
464 case ARMISD::VCGT: return "ARMISD::VCGT";
465 case ARMISD::VCGTU: return "ARMISD::VCGTU";
466 case ARMISD::VTST: return "ARMISD::VTST";
468 case ARMISD::VSHL: return "ARMISD::VSHL";
469 case ARMISD::VSHRs: return "ARMISD::VSHRs";
470 case ARMISD::VSHRu: return "ARMISD::VSHRu";
471 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
472 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
473 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
474 case ARMISD::VSHRN: return "ARMISD::VSHRN";
475 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
476 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
477 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
478 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
479 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
480 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
481 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
482 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
483 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
484 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
485 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
486 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
487 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
488 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
489 case ARMISD::VDUP: return "ARMISD::VDUP";
490 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
491 case ARMISD::VLD2D: return "ARMISD::VLD2D";
492 case ARMISD::VLD3D: return "ARMISD::VLD3D";
493 case ARMISD::VLD4D: return "ARMISD::VLD4D";
494 case ARMISD::VST2D: return "ARMISD::VST2D";
495 case ARMISD::VST3D: return "ARMISD::VST3D";
496 case ARMISD::VST4D: return "ARMISD::VST4D";
497 case ARMISD::VREV64: return "ARMISD::VREV64";
498 case ARMISD::VREV32: return "ARMISD::VREV32";
499 case ARMISD::VREV16: return "ARMISD::VREV16";
503 /// getFunctionAlignment - Return the Log2 alignment of this function.
504 unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
505 return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 1 : 2;
508 //===----------------------------------------------------------------------===//
510 //===----------------------------------------------------------------------===//
512 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
513 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
515 default: llvm_unreachable("Unknown condition code!");
516 case ISD::SETNE: return ARMCC::NE;
517 case ISD::SETEQ: return ARMCC::EQ;
518 case ISD::SETGT: return ARMCC::GT;
519 case ISD::SETGE: return ARMCC::GE;
520 case ISD::SETLT: return ARMCC::LT;
521 case ISD::SETLE: return ARMCC::LE;
522 case ISD::SETUGT: return ARMCC::HI;
523 case ISD::SETUGE: return ARMCC::HS;
524 case ISD::SETULT: return ARMCC::LO;
525 case ISD::SETULE: return ARMCC::LS;
529 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. It
530 /// returns true if the operands should be inverted to form the proper
532 static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
533 ARMCC::CondCodes &CondCode2) {
535 CondCode2 = ARMCC::AL;
537 default: llvm_unreachable("Unknown FP condition!");
539 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
541 case ISD::SETOGT: CondCode = ARMCC::GT; break;
543 case ISD::SETOGE: CondCode = ARMCC::GE; break;
544 case ISD::SETOLT: CondCode = ARMCC::MI; break;
545 case ISD::SETOLE: CondCode = ARMCC::GT; Invert = true; break;
546 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
547 case ISD::SETO: CondCode = ARMCC::VC; break;
548 case ISD::SETUO: CondCode = ARMCC::VS; break;
549 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
550 case ISD::SETUGT: CondCode = ARMCC::HI; break;
551 case ISD::SETUGE: CondCode = ARMCC::PL; break;
553 case ISD::SETULT: CondCode = ARMCC::LT; break;
555 case ISD::SETULE: CondCode = ARMCC::LE; break;
557 case ISD::SETUNE: CondCode = ARMCC::NE; break;
562 //===----------------------------------------------------------------------===//
563 // Calling Convention Implementation
564 //===----------------------------------------------------------------------===//
566 #include "ARMGenCallingConv.inc"
568 // APCS f64 is in register pairs, possibly split to stack
569 static bool f64AssignAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
570 CCValAssign::LocInfo &LocInfo,
571 CCState &State, bool CanFail) {
572 static const unsigned RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
574 // Try to get the first register.
575 if (unsigned Reg = State.AllocateReg(RegList, 4))
576 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
578 // For the 2nd half of a v2f64, do not fail.
582 // Put the whole thing on the stack.
583 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
584 State.AllocateStack(8, 4),
589 // Try to get the second register.
590 if (unsigned Reg = State.AllocateReg(RegList, 4))
591 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
593 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
594 State.AllocateStack(4, 4),
599 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
600 CCValAssign::LocInfo &LocInfo,
601 ISD::ArgFlagsTy &ArgFlags,
603 if (!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
605 if (LocVT == MVT::v2f64 &&
606 !f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
608 return true; // we handled it
611 // AAPCS f64 is in aligned register pairs
612 static bool f64AssignAAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
613 CCValAssign::LocInfo &LocInfo,
614 CCState &State, bool CanFail) {
615 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
616 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
618 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
620 // For the 2nd half of a v2f64, do not just fail.
624 // Put the whole thing on the stack.
625 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
626 State.AllocateStack(8, 8),
632 for (i = 0; i < 2; ++i)
633 if (HiRegList[i] == Reg)
636 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
637 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
642 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
643 CCValAssign::LocInfo &LocInfo,
644 ISD::ArgFlagsTy &ArgFlags,
646 if (!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
648 if (LocVT == MVT::v2f64 &&
649 !f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
651 return true; // we handled it
654 static bool f64RetAssign(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
655 CCValAssign::LocInfo &LocInfo, CCState &State) {
656 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
657 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
659 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
661 return false; // we didn't handle it
664 for (i = 0; i < 2; ++i)
665 if (HiRegList[i] == Reg)
668 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
669 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
674 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
675 CCValAssign::LocInfo &LocInfo,
676 ISD::ArgFlagsTy &ArgFlags,
678 if (!f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
680 if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
682 return true; // we handled it
685 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
686 CCValAssign::LocInfo &LocInfo,
687 ISD::ArgFlagsTy &ArgFlags,
689 return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags,
693 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
694 /// given CallingConvention value.
695 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(unsigned CC,
697 bool isVarArg) const {
700 llvm_unreachable("Unsupported calling convention");
702 case CallingConv::Fast:
703 // Use target triple & subtarget features to do actual dispatch.
704 if (Subtarget->isAAPCS_ABI()) {
705 if (Subtarget->hasVFP2() &&
706 FloatABIType == FloatABI::Hard && !isVarArg)
707 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
709 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
711 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
712 case CallingConv::ARM_AAPCS_VFP:
713 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
714 case CallingConv::ARM_AAPCS:
715 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
716 case CallingConv::ARM_APCS:
717 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
721 /// LowerCallResult - Lower the result values of a call into the
722 /// appropriate copies out of appropriate physical registers.
724 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
725 unsigned CallConv, bool isVarArg,
726 const SmallVectorImpl<ISD::InputArg> &Ins,
727 DebugLoc dl, SelectionDAG &DAG,
728 SmallVectorImpl<SDValue> &InVals) {
730 // Assign locations to each value returned by this call.
731 SmallVector<CCValAssign, 16> RVLocs;
732 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
733 RVLocs, *DAG.getContext());
734 CCInfo.AnalyzeCallResult(Ins,
735 CCAssignFnForNode(CallConv, /* Return*/ true,
738 // Copy all of the result registers out of their specified physreg.
739 for (unsigned i = 0; i != RVLocs.size(); ++i) {
740 CCValAssign VA = RVLocs[i];
743 if (VA.needsCustom()) {
744 // Handle f64 or half of a v2f64.
745 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
747 Chain = Lo.getValue(1);
748 InFlag = Lo.getValue(2);
749 VA = RVLocs[++i]; // skip ahead to next loc
750 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
752 Chain = Hi.getValue(1);
753 InFlag = Hi.getValue(2);
754 Val = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
756 if (VA.getLocVT() == MVT::v2f64) {
757 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
758 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
759 DAG.getConstant(0, MVT::i32));
761 VA = RVLocs[++i]; // skip ahead to next loc
762 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
763 Chain = Lo.getValue(1);
764 InFlag = Lo.getValue(2);
765 VA = RVLocs[++i]; // skip ahead to next loc
766 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
767 Chain = Hi.getValue(1);
768 InFlag = Hi.getValue(2);
769 Val = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
770 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
771 DAG.getConstant(1, MVT::i32));
774 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
776 Chain = Val.getValue(1);
777 InFlag = Val.getValue(2);
780 switch (VA.getLocInfo()) {
781 default: llvm_unreachable("Unknown loc info!");
782 case CCValAssign::Full: break;
783 case CCValAssign::BCvt:
784 Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val);
788 InVals.push_back(Val);
794 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
795 /// by "Src" to address "Dst" of size "Size". Alignment information is
796 /// specified by the specific parameter attribute. The copy will be passed as
797 /// a byval function parameter.
798 /// Sometimes what we are copying is the end of a larger object, the part that
799 /// does not fit in registers.
801 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
802 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
804 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
805 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
806 /*AlwaysInline=*/false, NULL, 0, NULL, 0);
809 /// LowerMemOpCallTo - Store the argument to the stack.
811 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
812 SDValue StackPtr, SDValue Arg,
813 DebugLoc dl, SelectionDAG &DAG,
814 const CCValAssign &VA,
815 ISD::ArgFlagsTy Flags) {
816 unsigned LocMemOffset = VA.getLocMemOffset();
817 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
818 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
819 if (Flags.isByVal()) {
820 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
822 return DAG.getStore(Chain, dl, Arg, PtrOff,
823 PseudoSourceValue::getStack(), LocMemOffset);
826 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
827 SDValue Chain, SDValue &Arg,
828 RegsToPassVector &RegsToPass,
829 CCValAssign &VA, CCValAssign &NextVA,
831 SmallVector<SDValue, 8> &MemOpChains,
832 ISD::ArgFlagsTy Flags) {
834 SDValue fmrrd = DAG.getNode(ARMISD::FMRRD, dl,
835 DAG.getVTList(MVT::i32, MVT::i32), Arg);
836 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
838 if (NextVA.isRegLoc())
839 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
841 assert(NextVA.isMemLoc());
842 if (StackPtr.getNode() == 0)
843 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
845 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
851 /// LowerCall - Lowering a call into a callseq_start <-
852 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
855 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
856 unsigned CallConv, bool isVarArg,
858 const SmallVectorImpl<ISD::OutputArg> &Outs,
859 const SmallVectorImpl<ISD::InputArg> &Ins,
860 DebugLoc dl, SelectionDAG &DAG,
861 SmallVectorImpl<SDValue> &InVals) {
863 // Analyze operands of the call, assigning locations to each operand.
864 SmallVector<CCValAssign, 16> ArgLocs;
865 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
867 CCInfo.AnalyzeCallOperands(Outs,
868 CCAssignFnForNode(CallConv, /* Return*/ false,
871 // Get a count of how many bytes are to be pushed on the stack.
872 unsigned NumBytes = CCInfo.getNextStackOffset();
874 // Adjust the stack pointer for the new arguments...
875 // These operations are automatically eliminated by the prolog/epilog pass
876 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
878 SDValue StackPtr = DAG.getRegister(ARM::SP, MVT::i32);
880 RegsToPassVector RegsToPass;
881 SmallVector<SDValue, 8> MemOpChains;
883 // Walk the register/memloc assignments, inserting copies/loads. In the case
884 // of tail call optimization, arguments are handled later.
885 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
888 CCValAssign &VA = ArgLocs[i];
889 SDValue Arg = Outs[realArgIdx].Val;
890 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
892 // Promote the value if needed.
893 switch (VA.getLocInfo()) {
894 default: llvm_unreachable("Unknown loc info!");
895 case CCValAssign::Full: break;
896 case CCValAssign::SExt:
897 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
899 case CCValAssign::ZExt:
900 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
902 case CCValAssign::AExt:
903 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
905 case CCValAssign::BCvt:
906 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
910 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
911 if (VA.needsCustom()) {
912 if (VA.getLocVT() == MVT::v2f64) {
913 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
914 DAG.getConstant(0, MVT::i32));
915 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
916 DAG.getConstant(1, MVT::i32));
918 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
919 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
921 VA = ArgLocs[++i]; // skip ahead to next loc
923 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
924 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
926 assert(VA.isMemLoc());
927 if (StackPtr.getNode() == 0)
928 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
930 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
931 dl, DAG, VA, Flags));
934 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
935 StackPtr, MemOpChains, Flags);
937 } else if (VA.isRegLoc()) {
938 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
940 assert(VA.isMemLoc());
941 if (StackPtr.getNode() == 0)
942 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
944 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
945 dl, DAG, VA, Flags));
949 if (!MemOpChains.empty())
950 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
951 &MemOpChains[0], MemOpChains.size());
953 // Build a sequence of copy-to-reg nodes chained together with token chain
954 // and flag operands which copy the outgoing args into the appropriate regs.
956 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
957 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
958 RegsToPass[i].second, InFlag);
959 InFlag = Chain.getValue(1);
962 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
963 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
964 // node so that legalize doesn't hack it.
965 bool isDirect = false;
966 bool isARMFunc = false;
967 bool isLocalARMFunc = false;
968 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
969 GlobalValue *GV = G->getGlobal();
971 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
972 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
973 getTargetMachine().getRelocationModel() != Reloc::Static;
974 isARMFunc = !Subtarget->isThumb() || isStub;
975 // ARM call to a local ARM function is predicable.
976 isLocalARMFunc = !Subtarget->isThumb() && !isExt;
977 // tBX takes a register source operand.
978 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
979 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
981 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
982 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
983 Callee = DAG.getLoad(getPointerTy(), dl,
984 DAG.getEntryNode(), CPAddr, NULL, 0);
985 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
986 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
987 getPointerTy(), Callee, PICLabel);
989 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy());
990 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
992 bool isStub = Subtarget->isTargetDarwin() &&
993 getTargetMachine().getRelocationModel() != Reloc::Static;
994 isARMFunc = !Subtarget->isThumb() || isStub;
995 // tBX takes a register source operand.
996 const char *Sym = S->getSymbol();
997 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
998 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
999 Sym, ARMPCLabelIndex,
1001 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1002 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1003 Callee = DAG.getLoad(getPointerTy(), dl,
1004 DAG.getEntryNode(), CPAddr, NULL, 0);
1005 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1006 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1007 getPointerTy(), Callee, PICLabel);
1009 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
1012 // FIXME: handle tail calls differently.
1014 if (Subtarget->isThumb()) {
1015 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1016 CallOpc = ARMISD::CALL_NOLINK;
1018 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1020 CallOpc = (isDirect || Subtarget->hasV5TOps())
1021 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
1022 : ARMISD::CALL_NOLINK;
1024 if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb1Only()) {
1025 // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK
1026 Chain = DAG.getCopyToReg(Chain, dl, ARM::LR, DAG.getUNDEF(MVT::i32),InFlag);
1027 InFlag = Chain.getValue(1);
1030 std::vector<SDValue> Ops;
1031 Ops.push_back(Chain);
1032 Ops.push_back(Callee);
1034 // Add argument registers to the end of the list so that they are known live
1036 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1037 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1038 RegsToPass[i].second.getValueType()));
1040 if (InFlag.getNode())
1041 Ops.push_back(InFlag);
1042 // Returns a chain and a flag for retval copy to use.
1043 Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(MVT::Other, MVT::Flag),
1044 &Ops[0], Ops.size());
1045 InFlag = Chain.getValue(1);
1047 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1048 DAG.getIntPtrConstant(0, true), InFlag);
1050 InFlag = Chain.getValue(1);
1052 // Handle result values, copying them out of physregs into vregs that we
1054 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1059 ARMTargetLowering::LowerReturn(SDValue Chain,
1060 unsigned CallConv, bool isVarArg,
1061 const SmallVectorImpl<ISD::OutputArg> &Outs,
1062 DebugLoc dl, SelectionDAG &DAG) {
1064 // CCValAssign - represent the assignment of the return value to a location.
1065 SmallVector<CCValAssign, 16> RVLocs;
1067 // CCState - Info about the registers and stack slots.
1068 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
1071 // Analyze outgoing return values.
1072 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1075 // If this is the first return lowered for this function, add
1076 // the regs to the liveout set for the function.
1077 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1078 for (unsigned i = 0; i != RVLocs.size(); ++i)
1079 if (RVLocs[i].isRegLoc())
1080 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1085 // Copy the result values into the output registers.
1086 for (unsigned i = 0, realRVLocIdx = 0;
1088 ++i, ++realRVLocIdx) {
1089 CCValAssign &VA = RVLocs[i];
1090 assert(VA.isRegLoc() && "Can only return in registers!");
1092 SDValue Arg = Outs[realRVLocIdx].Val;
1094 switch (VA.getLocInfo()) {
1095 default: llvm_unreachable("Unknown loc info!");
1096 case CCValAssign::Full: break;
1097 case CCValAssign::BCvt:
1098 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1102 if (VA.needsCustom()) {
1103 if (VA.getLocVT() == MVT::v2f64) {
1104 // Extract the first half and return it in two registers.
1105 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1106 DAG.getConstant(0, MVT::i32));
1107 SDValue HalfGPRs = DAG.getNode(ARMISD::FMRRD, dl,
1108 DAG.getVTList(MVT::i32, MVT::i32), Half);
1110 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1111 Flag = Chain.getValue(1);
1112 VA = RVLocs[++i]; // skip ahead to next loc
1113 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1114 HalfGPRs.getValue(1), Flag);
1115 Flag = Chain.getValue(1);
1116 VA = RVLocs[++i]; // skip ahead to next loc
1118 // Extract the 2nd half and fall through to handle it as an f64 value.
1119 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1120 DAG.getConstant(1, MVT::i32));
1122 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1124 SDValue fmrrd = DAG.getNode(ARMISD::FMRRD, dl,
1125 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1126 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1127 Flag = Chain.getValue(1);
1128 VA = RVLocs[++i]; // skip ahead to next loc
1129 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1132 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1134 // Guarantee that all emitted copies are
1135 // stuck together, avoiding something bad.
1136 Flag = Chain.getValue(1);
1141 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1143 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1148 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1149 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1150 // one of the above mentioned nodes. It has to be wrapped because otherwise
1151 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1152 // be used to form addressing mode. These wrapped nodes will be selected
1154 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1155 EVT PtrVT = Op.getValueType();
1156 // FIXME there is no actual debug info here
1157 DebugLoc dl = Op.getDebugLoc();
1158 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1160 if (CP->isMachineConstantPoolEntry())
1161 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1162 CP->getAlignment());
1164 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1165 CP->getAlignment());
1166 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1169 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
1171 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1172 SelectionDAG &DAG) {
1173 DebugLoc dl = GA->getDebugLoc();
1174 EVT PtrVT = getPointerTy();
1175 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1176 ARMConstantPoolValue *CPV =
1177 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
1178 PCAdj, "tlsgd", true);
1179 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1180 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
1181 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument, NULL, 0);
1182 SDValue Chain = Argument.getValue(1);
1184 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1185 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
1187 // call __tls_get_addr.
1190 Entry.Node = Argument;
1191 Entry.Ty = (const Type *) Type::getInt32Ty(*DAG.getContext());
1192 Args.push_back(Entry);
1193 // FIXME: is there useful debug info available here?
1194 std::pair<SDValue, SDValue> CallResult =
1195 LowerCallTo(Chain, (const Type *) Type::getInt32Ty(*DAG.getContext()),
1196 false, false, false, false,
1197 0, CallingConv::C, false, /*isReturnValueUsed=*/true,
1198 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
1199 return CallResult.first;
1202 // Lower ISD::GlobalTLSAddress using the "initial exec" or
1203 // "local exec" model.
1205 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
1206 SelectionDAG &DAG) {
1207 GlobalValue *GV = GA->getGlobal();
1208 DebugLoc dl = GA->getDebugLoc();
1210 SDValue Chain = DAG.getEntryNode();
1211 EVT PtrVT = getPointerTy();
1212 // Get the Thread Pointer
1213 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1215 if (GV->isDeclaration()) {
1216 // initial exec model
1217 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1218 ARMConstantPoolValue *CPV =
1219 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
1220 PCAdj, "gottpoff", true);
1221 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1222 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1223 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
1224 Chain = Offset.getValue(1);
1226 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1227 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
1229 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
1232 ARMConstantPoolValue *CPV =
1233 new ARMConstantPoolValue(GV, ARMCP::CPValue, "tpoff");
1234 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1235 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1236 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
1239 // The address of the thread local variable is the add of the thread
1240 // pointer with the offset of the variable.
1241 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
1245 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
1246 // TODO: implement the "local dynamic" model
1247 assert(Subtarget->isTargetELF() &&
1248 "TLS not implemented for non-ELF targets");
1249 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1250 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
1251 // otherwise use the "Local Exec" TLS Model
1252 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
1253 return LowerToTLSGeneralDynamicModel(GA, DAG);
1255 return LowerToTLSExecModels(GA, DAG);
1258 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
1259 SelectionDAG &DAG) {
1260 EVT PtrVT = getPointerTy();
1261 DebugLoc dl = Op.getDebugLoc();
1262 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1263 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1264 if (RelocM == Reloc::PIC_) {
1265 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
1266 ARMConstantPoolValue *CPV =
1267 new ARMConstantPoolValue(GV, ARMCP::CPValue, UseGOTOFF ? "GOTOFF":"GOT");
1268 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1269 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1270 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1272 SDValue Chain = Result.getValue(1);
1273 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1274 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
1276 Result = DAG.getLoad(PtrVT, dl, Chain, Result, NULL, 0);
1279 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1280 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1281 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
1285 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol
1286 /// even in non-static mode.
1287 static bool GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model RelocM) {
1288 // If symbol visibility is hidden, the extra load is not needed if
1289 // the symbol is definitely defined in the current translation unit.
1290 bool isDecl = GV->isDeclaration() || GV->hasAvailableExternallyLinkage();
1291 if (GV->hasHiddenVisibility() && (!isDecl && !GV->hasCommonLinkage()))
1293 return RelocM != Reloc::Static && (isDecl || GV->isWeakForLinker());
1296 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
1297 SelectionDAG &DAG) {
1298 EVT PtrVT = getPointerTy();
1299 DebugLoc dl = Op.getDebugLoc();
1300 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1301 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1302 bool IsIndirect = GVIsIndirectSymbol(GV, RelocM);
1304 if (RelocM == Reloc::Static)
1305 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1307 unsigned PCAdj = (RelocM != Reloc::PIC_)
1308 ? 0 : (Subtarget->isThumb() ? 4 : 8);
1309 ARMCP::ARMCPKind Kind = IsIndirect ? ARMCP::CPNonLazyPtr
1311 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
1313 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1315 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1317 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
1318 SDValue Chain = Result.getValue(1);
1320 if (RelocM == Reloc::PIC_) {
1321 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1322 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1325 Result = DAG.getLoad(PtrVT, dl, Chain, Result, NULL, 0);
1330 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
1332 assert(Subtarget->isTargetELF() &&
1333 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
1334 EVT PtrVT = getPointerTy();
1335 DebugLoc dl = Op.getDebugLoc();
1336 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1337 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1338 "_GLOBAL_OFFSET_TABLE_",
1340 ARMCP::CPValue, PCAdj);
1341 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1342 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1343 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
1344 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1345 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1348 static SDValue LowerNeonVLDIntrinsic(SDValue Op, SelectionDAG &DAG,
1350 SDNode *Node = Op.getNode();
1351 EVT VT = Node->getValueType(0);
1352 DebugLoc dl = Op.getDebugLoc();
1354 if (!VT.is64BitVector())
1355 return SDValue(); // unimplemented
1357 SDValue Ops[] = { Node->getOperand(0),
1358 Node->getOperand(2) };
1359 return DAG.getNode(Opcode, dl, Node->getVTList(), Ops, 2);
1362 static SDValue LowerNeonVSTIntrinsic(SDValue Op, SelectionDAG &DAG,
1363 unsigned Opcode, unsigned NumVecs) {
1364 SDNode *Node = Op.getNode();
1365 EVT VT = Node->getOperand(3).getValueType();
1366 DebugLoc dl = Op.getDebugLoc();
1368 if (!VT.is64BitVector())
1369 return SDValue(); // unimplemented
1371 SmallVector<SDValue, 6> Ops;
1372 Ops.push_back(Node->getOperand(0));
1373 Ops.push_back(Node->getOperand(2));
1374 for (unsigned N = 0; N < NumVecs; ++N)
1375 Ops.push_back(Node->getOperand(N + 3));
1376 return DAG.getNode(Opcode, dl, MVT::Other, Ops.data(), Ops.size());
1380 ARMTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) {
1381 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1383 case Intrinsic::arm_neon_vld2:
1384 return LowerNeonVLDIntrinsic(Op, DAG, ARMISD::VLD2D);
1385 case Intrinsic::arm_neon_vld3:
1386 return LowerNeonVLDIntrinsic(Op, DAG, ARMISD::VLD3D);
1387 case Intrinsic::arm_neon_vld4:
1388 return LowerNeonVLDIntrinsic(Op, DAG, ARMISD::VLD4D);
1389 case Intrinsic::arm_neon_vst2:
1390 return LowerNeonVSTIntrinsic(Op, DAG, ARMISD::VST2D, 2);
1391 case Intrinsic::arm_neon_vst3:
1392 return LowerNeonVSTIntrinsic(Op, DAG, ARMISD::VST3D, 3);
1393 case Intrinsic::arm_neon_vst4:
1394 return LowerNeonVSTIntrinsic(Op, DAG, ARMISD::VST4D, 4);
1395 default: return SDValue(); // Don't custom lower most intrinsics.
1400 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
1401 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1402 DebugLoc dl = Op.getDebugLoc();
1404 default: return SDValue(); // Don't custom lower most intrinsics.
1405 case Intrinsic::arm_thread_pointer: {
1406 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1407 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1409 case Intrinsic::eh_sjlj_lsda: {
1410 // blah. horrible, horrible hack with the forced magic name.
1411 // really need to clean this up. It belongs in the target-independent
1412 // layer somehow that doesn't require the coupling with the asm
1414 MachineFunction &MF = DAG.getMachineFunction();
1415 EVT PtrVT = getPointerTy();
1416 DebugLoc dl = Op.getDebugLoc();
1417 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1419 unsigned PCAdj = (RelocM != Reloc::PIC_)
1420 ? 0 : (Subtarget->isThumb() ? 4 : 8);
1421 ARMCP::ARMCPKind Kind = ARMCP::CPValue;
1422 // Save off the LSDA name for the AsmPrinter to use when it's time
1423 // to emit the table
1424 std::string LSDAName = "L_lsda_";
1425 LSDAName += MF.getFunction()->getName();
1426 ARMConstantPoolValue *CPV =
1427 new ARMConstantPoolValue(*DAG.getContext(), LSDAName.c_str(),
1428 ARMPCLabelIndex, Kind, PCAdj);
1429 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1430 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1432 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
1433 SDValue Chain = Result.getValue(1);
1435 if (RelocM == Reloc::PIC_) {
1436 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1437 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1441 case Intrinsic::eh_sjlj_setjmp:
1442 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(1));
1446 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
1447 unsigned VarArgsFrameIndex) {
1448 // vastart just stores the address of the VarArgsFrameIndex slot into the
1449 // memory location argument.
1450 DebugLoc dl = Op.getDebugLoc();
1451 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1452 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1453 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1454 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
1458 ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) {
1459 SDNode *Node = Op.getNode();
1460 DebugLoc dl = Node->getDebugLoc();
1461 EVT VT = Node->getValueType(0);
1462 SDValue Chain = Op.getOperand(0);
1463 SDValue Size = Op.getOperand(1);
1464 SDValue Align = Op.getOperand(2);
1466 // Chain the dynamic stack allocation so that it doesn't modify the stack
1467 // pointer when other instructions are using the stack.
1468 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1470 unsigned AlignVal = cast<ConstantSDNode>(Align)->getZExtValue();
1471 unsigned StackAlign = getTargetMachine().getFrameInfo()->getStackAlignment();
1472 if (AlignVal > StackAlign)
1473 // Do this now since selection pass cannot introduce new target
1474 // independent node.
1475 Align = DAG.getConstant(-(uint64_t)AlignVal, VT);
1477 // In Thumb1 mode, there isn't a "sub r, sp, r" instruction, we will end up
1478 // using a "add r, sp, r" instead. Negate the size now so we don't have to
1479 // do even more horrible hack later.
1480 MachineFunction &MF = DAG.getMachineFunction();
1481 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1482 if (AFI->isThumb1OnlyFunction()) {
1484 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Size);
1486 uint32_t Val = C->getZExtValue();
1487 if (Val <= 508 && ((Val & 3) == 0))
1491 Size = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, VT), Size);
1494 SDVTList VTList = DAG.getVTList(VT, MVT::Other);
1495 SDValue Ops1[] = { Chain, Size, Align };
1496 SDValue Res = DAG.getNode(ARMISD::DYN_ALLOC, dl, VTList, Ops1, 3);
1497 Chain = Res.getValue(1);
1498 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1499 DAG.getIntPtrConstant(0, true), SDValue());
1500 SDValue Ops2[] = { Res, Chain };
1501 return DAG.getMergeValues(Ops2, 2, dl);
1505 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
1506 SDValue &Root, SelectionDAG &DAG,
1508 MachineFunction &MF = DAG.getMachineFunction();
1509 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1511 TargetRegisterClass *RC;
1512 if (AFI->isThumb1OnlyFunction())
1513 RC = ARM::tGPRRegisterClass;
1515 RC = ARM::GPRRegisterClass;
1517 // Transform the arguments stored in physical registers into virtual ones.
1518 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1519 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
1522 if (NextVA.isMemLoc()) {
1523 unsigned ArgSize = NextVA.getLocVT().getSizeInBits()/8;
1524 MachineFrameInfo *MFI = MF.getFrameInfo();
1525 int FI = MFI->CreateFixedObject(ArgSize, NextVA.getLocMemOffset());
1527 // Create load node to retrieve arguments from the stack.
1528 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1529 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN, NULL, 0);
1531 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
1532 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
1535 return DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, ArgValue, ArgValue2);
1539 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
1540 unsigned CallConv, bool isVarArg,
1541 const SmallVectorImpl<ISD::InputArg>
1543 DebugLoc dl, SelectionDAG &DAG,
1544 SmallVectorImpl<SDValue> &InVals) {
1546 MachineFunction &MF = DAG.getMachineFunction();
1547 MachineFrameInfo *MFI = MF.getFrameInfo();
1549 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1551 // Assign locations to all of the incoming arguments.
1552 SmallVector<CCValAssign, 16> ArgLocs;
1553 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1555 CCInfo.AnalyzeFormalArguments(Ins,
1556 CCAssignFnForNode(CallConv, /* Return*/ false,
1559 SmallVector<SDValue, 16> ArgValues;
1561 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1562 CCValAssign &VA = ArgLocs[i];
1564 // Arguments stored in registers.
1565 if (VA.isRegLoc()) {
1566 EVT RegVT = VA.getLocVT();
1569 if (VA.needsCustom()) {
1570 // f64 and vector types are split up into multiple registers or
1571 // combinations of registers and stack slots.
1574 if (VA.getLocVT() == MVT::v2f64) {
1575 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
1577 VA = ArgLocs[++i]; // skip ahead to next loc
1578 SDValue ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
1580 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1581 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
1582 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
1583 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
1584 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
1586 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
1589 TargetRegisterClass *RC;
1591 if (RegVT == MVT::f32)
1592 RC = ARM::SPRRegisterClass;
1593 else if (RegVT == MVT::f64)
1594 RC = ARM::DPRRegisterClass;
1595 else if (RegVT == MVT::v2f64)
1596 RC = ARM::QPRRegisterClass;
1597 else if (RegVT == MVT::i32)
1598 RC = (AFI->isThumb1OnlyFunction() ?
1599 ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
1601 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
1603 // Transform the arguments in physical registers into virtual ones.
1604 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1605 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1608 // If this is an 8 or 16-bit value, it is really passed promoted
1609 // to 32 bits. Insert an assert[sz]ext to capture this, then
1610 // truncate to the right size.
1611 switch (VA.getLocInfo()) {
1612 default: llvm_unreachable("Unknown loc info!");
1613 case CCValAssign::Full: break;
1614 case CCValAssign::BCvt:
1615 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1617 case CCValAssign::SExt:
1618 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1619 DAG.getValueType(VA.getValVT()));
1620 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1622 case CCValAssign::ZExt:
1623 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1624 DAG.getValueType(VA.getValVT()));
1625 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1629 InVals.push_back(ArgValue);
1631 } else { // VA.isRegLoc()
1634 assert(VA.isMemLoc());
1635 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
1637 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
1638 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset());
1640 // Create load nodes to retrieve arguments from the stack.
1641 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1642 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, NULL, 0));
1648 static const unsigned GPRArgRegs[] = {
1649 ARM::R0, ARM::R1, ARM::R2, ARM::R3
1652 unsigned NumGPRs = CCInfo.getFirstUnallocated
1653 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
1655 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1656 unsigned VARegSize = (4 - NumGPRs) * 4;
1657 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
1658 unsigned ArgOffset = 0;
1659 if (VARegSaveSize) {
1660 // If this function is vararg, store any remaining integer argument regs
1661 // to their spots on the stack so that they may be loaded by deferencing
1662 // the result of va_next.
1663 AFI->setVarArgsRegSaveSize(VARegSaveSize);
1664 ArgOffset = CCInfo.getNextStackOffset();
1665 VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset +
1666 VARegSaveSize - VARegSize);
1667 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
1669 SmallVector<SDValue, 4> MemOps;
1670 for (; NumGPRs < 4; ++NumGPRs) {
1671 TargetRegisterClass *RC;
1672 if (AFI->isThumb1OnlyFunction())
1673 RC = ARM::tGPRRegisterClass;
1675 RC = ARM::GPRRegisterClass;
1677 unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
1678 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
1679 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
1680 MemOps.push_back(Store);
1681 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
1682 DAG.getConstant(4, getPointerTy()));
1684 if (!MemOps.empty())
1685 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1686 &MemOps[0], MemOps.size());
1688 // This will point to the next argument passed via stack.
1689 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
1695 /// isFloatingPointZero - Return true if this is +0.0.
1696 static bool isFloatingPointZero(SDValue Op) {
1697 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1698 return CFP->getValueAPF().isPosZero();
1699 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1700 // Maybe this has already been legalized into the constant pool?
1701 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
1702 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
1703 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
1704 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1705 return CFP->getValueAPF().isPosZero();
1711 static bool isLegalCmpImmediate(unsigned C, bool isThumb1Only) {
1712 return ( isThumb1Only && (C & ~255U) == 0) ||
1713 (!isThumb1Only && ARM_AM::getSOImmVal(C) != -1);
1716 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
1717 /// the given operands.
1718 static SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1719 SDValue &ARMCC, SelectionDAG &DAG, bool isThumb1Only,
1721 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1722 unsigned C = RHSC->getZExtValue();
1723 if (!isLegalCmpImmediate(C, isThumb1Only)) {
1724 // Constant does not fit, try adjusting it by one?
1729 if (isLegalCmpImmediate(C-1, isThumb1Only)) {
1730 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1731 RHS = DAG.getConstant(C-1, MVT::i32);
1736 if (C > 0 && isLegalCmpImmediate(C-1, isThumb1Only)) {
1737 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1738 RHS = DAG.getConstant(C-1, MVT::i32);
1743 if (isLegalCmpImmediate(C+1, isThumb1Only)) {
1744 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1745 RHS = DAG.getConstant(C+1, MVT::i32);
1750 if (C < 0xffffffff && isLegalCmpImmediate(C+1, isThumb1Only)) {
1751 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1752 RHS = DAG.getConstant(C+1, MVT::i32);
1759 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
1760 ARMISD::NodeType CompareType;
1763 CompareType = ARMISD::CMP;
1768 CompareType = ARMISD::CMPZ;
1771 ARMCC = DAG.getConstant(CondCode, MVT::i32);
1772 return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS);
1775 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
1776 static SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
1779 if (!isFloatingPointZero(RHS))
1780 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS);
1782 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS);
1783 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp);
1786 static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
1787 const ARMSubtarget *ST) {
1788 EVT VT = Op.getValueType();
1789 SDValue LHS = Op.getOperand(0);
1790 SDValue RHS = Op.getOperand(1);
1791 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1792 SDValue TrueVal = Op.getOperand(2);
1793 SDValue FalseVal = Op.getOperand(3);
1794 DebugLoc dl = Op.getDebugLoc();
1796 if (LHS.getValueType() == MVT::i32) {
1798 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1799 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb1Only(), dl);
1800 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC, CCR,Cmp);
1803 ARMCC::CondCodes CondCode, CondCode2;
1804 if (FPCCToARMCC(CC, CondCode, CondCode2))
1805 std::swap(TrueVal, FalseVal);
1807 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
1808 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1809 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
1810 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
1812 if (CondCode2 != ARMCC::AL) {
1813 SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
1814 // FIXME: Needs another CMP because flag can have but one use.
1815 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
1816 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
1817 Result, TrueVal, ARMCC2, CCR, Cmp2);
1822 static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
1823 const ARMSubtarget *ST) {
1824 SDValue Chain = Op.getOperand(0);
1825 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1826 SDValue LHS = Op.getOperand(2);
1827 SDValue RHS = Op.getOperand(3);
1828 SDValue Dest = Op.getOperand(4);
1829 DebugLoc dl = Op.getDebugLoc();
1831 if (LHS.getValueType() == MVT::i32) {
1833 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1834 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb1Only(), dl);
1835 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
1836 Chain, Dest, ARMCC, CCR,Cmp);
1839 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
1840 ARMCC::CondCodes CondCode, CondCode2;
1841 if (FPCCToARMCC(CC, CondCode, CondCode2))
1842 // Swap the LHS/RHS of the comparison if needed.
1843 std::swap(LHS, RHS);
1845 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
1846 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
1847 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1848 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
1849 SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp };
1850 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
1851 if (CondCode2 != ARMCC::AL) {
1852 ARMCC = DAG.getConstant(CondCode2, MVT::i32);
1853 SDValue Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) };
1854 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
1859 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) {
1860 SDValue Chain = Op.getOperand(0);
1861 SDValue Table = Op.getOperand(1);
1862 SDValue Index = Op.getOperand(2);
1863 DebugLoc dl = Op.getDebugLoc();
1865 EVT PTy = getPointerTy();
1866 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
1867 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
1868 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
1869 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
1870 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
1871 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
1872 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
1873 if (Subtarget->isThumb2()) {
1874 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
1875 // which does another jump to the destination. This also makes it easier
1876 // to translate it to TBB / TBH later.
1877 // FIXME: This might not work if the function is extremely large.
1878 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
1879 Addr, Op.getOperand(2), JTI, UId);
1881 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1882 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr, NULL, 0);
1883 Chain = Addr.getValue(1);
1884 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
1885 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
1887 Addr = DAG.getLoad(PTy, dl, Chain, Addr, NULL, 0);
1888 Chain = Addr.getValue(1);
1889 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
1893 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1894 DebugLoc dl = Op.getDebugLoc();
1896 Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI;
1897 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
1898 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
1901 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1902 EVT VT = Op.getValueType();
1903 DebugLoc dl = Op.getDebugLoc();
1905 Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF;
1907 Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
1908 return DAG.getNode(Opc, dl, VT, Op);
1911 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
1912 // Implement fcopysign with a fabs and a conditional fneg.
1913 SDValue Tmp0 = Op.getOperand(0);
1914 SDValue Tmp1 = Op.getOperand(1);
1915 DebugLoc dl = Op.getDebugLoc();
1916 EVT VT = Op.getValueType();
1917 EVT SrcVT = Tmp1.getValueType();
1918 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
1919 SDValue Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG, dl);
1920 SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
1921 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1922 return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp);
1925 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
1926 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1927 MFI->setFrameAddressIsTaken(true);
1928 EVT VT = Op.getValueType();
1929 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
1930 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1931 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
1932 ? ARM::R7 : ARM::R11;
1933 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
1935 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0);
1940 ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
1942 SDValue Dst, SDValue Src,
1943 SDValue Size, unsigned Align,
1945 const Value *DstSV, uint64_t DstSVOff,
1946 const Value *SrcSV, uint64_t SrcSVOff){
1947 // Do repeated 4-byte loads and stores. To be improved.
1948 // This requires 4-byte alignment.
1949 if ((Align & 3) != 0)
1951 // This requires the copy size to be a constant, preferrably
1952 // within a subtarget-specific limit.
1953 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
1956 uint64_t SizeVal = ConstantSize->getZExtValue();
1957 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
1960 unsigned BytesLeft = SizeVal & 3;
1961 unsigned NumMemOps = SizeVal >> 2;
1962 unsigned EmittedNumMemOps = 0;
1964 unsigned VTSize = 4;
1966 const unsigned MAX_LOADS_IN_LDM = 6;
1967 SDValue TFOps[MAX_LOADS_IN_LDM];
1968 SDValue Loads[MAX_LOADS_IN_LDM];
1969 uint64_t SrcOff = 0, DstOff = 0;
1971 // Emit up to MAX_LOADS_IN_LDM loads, then a TokenFactor barrier, then the
1972 // same number of stores. The loads and stores will get combined into
1973 // ldm/stm later on.
1974 while (EmittedNumMemOps < NumMemOps) {
1976 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
1977 Loads[i] = DAG.getLoad(VT, dl, Chain,
1978 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
1979 DAG.getConstant(SrcOff, MVT::i32)),
1980 SrcSV, SrcSVOff + SrcOff);
1981 TFOps[i] = Loads[i].getValue(1);
1984 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
1987 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
1988 TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
1989 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
1990 DAG.getConstant(DstOff, MVT::i32)),
1991 DstSV, DstSVOff + DstOff);
1994 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
1996 EmittedNumMemOps += i;
2002 // Issue loads / stores for the trailing (1 - 3) bytes.
2003 unsigned BytesLeftSave = BytesLeft;
2006 if (BytesLeft >= 2) {
2014 Loads[i] = DAG.getLoad(VT, dl, Chain,
2015 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
2016 DAG.getConstant(SrcOff, MVT::i32)),
2017 SrcSV, SrcSVOff + SrcOff);
2018 TFOps[i] = Loads[i].getValue(1);
2021 BytesLeft -= VTSize;
2023 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
2026 BytesLeft = BytesLeftSave;
2028 if (BytesLeft >= 2) {
2036 TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
2037 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
2038 DAG.getConstant(DstOff, MVT::i32)),
2039 DstSV, DstSVOff + DstOff);
2042 BytesLeft -= VTSize;
2044 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
2047 static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
2048 SDValue Op = N->getOperand(0);
2049 DebugLoc dl = N->getDebugLoc();
2050 if (N->getValueType(0) == MVT::f64) {
2051 // Turn i64->f64 into FMDRR.
2052 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2053 DAG.getConstant(0, MVT::i32));
2054 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2055 DAG.getConstant(1, MVT::i32));
2056 return DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
2059 // Turn f64->i64 into FMRRD.
2060 SDValue Cvt = DAG.getNode(ARMISD::FMRRD, dl,
2061 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
2063 // Merge the pieces into a single i64 value.
2064 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
2067 /// getZeroVector - Returns a vector of specified type with all zero elements.
2069 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2070 assert(VT.isVector() && "Expected a vector type");
2072 // Zero vectors are used to represent vector negation and in those cases
2073 // will be implemented with the NEON VNEG instruction. However, VNEG does
2074 // not support i64 elements, so sometimes the zero vectors will need to be
2075 // explicitly constructed. For those cases, and potentially other uses in
2076 // the future, always build zero vectors as <4 x i32> or <2 x i32> bitcasted
2077 // to their dest type. This ensures they get CSE'd.
2079 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
2080 if (VT.getSizeInBits() == 64)
2081 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
2083 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
2085 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2088 /// getOnesVector - Returns a vector of specified type with all bits set.
2090 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2091 assert(VT.isVector() && "Expected a vector type");
2093 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2094 // type. This ensures they get CSE'd.
2096 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
2097 if (VT.getSizeInBits() == 64)
2098 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
2100 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
2102 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2105 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
2106 const ARMSubtarget *ST) {
2107 EVT VT = N->getValueType(0);
2108 DebugLoc dl = N->getDebugLoc();
2110 // Lower vector shifts on NEON to use VSHL.
2111 if (VT.isVector()) {
2112 assert(ST->hasNEON() && "unexpected vector shift");
2114 // Left shifts translate directly to the vshiftu intrinsic.
2115 if (N->getOpcode() == ISD::SHL)
2116 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2117 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
2118 N->getOperand(0), N->getOperand(1));
2120 assert((N->getOpcode() == ISD::SRA ||
2121 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
2123 // NEON uses the same intrinsics for both left and right shifts. For
2124 // right shifts, the shift amounts are negative, so negate the vector of
2126 EVT ShiftVT = N->getOperand(1).getValueType();
2127 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
2128 getZeroVector(ShiftVT, DAG, dl),
2130 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
2131 Intrinsic::arm_neon_vshifts :
2132 Intrinsic::arm_neon_vshiftu);
2133 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2134 DAG.getConstant(vshiftInt, MVT::i32),
2135 N->getOperand(0), NegatedCount);
2138 assert(VT == MVT::i64 &&
2139 (N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
2140 "Unknown shift to lower!");
2142 // We only lower SRA, SRL of 1 here, all others use generic lowering.
2143 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
2144 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
2147 // If we are in thumb mode, we don't have RRX.
2148 if (ST->isThumb1Only()) return SDValue();
2150 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
2151 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2152 DAG.getConstant(0, MVT::i32));
2153 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2154 DAG.getConstant(1, MVT::i32));
2156 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
2157 // captures the result into a carry flag.
2158 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
2159 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
2161 // The low part is an ARMISD::RRX operand, which shifts the carry in.
2162 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
2164 // Merge the pieces into a single i64 value.
2165 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
2168 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
2169 SDValue TmpOp0, TmpOp1;
2170 bool Invert = false;
2174 SDValue Op0 = Op.getOperand(0);
2175 SDValue Op1 = Op.getOperand(1);
2176 SDValue CC = Op.getOperand(2);
2177 EVT VT = Op.getValueType();
2178 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
2179 DebugLoc dl = Op.getDebugLoc();
2181 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
2182 switch (SetCCOpcode) {
2183 default: llvm_unreachable("Illegal FP comparison"); break;
2185 case ISD::SETNE: Invert = true; // Fallthrough
2187 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2189 case ISD::SETLT: Swap = true; // Fallthrough
2191 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2193 case ISD::SETLE: Swap = true; // Fallthrough
2195 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2196 case ISD::SETUGE: Swap = true; // Fallthrough
2197 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
2198 case ISD::SETUGT: Swap = true; // Fallthrough
2199 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
2200 case ISD::SETUEQ: Invert = true; // Fallthrough
2202 // Expand this to (OLT | OGT).
2206 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2207 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
2209 case ISD::SETUO: Invert = true; // Fallthrough
2211 // Expand this to (OLT | OGE).
2215 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2216 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
2220 // Integer comparisons.
2221 switch (SetCCOpcode) {
2222 default: llvm_unreachable("Illegal integer comparison"); break;
2223 case ISD::SETNE: Invert = true;
2224 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2225 case ISD::SETLT: Swap = true;
2226 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2227 case ISD::SETLE: Swap = true;
2228 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2229 case ISD::SETULT: Swap = true;
2230 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
2231 case ISD::SETULE: Swap = true;
2232 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
2235 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
2236 if (Opc == ARMISD::VCEQ) {
2239 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
2241 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
2244 // Ignore bitconvert.
2245 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BIT_CONVERT)
2246 AndOp = AndOp.getOperand(0);
2248 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
2250 Op0 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(0));
2251 Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(1));
2258 std::swap(Op0, Op1);
2260 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
2263 Result = DAG.getNOT(dl, Result, VT);
2268 /// isVMOVSplat - Check if the specified splat value corresponds to an immediate
2269 /// VMOV instruction, and if so, return the constant being splatted.
2270 static SDValue isVMOVSplat(uint64_t SplatBits, uint64_t SplatUndef,
2271 unsigned SplatBitSize, SelectionDAG &DAG) {
2272 switch (SplatBitSize) {
2274 // Any 1-byte value is OK.
2275 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
2276 return DAG.getTargetConstant(SplatBits, MVT::i8);
2279 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
2280 if ((SplatBits & ~0xff) == 0 ||
2281 (SplatBits & ~0xff00) == 0)
2282 return DAG.getTargetConstant(SplatBits, MVT::i16);
2286 // NEON's 32-bit VMOV supports splat values where:
2287 // * only one byte is nonzero, or
2288 // * the least significant byte is 0xff and the second byte is nonzero, or
2289 // * the least significant 2 bytes are 0xff and the third is nonzero.
2290 if ((SplatBits & ~0xff) == 0 ||
2291 (SplatBits & ~0xff00) == 0 ||
2292 (SplatBits & ~0xff0000) == 0 ||
2293 (SplatBits & ~0xff000000) == 0)
2294 return DAG.getTargetConstant(SplatBits, MVT::i32);
2296 if ((SplatBits & ~0xffff) == 0 &&
2297 ((SplatBits | SplatUndef) & 0xff) == 0xff)
2298 return DAG.getTargetConstant(SplatBits | 0xff, MVT::i32);
2300 if ((SplatBits & ~0xffffff) == 0 &&
2301 ((SplatBits | SplatUndef) & 0xffff) == 0xffff)
2302 return DAG.getTargetConstant(SplatBits | 0xffff, MVT::i32);
2304 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
2305 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
2306 // VMOV.I32. A (very) minor optimization would be to replicate the value
2307 // and fall through here to test for a valid 64-bit splat. But, then the
2308 // caller would also need to check and handle the change in size.
2312 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
2313 uint64_t BitMask = 0xff;
2315 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
2316 if (((SplatBits | SplatUndef) & BitMask) == BitMask)
2318 else if ((SplatBits & BitMask) != 0)
2322 return DAG.getTargetConstant(Val, MVT::i64);
2326 llvm_unreachable("unexpected size for isVMOVSplat");
2333 /// getVMOVImm - If this is a build_vector of constants which can be
2334 /// formed by using a VMOV instruction of the specified element size,
2335 /// return the constant being splatted. The ByteSize field indicates the
2336 /// number of bytes of each element [1248].
2337 SDValue ARM::getVMOVImm(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
2338 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N);
2339 APInt SplatBits, SplatUndef;
2340 unsigned SplatBitSize;
2342 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
2343 HasAnyUndefs, ByteSize * 8))
2346 if (SplatBitSize > ByteSize * 8)
2349 return isVMOVSplat(SplatBits.getZExtValue(), SplatUndef.getZExtValue(),
2353 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
2354 /// instruction with the specified blocksize. (The order of the elements
2355 /// within each block of the vector is reversed.)
2356 static bool isVREVMask(ShuffleVectorSDNode *N, unsigned BlockSize) {
2357 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
2358 "Only possible block sizes for VREV are: 16, 32, 64");
2360 EVT VT = N->getValueType(0);
2361 unsigned NumElts = VT.getVectorNumElements();
2362 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2363 unsigned BlockElts = N->getMaskElt(0) + 1;
2365 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
2368 for (unsigned i = 0; i < NumElts; ++i) {
2369 if ((unsigned) N->getMaskElt(i) !=
2370 (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
2377 static SDValue BuildSplat(SDValue Val, EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2378 // Canonicalize all-zeros and all-ones vectors.
2379 ConstantSDNode *ConstVal = cast<ConstantSDNode>(Val.getNode());
2380 if (ConstVal->isNullValue())
2381 return getZeroVector(VT, DAG, dl);
2382 if (ConstVal->isAllOnesValue())
2383 return getOnesVector(VT, DAG, dl);
2386 if (VT.is64BitVector()) {
2387 switch (Val.getValueType().getSizeInBits()) {
2388 case 8: CanonicalVT = MVT::v8i8; break;
2389 case 16: CanonicalVT = MVT::v4i16; break;
2390 case 32: CanonicalVT = MVT::v2i32; break;
2391 case 64: CanonicalVT = MVT::v1i64; break;
2392 default: llvm_unreachable("unexpected splat element type"); break;
2395 assert(VT.is128BitVector() && "unknown splat vector size");
2396 switch (Val.getValueType().getSizeInBits()) {
2397 case 8: CanonicalVT = MVT::v16i8; break;
2398 case 16: CanonicalVT = MVT::v8i16; break;
2399 case 32: CanonicalVT = MVT::v4i32; break;
2400 case 64: CanonicalVT = MVT::v2i64; break;
2401 default: llvm_unreachable("unexpected splat element type"); break;
2405 // Build a canonical splat for this value.
2406 SmallVector<SDValue, 8> Ops;
2407 Ops.assign(CanonicalVT.getVectorNumElements(), Val);
2408 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, &Ops[0],
2410 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Res);
2413 // If this is a case we can't handle, return null and let the default
2414 // expansion code take care of it.
2415 static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
2416 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
2417 DebugLoc dl = Op.getDebugLoc();
2418 EVT VT = Op.getValueType();
2420 APInt SplatBits, SplatUndef;
2421 unsigned SplatBitSize;
2423 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
2424 SDValue Val = isVMOVSplat(SplatBits.getZExtValue(),
2425 SplatUndef.getZExtValue(), SplatBitSize, DAG);
2427 return BuildSplat(Val, VT, DAG, dl);
2430 // If there are only 2 elements in a 128-bit vector, insert them into an
2431 // undef vector. This handles the common case for 128-bit vector argument
2432 // passing, where the insertions should be translated to subreg accesses
2433 // with no real instructions.
2434 if (VT.is128BitVector() && Op.getNumOperands() == 2) {
2435 SDValue Val = DAG.getUNDEF(VT);
2436 SDValue Op0 = Op.getOperand(0);
2437 SDValue Op1 = Op.getOperand(1);
2438 if (Op0.getOpcode() != ISD::UNDEF)
2439 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, Op0,
2440 DAG.getIntPtrConstant(0));
2441 if (Op1.getOpcode() != ISD::UNDEF)
2442 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, Op1,
2443 DAG.getIntPtrConstant(1));
2450 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
2451 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
2452 DebugLoc dl = Op.getDebugLoc();
2453 EVT VT = Op.getValueType();
2455 // Convert shuffles that are directly supported on NEON to target-specific
2456 // DAG nodes, instead of keeping them as shuffles and matching them again
2457 // during code selection. This is more efficient and avoids the possibility
2458 // of inconsistencies between legalization and selection.
2459 // FIXME: floating-point vectors should be canonicalized to integer vectors
2460 // of the same time so that they get CSEd properly.
2461 if (SVN->isSplat()) {
2462 int Lane = SVN->getSplatIndex();
2463 SDValue Op0 = SVN->getOperand(0);
2464 if (Lane == 0 && Op0.getOpcode() == ISD::SCALAR_TO_VECTOR) {
2465 return DAG.getNode(ARMISD::VDUP, dl, VT, Op0.getOperand(0));
2467 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, SVN->getOperand(0),
2468 DAG.getConstant(Lane, MVT::i32));
2470 if (isVREVMask(SVN, 64))
2471 return DAG.getNode(ARMISD::VREV64, dl, VT, SVN->getOperand(0));
2472 if (isVREVMask(SVN, 32))
2473 return DAG.getNode(ARMISD::VREV32, dl, VT, SVN->getOperand(0));
2474 if (isVREVMask(SVN, 16))
2475 return DAG.getNode(ARMISD::VREV16, dl, VT, SVN->getOperand(0));
2480 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
2484 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
2485 EVT VT = Op.getValueType();
2486 DebugLoc dl = Op.getDebugLoc();
2487 assert((VT == MVT::i8 || VT == MVT::i16) &&
2488 "unexpected type for custom-lowering vector extract");
2489 SDValue Vec = Op.getOperand(0);
2490 SDValue Lane = Op.getOperand(1);
2491 Op = DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
2492 Op = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Op, DAG.getValueType(VT));
2493 return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
2496 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
2497 // The only time a CONCAT_VECTORS operation can have legal types is when
2498 // two 64-bit vectors are concatenated to a 128-bit vector.
2499 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
2500 "unexpected CONCAT_VECTORS");
2501 DebugLoc dl = Op.getDebugLoc();
2502 SDValue Val = DAG.getUNDEF(MVT::v2f64);
2503 SDValue Op0 = Op.getOperand(0);
2504 SDValue Op1 = Op.getOperand(1);
2505 if (Op0.getOpcode() != ISD::UNDEF)
2506 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
2507 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op0),
2508 DAG.getIntPtrConstant(0));
2509 if (Op1.getOpcode() != ISD::UNDEF)
2510 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
2511 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op1),
2512 DAG.getIntPtrConstant(1));
2513 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Val);
2516 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
2517 switch (Op.getOpcode()) {
2518 default: llvm_unreachable("Don't know how to custom lower this!");
2519 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2520 case ISD::GlobalAddress:
2521 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
2522 LowerGlobalAddressELF(Op, DAG);
2523 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
2524 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, Subtarget);
2525 case ISD::BR_CC: return LowerBR_CC(Op, DAG, Subtarget);
2526 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
2527 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
2528 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex);
2529 case ISD::SINT_TO_FP:
2530 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
2531 case ISD::FP_TO_SINT:
2532 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
2533 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
2534 case ISD::RETURNADDR: break;
2535 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
2536 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
2537 case ISD::INTRINSIC_VOID:
2538 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
2539 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2540 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(Op.getNode(), DAG);
2543 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
2544 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
2545 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
2546 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
2547 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
2548 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
2549 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
2554 /// ReplaceNodeResults - Replace the results of node with an illegal result
2555 /// type with new values built out of custom code.
2556 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
2557 SmallVectorImpl<SDValue>&Results,
2558 SelectionDAG &DAG) {
2559 switch (N->getOpcode()) {
2561 llvm_unreachable("Don't know how to custom expand this!");
2563 case ISD::BIT_CONVERT:
2564 Results.push_back(ExpandBIT_CONVERT(N, DAG));
2568 SDValue Res = LowerShift(N, DAG, Subtarget);
2570 Results.push_back(Res);
2576 //===----------------------------------------------------------------------===//
2577 // ARM Scheduler Hooks
2578 //===----------------------------------------------------------------------===//
2581 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
2582 MachineBasicBlock *BB) const {
2583 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2584 DebugLoc dl = MI->getDebugLoc();
2585 switch (MI->getOpcode()) {
2587 llvm_unreachable("Unexpected instr type to insert");
2588 case ARM::tMOVCCr_pseudo: {
2589 // To "insert" a SELECT_CC instruction, we actually have to insert the
2590 // diamond control-flow pattern. The incoming instruction knows the
2591 // destination vreg to set, the condition code register to branch on, the
2592 // true/false values to select between, and a branch opcode to use.
2593 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2594 MachineFunction::iterator It = BB;
2600 // cmpTY ccX, r1, r2
2602 // fallthrough --> copy0MBB
2603 MachineBasicBlock *thisMBB = BB;
2604 MachineFunction *F = BB->getParent();
2605 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
2606 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
2607 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
2608 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
2609 F->insert(It, copy0MBB);
2610 F->insert(It, sinkMBB);
2611 // Update machine-CFG edges by first adding all successors of the current
2612 // block to the new block which will contain the Phi node for the select.
2613 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
2614 e = BB->succ_end(); i != e; ++i)
2615 sinkMBB->addSuccessor(*i);
2616 // Next, remove all successors of the current block, and add the true
2617 // and fallthrough blocks as its successors.
2618 while(!BB->succ_empty())
2619 BB->removeSuccessor(BB->succ_begin());
2620 BB->addSuccessor(copy0MBB);
2621 BB->addSuccessor(sinkMBB);
2624 // %FalseValue = ...
2625 // # fallthrough to sinkMBB
2628 // Update machine-CFG edges
2629 BB->addSuccessor(sinkMBB);
2632 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
2635 BuildMI(BB, dl, TII->get(ARM::PHI), MI->getOperand(0).getReg())
2636 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
2637 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
2639 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
2646 case ARM::t2SUBrSPi_:
2647 case ARM::t2SUBrSPi12_:
2648 case ARM::t2SUBrSPs_: {
2649 MachineFunction *MF = BB->getParent();
2650 unsigned DstReg = MI->getOperand(0).getReg();
2651 unsigned SrcReg = MI->getOperand(1).getReg();
2652 bool DstIsDead = MI->getOperand(0).isDead();
2653 bool SrcIsKill = MI->getOperand(1).isKill();
2655 if (SrcReg != ARM::SP) {
2656 // Copy the source to SP from virtual register.
2657 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(SrcReg);
2658 unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
2659 ? ARM::tMOVtgpr2gpr : ARM::tMOVgpr2gpr;
2660 BuildMI(BB, dl, TII->get(CopyOpc), ARM::SP)
2661 .addReg(SrcReg, getKillRegState(SrcIsKill));
2665 bool NeedPred = false, NeedCC = false, NeedOp3 = false;
2666 switch (MI->getOpcode()) {
2668 llvm_unreachable("Unexpected pseudo instruction!");
2674 OpOpc = ARM::tADDspr;
2677 OpOpc = ARM::tSUBspi;
2679 case ARM::t2SUBrSPi_:
2680 OpOpc = ARM::t2SUBrSPi;
2681 NeedPred = true; NeedCC = true;
2683 case ARM::t2SUBrSPi12_:
2684 OpOpc = ARM::t2SUBrSPi12;
2687 case ARM::t2SUBrSPs_:
2688 OpOpc = ARM::t2SUBrSPs;
2689 NeedPred = true; NeedCC = true; NeedOp3 = true;
2692 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(OpOpc), ARM::SP);
2693 if (OpOpc == ARM::tAND)
2694 AddDefaultT1CC(MIB);
2695 MIB.addReg(ARM::SP);
2696 MIB.addOperand(MI->getOperand(2));
2698 MIB.addOperand(MI->getOperand(3));
2700 AddDefaultPred(MIB);
2704 // Copy the result from SP to virtual register.
2705 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(DstReg);
2706 unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
2707 ? ARM::tMOVgpr2tgpr : ARM::tMOVgpr2gpr;
2708 BuildMI(BB, dl, TII->get(CopyOpc))
2709 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead))
2711 MF->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
2717 //===----------------------------------------------------------------------===//
2718 // ARM Optimization Hooks
2719 //===----------------------------------------------------------------------===//
2722 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
2723 TargetLowering::DAGCombinerInfo &DCI) {
2724 SelectionDAG &DAG = DCI.DAG;
2725 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2726 EVT VT = N->getValueType(0);
2727 unsigned Opc = N->getOpcode();
2728 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
2729 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
2730 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
2731 ISD::CondCode CC = ISD::SETCC_INVALID;
2734 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
2736 SDValue CCOp = Slct.getOperand(0);
2737 if (CCOp.getOpcode() == ISD::SETCC)
2738 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
2741 bool DoXform = false;
2743 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
2746 if (LHS.getOpcode() == ISD::Constant &&
2747 cast<ConstantSDNode>(LHS)->isNullValue()) {
2749 } else if (CC != ISD::SETCC_INVALID &&
2750 RHS.getOpcode() == ISD::Constant &&
2751 cast<ConstantSDNode>(RHS)->isNullValue()) {
2752 std::swap(LHS, RHS);
2753 SDValue Op0 = Slct.getOperand(0);
2754 EVT OpVT = isSlctCC ? Op0.getValueType() :
2755 Op0.getOperand(0).getValueType();
2756 bool isInt = OpVT.isInteger();
2757 CC = ISD::getSetCCInverse(CC, isInt);
2759 if (!TLI.isCondCodeLegal(CC, OpVT))
2760 return SDValue(); // Inverse operator isn't legal.
2767 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
2769 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
2770 Slct.getOperand(0), Slct.getOperand(1), CC);
2771 SDValue CCOp = Slct.getOperand(0);
2773 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
2774 CCOp.getOperand(0), CCOp.getOperand(1), CC);
2775 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
2776 CCOp, OtherOp, Result);
2781 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
2782 static SDValue PerformADDCombine(SDNode *N,
2783 TargetLowering::DAGCombinerInfo &DCI) {
2784 // added by evan in r37685 with no testcase.
2785 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2787 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
2788 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
2789 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
2790 if (Result.getNode()) return Result;
2792 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
2793 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
2794 if (Result.getNode()) return Result;
2800 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
2801 static SDValue PerformSUBCombine(SDNode *N,
2802 TargetLowering::DAGCombinerInfo &DCI) {
2803 // added by evan in r37685 with no testcase.
2804 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2806 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
2807 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
2808 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
2809 if (Result.getNode()) return Result;
2816 /// PerformFMRRDCombine - Target-specific dag combine xforms for ARMISD::FMRRD.
2817 static SDValue PerformFMRRDCombine(SDNode *N,
2818 TargetLowering::DAGCombinerInfo &DCI) {
2819 // fmrrd(fmdrr x, y) -> x,y
2820 SDValue InDouble = N->getOperand(0);
2821 if (InDouble.getOpcode() == ARMISD::FMDRR)
2822 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
2826 /// getVShiftImm - Check if this is a valid build_vector for the immediate
2827 /// operand of a vector shift operation, where all the elements of the
2828 /// build_vector must have the same constant integer value.
2829 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
2830 // Ignore bit_converts.
2831 while (Op.getOpcode() == ISD::BIT_CONVERT)
2832 Op = Op.getOperand(0);
2833 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
2834 APInt SplatBits, SplatUndef;
2835 unsigned SplatBitSize;
2837 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
2838 HasAnyUndefs, ElementBits) ||
2839 SplatBitSize > ElementBits)
2841 Cnt = SplatBits.getSExtValue();
2845 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
2846 /// operand of a vector shift left operation. That value must be in the range:
2847 /// 0 <= Value < ElementBits for a left shift; or
2848 /// 0 <= Value <= ElementBits for a long left shift.
2849 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
2850 assert(VT.isVector() && "vector shift count is not a vector type");
2851 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
2852 if (! getVShiftImm(Op, ElementBits, Cnt))
2854 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
2857 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
2858 /// operand of a vector shift right operation. For a shift opcode, the value
2859 /// is positive, but for an intrinsic the value count must be negative. The
2860 /// absolute value must be in the range:
2861 /// 1 <= |Value| <= ElementBits for a right shift; or
2862 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
2863 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
2865 assert(VT.isVector() && "vector shift count is not a vector type");
2866 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
2867 if (! getVShiftImm(Op, ElementBits, Cnt))
2871 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
2874 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
2875 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
2876 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
2879 // Don't do anything for most intrinsics.
2882 // Vector shifts: check for immediate versions and lower them.
2883 // Note: This is done during DAG combining instead of DAG legalizing because
2884 // the build_vectors for 64-bit vector element shift counts are generally
2885 // not legal, and it is hard to see their values after they get legalized to
2886 // loads from a constant pool.
2887 case Intrinsic::arm_neon_vshifts:
2888 case Intrinsic::arm_neon_vshiftu:
2889 case Intrinsic::arm_neon_vshiftls:
2890 case Intrinsic::arm_neon_vshiftlu:
2891 case Intrinsic::arm_neon_vshiftn:
2892 case Intrinsic::arm_neon_vrshifts:
2893 case Intrinsic::arm_neon_vrshiftu:
2894 case Intrinsic::arm_neon_vrshiftn:
2895 case Intrinsic::arm_neon_vqshifts:
2896 case Intrinsic::arm_neon_vqshiftu:
2897 case Intrinsic::arm_neon_vqshiftsu:
2898 case Intrinsic::arm_neon_vqshiftns:
2899 case Intrinsic::arm_neon_vqshiftnu:
2900 case Intrinsic::arm_neon_vqshiftnsu:
2901 case Intrinsic::arm_neon_vqrshiftns:
2902 case Intrinsic::arm_neon_vqrshiftnu:
2903 case Intrinsic::arm_neon_vqrshiftnsu: {
2904 EVT VT = N->getOperand(1).getValueType();
2906 unsigned VShiftOpc = 0;
2909 case Intrinsic::arm_neon_vshifts:
2910 case Intrinsic::arm_neon_vshiftu:
2911 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
2912 VShiftOpc = ARMISD::VSHL;
2915 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
2916 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
2917 ARMISD::VSHRs : ARMISD::VSHRu);
2922 case Intrinsic::arm_neon_vshiftls:
2923 case Intrinsic::arm_neon_vshiftlu:
2924 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
2926 llvm_unreachable("invalid shift count for vshll intrinsic");
2928 case Intrinsic::arm_neon_vrshifts:
2929 case Intrinsic::arm_neon_vrshiftu:
2930 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
2934 case Intrinsic::arm_neon_vqshifts:
2935 case Intrinsic::arm_neon_vqshiftu:
2936 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
2940 case Intrinsic::arm_neon_vqshiftsu:
2941 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
2943 llvm_unreachable("invalid shift count for vqshlu intrinsic");
2945 case Intrinsic::arm_neon_vshiftn:
2946 case Intrinsic::arm_neon_vrshiftn:
2947 case Intrinsic::arm_neon_vqshiftns:
2948 case Intrinsic::arm_neon_vqshiftnu:
2949 case Intrinsic::arm_neon_vqshiftnsu:
2950 case Intrinsic::arm_neon_vqrshiftns:
2951 case Intrinsic::arm_neon_vqrshiftnu:
2952 case Intrinsic::arm_neon_vqrshiftnsu:
2953 // Narrowing shifts require an immediate right shift.
2954 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
2956 llvm_unreachable("invalid shift count for narrowing vector shift intrinsic");
2959 llvm_unreachable("unhandled vector shift");
2963 case Intrinsic::arm_neon_vshifts:
2964 case Intrinsic::arm_neon_vshiftu:
2965 // Opcode already set above.
2967 case Intrinsic::arm_neon_vshiftls:
2968 case Intrinsic::arm_neon_vshiftlu:
2969 if (Cnt == VT.getVectorElementType().getSizeInBits())
2970 VShiftOpc = ARMISD::VSHLLi;
2972 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
2973 ARMISD::VSHLLs : ARMISD::VSHLLu);
2975 case Intrinsic::arm_neon_vshiftn:
2976 VShiftOpc = ARMISD::VSHRN; break;
2977 case Intrinsic::arm_neon_vrshifts:
2978 VShiftOpc = ARMISD::VRSHRs; break;
2979 case Intrinsic::arm_neon_vrshiftu:
2980 VShiftOpc = ARMISD::VRSHRu; break;
2981 case Intrinsic::arm_neon_vrshiftn:
2982 VShiftOpc = ARMISD::VRSHRN; break;
2983 case Intrinsic::arm_neon_vqshifts:
2984 VShiftOpc = ARMISD::VQSHLs; break;
2985 case Intrinsic::arm_neon_vqshiftu:
2986 VShiftOpc = ARMISD::VQSHLu; break;
2987 case Intrinsic::arm_neon_vqshiftsu:
2988 VShiftOpc = ARMISD::VQSHLsu; break;
2989 case Intrinsic::arm_neon_vqshiftns:
2990 VShiftOpc = ARMISD::VQSHRNs; break;
2991 case Intrinsic::arm_neon_vqshiftnu:
2992 VShiftOpc = ARMISD::VQSHRNu; break;
2993 case Intrinsic::arm_neon_vqshiftnsu:
2994 VShiftOpc = ARMISD::VQSHRNsu; break;
2995 case Intrinsic::arm_neon_vqrshiftns:
2996 VShiftOpc = ARMISD::VQRSHRNs; break;
2997 case Intrinsic::arm_neon_vqrshiftnu:
2998 VShiftOpc = ARMISD::VQRSHRNu; break;
2999 case Intrinsic::arm_neon_vqrshiftnsu:
3000 VShiftOpc = ARMISD::VQRSHRNsu; break;
3003 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
3004 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
3007 case Intrinsic::arm_neon_vshiftins: {
3008 EVT VT = N->getOperand(1).getValueType();
3010 unsigned VShiftOpc = 0;
3012 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
3013 VShiftOpc = ARMISD::VSLI;
3014 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
3015 VShiftOpc = ARMISD::VSRI;
3017 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
3020 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
3021 N->getOperand(1), N->getOperand(2),
3022 DAG.getConstant(Cnt, MVT::i32));
3025 case Intrinsic::arm_neon_vqrshifts:
3026 case Intrinsic::arm_neon_vqrshiftu:
3027 // No immediate versions of these to check for.
3034 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
3035 /// lowers them. As with the vector shift intrinsics, this is done during DAG
3036 /// combining instead of DAG legalizing because the build_vectors for 64-bit
3037 /// vector element shift counts are generally not legal, and it is hard to see
3038 /// their values after they get legalized to loads from a constant pool.
3039 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
3040 const ARMSubtarget *ST) {
3041 EVT VT = N->getValueType(0);
3043 // Nothing to be done for scalar shifts.
3044 if (! VT.isVector())
3047 assert(ST->hasNEON() && "unexpected vector shift");
3050 switch (N->getOpcode()) {
3051 default: llvm_unreachable("unexpected shift opcode");
3054 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
3055 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
3056 DAG.getConstant(Cnt, MVT::i32));
3061 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
3062 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
3063 ARMISD::VSHRs : ARMISD::VSHRu);
3064 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
3065 DAG.getConstant(Cnt, MVT::i32));
3071 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
3072 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
3073 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
3074 const ARMSubtarget *ST) {
3075 SDValue N0 = N->getOperand(0);
3077 // Check for sign- and zero-extensions of vector extract operations of 8-
3078 // and 16-bit vector elements. NEON supports these directly. They are
3079 // handled during DAG combining because type legalization will promote them
3080 // to 32-bit types and it is messy to recognize the operations after that.
3081 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
3082 SDValue Vec = N0.getOperand(0);
3083 SDValue Lane = N0.getOperand(1);
3084 EVT VT = N->getValueType(0);
3085 EVT EltVT = N0.getValueType();
3086 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3088 if (VT == MVT::i32 &&
3089 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
3090 TLI.isTypeLegal(Vec.getValueType())) {
3093 switch (N->getOpcode()) {
3094 default: llvm_unreachable("unexpected opcode");
3095 case ISD::SIGN_EXTEND:
3096 Opc = ARMISD::VGETLANEs;
3098 case ISD::ZERO_EXTEND:
3099 case ISD::ANY_EXTEND:
3100 Opc = ARMISD::VGETLANEu;
3103 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
3110 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
3111 DAGCombinerInfo &DCI) const {
3112 switch (N->getOpcode()) {
3114 case ISD::ADD: return PerformADDCombine(N, DCI);
3115 case ISD::SUB: return PerformSUBCombine(N, DCI);
3116 case ARMISD::FMRRD: return PerformFMRRDCombine(N, DCI);
3117 case ISD::INTRINSIC_WO_CHAIN:
3118 return PerformIntrinsicCombine(N, DCI.DAG);
3122 return PerformShiftCombine(N, DCI.DAG, Subtarget);
3123 case ISD::SIGN_EXTEND:
3124 case ISD::ZERO_EXTEND:
3125 case ISD::ANY_EXTEND:
3126 return PerformExtendCombine(N, DCI.DAG, Subtarget);
3131 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
3136 switch (VT.getSimpleVT().SimpleTy) {
3137 default: return false;
3152 if ((V & (Scale - 1)) != 0)
3155 return V == (V & ((1LL << 5) - 1));
3158 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
3159 const ARMSubtarget *Subtarget) {
3166 switch (VT.getSimpleVT().SimpleTy) {
3167 default: return false;
3172 // + imm12 or - imm8
3174 return V == (V & ((1LL << 8) - 1));
3175 return V == (V & ((1LL << 12) - 1));
3178 // Same as ARM mode. FIXME: NEON?
3179 if (!Subtarget->hasVFP2())
3184 return V == (V & ((1LL << 8) - 1));
3188 /// isLegalAddressImmediate - Return true if the integer value can be used
3189 /// as the offset of the target addressing mode for load / store of the
3191 static bool isLegalAddressImmediate(int64_t V, EVT VT,
3192 const ARMSubtarget *Subtarget) {
3199 if (Subtarget->isThumb1Only())
3200 return isLegalT1AddressImmediate(V, VT);
3201 else if (Subtarget->isThumb2())
3202 return isLegalT2AddressImmediate(V, VT, Subtarget);
3207 switch (VT.getSimpleVT().SimpleTy) {
3208 default: return false;
3213 return V == (V & ((1LL << 12) - 1));
3216 return V == (V & ((1LL << 8) - 1));
3219 if (!Subtarget->hasVFP2()) // FIXME: NEON?
3224 return V == (V & ((1LL << 8) - 1));
3228 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
3230 int Scale = AM.Scale;
3234 switch (VT.getSimpleVT().SimpleTy) {
3235 default: return false;
3244 return Scale == 2 || Scale == 4 || Scale == 8;
3247 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
3251 // Note, we allow "void" uses (basically, uses that aren't loads or
3252 // stores), because arm allows folding a scale into many arithmetic
3253 // operations. This should be made more precise and revisited later.
3255 // Allow r << imm, but the imm has to be a multiple of two.
3256 if (Scale & 1) return false;
3257 return isPowerOf2_32(Scale);
3261 /// isLegalAddressingMode - Return true if the addressing mode represented
3262 /// by AM is legal for this target, for a load/store of the specified type.
3263 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
3264 const Type *Ty) const {
3265 EVT VT = getValueType(Ty, true);
3266 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
3269 // Can never fold addr of global into load/store.
3274 case 0: // no scale reg, must be "r+i" or "r", or "i".
3277 if (Subtarget->isThumb1Only())
3281 // ARM doesn't support any R+R*scale+imm addr modes.
3288 if (Subtarget->isThumb2())
3289 return isLegalT2ScaledAddressingMode(AM, VT);
3291 int Scale = AM.Scale;
3292 switch (VT.getSimpleVT().SimpleTy) {
3293 default: return false;
3297 if (Scale < 0) Scale = -Scale;
3301 return isPowerOf2_32(Scale & ~1);
3305 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
3310 // Note, we allow "void" uses (basically, uses that aren't loads or
3311 // stores), because arm allows folding a scale into many arithmetic
3312 // operations. This should be made more precise and revisited later.
3314 // Allow r << imm, but the imm has to be a multiple of two.
3315 if (Scale & 1) return false;
3316 return isPowerOf2_32(Scale);
3323 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
3324 bool isSEXTLoad, SDValue &Base,
3325 SDValue &Offset, bool &isInc,
3326 SelectionDAG &DAG) {
3327 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
3330 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
3332 Base = Ptr->getOperand(0);
3333 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
3334 int RHSC = (int)RHS->getZExtValue();
3335 if (RHSC < 0 && RHSC > -256) {
3336 assert(Ptr->getOpcode() == ISD::ADD);
3338 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
3342 isInc = (Ptr->getOpcode() == ISD::ADD);
3343 Offset = Ptr->getOperand(1);
3345 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
3347 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
3348 int RHSC = (int)RHS->getZExtValue();
3349 if (RHSC < 0 && RHSC > -0x1000) {
3350 assert(Ptr->getOpcode() == ISD::ADD);
3352 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
3353 Base = Ptr->getOperand(0);
3358 if (Ptr->getOpcode() == ISD::ADD) {
3360 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
3361 if (ShOpcVal != ARM_AM::no_shift) {
3362 Base = Ptr->getOperand(1);
3363 Offset = Ptr->getOperand(0);
3365 Base = Ptr->getOperand(0);
3366 Offset = Ptr->getOperand(1);
3371 isInc = (Ptr->getOpcode() == ISD::ADD);
3372 Base = Ptr->getOperand(0);
3373 Offset = Ptr->getOperand(1);
3377 // FIXME: Use FLDM / FSTM to emulate indexed FP load / store.
3381 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
3382 bool isSEXTLoad, SDValue &Base,
3383 SDValue &Offset, bool &isInc,
3384 SelectionDAG &DAG) {
3385 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
3388 Base = Ptr->getOperand(0);
3389 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
3390 int RHSC = (int)RHS->getZExtValue();
3391 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
3392 assert(Ptr->getOpcode() == ISD::ADD);
3394 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
3396 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
3397 isInc = Ptr->getOpcode() == ISD::ADD;
3398 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
3406 /// getPreIndexedAddressParts - returns true by value, base pointer and
3407 /// offset pointer and addressing mode by reference if the node's address
3408 /// can be legally represented as pre-indexed load / store address.
3410 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
3412 ISD::MemIndexedMode &AM,
3413 SelectionDAG &DAG) const {
3414 if (Subtarget->isThumb1Only())
3419 bool isSEXTLoad = false;
3420 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3421 Ptr = LD->getBasePtr();
3422 VT = LD->getMemoryVT();
3423 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
3424 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3425 Ptr = ST->getBasePtr();
3426 VT = ST->getMemoryVT();
3431 bool isLegal = false;
3432 if (Subtarget->isThumb2())
3433 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
3434 Offset, isInc, DAG);
3436 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
3437 Offset, isInc, DAG);
3441 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
3445 /// getPostIndexedAddressParts - returns true by value, base pointer and
3446 /// offset pointer and addressing mode by reference if this node can be
3447 /// combined with a load / store to form a post-indexed load / store.
3448 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
3451 ISD::MemIndexedMode &AM,
3452 SelectionDAG &DAG) const {
3453 if (Subtarget->isThumb1Only())
3458 bool isSEXTLoad = false;
3459 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3460 VT = LD->getMemoryVT();
3461 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
3462 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3463 VT = ST->getMemoryVT();
3468 bool isLegal = false;
3469 if (Subtarget->isThumb2())
3470 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
3473 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
3478 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
3482 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
3486 const SelectionDAG &DAG,
3487 unsigned Depth) const {
3488 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
3489 switch (Op.getOpcode()) {
3491 case ARMISD::CMOV: {
3492 // Bits are known zero/one if known on the LHS and RHS.
3493 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
3494 if (KnownZero == 0 && KnownOne == 0) return;
3496 APInt KnownZeroRHS, KnownOneRHS;
3497 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
3498 KnownZeroRHS, KnownOneRHS, Depth+1);
3499 KnownZero &= KnownZeroRHS;
3500 KnownOne &= KnownOneRHS;
3506 //===----------------------------------------------------------------------===//
3507 // ARM Inline Assembly Support
3508 //===----------------------------------------------------------------------===//
3510 /// getConstraintType - Given a constraint letter, return the type of
3511 /// constraint it is for this target.
3512 ARMTargetLowering::ConstraintType
3513 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
3514 if (Constraint.size() == 1) {
3515 switch (Constraint[0]) {
3517 case 'l': return C_RegisterClass;
3518 case 'w': return C_RegisterClass;
3521 return TargetLowering::getConstraintType(Constraint);
3524 std::pair<unsigned, const TargetRegisterClass*>
3525 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
3527 if (Constraint.size() == 1) {
3528 // GCC RS6000 Constraint Letters
3529 switch (Constraint[0]) {
3531 if (Subtarget->isThumb1Only())
3532 return std::make_pair(0U, ARM::tGPRRegisterClass);
3534 return std::make_pair(0U, ARM::GPRRegisterClass);
3536 return std::make_pair(0U, ARM::GPRRegisterClass);
3539 return std::make_pair(0U, ARM::SPRRegisterClass);
3541 return std::make_pair(0U, ARM::DPRRegisterClass);
3545 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3548 std::vector<unsigned> ARMTargetLowering::
3549 getRegClassForInlineAsmConstraint(const std::string &Constraint,
3551 if (Constraint.size() != 1)
3552 return std::vector<unsigned>();
3554 switch (Constraint[0]) { // GCC ARM Constraint Letters
3557 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
3558 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
3561 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
3562 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
3563 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
3564 ARM::R12, ARM::LR, 0);
3567 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
3568 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
3569 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
3570 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
3571 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
3572 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
3573 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
3574 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
3576 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
3577 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
3578 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
3579 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
3583 return std::vector<unsigned>();
3586 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3587 /// vector. If it is invalid, don't add anything to Ops.
3588 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
3591 std::vector<SDValue>&Ops,
3592 SelectionDAG &DAG) const {
3593 SDValue Result(0, 0);
3595 switch (Constraint) {
3597 case 'I': case 'J': case 'K': case 'L':
3598 case 'M': case 'N': case 'O':
3599 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3603 int64_t CVal64 = C->getSExtValue();
3604 int CVal = (int) CVal64;
3605 // None of these constraints allow values larger than 32 bits. Check
3606 // that the value fits in an int.
3610 switch (Constraint) {
3612 if (Subtarget->isThumb1Only()) {
3613 // This must be a constant between 0 and 255, for ADD
3615 if (CVal >= 0 && CVal <= 255)
3617 } else if (Subtarget->isThumb2()) {
3618 // A constant that can be used as an immediate value in a
3619 // data-processing instruction.
3620 if (ARM_AM::getT2SOImmVal(CVal) != -1)
3623 // A constant that can be used as an immediate value in a
3624 // data-processing instruction.
3625 if (ARM_AM::getSOImmVal(CVal) != -1)
3631 if (Subtarget->isThumb()) { // FIXME thumb2
3632 // This must be a constant between -255 and -1, for negated ADD
3633 // immediates. This can be used in GCC with an "n" modifier that
3634 // prints the negated value, for use with SUB instructions. It is
3635 // not useful otherwise but is implemented for compatibility.
3636 if (CVal >= -255 && CVal <= -1)
3639 // This must be a constant between -4095 and 4095. It is not clear
3640 // what this constraint is intended for. Implemented for
3641 // compatibility with GCC.
3642 if (CVal >= -4095 && CVal <= 4095)
3648 if (Subtarget->isThumb1Only()) {
3649 // A 32-bit value where only one byte has a nonzero value. Exclude
3650 // zero to match GCC. This constraint is used by GCC internally for
3651 // constants that can be loaded with a move/shift combination.
3652 // It is not useful otherwise but is implemented for compatibility.
3653 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
3655 } else if (Subtarget->isThumb2()) {
3656 // A constant whose bitwise inverse can be used as an immediate
3657 // value in a data-processing instruction. This can be used in GCC
3658 // with a "B" modifier that prints the inverted value, for use with
3659 // BIC and MVN instructions. It is not useful otherwise but is
3660 // implemented for compatibility.
3661 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
3664 // A constant whose bitwise inverse can be used as an immediate
3665 // value in a data-processing instruction. This can be used in GCC
3666 // with a "B" modifier that prints the inverted value, for use with
3667 // BIC and MVN instructions. It is not useful otherwise but is
3668 // implemented for compatibility.
3669 if (ARM_AM::getSOImmVal(~CVal) != -1)
3675 if (Subtarget->isThumb1Only()) {
3676 // This must be a constant between -7 and 7,
3677 // for 3-operand ADD/SUB immediate instructions.
3678 if (CVal >= -7 && CVal < 7)
3680 } else if (Subtarget->isThumb2()) {
3681 // A constant whose negation can be used as an immediate value in a
3682 // data-processing instruction. This can be used in GCC with an "n"
3683 // modifier that prints the negated value, for use with SUB
3684 // instructions. It is not useful otherwise but is implemented for
3686 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
3689 // A constant whose negation can be used as an immediate value in a
3690 // data-processing instruction. This can be used in GCC with an "n"
3691 // modifier that prints the negated value, for use with SUB
3692 // instructions. It is not useful otherwise but is implemented for
3694 if (ARM_AM::getSOImmVal(-CVal) != -1)
3700 if (Subtarget->isThumb()) { // FIXME thumb2
3701 // This must be a multiple of 4 between 0 and 1020, for
3702 // ADD sp + immediate.
3703 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
3706 // A power of two or a constant between 0 and 32. This is used in
3707 // GCC for the shift amount on shifted register operands, but it is
3708 // useful in general for any shift amounts.
3709 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
3715 if (Subtarget->isThumb()) { // FIXME thumb2
3716 // This must be a constant between 0 and 31, for shift amounts.
3717 if (CVal >= 0 && CVal <= 31)
3723 if (Subtarget->isThumb()) { // FIXME thumb2
3724 // This must be a multiple of 4 between -508 and 508, for
3725 // ADD/SUB sp = sp + immediate.
3726 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
3731 Result = DAG.getTargetConstant(CVal, Op.getValueType());
3735 if (Result.getNode()) {
3736 Ops.push_back(Result);
3739 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,