1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "arm-isel"
17 #include "ARMAddressingModes.h"
18 #include "ARMCallingConv.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMISelLowering.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMPerfectShuffle.h"
23 #include "ARMRegisterInfo.h"
24 #include "ARMSubtarget.h"
25 #include "ARMTargetMachine.h"
26 #include "ARMTargetObjectFile.h"
27 #include "llvm/CallingConv.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Function.h"
30 #include "llvm/GlobalValue.h"
31 #include "llvm/Instruction.h"
32 #include "llvm/Instructions.h"
33 #include "llvm/Intrinsics.h"
34 #include "llvm/Type.h"
35 #include "llvm/CodeGen/CallingConvLower.h"
36 #include "llvm/CodeGen/MachineBasicBlock.h"
37 #include "llvm/CodeGen/MachineFrameInfo.h"
38 #include "llvm/CodeGen/MachineFunction.h"
39 #include "llvm/CodeGen/MachineInstrBuilder.h"
40 #include "llvm/CodeGen/MachineRegisterInfo.h"
41 #include "llvm/CodeGen/PseudoSourceValue.h"
42 #include "llvm/CodeGen/SelectionDAG.h"
43 #include "llvm/MC/MCSectionMachO.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/ADT/VectorExtras.h"
46 #include "llvm/ADT/Statistic.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Support/raw_ostream.h"
54 STATISTIC(NumTailCalls, "Number of tail calls");
56 // This option should go away when tail calls fully work.
58 EnableARMTailCalls("arm-tail-calls", cl::Hidden,
59 cl::desc("Generate tail calls (TEMPORARY OPTION)."),
62 // This option should go away when Machine LICM is smart enough to hoist a
65 EnableARMVDUPsplat("arm-vdup-splat", cl::Hidden,
66 cl::desc("Generate VDUP for integer constant splats (TEMPORARY OPTION)."),
70 EnableARMLongCalls("arm-long-calls", cl::Hidden,
71 cl::desc("Generate calls via indirect call instructions"),
75 ARMInterworking("arm-interworking", cl::Hidden,
76 cl::desc("Enable / disable ARM interworking (for debugging only)"),
79 void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
80 EVT PromotedBitwiseVT) {
81 if (VT != PromotedLdStVT) {
82 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
83 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
84 PromotedLdStVT.getSimpleVT());
86 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
87 AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
88 PromotedLdStVT.getSimpleVT());
91 EVT ElemTy = VT.getVectorElementType();
92 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
93 setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
94 if (ElemTy == MVT::i8 || ElemTy == MVT::i16)
95 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
96 if (ElemTy != MVT::i32) {
97 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
98 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand);
99 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand);
100 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand);
102 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
103 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
104 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
105 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Expand);
106 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
107 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
108 if (VT.isInteger()) {
109 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
110 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
111 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
112 setLoadExtAction(ISD::SEXTLOAD, VT.getSimpleVT(), Expand);
113 setLoadExtAction(ISD::ZEXTLOAD, VT.getSimpleVT(), Expand);
115 setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand);
117 // Promote all bit-wise operations.
118 if (VT.isInteger() && VT != PromotedBitwiseVT) {
119 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
120 AddPromotedToType (ISD::AND, VT.getSimpleVT(),
121 PromotedBitwiseVT.getSimpleVT());
122 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
123 AddPromotedToType (ISD::OR, VT.getSimpleVT(),
124 PromotedBitwiseVT.getSimpleVT());
125 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
126 AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
127 PromotedBitwiseVT.getSimpleVT());
130 // Neon does not support vector divide/remainder operations.
131 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
132 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
133 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand);
134 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
135 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
136 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
139 void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
140 addRegisterClass(VT, ARM::DPRRegisterClass);
141 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
144 void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
145 addRegisterClass(VT, ARM::QPRRegisterClass);
146 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
149 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
150 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
151 return new TargetLoweringObjectFileMachO();
153 return new ARMElfTargetObjectFile();
156 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
157 : TargetLowering(TM, createTLOF(TM)) {
158 Subtarget = &TM.getSubtarget<ARMSubtarget>();
159 RegInfo = TM.getRegisterInfo();
160 Itins = TM.getInstrItineraryData();
162 if (Subtarget->isTargetDarwin()) {
163 // Uses VFP for Thumb libfuncs if available.
164 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
165 // Single-precision floating-point arithmetic.
166 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
167 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
168 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
169 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
171 // Double-precision floating-point arithmetic.
172 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
173 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
174 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
175 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
177 // Single-precision comparisons.
178 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
179 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
180 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
181 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
182 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
183 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
184 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
185 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
187 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
188 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
189 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
190 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
191 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
192 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
193 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
194 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
196 // Double-precision comparisons.
197 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
198 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
199 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
200 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
201 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
202 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
203 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
204 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
206 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
207 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
208 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
209 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
210 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
211 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
212 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
213 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
215 // Floating-point to integer conversions.
216 // i64 conversions are done via library routines even when generating VFP
217 // instructions, so use the same ones.
218 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
219 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
220 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
221 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
223 // Conversions between floating types.
224 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
225 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
227 // Integer to floating-point conversions.
228 // i64 conversions are done via library routines even when generating VFP
229 // instructions, so use the same ones.
230 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
231 // e.g., __floatunsidf vs. __floatunssidfvfp.
232 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
233 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
234 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
235 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
239 // These libcalls are not available in 32-bit.
240 setLibcallName(RTLIB::SHL_I128, 0);
241 setLibcallName(RTLIB::SRL_I128, 0);
242 setLibcallName(RTLIB::SRA_I128, 0);
244 if (Subtarget->isAAPCS_ABI()) {
245 // Double-precision floating-point arithmetic helper functions
246 // RTABI chapter 4.1.2, Table 2
247 setLibcallName(RTLIB::ADD_F64, "__aeabi_dadd");
248 setLibcallName(RTLIB::DIV_F64, "__aeabi_ddiv");
249 setLibcallName(RTLIB::MUL_F64, "__aeabi_dmul");
250 setLibcallName(RTLIB::SUB_F64, "__aeabi_dsub");
251 setLibcallCallingConv(RTLIB::ADD_F64, CallingConv::ARM_AAPCS);
252 setLibcallCallingConv(RTLIB::DIV_F64, CallingConv::ARM_AAPCS);
253 setLibcallCallingConv(RTLIB::MUL_F64, CallingConv::ARM_AAPCS);
254 setLibcallCallingConv(RTLIB::SUB_F64, CallingConv::ARM_AAPCS);
256 // Double-precision floating-point comparison helper functions
257 // RTABI chapter 4.1.2, Table 3
258 setLibcallName(RTLIB::OEQ_F64, "__aeabi_dcmpeq");
259 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
260 setLibcallName(RTLIB::UNE_F64, "__aeabi_dcmpeq");
261 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETEQ);
262 setLibcallName(RTLIB::OLT_F64, "__aeabi_dcmplt");
263 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
264 setLibcallName(RTLIB::OLE_F64, "__aeabi_dcmple");
265 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
266 setLibcallName(RTLIB::OGE_F64, "__aeabi_dcmpge");
267 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
268 setLibcallName(RTLIB::OGT_F64, "__aeabi_dcmpgt");
269 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
270 setLibcallName(RTLIB::UO_F64, "__aeabi_dcmpun");
271 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
272 setLibcallName(RTLIB::O_F64, "__aeabi_dcmpun");
273 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
274 setLibcallCallingConv(RTLIB::OEQ_F64, CallingConv::ARM_AAPCS);
275 setLibcallCallingConv(RTLIB::UNE_F64, CallingConv::ARM_AAPCS);
276 setLibcallCallingConv(RTLIB::OLT_F64, CallingConv::ARM_AAPCS);
277 setLibcallCallingConv(RTLIB::OLE_F64, CallingConv::ARM_AAPCS);
278 setLibcallCallingConv(RTLIB::OGE_F64, CallingConv::ARM_AAPCS);
279 setLibcallCallingConv(RTLIB::OGT_F64, CallingConv::ARM_AAPCS);
280 setLibcallCallingConv(RTLIB::UO_F64, CallingConv::ARM_AAPCS);
281 setLibcallCallingConv(RTLIB::O_F64, CallingConv::ARM_AAPCS);
283 // Single-precision floating-point arithmetic helper functions
284 // RTABI chapter 4.1.2, Table 4
285 setLibcallName(RTLIB::ADD_F32, "__aeabi_fadd");
286 setLibcallName(RTLIB::DIV_F32, "__aeabi_fdiv");
287 setLibcallName(RTLIB::MUL_F32, "__aeabi_fmul");
288 setLibcallName(RTLIB::SUB_F32, "__aeabi_fsub");
289 setLibcallCallingConv(RTLIB::ADD_F32, CallingConv::ARM_AAPCS);
290 setLibcallCallingConv(RTLIB::DIV_F32, CallingConv::ARM_AAPCS);
291 setLibcallCallingConv(RTLIB::MUL_F32, CallingConv::ARM_AAPCS);
292 setLibcallCallingConv(RTLIB::SUB_F32, CallingConv::ARM_AAPCS);
294 // Single-precision floating-point comparison helper functions
295 // RTABI chapter 4.1.2, Table 5
296 setLibcallName(RTLIB::OEQ_F32, "__aeabi_fcmpeq");
297 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
298 setLibcallName(RTLIB::UNE_F32, "__aeabi_fcmpeq");
299 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETEQ);
300 setLibcallName(RTLIB::OLT_F32, "__aeabi_fcmplt");
301 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
302 setLibcallName(RTLIB::OLE_F32, "__aeabi_fcmple");
303 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
304 setLibcallName(RTLIB::OGE_F32, "__aeabi_fcmpge");
305 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
306 setLibcallName(RTLIB::OGT_F32, "__aeabi_fcmpgt");
307 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
308 setLibcallName(RTLIB::UO_F32, "__aeabi_fcmpun");
309 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
310 setLibcallName(RTLIB::O_F32, "__aeabi_fcmpun");
311 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
312 setLibcallCallingConv(RTLIB::OEQ_F32, CallingConv::ARM_AAPCS);
313 setLibcallCallingConv(RTLIB::UNE_F32, CallingConv::ARM_AAPCS);
314 setLibcallCallingConv(RTLIB::OLT_F32, CallingConv::ARM_AAPCS);
315 setLibcallCallingConv(RTLIB::OLE_F32, CallingConv::ARM_AAPCS);
316 setLibcallCallingConv(RTLIB::OGE_F32, CallingConv::ARM_AAPCS);
317 setLibcallCallingConv(RTLIB::OGT_F32, CallingConv::ARM_AAPCS);
318 setLibcallCallingConv(RTLIB::UO_F32, CallingConv::ARM_AAPCS);
319 setLibcallCallingConv(RTLIB::O_F32, CallingConv::ARM_AAPCS);
321 // Floating-point to integer conversions.
322 // RTABI chapter 4.1.2, Table 6
323 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz");
324 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz");
325 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz");
326 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz");
327 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz");
328 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz");
329 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz");
330 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz");
331 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I32, CallingConv::ARM_AAPCS);
332 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I32, CallingConv::ARM_AAPCS);
333 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I64, CallingConv::ARM_AAPCS);
334 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::ARM_AAPCS);
335 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I32, CallingConv::ARM_AAPCS);
336 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I32, CallingConv::ARM_AAPCS);
337 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I64, CallingConv::ARM_AAPCS);
338 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::ARM_AAPCS);
340 // Conversions between floating types.
341 // RTABI chapter 4.1.2, Table 7
342 setLibcallName(RTLIB::FPROUND_F64_F32, "__aeabi_d2f");
343 setLibcallName(RTLIB::FPEXT_F32_F64, "__aeabi_f2d");
344 setLibcallCallingConv(RTLIB::FPROUND_F64_F32, CallingConv::ARM_AAPCS);
345 setLibcallCallingConv(RTLIB::FPEXT_F32_F64, CallingConv::ARM_AAPCS);
347 // Integer to floating-point conversions.
348 // RTABI chapter 4.1.2, Table 8
349 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d");
350 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d");
351 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d");
352 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d");
353 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f");
354 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f");
355 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f");
356 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f");
357 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
358 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
359 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
360 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
361 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
362 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
363 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
364 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
366 // Long long helper functions
367 // RTABI chapter 4.2, Table 9
368 setLibcallName(RTLIB::MUL_I64, "__aeabi_lmul");
369 setLibcallName(RTLIB::SDIV_I64, "__aeabi_ldivmod");
370 setLibcallName(RTLIB::UDIV_I64, "__aeabi_uldivmod");
371 setLibcallName(RTLIB::SHL_I64, "__aeabi_llsl");
372 setLibcallName(RTLIB::SRL_I64, "__aeabi_llsr");
373 setLibcallName(RTLIB::SRA_I64, "__aeabi_lasr");
374 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::ARM_AAPCS);
375 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::ARM_AAPCS);
376 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::ARM_AAPCS);
377 setLibcallCallingConv(RTLIB::SHL_I64, CallingConv::ARM_AAPCS);
378 setLibcallCallingConv(RTLIB::SRL_I64, CallingConv::ARM_AAPCS);
379 setLibcallCallingConv(RTLIB::SRA_I64, CallingConv::ARM_AAPCS);
381 // Integer division functions
382 // RTABI chapter 4.3.1
383 setLibcallName(RTLIB::SDIV_I8, "__aeabi_idiv");
384 setLibcallName(RTLIB::SDIV_I16, "__aeabi_idiv");
385 setLibcallName(RTLIB::SDIV_I32, "__aeabi_idiv");
386 setLibcallName(RTLIB::UDIV_I8, "__aeabi_uidiv");
387 setLibcallName(RTLIB::UDIV_I16, "__aeabi_uidiv");
388 setLibcallName(RTLIB::UDIV_I32, "__aeabi_uidiv");
389 setLibcallCallingConv(RTLIB::SDIV_I8, CallingConv::ARM_AAPCS);
390 setLibcallCallingConv(RTLIB::SDIV_I16, CallingConv::ARM_AAPCS);
391 setLibcallCallingConv(RTLIB::SDIV_I32, CallingConv::ARM_AAPCS);
392 setLibcallCallingConv(RTLIB::UDIV_I8, CallingConv::ARM_AAPCS);
393 setLibcallCallingConv(RTLIB::UDIV_I16, CallingConv::ARM_AAPCS);
394 setLibcallCallingConv(RTLIB::UDIV_I32, CallingConv::ARM_AAPCS);
397 if (Subtarget->isThumb1Only())
398 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
400 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
401 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
402 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
403 if (!Subtarget->isFPOnlySP())
404 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
406 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
409 if (Subtarget->hasNEON()) {
410 addDRTypeForNEON(MVT::v2f32);
411 addDRTypeForNEON(MVT::v8i8);
412 addDRTypeForNEON(MVT::v4i16);
413 addDRTypeForNEON(MVT::v2i32);
414 addDRTypeForNEON(MVT::v1i64);
416 addQRTypeForNEON(MVT::v4f32);
417 addQRTypeForNEON(MVT::v2f64);
418 addQRTypeForNEON(MVT::v16i8);
419 addQRTypeForNEON(MVT::v8i16);
420 addQRTypeForNEON(MVT::v4i32);
421 addQRTypeForNEON(MVT::v2i64);
423 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
424 // neither Neon nor VFP support any arithmetic operations on it.
425 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
426 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
427 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
428 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
429 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
430 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
431 setOperationAction(ISD::VSETCC, MVT::v2f64, Expand);
432 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
433 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
434 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
435 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
436 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
437 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
438 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
439 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
440 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
441 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
442 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
443 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
444 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
445 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
446 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
447 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
448 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
450 setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand);
452 // Neon does not support some operations on v1i64 and v2i64 types.
453 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
454 // Custom handling for some quad-vector types to detect VMULL.
455 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
456 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
457 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
458 setOperationAction(ISD::VSETCC, MVT::v1i64, Expand);
459 setOperationAction(ISD::VSETCC, MVT::v2i64, Expand);
461 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
462 setTargetDAGCombine(ISD::SHL);
463 setTargetDAGCombine(ISD::SRL);
464 setTargetDAGCombine(ISD::SRA);
465 setTargetDAGCombine(ISD::SIGN_EXTEND);
466 setTargetDAGCombine(ISD::ZERO_EXTEND);
467 setTargetDAGCombine(ISD::ANY_EXTEND);
468 setTargetDAGCombine(ISD::SELECT_CC);
469 setTargetDAGCombine(ISD::BUILD_VECTOR);
472 computeRegisterProperties();
474 // ARM does not have f32 extending load.
475 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
477 // ARM does not have i1 sign extending load.
478 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
480 // ARM supports all 4 flavors of integer indexed load / store.
481 if (!Subtarget->isThumb1Only()) {
482 for (unsigned im = (unsigned)ISD::PRE_INC;
483 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
484 setIndexedLoadAction(im, MVT::i1, Legal);
485 setIndexedLoadAction(im, MVT::i8, Legal);
486 setIndexedLoadAction(im, MVT::i16, Legal);
487 setIndexedLoadAction(im, MVT::i32, Legal);
488 setIndexedStoreAction(im, MVT::i1, Legal);
489 setIndexedStoreAction(im, MVT::i8, Legal);
490 setIndexedStoreAction(im, MVT::i16, Legal);
491 setIndexedStoreAction(im, MVT::i32, Legal);
495 // i64 operation support.
496 if (Subtarget->isThumb1Only()) {
497 setOperationAction(ISD::MUL, MVT::i64, Expand);
498 setOperationAction(ISD::MULHU, MVT::i32, Expand);
499 setOperationAction(ISD::MULHS, MVT::i32, Expand);
500 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
501 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
503 setOperationAction(ISD::MUL, MVT::i64, Expand);
504 setOperationAction(ISD::MULHU, MVT::i32, Expand);
505 if (!Subtarget->hasV6Ops())
506 setOperationAction(ISD::MULHS, MVT::i32, Expand);
508 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
509 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
510 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
511 setOperationAction(ISD::SRL, MVT::i64, Custom);
512 setOperationAction(ISD::SRA, MVT::i64, Custom);
514 // ARM does not have ROTL.
515 setOperationAction(ISD::ROTL, MVT::i32, Expand);
516 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
517 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
518 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
519 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
521 // Only ARMv6 has BSWAP.
522 if (!Subtarget->hasV6Ops())
523 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
525 // These are expanded into libcalls.
526 if (!Subtarget->hasDivide()) {
527 // v7M has a hardware divider
528 setOperationAction(ISD::SDIV, MVT::i32, Expand);
529 setOperationAction(ISD::UDIV, MVT::i32, Expand);
531 setOperationAction(ISD::SREM, MVT::i32, Expand);
532 setOperationAction(ISD::UREM, MVT::i32, Expand);
533 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
534 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
536 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
537 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
538 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
539 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
540 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
542 setOperationAction(ISD::TRAP, MVT::Other, Legal);
544 // Use the default implementation.
545 setOperationAction(ISD::VASTART, MVT::Other, Custom);
546 setOperationAction(ISD::VAARG, MVT::Other, Expand);
547 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
548 setOperationAction(ISD::VAEND, MVT::Other, Expand);
549 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
550 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
551 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
552 // FIXME: Shouldn't need this, since no register is used, but the legalizer
553 // doesn't yet know how to not do that for SjLj.
554 setExceptionSelectorRegister(ARM::R0);
555 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
556 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
557 // the default expansion.
558 if (Subtarget->hasDataBarrier() ||
559 (Subtarget->hasV6Ops() && !Subtarget->isThumb1Only())) {
560 // membarrier needs custom lowering; the rest are legal and handled
562 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
564 // Set them all for expansion, which will force libcalls.
565 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
566 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Expand);
567 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Expand);
568 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
569 setOperationAction(ISD::ATOMIC_SWAP, MVT::i8, Expand);
570 setOperationAction(ISD::ATOMIC_SWAP, MVT::i16, Expand);
571 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
572 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i8, Expand);
573 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i16, Expand);
574 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
575 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Expand);
576 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Expand);
577 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
578 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i8, Expand);
579 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i16, Expand);
580 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
581 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i8, Expand);
582 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i16, Expand);
583 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
584 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i8, Expand);
585 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i16, Expand);
586 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
587 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i8, Expand);
588 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i16, Expand);
589 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
590 // Since the libcalls include locking, fold in the fences
591 setShouldFoldAtomicFences(true);
593 // 64-bit versions are always libcalls (for now)
594 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Expand);
595 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Expand);
596 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Expand);
597 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Expand);
598 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Expand);
599 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Expand);
600 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Expand);
601 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Expand);
603 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
604 if (!Subtarget->hasV6Ops()) {
605 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
606 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
608 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
610 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
611 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
612 // iff target supports vfp2.
613 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
614 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
617 // We want to custom lower some of our intrinsics.
618 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
619 if (Subtarget->isTargetDarwin()) {
620 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
621 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
624 setOperationAction(ISD::SETCC, MVT::i32, Expand);
625 setOperationAction(ISD::SETCC, MVT::f32, Expand);
626 setOperationAction(ISD::SETCC, MVT::f64, Expand);
627 setOperationAction(ISD::SELECT, MVT::i32, Custom);
628 setOperationAction(ISD::SELECT, MVT::f32, Custom);
629 setOperationAction(ISD::SELECT, MVT::f64, Custom);
630 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
631 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
632 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
634 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
635 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
636 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
637 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
638 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
640 // We don't support sin/cos/fmod/copysign/pow
641 setOperationAction(ISD::FSIN, MVT::f64, Expand);
642 setOperationAction(ISD::FSIN, MVT::f32, Expand);
643 setOperationAction(ISD::FCOS, MVT::f32, Expand);
644 setOperationAction(ISD::FCOS, MVT::f64, Expand);
645 setOperationAction(ISD::FREM, MVT::f64, Expand);
646 setOperationAction(ISD::FREM, MVT::f32, Expand);
647 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
648 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
649 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
651 setOperationAction(ISD::FPOW, MVT::f64, Expand);
652 setOperationAction(ISD::FPOW, MVT::f32, Expand);
654 // Various VFP goodness
655 if (!UseSoftFloat && !Subtarget->isThumb1Only()) {
656 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
657 if (Subtarget->hasVFP2()) {
658 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
659 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
660 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
661 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
663 // Special handling for half-precision FP.
664 if (!Subtarget->hasFP16()) {
665 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
666 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand);
670 // We have target-specific dag combine patterns for the following nodes:
671 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
672 setTargetDAGCombine(ISD::ADD);
673 setTargetDAGCombine(ISD::SUB);
674 setTargetDAGCombine(ISD::MUL);
676 if (Subtarget->hasV6T2Ops())
677 setTargetDAGCombine(ISD::OR);
679 setStackPointerRegisterToSaveRestore(ARM::SP);
681 if (UseSoftFloat || Subtarget->isThumb1Only() || !Subtarget->hasVFP2())
682 setSchedulingPreference(Sched::RegPressure);
684 setSchedulingPreference(Sched::Hybrid);
686 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
688 // On ARM arguments smaller than 4 bytes are extended, so all arguments
689 // are at least 4 bytes aligned.
690 setMinStackArgumentAlignment(4);
692 benefitFromCodePlacementOpt = true;
695 std::pair<const TargetRegisterClass*, uint8_t>
696 ARMTargetLowering::findRepresentativeClass(EVT VT) const{
697 const TargetRegisterClass *RRC = 0;
699 switch (VT.getSimpleVT().SimpleTy) {
701 return TargetLowering::findRepresentativeClass(VT);
702 // Use DPR as representative register class for all floating point
703 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
704 // the cost is 1 for both f32 and f64.
705 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
706 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
707 RRC = ARM::DPRRegisterClass;
709 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
710 case MVT::v4f32: case MVT::v2f64:
711 RRC = ARM::DPRRegisterClass;
715 RRC = ARM::DPRRegisterClass;
719 RRC = ARM::DPRRegisterClass;
723 return std::make_pair(RRC, Cost);
726 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
729 case ARMISD::Wrapper: return "ARMISD::Wrapper";
730 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
731 case ARMISD::CALL: return "ARMISD::CALL";
732 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
733 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
734 case ARMISD::tCALL: return "ARMISD::tCALL";
735 case ARMISD::BRCOND: return "ARMISD::BRCOND";
736 case ARMISD::BR_JT: return "ARMISD::BR_JT";
737 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
738 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
739 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
740 case ARMISD::AND: return "ARMISD::AND";
741 case ARMISD::CMP: return "ARMISD::CMP";
742 case ARMISD::CMPZ: return "ARMISD::CMPZ";
743 case ARMISD::CMPFP: return "ARMISD::CMPFP";
744 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
745 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
746 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
747 case ARMISD::CMOV: return "ARMISD::CMOV";
748 case ARMISD::CNEG: return "ARMISD::CNEG";
750 case ARMISD::RBIT: return "ARMISD::RBIT";
752 case ARMISD::FTOSI: return "ARMISD::FTOSI";
753 case ARMISD::FTOUI: return "ARMISD::FTOUI";
754 case ARMISD::SITOF: return "ARMISD::SITOF";
755 case ARMISD::UITOF: return "ARMISD::UITOF";
757 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
758 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
759 case ARMISD::RRX: return "ARMISD::RRX";
761 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
762 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
764 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
765 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
767 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
769 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
771 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
773 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER";
774 case ARMISD::SYNCBARRIER: return "ARMISD::SYNCBARRIER";
776 case ARMISD::VCEQ: return "ARMISD::VCEQ";
777 case ARMISD::VCGE: return "ARMISD::VCGE";
778 case ARMISD::VCGEU: return "ARMISD::VCGEU";
779 case ARMISD::VCGT: return "ARMISD::VCGT";
780 case ARMISD::VCGTU: return "ARMISD::VCGTU";
781 case ARMISD::VTST: return "ARMISD::VTST";
783 case ARMISD::VSHL: return "ARMISD::VSHL";
784 case ARMISD::VSHRs: return "ARMISD::VSHRs";
785 case ARMISD::VSHRu: return "ARMISD::VSHRu";
786 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
787 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
788 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
789 case ARMISD::VSHRN: return "ARMISD::VSHRN";
790 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
791 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
792 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
793 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
794 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
795 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
796 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
797 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
798 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
799 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
800 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
801 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
802 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
803 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
804 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
805 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
806 case ARMISD::VDUP: return "ARMISD::VDUP";
807 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
808 case ARMISD::VEXT: return "ARMISD::VEXT";
809 case ARMISD::VREV64: return "ARMISD::VREV64";
810 case ARMISD::VREV32: return "ARMISD::VREV32";
811 case ARMISD::VREV16: return "ARMISD::VREV16";
812 case ARMISD::VZIP: return "ARMISD::VZIP";
813 case ARMISD::VUZP: return "ARMISD::VUZP";
814 case ARMISD::VTRN: return "ARMISD::VTRN";
815 case ARMISD::VMULLs: return "ARMISD::VMULLs";
816 case ARMISD::VMULLu: return "ARMISD::VMULLu";
817 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
818 case ARMISD::FMAX: return "ARMISD::FMAX";
819 case ARMISD::FMIN: return "ARMISD::FMIN";
820 case ARMISD::BFI: return "ARMISD::BFI";
824 /// getRegClassFor - Return the register class that should be used for the
825 /// specified value type.
826 TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const {
827 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
828 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
829 // load / store 4 to 8 consecutive D registers.
830 if (Subtarget->hasNEON()) {
831 if (VT == MVT::v4i64)
832 return ARM::QQPRRegisterClass;
833 else if (VT == MVT::v8i64)
834 return ARM::QQQQPRRegisterClass;
836 return TargetLowering::getRegClassFor(VT);
839 // Create a fast isel object.
841 ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
842 return ARM::createFastISel(funcInfo);
845 /// getFunctionAlignment - Return the Log2 alignment of this function.
846 unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
847 return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 1 : 2;
850 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
851 /// be used for loads / stores from the global.
852 unsigned ARMTargetLowering::getMaximalGlobalOffset() const {
853 return (Subtarget->isThumb1Only() ? 127 : 4095);
856 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
857 unsigned NumVals = N->getNumValues();
859 return Sched::RegPressure;
861 for (unsigned i = 0; i != NumVals; ++i) {
862 EVT VT = N->getValueType(i);
863 if (VT.isFloatingPoint() || VT.isVector())
864 return Sched::Latency;
867 if (!N->isMachineOpcode())
868 return Sched::RegPressure;
870 // Load are scheduled for latency even if there instruction itinerary
872 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
873 const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
875 return Sched::Latency;
877 if (!Itins->isEmpty() && Itins->getStageLatency(TID.getSchedClass()) > 2)
878 return Sched::Latency;
879 return Sched::RegPressure;
883 ARMTargetLowering::getRegPressureLimit(const TargetRegisterClass *RC,
884 MachineFunction &MF) const {
885 switch (RC->getID()) {
888 case ARM::tGPRRegClassID:
889 return RegInfo->hasFP(MF) ? 4 : 5;
890 case ARM::GPRRegClassID: {
891 unsigned FP = RegInfo->hasFP(MF) ? 1 : 0;
892 return 10 - FP - (Subtarget->isR9Reserved() ? 1 : 0);
894 case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
895 case ARM::DPRRegClassID:
900 //===----------------------------------------------------------------------===//
902 //===----------------------------------------------------------------------===//
904 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
905 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
907 default: llvm_unreachable("Unknown condition code!");
908 case ISD::SETNE: return ARMCC::NE;
909 case ISD::SETEQ: return ARMCC::EQ;
910 case ISD::SETGT: return ARMCC::GT;
911 case ISD::SETGE: return ARMCC::GE;
912 case ISD::SETLT: return ARMCC::LT;
913 case ISD::SETLE: return ARMCC::LE;
914 case ISD::SETUGT: return ARMCC::HI;
915 case ISD::SETUGE: return ARMCC::HS;
916 case ISD::SETULT: return ARMCC::LO;
917 case ISD::SETULE: return ARMCC::LS;
921 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
922 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
923 ARMCC::CondCodes &CondCode2) {
924 CondCode2 = ARMCC::AL;
926 default: llvm_unreachable("Unknown FP condition!");
928 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
930 case ISD::SETOGT: CondCode = ARMCC::GT; break;
932 case ISD::SETOGE: CondCode = ARMCC::GE; break;
933 case ISD::SETOLT: CondCode = ARMCC::MI; break;
934 case ISD::SETOLE: CondCode = ARMCC::LS; break;
935 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
936 case ISD::SETO: CondCode = ARMCC::VC; break;
937 case ISD::SETUO: CondCode = ARMCC::VS; break;
938 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
939 case ISD::SETUGT: CondCode = ARMCC::HI; break;
940 case ISD::SETUGE: CondCode = ARMCC::PL; break;
942 case ISD::SETULT: CondCode = ARMCC::LT; break;
944 case ISD::SETULE: CondCode = ARMCC::LE; break;
946 case ISD::SETUNE: CondCode = ARMCC::NE; break;
950 //===----------------------------------------------------------------------===//
951 // Calling Convention Implementation
952 //===----------------------------------------------------------------------===//
954 #include "ARMGenCallingConv.inc"
956 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
957 /// given CallingConvention value.
958 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
960 bool isVarArg) const {
963 llvm_unreachable("Unsupported calling convention");
965 case CallingConv::Fast:
966 // Use target triple & subtarget features to do actual dispatch.
967 if (Subtarget->isAAPCS_ABI()) {
968 if (Subtarget->hasVFP2() &&
969 FloatABIType == FloatABI::Hard && !isVarArg)
970 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
972 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
974 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
975 case CallingConv::ARM_AAPCS_VFP:
976 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
977 case CallingConv::ARM_AAPCS:
978 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
979 case CallingConv::ARM_APCS:
980 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
984 /// LowerCallResult - Lower the result values of a call into the
985 /// appropriate copies out of appropriate physical registers.
987 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
988 CallingConv::ID CallConv, bool isVarArg,
989 const SmallVectorImpl<ISD::InputArg> &Ins,
990 DebugLoc dl, SelectionDAG &DAG,
991 SmallVectorImpl<SDValue> &InVals) const {
993 // Assign locations to each value returned by this call.
994 SmallVector<CCValAssign, 16> RVLocs;
995 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
996 RVLocs, *DAG.getContext());
997 CCInfo.AnalyzeCallResult(Ins,
998 CCAssignFnForNode(CallConv, /* Return*/ true,
1001 // Copy all of the result registers out of their specified physreg.
1002 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1003 CCValAssign VA = RVLocs[i];
1006 if (VA.needsCustom()) {
1007 // Handle f64 or half of a v2f64.
1008 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1010 Chain = Lo.getValue(1);
1011 InFlag = Lo.getValue(2);
1012 VA = RVLocs[++i]; // skip ahead to next loc
1013 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1015 Chain = Hi.getValue(1);
1016 InFlag = Hi.getValue(2);
1017 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1019 if (VA.getLocVT() == MVT::v2f64) {
1020 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1021 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1022 DAG.getConstant(0, MVT::i32));
1024 VA = RVLocs[++i]; // skip ahead to next loc
1025 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1026 Chain = Lo.getValue(1);
1027 InFlag = Lo.getValue(2);
1028 VA = RVLocs[++i]; // skip ahead to next loc
1029 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1030 Chain = Hi.getValue(1);
1031 InFlag = Hi.getValue(2);
1032 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1033 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1034 DAG.getConstant(1, MVT::i32));
1037 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1039 Chain = Val.getValue(1);
1040 InFlag = Val.getValue(2);
1043 switch (VA.getLocInfo()) {
1044 default: llvm_unreachable("Unknown loc info!");
1045 case CCValAssign::Full: break;
1046 case CCValAssign::BCvt:
1047 Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val);
1051 InVals.push_back(Val);
1057 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1058 /// by "Src" to address "Dst" of size "Size". Alignment information is
1059 /// specified by the specific parameter attribute. The copy will be passed as
1060 /// a byval function parameter.
1061 /// Sometimes what we are copying is the end of a larger object, the part that
1062 /// does not fit in registers.
1064 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1065 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1067 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1068 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1069 /*isVolatile=*/false, /*AlwaysInline=*/false,
1070 MachinePointerInfo(0), MachinePointerInfo(0));
1073 /// LowerMemOpCallTo - Store the argument to the stack.
1075 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
1076 SDValue StackPtr, SDValue Arg,
1077 DebugLoc dl, SelectionDAG &DAG,
1078 const CCValAssign &VA,
1079 ISD::ArgFlagsTy Flags) const {
1080 unsigned LocMemOffset = VA.getLocMemOffset();
1081 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1082 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1083 if (Flags.isByVal())
1084 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1086 return DAG.getStore(Chain, dl, Arg, PtrOff,
1087 MachinePointerInfo::getStack(LocMemOffset),
1091 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
1092 SDValue Chain, SDValue &Arg,
1093 RegsToPassVector &RegsToPass,
1094 CCValAssign &VA, CCValAssign &NextVA,
1096 SmallVector<SDValue, 8> &MemOpChains,
1097 ISD::ArgFlagsTy Flags) const {
1099 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1100 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1101 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
1103 if (NextVA.isRegLoc())
1104 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
1106 assert(NextVA.isMemLoc());
1107 if (StackPtr.getNode() == 0)
1108 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1110 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
1116 /// LowerCall - Lowering a call into a callseq_start <-
1117 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1120 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1121 CallingConv::ID CallConv, bool isVarArg,
1123 const SmallVectorImpl<ISD::OutputArg> &Outs,
1124 const SmallVectorImpl<SDValue> &OutVals,
1125 const SmallVectorImpl<ISD::InputArg> &Ins,
1126 DebugLoc dl, SelectionDAG &DAG,
1127 SmallVectorImpl<SDValue> &InVals) const {
1128 MachineFunction &MF = DAG.getMachineFunction();
1129 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1130 bool IsSibCall = false;
1131 // Temporarily disable tail calls so things don't break.
1132 if (!EnableARMTailCalls)
1135 // Check if it's really possible to do a tail call.
1136 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1137 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1138 Outs, OutVals, Ins, DAG);
1139 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1140 // detected sibcalls.
1147 // Analyze operands of the call, assigning locations to each operand.
1148 SmallVector<CCValAssign, 16> ArgLocs;
1149 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1151 CCInfo.AnalyzeCallOperands(Outs,
1152 CCAssignFnForNode(CallConv, /* Return*/ false,
1155 // Get a count of how many bytes are to be pushed on the stack.
1156 unsigned NumBytes = CCInfo.getNextStackOffset();
1158 // For tail calls, memory operands are available in our caller's stack.
1162 // Adjust the stack pointer for the new arguments...
1163 // These operations are automatically eliminated by the prolog/epilog pass
1165 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1167 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1169 RegsToPassVector RegsToPass;
1170 SmallVector<SDValue, 8> MemOpChains;
1172 // Walk the register/memloc assignments, inserting copies/loads. In the case
1173 // of tail call optimization, arguments are handled later.
1174 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1176 ++i, ++realArgIdx) {
1177 CCValAssign &VA = ArgLocs[i];
1178 SDValue Arg = OutVals[realArgIdx];
1179 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1181 // Promote the value if needed.
1182 switch (VA.getLocInfo()) {
1183 default: llvm_unreachable("Unknown loc info!");
1184 case CCValAssign::Full: break;
1185 case CCValAssign::SExt:
1186 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1188 case CCValAssign::ZExt:
1189 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1191 case CCValAssign::AExt:
1192 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1194 case CCValAssign::BCvt:
1195 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1199 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1200 if (VA.needsCustom()) {
1201 if (VA.getLocVT() == MVT::v2f64) {
1202 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1203 DAG.getConstant(0, MVT::i32));
1204 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1205 DAG.getConstant(1, MVT::i32));
1207 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1208 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1210 VA = ArgLocs[++i]; // skip ahead to next loc
1211 if (VA.isRegLoc()) {
1212 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1213 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1215 assert(VA.isMemLoc());
1217 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1218 dl, DAG, VA, Flags));
1221 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1222 StackPtr, MemOpChains, Flags);
1224 } else if (VA.isRegLoc()) {
1225 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1226 } else if (!IsSibCall) {
1227 assert(VA.isMemLoc());
1229 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1230 dl, DAG, VA, Flags));
1234 if (!MemOpChains.empty())
1235 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1236 &MemOpChains[0], MemOpChains.size());
1238 // Build a sequence of copy-to-reg nodes chained together with token chain
1239 // and flag operands which copy the outgoing args into the appropriate regs.
1241 // Tail call byval lowering might overwrite argument registers so in case of
1242 // tail call optimization the copies to registers are lowered later.
1244 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1245 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1246 RegsToPass[i].second, InFlag);
1247 InFlag = Chain.getValue(1);
1250 // For tail calls lower the arguments to the 'real' stack slot.
1252 // Force all the incoming stack arguments to be loaded from the stack
1253 // before any new outgoing arguments are stored to the stack, because the
1254 // outgoing stack slots may alias the incoming argument stack slots, and
1255 // the alias isn't otherwise explicit. This is slightly more conservative
1256 // than necessary, because it means that each store effectively depends
1257 // on every argument instead of just those arguments it would clobber.
1259 // Do not flag preceeding copytoreg stuff together with the following stuff.
1261 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1262 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1263 RegsToPass[i].second, InFlag);
1264 InFlag = Chain.getValue(1);
1269 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1270 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1271 // node so that legalize doesn't hack it.
1272 bool isDirect = false;
1273 bool isARMFunc = false;
1274 bool isLocalARMFunc = false;
1275 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1277 if (EnableARMLongCalls) {
1278 assert (getTargetMachine().getRelocationModel() == Reloc::Static
1279 && "long-calls with non-static relocation model!");
1280 // Handle a global address or an external symbol. If it's not one of
1281 // those, the target's already in a register, so we don't need to do
1283 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1284 const GlobalValue *GV = G->getGlobal();
1285 // Create a constant pool entry for the callee address
1286 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1287 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1290 // Get the address of the callee into a register
1291 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1292 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1293 Callee = DAG.getLoad(getPointerTy(), dl,
1294 DAG.getEntryNode(), CPAddr,
1295 MachinePointerInfo::getConstantPool(),
1297 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1298 const char *Sym = S->getSymbol();
1300 // Create a constant pool entry for the callee address
1301 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1302 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1303 Sym, ARMPCLabelIndex, 0);
1304 // Get the address of the callee into a register
1305 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1306 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1307 Callee = DAG.getLoad(getPointerTy(), dl,
1308 DAG.getEntryNode(), CPAddr,
1309 MachinePointerInfo::getConstantPool(),
1312 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1313 const GlobalValue *GV = G->getGlobal();
1315 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1316 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
1317 getTargetMachine().getRelocationModel() != Reloc::Static;
1318 isARMFunc = !Subtarget->isThumb() || isStub;
1319 // ARM call to a local ARM function is predicable.
1320 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
1321 // tBX takes a register source operand.
1322 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1323 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1324 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1327 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1328 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1329 Callee = DAG.getLoad(getPointerTy(), dl,
1330 DAG.getEntryNode(), CPAddr,
1331 MachinePointerInfo::getConstantPool(),
1333 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1334 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1335 getPointerTy(), Callee, PICLabel);
1337 // On ELF targets for PIC code, direct calls should go through the PLT
1338 unsigned OpFlags = 0;
1339 if (Subtarget->isTargetELF() &&
1340 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1341 OpFlags = ARMII::MO_PLT;
1342 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
1344 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1346 bool isStub = Subtarget->isTargetDarwin() &&
1347 getTargetMachine().getRelocationModel() != Reloc::Static;
1348 isARMFunc = !Subtarget->isThumb() || isStub;
1349 // tBX takes a register source operand.
1350 const char *Sym = S->getSymbol();
1351 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1352 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1353 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1354 Sym, ARMPCLabelIndex, 4);
1355 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1356 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1357 Callee = DAG.getLoad(getPointerTy(), dl,
1358 DAG.getEntryNode(), CPAddr,
1359 MachinePointerInfo::getConstantPool(),
1361 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1362 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1363 getPointerTy(), Callee, PICLabel);
1365 unsigned OpFlags = 0;
1366 // On ELF targets for PIC code, direct calls should go through the PLT
1367 if (Subtarget->isTargetELF() &&
1368 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1369 OpFlags = ARMII::MO_PLT;
1370 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags);
1374 // FIXME: handle tail calls differently.
1376 if (Subtarget->isThumb()) {
1377 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1378 CallOpc = ARMISD::CALL_NOLINK;
1380 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1382 CallOpc = (isDirect || Subtarget->hasV5TOps())
1383 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
1384 : ARMISD::CALL_NOLINK;
1387 std::vector<SDValue> Ops;
1388 Ops.push_back(Chain);
1389 Ops.push_back(Callee);
1391 // Add argument registers to the end of the list so that they are known live
1393 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1394 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1395 RegsToPass[i].second.getValueType()));
1397 if (InFlag.getNode())
1398 Ops.push_back(InFlag);
1400 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1402 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
1404 // Returns a chain and a flag for retval copy to use.
1405 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
1406 InFlag = Chain.getValue(1);
1408 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1409 DAG.getIntPtrConstant(0, true), InFlag);
1411 InFlag = Chain.getValue(1);
1413 // Handle result values, copying them out of physregs into vregs that we
1415 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1419 /// MatchingStackOffset - Return true if the given stack call argument is
1420 /// already available in the same position (relatively) of the caller's
1421 /// incoming argument stack.
1423 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1424 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1425 const ARMInstrInfo *TII) {
1426 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
1428 if (Arg.getOpcode() == ISD::CopyFromReg) {
1429 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
1430 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR))
1432 MachineInstr *Def = MRI->getVRegDef(VR);
1435 if (!Flags.isByVal()) {
1436 if (!TII->isLoadFromStackSlot(Def, FI))
1441 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
1442 if (Flags.isByVal())
1443 // ByVal argument is passed in as a pointer but it's now being
1444 // dereferenced. e.g.
1445 // define @foo(%struct.X* %A) {
1446 // tail call @bar(%struct.X* byval %A)
1449 SDValue Ptr = Ld->getBasePtr();
1450 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
1453 FI = FINode->getIndex();
1457 assert(FI != INT_MAX);
1458 if (!MFI->isFixedObjectIndex(FI))
1460 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
1463 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1464 /// for tail call optimization. Targets which want to do tail call
1465 /// optimization should implement this function.
1467 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1468 CallingConv::ID CalleeCC,
1470 bool isCalleeStructRet,
1471 bool isCallerStructRet,
1472 const SmallVectorImpl<ISD::OutputArg> &Outs,
1473 const SmallVectorImpl<SDValue> &OutVals,
1474 const SmallVectorImpl<ISD::InputArg> &Ins,
1475 SelectionDAG& DAG) const {
1476 const Function *CallerF = DAG.getMachineFunction().getFunction();
1477 CallingConv::ID CallerCC = CallerF->getCallingConv();
1478 bool CCMatch = CallerCC == CalleeCC;
1480 // Look for obvious safe cases to perform tail call optimization that do not
1481 // require ABI changes. This is what gcc calls sibcall.
1483 // Do not sibcall optimize vararg calls unless the call site is not passing
1485 if (isVarArg && !Outs.empty())
1488 // Also avoid sibcall optimization if either caller or callee uses struct
1489 // return semantics.
1490 if (isCalleeStructRet || isCallerStructRet)
1493 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
1494 // emitEpilogue is not ready for them.
1495 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
1496 // LR. This means if we need to reload LR, it takes an extra instructions,
1497 // which outweighs the value of the tail call; but here we don't know yet
1498 // whether LR is going to be used. Probably the right approach is to
1499 // generate the tail call here and turn it back into CALL/RET in
1500 // emitEpilogue if LR is used.
1501 if (Subtarget->isThumb1Only())
1504 // For the moment, we can only do this to functions defined in this
1505 // compilation, or to indirect calls. A Thumb B to an ARM function,
1506 // or vice versa, is not easily fixed up in the linker unlike BL.
1507 // (We could do this by loading the address of the callee into a register;
1508 // that is an extra instruction over the direct call and burns a register
1509 // as well, so is not likely to be a win.)
1511 // It might be safe to remove this restriction on non-Darwin.
1513 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
1514 // but we need to make sure there are enough registers; the only valid
1515 // registers are the 4 used for parameters. We don't currently do this
1517 if (isa<ExternalSymbolSDNode>(Callee))
1520 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1521 const GlobalValue *GV = G->getGlobal();
1522 if (GV->isDeclaration() || GV->isWeakForLinker())
1526 // If the calling conventions do not match, then we'd better make sure the
1527 // results are returned in the same way as what the caller expects.
1529 SmallVector<CCValAssign, 16> RVLocs1;
1530 CCState CCInfo1(CalleeCC, false, getTargetMachine(),
1531 RVLocs1, *DAG.getContext());
1532 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
1534 SmallVector<CCValAssign, 16> RVLocs2;
1535 CCState CCInfo2(CallerCC, false, getTargetMachine(),
1536 RVLocs2, *DAG.getContext());
1537 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
1539 if (RVLocs1.size() != RVLocs2.size())
1541 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
1542 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
1544 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
1546 if (RVLocs1[i].isRegLoc()) {
1547 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
1550 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
1556 // If the callee takes no arguments then go on to check the results of the
1558 if (!Outs.empty()) {
1559 // Check if stack adjustment is needed. For now, do not do this if any
1560 // argument is passed on the stack.
1561 SmallVector<CCValAssign, 16> ArgLocs;
1562 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
1563 ArgLocs, *DAG.getContext());
1564 CCInfo.AnalyzeCallOperands(Outs,
1565 CCAssignFnForNode(CalleeCC, false, isVarArg));
1566 if (CCInfo.getNextStackOffset()) {
1567 MachineFunction &MF = DAG.getMachineFunction();
1569 // Check if the arguments are already laid out in the right way as
1570 // the caller's fixed stack objects.
1571 MachineFrameInfo *MFI = MF.getFrameInfo();
1572 const MachineRegisterInfo *MRI = &MF.getRegInfo();
1573 const ARMInstrInfo *TII =
1574 ((ARMTargetMachine&)getTargetMachine()).getInstrInfo();
1575 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1577 ++i, ++realArgIdx) {
1578 CCValAssign &VA = ArgLocs[i];
1579 EVT RegVT = VA.getLocVT();
1580 SDValue Arg = OutVals[realArgIdx];
1581 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1582 if (VA.getLocInfo() == CCValAssign::Indirect)
1584 if (VA.needsCustom()) {
1585 // f64 and vector types are split into multiple registers or
1586 // register/stack-slot combinations. The types will not match
1587 // the registers; give up on memory f64 refs until we figure
1588 // out what to do about this.
1591 if (!ArgLocs[++i].isRegLoc())
1593 if (RegVT == MVT::v2f64) {
1594 if (!ArgLocs[++i].isRegLoc())
1596 if (!ArgLocs[++i].isRegLoc())
1599 } else if (!VA.isRegLoc()) {
1600 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
1612 ARMTargetLowering::LowerReturn(SDValue Chain,
1613 CallingConv::ID CallConv, bool isVarArg,
1614 const SmallVectorImpl<ISD::OutputArg> &Outs,
1615 const SmallVectorImpl<SDValue> &OutVals,
1616 DebugLoc dl, SelectionDAG &DAG) const {
1618 // CCValAssign - represent the assignment of the return value to a location.
1619 SmallVector<CCValAssign, 16> RVLocs;
1621 // CCState - Info about the registers and stack slots.
1622 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
1625 // Analyze outgoing return values.
1626 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1629 // If this is the first return lowered for this function, add
1630 // the regs to the liveout set for the function.
1631 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1632 for (unsigned i = 0; i != RVLocs.size(); ++i)
1633 if (RVLocs[i].isRegLoc())
1634 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1639 // Copy the result values into the output registers.
1640 for (unsigned i = 0, realRVLocIdx = 0;
1642 ++i, ++realRVLocIdx) {
1643 CCValAssign &VA = RVLocs[i];
1644 assert(VA.isRegLoc() && "Can only return in registers!");
1646 SDValue Arg = OutVals[realRVLocIdx];
1648 switch (VA.getLocInfo()) {
1649 default: llvm_unreachable("Unknown loc info!");
1650 case CCValAssign::Full: break;
1651 case CCValAssign::BCvt:
1652 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1656 if (VA.needsCustom()) {
1657 if (VA.getLocVT() == MVT::v2f64) {
1658 // Extract the first half and return it in two registers.
1659 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1660 DAG.getConstant(0, MVT::i32));
1661 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
1662 DAG.getVTList(MVT::i32, MVT::i32), Half);
1664 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1665 Flag = Chain.getValue(1);
1666 VA = RVLocs[++i]; // skip ahead to next loc
1667 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1668 HalfGPRs.getValue(1), Flag);
1669 Flag = Chain.getValue(1);
1670 VA = RVLocs[++i]; // skip ahead to next loc
1672 // Extract the 2nd half and fall through to handle it as an f64 value.
1673 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1674 DAG.getConstant(1, MVT::i32));
1676 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1678 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1679 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1680 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1681 Flag = Chain.getValue(1);
1682 VA = RVLocs[++i]; // skip ahead to next loc
1683 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1686 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1688 // Guarantee that all emitted copies are
1689 // stuck together, avoiding something bad.
1690 Flag = Chain.getValue(1);
1695 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1697 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1702 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1703 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1704 // one of the above mentioned nodes. It has to be wrapped because otherwise
1705 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1706 // be used to form addressing mode. These wrapped nodes will be selected
1708 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1709 EVT PtrVT = Op.getValueType();
1710 // FIXME there is no actual debug info here
1711 DebugLoc dl = Op.getDebugLoc();
1712 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1714 if (CP->isMachineConstantPoolEntry())
1715 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1716 CP->getAlignment());
1718 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1719 CP->getAlignment());
1720 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1723 unsigned ARMTargetLowering::getJumpTableEncoding() const {
1724 return MachineJumpTableInfo::EK_Inline;
1727 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
1728 SelectionDAG &DAG) const {
1729 MachineFunction &MF = DAG.getMachineFunction();
1730 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1731 unsigned ARMPCLabelIndex = 0;
1732 DebugLoc DL = Op.getDebugLoc();
1733 EVT PtrVT = getPointerTy();
1734 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1735 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1737 if (RelocM == Reloc::Static) {
1738 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
1740 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1741 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1742 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(BA, ARMPCLabelIndex,
1743 ARMCP::CPBlockAddress,
1745 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1747 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
1748 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
1749 MachinePointerInfo::getConstantPool(),
1751 if (RelocM == Reloc::Static)
1753 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1754 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
1757 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
1759 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1760 SelectionDAG &DAG) const {
1761 DebugLoc dl = GA->getDebugLoc();
1762 EVT PtrVT = getPointerTy();
1763 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1764 MachineFunction &MF = DAG.getMachineFunction();
1765 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1766 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1767 ARMConstantPoolValue *CPV =
1768 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1769 ARMCP::CPValue, PCAdj, "tlsgd", true);
1770 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1771 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
1772 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
1773 MachinePointerInfo::getConstantPool(),
1775 SDValue Chain = Argument.getValue(1);
1777 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1778 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
1780 // call __tls_get_addr.
1783 Entry.Node = Argument;
1784 Entry.Ty = (const Type *) Type::getInt32Ty(*DAG.getContext());
1785 Args.push_back(Entry);
1786 // FIXME: is there useful debug info available here?
1787 std::pair<SDValue, SDValue> CallResult =
1788 LowerCallTo(Chain, (const Type *) Type::getInt32Ty(*DAG.getContext()),
1789 false, false, false, false,
1790 0, CallingConv::C, false, /*isReturnValueUsed=*/true,
1791 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
1792 return CallResult.first;
1795 // Lower ISD::GlobalTLSAddress using the "initial exec" or
1796 // "local exec" model.
1798 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
1799 SelectionDAG &DAG) const {
1800 const GlobalValue *GV = GA->getGlobal();
1801 DebugLoc dl = GA->getDebugLoc();
1803 SDValue Chain = DAG.getEntryNode();
1804 EVT PtrVT = getPointerTy();
1805 // Get the Thread Pointer
1806 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1808 if (GV->isDeclaration()) {
1809 MachineFunction &MF = DAG.getMachineFunction();
1810 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1811 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1812 // Initial exec model.
1813 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1814 ARMConstantPoolValue *CPV =
1815 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1816 ARMCP::CPValue, PCAdj, "gottpoff", true);
1817 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1818 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1819 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1820 MachinePointerInfo::getConstantPool(),
1822 Chain = Offset.getValue(1);
1824 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1825 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
1827 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1828 MachinePointerInfo::getConstantPool(),
1832 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, "tpoff");
1833 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1834 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1835 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1836 MachinePointerInfo::getConstantPool(),
1840 // The address of the thread local variable is the add of the thread
1841 // pointer with the offset of the variable.
1842 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
1846 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
1847 // TODO: implement the "local dynamic" model
1848 assert(Subtarget->isTargetELF() &&
1849 "TLS not implemented for non-ELF targets");
1850 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1851 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
1852 // otherwise use the "Local Exec" TLS Model
1853 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
1854 return LowerToTLSGeneralDynamicModel(GA, DAG);
1856 return LowerToTLSExecModels(GA, DAG);
1859 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
1860 SelectionDAG &DAG) const {
1861 EVT PtrVT = getPointerTy();
1862 DebugLoc dl = Op.getDebugLoc();
1863 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1864 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1865 if (RelocM == Reloc::PIC_) {
1866 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
1867 ARMConstantPoolValue *CPV =
1868 new ARMConstantPoolValue(GV, UseGOTOFF ? "GOTOFF" : "GOT");
1869 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1870 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1871 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1873 MachinePointerInfo::getConstantPool(),
1875 SDValue Chain = Result.getValue(1);
1876 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1877 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
1879 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
1880 MachinePointerInfo::getGOT(), false, false, 0);
1883 // If we have T2 ops, we can materialize the address directly via movt/movw
1884 // pair. This is always cheaper.
1885 if (Subtarget->useMovt()) {
1886 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
1887 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
1889 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1890 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1891 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1892 MachinePointerInfo::getConstantPool(),
1898 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
1899 SelectionDAG &DAG) const {
1900 MachineFunction &MF = DAG.getMachineFunction();
1901 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1902 unsigned ARMPCLabelIndex = 0;
1903 EVT PtrVT = getPointerTy();
1904 DebugLoc dl = Op.getDebugLoc();
1905 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1906 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1908 if (RelocM == Reloc::Static)
1909 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1911 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1912 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8);
1913 ARMConstantPoolValue *CPV =
1914 new ARMConstantPoolValue(GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj);
1915 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1917 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1919 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1920 MachinePointerInfo::getConstantPool(),
1922 SDValue Chain = Result.getValue(1);
1924 if (RelocM == Reloc::PIC_) {
1925 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1926 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1929 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
1930 Result = DAG.getLoad(PtrVT, dl, Chain, Result, MachinePointerInfo::getGOT(),
1936 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
1937 SelectionDAG &DAG) const {
1938 assert(Subtarget->isTargetELF() &&
1939 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
1940 MachineFunction &MF = DAG.getMachineFunction();
1941 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1942 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1943 EVT PtrVT = getPointerTy();
1944 DebugLoc dl = Op.getDebugLoc();
1945 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1946 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1947 "_GLOBAL_OFFSET_TABLE_",
1948 ARMPCLabelIndex, PCAdj);
1949 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1950 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1951 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1952 MachinePointerInfo::getConstantPool(),
1954 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1955 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1959 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
1960 DebugLoc dl = Op.getDebugLoc();
1961 SDValue Val = DAG.getConstant(0, MVT::i32);
1962 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(0),
1963 Op.getOperand(1), Val);
1967 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
1968 DebugLoc dl = Op.getDebugLoc();
1969 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
1970 Op.getOperand(1), DAG.getConstant(0, MVT::i32));
1974 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
1975 const ARMSubtarget *Subtarget) const {
1976 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1977 DebugLoc dl = Op.getDebugLoc();
1979 default: return SDValue(); // Don't custom lower most intrinsics.
1980 case Intrinsic::arm_thread_pointer: {
1981 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1982 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1984 case Intrinsic::eh_sjlj_lsda: {
1985 MachineFunction &MF = DAG.getMachineFunction();
1986 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1987 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1988 EVT PtrVT = getPointerTy();
1989 DebugLoc dl = Op.getDebugLoc();
1990 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1992 unsigned PCAdj = (RelocM != Reloc::PIC_)
1993 ? 0 : (Subtarget->isThumb() ? 4 : 8);
1994 ARMConstantPoolValue *CPV =
1995 new ARMConstantPoolValue(MF.getFunction(), ARMPCLabelIndex,
1996 ARMCP::CPLSDA, PCAdj);
1997 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1998 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2000 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2001 MachinePointerInfo::getConstantPool(),
2004 if (RelocM == Reloc::PIC_) {
2005 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2006 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2013 static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG,
2014 const ARMSubtarget *Subtarget) {
2015 DebugLoc dl = Op.getDebugLoc();
2016 SDValue Op5 = Op.getOperand(5);
2017 unsigned isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue();
2018 // Some subtargets which have dmb and dsb instructions can handle barriers
2019 // directly. Some ARMv6 cpus can support them with the help of mcr
2020 // instruction. Thumb1 and pre-v6 ARM mode use a libcall instead and should
2022 unsigned Opc = isDeviceBarrier ? ARMISD::SYNCBARRIER : ARMISD::MEMBARRIER;
2023 if (Subtarget->hasDataBarrier())
2024 return DAG.getNode(Opc, dl, MVT::Other, Op.getOperand(0));
2026 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb1Only() &&
2027 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!");
2028 return DAG.getNode(Opc, dl, MVT::Other, Op.getOperand(0),
2029 DAG.getConstant(0, MVT::i32));
2033 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
2034 MachineFunction &MF = DAG.getMachineFunction();
2035 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
2037 // vastart just stores the address of the VarArgsFrameIndex slot into the
2038 // memory location argument.
2039 DebugLoc dl = Op.getDebugLoc();
2040 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2041 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2042 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2043 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2044 MachinePointerInfo(SV), false, false, 0);
2048 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
2049 SDValue &Root, SelectionDAG &DAG,
2050 DebugLoc dl) const {
2051 MachineFunction &MF = DAG.getMachineFunction();
2052 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2054 TargetRegisterClass *RC;
2055 if (AFI->isThumb1OnlyFunction())
2056 RC = ARM::tGPRRegisterClass;
2058 RC = ARM::GPRRegisterClass;
2060 // Transform the arguments stored in physical registers into virtual ones.
2061 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2062 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2065 if (NextVA.isMemLoc()) {
2066 MachineFrameInfo *MFI = MF.getFrameInfo();
2067 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
2069 // Create load node to retrieve arguments from the stack.
2070 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2071 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
2072 MachinePointerInfo::getFixedStack(FI),
2075 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2076 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2079 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
2083 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
2084 CallingConv::ID CallConv, bool isVarArg,
2085 const SmallVectorImpl<ISD::InputArg>
2087 DebugLoc dl, SelectionDAG &DAG,
2088 SmallVectorImpl<SDValue> &InVals)
2091 MachineFunction &MF = DAG.getMachineFunction();
2092 MachineFrameInfo *MFI = MF.getFrameInfo();
2094 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2096 // Assign locations to all of the incoming arguments.
2097 SmallVector<CCValAssign, 16> ArgLocs;
2098 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
2100 CCInfo.AnalyzeFormalArguments(Ins,
2101 CCAssignFnForNode(CallConv, /* Return*/ false,
2104 SmallVector<SDValue, 16> ArgValues;
2106 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2107 CCValAssign &VA = ArgLocs[i];
2109 // Arguments stored in registers.
2110 if (VA.isRegLoc()) {
2111 EVT RegVT = VA.getLocVT();
2114 if (VA.needsCustom()) {
2115 // f64 and vector types are split up into multiple registers or
2116 // combinations of registers and stack slots.
2117 if (VA.getLocVT() == MVT::v2f64) {
2118 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
2120 VA = ArgLocs[++i]; // skip ahead to next loc
2122 if (VA.isMemLoc()) {
2123 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
2124 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2125 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
2126 MachinePointerInfo::getFixedStack(FI),
2129 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
2132 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2133 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2134 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
2135 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2136 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
2138 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
2141 TargetRegisterClass *RC;
2143 if (RegVT == MVT::f32)
2144 RC = ARM::SPRRegisterClass;
2145 else if (RegVT == MVT::f64)
2146 RC = ARM::DPRRegisterClass;
2147 else if (RegVT == MVT::v2f64)
2148 RC = ARM::QPRRegisterClass;
2149 else if (RegVT == MVT::i32)
2150 RC = (AFI->isThumb1OnlyFunction() ?
2151 ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
2153 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2155 // Transform the arguments in physical registers into virtual ones.
2156 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2157 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2160 // If this is an 8 or 16-bit value, it is really passed promoted
2161 // to 32 bits. Insert an assert[sz]ext to capture this, then
2162 // truncate to the right size.
2163 switch (VA.getLocInfo()) {
2164 default: llvm_unreachable("Unknown loc info!");
2165 case CCValAssign::Full: break;
2166 case CCValAssign::BCvt:
2167 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
2169 case CCValAssign::SExt:
2170 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2171 DAG.getValueType(VA.getValVT()));
2172 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2174 case CCValAssign::ZExt:
2175 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2176 DAG.getValueType(VA.getValVT()));
2177 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2181 InVals.push_back(ArgValue);
2183 } else { // VA.isRegLoc()
2186 assert(VA.isMemLoc());
2187 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
2189 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
2190 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(), true);
2192 // Create load nodes to retrieve arguments from the stack.
2193 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2194 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2195 MachinePointerInfo::getFixedStack(FI),
2202 static const unsigned GPRArgRegs[] = {
2203 ARM::R0, ARM::R1, ARM::R2, ARM::R3
2206 unsigned NumGPRs = CCInfo.getFirstUnallocated
2207 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
2209 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
2210 unsigned VARegSize = (4 - NumGPRs) * 4;
2211 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
2212 unsigned ArgOffset = CCInfo.getNextStackOffset();
2213 if (VARegSaveSize) {
2214 // If this function is vararg, store any remaining integer argument regs
2215 // to their spots on the stack so that they may be loaded by deferencing
2216 // the result of va_next.
2217 AFI->setVarArgsRegSaveSize(VARegSaveSize);
2218 AFI->setVarArgsFrameIndex(
2219 MFI->CreateFixedObject(VARegSaveSize,
2220 ArgOffset + VARegSaveSize - VARegSize,
2222 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(),
2225 SmallVector<SDValue, 4> MemOps;
2226 for (; NumGPRs < 4; ++NumGPRs) {
2227 TargetRegisterClass *RC;
2228 if (AFI->isThumb1OnlyFunction())
2229 RC = ARM::tGPRRegisterClass;
2231 RC = ARM::GPRRegisterClass;
2233 unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
2234 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2236 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2237 MachinePointerInfo::getFixedStack(AFI->getVarArgsFrameIndex()),
2239 MemOps.push_back(Store);
2240 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
2241 DAG.getConstant(4, getPointerTy()));
2243 if (!MemOps.empty())
2244 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2245 &MemOps[0], MemOps.size());
2247 // This will point to the next argument passed via stack.
2248 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset, true));
2254 /// isFloatingPointZero - Return true if this is +0.0.
2255 static bool isFloatingPointZero(SDValue Op) {
2256 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
2257 return CFP->getValueAPF().isPosZero();
2258 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
2259 // Maybe this has already been legalized into the constant pool?
2260 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
2261 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
2262 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
2263 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
2264 return CFP->getValueAPF().isPosZero();
2270 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
2271 /// the given operands.
2273 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2274 SDValue &ARMcc, SelectionDAG &DAG,
2275 DebugLoc dl) const {
2276 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
2277 unsigned C = RHSC->getZExtValue();
2278 if (!isLegalICmpImmediate(C)) {
2279 // Constant does not fit, try adjusting it by one?
2284 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
2285 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
2286 RHS = DAG.getConstant(C-1, MVT::i32);
2291 if (C != 0 && isLegalICmpImmediate(C-1)) {
2292 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
2293 RHS = DAG.getConstant(C-1, MVT::i32);
2298 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
2299 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
2300 RHS = DAG.getConstant(C+1, MVT::i32);
2305 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
2306 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2307 RHS = DAG.getConstant(C+1, MVT::i32);
2314 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2315 ARMISD::NodeType CompareType;
2318 CompareType = ARMISD::CMP;
2323 CompareType = ARMISD::CMPZ;
2326 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2327 return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS);
2330 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
2332 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
2333 DebugLoc dl) const {
2335 if (!isFloatingPointZero(RHS))
2336 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS);
2338 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS);
2339 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp);
2342 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2343 SDValue Cond = Op.getOperand(0);
2344 SDValue SelectTrue = Op.getOperand(1);
2345 SDValue SelectFalse = Op.getOperand(2);
2346 DebugLoc dl = Op.getDebugLoc();
2350 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
2351 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
2353 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
2354 const ConstantSDNode *CMOVTrue =
2355 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
2356 const ConstantSDNode *CMOVFalse =
2357 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
2359 if (CMOVTrue && CMOVFalse) {
2360 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
2361 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
2365 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
2367 False = SelectFalse;
2368 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
2373 if (True.getNode() && False.getNode()) {
2374 EVT VT = Cond.getValueType();
2375 SDValue ARMcc = Cond.getOperand(2);
2376 SDValue CCR = Cond.getOperand(3);
2377 SDValue Cmp = Cond.getOperand(4);
2378 return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp);
2383 return DAG.getSelectCC(dl, Cond,
2384 DAG.getConstant(0, Cond.getValueType()),
2385 SelectTrue, SelectFalse, ISD::SETNE);
2388 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
2389 EVT VT = Op.getValueType();
2390 SDValue LHS = Op.getOperand(0);
2391 SDValue RHS = Op.getOperand(1);
2392 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2393 SDValue TrueVal = Op.getOperand(2);
2394 SDValue FalseVal = Op.getOperand(3);
2395 DebugLoc dl = Op.getDebugLoc();
2397 if (LHS.getValueType() == MVT::i32) {
2399 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2400 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2401 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,Cmp);
2404 ARMCC::CondCodes CondCode, CondCode2;
2405 FPCCToARMCC(CC, CondCode, CondCode2);
2407 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2408 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2409 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2410 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
2412 if (CondCode2 != ARMCC::AL) {
2413 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32);
2414 // FIXME: Needs another CMP because flag can have but one use.
2415 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
2416 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
2417 Result, TrueVal, ARMcc2, CCR, Cmp2);
2422 /// canChangeToInt - Given the fp compare operand, return true if it is suitable
2423 /// to morph to an integer compare sequence.
2424 static bool canChangeToInt(SDValue Op, bool &SeenZero,
2425 const ARMSubtarget *Subtarget) {
2426 SDNode *N = Op.getNode();
2427 if (!N->hasOneUse())
2428 // Otherwise it requires moving the value from fp to integer registers.
2430 if (!N->getNumValues())
2432 EVT VT = Op.getValueType();
2433 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
2434 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
2435 // vmrs are very slow, e.g. cortex-a8.
2438 if (isFloatingPointZero(Op)) {
2442 return ISD::isNormalLoad(N);
2445 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
2446 if (isFloatingPointZero(Op))
2447 return DAG.getConstant(0, MVT::i32);
2449 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
2450 return DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2451 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(),
2452 Ld->isVolatile(), Ld->isNonTemporal(),
2453 Ld->getAlignment());
2455 llvm_unreachable("Unknown VFP cmp argument!");
2458 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
2459 SDValue &RetVal1, SDValue &RetVal2) {
2460 if (isFloatingPointZero(Op)) {
2461 RetVal1 = DAG.getConstant(0, MVT::i32);
2462 RetVal2 = DAG.getConstant(0, MVT::i32);
2466 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
2467 SDValue Ptr = Ld->getBasePtr();
2468 RetVal1 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2469 Ld->getChain(), Ptr,
2470 Ld->getPointerInfo(),
2471 Ld->isVolatile(), Ld->isNonTemporal(),
2472 Ld->getAlignment());
2474 EVT PtrType = Ptr.getValueType();
2475 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
2476 SDValue NewPtr = DAG.getNode(ISD::ADD, Op.getDebugLoc(),
2477 PtrType, Ptr, DAG.getConstant(4, PtrType));
2478 RetVal2 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2479 Ld->getChain(), NewPtr,
2480 Ld->getPointerInfo().getWithOffset(4),
2481 Ld->isVolatile(), Ld->isNonTemporal(),
2486 llvm_unreachable("Unknown VFP cmp argument!");
2489 /// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
2490 /// f32 and even f64 comparisons to integer ones.
2492 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
2493 SDValue Chain = Op.getOperand(0);
2494 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2495 SDValue LHS = Op.getOperand(2);
2496 SDValue RHS = Op.getOperand(3);
2497 SDValue Dest = Op.getOperand(4);
2498 DebugLoc dl = Op.getDebugLoc();
2500 bool SeenZero = false;
2501 if (canChangeToInt(LHS, SeenZero, Subtarget) &&
2502 canChangeToInt(RHS, SeenZero, Subtarget) &&
2503 // If one of the operand is zero, it's safe to ignore the NaN case since
2504 // we only care about equality comparisons.
2505 (SeenZero || (DAG.isKnownNeverNaN(LHS) && DAG.isKnownNeverNaN(RHS)))) {
2506 // If unsafe fp math optimization is enabled and there are no othter uses of
2507 // the CMP operands, and the condition code is EQ oe NE, we can optimize it
2508 // to an integer comparison.
2509 if (CC == ISD::SETOEQ)
2511 else if (CC == ISD::SETUNE)
2515 if (LHS.getValueType() == MVT::f32) {
2516 LHS = bitcastf32Toi32(LHS, DAG);
2517 RHS = bitcastf32Toi32(RHS, DAG);
2518 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2519 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2520 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2521 Chain, Dest, ARMcc, CCR, Cmp);
2526 expandf64Toi32(LHS, DAG, LHS1, LHS2);
2527 expandf64Toi32(RHS, DAG, RHS1, RHS2);
2528 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2529 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2530 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
2531 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
2532 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7);
2538 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2539 SDValue Chain = Op.getOperand(0);
2540 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2541 SDValue LHS = Op.getOperand(2);
2542 SDValue RHS = Op.getOperand(3);
2543 SDValue Dest = Op.getOperand(4);
2544 DebugLoc dl = Op.getDebugLoc();
2546 if (LHS.getValueType() == MVT::i32) {
2548 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2549 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2550 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2551 Chain, Dest, ARMcc, CCR, Cmp);
2554 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
2557 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
2558 CC == ISD::SETNE || CC == ISD::SETUNE)) {
2559 SDValue Result = OptimizeVFPBrcond(Op, DAG);
2560 if (Result.getNode())
2564 ARMCC::CondCodes CondCode, CondCode2;
2565 FPCCToARMCC(CC, CondCode, CondCode2);
2567 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2568 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2569 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2570 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
2571 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
2572 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2573 if (CondCode2 != ARMCC::AL) {
2574 ARMcc = DAG.getConstant(CondCode2, MVT::i32);
2575 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
2576 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2581 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
2582 SDValue Chain = Op.getOperand(0);
2583 SDValue Table = Op.getOperand(1);
2584 SDValue Index = Op.getOperand(2);
2585 DebugLoc dl = Op.getDebugLoc();
2587 EVT PTy = getPointerTy();
2588 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
2589 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
2590 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
2591 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
2592 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
2593 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
2594 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2595 if (Subtarget->isThumb2()) {
2596 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
2597 // which does another jump to the destination. This also makes it easier
2598 // to translate it to TBB / TBH later.
2599 // FIXME: This might not work if the function is extremely large.
2600 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
2601 Addr, Op.getOperand(2), JTI, UId);
2603 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2604 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
2605 MachinePointerInfo::getJumpTable(),
2607 Chain = Addr.getValue(1);
2608 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
2609 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2611 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
2612 MachinePointerInfo::getJumpTable(), false, false, 0);
2613 Chain = Addr.getValue(1);
2614 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2618 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
2619 DebugLoc dl = Op.getDebugLoc();
2622 switch (Op.getOpcode()) {
2624 assert(0 && "Invalid opcode!");
2625 case ISD::FP_TO_SINT:
2626 Opc = ARMISD::FTOSI;
2628 case ISD::FP_TO_UINT:
2629 Opc = ARMISD::FTOUI;
2632 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
2633 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
2636 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
2637 EVT VT = Op.getValueType();
2638 DebugLoc dl = Op.getDebugLoc();
2641 switch (Op.getOpcode()) {
2643 assert(0 && "Invalid opcode!");
2644 case ISD::SINT_TO_FP:
2645 Opc = ARMISD::SITOF;
2647 case ISD::UINT_TO_FP:
2648 Opc = ARMISD::UITOF;
2652 Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
2653 return DAG.getNode(Opc, dl, VT, Op);
2656 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
2657 // Implement fcopysign with a fabs and a conditional fneg.
2658 SDValue Tmp0 = Op.getOperand(0);
2659 SDValue Tmp1 = Op.getOperand(1);
2660 DebugLoc dl = Op.getDebugLoc();
2661 EVT VT = Op.getValueType();
2662 EVT SrcVT = Tmp1.getValueType();
2663 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
2664 SDValue ARMcc = DAG.getConstant(ARMCC::LT, MVT::i32);
2665 SDValue FP0 = DAG.getConstantFP(0.0, SrcVT);
2666 SDValue Cmp = getVFPCmp(Tmp1, FP0, DAG, dl);
2667 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2668 return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMcc, CCR, Cmp);
2671 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
2672 MachineFunction &MF = DAG.getMachineFunction();
2673 MachineFrameInfo *MFI = MF.getFrameInfo();
2674 MFI->setReturnAddressIsTaken(true);
2676 EVT VT = Op.getValueType();
2677 DebugLoc dl = Op.getDebugLoc();
2678 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2680 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
2681 SDValue Offset = DAG.getConstant(4, MVT::i32);
2682 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
2683 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
2684 MachinePointerInfo(), false, false, 0);
2687 // Return LR, which contains the return address. Mark it an implicit live-in.
2688 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
2689 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
2692 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2693 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2694 MFI->setFrameAddressIsTaken(true);
2696 EVT VT = Op.getValueType();
2697 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
2698 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2699 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
2700 ? ARM::R7 : ARM::R11;
2701 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
2703 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
2704 MachinePointerInfo(),
2709 /// ExpandBIT_CONVERT - If the target supports VFP, this function is called to
2710 /// expand a bit convert where either the source or destination type is i64 to
2711 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
2712 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
2713 /// vectors), since the legalizer won't know what to do with that.
2714 static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
2715 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2716 DebugLoc dl = N->getDebugLoc();
2717 SDValue Op = N->getOperand(0);
2719 // This function is only supposed to be called for i64 types, either as the
2720 // source or destination of the bit convert.
2721 EVT SrcVT = Op.getValueType();
2722 EVT DstVT = N->getValueType(0);
2723 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
2724 "ExpandBIT_CONVERT called for non-i64 type");
2726 // Turn i64->f64 into VMOVDRR.
2727 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
2728 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2729 DAG.getConstant(0, MVT::i32));
2730 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2731 DAG.getConstant(1, MVT::i32));
2732 return DAG.getNode(ISD::BIT_CONVERT, dl, DstVT,
2733 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
2736 // Turn f64->i64 into VMOVRRD.
2737 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
2738 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
2739 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
2740 // Merge the pieces into a single i64 value.
2741 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
2747 /// getZeroVector - Returns a vector of specified type with all zero elements.
2748 /// Zero vectors are used to represent vector negation and in those cases
2749 /// will be implemented with the NEON VNEG instruction. However, VNEG does
2750 /// not support i64 elements, so sometimes the zero vectors will need to be
2751 /// explicitly constructed. Regardless, use a canonical VMOV to create the
2753 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2754 assert(VT.isVector() && "Expected a vector type");
2755 // The canonical modified immediate encoding of a zero vector is....0!
2756 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32);
2757 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
2758 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
2759 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov);
2762 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
2763 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2764 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
2765 SelectionDAG &DAG) const {
2766 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2767 EVT VT = Op.getValueType();
2768 unsigned VTBits = VT.getSizeInBits();
2769 DebugLoc dl = Op.getDebugLoc();
2770 SDValue ShOpLo = Op.getOperand(0);
2771 SDValue ShOpHi = Op.getOperand(1);
2772 SDValue ShAmt = Op.getOperand(2);
2774 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
2776 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
2778 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2779 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2780 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
2781 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2782 DAG.getConstant(VTBits, MVT::i32));
2783 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
2784 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2785 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
2787 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2788 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
2790 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
2791 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
2794 SDValue Ops[2] = { Lo, Hi };
2795 return DAG.getMergeValues(Ops, 2, dl);
2798 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
2799 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2800 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
2801 SelectionDAG &DAG) const {
2802 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2803 EVT VT = Op.getValueType();
2804 unsigned VTBits = VT.getSizeInBits();
2805 DebugLoc dl = Op.getDebugLoc();
2806 SDValue ShOpLo = Op.getOperand(0);
2807 SDValue ShOpHi = Op.getOperand(1);
2808 SDValue ShAmt = Op.getOperand(2);
2811 assert(Op.getOpcode() == ISD::SHL_PARTS);
2812 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2813 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2814 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
2815 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2816 DAG.getConstant(VTBits, MVT::i32));
2817 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
2818 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
2820 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2821 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2822 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
2824 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
2825 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
2828 SDValue Ops[2] = { Lo, Hi };
2829 return DAG.getMergeValues(Ops, 2, dl);
2832 SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
2833 SelectionDAG &DAG) const {
2834 // The rounding mode is in bits 23:22 of the FPSCR.
2835 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
2836 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
2837 // so that the shift + and get folded into a bitfield extract.
2838 DebugLoc dl = Op.getDebugLoc();
2839 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
2840 DAG.getConstant(Intrinsic::arm_get_fpscr,
2842 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
2843 DAG.getConstant(1U << 22, MVT::i32));
2844 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
2845 DAG.getConstant(22, MVT::i32));
2846 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
2847 DAG.getConstant(3, MVT::i32));
2850 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
2851 const ARMSubtarget *ST) {
2852 EVT VT = N->getValueType(0);
2853 DebugLoc dl = N->getDebugLoc();
2855 if (!ST->hasV6T2Ops())
2858 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
2859 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
2862 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
2863 const ARMSubtarget *ST) {
2864 EVT VT = N->getValueType(0);
2865 DebugLoc dl = N->getDebugLoc();
2867 // Lower vector shifts on NEON to use VSHL.
2868 if (VT.isVector()) {
2869 assert(ST->hasNEON() && "unexpected vector shift");
2871 // Left shifts translate directly to the vshiftu intrinsic.
2872 if (N->getOpcode() == ISD::SHL)
2873 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2874 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
2875 N->getOperand(0), N->getOperand(1));
2877 assert((N->getOpcode() == ISD::SRA ||
2878 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
2880 // NEON uses the same intrinsics for both left and right shifts. For
2881 // right shifts, the shift amounts are negative, so negate the vector of
2883 EVT ShiftVT = N->getOperand(1).getValueType();
2884 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
2885 getZeroVector(ShiftVT, DAG, dl),
2887 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
2888 Intrinsic::arm_neon_vshifts :
2889 Intrinsic::arm_neon_vshiftu);
2890 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2891 DAG.getConstant(vshiftInt, MVT::i32),
2892 N->getOperand(0), NegatedCount);
2895 // We can get here for a node like i32 = ISD::SHL i32, i64
2899 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
2900 "Unknown shift to lower!");
2902 // We only lower SRA, SRL of 1 here, all others use generic lowering.
2903 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
2904 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
2907 // If we are in thumb mode, we don't have RRX.
2908 if (ST->isThumb1Only()) return SDValue();
2910 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
2911 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2912 DAG.getConstant(0, MVT::i32));
2913 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2914 DAG.getConstant(1, MVT::i32));
2916 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
2917 // captures the result into a carry flag.
2918 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
2919 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
2921 // The low part is an ARMISD::RRX operand, which shifts the carry in.
2922 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
2924 // Merge the pieces into a single i64 value.
2925 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
2928 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
2929 SDValue TmpOp0, TmpOp1;
2930 bool Invert = false;
2934 SDValue Op0 = Op.getOperand(0);
2935 SDValue Op1 = Op.getOperand(1);
2936 SDValue CC = Op.getOperand(2);
2937 EVT VT = Op.getValueType();
2938 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
2939 DebugLoc dl = Op.getDebugLoc();
2941 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
2942 switch (SetCCOpcode) {
2943 default: llvm_unreachable("Illegal FP comparison"); break;
2945 case ISD::SETNE: Invert = true; // Fallthrough
2947 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2949 case ISD::SETLT: Swap = true; // Fallthrough
2951 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2953 case ISD::SETLE: Swap = true; // Fallthrough
2955 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2956 case ISD::SETUGE: Swap = true; // Fallthrough
2957 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
2958 case ISD::SETUGT: Swap = true; // Fallthrough
2959 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
2960 case ISD::SETUEQ: Invert = true; // Fallthrough
2962 // Expand this to (OLT | OGT).
2966 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2967 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
2969 case ISD::SETUO: Invert = true; // Fallthrough
2971 // Expand this to (OLT | OGE).
2975 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2976 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
2980 // Integer comparisons.
2981 switch (SetCCOpcode) {
2982 default: llvm_unreachable("Illegal integer comparison"); break;
2983 case ISD::SETNE: Invert = true;
2984 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2985 case ISD::SETLT: Swap = true;
2986 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2987 case ISD::SETLE: Swap = true;
2988 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2989 case ISD::SETULT: Swap = true;
2990 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
2991 case ISD::SETULE: Swap = true;
2992 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
2995 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
2996 if (Opc == ARMISD::VCEQ) {
2999 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
3001 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
3004 // Ignore bitconvert.
3005 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BIT_CONVERT)
3006 AndOp = AndOp.getOperand(0);
3008 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
3010 Op0 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(0));
3011 Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(1));
3018 std::swap(Op0, Op1);
3020 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3023 Result = DAG.getNOT(dl, Result, VT);
3028 /// isNEONModifiedImm - Check if the specified splat value corresponds to a
3029 /// valid vector constant for a NEON instruction with a "modified immediate"
3030 /// operand (e.g., VMOV). If so, return the encoded value.
3031 static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
3032 unsigned SplatBitSize, SelectionDAG &DAG,
3033 EVT &VT, bool is128Bits, bool isVMOV) {
3034 unsigned OpCmode, Imm;
3036 // SplatBitSize is set to the smallest size that splats the vector, so a
3037 // zero vector will always have SplatBitSize == 8. However, NEON modified
3038 // immediate instructions others than VMOV do not support the 8-bit encoding
3039 // of a zero vector, and the default encoding of zero is supposed to be the
3044 switch (SplatBitSize) {
3048 // Any 1-byte value is OK. Op=0, Cmode=1110.
3049 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
3052 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
3056 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
3057 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
3058 if ((SplatBits & ~0xff) == 0) {
3059 // Value = 0x00nn: Op=x, Cmode=100x.
3064 if ((SplatBits & ~0xff00) == 0) {
3065 // Value = 0xnn00: Op=x, Cmode=101x.
3067 Imm = SplatBits >> 8;
3073 // NEON's 32-bit VMOV supports splat values where:
3074 // * only one byte is nonzero, or
3075 // * the least significant byte is 0xff and the second byte is nonzero, or
3076 // * the least significant 2 bytes are 0xff and the third is nonzero.
3077 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
3078 if ((SplatBits & ~0xff) == 0) {
3079 // Value = 0x000000nn: Op=x, Cmode=000x.
3084 if ((SplatBits & ~0xff00) == 0) {
3085 // Value = 0x0000nn00: Op=x, Cmode=001x.
3087 Imm = SplatBits >> 8;
3090 if ((SplatBits & ~0xff0000) == 0) {
3091 // Value = 0x00nn0000: Op=x, Cmode=010x.
3093 Imm = SplatBits >> 16;
3096 if ((SplatBits & ~0xff000000) == 0) {
3097 // Value = 0xnn000000: Op=x, Cmode=011x.
3099 Imm = SplatBits >> 24;
3103 if ((SplatBits & ~0xffff) == 0 &&
3104 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
3105 // Value = 0x0000nnff: Op=x, Cmode=1100.
3107 Imm = SplatBits >> 8;
3112 if ((SplatBits & ~0xffffff) == 0 &&
3113 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
3114 // Value = 0x00nnffff: Op=x, Cmode=1101.
3116 Imm = SplatBits >> 16;
3117 SplatBits |= 0xffff;
3121 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
3122 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
3123 // VMOV.I32. A (very) minor optimization would be to replicate the value
3124 // and fall through here to test for a valid 64-bit splat. But, then the
3125 // caller would also need to check and handle the change in size.
3131 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
3132 uint64_t BitMask = 0xff;
3134 unsigned ImmMask = 1;
3136 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
3137 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
3140 } else if ((SplatBits & BitMask) != 0) {
3146 // Op=1, Cmode=1110.
3149 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
3154 llvm_unreachable("unexpected size for isNEONModifiedImm");
3158 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
3159 return DAG.getTargetConstant(EncodedVal, MVT::i32);
3162 static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT,
3163 bool &ReverseVEXT, unsigned &Imm) {
3164 unsigned NumElts = VT.getVectorNumElements();
3165 ReverseVEXT = false;
3167 // Assume that the first shuffle index is not UNDEF. Fail if it is.
3173 // If this is a VEXT shuffle, the immediate value is the index of the first
3174 // element. The other shuffle indices must be the successive elements after
3176 unsigned ExpectedElt = Imm;
3177 for (unsigned i = 1; i < NumElts; ++i) {
3178 // Increment the expected index. If it wraps around, it may still be
3179 // a VEXT but the source vectors must be swapped.
3181 if (ExpectedElt == NumElts * 2) {
3186 if (M[i] < 0) continue; // ignore UNDEF indices
3187 if (ExpectedElt != static_cast<unsigned>(M[i]))
3191 // Adjust the index value if the source operands will be swapped.
3198 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
3199 /// instruction with the specified blocksize. (The order of the elements
3200 /// within each block of the vector is reversed.)
3201 static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT,
3202 unsigned BlockSize) {
3203 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
3204 "Only possible block sizes for VREV are: 16, 32, 64");
3206 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3210 unsigned NumElts = VT.getVectorNumElements();
3211 unsigned BlockElts = M[0] + 1;
3212 // If the first shuffle index is UNDEF, be optimistic.
3214 BlockElts = BlockSize / EltSz;
3216 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
3219 for (unsigned i = 0; i < NumElts; ++i) {
3220 if (M[i] < 0) continue; // ignore UNDEF indices
3221 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
3228 static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT,
3229 unsigned &WhichResult) {
3230 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3234 unsigned NumElts = VT.getVectorNumElements();
3235 WhichResult = (M[0] == 0 ? 0 : 1);
3236 for (unsigned i = 0; i < NumElts; i += 2) {
3237 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3238 (M[i+1] >= 0 && (unsigned) M[i+1] != i + NumElts + WhichResult))
3244 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
3245 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3246 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
3247 static bool isVTRN_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3248 unsigned &WhichResult) {
3249 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3253 unsigned NumElts = VT.getVectorNumElements();
3254 WhichResult = (M[0] == 0 ? 0 : 1);
3255 for (unsigned i = 0; i < NumElts; i += 2) {
3256 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3257 (M[i+1] >= 0 && (unsigned) M[i+1] != i + WhichResult))
3263 static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT,
3264 unsigned &WhichResult) {
3265 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3269 unsigned NumElts = VT.getVectorNumElements();
3270 WhichResult = (M[0] == 0 ? 0 : 1);
3271 for (unsigned i = 0; i != NumElts; ++i) {
3272 if (M[i] < 0) continue; // ignore UNDEF indices
3273 if ((unsigned) M[i] != 2 * i + WhichResult)
3277 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3278 if (VT.is64BitVector() && EltSz == 32)
3284 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
3285 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3286 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
3287 static bool isVUZP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3288 unsigned &WhichResult) {
3289 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3293 unsigned Half = VT.getVectorNumElements() / 2;
3294 WhichResult = (M[0] == 0 ? 0 : 1);
3295 for (unsigned j = 0; j != 2; ++j) {
3296 unsigned Idx = WhichResult;
3297 for (unsigned i = 0; i != Half; ++i) {
3298 int MIdx = M[i + j * Half];
3299 if (MIdx >= 0 && (unsigned) MIdx != Idx)
3305 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3306 if (VT.is64BitVector() && EltSz == 32)
3312 static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT,
3313 unsigned &WhichResult) {
3314 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3318 unsigned NumElts = VT.getVectorNumElements();
3319 WhichResult = (M[0] == 0 ? 0 : 1);
3320 unsigned Idx = WhichResult * NumElts / 2;
3321 for (unsigned i = 0; i != NumElts; i += 2) {
3322 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3323 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts))
3328 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3329 if (VT.is64BitVector() && EltSz == 32)
3335 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
3336 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3337 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
3338 static bool isVZIP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3339 unsigned &WhichResult) {
3340 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3344 unsigned NumElts = VT.getVectorNumElements();
3345 WhichResult = (M[0] == 0 ? 0 : 1);
3346 unsigned Idx = WhichResult * NumElts / 2;
3347 for (unsigned i = 0; i != NumElts; i += 2) {
3348 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3349 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx))
3354 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3355 if (VT.is64BitVector() && EltSz == 32)
3361 // If N is an integer constant that can be moved into a register in one
3362 // instruction, return an SDValue of such a constant (will become a MOV
3363 // instruction). Otherwise return null.
3364 static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG,
3365 const ARMSubtarget *ST, DebugLoc dl) {
3367 if (!isa<ConstantSDNode>(N))
3369 Val = cast<ConstantSDNode>(N)->getZExtValue();
3371 if (ST->isThumb1Only()) {
3372 if (Val <= 255 || ~Val <= 255)
3373 return DAG.getConstant(Val, MVT::i32);
3375 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1)
3376 return DAG.getConstant(Val, MVT::i32);
3381 // If this is a case we can't handle, return null and let the default
3382 // expansion code take care of it.
3383 static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
3384 const ARMSubtarget *ST) {
3385 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
3386 DebugLoc dl = Op.getDebugLoc();
3387 EVT VT = Op.getValueType();
3389 APInt SplatBits, SplatUndef;
3390 unsigned SplatBitSize;
3392 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
3393 if (SplatBitSize <= 64) {
3394 // Check if an immediate VMOV works.
3396 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
3397 SplatUndef.getZExtValue(), SplatBitSize,
3398 DAG, VmovVT, VT.is128BitVector(), true);
3399 if (Val.getNode()) {
3400 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
3401 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov);
3404 // Try an immediate VMVN.
3405 uint64_t NegatedImm = (SplatBits.getZExtValue() ^
3406 ((1LL << SplatBitSize) - 1));
3407 Val = isNEONModifiedImm(NegatedImm,
3408 SplatUndef.getZExtValue(), SplatBitSize,
3409 DAG, VmovVT, VT.is128BitVector(), false);
3410 if (Val.getNode()) {
3411 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
3412 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov);
3417 // Scan through the operands to see if only one value is used.
3418 unsigned NumElts = VT.getVectorNumElements();
3419 bool isOnlyLowElement = true;
3420 bool usesOnlyOneValue = true;
3421 bool isConstant = true;
3423 for (unsigned i = 0; i < NumElts; ++i) {
3424 SDValue V = Op.getOperand(i);
3425 if (V.getOpcode() == ISD::UNDEF)
3428 isOnlyLowElement = false;
3429 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
3432 if (!Value.getNode())
3434 else if (V != Value)
3435 usesOnlyOneValue = false;
3438 if (!Value.getNode())
3439 return DAG.getUNDEF(VT);
3441 if (isOnlyLowElement)
3442 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
3444 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3446 if (EnableARMVDUPsplat) {
3447 // Use VDUP for non-constant splats. For f32 constant splats, reduce to
3448 // i32 and try again.
3449 if (usesOnlyOneValue && EltSize <= 32) {
3451 return DAG.getNode(ARMISD::VDUP, dl, VT, Value);
3452 if (VT.getVectorElementType().isFloatingPoint()) {
3453 SmallVector<SDValue, 8> Ops;
3454 for (unsigned i = 0; i < NumElts; ++i)
3455 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32,
3457 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &Ops[0],
3459 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3460 LowerBUILD_VECTOR(Val, DAG, ST));
3462 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
3464 return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
3468 // If all elements are constants and the case above didn't get hit, fall back
3469 // to the default expansion, which will generate a load from the constant
3474 if (!EnableARMVDUPsplat) {
3475 // Use VDUP for non-constant splats.
3476 if (usesOnlyOneValue && EltSize <= 32)
3477 return DAG.getNode(ARMISD::VDUP, dl, VT, Value);
3480 // Vectors with 32- or 64-bit elements can be built by directly assigning
3481 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
3482 // will be legalized.
3483 if (EltSize >= 32) {
3484 // Do the expansion with floating-point types, since that is what the VFP
3485 // registers are defined to use, and since i64 is not legal.
3486 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3487 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3488 SmallVector<SDValue, 8> Ops;
3489 for (unsigned i = 0; i < NumElts; ++i)
3490 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, EltVT, Op.getOperand(i)));
3491 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
3492 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val);
3498 /// isShuffleMaskLegal - Targets can use this to indicate that they only
3499 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
3500 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
3501 /// are assumed to be legal.
3503 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
3505 if (VT.getVectorNumElements() == 4 &&
3506 (VT.is128BitVector() || VT.is64BitVector())) {
3507 unsigned PFIndexes[4];
3508 for (unsigned i = 0; i != 4; ++i) {
3512 PFIndexes[i] = M[i];
3515 // Compute the index in the perfect shuffle table.
3516 unsigned PFTableIndex =
3517 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3518 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3519 unsigned Cost = (PFEntry >> 30);
3526 unsigned Imm, WhichResult;
3528 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3529 return (EltSize >= 32 ||
3530 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
3531 isVREVMask(M, VT, 64) ||
3532 isVREVMask(M, VT, 32) ||
3533 isVREVMask(M, VT, 16) ||
3534 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
3535 isVTRNMask(M, VT, WhichResult) ||
3536 isVUZPMask(M, VT, WhichResult) ||
3537 isVZIPMask(M, VT, WhichResult) ||
3538 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
3539 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
3540 isVZIP_v_undef_Mask(M, VT, WhichResult));
3543 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
3544 /// the specified operations to build the shuffle.
3545 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
3546 SDValue RHS, SelectionDAG &DAG,
3548 unsigned OpNum = (PFEntry >> 26) & 0x0F;
3549 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
3550 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
3553 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
3562 OP_VUZPL, // VUZP, left result
3563 OP_VUZPR, // VUZP, right result
3564 OP_VZIPL, // VZIP, left result
3565 OP_VZIPR, // VZIP, right result
3566 OP_VTRNL, // VTRN, left result
3567 OP_VTRNR // VTRN, right result
3570 if (OpNum == OP_COPY) {
3571 if (LHSID == (1*9+2)*9+3) return LHS;
3572 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
3576 SDValue OpLHS, OpRHS;
3577 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
3578 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
3579 EVT VT = OpLHS.getValueType();
3582 default: llvm_unreachable("Unknown shuffle opcode!");
3584 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
3589 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
3590 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
3594 return DAG.getNode(ARMISD::VEXT, dl, VT,
3596 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
3599 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3600 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
3603 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3604 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
3607 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3608 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
3612 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
3613 SDValue V1 = Op.getOperand(0);
3614 SDValue V2 = Op.getOperand(1);
3615 DebugLoc dl = Op.getDebugLoc();
3616 EVT VT = Op.getValueType();
3617 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
3618 SmallVector<int, 8> ShuffleMask;
3620 // Convert shuffles that are directly supported on NEON to target-specific
3621 // DAG nodes, instead of keeping them as shuffles and matching them again
3622 // during code selection. This is more efficient and avoids the possibility
3623 // of inconsistencies between legalization and selection.
3624 // FIXME: floating-point vectors should be canonicalized to integer vectors
3625 // of the same time so that they get CSEd properly.
3626 SVN->getMask(ShuffleMask);
3628 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3629 if (EltSize <= 32) {
3630 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
3631 int Lane = SVN->getSplatIndex();
3632 // If this is undef splat, generate it via "just" vdup, if possible.
3633 if (Lane == -1) Lane = 0;
3635 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
3636 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
3638 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
3639 DAG.getConstant(Lane, MVT::i32));
3644 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
3647 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
3648 DAG.getConstant(Imm, MVT::i32));
3651 if (isVREVMask(ShuffleMask, VT, 64))
3652 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
3653 if (isVREVMask(ShuffleMask, VT, 32))
3654 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
3655 if (isVREVMask(ShuffleMask, VT, 16))
3656 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
3658 // Check for Neon shuffles that modify both input vectors in place.
3659 // If both results are used, i.e., if there are two shuffles with the same
3660 // source operands and with masks corresponding to both results of one of
3661 // these operations, DAG memoization will ensure that a single node is
3662 // used for both shuffles.
3663 unsigned WhichResult;
3664 if (isVTRNMask(ShuffleMask, VT, WhichResult))
3665 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3666 V1, V2).getValue(WhichResult);
3667 if (isVUZPMask(ShuffleMask, VT, WhichResult))
3668 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3669 V1, V2).getValue(WhichResult);
3670 if (isVZIPMask(ShuffleMask, VT, WhichResult))
3671 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3672 V1, V2).getValue(WhichResult);
3674 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
3675 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3676 V1, V1).getValue(WhichResult);
3677 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
3678 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3679 V1, V1).getValue(WhichResult);
3680 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
3681 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3682 V1, V1).getValue(WhichResult);
3685 // If the shuffle is not directly supported and it has 4 elements, use
3686 // the PerfectShuffle-generated table to synthesize it from other shuffles.
3687 unsigned NumElts = VT.getVectorNumElements();
3689 unsigned PFIndexes[4];
3690 for (unsigned i = 0; i != 4; ++i) {
3691 if (ShuffleMask[i] < 0)
3694 PFIndexes[i] = ShuffleMask[i];
3697 // Compute the index in the perfect shuffle table.
3698 unsigned PFTableIndex =
3699 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3700 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3701 unsigned Cost = (PFEntry >> 30);
3704 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
3707 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
3708 if (EltSize >= 32) {
3709 // Do the expansion with floating-point types, since that is what the VFP
3710 // registers are defined to use, and since i64 is not legal.
3711 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3712 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3713 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, V1);
3714 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, V2);
3715 SmallVector<SDValue, 8> Ops;
3716 for (unsigned i = 0; i < NumElts; ++i) {
3717 if (ShuffleMask[i] < 0)
3718 Ops.push_back(DAG.getUNDEF(EltVT));
3720 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3721 ShuffleMask[i] < (int)NumElts ? V1 : V2,
3722 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
3725 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
3726 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val);
3732 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
3733 EVT VT = Op.getValueType();
3734 DebugLoc dl = Op.getDebugLoc();
3735 SDValue Vec = Op.getOperand(0);
3736 SDValue Lane = Op.getOperand(1);
3737 assert(VT == MVT::i32 &&
3738 Vec.getValueType().getVectorElementType().getSizeInBits() < 32 &&
3739 "unexpected type for custom-lowering vector extract");
3740 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
3743 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
3744 // The only time a CONCAT_VECTORS operation can have legal types is when
3745 // two 64-bit vectors are concatenated to a 128-bit vector.
3746 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
3747 "unexpected CONCAT_VECTORS");
3748 DebugLoc dl = Op.getDebugLoc();
3749 SDValue Val = DAG.getUNDEF(MVT::v2f64);
3750 SDValue Op0 = Op.getOperand(0);
3751 SDValue Op1 = Op.getOperand(1);
3752 if (Op0.getOpcode() != ISD::UNDEF)
3753 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
3754 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op0),
3755 DAG.getIntPtrConstant(0));
3756 if (Op1.getOpcode() != ISD::UNDEF)
3757 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
3758 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op1),
3759 DAG.getIntPtrConstant(1));
3760 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Val);
3763 /// SkipExtension - For a node that is either a SIGN_EXTEND, ZERO_EXTEND, or
3764 /// an extending load, return the unextended value.
3765 static SDValue SkipExtension(SDNode *N, SelectionDAG &DAG) {
3766 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
3767 return N->getOperand(0);
3768 LoadSDNode *LD = cast<LoadSDNode>(N);
3769 return DAG.getLoad(LD->getMemoryVT(), N->getDebugLoc(), LD->getChain(),
3770 LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(),
3771 LD->isNonTemporal(), LD->getAlignment());
3774 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
3775 // Multiplications are only custom-lowered for 128-bit vectors so that
3776 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
3777 EVT VT = Op.getValueType();
3778 assert(VT.is128BitVector() && "unexpected type for custom-lowering ISD::MUL");
3779 SDNode *N0 = Op.getOperand(0).getNode();
3780 SDNode *N1 = Op.getOperand(1).getNode();
3781 unsigned NewOpc = 0;
3782 if ((N0->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N0)) &&
3783 (N1->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N1))) {
3784 NewOpc = ARMISD::VMULLs;
3785 } else if ((N0->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N0)) &&
3786 (N1->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N1))) {
3787 NewOpc = ARMISD::VMULLu;
3788 } else if (VT.getSimpleVT().SimpleTy == MVT::v2i64) {
3789 // Fall through to expand this. It is not legal.
3792 // Other vector multiplications are legal.
3796 // Legalize to a VMULL instruction.
3797 DebugLoc DL = Op.getDebugLoc();
3798 SDValue Op0 = SkipExtension(N0, DAG);
3799 SDValue Op1 = SkipExtension(N1, DAG);
3801 assert(Op0.getValueType().is64BitVector() &&
3802 Op1.getValueType().is64BitVector() &&
3803 "unexpected types for extended operands to VMULL");
3804 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
3807 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
3808 switch (Op.getOpcode()) {
3809 default: llvm_unreachable("Don't know how to custom lower this!");
3810 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3811 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
3812 case ISD::GlobalAddress:
3813 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
3814 LowerGlobalAddressELF(Op, DAG);
3815 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
3816 case ISD::SELECT: return LowerSELECT(Op, DAG);
3817 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
3818 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
3819 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
3820 case ISD::VASTART: return LowerVASTART(Op, DAG);
3821 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget);
3822 case ISD::SINT_TO_FP:
3823 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
3824 case ISD::FP_TO_SINT:
3825 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
3826 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
3827 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
3828 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
3829 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
3830 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
3831 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
3832 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
3834 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(Op.getNode(), DAG);
3837 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
3838 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
3839 case ISD::SRL_PARTS:
3840 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
3841 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
3842 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
3843 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
3844 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
3845 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
3846 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
3847 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
3848 case ISD::MUL: return LowerMUL(Op, DAG);
3853 /// ReplaceNodeResults - Replace the results of node with an illegal result
3854 /// type with new values built out of custom code.
3855 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
3856 SmallVectorImpl<SDValue>&Results,
3857 SelectionDAG &DAG) const {
3859 switch (N->getOpcode()) {
3861 llvm_unreachable("Don't know how to custom expand this!");
3863 case ISD::BIT_CONVERT:
3864 Res = ExpandBIT_CONVERT(N, DAG);
3868 Res = LowerShift(N, DAG, Subtarget);
3872 Results.push_back(Res);
3875 //===----------------------------------------------------------------------===//
3876 // ARM Scheduler Hooks
3877 //===----------------------------------------------------------------------===//
3880 ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
3881 MachineBasicBlock *BB,
3882 unsigned Size) const {
3883 unsigned dest = MI->getOperand(0).getReg();
3884 unsigned ptr = MI->getOperand(1).getReg();
3885 unsigned oldval = MI->getOperand(2).getReg();
3886 unsigned newval = MI->getOperand(3).getReg();
3887 unsigned scratch = BB->getParent()->getRegInfo()
3888 .createVirtualRegister(ARM::GPRRegisterClass);
3889 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3890 DebugLoc dl = MI->getDebugLoc();
3891 bool isThumb2 = Subtarget->isThumb2();
3893 unsigned ldrOpc, strOpc;
3895 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
3897 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
3898 strOpc = isThumb2 ? ARM::t2LDREXB : ARM::STREXB;
3901 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
3902 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
3905 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
3906 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
3910 MachineFunction *MF = BB->getParent();
3911 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3912 MachineFunction::iterator It = BB;
3913 ++It; // insert the new blocks after the current block
3915 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
3916 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
3917 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3918 MF->insert(It, loop1MBB);
3919 MF->insert(It, loop2MBB);
3920 MF->insert(It, exitMBB);
3922 // Transfer the remainder of BB and its successor edges to exitMBB.
3923 exitMBB->splice(exitMBB->begin(), BB,
3924 llvm::next(MachineBasicBlock::iterator(MI)),
3926 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
3930 // fallthrough --> loop1MBB
3931 BB->addSuccessor(loop1MBB);
3934 // ldrex dest, [ptr]
3938 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
3939 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
3940 .addReg(dest).addReg(oldval));
3941 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3942 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
3943 BB->addSuccessor(loop2MBB);
3944 BB->addSuccessor(exitMBB);
3947 // strex scratch, newval, [ptr]
3951 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval)
3953 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
3954 .addReg(scratch).addImm(0));
3955 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3956 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
3957 BB->addSuccessor(loop1MBB);
3958 BB->addSuccessor(exitMBB);
3964 MI->eraseFromParent(); // The instruction is gone now.
3970 ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
3971 unsigned Size, unsigned BinOpcode) const {
3972 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
3973 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3975 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3976 MachineFunction *MF = BB->getParent();
3977 MachineFunction::iterator It = BB;
3980 unsigned dest = MI->getOperand(0).getReg();
3981 unsigned ptr = MI->getOperand(1).getReg();
3982 unsigned incr = MI->getOperand(2).getReg();
3983 DebugLoc dl = MI->getDebugLoc();
3985 bool isThumb2 = Subtarget->isThumb2();
3986 unsigned ldrOpc, strOpc;
3988 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
3990 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
3991 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
3994 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
3995 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
3998 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
3999 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
4003 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
4004 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
4005 MF->insert(It, loopMBB);
4006 MF->insert(It, exitMBB);
4008 // Transfer the remainder of BB and its successor edges to exitMBB.
4009 exitMBB->splice(exitMBB->begin(), BB,
4010 llvm::next(MachineBasicBlock::iterator(MI)),
4012 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4014 MachineRegisterInfo &RegInfo = MF->getRegInfo();
4015 unsigned scratch = RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
4016 unsigned scratch2 = (!BinOpcode) ? incr :
4017 RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
4021 // fallthrough --> loopMBB
4022 BB->addSuccessor(loopMBB);
4026 // <binop> scratch2, dest, incr
4027 // strex scratch, scratch2, ptr
4030 // fallthrough --> exitMBB
4032 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
4034 // operand order needs to go the other way for NAND
4035 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr)
4036 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
4037 addReg(incr).addReg(dest)).addReg(0);
4039 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
4040 addReg(dest).addReg(incr)).addReg(0);
4043 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2)
4045 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4046 .addReg(scratch).addImm(0));
4047 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4048 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
4050 BB->addSuccessor(loopMBB);
4051 BB->addSuccessor(exitMBB);
4057 MI->eraseFromParent(); // The instruction is gone now.
4063 MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
4064 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
4065 E = MBB->succ_end(); I != E; ++I)
4068 llvm_unreachable("Expecting a BB with two successors!");
4072 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4073 MachineBasicBlock *BB) const {
4074 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4075 DebugLoc dl = MI->getDebugLoc();
4076 bool isThumb2 = Subtarget->isThumb2();
4077 switch (MI->getOpcode()) {
4080 llvm_unreachable("Unexpected instr type to insert");
4082 case ARM::ATOMIC_LOAD_ADD_I8:
4083 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
4084 case ARM::ATOMIC_LOAD_ADD_I16:
4085 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
4086 case ARM::ATOMIC_LOAD_ADD_I32:
4087 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
4089 case ARM::ATOMIC_LOAD_AND_I8:
4090 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
4091 case ARM::ATOMIC_LOAD_AND_I16:
4092 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
4093 case ARM::ATOMIC_LOAD_AND_I32:
4094 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
4096 case ARM::ATOMIC_LOAD_OR_I8:
4097 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
4098 case ARM::ATOMIC_LOAD_OR_I16:
4099 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
4100 case ARM::ATOMIC_LOAD_OR_I32:
4101 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
4103 case ARM::ATOMIC_LOAD_XOR_I8:
4104 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
4105 case ARM::ATOMIC_LOAD_XOR_I16:
4106 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
4107 case ARM::ATOMIC_LOAD_XOR_I32:
4108 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
4110 case ARM::ATOMIC_LOAD_NAND_I8:
4111 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
4112 case ARM::ATOMIC_LOAD_NAND_I16:
4113 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
4114 case ARM::ATOMIC_LOAD_NAND_I32:
4115 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
4117 case ARM::ATOMIC_LOAD_SUB_I8:
4118 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
4119 case ARM::ATOMIC_LOAD_SUB_I16:
4120 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
4121 case ARM::ATOMIC_LOAD_SUB_I32:
4122 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
4124 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0);
4125 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0);
4126 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0);
4128 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1);
4129 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
4130 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
4132 case ARM::tMOVCCr_pseudo: {
4133 // To "insert" a SELECT_CC instruction, we actually have to insert the
4134 // diamond control-flow pattern. The incoming instruction knows the
4135 // destination vreg to set, the condition code register to branch on, the
4136 // true/false values to select between, and a branch opcode to use.
4137 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4138 MachineFunction::iterator It = BB;
4144 // cmpTY ccX, r1, r2
4146 // fallthrough --> copy0MBB
4147 MachineBasicBlock *thisMBB = BB;
4148 MachineFunction *F = BB->getParent();
4149 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4150 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
4151 F->insert(It, copy0MBB);
4152 F->insert(It, sinkMBB);
4154 // Transfer the remainder of BB and its successor edges to sinkMBB.
4155 sinkMBB->splice(sinkMBB->begin(), BB,
4156 llvm::next(MachineBasicBlock::iterator(MI)),
4158 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
4160 BB->addSuccessor(copy0MBB);
4161 BB->addSuccessor(sinkMBB);
4163 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
4164 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
4167 // %FalseValue = ...
4168 // # fallthrough to sinkMBB
4171 // Update machine-CFG edges
4172 BB->addSuccessor(sinkMBB);
4175 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
4178 BuildMI(*BB, BB->begin(), dl,
4179 TII->get(ARM::PHI), MI->getOperand(0).getReg())
4180 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
4181 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
4183 MI->eraseFromParent(); // The pseudo instruction is gone now.
4188 case ARM::BCCZi64: {
4189 // Compare both parts that make up the double comparison separately for
4191 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
4193 unsigned LHS1 = MI->getOperand(1).getReg();
4194 unsigned LHS2 = MI->getOperand(2).getReg();
4196 AddDefaultPred(BuildMI(BB, dl,
4197 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4198 .addReg(LHS1).addImm(0));
4199 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4200 .addReg(LHS2).addImm(0)
4201 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
4203 unsigned RHS1 = MI->getOperand(3).getReg();
4204 unsigned RHS2 = MI->getOperand(4).getReg();
4205 AddDefaultPred(BuildMI(BB, dl,
4206 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
4207 .addReg(LHS1).addReg(RHS1));
4208 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
4209 .addReg(LHS2).addReg(RHS2)
4210 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
4213 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB();
4214 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
4215 if (MI->getOperand(0).getImm() == ARMCC::NE)
4216 std::swap(destMBB, exitMBB);
4218 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4219 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
4220 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2B : ARM::B))
4223 MI->eraseFromParent(); // The pseudo instruction is gone now.
4229 //===----------------------------------------------------------------------===//
4230 // ARM Optimization Hooks
4231 //===----------------------------------------------------------------------===//
4234 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
4235 TargetLowering::DAGCombinerInfo &DCI) {
4236 SelectionDAG &DAG = DCI.DAG;
4237 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4238 EVT VT = N->getValueType(0);
4239 unsigned Opc = N->getOpcode();
4240 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
4241 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
4242 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
4243 ISD::CondCode CC = ISD::SETCC_INVALID;
4246 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
4248 SDValue CCOp = Slct.getOperand(0);
4249 if (CCOp.getOpcode() == ISD::SETCC)
4250 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
4253 bool DoXform = false;
4255 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
4258 if (LHS.getOpcode() == ISD::Constant &&
4259 cast<ConstantSDNode>(LHS)->isNullValue()) {
4261 } else if (CC != ISD::SETCC_INVALID &&
4262 RHS.getOpcode() == ISD::Constant &&
4263 cast<ConstantSDNode>(RHS)->isNullValue()) {
4264 std::swap(LHS, RHS);
4265 SDValue Op0 = Slct.getOperand(0);
4266 EVT OpVT = isSlctCC ? Op0.getValueType() :
4267 Op0.getOperand(0).getValueType();
4268 bool isInt = OpVT.isInteger();
4269 CC = ISD::getSetCCInverse(CC, isInt);
4271 if (!TLI.isCondCodeLegal(CC, OpVT))
4272 return SDValue(); // Inverse operator isn't legal.
4279 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
4281 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
4282 Slct.getOperand(0), Slct.getOperand(1), CC);
4283 SDValue CCOp = Slct.getOperand(0);
4285 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
4286 CCOp.getOperand(0), CCOp.getOperand(1), CC);
4287 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
4288 CCOp, OtherOp, Result);
4293 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
4294 /// operands N0 and N1. This is a helper for PerformADDCombine that is
4295 /// called with the default operands, and if that fails, with commuted
4297 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
4298 TargetLowering::DAGCombinerInfo &DCI) {
4299 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
4300 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
4301 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
4302 if (Result.getNode()) return Result;
4307 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
4309 static SDValue PerformADDCombine(SDNode *N,
4310 TargetLowering::DAGCombinerInfo &DCI) {
4311 SDValue N0 = N->getOperand(0);
4312 SDValue N1 = N->getOperand(1);
4314 // First try with the default operand order.
4315 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI);
4316 if (Result.getNode())
4319 // If that didn't work, try again with the operands commuted.
4320 return PerformADDCombineWithOperands(N, N1, N0, DCI);
4323 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
4325 static SDValue PerformSUBCombine(SDNode *N,
4326 TargetLowering::DAGCombinerInfo &DCI) {
4327 SDValue N0 = N->getOperand(0);
4328 SDValue N1 = N->getOperand(1);
4330 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
4331 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
4332 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
4333 if (Result.getNode()) return Result;
4339 static SDValue PerformMULCombine(SDNode *N,
4340 TargetLowering::DAGCombinerInfo &DCI,
4341 const ARMSubtarget *Subtarget) {
4342 SelectionDAG &DAG = DCI.DAG;
4344 if (Subtarget->isThumb1Only())
4347 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
4350 EVT VT = N->getValueType(0);
4354 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
4358 uint64_t MulAmt = C->getZExtValue();
4359 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt);
4360 ShiftAmt = ShiftAmt & (32 - 1);
4361 SDValue V = N->getOperand(0);
4362 DebugLoc DL = N->getDebugLoc();
4365 MulAmt >>= ShiftAmt;
4366 if (isPowerOf2_32(MulAmt - 1)) {
4367 // (mul x, 2^N + 1) => (add (shl x, N), x)
4368 Res = DAG.getNode(ISD::ADD, DL, VT,
4369 V, DAG.getNode(ISD::SHL, DL, VT,
4370 V, DAG.getConstant(Log2_32(MulAmt-1),
4372 } else if (isPowerOf2_32(MulAmt + 1)) {
4373 // (mul x, 2^N - 1) => (sub (shl x, N), x)
4374 Res = DAG.getNode(ISD::SUB, DL, VT,
4375 DAG.getNode(ISD::SHL, DL, VT,
4376 V, DAG.getConstant(Log2_32(MulAmt+1),
4383 Res = DAG.getNode(ISD::SHL, DL, VT, Res,
4384 DAG.getConstant(ShiftAmt, MVT::i32));
4386 // Do not add new nodes to DAG combiner worklist.
4387 DCI.CombineTo(N, Res, false);
4391 /// PerformORCombine - Target-specific dag combine xforms for ISD::OR
4392 static SDValue PerformORCombine(SDNode *N,
4393 TargetLowering::DAGCombinerInfo &DCI,
4394 const ARMSubtarget *Subtarget) {
4395 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when
4398 // BFI is only available on V6T2+
4399 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops())
4402 SelectionDAG &DAG = DCI.DAG;
4403 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
4404 DebugLoc DL = N->getDebugLoc();
4405 // 1) or (and A, mask), val => ARMbfi A, val, mask
4406 // iff (val & mask) == val
4408 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
4409 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2)
4410 // && CountPopulation_32(mask) == CountPopulation_32(~mask2)
4411 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2)
4412 // && CountPopulation_32(mask) == CountPopulation_32(~mask2)
4413 // (i.e., copy a bitfield value into another bitfield of the same width)
4414 if (N0.getOpcode() != ISD::AND)
4417 EVT VT = N->getValueType(0);
4422 // The value and the mask need to be constants so we can verify this is
4423 // actually a bitfield set. If the mask is 0xffff, we can do better
4424 // via a movt instruction, so don't use BFI in that case.
4425 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
4428 unsigned Mask = C->getZExtValue();
4432 // Case (1): or (and A, mask), val => ARMbfi A, val, mask
4433 if ((C = dyn_cast<ConstantSDNode>(N1))) {
4434 unsigned Val = C->getZExtValue();
4435 if (!ARM::isBitFieldInvertedMask(Mask) || (Val & ~Mask) != Val)
4437 Val >>= CountTrailingZeros_32(~Mask);
4439 Res = DAG.getNode(ARMISD::BFI, DL, VT, N0.getOperand(0),
4440 DAG.getConstant(Val, MVT::i32),
4441 DAG.getConstant(Mask, MVT::i32));
4443 // Do not add new nodes to DAG combiner worklist.
4444 DCI.CombineTo(N, Res, false);
4445 } else if (N1.getOpcode() == ISD::AND) {
4446 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
4447 C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
4450 unsigned Mask2 = C->getZExtValue();
4452 if (ARM::isBitFieldInvertedMask(Mask) &&
4453 ARM::isBitFieldInvertedMask(~Mask2) &&
4454 (CountPopulation_32(Mask) == CountPopulation_32(~Mask2))) {
4455 // The pack halfword instruction works better for masks that fit it,
4456 // so use that when it's available.
4457 if (Subtarget->hasT2ExtractPack() &&
4458 (Mask == 0xffff || Mask == 0xffff0000))
4461 unsigned lsb = CountTrailingZeros_32(Mask2);
4462 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
4463 DAG.getConstant(lsb, MVT::i32));
4464 Res = DAG.getNode(ARMISD::BFI, DL, VT, N0.getOperand(0), Res,
4465 DAG.getConstant(Mask, MVT::i32));
4466 // Do not add new nodes to DAG combiner worklist.
4467 DCI.CombineTo(N, Res, false);
4468 } else if (ARM::isBitFieldInvertedMask(~Mask) &&
4469 ARM::isBitFieldInvertedMask(Mask2) &&
4470 (CountPopulation_32(~Mask) == CountPopulation_32(Mask2))) {
4471 // The pack halfword instruction works better for masks that fit it,
4472 // so use that when it's available.
4473 if (Subtarget->hasT2ExtractPack() &&
4474 (Mask2 == 0xffff || Mask2 == 0xffff0000))
4477 unsigned lsb = CountTrailingZeros_32(Mask);
4478 Res = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0),
4479 DAG.getConstant(lsb, MVT::i32));
4480 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
4481 DAG.getConstant(Mask2, MVT::i32));
4482 // Do not add new nodes to DAG combiner worklist.
4483 DCI.CombineTo(N, Res, false);
4490 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
4491 /// ARMISD::VMOVRRD.
4492 static SDValue PerformVMOVRRDCombine(SDNode *N,
4493 TargetLowering::DAGCombinerInfo &DCI) {
4494 // vmovrrd(vmovdrr x, y) -> x,y
4495 SDValue InDouble = N->getOperand(0);
4496 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
4497 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
4501 /// PerformVMOVDRRCombine - Target-specific dag combine xforms for
4502 /// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands.
4503 static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) {
4504 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X)
4505 SDValue Op0 = N->getOperand(0);
4506 SDValue Op1 = N->getOperand(1);
4507 if (Op0.getOpcode() == ISD::BIT_CONVERT)
4508 Op0 = Op0.getOperand(0);
4509 if (Op1.getOpcode() == ISD::BIT_CONVERT)
4510 Op1 = Op1.getOperand(0);
4511 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
4512 Op0.getNode() == Op1.getNode() &&
4513 Op0.getResNo() == 0 && Op1.getResNo() == 1)
4514 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
4515 N->getValueType(0), Op0.getOperand(0));
4519 /// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for
4520 /// ISD::BUILD_VECTOR.
4521 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG) {
4522 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X):
4523 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value
4524 // into a pair of GPRs, which is fine when the value is used as a scalar,
4525 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD.
4526 if (N->getNumOperands() == 2)
4527 return PerformVMOVDRRCombine(N, DAG);
4532 /// PerformVDUPLANECombine - Target-specific dag combine xforms for
4533 /// ARMISD::VDUPLANE.
4534 static SDValue PerformVDUPLANECombine(SDNode *N, SelectionDAG &DAG) {
4535 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
4537 SDValue Op = N->getOperand(0);
4538 EVT VT = N->getValueType(0);
4540 // Ignore bit_converts.
4541 while (Op.getOpcode() == ISD::BIT_CONVERT)
4542 Op = Op.getOperand(0);
4543 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
4546 // Make sure the VMOV element size is not bigger than the VDUPLANE elements.
4547 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits();
4548 // The canonical VMOV for a zero vector uses a 32-bit element size.
4549 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4551 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
4553 if (EltSize > VT.getVectorElementType().getSizeInBits())
4556 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
4559 /// getVShiftImm - Check if this is a valid build_vector for the immediate
4560 /// operand of a vector shift operation, where all the elements of the
4561 /// build_vector must have the same constant integer value.
4562 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
4563 // Ignore bit_converts.
4564 while (Op.getOpcode() == ISD::BIT_CONVERT)
4565 Op = Op.getOperand(0);
4566 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
4567 APInt SplatBits, SplatUndef;
4568 unsigned SplatBitSize;
4570 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
4571 HasAnyUndefs, ElementBits) ||
4572 SplatBitSize > ElementBits)
4574 Cnt = SplatBits.getSExtValue();
4578 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
4579 /// operand of a vector shift left operation. That value must be in the range:
4580 /// 0 <= Value < ElementBits for a left shift; or
4581 /// 0 <= Value <= ElementBits for a long left shift.
4582 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
4583 assert(VT.isVector() && "vector shift count is not a vector type");
4584 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
4585 if (! getVShiftImm(Op, ElementBits, Cnt))
4587 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
4590 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
4591 /// operand of a vector shift right operation. For a shift opcode, the value
4592 /// is positive, but for an intrinsic the value count must be negative. The
4593 /// absolute value must be in the range:
4594 /// 1 <= |Value| <= ElementBits for a right shift; or
4595 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
4596 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
4598 assert(VT.isVector() && "vector shift count is not a vector type");
4599 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
4600 if (! getVShiftImm(Op, ElementBits, Cnt))
4604 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
4607 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
4608 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
4609 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
4612 // Don't do anything for most intrinsics.
4615 // Vector shifts: check for immediate versions and lower them.
4616 // Note: This is done during DAG combining instead of DAG legalizing because
4617 // the build_vectors for 64-bit vector element shift counts are generally
4618 // not legal, and it is hard to see their values after they get legalized to
4619 // loads from a constant pool.
4620 case Intrinsic::arm_neon_vshifts:
4621 case Intrinsic::arm_neon_vshiftu:
4622 case Intrinsic::arm_neon_vshiftls:
4623 case Intrinsic::arm_neon_vshiftlu:
4624 case Intrinsic::arm_neon_vshiftn:
4625 case Intrinsic::arm_neon_vrshifts:
4626 case Intrinsic::arm_neon_vrshiftu:
4627 case Intrinsic::arm_neon_vrshiftn:
4628 case Intrinsic::arm_neon_vqshifts:
4629 case Intrinsic::arm_neon_vqshiftu:
4630 case Intrinsic::arm_neon_vqshiftsu:
4631 case Intrinsic::arm_neon_vqshiftns:
4632 case Intrinsic::arm_neon_vqshiftnu:
4633 case Intrinsic::arm_neon_vqshiftnsu:
4634 case Intrinsic::arm_neon_vqrshiftns:
4635 case Intrinsic::arm_neon_vqrshiftnu:
4636 case Intrinsic::arm_neon_vqrshiftnsu: {
4637 EVT VT = N->getOperand(1).getValueType();
4639 unsigned VShiftOpc = 0;
4642 case Intrinsic::arm_neon_vshifts:
4643 case Intrinsic::arm_neon_vshiftu:
4644 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
4645 VShiftOpc = ARMISD::VSHL;
4648 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
4649 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
4650 ARMISD::VSHRs : ARMISD::VSHRu);
4655 case Intrinsic::arm_neon_vshiftls:
4656 case Intrinsic::arm_neon_vshiftlu:
4657 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
4659 llvm_unreachable("invalid shift count for vshll intrinsic");
4661 case Intrinsic::arm_neon_vrshifts:
4662 case Intrinsic::arm_neon_vrshiftu:
4663 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
4667 case Intrinsic::arm_neon_vqshifts:
4668 case Intrinsic::arm_neon_vqshiftu:
4669 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
4673 case Intrinsic::arm_neon_vqshiftsu:
4674 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
4676 llvm_unreachable("invalid shift count for vqshlu intrinsic");
4678 case Intrinsic::arm_neon_vshiftn:
4679 case Intrinsic::arm_neon_vrshiftn:
4680 case Intrinsic::arm_neon_vqshiftns:
4681 case Intrinsic::arm_neon_vqshiftnu:
4682 case Intrinsic::arm_neon_vqshiftnsu:
4683 case Intrinsic::arm_neon_vqrshiftns:
4684 case Intrinsic::arm_neon_vqrshiftnu:
4685 case Intrinsic::arm_neon_vqrshiftnsu:
4686 // Narrowing shifts require an immediate right shift.
4687 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
4689 llvm_unreachable("invalid shift count for narrowing vector shift "
4693 llvm_unreachable("unhandled vector shift");
4697 case Intrinsic::arm_neon_vshifts:
4698 case Intrinsic::arm_neon_vshiftu:
4699 // Opcode already set above.
4701 case Intrinsic::arm_neon_vshiftls:
4702 case Intrinsic::arm_neon_vshiftlu:
4703 if (Cnt == VT.getVectorElementType().getSizeInBits())
4704 VShiftOpc = ARMISD::VSHLLi;
4706 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
4707 ARMISD::VSHLLs : ARMISD::VSHLLu);
4709 case Intrinsic::arm_neon_vshiftn:
4710 VShiftOpc = ARMISD::VSHRN; break;
4711 case Intrinsic::arm_neon_vrshifts:
4712 VShiftOpc = ARMISD::VRSHRs; break;
4713 case Intrinsic::arm_neon_vrshiftu:
4714 VShiftOpc = ARMISD::VRSHRu; break;
4715 case Intrinsic::arm_neon_vrshiftn:
4716 VShiftOpc = ARMISD::VRSHRN; break;
4717 case Intrinsic::arm_neon_vqshifts:
4718 VShiftOpc = ARMISD::VQSHLs; break;
4719 case Intrinsic::arm_neon_vqshiftu:
4720 VShiftOpc = ARMISD::VQSHLu; break;
4721 case Intrinsic::arm_neon_vqshiftsu:
4722 VShiftOpc = ARMISD::VQSHLsu; break;
4723 case Intrinsic::arm_neon_vqshiftns:
4724 VShiftOpc = ARMISD::VQSHRNs; break;
4725 case Intrinsic::arm_neon_vqshiftnu:
4726 VShiftOpc = ARMISD::VQSHRNu; break;
4727 case Intrinsic::arm_neon_vqshiftnsu:
4728 VShiftOpc = ARMISD::VQSHRNsu; break;
4729 case Intrinsic::arm_neon_vqrshiftns:
4730 VShiftOpc = ARMISD::VQRSHRNs; break;
4731 case Intrinsic::arm_neon_vqrshiftnu:
4732 VShiftOpc = ARMISD::VQRSHRNu; break;
4733 case Intrinsic::arm_neon_vqrshiftnsu:
4734 VShiftOpc = ARMISD::VQRSHRNsu; break;
4737 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
4738 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
4741 case Intrinsic::arm_neon_vshiftins: {
4742 EVT VT = N->getOperand(1).getValueType();
4744 unsigned VShiftOpc = 0;
4746 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
4747 VShiftOpc = ARMISD::VSLI;
4748 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
4749 VShiftOpc = ARMISD::VSRI;
4751 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
4754 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
4755 N->getOperand(1), N->getOperand(2),
4756 DAG.getConstant(Cnt, MVT::i32));
4759 case Intrinsic::arm_neon_vqrshifts:
4760 case Intrinsic::arm_neon_vqrshiftu:
4761 // No immediate versions of these to check for.
4768 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
4769 /// lowers them. As with the vector shift intrinsics, this is done during DAG
4770 /// combining instead of DAG legalizing because the build_vectors for 64-bit
4771 /// vector element shift counts are generally not legal, and it is hard to see
4772 /// their values after they get legalized to loads from a constant pool.
4773 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
4774 const ARMSubtarget *ST) {
4775 EVT VT = N->getValueType(0);
4777 // Nothing to be done for scalar shifts.
4778 if (! VT.isVector())
4781 assert(ST->hasNEON() && "unexpected vector shift");
4784 switch (N->getOpcode()) {
4785 default: llvm_unreachable("unexpected shift opcode");
4788 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
4789 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
4790 DAG.getConstant(Cnt, MVT::i32));
4795 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
4796 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
4797 ARMISD::VSHRs : ARMISD::VSHRu);
4798 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
4799 DAG.getConstant(Cnt, MVT::i32));
4805 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
4806 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
4807 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
4808 const ARMSubtarget *ST) {
4809 SDValue N0 = N->getOperand(0);
4811 // Check for sign- and zero-extensions of vector extract operations of 8-
4812 // and 16-bit vector elements. NEON supports these directly. They are
4813 // handled during DAG combining because type legalization will promote them
4814 // to 32-bit types and it is messy to recognize the operations after that.
4815 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
4816 SDValue Vec = N0.getOperand(0);
4817 SDValue Lane = N0.getOperand(1);
4818 EVT VT = N->getValueType(0);
4819 EVT EltVT = N0.getValueType();
4820 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4822 if (VT == MVT::i32 &&
4823 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
4824 TLI.isTypeLegal(Vec.getValueType())) {
4827 switch (N->getOpcode()) {
4828 default: llvm_unreachable("unexpected opcode");
4829 case ISD::SIGN_EXTEND:
4830 Opc = ARMISD::VGETLANEs;
4832 case ISD::ZERO_EXTEND:
4833 case ISD::ANY_EXTEND:
4834 Opc = ARMISD::VGETLANEu;
4837 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
4844 /// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
4845 /// to match f32 max/min patterns to use NEON vmax/vmin instructions.
4846 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
4847 const ARMSubtarget *ST) {
4848 // If the target supports NEON, try to use vmax/vmin instructions for f32
4849 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set,
4850 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
4851 // a NaN; only do the transformation when it matches that behavior.
4853 // For now only do this when using NEON for FP operations; if using VFP, it
4854 // is not obvious that the benefit outweighs the cost of switching to the
4856 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
4857 N->getValueType(0) != MVT::f32)
4860 SDValue CondLHS = N->getOperand(0);
4861 SDValue CondRHS = N->getOperand(1);
4862 SDValue LHS = N->getOperand(2);
4863 SDValue RHS = N->getOperand(3);
4864 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
4866 unsigned Opcode = 0;
4868 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
4869 IsReversed = false; // x CC y ? x : y
4870 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
4871 IsReversed = true ; // x CC y ? y : x
4885 // If LHS is NaN, an ordered comparison will be false and the result will
4886 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
4887 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
4888 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
4889 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
4891 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
4892 // will return -0, so vmin can only be used for unsafe math or if one of
4893 // the operands is known to be nonzero.
4894 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
4896 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
4898 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
4907 // If LHS is NaN, an ordered comparison will be false and the result will
4908 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
4909 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
4910 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
4911 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
4913 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
4914 // will return +0, so vmax can only be used for unsafe math or if one of
4915 // the operands is known to be nonzero.
4916 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
4918 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
4920 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
4926 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS);
4929 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
4930 DAGCombinerInfo &DCI) const {
4931 switch (N->getOpcode()) {
4933 case ISD::ADD: return PerformADDCombine(N, DCI);
4934 case ISD::SUB: return PerformSUBCombine(N, DCI);
4935 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
4936 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
4937 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
4938 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
4939 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI.DAG);
4940 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI.DAG);
4941 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
4944 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
4945 case ISD::SIGN_EXTEND:
4946 case ISD::ZERO_EXTEND:
4947 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
4948 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
4953 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
4954 if (!Subtarget->allowsUnalignedMem())
4957 switch (VT.getSimpleVT().SimpleTy) {
4964 // FIXME: VLD1 etc with standard alignment is legal.
4968 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
4973 switch (VT.getSimpleVT().SimpleTy) {
4974 default: return false;
4989 if ((V & (Scale - 1)) != 0)
4992 return V == (V & ((1LL << 5) - 1));
4995 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
4996 const ARMSubtarget *Subtarget) {
5003 switch (VT.getSimpleVT().SimpleTy) {
5004 default: return false;
5009 // + imm12 or - imm8
5011 return V == (V & ((1LL << 8) - 1));
5012 return V == (V & ((1LL << 12) - 1));
5015 // Same as ARM mode. FIXME: NEON?
5016 if (!Subtarget->hasVFP2())
5021 return V == (V & ((1LL << 8) - 1));
5025 /// isLegalAddressImmediate - Return true if the integer value can be used
5026 /// as the offset of the target addressing mode for load / store of the
5028 static bool isLegalAddressImmediate(int64_t V, EVT VT,
5029 const ARMSubtarget *Subtarget) {
5036 if (Subtarget->isThumb1Only())
5037 return isLegalT1AddressImmediate(V, VT);
5038 else if (Subtarget->isThumb2())
5039 return isLegalT2AddressImmediate(V, VT, Subtarget);
5044 switch (VT.getSimpleVT().SimpleTy) {
5045 default: return false;
5050 return V == (V & ((1LL << 12) - 1));
5053 return V == (V & ((1LL << 8) - 1));
5056 if (!Subtarget->hasVFP2()) // FIXME: NEON?
5061 return V == (V & ((1LL << 8) - 1));
5065 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
5067 int Scale = AM.Scale;
5071 switch (VT.getSimpleVT().SimpleTy) {
5072 default: return false;
5081 return Scale == 2 || Scale == 4 || Scale == 8;
5084 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
5088 // Note, we allow "void" uses (basically, uses that aren't loads or
5089 // stores), because arm allows folding a scale into many arithmetic
5090 // operations. This should be made more precise and revisited later.
5092 // Allow r << imm, but the imm has to be a multiple of two.
5093 if (Scale & 1) return false;
5094 return isPowerOf2_32(Scale);
5098 /// isLegalAddressingMode - Return true if the addressing mode represented
5099 /// by AM is legal for this target, for a load/store of the specified type.
5100 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
5101 const Type *Ty) const {
5102 EVT VT = getValueType(Ty, true);
5103 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
5106 // Can never fold addr of global into load/store.
5111 case 0: // no scale reg, must be "r+i" or "r", or "i".
5114 if (Subtarget->isThumb1Only())
5118 // ARM doesn't support any R+R*scale+imm addr modes.
5125 if (Subtarget->isThumb2())
5126 return isLegalT2ScaledAddressingMode(AM, VT);
5128 int Scale = AM.Scale;
5129 switch (VT.getSimpleVT().SimpleTy) {
5130 default: return false;
5134 if (Scale < 0) Scale = -Scale;
5138 return isPowerOf2_32(Scale & ~1);
5142 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
5147 // Note, we allow "void" uses (basically, uses that aren't loads or
5148 // stores), because arm allows folding a scale into many arithmetic
5149 // operations. This should be made more precise and revisited later.
5151 // Allow r << imm, but the imm has to be a multiple of two.
5152 if (Scale & 1) return false;
5153 return isPowerOf2_32(Scale);
5160 /// isLegalICmpImmediate - Return true if the specified immediate is legal
5161 /// icmp immediate, that is the target has icmp instructions which can compare
5162 /// a register against the immediate without having to materialize the
5163 /// immediate into a register.
5164 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
5165 if (!Subtarget->isThumb())
5166 return ARM_AM::getSOImmVal(Imm) != -1;
5167 if (Subtarget->isThumb2())
5168 return ARM_AM::getT2SOImmVal(Imm) != -1;
5169 return Imm >= 0 && Imm <= 255;
5172 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
5173 bool isSEXTLoad, SDValue &Base,
5174 SDValue &Offset, bool &isInc,
5175 SelectionDAG &DAG) {
5176 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
5179 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
5181 Base = Ptr->getOperand(0);
5182 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
5183 int RHSC = (int)RHS->getZExtValue();
5184 if (RHSC < 0 && RHSC > -256) {
5185 assert(Ptr->getOpcode() == ISD::ADD);
5187 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
5191 isInc = (Ptr->getOpcode() == ISD::ADD);
5192 Offset = Ptr->getOperand(1);
5194 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
5196 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
5197 int RHSC = (int)RHS->getZExtValue();
5198 if (RHSC < 0 && RHSC > -0x1000) {
5199 assert(Ptr->getOpcode() == ISD::ADD);
5201 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
5202 Base = Ptr->getOperand(0);
5207 if (Ptr->getOpcode() == ISD::ADD) {
5209 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
5210 if (ShOpcVal != ARM_AM::no_shift) {
5211 Base = Ptr->getOperand(1);
5212 Offset = Ptr->getOperand(0);
5214 Base = Ptr->getOperand(0);
5215 Offset = Ptr->getOperand(1);
5220 isInc = (Ptr->getOpcode() == ISD::ADD);
5221 Base = Ptr->getOperand(0);
5222 Offset = Ptr->getOperand(1);
5226 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
5230 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
5231 bool isSEXTLoad, SDValue &Base,
5232 SDValue &Offset, bool &isInc,
5233 SelectionDAG &DAG) {
5234 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
5237 Base = Ptr->getOperand(0);
5238 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
5239 int RHSC = (int)RHS->getZExtValue();
5240 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
5241 assert(Ptr->getOpcode() == ISD::ADD);
5243 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
5245 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
5246 isInc = Ptr->getOpcode() == ISD::ADD;
5247 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
5255 /// getPreIndexedAddressParts - returns true by value, base pointer and
5256 /// offset pointer and addressing mode by reference if the node's address
5257 /// can be legally represented as pre-indexed load / store address.
5259 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
5261 ISD::MemIndexedMode &AM,
5262 SelectionDAG &DAG) const {
5263 if (Subtarget->isThumb1Only())
5268 bool isSEXTLoad = false;
5269 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5270 Ptr = LD->getBasePtr();
5271 VT = LD->getMemoryVT();
5272 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
5273 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5274 Ptr = ST->getBasePtr();
5275 VT = ST->getMemoryVT();
5280 bool isLegal = false;
5281 if (Subtarget->isThumb2())
5282 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
5283 Offset, isInc, DAG);
5285 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
5286 Offset, isInc, DAG);
5290 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
5294 /// getPostIndexedAddressParts - returns true by value, base pointer and
5295 /// offset pointer and addressing mode by reference if this node can be
5296 /// combined with a load / store to form a post-indexed load / store.
5297 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
5300 ISD::MemIndexedMode &AM,
5301 SelectionDAG &DAG) const {
5302 if (Subtarget->isThumb1Only())
5307 bool isSEXTLoad = false;
5308 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5309 VT = LD->getMemoryVT();
5310 Ptr = LD->getBasePtr();
5311 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
5312 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5313 VT = ST->getMemoryVT();
5314 Ptr = ST->getBasePtr();
5319 bool isLegal = false;
5320 if (Subtarget->isThumb2())
5321 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
5324 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
5330 // Swap base ptr and offset to catch more post-index load / store when
5331 // it's legal. In Thumb2 mode, offset must be an immediate.
5332 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
5333 !Subtarget->isThumb2())
5334 std::swap(Base, Offset);
5336 // Post-indexed load / store update the base pointer.
5341 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
5345 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
5349 const SelectionDAG &DAG,
5350 unsigned Depth) const {
5351 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
5352 switch (Op.getOpcode()) {
5354 case ARMISD::CMOV: {
5355 // Bits are known zero/one if known on the LHS and RHS.
5356 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
5357 if (KnownZero == 0 && KnownOne == 0) return;
5359 APInt KnownZeroRHS, KnownOneRHS;
5360 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
5361 KnownZeroRHS, KnownOneRHS, Depth+1);
5362 KnownZero &= KnownZeroRHS;
5363 KnownOne &= KnownOneRHS;
5369 //===----------------------------------------------------------------------===//
5370 // ARM Inline Assembly Support
5371 //===----------------------------------------------------------------------===//
5373 /// getConstraintType - Given a constraint letter, return the type of
5374 /// constraint it is for this target.
5375 ARMTargetLowering::ConstraintType
5376 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
5377 if (Constraint.size() == 1) {
5378 switch (Constraint[0]) {
5380 case 'l': return C_RegisterClass;
5381 case 'w': return C_RegisterClass;
5384 return TargetLowering::getConstraintType(Constraint);
5387 std::pair<unsigned, const TargetRegisterClass*>
5388 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
5390 if (Constraint.size() == 1) {
5391 // GCC ARM Constraint Letters
5392 switch (Constraint[0]) {
5394 if (Subtarget->isThumb())
5395 return std::make_pair(0U, ARM::tGPRRegisterClass);
5397 return std::make_pair(0U, ARM::GPRRegisterClass);
5399 return std::make_pair(0U, ARM::GPRRegisterClass);
5402 return std::make_pair(0U, ARM::SPRRegisterClass);
5403 if (VT.getSizeInBits() == 64)
5404 return std::make_pair(0U, ARM::DPRRegisterClass);
5405 if (VT.getSizeInBits() == 128)
5406 return std::make_pair(0U, ARM::QPRRegisterClass);
5410 if (StringRef("{cc}").equals_lower(Constraint))
5411 return std::make_pair(unsigned(ARM::CPSR), ARM::CCRRegisterClass);
5413 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
5416 std::vector<unsigned> ARMTargetLowering::
5417 getRegClassForInlineAsmConstraint(const std::string &Constraint,
5419 if (Constraint.size() != 1)
5420 return std::vector<unsigned>();
5422 switch (Constraint[0]) { // GCC ARM Constraint Letters
5425 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
5426 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
5429 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
5430 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
5431 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
5432 ARM::R12, ARM::LR, 0);
5435 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
5436 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
5437 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
5438 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
5439 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
5440 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
5441 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
5442 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
5443 if (VT.getSizeInBits() == 64)
5444 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
5445 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
5446 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
5447 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
5448 if (VT.getSizeInBits() == 128)
5449 return make_vector<unsigned>(ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
5450 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 0);
5454 return std::vector<unsigned>();
5457 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
5458 /// vector. If it is invalid, don't add anything to Ops.
5459 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
5461 std::vector<SDValue>&Ops,
5462 SelectionDAG &DAG) const {
5463 SDValue Result(0, 0);
5465 switch (Constraint) {
5467 case 'I': case 'J': case 'K': case 'L':
5468 case 'M': case 'N': case 'O':
5469 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
5473 int64_t CVal64 = C->getSExtValue();
5474 int CVal = (int) CVal64;
5475 // None of these constraints allow values larger than 32 bits. Check
5476 // that the value fits in an int.
5480 switch (Constraint) {
5482 if (Subtarget->isThumb1Only()) {
5483 // This must be a constant between 0 and 255, for ADD
5485 if (CVal >= 0 && CVal <= 255)
5487 } else if (Subtarget->isThumb2()) {
5488 // A constant that can be used as an immediate value in a
5489 // data-processing instruction.
5490 if (ARM_AM::getT2SOImmVal(CVal) != -1)
5493 // A constant that can be used as an immediate value in a
5494 // data-processing instruction.
5495 if (ARM_AM::getSOImmVal(CVal) != -1)
5501 if (Subtarget->isThumb()) { // FIXME thumb2
5502 // This must be a constant between -255 and -1, for negated ADD
5503 // immediates. This can be used in GCC with an "n" modifier that
5504 // prints the negated value, for use with SUB instructions. It is
5505 // not useful otherwise but is implemented for compatibility.
5506 if (CVal >= -255 && CVal <= -1)
5509 // This must be a constant between -4095 and 4095. It is not clear
5510 // what this constraint is intended for. Implemented for
5511 // compatibility with GCC.
5512 if (CVal >= -4095 && CVal <= 4095)
5518 if (Subtarget->isThumb1Only()) {
5519 // A 32-bit value where only one byte has a nonzero value. Exclude
5520 // zero to match GCC. This constraint is used by GCC internally for
5521 // constants that can be loaded with a move/shift combination.
5522 // It is not useful otherwise but is implemented for compatibility.
5523 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
5525 } else if (Subtarget->isThumb2()) {
5526 // A constant whose bitwise inverse can be used as an immediate
5527 // value in a data-processing instruction. This can be used in GCC
5528 // with a "B" modifier that prints the inverted value, for use with
5529 // BIC and MVN instructions. It is not useful otherwise but is
5530 // implemented for compatibility.
5531 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
5534 // A constant whose bitwise inverse can be used as an immediate
5535 // value in a data-processing instruction. This can be used in GCC
5536 // with a "B" modifier that prints the inverted value, for use with
5537 // BIC and MVN instructions. It is not useful otherwise but is
5538 // implemented for compatibility.
5539 if (ARM_AM::getSOImmVal(~CVal) != -1)
5545 if (Subtarget->isThumb1Only()) {
5546 // This must be a constant between -7 and 7,
5547 // for 3-operand ADD/SUB immediate instructions.
5548 if (CVal >= -7 && CVal < 7)
5550 } else if (Subtarget->isThumb2()) {
5551 // A constant whose negation can be used as an immediate value in a
5552 // data-processing instruction. This can be used in GCC with an "n"
5553 // modifier that prints the negated value, for use with SUB
5554 // instructions. It is not useful otherwise but is implemented for
5556 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
5559 // A constant whose negation can be used as an immediate value in a
5560 // data-processing instruction. This can be used in GCC with an "n"
5561 // modifier that prints the negated value, for use with SUB
5562 // instructions. It is not useful otherwise but is implemented for
5564 if (ARM_AM::getSOImmVal(-CVal) != -1)
5570 if (Subtarget->isThumb()) { // FIXME thumb2
5571 // This must be a multiple of 4 between 0 and 1020, for
5572 // ADD sp + immediate.
5573 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
5576 // A power of two or a constant between 0 and 32. This is used in
5577 // GCC for the shift amount on shifted register operands, but it is
5578 // useful in general for any shift amounts.
5579 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
5585 if (Subtarget->isThumb()) { // FIXME thumb2
5586 // This must be a constant between 0 and 31, for shift amounts.
5587 if (CVal >= 0 && CVal <= 31)
5593 if (Subtarget->isThumb()) { // FIXME thumb2
5594 // This must be a multiple of 4 between -508 and 508, for
5595 // ADD/SUB sp = sp + immediate.
5596 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
5601 Result = DAG.getTargetConstant(CVal, Op.getValueType());
5605 if (Result.getNode()) {
5606 Ops.push_back(Result);
5609 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
5613 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
5614 // The ARM target isn't yet aware of offsets.
5618 int ARM::getVFPf32Imm(const APFloat &FPImm) {
5619 APInt Imm = FPImm.bitcastToAPInt();
5620 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
5621 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127
5622 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits
5624 // We can handle 4 bits of mantissa.
5625 // mantissa = (16+UInt(e:f:g:h))/16.
5626 if (Mantissa & 0x7ffff)
5629 if ((Mantissa & 0xf) != Mantissa)
5632 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
5633 if (Exp < -3 || Exp > 4)
5635 Exp = ((Exp+3) & 0x7) ^ 4;
5637 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
5640 int ARM::getVFPf64Imm(const APFloat &FPImm) {
5641 APInt Imm = FPImm.bitcastToAPInt();
5642 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
5643 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
5644 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffLL;
5646 // We can handle 4 bits of mantissa.
5647 // mantissa = (16+UInt(e:f:g:h))/16.
5648 if (Mantissa & 0xffffffffffffLL)
5651 if ((Mantissa & 0xf) != Mantissa)
5654 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
5655 if (Exp < -3 || Exp > 4)
5657 Exp = ((Exp+3) & 0x7) ^ 4;
5659 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
5662 bool ARM::isBitFieldInvertedMask(unsigned v) {
5663 if (v == 0xffffffff)
5665 // there can be 1's on either or both "outsides", all the "inside"
5667 unsigned int lsb = 0, msb = 31;
5668 while (v & (1 << msb)) --msb;
5669 while (v & (1 << lsb)) ++lsb;
5670 for (unsigned int i = lsb; i <= msb; ++i) {
5677 /// isFPImmLegal - Returns true if the target can instruction select the
5678 /// specified FP immediate natively. If false, the legalizer will
5679 /// materialize the FP immediate as a load from a constant pool.
5680 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
5681 if (!Subtarget->hasVFP3())
5684 return ARM::getVFPf32Imm(Imm) != -1;
5686 return ARM::getVFPf64Imm(Imm) != -1;
5690 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
5691 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
5692 /// specified in the intrinsic calls.
5693 bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
5695 unsigned Intrinsic) const {
5696 switch (Intrinsic) {
5697 case Intrinsic::arm_neon_vld1:
5698 case Intrinsic::arm_neon_vld2:
5699 case Intrinsic::arm_neon_vld3:
5700 case Intrinsic::arm_neon_vld4:
5701 case Intrinsic::arm_neon_vld2lane:
5702 case Intrinsic::arm_neon_vld3lane:
5703 case Intrinsic::arm_neon_vld4lane: {
5704 Info.opc = ISD::INTRINSIC_W_CHAIN;
5705 // Conservatively set memVT to the entire set of vectors loaded.
5706 uint64_t NumElts = getTargetData()->getTypeAllocSize(I.getType()) / 8;
5707 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
5708 Info.ptrVal = I.getArgOperand(0);
5710 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
5711 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
5712 Info.vol = false; // volatile loads with NEON intrinsics not supported
5713 Info.readMem = true;
5714 Info.writeMem = false;
5717 case Intrinsic::arm_neon_vst1:
5718 case Intrinsic::arm_neon_vst2:
5719 case Intrinsic::arm_neon_vst3:
5720 case Intrinsic::arm_neon_vst4:
5721 case Intrinsic::arm_neon_vst2lane:
5722 case Intrinsic::arm_neon_vst3lane:
5723 case Intrinsic::arm_neon_vst4lane: {
5724 Info.opc = ISD::INTRINSIC_VOID;
5725 // Conservatively set memVT to the entire set of vectors stored.
5726 unsigned NumElts = 0;
5727 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
5728 const Type *ArgTy = I.getArgOperand(ArgI)->getType();
5729 if (!ArgTy->isVectorTy())
5731 NumElts += getTargetData()->getTypeAllocSize(ArgTy) / 8;
5733 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
5734 Info.ptrVal = I.getArgOperand(0);
5736 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
5737 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
5738 Info.vol = false; // volatile stores with NEON intrinsics not supported
5739 Info.readMem = false;
5740 Info.writeMem = true;