1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "ARMAddressingModes.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMISelLowering.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMRegisterInfo.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/Constants.h"
25 #include "llvm/Instruction.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/GlobalValue.h"
28 #include "llvm/CodeGen/MachineBasicBlock.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/SelectionDAG.h"
34 #include "llvm/Target/TargetOptions.h"
35 #include "llvm/ADT/VectorExtras.h"
36 #include "llvm/Support/MathExtras.h"
39 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
40 : TargetLowering(TM), ARMPCLabelIndex(0) {
41 Subtarget = &TM.getSubtarget<ARMSubtarget>();
43 if (Subtarget->isTargetDarwin()) {
45 setLibcallName(RTLIB::UINTTOFP_I64_F32, NULL);
46 setLibcallName(RTLIB::UINTTOFP_I64_F64, NULL);
48 // Uses VFP for Thumb libfuncs if available.
49 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
50 // Single-precision floating-point arithmetic.
51 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
52 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
53 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
54 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
56 // Double-precision floating-point arithmetic.
57 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
58 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
59 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
60 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
62 // Single-precision comparisons.
63 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
64 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
65 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
66 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
67 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
68 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
69 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
70 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
72 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
73 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
74 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
75 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
76 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
77 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
78 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
79 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
81 // Double-precision comparisons.
82 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
83 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
84 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
85 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
86 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
87 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
88 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
89 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
91 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
92 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
93 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
94 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
95 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
96 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
97 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
98 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
100 // Floating-point to integer conversions.
101 // i64 conversions are done via library routines even when generating VFP
102 // instructions, so use the same ones.
103 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
104 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
105 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
106 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
108 // Conversions between floating types.
109 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
110 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
112 // Integer to floating-point conversions.
113 // i64 conversions are done via library routines even when generating VFP
114 // instructions, so use the same ones.
115 // FIXME: There appears to be some naming inconsistency in ARM libgcc: e.g.
116 // __floatunsidf vs. __floatunssidfvfp.
117 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
118 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
119 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
120 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
124 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
125 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) {
126 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
127 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
129 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
131 computeRegisterProperties();
133 // ARM does not have f32 extending load.
134 setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
136 // ARM does not have i1 sign extending load.
137 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
139 // ARM supports all 4 flavors of integer indexed load / store.
140 for (unsigned im = (unsigned)ISD::PRE_INC;
141 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
142 setIndexedLoadAction(im, MVT::i1, Legal);
143 setIndexedLoadAction(im, MVT::i8, Legal);
144 setIndexedLoadAction(im, MVT::i16, Legal);
145 setIndexedLoadAction(im, MVT::i32, Legal);
146 setIndexedStoreAction(im, MVT::i1, Legal);
147 setIndexedStoreAction(im, MVT::i8, Legal);
148 setIndexedStoreAction(im, MVT::i16, Legal);
149 setIndexedStoreAction(im, MVT::i32, Legal);
152 // i64 operation support.
153 if (Subtarget->isThumb()) {
154 setOperationAction(ISD::MUL, MVT::i64, Expand);
155 setOperationAction(ISD::MULHU, MVT::i32, Expand);
156 setOperationAction(ISD::MULHS, MVT::i32, Expand);
157 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
158 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
160 setOperationAction(ISD::MUL, MVT::i64, Expand);
161 setOperationAction(ISD::MULHU, MVT::i32, Expand);
162 if (!Subtarget->hasV6Ops())
163 setOperationAction(ISD::MULHS, MVT::i32, Expand);
165 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
166 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
167 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
168 setOperationAction(ISD::SRL, MVT::i64, Custom);
169 setOperationAction(ISD::SRA, MVT::i64, Custom);
171 // ARM does not have ROTL.
172 setOperationAction(ISD::ROTL, MVT::i32, Expand);
173 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
174 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
175 if (!Subtarget->hasV5TOps() || Subtarget->isThumb())
176 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
178 // Only ARMv6 has BSWAP.
179 if (!Subtarget->hasV6Ops())
180 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
182 // These are expanded into libcalls.
183 setOperationAction(ISD::SDIV, MVT::i32, Expand);
184 setOperationAction(ISD::UDIV, MVT::i32, Expand);
185 setOperationAction(ISD::SREM, MVT::i32, Expand);
186 setOperationAction(ISD::UREM, MVT::i32, Expand);
187 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
188 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
190 // Support label based line numbers.
191 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
192 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
194 setOperationAction(ISD::RET, MVT::Other, Custom);
195 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
196 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
197 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
198 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
200 // Use the default implementation.
201 setOperationAction(ISD::VASTART , MVT::Other, Custom);
202 setOperationAction(ISD::VAARG , MVT::Other, Expand);
203 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
204 setOperationAction(ISD::VAEND , MVT::Other, Expand);
205 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
206 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
207 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
208 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
210 if (!Subtarget->hasV6Ops()) {
211 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
212 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
214 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
216 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb())
217 // Turn f64->i64 into FMRRD iff target supports vfp2.
218 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
220 // We want to custom lower some of our intrinsics.
221 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
223 setOperationAction(ISD::SETCC , MVT::i32, Expand);
224 setOperationAction(ISD::SETCC , MVT::f32, Expand);
225 setOperationAction(ISD::SETCC , MVT::f64, Expand);
226 setOperationAction(ISD::SELECT , MVT::i32, Expand);
227 setOperationAction(ISD::SELECT , MVT::f32, Expand);
228 setOperationAction(ISD::SELECT , MVT::f64, Expand);
229 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
230 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
231 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
233 setOperationAction(ISD::BRCOND , MVT::Other, Expand);
234 setOperationAction(ISD::BR_CC , MVT::i32, Custom);
235 setOperationAction(ISD::BR_CC , MVT::f32, Custom);
236 setOperationAction(ISD::BR_CC , MVT::f64, Custom);
237 setOperationAction(ISD::BR_JT , MVT::Other, Custom);
239 // We don't support sin/cos/fmod/copysign/pow
240 setOperationAction(ISD::FSIN , MVT::f64, Expand);
241 setOperationAction(ISD::FSIN , MVT::f32, Expand);
242 setOperationAction(ISD::FCOS , MVT::f32, Expand);
243 setOperationAction(ISD::FCOS , MVT::f64, Expand);
244 setOperationAction(ISD::FREM , MVT::f64, Expand);
245 setOperationAction(ISD::FREM , MVT::f32, Expand);
246 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) {
247 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
248 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
250 setOperationAction(ISD::FPOW , MVT::f64, Expand);
251 setOperationAction(ISD::FPOW , MVT::f32, Expand);
253 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
254 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) {
255 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
256 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
257 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
258 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
261 // We have target-specific dag combine patterns for the following nodes:
262 // ARMISD::FMRRD - No need to call setTargetDAGCombine
264 setStackPointerRegisterToSaveRestore(ARM::SP);
265 setSchedulingPreference(SchedulingForRegPressure);
266 setIfCvtBlockSizeLimit(Subtarget->isThumb() ? 0 : 10);
267 setIfCvtDupBlockSizeLimit(Subtarget->isThumb() ? 0 : 2);
269 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
273 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
276 case ARMISD::Wrapper: return "ARMISD::Wrapper";
277 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
278 case ARMISD::CALL: return "ARMISD::CALL";
279 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
280 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
281 case ARMISD::tCALL: return "ARMISD::tCALL";
282 case ARMISD::BRCOND: return "ARMISD::BRCOND";
283 case ARMISD::BR_JT: return "ARMISD::BR_JT";
284 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
285 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
286 case ARMISD::CMP: return "ARMISD::CMP";
287 case ARMISD::CMPNZ: return "ARMISD::CMPNZ";
288 case ARMISD::CMPFP: return "ARMISD::CMPFP";
289 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
290 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
291 case ARMISD::CMOV: return "ARMISD::CMOV";
292 case ARMISD::CNEG: return "ARMISD::CNEG";
294 case ARMISD::FTOSI: return "ARMISD::FTOSI";
295 case ARMISD::FTOUI: return "ARMISD::FTOUI";
296 case ARMISD::SITOF: return "ARMISD::SITOF";
297 case ARMISD::UITOF: return "ARMISD::UITOF";
299 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
300 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
301 case ARMISD::RRX: return "ARMISD::RRX";
303 case ARMISD::FMRRD: return "ARMISD::FMRRD";
304 case ARMISD::FMDRR: return "ARMISD::FMDRR";
306 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
310 //===----------------------------------------------------------------------===//
312 //===----------------------------------------------------------------------===//
315 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
316 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
318 default: assert(0 && "Unknown condition code!");
319 case ISD::SETNE: return ARMCC::NE;
320 case ISD::SETEQ: return ARMCC::EQ;
321 case ISD::SETGT: return ARMCC::GT;
322 case ISD::SETGE: return ARMCC::GE;
323 case ISD::SETLT: return ARMCC::LT;
324 case ISD::SETLE: return ARMCC::LE;
325 case ISD::SETUGT: return ARMCC::HI;
326 case ISD::SETUGE: return ARMCC::HS;
327 case ISD::SETULT: return ARMCC::LO;
328 case ISD::SETULE: return ARMCC::LS;
332 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. It
333 /// returns true if the operands should be inverted to form the proper
335 static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
336 ARMCC::CondCodes &CondCode2) {
338 CondCode2 = ARMCC::AL;
340 default: assert(0 && "Unknown FP condition!");
342 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
344 case ISD::SETOGT: CondCode = ARMCC::GT; break;
346 case ISD::SETOGE: CondCode = ARMCC::GE; break;
347 case ISD::SETOLT: CondCode = ARMCC::MI; break;
348 case ISD::SETOLE: CondCode = ARMCC::GT; Invert = true; break;
349 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
350 case ISD::SETO: CondCode = ARMCC::VC; break;
351 case ISD::SETUO: CondCode = ARMCC::VS; break;
352 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
353 case ISD::SETUGT: CondCode = ARMCC::HI; break;
354 case ISD::SETUGE: CondCode = ARMCC::PL; break;
356 case ISD::SETULT: CondCode = ARMCC::LT; break;
358 case ISD::SETULE: CondCode = ARMCC::LE; break;
360 case ISD::SETUNE: CondCode = ARMCC::NE; break;
366 HowToPassArgument(MVT ObjectVT, unsigned NumGPRs,
367 unsigned StackOffset, unsigned &NeededGPRs,
368 unsigned &NeededStackSize, unsigned &GPRPad,
369 unsigned &StackPad, ISD::ArgFlagsTy Flags) {
374 unsigned align = Flags.getOrigAlign();
375 GPRPad = NumGPRs % ((align + 3)/4);
376 StackPad = StackOffset % align;
377 unsigned firstGPR = NumGPRs + GPRPad;
378 switch (ObjectVT.getSimpleVT()) {
379 default: assert(0 && "Unhandled argument type!");
391 else if (firstGPR == 3) {
399 /// LowerCALL - Lowering a ISD::CALL node into a callseq_start <-
400 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
402 SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
403 MVT RetVT= Op.Val->getValueType(0);
404 SDOperand Chain = Op.getOperand(0);
405 unsigned CallConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
406 assert((CallConv == CallingConv::C ||
407 CallConv == CallingConv::Fast) && "unknown calling convention");
408 SDOperand Callee = Op.getOperand(4);
409 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
410 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
411 unsigned NumGPRs = 0; // GPRs used for parameter passing.
413 // Count how many bytes are to be pushed on the stack.
414 unsigned NumBytes = 0;
416 // Add up all the space actually used.
417 for (unsigned i = 0; i < NumOps; ++i) {
422 MVT ObjectVT = Op.getOperand(5+2*i).getValueType();
423 ISD::ArgFlagsTy Flags =
424 cast<ARG_FLAGSSDNode>(Op.getOperand(5+2*i+1))->getArgFlags();
425 HowToPassArgument(ObjectVT, NumGPRs, NumBytes, ObjGPRs, ObjSize,
426 GPRPad, StackPad, Flags);
427 NumBytes += ObjSize + StackPad;
428 NumGPRs += ObjGPRs + GPRPad;
431 // Adjust the stack pointer for the new arguments...
432 // These operations are automatically eliminated by the prolog/epilog pass
433 Chain = DAG.getCALLSEQ_START(Chain,
434 DAG.getConstant(NumBytes, MVT::i32));
436 SDOperand StackPtr = DAG.getRegister(ARM::SP, MVT::i32);
438 static const unsigned GPRArgRegs[] = {
439 ARM::R0, ARM::R1, ARM::R2, ARM::R3
443 std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
444 std::vector<SDOperand> MemOpChains;
445 for (unsigned i = 0; i != NumOps; ++i) {
446 SDOperand Arg = Op.getOperand(5+2*i);
447 ISD::ArgFlagsTy Flags =
448 cast<ARG_FLAGSSDNode>(Op.getOperand(5+2*i+1))->getArgFlags();
449 MVT ArgVT = Arg.getValueType();
455 HowToPassArgument(ArgVT, NumGPRs, ArgOffset, ObjGPRs,
456 ObjSize, GPRPad, StackPad, Flags);
458 ArgOffset += StackPad;
460 switch (ArgVT.getSimpleVT()) {
461 default: assert(0 && "Unexpected ValueType for argument!");
463 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Arg));
466 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs],
467 DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Arg)));
470 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg,
471 DAG.getConstant(0, getPointerTy()));
472 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg,
473 DAG.getConstant(1, getPointerTy()));
474 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Lo));
476 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1], Hi));
478 SDOperand PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType());
479 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
480 MemOpChains.push_back(DAG.getStore(Chain, Hi, PtrOff, NULL, 0));
485 SDOperand Cvt = DAG.getNode(ARMISD::FMRRD,
486 DAG.getVTList(MVT::i32, MVT::i32),
488 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Cvt));
490 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1],
493 SDOperand PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType());
494 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
495 MemOpChains.push_back(DAG.getStore(Chain, Cvt.getValue(1), PtrOff,
502 assert(ObjSize != 0);
503 SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
504 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
505 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
509 ArgOffset += ObjSize;
512 if (!MemOpChains.empty())
513 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
514 &MemOpChains[0], MemOpChains.size());
516 // Build a sequence of copy-to-reg nodes chained together with token chain
517 // and flag operands which copy the outgoing args into the appropriate regs.
519 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
520 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
522 InFlag = Chain.getValue(1);
525 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
526 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
527 // node so that legalize doesn't hack it.
528 bool isDirect = false;
529 bool isARMFunc = false;
530 bool isLocalARMFunc = false;
531 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
532 GlobalValue *GV = G->getGlobal();
534 bool isExt = (GV->isDeclaration() || GV->hasWeakLinkage() ||
535 GV->hasLinkOnceLinkage());
536 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
537 getTargetMachine().getRelocationModel() != Reloc::Static;
538 isARMFunc = !Subtarget->isThumb() || isStub;
539 // ARM call to a local ARM function is predicable.
540 isLocalARMFunc = !Subtarget->isThumb() && !isExt;
541 // tBX takes a register source operand.
542 if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) {
543 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
545 SDOperand CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2);
546 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
547 Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0);
548 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
549 Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel);
551 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy());
552 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
554 bool isStub = Subtarget->isTargetDarwin() &&
555 getTargetMachine().getRelocationModel() != Reloc::Static;
556 isARMFunc = !Subtarget->isThumb() || isStub;
557 // tBX takes a register source operand.
558 const char *Sym = S->getSymbol();
559 if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) {
560 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(Sym, ARMPCLabelIndex,
562 SDOperand CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2);
563 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
564 Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0);
565 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
566 Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel);
568 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
571 // FIXME: handle tail calls differently.
573 if (Subtarget->isThumb()) {
574 if (!Subtarget->hasV5TOps() && (!isDirect || isARMFunc))
575 CallOpc = ARMISD::CALL_NOLINK;
577 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
579 CallOpc = (isDirect || Subtarget->hasV5TOps())
580 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
581 : ARMISD::CALL_NOLINK;
583 if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb()) {
584 // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK
585 Chain = DAG.getCopyToReg(Chain, ARM::LR,
586 DAG.getNode(ISD::UNDEF, MVT::i32), InFlag);
587 InFlag = Chain.getValue(1);
590 std::vector<SDOperand> Ops;
591 Ops.push_back(Chain);
592 Ops.push_back(Callee);
594 // Add argument registers to the end of the list so that they are known live
596 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
597 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
598 RegsToPass[i].second.getValueType()));
601 Ops.push_back(InFlag);
602 // Returns a chain and a flag for retval copy to use.
603 Chain = DAG.getNode(CallOpc, DAG.getVTList(MVT::Other, MVT::Flag),
604 &Ops[0], Ops.size());
605 InFlag = Chain.getValue(1);
607 Chain = DAG.getCALLSEQ_END(Chain,
608 DAG.getConstant(NumBytes, MVT::i32),
609 DAG.getConstant(0, MVT::i32),
611 if (RetVT != MVT::Other)
612 InFlag = Chain.getValue(1);
614 std::vector<SDOperand> ResultVals;
616 // If the call has results, copy the values out of the ret val registers.
617 switch (RetVT.getSimpleVT()) {
618 default: assert(0 && "Unexpected ret value!");
622 Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1);
623 ResultVals.push_back(Chain.getValue(0));
624 if (Op.Val->getValueType(1) == MVT::i32) {
625 // Returns a i64 value.
626 Chain = DAG.getCopyFromReg(Chain, ARM::R1, MVT::i32,
627 Chain.getValue(2)).getValue(1);
628 ResultVals.push_back(Chain.getValue(0));
632 Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1);
633 ResultVals.push_back(DAG.getNode(ISD::BIT_CONVERT, MVT::f32,
637 SDOperand Lo = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag);
638 SDOperand Hi = DAG.getCopyFromReg(Lo, ARM::R1, MVT::i32, Lo.getValue(2));
639 ResultVals.push_back(DAG.getNode(ARMISD::FMDRR, MVT::f64, Lo, Hi));
644 if (ResultVals.empty())
647 ResultVals.push_back(Chain);
648 SDOperand Res = DAG.getMergeValues(&ResultVals[0], ResultVals.size());
649 return Res.getValue(Op.ResNo);
652 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
654 SDOperand Chain = Op.getOperand(0);
655 switch(Op.getNumOperands()) {
657 assert(0 && "Do not know how to return this many arguments!");
660 SDOperand LR = DAG.getRegister(ARM::LR, MVT::i32);
661 return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Chain);
664 Op = Op.getOperand(1);
665 if (Op.getValueType() == MVT::f32) {
666 Op = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
667 } else if (Op.getValueType() == MVT::f64) {
668 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
670 Op = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32), &Op,1);
671 SDOperand Sign = DAG.getConstant(0, MVT::i32);
672 return DAG.getNode(ISD::RET, MVT::Other, Chain, Op, Sign,
673 Op.getValue(1), Sign);
675 Copy = DAG.getCopyToReg(Chain, ARM::R0, Op, SDOperand());
676 if (DAG.getMachineFunction().getRegInfo().liveout_empty())
677 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0);
680 Copy = DAG.getCopyToReg(Chain, ARM::R1, Op.getOperand(3), SDOperand());
681 Copy = DAG.getCopyToReg(Copy, ARM::R0, Op.getOperand(1), Copy.getValue(1));
682 // If we haven't noted the R0+R1 are live out, do so now.
683 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
684 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0);
685 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R1);
688 case 9: // i128 -> 4 regs
689 Copy = DAG.getCopyToReg(Chain, ARM::R3, Op.getOperand(7), SDOperand());
690 Copy = DAG.getCopyToReg(Copy , ARM::R2, Op.getOperand(5), Copy.getValue(1));
691 Copy = DAG.getCopyToReg(Copy , ARM::R1, Op.getOperand(3), Copy.getValue(1));
692 Copy = DAG.getCopyToReg(Copy , ARM::R0, Op.getOperand(1), Copy.getValue(1));
693 // If we haven't noted the R0+R1 are live out, do so now.
694 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
695 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0);
696 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R1);
697 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R2);
698 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R3);
704 //We must use RET_FLAG instead of BRIND because BRIND doesn't have a flag
705 return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
708 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
709 // their target countpart wrapped in the ARMISD::Wrapper node. Suppose N is
710 // one of the above mentioned nodes. It has to be wrapped because otherwise
711 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
712 // be used to form addressing mode. These wrapped nodes will be selected
714 static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
715 MVT PtrVT = Op.getValueType();
716 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
718 if (CP->isMachineConstantPoolEntry())
719 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
722 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
724 return DAG.getNode(ARMISD::Wrapper, MVT::i32, Res);
727 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
729 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
731 MVT PtrVT = getPointerTy();
732 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
733 ARMConstantPoolValue *CPV =
734 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
735 PCAdj, "tlsgd", true);
736 SDOperand Argument = DAG.getTargetConstantPool(CPV, PtrVT, 2);
737 Argument = DAG.getNode(ARMISD::Wrapper, MVT::i32, Argument);
738 Argument = DAG.getLoad(PtrVT, DAG.getEntryNode(), Argument, NULL, 0);
739 SDOperand Chain = Argument.getValue(1);
741 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
742 Argument = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Argument, PICLabel);
744 // call __tls_get_addr.
747 Entry.Node = Argument;
748 Entry.Ty = (const Type *) Type::Int32Ty;
749 Args.push_back(Entry);
750 std::pair<SDOperand, SDOperand> CallResult =
751 LowerCallTo(Chain, (const Type *) Type::Int32Ty, false, false, false,
752 CallingConv::C, false,
753 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG);
754 return CallResult.first;
757 // Lower ISD::GlobalTLSAddress using the "initial exec" or
758 // "local exec" model.
760 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
762 GlobalValue *GV = GA->getGlobal();
764 SDOperand Chain = DAG.getEntryNode();
765 MVT PtrVT = getPointerTy();
766 // Get the Thread Pointer
767 SDOperand ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, PtrVT);
769 if (GV->isDeclaration()){
770 // initial exec model
771 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
772 ARMConstantPoolValue *CPV =
773 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
774 PCAdj, "gottpoff", true);
775 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 2);
776 Offset = DAG.getNode(ARMISD::Wrapper, MVT::i32, Offset);
777 Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0);
778 Chain = Offset.getValue(1);
780 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
781 Offset = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Offset, PICLabel);
783 Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0);
786 ARMConstantPoolValue *CPV =
787 new ARMConstantPoolValue(GV, ARMCP::CPValue, "tpoff");
788 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 2);
789 Offset = DAG.getNode(ARMISD::Wrapper, MVT::i32, Offset);
790 Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0);
793 // The address of the thread local variable is the add of the thread
794 // pointer with the offset of the variable.
795 return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset);
799 ARMTargetLowering::LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) {
800 // TODO: implement the "local dynamic" model
801 assert(Subtarget->isTargetELF() &&
802 "TLS not implemented for non-ELF targets");
803 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
804 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
805 // otherwise use the "Local Exec" TLS Model
806 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
807 return LowerToTLSGeneralDynamicModel(GA, DAG);
809 return LowerToTLSExecModels(GA, DAG);
812 SDOperand ARMTargetLowering::LowerGlobalAddressELF(SDOperand Op,
814 MVT PtrVT = getPointerTy();
815 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
816 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
817 if (RelocM == Reloc::PIC_) {
818 bool UseGOTOFF = GV->hasInternalLinkage() || GV->hasHiddenVisibility();
819 ARMConstantPoolValue *CPV =
820 new ARMConstantPoolValue(GV, ARMCP::CPValue, UseGOTOFF ? "GOTOFF":"GOT");
821 SDOperand CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
822 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
823 SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
824 SDOperand Chain = Result.getValue(1);
825 SDOperand GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PtrVT);
826 Result = DAG.getNode(ISD::ADD, PtrVT, Result, GOT);
828 Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0);
831 SDOperand CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2);
832 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
833 return DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
837 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol
838 /// even in non-static mode.
839 static bool GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model RelocM) {
840 return RelocM != Reloc::Static &&
841 (GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
842 (GV->isDeclaration() && !GV->hasNotBeenReadFromBitcode()));
845 SDOperand ARMTargetLowering::LowerGlobalAddressDarwin(SDOperand Op,
847 MVT PtrVT = getPointerTy();
848 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
849 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
850 bool IsIndirect = GVIsIndirectSymbol(GV, RelocM);
852 if (RelocM == Reloc::Static)
853 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2);
855 unsigned PCAdj = (RelocM != Reloc::PIC_)
856 ? 0 : (Subtarget->isThumb() ? 4 : 8);
857 ARMCP::ARMCPKind Kind = IsIndirect ? ARMCP::CPNonLazyPtr
859 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
861 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
863 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
865 SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
866 SDOperand Chain = Result.getValue(1);
868 if (RelocM == Reloc::PIC_) {
869 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
870 Result = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel);
873 Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0);
878 SDOperand ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDOperand Op,
880 assert(Subtarget->isTargetELF() &&
881 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
882 MVT PtrVT = getPointerTy();
883 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
884 ARMConstantPoolValue *CPV = new ARMConstantPoolValue("_GLOBAL_OFFSET_TABLE_",
886 ARMCP::CPValue, PCAdj);
887 SDOperand CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
888 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
889 SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
890 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
891 return DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel);
894 static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
895 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
896 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue();
898 default: return SDOperand(); // Don't custom lower most intrinsics.
899 case Intrinsic::arm_thread_pointer:
900 return DAG.getNode(ARMISD::THREAD_POINTER, PtrVT);
904 static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
905 unsigned VarArgsFrameIndex) {
906 // vastart just stores the address of the VarArgsFrameIndex slot into the
907 // memory location argument.
908 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
909 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
910 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
911 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0);
914 static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG,
915 unsigned ArgNo, unsigned &NumGPRs,
916 unsigned &ArgOffset) {
917 MachineFunction &MF = DAG.getMachineFunction();
918 MVT ObjectVT = Op.getValue(ArgNo).getValueType();
919 SDOperand Root = Op.getOperand(0);
920 std::vector<SDOperand> ArgValues;
921 MachineRegisterInfo &RegInfo = MF.getRegInfo();
923 static const unsigned GPRArgRegs[] = {
924 ARM::R0, ARM::R1, ARM::R2, ARM::R3
931 ISD::ArgFlagsTy Flags =
932 cast<ARG_FLAGSSDNode>(Op.getOperand(ArgNo + 3))->getArgFlags();
933 HowToPassArgument(ObjectVT, NumGPRs, ArgOffset, ObjGPRs,
934 ObjSize, GPRPad, StackPad, Flags);
936 ArgOffset += StackPad;
940 unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
941 RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
942 ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32);
943 if (ObjectVT == MVT::f32)
944 ArgValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, ArgValue);
945 } else if (ObjGPRs == 2) {
946 unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
947 RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
948 ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32);
950 VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
951 RegInfo.addLiveIn(GPRArgRegs[NumGPRs+1], VReg);
952 SDOperand ArgValue2 = DAG.getCopyFromReg(Root, VReg, MVT::i32);
954 assert(ObjectVT != MVT::i64 && "i64 should already be lowered");
955 ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2);
960 MachineFrameInfo *MFI = MF.getFrameInfo();
961 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
962 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
964 ArgValue = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
966 SDOperand ArgValue2 = DAG.getLoad(MVT::i32, Root, FIN, NULL, 0);
967 assert(ObjectVT != MVT::i64 && "i64 should already be lowered");
968 ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2);
971 ArgOffset += ObjSize; // Move on to the next argument.
978 ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
979 std::vector<SDOperand> ArgValues;
980 SDOperand Root = Op.getOperand(0);
981 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
982 unsigned NumGPRs = 0; // GPRs used for parameter passing.
984 unsigned NumArgs = Op.Val->getNumValues()-1;
985 for (unsigned ArgNo = 0; ArgNo < NumArgs; ++ArgNo)
986 ArgValues.push_back(LowerFORMAL_ARGUMENT(Op, DAG, ArgNo,
987 NumGPRs, ArgOffset));
989 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
991 static const unsigned GPRArgRegs[] = {
992 ARM::R0, ARM::R1, ARM::R2, ARM::R3
995 MachineFunction &MF = DAG.getMachineFunction();
996 MachineRegisterInfo &RegInfo = MF.getRegInfo();
997 MachineFrameInfo *MFI = MF.getFrameInfo();
998 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
999 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1000 unsigned VARegSize = (4 - NumGPRs) * 4;
1001 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
1002 if (VARegSaveSize) {
1003 // If this function is vararg, store any remaining integer argument regs
1004 // to their spots on the stack so that they may be loaded by deferencing
1005 // the result of va_next.
1006 AFI->setVarArgsRegSaveSize(VARegSaveSize);
1007 VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset +
1008 VARegSaveSize - VARegSize);
1009 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
1011 SmallVector<SDOperand, 4> MemOps;
1012 for (; NumGPRs < 4; ++NumGPRs) {
1013 unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass);
1014 RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg);
1015 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i32);
1016 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1017 MemOps.push_back(Store);
1018 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1019 DAG.getConstant(4, getPointerTy()));
1021 if (!MemOps.empty())
1022 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
1023 &MemOps[0], MemOps.size());
1025 // This will point to the next argument passed via stack.
1026 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
1029 ArgValues.push_back(Root);
1031 // Return the new list of results.
1032 return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
1036 /// isFloatingPointZero - Return true if this is +0.0.
1037 static bool isFloatingPointZero(SDOperand Op) {
1038 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1039 return CFP->getValueAPF().isPosZero();
1040 else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
1041 // Maybe this has already been legalized into the constant pool?
1042 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
1043 SDOperand WrapperOp = Op.getOperand(1).getOperand(0);
1044 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
1045 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1046 return CFP->getValueAPF().isPosZero();
1052 static bool isLegalCmpImmediate(unsigned C, bool isThumb) {
1053 return ( isThumb && (C & ~255U) == 0) ||
1054 (!isThumb && ARM_AM::getSOImmVal(C) != -1);
1057 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
1058 /// the given operands.
1059 static SDOperand getARMCmp(SDOperand LHS, SDOperand RHS, ISD::CondCode CC,
1060 SDOperand &ARMCC, SelectionDAG &DAG, bool isThumb) {
1061 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.Val)) {
1062 unsigned C = RHSC->getValue();
1063 if (!isLegalCmpImmediate(C, isThumb)) {
1064 // Constant does not fit, try adjusting it by one?
1069 if (isLegalCmpImmediate(C-1, isThumb)) {
1070 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1071 RHS = DAG.getConstant(C-1, MVT::i32);
1076 if (C > 0 && isLegalCmpImmediate(C-1, isThumb)) {
1077 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1078 RHS = DAG.getConstant(C-1, MVT::i32);
1083 if (isLegalCmpImmediate(C+1, isThumb)) {
1084 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1085 RHS = DAG.getConstant(C+1, MVT::i32);
1090 if (C < 0xffffffff && isLegalCmpImmediate(C+1, isThumb)) {
1091 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1092 RHS = DAG.getConstant(C+1, MVT::i32);
1099 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
1100 ARMISD::NodeType CompareType;
1103 CompareType = ARMISD::CMP;
1109 // Uses only N and Z Flags
1110 CompareType = ARMISD::CMPNZ;
1113 ARMCC = DAG.getConstant(CondCode, MVT::i32);
1114 return DAG.getNode(CompareType, MVT::Flag, LHS, RHS);
1117 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
1118 static SDOperand getVFPCmp(SDOperand LHS, SDOperand RHS, SelectionDAG &DAG) {
1120 if (!isFloatingPointZero(RHS))
1121 Cmp = DAG.getNode(ARMISD::CMPFP, MVT::Flag, LHS, RHS);
1123 Cmp = DAG.getNode(ARMISD::CMPFPw0, MVT::Flag, LHS);
1124 return DAG.getNode(ARMISD::FMSTAT, MVT::Flag, Cmp);
1127 static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG,
1128 const ARMSubtarget *ST) {
1129 MVT VT = Op.getValueType();
1130 SDOperand LHS = Op.getOperand(0);
1131 SDOperand RHS = Op.getOperand(1);
1132 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1133 SDOperand TrueVal = Op.getOperand(2);
1134 SDOperand FalseVal = Op.getOperand(3);
1136 if (LHS.getValueType() == MVT::i32) {
1138 SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1139 SDOperand Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb());
1140 return DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal, ARMCC, CCR, Cmp);
1143 ARMCC::CondCodes CondCode, CondCode2;
1144 if (FPCCToARMCC(CC, CondCode, CondCode2))
1145 std::swap(TrueVal, FalseVal);
1147 SDOperand ARMCC = DAG.getConstant(CondCode, MVT::i32);
1148 SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1149 SDOperand Cmp = getVFPCmp(LHS, RHS, DAG);
1150 SDOperand Result = DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal,
1152 if (CondCode2 != ARMCC::AL) {
1153 SDOperand ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
1154 // FIXME: Needs another CMP because flag can have but one use.
1155 SDOperand Cmp2 = getVFPCmp(LHS, RHS, DAG);
1156 Result = DAG.getNode(ARMISD::CMOV, VT, Result, TrueVal, ARMCC2, CCR, Cmp2);
1161 static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG,
1162 const ARMSubtarget *ST) {
1163 SDOperand Chain = Op.getOperand(0);
1164 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1165 SDOperand LHS = Op.getOperand(2);
1166 SDOperand RHS = Op.getOperand(3);
1167 SDOperand Dest = Op.getOperand(4);
1169 if (LHS.getValueType() == MVT::i32) {
1171 SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1172 SDOperand Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb());
1173 return DAG.getNode(ARMISD::BRCOND, MVT::Other, Chain, Dest, ARMCC, CCR,Cmp);
1176 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
1177 ARMCC::CondCodes CondCode, CondCode2;
1178 if (FPCCToARMCC(CC, CondCode, CondCode2))
1179 // Swap the LHS/RHS of the comparison if needed.
1180 std::swap(LHS, RHS);
1182 SDOperand Cmp = getVFPCmp(LHS, RHS, DAG);
1183 SDOperand ARMCC = DAG.getConstant(CondCode, MVT::i32);
1184 SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1185 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
1186 SDOperand Ops[] = { Chain, Dest, ARMCC, CCR, Cmp };
1187 SDOperand Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5);
1188 if (CondCode2 != ARMCC::AL) {
1189 ARMCC = DAG.getConstant(CondCode2, MVT::i32);
1190 SDOperand Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) };
1191 Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5);
1196 SDOperand ARMTargetLowering::LowerBR_JT(SDOperand Op, SelectionDAG &DAG) {
1197 SDOperand Chain = Op.getOperand(0);
1198 SDOperand Table = Op.getOperand(1);
1199 SDOperand Index = Op.getOperand(2);
1201 MVT PTy = getPointerTy();
1202 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
1203 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
1204 SDOperand UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
1205 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
1206 Table = DAG.getNode(ARMISD::WrapperJT, MVT::i32, JTI, UId);
1207 Index = DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(4, PTy));
1208 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1209 bool isPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
1210 Addr = DAG.getLoad(isPIC ? (MVT)MVT::i32 : PTy,
1211 Chain, Addr, NULL, 0);
1212 Chain = Addr.getValue(1);
1214 Addr = DAG.getNode(ISD::ADD, PTy, Addr, Table);
1215 return DAG.getNode(ARMISD::BR_JT, MVT::Other, Chain, Addr, JTI, UId);
1218 static SDOperand LowerFP_TO_INT(SDOperand Op, SelectionDAG &DAG) {
1220 Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI;
1221 Op = DAG.getNode(Opc, MVT::f32, Op.getOperand(0));
1222 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
1225 static SDOperand LowerINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
1226 MVT VT = Op.getValueType();
1228 Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF;
1230 Op = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
1231 return DAG.getNode(Opc, VT, Op);
1234 static SDOperand LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) {
1235 // Implement fcopysign with a fabs and a conditional fneg.
1236 SDOperand Tmp0 = Op.getOperand(0);
1237 SDOperand Tmp1 = Op.getOperand(1);
1238 MVT VT = Op.getValueType();
1239 MVT SrcVT = Tmp1.getValueType();
1240 SDOperand AbsVal = DAG.getNode(ISD::FABS, VT, Tmp0);
1241 SDOperand Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG);
1242 SDOperand ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
1243 SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1244 return DAG.getNode(ARMISD::CNEG, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp);
1248 ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG,
1250 SDOperand Dst, SDOperand Src,
1251 SDOperand Size, unsigned Align,
1253 const Value *DstSV, uint64_t DstSVOff,
1254 const Value *SrcSV, uint64_t SrcSVOff){
1255 // Do repeated 4-byte loads and stores. To be improved.
1256 // This requires 4-byte alignment.
1257 if ((Align & 3) != 0)
1259 // This requires the copy size to be a constant, preferrably
1260 // within a subtarget-specific limit.
1261 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
1264 uint64_t SizeVal = ConstantSize->getValue();
1265 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
1268 unsigned BytesLeft = SizeVal & 3;
1269 unsigned NumMemOps = SizeVal >> 2;
1270 unsigned EmittedNumMemOps = 0;
1272 unsigned VTSize = 4;
1274 const unsigned MAX_LOADS_IN_LDM = 6;
1275 SDOperand TFOps[MAX_LOADS_IN_LDM];
1276 SDOperand Loads[MAX_LOADS_IN_LDM];
1277 uint64_t SrcOff = 0, DstOff = 0;
1279 // Emit up to MAX_LOADS_IN_LDM loads, then a TokenFactor barrier, then the
1280 // same number of stores. The loads and stores will get combined into
1281 // ldm/stm later on.
1282 while (EmittedNumMemOps < NumMemOps) {
1284 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
1285 Loads[i] = DAG.getLoad(VT, Chain,
1286 DAG.getNode(ISD::ADD, MVT::i32, Src,
1287 DAG.getConstant(SrcOff, MVT::i32)),
1288 SrcSV, SrcSVOff + SrcOff);
1289 TFOps[i] = Loads[i].getValue(1);
1292 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i);
1295 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
1296 TFOps[i] = DAG.getStore(Chain, Loads[i],
1297 DAG.getNode(ISD::ADD, MVT::i32, Dst,
1298 DAG.getConstant(DstOff, MVT::i32)),
1299 DstSV, DstSVOff + DstOff);
1302 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i);
1304 EmittedNumMemOps += i;
1310 // Issue loads / stores for the trailing (1 - 3) bytes.
1311 unsigned BytesLeftSave = BytesLeft;
1314 if (BytesLeft >= 2) {
1322 Loads[i] = DAG.getLoad(VT, Chain,
1323 DAG.getNode(ISD::ADD, MVT::i32, Src,
1324 DAG.getConstant(SrcOff, MVT::i32)),
1325 SrcSV, SrcSVOff + SrcOff);
1326 TFOps[i] = Loads[i].getValue(1);
1329 BytesLeft -= VTSize;
1331 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i);
1334 BytesLeft = BytesLeftSave;
1336 if (BytesLeft >= 2) {
1344 TFOps[i] = DAG.getStore(Chain, Loads[i],
1345 DAG.getNode(ISD::ADD, MVT::i32, Dst,
1346 DAG.getConstant(DstOff, MVT::i32)),
1347 DstSV, DstSVOff + DstOff);
1350 BytesLeft -= VTSize;
1352 return DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i);
1355 static SDNode *ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
1356 // Turn f64->i64 into FMRRD.
1357 assert(N->getValueType(0) == MVT::i64 &&
1358 N->getOperand(0).getValueType() == MVT::f64);
1360 SDOperand Op = N->getOperand(0);
1361 SDOperand Cvt = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32),
1364 // Merge the pieces into a single i64 value.
1365 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Cvt, Cvt.getValue(1)).Val;
1368 static SDNode *ExpandSRx(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) {
1369 assert(N->getValueType(0) == MVT::i64 &&
1370 (N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
1371 "Unknown shift to lower!");
1373 // We only lower SRA, SRL of 1 here, all others use generic lowering.
1374 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
1375 cast<ConstantSDNode>(N->getOperand(1))->getValue() != 1)
1378 // If we are in thumb mode, we don't have RRX.
1379 if (ST->isThumb()) return 0;
1381 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
1382 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0),
1383 DAG.getConstant(0, MVT::i32));
1384 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0),
1385 DAG.getConstant(1, MVT::i32));
1387 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
1388 // captures the result into a carry flag.
1389 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
1390 Hi = DAG.getNode(Opc, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
1392 // The low part is an ARMISD::RRX operand, which shifts the carry in.
1393 Lo = DAG.getNode(ARMISD::RRX, MVT::i32, Lo, Hi.getValue(1));
1395 // Merge the pieces into a single i64 value.
1396 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi).Val;
1400 SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
1401 switch (Op.getOpcode()) {
1402 default: assert(0 && "Don't know how to custom lower this!"); abort();
1403 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
1404 case ISD::GlobalAddress:
1405 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
1406 LowerGlobalAddressELF(Op, DAG);
1407 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
1408 case ISD::CALL: return LowerCALL(Op, DAG);
1409 case ISD::RET: return LowerRET(Op, DAG);
1410 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, Subtarget);
1411 case ISD::BR_CC: return LowerBR_CC(Op, DAG, Subtarget);
1412 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
1413 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex);
1414 case ISD::SINT_TO_FP:
1415 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
1416 case ISD::FP_TO_SINT:
1417 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
1418 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
1419 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
1420 case ISD::RETURNADDR: break;
1421 case ISD::FRAMEADDR: break;
1422 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
1423 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
1426 // FIXME: Remove these when LegalizeDAGTypes lands.
1427 case ISD::BIT_CONVERT: return SDOperand(ExpandBIT_CONVERT(Op.Val, DAG), 0);
1429 case ISD::SRA: return SDOperand(ExpandSRx(Op.Val, DAG,Subtarget),0);
1435 /// ReplaceNodeResults - Provide custom lowering hooks for nodes with illegal
1437 SDNode *ARMTargetLowering::ReplaceNodeResults(SDNode *N, SelectionDAG &DAG) {
1438 switch (N->getOpcode()) {
1439 default: assert(0 && "Don't know how to custom expand this!"); abort();
1440 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(N, DAG);
1442 case ISD::SRA: return ExpandSRx(N, DAG, Subtarget);
1447 //===----------------------------------------------------------------------===//
1448 // ARM Scheduler Hooks
1449 //===----------------------------------------------------------------------===//
1452 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1453 MachineBasicBlock *BB) {
1454 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1455 switch (MI->getOpcode()) {
1456 default: assert(false && "Unexpected instr type to insert");
1457 case ARM::tMOVCCr: {
1458 // To "insert" a SELECT_CC instruction, we actually have to insert the
1459 // diamond control-flow pattern. The incoming instruction knows the
1460 // destination vreg to set, the condition code register to branch on, the
1461 // true/false values to select between, and a branch opcode to use.
1462 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1463 MachineFunction::iterator It = BB;
1469 // cmpTY ccX, r1, r2
1471 // fallthrough --> copy0MBB
1472 MachineBasicBlock *thisMBB = BB;
1473 MachineFunction *F = BB->getParent();
1474 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1475 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
1476 BuildMI(BB, TII->get(ARM::tBcc)).addMBB(sinkMBB)
1477 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
1478 F->insert(It, copy0MBB);
1479 F->insert(It, sinkMBB);
1480 // Update machine-CFG edges by first adding all successors of the current
1481 // block to the new block which will contain the Phi node for the select.
1482 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
1483 e = BB->succ_end(); i != e; ++i)
1484 sinkMBB->addSuccessor(*i);
1485 // Next, remove all successors of the current block, and add the true
1486 // and fallthrough blocks as its successors.
1487 while(!BB->succ_empty())
1488 BB->removeSuccessor(BB->succ_begin());
1489 BB->addSuccessor(copy0MBB);
1490 BB->addSuccessor(sinkMBB);
1493 // %FalseValue = ...
1494 // # fallthrough to sinkMBB
1497 // Update machine-CFG edges
1498 BB->addSuccessor(sinkMBB);
1501 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1504 BuildMI(BB, TII->get(ARM::PHI), MI->getOperand(0).getReg())
1505 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
1506 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
1508 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
1514 //===----------------------------------------------------------------------===//
1515 // ARM Optimization Hooks
1516 //===----------------------------------------------------------------------===//
1518 /// PerformFMRRDCombine - Target-specific dag combine xforms for ARMISD::FMRRD.
1519 static SDOperand PerformFMRRDCombine(SDNode *N,
1520 TargetLowering::DAGCombinerInfo &DCI) {
1521 // fmrrd(fmdrr x, y) -> x,y
1522 SDOperand InDouble = N->getOperand(0);
1523 if (InDouble.getOpcode() == ARMISD::FMDRR)
1524 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
1528 SDOperand ARMTargetLowering::PerformDAGCombine(SDNode *N,
1529 DAGCombinerInfo &DCI) const {
1530 switch (N->getOpcode()) {
1532 case ARMISD::FMRRD: return PerformFMRRDCombine(N, DCI);
1539 /// isLegalAddressImmediate - Return true if the integer value can be used
1540 /// as the offset of the target addressing mode for load / store of the
1542 static bool isLegalAddressImmediate(int64_t V, MVT VT,
1543 const ARMSubtarget *Subtarget) {
1547 if (Subtarget->isThumb()) {
1552 switch (VT.getSimpleVT()) {
1553 default: return false;
1568 if ((V & (Scale - 1)) != 0)
1571 return V == (V & ((1LL << 5) - 1));
1576 switch (VT.getSimpleVT()) {
1577 default: return false;
1582 return V == (V & ((1LL << 12) - 1));
1585 return V == (V & ((1LL << 8) - 1));
1588 if (!Subtarget->hasVFP2())
1593 return V == (V & ((1LL << 8) - 1));
1597 /// isLegalAddressingMode - Return true if the addressing mode represented
1598 /// by AM is legal for this target, for a load/store of the specified type.
1599 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
1600 const Type *Ty) const {
1601 if (!isLegalAddressImmediate(AM.BaseOffs, getValueType(Ty, true), Subtarget))
1604 // Can never fold addr of global into load/store.
1609 case 0: // no scale reg, must be "r+i" or "r", or "i".
1612 if (Subtarget->isThumb())
1616 // ARM doesn't support any R+R*scale+imm addr modes.
1620 int Scale = AM.Scale;
1621 switch (getValueType(Ty).getSimpleVT()) {
1622 default: return false;
1627 // This assumes i64 is legalized to a pair of i32. If not (i.e.
1628 // ldrd / strd are used, then its address mode is same as i16.
1630 if (Scale < 0) Scale = -Scale;
1634 return isPowerOf2_32(Scale & ~1);
1637 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
1642 // Note, we allow "void" uses (basically, uses that aren't loads or
1643 // stores), because arm allows folding a scale into many arithmetic
1644 // operations. This should be made more precise and revisited later.
1646 // Allow r << imm, but the imm has to be a multiple of two.
1647 if (AM.Scale & 1) return false;
1648 return isPowerOf2_32(AM.Scale);
1656 static bool getIndexedAddressParts(SDNode *Ptr, MVT VT,
1657 bool isSEXTLoad, SDOperand &Base,
1658 SDOperand &Offset, bool &isInc,
1659 SelectionDAG &DAG) {
1660 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
1663 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
1665 Base = Ptr->getOperand(0);
1666 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
1667 int RHSC = (int)RHS->getValue();
1668 if (RHSC < 0 && RHSC > -256) {
1670 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
1674 isInc = (Ptr->getOpcode() == ISD::ADD);
1675 Offset = Ptr->getOperand(1);
1677 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
1679 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
1680 int RHSC = (int)RHS->getValue();
1681 if (RHSC < 0 && RHSC > -0x1000) {
1683 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
1684 Base = Ptr->getOperand(0);
1689 if (Ptr->getOpcode() == ISD::ADD) {
1691 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
1692 if (ShOpcVal != ARM_AM::no_shift) {
1693 Base = Ptr->getOperand(1);
1694 Offset = Ptr->getOperand(0);
1696 Base = Ptr->getOperand(0);
1697 Offset = Ptr->getOperand(1);
1702 isInc = (Ptr->getOpcode() == ISD::ADD);
1703 Base = Ptr->getOperand(0);
1704 Offset = Ptr->getOperand(1);
1708 // FIXME: Use FLDM / FSTM to emulate indexed FP load / store.
1712 /// getPreIndexedAddressParts - returns true by value, base pointer and
1713 /// offset pointer and addressing mode by reference if the node's address
1714 /// can be legally represented as pre-indexed load / store address.
1716 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
1718 ISD::MemIndexedMode &AM,
1719 SelectionDAG &DAG) {
1720 if (Subtarget->isThumb())
1725 bool isSEXTLoad = false;
1726 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1727 Ptr = LD->getBasePtr();
1728 VT = LD->getMemoryVT();
1729 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
1730 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1731 Ptr = ST->getBasePtr();
1732 VT = ST->getMemoryVT();
1737 bool isLegal = getIndexedAddressParts(Ptr.Val, VT, isSEXTLoad, Base, Offset,
1740 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
1746 /// getPostIndexedAddressParts - returns true by value, base pointer and
1747 /// offset pointer and addressing mode by reference if this node can be
1748 /// combined with a load / store to form a post-indexed load / store.
1749 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
1752 ISD::MemIndexedMode &AM,
1753 SelectionDAG &DAG) {
1754 if (Subtarget->isThumb())
1759 bool isSEXTLoad = false;
1760 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1761 VT = LD->getMemoryVT();
1762 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
1763 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1764 VT = ST->getMemoryVT();
1769 bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
1772 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
1778 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
1782 const SelectionDAG &DAG,
1783 unsigned Depth) const {
1784 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
1785 switch (Op.getOpcode()) {
1787 case ARMISD::CMOV: {
1788 // Bits are known zero/one if known on the LHS and RHS.
1789 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
1790 if (KnownZero == 0 && KnownOne == 0) return;
1792 APInt KnownZeroRHS, KnownOneRHS;
1793 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
1794 KnownZeroRHS, KnownOneRHS, Depth+1);
1795 KnownZero &= KnownZeroRHS;
1796 KnownOne &= KnownOneRHS;
1802 //===----------------------------------------------------------------------===//
1803 // ARM Inline Assembly Support
1804 //===----------------------------------------------------------------------===//
1806 /// getConstraintType - Given a constraint letter, return the type of
1807 /// constraint it is for this target.
1808 ARMTargetLowering::ConstraintType
1809 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
1810 if (Constraint.size() == 1) {
1811 switch (Constraint[0]) {
1813 case 'l': return C_RegisterClass;
1814 case 'w': return C_RegisterClass;
1817 return TargetLowering::getConstraintType(Constraint);
1820 std::pair<unsigned, const TargetRegisterClass*>
1821 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
1823 if (Constraint.size() == 1) {
1824 // GCC RS6000 Constraint Letters
1825 switch (Constraint[0]) {
1827 // FIXME: in thumb mode, 'l' is only low-regs.
1830 return std::make_pair(0U, ARM::GPRRegisterClass);
1833 return std::make_pair(0U, ARM::SPRRegisterClass);
1835 return std::make_pair(0U, ARM::DPRRegisterClass);
1839 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1842 std::vector<unsigned> ARMTargetLowering::
1843 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1845 if (Constraint.size() != 1)
1846 return std::vector<unsigned>();
1848 switch (Constraint[0]) { // GCC ARM Constraint Letters
1852 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1853 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1854 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1855 ARM::R12, ARM::LR, 0);
1858 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
1859 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
1860 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
1861 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
1862 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
1863 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
1864 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
1865 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
1867 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1868 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1869 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
1870 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
1874 return std::vector<unsigned>();