1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "arm-isel"
17 #include "ARMCallingConv.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMISelLowering.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMPerfectShuffle.h"
22 #include "ARMRegisterInfo.h"
23 #include "ARMSubtarget.h"
24 #include "ARMTargetMachine.h"
25 #include "ARMTargetObjectFile.h"
26 #include "MCTargetDesc/ARMAddressingModes.h"
27 #include "llvm/CallingConv.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Function.h"
30 #include "llvm/GlobalValue.h"
31 #include "llvm/Instruction.h"
32 #include "llvm/Instructions.h"
33 #include "llvm/Intrinsics.h"
34 #include "llvm/Type.h"
35 #include "llvm/CodeGen/CallingConvLower.h"
36 #include "llvm/CodeGen/IntrinsicLowering.h"
37 #include "llvm/CodeGen/MachineBasicBlock.h"
38 #include "llvm/CodeGen/MachineFrameInfo.h"
39 #include "llvm/CodeGen/MachineFunction.h"
40 #include "llvm/CodeGen/MachineInstrBuilder.h"
41 #include "llvm/CodeGen/MachineModuleInfo.h"
42 #include "llvm/CodeGen/MachineRegisterInfo.h"
43 #include "llvm/CodeGen/SelectionDAG.h"
44 #include "llvm/MC/MCSectionMachO.h"
45 #include "llvm/Target/TargetOptions.h"
46 #include "llvm/ADT/StringExtras.h"
47 #include "llvm/ADT/Statistic.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/MathExtras.h"
51 #include "llvm/Support/raw_ostream.h"
55 STATISTIC(NumTailCalls, "Number of tail calls");
56 STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt");
58 // This option should go away when tail calls fully work.
60 EnableARMTailCalls("arm-tail-calls", cl::Hidden,
61 cl::desc("Generate tail calls (TEMPORARY OPTION)."),
65 EnableARMLongCalls("arm-long-calls", cl::Hidden,
66 cl::desc("Generate calls via indirect call instructions"),
70 ARMInterworking("arm-interworking", cl::Hidden,
71 cl::desc("Enable / disable ARM interworking (for debugging only)"),
75 class ARMCCState : public CCState {
77 ARMCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
78 const TargetMachine &TM, SmallVector<CCValAssign, 16> &locs,
79 LLVMContext &C, ParmContext PC)
80 : CCState(CC, isVarArg, MF, TM, locs, C) {
81 assert(((PC == Call) || (PC == Prologue)) &&
82 "ARMCCState users must specify whether their context is call"
83 "or prologue generation.");
89 // The APCS parameter registers.
90 static const unsigned GPRArgRegs[] = {
91 ARM::R0, ARM::R1, ARM::R2, ARM::R3
94 void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
95 EVT PromotedBitwiseVT) {
96 if (VT != PromotedLdStVT) {
97 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
98 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
99 PromotedLdStVT.getSimpleVT());
101 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
102 AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
103 PromotedLdStVT.getSimpleVT());
106 EVT ElemTy = VT.getVectorElementType();
107 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
108 setOperationAction(ISD::SETCC, VT.getSimpleVT(), Custom);
109 setOperationAction(ISD::INSERT_VECTOR_ELT, VT.getSimpleVT(), Custom);
110 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
111 if (ElemTy == MVT::i32) {
112 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Custom);
113 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Custom);
114 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Custom);
115 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Custom);
117 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
118 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand);
119 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand);
120 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand);
122 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
123 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
124 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
125 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Legal);
126 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
127 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
128 setOperationAction(ISD::SIGN_EXTEND_INREG, VT.getSimpleVT(), Expand);
129 if (VT.isInteger()) {
130 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
131 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
132 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
135 // Promote all bit-wise operations.
136 if (VT.isInteger() && VT != PromotedBitwiseVT) {
137 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
138 AddPromotedToType (ISD::AND, VT.getSimpleVT(),
139 PromotedBitwiseVT.getSimpleVT());
140 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
141 AddPromotedToType (ISD::OR, VT.getSimpleVT(),
142 PromotedBitwiseVT.getSimpleVT());
143 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
144 AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
145 PromotedBitwiseVT.getSimpleVT());
148 // Neon does not support vector divide/remainder operations.
149 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
150 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
151 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand);
152 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
153 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
154 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
157 void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
158 addRegisterClass(VT, ARM::DPRRegisterClass);
159 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
162 void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
163 addRegisterClass(VT, ARM::QPRRegisterClass);
164 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
167 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
168 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
169 return new TargetLoweringObjectFileMachO();
171 return new ARMElfTargetObjectFile();
174 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
175 : TargetLowering(TM, createTLOF(TM)) {
176 Subtarget = &TM.getSubtarget<ARMSubtarget>();
177 RegInfo = TM.getRegisterInfo();
178 Itins = TM.getInstrItineraryData();
180 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
182 if (Subtarget->isTargetDarwin()) {
183 // Uses VFP for Thumb libfuncs if available.
184 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
185 // Single-precision floating-point arithmetic.
186 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
187 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
188 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
189 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
191 // Double-precision floating-point arithmetic.
192 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
193 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
194 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
195 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
197 // Single-precision comparisons.
198 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
199 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
200 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
201 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
202 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
203 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
204 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
205 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
207 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
208 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
209 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
210 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
211 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
212 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
213 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
214 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
216 // Double-precision comparisons.
217 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
218 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
219 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
220 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
221 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
222 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
223 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
224 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
226 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
227 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
228 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
229 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
230 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
231 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
232 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
233 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
235 // Floating-point to integer conversions.
236 // i64 conversions are done via library routines even when generating VFP
237 // instructions, so use the same ones.
238 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
239 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
240 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
241 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
243 // Conversions between floating types.
244 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
245 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
247 // Integer to floating-point conversions.
248 // i64 conversions are done via library routines even when generating VFP
249 // instructions, so use the same ones.
250 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
251 // e.g., __floatunsidf vs. __floatunssidfvfp.
252 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
253 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
254 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
255 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
259 // These libcalls are not available in 32-bit.
260 setLibcallName(RTLIB::SHL_I128, 0);
261 setLibcallName(RTLIB::SRL_I128, 0);
262 setLibcallName(RTLIB::SRA_I128, 0);
264 if (Subtarget->isAAPCS_ABI()) {
265 // Double-precision floating-point arithmetic helper functions
266 // RTABI chapter 4.1.2, Table 2
267 setLibcallName(RTLIB::ADD_F64, "__aeabi_dadd");
268 setLibcallName(RTLIB::DIV_F64, "__aeabi_ddiv");
269 setLibcallName(RTLIB::MUL_F64, "__aeabi_dmul");
270 setLibcallName(RTLIB::SUB_F64, "__aeabi_dsub");
271 setLibcallCallingConv(RTLIB::ADD_F64, CallingConv::ARM_AAPCS);
272 setLibcallCallingConv(RTLIB::DIV_F64, CallingConv::ARM_AAPCS);
273 setLibcallCallingConv(RTLIB::MUL_F64, CallingConv::ARM_AAPCS);
274 setLibcallCallingConv(RTLIB::SUB_F64, CallingConv::ARM_AAPCS);
276 // Double-precision floating-point comparison helper functions
277 // RTABI chapter 4.1.2, Table 3
278 setLibcallName(RTLIB::OEQ_F64, "__aeabi_dcmpeq");
279 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
280 setLibcallName(RTLIB::UNE_F64, "__aeabi_dcmpeq");
281 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETEQ);
282 setLibcallName(RTLIB::OLT_F64, "__aeabi_dcmplt");
283 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
284 setLibcallName(RTLIB::OLE_F64, "__aeabi_dcmple");
285 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
286 setLibcallName(RTLIB::OGE_F64, "__aeabi_dcmpge");
287 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
288 setLibcallName(RTLIB::OGT_F64, "__aeabi_dcmpgt");
289 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
290 setLibcallName(RTLIB::UO_F64, "__aeabi_dcmpun");
291 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
292 setLibcallName(RTLIB::O_F64, "__aeabi_dcmpun");
293 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
294 setLibcallCallingConv(RTLIB::OEQ_F64, CallingConv::ARM_AAPCS);
295 setLibcallCallingConv(RTLIB::UNE_F64, CallingConv::ARM_AAPCS);
296 setLibcallCallingConv(RTLIB::OLT_F64, CallingConv::ARM_AAPCS);
297 setLibcallCallingConv(RTLIB::OLE_F64, CallingConv::ARM_AAPCS);
298 setLibcallCallingConv(RTLIB::OGE_F64, CallingConv::ARM_AAPCS);
299 setLibcallCallingConv(RTLIB::OGT_F64, CallingConv::ARM_AAPCS);
300 setLibcallCallingConv(RTLIB::UO_F64, CallingConv::ARM_AAPCS);
301 setLibcallCallingConv(RTLIB::O_F64, CallingConv::ARM_AAPCS);
303 // Single-precision floating-point arithmetic helper functions
304 // RTABI chapter 4.1.2, Table 4
305 setLibcallName(RTLIB::ADD_F32, "__aeabi_fadd");
306 setLibcallName(RTLIB::DIV_F32, "__aeabi_fdiv");
307 setLibcallName(RTLIB::MUL_F32, "__aeabi_fmul");
308 setLibcallName(RTLIB::SUB_F32, "__aeabi_fsub");
309 setLibcallCallingConv(RTLIB::ADD_F32, CallingConv::ARM_AAPCS);
310 setLibcallCallingConv(RTLIB::DIV_F32, CallingConv::ARM_AAPCS);
311 setLibcallCallingConv(RTLIB::MUL_F32, CallingConv::ARM_AAPCS);
312 setLibcallCallingConv(RTLIB::SUB_F32, CallingConv::ARM_AAPCS);
314 // Single-precision floating-point comparison helper functions
315 // RTABI chapter 4.1.2, Table 5
316 setLibcallName(RTLIB::OEQ_F32, "__aeabi_fcmpeq");
317 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
318 setLibcallName(RTLIB::UNE_F32, "__aeabi_fcmpeq");
319 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETEQ);
320 setLibcallName(RTLIB::OLT_F32, "__aeabi_fcmplt");
321 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
322 setLibcallName(RTLIB::OLE_F32, "__aeabi_fcmple");
323 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
324 setLibcallName(RTLIB::OGE_F32, "__aeabi_fcmpge");
325 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
326 setLibcallName(RTLIB::OGT_F32, "__aeabi_fcmpgt");
327 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
328 setLibcallName(RTLIB::UO_F32, "__aeabi_fcmpun");
329 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
330 setLibcallName(RTLIB::O_F32, "__aeabi_fcmpun");
331 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
332 setLibcallCallingConv(RTLIB::OEQ_F32, CallingConv::ARM_AAPCS);
333 setLibcallCallingConv(RTLIB::UNE_F32, CallingConv::ARM_AAPCS);
334 setLibcallCallingConv(RTLIB::OLT_F32, CallingConv::ARM_AAPCS);
335 setLibcallCallingConv(RTLIB::OLE_F32, CallingConv::ARM_AAPCS);
336 setLibcallCallingConv(RTLIB::OGE_F32, CallingConv::ARM_AAPCS);
337 setLibcallCallingConv(RTLIB::OGT_F32, CallingConv::ARM_AAPCS);
338 setLibcallCallingConv(RTLIB::UO_F32, CallingConv::ARM_AAPCS);
339 setLibcallCallingConv(RTLIB::O_F32, CallingConv::ARM_AAPCS);
341 // Floating-point to integer conversions.
342 // RTABI chapter 4.1.2, Table 6
343 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz");
344 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz");
345 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz");
346 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz");
347 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz");
348 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz");
349 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz");
350 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz");
351 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I32, CallingConv::ARM_AAPCS);
352 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I32, CallingConv::ARM_AAPCS);
353 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I64, CallingConv::ARM_AAPCS);
354 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::ARM_AAPCS);
355 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I32, CallingConv::ARM_AAPCS);
356 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I32, CallingConv::ARM_AAPCS);
357 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I64, CallingConv::ARM_AAPCS);
358 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::ARM_AAPCS);
360 // Conversions between floating types.
361 // RTABI chapter 4.1.2, Table 7
362 setLibcallName(RTLIB::FPROUND_F64_F32, "__aeabi_d2f");
363 setLibcallName(RTLIB::FPEXT_F32_F64, "__aeabi_f2d");
364 setLibcallCallingConv(RTLIB::FPROUND_F64_F32, CallingConv::ARM_AAPCS);
365 setLibcallCallingConv(RTLIB::FPEXT_F32_F64, CallingConv::ARM_AAPCS);
367 // Integer to floating-point conversions.
368 // RTABI chapter 4.1.2, Table 8
369 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d");
370 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d");
371 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d");
372 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d");
373 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f");
374 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f");
375 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f");
376 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f");
377 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
378 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
379 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
380 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
381 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
382 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
383 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
384 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
386 // Long long helper functions
387 // RTABI chapter 4.2, Table 9
388 setLibcallName(RTLIB::MUL_I64, "__aeabi_lmul");
389 setLibcallName(RTLIB::SHL_I64, "__aeabi_llsl");
390 setLibcallName(RTLIB::SRL_I64, "__aeabi_llsr");
391 setLibcallName(RTLIB::SRA_I64, "__aeabi_lasr");
392 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::ARM_AAPCS);
393 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::ARM_AAPCS);
394 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::ARM_AAPCS);
395 setLibcallCallingConv(RTLIB::SHL_I64, CallingConv::ARM_AAPCS);
396 setLibcallCallingConv(RTLIB::SRL_I64, CallingConv::ARM_AAPCS);
397 setLibcallCallingConv(RTLIB::SRA_I64, CallingConv::ARM_AAPCS);
399 // Integer division functions
400 // RTABI chapter 4.3.1
401 setLibcallName(RTLIB::SDIV_I8, "__aeabi_idiv");
402 setLibcallName(RTLIB::SDIV_I16, "__aeabi_idiv");
403 setLibcallName(RTLIB::SDIV_I32, "__aeabi_idiv");
404 setLibcallName(RTLIB::SDIV_I64, "__aeabi_ldivmod");
405 setLibcallName(RTLIB::UDIV_I8, "__aeabi_uidiv");
406 setLibcallName(RTLIB::UDIV_I16, "__aeabi_uidiv");
407 setLibcallName(RTLIB::UDIV_I32, "__aeabi_uidiv");
408 setLibcallName(RTLIB::UDIV_I64, "__aeabi_uldivmod");
409 setLibcallCallingConv(RTLIB::SDIV_I8, CallingConv::ARM_AAPCS);
410 setLibcallCallingConv(RTLIB::SDIV_I16, CallingConv::ARM_AAPCS);
411 setLibcallCallingConv(RTLIB::SDIV_I32, CallingConv::ARM_AAPCS);
412 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::ARM_AAPCS);
413 setLibcallCallingConv(RTLIB::UDIV_I8, CallingConv::ARM_AAPCS);
414 setLibcallCallingConv(RTLIB::UDIV_I16, CallingConv::ARM_AAPCS);
415 setLibcallCallingConv(RTLIB::UDIV_I32, CallingConv::ARM_AAPCS);
416 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::ARM_AAPCS);
419 // RTABI chapter 4.3.4
420 setLibcallName(RTLIB::MEMCPY, "__aeabi_memcpy");
421 setLibcallName(RTLIB::MEMMOVE, "__aeabi_memmove");
422 setLibcallName(RTLIB::MEMSET, "__aeabi_memset");
423 setLibcallCallingConv(RTLIB::MEMCPY, CallingConv::ARM_AAPCS);
424 setLibcallCallingConv(RTLIB::MEMMOVE, CallingConv::ARM_AAPCS);
425 setLibcallCallingConv(RTLIB::MEMSET, CallingConv::ARM_AAPCS);
428 // Use divmod compiler-rt calls for iOS 5.0 and later.
429 if (Subtarget->getTargetTriple().getOS() == Triple::IOS &&
430 !Subtarget->getTargetTriple().isOSVersionLT(5, 0)) {
431 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
432 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
435 if (Subtarget->isThumb1Only())
436 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
438 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
439 if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
440 !Subtarget->isThumb1Only()) {
441 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
442 if (!Subtarget->isFPOnlySP())
443 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
445 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
448 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
449 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
450 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
451 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
452 setTruncStoreAction((MVT::SimpleValueType)VT,
453 (MVT::SimpleValueType)InnerVT, Expand);
454 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
455 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
456 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
459 if (Subtarget->hasNEON()) {
460 addDRTypeForNEON(MVT::v2f32);
461 addDRTypeForNEON(MVT::v8i8);
462 addDRTypeForNEON(MVT::v4i16);
463 addDRTypeForNEON(MVT::v2i32);
464 addDRTypeForNEON(MVT::v1i64);
466 addQRTypeForNEON(MVT::v4f32);
467 addQRTypeForNEON(MVT::v2f64);
468 addQRTypeForNEON(MVT::v16i8);
469 addQRTypeForNEON(MVT::v8i16);
470 addQRTypeForNEON(MVT::v4i32);
471 addQRTypeForNEON(MVT::v2i64);
473 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
474 // neither Neon nor VFP support any arithmetic operations on it.
475 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
476 // supported for v4f32.
477 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
478 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
479 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
480 // FIXME: Code duplication: FDIV and FREM are expanded always, see
481 // ARMTargetLowering::addTypeForNEON method for details.
482 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
483 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
484 // FIXME: Create unittest.
485 // In another words, find a way when "copysign" appears in DAG with vector
487 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
488 // FIXME: Code duplication: SETCC has custom operation action, see
489 // ARMTargetLowering::addTypeForNEON method for details.
490 setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
491 // FIXME: Create unittest for FNEG and for FABS.
492 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
493 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
494 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
495 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
496 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
497 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
498 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
499 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
500 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
501 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
502 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
503 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
504 // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR.
505 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
506 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
507 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
508 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
509 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
511 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
512 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
513 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
514 setOperationAction(ISD::FPOWI, MVT::v4f32, Expand);
515 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
516 setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
517 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
518 setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
519 setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
520 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
522 // Neon does not support some operations on v1i64 and v2i64 types.
523 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
524 // Custom handling for some quad-vector types to detect VMULL.
525 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
526 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
527 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
528 // Custom handling for some vector types to avoid expensive expansions
529 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
530 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
531 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
532 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
533 setOperationAction(ISD::SETCC, MVT::v1i64, Expand);
534 setOperationAction(ISD::SETCC, MVT::v2i64, Expand);
535 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
536 // a destination type that is wider than the source.
537 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
538 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
540 setTargetDAGCombine(ISD::INTRINSIC_VOID);
541 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
542 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
543 setTargetDAGCombine(ISD::SHL);
544 setTargetDAGCombine(ISD::SRL);
545 setTargetDAGCombine(ISD::SRA);
546 setTargetDAGCombine(ISD::SIGN_EXTEND);
547 setTargetDAGCombine(ISD::ZERO_EXTEND);
548 setTargetDAGCombine(ISD::ANY_EXTEND);
549 setTargetDAGCombine(ISD::SELECT_CC);
550 setTargetDAGCombine(ISD::BUILD_VECTOR);
551 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
552 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
553 setTargetDAGCombine(ISD::STORE);
554 setTargetDAGCombine(ISD::FP_TO_SINT);
555 setTargetDAGCombine(ISD::FP_TO_UINT);
556 setTargetDAGCombine(ISD::FDIV);
558 setLoadExtAction(ISD::EXTLOAD, MVT::v4i8, Expand);
561 computeRegisterProperties();
563 // ARM does not have f32 extending load.
564 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
566 // ARM does not have i1 sign extending load.
567 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
569 // ARM supports all 4 flavors of integer indexed load / store.
570 if (!Subtarget->isThumb1Only()) {
571 for (unsigned im = (unsigned)ISD::PRE_INC;
572 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
573 setIndexedLoadAction(im, MVT::i1, Legal);
574 setIndexedLoadAction(im, MVT::i8, Legal);
575 setIndexedLoadAction(im, MVT::i16, Legal);
576 setIndexedLoadAction(im, MVT::i32, Legal);
577 setIndexedStoreAction(im, MVT::i1, Legal);
578 setIndexedStoreAction(im, MVT::i8, Legal);
579 setIndexedStoreAction(im, MVT::i16, Legal);
580 setIndexedStoreAction(im, MVT::i32, Legal);
584 // i64 operation support.
585 setOperationAction(ISD::MUL, MVT::i64, Expand);
586 setOperationAction(ISD::MULHU, MVT::i32, Expand);
587 if (Subtarget->isThumb1Only()) {
588 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
589 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
591 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
592 || (Subtarget->isThumb2() && !Subtarget->hasThumb2DSP()))
593 setOperationAction(ISD::MULHS, MVT::i32, Expand);
595 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
596 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
597 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
598 setOperationAction(ISD::SRL, MVT::i64, Custom);
599 setOperationAction(ISD::SRA, MVT::i64, Custom);
601 if (!Subtarget->isThumb1Only()) {
602 // FIXME: We should do this for Thumb1 as well.
603 setOperationAction(ISD::ADDC, MVT::i32, Custom);
604 setOperationAction(ISD::ADDE, MVT::i32, Custom);
605 setOperationAction(ISD::SUBC, MVT::i32, Custom);
606 setOperationAction(ISD::SUBE, MVT::i32, Custom);
609 // ARM does not have ROTL.
610 setOperationAction(ISD::ROTL, MVT::i32, Expand);
611 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
612 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
613 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
614 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
616 // These just redirect to CTTZ and CTLZ on ARM.
617 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i32 , Expand);
618 setOperationAction(ISD::CTLZ_ZERO_UNDEF , MVT::i32 , Expand);
620 // Only ARMv6 has BSWAP.
621 if (!Subtarget->hasV6Ops())
622 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
624 // These are expanded into libcalls.
625 if (!Subtarget->hasDivide() || !Subtarget->isThumb2()) {
626 // v7M has a hardware divider
627 setOperationAction(ISD::SDIV, MVT::i32, Expand);
628 setOperationAction(ISD::UDIV, MVT::i32, Expand);
630 setOperationAction(ISD::SREM, MVT::i32, Expand);
631 setOperationAction(ISD::UREM, MVT::i32, Expand);
632 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
633 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
635 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
636 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
637 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
638 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
639 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
641 setOperationAction(ISD::TRAP, MVT::Other, Legal);
643 // Use the default implementation.
644 setOperationAction(ISD::VASTART, MVT::Other, Custom);
645 setOperationAction(ISD::VAARG, MVT::Other, Expand);
646 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
647 setOperationAction(ISD::VAEND, MVT::Other, Expand);
648 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
649 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
650 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
651 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
652 setExceptionPointerRegister(ARM::R0);
653 setExceptionSelectorRegister(ARM::R1);
655 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
656 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
657 // the default expansion.
658 // FIXME: This should be checking for v6k, not just v6.
659 if (Subtarget->hasDataBarrier() ||
660 (Subtarget->hasV6Ops() && !Subtarget->isThumb())) {
661 // membarrier needs custom lowering; the rest are legal and handled
663 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
664 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
665 // Custom lowering for 64-bit ops
666 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
667 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
668 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
669 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
670 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
671 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
672 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
673 // Automatically insert fences (dmb ist) around ATOMIC_SWAP etc.
674 setInsertFencesForAtomic(true);
676 // Set them all for expansion, which will force libcalls.
677 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
678 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
679 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
680 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
681 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
682 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
683 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
684 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
685 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
686 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
687 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
688 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
689 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
690 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
691 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the
692 // Unordered/Monotonic case.
693 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
694 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
695 // Since the libcalls include locking, fold in the fences
696 setShouldFoldAtomicFences(true);
699 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
701 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
702 if (!Subtarget->hasV6Ops()) {
703 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
704 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
706 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
708 if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
709 !Subtarget->isThumb1Only()) {
710 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
711 // iff target supports vfp2.
712 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
713 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
716 // We want to custom lower some of our intrinsics.
717 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
718 if (Subtarget->isTargetDarwin()) {
719 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
720 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
721 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
724 setOperationAction(ISD::SETCC, MVT::i32, Expand);
725 setOperationAction(ISD::SETCC, MVT::f32, Expand);
726 setOperationAction(ISD::SETCC, MVT::f64, Expand);
727 setOperationAction(ISD::SELECT, MVT::i32, Custom);
728 setOperationAction(ISD::SELECT, MVT::f32, Custom);
729 setOperationAction(ISD::SELECT, MVT::f64, Custom);
730 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
731 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
732 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
734 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
735 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
736 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
737 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
738 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
740 // We don't support sin/cos/fmod/copysign/pow
741 setOperationAction(ISD::FSIN, MVT::f64, Expand);
742 setOperationAction(ISD::FSIN, MVT::f32, Expand);
743 setOperationAction(ISD::FCOS, MVT::f32, Expand);
744 setOperationAction(ISD::FCOS, MVT::f64, Expand);
745 setOperationAction(ISD::FREM, MVT::f64, Expand);
746 setOperationAction(ISD::FREM, MVT::f32, Expand);
747 if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
748 !Subtarget->isThumb1Only()) {
749 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
750 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
752 setOperationAction(ISD::FPOW, MVT::f64, Expand);
753 setOperationAction(ISD::FPOW, MVT::f32, Expand);
755 setOperationAction(ISD::FMA, MVT::f64, Expand);
756 setOperationAction(ISD::FMA, MVT::f32, Expand);
758 // Various VFP goodness
759 if (!TM.Options.UseSoftFloat && !Subtarget->isThumb1Only()) {
760 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
761 if (Subtarget->hasVFP2()) {
762 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
763 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
764 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
765 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
767 // Special handling for half-precision FP.
768 if (!Subtarget->hasFP16()) {
769 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
770 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand);
774 // We have target-specific dag combine patterns for the following nodes:
775 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
776 setTargetDAGCombine(ISD::ADD);
777 setTargetDAGCombine(ISD::SUB);
778 setTargetDAGCombine(ISD::MUL);
780 if (Subtarget->hasV6T2Ops() || Subtarget->hasNEON())
781 setTargetDAGCombine(ISD::OR);
782 if (Subtarget->hasNEON())
783 setTargetDAGCombine(ISD::AND);
785 setStackPointerRegisterToSaveRestore(ARM::SP);
787 if (TM.Options.UseSoftFloat || Subtarget->isThumb1Only() ||
788 !Subtarget->hasVFP2())
789 setSchedulingPreference(Sched::RegPressure);
791 setSchedulingPreference(Sched::Hybrid);
793 //// temporary - rewrite interface to use type
794 maxStoresPerMemcpy = maxStoresPerMemcpyOptSize = 1;
795 maxStoresPerMemset = 16;
796 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
798 // On ARM arguments smaller than 4 bytes are extended, so all arguments
799 // are at least 4 bytes aligned.
800 setMinStackArgumentAlignment(4);
802 benefitFromCodePlacementOpt = true;
804 setMinFunctionAlignment(Subtarget->isThumb() ? 1 : 2);
807 // FIXME: It might make sense to define the representative register class as the
808 // nearest super-register that has a non-null superset. For example, DPR_VFP2 is
809 // a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
810 // SPR's representative would be DPR_VFP2. This should work well if register
811 // pressure tracking were modified such that a register use would increment the
812 // pressure of the register class's representative and all of it's super
813 // classes' representatives transitively. We have not implemented this because
814 // of the difficulty prior to coalescing of modeling operand register classes
815 // due to the common occurrence of cross class copies and subregister insertions
817 std::pair<const TargetRegisterClass*, uint8_t>
818 ARMTargetLowering::findRepresentativeClass(EVT VT) const{
819 const TargetRegisterClass *RRC = 0;
821 switch (VT.getSimpleVT().SimpleTy) {
823 return TargetLowering::findRepresentativeClass(VT);
824 // Use DPR as representative register class for all floating point
825 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
826 // the cost is 1 for both f32 and f64.
827 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
828 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
829 RRC = ARM::DPRRegisterClass;
830 // When NEON is used for SP, only half of the register file is available
831 // because operations that define both SP and DP results will be constrained
832 // to the VFP2 class (D0-D15). We currently model this constraint prior to
833 // coalescing by double-counting the SP regs. See the FIXME above.
834 if (Subtarget->useNEONForSinglePrecisionFP())
837 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
838 case MVT::v4f32: case MVT::v2f64:
839 RRC = ARM::DPRRegisterClass;
843 RRC = ARM::DPRRegisterClass;
847 RRC = ARM::DPRRegisterClass;
851 return std::make_pair(RRC, Cost);
854 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
857 case ARMISD::Wrapper: return "ARMISD::Wrapper";
858 case ARMISD::WrapperDYN: return "ARMISD::WrapperDYN";
859 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
860 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
861 case ARMISD::CALL: return "ARMISD::CALL";
862 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
863 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
864 case ARMISD::tCALL: return "ARMISD::tCALL";
865 case ARMISD::BRCOND: return "ARMISD::BRCOND";
866 case ARMISD::BR_JT: return "ARMISD::BR_JT";
867 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
868 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
869 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
870 case ARMISD::CMP: return "ARMISD::CMP";
871 case ARMISD::CMPZ: return "ARMISD::CMPZ";
872 case ARMISD::CMPFP: return "ARMISD::CMPFP";
873 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
874 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
875 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
876 case ARMISD::CMOV: return "ARMISD::CMOV";
878 case ARMISD::RBIT: return "ARMISD::RBIT";
880 case ARMISD::FTOSI: return "ARMISD::FTOSI";
881 case ARMISD::FTOUI: return "ARMISD::FTOUI";
882 case ARMISD::SITOF: return "ARMISD::SITOF";
883 case ARMISD::UITOF: return "ARMISD::UITOF";
885 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
886 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
887 case ARMISD::RRX: return "ARMISD::RRX";
889 case ARMISD::ADDC: return "ARMISD::ADDC";
890 case ARMISD::ADDE: return "ARMISD::ADDE";
891 case ARMISD::SUBC: return "ARMISD::SUBC";
892 case ARMISD::SUBE: return "ARMISD::SUBE";
894 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
895 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
897 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
898 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
900 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
902 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
904 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
906 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER";
907 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
909 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
911 case ARMISD::VCEQ: return "ARMISD::VCEQ";
912 case ARMISD::VCEQZ: return "ARMISD::VCEQZ";
913 case ARMISD::VCGE: return "ARMISD::VCGE";
914 case ARMISD::VCGEZ: return "ARMISD::VCGEZ";
915 case ARMISD::VCLEZ: return "ARMISD::VCLEZ";
916 case ARMISD::VCGEU: return "ARMISD::VCGEU";
917 case ARMISD::VCGT: return "ARMISD::VCGT";
918 case ARMISD::VCGTZ: return "ARMISD::VCGTZ";
919 case ARMISD::VCLTZ: return "ARMISD::VCLTZ";
920 case ARMISD::VCGTU: return "ARMISD::VCGTU";
921 case ARMISD::VTST: return "ARMISD::VTST";
923 case ARMISD::VSHL: return "ARMISD::VSHL";
924 case ARMISD::VSHRs: return "ARMISD::VSHRs";
925 case ARMISD::VSHRu: return "ARMISD::VSHRu";
926 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
927 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
928 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
929 case ARMISD::VSHRN: return "ARMISD::VSHRN";
930 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
931 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
932 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
933 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
934 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
935 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
936 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
937 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
938 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
939 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
940 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
941 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
942 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
943 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
944 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
945 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
946 case ARMISD::VMOVFPIMM: return "ARMISD::VMOVFPIMM";
947 case ARMISD::VDUP: return "ARMISD::VDUP";
948 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
949 case ARMISD::VEXT: return "ARMISD::VEXT";
950 case ARMISD::VREV64: return "ARMISD::VREV64";
951 case ARMISD::VREV32: return "ARMISD::VREV32";
952 case ARMISD::VREV16: return "ARMISD::VREV16";
953 case ARMISD::VZIP: return "ARMISD::VZIP";
954 case ARMISD::VUZP: return "ARMISD::VUZP";
955 case ARMISD::VTRN: return "ARMISD::VTRN";
956 case ARMISD::VTBL1: return "ARMISD::VTBL1";
957 case ARMISD::VTBL2: return "ARMISD::VTBL2";
958 case ARMISD::VMULLs: return "ARMISD::VMULLs";
959 case ARMISD::VMULLu: return "ARMISD::VMULLu";
960 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
961 case ARMISD::FMAX: return "ARMISD::FMAX";
962 case ARMISD::FMIN: return "ARMISD::FMIN";
963 case ARMISD::BFI: return "ARMISD::BFI";
964 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
965 case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
966 case ARMISD::VBSL: return "ARMISD::VBSL";
967 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
968 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
969 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
970 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD";
971 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD";
972 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD";
973 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD";
974 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD";
975 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD";
976 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD";
977 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD";
978 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD";
979 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD";
980 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD";
981 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD";
982 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD";
983 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD";
984 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD";
985 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD";
986 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD";
990 EVT ARMTargetLowering::getSetCCResultType(EVT VT) const {
991 if (!VT.isVector()) return getPointerTy();
992 return VT.changeVectorElementTypeToInteger();
995 /// getRegClassFor - Return the register class that should be used for the
996 /// specified value type.
997 TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const {
998 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
999 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
1000 // load / store 4 to 8 consecutive D registers.
1001 if (Subtarget->hasNEON()) {
1002 if (VT == MVT::v4i64)
1003 return ARM::QQPRRegisterClass;
1004 else if (VT == MVT::v8i64)
1005 return ARM::QQQQPRRegisterClass;
1007 return TargetLowering::getRegClassFor(VT);
1010 // Create a fast isel object.
1012 ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
1013 return ARM::createFastISel(funcInfo);
1016 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
1017 /// be used for loads / stores from the global.
1018 unsigned ARMTargetLowering::getMaximalGlobalOffset() const {
1019 return (Subtarget->isThumb1Only() ? 127 : 4095);
1022 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
1023 unsigned NumVals = N->getNumValues();
1025 return Sched::RegPressure;
1027 for (unsigned i = 0; i != NumVals; ++i) {
1028 EVT VT = N->getValueType(i);
1029 if (VT == MVT::Glue || VT == MVT::Other)
1031 if (VT.isFloatingPoint() || VT.isVector())
1035 if (!N->isMachineOpcode())
1036 return Sched::RegPressure;
1038 // Load are scheduled for latency even if there instruction itinerary
1039 // is not available.
1040 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1041 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1043 if (MCID.getNumDefs() == 0)
1044 return Sched::RegPressure;
1045 if (!Itins->isEmpty() &&
1046 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
1049 return Sched::RegPressure;
1052 //===----------------------------------------------------------------------===//
1054 //===----------------------------------------------------------------------===//
1056 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
1057 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
1059 default: llvm_unreachable("Unknown condition code!");
1060 case ISD::SETNE: return ARMCC::NE;
1061 case ISD::SETEQ: return ARMCC::EQ;
1062 case ISD::SETGT: return ARMCC::GT;
1063 case ISD::SETGE: return ARMCC::GE;
1064 case ISD::SETLT: return ARMCC::LT;
1065 case ISD::SETLE: return ARMCC::LE;
1066 case ISD::SETUGT: return ARMCC::HI;
1067 case ISD::SETUGE: return ARMCC::HS;
1068 case ISD::SETULT: return ARMCC::LO;
1069 case ISD::SETULE: return ARMCC::LS;
1073 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
1074 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
1075 ARMCC::CondCodes &CondCode2) {
1076 CondCode2 = ARMCC::AL;
1078 default: llvm_unreachable("Unknown FP condition!");
1080 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
1082 case ISD::SETOGT: CondCode = ARMCC::GT; break;
1084 case ISD::SETOGE: CondCode = ARMCC::GE; break;
1085 case ISD::SETOLT: CondCode = ARMCC::MI; break;
1086 case ISD::SETOLE: CondCode = ARMCC::LS; break;
1087 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
1088 case ISD::SETO: CondCode = ARMCC::VC; break;
1089 case ISD::SETUO: CondCode = ARMCC::VS; break;
1090 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
1091 case ISD::SETUGT: CondCode = ARMCC::HI; break;
1092 case ISD::SETUGE: CondCode = ARMCC::PL; break;
1094 case ISD::SETULT: CondCode = ARMCC::LT; break;
1096 case ISD::SETULE: CondCode = ARMCC::LE; break;
1098 case ISD::SETUNE: CondCode = ARMCC::NE; break;
1102 //===----------------------------------------------------------------------===//
1103 // Calling Convention Implementation
1104 //===----------------------------------------------------------------------===//
1106 #include "ARMGenCallingConv.inc"
1108 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1109 /// given CallingConvention value.
1110 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
1112 bool isVarArg) const {
1115 llvm_unreachable("Unsupported calling convention");
1116 case CallingConv::Fast:
1117 if (Subtarget->hasVFP2() && !isVarArg) {
1118 if (!Subtarget->isAAPCS_ABI())
1119 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1120 // For AAPCS ABI targets, just use VFP variant of the calling convention.
1121 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1124 case CallingConv::C: {
1125 // Use target triple & subtarget features to do actual dispatch.
1126 if (!Subtarget->isAAPCS_ABI())
1127 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1128 else if (Subtarget->hasVFP2() &&
1129 getTargetMachine().Options.FloatABIType == FloatABI::Hard &&
1131 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1132 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1134 case CallingConv::ARM_AAPCS_VFP:
1136 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1138 case CallingConv::ARM_AAPCS:
1139 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1140 case CallingConv::ARM_APCS:
1141 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1145 /// LowerCallResult - Lower the result values of a call into the
1146 /// appropriate copies out of appropriate physical registers.
1148 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1149 CallingConv::ID CallConv, bool isVarArg,
1150 const SmallVectorImpl<ISD::InputArg> &Ins,
1151 DebugLoc dl, SelectionDAG &DAG,
1152 SmallVectorImpl<SDValue> &InVals) const {
1154 // Assign locations to each value returned by this call.
1155 SmallVector<CCValAssign, 16> RVLocs;
1156 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1157 getTargetMachine(), RVLocs, *DAG.getContext(), Call);
1158 CCInfo.AnalyzeCallResult(Ins,
1159 CCAssignFnForNode(CallConv, /* Return*/ true,
1162 // Copy all of the result registers out of their specified physreg.
1163 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1164 CCValAssign VA = RVLocs[i];
1167 if (VA.needsCustom()) {
1168 // Handle f64 or half of a v2f64.
1169 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1171 Chain = Lo.getValue(1);
1172 InFlag = Lo.getValue(2);
1173 VA = RVLocs[++i]; // skip ahead to next loc
1174 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1176 Chain = Hi.getValue(1);
1177 InFlag = Hi.getValue(2);
1178 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1180 if (VA.getLocVT() == MVT::v2f64) {
1181 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1182 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1183 DAG.getConstant(0, MVT::i32));
1185 VA = RVLocs[++i]; // skip ahead to next loc
1186 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1187 Chain = Lo.getValue(1);
1188 InFlag = Lo.getValue(2);
1189 VA = RVLocs[++i]; // skip ahead to next loc
1190 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1191 Chain = Hi.getValue(1);
1192 InFlag = Hi.getValue(2);
1193 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1194 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1195 DAG.getConstant(1, MVT::i32));
1198 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1200 Chain = Val.getValue(1);
1201 InFlag = Val.getValue(2);
1204 switch (VA.getLocInfo()) {
1205 default: llvm_unreachable("Unknown loc info!");
1206 case CCValAssign::Full: break;
1207 case CCValAssign::BCvt:
1208 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1212 InVals.push_back(Val);
1218 /// LowerMemOpCallTo - Store the argument to the stack.
1220 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
1221 SDValue StackPtr, SDValue Arg,
1222 DebugLoc dl, SelectionDAG &DAG,
1223 const CCValAssign &VA,
1224 ISD::ArgFlagsTy Flags) const {
1225 unsigned LocMemOffset = VA.getLocMemOffset();
1226 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1227 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1228 return DAG.getStore(Chain, dl, Arg, PtrOff,
1229 MachinePointerInfo::getStack(LocMemOffset),
1233 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
1234 SDValue Chain, SDValue &Arg,
1235 RegsToPassVector &RegsToPass,
1236 CCValAssign &VA, CCValAssign &NextVA,
1238 SmallVector<SDValue, 8> &MemOpChains,
1239 ISD::ArgFlagsTy Flags) const {
1241 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1242 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1243 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
1245 if (NextVA.isRegLoc())
1246 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
1248 assert(NextVA.isMemLoc());
1249 if (StackPtr.getNode() == 0)
1250 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1252 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
1258 /// LowerCall - Lowering a call into a callseq_start <-
1259 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1262 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1263 CallingConv::ID CallConv, bool isVarArg,
1265 const SmallVectorImpl<ISD::OutputArg> &Outs,
1266 const SmallVectorImpl<SDValue> &OutVals,
1267 const SmallVectorImpl<ISD::InputArg> &Ins,
1268 DebugLoc dl, SelectionDAG &DAG,
1269 SmallVectorImpl<SDValue> &InVals) const {
1270 MachineFunction &MF = DAG.getMachineFunction();
1271 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1272 bool IsSibCall = false;
1273 // Disable tail calls if they're not supported.
1274 if (!EnableARMTailCalls && !Subtarget->supportsTailCall())
1277 // Check if it's really possible to do a tail call.
1278 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1279 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1280 Outs, OutVals, Ins, DAG);
1281 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1282 // detected sibcalls.
1289 // Analyze operands of the call, assigning locations to each operand.
1290 SmallVector<CCValAssign, 16> ArgLocs;
1291 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1292 getTargetMachine(), ArgLocs, *DAG.getContext(), Call);
1293 CCInfo.AnalyzeCallOperands(Outs,
1294 CCAssignFnForNode(CallConv, /* Return*/ false,
1297 // Get a count of how many bytes are to be pushed on the stack.
1298 unsigned NumBytes = CCInfo.getNextStackOffset();
1300 // For tail calls, memory operands are available in our caller's stack.
1304 // Adjust the stack pointer for the new arguments...
1305 // These operations are automatically eliminated by the prolog/epilog pass
1307 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1309 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1311 RegsToPassVector RegsToPass;
1312 SmallVector<SDValue, 8> MemOpChains;
1314 // Walk the register/memloc assignments, inserting copies/loads. In the case
1315 // of tail call optimization, arguments are handled later.
1316 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1318 ++i, ++realArgIdx) {
1319 CCValAssign &VA = ArgLocs[i];
1320 SDValue Arg = OutVals[realArgIdx];
1321 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1322 bool isByVal = Flags.isByVal();
1324 // Promote the value if needed.
1325 switch (VA.getLocInfo()) {
1326 default: llvm_unreachable("Unknown loc info!");
1327 case CCValAssign::Full: break;
1328 case CCValAssign::SExt:
1329 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1331 case CCValAssign::ZExt:
1332 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1334 case CCValAssign::AExt:
1335 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1337 case CCValAssign::BCvt:
1338 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1342 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1343 if (VA.needsCustom()) {
1344 if (VA.getLocVT() == MVT::v2f64) {
1345 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1346 DAG.getConstant(0, MVT::i32));
1347 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1348 DAG.getConstant(1, MVT::i32));
1350 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1351 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1353 VA = ArgLocs[++i]; // skip ahead to next loc
1354 if (VA.isRegLoc()) {
1355 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1356 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1358 assert(VA.isMemLoc());
1360 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1361 dl, DAG, VA, Flags));
1364 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1365 StackPtr, MemOpChains, Flags);
1367 } else if (VA.isRegLoc()) {
1368 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1369 } else if (isByVal) {
1370 assert(VA.isMemLoc());
1371 unsigned offset = 0;
1373 // True if this byval aggregate will be split between registers
1375 if (CCInfo.isFirstByValRegValid()) {
1376 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1378 for (i = 0, j = CCInfo.getFirstByValReg(); j < ARM::R4; i++, j++) {
1379 SDValue Const = DAG.getConstant(4*i, MVT::i32);
1380 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
1381 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
1382 MachinePointerInfo(),
1383 false, false, false, 0);
1384 MemOpChains.push_back(Load.getValue(1));
1385 RegsToPass.push_back(std::make_pair(j, Load));
1387 offset = ARM::R4 - CCInfo.getFirstByValReg();
1388 CCInfo.clearFirstByValReg();
1391 unsigned LocMemOffset = VA.getLocMemOffset();
1392 SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset);
1393 SDValue Dst = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr,
1395 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset);
1396 SDValue Src = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg, SrcOffset);
1397 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset,
1399 MemOpChains.push_back(DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode,
1400 Flags.getByValAlign(),
1401 /*isVolatile=*/false,
1402 /*AlwaysInline=*/false,
1403 MachinePointerInfo(0),
1404 MachinePointerInfo(0)));
1406 } else if (!IsSibCall) {
1407 assert(VA.isMemLoc());
1409 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1410 dl, DAG, VA, Flags));
1414 if (!MemOpChains.empty())
1415 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1416 &MemOpChains[0], MemOpChains.size());
1418 // Build a sequence of copy-to-reg nodes chained together with token chain
1419 // and flag operands which copy the outgoing args into the appropriate regs.
1421 // Tail call byval lowering might overwrite argument registers so in case of
1422 // tail call optimization the copies to registers are lowered later.
1424 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1425 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1426 RegsToPass[i].second, InFlag);
1427 InFlag = Chain.getValue(1);
1430 // For tail calls lower the arguments to the 'real' stack slot.
1432 // Force all the incoming stack arguments to be loaded from the stack
1433 // before any new outgoing arguments are stored to the stack, because the
1434 // outgoing stack slots may alias the incoming argument stack slots, and
1435 // the alias isn't otherwise explicit. This is slightly more conservative
1436 // than necessary, because it means that each store effectively depends
1437 // on every argument instead of just those arguments it would clobber.
1439 // Do not flag preceding copytoreg stuff together with the following stuff.
1441 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1442 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1443 RegsToPass[i].second, InFlag);
1444 InFlag = Chain.getValue(1);
1449 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1450 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1451 // node so that legalize doesn't hack it.
1452 bool isDirect = false;
1453 bool isARMFunc = false;
1454 bool isLocalARMFunc = false;
1455 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1457 if (EnableARMLongCalls) {
1458 assert (getTargetMachine().getRelocationModel() == Reloc::Static
1459 && "long-calls with non-static relocation model!");
1460 // Handle a global address or an external symbol. If it's not one of
1461 // those, the target's already in a register, so we don't need to do
1463 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1464 const GlobalValue *GV = G->getGlobal();
1465 // Create a constant pool entry for the callee address
1466 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1467 ARMConstantPoolValue *CPV =
1468 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0);
1470 // Get the address of the callee into a register
1471 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1472 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1473 Callee = DAG.getLoad(getPointerTy(), dl,
1474 DAG.getEntryNode(), CPAddr,
1475 MachinePointerInfo::getConstantPool(),
1476 false, false, false, 0);
1477 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1478 const char *Sym = S->getSymbol();
1480 // Create a constant pool entry for the callee address
1481 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1482 ARMConstantPoolValue *CPV =
1483 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
1484 ARMPCLabelIndex, 0);
1485 // Get the address of the callee into a register
1486 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1487 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1488 Callee = DAG.getLoad(getPointerTy(), dl,
1489 DAG.getEntryNode(), CPAddr,
1490 MachinePointerInfo::getConstantPool(),
1491 false, false, false, 0);
1493 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1494 const GlobalValue *GV = G->getGlobal();
1496 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1497 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
1498 getTargetMachine().getRelocationModel() != Reloc::Static;
1499 isARMFunc = !Subtarget->isThumb() || isStub;
1500 // ARM call to a local ARM function is predicable.
1501 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
1502 // tBX takes a register source operand.
1503 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1504 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1505 ARMConstantPoolValue *CPV =
1506 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 4);
1507 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1508 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1509 Callee = DAG.getLoad(getPointerTy(), dl,
1510 DAG.getEntryNode(), CPAddr,
1511 MachinePointerInfo::getConstantPool(),
1512 false, false, false, 0);
1513 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1514 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1515 getPointerTy(), Callee, PICLabel);
1517 // On ELF targets for PIC code, direct calls should go through the PLT
1518 unsigned OpFlags = 0;
1519 if (Subtarget->isTargetELF() &&
1520 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1521 OpFlags = ARMII::MO_PLT;
1522 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
1524 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1526 bool isStub = Subtarget->isTargetDarwin() &&
1527 getTargetMachine().getRelocationModel() != Reloc::Static;
1528 isARMFunc = !Subtarget->isThumb() || isStub;
1529 // tBX takes a register source operand.
1530 const char *Sym = S->getSymbol();
1531 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1532 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1533 ARMConstantPoolValue *CPV =
1534 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
1535 ARMPCLabelIndex, 4);
1536 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1537 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1538 Callee = DAG.getLoad(getPointerTy(), dl,
1539 DAG.getEntryNode(), CPAddr,
1540 MachinePointerInfo::getConstantPool(),
1541 false, false, false, 0);
1542 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1543 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1544 getPointerTy(), Callee, PICLabel);
1546 unsigned OpFlags = 0;
1547 // On ELF targets for PIC code, direct calls should go through the PLT
1548 if (Subtarget->isTargetELF() &&
1549 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1550 OpFlags = ARMII::MO_PLT;
1551 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags);
1555 // FIXME: handle tail calls differently.
1557 if (Subtarget->isThumb()) {
1558 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1559 CallOpc = ARMISD::CALL_NOLINK;
1561 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1563 CallOpc = (isDirect || Subtarget->hasV5TOps())
1564 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
1565 : ARMISD::CALL_NOLINK;
1568 std::vector<SDValue> Ops;
1569 Ops.push_back(Chain);
1570 Ops.push_back(Callee);
1572 // Add argument registers to the end of the list so that they are known live
1574 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1575 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1576 RegsToPass[i].second.getValueType()));
1578 if (InFlag.getNode())
1579 Ops.push_back(InFlag);
1581 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1583 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
1585 // Returns a chain and a flag for retval copy to use.
1586 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
1587 InFlag = Chain.getValue(1);
1589 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1590 DAG.getIntPtrConstant(0, true), InFlag);
1592 InFlag = Chain.getValue(1);
1594 // Handle result values, copying them out of physregs into vregs that we
1596 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1600 /// HandleByVal - Every parameter *after* a byval parameter is passed
1601 /// on the stack. Remember the next parameter register to allocate,
1602 /// and then confiscate the rest of the parameter registers to insure
1605 llvm::ARMTargetLowering::HandleByVal(CCState *State, unsigned &size) const {
1606 unsigned reg = State->AllocateReg(GPRArgRegs, 4);
1607 assert((State->getCallOrPrologue() == Prologue ||
1608 State->getCallOrPrologue() == Call) &&
1609 "unhandled ParmContext");
1610 if ((!State->isFirstByValRegValid()) &&
1611 (ARM::R0 <= reg) && (reg <= ARM::R3)) {
1612 State->setFirstByValReg(reg);
1613 // At a call site, a byval parameter that is split between
1614 // registers and memory needs its size truncated here. In a
1615 // function prologue, such byval parameters are reassembled in
1616 // memory, and are not truncated.
1617 if (State->getCallOrPrologue() == Call) {
1618 unsigned excess = 4 * (ARM::R4 - reg);
1619 assert(size >= excess && "expected larger existing stack allocation");
1623 // Confiscate any remaining parameter registers to preclude their
1624 // assignment to subsequent parameters.
1625 while (State->AllocateReg(GPRArgRegs, 4))
1629 /// MatchingStackOffset - Return true if the given stack call argument is
1630 /// already available in the same position (relatively) of the caller's
1631 /// incoming argument stack.
1633 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1634 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1635 const ARMInstrInfo *TII) {
1636 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
1638 if (Arg.getOpcode() == ISD::CopyFromReg) {
1639 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
1640 if (!TargetRegisterInfo::isVirtualRegister(VR))
1642 MachineInstr *Def = MRI->getVRegDef(VR);
1645 if (!Flags.isByVal()) {
1646 if (!TII->isLoadFromStackSlot(Def, FI))
1651 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
1652 if (Flags.isByVal())
1653 // ByVal argument is passed in as a pointer but it's now being
1654 // dereferenced. e.g.
1655 // define @foo(%struct.X* %A) {
1656 // tail call @bar(%struct.X* byval %A)
1659 SDValue Ptr = Ld->getBasePtr();
1660 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
1663 FI = FINode->getIndex();
1667 assert(FI != INT_MAX);
1668 if (!MFI->isFixedObjectIndex(FI))
1670 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
1673 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1674 /// for tail call optimization. Targets which want to do tail call
1675 /// optimization should implement this function.
1677 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1678 CallingConv::ID CalleeCC,
1680 bool isCalleeStructRet,
1681 bool isCallerStructRet,
1682 const SmallVectorImpl<ISD::OutputArg> &Outs,
1683 const SmallVectorImpl<SDValue> &OutVals,
1684 const SmallVectorImpl<ISD::InputArg> &Ins,
1685 SelectionDAG& DAG) const {
1686 const Function *CallerF = DAG.getMachineFunction().getFunction();
1687 CallingConv::ID CallerCC = CallerF->getCallingConv();
1688 bool CCMatch = CallerCC == CalleeCC;
1690 // Look for obvious safe cases to perform tail call optimization that do not
1691 // require ABI changes. This is what gcc calls sibcall.
1693 // Do not sibcall optimize vararg calls unless the call site is not passing
1695 if (isVarArg && !Outs.empty())
1698 // Also avoid sibcall optimization if either caller or callee uses struct
1699 // return semantics.
1700 if (isCalleeStructRet || isCallerStructRet)
1703 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
1704 // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
1705 // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
1706 // support in the assembler and linker to be used. This would need to be
1707 // fixed to fully support tail calls in Thumb1.
1709 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
1710 // LR. This means if we need to reload LR, it takes an extra instructions,
1711 // which outweighs the value of the tail call; but here we don't know yet
1712 // whether LR is going to be used. Probably the right approach is to
1713 // generate the tail call here and turn it back into CALL/RET in
1714 // emitEpilogue if LR is used.
1716 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
1717 // but we need to make sure there are enough registers; the only valid
1718 // registers are the 4 used for parameters. We don't currently do this
1720 if (Subtarget->isThumb1Only())
1723 // If the calling conventions do not match, then we'd better make sure the
1724 // results are returned in the same way as what the caller expects.
1726 SmallVector<CCValAssign, 16> RVLocs1;
1727 ARMCCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
1728 getTargetMachine(), RVLocs1, *DAG.getContext(), Call);
1729 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
1731 SmallVector<CCValAssign, 16> RVLocs2;
1732 ARMCCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
1733 getTargetMachine(), RVLocs2, *DAG.getContext(), Call);
1734 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
1736 if (RVLocs1.size() != RVLocs2.size())
1738 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
1739 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
1741 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
1743 if (RVLocs1[i].isRegLoc()) {
1744 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
1747 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
1753 // If the callee takes no arguments then go on to check the results of the
1755 if (!Outs.empty()) {
1756 // Check if stack adjustment is needed. For now, do not do this if any
1757 // argument is passed on the stack.
1758 SmallVector<CCValAssign, 16> ArgLocs;
1759 ARMCCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
1760 getTargetMachine(), ArgLocs, *DAG.getContext(), Call);
1761 CCInfo.AnalyzeCallOperands(Outs,
1762 CCAssignFnForNode(CalleeCC, false, isVarArg));
1763 if (CCInfo.getNextStackOffset()) {
1764 MachineFunction &MF = DAG.getMachineFunction();
1766 // Check if the arguments are already laid out in the right way as
1767 // the caller's fixed stack objects.
1768 MachineFrameInfo *MFI = MF.getFrameInfo();
1769 const MachineRegisterInfo *MRI = &MF.getRegInfo();
1770 const ARMInstrInfo *TII =
1771 ((ARMTargetMachine&)getTargetMachine()).getInstrInfo();
1772 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1774 ++i, ++realArgIdx) {
1775 CCValAssign &VA = ArgLocs[i];
1776 EVT RegVT = VA.getLocVT();
1777 SDValue Arg = OutVals[realArgIdx];
1778 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1779 if (VA.getLocInfo() == CCValAssign::Indirect)
1781 if (VA.needsCustom()) {
1782 // f64 and vector types are split into multiple registers or
1783 // register/stack-slot combinations. The types will not match
1784 // the registers; give up on memory f64 refs until we figure
1785 // out what to do about this.
1788 if (!ArgLocs[++i].isRegLoc())
1790 if (RegVT == MVT::v2f64) {
1791 if (!ArgLocs[++i].isRegLoc())
1793 if (!ArgLocs[++i].isRegLoc())
1796 } else if (!VA.isRegLoc()) {
1797 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
1809 ARMTargetLowering::LowerReturn(SDValue Chain,
1810 CallingConv::ID CallConv, bool isVarArg,
1811 const SmallVectorImpl<ISD::OutputArg> &Outs,
1812 const SmallVectorImpl<SDValue> &OutVals,
1813 DebugLoc dl, SelectionDAG &DAG) const {
1815 // CCValAssign - represent the assignment of the return value to a location.
1816 SmallVector<CCValAssign, 16> RVLocs;
1818 // CCState - Info about the registers and stack slots.
1819 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1820 getTargetMachine(), RVLocs, *DAG.getContext(), Call);
1822 // Analyze outgoing return values.
1823 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1826 // If this is the first return lowered for this function, add
1827 // the regs to the liveout set for the function.
1828 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1829 for (unsigned i = 0; i != RVLocs.size(); ++i)
1830 if (RVLocs[i].isRegLoc())
1831 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1836 // Copy the result values into the output registers.
1837 for (unsigned i = 0, realRVLocIdx = 0;
1839 ++i, ++realRVLocIdx) {
1840 CCValAssign &VA = RVLocs[i];
1841 assert(VA.isRegLoc() && "Can only return in registers!");
1843 SDValue Arg = OutVals[realRVLocIdx];
1845 switch (VA.getLocInfo()) {
1846 default: llvm_unreachable("Unknown loc info!");
1847 case CCValAssign::Full: break;
1848 case CCValAssign::BCvt:
1849 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1853 if (VA.needsCustom()) {
1854 if (VA.getLocVT() == MVT::v2f64) {
1855 // Extract the first half and return it in two registers.
1856 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1857 DAG.getConstant(0, MVT::i32));
1858 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
1859 DAG.getVTList(MVT::i32, MVT::i32), Half);
1861 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1862 Flag = Chain.getValue(1);
1863 VA = RVLocs[++i]; // skip ahead to next loc
1864 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1865 HalfGPRs.getValue(1), Flag);
1866 Flag = Chain.getValue(1);
1867 VA = RVLocs[++i]; // skip ahead to next loc
1869 // Extract the 2nd half and fall through to handle it as an f64 value.
1870 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1871 DAG.getConstant(1, MVT::i32));
1873 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1875 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1876 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1877 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1878 Flag = Chain.getValue(1);
1879 VA = RVLocs[++i]; // skip ahead to next loc
1880 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1883 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1885 // Guarantee that all emitted copies are
1886 // stuck together, avoiding something bad.
1887 Flag = Chain.getValue(1);
1892 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1894 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1899 bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N) const {
1900 if (N->getNumValues() != 1)
1902 if (!N->hasNUsesOfValue(1, 0))
1905 unsigned NumCopies = 0;
1906 SDNode* Copies[2] = { 0, 0 };
1907 SDNode *Use = *N->use_begin();
1908 if (Use->getOpcode() == ISD::CopyToReg) {
1909 Copies[NumCopies++] = Use;
1910 } else if (Use->getOpcode() == ARMISD::VMOVRRD) {
1911 // f64 returned in a pair of GPRs.
1912 for (SDNode::use_iterator UI = Use->use_begin(), UE = Use->use_end();
1914 if (UI->getOpcode() != ISD::CopyToReg)
1916 Copies[UI.getUse().getResNo()] = *UI;
1919 } else if (Use->getOpcode() == ISD::BITCAST) {
1920 // f32 returned in a single GPR.
1921 if (!Use->hasNUsesOfValue(1, 0))
1923 Use = *Use->use_begin();
1924 if (Use->getOpcode() != ISD::CopyToReg || !Use->hasNUsesOfValue(1, 0))
1926 Copies[NumCopies++] = Use;
1931 if (NumCopies != 1 && NumCopies != 2)
1934 bool HasRet = false;
1935 for (unsigned i = 0; i < NumCopies; ++i) {
1936 SDNode *Copy = Copies[i];
1937 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1939 if (UI->getOpcode() == ISD::CopyToReg) {
1941 if (Use == Copies[0] || ((NumCopies == 2) && (Use == Copies[1])))
1945 if (UI->getOpcode() != ARMISD::RET_FLAG)
1954 bool ARMTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1955 if (!EnableARMTailCalls)
1958 if (!CI->isTailCall())
1961 return !Subtarget->isThumb1Only();
1964 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1965 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1966 // one of the above mentioned nodes. It has to be wrapped because otherwise
1967 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1968 // be used to form addressing mode. These wrapped nodes will be selected
1970 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1971 EVT PtrVT = Op.getValueType();
1972 // FIXME there is no actual debug info here
1973 DebugLoc dl = Op.getDebugLoc();
1974 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1976 if (CP->isMachineConstantPoolEntry())
1977 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1978 CP->getAlignment());
1980 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1981 CP->getAlignment());
1982 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1985 unsigned ARMTargetLowering::getJumpTableEncoding() const {
1986 return MachineJumpTableInfo::EK_Inline;
1989 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
1990 SelectionDAG &DAG) const {
1991 MachineFunction &MF = DAG.getMachineFunction();
1992 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1993 unsigned ARMPCLabelIndex = 0;
1994 DebugLoc DL = Op.getDebugLoc();
1995 EVT PtrVT = getPointerTy();
1996 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1997 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1999 if (RelocM == Reloc::Static) {
2000 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
2002 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2003 ARMPCLabelIndex = AFI->createPICLabelUId();
2004 ARMConstantPoolValue *CPV =
2005 ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex,
2006 ARMCP::CPBlockAddress, PCAdj);
2007 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2009 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
2010 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
2011 MachinePointerInfo::getConstantPool(),
2012 false, false, false, 0);
2013 if (RelocM == Reloc::Static)
2015 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2016 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
2019 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
2021 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
2022 SelectionDAG &DAG) const {
2023 DebugLoc dl = GA->getDebugLoc();
2024 EVT PtrVT = getPointerTy();
2025 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2026 MachineFunction &MF = DAG.getMachineFunction();
2027 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2028 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2029 ARMConstantPoolValue *CPV =
2030 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2031 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
2032 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2033 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
2034 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
2035 MachinePointerInfo::getConstantPool(),
2036 false, false, false, 0);
2037 SDValue Chain = Argument.getValue(1);
2039 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2040 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
2042 // call __tls_get_addr.
2045 Entry.Node = Argument;
2046 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
2047 Args.push_back(Entry);
2048 // FIXME: is there useful debug info available here?
2049 std::pair<SDValue, SDValue> CallResult =
2050 LowerCallTo(Chain, (Type *) Type::getInt32Ty(*DAG.getContext()),
2051 false, false, false, false,
2052 0, CallingConv::C, false, /*isReturnValueUsed=*/true,
2053 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
2054 return CallResult.first;
2057 // Lower ISD::GlobalTLSAddress using the "initial exec" or
2058 // "local exec" model.
2060 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
2061 SelectionDAG &DAG) const {
2062 const GlobalValue *GV = GA->getGlobal();
2063 DebugLoc dl = GA->getDebugLoc();
2065 SDValue Chain = DAG.getEntryNode();
2066 EVT PtrVT = getPointerTy();
2067 // Get the Thread Pointer
2068 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2070 if (GV->isDeclaration()) {
2071 MachineFunction &MF = DAG.getMachineFunction();
2072 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2073 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2074 // Initial exec model.
2075 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2076 ARMConstantPoolValue *CPV =
2077 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2078 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF,
2080 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2081 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2082 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2083 MachinePointerInfo::getConstantPool(),
2084 false, false, false, 0);
2085 Chain = Offset.getValue(1);
2087 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2088 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
2090 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2091 MachinePointerInfo::getConstantPool(),
2092 false, false, false, 0);
2095 ARMConstantPoolValue *CPV =
2096 ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF);
2097 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2098 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2099 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2100 MachinePointerInfo::getConstantPool(),
2101 false, false, false, 0);
2104 // The address of the thread local variable is the add of the thread
2105 // pointer with the offset of the variable.
2106 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
2110 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
2111 // TODO: implement the "local dynamic" model
2112 assert(Subtarget->isTargetELF() &&
2113 "TLS not implemented for non-ELF targets");
2114 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2115 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
2116 // otherwise use the "Local Exec" TLS Model
2117 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
2118 return LowerToTLSGeneralDynamicModel(GA, DAG);
2120 return LowerToTLSExecModels(GA, DAG);
2123 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
2124 SelectionDAG &DAG) const {
2125 EVT PtrVT = getPointerTy();
2126 DebugLoc dl = Op.getDebugLoc();
2127 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2128 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2129 if (RelocM == Reloc::PIC_) {
2130 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
2131 ARMConstantPoolValue *CPV =
2132 ARMConstantPoolConstant::Create(GV,
2133 UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
2134 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2135 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2136 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
2138 MachinePointerInfo::getConstantPool(),
2139 false, false, false, 0);
2140 SDValue Chain = Result.getValue(1);
2141 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
2142 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
2144 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
2145 MachinePointerInfo::getGOT(),
2146 false, false, false, 0);
2150 // If we have T2 ops, we can materialize the address directly via movt/movw
2151 // pair. This is always cheaper.
2152 if (Subtarget->useMovt()) {
2154 // FIXME: Once remat is capable of dealing with instructions with register
2155 // operands, expand this into two nodes.
2156 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2157 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2159 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
2160 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2161 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2162 MachinePointerInfo::getConstantPool(),
2163 false, false, false, 0);
2167 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
2168 SelectionDAG &DAG) const {
2169 EVT PtrVT = getPointerTy();
2170 DebugLoc dl = Op.getDebugLoc();
2171 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2172 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2173 MachineFunction &MF = DAG.getMachineFunction();
2174 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2176 // FIXME: Enable this for static codegen when tool issues are fixed. Also
2177 // update ARMFastISel::ARMMaterializeGV.
2178 if (Subtarget->useMovt() && RelocM != Reloc::Static) {
2180 // FIXME: Once remat is capable of dealing with instructions with register
2181 // operands, expand this into two nodes.
2182 if (RelocM == Reloc::Static)
2183 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2184 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2186 unsigned Wrapper = (RelocM == Reloc::PIC_)
2187 ? ARMISD::WrapperPIC : ARMISD::WrapperDYN;
2188 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT,
2189 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2190 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
2191 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
2192 MachinePointerInfo::getGOT(),
2193 false, false, false, 0);
2197 unsigned ARMPCLabelIndex = 0;
2199 if (RelocM == Reloc::Static) {
2200 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
2202 ARMPCLabelIndex = AFI->createPICLabelUId();
2203 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8);
2204 ARMConstantPoolValue *CPV =
2205 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue,
2207 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2209 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2211 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2212 MachinePointerInfo::getConstantPool(),
2213 false, false, false, 0);
2214 SDValue Chain = Result.getValue(1);
2216 if (RelocM == Reloc::PIC_) {
2217 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2218 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2221 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
2222 Result = DAG.getLoad(PtrVT, dl, Chain, Result, MachinePointerInfo::getGOT(),
2223 false, false, false, 0);
2228 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
2229 SelectionDAG &DAG) const {
2230 assert(Subtarget->isTargetELF() &&
2231 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
2232 MachineFunction &MF = DAG.getMachineFunction();
2233 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2234 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2235 EVT PtrVT = getPointerTy();
2236 DebugLoc dl = Op.getDebugLoc();
2237 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2238 ARMConstantPoolValue *CPV =
2239 ARMConstantPoolSymbol::Create(*DAG.getContext(), "_GLOBAL_OFFSET_TABLE_",
2240 ARMPCLabelIndex, PCAdj);
2241 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2242 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2243 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2244 MachinePointerInfo::getConstantPool(),
2245 false, false, false, 0);
2246 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2247 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2251 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
2252 DebugLoc dl = Op.getDebugLoc();
2253 SDValue Val = DAG.getConstant(0, MVT::i32);
2254 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl,
2255 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
2256 Op.getOperand(1), Val);
2260 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
2261 DebugLoc dl = Op.getDebugLoc();
2262 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
2263 Op.getOperand(1), DAG.getConstant(0, MVT::i32));
2267 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
2268 const ARMSubtarget *Subtarget) const {
2269 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2270 DebugLoc dl = Op.getDebugLoc();
2272 default: return SDValue(); // Don't custom lower most intrinsics.
2273 case Intrinsic::arm_thread_pointer: {
2274 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2275 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2277 case Intrinsic::eh_sjlj_lsda: {
2278 MachineFunction &MF = DAG.getMachineFunction();
2279 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2280 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2281 EVT PtrVT = getPointerTy();
2282 DebugLoc dl = Op.getDebugLoc();
2283 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2285 unsigned PCAdj = (RelocM != Reloc::PIC_)
2286 ? 0 : (Subtarget->isThumb() ? 4 : 8);
2287 ARMConstantPoolValue *CPV =
2288 ARMConstantPoolConstant::Create(MF.getFunction(), ARMPCLabelIndex,
2289 ARMCP::CPLSDA, PCAdj);
2290 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2291 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2293 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2294 MachinePointerInfo::getConstantPool(),
2295 false, false, false, 0);
2297 if (RelocM == Reloc::PIC_) {
2298 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2299 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2303 case Intrinsic::arm_neon_vmulls:
2304 case Intrinsic::arm_neon_vmullu: {
2305 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
2306 ? ARMISD::VMULLs : ARMISD::VMULLu;
2307 return DAG.getNode(NewOpc, Op.getDebugLoc(), Op.getValueType(),
2308 Op.getOperand(1), Op.getOperand(2));
2313 static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG,
2314 const ARMSubtarget *Subtarget) {
2315 DebugLoc dl = Op.getDebugLoc();
2316 if (!Subtarget->hasDataBarrier()) {
2317 // Some ARMv6 cpus can support data barriers with an mcr instruction.
2318 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
2320 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&
2321 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!");
2322 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2323 DAG.getConstant(0, MVT::i32));
2326 SDValue Op5 = Op.getOperand(5);
2327 bool isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue() != 0;
2328 unsigned isLL = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
2329 unsigned isLS = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
2330 bool isOnlyStoreBarrier = (isLL == 0 && isLS == 0);
2332 ARM_MB::MemBOpt DMBOpt;
2333 if (isDeviceBarrier)
2334 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ST : ARM_MB::SY;
2336 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ISHST : ARM_MB::ISH;
2337 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
2338 DAG.getConstant(DMBOpt, MVT::i32));
2342 static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
2343 const ARMSubtarget *Subtarget) {
2344 // FIXME: handle "fence singlethread" more efficiently.
2345 DebugLoc dl = Op.getDebugLoc();
2346 if (!Subtarget->hasDataBarrier()) {
2347 // Some ARMv6 cpus can support data barriers with an mcr instruction.
2348 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
2350 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&
2351 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!");
2352 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2353 DAG.getConstant(0, MVT::i32));
2356 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
2357 DAG.getConstant(ARM_MB::ISH, MVT::i32));
2360 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
2361 const ARMSubtarget *Subtarget) {
2362 // ARM pre v5TE and Thumb1 does not have preload instructions.
2363 if (!(Subtarget->isThumb2() ||
2364 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
2365 // Just preserve the chain.
2366 return Op.getOperand(0);
2368 DebugLoc dl = Op.getDebugLoc();
2369 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
2371 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
2372 // ARMv7 with MP extension has PLDW.
2373 return Op.getOperand(0);
2375 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
2376 if (Subtarget->isThumb()) {
2378 isRead = ~isRead & 1;
2379 isData = ~isData & 1;
2382 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
2383 Op.getOperand(1), DAG.getConstant(isRead, MVT::i32),
2384 DAG.getConstant(isData, MVT::i32));
2387 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
2388 MachineFunction &MF = DAG.getMachineFunction();
2389 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
2391 // vastart just stores the address of the VarArgsFrameIndex slot into the
2392 // memory location argument.
2393 DebugLoc dl = Op.getDebugLoc();
2394 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2395 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2396 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2397 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2398 MachinePointerInfo(SV), false, false, 0);
2402 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
2403 SDValue &Root, SelectionDAG &DAG,
2404 DebugLoc dl) const {
2405 MachineFunction &MF = DAG.getMachineFunction();
2406 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2408 TargetRegisterClass *RC;
2409 if (AFI->isThumb1OnlyFunction())
2410 RC = ARM::tGPRRegisterClass;
2412 RC = ARM::GPRRegisterClass;
2414 // Transform the arguments stored in physical registers into virtual ones.
2415 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2416 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2419 if (NextVA.isMemLoc()) {
2420 MachineFrameInfo *MFI = MF.getFrameInfo();
2421 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
2423 // Create load node to retrieve arguments from the stack.
2424 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2425 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
2426 MachinePointerInfo::getFixedStack(FI),
2427 false, false, false, 0);
2429 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2430 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2433 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
2437 ARMTargetLowering::computeRegArea(CCState &CCInfo, MachineFunction &MF,
2438 unsigned &VARegSize, unsigned &VARegSaveSize)
2441 if (CCInfo.isFirstByValRegValid())
2442 NumGPRs = ARM::R4 - CCInfo.getFirstByValReg();
2444 unsigned int firstUnalloced;
2445 firstUnalloced = CCInfo.getFirstUnallocated(GPRArgRegs,
2446 sizeof(GPRArgRegs) /
2447 sizeof(GPRArgRegs[0]));
2448 NumGPRs = (firstUnalloced <= 3) ? (4 - firstUnalloced) : 0;
2451 unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment();
2452 VARegSize = NumGPRs * 4;
2453 VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
2456 // The remaining GPRs hold either the beginning of variable-argument
2457 // data, or the beginning of an aggregate passed by value (usuall
2458 // byval). Either way, we allocate stack slots adjacent to the data
2459 // provided by our caller, and store the unallocated registers there.
2460 // If this is a variadic function, the va_list pointer will begin with
2461 // these values; otherwise, this reassembles a (byval) structure that
2462 // was split between registers and memory.
2464 ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
2465 DebugLoc dl, SDValue &Chain,
2466 unsigned ArgOffset) const {
2467 MachineFunction &MF = DAG.getMachineFunction();
2468 MachineFrameInfo *MFI = MF.getFrameInfo();
2469 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2470 unsigned firstRegToSaveIndex;
2471 if (CCInfo.isFirstByValRegValid())
2472 firstRegToSaveIndex = CCInfo.getFirstByValReg() - ARM::R0;
2474 firstRegToSaveIndex = CCInfo.getFirstUnallocated
2475 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
2478 unsigned VARegSize, VARegSaveSize;
2479 computeRegArea(CCInfo, MF, VARegSize, VARegSaveSize);
2480 if (VARegSaveSize) {
2481 // If this function is vararg, store any remaining integer argument regs
2482 // to their spots on the stack so that they may be loaded by deferencing
2483 // the result of va_next.
2484 AFI->setVarArgsRegSaveSize(VARegSaveSize);
2485 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(VARegSaveSize,
2486 ArgOffset + VARegSaveSize
2489 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(),
2492 SmallVector<SDValue, 4> MemOps;
2493 for (; firstRegToSaveIndex < 4; ++firstRegToSaveIndex) {
2494 TargetRegisterClass *RC;
2495 if (AFI->isThumb1OnlyFunction())
2496 RC = ARM::tGPRRegisterClass;
2498 RC = ARM::GPRRegisterClass;
2500 unsigned VReg = MF.addLiveIn(GPRArgRegs[firstRegToSaveIndex], RC);
2501 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2503 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2504 MachinePointerInfo::getFixedStack(AFI->getVarArgsFrameIndex()),
2506 MemOps.push_back(Store);
2507 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
2508 DAG.getConstant(4, getPointerTy()));
2510 if (!MemOps.empty())
2511 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2512 &MemOps[0], MemOps.size());
2514 // This will point to the next argument passed via stack.
2515 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset, true));
2519 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
2520 CallingConv::ID CallConv, bool isVarArg,
2521 const SmallVectorImpl<ISD::InputArg>
2523 DebugLoc dl, SelectionDAG &DAG,
2524 SmallVectorImpl<SDValue> &InVals)
2526 MachineFunction &MF = DAG.getMachineFunction();
2527 MachineFrameInfo *MFI = MF.getFrameInfo();
2529 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2531 // Assign locations to all of the incoming arguments.
2532 SmallVector<CCValAssign, 16> ArgLocs;
2533 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2534 getTargetMachine(), ArgLocs, *DAG.getContext(), Prologue);
2535 CCInfo.AnalyzeFormalArguments(Ins,
2536 CCAssignFnForNode(CallConv, /* Return*/ false,
2539 SmallVector<SDValue, 16> ArgValues;
2540 int lastInsIndex = -1;
2543 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2544 CCValAssign &VA = ArgLocs[i];
2546 // Arguments stored in registers.
2547 if (VA.isRegLoc()) {
2548 EVT RegVT = VA.getLocVT();
2550 if (VA.needsCustom()) {
2551 // f64 and vector types are split up into multiple registers or
2552 // combinations of registers and stack slots.
2553 if (VA.getLocVT() == MVT::v2f64) {
2554 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
2556 VA = ArgLocs[++i]; // skip ahead to next loc
2558 if (VA.isMemLoc()) {
2559 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
2560 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2561 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
2562 MachinePointerInfo::getFixedStack(FI),
2563 false, false, false, 0);
2565 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
2568 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2569 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2570 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
2571 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2572 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
2574 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
2577 TargetRegisterClass *RC;
2579 if (RegVT == MVT::f32)
2580 RC = ARM::SPRRegisterClass;
2581 else if (RegVT == MVT::f64)
2582 RC = ARM::DPRRegisterClass;
2583 else if (RegVT == MVT::v2f64)
2584 RC = ARM::QPRRegisterClass;
2585 else if (RegVT == MVT::i32)
2586 RC = (AFI->isThumb1OnlyFunction() ?
2587 ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
2589 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2591 // Transform the arguments in physical registers into virtual ones.
2592 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2593 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2596 // If this is an 8 or 16-bit value, it is really passed promoted
2597 // to 32 bits. Insert an assert[sz]ext to capture this, then
2598 // truncate to the right size.
2599 switch (VA.getLocInfo()) {
2600 default: llvm_unreachable("Unknown loc info!");
2601 case CCValAssign::Full: break;
2602 case CCValAssign::BCvt:
2603 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2605 case CCValAssign::SExt:
2606 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2607 DAG.getValueType(VA.getValVT()));
2608 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2610 case CCValAssign::ZExt:
2611 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2612 DAG.getValueType(VA.getValVT()));
2613 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2617 InVals.push_back(ArgValue);
2619 } else { // VA.isRegLoc()
2622 assert(VA.isMemLoc());
2623 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
2625 int index = ArgLocs[i].getValNo();
2627 // Some Ins[] entries become multiple ArgLoc[] entries.
2628 // Process them only once.
2629 if (index != lastInsIndex)
2631 ISD::ArgFlagsTy Flags = Ins[index].Flags;
2632 // FIXME: For now, all byval parameter objects are marked mutable.
2633 // This can be changed with more analysis.
2634 // In case of tail call optimization mark all arguments mutable.
2635 // Since they could be overwritten by lowering of arguments in case of
2637 if (Flags.isByVal()) {
2638 unsigned VARegSize, VARegSaveSize;
2639 computeRegArea(CCInfo, MF, VARegSize, VARegSaveSize);
2640 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, 0);
2641 unsigned Bytes = Flags.getByValSize() - VARegSize;
2642 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2643 int FI = MFI->CreateFixedObject(Bytes,
2644 VA.getLocMemOffset(), false);
2645 InVals.push_back(DAG.getFrameIndex(FI, getPointerTy()));
2647 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
2648 VA.getLocMemOffset(), true);
2650 // Create load nodes to retrieve arguments from the stack.
2651 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2652 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2653 MachinePointerInfo::getFixedStack(FI),
2654 false, false, false, 0));
2656 lastInsIndex = index;
2663 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, CCInfo.getNextStackOffset());
2668 /// isFloatingPointZero - Return true if this is +0.0.
2669 static bool isFloatingPointZero(SDValue Op) {
2670 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
2671 return CFP->getValueAPF().isPosZero();
2672 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
2673 // Maybe this has already been legalized into the constant pool?
2674 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
2675 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
2676 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
2677 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
2678 return CFP->getValueAPF().isPosZero();
2684 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
2685 /// the given operands.
2687 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2688 SDValue &ARMcc, SelectionDAG &DAG,
2689 DebugLoc dl) const {
2690 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
2691 unsigned C = RHSC->getZExtValue();
2692 if (!isLegalICmpImmediate(C)) {
2693 // Constant does not fit, try adjusting it by one?
2698 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
2699 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
2700 RHS = DAG.getConstant(C-1, MVT::i32);
2705 if (C != 0 && isLegalICmpImmediate(C-1)) {
2706 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
2707 RHS = DAG.getConstant(C-1, MVT::i32);
2712 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
2713 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
2714 RHS = DAG.getConstant(C+1, MVT::i32);
2719 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
2720 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2721 RHS = DAG.getConstant(C+1, MVT::i32);
2728 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2729 ARMISD::NodeType CompareType;
2732 CompareType = ARMISD::CMP;
2737 CompareType = ARMISD::CMPZ;
2740 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2741 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
2744 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
2746 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
2747 DebugLoc dl) const {
2749 if (!isFloatingPointZero(RHS))
2750 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS);
2752 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS);
2753 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
2756 /// duplicateCmp - Glue values can have only one use, so this function
2757 /// duplicates a comparison node.
2759 ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
2760 unsigned Opc = Cmp.getOpcode();
2761 DebugLoc DL = Cmp.getDebugLoc();
2762 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
2763 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
2765 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation");
2766 Cmp = Cmp.getOperand(0);
2767 Opc = Cmp.getOpcode();
2768 if (Opc == ARMISD::CMPFP)
2769 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
2771 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT");
2772 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0));
2774 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
2777 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2778 SDValue Cond = Op.getOperand(0);
2779 SDValue SelectTrue = Op.getOperand(1);
2780 SDValue SelectFalse = Op.getOperand(2);
2781 DebugLoc dl = Op.getDebugLoc();
2785 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
2786 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
2788 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
2789 const ConstantSDNode *CMOVTrue =
2790 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
2791 const ConstantSDNode *CMOVFalse =
2792 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
2794 if (CMOVTrue && CMOVFalse) {
2795 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
2796 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
2800 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
2802 False = SelectFalse;
2803 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
2808 if (True.getNode() && False.getNode()) {
2809 EVT VT = Op.getValueType();
2810 SDValue ARMcc = Cond.getOperand(2);
2811 SDValue CCR = Cond.getOperand(3);
2812 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
2813 assert(True.getValueType() == VT);
2814 return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp);
2819 return DAG.getSelectCC(dl, Cond,
2820 DAG.getConstant(0, Cond.getValueType()),
2821 SelectTrue, SelectFalse, ISD::SETNE);
2824 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
2825 EVT VT = Op.getValueType();
2826 SDValue LHS = Op.getOperand(0);
2827 SDValue RHS = Op.getOperand(1);
2828 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2829 SDValue TrueVal = Op.getOperand(2);
2830 SDValue FalseVal = Op.getOperand(3);
2831 DebugLoc dl = Op.getDebugLoc();
2833 if (LHS.getValueType() == MVT::i32) {
2835 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2836 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2837 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,Cmp);
2840 ARMCC::CondCodes CondCode, CondCode2;
2841 FPCCToARMCC(CC, CondCode, CondCode2);
2843 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2844 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2845 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2846 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
2848 if (CondCode2 != ARMCC::AL) {
2849 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32);
2850 // FIXME: Needs another CMP because flag can have but one use.
2851 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
2852 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
2853 Result, TrueVal, ARMcc2, CCR, Cmp2);
2858 /// canChangeToInt - Given the fp compare operand, return true if it is suitable
2859 /// to morph to an integer compare sequence.
2860 static bool canChangeToInt(SDValue Op, bool &SeenZero,
2861 const ARMSubtarget *Subtarget) {
2862 SDNode *N = Op.getNode();
2863 if (!N->hasOneUse())
2864 // Otherwise it requires moving the value from fp to integer registers.
2866 if (!N->getNumValues())
2868 EVT VT = Op.getValueType();
2869 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
2870 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
2871 // vmrs are very slow, e.g. cortex-a8.
2874 if (isFloatingPointZero(Op)) {
2878 return ISD::isNormalLoad(N);
2881 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
2882 if (isFloatingPointZero(Op))
2883 return DAG.getConstant(0, MVT::i32);
2885 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
2886 return DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2887 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(),
2888 Ld->isVolatile(), Ld->isNonTemporal(),
2889 Ld->isInvariant(), Ld->getAlignment());
2891 llvm_unreachable("Unknown VFP cmp argument!");
2894 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
2895 SDValue &RetVal1, SDValue &RetVal2) {
2896 if (isFloatingPointZero(Op)) {
2897 RetVal1 = DAG.getConstant(0, MVT::i32);
2898 RetVal2 = DAG.getConstant(0, MVT::i32);
2902 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
2903 SDValue Ptr = Ld->getBasePtr();
2904 RetVal1 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2905 Ld->getChain(), Ptr,
2906 Ld->getPointerInfo(),
2907 Ld->isVolatile(), Ld->isNonTemporal(),
2908 Ld->isInvariant(), Ld->getAlignment());
2910 EVT PtrType = Ptr.getValueType();
2911 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
2912 SDValue NewPtr = DAG.getNode(ISD::ADD, Op.getDebugLoc(),
2913 PtrType, Ptr, DAG.getConstant(4, PtrType));
2914 RetVal2 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2915 Ld->getChain(), NewPtr,
2916 Ld->getPointerInfo().getWithOffset(4),
2917 Ld->isVolatile(), Ld->isNonTemporal(),
2918 Ld->isInvariant(), NewAlign);
2922 llvm_unreachable("Unknown VFP cmp argument!");
2925 /// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
2926 /// f32 and even f64 comparisons to integer ones.
2928 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
2929 SDValue Chain = Op.getOperand(0);
2930 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2931 SDValue LHS = Op.getOperand(2);
2932 SDValue RHS = Op.getOperand(3);
2933 SDValue Dest = Op.getOperand(4);
2934 DebugLoc dl = Op.getDebugLoc();
2936 bool SeenZero = false;
2937 if (canChangeToInt(LHS, SeenZero, Subtarget) &&
2938 canChangeToInt(RHS, SeenZero, Subtarget) &&
2939 // If one of the operand is zero, it's safe to ignore the NaN case since
2940 // we only care about equality comparisons.
2941 (SeenZero || (DAG.isKnownNeverNaN(LHS) && DAG.isKnownNeverNaN(RHS)))) {
2942 // If unsafe fp math optimization is enabled and there are no other uses of
2943 // the CMP operands, and the condition code is EQ or NE, we can optimize it
2944 // to an integer comparison.
2945 if (CC == ISD::SETOEQ)
2947 else if (CC == ISD::SETUNE)
2951 if (LHS.getValueType() == MVT::f32) {
2952 LHS = bitcastf32Toi32(LHS, DAG);
2953 RHS = bitcastf32Toi32(RHS, DAG);
2954 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2955 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2956 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2957 Chain, Dest, ARMcc, CCR, Cmp);
2962 expandf64Toi32(LHS, DAG, LHS1, LHS2);
2963 expandf64Toi32(RHS, DAG, RHS1, RHS2);
2964 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2965 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2966 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
2967 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
2968 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7);
2974 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2975 SDValue Chain = Op.getOperand(0);
2976 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2977 SDValue LHS = Op.getOperand(2);
2978 SDValue RHS = Op.getOperand(3);
2979 SDValue Dest = Op.getOperand(4);
2980 DebugLoc dl = Op.getDebugLoc();
2982 if (LHS.getValueType() == MVT::i32) {
2984 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2985 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2986 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2987 Chain, Dest, ARMcc, CCR, Cmp);
2990 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
2992 if (getTargetMachine().Options.UnsafeFPMath &&
2993 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
2994 CC == ISD::SETNE || CC == ISD::SETUNE)) {
2995 SDValue Result = OptimizeVFPBrcond(Op, DAG);
2996 if (Result.getNode())
3000 ARMCC::CondCodes CondCode, CondCode2;
3001 FPCCToARMCC(CC, CondCode, CondCode2);
3003 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
3004 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
3005 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3006 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
3007 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
3008 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
3009 if (CondCode2 != ARMCC::AL) {
3010 ARMcc = DAG.getConstant(CondCode2, MVT::i32);
3011 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
3012 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
3017 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
3018 SDValue Chain = Op.getOperand(0);
3019 SDValue Table = Op.getOperand(1);
3020 SDValue Index = Op.getOperand(2);
3021 DebugLoc dl = Op.getDebugLoc();
3023 EVT PTy = getPointerTy();
3024 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
3025 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
3026 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
3027 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
3028 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
3029 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
3030 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
3031 if (Subtarget->isThumb2()) {
3032 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
3033 // which does another jump to the destination. This also makes it easier
3034 // to translate it to TBB / TBH later.
3035 // FIXME: This might not work if the function is extremely large.
3036 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
3037 Addr, Op.getOperand(2), JTI, UId);
3039 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
3040 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
3041 MachinePointerInfo::getJumpTable(),
3042 false, false, false, 0);
3043 Chain = Addr.getValue(1);
3044 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
3045 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
3047 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
3048 MachinePointerInfo::getJumpTable(),
3049 false, false, false, 0);
3050 Chain = Addr.getValue(1);
3051 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
3055 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
3056 assert(Op.getValueType().getVectorElementType() == MVT::i32
3057 && "Unexpected custom lowering");
3059 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32)
3061 return DAG.UnrollVectorOp(Op.getNode());
3064 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
3065 EVT VT = Op.getValueType();
3067 return LowerVectorFP_TO_INT(Op, DAG);
3069 DebugLoc dl = Op.getDebugLoc();
3072 switch (Op.getOpcode()) {
3073 default: llvm_unreachable("Invalid opcode!");
3074 case ISD::FP_TO_SINT:
3075 Opc = ARMISD::FTOSI;
3077 case ISD::FP_TO_UINT:
3078 Opc = ARMISD::FTOUI;
3081 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
3082 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3085 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
3086 EVT VT = Op.getValueType();
3087 DebugLoc dl = Op.getDebugLoc();
3089 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) {
3090 if (VT.getVectorElementType() == MVT::f32)
3092 return DAG.UnrollVectorOp(Op.getNode());
3095 assert(Op.getOperand(0).getValueType() == MVT::v4i16 &&
3096 "Invalid type for custom lowering!");
3097 if (VT != MVT::v4f32)
3098 return DAG.UnrollVectorOp(Op.getNode());
3102 switch (Op.getOpcode()) {
3103 default: llvm_unreachable("Invalid opcode!");
3104 case ISD::SINT_TO_FP:
3105 CastOpc = ISD::SIGN_EXTEND;
3106 Opc = ISD::SINT_TO_FP;
3108 case ISD::UINT_TO_FP:
3109 CastOpc = ISD::ZERO_EXTEND;
3110 Opc = ISD::UINT_TO_FP;
3114 Op = DAG.getNode(CastOpc, dl, MVT::v4i32, Op.getOperand(0));
3115 return DAG.getNode(Opc, dl, VT, Op);
3118 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
3119 EVT VT = Op.getValueType();
3121 return LowerVectorINT_TO_FP(Op, DAG);
3123 DebugLoc dl = Op.getDebugLoc();
3126 switch (Op.getOpcode()) {
3127 default: llvm_unreachable("Invalid opcode!");
3128 case ISD::SINT_TO_FP:
3129 Opc = ARMISD::SITOF;
3131 case ISD::UINT_TO_FP:
3132 Opc = ARMISD::UITOF;
3136 Op = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0));
3137 return DAG.getNode(Opc, dl, VT, Op);
3140 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
3141 // Implement fcopysign with a fabs and a conditional fneg.
3142 SDValue Tmp0 = Op.getOperand(0);
3143 SDValue Tmp1 = Op.getOperand(1);
3144 DebugLoc dl = Op.getDebugLoc();
3145 EVT VT = Op.getValueType();
3146 EVT SrcVT = Tmp1.getValueType();
3147 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
3148 Tmp0.getOpcode() == ARMISD::VMOVDRR;
3149 bool UseNEON = !InGPR && Subtarget->hasNEON();
3152 // Use VBSL to copy the sign bit.
3153 unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80);
3154 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
3155 DAG.getTargetConstant(EncodedVal, MVT::i32));
3156 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
3158 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT,
3159 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
3160 DAG.getConstant(32, MVT::i32));
3161 else /*if (VT == MVT::f32)*/
3162 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
3163 if (SrcVT == MVT::f32) {
3164 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
3166 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT,
3167 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
3168 DAG.getConstant(32, MVT::i32));
3169 } else if (VT == MVT::f32)
3170 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64,
3171 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
3172 DAG.getConstant(32, MVT::i32));
3173 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
3174 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
3176 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff),
3178 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
3179 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
3180 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
3182 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
3183 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
3184 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
3185 if (VT == MVT::f32) {
3186 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
3187 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
3188 DAG.getConstant(0, MVT::i32));
3190 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
3196 // Bitcast operand 1 to i32.
3197 if (SrcVT == MVT::f64)
3198 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
3199 &Tmp1, 1).getValue(1);
3200 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
3202 // Or in the signbit with integer operations.
3203 SDValue Mask1 = DAG.getConstant(0x80000000, MVT::i32);
3204 SDValue Mask2 = DAG.getConstant(0x7fffffff, MVT::i32);
3205 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
3206 if (VT == MVT::f32) {
3207 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
3208 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
3209 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3210 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
3213 // f64: Or the high part with signbit and then combine two parts.
3214 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
3216 SDValue Lo = Tmp0.getValue(0);
3217 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
3218 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
3219 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
3222 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
3223 MachineFunction &MF = DAG.getMachineFunction();
3224 MachineFrameInfo *MFI = MF.getFrameInfo();
3225 MFI->setReturnAddressIsTaken(true);
3227 EVT VT = Op.getValueType();
3228 DebugLoc dl = Op.getDebugLoc();
3229 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3231 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
3232 SDValue Offset = DAG.getConstant(4, MVT::i32);
3233 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
3234 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
3235 MachinePointerInfo(), false, false, false, 0);
3238 // Return LR, which contains the return address. Mark it an implicit live-in.
3239 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
3240 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
3243 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
3244 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3245 MFI->setFrameAddressIsTaken(true);
3247 EVT VT = Op.getValueType();
3248 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
3249 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3250 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
3251 ? ARM::R7 : ARM::R11;
3252 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
3254 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
3255 MachinePointerInfo(),
3256 false, false, false, 0);
3260 /// ExpandBITCAST - If the target supports VFP, this function is called to
3261 /// expand a bit convert where either the source or destination type is i64 to
3262 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
3263 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
3264 /// vectors), since the legalizer won't know what to do with that.
3265 static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) {
3266 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3267 DebugLoc dl = N->getDebugLoc();
3268 SDValue Op = N->getOperand(0);
3270 // This function is only supposed to be called for i64 types, either as the
3271 // source or destination of the bit convert.
3272 EVT SrcVT = Op.getValueType();
3273 EVT DstVT = N->getValueType(0);
3274 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
3275 "ExpandBITCAST called for non-i64 type");
3277 // Turn i64->f64 into VMOVDRR.
3278 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
3279 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
3280 DAG.getConstant(0, MVT::i32));
3281 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
3282 DAG.getConstant(1, MVT::i32));
3283 return DAG.getNode(ISD::BITCAST, dl, DstVT,
3284 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
3287 // Turn f64->i64 into VMOVRRD.
3288 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
3289 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
3290 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
3291 // Merge the pieces into a single i64 value.
3292 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
3298 /// getZeroVector - Returns a vector of specified type with all zero elements.
3299 /// Zero vectors are used to represent vector negation and in those cases
3300 /// will be implemented with the NEON VNEG instruction. However, VNEG does
3301 /// not support i64 elements, so sometimes the zero vectors will need to be
3302 /// explicitly constructed. Regardless, use a canonical VMOV to create the
3304 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3305 assert(VT.isVector() && "Expected a vector type");
3306 // The canonical modified immediate encoding of a zero vector is....0!
3307 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32);
3308 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
3309 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
3310 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3313 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
3314 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
3315 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
3316 SelectionDAG &DAG) const {
3317 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3318 EVT VT = Op.getValueType();
3319 unsigned VTBits = VT.getSizeInBits();
3320 DebugLoc dl = Op.getDebugLoc();
3321 SDValue ShOpLo = Op.getOperand(0);
3322 SDValue ShOpHi = Op.getOperand(1);
3323 SDValue ShAmt = Op.getOperand(2);
3325 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
3327 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
3329 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
3330 DAG.getConstant(VTBits, MVT::i32), ShAmt);
3331 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
3332 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
3333 DAG.getConstant(VTBits, MVT::i32));
3334 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
3335 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3336 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
3338 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3339 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
3341 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
3342 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
3345 SDValue Ops[2] = { Lo, Hi };
3346 return DAG.getMergeValues(Ops, 2, dl);
3349 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
3350 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
3351 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
3352 SelectionDAG &DAG) const {
3353 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3354 EVT VT = Op.getValueType();
3355 unsigned VTBits = VT.getSizeInBits();
3356 DebugLoc dl = Op.getDebugLoc();
3357 SDValue ShOpLo = Op.getOperand(0);
3358 SDValue ShOpHi = Op.getOperand(1);
3359 SDValue ShAmt = Op.getOperand(2);
3362 assert(Op.getOpcode() == ISD::SHL_PARTS);
3363 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
3364 DAG.getConstant(VTBits, MVT::i32), ShAmt);
3365 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
3366 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
3367 DAG.getConstant(VTBits, MVT::i32));
3368 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
3369 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
3371 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3372 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3373 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
3375 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
3376 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
3379 SDValue Ops[2] = { Lo, Hi };
3380 return DAG.getMergeValues(Ops, 2, dl);
3383 SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
3384 SelectionDAG &DAG) const {
3385 // The rounding mode is in bits 23:22 of the FPSCR.
3386 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
3387 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
3388 // so that the shift + and get folded into a bitfield extract.
3389 DebugLoc dl = Op.getDebugLoc();
3390 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
3391 DAG.getConstant(Intrinsic::arm_get_fpscr,
3393 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
3394 DAG.getConstant(1U << 22, MVT::i32));
3395 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
3396 DAG.getConstant(22, MVT::i32));
3397 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
3398 DAG.getConstant(3, MVT::i32));
3401 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
3402 const ARMSubtarget *ST) {
3403 EVT VT = N->getValueType(0);
3404 DebugLoc dl = N->getDebugLoc();
3406 if (!ST->hasV6T2Ops())
3409 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
3410 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
3413 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
3414 const ARMSubtarget *ST) {
3415 EVT VT = N->getValueType(0);
3416 DebugLoc dl = N->getDebugLoc();
3421 // Lower vector shifts on NEON to use VSHL.
3422 assert(ST->hasNEON() && "unexpected vector shift");
3424 // Left shifts translate directly to the vshiftu intrinsic.
3425 if (N->getOpcode() == ISD::SHL)
3426 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
3427 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
3428 N->getOperand(0), N->getOperand(1));
3430 assert((N->getOpcode() == ISD::SRA ||
3431 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
3433 // NEON uses the same intrinsics for both left and right shifts. For
3434 // right shifts, the shift amounts are negative, so negate the vector of
3436 EVT ShiftVT = N->getOperand(1).getValueType();
3437 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
3438 getZeroVector(ShiftVT, DAG, dl),
3440 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
3441 Intrinsic::arm_neon_vshifts :
3442 Intrinsic::arm_neon_vshiftu);
3443 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
3444 DAG.getConstant(vshiftInt, MVT::i32),
3445 N->getOperand(0), NegatedCount);
3448 static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
3449 const ARMSubtarget *ST) {
3450 EVT VT = N->getValueType(0);
3451 DebugLoc dl = N->getDebugLoc();
3453 // We can get here for a node like i32 = ISD::SHL i32, i64
3457 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
3458 "Unknown shift to lower!");
3460 // We only lower SRA, SRL of 1 here, all others use generic lowering.
3461 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
3462 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
3465 // If we are in thumb mode, we don't have RRX.
3466 if (ST->isThumb1Only()) return SDValue();
3468 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
3469 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
3470 DAG.getConstant(0, MVT::i32));
3471 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
3472 DAG.getConstant(1, MVT::i32));
3474 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
3475 // captures the result into a carry flag.
3476 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
3477 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), &Hi, 1);
3479 // The low part is an ARMISD::RRX operand, which shifts the carry in.
3480 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
3482 // Merge the pieces into a single i64 value.
3483 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
3486 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
3487 SDValue TmpOp0, TmpOp1;
3488 bool Invert = false;
3492 SDValue Op0 = Op.getOperand(0);
3493 SDValue Op1 = Op.getOperand(1);
3494 SDValue CC = Op.getOperand(2);
3495 EVT VT = Op.getValueType();
3496 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
3497 DebugLoc dl = Op.getDebugLoc();
3499 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
3500 switch (SetCCOpcode) {
3501 default: llvm_unreachable("Illegal FP comparison");
3503 case ISD::SETNE: Invert = true; // Fallthrough
3505 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3507 case ISD::SETLT: Swap = true; // Fallthrough
3509 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3511 case ISD::SETLE: Swap = true; // Fallthrough
3513 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3514 case ISD::SETUGE: Swap = true; // Fallthrough
3515 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
3516 case ISD::SETUGT: Swap = true; // Fallthrough
3517 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
3518 case ISD::SETUEQ: Invert = true; // Fallthrough
3520 // Expand this to (OLT | OGT).
3524 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3525 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
3527 case ISD::SETUO: Invert = true; // Fallthrough
3529 // Expand this to (OLT | OGE).
3533 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3534 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
3538 // Integer comparisons.
3539 switch (SetCCOpcode) {
3540 default: llvm_unreachable("Illegal integer comparison");
3541 case ISD::SETNE: Invert = true;
3542 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3543 case ISD::SETLT: Swap = true;
3544 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3545 case ISD::SETLE: Swap = true;
3546 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3547 case ISD::SETULT: Swap = true;
3548 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
3549 case ISD::SETULE: Swap = true;
3550 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
3553 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
3554 if (Opc == ARMISD::VCEQ) {
3557 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
3559 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
3562 // Ignore bitconvert.
3563 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST)
3564 AndOp = AndOp.getOperand(0);
3566 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
3568 Op0 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(0));
3569 Op1 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(1));
3576 std::swap(Op0, Op1);
3578 // If one of the operands is a constant vector zero, attempt to fold the
3579 // comparison to a specialized compare-against-zero form.
3581 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
3583 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) {
3584 if (Opc == ARMISD::VCGE)
3585 Opc = ARMISD::VCLEZ;
3586 else if (Opc == ARMISD::VCGT)
3587 Opc = ARMISD::VCLTZ;
3592 if (SingleOp.getNode()) {
3595 Result = DAG.getNode(ARMISD::VCEQZ, dl, VT, SingleOp); break;
3597 Result = DAG.getNode(ARMISD::VCGEZ, dl, VT, SingleOp); break;
3599 Result = DAG.getNode(ARMISD::VCLEZ, dl, VT, SingleOp); break;
3601 Result = DAG.getNode(ARMISD::VCGTZ, dl, VT, SingleOp); break;
3603 Result = DAG.getNode(ARMISD::VCLTZ, dl, VT, SingleOp); break;
3605 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3608 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3612 Result = DAG.getNOT(dl, Result, VT);
3617 /// isNEONModifiedImm - Check if the specified splat value corresponds to a
3618 /// valid vector constant for a NEON instruction with a "modified immediate"
3619 /// operand (e.g., VMOV). If so, return the encoded value.
3620 static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
3621 unsigned SplatBitSize, SelectionDAG &DAG,
3622 EVT &VT, bool is128Bits, NEONModImmType type) {
3623 unsigned OpCmode, Imm;
3625 // SplatBitSize is set to the smallest size that splats the vector, so a
3626 // zero vector will always have SplatBitSize == 8. However, NEON modified
3627 // immediate instructions others than VMOV do not support the 8-bit encoding
3628 // of a zero vector, and the default encoding of zero is supposed to be the
3633 switch (SplatBitSize) {
3635 if (type != VMOVModImm)
3637 // Any 1-byte value is OK. Op=0, Cmode=1110.
3638 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
3641 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
3645 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
3646 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
3647 if ((SplatBits & ~0xff) == 0) {
3648 // Value = 0x00nn: Op=x, Cmode=100x.
3653 if ((SplatBits & ~0xff00) == 0) {
3654 // Value = 0xnn00: Op=x, Cmode=101x.
3656 Imm = SplatBits >> 8;
3662 // NEON's 32-bit VMOV supports splat values where:
3663 // * only one byte is nonzero, or
3664 // * the least significant byte is 0xff and the second byte is nonzero, or
3665 // * the least significant 2 bytes are 0xff and the third is nonzero.
3666 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
3667 if ((SplatBits & ~0xff) == 0) {
3668 // Value = 0x000000nn: Op=x, Cmode=000x.
3673 if ((SplatBits & ~0xff00) == 0) {
3674 // Value = 0x0000nn00: Op=x, Cmode=001x.
3676 Imm = SplatBits >> 8;
3679 if ((SplatBits & ~0xff0000) == 0) {
3680 // Value = 0x00nn0000: Op=x, Cmode=010x.
3682 Imm = SplatBits >> 16;
3685 if ((SplatBits & ~0xff000000) == 0) {
3686 // Value = 0xnn000000: Op=x, Cmode=011x.
3688 Imm = SplatBits >> 24;
3692 // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC
3693 if (type == OtherModImm) return SDValue();
3695 if ((SplatBits & ~0xffff) == 0 &&
3696 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
3697 // Value = 0x0000nnff: Op=x, Cmode=1100.
3699 Imm = SplatBits >> 8;
3704 if ((SplatBits & ~0xffffff) == 0 &&
3705 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
3706 // Value = 0x00nnffff: Op=x, Cmode=1101.
3708 Imm = SplatBits >> 16;
3709 SplatBits |= 0xffff;
3713 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
3714 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
3715 // VMOV.I32. A (very) minor optimization would be to replicate the value
3716 // and fall through here to test for a valid 64-bit splat. But, then the
3717 // caller would also need to check and handle the change in size.
3721 if (type != VMOVModImm)
3723 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
3724 uint64_t BitMask = 0xff;
3726 unsigned ImmMask = 1;
3728 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
3729 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
3732 } else if ((SplatBits & BitMask) != 0) {
3738 // Op=1, Cmode=1110.
3741 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
3746 llvm_unreachable("unexpected size for isNEONModifiedImm");
3749 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
3750 return DAG.getTargetConstant(EncodedVal, MVT::i32);
3753 static bool isVEXTMask(ArrayRef<int> M, EVT VT,
3754 bool &ReverseVEXT, unsigned &Imm) {
3755 unsigned NumElts = VT.getVectorNumElements();
3756 ReverseVEXT = false;
3758 // Assume that the first shuffle index is not UNDEF. Fail if it is.
3764 // If this is a VEXT shuffle, the immediate value is the index of the first
3765 // element. The other shuffle indices must be the successive elements after
3767 unsigned ExpectedElt = Imm;
3768 for (unsigned i = 1; i < NumElts; ++i) {
3769 // Increment the expected index. If it wraps around, it may still be
3770 // a VEXT but the source vectors must be swapped.
3772 if (ExpectedElt == NumElts * 2) {
3777 if (M[i] < 0) continue; // ignore UNDEF indices
3778 if (ExpectedElt != static_cast<unsigned>(M[i]))
3782 // Adjust the index value if the source operands will be swapped.
3789 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
3790 /// instruction with the specified blocksize. (The order of the elements
3791 /// within each block of the vector is reversed.)
3792 static bool isVREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
3793 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
3794 "Only possible block sizes for VREV are: 16, 32, 64");
3796 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3800 unsigned NumElts = VT.getVectorNumElements();
3801 unsigned BlockElts = M[0] + 1;
3802 // If the first shuffle index is UNDEF, be optimistic.
3804 BlockElts = BlockSize / EltSz;
3806 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
3809 for (unsigned i = 0; i < NumElts; ++i) {
3810 if (M[i] < 0) continue; // ignore UNDEF indices
3811 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
3818 static bool isVTBLMask(ArrayRef<int> M, EVT VT) {
3819 // We can handle <8 x i8> vector shuffles. If the index in the mask is out of
3820 // range, then 0 is placed into the resulting vector. So pretty much any mask
3821 // of 8 elements can work here.
3822 return VT == MVT::v8i8 && M.size() == 8;
3825 static bool isVTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
3826 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3830 unsigned NumElts = VT.getVectorNumElements();
3831 WhichResult = (M[0] == 0 ? 0 : 1);
3832 for (unsigned i = 0; i < NumElts; i += 2) {
3833 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3834 (M[i+1] >= 0 && (unsigned) M[i+1] != i + NumElts + WhichResult))
3840 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
3841 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3842 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
3843 static bool isVTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
3844 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3848 unsigned NumElts = VT.getVectorNumElements();
3849 WhichResult = (M[0] == 0 ? 0 : 1);
3850 for (unsigned i = 0; i < NumElts; i += 2) {
3851 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3852 (M[i+1] >= 0 && (unsigned) M[i+1] != i + WhichResult))
3858 static bool isVUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
3859 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3863 unsigned NumElts = VT.getVectorNumElements();
3864 WhichResult = (M[0] == 0 ? 0 : 1);
3865 for (unsigned i = 0; i != NumElts; ++i) {
3866 if (M[i] < 0) continue; // ignore UNDEF indices
3867 if ((unsigned) M[i] != 2 * i + WhichResult)
3871 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3872 if (VT.is64BitVector() && EltSz == 32)
3878 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
3879 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3880 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
3881 static bool isVUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
3882 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3886 unsigned Half = VT.getVectorNumElements() / 2;
3887 WhichResult = (M[0] == 0 ? 0 : 1);
3888 for (unsigned j = 0; j != 2; ++j) {
3889 unsigned Idx = WhichResult;
3890 for (unsigned i = 0; i != Half; ++i) {
3891 int MIdx = M[i + j * Half];
3892 if (MIdx >= 0 && (unsigned) MIdx != Idx)
3898 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3899 if (VT.is64BitVector() && EltSz == 32)
3905 static bool isVZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
3906 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3910 unsigned NumElts = VT.getVectorNumElements();
3911 WhichResult = (M[0] == 0 ? 0 : 1);
3912 unsigned Idx = WhichResult * NumElts / 2;
3913 for (unsigned i = 0; i != NumElts; i += 2) {
3914 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3915 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts))
3920 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3921 if (VT.is64BitVector() && EltSz == 32)
3927 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
3928 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3929 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
3930 static bool isVZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
3931 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3935 unsigned NumElts = VT.getVectorNumElements();
3936 WhichResult = (M[0] == 0 ? 0 : 1);
3937 unsigned Idx = WhichResult * NumElts / 2;
3938 for (unsigned i = 0; i != NumElts; i += 2) {
3939 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3940 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx))
3945 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3946 if (VT.is64BitVector() && EltSz == 32)
3952 // If N is an integer constant that can be moved into a register in one
3953 // instruction, return an SDValue of such a constant (will become a MOV
3954 // instruction). Otherwise return null.
3955 static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG,
3956 const ARMSubtarget *ST, DebugLoc dl) {
3958 if (!isa<ConstantSDNode>(N))
3960 Val = cast<ConstantSDNode>(N)->getZExtValue();
3962 if (ST->isThumb1Only()) {
3963 if (Val <= 255 || ~Val <= 255)
3964 return DAG.getConstant(Val, MVT::i32);
3966 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1)
3967 return DAG.getConstant(Val, MVT::i32);
3972 // If this is a case we can't handle, return null and let the default
3973 // expansion code take care of it.
3974 SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
3975 const ARMSubtarget *ST) const {
3976 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
3977 DebugLoc dl = Op.getDebugLoc();
3978 EVT VT = Op.getValueType();
3980 APInt SplatBits, SplatUndef;
3981 unsigned SplatBitSize;
3983 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
3984 if (SplatBitSize <= 64) {
3985 // Check if an immediate VMOV works.
3987 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
3988 SplatUndef.getZExtValue(), SplatBitSize,
3989 DAG, VmovVT, VT.is128BitVector(),
3991 if (Val.getNode()) {
3992 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
3993 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3996 // Try an immediate VMVN.
3997 uint64_t NegatedImm = (~SplatBits).getZExtValue();
3998 Val = isNEONModifiedImm(NegatedImm,
3999 SplatUndef.getZExtValue(), SplatBitSize,
4000 DAG, VmovVT, VT.is128BitVector(),
4002 if (Val.getNode()) {
4003 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
4004 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
4007 // Use vmov.f32 to materialize other v2f32 and v4f32 splats.
4008 if ((VT == MVT::v2f32 || VT == MVT::v4f32) && SplatBitSize == 32) {
4009 int ImmVal = ARM_AM::getFP32Imm(SplatBits);
4011 SDValue Val = DAG.getTargetConstant(ImmVal, MVT::i32);
4012 return DAG.getNode(ARMISD::VMOVFPIMM, dl, VT, Val);
4018 // Scan through the operands to see if only one value is used.
4019 unsigned NumElts = VT.getVectorNumElements();
4020 bool isOnlyLowElement = true;
4021 bool usesOnlyOneValue = true;
4022 bool isConstant = true;
4024 for (unsigned i = 0; i < NumElts; ++i) {
4025 SDValue V = Op.getOperand(i);
4026 if (V.getOpcode() == ISD::UNDEF)
4029 isOnlyLowElement = false;
4030 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
4033 if (!Value.getNode())
4035 else if (V != Value)
4036 usesOnlyOneValue = false;
4039 if (!Value.getNode())
4040 return DAG.getUNDEF(VT);
4042 if (isOnlyLowElement)
4043 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
4045 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4047 // Use VDUP for non-constant splats. For f32 constant splats, reduce to
4048 // i32 and try again.
4049 if (usesOnlyOneValue && EltSize <= 32) {
4051 return DAG.getNode(ARMISD::VDUP, dl, VT, Value);
4052 if (VT.getVectorElementType().isFloatingPoint()) {
4053 SmallVector<SDValue, 8> Ops;
4054 for (unsigned i = 0; i < NumElts; ++i)
4055 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32,
4057 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
4058 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], NumElts);
4059 Val = LowerBUILD_VECTOR(Val, DAG, ST);
4061 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
4063 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
4065 return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
4068 // If all elements are constants and the case above didn't get hit, fall back
4069 // to the default expansion, which will generate a load from the constant
4074 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
4076 SDValue shuffle = ReconstructShuffle(Op, DAG);
4077 if (shuffle != SDValue())
4081 // Vectors with 32- or 64-bit elements can be built by directly assigning
4082 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
4083 // will be legalized.
4084 if (EltSize >= 32) {
4085 // Do the expansion with floating-point types, since that is what the VFP
4086 // registers are defined to use, and since i64 is not legal.
4087 EVT EltVT = EVT::getFloatingPointVT(EltSize);
4088 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
4089 SmallVector<SDValue, 8> Ops;
4090 for (unsigned i = 0; i < NumElts; ++i)
4091 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i)));
4092 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
4093 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
4099 // Gather data to see if the operation can be modelled as a
4100 // shuffle in combination with VEXTs.
4101 SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
4102 SelectionDAG &DAG) const {
4103 DebugLoc dl = Op.getDebugLoc();
4104 EVT VT = Op.getValueType();
4105 unsigned NumElts = VT.getVectorNumElements();
4107 SmallVector<SDValue, 2> SourceVecs;
4108 SmallVector<unsigned, 2> MinElts;
4109 SmallVector<unsigned, 2> MaxElts;
4111 for (unsigned i = 0; i < NumElts; ++i) {
4112 SDValue V = Op.getOperand(i);
4113 if (V.getOpcode() == ISD::UNDEF)
4115 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
4116 // A shuffle can only come from building a vector from various
4117 // elements of other vectors.
4119 } else if (V.getOperand(0).getValueType().getVectorElementType() !=
4120 VT.getVectorElementType()) {
4121 // This code doesn't know how to handle shuffles where the vector
4122 // element types do not match (this happens because type legalization
4123 // promotes the return type of EXTRACT_VECTOR_ELT).
4124 // FIXME: It might be appropriate to extend this code to handle
4125 // mismatched types.
4129 // Record this extraction against the appropriate vector if possible...
4130 SDValue SourceVec = V.getOperand(0);
4131 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
4132 bool FoundSource = false;
4133 for (unsigned j = 0; j < SourceVecs.size(); ++j) {
4134 if (SourceVecs[j] == SourceVec) {
4135 if (MinElts[j] > EltNo)
4137 if (MaxElts[j] < EltNo)
4144 // Or record a new source if not...
4146 SourceVecs.push_back(SourceVec);
4147 MinElts.push_back(EltNo);
4148 MaxElts.push_back(EltNo);
4152 // Currently only do something sane when at most two source vectors
4154 if (SourceVecs.size() > 2)
4157 SDValue ShuffleSrcs[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT) };
4158 int VEXTOffsets[2] = {0, 0};
4160 // This loop extracts the usage patterns of the source vectors
4161 // and prepares appropriate SDValues for a shuffle if possible.
4162 for (unsigned i = 0; i < SourceVecs.size(); ++i) {
4163 if (SourceVecs[i].getValueType() == VT) {
4164 // No VEXT necessary
4165 ShuffleSrcs[i] = SourceVecs[i];
4168 } else if (SourceVecs[i].getValueType().getVectorNumElements() < NumElts) {
4169 // It probably isn't worth padding out a smaller vector just to
4170 // break it down again in a shuffle.
4174 // Since only 64-bit and 128-bit vectors are legal on ARM and
4175 // we've eliminated the other cases...
4176 assert(SourceVecs[i].getValueType().getVectorNumElements() == 2*NumElts &&
4177 "unexpected vector sizes in ReconstructShuffle");
4179 if (MaxElts[i] - MinElts[i] >= NumElts) {
4180 // Span too large for a VEXT to cope
4184 if (MinElts[i] >= NumElts) {
4185 // The extraction can just take the second half
4186 VEXTOffsets[i] = NumElts;
4187 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4189 DAG.getIntPtrConstant(NumElts));
4190 } else if (MaxElts[i] < NumElts) {
4191 // The extraction can just take the first half
4193 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4195 DAG.getIntPtrConstant(0));
4197 // An actual VEXT is needed
4198 VEXTOffsets[i] = MinElts[i];
4199 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4201 DAG.getIntPtrConstant(0));
4202 SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4204 DAG.getIntPtrConstant(NumElts));
4205 ShuffleSrcs[i] = DAG.getNode(ARMISD::VEXT, dl, VT, VEXTSrc1, VEXTSrc2,
4206 DAG.getConstant(VEXTOffsets[i], MVT::i32));
4210 SmallVector<int, 8> Mask;
4212 for (unsigned i = 0; i < NumElts; ++i) {
4213 SDValue Entry = Op.getOperand(i);
4214 if (Entry.getOpcode() == ISD::UNDEF) {
4219 SDValue ExtractVec = Entry.getOperand(0);
4220 int ExtractElt = cast<ConstantSDNode>(Op.getOperand(i)
4221 .getOperand(1))->getSExtValue();
4222 if (ExtractVec == SourceVecs[0]) {
4223 Mask.push_back(ExtractElt - VEXTOffsets[0]);
4225 Mask.push_back(ExtractElt + NumElts - VEXTOffsets[1]);
4229 // Final check before we try to produce nonsense...
4230 if (isShuffleMaskLegal(Mask, VT))
4231 return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1],
4237 /// isShuffleMaskLegal - Targets can use this to indicate that they only
4238 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
4239 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
4240 /// are assumed to be legal.
4242 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
4244 if (VT.getVectorNumElements() == 4 &&
4245 (VT.is128BitVector() || VT.is64BitVector())) {
4246 unsigned PFIndexes[4];
4247 for (unsigned i = 0; i != 4; ++i) {
4251 PFIndexes[i] = M[i];
4254 // Compute the index in the perfect shuffle table.
4255 unsigned PFTableIndex =
4256 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
4257 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4258 unsigned Cost = (PFEntry >> 30);
4265 unsigned Imm, WhichResult;
4267 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4268 return (EltSize >= 32 ||
4269 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
4270 isVREVMask(M, VT, 64) ||
4271 isVREVMask(M, VT, 32) ||
4272 isVREVMask(M, VT, 16) ||
4273 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
4274 isVTBLMask(M, VT) ||
4275 isVTRNMask(M, VT, WhichResult) ||
4276 isVUZPMask(M, VT, WhichResult) ||
4277 isVZIPMask(M, VT, WhichResult) ||
4278 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
4279 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
4280 isVZIP_v_undef_Mask(M, VT, WhichResult));
4283 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
4284 /// the specified operations to build the shuffle.
4285 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
4286 SDValue RHS, SelectionDAG &DAG,
4288 unsigned OpNum = (PFEntry >> 26) & 0x0F;
4289 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
4290 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
4293 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
4302 OP_VUZPL, // VUZP, left result
4303 OP_VUZPR, // VUZP, right result
4304 OP_VZIPL, // VZIP, left result
4305 OP_VZIPR, // VZIP, right result
4306 OP_VTRNL, // VTRN, left result
4307 OP_VTRNR // VTRN, right result
4310 if (OpNum == OP_COPY) {
4311 if (LHSID == (1*9+2)*9+3) return LHS;
4312 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
4316 SDValue OpLHS, OpRHS;
4317 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
4318 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
4319 EVT VT = OpLHS.getValueType();
4322 default: llvm_unreachable("Unknown shuffle opcode!");
4324 // VREV divides the vector in half and swaps within the half.
4325 if (VT.getVectorElementType() == MVT::i32 ||
4326 VT.getVectorElementType() == MVT::f32)
4327 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
4328 // vrev <4 x i16> -> VREV32
4329 if (VT.getVectorElementType() == MVT::i16)
4330 return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS);
4331 // vrev <4 x i8> -> VREV16
4332 assert(VT.getVectorElementType() == MVT::i8);
4333 return DAG.getNode(ARMISD::VREV16, dl, VT, OpLHS);
4338 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
4339 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
4343 return DAG.getNode(ARMISD::VEXT, dl, VT,
4345 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
4348 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4349 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
4352 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4353 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
4356 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4357 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
4361 static SDValue LowerVECTOR_SHUFFLEv8i8(SDValue Op,
4362 ArrayRef<int> ShuffleMask,
4363 SelectionDAG &DAG) {
4364 // Check to see if we can use the VTBL instruction.
4365 SDValue V1 = Op.getOperand(0);
4366 SDValue V2 = Op.getOperand(1);
4367 DebugLoc DL = Op.getDebugLoc();
4369 SmallVector<SDValue, 8> VTBLMask;
4370 for (ArrayRef<int>::iterator
4371 I = ShuffleMask.begin(), E = ShuffleMask.end(); I != E; ++I)
4372 VTBLMask.push_back(DAG.getConstant(*I, MVT::i32));
4374 if (V2.getNode()->getOpcode() == ISD::UNDEF)
4375 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1,
4376 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
4379 return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2,
4380 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
4384 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
4385 SDValue V1 = Op.getOperand(0);
4386 SDValue V2 = Op.getOperand(1);
4387 DebugLoc dl = Op.getDebugLoc();
4388 EVT VT = Op.getValueType();
4389 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
4391 // Convert shuffles that are directly supported on NEON to target-specific
4392 // DAG nodes, instead of keeping them as shuffles and matching them again
4393 // during code selection. This is more efficient and avoids the possibility
4394 // of inconsistencies between legalization and selection.
4395 // FIXME: floating-point vectors should be canonicalized to integer vectors
4396 // of the same time so that they get CSEd properly.
4397 ArrayRef<int> ShuffleMask = SVN->getMask();
4399 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4400 if (EltSize <= 32) {
4401 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
4402 int Lane = SVN->getSplatIndex();
4403 // If this is undef splat, generate it via "just" vdup, if possible.
4404 if (Lane == -1) Lane = 0;
4406 // Test if V1 is a SCALAR_TO_VECTOR.
4407 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4408 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
4410 // Test if V1 is a BUILD_VECTOR which is equivalent to a SCALAR_TO_VECTOR
4411 // (and probably will turn into a SCALAR_TO_VECTOR once legalization
4413 if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
4414 !isa<ConstantSDNode>(V1.getOperand(0))) {
4415 bool IsScalarToVector = true;
4416 for (unsigned i = 1, e = V1.getNumOperands(); i != e; ++i)
4417 if (V1.getOperand(i).getOpcode() != ISD::UNDEF) {
4418 IsScalarToVector = false;
4421 if (IsScalarToVector)
4422 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
4424 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
4425 DAG.getConstant(Lane, MVT::i32));
4430 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
4433 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
4434 DAG.getConstant(Imm, MVT::i32));
4437 if (isVREVMask(ShuffleMask, VT, 64))
4438 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
4439 if (isVREVMask(ShuffleMask, VT, 32))
4440 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
4441 if (isVREVMask(ShuffleMask, VT, 16))
4442 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
4444 // Check for Neon shuffles that modify both input vectors in place.
4445 // If both results are used, i.e., if there are two shuffles with the same
4446 // source operands and with masks corresponding to both results of one of
4447 // these operations, DAG memoization will ensure that a single node is
4448 // used for both shuffles.
4449 unsigned WhichResult;
4450 if (isVTRNMask(ShuffleMask, VT, WhichResult))
4451 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4452 V1, V2).getValue(WhichResult);
4453 if (isVUZPMask(ShuffleMask, VT, WhichResult))
4454 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4455 V1, V2).getValue(WhichResult);
4456 if (isVZIPMask(ShuffleMask, VT, WhichResult))
4457 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4458 V1, V2).getValue(WhichResult);
4460 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
4461 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4462 V1, V1).getValue(WhichResult);
4463 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
4464 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4465 V1, V1).getValue(WhichResult);
4466 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
4467 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4468 V1, V1).getValue(WhichResult);
4471 // If the shuffle is not directly supported and it has 4 elements, use
4472 // the PerfectShuffle-generated table to synthesize it from other shuffles.
4473 unsigned NumElts = VT.getVectorNumElements();
4475 unsigned PFIndexes[4];
4476 for (unsigned i = 0; i != 4; ++i) {
4477 if (ShuffleMask[i] < 0)
4480 PFIndexes[i] = ShuffleMask[i];
4483 // Compute the index in the perfect shuffle table.
4484 unsigned PFTableIndex =
4485 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
4486 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4487 unsigned Cost = (PFEntry >> 30);
4490 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
4493 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
4494 if (EltSize >= 32) {
4495 // Do the expansion with floating-point types, since that is what the VFP
4496 // registers are defined to use, and since i64 is not legal.
4497 EVT EltVT = EVT::getFloatingPointVT(EltSize);
4498 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
4499 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1);
4500 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2);
4501 SmallVector<SDValue, 8> Ops;
4502 for (unsigned i = 0; i < NumElts; ++i) {
4503 if (ShuffleMask[i] < 0)
4504 Ops.push_back(DAG.getUNDEF(EltVT));
4506 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
4507 ShuffleMask[i] < (int)NumElts ? V1 : V2,
4508 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
4511 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
4512 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
4515 if (VT == MVT::v8i8) {
4516 SDValue NewOp = LowerVECTOR_SHUFFLEv8i8(Op, ShuffleMask, DAG);
4517 if (NewOp.getNode())
4524 static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4525 // INSERT_VECTOR_ELT is legal only for immediate indexes.
4526 SDValue Lane = Op.getOperand(2);
4527 if (!isa<ConstantSDNode>(Lane))
4533 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4534 // EXTRACT_VECTOR_ELT is legal only for immediate indexes.
4535 SDValue Lane = Op.getOperand(1);
4536 if (!isa<ConstantSDNode>(Lane))
4539 SDValue Vec = Op.getOperand(0);
4540 if (Op.getValueType() == MVT::i32 &&
4541 Vec.getValueType().getVectorElementType().getSizeInBits() < 32) {
4542 DebugLoc dl = Op.getDebugLoc();
4543 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
4549 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
4550 // The only time a CONCAT_VECTORS operation can have legal types is when
4551 // two 64-bit vectors are concatenated to a 128-bit vector.
4552 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
4553 "unexpected CONCAT_VECTORS");
4554 DebugLoc dl = Op.getDebugLoc();
4555 SDValue Val = DAG.getUNDEF(MVT::v2f64);
4556 SDValue Op0 = Op.getOperand(0);
4557 SDValue Op1 = Op.getOperand(1);
4558 if (Op0.getOpcode() != ISD::UNDEF)
4559 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
4560 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0),
4561 DAG.getIntPtrConstant(0));
4562 if (Op1.getOpcode() != ISD::UNDEF)
4563 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
4564 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1),
4565 DAG.getIntPtrConstant(1));
4566 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val);
4569 /// isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each
4570 /// element has been zero/sign-extended, depending on the isSigned parameter,
4571 /// from an integer type half its size.
4572 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
4574 // A v2i64 BUILD_VECTOR will have been legalized to a BITCAST from v4i32.
4575 EVT VT = N->getValueType(0);
4576 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) {
4577 SDNode *BVN = N->getOperand(0).getNode();
4578 if (BVN->getValueType(0) != MVT::v4i32 ||
4579 BVN->getOpcode() != ISD::BUILD_VECTOR)
4581 unsigned LoElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
4582 unsigned HiElt = 1 - LoElt;
4583 ConstantSDNode *Lo0 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt));
4584 ConstantSDNode *Hi0 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt));
4585 ConstantSDNode *Lo1 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt+2));
4586 ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2));
4587 if (!Lo0 || !Hi0 || !Lo1 || !Hi1)
4590 if (Hi0->getSExtValue() == Lo0->getSExtValue() >> 32 &&
4591 Hi1->getSExtValue() == Lo1->getSExtValue() >> 32)
4594 if (Hi0->isNullValue() && Hi1->isNullValue())
4600 if (N->getOpcode() != ISD::BUILD_VECTOR)
4603 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
4604 SDNode *Elt = N->getOperand(i).getNode();
4605 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
4606 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4607 unsigned HalfSize = EltSize / 2;
4609 if (!isIntN(HalfSize, C->getSExtValue()))
4612 if (!isUIntN(HalfSize, C->getZExtValue()))
4623 /// isSignExtended - Check if a node is a vector value that is sign-extended
4624 /// or a constant BUILD_VECTOR with sign-extended elements.
4625 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
4626 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N))
4628 if (isExtendedBUILD_VECTOR(N, DAG, true))
4633 /// isZeroExtended - Check if a node is a vector value that is zero-extended
4634 /// or a constant BUILD_VECTOR with zero-extended elements.
4635 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
4636 if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N))
4638 if (isExtendedBUILD_VECTOR(N, DAG, false))
4643 /// SkipExtension - For a node that is a SIGN_EXTEND, ZERO_EXTEND, extending
4644 /// load, or BUILD_VECTOR with extended elements, return the unextended value.
4645 static SDValue SkipExtension(SDNode *N, SelectionDAG &DAG) {
4646 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
4647 return N->getOperand(0);
4648 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
4649 return DAG.getLoad(LD->getMemoryVT(), N->getDebugLoc(), LD->getChain(),
4650 LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(),
4651 LD->isNonTemporal(), LD->isInvariant(),
4652 LD->getAlignment());
4653 // Otherwise, the value must be a BUILD_VECTOR. For v2i64, it will
4654 // have been legalized as a BITCAST from v4i32.
4655 if (N->getOpcode() == ISD::BITCAST) {
4656 SDNode *BVN = N->getOperand(0).getNode();
4657 assert(BVN->getOpcode() == ISD::BUILD_VECTOR &&
4658 BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR");
4659 unsigned LowElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
4660 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), MVT::v2i32,
4661 BVN->getOperand(LowElt), BVN->getOperand(LowElt+2));
4663 // Construct a new BUILD_VECTOR with elements truncated to half the size.
4664 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
4665 EVT VT = N->getValueType(0);
4666 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
4667 unsigned NumElts = VT.getVectorNumElements();
4668 MVT TruncVT = MVT::getIntegerVT(EltSize);
4669 SmallVector<SDValue, 8> Ops;
4670 for (unsigned i = 0; i != NumElts; ++i) {
4671 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
4672 const APInt &CInt = C->getAPIntValue();
4673 Ops.push_back(DAG.getConstant(CInt.trunc(EltSize), TruncVT));
4675 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
4676 MVT::getVectorVT(TruncVT, NumElts), Ops.data(), NumElts);
4679 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
4680 unsigned Opcode = N->getOpcode();
4681 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
4682 SDNode *N0 = N->getOperand(0).getNode();
4683 SDNode *N1 = N->getOperand(1).getNode();
4684 return N0->hasOneUse() && N1->hasOneUse() &&
4685 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
4690 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
4691 unsigned Opcode = N->getOpcode();
4692 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
4693 SDNode *N0 = N->getOperand(0).getNode();
4694 SDNode *N1 = N->getOperand(1).getNode();
4695 return N0->hasOneUse() && N1->hasOneUse() &&
4696 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
4701 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
4702 // Multiplications are only custom-lowered for 128-bit vectors so that
4703 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
4704 EVT VT = Op.getValueType();
4705 assert(VT.is128BitVector() && "unexpected type for custom-lowering ISD::MUL");
4706 SDNode *N0 = Op.getOperand(0).getNode();
4707 SDNode *N1 = Op.getOperand(1).getNode();
4708 unsigned NewOpc = 0;
4710 bool isN0SExt = isSignExtended(N0, DAG);
4711 bool isN1SExt = isSignExtended(N1, DAG);
4712 if (isN0SExt && isN1SExt)
4713 NewOpc = ARMISD::VMULLs;
4715 bool isN0ZExt = isZeroExtended(N0, DAG);
4716 bool isN1ZExt = isZeroExtended(N1, DAG);
4717 if (isN0ZExt && isN1ZExt)
4718 NewOpc = ARMISD::VMULLu;
4719 else if (isN1SExt || isN1ZExt) {
4720 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
4721 // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
4722 if (isN1SExt && isAddSubSExt(N0, DAG)) {
4723 NewOpc = ARMISD::VMULLs;
4725 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
4726 NewOpc = ARMISD::VMULLu;
4728 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
4730 NewOpc = ARMISD::VMULLu;
4736 if (VT == MVT::v2i64)
4737 // Fall through to expand this. It is not legal.
4740 // Other vector multiplications are legal.
4745 // Legalize to a VMULL instruction.
4746 DebugLoc DL = Op.getDebugLoc();
4748 SDValue Op1 = SkipExtension(N1, DAG);
4750 Op0 = SkipExtension(N0, DAG);
4751 assert(Op0.getValueType().is64BitVector() &&
4752 Op1.getValueType().is64BitVector() &&
4753 "unexpected types for extended operands to VMULL");
4754 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
4757 // Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during
4758 // isel lowering to take advantage of no-stall back to back vmul + vmla.
4765 SDValue N00 = SkipExtension(N0->getOperand(0).getNode(), DAG);
4766 SDValue N01 = SkipExtension(N0->getOperand(1).getNode(), DAG);
4767 EVT Op1VT = Op1.getValueType();
4768 return DAG.getNode(N0->getOpcode(), DL, VT,
4769 DAG.getNode(NewOpc, DL, VT,
4770 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
4771 DAG.getNode(NewOpc, DL, VT,
4772 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
4776 LowerSDIV_v4i8(SDValue X, SDValue Y, DebugLoc dl, SelectionDAG &DAG) {
4778 // float4 xf = vcvt_f32_s32(vmovl_s16(a.lo));
4779 // float4 yf = vcvt_f32_s32(vmovl_s16(b.lo));
4780 X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X);
4781 Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y);
4782 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X);
4783 Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y);
4784 // Get reciprocal estimate.
4785 // float4 recip = vrecpeq_f32(yf);
4786 Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4787 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), Y);
4788 // Because char has a smaller range than uchar, we can actually get away
4789 // without any newton steps. This requires that we use a weird bias
4790 // of 0xb000, however (again, this has been exhaustively tested).
4791 // float4 result = as_float4(as_int4(xf*recip) + 0xb000);
4792 X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y);
4793 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X);
4794 Y = DAG.getConstant(0xb000, MVT::i32);
4795 Y = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Y, Y, Y, Y);
4796 X = DAG.getNode(ISD::ADD, dl, MVT::v4i32, X, Y);
4797 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X);
4798 // Convert back to short.
4799 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X);
4800 X = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, X);
4805 LowerSDIV_v4i16(SDValue N0, SDValue N1, DebugLoc dl, SelectionDAG &DAG) {
4807 // Convert to float.
4808 // float4 yf = vcvt_f32_s32(vmovl_s16(y));
4809 // float4 xf = vcvt_f32_s32(vmovl_s16(x));
4810 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0);
4811 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1);
4812 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
4813 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
4815 // Use reciprocal estimate and one refinement step.
4816 // float4 recip = vrecpeq_f32(yf);
4817 // recip *= vrecpsq_f32(yf, recip);
4818 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4819 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1);
4820 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4821 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
4823 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
4824 // Because short has a smaller range than ushort, we can actually get away
4825 // with only a single newton step. This requires that we use a weird bias
4826 // of 89, however (again, this has been exhaustively tested).
4827 // float4 result = as_float4(as_int4(xf*recip) + 0x89);
4828 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
4829 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
4830 N1 = DAG.getConstant(0x89, MVT::i32);
4831 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
4832 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
4833 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
4834 // Convert back to integer and return.
4835 // return vmovn_s32(vcvt_s32_f32(result));
4836 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
4837 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
4841 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
4842 EVT VT = Op.getValueType();
4843 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
4844 "unexpected type for custom-lowering ISD::SDIV");
4846 DebugLoc dl = Op.getDebugLoc();
4847 SDValue N0 = Op.getOperand(0);
4848 SDValue N1 = Op.getOperand(1);
4851 if (VT == MVT::v8i8) {
4852 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0);
4853 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1);
4855 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4856 DAG.getIntPtrConstant(4));
4857 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4858 DAG.getIntPtrConstant(4));
4859 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4860 DAG.getIntPtrConstant(0));
4861 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4862 DAG.getIntPtrConstant(0));
4864 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16
4865 N2 = LowerSDIV_v4i8(N2, N3, dl, DAG); // v4i16
4867 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
4868 N0 = LowerCONCAT_VECTORS(N0, DAG);
4870 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0);
4873 return LowerSDIV_v4i16(N0, N1, dl, DAG);
4876 static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG) {
4877 EVT VT = Op.getValueType();
4878 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
4879 "unexpected type for custom-lowering ISD::UDIV");
4881 DebugLoc dl = Op.getDebugLoc();
4882 SDValue N0 = Op.getOperand(0);
4883 SDValue N1 = Op.getOperand(1);
4886 if (VT == MVT::v8i8) {
4887 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0);
4888 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1);
4890 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4891 DAG.getIntPtrConstant(4));
4892 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4893 DAG.getIntPtrConstant(4));
4894 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4895 DAG.getIntPtrConstant(0));
4896 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4897 DAG.getIntPtrConstant(0));
4899 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16
4900 N2 = LowerSDIV_v4i16(N2, N3, dl, DAG); // v4i16
4902 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
4903 N0 = LowerCONCAT_VECTORS(N0, DAG);
4905 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8,
4906 DAG.getConstant(Intrinsic::arm_neon_vqmovnsu, MVT::i32),
4911 // v4i16 sdiv ... Convert to float.
4912 // float4 yf = vcvt_f32_s32(vmovl_u16(y));
4913 // float4 xf = vcvt_f32_s32(vmovl_u16(x));
4914 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0);
4915 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1);
4916 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
4917 SDValue BN1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
4919 // Use reciprocal estimate and two refinement steps.
4920 // float4 recip = vrecpeq_f32(yf);
4921 // recip *= vrecpsq_f32(yf, recip);
4922 // recip *= vrecpsq_f32(yf, recip);
4923 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4924 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), BN1);
4925 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4926 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
4928 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
4929 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4930 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
4932 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
4933 // Simply multiplying by the reciprocal estimate can leave us a few ulps
4934 // too low, so we add 2 ulps (exhaustive testing shows that this is enough,
4935 // and that it will never cause us to return an answer too large).
4936 // float4 result = as_float4(as_int4(xf*recip) + 2);
4937 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
4938 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
4939 N1 = DAG.getConstant(2, MVT::i32);
4940 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
4941 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
4942 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
4943 // Convert back to integer and return.
4944 // return vmovn_u32(vcvt_s32_f32(result));
4945 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
4946 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
4950 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
4951 EVT VT = Op.getNode()->getValueType(0);
4952 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
4955 bool ExtraOp = false;
4956 switch (Op.getOpcode()) {
4957 default: llvm_unreachable("Invalid code");
4958 case ISD::ADDC: Opc = ARMISD::ADDC; break;
4959 case ISD::ADDE: Opc = ARMISD::ADDE; ExtraOp = true; break;
4960 case ISD::SUBC: Opc = ARMISD::SUBC; break;
4961 case ISD::SUBE: Opc = ARMISD::SUBE; ExtraOp = true; break;
4965 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
4967 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
4968 Op.getOperand(1), Op.getOperand(2));
4971 static SDValue LowerAtomicLoadStore(SDValue Op, SelectionDAG &DAG) {
4972 // Monotonic load/store is legal for all targets
4973 if (cast<AtomicSDNode>(Op)->getOrdering() <= Monotonic)
4976 // Aquire/Release load/store is not legal for targets without a
4977 // dmb or equivalent available.
4983 ReplaceATOMIC_OP_64(SDNode *Node, SmallVectorImpl<SDValue>& Results,
4984 SelectionDAG &DAG, unsigned NewOp) {
4985 DebugLoc dl = Node->getDebugLoc();
4986 assert (Node->getValueType(0) == MVT::i64 &&
4987 "Only know how to expand i64 atomics");
4989 SmallVector<SDValue, 6> Ops;
4990 Ops.push_back(Node->getOperand(0)); // Chain
4991 Ops.push_back(Node->getOperand(1)); // Ptr
4993 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
4994 Node->getOperand(2), DAG.getIntPtrConstant(0)));
4995 // High part of Val1
4996 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
4997 Node->getOperand(2), DAG.getIntPtrConstant(1)));
4998 if (NewOp == ARMISD::ATOMCMPXCHG64_DAG) {
4999 // High part of Val1
5000 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5001 Node->getOperand(3), DAG.getIntPtrConstant(0)));
5002 // High part of Val2
5003 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5004 Node->getOperand(3), DAG.getIntPtrConstant(1)));
5006 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
5008 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops.data(), Ops.size(), MVT::i64,
5009 cast<MemSDNode>(Node)->getMemOperand());
5010 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1) };
5011 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
5012 Results.push_back(Result.getValue(2));
5015 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
5016 switch (Op.getOpcode()) {
5017 default: llvm_unreachable("Don't know how to custom lower this!");
5018 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
5019 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
5020 case ISD::GlobalAddress:
5021 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
5022 LowerGlobalAddressELF(Op, DAG);
5023 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
5024 case ISD::SELECT: return LowerSELECT(Op, DAG);
5025 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
5026 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
5027 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
5028 case ISD::VASTART: return LowerVASTART(Op, DAG);
5029 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget);
5030 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG, Subtarget);
5031 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget);
5032 case ISD::SINT_TO_FP:
5033 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
5034 case ISD::FP_TO_SINT:
5035 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
5036 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
5037 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
5038 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
5039 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
5040 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
5041 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
5042 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
5044 case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG);
5047 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
5048 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
5049 case ISD::SRL_PARTS:
5050 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
5051 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
5052 case ISD::SETCC: return LowerVSETCC(Op, DAG);
5053 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
5054 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
5055 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
5056 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
5057 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
5058 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
5059 case ISD::MUL: return LowerMUL(Op, DAG);
5060 case ISD::SDIV: return LowerSDIV(Op, DAG);
5061 case ISD::UDIV: return LowerUDIV(Op, DAG);
5065 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
5066 case ISD::ATOMIC_LOAD:
5067 case ISD::ATOMIC_STORE: return LowerAtomicLoadStore(Op, DAG);
5071 /// ReplaceNodeResults - Replace the results of node with an illegal result
5072 /// type with new values built out of custom code.
5073 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
5074 SmallVectorImpl<SDValue>&Results,
5075 SelectionDAG &DAG) const {
5077 switch (N->getOpcode()) {
5079 llvm_unreachable("Don't know how to custom expand this!");
5081 Res = ExpandBITCAST(N, DAG);
5085 Res = Expand64BitShift(N, DAG, Subtarget);
5087 case ISD::ATOMIC_LOAD_ADD:
5088 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMADD64_DAG);
5090 case ISD::ATOMIC_LOAD_AND:
5091 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMAND64_DAG);
5093 case ISD::ATOMIC_LOAD_NAND:
5094 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMNAND64_DAG);
5096 case ISD::ATOMIC_LOAD_OR:
5097 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMOR64_DAG);
5099 case ISD::ATOMIC_LOAD_SUB:
5100 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMSUB64_DAG);
5102 case ISD::ATOMIC_LOAD_XOR:
5103 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMXOR64_DAG);
5105 case ISD::ATOMIC_SWAP:
5106 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMSWAP64_DAG);
5108 case ISD::ATOMIC_CMP_SWAP:
5109 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMCMPXCHG64_DAG);
5113 Results.push_back(Res);
5116 //===----------------------------------------------------------------------===//
5117 // ARM Scheduler Hooks
5118 //===----------------------------------------------------------------------===//
5121 ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
5122 MachineBasicBlock *BB,
5123 unsigned Size) const {
5124 unsigned dest = MI->getOperand(0).getReg();
5125 unsigned ptr = MI->getOperand(1).getReg();
5126 unsigned oldval = MI->getOperand(2).getReg();
5127 unsigned newval = MI->getOperand(3).getReg();
5128 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5129 DebugLoc dl = MI->getDebugLoc();
5130 bool isThumb2 = Subtarget->isThumb2();
5132 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
5134 MRI.createVirtualRegister(isThumb2 ? ARM::rGPRRegisterClass
5135 : ARM::GPRRegisterClass);
5138 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass);
5139 MRI.constrainRegClass(oldval, ARM::rGPRRegisterClass);
5140 MRI.constrainRegClass(newval, ARM::rGPRRegisterClass);
5143 unsigned ldrOpc, strOpc;
5145 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
5147 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
5148 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
5151 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
5152 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
5155 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
5156 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
5160 MachineFunction *MF = BB->getParent();
5161 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5162 MachineFunction::iterator It = BB;
5163 ++It; // insert the new blocks after the current block
5165 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
5166 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
5167 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5168 MF->insert(It, loop1MBB);
5169 MF->insert(It, loop2MBB);
5170 MF->insert(It, exitMBB);
5172 // Transfer the remainder of BB and its successor edges to exitMBB.
5173 exitMBB->splice(exitMBB->begin(), BB,
5174 llvm::next(MachineBasicBlock::iterator(MI)),
5176 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5180 // fallthrough --> loop1MBB
5181 BB->addSuccessor(loop1MBB);
5184 // ldrex dest, [ptr]
5188 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
5189 if (ldrOpc == ARM::t2LDREX)
5191 AddDefaultPred(MIB);
5192 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
5193 .addReg(dest).addReg(oldval));
5194 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5195 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5196 BB->addSuccessor(loop2MBB);
5197 BB->addSuccessor(exitMBB);
5200 // strex scratch, newval, [ptr]
5204 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval).addReg(ptr);
5205 if (strOpc == ARM::t2STREX)
5207 AddDefaultPred(MIB);
5208 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5209 .addReg(scratch).addImm(0));
5210 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5211 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5212 BB->addSuccessor(loop1MBB);
5213 BB->addSuccessor(exitMBB);
5219 MI->eraseFromParent(); // The instruction is gone now.
5225 ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
5226 unsigned Size, unsigned BinOpcode) const {
5227 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
5228 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5230 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5231 MachineFunction *MF = BB->getParent();
5232 MachineFunction::iterator It = BB;
5235 unsigned dest = MI->getOperand(0).getReg();
5236 unsigned ptr = MI->getOperand(1).getReg();
5237 unsigned incr = MI->getOperand(2).getReg();
5238 DebugLoc dl = MI->getDebugLoc();
5239 bool isThumb2 = Subtarget->isThumb2();
5241 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
5243 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass);
5244 MRI.constrainRegClass(ptr, ARM::rGPRRegisterClass);
5247 unsigned ldrOpc, strOpc;
5249 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
5251 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
5252 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
5255 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
5256 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
5259 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
5260 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
5264 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5265 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5266 MF->insert(It, loopMBB);
5267 MF->insert(It, exitMBB);
5269 // Transfer the remainder of BB and its successor edges to exitMBB.
5270 exitMBB->splice(exitMBB->begin(), BB,
5271 llvm::next(MachineBasicBlock::iterator(MI)),
5273 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5275 TargetRegisterClass *TRC =
5276 isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
5277 unsigned scratch = MRI.createVirtualRegister(TRC);
5278 unsigned scratch2 = (!BinOpcode) ? incr : MRI.createVirtualRegister(TRC);
5282 // fallthrough --> loopMBB
5283 BB->addSuccessor(loopMBB);
5287 // <binop> scratch2, dest, incr
5288 // strex scratch, scratch2, ptr
5291 // fallthrough --> exitMBB
5293 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
5294 if (ldrOpc == ARM::t2LDREX)
5296 AddDefaultPred(MIB);
5298 // operand order needs to go the other way for NAND
5299 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr)
5300 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
5301 addReg(incr).addReg(dest)).addReg(0);
5303 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
5304 addReg(dest).addReg(incr)).addReg(0);
5307 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2).addReg(ptr);
5308 if (strOpc == ARM::t2STREX)
5310 AddDefaultPred(MIB);
5311 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5312 .addReg(scratch).addImm(0));
5313 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5314 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5316 BB->addSuccessor(loopMBB);
5317 BB->addSuccessor(exitMBB);
5323 MI->eraseFromParent(); // The instruction is gone now.
5329 ARMTargetLowering::EmitAtomicBinaryMinMax(MachineInstr *MI,
5330 MachineBasicBlock *BB,
5333 ARMCC::CondCodes Cond) const {
5334 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5336 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5337 MachineFunction *MF = BB->getParent();
5338 MachineFunction::iterator It = BB;
5341 unsigned dest = MI->getOperand(0).getReg();
5342 unsigned ptr = MI->getOperand(1).getReg();
5343 unsigned incr = MI->getOperand(2).getReg();
5344 unsigned oldval = dest;
5345 DebugLoc dl = MI->getDebugLoc();
5346 bool isThumb2 = Subtarget->isThumb2();
5348 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
5350 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass);
5351 MRI.constrainRegClass(ptr, ARM::rGPRRegisterClass);
5354 unsigned ldrOpc, strOpc, extendOpc;
5356 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
5358 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
5359 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
5360 extendOpc = isThumb2 ? ARM::t2SXTB : ARM::SXTB;
5363 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
5364 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
5365 extendOpc = isThumb2 ? ARM::t2SXTH : ARM::SXTH;
5368 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
5369 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
5374 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5375 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5376 MF->insert(It, loopMBB);
5377 MF->insert(It, exitMBB);
5379 // Transfer the remainder of BB and its successor edges to exitMBB.
5380 exitMBB->splice(exitMBB->begin(), BB,
5381 llvm::next(MachineBasicBlock::iterator(MI)),
5383 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5385 TargetRegisterClass *TRC =
5386 isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
5387 unsigned scratch = MRI.createVirtualRegister(TRC);
5388 unsigned scratch2 = MRI.createVirtualRegister(TRC);
5392 // fallthrough --> loopMBB
5393 BB->addSuccessor(loopMBB);
5397 // (sign extend dest, if required)
5399 // cmov.cond scratch2, dest, incr
5400 // strex scratch, scratch2, ptr
5403 // fallthrough --> exitMBB
5405 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
5406 if (ldrOpc == ARM::t2LDREX)
5408 AddDefaultPred(MIB);
5410 // Sign extend the value, if necessary.
5411 if (signExtend && extendOpc) {
5412 oldval = MRI.createVirtualRegister(ARM::GPRRegisterClass);
5413 AddDefaultPred(BuildMI(BB, dl, TII->get(extendOpc), oldval)
5418 // Build compare and cmov instructions.
5419 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
5420 .addReg(oldval).addReg(incr));
5421 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr), scratch2)
5422 .addReg(oldval).addReg(incr).addImm(Cond).addReg(ARM::CPSR);
5424 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2).addReg(ptr);
5425 if (strOpc == ARM::t2STREX)
5427 AddDefaultPred(MIB);
5428 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5429 .addReg(scratch).addImm(0));
5430 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5431 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5433 BB->addSuccessor(loopMBB);
5434 BB->addSuccessor(exitMBB);
5440 MI->eraseFromParent(); // The instruction is gone now.
5446 ARMTargetLowering::EmitAtomicBinary64(MachineInstr *MI, MachineBasicBlock *BB,
5447 unsigned Op1, unsigned Op2,
5448 bool NeedsCarry, bool IsCmpxchg) const {
5449 // This also handles ATOMIC_SWAP, indicated by Op1==0.
5450 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5452 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5453 MachineFunction *MF = BB->getParent();
5454 MachineFunction::iterator It = BB;
5457 unsigned destlo = MI->getOperand(0).getReg();
5458 unsigned desthi = MI->getOperand(1).getReg();
5459 unsigned ptr = MI->getOperand(2).getReg();
5460 unsigned vallo = MI->getOperand(3).getReg();
5461 unsigned valhi = MI->getOperand(4).getReg();
5462 DebugLoc dl = MI->getDebugLoc();
5463 bool isThumb2 = Subtarget->isThumb2();
5465 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
5467 MRI.constrainRegClass(destlo, ARM::rGPRRegisterClass);
5468 MRI.constrainRegClass(desthi, ARM::rGPRRegisterClass);
5469 MRI.constrainRegClass(ptr, ARM::rGPRRegisterClass);
5472 unsigned ldrOpc = isThumb2 ? ARM::t2LDREXD : ARM::LDREXD;
5473 unsigned strOpc = isThumb2 ? ARM::t2STREXD : ARM::STREXD;
5475 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5476 MachineBasicBlock *contBB = 0, *cont2BB = 0;
5478 contBB = MF->CreateMachineBasicBlock(LLVM_BB);
5479 cont2BB = MF->CreateMachineBasicBlock(LLVM_BB);
5481 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5482 MF->insert(It, loopMBB);
5484 MF->insert(It, contBB);
5485 MF->insert(It, cont2BB);
5487 MF->insert(It, exitMBB);
5489 // Transfer the remainder of BB and its successor edges to exitMBB.
5490 exitMBB->splice(exitMBB->begin(), BB,
5491 llvm::next(MachineBasicBlock::iterator(MI)),
5493 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5495 TargetRegisterClass *TRC =
5496 isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
5497 unsigned storesuccess = MRI.createVirtualRegister(TRC);
5501 // fallthrough --> loopMBB
5502 BB->addSuccessor(loopMBB);
5505 // ldrexd r2, r3, ptr
5506 // <binopa> r0, r2, incr
5507 // <binopb> r1, r3, incr
5508 // strexd storesuccess, r0, r1, ptr
5509 // cmp storesuccess, #0
5511 // fallthrough --> exitMBB
5513 // Note that the registers are explicitly specified because there is not any
5514 // way to force the register allocator to allocate a register pair.
5516 // FIXME: The hardcoded registers are not necessary for Thumb2, but we
5517 // need to properly enforce the restriction that the two output registers
5518 // for ldrexd must be different.
5521 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc))
5522 .addReg(ARM::R2, RegState::Define)
5523 .addReg(ARM::R3, RegState::Define).addReg(ptr));
5524 // Copy r2/r3 into dest. (This copy will normally be coalesced.)
5525 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), destlo).addReg(ARM::R2);
5526 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), desthi).addReg(ARM::R3);
5530 for (unsigned i = 0; i < 2; i++) {
5531 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr :
5533 .addReg(i == 0 ? destlo : desthi)
5534 .addReg(i == 0 ? vallo : valhi));
5535 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5536 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5537 BB->addSuccessor(exitMBB);
5538 BB->addSuccessor(i == 0 ? contBB : cont2BB);
5539 BB = (i == 0 ? contBB : cont2BB);
5542 // Copy to physregs for strexd
5543 unsigned setlo = MI->getOperand(5).getReg();
5544 unsigned sethi = MI->getOperand(6).getReg();
5545 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R0).addReg(setlo);
5546 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R1).addReg(sethi);
5548 // Perform binary operation
5549 AddDefaultPred(BuildMI(BB, dl, TII->get(Op1), ARM::R0)
5550 .addReg(destlo).addReg(vallo))
5551 .addReg(NeedsCarry ? ARM::CPSR : 0, getDefRegState(NeedsCarry));
5552 AddDefaultPred(BuildMI(BB, dl, TII->get(Op2), ARM::R1)
5553 .addReg(desthi).addReg(valhi)).addReg(0);
5555 // Copy to physregs for strexd
5556 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R0).addReg(vallo);
5557 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R1).addReg(valhi);
5561 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), storesuccess)
5562 .addReg(ARM::R0).addReg(ARM::R1).addReg(ptr));
5564 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5565 .addReg(storesuccess).addImm(0));
5566 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5567 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5569 BB->addSuccessor(loopMBB);
5570 BB->addSuccessor(exitMBB);
5576 MI->eraseFromParent(); // The instruction is gone now.
5581 /// SetupEntryBlockForSjLj - Insert code into the entry block that creates and
5582 /// registers the function context.
5583 void ARMTargetLowering::
5584 SetupEntryBlockForSjLj(MachineInstr *MI, MachineBasicBlock *MBB,
5585 MachineBasicBlock *DispatchBB, int FI) const {
5586 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5587 DebugLoc dl = MI->getDebugLoc();
5588 MachineFunction *MF = MBB->getParent();
5589 MachineRegisterInfo *MRI = &MF->getRegInfo();
5590 MachineConstantPool *MCP = MF->getConstantPool();
5591 ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>();
5592 const Function *F = MF->getFunction();
5594 bool isThumb = Subtarget->isThumb();
5595 bool isThumb2 = Subtarget->isThumb2();
5597 unsigned PCLabelId = AFI->createPICLabelUId();
5598 unsigned PCAdj = (isThumb || isThumb2) ? 4 : 8;
5599 ARMConstantPoolValue *CPV =
5600 ARMConstantPoolMBB::Create(F->getContext(), DispatchBB, PCLabelId, PCAdj);
5601 unsigned CPI = MCP->getConstantPoolIndex(CPV, 4);
5603 const TargetRegisterClass *TRC =
5604 isThumb ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
5606 // Grab constant pool and fixed stack memory operands.
5607 MachineMemOperand *CPMMO =
5608 MF->getMachineMemOperand(MachinePointerInfo::getConstantPool(),
5609 MachineMemOperand::MOLoad, 4, 4);
5611 MachineMemOperand *FIMMOSt =
5612 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
5613 MachineMemOperand::MOStore, 4, 4);
5615 // Load the address of the dispatch MBB into the jump buffer.
5617 // Incoming value: jbuf
5618 // ldr.n r5, LCPI1_1
5621 // str r5, [$jbuf, #+4] ; &jbuf[1]
5622 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
5623 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2LDRpci), NewVReg1)
5624 .addConstantPoolIndex(CPI)
5625 .addMemOperand(CPMMO));
5626 // Set the low bit because of thumb mode.
5627 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
5629 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2ORRri), NewVReg2)
5630 .addReg(NewVReg1, RegState::Kill)
5632 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
5633 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg3)
5634 .addReg(NewVReg2, RegState::Kill)
5636 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2STRi12))
5637 .addReg(NewVReg3, RegState::Kill)
5639 .addImm(36) // &jbuf[1] :: pc
5640 .addMemOperand(FIMMOSt));
5641 } else if (isThumb) {
5642 // Incoming value: jbuf
5643 // ldr.n r1, LCPI1_4
5647 // add r2, $jbuf, #+4 ; &jbuf[1]
5649 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
5650 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tLDRpci), NewVReg1)
5651 .addConstantPoolIndex(CPI)
5652 .addMemOperand(CPMMO));
5653 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
5654 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg2)
5655 .addReg(NewVReg1, RegState::Kill)
5657 // Set the low bit because of thumb mode.
5658 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
5659 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tMOVi8), NewVReg3)
5660 .addReg(ARM::CPSR, RegState::Define)
5662 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
5663 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tORR), NewVReg4)
5664 .addReg(ARM::CPSR, RegState::Define)
5665 .addReg(NewVReg2, RegState::Kill)
5666 .addReg(NewVReg3, RegState::Kill));
5667 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
5668 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tADDrSPi), NewVReg5)
5670 .addImm(36)); // &jbuf[1] :: pc
5671 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tSTRi))
5672 .addReg(NewVReg4, RegState::Kill)
5673 .addReg(NewVReg5, RegState::Kill)
5675 .addMemOperand(FIMMOSt));
5677 // Incoming value: jbuf
5680 // str r1, [$jbuf, #+4] ; &jbuf[1]
5681 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
5682 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::LDRi12), NewVReg1)
5683 .addConstantPoolIndex(CPI)
5685 .addMemOperand(CPMMO));
5686 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
5687 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::PICADD), NewVReg2)
5688 .addReg(NewVReg1, RegState::Kill)
5689 .addImm(PCLabelId));
5690 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::STRi12))
5691 .addReg(NewVReg2, RegState::Kill)
5693 .addImm(36) // &jbuf[1] :: pc
5694 .addMemOperand(FIMMOSt));
5698 MachineBasicBlock *ARMTargetLowering::
5699 EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const {
5700 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5701 DebugLoc dl = MI->getDebugLoc();
5702 MachineFunction *MF = MBB->getParent();
5703 MachineRegisterInfo *MRI = &MF->getRegInfo();
5704 ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>();
5705 MachineFrameInfo *MFI = MF->getFrameInfo();
5706 int FI = MFI->getFunctionContextIndex();
5708 const TargetRegisterClass *TRC =
5709 Subtarget->isThumb() ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
5711 // Get a mapping of the call site numbers to all of the landing pads they're
5713 DenseMap<unsigned, SmallVector<MachineBasicBlock*, 2> > CallSiteNumToLPad;
5714 unsigned MaxCSNum = 0;
5715 MachineModuleInfo &MMI = MF->getMMI();
5716 for (MachineFunction::iterator BB = MF->begin(), E = MF->end(); BB != E; ++BB) {
5717 if (!BB->isLandingPad()) continue;
5719 // FIXME: We should assert that the EH_LABEL is the first MI in the landing
5721 for (MachineBasicBlock::iterator
5722 II = BB->begin(), IE = BB->end(); II != IE; ++II) {
5723 if (!II->isEHLabel()) continue;
5725 MCSymbol *Sym = II->getOperand(0).getMCSymbol();
5726 if (!MMI.hasCallSiteLandingPad(Sym)) continue;
5728 SmallVectorImpl<unsigned> &CallSiteIdxs = MMI.getCallSiteLandingPad(Sym);
5729 for (SmallVectorImpl<unsigned>::iterator
5730 CSI = CallSiteIdxs.begin(), CSE = CallSiteIdxs.end();
5731 CSI != CSE; ++CSI) {
5732 CallSiteNumToLPad[*CSI].push_back(BB);
5733 MaxCSNum = std::max(MaxCSNum, *CSI);
5739 // Get an ordered list of the machine basic blocks for the jump table.
5740 std::vector<MachineBasicBlock*> LPadList;
5741 SmallPtrSet<MachineBasicBlock*, 64> InvokeBBs;
5742 LPadList.reserve(CallSiteNumToLPad.size());
5743 for (unsigned I = 1; I <= MaxCSNum; ++I) {
5744 SmallVectorImpl<MachineBasicBlock*> &MBBList = CallSiteNumToLPad[I];
5745 for (SmallVectorImpl<MachineBasicBlock*>::iterator
5746 II = MBBList.begin(), IE = MBBList.end(); II != IE; ++II) {
5747 LPadList.push_back(*II);
5748 InvokeBBs.insert((*II)->pred_begin(), (*II)->pred_end());
5752 assert(!LPadList.empty() &&
5753 "No landing pad destinations for the dispatch jump table!");
5755 // Create the jump table and associated information.
5756 MachineJumpTableInfo *JTI =
5757 MF->getOrCreateJumpTableInfo(MachineJumpTableInfo::EK_Inline);
5758 unsigned MJTI = JTI->createJumpTableIndex(LPadList);
5759 unsigned UId = AFI->createJumpTableUId();
5761 // Create the MBBs for the dispatch code.
5763 // Shove the dispatch's address into the return slot in the function context.
5764 MachineBasicBlock *DispatchBB = MF->CreateMachineBasicBlock();
5765 DispatchBB->setIsLandingPad();
5767 MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock();
5768 BuildMI(TrapBB, dl, TII->get(Subtarget->isThumb() ? ARM::tTRAP : ARM::TRAP));
5769 DispatchBB->addSuccessor(TrapBB);
5771 MachineBasicBlock *DispContBB = MF->CreateMachineBasicBlock();
5772 DispatchBB->addSuccessor(DispContBB);
5775 MF->insert(MF->end(), DispatchBB);
5776 MF->insert(MF->end(), DispContBB);
5777 MF->insert(MF->end(), TrapBB);
5779 // Insert code into the entry block that creates and registers the function
5781 SetupEntryBlockForSjLj(MI, MBB, DispatchBB, FI);
5783 MachineMemOperand *FIMMOLd =
5784 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
5785 MachineMemOperand::MOLoad |
5786 MachineMemOperand::MOVolatile, 4, 4);
5788 if (AFI->isThumb1OnlyFunction())
5789 BuildMI(DispatchBB, dl, TII->get(ARM::tInt_eh_sjlj_dispatchsetup));
5790 else if (!Subtarget->hasVFP2())
5791 BuildMI(DispatchBB, dl, TII->get(ARM::Int_eh_sjlj_dispatchsetup_nofp));
5793 BuildMI(DispatchBB, dl, TII->get(ARM::Int_eh_sjlj_dispatchsetup));
5795 unsigned NumLPads = LPadList.size();
5796 if (Subtarget->isThumb2()) {
5797 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
5798 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2LDRi12), NewVReg1)
5801 .addMemOperand(FIMMOLd));
5803 if (NumLPads < 256) {
5804 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPri))
5806 .addImm(LPadList.size()));
5808 unsigned VReg1 = MRI->createVirtualRegister(TRC);
5809 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVi16), VReg1)
5810 .addImm(NumLPads & 0xFFFF));
5812 unsigned VReg2 = VReg1;
5813 if ((NumLPads & 0xFFFF0000) != 0) {
5814 VReg2 = MRI->createVirtualRegister(TRC);
5815 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVTi16), VReg2)
5817 .addImm(NumLPads >> 16));
5820 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPrr))
5825 BuildMI(DispatchBB, dl, TII->get(ARM::t2Bcc))
5830 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
5831 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::t2LEApcrelJT),NewVReg3)
5832 .addJumpTableIndex(MJTI)
5835 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
5838 BuildMI(DispContBB, dl, TII->get(ARM::t2ADDrs), NewVReg4)
5839 .addReg(NewVReg3, RegState::Kill)
5841 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))));
5843 BuildMI(DispContBB, dl, TII->get(ARM::t2BR_JT))
5844 .addReg(NewVReg4, RegState::Kill)
5846 .addJumpTableIndex(MJTI)
5848 } else if (Subtarget->isThumb()) {
5849 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
5850 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRspi), NewVReg1)
5853 .addMemOperand(FIMMOLd));
5855 if (NumLPads < 256) {
5856 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPi8))
5860 MachineConstantPool *ConstantPool = MF->getConstantPool();
5861 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
5862 const Constant *C = ConstantInt::get(Int32Ty, NumLPads);
5864 // MachineConstantPool wants an explicit alignment.
5865 unsigned Align = getTargetData()->getPrefTypeAlignment(Int32Ty);
5867 Align = getTargetData()->getTypeAllocSize(C->getType());
5868 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
5870 unsigned VReg1 = MRI->createVirtualRegister(TRC);
5871 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRpci))
5872 .addReg(VReg1, RegState::Define)
5873 .addConstantPoolIndex(Idx));
5874 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPr))
5879 BuildMI(DispatchBB, dl, TII->get(ARM::tBcc))
5884 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
5885 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLSLri), NewVReg2)
5886 .addReg(ARM::CPSR, RegState::Define)
5890 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
5891 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLEApcrelJT), NewVReg3)
5892 .addJumpTableIndex(MJTI)
5895 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
5896 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg4)
5897 .addReg(ARM::CPSR, RegState::Define)
5898 .addReg(NewVReg2, RegState::Kill)
5901 MachineMemOperand *JTMMOLd =
5902 MF->getMachineMemOperand(MachinePointerInfo::getJumpTable(),
5903 MachineMemOperand::MOLoad, 4, 4);
5905 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
5906 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLDRi), NewVReg5)
5907 .addReg(NewVReg4, RegState::Kill)
5909 .addMemOperand(JTMMOLd));
5911 unsigned NewVReg6 = MRI->createVirtualRegister(TRC);
5912 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg6)
5913 .addReg(ARM::CPSR, RegState::Define)
5914 .addReg(NewVReg5, RegState::Kill)
5917 BuildMI(DispContBB, dl, TII->get(ARM::tBR_JTr))
5918 .addReg(NewVReg6, RegState::Kill)
5919 .addJumpTableIndex(MJTI)
5922 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
5923 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRi12), NewVReg1)
5926 .addMemOperand(FIMMOLd));
5928 if (NumLPads < 256) {
5929 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPri))
5932 } else if (Subtarget->hasV6T2Ops() && isUInt<16>(NumLPads)) {
5933 unsigned VReg1 = MRI->createVirtualRegister(TRC);
5934 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVi16), VReg1)
5935 .addImm(NumLPads & 0xFFFF));
5937 unsigned VReg2 = VReg1;
5938 if ((NumLPads & 0xFFFF0000) != 0) {
5939 VReg2 = MRI->createVirtualRegister(TRC);
5940 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVTi16), VReg2)
5942 .addImm(NumLPads >> 16));
5945 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
5949 MachineConstantPool *ConstantPool = MF->getConstantPool();
5950 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
5951 const Constant *C = ConstantInt::get(Int32Ty, NumLPads);
5953 // MachineConstantPool wants an explicit alignment.
5954 unsigned Align = getTargetData()->getPrefTypeAlignment(Int32Ty);
5956 Align = getTargetData()->getTypeAllocSize(C->getType());
5957 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
5959 unsigned VReg1 = MRI->createVirtualRegister(TRC);
5960 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRcp))
5961 .addReg(VReg1, RegState::Define)
5962 .addConstantPoolIndex(Idx)
5964 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
5966 .addReg(VReg1, RegState::Kill));
5969 BuildMI(DispatchBB, dl, TII->get(ARM::Bcc))
5974 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
5976 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::MOVsi), NewVReg3)
5978 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))));
5979 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
5980 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::LEApcrelJT), NewVReg4)
5981 .addJumpTableIndex(MJTI)
5984 MachineMemOperand *JTMMOLd =
5985 MF->getMachineMemOperand(MachinePointerInfo::getJumpTable(),
5986 MachineMemOperand::MOLoad, 4, 4);
5987 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
5989 BuildMI(DispContBB, dl, TII->get(ARM::LDRrs), NewVReg5)
5990 .addReg(NewVReg3, RegState::Kill)
5993 .addMemOperand(JTMMOLd));
5995 BuildMI(DispContBB, dl, TII->get(ARM::BR_JTadd))
5996 .addReg(NewVReg5, RegState::Kill)
5998 .addJumpTableIndex(MJTI)
6002 // Add the jump table entries as successors to the MBB.
6003 MachineBasicBlock *PrevMBB = 0;
6004 for (std::vector<MachineBasicBlock*>::iterator
6005 I = LPadList.begin(), E = LPadList.end(); I != E; ++I) {
6006 MachineBasicBlock *CurMBB = *I;
6007 if (PrevMBB != CurMBB)
6008 DispContBB->addSuccessor(CurMBB);
6012 // N.B. the order the invoke BBs are processed in doesn't matter here.
6013 const ARMBaseInstrInfo *AII = static_cast<const ARMBaseInstrInfo*>(TII);
6014 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
6015 const unsigned *SavedRegs = RI.getCalleeSavedRegs(MF);
6016 SmallVector<MachineBasicBlock*, 64> MBBLPads;
6017 for (SmallPtrSet<MachineBasicBlock*, 64>::iterator
6018 I = InvokeBBs.begin(), E = InvokeBBs.end(); I != E; ++I) {
6019 MachineBasicBlock *BB = *I;
6021 // Remove the landing pad successor from the invoke block and replace it
6022 // with the new dispatch block.
6023 SmallVector<MachineBasicBlock*, 4> Successors(BB->succ_begin(),
6025 while (!Successors.empty()) {
6026 MachineBasicBlock *SMBB = Successors.pop_back_val();
6027 if (SMBB->isLandingPad()) {
6028 BB->removeSuccessor(SMBB);
6029 MBBLPads.push_back(SMBB);
6033 BB->addSuccessor(DispatchBB);
6035 // Find the invoke call and mark all of the callee-saved registers as
6036 // 'implicit defined' so that they're spilled. This prevents code from
6037 // moving instructions to before the EH block, where they will never be
6039 for (MachineBasicBlock::reverse_iterator
6040 II = BB->rbegin(), IE = BB->rend(); II != IE; ++II) {
6041 if (!II->isCall()) continue;
6043 DenseMap<unsigned, bool> DefRegs;
6044 for (MachineInstr::mop_iterator
6045 OI = II->operands_begin(), OE = II->operands_end();
6047 if (!OI->isReg()) continue;
6048 DefRegs[OI->getReg()] = true;
6051 MachineInstrBuilder MIB(&*II);
6053 for (unsigned i = 0; SavedRegs[i] != 0; ++i) {
6054 unsigned Reg = SavedRegs[i];
6055 if (Subtarget->isThumb2() &&
6056 !ARM::tGPRRegisterClass->contains(Reg) &&
6057 !ARM::hGPRRegisterClass->contains(Reg))
6059 else if (Subtarget->isThumb1Only() &&
6060 !ARM::tGPRRegisterClass->contains(Reg))
6062 else if (!Subtarget->isThumb() &&
6063 !ARM::GPRRegisterClass->contains(Reg))
6066 MIB.addReg(Reg, RegState::ImplicitDefine | RegState::Dead);
6073 // Mark all former landing pads as non-landing pads. The dispatch is the only
6075 for (SmallVectorImpl<MachineBasicBlock*>::iterator
6076 I = MBBLPads.begin(), E = MBBLPads.end(); I != E; ++I)
6077 (*I)->setIsLandingPad(false);
6079 // The instruction is gone now.
6080 MI->eraseFromParent();
6086 MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
6087 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
6088 E = MBB->succ_end(); I != E; ++I)
6091 llvm_unreachable("Expecting a BB with two successors!");
6095 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
6096 MachineBasicBlock *BB) const {
6097 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6098 DebugLoc dl = MI->getDebugLoc();
6099 bool isThumb2 = Subtarget->isThumb2();
6100 switch (MI->getOpcode()) {
6103 llvm_unreachable("Unexpected instr type to insert");
6105 // The Thumb2 pre-indexed stores have the same MI operands, they just
6106 // define them differently in the .td files from the isel patterns, so
6107 // they need pseudos.
6108 case ARM::t2STR_preidx:
6109 MI->setDesc(TII->get(ARM::t2STR_PRE));
6111 case ARM::t2STRB_preidx:
6112 MI->setDesc(TII->get(ARM::t2STRB_PRE));
6114 case ARM::t2STRH_preidx:
6115 MI->setDesc(TII->get(ARM::t2STRH_PRE));
6118 case ARM::STRi_preidx:
6119 case ARM::STRBi_preidx: {
6120 unsigned NewOpc = MI->getOpcode() == ARM::STRi_preidx ?
6121 ARM::STR_PRE_IMM : ARM::STRB_PRE_IMM;
6122 // Decode the offset.
6123 unsigned Offset = MI->getOperand(4).getImm();
6124 bool isSub = ARM_AM::getAM2Op(Offset) == ARM_AM::sub;
6125 Offset = ARM_AM::getAM2Offset(Offset);
6129 MachineMemOperand *MMO = *MI->memoperands_begin();
6130 BuildMI(*BB, MI, dl, TII->get(NewOpc))
6131 .addOperand(MI->getOperand(0)) // Rn_wb
6132 .addOperand(MI->getOperand(1)) // Rt
6133 .addOperand(MI->getOperand(2)) // Rn
6134 .addImm(Offset) // offset (skip GPR==zero_reg)
6135 .addOperand(MI->getOperand(5)) // pred
6136 .addOperand(MI->getOperand(6))
6137 .addMemOperand(MMO);
6138 MI->eraseFromParent();
6141 case ARM::STRr_preidx:
6142 case ARM::STRBr_preidx:
6143 case ARM::STRH_preidx: {
6145 switch (MI->getOpcode()) {
6146 default: llvm_unreachable("unexpected opcode!");
6147 case ARM::STRr_preidx: NewOpc = ARM::STR_PRE_REG; break;
6148 case ARM::STRBr_preidx: NewOpc = ARM::STRB_PRE_REG; break;
6149 case ARM::STRH_preidx: NewOpc = ARM::STRH_PRE; break;
6151 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc));
6152 for (unsigned i = 0; i < MI->getNumOperands(); ++i)
6153 MIB.addOperand(MI->getOperand(i));
6154 MI->eraseFromParent();
6157 case ARM::ATOMIC_LOAD_ADD_I8:
6158 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
6159 case ARM::ATOMIC_LOAD_ADD_I16:
6160 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
6161 case ARM::ATOMIC_LOAD_ADD_I32:
6162 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
6164 case ARM::ATOMIC_LOAD_AND_I8:
6165 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
6166 case ARM::ATOMIC_LOAD_AND_I16:
6167 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
6168 case ARM::ATOMIC_LOAD_AND_I32:
6169 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
6171 case ARM::ATOMIC_LOAD_OR_I8:
6172 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
6173 case ARM::ATOMIC_LOAD_OR_I16:
6174 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
6175 case ARM::ATOMIC_LOAD_OR_I32:
6176 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
6178 case ARM::ATOMIC_LOAD_XOR_I8:
6179 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
6180 case ARM::ATOMIC_LOAD_XOR_I16:
6181 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
6182 case ARM::ATOMIC_LOAD_XOR_I32:
6183 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
6185 case ARM::ATOMIC_LOAD_NAND_I8:
6186 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
6187 case ARM::ATOMIC_LOAD_NAND_I16:
6188 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
6189 case ARM::ATOMIC_LOAD_NAND_I32:
6190 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
6192 case ARM::ATOMIC_LOAD_SUB_I8:
6193 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
6194 case ARM::ATOMIC_LOAD_SUB_I16:
6195 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
6196 case ARM::ATOMIC_LOAD_SUB_I32:
6197 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
6199 case ARM::ATOMIC_LOAD_MIN_I8:
6200 return EmitAtomicBinaryMinMax(MI, BB, 1, true, ARMCC::LT);
6201 case ARM::ATOMIC_LOAD_MIN_I16:
6202 return EmitAtomicBinaryMinMax(MI, BB, 2, true, ARMCC::LT);
6203 case ARM::ATOMIC_LOAD_MIN_I32:
6204 return EmitAtomicBinaryMinMax(MI, BB, 4, true, ARMCC::LT);
6206 case ARM::ATOMIC_LOAD_MAX_I8:
6207 return EmitAtomicBinaryMinMax(MI, BB, 1, true, ARMCC::GT);
6208 case ARM::ATOMIC_LOAD_MAX_I16:
6209 return EmitAtomicBinaryMinMax(MI, BB, 2, true, ARMCC::GT);
6210 case ARM::ATOMIC_LOAD_MAX_I32:
6211 return EmitAtomicBinaryMinMax(MI, BB, 4, true, ARMCC::GT);
6213 case ARM::ATOMIC_LOAD_UMIN_I8:
6214 return EmitAtomicBinaryMinMax(MI, BB, 1, false, ARMCC::LO);
6215 case ARM::ATOMIC_LOAD_UMIN_I16:
6216 return EmitAtomicBinaryMinMax(MI, BB, 2, false, ARMCC::LO);
6217 case ARM::ATOMIC_LOAD_UMIN_I32:
6218 return EmitAtomicBinaryMinMax(MI, BB, 4, false, ARMCC::LO);
6220 case ARM::ATOMIC_LOAD_UMAX_I8:
6221 return EmitAtomicBinaryMinMax(MI, BB, 1, false, ARMCC::HI);
6222 case ARM::ATOMIC_LOAD_UMAX_I16:
6223 return EmitAtomicBinaryMinMax(MI, BB, 2, false, ARMCC::HI);
6224 case ARM::ATOMIC_LOAD_UMAX_I32:
6225 return EmitAtomicBinaryMinMax(MI, BB, 4, false, ARMCC::HI);
6227 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0);
6228 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0);
6229 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0);
6231 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1);
6232 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
6233 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
6236 case ARM::ATOMADD6432:
6237 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr,
6238 isThumb2 ? ARM::t2ADCrr : ARM::ADCrr,
6239 /*NeedsCarry*/ true);
6240 case ARM::ATOMSUB6432:
6241 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr,
6242 isThumb2 ? ARM::t2SBCrr : ARM::SBCrr,
6243 /*NeedsCarry*/ true);
6244 case ARM::ATOMOR6432:
6245 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr,
6246 isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
6247 case ARM::ATOMXOR6432:
6248 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2EORrr : ARM::EORrr,
6249 isThumb2 ? ARM::t2EORrr : ARM::EORrr);
6250 case ARM::ATOMAND6432:
6251 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr,
6252 isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
6253 case ARM::ATOMSWAP6432:
6254 return EmitAtomicBinary64(MI, BB, 0, 0, false);
6255 case ARM::ATOMCMPXCHG6432:
6256 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr,
6257 isThumb2 ? ARM::t2SBCrr : ARM::SBCrr,
6258 /*NeedsCarry*/ false, /*IsCmpxchg*/true);
6260 case ARM::tMOVCCr_pseudo: {
6261 // To "insert" a SELECT_CC instruction, we actually have to insert the
6262 // diamond control-flow pattern. The incoming instruction knows the
6263 // destination vreg to set, the condition code register to branch on, the
6264 // true/false values to select between, and a branch opcode to use.
6265 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6266 MachineFunction::iterator It = BB;
6272 // cmpTY ccX, r1, r2
6274 // fallthrough --> copy0MBB
6275 MachineBasicBlock *thisMBB = BB;
6276 MachineFunction *F = BB->getParent();
6277 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
6278 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
6279 F->insert(It, copy0MBB);
6280 F->insert(It, sinkMBB);
6282 // Transfer the remainder of BB and its successor edges to sinkMBB.
6283 sinkMBB->splice(sinkMBB->begin(), BB,
6284 llvm::next(MachineBasicBlock::iterator(MI)),
6286 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
6288 BB->addSuccessor(copy0MBB);
6289 BB->addSuccessor(sinkMBB);
6291 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
6292 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
6295 // %FalseValue = ...
6296 // # fallthrough to sinkMBB
6299 // Update machine-CFG edges
6300 BB->addSuccessor(sinkMBB);
6303 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
6306 BuildMI(*BB, BB->begin(), dl,
6307 TII->get(ARM::PHI), MI->getOperand(0).getReg())
6308 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
6309 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
6311 MI->eraseFromParent(); // The pseudo instruction is gone now.
6316 case ARM::BCCZi64: {
6317 // If there is an unconditional branch to the other successor, remove it.
6318 BB->erase(llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
6320 // Compare both parts that make up the double comparison separately for
6322 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
6324 unsigned LHS1 = MI->getOperand(1).getReg();
6325 unsigned LHS2 = MI->getOperand(2).getReg();
6327 AddDefaultPred(BuildMI(BB, dl,
6328 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
6329 .addReg(LHS1).addImm(0));
6330 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
6331 .addReg(LHS2).addImm(0)
6332 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
6334 unsigned RHS1 = MI->getOperand(3).getReg();
6335 unsigned RHS2 = MI->getOperand(4).getReg();
6336 AddDefaultPred(BuildMI(BB, dl,
6337 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
6338 .addReg(LHS1).addReg(RHS1));
6339 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
6340 .addReg(LHS2).addReg(RHS2)
6341 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
6344 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB();
6345 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
6346 if (MI->getOperand(0).getImm() == ARMCC::NE)
6347 std::swap(destMBB, exitMBB);
6349 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
6350 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
6352 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2B)).addMBB(exitMBB));
6354 BuildMI(BB, dl, TII->get(ARM::B)) .addMBB(exitMBB);
6356 MI->eraseFromParent(); // The pseudo instruction is gone now.
6360 case ARM::Int_eh_sjlj_setjmp:
6361 case ARM::Int_eh_sjlj_setjmp_nofp:
6362 case ARM::tInt_eh_sjlj_setjmp:
6363 case ARM::t2Int_eh_sjlj_setjmp:
6364 case ARM::t2Int_eh_sjlj_setjmp_nofp:
6365 EmitSjLjDispatchBlock(MI, BB);
6370 // To insert an ABS instruction, we have to insert the
6371 // diamond control-flow pattern. The incoming instruction knows the
6372 // source vreg to test against 0, the destination vreg to set,
6373 // the condition code register to branch on, the
6374 // true/false values to select between, and a branch opcode to use.
6379 // BCC (branch to SinkBB if V0 >= 0)
6380 // RSBBB: V3 = RSBri V2, 0 (compute ABS if V2 < 0)
6381 // SinkBB: V1 = PHI(V2, V3)
6382 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6383 MachineFunction::iterator BBI = BB;
6385 MachineFunction *Fn = BB->getParent();
6386 MachineBasicBlock *RSBBB = Fn->CreateMachineBasicBlock(LLVM_BB);
6387 MachineBasicBlock *SinkBB = Fn->CreateMachineBasicBlock(LLVM_BB);
6388 Fn->insert(BBI, RSBBB);
6389 Fn->insert(BBI, SinkBB);
6391 unsigned int ABSSrcReg = MI->getOperand(1).getReg();
6392 unsigned int ABSDstReg = MI->getOperand(0).getReg();
6393 bool isThumb2 = Subtarget->isThumb2();
6394 MachineRegisterInfo &MRI = Fn->getRegInfo();
6395 // In Thumb mode S must not be specified if source register is the SP or
6396 // PC and if destination register is the SP, so restrict register class
6397 unsigned NewMovDstReg = MRI.createVirtualRegister(
6398 isThumb2 ? ARM::rGPRRegisterClass : ARM::GPRRegisterClass);
6399 unsigned NewRsbDstReg = MRI.createVirtualRegister(
6400 isThumb2 ? ARM::rGPRRegisterClass : ARM::GPRRegisterClass);
6402 // Transfer the remainder of BB and its successor edges to sinkMBB.
6403 SinkBB->splice(SinkBB->begin(), BB,
6404 llvm::next(MachineBasicBlock::iterator(MI)),
6406 SinkBB->transferSuccessorsAndUpdatePHIs(BB);
6408 BB->addSuccessor(RSBBB);
6409 BB->addSuccessor(SinkBB);
6411 // fall through to SinkMBB
6412 RSBBB->addSuccessor(SinkBB);
6414 // insert a movs at the end of BB
6415 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2MOVr : ARM::MOVr),
6417 .addReg(ABSSrcReg, RegState::Kill)
6418 .addImm((unsigned)ARMCC::AL).addReg(0)
6419 .addReg(ARM::CPSR, RegState::Define);
6421 // insert a bcc with opposite CC to ARMCC::MI at the end of BB
6423 TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)).addMBB(SinkBB)
6424 .addImm(ARMCC::getOppositeCondition(ARMCC::MI)).addReg(ARM::CPSR);
6426 // insert rsbri in RSBBB
6427 // Note: BCC and rsbri will be converted into predicated rsbmi
6428 // by if-conversion pass
6429 BuildMI(*RSBBB, RSBBB->begin(), dl,
6430 TII->get(isThumb2 ? ARM::t2RSBri : ARM::RSBri), NewRsbDstReg)
6431 .addReg(NewMovDstReg, RegState::Kill)
6432 .addImm(0).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
6434 // insert PHI in SinkBB,
6435 // reuse ABSDstReg to not change uses of ABS instruction
6436 BuildMI(*SinkBB, SinkBB->begin(), dl,
6437 TII->get(ARM::PHI), ABSDstReg)
6438 .addReg(NewRsbDstReg).addMBB(RSBBB)
6439 .addReg(NewMovDstReg).addMBB(BB);
6441 // remove ABS instruction
6442 MI->eraseFromParent();
6444 // return last added BB
6450 void ARMTargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
6451 SDNode *Node) const {
6452 if (!MI->hasPostISelHook()) {
6453 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
6454 "Pseudo flag-setting opcodes must be marked with 'hasPostISelHook'");
6458 const MCInstrDesc *MCID = &MI->getDesc();
6459 // Adjust potentially 's' setting instructions after isel, i.e. ADC, SBC, RSB,
6460 // RSC. Coming out of isel, they have an implicit CPSR def, but the optional
6461 // operand is still set to noreg. If needed, set the optional operand's
6462 // register to CPSR, and remove the redundant implicit def.
6464 // e.g. ADCS (..., CPSR<imp-def>) -> ADC (... opt:CPSR<def>).
6466 // Rename pseudo opcodes.
6467 unsigned NewOpc = convertAddSubFlagsOpcode(MI->getOpcode());
6469 const ARMBaseInstrInfo *TII =
6470 static_cast<const ARMBaseInstrInfo*>(getTargetMachine().getInstrInfo());
6471 MCID = &TII->get(NewOpc);
6473 assert(MCID->getNumOperands() == MI->getDesc().getNumOperands() + 1 &&
6474 "converted opcode should be the same except for cc_out");
6478 // Add the optional cc_out operand
6479 MI->addOperand(MachineOperand::CreateReg(0, /*isDef=*/true));
6481 unsigned ccOutIdx = MCID->getNumOperands() - 1;
6483 // Any ARM instruction that sets the 's' bit should specify an optional
6484 // "cc_out" operand in the last operand position.
6485 if (!MI->hasOptionalDef() || !MCID->OpInfo[ccOutIdx].isOptionalDef()) {
6486 assert(!NewOpc && "Optional cc_out operand required");
6489 // Look for an implicit def of CPSR added by MachineInstr ctor. Remove it
6490 // since we already have an optional CPSR def.
6491 bool definesCPSR = false;
6492 bool deadCPSR = false;
6493 for (unsigned i = MCID->getNumOperands(), e = MI->getNumOperands();
6495 const MachineOperand &MO = MI->getOperand(i);
6496 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) {
6500 MI->RemoveOperand(i);
6505 assert(!NewOpc && "Optional cc_out operand required");
6508 assert(deadCPSR == !Node->hasAnyUseOfValue(1) && "inconsistent dead flag");
6510 assert(!MI->getOperand(ccOutIdx).getReg() &&
6511 "expect uninitialized optional cc_out operand");
6515 // If this instruction was defined with an optional CPSR def and its dag node
6516 // had a live implicit CPSR def, then activate the optional CPSR def.
6517 MachineOperand &MO = MI->getOperand(ccOutIdx);
6518 MO.setReg(ARM::CPSR);
6522 //===----------------------------------------------------------------------===//
6523 // ARM Optimization Hooks
6524 //===----------------------------------------------------------------------===//
6527 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
6528 TargetLowering::DAGCombinerInfo &DCI) {
6529 SelectionDAG &DAG = DCI.DAG;
6530 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6531 EVT VT = N->getValueType(0);
6532 unsigned Opc = N->getOpcode();
6533 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
6534 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
6535 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
6536 ISD::CondCode CC = ISD::SETCC_INVALID;
6539 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
6541 SDValue CCOp = Slct.getOperand(0);
6542 if (CCOp.getOpcode() == ISD::SETCC)
6543 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
6546 bool DoXform = false;
6548 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
6551 if (LHS.getOpcode() == ISD::Constant &&
6552 cast<ConstantSDNode>(LHS)->isNullValue()) {
6554 } else if (CC != ISD::SETCC_INVALID &&
6555 RHS.getOpcode() == ISD::Constant &&
6556 cast<ConstantSDNode>(RHS)->isNullValue()) {
6557 std::swap(LHS, RHS);
6558 SDValue Op0 = Slct.getOperand(0);
6559 EVT OpVT = isSlctCC ? Op0.getValueType() :
6560 Op0.getOperand(0).getValueType();
6561 bool isInt = OpVT.isInteger();
6562 CC = ISD::getSetCCInverse(CC, isInt);
6564 if (!TLI.isCondCodeLegal(CC, OpVT))
6565 return SDValue(); // Inverse operator isn't legal.
6572 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
6574 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
6575 Slct.getOperand(0), Slct.getOperand(1), CC);
6576 SDValue CCOp = Slct.getOperand(0);
6578 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
6579 CCOp.getOperand(0), CCOp.getOperand(1), CC);
6580 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
6581 CCOp, OtherOp, Result);
6586 // AddCombineToVPADDL- For pair-wise add on neon, use the vpaddl instruction
6587 // (only after legalization).
6588 static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1,
6589 TargetLowering::DAGCombinerInfo &DCI,
6590 const ARMSubtarget *Subtarget) {
6592 // Only perform optimization if after legalize, and if NEON is available. We
6593 // also expected both operands to be BUILD_VECTORs.
6594 if (DCI.isBeforeLegalize() || !Subtarget->hasNEON()
6595 || N0.getOpcode() != ISD::BUILD_VECTOR
6596 || N1.getOpcode() != ISD::BUILD_VECTOR)
6599 // Check output type since VPADDL operand elements can only be 8, 16, or 32.
6600 EVT VT = N->getValueType(0);
6601 if (!VT.isInteger() || VT.getVectorElementType() == MVT::i64)
6604 // Check that the vector operands are of the right form.
6605 // N0 and N1 are BUILD_VECTOR nodes with N number of EXTRACT_VECTOR
6606 // operands, where N is the size of the formed vector.
6607 // Each EXTRACT_VECTOR should have the same input vector and odd or even
6608 // index such that we have a pair wise add pattern.
6610 // Grab the vector that all EXTRACT_VECTOR nodes should be referencing.
6611 if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
6613 SDValue Vec = N0->getOperand(0)->getOperand(0);
6614 SDNode *V = Vec.getNode();
6615 unsigned nextIndex = 0;
6617 // For each operands to the ADD which are BUILD_VECTORs,
6618 // check to see if each of their operands are an EXTRACT_VECTOR with
6619 // the same vector and appropriate index.
6620 for (unsigned i = 0, e = N0->getNumOperands(); i != e; ++i) {
6621 if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT
6622 && N1->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
6624 SDValue ExtVec0 = N0->getOperand(i);
6625 SDValue ExtVec1 = N1->getOperand(i);
6627 // First operand is the vector, verify its the same.
6628 if (V != ExtVec0->getOperand(0).getNode() ||
6629 V != ExtVec1->getOperand(0).getNode())
6632 // Second is the constant, verify its correct.
6633 ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(ExtVec0->getOperand(1));
6634 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(ExtVec1->getOperand(1));
6636 // For the constant, we want to see all the even or all the odd.
6637 if (!C0 || !C1 || C0->getZExtValue() != nextIndex
6638 || C1->getZExtValue() != nextIndex+1)
6647 // Create VPADDL node.
6648 SelectionDAG &DAG = DCI.DAG;
6649 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6651 // Build operand list.
6652 SmallVector<SDValue, 8> Ops;
6653 Ops.push_back(DAG.getConstant(Intrinsic::arm_neon_vpaddls,
6654 TLI.getPointerTy()));
6656 // Input is the vector.
6659 // Get widened type and narrowed type.
6661 unsigned numElem = VT.getVectorNumElements();
6662 switch (VT.getVectorElementType().getSimpleVT().SimpleTy) {
6663 case MVT::i8: widenType = MVT::getVectorVT(MVT::i16, numElem); break;
6664 case MVT::i16: widenType = MVT::getVectorVT(MVT::i32, numElem); break;
6665 case MVT::i32: widenType = MVT::getVectorVT(MVT::i64, numElem); break;
6667 llvm_unreachable("Invalid vector element type for padd optimization.");
6670 SDValue tmp = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(),
6671 widenType, &Ops[0], Ops.size());
6672 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, tmp);
6675 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
6676 /// operands N0 and N1. This is a helper for PerformADDCombine that is
6677 /// called with the default operands, and if that fails, with commuted
6679 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
6680 TargetLowering::DAGCombinerInfo &DCI,
6681 const ARMSubtarget *Subtarget){
6683 // Attempt to create vpaddl for this add.
6684 SDValue Result = AddCombineToVPADDL(N, N0, N1, DCI, Subtarget);
6685 if (Result.getNode())
6688 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
6689 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
6690 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
6691 if (Result.getNode()) return Result;
6696 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
6698 static SDValue PerformADDCombine(SDNode *N,
6699 TargetLowering::DAGCombinerInfo &DCI,
6700 const ARMSubtarget *Subtarget) {
6701 SDValue N0 = N->getOperand(0);
6702 SDValue N1 = N->getOperand(1);
6704 // First try with the default operand order.
6705 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget);
6706 if (Result.getNode())
6709 // If that didn't work, try again with the operands commuted.
6710 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget);
6713 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
6715 static SDValue PerformSUBCombine(SDNode *N,
6716 TargetLowering::DAGCombinerInfo &DCI) {
6717 SDValue N0 = N->getOperand(0);
6718 SDValue N1 = N->getOperand(1);
6720 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
6721 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
6722 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
6723 if (Result.getNode()) return Result;
6729 /// PerformVMULCombine
6730 /// Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the
6731 /// special multiplier accumulator forwarding.
6737 static SDValue PerformVMULCombine(SDNode *N,
6738 TargetLowering::DAGCombinerInfo &DCI,
6739 const ARMSubtarget *Subtarget) {
6740 if (!Subtarget->hasVMLxForwarding())
6743 SelectionDAG &DAG = DCI.DAG;
6744 SDValue N0 = N->getOperand(0);
6745 SDValue N1 = N->getOperand(1);
6746 unsigned Opcode = N0.getOpcode();
6747 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
6748 Opcode != ISD::FADD && Opcode != ISD::FSUB) {
6749 Opcode = N1.getOpcode();
6750 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
6751 Opcode != ISD::FADD && Opcode != ISD::FSUB)
6756 EVT VT = N->getValueType(0);
6757 DebugLoc DL = N->getDebugLoc();
6758 SDValue N00 = N0->getOperand(0);
6759 SDValue N01 = N0->getOperand(1);
6760 return DAG.getNode(Opcode, DL, VT,
6761 DAG.getNode(ISD::MUL, DL, VT, N00, N1),
6762 DAG.getNode(ISD::MUL, DL, VT, N01, N1));
6765 static SDValue PerformMULCombine(SDNode *N,
6766 TargetLowering::DAGCombinerInfo &DCI,
6767 const ARMSubtarget *Subtarget) {
6768 SelectionDAG &DAG = DCI.DAG;
6770 if (Subtarget->isThumb1Only())
6773 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
6776 EVT VT = N->getValueType(0);
6777 if (VT.is64BitVector() || VT.is128BitVector())
6778 return PerformVMULCombine(N, DCI, Subtarget);
6782 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
6786 uint64_t MulAmt = C->getZExtValue();
6787 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt);
6788 ShiftAmt = ShiftAmt & (32 - 1);
6789 SDValue V = N->getOperand(0);
6790 DebugLoc DL = N->getDebugLoc();
6793 MulAmt >>= ShiftAmt;
6794 if (isPowerOf2_32(MulAmt - 1)) {
6795 // (mul x, 2^N + 1) => (add (shl x, N), x)
6796 Res = DAG.getNode(ISD::ADD, DL, VT,
6797 V, DAG.getNode(ISD::SHL, DL, VT,
6798 V, DAG.getConstant(Log2_32(MulAmt-1),
6800 } else if (isPowerOf2_32(MulAmt + 1)) {
6801 // (mul x, 2^N - 1) => (sub (shl x, N), x)
6802 Res = DAG.getNode(ISD::SUB, DL, VT,
6803 DAG.getNode(ISD::SHL, DL, VT,
6804 V, DAG.getConstant(Log2_32(MulAmt+1),
6811 Res = DAG.getNode(ISD::SHL, DL, VT, Res,
6812 DAG.getConstant(ShiftAmt, MVT::i32));
6814 // Do not add new nodes to DAG combiner worklist.
6815 DCI.CombineTo(N, Res, false);
6819 static SDValue PerformANDCombine(SDNode *N,
6820 TargetLowering::DAGCombinerInfo &DCI) {
6822 // Attempt to use immediate-form VBIC
6823 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
6824 DebugLoc dl = N->getDebugLoc();
6825 EVT VT = N->getValueType(0);
6826 SelectionDAG &DAG = DCI.DAG;
6828 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
6831 APInt SplatBits, SplatUndef;
6832 unsigned SplatBitSize;
6835 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
6836 if (SplatBitSize <= 64) {
6838 SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(),
6839 SplatUndef.getZExtValue(), SplatBitSize,
6840 DAG, VbicVT, VT.is128BitVector(),
6842 if (Val.getNode()) {
6844 DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0));
6845 SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val);
6846 return DAG.getNode(ISD::BITCAST, dl, VT, Vbic);
6854 /// PerformORCombine - Target-specific dag combine xforms for ISD::OR
6855 static SDValue PerformORCombine(SDNode *N,
6856 TargetLowering::DAGCombinerInfo &DCI,
6857 const ARMSubtarget *Subtarget) {
6858 // Attempt to use immediate-form VORR
6859 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
6860 DebugLoc dl = N->getDebugLoc();
6861 EVT VT = N->getValueType(0);
6862 SelectionDAG &DAG = DCI.DAG;
6864 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
6867 APInt SplatBits, SplatUndef;
6868 unsigned SplatBitSize;
6870 if (BVN && Subtarget->hasNEON() &&
6871 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
6872 if (SplatBitSize <= 64) {
6874 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
6875 SplatUndef.getZExtValue(), SplatBitSize,
6876 DAG, VorrVT, VT.is128BitVector(),
6878 if (Val.getNode()) {
6880 DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0));
6881 SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val);
6882 return DAG.getNode(ISD::BITCAST, dl, VT, Vorr);
6887 SDValue N0 = N->getOperand(0);
6888 if (N0.getOpcode() != ISD::AND)
6890 SDValue N1 = N->getOperand(1);
6892 // (or (and B, A), (and C, ~A)) => (VBSL A, B, C) when A is a constant.
6893 if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() &&
6894 DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
6896 unsigned SplatBitSize;
6899 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1));
6901 if (BVN0 && BVN0->isConstantSplat(SplatBits0, SplatUndef, SplatBitSize,
6902 HasAnyUndefs) && !HasAnyUndefs) {
6903 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(1));
6905 if (BVN1 && BVN1->isConstantSplat(SplatBits1, SplatUndef, SplatBitSize,
6906 HasAnyUndefs) && !HasAnyUndefs &&
6907 SplatBits0 == ~SplatBits1) {
6908 // Canonicalize the vector type to make instruction selection simpler.
6909 EVT CanonicalVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
6910 SDValue Result = DAG.getNode(ARMISD::VBSL, dl, CanonicalVT,
6911 N0->getOperand(1), N0->getOperand(0),
6913 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
6918 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when
6921 // BFI is only available on V6T2+
6922 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops())
6925 DebugLoc DL = N->getDebugLoc();
6926 // 1) or (and A, mask), val => ARMbfi A, val, mask
6927 // iff (val & mask) == val
6929 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
6930 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2)
6931 // && mask == ~mask2
6932 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2)
6933 // && ~mask == mask2
6934 // (i.e., copy a bitfield value into another bitfield of the same width)
6939 SDValue N00 = N0.getOperand(0);
6941 // The value and the mask need to be constants so we can verify this is
6942 // actually a bitfield set. If the mask is 0xffff, we can do better
6943 // via a movt instruction, so don't use BFI in that case.
6944 SDValue MaskOp = N0.getOperand(1);
6945 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(MaskOp);
6948 unsigned Mask = MaskC->getZExtValue();
6952 // Case (1): or (and A, mask), val => ARMbfi A, val, mask
6953 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
6955 unsigned Val = N1C->getZExtValue();
6956 if ((Val & ~Mask) != Val)
6959 if (ARM::isBitFieldInvertedMask(Mask)) {
6960 Val >>= CountTrailingZeros_32(~Mask);
6962 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00,
6963 DAG.getConstant(Val, MVT::i32),
6964 DAG.getConstant(Mask, MVT::i32));
6966 // Do not add new nodes to DAG combiner worklist.
6967 DCI.CombineTo(N, Res, false);
6970 } else if (N1.getOpcode() == ISD::AND) {
6971 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
6972 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
6975 unsigned Mask2 = N11C->getZExtValue();
6977 // Mask and ~Mask2 (or reverse) must be equivalent for the BFI pattern
6979 if (ARM::isBitFieldInvertedMask(Mask) &&
6981 // The pack halfword instruction works better for masks that fit it,
6982 // so use that when it's available.
6983 if (Subtarget->hasT2ExtractPack() &&
6984 (Mask == 0xffff || Mask == 0xffff0000))
6987 unsigned amt = CountTrailingZeros_32(Mask2);
6988 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
6989 DAG.getConstant(amt, MVT::i32));
6990 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res,
6991 DAG.getConstant(Mask, MVT::i32));
6992 // Do not add new nodes to DAG combiner worklist.
6993 DCI.CombineTo(N, Res, false);
6995 } else if (ARM::isBitFieldInvertedMask(~Mask) &&
6997 // The pack halfword instruction works better for masks that fit it,
6998 // so use that when it's available.
6999 if (Subtarget->hasT2ExtractPack() &&
7000 (Mask2 == 0xffff || Mask2 == 0xffff0000))
7003 unsigned lsb = CountTrailingZeros_32(Mask);
7004 Res = DAG.getNode(ISD::SRL, DL, VT, N00,
7005 DAG.getConstant(lsb, MVT::i32));
7006 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
7007 DAG.getConstant(Mask2, MVT::i32));
7008 // Do not add new nodes to DAG combiner worklist.
7009 DCI.CombineTo(N, Res, false);
7014 if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) &&
7015 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) &&
7016 ARM::isBitFieldInvertedMask(~Mask)) {
7017 // Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask
7018 // where lsb(mask) == #shamt and masked bits of B are known zero.
7019 SDValue ShAmt = N00.getOperand(1);
7020 unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue();
7021 unsigned LSB = CountTrailingZeros_32(Mask);
7025 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0),
7026 DAG.getConstant(~Mask, MVT::i32));
7028 // Do not add new nodes to DAG combiner worklist.
7029 DCI.CombineTo(N, Res, false);
7035 /// PerformBFICombine - (bfi A, (and B, Mask1), Mask2) -> (bfi A, B, Mask2) iff
7036 /// the bits being cleared by the AND are not demanded by the BFI.
7037 static SDValue PerformBFICombine(SDNode *N,
7038 TargetLowering::DAGCombinerInfo &DCI) {
7039 SDValue N1 = N->getOperand(1);
7040 if (N1.getOpcode() == ISD::AND) {
7041 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
7044 unsigned InvMask = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
7045 unsigned LSB = CountTrailingZeros_32(~InvMask);
7046 unsigned Width = (32 - CountLeadingZeros_32(~InvMask)) - LSB;
7047 unsigned Mask = (1 << Width)-1;
7048 unsigned Mask2 = N11C->getZExtValue();
7049 if ((Mask & (~Mask2)) == 0)
7050 return DCI.DAG.getNode(ARMISD::BFI, N->getDebugLoc(), N->getValueType(0),
7051 N->getOperand(0), N1.getOperand(0),
7057 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
7058 /// ARMISD::VMOVRRD.
7059 static SDValue PerformVMOVRRDCombine(SDNode *N,
7060 TargetLowering::DAGCombinerInfo &DCI) {
7061 // vmovrrd(vmovdrr x, y) -> x,y
7062 SDValue InDouble = N->getOperand(0);
7063 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
7064 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
7066 // vmovrrd(load f64) -> (load i32), (load i32)
7067 SDNode *InNode = InDouble.getNode();
7068 if (ISD::isNormalLoad(InNode) && InNode->hasOneUse() &&
7069 InNode->getValueType(0) == MVT::f64 &&
7070 InNode->getOperand(1).getOpcode() == ISD::FrameIndex &&
7071 !cast<LoadSDNode>(InNode)->isVolatile()) {
7072 // TODO: Should this be done for non-FrameIndex operands?
7073 LoadSDNode *LD = cast<LoadSDNode>(InNode);
7075 SelectionDAG &DAG = DCI.DAG;
7076 DebugLoc DL = LD->getDebugLoc();
7077 SDValue BasePtr = LD->getBasePtr();
7078 SDValue NewLD1 = DAG.getLoad(MVT::i32, DL, LD->getChain(), BasePtr,
7079 LD->getPointerInfo(), LD->isVolatile(),
7080 LD->isNonTemporal(), LD->isInvariant(),
7081 LD->getAlignment());
7083 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
7084 DAG.getConstant(4, MVT::i32));
7085 SDValue NewLD2 = DAG.getLoad(MVT::i32, DL, NewLD1.getValue(1), OffsetPtr,
7086 LD->getPointerInfo(), LD->isVolatile(),
7087 LD->isNonTemporal(), LD->isInvariant(),
7088 std::min(4U, LD->getAlignment() / 2));
7090 DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), NewLD2.getValue(1));
7091 SDValue Result = DCI.CombineTo(N, NewLD1, NewLD2);
7092 DCI.RemoveFromWorklist(LD);
7100 /// PerformVMOVDRRCombine - Target-specific dag combine xforms for
7101 /// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands.
7102 static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) {
7103 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X)
7104 SDValue Op0 = N->getOperand(0);
7105 SDValue Op1 = N->getOperand(1);
7106 if (Op0.getOpcode() == ISD::BITCAST)
7107 Op0 = Op0.getOperand(0);
7108 if (Op1.getOpcode() == ISD::BITCAST)
7109 Op1 = Op1.getOperand(0);
7110 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
7111 Op0.getNode() == Op1.getNode() &&
7112 Op0.getResNo() == 0 && Op1.getResNo() == 1)
7113 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
7114 N->getValueType(0), Op0.getOperand(0));
7118 /// PerformSTORECombine - Target-specific dag combine xforms for
7120 static SDValue PerformSTORECombine(SDNode *N,
7121 TargetLowering::DAGCombinerInfo &DCI) {
7122 // Bitcast an i64 store extracted from a vector to f64.
7123 // Otherwise, the i64 value will be legalized to a pair of i32 values.
7124 StoreSDNode *St = cast<StoreSDNode>(N);
7125 SDValue StVal = St->getValue();
7126 if (!ISD::isNormalStore(St) || St->isVolatile())
7129 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR &&
7130 StVal.getNode()->hasOneUse() && !St->isVolatile()) {
7131 SelectionDAG &DAG = DCI.DAG;
7132 DebugLoc DL = St->getDebugLoc();
7133 SDValue BasePtr = St->getBasePtr();
7134 SDValue NewST1 = DAG.getStore(St->getChain(), DL,
7135 StVal.getNode()->getOperand(0), BasePtr,
7136 St->getPointerInfo(), St->isVolatile(),
7137 St->isNonTemporal(), St->getAlignment());
7139 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
7140 DAG.getConstant(4, MVT::i32));
7141 return DAG.getStore(NewST1.getValue(0), DL, StVal.getNode()->getOperand(1),
7142 OffsetPtr, St->getPointerInfo(), St->isVolatile(),
7143 St->isNonTemporal(),
7144 std::min(4U, St->getAlignment() / 2));
7147 if (StVal.getValueType() != MVT::i64 ||
7148 StVal.getNode()->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
7151 SelectionDAG &DAG = DCI.DAG;
7152 DebugLoc dl = StVal.getDebugLoc();
7153 SDValue IntVec = StVal.getOperand(0);
7154 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
7155 IntVec.getValueType().getVectorNumElements());
7156 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec);
7157 SDValue ExtElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
7158 Vec, StVal.getOperand(1));
7159 dl = N->getDebugLoc();
7160 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt);
7161 // Make the DAGCombiner fold the bitcasts.
7162 DCI.AddToWorklist(Vec.getNode());
7163 DCI.AddToWorklist(ExtElt.getNode());
7164 DCI.AddToWorklist(V.getNode());
7165 return DAG.getStore(St->getChain(), dl, V, St->getBasePtr(),
7166 St->getPointerInfo(), St->isVolatile(),
7167 St->isNonTemporal(), St->getAlignment(),
7171 /// hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node
7172 /// are normal, non-volatile loads. If so, it is profitable to bitcast an
7173 /// i64 vector to have f64 elements, since the value can then be loaded
7174 /// directly into a VFP register.
7175 static bool hasNormalLoadOperand(SDNode *N) {
7176 unsigned NumElts = N->getValueType(0).getVectorNumElements();
7177 for (unsigned i = 0; i < NumElts; ++i) {
7178 SDNode *Elt = N->getOperand(i).getNode();
7179 if (ISD::isNormalLoad(Elt) && !cast<LoadSDNode>(Elt)->isVolatile())
7185 /// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for
7186 /// ISD::BUILD_VECTOR.
7187 static SDValue PerformBUILD_VECTORCombine(SDNode *N,
7188 TargetLowering::DAGCombinerInfo &DCI){
7189 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X):
7190 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value
7191 // into a pair of GPRs, which is fine when the value is used as a scalar,
7192 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD.
7193 SelectionDAG &DAG = DCI.DAG;
7194 if (N->getNumOperands() == 2) {
7195 SDValue RV = PerformVMOVDRRCombine(N, DAG);
7200 // Load i64 elements as f64 values so that type legalization does not split
7201 // them up into i32 values.
7202 EVT VT = N->getValueType(0);
7203 if (VT.getVectorElementType() != MVT::i64 || !hasNormalLoadOperand(N))
7205 DebugLoc dl = N->getDebugLoc();
7206 SmallVector<SDValue, 8> Ops;
7207 unsigned NumElts = VT.getVectorNumElements();
7208 for (unsigned i = 0; i < NumElts; ++i) {
7209 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(i));
7211 // Make the DAGCombiner fold the bitcast.
7212 DCI.AddToWorklist(V.getNode());
7214 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, NumElts);
7215 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, FloatVT, Ops.data(), NumElts);
7216 return DAG.getNode(ISD::BITCAST, dl, VT, BV);
7219 /// PerformInsertEltCombine - Target-specific dag combine xforms for
7220 /// ISD::INSERT_VECTOR_ELT.
7221 static SDValue PerformInsertEltCombine(SDNode *N,
7222 TargetLowering::DAGCombinerInfo &DCI) {
7223 // Bitcast an i64 load inserted into a vector to f64.
7224 // Otherwise, the i64 value will be legalized to a pair of i32 values.
7225 EVT VT = N->getValueType(0);
7226 SDNode *Elt = N->getOperand(1).getNode();
7227 if (VT.getVectorElementType() != MVT::i64 ||
7228 !ISD::isNormalLoad(Elt) || cast<LoadSDNode>(Elt)->isVolatile())
7231 SelectionDAG &DAG = DCI.DAG;
7232 DebugLoc dl = N->getDebugLoc();
7233 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
7234 VT.getVectorNumElements());
7235 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, N->getOperand(0));
7236 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(1));
7237 // Make the DAGCombiner fold the bitcasts.
7238 DCI.AddToWorklist(Vec.getNode());
7239 DCI.AddToWorklist(V.getNode());
7240 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT,
7241 Vec, V, N->getOperand(2));
7242 return DAG.getNode(ISD::BITCAST, dl, VT, InsElt);
7245 /// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for
7246 /// ISD::VECTOR_SHUFFLE.
7247 static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) {
7248 // The LLVM shufflevector instruction does not require the shuffle mask
7249 // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does
7250 // have that requirement. When translating to ISD::VECTOR_SHUFFLE, if the
7251 // operands do not match the mask length, they are extended by concatenating
7252 // them with undef vectors. That is probably the right thing for other
7253 // targets, but for NEON it is better to concatenate two double-register
7254 // size vector operands into a single quad-register size vector. Do that
7255 // transformation here:
7256 // shuffle(concat(v1, undef), concat(v2, undef)) ->
7257 // shuffle(concat(v1, v2), undef)
7258 SDValue Op0 = N->getOperand(0);
7259 SDValue Op1 = N->getOperand(1);
7260 if (Op0.getOpcode() != ISD::CONCAT_VECTORS ||
7261 Op1.getOpcode() != ISD::CONCAT_VECTORS ||
7262 Op0.getNumOperands() != 2 ||
7263 Op1.getNumOperands() != 2)
7265 SDValue Concat0Op1 = Op0.getOperand(1);
7266 SDValue Concat1Op1 = Op1.getOperand(1);
7267 if (Concat0Op1.getOpcode() != ISD::UNDEF ||
7268 Concat1Op1.getOpcode() != ISD::UNDEF)
7270 // Skip the transformation if any of the types are illegal.
7271 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7272 EVT VT = N->getValueType(0);
7273 if (!TLI.isTypeLegal(VT) ||
7274 !TLI.isTypeLegal(Concat0Op1.getValueType()) ||
7275 !TLI.isTypeLegal(Concat1Op1.getValueType()))
7278 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT,
7279 Op0.getOperand(0), Op1.getOperand(0));
7280 // Translate the shuffle mask.
7281 SmallVector<int, 16> NewMask;
7282 unsigned NumElts = VT.getVectorNumElements();
7283 unsigned HalfElts = NumElts/2;
7284 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
7285 for (unsigned n = 0; n < NumElts; ++n) {
7286 int MaskElt = SVN->getMaskElt(n);
7288 if (MaskElt < (int)HalfElts)
7290 else if (MaskElt >= (int)NumElts && MaskElt < (int)(NumElts + HalfElts))
7291 NewElt = HalfElts + MaskElt - NumElts;
7292 NewMask.push_back(NewElt);
7294 return DAG.getVectorShuffle(VT, N->getDebugLoc(), NewConcat,
7295 DAG.getUNDEF(VT), NewMask.data());
7298 /// CombineBaseUpdate - Target-specific DAG combine function for VLDDUP and
7299 /// NEON load/store intrinsics to merge base address updates.
7300 static SDValue CombineBaseUpdate(SDNode *N,
7301 TargetLowering::DAGCombinerInfo &DCI) {
7302 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
7305 SelectionDAG &DAG = DCI.DAG;
7306 bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID ||
7307 N->getOpcode() == ISD::INTRINSIC_W_CHAIN);
7308 unsigned AddrOpIdx = (isIntrinsic ? 2 : 1);
7309 SDValue Addr = N->getOperand(AddrOpIdx);
7311 // Search for a use of the address operand that is an increment.
7312 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
7313 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
7315 if (User->getOpcode() != ISD::ADD ||
7316 UI.getUse().getResNo() != Addr.getResNo())
7319 // Check that the add is independent of the load/store. Otherwise, folding
7320 // it would create a cycle.
7321 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
7324 // Find the new opcode for the updating load/store.
7326 bool isLaneOp = false;
7327 unsigned NewOpc = 0;
7328 unsigned NumVecs = 0;
7330 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
7332 default: llvm_unreachable("unexpected intrinsic for Neon base update");
7333 case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD;
7335 case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD;
7337 case Intrinsic::arm_neon_vld3: NewOpc = ARMISD::VLD3_UPD;
7339 case Intrinsic::arm_neon_vld4: NewOpc = ARMISD::VLD4_UPD;
7341 case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD;
7342 NumVecs = 2; isLaneOp = true; break;
7343 case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD;
7344 NumVecs = 3; isLaneOp = true; break;
7345 case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD;
7346 NumVecs = 4; isLaneOp = true; break;
7347 case Intrinsic::arm_neon_vst1: NewOpc = ARMISD::VST1_UPD;
7348 NumVecs = 1; isLoad = false; break;
7349 case Intrinsic::arm_neon_vst2: NewOpc = ARMISD::VST2_UPD;
7350 NumVecs = 2; isLoad = false; break;
7351 case Intrinsic::arm_neon_vst3: NewOpc = ARMISD::VST3_UPD;
7352 NumVecs = 3; isLoad = false; break;
7353 case Intrinsic::arm_neon_vst4: NewOpc = ARMISD::VST4_UPD;
7354 NumVecs = 4; isLoad = false; break;
7355 case Intrinsic::arm_neon_vst2lane: NewOpc = ARMISD::VST2LN_UPD;
7356 NumVecs = 2; isLoad = false; isLaneOp = true; break;
7357 case Intrinsic::arm_neon_vst3lane: NewOpc = ARMISD::VST3LN_UPD;
7358 NumVecs = 3; isLoad = false; isLaneOp = true; break;
7359 case Intrinsic::arm_neon_vst4lane: NewOpc = ARMISD::VST4LN_UPD;
7360 NumVecs = 4; isLoad = false; isLaneOp = true; break;
7364 switch (N->getOpcode()) {
7365 default: llvm_unreachable("unexpected opcode for Neon base update");
7366 case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break;
7367 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break;
7368 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break;
7372 // Find the size of memory referenced by the load/store.
7375 VecTy = N->getValueType(0);
7377 VecTy = N->getOperand(AddrOpIdx+1).getValueType();
7378 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
7380 NumBytes /= VecTy.getVectorNumElements();
7382 // If the increment is a constant, it must match the memory ref size.
7383 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
7384 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
7385 uint64_t IncVal = CInc->getZExtValue();
7386 if (IncVal != NumBytes)
7388 } else if (NumBytes >= 3 * 16) {
7389 // VLD3/4 and VST3/4 for 128-bit vectors are implemented with two
7390 // separate instructions that make it harder to use a non-constant update.
7394 // Create the new updating load/store node.
7396 unsigned NumResultVecs = (isLoad ? NumVecs : 0);
7398 for (n = 0; n < NumResultVecs; ++n)
7400 Tys[n++] = MVT::i32;
7401 Tys[n] = MVT::Other;
7402 SDVTList SDTys = DAG.getVTList(Tys, NumResultVecs+2);
7403 SmallVector<SDValue, 8> Ops;
7404 Ops.push_back(N->getOperand(0)); // incoming chain
7405 Ops.push_back(N->getOperand(AddrOpIdx));
7407 for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands(); ++i) {
7408 Ops.push_back(N->getOperand(i));
7410 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
7411 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, N->getDebugLoc(), SDTys,
7412 Ops.data(), Ops.size(),
7413 MemInt->getMemoryVT(),
7414 MemInt->getMemOperand());
7417 std::vector<SDValue> NewResults;
7418 for (unsigned i = 0; i < NumResultVecs; ++i) {
7419 NewResults.push_back(SDValue(UpdN.getNode(), i));
7421 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs+1)); // chain
7422 DCI.CombineTo(N, NewResults);
7423 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
7430 /// CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a
7431 /// vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic
7432 /// are also VDUPLANEs. If so, combine them to a vldN-dup operation and
7434 static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
7435 SelectionDAG &DAG = DCI.DAG;
7436 EVT VT = N->getValueType(0);
7437 // vldN-dup instructions only support 64-bit vectors for N > 1.
7438 if (!VT.is64BitVector())
7441 // Check if the VDUPLANE operand is a vldN-dup intrinsic.
7442 SDNode *VLD = N->getOperand(0).getNode();
7443 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN)
7445 unsigned NumVecs = 0;
7446 unsigned NewOpc = 0;
7447 unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue();
7448 if (IntNo == Intrinsic::arm_neon_vld2lane) {
7450 NewOpc = ARMISD::VLD2DUP;
7451 } else if (IntNo == Intrinsic::arm_neon_vld3lane) {
7453 NewOpc = ARMISD::VLD3DUP;
7454 } else if (IntNo == Intrinsic::arm_neon_vld4lane) {
7456 NewOpc = ARMISD::VLD4DUP;
7461 // First check that all the vldN-lane uses are VDUPLANEs and that the lane
7462 // numbers match the load.
7463 unsigned VLDLaneNo =
7464 cast<ConstantSDNode>(VLD->getOperand(NumVecs+3))->getZExtValue();
7465 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
7467 // Ignore uses of the chain result.
7468 if (UI.getUse().getResNo() == NumVecs)
7471 if (User->getOpcode() != ARMISD::VDUPLANE ||
7472 VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue())
7476 // Create the vldN-dup node.
7479 for (n = 0; n < NumVecs; ++n)
7481 Tys[n] = MVT::Other;
7482 SDVTList SDTys = DAG.getVTList(Tys, NumVecs+1);
7483 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) };
7484 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD);
7485 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, VLD->getDebugLoc(), SDTys,
7486 Ops, 2, VLDMemInt->getMemoryVT(),
7487 VLDMemInt->getMemOperand());
7490 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
7492 unsigned ResNo = UI.getUse().getResNo();
7493 // Ignore uses of the chain result.
7494 if (ResNo == NumVecs)
7497 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo));
7500 // Now the vldN-lane intrinsic is dead except for its chain result.
7501 // Update uses of the chain.
7502 std::vector<SDValue> VLDDupResults;
7503 for (unsigned n = 0; n < NumVecs; ++n)
7504 VLDDupResults.push_back(SDValue(VLDDup.getNode(), n));
7505 VLDDupResults.push_back(SDValue(VLDDup.getNode(), NumVecs));
7506 DCI.CombineTo(VLD, VLDDupResults);
7511 /// PerformVDUPLANECombine - Target-specific dag combine xforms for
7512 /// ARMISD::VDUPLANE.
7513 static SDValue PerformVDUPLANECombine(SDNode *N,
7514 TargetLowering::DAGCombinerInfo &DCI) {
7515 SDValue Op = N->getOperand(0);
7517 // If the source is a vldN-lane (N > 1) intrinsic, and all the other uses
7518 // of that intrinsic are also VDUPLANEs, combine them to a vldN-dup operation.
7519 if (CombineVLDDUP(N, DCI))
7520 return SDValue(N, 0);
7522 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
7523 // redundant. Ignore bit_converts for now; element sizes are checked below.
7524 while (Op.getOpcode() == ISD::BITCAST)
7525 Op = Op.getOperand(0);
7526 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
7529 // Make sure the VMOV element size is not bigger than the VDUPLANE elements.
7530 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits();
7531 // The canonical VMOV for a zero vector uses a 32-bit element size.
7532 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7534 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
7536 EVT VT = N->getValueType(0);
7537 if (EltSize > VT.getVectorElementType().getSizeInBits())
7540 return DCI.DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
7543 // isConstVecPow2 - Return true if each vector element is a power of 2, all
7544 // elements are the same constant, C, and Log2(C) ranges from 1 to 32.
7545 static bool isConstVecPow2(SDValue ConstVec, bool isSigned, uint64_t &C)
7549 for (unsigned I = 0, E = ConstVec.getValueType().getVectorNumElements();
7551 ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(ConstVec.getOperand(I));
7556 APFloat APF = C->getValueAPF();
7557 if (APF.convertToInteger(&cN, 64, isSigned, APFloat::rmTowardZero, &isExact)
7558 != APFloat::opOK || !isExact)
7561 c0 = (I == 0) ? cN : c0;
7562 if (!isPowerOf2_64(cN) || c0 != cN || Log2_64(c0) < 1 || Log2_64(c0) > 32)
7569 /// PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD)
7570 /// can replace combinations of VMUL and VCVT (floating-point to integer)
7571 /// when the VMUL has a constant operand that is a power of 2.
7573 /// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
7574 /// vmul.f32 d16, d17, d16
7575 /// vcvt.s32.f32 d16, d16
7577 /// vcvt.s32.f32 d16, d16, #3
7578 static SDValue PerformVCVTCombine(SDNode *N,
7579 TargetLowering::DAGCombinerInfo &DCI,
7580 const ARMSubtarget *Subtarget) {
7581 SelectionDAG &DAG = DCI.DAG;
7582 SDValue Op = N->getOperand(0);
7584 if (!Subtarget->hasNEON() || !Op.getValueType().isVector() ||
7585 Op.getOpcode() != ISD::FMUL)
7589 SDValue N0 = Op->getOperand(0);
7590 SDValue ConstVec = Op->getOperand(1);
7591 bool isSigned = N->getOpcode() == ISD::FP_TO_SINT;
7593 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
7594 !isConstVecPow2(ConstVec, isSigned, C))
7597 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfp2fxs :
7598 Intrinsic::arm_neon_vcvtfp2fxu;
7599 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(),
7601 DAG.getConstant(IntrinsicOpcode, MVT::i32), N0,
7602 DAG.getConstant(Log2_64(C), MVT::i32));
7605 /// PerformVDIVCombine - VCVT (fixed-point to floating-point, Advanced SIMD)
7606 /// can replace combinations of VCVT (integer to floating-point) and VDIV
7607 /// when the VDIV has a constant operand that is a power of 2.
7609 /// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
7610 /// vcvt.f32.s32 d16, d16
7611 /// vdiv.f32 d16, d17, d16
7613 /// vcvt.f32.s32 d16, d16, #3
7614 static SDValue PerformVDIVCombine(SDNode *N,
7615 TargetLowering::DAGCombinerInfo &DCI,
7616 const ARMSubtarget *Subtarget) {
7617 SelectionDAG &DAG = DCI.DAG;
7618 SDValue Op = N->getOperand(0);
7619 unsigned OpOpcode = Op.getNode()->getOpcode();
7621 if (!Subtarget->hasNEON() || !N->getValueType(0).isVector() ||
7622 (OpOpcode != ISD::SINT_TO_FP && OpOpcode != ISD::UINT_TO_FP))
7626 SDValue ConstVec = N->getOperand(1);
7627 bool isSigned = OpOpcode == ISD::SINT_TO_FP;
7629 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
7630 !isConstVecPow2(ConstVec, isSigned, C))
7633 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfxs2fp :
7634 Intrinsic::arm_neon_vcvtfxu2fp;
7635 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(),
7637 DAG.getConstant(IntrinsicOpcode, MVT::i32),
7638 Op.getOperand(0), DAG.getConstant(Log2_64(C), MVT::i32));
7641 /// Getvshiftimm - Check if this is a valid build_vector for the immediate
7642 /// operand of a vector shift operation, where all the elements of the
7643 /// build_vector must have the same constant integer value.
7644 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
7645 // Ignore bit_converts.
7646 while (Op.getOpcode() == ISD::BITCAST)
7647 Op = Op.getOperand(0);
7648 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
7649 APInt SplatBits, SplatUndef;
7650 unsigned SplatBitSize;
7652 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
7653 HasAnyUndefs, ElementBits) ||
7654 SplatBitSize > ElementBits)
7656 Cnt = SplatBits.getSExtValue();
7660 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
7661 /// operand of a vector shift left operation. That value must be in the range:
7662 /// 0 <= Value < ElementBits for a left shift; or
7663 /// 0 <= Value <= ElementBits for a long left shift.
7664 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
7665 assert(VT.isVector() && "vector shift count is not a vector type");
7666 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
7667 if (! getVShiftImm(Op, ElementBits, Cnt))
7669 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
7672 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
7673 /// operand of a vector shift right operation. For a shift opcode, the value
7674 /// is positive, but for an intrinsic the value count must be negative. The
7675 /// absolute value must be in the range:
7676 /// 1 <= |Value| <= ElementBits for a right shift; or
7677 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
7678 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
7680 assert(VT.isVector() && "vector shift count is not a vector type");
7681 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
7682 if (! getVShiftImm(Op, ElementBits, Cnt))
7686 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
7689 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
7690 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
7691 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
7694 // Don't do anything for most intrinsics.
7697 // Vector shifts: check for immediate versions and lower them.
7698 // Note: This is done during DAG combining instead of DAG legalizing because
7699 // the build_vectors for 64-bit vector element shift counts are generally
7700 // not legal, and it is hard to see their values after they get legalized to
7701 // loads from a constant pool.
7702 case Intrinsic::arm_neon_vshifts:
7703 case Intrinsic::arm_neon_vshiftu:
7704 case Intrinsic::arm_neon_vshiftls:
7705 case Intrinsic::arm_neon_vshiftlu:
7706 case Intrinsic::arm_neon_vshiftn:
7707 case Intrinsic::arm_neon_vrshifts:
7708 case Intrinsic::arm_neon_vrshiftu:
7709 case Intrinsic::arm_neon_vrshiftn:
7710 case Intrinsic::arm_neon_vqshifts:
7711 case Intrinsic::arm_neon_vqshiftu:
7712 case Intrinsic::arm_neon_vqshiftsu:
7713 case Intrinsic::arm_neon_vqshiftns:
7714 case Intrinsic::arm_neon_vqshiftnu:
7715 case Intrinsic::arm_neon_vqshiftnsu:
7716 case Intrinsic::arm_neon_vqrshiftns:
7717 case Intrinsic::arm_neon_vqrshiftnu:
7718 case Intrinsic::arm_neon_vqrshiftnsu: {
7719 EVT VT = N->getOperand(1).getValueType();
7721 unsigned VShiftOpc = 0;
7724 case Intrinsic::arm_neon_vshifts:
7725 case Intrinsic::arm_neon_vshiftu:
7726 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
7727 VShiftOpc = ARMISD::VSHL;
7730 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
7731 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
7732 ARMISD::VSHRs : ARMISD::VSHRu);
7737 case Intrinsic::arm_neon_vshiftls:
7738 case Intrinsic::arm_neon_vshiftlu:
7739 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
7741 llvm_unreachable("invalid shift count for vshll intrinsic");
7743 case Intrinsic::arm_neon_vrshifts:
7744 case Intrinsic::arm_neon_vrshiftu:
7745 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
7749 case Intrinsic::arm_neon_vqshifts:
7750 case Intrinsic::arm_neon_vqshiftu:
7751 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
7755 case Intrinsic::arm_neon_vqshiftsu:
7756 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
7758 llvm_unreachable("invalid shift count for vqshlu intrinsic");
7760 case Intrinsic::arm_neon_vshiftn:
7761 case Intrinsic::arm_neon_vrshiftn:
7762 case Intrinsic::arm_neon_vqshiftns:
7763 case Intrinsic::arm_neon_vqshiftnu:
7764 case Intrinsic::arm_neon_vqshiftnsu:
7765 case Intrinsic::arm_neon_vqrshiftns:
7766 case Intrinsic::arm_neon_vqrshiftnu:
7767 case Intrinsic::arm_neon_vqrshiftnsu:
7768 // Narrowing shifts require an immediate right shift.
7769 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
7771 llvm_unreachable("invalid shift count for narrowing vector shift "
7775 llvm_unreachable("unhandled vector shift");
7779 case Intrinsic::arm_neon_vshifts:
7780 case Intrinsic::arm_neon_vshiftu:
7781 // Opcode already set above.
7783 case Intrinsic::arm_neon_vshiftls:
7784 case Intrinsic::arm_neon_vshiftlu:
7785 if (Cnt == VT.getVectorElementType().getSizeInBits())
7786 VShiftOpc = ARMISD::VSHLLi;
7788 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
7789 ARMISD::VSHLLs : ARMISD::VSHLLu);
7791 case Intrinsic::arm_neon_vshiftn:
7792 VShiftOpc = ARMISD::VSHRN; break;
7793 case Intrinsic::arm_neon_vrshifts:
7794 VShiftOpc = ARMISD::VRSHRs; break;
7795 case Intrinsic::arm_neon_vrshiftu:
7796 VShiftOpc = ARMISD::VRSHRu; break;
7797 case Intrinsic::arm_neon_vrshiftn:
7798 VShiftOpc = ARMISD::VRSHRN; break;
7799 case Intrinsic::arm_neon_vqshifts:
7800 VShiftOpc = ARMISD::VQSHLs; break;
7801 case Intrinsic::arm_neon_vqshiftu:
7802 VShiftOpc = ARMISD::VQSHLu; break;
7803 case Intrinsic::arm_neon_vqshiftsu:
7804 VShiftOpc = ARMISD::VQSHLsu; break;
7805 case Intrinsic::arm_neon_vqshiftns:
7806 VShiftOpc = ARMISD::VQSHRNs; break;
7807 case Intrinsic::arm_neon_vqshiftnu:
7808 VShiftOpc = ARMISD::VQSHRNu; break;
7809 case Intrinsic::arm_neon_vqshiftnsu:
7810 VShiftOpc = ARMISD::VQSHRNsu; break;
7811 case Intrinsic::arm_neon_vqrshiftns:
7812 VShiftOpc = ARMISD::VQRSHRNs; break;
7813 case Intrinsic::arm_neon_vqrshiftnu:
7814 VShiftOpc = ARMISD::VQRSHRNu; break;
7815 case Intrinsic::arm_neon_vqrshiftnsu:
7816 VShiftOpc = ARMISD::VQRSHRNsu; break;
7819 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
7820 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
7823 case Intrinsic::arm_neon_vshiftins: {
7824 EVT VT = N->getOperand(1).getValueType();
7826 unsigned VShiftOpc = 0;
7828 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
7829 VShiftOpc = ARMISD::VSLI;
7830 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
7831 VShiftOpc = ARMISD::VSRI;
7833 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
7836 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
7837 N->getOperand(1), N->getOperand(2),
7838 DAG.getConstant(Cnt, MVT::i32));
7841 case Intrinsic::arm_neon_vqrshifts:
7842 case Intrinsic::arm_neon_vqrshiftu:
7843 // No immediate versions of these to check for.
7850 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
7851 /// lowers them. As with the vector shift intrinsics, this is done during DAG
7852 /// combining instead of DAG legalizing because the build_vectors for 64-bit
7853 /// vector element shift counts are generally not legal, and it is hard to see
7854 /// their values after they get legalized to loads from a constant pool.
7855 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
7856 const ARMSubtarget *ST) {
7857 EVT VT = N->getValueType(0);
7859 // Nothing to be done for scalar shifts.
7860 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7861 if (!VT.isVector() || !TLI.isTypeLegal(VT))
7864 assert(ST->hasNEON() && "unexpected vector shift");
7867 switch (N->getOpcode()) {
7868 default: llvm_unreachable("unexpected shift opcode");
7871 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
7872 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
7873 DAG.getConstant(Cnt, MVT::i32));
7878 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
7879 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
7880 ARMISD::VSHRs : ARMISD::VSHRu);
7881 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
7882 DAG.getConstant(Cnt, MVT::i32));
7888 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
7889 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
7890 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
7891 const ARMSubtarget *ST) {
7892 SDValue N0 = N->getOperand(0);
7894 // Check for sign- and zero-extensions of vector extract operations of 8-
7895 // and 16-bit vector elements. NEON supports these directly. They are
7896 // handled during DAG combining because type legalization will promote them
7897 // to 32-bit types and it is messy to recognize the operations after that.
7898 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
7899 SDValue Vec = N0.getOperand(0);
7900 SDValue Lane = N0.getOperand(1);
7901 EVT VT = N->getValueType(0);
7902 EVT EltVT = N0.getValueType();
7903 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7905 if (VT == MVT::i32 &&
7906 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
7907 TLI.isTypeLegal(Vec.getValueType()) &&
7908 isa<ConstantSDNode>(Lane)) {
7911 switch (N->getOpcode()) {
7912 default: llvm_unreachable("unexpected opcode");
7913 case ISD::SIGN_EXTEND:
7914 Opc = ARMISD::VGETLANEs;
7916 case ISD::ZERO_EXTEND:
7917 case ISD::ANY_EXTEND:
7918 Opc = ARMISD::VGETLANEu;
7921 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
7928 /// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
7929 /// to match f32 max/min patterns to use NEON vmax/vmin instructions.
7930 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
7931 const ARMSubtarget *ST) {
7932 // If the target supports NEON, try to use vmax/vmin instructions for f32
7933 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set,
7934 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
7935 // a NaN; only do the transformation when it matches that behavior.
7937 // For now only do this when using NEON for FP operations; if using VFP, it
7938 // is not obvious that the benefit outweighs the cost of switching to the
7940 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
7941 N->getValueType(0) != MVT::f32)
7944 SDValue CondLHS = N->getOperand(0);
7945 SDValue CondRHS = N->getOperand(1);
7946 SDValue LHS = N->getOperand(2);
7947 SDValue RHS = N->getOperand(3);
7948 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
7950 unsigned Opcode = 0;
7952 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
7953 IsReversed = false; // x CC y ? x : y
7954 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
7955 IsReversed = true ; // x CC y ? y : x
7969 // If LHS is NaN, an ordered comparison will be false and the result will
7970 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
7971 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
7972 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
7973 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
7975 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
7976 // will return -0, so vmin can only be used for unsafe math or if one of
7977 // the operands is known to be nonzero.
7978 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
7979 !DAG.getTarget().Options.UnsafeFPMath &&
7980 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
7982 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
7991 // If LHS is NaN, an ordered comparison will be false and the result will
7992 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
7993 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
7994 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
7995 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
7997 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
7998 // will return +0, so vmax can only be used for unsafe math or if one of
7999 // the operands is known to be nonzero.
8000 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
8001 !DAG.getTarget().Options.UnsafeFPMath &&
8002 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
8004 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
8010 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS);
8013 /// PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV.
8015 ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const {
8016 SDValue Cmp = N->getOperand(4);
8017 if (Cmp.getOpcode() != ARMISD::CMPZ)
8018 // Only looking at EQ and NE cases.
8021 EVT VT = N->getValueType(0);
8022 DebugLoc dl = N->getDebugLoc();
8023 SDValue LHS = Cmp.getOperand(0);
8024 SDValue RHS = Cmp.getOperand(1);
8025 SDValue FalseVal = N->getOperand(0);
8026 SDValue TrueVal = N->getOperand(1);
8027 SDValue ARMcc = N->getOperand(2);
8028 ARMCC::CondCodes CC =
8029 (ARMCC::CondCodes)cast<ConstantSDNode>(ARMcc)->getZExtValue();
8047 /// FIXME: Turn this into a target neutral optimization?
8049 if (CC == ARMCC::NE && FalseVal == RHS && FalseVal != LHS) {
8050 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, TrueVal, ARMcc,
8051 N->getOperand(3), Cmp);
8052 } else if (CC == ARMCC::EQ && TrueVal == RHS) {
8054 SDValue NewCmp = getARMCmp(LHS, RHS, ISD::SETNE, ARMcc, DAG, dl);
8055 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, FalseVal, ARMcc,
8056 N->getOperand(3), NewCmp);
8059 if (Res.getNode()) {
8060 APInt KnownZero, KnownOne;
8061 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
8062 DAG.ComputeMaskedBits(SDValue(N,0), Mask, KnownZero, KnownOne);
8063 // Capture demanded bits information that would be otherwise lost.
8064 if (KnownZero == 0xfffffffe)
8065 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
8066 DAG.getValueType(MVT::i1));
8067 else if (KnownZero == 0xffffff00)
8068 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
8069 DAG.getValueType(MVT::i8));
8070 else if (KnownZero == 0xffff0000)
8071 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
8072 DAG.getValueType(MVT::i16));
8078 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
8079 DAGCombinerInfo &DCI) const {
8080 switch (N->getOpcode()) {
8082 case ISD::ADD: return PerformADDCombine(N, DCI, Subtarget);
8083 case ISD::SUB: return PerformSUBCombine(N, DCI);
8084 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
8085 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
8086 case ISD::AND: return PerformANDCombine(N, DCI);
8087 case ARMISD::BFI: return PerformBFICombine(N, DCI);
8088 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
8089 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
8090 case ISD::STORE: return PerformSTORECombine(N, DCI);
8091 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI);
8092 case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI);
8093 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
8094 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
8095 case ISD::FP_TO_SINT:
8096 case ISD::FP_TO_UINT: return PerformVCVTCombine(N, DCI, Subtarget);
8097 case ISD::FDIV: return PerformVDIVCombine(N, DCI, Subtarget);
8098 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
8101 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
8102 case ISD::SIGN_EXTEND:
8103 case ISD::ZERO_EXTEND:
8104 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
8105 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
8106 case ARMISD::CMOV: return PerformCMOVCombine(N, DCI.DAG);
8107 case ARMISD::VLD2DUP:
8108 case ARMISD::VLD3DUP:
8109 case ARMISD::VLD4DUP:
8110 return CombineBaseUpdate(N, DCI);
8111 case ISD::INTRINSIC_VOID:
8112 case ISD::INTRINSIC_W_CHAIN:
8113 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
8114 case Intrinsic::arm_neon_vld1:
8115 case Intrinsic::arm_neon_vld2:
8116 case Intrinsic::arm_neon_vld3:
8117 case Intrinsic::arm_neon_vld4:
8118 case Intrinsic::arm_neon_vld2lane:
8119 case Intrinsic::arm_neon_vld3lane:
8120 case Intrinsic::arm_neon_vld4lane:
8121 case Intrinsic::arm_neon_vst1:
8122 case Intrinsic::arm_neon_vst2:
8123 case Intrinsic::arm_neon_vst3:
8124 case Intrinsic::arm_neon_vst4:
8125 case Intrinsic::arm_neon_vst2lane:
8126 case Intrinsic::arm_neon_vst3lane:
8127 case Intrinsic::arm_neon_vst4lane:
8128 return CombineBaseUpdate(N, DCI);
8136 bool ARMTargetLowering::isDesirableToTransformToIntegerOp(unsigned Opc,
8138 return (VT == MVT::f32) && (Opc == ISD::LOAD || Opc == ISD::STORE);
8141 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
8142 if (!Subtarget->allowsUnalignedMem())
8145 switch (VT.getSimpleVT().SimpleTy) {
8152 // FIXME: VLD1 etc with standard alignment is legal.
8156 static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign,
8157 unsigned AlignCheck) {
8158 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) &&
8159 (DstAlign == 0 || DstAlign % AlignCheck == 0));
8162 EVT ARMTargetLowering::getOptimalMemOpType(uint64_t Size,
8163 unsigned DstAlign, unsigned SrcAlign,
8166 MachineFunction &MF) const {
8167 const Function *F = MF.getFunction();
8169 // See if we can use NEON instructions for this...
8171 !F->hasFnAttr(Attribute::NoImplicitFloat) &&
8172 Subtarget->hasNEON()) {
8173 if (memOpAlign(SrcAlign, DstAlign, 16) && Size >= 16) {
8175 } else if (memOpAlign(SrcAlign, DstAlign, 8) && Size >= 8) {
8180 // Lowering to i32/i16 if the size permits.
8183 } else if (Size >= 2) {
8187 // Let the target-independent logic figure it out.
8191 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
8196 switch (VT.getSimpleVT().SimpleTy) {
8197 default: return false;
8212 if ((V & (Scale - 1)) != 0)
8215 return V == (V & ((1LL << 5) - 1));
8218 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
8219 const ARMSubtarget *Subtarget) {
8226 switch (VT.getSimpleVT().SimpleTy) {
8227 default: return false;
8232 // + imm12 or - imm8
8234 return V == (V & ((1LL << 8) - 1));
8235 return V == (V & ((1LL << 12) - 1));
8238 // Same as ARM mode. FIXME: NEON?
8239 if (!Subtarget->hasVFP2())
8244 return V == (V & ((1LL << 8) - 1));
8248 /// isLegalAddressImmediate - Return true if the integer value can be used
8249 /// as the offset of the target addressing mode for load / store of the
8251 static bool isLegalAddressImmediate(int64_t V, EVT VT,
8252 const ARMSubtarget *Subtarget) {
8259 if (Subtarget->isThumb1Only())
8260 return isLegalT1AddressImmediate(V, VT);
8261 else if (Subtarget->isThumb2())
8262 return isLegalT2AddressImmediate(V, VT, Subtarget);
8267 switch (VT.getSimpleVT().SimpleTy) {
8268 default: return false;
8273 return V == (V & ((1LL << 12) - 1));
8276 return V == (V & ((1LL << 8) - 1));
8279 if (!Subtarget->hasVFP2()) // FIXME: NEON?
8284 return V == (V & ((1LL << 8) - 1));
8288 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
8290 int Scale = AM.Scale;
8294 switch (VT.getSimpleVT().SimpleTy) {
8295 default: return false;
8304 return Scale == 2 || Scale == 4 || Scale == 8;
8307 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
8311 // Note, we allow "void" uses (basically, uses that aren't loads or
8312 // stores), because arm allows folding a scale into many arithmetic
8313 // operations. This should be made more precise and revisited later.
8315 // Allow r << imm, but the imm has to be a multiple of two.
8316 if (Scale & 1) return false;
8317 return isPowerOf2_32(Scale);
8321 /// isLegalAddressingMode - Return true if the addressing mode represented
8322 /// by AM is legal for this target, for a load/store of the specified type.
8323 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
8325 EVT VT = getValueType(Ty, true);
8326 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
8329 // Can never fold addr of global into load/store.
8334 case 0: // no scale reg, must be "r+i" or "r", or "i".
8337 if (Subtarget->isThumb1Only())
8341 // ARM doesn't support any R+R*scale+imm addr modes.
8348 if (Subtarget->isThumb2())
8349 return isLegalT2ScaledAddressingMode(AM, VT);
8351 int Scale = AM.Scale;
8352 switch (VT.getSimpleVT().SimpleTy) {
8353 default: return false;
8357 if (Scale < 0) Scale = -Scale;
8361 return isPowerOf2_32(Scale & ~1);
8365 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
8370 // Note, we allow "void" uses (basically, uses that aren't loads or
8371 // stores), because arm allows folding a scale into many arithmetic
8372 // operations. This should be made more precise and revisited later.
8374 // Allow r << imm, but the imm has to be a multiple of two.
8375 if (Scale & 1) return false;
8376 return isPowerOf2_32(Scale);
8382 /// isLegalICmpImmediate - Return true if the specified immediate is legal
8383 /// icmp immediate, that is the target has icmp instructions which can compare
8384 /// a register against the immediate without having to materialize the
8385 /// immediate into a register.
8386 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
8387 if (!Subtarget->isThumb())
8388 return ARM_AM::getSOImmVal(Imm) != -1;
8389 if (Subtarget->isThumb2())
8390 return ARM_AM::getT2SOImmVal(Imm) != -1;
8391 return Imm >= 0 && Imm <= 255;
8394 /// isLegalAddImmediate - Return true if the specified immediate is legal
8395 /// add immediate, that is the target has add instructions which can add
8396 /// a register with the immediate without having to materialize the
8397 /// immediate into a register.
8398 bool ARMTargetLowering::isLegalAddImmediate(int64_t Imm) const {
8399 return ARM_AM::getSOImmVal(Imm) != -1;
8402 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
8403 bool isSEXTLoad, SDValue &Base,
8404 SDValue &Offset, bool &isInc,
8405 SelectionDAG &DAG) {
8406 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
8409 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
8411 Base = Ptr->getOperand(0);
8412 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
8413 int RHSC = (int)RHS->getZExtValue();
8414 if (RHSC < 0 && RHSC > -256) {
8415 assert(Ptr->getOpcode() == ISD::ADD);
8417 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
8421 isInc = (Ptr->getOpcode() == ISD::ADD);
8422 Offset = Ptr->getOperand(1);
8424 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
8426 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
8427 int RHSC = (int)RHS->getZExtValue();
8428 if (RHSC < 0 && RHSC > -0x1000) {
8429 assert(Ptr->getOpcode() == ISD::ADD);
8431 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
8432 Base = Ptr->getOperand(0);
8437 if (Ptr->getOpcode() == ISD::ADD) {
8439 ARM_AM::ShiftOpc ShOpcVal=
8440 ARM_AM::getShiftOpcForNode(Ptr->getOperand(0).getOpcode());
8441 if (ShOpcVal != ARM_AM::no_shift) {
8442 Base = Ptr->getOperand(1);
8443 Offset = Ptr->getOperand(0);
8445 Base = Ptr->getOperand(0);
8446 Offset = Ptr->getOperand(1);
8451 isInc = (Ptr->getOpcode() == ISD::ADD);
8452 Base = Ptr->getOperand(0);
8453 Offset = Ptr->getOperand(1);
8457 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
8461 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
8462 bool isSEXTLoad, SDValue &Base,
8463 SDValue &Offset, bool &isInc,
8464 SelectionDAG &DAG) {
8465 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
8468 Base = Ptr->getOperand(0);
8469 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
8470 int RHSC = (int)RHS->getZExtValue();
8471 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
8472 assert(Ptr->getOpcode() == ISD::ADD);
8474 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
8476 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
8477 isInc = Ptr->getOpcode() == ISD::ADD;
8478 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
8486 /// getPreIndexedAddressParts - returns true by value, base pointer and
8487 /// offset pointer and addressing mode by reference if the node's address
8488 /// can be legally represented as pre-indexed load / store address.
8490 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
8492 ISD::MemIndexedMode &AM,
8493 SelectionDAG &DAG) const {
8494 if (Subtarget->isThumb1Only())
8499 bool isSEXTLoad = false;
8500 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
8501 Ptr = LD->getBasePtr();
8502 VT = LD->getMemoryVT();
8503 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
8504 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
8505 Ptr = ST->getBasePtr();
8506 VT = ST->getMemoryVT();
8511 bool isLegal = false;
8512 if (Subtarget->isThumb2())
8513 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
8514 Offset, isInc, DAG);
8516 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
8517 Offset, isInc, DAG);
8521 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
8525 /// getPostIndexedAddressParts - returns true by value, base pointer and
8526 /// offset pointer and addressing mode by reference if this node can be
8527 /// combined with a load / store to form a post-indexed load / store.
8528 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
8531 ISD::MemIndexedMode &AM,
8532 SelectionDAG &DAG) const {
8533 if (Subtarget->isThumb1Only())
8538 bool isSEXTLoad = false;
8539 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
8540 VT = LD->getMemoryVT();
8541 Ptr = LD->getBasePtr();
8542 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
8543 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
8544 VT = ST->getMemoryVT();
8545 Ptr = ST->getBasePtr();
8550 bool isLegal = false;
8551 if (Subtarget->isThumb2())
8552 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
8555 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
8561 // Swap base ptr and offset to catch more post-index load / store when
8562 // it's legal. In Thumb2 mode, offset must be an immediate.
8563 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
8564 !Subtarget->isThumb2())
8565 std::swap(Base, Offset);
8567 // Post-indexed load / store update the base pointer.
8572 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
8576 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
8580 const SelectionDAG &DAG,
8581 unsigned Depth) const {
8582 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
8583 switch (Op.getOpcode()) {
8585 case ARMISD::CMOV: {
8586 // Bits are known zero/one if known on the LHS and RHS.
8587 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
8588 if (KnownZero == 0 && KnownOne == 0) return;
8590 APInt KnownZeroRHS, KnownOneRHS;
8591 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
8592 KnownZeroRHS, KnownOneRHS, Depth+1);
8593 KnownZero &= KnownZeroRHS;
8594 KnownOne &= KnownOneRHS;
8600 //===----------------------------------------------------------------------===//
8601 // ARM Inline Assembly Support
8602 //===----------------------------------------------------------------------===//
8604 bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const {
8605 // Looking for "rev" which is V6+.
8606 if (!Subtarget->hasV6Ops())
8609 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
8610 std::string AsmStr = IA->getAsmString();
8611 SmallVector<StringRef, 4> AsmPieces;
8612 SplitString(AsmStr, AsmPieces, ";\n");
8614 switch (AsmPieces.size()) {
8615 default: return false;
8617 AsmStr = AsmPieces[0];
8619 SplitString(AsmStr, AsmPieces, " \t,");
8622 if (AsmPieces.size() == 3 &&
8623 AsmPieces[0] == "rev" && AsmPieces[1] == "$0" && AsmPieces[2] == "$1" &&
8624 IA->getConstraintString().compare(0, 4, "=l,l") == 0) {
8625 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
8626 if (Ty && Ty->getBitWidth() == 32)
8627 return IntrinsicLowering::LowerToByteSwap(CI);
8635 /// getConstraintType - Given a constraint letter, return the type of
8636 /// constraint it is for this target.
8637 ARMTargetLowering::ConstraintType
8638 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
8639 if (Constraint.size() == 1) {
8640 switch (Constraint[0]) {
8642 case 'l': return C_RegisterClass;
8643 case 'w': return C_RegisterClass;
8644 case 'h': return C_RegisterClass;
8645 case 'x': return C_RegisterClass;
8646 case 't': return C_RegisterClass;
8647 case 'j': return C_Other; // Constant for movw.
8648 // An address with a single base register. Due to the way we
8649 // currently handle addresses it is the same as an 'r' memory constraint.
8650 case 'Q': return C_Memory;
8652 } else if (Constraint.size() == 2) {
8653 switch (Constraint[0]) {
8655 // All 'U+' constraints are addresses.
8656 case 'U': return C_Memory;
8659 return TargetLowering::getConstraintType(Constraint);
8662 /// Examine constraint type and operand type and determine a weight value.
8663 /// This object must already have been set up with the operand type
8664 /// and the current alternative constraint selected.
8665 TargetLowering::ConstraintWeight
8666 ARMTargetLowering::getSingleConstraintMatchWeight(
8667 AsmOperandInfo &info, const char *constraint) const {
8668 ConstraintWeight weight = CW_Invalid;
8669 Value *CallOperandVal = info.CallOperandVal;
8670 // If we don't have a value, we can't do a match,
8671 // but allow it at the lowest weight.
8672 if (CallOperandVal == NULL)
8674 Type *type = CallOperandVal->getType();
8675 // Look at the constraint type.
8676 switch (*constraint) {
8678 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
8681 if (type->isIntegerTy()) {
8682 if (Subtarget->isThumb())
8683 weight = CW_SpecificReg;
8685 weight = CW_Register;
8689 if (type->isFloatingPointTy())
8690 weight = CW_Register;
8696 typedef std::pair<unsigned, const TargetRegisterClass*> RCPair;
8698 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
8700 if (Constraint.size() == 1) {
8701 // GCC ARM Constraint Letters
8702 switch (Constraint[0]) {
8703 case 'l': // Low regs or general regs.
8704 if (Subtarget->isThumb())
8705 return RCPair(0U, ARM::tGPRRegisterClass);
8707 return RCPair(0U, ARM::GPRRegisterClass);
8708 case 'h': // High regs or no regs.
8709 if (Subtarget->isThumb())
8710 return RCPair(0U, ARM::hGPRRegisterClass);
8713 return RCPair(0U, ARM::GPRRegisterClass);
8716 return RCPair(0U, ARM::SPRRegisterClass);
8717 if (VT.getSizeInBits() == 64)
8718 return RCPair(0U, ARM::DPRRegisterClass);
8719 if (VT.getSizeInBits() == 128)
8720 return RCPair(0U, ARM::QPRRegisterClass);
8724 return RCPair(0U, ARM::SPR_8RegisterClass);
8725 if (VT.getSizeInBits() == 64)
8726 return RCPair(0U, ARM::DPR_8RegisterClass);
8727 if (VT.getSizeInBits() == 128)
8728 return RCPair(0U, ARM::QPR_8RegisterClass);
8732 return RCPair(0U, ARM::SPRRegisterClass);
8736 if (StringRef("{cc}").equals_lower(Constraint))
8737 return std::make_pair(unsigned(ARM::CPSR), ARM::CCRRegisterClass);
8739 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
8742 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
8743 /// vector. If it is invalid, don't add anything to Ops.
8744 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
8745 std::string &Constraint,
8746 std::vector<SDValue>&Ops,
8747 SelectionDAG &DAG) const {
8748 SDValue Result(0, 0);
8750 // Currently only support length 1 constraints.
8751 if (Constraint.length() != 1) return;
8753 char ConstraintLetter = Constraint[0];
8754 switch (ConstraintLetter) {
8757 case 'I': case 'J': case 'K': case 'L':
8758 case 'M': case 'N': case 'O':
8759 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
8763 int64_t CVal64 = C->getSExtValue();
8764 int CVal = (int) CVal64;
8765 // None of these constraints allow values larger than 32 bits. Check
8766 // that the value fits in an int.
8770 switch (ConstraintLetter) {
8772 // Constant suitable for movw, must be between 0 and
8774 if (Subtarget->hasV6T2Ops())
8775 if (CVal >= 0 && CVal <= 65535)
8779 if (Subtarget->isThumb1Only()) {
8780 // This must be a constant between 0 and 255, for ADD
8782 if (CVal >= 0 && CVal <= 255)
8784 } else if (Subtarget->isThumb2()) {
8785 // A constant that can be used as an immediate value in a
8786 // data-processing instruction.
8787 if (ARM_AM::getT2SOImmVal(CVal) != -1)
8790 // A constant that can be used as an immediate value in a
8791 // data-processing instruction.
8792 if (ARM_AM::getSOImmVal(CVal) != -1)
8798 if (Subtarget->isThumb()) { // FIXME thumb2
8799 // This must be a constant between -255 and -1, for negated ADD
8800 // immediates. This can be used in GCC with an "n" modifier that
8801 // prints the negated value, for use with SUB instructions. It is
8802 // not useful otherwise but is implemented for compatibility.
8803 if (CVal >= -255 && CVal <= -1)
8806 // This must be a constant between -4095 and 4095. It is not clear
8807 // what this constraint is intended for. Implemented for
8808 // compatibility with GCC.
8809 if (CVal >= -4095 && CVal <= 4095)
8815 if (Subtarget->isThumb1Only()) {
8816 // A 32-bit value where only one byte has a nonzero value. Exclude
8817 // zero to match GCC. This constraint is used by GCC internally for
8818 // constants that can be loaded with a move/shift combination.
8819 // It is not useful otherwise but is implemented for compatibility.
8820 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
8822 } else if (Subtarget->isThumb2()) {
8823 // A constant whose bitwise inverse can be used as an immediate
8824 // value in a data-processing instruction. This can be used in GCC
8825 // with a "B" modifier that prints the inverted value, for use with
8826 // BIC and MVN instructions. It is not useful otherwise but is
8827 // implemented for compatibility.
8828 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
8831 // A constant whose bitwise inverse can be used as an immediate
8832 // value in a data-processing instruction. This can be used in GCC
8833 // with a "B" modifier that prints the inverted value, for use with
8834 // BIC and MVN instructions. It is not useful otherwise but is
8835 // implemented for compatibility.
8836 if (ARM_AM::getSOImmVal(~CVal) != -1)
8842 if (Subtarget->isThumb1Only()) {
8843 // This must be a constant between -7 and 7,
8844 // for 3-operand ADD/SUB immediate instructions.
8845 if (CVal >= -7 && CVal < 7)
8847 } else if (Subtarget->isThumb2()) {
8848 // A constant whose negation can be used as an immediate value in a
8849 // data-processing instruction. This can be used in GCC with an "n"
8850 // modifier that prints the negated value, for use with SUB
8851 // instructions. It is not useful otherwise but is implemented for
8853 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
8856 // A constant whose negation can be used as an immediate value in a
8857 // data-processing instruction. This can be used in GCC with an "n"
8858 // modifier that prints the negated value, for use with SUB
8859 // instructions. It is not useful otherwise but is implemented for
8861 if (ARM_AM::getSOImmVal(-CVal) != -1)
8867 if (Subtarget->isThumb()) { // FIXME thumb2
8868 // This must be a multiple of 4 between 0 and 1020, for
8869 // ADD sp + immediate.
8870 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
8873 // A power of two or a constant between 0 and 32. This is used in
8874 // GCC for the shift amount on shifted register operands, but it is
8875 // useful in general for any shift amounts.
8876 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
8882 if (Subtarget->isThumb()) { // FIXME thumb2
8883 // This must be a constant between 0 and 31, for shift amounts.
8884 if (CVal >= 0 && CVal <= 31)
8890 if (Subtarget->isThumb()) { // FIXME thumb2
8891 // This must be a multiple of 4 between -508 and 508, for
8892 // ADD/SUB sp = sp + immediate.
8893 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
8898 Result = DAG.getTargetConstant(CVal, Op.getValueType());
8902 if (Result.getNode()) {
8903 Ops.push_back(Result);
8906 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
8910 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
8911 // The ARM target isn't yet aware of offsets.
8915 bool ARM::isBitFieldInvertedMask(unsigned v) {
8916 if (v == 0xffffffff)
8918 // there can be 1's on either or both "outsides", all the "inside"
8920 unsigned int lsb = 0, msb = 31;
8921 while (v & (1 << msb)) --msb;
8922 while (v & (1 << lsb)) ++lsb;
8923 for (unsigned int i = lsb; i <= msb; ++i) {
8930 /// isFPImmLegal - Returns true if the target can instruction select the
8931 /// specified FP immediate natively. If false, the legalizer will
8932 /// materialize the FP immediate as a load from a constant pool.
8933 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
8934 if (!Subtarget->hasVFP3())
8937 return ARM_AM::getFP32Imm(Imm) != -1;
8939 return ARM_AM::getFP64Imm(Imm) != -1;
8943 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
8944 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
8945 /// specified in the intrinsic calls.
8946 bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
8948 unsigned Intrinsic) const {
8949 switch (Intrinsic) {
8950 case Intrinsic::arm_neon_vld1:
8951 case Intrinsic::arm_neon_vld2:
8952 case Intrinsic::arm_neon_vld3:
8953 case Intrinsic::arm_neon_vld4:
8954 case Intrinsic::arm_neon_vld2lane:
8955 case Intrinsic::arm_neon_vld3lane:
8956 case Intrinsic::arm_neon_vld4lane: {
8957 Info.opc = ISD::INTRINSIC_W_CHAIN;
8958 // Conservatively set memVT to the entire set of vectors loaded.
8959 uint64_t NumElts = getTargetData()->getTypeAllocSize(I.getType()) / 8;
8960 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
8961 Info.ptrVal = I.getArgOperand(0);
8963 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
8964 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
8965 Info.vol = false; // volatile loads with NEON intrinsics not supported
8966 Info.readMem = true;
8967 Info.writeMem = false;
8970 case Intrinsic::arm_neon_vst1:
8971 case Intrinsic::arm_neon_vst2:
8972 case Intrinsic::arm_neon_vst3:
8973 case Intrinsic::arm_neon_vst4:
8974 case Intrinsic::arm_neon_vst2lane:
8975 case Intrinsic::arm_neon_vst3lane:
8976 case Intrinsic::arm_neon_vst4lane: {
8977 Info.opc = ISD::INTRINSIC_VOID;
8978 // Conservatively set memVT to the entire set of vectors stored.
8979 unsigned NumElts = 0;
8980 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
8981 Type *ArgTy = I.getArgOperand(ArgI)->getType();
8982 if (!ArgTy->isVectorTy())
8984 NumElts += getTargetData()->getTypeAllocSize(ArgTy) / 8;
8986 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
8987 Info.ptrVal = I.getArgOperand(0);
8989 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
8990 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
8991 Info.vol = false; // volatile stores with NEON intrinsics not supported
8992 Info.readMem = false;
8993 Info.writeMem = true;
8996 case Intrinsic::arm_strexd: {
8997 Info.opc = ISD::INTRINSIC_W_CHAIN;
8998 Info.memVT = MVT::i64;
8999 Info.ptrVal = I.getArgOperand(2);
9003 Info.readMem = false;
9004 Info.writeMem = true;
9007 case Intrinsic::arm_ldrexd: {
9008 Info.opc = ISD::INTRINSIC_W_CHAIN;
9009 Info.memVT = MVT::i64;
9010 Info.ptrVal = I.getArgOperand(0);
9014 Info.readMem = true;
9015 Info.writeMem = false;