1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "ARMAddressingModes.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMISelLowering.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMPerfectShuffle.h"
21 #include "ARMRegisterInfo.h"
22 #include "ARMSubtarget.h"
23 #include "ARMTargetMachine.h"
24 #include "ARMTargetObjectFile.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/Constants.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instruction.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/GlobalValue.h"
31 #include "llvm/CodeGen/CallingConvLower.h"
32 #include "llvm/CodeGen/MachineBasicBlock.h"
33 #include "llvm/CodeGen/MachineFrameInfo.h"
34 #include "llvm/CodeGen/MachineFunction.h"
35 #include "llvm/CodeGen/MachineInstrBuilder.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/PseudoSourceValue.h"
38 #include "llvm/CodeGen/SelectionDAG.h"
39 #include "llvm/Target/TargetOptions.h"
40 #include "llvm/ADT/VectorExtras.h"
41 #include "llvm/Support/ErrorHandling.h"
42 #include "llvm/Support/MathExtras.h"
46 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
47 CCValAssign::LocInfo &LocInfo,
48 ISD::ArgFlagsTy &ArgFlags,
50 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
51 CCValAssign::LocInfo &LocInfo,
52 ISD::ArgFlagsTy &ArgFlags,
54 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
55 CCValAssign::LocInfo &LocInfo,
56 ISD::ArgFlagsTy &ArgFlags,
58 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
59 CCValAssign::LocInfo &LocInfo,
60 ISD::ArgFlagsTy &ArgFlags,
63 void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
64 EVT PromotedBitwiseVT) {
65 if (VT != PromotedLdStVT) {
66 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
67 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
68 PromotedLdStVT.getSimpleVT());
70 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
71 AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
72 PromotedLdStVT.getSimpleVT());
75 EVT ElemTy = VT.getVectorElementType();
76 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
77 setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
78 if (ElemTy == MVT::i8 || ElemTy == MVT::i16)
79 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
80 if (ElemTy != MVT::i32) {
81 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
82 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand);
83 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand);
84 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand);
86 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
87 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
88 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Custom);
89 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Expand);
91 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
92 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
93 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
96 // Promote all bit-wise operations.
97 if (VT.isInteger() && VT != PromotedBitwiseVT) {
98 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
99 AddPromotedToType (ISD::AND, VT.getSimpleVT(),
100 PromotedBitwiseVT.getSimpleVT());
101 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
102 AddPromotedToType (ISD::OR, VT.getSimpleVT(),
103 PromotedBitwiseVT.getSimpleVT());
104 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
105 AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
106 PromotedBitwiseVT.getSimpleVT());
109 // Neon does not support vector divide/remainder operations.
110 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
111 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
112 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand);
113 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
114 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
115 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
118 void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
119 addRegisterClass(VT, ARM::DPRRegisterClass);
120 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
123 void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
124 addRegisterClass(VT, ARM::QPRRegisterClass);
125 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
128 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
129 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
130 return new TargetLoweringObjectFileMachO();
131 return new ARMElfTargetObjectFile();
134 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
135 : TargetLowering(TM, createTLOF(TM)), ARMPCLabelIndex(0) {
136 Subtarget = &TM.getSubtarget<ARMSubtarget>();
138 if (Subtarget->isTargetDarwin()) {
139 // Uses VFP for Thumb libfuncs if available.
140 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
141 // Single-precision floating-point arithmetic.
142 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
143 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
144 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
145 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
147 // Double-precision floating-point arithmetic.
148 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
149 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
150 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
151 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
153 // Single-precision comparisons.
154 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
155 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
156 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
157 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
158 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
159 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
160 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
161 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
163 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
164 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
165 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
166 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
167 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
168 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
169 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
170 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
172 // Double-precision comparisons.
173 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
174 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
175 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
176 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
177 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
178 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
179 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
180 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
182 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
183 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
184 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
185 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
186 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
187 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
188 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
189 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
191 // Floating-point to integer conversions.
192 // i64 conversions are done via library routines even when generating VFP
193 // instructions, so use the same ones.
194 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
195 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
196 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
197 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
199 // Conversions between floating types.
200 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
201 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
203 // Integer to floating-point conversions.
204 // i64 conversions are done via library routines even when generating VFP
205 // instructions, so use the same ones.
206 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
207 // e.g., __floatunsidf vs. __floatunssidfvfp.
208 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
209 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
210 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
211 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
215 // These libcalls are not available in 32-bit.
216 setLibcallName(RTLIB::SHL_I128, 0);
217 setLibcallName(RTLIB::SRL_I128, 0);
218 setLibcallName(RTLIB::SRA_I128, 0);
220 // Libcalls should use the AAPCS base standard ABI, even if hard float
221 // is in effect, as per the ARM RTABI specification, section 4.1.2.
222 if (Subtarget->isAAPCS_ABI()) {
223 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
224 setLibcallCallingConv(static_cast<RTLIB::Libcall>(i),
225 CallingConv::ARM_AAPCS);
229 if (Subtarget->isThumb1Only())
230 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
232 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
233 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
234 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
235 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
237 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
240 if (Subtarget->hasNEON()) {
241 addDRTypeForNEON(MVT::v2f32);
242 addDRTypeForNEON(MVT::v8i8);
243 addDRTypeForNEON(MVT::v4i16);
244 addDRTypeForNEON(MVT::v2i32);
245 addDRTypeForNEON(MVT::v1i64);
247 addQRTypeForNEON(MVT::v4f32);
248 addQRTypeForNEON(MVT::v2f64);
249 addQRTypeForNEON(MVT::v16i8);
250 addQRTypeForNEON(MVT::v8i16);
251 addQRTypeForNEON(MVT::v4i32);
252 addQRTypeForNEON(MVT::v2i64);
254 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
255 // neither Neon nor VFP support any arithmetic operations on it.
256 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
257 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
258 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
259 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
260 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
261 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
262 setOperationAction(ISD::VSETCC, MVT::v2f64, Expand);
263 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
264 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
265 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
266 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
267 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
268 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
269 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
270 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
271 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
272 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
273 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
274 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
275 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
276 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
277 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
278 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
279 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
281 // Neon does not support some operations on v1i64 and v2i64 types.
282 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
283 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
284 setOperationAction(ISD::VSETCC, MVT::v1i64, Expand);
285 setOperationAction(ISD::VSETCC, MVT::v2i64, Expand);
287 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
288 setTargetDAGCombine(ISD::SHL);
289 setTargetDAGCombine(ISD::SRL);
290 setTargetDAGCombine(ISD::SRA);
291 setTargetDAGCombine(ISD::SIGN_EXTEND);
292 setTargetDAGCombine(ISD::ZERO_EXTEND);
293 setTargetDAGCombine(ISD::ANY_EXTEND);
296 computeRegisterProperties();
298 // ARM does not have f32 extending load.
299 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
301 // ARM does not have i1 sign extending load.
302 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
304 // ARM supports all 4 flavors of integer indexed load / store.
305 if (!Subtarget->isThumb1Only()) {
306 for (unsigned im = (unsigned)ISD::PRE_INC;
307 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
308 setIndexedLoadAction(im, MVT::i1, Legal);
309 setIndexedLoadAction(im, MVT::i8, Legal);
310 setIndexedLoadAction(im, MVT::i16, Legal);
311 setIndexedLoadAction(im, MVT::i32, Legal);
312 setIndexedStoreAction(im, MVT::i1, Legal);
313 setIndexedStoreAction(im, MVT::i8, Legal);
314 setIndexedStoreAction(im, MVT::i16, Legal);
315 setIndexedStoreAction(im, MVT::i32, Legal);
319 // i64 operation support.
320 if (Subtarget->isThumb1Only()) {
321 setOperationAction(ISD::MUL, MVT::i64, Expand);
322 setOperationAction(ISD::MULHU, MVT::i32, Expand);
323 setOperationAction(ISD::MULHS, MVT::i32, Expand);
324 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
325 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
327 setOperationAction(ISD::MUL, MVT::i64, Expand);
328 setOperationAction(ISD::MULHU, MVT::i32, Expand);
329 if (!Subtarget->hasV6Ops())
330 setOperationAction(ISD::MULHS, MVT::i32, Expand);
332 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
333 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
334 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
335 setOperationAction(ISD::SRL, MVT::i64, Custom);
336 setOperationAction(ISD::SRA, MVT::i64, Custom);
338 // ARM does not have ROTL.
339 setOperationAction(ISD::ROTL, MVT::i32, Expand);
340 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
341 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
342 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
343 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
345 // Only ARMv6 has BSWAP.
346 if (!Subtarget->hasV6Ops())
347 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
349 // These are expanded into libcalls.
350 setOperationAction(ISD::SDIV, MVT::i32, Expand);
351 setOperationAction(ISD::UDIV, MVT::i32, Expand);
352 setOperationAction(ISD::SREM, MVT::i32, Expand);
353 setOperationAction(ISD::UREM, MVT::i32, Expand);
354 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
355 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
357 // Support label based line numbers.
358 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
359 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
361 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
362 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
363 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
364 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
366 // Use the default implementation.
367 setOperationAction(ISD::VASTART, MVT::Other, Custom);
368 setOperationAction(ISD::VAARG, MVT::Other, Expand);
369 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
370 setOperationAction(ISD::VAEND, MVT::Other, Expand);
371 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
372 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
373 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
374 // FIXME: Shouldn't need this, since no register is used, but the legalizer
375 // doesn't yet know how to not do that for SjLj.
376 setExceptionSelectorRegister(ARM::R0);
377 if (Subtarget->isThumb())
378 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
380 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
381 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
383 if (!Subtarget->hasV6Ops() && !Subtarget->isThumb2()) {
384 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
385 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
387 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
389 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only())
390 // Turn f64->i64 into FMRRD, i64 -> f64 to FMDRR iff target supports vfp2.
391 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
393 // We want to custom lower some of our intrinsics.
394 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
396 setOperationAction(ISD::SETCC, MVT::i32, Expand);
397 setOperationAction(ISD::SETCC, MVT::f32, Expand);
398 setOperationAction(ISD::SETCC, MVT::f64, Expand);
399 setOperationAction(ISD::SELECT, MVT::i32, Expand);
400 setOperationAction(ISD::SELECT, MVT::f32, Expand);
401 setOperationAction(ISD::SELECT, MVT::f64, Expand);
402 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
403 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
404 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
406 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
407 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
408 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
409 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
410 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
412 // We don't support sin/cos/fmod/copysign/pow
413 setOperationAction(ISD::FSIN, MVT::f64, Expand);
414 setOperationAction(ISD::FSIN, MVT::f32, Expand);
415 setOperationAction(ISD::FCOS, MVT::f32, Expand);
416 setOperationAction(ISD::FCOS, MVT::f64, Expand);
417 setOperationAction(ISD::FREM, MVT::f64, Expand);
418 setOperationAction(ISD::FREM, MVT::f32, Expand);
419 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
420 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
421 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
423 setOperationAction(ISD::FPOW, MVT::f64, Expand);
424 setOperationAction(ISD::FPOW, MVT::f32, Expand);
426 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
427 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
428 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
429 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
430 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
431 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
434 // We have target-specific dag combine patterns for the following nodes:
435 // ARMISD::FMRRD - No need to call setTargetDAGCombine
436 setTargetDAGCombine(ISD::ADD);
437 setTargetDAGCombine(ISD::SUB);
439 setStackPointerRegisterToSaveRestore(ARM::SP);
440 setSchedulingPreference(SchedulingForRegPressure);
442 // FIXME: If-converter should use instruction latency to determine
443 // profitability rather than relying on fixed limits.
444 if (Subtarget->getCPUString() == "generic") {
445 // Generic (and overly aggressive) if-conversion limits.
446 setIfCvtBlockSizeLimit(10);
447 setIfCvtDupBlockSizeLimit(2);
448 } else if (Subtarget->hasV6Ops()) {
449 setIfCvtBlockSizeLimit(2);
450 setIfCvtDupBlockSizeLimit(1);
452 setIfCvtBlockSizeLimit(3);
453 setIfCvtDupBlockSizeLimit(2);
456 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
457 // Do not enable CodePlacementOpt for now: it currently runs after the
458 // ARMConstantIslandPass and messes up branch relaxation and placement
459 // of constant islands.
460 // benefitFromCodePlacementOpt = true;
463 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
466 case ARMISD::Wrapper: return "ARMISD::Wrapper";
467 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
468 case ARMISD::CALL: return "ARMISD::CALL";
469 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
470 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
471 case ARMISD::tCALL: return "ARMISD::tCALL";
472 case ARMISD::BRCOND: return "ARMISD::BRCOND";
473 case ARMISD::BR_JT: return "ARMISD::BR_JT";
474 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
475 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
476 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
477 case ARMISD::CMP: return "ARMISD::CMP";
478 case ARMISD::CMPZ: return "ARMISD::CMPZ";
479 case ARMISD::CMPFP: return "ARMISD::CMPFP";
480 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
481 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
482 case ARMISD::CMOV: return "ARMISD::CMOV";
483 case ARMISD::CNEG: return "ARMISD::CNEG";
485 case ARMISD::FTOSI: return "ARMISD::FTOSI";
486 case ARMISD::FTOUI: return "ARMISD::FTOUI";
487 case ARMISD::SITOF: return "ARMISD::SITOF";
488 case ARMISD::UITOF: return "ARMISD::UITOF";
490 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
491 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
492 case ARMISD::RRX: return "ARMISD::RRX";
494 case ARMISD::FMRRD: return "ARMISD::FMRRD";
495 case ARMISD::FMDRR: return "ARMISD::FMDRR";
497 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
499 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
501 case ARMISD::VCEQ: return "ARMISD::VCEQ";
502 case ARMISD::VCGE: return "ARMISD::VCGE";
503 case ARMISD::VCGEU: return "ARMISD::VCGEU";
504 case ARMISD::VCGT: return "ARMISD::VCGT";
505 case ARMISD::VCGTU: return "ARMISD::VCGTU";
506 case ARMISD::VTST: return "ARMISD::VTST";
508 case ARMISD::VSHL: return "ARMISD::VSHL";
509 case ARMISD::VSHRs: return "ARMISD::VSHRs";
510 case ARMISD::VSHRu: return "ARMISD::VSHRu";
511 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
512 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
513 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
514 case ARMISD::VSHRN: return "ARMISD::VSHRN";
515 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
516 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
517 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
518 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
519 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
520 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
521 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
522 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
523 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
524 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
525 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
526 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
527 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
528 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
529 case ARMISD::VDUP: return "ARMISD::VDUP";
530 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
531 case ARMISD::VEXT: return "ARMISD::VEXT";
532 case ARMISD::VREV64: return "ARMISD::VREV64";
533 case ARMISD::VREV32: return "ARMISD::VREV32";
534 case ARMISD::VREV16: return "ARMISD::VREV16";
535 case ARMISD::VZIP: return "ARMISD::VZIP";
536 case ARMISD::VUZP: return "ARMISD::VUZP";
537 case ARMISD::VTRN: return "ARMISD::VTRN";
541 /// getFunctionAlignment - Return the Log2 alignment of this function.
542 unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
543 return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 0 : 1;
546 //===----------------------------------------------------------------------===//
548 //===----------------------------------------------------------------------===//
550 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
551 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
553 default: llvm_unreachable("Unknown condition code!");
554 case ISD::SETNE: return ARMCC::NE;
555 case ISD::SETEQ: return ARMCC::EQ;
556 case ISD::SETGT: return ARMCC::GT;
557 case ISD::SETGE: return ARMCC::GE;
558 case ISD::SETLT: return ARMCC::LT;
559 case ISD::SETLE: return ARMCC::LE;
560 case ISD::SETUGT: return ARMCC::HI;
561 case ISD::SETUGE: return ARMCC::HS;
562 case ISD::SETULT: return ARMCC::LO;
563 case ISD::SETULE: return ARMCC::LS;
567 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
568 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
569 ARMCC::CondCodes &CondCode2) {
570 CondCode2 = ARMCC::AL;
572 default: llvm_unreachable("Unknown FP condition!");
574 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
576 case ISD::SETOGT: CondCode = ARMCC::GT; break;
578 case ISD::SETOGE: CondCode = ARMCC::GE; break;
579 case ISD::SETOLT: CondCode = ARMCC::MI; break;
580 case ISD::SETOLE: CondCode = ARMCC::LS; break;
581 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
582 case ISD::SETO: CondCode = ARMCC::VC; break;
583 case ISD::SETUO: CondCode = ARMCC::VS; break;
584 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
585 case ISD::SETUGT: CondCode = ARMCC::HI; break;
586 case ISD::SETUGE: CondCode = ARMCC::PL; break;
588 case ISD::SETULT: CondCode = ARMCC::LT; break;
590 case ISD::SETULE: CondCode = ARMCC::LE; break;
592 case ISD::SETUNE: CondCode = ARMCC::NE; break;
596 //===----------------------------------------------------------------------===//
597 // Calling Convention Implementation
598 //===----------------------------------------------------------------------===//
600 #include "ARMGenCallingConv.inc"
602 // APCS f64 is in register pairs, possibly split to stack
603 static bool f64AssignAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
604 CCValAssign::LocInfo &LocInfo,
605 CCState &State, bool CanFail) {
606 static const unsigned RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
608 // Try to get the first register.
609 if (unsigned Reg = State.AllocateReg(RegList, 4))
610 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
612 // For the 2nd half of a v2f64, do not fail.
616 // Put the whole thing on the stack.
617 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
618 State.AllocateStack(8, 4),
623 // Try to get the second register.
624 if (unsigned Reg = State.AllocateReg(RegList, 4))
625 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
627 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
628 State.AllocateStack(4, 4),
633 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
634 CCValAssign::LocInfo &LocInfo,
635 ISD::ArgFlagsTy &ArgFlags,
637 if (!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
639 if (LocVT == MVT::v2f64 &&
640 !f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
642 return true; // we handled it
645 // AAPCS f64 is in aligned register pairs
646 static bool f64AssignAAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
647 CCValAssign::LocInfo &LocInfo,
648 CCState &State, bool CanFail) {
649 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
650 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
652 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
654 // For the 2nd half of a v2f64, do not just fail.
658 // Put the whole thing on the stack.
659 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
660 State.AllocateStack(8, 8),
666 for (i = 0; i < 2; ++i)
667 if (HiRegList[i] == Reg)
670 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
671 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
676 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
677 CCValAssign::LocInfo &LocInfo,
678 ISD::ArgFlagsTy &ArgFlags,
680 if (!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
682 if (LocVT == MVT::v2f64 &&
683 !f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
685 return true; // we handled it
688 static bool f64RetAssign(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
689 CCValAssign::LocInfo &LocInfo, CCState &State) {
690 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
691 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
693 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
695 return false; // we didn't handle it
698 for (i = 0; i < 2; ++i)
699 if (HiRegList[i] == Reg)
702 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
703 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
708 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
709 CCValAssign::LocInfo &LocInfo,
710 ISD::ArgFlagsTy &ArgFlags,
712 if (!f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
714 if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
716 return true; // we handled it
719 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
720 CCValAssign::LocInfo &LocInfo,
721 ISD::ArgFlagsTy &ArgFlags,
723 return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags,
727 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
728 /// given CallingConvention value.
729 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
731 bool isVarArg) const {
734 llvm_unreachable("Unsupported calling convention");
736 case CallingConv::Fast:
737 // Use target triple & subtarget features to do actual dispatch.
738 if (Subtarget->isAAPCS_ABI()) {
739 if (Subtarget->hasVFP2() &&
740 FloatABIType == FloatABI::Hard && !isVarArg)
741 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
743 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
745 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
746 case CallingConv::ARM_AAPCS_VFP:
747 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
748 case CallingConv::ARM_AAPCS:
749 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
750 case CallingConv::ARM_APCS:
751 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
755 /// LowerCallResult - Lower the result values of a call into the
756 /// appropriate copies out of appropriate physical registers.
758 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
759 CallingConv::ID CallConv, bool isVarArg,
760 const SmallVectorImpl<ISD::InputArg> &Ins,
761 DebugLoc dl, SelectionDAG &DAG,
762 SmallVectorImpl<SDValue> &InVals) {
764 // Assign locations to each value returned by this call.
765 SmallVector<CCValAssign, 16> RVLocs;
766 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
767 RVLocs, *DAG.getContext());
768 CCInfo.AnalyzeCallResult(Ins,
769 CCAssignFnForNode(CallConv, /* Return*/ true,
772 // Copy all of the result registers out of their specified physreg.
773 for (unsigned i = 0; i != RVLocs.size(); ++i) {
774 CCValAssign VA = RVLocs[i];
777 if (VA.needsCustom()) {
778 // Handle f64 or half of a v2f64.
779 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
781 Chain = Lo.getValue(1);
782 InFlag = Lo.getValue(2);
783 VA = RVLocs[++i]; // skip ahead to next loc
784 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
786 Chain = Hi.getValue(1);
787 InFlag = Hi.getValue(2);
788 Val = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
790 if (VA.getLocVT() == MVT::v2f64) {
791 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
792 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
793 DAG.getConstant(0, MVT::i32));
795 VA = RVLocs[++i]; // skip ahead to next loc
796 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
797 Chain = Lo.getValue(1);
798 InFlag = Lo.getValue(2);
799 VA = RVLocs[++i]; // skip ahead to next loc
800 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
801 Chain = Hi.getValue(1);
802 InFlag = Hi.getValue(2);
803 Val = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
804 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
805 DAG.getConstant(1, MVT::i32));
808 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
810 Chain = Val.getValue(1);
811 InFlag = Val.getValue(2);
814 switch (VA.getLocInfo()) {
815 default: llvm_unreachable("Unknown loc info!");
816 case CCValAssign::Full: break;
817 case CCValAssign::BCvt:
818 Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val);
822 InVals.push_back(Val);
828 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
829 /// by "Src" to address "Dst" of size "Size". Alignment information is
830 /// specified by the specific parameter attribute. The copy will be passed as
831 /// a byval function parameter.
832 /// Sometimes what we are copying is the end of a larger object, the part that
833 /// does not fit in registers.
835 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
836 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
838 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
839 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
840 /*AlwaysInline=*/false, NULL, 0, NULL, 0);
843 /// LowerMemOpCallTo - Store the argument to the stack.
845 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
846 SDValue StackPtr, SDValue Arg,
847 DebugLoc dl, SelectionDAG &DAG,
848 const CCValAssign &VA,
849 ISD::ArgFlagsTy Flags) {
850 unsigned LocMemOffset = VA.getLocMemOffset();
851 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
852 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
853 if (Flags.isByVal()) {
854 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
856 return DAG.getStore(Chain, dl, Arg, PtrOff,
857 PseudoSourceValue::getStack(), LocMemOffset);
860 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
861 SDValue Chain, SDValue &Arg,
862 RegsToPassVector &RegsToPass,
863 CCValAssign &VA, CCValAssign &NextVA,
865 SmallVector<SDValue, 8> &MemOpChains,
866 ISD::ArgFlagsTy Flags) {
868 SDValue fmrrd = DAG.getNode(ARMISD::FMRRD, dl,
869 DAG.getVTList(MVT::i32, MVT::i32), Arg);
870 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
872 if (NextVA.isRegLoc())
873 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
875 assert(NextVA.isMemLoc());
876 if (StackPtr.getNode() == 0)
877 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
879 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
885 /// LowerCall - Lowering a call into a callseq_start <-
886 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
889 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
890 CallingConv::ID CallConv, bool isVarArg,
892 const SmallVectorImpl<ISD::OutputArg> &Outs,
893 const SmallVectorImpl<ISD::InputArg> &Ins,
894 DebugLoc dl, SelectionDAG &DAG,
895 SmallVectorImpl<SDValue> &InVals) {
897 // Analyze operands of the call, assigning locations to each operand.
898 SmallVector<CCValAssign, 16> ArgLocs;
899 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
901 CCInfo.AnalyzeCallOperands(Outs,
902 CCAssignFnForNode(CallConv, /* Return*/ false,
905 // Get a count of how many bytes are to be pushed on the stack.
906 unsigned NumBytes = CCInfo.getNextStackOffset();
908 // Adjust the stack pointer for the new arguments...
909 // These operations are automatically eliminated by the prolog/epilog pass
910 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
912 SDValue StackPtr = DAG.getRegister(ARM::SP, MVT::i32);
914 RegsToPassVector RegsToPass;
915 SmallVector<SDValue, 8> MemOpChains;
917 // Walk the register/memloc assignments, inserting copies/loads. In the case
918 // of tail call optimization, arguments are handled later.
919 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
922 CCValAssign &VA = ArgLocs[i];
923 SDValue Arg = Outs[realArgIdx].Val;
924 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
926 // Promote the value if needed.
927 switch (VA.getLocInfo()) {
928 default: llvm_unreachable("Unknown loc info!");
929 case CCValAssign::Full: break;
930 case CCValAssign::SExt:
931 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
933 case CCValAssign::ZExt:
934 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
936 case CCValAssign::AExt:
937 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
939 case CCValAssign::BCvt:
940 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
944 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
945 if (VA.needsCustom()) {
946 if (VA.getLocVT() == MVT::v2f64) {
947 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
948 DAG.getConstant(0, MVT::i32));
949 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
950 DAG.getConstant(1, MVT::i32));
952 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
953 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
955 VA = ArgLocs[++i]; // skip ahead to next loc
957 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
958 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
960 assert(VA.isMemLoc());
961 if (StackPtr.getNode() == 0)
962 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
964 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
965 dl, DAG, VA, Flags));
968 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
969 StackPtr, MemOpChains, Flags);
971 } else if (VA.isRegLoc()) {
972 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
974 assert(VA.isMemLoc());
975 if (StackPtr.getNode() == 0)
976 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
978 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
979 dl, DAG, VA, Flags));
983 if (!MemOpChains.empty())
984 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
985 &MemOpChains[0], MemOpChains.size());
987 // Build a sequence of copy-to-reg nodes chained together with token chain
988 // and flag operands which copy the outgoing args into the appropriate regs.
990 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
991 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
992 RegsToPass[i].second, InFlag);
993 InFlag = Chain.getValue(1);
996 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
997 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
998 // node so that legalize doesn't hack it.
999 bool isDirect = false;
1000 bool isARMFunc = false;
1001 bool isLocalARMFunc = false;
1002 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1003 GlobalValue *GV = G->getGlobal();
1005 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1006 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
1007 getTargetMachine().getRelocationModel() != Reloc::Static;
1008 isARMFunc = !Subtarget->isThumb() || isStub;
1009 // ARM call to a local ARM function is predicable.
1010 isLocalARMFunc = !Subtarget->isThumb() && !isExt;
1011 // tBX takes a register source operand.
1012 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1013 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1016 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1017 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1018 Callee = DAG.getLoad(getPointerTy(), dl,
1019 DAG.getEntryNode(), CPAddr, NULL, 0);
1020 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1021 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1022 getPointerTy(), Callee, PICLabel);
1024 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy());
1025 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1027 bool isStub = Subtarget->isTargetDarwin() &&
1028 getTargetMachine().getRelocationModel() != Reloc::Static;
1029 isARMFunc = !Subtarget->isThumb() || isStub;
1030 // tBX takes a register source operand.
1031 const char *Sym = S->getSymbol();
1032 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1033 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1034 Sym, ARMPCLabelIndex, 4);
1035 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1036 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1037 Callee = DAG.getLoad(getPointerTy(), dl,
1038 DAG.getEntryNode(), CPAddr, NULL, 0);
1039 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1040 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1041 getPointerTy(), Callee, PICLabel);
1043 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
1046 // FIXME: handle tail calls differently.
1048 if (Subtarget->isThumb()) {
1049 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1050 CallOpc = ARMISD::CALL_NOLINK;
1052 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1054 CallOpc = (isDirect || Subtarget->hasV5TOps())
1055 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
1056 : ARMISD::CALL_NOLINK;
1058 if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb1Only()) {
1059 // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK
1060 Chain = DAG.getCopyToReg(Chain, dl, ARM::LR, DAG.getUNDEF(MVT::i32),InFlag);
1061 InFlag = Chain.getValue(1);
1064 std::vector<SDValue> Ops;
1065 Ops.push_back(Chain);
1066 Ops.push_back(Callee);
1068 // Add argument registers to the end of the list so that they are known live
1070 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1071 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1072 RegsToPass[i].second.getValueType()));
1074 if (InFlag.getNode())
1075 Ops.push_back(InFlag);
1076 // Returns a chain and a flag for retval copy to use.
1077 Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(MVT::Other, MVT::Flag),
1078 &Ops[0], Ops.size());
1079 InFlag = Chain.getValue(1);
1081 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1082 DAG.getIntPtrConstant(0, true), InFlag);
1084 InFlag = Chain.getValue(1);
1086 // Handle result values, copying them out of physregs into vregs that we
1088 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1093 ARMTargetLowering::LowerReturn(SDValue Chain,
1094 CallingConv::ID CallConv, bool isVarArg,
1095 const SmallVectorImpl<ISD::OutputArg> &Outs,
1096 DebugLoc dl, SelectionDAG &DAG) {
1098 // CCValAssign - represent the assignment of the return value to a location.
1099 SmallVector<CCValAssign, 16> RVLocs;
1101 // CCState - Info about the registers and stack slots.
1102 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
1105 // Analyze outgoing return values.
1106 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1109 // If this is the first return lowered for this function, add
1110 // the regs to the liveout set for the function.
1111 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1112 for (unsigned i = 0; i != RVLocs.size(); ++i)
1113 if (RVLocs[i].isRegLoc())
1114 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1119 // Copy the result values into the output registers.
1120 for (unsigned i = 0, realRVLocIdx = 0;
1122 ++i, ++realRVLocIdx) {
1123 CCValAssign &VA = RVLocs[i];
1124 assert(VA.isRegLoc() && "Can only return in registers!");
1126 SDValue Arg = Outs[realRVLocIdx].Val;
1128 switch (VA.getLocInfo()) {
1129 default: llvm_unreachable("Unknown loc info!");
1130 case CCValAssign::Full: break;
1131 case CCValAssign::BCvt:
1132 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1136 if (VA.needsCustom()) {
1137 if (VA.getLocVT() == MVT::v2f64) {
1138 // Extract the first half and return it in two registers.
1139 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1140 DAG.getConstant(0, MVT::i32));
1141 SDValue HalfGPRs = DAG.getNode(ARMISD::FMRRD, dl,
1142 DAG.getVTList(MVT::i32, MVT::i32), Half);
1144 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1145 Flag = Chain.getValue(1);
1146 VA = RVLocs[++i]; // skip ahead to next loc
1147 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1148 HalfGPRs.getValue(1), Flag);
1149 Flag = Chain.getValue(1);
1150 VA = RVLocs[++i]; // skip ahead to next loc
1152 // Extract the 2nd half and fall through to handle it as an f64 value.
1153 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1154 DAG.getConstant(1, MVT::i32));
1156 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1158 SDValue fmrrd = DAG.getNode(ARMISD::FMRRD, dl,
1159 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1160 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1161 Flag = Chain.getValue(1);
1162 VA = RVLocs[++i]; // skip ahead to next loc
1163 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1166 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1168 // Guarantee that all emitted copies are
1169 // stuck together, avoiding something bad.
1170 Flag = Chain.getValue(1);
1175 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1177 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1182 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1183 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1184 // one of the above mentioned nodes. It has to be wrapped because otherwise
1185 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1186 // be used to form addressing mode. These wrapped nodes will be selected
1188 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1189 EVT PtrVT = Op.getValueType();
1190 // FIXME there is no actual debug info here
1191 DebugLoc dl = Op.getDebugLoc();
1192 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1194 if (CP->isMachineConstantPoolEntry())
1195 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1196 CP->getAlignment());
1198 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1199 CP->getAlignment());
1200 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1203 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
1205 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1206 SelectionDAG &DAG) {
1207 DebugLoc dl = GA->getDebugLoc();
1208 EVT PtrVT = getPointerTy();
1209 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1210 ARMConstantPoolValue *CPV =
1211 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1212 ARMCP::CPValue, PCAdj, "tlsgd", true);
1213 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1214 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
1215 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument, NULL, 0);
1216 SDValue Chain = Argument.getValue(1);
1218 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1219 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
1221 // call __tls_get_addr.
1224 Entry.Node = Argument;
1225 Entry.Ty = (const Type *) Type::getInt32Ty(*DAG.getContext());
1226 Args.push_back(Entry);
1227 // FIXME: is there useful debug info available here?
1228 std::pair<SDValue, SDValue> CallResult =
1229 LowerCallTo(Chain, (const Type *) Type::getInt32Ty(*DAG.getContext()),
1230 false, false, false, false,
1231 0, CallingConv::C, false, /*isReturnValueUsed=*/true,
1232 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
1233 return CallResult.first;
1236 // Lower ISD::GlobalTLSAddress using the "initial exec" or
1237 // "local exec" model.
1239 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
1240 SelectionDAG &DAG) {
1241 GlobalValue *GV = GA->getGlobal();
1242 DebugLoc dl = GA->getDebugLoc();
1244 SDValue Chain = DAG.getEntryNode();
1245 EVT PtrVT = getPointerTy();
1246 // Get the Thread Pointer
1247 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1249 if (GV->isDeclaration()) {
1250 // initial exec model
1251 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1252 ARMConstantPoolValue *CPV =
1253 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1254 ARMCP::CPValue, PCAdj, "gottpoff", true);
1255 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1256 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1257 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
1258 Chain = Offset.getValue(1);
1260 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1261 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
1263 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
1266 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, "tpoff");
1267 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1268 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1269 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
1272 // The address of the thread local variable is the add of the thread
1273 // pointer with the offset of the variable.
1274 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
1278 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
1279 // TODO: implement the "local dynamic" model
1280 assert(Subtarget->isTargetELF() &&
1281 "TLS not implemented for non-ELF targets");
1282 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1283 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
1284 // otherwise use the "Local Exec" TLS Model
1285 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
1286 return LowerToTLSGeneralDynamicModel(GA, DAG);
1288 return LowerToTLSExecModels(GA, DAG);
1291 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
1292 SelectionDAG &DAG) {
1293 EVT PtrVT = getPointerTy();
1294 DebugLoc dl = Op.getDebugLoc();
1295 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1296 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1297 if (RelocM == Reloc::PIC_) {
1298 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
1299 ARMConstantPoolValue *CPV =
1300 new ARMConstantPoolValue(GV, UseGOTOFF ? "GOTOFF" : "GOT");
1301 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1302 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1303 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1305 PseudoSourceValue::getConstantPool(), 0);
1306 SDValue Chain = Result.getValue(1);
1307 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1308 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
1310 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
1311 PseudoSourceValue::getGOT(), 0);
1314 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1315 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1316 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1317 PseudoSourceValue::getConstantPool(), 0);
1321 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
1322 SelectionDAG &DAG) {
1323 EVT PtrVT = getPointerTy();
1324 DebugLoc dl = Op.getDebugLoc();
1325 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1326 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1328 if (RelocM == Reloc::Static)
1329 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1331 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8);
1332 ARMConstantPoolValue *CPV =
1333 new ARMConstantPoolValue(GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj);
1334 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1336 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1338 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
1339 SDValue Chain = Result.getValue(1);
1341 if (RelocM == Reloc::PIC_) {
1342 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1343 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1346 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
1347 Result = DAG.getLoad(PtrVT, dl, Chain, Result, NULL, 0);
1352 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
1354 assert(Subtarget->isTargetELF() &&
1355 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
1356 EVT PtrVT = getPointerTy();
1357 DebugLoc dl = Op.getDebugLoc();
1358 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1359 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1360 "_GLOBAL_OFFSET_TABLE_",
1361 ARMPCLabelIndex, PCAdj);
1362 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1363 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1364 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1365 PseudoSourceValue::getConstantPool(), 0);
1366 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1367 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1371 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
1372 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1373 DebugLoc dl = Op.getDebugLoc();
1375 default: return SDValue(); // Don't custom lower most intrinsics.
1376 case Intrinsic::arm_thread_pointer: {
1377 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1378 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1380 case Intrinsic::eh_sjlj_lsda: {
1381 MachineFunction &MF = DAG.getMachineFunction();
1382 EVT PtrVT = getPointerTy();
1383 DebugLoc dl = Op.getDebugLoc();
1384 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1386 unsigned PCAdj = (RelocM != Reloc::PIC_)
1387 ? 0 : (Subtarget->isThumb() ? 4 : 8);
1388 ARMConstantPoolValue *CPV =
1389 new ARMConstantPoolValue(MF.getFunction(), ARMPCLabelIndex,
1390 ARMCP::CPLSDA, PCAdj);
1391 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1392 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1394 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
1395 SDValue Chain = Result.getValue(1);
1397 if (RelocM == Reloc::PIC_) {
1398 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1399 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1403 case Intrinsic::eh_sjlj_setjmp:
1404 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(1));
1408 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
1409 unsigned VarArgsFrameIndex) {
1410 // vastart just stores the address of the VarArgsFrameIndex slot into the
1411 // memory location argument.
1412 DebugLoc dl = Op.getDebugLoc();
1413 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1414 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1415 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1416 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
1420 ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) {
1421 SDNode *Node = Op.getNode();
1422 DebugLoc dl = Node->getDebugLoc();
1423 EVT VT = Node->getValueType(0);
1424 SDValue Chain = Op.getOperand(0);
1425 SDValue Size = Op.getOperand(1);
1426 SDValue Align = Op.getOperand(2);
1428 // Chain the dynamic stack allocation so that it doesn't modify the stack
1429 // pointer when other instructions are using the stack.
1430 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1432 unsigned AlignVal = cast<ConstantSDNode>(Align)->getZExtValue();
1433 unsigned StackAlign = getTargetMachine().getFrameInfo()->getStackAlignment();
1434 if (AlignVal > StackAlign)
1435 // Do this now since selection pass cannot introduce new target
1436 // independent node.
1437 Align = DAG.getConstant(-(uint64_t)AlignVal, VT);
1439 // In Thumb1 mode, there isn't a "sub r, sp, r" instruction, we will end up
1440 // using a "add r, sp, r" instead. Negate the size now so we don't have to
1441 // do even more horrible hack later.
1442 MachineFunction &MF = DAG.getMachineFunction();
1443 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1444 if (AFI->isThumb1OnlyFunction()) {
1446 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Size);
1448 uint32_t Val = C->getZExtValue();
1449 if (Val <= 508 && ((Val & 3) == 0))
1453 Size = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, VT), Size);
1456 SDVTList VTList = DAG.getVTList(VT, MVT::Other);
1457 SDValue Ops1[] = { Chain, Size, Align };
1458 SDValue Res = DAG.getNode(ARMISD::DYN_ALLOC, dl, VTList, Ops1, 3);
1459 Chain = Res.getValue(1);
1460 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1461 DAG.getIntPtrConstant(0, true), SDValue());
1462 SDValue Ops2[] = { Res, Chain };
1463 return DAG.getMergeValues(Ops2, 2, dl);
1467 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
1468 SDValue &Root, SelectionDAG &DAG,
1470 MachineFunction &MF = DAG.getMachineFunction();
1471 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1473 TargetRegisterClass *RC;
1474 if (AFI->isThumb1OnlyFunction())
1475 RC = ARM::tGPRRegisterClass;
1477 RC = ARM::GPRRegisterClass;
1479 // Transform the arguments stored in physical registers into virtual ones.
1480 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1481 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
1484 if (NextVA.isMemLoc()) {
1485 unsigned ArgSize = NextVA.getLocVT().getSizeInBits()/8;
1486 MachineFrameInfo *MFI = MF.getFrameInfo();
1487 int FI = MFI->CreateFixedObject(ArgSize, NextVA.getLocMemOffset());
1489 // Create load node to retrieve arguments from the stack.
1490 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1491 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN, NULL, 0);
1493 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
1494 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
1497 return DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, ArgValue, ArgValue2);
1501 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
1502 CallingConv::ID CallConv, bool isVarArg,
1503 const SmallVectorImpl<ISD::InputArg>
1505 DebugLoc dl, SelectionDAG &DAG,
1506 SmallVectorImpl<SDValue> &InVals) {
1508 MachineFunction &MF = DAG.getMachineFunction();
1509 MachineFrameInfo *MFI = MF.getFrameInfo();
1511 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1513 // Assign locations to all of the incoming arguments.
1514 SmallVector<CCValAssign, 16> ArgLocs;
1515 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1517 CCInfo.AnalyzeFormalArguments(Ins,
1518 CCAssignFnForNode(CallConv, /* Return*/ false,
1521 SmallVector<SDValue, 16> ArgValues;
1523 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1524 CCValAssign &VA = ArgLocs[i];
1526 // Arguments stored in registers.
1527 if (VA.isRegLoc()) {
1528 EVT RegVT = VA.getLocVT();
1531 if (VA.needsCustom()) {
1532 // f64 and vector types are split up into multiple registers or
1533 // combinations of registers and stack slots.
1536 if (VA.getLocVT() == MVT::v2f64) {
1537 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
1539 VA = ArgLocs[++i]; // skip ahead to next loc
1540 SDValue ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
1542 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1543 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
1544 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
1545 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
1546 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
1548 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
1551 TargetRegisterClass *RC;
1553 if (RegVT == MVT::f32)
1554 RC = ARM::SPRRegisterClass;
1555 else if (RegVT == MVT::f64)
1556 RC = ARM::DPRRegisterClass;
1557 else if (RegVT == MVT::v2f64)
1558 RC = ARM::QPRRegisterClass;
1559 else if (RegVT == MVT::i32)
1560 RC = (AFI->isThumb1OnlyFunction() ?
1561 ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
1563 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
1565 // Transform the arguments in physical registers into virtual ones.
1566 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1567 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1570 // If this is an 8 or 16-bit value, it is really passed promoted
1571 // to 32 bits. Insert an assert[sz]ext to capture this, then
1572 // truncate to the right size.
1573 switch (VA.getLocInfo()) {
1574 default: llvm_unreachable("Unknown loc info!");
1575 case CCValAssign::Full: break;
1576 case CCValAssign::BCvt:
1577 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1579 case CCValAssign::SExt:
1580 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1581 DAG.getValueType(VA.getValVT()));
1582 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1584 case CCValAssign::ZExt:
1585 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1586 DAG.getValueType(VA.getValVT()));
1587 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1591 InVals.push_back(ArgValue);
1593 } else { // VA.isRegLoc()
1596 assert(VA.isMemLoc());
1597 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
1599 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
1600 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset());
1602 // Create load nodes to retrieve arguments from the stack.
1603 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1604 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, NULL, 0));
1610 static const unsigned GPRArgRegs[] = {
1611 ARM::R0, ARM::R1, ARM::R2, ARM::R3
1614 unsigned NumGPRs = CCInfo.getFirstUnallocated
1615 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
1617 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1618 unsigned VARegSize = (4 - NumGPRs) * 4;
1619 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
1620 unsigned ArgOffset = 0;
1621 if (VARegSaveSize) {
1622 // If this function is vararg, store any remaining integer argument regs
1623 // to their spots on the stack so that they may be loaded by deferencing
1624 // the result of va_next.
1625 AFI->setVarArgsRegSaveSize(VARegSaveSize);
1626 ArgOffset = CCInfo.getNextStackOffset();
1627 VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset +
1628 VARegSaveSize - VARegSize);
1629 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
1631 SmallVector<SDValue, 4> MemOps;
1632 for (; NumGPRs < 4; ++NumGPRs) {
1633 TargetRegisterClass *RC;
1634 if (AFI->isThumb1OnlyFunction())
1635 RC = ARM::tGPRRegisterClass;
1637 RC = ARM::GPRRegisterClass;
1639 unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
1640 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
1641 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
1642 MemOps.push_back(Store);
1643 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
1644 DAG.getConstant(4, getPointerTy()));
1646 if (!MemOps.empty())
1647 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1648 &MemOps[0], MemOps.size());
1650 // This will point to the next argument passed via stack.
1651 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
1657 /// isFloatingPointZero - Return true if this is +0.0.
1658 static bool isFloatingPointZero(SDValue Op) {
1659 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1660 return CFP->getValueAPF().isPosZero();
1661 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1662 // Maybe this has already been legalized into the constant pool?
1663 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
1664 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
1665 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
1666 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1667 return CFP->getValueAPF().isPosZero();
1673 static bool isLegalCmpImmediate(unsigned C, bool isThumb1Only) {
1674 return ( isThumb1Only && (C & ~255U) == 0) ||
1675 (!isThumb1Only && ARM_AM::getSOImmVal(C) != -1);
1678 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
1679 /// the given operands.
1680 static SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1681 SDValue &ARMCC, SelectionDAG &DAG, bool isThumb1Only,
1683 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1684 unsigned C = RHSC->getZExtValue();
1685 if (!isLegalCmpImmediate(C, isThumb1Only)) {
1686 // Constant does not fit, try adjusting it by one?
1691 if (isLegalCmpImmediate(C-1, isThumb1Only)) {
1692 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1693 RHS = DAG.getConstant(C-1, MVT::i32);
1698 if (C > 0 && isLegalCmpImmediate(C-1, isThumb1Only)) {
1699 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1700 RHS = DAG.getConstant(C-1, MVT::i32);
1705 if (isLegalCmpImmediate(C+1, isThumb1Only)) {
1706 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1707 RHS = DAG.getConstant(C+1, MVT::i32);
1712 if (C < 0xffffffff && isLegalCmpImmediate(C+1, isThumb1Only)) {
1713 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1714 RHS = DAG.getConstant(C+1, MVT::i32);
1721 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
1722 ARMISD::NodeType CompareType;
1725 CompareType = ARMISD::CMP;
1730 CompareType = ARMISD::CMPZ;
1733 ARMCC = DAG.getConstant(CondCode, MVT::i32);
1734 return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS);
1737 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
1738 static SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
1741 if (!isFloatingPointZero(RHS))
1742 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS);
1744 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS);
1745 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp);
1748 static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
1749 const ARMSubtarget *ST) {
1750 EVT VT = Op.getValueType();
1751 SDValue LHS = Op.getOperand(0);
1752 SDValue RHS = Op.getOperand(1);
1753 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1754 SDValue TrueVal = Op.getOperand(2);
1755 SDValue FalseVal = Op.getOperand(3);
1756 DebugLoc dl = Op.getDebugLoc();
1758 if (LHS.getValueType() == MVT::i32) {
1760 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1761 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb1Only(), dl);
1762 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC, CCR,Cmp);
1765 ARMCC::CondCodes CondCode, CondCode2;
1766 FPCCToARMCC(CC, CondCode, CondCode2);
1768 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
1769 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1770 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
1771 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
1773 if (CondCode2 != ARMCC::AL) {
1774 SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
1775 // FIXME: Needs another CMP because flag can have but one use.
1776 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
1777 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
1778 Result, TrueVal, ARMCC2, CCR, Cmp2);
1783 static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
1784 const ARMSubtarget *ST) {
1785 SDValue Chain = Op.getOperand(0);
1786 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1787 SDValue LHS = Op.getOperand(2);
1788 SDValue RHS = Op.getOperand(3);
1789 SDValue Dest = Op.getOperand(4);
1790 DebugLoc dl = Op.getDebugLoc();
1792 if (LHS.getValueType() == MVT::i32) {
1794 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1795 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb1Only(), dl);
1796 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
1797 Chain, Dest, ARMCC, CCR,Cmp);
1800 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
1801 ARMCC::CondCodes CondCode, CondCode2;
1802 FPCCToARMCC(CC, CondCode, CondCode2);
1804 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
1805 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
1806 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1807 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
1808 SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp };
1809 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
1810 if (CondCode2 != ARMCC::AL) {
1811 ARMCC = DAG.getConstant(CondCode2, MVT::i32);
1812 SDValue Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) };
1813 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
1818 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) {
1819 SDValue Chain = Op.getOperand(0);
1820 SDValue Table = Op.getOperand(1);
1821 SDValue Index = Op.getOperand(2);
1822 DebugLoc dl = Op.getDebugLoc();
1824 EVT PTy = getPointerTy();
1825 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
1826 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
1827 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
1828 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
1829 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
1830 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
1831 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
1832 if (Subtarget->isThumb2()) {
1833 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
1834 // which does another jump to the destination. This also makes it easier
1835 // to translate it to TBB / TBH later.
1836 // FIXME: This might not work if the function is extremely large.
1837 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
1838 Addr, Op.getOperand(2), JTI, UId);
1840 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1841 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr, NULL, 0);
1842 Chain = Addr.getValue(1);
1843 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
1844 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
1846 Addr = DAG.getLoad(PTy, dl, Chain, Addr, NULL, 0);
1847 Chain = Addr.getValue(1);
1848 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
1852 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1853 DebugLoc dl = Op.getDebugLoc();
1855 Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI;
1856 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
1857 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
1860 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1861 EVT VT = Op.getValueType();
1862 DebugLoc dl = Op.getDebugLoc();
1864 Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF;
1866 Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
1867 return DAG.getNode(Opc, dl, VT, Op);
1870 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
1871 // Implement fcopysign with a fabs and a conditional fneg.
1872 SDValue Tmp0 = Op.getOperand(0);
1873 SDValue Tmp1 = Op.getOperand(1);
1874 DebugLoc dl = Op.getDebugLoc();
1875 EVT VT = Op.getValueType();
1876 EVT SrcVT = Tmp1.getValueType();
1877 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
1878 SDValue Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG, dl);
1879 SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
1880 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1881 return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp);
1884 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
1885 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1886 MFI->setFrameAddressIsTaken(true);
1887 EVT VT = Op.getValueType();
1888 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
1889 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1890 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
1891 ? ARM::R7 : ARM::R11;
1892 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
1894 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0);
1899 ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
1901 SDValue Dst, SDValue Src,
1902 SDValue Size, unsigned Align,
1904 const Value *DstSV, uint64_t DstSVOff,
1905 const Value *SrcSV, uint64_t SrcSVOff){
1906 // Do repeated 4-byte loads and stores. To be improved.
1907 // This requires 4-byte alignment.
1908 if ((Align & 3) != 0)
1910 // This requires the copy size to be a constant, preferrably
1911 // within a subtarget-specific limit.
1912 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
1915 uint64_t SizeVal = ConstantSize->getZExtValue();
1916 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
1919 unsigned BytesLeft = SizeVal & 3;
1920 unsigned NumMemOps = SizeVal >> 2;
1921 unsigned EmittedNumMemOps = 0;
1923 unsigned VTSize = 4;
1925 const unsigned MAX_LOADS_IN_LDM = 6;
1926 SDValue TFOps[MAX_LOADS_IN_LDM];
1927 SDValue Loads[MAX_LOADS_IN_LDM];
1928 uint64_t SrcOff = 0, DstOff = 0;
1930 // Emit up to MAX_LOADS_IN_LDM loads, then a TokenFactor barrier, then the
1931 // same number of stores. The loads and stores will get combined into
1932 // ldm/stm later on.
1933 while (EmittedNumMemOps < NumMemOps) {
1935 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
1936 Loads[i] = DAG.getLoad(VT, dl, Chain,
1937 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
1938 DAG.getConstant(SrcOff, MVT::i32)),
1939 SrcSV, SrcSVOff + SrcOff);
1940 TFOps[i] = Loads[i].getValue(1);
1943 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
1946 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
1947 TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
1948 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
1949 DAG.getConstant(DstOff, MVT::i32)),
1950 DstSV, DstSVOff + DstOff);
1953 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
1955 EmittedNumMemOps += i;
1961 // Issue loads / stores for the trailing (1 - 3) bytes.
1962 unsigned BytesLeftSave = BytesLeft;
1965 if (BytesLeft >= 2) {
1973 Loads[i] = DAG.getLoad(VT, dl, Chain,
1974 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
1975 DAG.getConstant(SrcOff, MVT::i32)),
1976 SrcSV, SrcSVOff + SrcOff);
1977 TFOps[i] = Loads[i].getValue(1);
1980 BytesLeft -= VTSize;
1982 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
1985 BytesLeft = BytesLeftSave;
1987 if (BytesLeft >= 2) {
1995 TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
1996 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
1997 DAG.getConstant(DstOff, MVT::i32)),
1998 DstSV, DstSVOff + DstOff);
2001 BytesLeft -= VTSize;
2003 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
2006 static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
2007 SDValue Op = N->getOperand(0);
2008 DebugLoc dl = N->getDebugLoc();
2009 if (N->getValueType(0) == MVT::f64) {
2010 // Turn i64->f64 into FMDRR.
2011 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2012 DAG.getConstant(0, MVT::i32));
2013 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2014 DAG.getConstant(1, MVT::i32));
2015 return DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
2018 // Turn f64->i64 into FMRRD.
2019 SDValue Cvt = DAG.getNode(ARMISD::FMRRD, dl,
2020 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
2022 // Merge the pieces into a single i64 value.
2023 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
2026 /// getZeroVector - Returns a vector of specified type with all zero elements.
2028 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2029 assert(VT.isVector() && "Expected a vector type");
2031 // Zero vectors are used to represent vector negation and in those cases
2032 // will be implemented with the NEON VNEG instruction. However, VNEG does
2033 // not support i64 elements, so sometimes the zero vectors will need to be
2034 // explicitly constructed. For those cases, and potentially other uses in
2035 // the future, always build zero vectors as <16 x i8> or <8 x i8> bitcasted
2036 // to their dest type. This ensures they get CSE'd.
2038 SDValue Cst = DAG.getTargetConstant(0, MVT::i8);
2039 SmallVector<SDValue, 8> Ops;
2042 if (VT.getSizeInBits() == 64) {
2043 Ops.assign(8, Cst); TVT = MVT::v8i8;
2045 Ops.assign(16, Cst); TVT = MVT::v16i8;
2047 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, TVT, &Ops[0], Ops.size());
2049 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2052 /// getOnesVector - Returns a vector of specified type with all bits set.
2054 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2055 assert(VT.isVector() && "Expected a vector type");
2057 // Always build ones vectors as <16 x i32> or <8 x i32> bitcasted to their
2058 // dest type. This ensures they get CSE'd.
2060 SDValue Cst = DAG.getTargetConstant(0xFF, MVT::i8);
2061 SmallVector<SDValue, 8> Ops;
2064 if (VT.getSizeInBits() == 64) {
2065 Ops.assign(8, Cst); TVT = MVT::v8i8;
2067 Ops.assign(16, Cst); TVT = MVT::v16i8;
2069 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, TVT, &Ops[0], Ops.size());
2071 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2074 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
2075 const ARMSubtarget *ST) {
2076 EVT VT = N->getValueType(0);
2077 DebugLoc dl = N->getDebugLoc();
2079 // Lower vector shifts on NEON to use VSHL.
2080 if (VT.isVector()) {
2081 assert(ST->hasNEON() && "unexpected vector shift");
2083 // Left shifts translate directly to the vshiftu intrinsic.
2084 if (N->getOpcode() == ISD::SHL)
2085 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2086 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
2087 N->getOperand(0), N->getOperand(1));
2089 assert((N->getOpcode() == ISD::SRA ||
2090 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
2092 // NEON uses the same intrinsics for both left and right shifts. For
2093 // right shifts, the shift amounts are negative, so negate the vector of
2095 EVT ShiftVT = N->getOperand(1).getValueType();
2096 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
2097 getZeroVector(ShiftVT, DAG, dl),
2099 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
2100 Intrinsic::arm_neon_vshifts :
2101 Intrinsic::arm_neon_vshiftu);
2102 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2103 DAG.getConstant(vshiftInt, MVT::i32),
2104 N->getOperand(0), NegatedCount);
2107 // We can get here for a node like i32 = ISD::SHL i32, i64
2111 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
2112 "Unknown shift to lower!");
2114 // We only lower SRA, SRL of 1 here, all others use generic lowering.
2115 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
2116 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
2119 // If we are in thumb mode, we don't have RRX.
2120 if (ST->isThumb1Only()) return SDValue();
2122 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
2123 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2124 DAG.getConstant(0, MVT::i32));
2125 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2126 DAG.getConstant(1, MVT::i32));
2128 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
2129 // captures the result into a carry flag.
2130 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
2131 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
2133 // The low part is an ARMISD::RRX operand, which shifts the carry in.
2134 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
2136 // Merge the pieces into a single i64 value.
2137 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
2140 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
2141 SDValue TmpOp0, TmpOp1;
2142 bool Invert = false;
2146 SDValue Op0 = Op.getOperand(0);
2147 SDValue Op1 = Op.getOperand(1);
2148 SDValue CC = Op.getOperand(2);
2149 EVT VT = Op.getValueType();
2150 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
2151 DebugLoc dl = Op.getDebugLoc();
2153 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
2154 switch (SetCCOpcode) {
2155 default: llvm_unreachable("Illegal FP comparison"); break;
2157 case ISD::SETNE: Invert = true; // Fallthrough
2159 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2161 case ISD::SETLT: Swap = true; // Fallthrough
2163 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2165 case ISD::SETLE: Swap = true; // Fallthrough
2167 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2168 case ISD::SETUGE: Swap = true; // Fallthrough
2169 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
2170 case ISD::SETUGT: Swap = true; // Fallthrough
2171 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
2172 case ISD::SETUEQ: Invert = true; // Fallthrough
2174 // Expand this to (OLT | OGT).
2178 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2179 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
2181 case ISD::SETUO: Invert = true; // Fallthrough
2183 // Expand this to (OLT | OGE).
2187 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2188 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
2192 // Integer comparisons.
2193 switch (SetCCOpcode) {
2194 default: llvm_unreachable("Illegal integer comparison"); break;
2195 case ISD::SETNE: Invert = true;
2196 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2197 case ISD::SETLT: Swap = true;
2198 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2199 case ISD::SETLE: Swap = true;
2200 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2201 case ISD::SETULT: Swap = true;
2202 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
2203 case ISD::SETULE: Swap = true;
2204 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
2207 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
2208 if (Opc == ARMISD::VCEQ) {
2211 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
2213 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
2216 // Ignore bitconvert.
2217 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BIT_CONVERT)
2218 AndOp = AndOp.getOperand(0);
2220 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
2222 Op0 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(0));
2223 Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(1));
2230 std::swap(Op0, Op1);
2232 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
2235 Result = DAG.getNOT(dl, Result, VT);
2240 /// isVMOVSplat - Check if the specified splat value corresponds to an immediate
2241 /// VMOV instruction, and if so, return the constant being splatted.
2242 static SDValue isVMOVSplat(uint64_t SplatBits, uint64_t SplatUndef,
2243 unsigned SplatBitSize, SelectionDAG &DAG) {
2244 switch (SplatBitSize) {
2246 // Any 1-byte value is OK.
2247 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
2248 return DAG.getTargetConstant(SplatBits, MVT::i8);
2251 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
2252 if ((SplatBits & ~0xff) == 0 ||
2253 (SplatBits & ~0xff00) == 0)
2254 return DAG.getTargetConstant(SplatBits, MVT::i16);
2258 // NEON's 32-bit VMOV supports splat values where:
2259 // * only one byte is nonzero, or
2260 // * the least significant byte is 0xff and the second byte is nonzero, or
2261 // * the least significant 2 bytes are 0xff and the third is nonzero.
2262 if ((SplatBits & ~0xff) == 0 ||
2263 (SplatBits & ~0xff00) == 0 ||
2264 (SplatBits & ~0xff0000) == 0 ||
2265 (SplatBits & ~0xff000000) == 0)
2266 return DAG.getTargetConstant(SplatBits, MVT::i32);
2268 if ((SplatBits & ~0xffff) == 0 &&
2269 ((SplatBits | SplatUndef) & 0xff) == 0xff)
2270 return DAG.getTargetConstant(SplatBits | 0xff, MVT::i32);
2272 if ((SplatBits & ~0xffffff) == 0 &&
2273 ((SplatBits | SplatUndef) & 0xffff) == 0xffff)
2274 return DAG.getTargetConstant(SplatBits | 0xffff, MVT::i32);
2276 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
2277 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
2278 // VMOV.I32. A (very) minor optimization would be to replicate the value
2279 // and fall through here to test for a valid 64-bit splat. But, then the
2280 // caller would also need to check and handle the change in size.
2284 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
2285 uint64_t BitMask = 0xff;
2287 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
2288 if (((SplatBits | SplatUndef) & BitMask) == BitMask)
2290 else if ((SplatBits & BitMask) != 0)
2294 return DAG.getTargetConstant(Val, MVT::i64);
2298 llvm_unreachable("unexpected size for isVMOVSplat");
2305 /// getVMOVImm - If this is a build_vector of constants which can be
2306 /// formed by using a VMOV instruction of the specified element size,
2307 /// return the constant being splatted. The ByteSize field indicates the
2308 /// number of bytes of each element [1248].
2309 SDValue ARM::getVMOVImm(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
2310 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N);
2311 APInt SplatBits, SplatUndef;
2312 unsigned SplatBitSize;
2314 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
2315 HasAnyUndefs, ByteSize * 8))
2318 if (SplatBitSize > ByteSize * 8)
2321 return isVMOVSplat(SplatBits.getZExtValue(), SplatUndef.getZExtValue(),
2325 static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT,
2326 bool &ReverseVEXT, unsigned &Imm) {
2327 unsigned NumElts = VT.getVectorNumElements();
2328 ReverseVEXT = false;
2331 // If this is a VEXT shuffle, the immediate value is the index of the first
2332 // element. The other shuffle indices must be the successive elements after
2334 unsigned ExpectedElt = Imm;
2335 for (unsigned i = 1; i < NumElts; ++i) {
2336 // Increment the expected index. If it wraps around, it may still be
2337 // a VEXT but the source vectors must be swapped.
2339 if (ExpectedElt == NumElts * 2) {
2344 if (ExpectedElt != static_cast<unsigned>(M[i]))
2348 // Adjust the index value if the source operands will be swapped.
2355 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
2356 /// instruction with the specified blocksize. (The order of the elements
2357 /// within each block of the vector is reversed.)
2358 static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT,
2359 unsigned BlockSize) {
2360 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
2361 "Only possible block sizes for VREV are: 16, 32, 64");
2363 unsigned NumElts = VT.getVectorNumElements();
2364 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2365 unsigned BlockElts = M[0] + 1;
2367 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
2370 for (unsigned i = 0; i < NumElts; ++i) {
2371 if ((unsigned) M[i] !=
2372 (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
2379 static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT,
2380 unsigned &WhichResult) {
2381 unsigned NumElts = VT.getVectorNumElements();
2382 WhichResult = (M[0] == 0 ? 0 : 1);
2383 for (unsigned i = 0; i < NumElts; i += 2) {
2384 if ((unsigned) M[i] != i + WhichResult ||
2385 (unsigned) M[i+1] != i + NumElts + WhichResult)
2391 static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT,
2392 unsigned &WhichResult) {
2393 unsigned NumElts = VT.getVectorNumElements();
2394 WhichResult = (M[0] == 0 ? 0 : 1);
2395 for (unsigned i = 0; i != NumElts; ++i) {
2396 if ((unsigned) M[i] != 2 * i + WhichResult)
2400 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
2401 if (VT.is64BitVector() && VT.getVectorElementType().getSizeInBits() == 32)
2407 static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT,
2408 unsigned &WhichResult) {
2409 unsigned NumElts = VT.getVectorNumElements();
2410 WhichResult = (M[0] == 0 ? 0 : 1);
2411 unsigned Idx = WhichResult * NumElts / 2;
2412 for (unsigned i = 0; i != NumElts; i += 2) {
2413 if ((unsigned) M[i] != Idx ||
2414 (unsigned) M[i+1] != Idx + NumElts)
2419 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
2420 if (VT.is64BitVector() && VT.getVectorElementType().getSizeInBits() == 32)
2426 static SDValue BuildSplat(SDValue Val, EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2427 // Canonicalize all-zeros and all-ones vectors.
2428 ConstantSDNode *ConstVal = cast<ConstantSDNode>(Val.getNode());
2429 if (ConstVal->isNullValue())
2430 return getZeroVector(VT, DAG, dl);
2431 if (ConstVal->isAllOnesValue())
2432 return getOnesVector(VT, DAG, dl);
2435 if (VT.is64BitVector()) {
2436 switch (Val.getValueType().getSizeInBits()) {
2437 case 8: CanonicalVT = MVT::v8i8; break;
2438 case 16: CanonicalVT = MVT::v4i16; break;
2439 case 32: CanonicalVT = MVT::v2i32; break;
2440 case 64: CanonicalVT = MVT::v1i64; break;
2441 default: llvm_unreachable("unexpected splat element type"); break;
2444 assert(VT.is128BitVector() && "unknown splat vector size");
2445 switch (Val.getValueType().getSizeInBits()) {
2446 case 8: CanonicalVT = MVT::v16i8; break;
2447 case 16: CanonicalVT = MVT::v8i16; break;
2448 case 32: CanonicalVT = MVT::v4i32; break;
2449 case 64: CanonicalVT = MVT::v2i64; break;
2450 default: llvm_unreachable("unexpected splat element type"); break;
2454 // Build a canonical splat for this value.
2455 SmallVector<SDValue, 8> Ops;
2456 Ops.assign(CanonicalVT.getVectorNumElements(), Val);
2457 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, &Ops[0],
2459 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Res);
2462 // If this is a case we can't handle, return null and let the default
2463 // expansion code take care of it.
2464 static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
2465 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
2466 DebugLoc dl = Op.getDebugLoc();
2467 EVT VT = Op.getValueType();
2469 APInt SplatBits, SplatUndef;
2470 unsigned SplatBitSize;
2472 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
2473 if (SplatBitSize <= 64) {
2474 SDValue Val = isVMOVSplat(SplatBits.getZExtValue(),
2475 SplatUndef.getZExtValue(), SplatBitSize, DAG);
2477 return BuildSplat(Val, VT, DAG, dl);
2481 // If there are only 2 elements in a 128-bit vector, insert them into an
2482 // undef vector. This handles the common case for 128-bit vector argument
2483 // passing, where the insertions should be translated to subreg accesses
2484 // with no real instructions.
2485 if (VT.is128BitVector() && Op.getNumOperands() == 2) {
2486 SDValue Val = DAG.getUNDEF(VT);
2487 SDValue Op0 = Op.getOperand(0);
2488 SDValue Op1 = Op.getOperand(1);
2489 if (Op0.getOpcode() != ISD::UNDEF)
2490 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, Op0,
2491 DAG.getIntPtrConstant(0));
2492 if (Op1.getOpcode() != ISD::UNDEF)
2493 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, Op1,
2494 DAG.getIntPtrConstant(1));
2501 /// isShuffleMaskLegal - Targets can use this to indicate that they only
2502 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
2503 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
2504 /// are assumed to be legal.
2506 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
2508 if (VT.getVectorNumElements() == 4 &&
2509 (VT.is128BitVector() || VT.is64BitVector())) {
2510 unsigned PFIndexes[4];
2511 for (unsigned i = 0; i != 4; ++i) {
2515 PFIndexes[i] = M[i];
2518 // Compute the index in the perfect shuffle table.
2519 unsigned PFTableIndex =
2520 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
2521 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
2522 unsigned Cost = (PFEntry >> 30);
2529 unsigned Imm, WhichResult;
2531 return (ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
2532 isVREVMask(M, VT, 64) ||
2533 isVREVMask(M, VT, 32) ||
2534 isVREVMask(M, VT, 16) ||
2535 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
2536 isVTRNMask(M, VT, WhichResult) ||
2537 isVUZPMask(M, VT, WhichResult) ||
2538 isVZIPMask(M, VT, WhichResult));
2541 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
2542 /// the specified operations to build the shuffle.
2543 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
2544 SDValue RHS, SelectionDAG &DAG,
2546 unsigned OpNum = (PFEntry >> 26) & 0x0F;
2547 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
2548 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
2551 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
2560 OP_VUZPL, // VUZP, left result
2561 OP_VUZPR, // VUZP, right result
2562 OP_VZIPL, // VZIP, left result
2563 OP_VZIPR, // VZIP, right result
2564 OP_VTRNL, // VTRN, left result
2565 OP_VTRNR // VTRN, right result
2568 if (OpNum == OP_COPY) {
2569 if (LHSID == (1*9+2)*9+3) return LHS;
2570 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
2574 SDValue OpLHS, OpRHS;
2575 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
2576 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
2577 EVT VT = OpLHS.getValueType();
2580 default: llvm_unreachable("Unknown shuffle opcode!");
2582 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
2587 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
2588 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
2592 return DAG.getNode(ARMISD::VEXT, dl, VT,
2594 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
2597 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
2598 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
2601 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
2602 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
2605 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
2606 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
2610 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
2611 SDValue V1 = Op.getOperand(0);
2612 SDValue V2 = Op.getOperand(1);
2613 DebugLoc dl = Op.getDebugLoc();
2614 EVT VT = Op.getValueType();
2615 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
2616 SmallVector<int, 8> ShuffleMask;
2618 // Convert shuffles that are directly supported on NEON to target-specific
2619 // DAG nodes, instead of keeping them as shuffles and matching them again
2620 // during code selection. This is more efficient and avoids the possibility
2621 // of inconsistencies between legalization and selection.
2622 // FIXME: floating-point vectors should be canonicalized to integer vectors
2623 // of the same time so that they get CSEd properly.
2624 SVN->getMask(ShuffleMask);
2626 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
2627 int Lane = SVN->getSplatIndex();
2628 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
2629 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
2631 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
2632 DAG.getConstant(Lane, MVT::i32));
2637 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
2640 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
2641 DAG.getConstant(Imm, MVT::i32));
2644 if (isVREVMask(ShuffleMask, VT, 64))
2645 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
2646 if (isVREVMask(ShuffleMask, VT, 32))
2647 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
2648 if (isVREVMask(ShuffleMask, VT, 16))
2649 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
2651 // Check for Neon shuffles that modify both input vectors in place.
2652 // If both results are used, i.e., if there are two shuffles with the same
2653 // source operands and with masks corresponding to both results of one of
2654 // these operations, DAG memoization will ensure that a single node is
2655 // used for both shuffles.
2656 unsigned WhichResult;
2657 if (isVTRNMask(ShuffleMask, VT, WhichResult))
2658 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
2659 V1, V2).getValue(WhichResult);
2660 if (isVUZPMask(ShuffleMask, VT, WhichResult))
2661 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
2662 V1, V2).getValue(WhichResult);
2663 if (isVZIPMask(ShuffleMask, VT, WhichResult))
2664 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
2665 V1, V2).getValue(WhichResult);
2667 // If the shuffle is not directly supported and it has 4 elements, use
2668 // the PerfectShuffle-generated table to synthesize it from other shuffles.
2669 if (VT.getVectorNumElements() == 4 &&
2670 (VT.is128BitVector() || VT.is64BitVector())) {
2671 unsigned PFIndexes[4];
2672 for (unsigned i = 0; i != 4; ++i) {
2673 if (ShuffleMask[i] < 0)
2676 PFIndexes[i] = ShuffleMask[i];
2679 // Compute the index in the perfect shuffle table.
2680 unsigned PFTableIndex =
2681 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
2683 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
2684 unsigned Cost = (PFEntry >> 30);
2687 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
2693 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
2694 EVT VT = Op.getValueType();
2695 DebugLoc dl = Op.getDebugLoc();
2696 SDValue Vec = Op.getOperand(0);
2697 SDValue Lane = Op.getOperand(1);
2698 assert(VT == MVT::i32 &&
2699 Vec.getValueType().getVectorElementType().getSizeInBits() < 32 &&
2700 "unexpected type for custom-lowering vector extract");
2701 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
2704 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
2705 // The only time a CONCAT_VECTORS operation can have legal types is when
2706 // two 64-bit vectors are concatenated to a 128-bit vector.
2707 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
2708 "unexpected CONCAT_VECTORS");
2709 DebugLoc dl = Op.getDebugLoc();
2710 SDValue Val = DAG.getUNDEF(MVT::v2f64);
2711 SDValue Op0 = Op.getOperand(0);
2712 SDValue Op1 = Op.getOperand(1);
2713 if (Op0.getOpcode() != ISD::UNDEF)
2714 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
2715 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op0),
2716 DAG.getIntPtrConstant(0));
2717 if (Op1.getOpcode() != ISD::UNDEF)
2718 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
2719 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op1),
2720 DAG.getIntPtrConstant(1));
2721 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Val);
2724 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
2725 switch (Op.getOpcode()) {
2726 default: llvm_unreachable("Don't know how to custom lower this!");
2727 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2728 case ISD::GlobalAddress:
2729 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
2730 LowerGlobalAddressELF(Op, DAG);
2731 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
2732 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, Subtarget);
2733 case ISD::BR_CC: return LowerBR_CC(Op, DAG, Subtarget);
2734 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
2735 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
2736 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex);
2737 case ISD::SINT_TO_FP:
2738 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
2739 case ISD::FP_TO_SINT:
2740 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
2741 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
2742 case ISD::RETURNADDR: break;
2743 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
2744 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
2745 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2746 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(Op.getNode(), DAG);
2749 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
2750 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
2751 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
2752 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
2753 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
2754 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
2759 /// ReplaceNodeResults - Replace the results of node with an illegal result
2760 /// type with new values built out of custom code.
2761 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
2762 SmallVectorImpl<SDValue>&Results,
2763 SelectionDAG &DAG) {
2764 switch (N->getOpcode()) {
2766 llvm_unreachable("Don't know how to custom expand this!");
2768 case ISD::BIT_CONVERT:
2769 Results.push_back(ExpandBIT_CONVERT(N, DAG));
2773 SDValue Res = LowerShift(N, DAG, Subtarget);
2775 Results.push_back(Res);
2781 //===----------------------------------------------------------------------===//
2782 // ARM Scheduler Hooks
2783 //===----------------------------------------------------------------------===//
2786 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
2787 MachineBasicBlock *BB,
2788 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
2789 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2790 DebugLoc dl = MI->getDebugLoc();
2791 switch (MI->getOpcode()) {
2793 llvm_unreachable("Unexpected instr type to insert");
2794 case ARM::tMOVCCr_pseudo: {
2795 // To "insert" a SELECT_CC instruction, we actually have to insert the
2796 // diamond control-flow pattern. The incoming instruction knows the
2797 // destination vreg to set, the condition code register to branch on, the
2798 // true/false values to select between, and a branch opcode to use.
2799 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2800 MachineFunction::iterator It = BB;
2806 // cmpTY ccX, r1, r2
2808 // fallthrough --> copy0MBB
2809 MachineBasicBlock *thisMBB = BB;
2810 MachineFunction *F = BB->getParent();
2811 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
2812 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
2813 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
2814 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
2815 F->insert(It, copy0MBB);
2816 F->insert(It, sinkMBB);
2817 // Update machine-CFG edges by first adding all successors of the current
2818 // block to the new block which will contain the Phi node for the select.
2819 // Also inform sdisel of the edge changes.
2820 for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
2821 E = BB->succ_end(); I != E; ++I) {
2822 EM->insert(std::make_pair(*I, sinkMBB));
2823 sinkMBB->addSuccessor(*I);
2825 // Next, remove all successors of the current block, and add the true
2826 // and fallthrough blocks as its successors.
2827 while (!BB->succ_empty())
2828 BB->removeSuccessor(BB->succ_begin());
2829 BB->addSuccessor(copy0MBB);
2830 BB->addSuccessor(sinkMBB);
2833 // %FalseValue = ...
2834 // # fallthrough to sinkMBB
2837 // Update machine-CFG edges
2838 BB->addSuccessor(sinkMBB);
2841 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
2844 BuildMI(BB, dl, TII->get(ARM::PHI), MI->getOperand(0).getReg())
2845 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
2846 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
2848 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
2855 case ARM::t2SUBrSPi_:
2856 case ARM::t2SUBrSPi12_:
2857 case ARM::t2SUBrSPs_: {
2858 MachineFunction *MF = BB->getParent();
2859 unsigned DstReg = MI->getOperand(0).getReg();
2860 unsigned SrcReg = MI->getOperand(1).getReg();
2861 bool DstIsDead = MI->getOperand(0).isDead();
2862 bool SrcIsKill = MI->getOperand(1).isKill();
2864 if (SrcReg != ARM::SP) {
2865 // Copy the source to SP from virtual register.
2866 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(SrcReg);
2867 unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
2868 ? ARM::tMOVtgpr2gpr : ARM::tMOVgpr2gpr;
2869 BuildMI(BB, dl, TII->get(CopyOpc), ARM::SP)
2870 .addReg(SrcReg, getKillRegState(SrcIsKill));
2874 bool NeedPred = false, NeedCC = false, NeedOp3 = false;
2875 switch (MI->getOpcode()) {
2877 llvm_unreachable("Unexpected pseudo instruction!");
2883 OpOpc = ARM::tADDspr;
2886 OpOpc = ARM::tSUBspi;
2888 case ARM::t2SUBrSPi_:
2889 OpOpc = ARM::t2SUBrSPi;
2890 NeedPred = true; NeedCC = true;
2892 case ARM::t2SUBrSPi12_:
2893 OpOpc = ARM::t2SUBrSPi12;
2896 case ARM::t2SUBrSPs_:
2897 OpOpc = ARM::t2SUBrSPs;
2898 NeedPred = true; NeedCC = true; NeedOp3 = true;
2901 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(OpOpc), ARM::SP);
2902 if (OpOpc == ARM::tAND)
2903 AddDefaultT1CC(MIB);
2904 MIB.addReg(ARM::SP);
2905 MIB.addOperand(MI->getOperand(2));
2907 MIB.addOperand(MI->getOperand(3));
2909 AddDefaultPred(MIB);
2913 // Copy the result from SP to virtual register.
2914 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(DstReg);
2915 unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
2916 ? ARM::tMOVgpr2tgpr : ARM::tMOVgpr2gpr;
2917 BuildMI(BB, dl, TII->get(CopyOpc))
2918 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead))
2920 MF->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
2926 //===----------------------------------------------------------------------===//
2927 // ARM Optimization Hooks
2928 //===----------------------------------------------------------------------===//
2931 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
2932 TargetLowering::DAGCombinerInfo &DCI) {
2933 SelectionDAG &DAG = DCI.DAG;
2934 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2935 EVT VT = N->getValueType(0);
2936 unsigned Opc = N->getOpcode();
2937 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
2938 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
2939 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
2940 ISD::CondCode CC = ISD::SETCC_INVALID;
2943 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
2945 SDValue CCOp = Slct.getOperand(0);
2946 if (CCOp.getOpcode() == ISD::SETCC)
2947 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
2950 bool DoXform = false;
2952 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
2955 if (LHS.getOpcode() == ISD::Constant &&
2956 cast<ConstantSDNode>(LHS)->isNullValue()) {
2958 } else if (CC != ISD::SETCC_INVALID &&
2959 RHS.getOpcode() == ISD::Constant &&
2960 cast<ConstantSDNode>(RHS)->isNullValue()) {
2961 std::swap(LHS, RHS);
2962 SDValue Op0 = Slct.getOperand(0);
2963 EVT OpVT = isSlctCC ? Op0.getValueType() :
2964 Op0.getOperand(0).getValueType();
2965 bool isInt = OpVT.isInteger();
2966 CC = ISD::getSetCCInverse(CC, isInt);
2968 if (!TLI.isCondCodeLegal(CC, OpVT))
2969 return SDValue(); // Inverse operator isn't legal.
2976 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
2978 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
2979 Slct.getOperand(0), Slct.getOperand(1), CC);
2980 SDValue CCOp = Slct.getOperand(0);
2982 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
2983 CCOp.getOperand(0), CCOp.getOperand(1), CC);
2984 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
2985 CCOp, OtherOp, Result);
2990 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
2991 static SDValue PerformADDCombine(SDNode *N,
2992 TargetLowering::DAGCombinerInfo &DCI) {
2993 // added by evan in r37685 with no testcase.
2994 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2996 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
2997 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
2998 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
2999 if (Result.getNode()) return Result;
3001 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
3002 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
3003 if (Result.getNode()) return Result;
3009 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
3010 static SDValue PerformSUBCombine(SDNode *N,
3011 TargetLowering::DAGCombinerInfo &DCI) {
3012 // added by evan in r37685 with no testcase.
3013 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
3015 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
3016 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
3017 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
3018 if (Result.getNode()) return Result;
3025 /// PerformFMRRDCombine - Target-specific dag combine xforms for ARMISD::FMRRD.
3026 static SDValue PerformFMRRDCombine(SDNode *N,
3027 TargetLowering::DAGCombinerInfo &DCI) {
3028 // fmrrd(fmdrr x, y) -> x,y
3029 SDValue InDouble = N->getOperand(0);
3030 if (InDouble.getOpcode() == ARMISD::FMDRR)
3031 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
3035 /// getVShiftImm - Check if this is a valid build_vector for the immediate
3036 /// operand of a vector shift operation, where all the elements of the
3037 /// build_vector must have the same constant integer value.
3038 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
3039 // Ignore bit_converts.
3040 while (Op.getOpcode() == ISD::BIT_CONVERT)
3041 Op = Op.getOperand(0);
3042 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
3043 APInt SplatBits, SplatUndef;
3044 unsigned SplatBitSize;
3046 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
3047 HasAnyUndefs, ElementBits) ||
3048 SplatBitSize > ElementBits)
3050 Cnt = SplatBits.getSExtValue();
3054 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
3055 /// operand of a vector shift left operation. That value must be in the range:
3056 /// 0 <= Value < ElementBits for a left shift; or
3057 /// 0 <= Value <= ElementBits for a long left shift.
3058 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
3059 assert(VT.isVector() && "vector shift count is not a vector type");
3060 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
3061 if (! getVShiftImm(Op, ElementBits, Cnt))
3063 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
3066 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
3067 /// operand of a vector shift right operation. For a shift opcode, the value
3068 /// is positive, but for an intrinsic the value count must be negative. The
3069 /// absolute value must be in the range:
3070 /// 1 <= |Value| <= ElementBits for a right shift; or
3071 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
3072 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
3074 assert(VT.isVector() && "vector shift count is not a vector type");
3075 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
3076 if (! getVShiftImm(Op, ElementBits, Cnt))
3080 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
3083 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
3084 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
3085 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
3088 // Don't do anything for most intrinsics.
3091 // Vector shifts: check for immediate versions and lower them.
3092 // Note: This is done during DAG combining instead of DAG legalizing because
3093 // the build_vectors for 64-bit vector element shift counts are generally
3094 // not legal, and it is hard to see their values after they get legalized to
3095 // loads from a constant pool.
3096 case Intrinsic::arm_neon_vshifts:
3097 case Intrinsic::arm_neon_vshiftu:
3098 case Intrinsic::arm_neon_vshiftls:
3099 case Intrinsic::arm_neon_vshiftlu:
3100 case Intrinsic::arm_neon_vshiftn:
3101 case Intrinsic::arm_neon_vrshifts:
3102 case Intrinsic::arm_neon_vrshiftu:
3103 case Intrinsic::arm_neon_vrshiftn:
3104 case Intrinsic::arm_neon_vqshifts:
3105 case Intrinsic::arm_neon_vqshiftu:
3106 case Intrinsic::arm_neon_vqshiftsu:
3107 case Intrinsic::arm_neon_vqshiftns:
3108 case Intrinsic::arm_neon_vqshiftnu:
3109 case Intrinsic::arm_neon_vqshiftnsu:
3110 case Intrinsic::arm_neon_vqrshiftns:
3111 case Intrinsic::arm_neon_vqrshiftnu:
3112 case Intrinsic::arm_neon_vqrshiftnsu: {
3113 EVT VT = N->getOperand(1).getValueType();
3115 unsigned VShiftOpc = 0;
3118 case Intrinsic::arm_neon_vshifts:
3119 case Intrinsic::arm_neon_vshiftu:
3120 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
3121 VShiftOpc = ARMISD::VSHL;
3124 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
3125 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
3126 ARMISD::VSHRs : ARMISD::VSHRu);
3131 case Intrinsic::arm_neon_vshiftls:
3132 case Intrinsic::arm_neon_vshiftlu:
3133 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
3135 llvm_unreachable("invalid shift count for vshll intrinsic");
3137 case Intrinsic::arm_neon_vrshifts:
3138 case Intrinsic::arm_neon_vrshiftu:
3139 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
3143 case Intrinsic::arm_neon_vqshifts:
3144 case Intrinsic::arm_neon_vqshiftu:
3145 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
3149 case Intrinsic::arm_neon_vqshiftsu:
3150 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
3152 llvm_unreachable("invalid shift count for vqshlu intrinsic");
3154 case Intrinsic::arm_neon_vshiftn:
3155 case Intrinsic::arm_neon_vrshiftn:
3156 case Intrinsic::arm_neon_vqshiftns:
3157 case Intrinsic::arm_neon_vqshiftnu:
3158 case Intrinsic::arm_neon_vqshiftnsu:
3159 case Intrinsic::arm_neon_vqrshiftns:
3160 case Intrinsic::arm_neon_vqrshiftnu:
3161 case Intrinsic::arm_neon_vqrshiftnsu:
3162 // Narrowing shifts require an immediate right shift.
3163 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
3165 llvm_unreachable("invalid shift count for narrowing vector shift intrinsic");
3168 llvm_unreachable("unhandled vector shift");
3172 case Intrinsic::arm_neon_vshifts:
3173 case Intrinsic::arm_neon_vshiftu:
3174 // Opcode already set above.
3176 case Intrinsic::arm_neon_vshiftls:
3177 case Intrinsic::arm_neon_vshiftlu:
3178 if (Cnt == VT.getVectorElementType().getSizeInBits())
3179 VShiftOpc = ARMISD::VSHLLi;
3181 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
3182 ARMISD::VSHLLs : ARMISD::VSHLLu);
3184 case Intrinsic::arm_neon_vshiftn:
3185 VShiftOpc = ARMISD::VSHRN; break;
3186 case Intrinsic::arm_neon_vrshifts:
3187 VShiftOpc = ARMISD::VRSHRs; break;
3188 case Intrinsic::arm_neon_vrshiftu:
3189 VShiftOpc = ARMISD::VRSHRu; break;
3190 case Intrinsic::arm_neon_vrshiftn:
3191 VShiftOpc = ARMISD::VRSHRN; break;
3192 case Intrinsic::arm_neon_vqshifts:
3193 VShiftOpc = ARMISD::VQSHLs; break;
3194 case Intrinsic::arm_neon_vqshiftu:
3195 VShiftOpc = ARMISD::VQSHLu; break;
3196 case Intrinsic::arm_neon_vqshiftsu:
3197 VShiftOpc = ARMISD::VQSHLsu; break;
3198 case Intrinsic::arm_neon_vqshiftns:
3199 VShiftOpc = ARMISD::VQSHRNs; break;
3200 case Intrinsic::arm_neon_vqshiftnu:
3201 VShiftOpc = ARMISD::VQSHRNu; break;
3202 case Intrinsic::arm_neon_vqshiftnsu:
3203 VShiftOpc = ARMISD::VQSHRNsu; break;
3204 case Intrinsic::arm_neon_vqrshiftns:
3205 VShiftOpc = ARMISD::VQRSHRNs; break;
3206 case Intrinsic::arm_neon_vqrshiftnu:
3207 VShiftOpc = ARMISD::VQRSHRNu; break;
3208 case Intrinsic::arm_neon_vqrshiftnsu:
3209 VShiftOpc = ARMISD::VQRSHRNsu; break;
3212 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
3213 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
3216 case Intrinsic::arm_neon_vshiftins: {
3217 EVT VT = N->getOperand(1).getValueType();
3219 unsigned VShiftOpc = 0;
3221 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
3222 VShiftOpc = ARMISD::VSLI;
3223 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
3224 VShiftOpc = ARMISD::VSRI;
3226 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
3229 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
3230 N->getOperand(1), N->getOperand(2),
3231 DAG.getConstant(Cnt, MVT::i32));
3234 case Intrinsic::arm_neon_vqrshifts:
3235 case Intrinsic::arm_neon_vqrshiftu:
3236 // No immediate versions of these to check for.
3243 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
3244 /// lowers them. As with the vector shift intrinsics, this is done during DAG
3245 /// combining instead of DAG legalizing because the build_vectors for 64-bit
3246 /// vector element shift counts are generally not legal, and it is hard to see
3247 /// their values after they get legalized to loads from a constant pool.
3248 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
3249 const ARMSubtarget *ST) {
3250 EVT VT = N->getValueType(0);
3252 // Nothing to be done for scalar shifts.
3253 if (! VT.isVector())
3256 assert(ST->hasNEON() && "unexpected vector shift");
3259 switch (N->getOpcode()) {
3260 default: llvm_unreachable("unexpected shift opcode");
3263 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
3264 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
3265 DAG.getConstant(Cnt, MVT::i32));
3270 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
3271 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
3272 ARMISD::VSHRs : ARMISD::VSHRu);
3273 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
3274 DAG.getConstant(Cnt, MVT::i32));
3280 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
3281 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
3282 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
3283 const ARMSubtarget *ST) {
3284 SDValue N0 = N->getOperand(0);
3286 // Check for sign- and zero-extensions of vector extract operations of 8-
3287 // and 16-bit vector elements. NEON supports these directly. They are
3288 // handled during DAG combining because type legalization will promote them
3289 // to 32-bit types and it is messy to recognize the operations after that.
3290 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
3291 SDValue Vec = N0.getOperand(0);
3292 SDValue Lane = N0.getOperand(1);
3293 EVT VT = N->getValueType(0);
3294 EVT EltVT = N0.getValueType();
3295 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3297 if (VT == MVT::i32 &&
3298 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
3299 TLI.isTypeLegal(Vec.getValueType())) {
3302 switch (N->getOpcode()) {
3303 default: llvm_unreachable("unexpected opcode");
3304 case ISD::SIGN_EXTEND:
3305 Opc = ARMISD::VGETLANEs;
3307 case ISD::ZERO_EXTEND:
3308 case ISD::ANY_EXTEND:
3309 Opc = ARMISD::VGETLANEu;
3312 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
3319 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
3320 DAGCombinerInfo &DCI) const {
3321 switch (N->getOpcode()) {
3323 case ISD::ADD: return PerformADDCombine(N, DCI);
3324 case ISD::SUB: return PerformSUBCombine(N, DCI);
3325 case ARMISD::FMRRD: return PerformFMRRDCombine(N, DCI);
3326 case ISD::INTRINSIC_WO_CHAIN:
3327 return PerformIntrinsicCombine(N, DCI.DAG);
3331 return PerformShiftCombine(N, DCI.DAG, Subtarget);
3332 case ISD::SIGN_EXTEND:
3333 case ISD::ZERO_EXTEND:
3334 case ISD::ANY_EXTEND:
3335 return PerformExtendCombine(N, DCI.DAG, Subtarget);
3340 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
3341 if (!Subtarget->hasV6Ops())
3342 // Pre-v6 does not support unaligned mem access.
3344 else if (!Subtarget->hasV6Ops()) {
3345 // v6 may or may not support unaligned mem access.
3346 if (!Subtarget->isTargetDarwin())
3350 switch (VT.getSimpleVT().SimpleTy) {
3357 // FIXME: VLD1 etc with standard alignment is legal.
3361 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
3366 switch (VT.getSimpleVT().SimpleTy) {
3367 default: return false;
3382 if ((V & (Scale - 1)) != 0)
3385 return V == (V & ((1LL << 5) - 1));
3388 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
3389 const ARMSubtarget *Subtarget) {
3396 switch (VT.getSimpleVT().SimpleTy) {
3397 default: return false;
3402 // + imm12 or - imm8
3404 return V == (V & ((1LL << 8) - 1));
3405 return V == (V & ((1LL << 12) - 1));
3408 // Same as ARM mode. FIXME: NEON?
3409 if (!Subtarget->hasVFP2())
3414 return V == (V & ((1LL << 8) - 1));
3418 /// isLegalAddressImmediate - Return true if the integer value can be used
3419 /// as the offset of the target addressing mode for load / store of the
3421 static bool isLegalAddressImmediate(int64_t V, EVT VT,
3422 const ARMSubtarget *Subtarget) {
3429 if (Subtarget->isThumb1Only())
3430 return isLegalT1AddressImmediate(V, VT);
3431 else if (Subtarget->isThumb2())
3432 return isLegalT2AddressImmediate(V, VT, Subtarget);
3437 switch (VT.getSimpleVT().SimpleTy) {
3438 default: return false;
3443 return V == (V & ((1LL << 12) - 1));
3446 return V == (V & ((1LL << 8) - 1));
3449 if (!Subtarget->hasVFP2()) // FIXME: NEON?
3454 return V == (V & ((1LL << 8) - 1));
3458 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
3460 int Scale = AM.Scale;
3464 switch (VT.getSimpleVT().SimpleTy) {
3465 default: return false;
3474 return Scale == 2 || Scale == 4 || Scale == 8;
3477 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
3481 // Note, we allow "void" uses (basically, uses that aren't loads or
3482 // stores), because arm allows folding a scale into many arithmetic
3483 // operations. This should be made more precise and revisited later.
3485 // Allow r << imm, but the imm has to be a multiple of two.
3486 if (Scale & 1) return false;
3487 return isPowerOf2_32(Scale);
3491 /// isLegalAddressingMode - Return true if the addressing mode represented
3492 /// by AM is legal for this target, for a load/store of the specified type.
3493 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
3494 const Type *Ty) const {
3495 EVT VT = getValueType(Ty, true);
3496 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
3499 // Can never fold addr of global into load/store.
3504 case 0: // no scale reg, must be "r+i" or "r", or "i".
3507 if (Subtarget->isThumb1Only())
3511 // ARM doesn't support any R+R*scale+imm addr modes.
3518 if (Subtarget->isThumb2())
3519 return isLegalT2ScaledAddressingMode(AM, VT);
3521 int Scale = AM.Scale;
3522 switch (VT.getSimpleVT().SimpleTy) {
3523 default: return false;
3527 if (Scale < 0) Scale = -Scale;
3531 return isPowerOf2_32(Scale & ~1);
3535 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
3540 // Note, we allow "void" uses (basically, uses that aren't loads or
3541 // stores), because arm allows folding a scale into many arithmetic
3542 // operations. This should be made more precise and revisited later.
3544 // Allow r << imm, but the imm has to be a multiple of two.
3545 if (Scale & 1) return false;
3546 return isPowerOf2_32(Scale);
3553 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
3554 bool isSEXTLoad, SDValue &Base,
3555 SDValue &Offset, bool &isInc,
3556 SelectionDAG &DAG) {
3557 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
3560 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
3562 Base = Ptr->getOperand(0);
3563 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
3564 int RHSC = (int)RHS->getZExtValue();
3565 if (RHSC < 0 && RHSC > -256) {
3566 assert(Ptr->getOpcode() == ISD::ADD);
3568 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
3572 isInc = (Ptr->getOpcode() == ISD::ADD);
3573 Offset = Ptr->getOperand(1);
3575 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
3577 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
3578 int RHSC = (int)RHS->getZExtValue();
3579 if (RHSC < 0 && RHSC > -0x1000) {
3580 assert(Ptr->getOpcode() == ISD::ADD);
3582 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
3583 Base = Ptr->getOperand(0);
3588 if (Ptr->getOpcode() == ISD::ADD) {
3590 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
3591 if (ShOpcVal != ARM_AM::no_shift) {
3592 Base = Ptr->getOperand(1);
3593 Offset = Ptr->getOperand(0);
3595 Base = Ptr->getOperand(0);
3596 Offset = Ptr->getOperand(1);
3601 isInc = (Ptr->getOpcode() == ISD::ADD);
3602 Base = Ptr->getOperand(0);
3603 Offset = Ptr->getOperand(1);
3607 // FIXME: Use FLDM / FSTM to emulate indexed FP load / store.
3611 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
3612 bool isSEXTLoad, SDValue &Base,
3613 SDValue &Offset, bool &isInc,
3614 SelectionDAG &DAG) {
3615 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
3618 Base = Ptr->getOperand(0);
3619 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
3620 int RHSC = (int)RHS->getZExtValue();
3621 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
3622 assert(Ptr->getOpcode() == ISD::ADD);
3624 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
3626 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
3627 isInc = Ptr->getOpcode() == ISD::ADD;
3628 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
3636 /// getPreIndexedAddressParts - returns true by value, base pointer and
3637 /// offset pointer and addressing mode by reference if the node's address
3638 /// can be legally represented as pre-indexed load / store address.
3640 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
3642 ISD::MemIndexedMode &AM,
3643 SelectionDAG &DAG) const {
3644 if (Subtarget->isThumb1Only())
3649 bool isSEXTLoad = false;
3650 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3651 Ptr = LD->getBasePtr();
3652 VT = LD->getMemoryVT();
3653 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
3654 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3655 Ptr = ST->getBasePtr();
3656 VT = ST->getMemoryVT();
3661 bool isLegal = false;
3662 if (Subtarget->isThumb2())
3663 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
3664 Offset, isInc, DAG);
3666 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
3667 Offset, isInc, DAG);
3671 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
3675 /// getPostIndexedAddressParts - returns true by value, base pointer and
3676 /// offset pointer and addressing mode by reference if this node can be
3677 /// combined with a load / store to form a post-indexed load / store.
3678 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
3681 ISD::MemIndexedMode &AM,
3682 SelectionDAG &DAG) const {
3683 if (Subtarget->isThumb1Only())
3688 bool isSEXTLoad = false;
3689 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3690 VT = LD->getMemoryVT();
3691 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
3692 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3693 VT = ST->getMemoryVT();
3698 bool isLegal = false;
3699 if (Subtarget->isThumb2())
3700 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
3703 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
3708 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
3712 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
3716 const SelectionDAG &DAG,
3717 unsigned Depth) const {
3718 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
3719 switch (Op.getOpcode()) {
3721 case ARMISD::CMOV: {
3722 // Bits are known zero/one if known on the LHS and RHS.
3723 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
3724 if (KnownZero == 0 && KnownOne == 0) return;
3726 APInt KnownZeroRHS, KnownOneRHS;
3727 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
3728 KnownZeroRHS, KnownOneRHS, Depth+1);
3729 KnownZero &= KnownZeroRHS;
3730 KnownOne &= KnownOneRHS;
3736 //===----------------------------------------------------------------------===//
3737 // ARM Inline Assembly Support
3738 //===----------------------------------------------------------------------===//
3740 /// getConstraintType - Given a constraint letter, return the type of
3741 /// constraint it is for this target.
3742 ARMTargetLowering::ConstraintType
3743 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
3744 if (Constraint.size() == 1) {
3745 switch (Constraint[0]) {
3747 case 'l': return C_RegisterClass;
3748 case 'w': return C_RegisterClass;
3751 return TargetLowering::getConstraintType(Constraint);
3754 std::pair<unsigned, const TargetRegisterClass*>
3755 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
3757 if (Constraint.size() == 1) {
3758 // GCC RS6000 Constraint Letters
3759 switch (Constraint[0]) {
3761 if (Subtarget->isThumb1Only())
3762 return std::make_pair(0U, ARM::tGPRRegisterClass);
3764 return std::make_pair(0U, ARM::GPRRegisterClass);
3766 return std::make_pair(0U, ARM::GPRRegisterClass);
3769 return std::make_pair(0U, ARM::SPRRegisterClass);
3771 return std::make_pair(0U, ARM::DPRRegisterClass);
3775 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3778 std::vector<unsigned> ARMTargetLowering::
3779 getRegClassForInlineAsmConstraint(const std::string &Constraint,
3781 if (Constraint.size() != 1)
3782 return std::vector<unsigned>();
3784 switch (Constraint[0]) { // GCC ARM Constraint Letters
3787 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
3788 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
3791 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
3792 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
3793 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
3794 ARM::R12, ARM::LR, 0);
3797 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
3798 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
3799 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
3800 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
3801 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
3802 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
3803 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
3804 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
3806 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
3807 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
3808 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
3809 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
3813 return std::vector<unsigned>();
3816 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3817 /// vector. If it is invalid, don't add anything to Ops.
3818 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
3821 std::vector<SDValue>&Ops,
3822 SelectionDAG &DAG) const {
3823 SDValue Result(0, 0);
3825 switch (Constraint) {
3827 case 'I': case 'J': case 'K': case 'L':
3828 case 'M': case 'N': case 'O':
3829 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3833 int64_t CVal64 = C->getSExtValue();
3834 int CVal = (int) CVal64;
3835 // None of these constraints allow values larger than 32 bits. Check
3836 // that the value fits in an int.
3840 switch (Constraint) {
3842 if (Subtarget->isThumb1Only()) {
3843 // This must be a constant between 0 and 255, for ADD
3845 if (CVal >= 0 && CVal <= 255)
3847 } else if (Subtarget->isThumb2()) {
3848 // A constant that can be used as an immediate value in a
3849 // data-processing instruction.
3850 if (ARM_AM::getT2SOImmVal(CVal) != -1)
3853 // A constant that can be used as an immediate value in a
3854 // data-processing instruction.
3855 if (ARM_AM::getSOImmVal(CVal) != -1)
3861 if (Subtarget->isThumb()) { // FIXME thumb2
3862 // This must be a constant between -255 and -1, for negated ADD
3863 // immediates. This can be used in GCC with an "n" modifier that
3864 // prints the negated value, for use with SUB instructions. It is
3865 // not useful otherwise but is implemented for compatibility.
3866 if (CVal >= -255 && CVal <= -1)
3869 // This must be a constant between -4095 and 4095. It is not clear
3870 // what this constraint is intended for. Implemented for
3871 // compatibility with GCC.
3872 if (CVal >= -4095 && CVal <= 4095)
3878 if (Subtarget->isThumb1Only()) {
3879 // A 32-bit value where only one byte has a nonzero value. Exclude
3880 // zero to match GCC. This constraint is used by GCC internally for
3881 // constants that can be loaded with a move/shift combination.
3882 // It is not useful otherwise but is implemented for compatibility.
3883 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
3885 } else if (Subtarget->isThumb2()) {
3886 // A constant whose bitwise inverse can be used as an immediate
3887 // value in a data-processing instruction. This can be used in GCC
3888 // with a "B" modifier that prints the inverted value, for use with
3889 // BIC and MVN instructions. It is not useful otherwise but is
3890 // implemented for compatibility.
3891 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
3894 // A constant whose bitwise inverse can be used as an immediate
3895 // value in a data-processing instruction. This can be used in GCC
3896 // with a "B" modifier that prints the inverted value, for use with
3897 // BIC and MVN instructions. It is not useful otherwise but is
3898 // implemented for compatibility.
3899 if (ARM_AM::getSOImmVal(~CVal) != -1)
3905 if (Subtarget->isThumb1Only()) {
3906 // This must be a constant between -7 and 7,
3907 // for 3-operand ADD/SUB immediate instructions.
3908 if (CVal >= -7 && CVal < 7)
3910 } else if (Subtarget->isThumb2()) {
3911 // A constant whose negation can be used as an immediate value in a
3912 // data-processing instruction. This can be used in GCC with an "n"
3913 // modifier that prints the negated value, for use with SUB
3914 // instructions. It is not useful otherwise but is implemented for
3916 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
3919 // A constant whose negation can be used as an immediate value in a
3920 // data-processing instruction. This can be used in GCC with an "n"
3921 // modifier that prints the negated value, for use with SUB
3922 // instructions. It is not useful otherwise but is implemented for
3924 if (ARM_AM::getSOImmVal(-CVal) != -1)
3930 if (Subtarget->isThumb()) { // FIXME thumb2
3931 // This must be a multiple of 4 between 0 and 1020, for
3932 // ADD sp + immediate.
3933 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
3936 // A power of two or a constant between 0 and 32. This is used in
3937 // GCC for the shift amount on shifted register operands, but it is
3938 // useful in general for any shift amounts.
3939 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
3945 if (Subtarget->isThumb()) { // FIXME thumb2
3946 // This must be a constant between 0 and 31, for shift amounts.
3947 if (CVal >= 0 && CVal <= 31)
3953 if (Subtarget->isThumb()) { // FIXME thumb2
3954 // This must be a multiple of 4 between -508 and 508, for
3955 // ADD/SUB sp = sp + immediate.
3956 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
3961 Result = DAG.getTargetConstant(CVal, Op.getValueType());
3965 if (Result.getNode()) {
3966 Ops.push_back(Result);
3969 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,
3974 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
3975 // The ARM target isn't yet aware of offsets.