1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "ARMISelLowering.h"
16 #include "ARMCallingConv.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMPerfectShuffle.h"
20 #include "ARMSubtarget.h"
21 #include "ARMTargetMachine.h"
22 #include "ARMTargetObjectFile.h"
23 #include "MCTargetDesc/ARMAddressingModes.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/CodeGen/CallingConvLower.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineBasicBlock.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SelectionDAG.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalValue.h"
41 #include "llvm/IR/IRBuilder.h"
42 #include "llvm/IR/Instruction.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/IntrinsicInst.h"
45 #include "llvm/IR/Intrinsics.h"
46 #include "llvm/IR/Type.h"
47 #include "llvm/MC/MCSectionMachO.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Support/raw_ostream.h"
53 #include "llvm/Target/TargetOptions.h"
57 #define DEBUG_TYPE "arm-isel"
59 STATISTIC(NumTailCalls, "Number of tail calls");
60 STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt");
61 STATISTIC(NumLoopByVals, "Number of loops generated for byval arguments");
64 EnableARMLongCalls("arm-long-calls", cl::Hidden,
65 cl::desc("Generate calls via indirect call instructions"),
69 ARMInterworking("arm-interworking", cl::Hidden,
70 cl::desc("Enable / disable ARM interworking (for debugging only)"),
74 class ARMCCState : public CCState {
76 ARMCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
77 SmallVectorImpl<CCValAssign> &locs, LLVMContext &C,
79 : CCState(CC, isVarArg, MF, locs, C) {
80 assert(((PC == Call) || (PC == Prologue)) &&
81 "ARMCCState users must specify whether their context is call"
82 "or prologue generation.");
88 // The APCS parameter registers.
89 static const MCPhysReg GPRArgRegs[] = {
90 ARM::R0, ARM::R1, ARM::R2, ARM::R3
93 void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT,
94 MVT PromotedBitwiseVT) {
95 if (VT != PromotedLdStVT) {
96 setOperationAction(ISD::LOAD, VT, Promote);
97 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
99 setOperationAction(ISD::STORE, VT, Promote);
100 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
103 MVT ElemTy = VT.getVectorElementType();
104 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
105 setOperationAction(ISD::SETCC, VT, Custom);
106 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
107 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
108 if (ElemTy == MVT::i32) {
109 setOperationAction(ISD::SINT_TO_FP, VT, Custom);
110 setOperationAction(ISD::UINT_TO_FP, VT, Custom);
111 setOperationAction(ISD::FP_TO_SINT, VT, Custom);
112 setOperationAction(ISD::FP_TO_UINT, VT, Custom);
114 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
115 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
116 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
117 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
119 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
120 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
121 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
122 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
123 setOperationAction(ISD::SELECT, VT, Expand);
124 setOperationAction(ISD::SELECT_CC, VT, Expand);
125 setOperationAction(ISD::VSELECT, VT, Expand);
126 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
127 if (VT.isInteger()) {
128 setOperationAction(ISD::SHL, VT, Custom);
129 setOperationAction(ISD::SRA, VT, Custom);
130 setOperationAction(ISD::SRL, VT, Custom);
133 // Promote all bit-wise operations.
134 if (VT.isInteger() && VT != PromotedBitwiseVT) {
135 setOperationAction(ISD::AND, VT, Promote);
136 AddPromotedToType (ISD::AND, VT, PromotedBitwiseVT);
137 setOperationAction(ISD::OR, VT, Promote);
138 AddPromotedToType (ISD::OR, VT, PromotedBitwiseVT);
139 setOperationAction(ISD::XOR, VT, Promote);
140 AddPromotedToType (ISD::XOR, VT, PromotedBitwiseVT);
143 // Neon does not support vector divide/remainder operations.
144 setOperationAction(ISD::SDIV, VT, Expand);
145 setOperationAction(ISD::UDIV, VT, Expand);
146 setOperationAction(ISD::FDIV, VT, Expand);
147 setOperationAction(ISD::SREM, VT, Expand);
148 setOperationAction(ISD::UREM, VT, Expand);
149 setOperationAction(ISD::FREM, VT, Expand);
152 void ARMTargetLowering::addDRTypeForNEON(MVT VT) {
153 addRegisterClass(VT, &ARM::DPRRegClass);
154 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
157 void ARMTargetLowering::addQRTypeForNEON(MVT VT) {
158 addRegisterClass(VT, &ARM::DPairRegClass);
159 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
162 ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
163 const ARMSubtarget &STI)
164 : TargetLowering(TM), Subtarget(&STI) {
165 RegInfo = Subtarget->getRegisterInfo();
166 Itins = Subtarget->getInstrItineraryData();
168 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
170 if (Subtarget->isTargetMachO()) {
171 // Uses VFP for Thumb libfuncs if available.
172 if (Subtarget->isThumb() && Subtarget->hasVFP2() &&
173 Subtarget->hasARMOps() && !TM.Options.UseSoftFloat) {
174 // Single-precision floating-point arithmetic.
175 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
176 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
177 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
178 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
180 // Double-precision floating-point arithmetic.
181 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
182 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
183 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
184 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
186 // Single-precision comparisons.
187 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
188 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
189 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
190 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
191 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
192 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
193 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
194 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
196 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
197 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
198 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
199 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
200 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
201 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
202 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
203 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
205 // Double-precision comparisons.
206 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
207 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
208 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
209 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
210 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
211 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
212 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
213 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
215 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
216 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
217 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
218 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
219 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
220 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
221 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
222 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
224 // Floating-point to integer conversions.
225 // i64 conversions are done via library routines even when generating VFP
226 // instructions, so use the same ones.
227 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
228 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
229 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
230 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
232 // Conversions between floating types.
233 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
234 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
236 // Integer to floating-point conversions.
237 // i64 conversions are done via library routines even when generating VFP
238 // instructions, so use the same ones.
239 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
240 // e.g., __floatunsidf vs. __floatunssidfvfp.
241 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
242 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
243 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
244 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
248 // These libcalls are not available in 32-bit.
249 setLibcallName(RTLIB::SHL_I128, nullptr);
250 setLibcallName(RTLIB::SRL_I128, nullptr);
251 setLibcallName(RTLIB::SRA_I128, nullptr);
253 if (Subtarget->isAAPCS_ABI() && !Subtarget->isTargetMachO() &&
254 !Subtarget->isTargetWindows()) {
255 static const struct {
256 const RTLIB::Libcall Op;
257 const char * const Name;
258 const CallingConv::ID CC;
259 const ISD::CondCode Cond;
261 // Double-precision floating-point arithmetic helper functions
262 // RTABI chapter 4.1.2, Table 2
263 { RTLIB::ADD_F64, "__aeabi_dadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
264 { RTLIB::DIV_F64, "__aeabi_ddiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
265 { RTLIB::MUL_F64, "__aeabi_dmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
266 { RTLIB::SUB_F64, "__aeabi_dsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
268 // Double-precision floating-point comparison helper functions
269 // RTABI chapter 4.1.2, Table 3
270 { RTLIB::OEQ_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
271 { RTLIB::UNE_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
272 { RTLIB::OLT_F64, "__aeabi_dcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
273 { RTLIB::OLE_F64, "__aeabi_dcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
274 { RTLIB::OGE_F64, "__aeabi_dcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
275 { RTLIB::OGT_F64, "__aeabi_dcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
276 { RTLIB::UO_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
277 { RTLIB::O_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ },
279 // Single-precision floating-point arithmetic helper functions
280 // RTABI chapter 4.1.2, Table 4
281 { RTLIB::ADD_F32, "__aeabi_fadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
282 { RTLIB::DIV_F32, "__aeabi_fdiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
283 { RTLIB::MUL_F32, "__aeabi_fmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
284 { RTLIB::SUB_F32, "__aeabi_fsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
286 // Single-precision floating-point comparison helper functions
287 // RTABI chapter 4.1.2, Table 5
288 { RTLIB::OEQ_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
289 { RTLIB::UNE_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
290 { RTLIB::OLT_F32, "__aeabi_fcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
291 { RTLIB::OLE_F32, "__aeabi_fcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
292 { RTLIB::OGE_F32, "__aeabi_fcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
293 { RTLIB::OGT_F32, "__aeabi_fcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
294 { RTLIB::UO_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
295 { RTLIB::O_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ },
297 // Floating-point to integer conversions.
298 // RTABI chapter 4.1.2, Table 6
299 { RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
300 { RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
301 { RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
302 { RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
303 { RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
304 { RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
305 { RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
306 { RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
308 // Conversions between floating types.
309 // RTABI chapter 4.1.2, Table 7
310 { RTLIB::FPROUND_F64_F32, "__aeabi_d2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
311 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
312 { RTLIB::FPEXT_F32_F64, "__aeabi_f2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
314 // Integer to floating-point conversions.
315 // RTABI chapter 4.1.2, Table 8
316 { RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
317 { RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
318 { RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
319 { RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
320 { RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
321 { RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
322 { RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
323 { RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
325 // Long long helper functions
326 // RTABI chapter 4.2, Table 9
327 { RTLIB::MUL_I64, "__aeabi_lmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
328 { RTLIB::SHL_I64, "__aeabi_llsl", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
329 { RTLIB::SRL_I64, "__aeabi_llsr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
330 { RTLIB::SRA_I64, "__aeabi_lasr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
332 // Integer division functions
333 // RTABI chapter 4.3.1
334 { RTLIB::SDIV_I8, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
335 { RTLIB::SDIV_I16, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
336 { RTLIB::SDIV_I32, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
337 { RTLIB::SDIV_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
338 { RTLIB::UDIV_I8, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
339 { RTLIB::UDIV_I16, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
340 { RTLIB::UDIV_I32, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
341 { RTLIB::UDIV_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
344 // RTABI chapter 4.3.4
345 { RTLIB::MEMCPY, "__aeabi_memcpy", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
346 { RTLIB::MEMMOVE, "__aeabi_memmove", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
347 { RTLIB::MEMSET, "__aeabi_memset", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
350 for (const auto &LC : LibraryCalls) {
351 setLibcallName(LC.Op, LC.Name);
352 setLibcallCallingConv(LC.Op, LC.CC);
353 if (LC.Cond != ISD::SETCC_INVALID)
354 setCmpLibcallCC(LC.Op, LC.Cond);
358 if (Subtarget->isTargetWindows()) {
359 static const struct {
360 const RTLIB::Libcall Op;
361 const char * const Name;
362 const CallingConv::ID CC;
364 { RTLIB::FPTOSINT_F32_I64, "__stoi64", CallingConv::ARM_AAPCS_VFP },
365 { RTLIB::FPTOSINT_F64_I64, "__dtoi64", CallingConv::ARM_AAPCS_VFP },
366 { RTLIB::FPTOUINT_F32_I64, "__stou64", CallingConv::ARM_AAPCS_VFP },
367 { RTLIB::FPTOUINT_F64_I64, "__dtou64", CallingConv::ARM_AAPCS_VFP },
368 { RTLIB::SINTTOFP_I64_F32, "__i64tos", CallingConv::ARM_AAPCS_VFP },
369 { RTLIB::SINTTOFP_I64_F64, "__i64tod", CallingConv::ARM_AAPCS_VFP },
370 { RTLIB::UINTTOFP_I64_F32, "__u64tos", CallingConv::ARM_AAPCS_VFP },
371 { RTLIB::UINTTOFP_I64_F64, "__u64tod", CallingConv::ARM_AAPCS_VFP },
374 for (const auto &LC : LibraryCalls) {
375 setLibcallName(LC.Op, LC.Name);
376 setLibcallCallingConv(LC.Op, LC.CC);
380 // Use divmod compiler-rt calls for iOS 5.0 and later.
381 if (Subtarget->getTargetTriple().isiOS() &&
382 !Subtarget->getTargetTriple().isOSVersionLT(5, 0)) {
383 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
384 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
387 // The half <-> float conversion functions are always soft-float, but are
388 // needed for some targets which use a hard-float calling convention by
390 if (Subtarget->isAAPCS_ABI()) {
391 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_AAPCS);
392 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_AAPCS);
393 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_AAPCS);
395 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_APCS);
396 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_APCS);
397 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_APCS);
400 if (Subtarget->isThumb1Only())
401 addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
403 addRegisterClass(MVT::i32, &ARM::GPRRegClass);
404 if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
405 !Subtarget->isThumb1Only()) {
406 addRegisterClass(MVT::f32, &ARM::SPRRegClass);
407 addRegisterClass(MVT::f64, &ARM::DPRRegClass);
410 for (MVT VT : MVT::vector_valuetypes()) {
411 for (MVT InnerVT : MVT::vector_valuetypes()) {
412 setTruncStoreAction(VT, InnerVT, Expand);
413 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
414 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
415 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
418 setOperationAction(ISD::MULHS, VT, Expand);
419 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
420 setOperationAction(ISD::MULHU, VT, Expand);
421 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
423 setOperationAction(ISD::BSWAP, VT, Expand);
426 setOperationAction(ISD::ConstantFP, MVT::f32, Custom);
427 setOperationAction(ISD::ConstantFP, MVT::f64, Custom);
429 if (Subtarget->hasNEON()) {
430 addDRTypeForNEON(MVT::v2f32);
431 addDRTypeForNEON(MVT::v8i8);
432 addDRTypeForNEON(MVT::v4i16);
433 addDRTypeForNEON(MVT::v2i32);
434 addDRTypeForNEON(MVT::v1i64);
436 addQRTypeForNEON(MVT::v4f32);
437 addQRTypeForNEON(MVT::v2f64);
438 addQRTypeForNEON(MVT::v16i8);
439 addQRTypeForNEON(MVT::v8i16);
440 addQRTypeForNEON(MVT::v4i32);
441 addQRTypeForNEON(MVT::v2i64);
443 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
444 // neither Neon nor VFP support any arithmetic operations on it.
445 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
446 // supported for v4f32.
447 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
448 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
449 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
450 // FIXME: Code duplication: FDIV and FREM are expanded always, see
451 // ARMTargetLowering::addTypeForNEON method for details.
452 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
453 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
454 // FIXME: Create unittest.
455 // In another words, find a way when "copysign" appears in DAG with vector
457 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
458 // FIXME: Code duplication: SETCC has custom operation action, see
459 // ARMTargetLowering::addTypeForNEON method for details.
460 setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
461 // FIXME: Create unittest for FNEG and for FABS.
462 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
463 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
464 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
465 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
466 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
467 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
468 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
469 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
470 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
471 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
472 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
473 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
474 // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR.
475 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
476 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
477 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
478 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
479 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
480 setOperationAction(ISD::FMA, MVT::v2f64, Expand);
482 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
483 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
484 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
485 setOperationAction(ISD::FPOWI, MVT::v4f32, Expand);
486 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
487 setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
488 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
489 setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
490 setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
491 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
492 setOperationAction(ISD::FCEIL, MVT::v4f32, Expand);
493 setOperationAction(ISD::FTRUNC, MVT::v4f32, Expand);
494 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
495 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
496 setOperationAction(ISD::FFLOOR, MVT::v4f32, Expand);
498 // Mark v2f32 intrinsics.
499 setOperationAction(ISD::FSQRT, MVT::v2f32, Expand);
500 setOperationAction(ISD::FSIN, MVT::v2f32, Expand);
501 setOperationAction(ISD::FCOS, MVT::v2f32, Expand);
502 setOperationAction(ISD::FPOWI, MVT::v2f32, Expand);
503 setOperationAction(ISD::FPOW, MVT::v2f32, Expand);
504 setOperationAction(ISD::FLOG, MVT::v2f32, Expand);
505 setOperationAction(ISD::FLOG2, MVT::v2f32, Expand);
506 setOperationAction(ISD::FLOG10, MVT::v2f32, Expand);
507 setOperationAction(ISD::FEXP, MVT::v2f32, Expand);
508 setOperationAction(ISD::FEXP2, MVT::v2f32, Expand);
509 setOperationAction(ISD::FCEIL, MVT::v2f32, Expand);
510 setOperationAction(ISD::FTRUNC, MVT::v2f32, Expand);
511 setOperationAction(ISD::FRINT, MVT::v2f32, Expand);
512 setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Expand);
513 setOperationAction(ISD::FFLOOR, MVT::v2f32, Expand);
515 // Neon does not support some operations on v1i64 and v2i64 types.
516 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
517 // Custom handling for some quad-vector types to detect VMULL.
518 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
519 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
520 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
521 // Custom handling for some vector types to avoid expensive expansions
522 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
523 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
524 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
525 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
526 setOperationAction(ISD::SETCC, MVT::v1i64, Expand);
527 setOperationAction(ISD::SETCC, MVT::v2i64, Expand);
528 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
529 // a destination type that is wider than the source, and nor does
530 // it have a FP_TO_[SU]INT instruction with a narrower destination than
532 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
533 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
534 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
535 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
537 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
538 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand);
540 // NEON does not have single instruction CTPOP for vectors with element
541 // types wider than 8-bits. However, custom lowering can leverage the
542 // v8i8/v16i8 vcnt instruction.
543 setOperationAction(ISD::CTPOP, MVT::v2i32, Custom);
544 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
545 setOperationAction(ISD::CTPOP, MVT::v4i16, Custom);
546 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
548 // NEON only has FMA instructions as of VFP4.
549 if (!Subtarget->hasVFP4()) {
550 setOperationAction(ISD::FMA, MVT::v2f32, Expand);
551 setOperationAction(ISD::FMA, MVT::v4f32, Expand);
554 setTargetDAGCombine(ISD::INTRINSIC_VOID);
555 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
556 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
557 setTargetDAGCombine(ISD::SHL);
558 setTargetDAGCombine(ISD::SRL);
559 setTargetDAGCombine(ISD::SRA);
560 setTargetDAGCombine(ISD::SIGN_EXTEND);
561 setTargetDAGCombine(ISD::ZERO_EXTEND);
562 setTargetDAGCombine(ISD::ANY_EXTEND);
563 setTargetDAGCombine(ISD::SELECT_CC);
564 setTargetDAGCombine(ISD::BUILD_VECTOR);
565 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
566 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
567 setTargetDAGCombine(ISD::STORE);
568 setTargetDAGCombine(ISD::FP_TO_SINT);
569 setTargetDAGCombine(ISD::FP_TO_UINT);
570 setTargetDAGCombine(ISD::FDIV);
571 setTargetDAGCombine(ISD::LOAD);
573 // It is legal to extload from v4i8 to v4i16 or v4i32.
574 for (MVT Ty : {MVT::v8i8, MVT::v4i8, MVT::v2i8, MVT::v4i16, MVT::v2i16,
576 for (MVT VT : MVT::integer_vector_valuetypes()) {
577 setLoadExtAction(ISD::EXTLOAD, VT, Ty, Legal);
578 setLoadExtAction(ISD::ZEXTLOAD, VT, Ty, Legal);
579 setLoadExtAction(ISD::SEXTLOAD, VT, Ty, Legal);
584 // ARM and Thumb2 support UMLAL/SMLAL.
585 if (!Subtarget->isThumb1Only())
586 setTargetDAGCombine(ISD::ADDC);
588 if (Subtarget->isFPOnlySP()) {
589 // When targetting a floating-point unit with only single-precision
590 // operations, f64 is legal for the few double-precision instructions which
591 // are present However, no double-precision operations other than moves,
592 // loads and stores are provided by the hardware.
593 setOperationAction(ISD::FADD, MVT::f64, Expand);
594 setOperationAction(ISD::FSUB, MVT::f64, Expand);
595 setOperationAction(ISD::FMUL, MVT::f64, Expand);
596 setOperationAction(ISD::FMA, MVT::f64, Expand);
597 setOperationAction(ISD::FDIV, MVT::f64, Expand);
598 setOperationAction(ISD::FREM, MVT::f64, Expand);
599 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
600 setOperationAction(ISD::FGETSIGN, MVT::f64, Expand);
601 setOperationAction(ISD::FNEG, MVT::f64, Expand);
602 setOperationAction(ISD::FABS, MVT::f64, Expand);
603 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
604 setOperationAction(ISD::FSIN, MVT::f64, Expand);
605 setOperationAction(ISD::FCOS, MVT::f64, Expand);
606 setOperationAction(ISD::FPOWI, MVT::f64, Expand);
607 setOperationAction(ISD::FPOW, MVT::f64, Expand);
608 setOperationAction(ISD::FLOG, MVT::f64, Expand);
609 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
610 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
611 setOperationAction(ISD::FEXP, MVT::f64, Expand);
612 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
613 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
614 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
615 setOperationAction(ISD::FRINT, MVT::f64, Expand);
616 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
617 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
618 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
619 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
620 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
621 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
622 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Custom);
623 setOperationAction(ISD::FP_TO_UINT, MVT::f64, Custom);
624 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
625 setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom);
628 computeRegisterProperties(Subtarget->getRegisterInfo());
630 // ARM does not have floating-point extending loads.
631 for (MVT VT : MVT::fp_valuetypes()) {
632 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
633 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
636 // ... or truncating stores
637 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
638 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
639 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
641 // ARM does not have i1 sign extending load.
642 for (MVT VT : MVT::integer_valuetypes())
643 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
645 // ARM supports all 4 flavors of integer indexed load / store.
646 if (!Subtarget->isThumb1Only()) {
647 for (unsigned im = (unsigned)ISD::PRE_INC;
648 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
649 setIndexedLoadAction(im, MVT::i1, Legal);
650 setIndexedLoadAction(im, MVT::i8, Legal);
651 setIndexedLoadAction(im, MVT::i16, Legal);
652 setIndexedLoadAction(im, MVT::i32, Legal);
653 setIndexedStoreAction(im, MVT::i1, Legal);
654 setIndexedStoreAction(im, MVT::i8, Legal);
655 setIndexedStoreAction(im, MVT::i16, Legal);
656 setIndexedStoreAction(im, MVT::i32, Legal);
660 setOperationAction(ISD::SADDO, MVT::i32, Custom);
661 setOperationAction(ISD::UADDO, MVT::i32, Custom);
662 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
663 setOperationAction(ISD::USUBO, MVT::i32, Custom);
665 // i64 operation support.
666 setOperationAction(ISD::MUL, MVT::i64, Expand);
667 setOperationAction(ISD::MULHU, MVT::i32, Expand);
668 if (Subtarget->isThumb1Only()) {
669 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
670 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
672 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
673 || (Subtarget->isThumb2() && !Subtarget->hasThumb2DSP()))
674 setOperationAction(ISD::MULHS, MVT::i32, Expand);
676 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
677 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
678 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
679 setOperationAction(ISD::SRL, MVT::i64, Custom);
680 setOperationAction(ISD::SRA, MVT::i64, Custom);
682 if (!Subtarget->isThumb1Only()) {
683 // FIXME: We should do this for Thumb1 as well.
684 setOperationAction(ISD::ADDC, MVT::i32, Custom);
685 setOperationAction(ISD::ADDE, MVT::i32, Custom);
686 setOperationAction(ISD::SUBC, MVT::i32, Custom);
687 setOperationAction(ISD::SUBE, MVT::i32, Custom);
690 // ARM does not have ROTL.
691 setOperationAction(ISD::ROTL, MVT::i32, Expand);
692 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
693 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
694 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
695 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
697 // These just redirect to CTTZ and CTLZ on ARM.
698 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i32 , Expand);
699 setOperationAction(ISD::CTLZ_ZERO_UNDEF , MVT::i32 , Expand);
701 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
703 // Only ARMv6 has BSWAP.
704 if (!Subtarget->hasV6Ops())
705 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
707 if (!(Subtarget->hasDivide() && Subtarget->isThumb2()) &&
708 !(Subtarget->hasDivideInARMMode() && !Subtarget->isThumb())) {
709 // These are expanded into libcalls if the cpu doesn't have HW divider.
710 setOperationAction(ISD::SDIV, MVT::i32, Expand);
711 setOperationAction(ISD::UDIV, MVT::i32, Expand);
714 // FIXME: Also set divmod for SREM on EABI
715 setOperationAction(ISD::SREM, MVT::i32, Expand);
716 setOperationAction(ISD::UREM, MVT::i32, Expand);
717 // Register based DivRem for AEABI (RTABI 4.2)
718 if (Subtarget->isTargetAEABI()) {
719 setLibcallName(RTLIB::SDIVREM_I8, "__aeabi_idivmod");
720 setLibcallName(RTLIB::SDIVREM_I16, "__aeabi_idivmod");
721 setLibcallName(RTLIB::SDIVREM_I32, "__aeabi_idivmod");
722 setLibcallName(RTLIB::SDIVREM_I64, "__aeabi_ldivmod");
723 setLibcallName(RTLIB::UDIVREM_I8, "__aeabi_uidivmod");
724 setLibcallName(RTLIB::UDIVREM_I16, "__aeabi_uidivmod");
725 setLibcallName(RTLIB::UDIVREM_I32, "__aeabi_uidivmod");
726 setLibcallName(RTLIB::UDIVREM_I64, "__aeabi_uldivmod");
728 setLibcallCallingConv(RTLIB::SDIVREM_I8, CallingConv::ARM_AAPCS);
729 setLibcallCallingConv(RTLIB::SDIVREM_I16, CallingConv::ARM_AAPCS);
730 setLibcallCallingConv(RTLIB::SDIVREM_I32, CallingConv::ARM_AAPCS);
731 setLibcallCallingConv(RTLIB::SDIVREM_I64, CallingConv::ARM_AAPCS);
732 setLibcallCallingConv(RTLIB::UDIVREM_I8, CallingConv::ARM_AAPCS);
733 setLibcallCallingConv(RTLIB::UDIVREM_I16, CallingConv::ARM_AAPCS);
734 setLibcallCallingConv(RTLIB::UDIVREM_I32, CallingConv::ARM_AAPCS);
735 setLibcallCallingConv(RTLIB::UDIVREM_I64, CallingConv::ARM_AAPCS);
737 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
738 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
740 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
741 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
744 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
745 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
746 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
747 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
748 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
750 setOperationAction(ISD::TRAP, MVT::Other, Legal);
752 // Use the default implementation.
753 setOperationAction(ISD::VASTART, MVT::Other, Custom);
754 setOperationAction(ISD::VAARG, MVT::Other, Expand);
755 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
756 setOperationAction(ISD::VAEND, MVT::Other, Expand);
757 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
758 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
760 if (!Subtarget->isTargetMachO()) {
761 // Non-MachO platforms may return values in these registers via the
762 // personality function.
763 setExceptionPointerRegister(ARM::R0);
764 setExceptionSelectorRegister(ARM::R1);
767 if (Subtarget->getTargetTriple().isWindowsItaniumEnvironment())
768 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
770 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
772 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
773 // the default expansion. If we are targeting a single threaded system,
774 // then set them all for expand so we can lower them later into their
776 if (TM.Options.ThreadModel == ThreadModel::Single)
777 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
778 else if (Subtarget->hasAnyDataBarrier() && !Subtarget->isThumb1Only()) {
779 // ATOMIC_FENCE needs custom lowering; the others should have been expanded
780 // to ldrex/strex loops already.
781 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
783 // On v8, we have particularly efficient implementations of atomic fences
784 // if they can be combined with nearby atomic loads and stores.
785 if (!Subtarget->hasV8Ops()) {
786 // Automatically insert fences (dmb ish) around ATOMIC_SWAP etc.
787 setInsertFencesForAtomic(true);
790 // If there's anything we can use as a barrier, go through custom lowering
792 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other,
793 Subtarget->hasAnyDataBarrier() ? Custom : Expand);
795 // Set them all for expansion, which will force libcalls.
796 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
797 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
798 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
799 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
800 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
801 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
802 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
803 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
804 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
805 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
806 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
807 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
808 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the
809 // Unordered/Monotonic case.
810 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
811 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
814 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
816 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
817 if (!Subtarget->hasV6Ops()) {
818 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
819 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
821 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
823 if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
824 !Subtarget->isThumb1Only()) {
825 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
826 // iff target supports vfp2.
827 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
828 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
831 // We want to custom lower some of our intrinsics.
832 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
833 if (Subtarget->isTargetDarwin()) {
834 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
835 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
836 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
839 setOperationAction(ISD::SETCC, MVT::i32, Expand);
840 setOperationAction(ISD::SETCC, MVT::f32, Expand);
841 setOperationAction(ISD::SETCC, MVT::f64, Expand);
842 setOperationAction(ISD::SELECT, MVT::i32, Custom);
843 setOperationAction(ISD::SELECT, MVT::f32, Custom);
844 setOperationAction(ISD::SELECT, MVT::f64, Custom);
845 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
846 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
847 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
849 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
850 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
851 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
852 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
853 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
855 // We don't support sin/cos/fmod/copysign/pow
856 setOperationAction(ISD::FSIN, MVT::f64, Expand);
857 setOperationAction(ISD::FSIN, MVT::f32, Expand);
858 setOperationAction(ISD::FCOS, MVT::f32, Expand);
859 setOperationAction(ISD::FCOS, MVT::f64, Expand);
860 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
861 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
862 setOperationAction(ISD::FREM, MVT::f64, Expand);
863 setOperationAction(ISD::FREM, MVT::f32, Expand);
864 if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
865 !Subtarget->isThumb1Only()) {
866 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
867 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
869 setOperationAction(ISD::FPOW, MVT::f64, Expand);
870 setOperationAction(ISD::FPOW, MVT::f32, Expand);
872 if (!Subtarget->hasVFP4()) {
873 setOperationAction(ISD::FMA, MVT::f64, Expand);
874 setOperationAction(ISD::FMA, MVT::f32, Expand);
877 // Various VFP goodness
878 if (!TM.Options.UseSoftFloat && !Subtarget->isThumb1Only()) {
879 // FP-ARMv8 adds f64 <-> f16 conversion. Before that it should be expanded.
880 if (!Subtarget->hasFPARMv8() || Subtarget->isFPOnlySP()) {
881 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
882 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
885 // fp16 is a special v7 extension that adds f16 <-> f32 conversions.
886 if (!Subtarget->hasFP16()) {
887 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
888 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
892 // Combine sin / cos into one node or libcall if possible.
893 if (Subtarget->hasSinCos()) {
894 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
895 setLibcallName(RTLIB::SINCOS_F64, "sincos");
896 if (Subtarget->getTargetTriple().isiOS()) {
897 // For iOS, we don't want to the normal expansion of a libcall to
898 // sincos. We want to issue a libcall to __sincos_stret.
899 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
900 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
904 // FP-ARMv8 implements a lot of rounding-like FP operations.
905 if (Subtarget->hasFPARMv8()) {
906 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
907 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
908 setOperationAction(ISD::FROUND, MVT::f32, Legal);
909 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
910 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
911 setOperationAction(ISD::FRINT, MVT::f32, Legal);
912 if (!Subtarget->isFPOnlySP()) {
913 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
914 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
915 setOperationAction(ISD::FROUND, MVT::f64, Legal);
916 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
917 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
918 setOperationAction(ISD::FRINT, MVT::f64, Legal);
921 // We have target-specific dag combine patterns for the following nodes:
922 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
923 setTargetDAGCombine(ISD::ADD);
924 setTargetDAGCombine(ISD::SUB);
925 setTargetDAGCombine(ISD::MUL);
926 setTargetDAGCombine(ISD::AND);
927 setTargetDAGCombine(ISD::OR);
928 setTargetDAGCombine(ISD::XOR);
930 if (Subtarget->hasV6Ops())
931 setTargetDAGCombine(ISD::SRL);
933 setStackPointerRegisterToSaveRestore(ARM::SP);
935 if (TM.Options.UseSoftFloat || Subtarget->isThumb1Only() ||
936 !Subtarget->hasVFP2())
937 setSchedulingPreference(Sched::RegPressure);
939 setSchedulingPreference(Sched::Hybrid);
941 //// temporary - rewrite interface to use type
942 MaxStoresPerMemset = 8;
943 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
944 MaxStoresPerMemcpy = 4; // For @llvm.memcpy -> sequence of stores
945 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 4 : 2;
946 MaxStoresPerMemmove = 4; // For @llvm.memmove -> sequence of stores
947 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 4 : 2;
949 // On ARM arguments smaller than 4 bytes are extended, so all arguments
950 // are at least 4 bytes aligned.
951 setMinStackArgumentAlignment(4);
953 // Prefer likely predicted branches to selects on out-of-order cores.
954 PredictableSelectIsExpensive = Subtarget->isLikeA9();
956 setMinFunctionAlignment(Subtarget->isThumb() ? 1 : 2);
959 // FIXME: It might make sense to define the representative register class as the
960 // nearest super-register that has a non-null superset. For example, DPR_VFP2 is
961 // a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
962 // SPR's representative would be DPR_VFP2. This should work well if register
963 // pressure tracking were modified such that a register use would increment the
964 // pressure of the register class's representative and all of it's super
965 // classes' representatives transitively. We have not implemented this because
966 // of the difficulty prior to coalescing of modeling operand register classes
967 // due to the common occurrence of cross class copies and subregister insertions
969 std::pair<const TargetRegisterClass *, uint8_t>
970 ARMTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
972 const TargetRegisterClass *RRC = nullptr;
974 switch (VT.SimpleTy) {
976 return TargetLowering::findRepresentativeClass(TRI, VT);
977 // Use DPR as representative register class for all floating point
978 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
979 // the cost is 1 for both f32 and f64.
980 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
981 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
982 RRC = &ARM::DPRRegClass;
983 // When NEON is used for SP, only half of the register file is available
984 // because operations that define both SP and DP results will be constrained
985 // to the VFP2 class (D0-D15). We currently model this constraint prior to
986 // coalescing by double-counting the SP regs. See the FIXME above.
987 if (Subtarget->useNEONForSinglePrecisionFP())
990 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
991 case MVT::v4f32: case MVT::v2f64:
992 RRC = &ARM::DPRRegClass;
996 RRC = &ARM::DPRRegClass;
1000 RRC = &ARM::DPRRegClass;
1004 return std::make_pair(RRC, Cost);
1007 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
1009 default: return nullptr;
1010 case ARMISD::Wrapper: return "ARMISD::Wrapper";
1011 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
1012 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
1013 case ARMISD::CALL: return "ARMISD::CALL";
1014 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
1015 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
1016 case ARMISD::tCALL: return "ARMISD::tCALL";
1017 case ARMISD::BRCOND: return "ARMISD::BRCOND";
1018 case ARMISD::BR_JT: return "ARMISD::BR_JT";
1019 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
1020 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
1021 case ARMISD::INTRET_FLAG: return "ARMISD::INTRET_FLAG";
1022 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
1023 case ARMISD::CMP: return "ARMISD::CMP";
1024 case ARMISD::CMN: return "ARMISD::CMN";
1025 case ARMISD::CMPZ: return "ARMISD::CMPZ";
1026 case ARMISD::CMPFP: return "ARMISD::CMPFP";
1027 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
1028 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
1029 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
1031 case ARMISD::CMOV: return "ARMISD::CMOV";
1033 case ARMISD::RBIT: return "ARMISD::RBIT";
1035 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
1036 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
1037 case ARMISD::RRX: return "ARMISD::RRX";
1039 case ARMISD::ADDC: return "ARMISD::ADDC";
1040 case ARMISD::ADDE: return "ARMISD::ADDE";
1041 case ARMISD::SUBC: return "ARMISD::SUBC";
1042 case ARMISD::SUBE: return "ARMISD::SUBE";
1044 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
1045 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
1047 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
1048 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
1050 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
1052 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
1054 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
1056 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
1058 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
1060 case ARMISD::WIN__CHKSTK: return "ARMISD:::WIN__CHKSTK";
1062 case ARMISD::VCEQ: return "ARMISD::VCEQ";
1063 case ARMISD::VCEQZ: return "ARMISD::VCEQZ";
1064 case ARMISD::VCGE: return "ARMISD::VCGE";
1065 case ARMISD::VCGEZ: return "ARMISD::VCGEZ";
1066 case ARMISD::VCLEZ: return "ARMISD::VCLEZ";
1067 case ARMISD::VCGEU: return "ARMISD::VCGEU";
1068 case ARMISD::VCGT: return "ARMISD::VCGT";
1069 case ARMISD::VCGTZ: return "ARMISD::VCGTZ";
1070 case ARMISD::VCLTZ: return "ARMISD::VCLTZ";
1071 case ARMISD::VCGTU: return "ARMISD::VCGTU";
1072 case ARMISD::VTST: return "ARMISD::VTST";
1074 case ARMISD::VSHL: return "ARMISD::VSHL";
1075 case ARMISD::VSHRs: return "ARMISD::VSHRs";
1076 case ARMISD::VSHRu: return "ARMISD::VSHRu";
1077 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
1078 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
1079 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
1080 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
1081 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
1082 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
1083 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
1084 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
1085 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
1086 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
1087 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
1088 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
1089 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
1090 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
1091 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
1092 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
1093 case ARMISD::VMOVFPIMM: return "ARMISD::VMOVFPIMM";
1094 case ARMISD::VDUP: return "ARMISD::VDUP";
1095 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
1096 case ARMISD::VEXT: return "ARMISD::VEXT";
1097 case ARMISD::VREV64: return "ARMISD::VREV64";
1098 case ARMISD::VREV32: return "ARMISD::VREV32";
1099 case ARMISD::VREV16: return "ARMISD::VREV16";
1100 case ARMISD::VZIP: return "ARMISD::VZIP";
1101 case ARMISD::VUZP: return "ARMISD::VUZP";
1102 case ARMISD::VTRN: return "ARMISD::VTRN";
1103 case ARMISD::VTBL1: return "ARMISD::VTBL1";
1104 case ARMISD::VTBL2: return "ARMISD::VTBL2";
1105 case ARMISD::VMULLs: return "ARMISD::VMULLs";
1106 case ARMISD::VMULLu: return "ARMISD::VMULLu";
1107 case ARMISD::UMLAL: return "ARMISD::UMLAL";
1108 case ARMISD::SMLAL: return "ARMISD::SMLAL";
1109 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
1110 case ARMISD::FMAX: return "ARMISD::FMAX";
1111 case ARMISD::FMIN: return "ARMISD::FMIN";
1112 case ARMISD::VMAXNM: return "ARMISD::VMAX";
1113 case ARMISD::VMINNM: return "ARMISD::VMIN";
1114 case ARMISD::BFI: return "ARMISD::BFI";
1115 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
1116 case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
1117 case ARMISD::VBSL: return "ARMISD::VBSL";
1118 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
1119 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
1120 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
1121 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD";
1122 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD";
1123 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD";
1124 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD";
1125 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD";
1126 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD";
1127 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD";
1128 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD";
1129 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD";
1130 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD";
1131 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD";
1132 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD";
1133 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD";
1134 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD";
1135 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD";
1136 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD";
1137 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD";
1141 EVT ARMTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1142 if (!VT.isVector()) return getPointerTy();
1143 return VT.changeVectorElementTypeToInteger();
1146 /// getRegClassFor - Return the register class that should be used for the
1147 /// specified value type.
1148 const TargetRegisterClass *ARMTargetLowering::getRegClassFor(MVT VT) const {
1149 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
1150 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
1151 // load / store 4 to 8 consecutive D registers.
1152 if (Subtarget->hasNEON()) {
1153 if (VT == MVT::v4i64)
1154 return &ARM::QQPRRegClass;
1155 if (VT == MVT::v8i64)
1156 return &ARM::QQQQPRRegClass;
1158 return TargetLowering::getRegClassFor(VT);
1161 // memcpy, and other memory intrinsics, typically tries to use LDM/STM if the
1162 // source/dest is aligned and the copy size is large enough. We therefore want
1163 // to align such objects passed to memory intrinsics.
1164 bool ARMTargetLowering::shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
1165 unsigned &PrefAlign) const {
1166 if (!isa<MemIntrinsic>(CI))
1169 // On ARM11 onwards (excluding M class) 8-byte aligned LDM is typically 1
1170 // cycle faster than 4-byte aligned LDM.
1171 PrefAlign = (Subtarget->hasV6Ops() && !Subtarget->isMClass() ? 8 : 4);
1175 // Create a fast isel object.
1177 ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
1178 const TargetLibraryInfo *libInfo) const {
1179 return ARM::createFastISel(funcInfo, libInfo);
1182 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
1183 unsigned NumVals = N->getNumValues();
1185 return Sched::RegPressure;
1187 for (unsigned i = 0; i != NumVals; ++i) {
1188 EVT VT = N->getValueType(i);
1189 if (VT == MVT::Glue || VT == MVT::Other)
1191 if (VT.isFloatingPoint() || VT.isVector())
1195 if (!N->isMachineOpcode())
1196 return Sched::RegPressure;
1198 // Load are scheduled for latency even if there instruction itinerary
1199 // is not available.
1200 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
1201 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1203 if (MCID.getNumDefs() == 0)
1204 return Sched::RegPressure;
1205 if (!Itins->isEmpty() &&
1206 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
1209 return Sched::RegPressure;
1212 //===----------------------------------------------------------------------===//
1214 //===----------------------------------------------------------------------===//
1216 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
1217 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
1219 default: llvm_unreachable("Unknown condition code!");
1220 case ISD::SETNE: return ARMCC::NE;
1221 case ISD::SETEQ: return ARMCC::EQ;
1222 case ISD::SETGT: return ARMCC::GT;
1223 case ISD::SETGE: return ARMCC::GE;
1224 case ISD::SETLT: return ARMCC::LT;
1225 case ISD::SETLE: return ARMCC::LE;
1226 case ISD::SETUGT: return ARMCC::HI;
1227 case ISD::SETUGE: return ARMCC::HS;
1228 case ISD::SETULT: return ARMCC::LO;
1229 case ISD::SETULE: return ARMCC::LS;
1233 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
1234 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
1235 ARMCC::CondCodes &CondCode2) {
1236 CondCode2 = ARMCC::AL;
1238 default: llvm_unreachable("Unknown FP condition!");
1240 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
1242 case ISD::SETOGT: CondCode = ARMCC::GT; break;
1244 case ISD::SETOGE: CondCode = ARMCC::GE; break;
1245 case ISD::SETOLT: CondCode = ARMCC::MI; break;
1246 case ISD::SETOLE: CondCode = ARMCC::LS; break;
1247 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
1248 case ISD::SETO: CondCode = ARMCC::VC; break;
1249 case ISD::SETUO: CondCode = ARMCC::VS; break;
1250 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
1251 case ISD::SETUGT: CondCode = ARMCC::HI; break;
1252 case ISD::SETUGE: CondCode = ARMCC::PL; break;
1254 case ISD::SETULT: CondCode = ARMCC::LT; break;
1256 case ISD::SETULE: CondCode = ARMCC::LE; break;
1258 case ISD::SETUNE: CondCode = ARMCC::NE; break;
1262 //===----------------------------------------------------------------------===//
1263 // Calling Convention Implementation
1264 //===----------------------------------------------------------------------===//
1266 #include "ARMGenCallingConv.inc"
1268 /// getEffectiveCallingConv - Get the effective calling convention, taking into
1269 /// account presence of floating point hardware and calling convention
1270 /// limitations, such as support for variadic functions.
1272 ARMTargetLowering::getEffectiveCallingConv(CallingConv::ID CC,
1273 bool isVarArg) const {
1276 llvm_unreachable("Unsupported calling convention");
1277 case CallingConv::ARM_AAPCS:
1278 case CallingConv::ARM_APCS:
1279 case CallingConv::GHC:
1281 case CallingConv::ARM_AAPCS_VFP:
1282 return isVarArg ? CallingConv::ARM_AAPCS : CallingConv::ARM_AAPCS_VFP;
1283 case CallingConv::C:
1284 if (!Subtarget->isAAPCS_ABI())
1285 return CallingConv::ARM_APCS;
1286 else if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() &&
1287 getTargetMachine().Options.FloatABIType == FloatABI::Hard &&
1289 return CallingConv::ARM_AAPCS_VFP;
1291 return CallingConv::ARM_AAPCS;
1292 case CallingConv::Fast:
1293 if (!Subtarget->isAAPCS_ABI()) {
1294 if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() && !isVarArg)
1295 return CallingConv::Fast;
1296 return CallingConv::ARM_APCS;
1297 } else if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() && !isVarArg)
1298 return CallingConv::ARM_AAPCS_VFP;
1300 return CallingConv::ARM_AAPCS;
1304 /// CCAssignFnForNode - Selects the correct CCAssignFn for the given
1305 /// CallingConvention.
1306 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
1308 bool isVarArg) const {
1309 switch (getEffectiveCallingConv(CC, isVarArg)) {
1311 llvm_unreachable("Unsupported calling convention");
1312 case CallingConv::ARM_APCS:
1313 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1314 case CallingConv::ARM_AAPCS:
1315 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1316 case CallingConv::ARM_AAPCS_VFP:
1317 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1318 case CallingConv::Fast:
1319 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1320 case CallingConv::GHC:
1321 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC);
1325 /// LowerCallResult - Lower the result values of a call into the
1326 /// appropriate copies out of appropriate physical registers.
1328 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1329 CallingConv::ID CallConv, bool isVarArg,
1330 const SmallVectorImpl<ISD::InputArg> &Ins,
1331 SDLoc dl, SelectionDAG &DAG,
1332 SmallVectorImpl<SDValue> &InVals,
1333 bool isThisReturn, SDValue ThisVal) const {
1335 // Assign locations to each value returned by this call.
1336 SmallVector<CCValAssign, 16> RVLocs;
1337 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1338 *DAG.getContext(), Call);
1339 CCInfo.AnalyzeCallResult(Ins,
1340 CCAssignFnForNode(CallConv, /* Return*/ true,
1343 // Copy all of the result registers out of their specified physreg.
1344 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1345 CCValAssign VA = RVLocs[i];
1347 // Pass 'this' value directly from the argument to return value, to avoid
1348 // reg unit interference
1349 if (i == 0 && isThisReturn) {
1350 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&
1351 "unexpected return calling convention register assignment");
1352 InVals.push_back(ThisVal);
1357 if (VA.needsCustom()) {
1358 // Handle f64 or half of a v2f64.
1359 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1361 Chain = Lo.getValue(1);
1362 InFlag = Lo.getValue(2);
1363 VA = RVLocs[++i]; // skip ahead to next loc
1364 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1366 Chain = Hi.getValue(1);
1367 InFlag = Hi.getValue(2);
1368 if (!Subtarget->isLittle())
1370 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1372 if (VA.getLocVT() == MVT::v2f64) {
1373 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1374 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1375 DAG.getConstant(0, dl, MVT::i32));
1377 VA = RVLocs[++i]; // skip ahead to next loc
1378 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1379 Chain = Lo.getValue(1);
1380 InFlag = Lo.getValue(2);
1381 VA = RVLocs[++i]; // skip ahead to next loc
1382 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1383 Chain = Hi.getValue(1);
1384 InFlag = Hi.getValue(2);
1385 if (!Subtarget->isLittle())
1387 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1388 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1389 DAG.getConstant(1, dl, MVT::i32));
1392 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1394 Chain = Val.getValue(1);
1395 InFlag = Val.getValue(2);
1398 switch (VA.getLocInfo()) {
1399 default: llvm_unreachable("Unknown loc info!");
1400 case CCValAssign::Full: break;
1401 case CCValAssign::BCvt:
1402 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1406 InVals.push_back(Val);
1412 /// LowerMemOpCallTo - Store the argument to the stack.
1414 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
1415 SDValue StackPtr, SDValue Arg,
1416 SDLoc dl, SelectionDAG &DAG,
1417 const CCValAssign &VA,
1418 ISD::ArgFlagsTy Flags) const {
1419 unsigned LocMemOffset = VA.getLocMemOffset();
1420 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
1421 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1422 return DAG.getStore(Chain, dl, Arg, PtrOff,
1423 MachinePointerInfo::getStack(LocMemOffset),
1427 void ARMTargetLowering::PassF64ArgInRegs(SDLoc dl, SelectionDAG &DAG,
1428 SDValue Chain, SDValue &Arg,
1429 RegsToPassVector &RegsToPass,
1430 CCValAssign &VA, CCValAssign &NextVA,
1432 SmallVectorImpl<SDValue> &MemOpChains,
1433 ISD::ArgFlagsTy Flags) const {
1435 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1436 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1437 unsigned id = Subtarget->isLittle() ? 0 : 1;
1438 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(id)));
1440 if (NextVA.isRegLoc())
1441 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1-id)));
1443 assert(NextVA.isMemLoc());
1444 if (!StackPtr.getNode())
1445 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1447 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1-id),
1453 /// LowerCall - Lowering a call into a callseq_start <-
1454 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1457 ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1458 SmallVectorImpl<SDValue> &InVals) const {
1459 SelectionDAG &DAG = CLI.DAG;
1461 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1462 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1463 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1464 SDValue Chain = CLI.Chain;
1465 SDValue Callee = CLI.Callee;
1466 bool &isTailCall = CLI.IsTailCall;
1467 CallingConv::ID CallConv = CLI.CallConv;
1468 bool doesNotRet = CLI.DoesNotReturn;
1469 bool isVarArg = CLI.IsVarArg;
1471 MachineFunction &MF = DAG.getMachineFunction();
1472 bool isStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1473 bool isThisReturn = false;
1474 bool isSibCall = false;
1476 // Disable tail calls if they're not supported.
1477 if (!Subtarget->supportsTailCall() || MF.getTarget().Options.DisableTailCalls)
1481 // Check if it's really possible to do a tail call.
1482 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1483 isVarArg, isStructRet, MF.getFunction()->hasStructRetAttr(),
1484 Outs, OutVals, Ins, DAG);
1485 if (!isTailCall && CLI.CS && CLI.CS->isMustTailCall())
1486 report_fatal_error("failed to perform tail call elimination on a call "
1487 "site marked musttail");
1488 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1489 // detected sibcalls.
1496 // Analyze operands of the call, assigning locations to each operand.
1497 SmallVector<CCValAssign, 16> ArgLocs;
1498 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1499 *DAG.getContext(), Call);
1500 CCInfo.AnalyzeCallOperands(Outs,
1501 CCAssignFnForNode(CallConv, /* Return*/ false,
1504 // Get a count of how many bytes are to be pushed on the stack.
1505 unsigned NumBytes = CCInfo.getNextStackOffset();
1507 // For tail calls, memory operands are available in our caller's stack.
1511 // Adjust the stack pointer for the new arguments...
1512 // These operations are automatically eliminated by the prolog/epilog pass
1514 Chain = DAG.getCALLSEQ_START(Chain,
1515 DAG.getIntPtrConstant(NumBytes, dl, true), dl);
1517 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1519 RegsToPassVector RegsToPass;
1520 SmallVector<SDValue, 8> MemOpChains;
1522 // Walk the register/memloc assignments, inserting copies/loads. In the case
1523 // of tail call optimization, arguments are handled later.
1524 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1526 ++i, ++realArgIdx) {
1527 CCValAssign &VA = ArgLocs[i];
1528 SDValue Arg = OutVals[realArgIdx];
1529 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1530 bool isByVal = Flags.isByVal();
1532 // Promote the value if needed.
1533 switch (VA.getLocInfo()) {
1534 default: llvm_unreachable("Unknown loc info!");
1535 case CCValAssign::Full: break;
1536 case CCValAssign::SExt:
1537 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1539 case CCValAssign::ZExt:
1540 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1542 case CCValAssign::AExt:
1543 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1545 case CCValAssign::BCvt:
1546 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1550 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1551 if (VA.needsCustom()) {
1552 if (VA.getLocVT() == MVT::v2f64) {
1553 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1554 DAG.getConstant(0, dl, MVT::i32));
1555 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1556 DAG.getConstant(1, dl, MVT::i32));
1558 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1559 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1561 VA = ArgLocs[++i]; // skip ahead to next loc
1562 if (VA.isRegLoc()) {
1563 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1564 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1566 assert(VA.isMemLoc());
1568 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1569 dl, DAG, VA, Flags));
1572 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1573 StackPtr, MemOpChains, Flags);
1575 } else if (VA.isRegLoc()) {
1576 if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i32) {
1577 assert(VA.getLocVT() == MVT::i32 &&
1578 "unexpected calling convention register assignment");
1579 assert(!Ins.empty() && Ins[0].VT == MVT::i32 &&
1580 "unexpected use of 'returned'");
1581 isThisReturn = true;
1583 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1584 } else if (isByVal) {
1585 assert(VA.isMemLoc());
1586 unsigned offset = 0;
1588 // True if this byval aggregate will be split between registers
1590 unsigned ByValArgsCount = CCInfo.getInRegsParamsCount();
1591 unsigned CurByValIdx = CCInfo.getInRegsParamsProcessed();
1593 if (CurByValIdx < ByValArgsCount) {
1595 unsigned RegBegin, RegEnd;
1596 CCInfo.getInRegsParamInfo(CurByValIdx, RegBegin, RegEnd);
1598 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1600 for (i = 0, j = RegBegin; j < RegEnd; i++, j++) {
1601 SDValue Const = DAG.getConstant(4*i, dl, MVT::i32);
1602 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
1603 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
1604 MachinePointerInfo(),
1605 false, false, false,
1606 DAG.InferPtrAlignment(AddArg));
1607 MemOpChains.push_back(Load.getValue(1));
1608 RegsToPass.push_back(std::make_pair(j, Load));
1611 // If parameter size outsides register area, "offset" value
1612 // helps us to calculate stack slot for remained part properly.
1613 offset = RegEnd - RegBegin;
1615 CCInfo.nextInRegsParam();
1618 if (Flags.getByValSize() > 4*offset) {
1619 unsigned LocMemOffset = VA.getLocMemOffset();
1620 SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
1621 SDValue Dst = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr,
1623 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset, dl);
1624 SDValue Src = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg, SrcOffset);
1625 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset, dl,
1627 SDValue AlignNode = DAG.getConstant(Flags.getByValAlign(), dl,
1630 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
1631 SDValue Ops[] = { Chain, Dst, Src, SizeNode, AlignNode};
1632 MemOpChains.push_back(DAG.getNode(ARMISD::COPY_STRUCT_BYVAL, dl, VTs,
1635 } else if (!isSibCall) {
1636 assert(VA.isMemLoc());
1638 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1639 dl, DAG, VA, Flags));
1643 if (!MemOpChains.empty())
1644 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
1646 // Build a sequence of copy-to-reg nodes chained together with token chain
1647 // and flag operands which copy the outgoing args into the appropriate regs.
1649 // Tail call byval lowering might overwrite argument registers so in case of
1650 // tail call optimization the copies to registers are lowered later.
1652 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1653 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1654 RegsToPass[i].second, InFlag);
1655 InFlag = Chain.getValue(1);
1658 // For tail calls lower the arguments to the 'real' stack slot.
1660 // Force all the incoming stack arguments to be loaded from the stack
1661 // before any new outgoing arguments are stored to the stack, because the
1662 // outgoing stack slots may alias the incoming argument stack slots, and
1663 // the alias isn't otherwise explicit. This is slightly more conservative
1664 // than necessary, because it means that each store effectively depends
1665 // on every argument instead of just those arguments it would clobber.
1667 // Do not flag preceding copytoreg stuff together with the following stuff.
1669 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1670 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1671 RegsToPass[i].second, InFlag);
1672 InFlag = Chain.getValue(1);
1677 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1678 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1679 // node so that legalize doesn't hack it.
1680 bool isDirect = false;
1681 bool isARMFunc = false;
1682 bool isLocalARMFunc = false;
1683 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1685 if (EnableARMLongCalls) {
1686 assert((Subtarget->isTargetWindows() ||
1687 getTargetMachine().getRelocationModel() == Reloc::Static) &&
1688 "long-calls with non-static relocation model!");
1689 // Handle a global address or an external symbol. If it's not one of
1690 // those, the target's already in a register, so we don't need to do
1692 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1693 const GlobalValue *GV = G->getGlobal();
1694 // Create a constant pool entry for the callee address
1695 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1696 ARMConstantPoolValue *CPV =
1697 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0);
1699 // Get the address of the callee into a register
1700 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1701 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1702 Callee = DAG.getLoad(getPointerTy(), dl,
1703 DAG.getEntryNode(), CPAddr,
1704 MachinePointerInfo::getConstantPool(),
1705 false, false, false, 0);
1706 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1707 const char *Sym = S->getSymbol();
1709 // Create a constant pool entry for the callee address
1710 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1711 ARMConstantPoolValue *CPV =
1712 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
1713 ARMPCLabelIndex, 0);
1714 // Get the address of the callee into a register
1715 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1716 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1717 Callee = DAG.getLoad(getPointerTy(), dl,
1718 DAG.getEntryNode(), CPAddr,
1719 MachinePointerInfo::getConstantPool(),
1720 false, false, false, 0);
1722 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1723 const GlobalValue *GV = G->getGlobal();
1725 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1726 bool isStub = (isExt && Subtarget->isTargetMachO()) &&
1727 getTargetMachine().getRelocationModel() != Reloc::Static;
1728 isARMFunc = !Subtarget->isThumb() || (isStub && !Subtarget->isMClass());
1729 // ARM call to a local ARM function is predicable.
1730 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
1731 // tBX takes a register source operand.
1732 if (isStub && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1733 assert(Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?");
1734 Callee = DAG.getNode(ARMISD::WrapperPIC, dl, getPointerTy(),
1735 DAG.getTargetGlobalAddress(GV, dl, getPointerTy(),
1736 0, ARMII::MO_NONLAZY));
1737 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee,
1738 MachinePointerInfo::getGOT(), false, false, true, 0);
1739 } else if (Subtarget->isTargetCOFF()) {
1740 assert(Subtarget->isTargetWindows() &&
1741 "Windows is the only supported COFF target");
1742 unsigned TargetFlags = GV->hasDLLImportStorageClass()
1743 ? ARMII::MO_DLLIMPORT
1744 : ARMII::MO_NO_FLAG;
1745 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), /*Offset=*/0,
1747 if (GV->hasDLLImportStorageClass())
1748 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
1749 DAG.getNode(ARMISD::Wrapper, dl, getPointerTy(),
1750 Callee), MachinePointerInfo::getGOT(),
1751 false, false, false, 0);
1753 // On ELF targets for PIC code, direct calls should go through the PLT
1754 unsigned OpFlags = 0;
1755 if (Subtarget->isTargetELF() &&
1756 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1757 OpFlags = ARMII::MO_PLT;
1758 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
1760 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1762 bool isStub = Subtarget->isTargetMachO() &&
1763 getTargetMachine().getRelocationModel() != Reloc::Static;
1764 isARMFunc = !Subtarget->isThumb() || (isStub && !Subtarget->isMClass());
1765 // tBX takes a register source operand.
1766 const char *Sym = S->getSymbol();
1767 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1768 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1769 ARMConstantPoolValue *CPV =
1770 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
1771 ARMPCLabelIndex, 4);
1772 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1773 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1774 Callee = DAG.getLoad(getPointerTy(), dl,
1775 DAG.getEntryNode(), CPAddr,
1776 MachinePointerInfo::getConstantPool(),
1777 false, false, false, 0);
1778 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
1779 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1780 getPointerTy(), Callee, PICLabel);
1782 unsigned OpFlags = 0;
1783 // On ELF targets for PIC code, direct calls should go through the PLT
1784 if (Subtarget->isTargetELF() &&
1785 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1786 OpFlags = ARMII::MO_PLT;
1787 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags);
1791 // FIXME: handle tail calls differently.
1793 bool HasMinSizeAttr = MF.getFunction()->hasFnAttribute(Attribute::MinSize);
1794 if (Subtarget->isThumb()) {
1795 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1796 CallOpc = ARMISD::CALL_NOLINK;
1798 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1800 if (!isDirect && !Subtarget->hasV5TOps())
1801 CallOpc = ARMISD::CALL_NOLINK;
1802 else if (doesNotRet && isDirect && Subtarget->hasRAS() &&
1803 // Emit regular call when code size is the priority
1805 // "mov lr, pc; b _foo" to avoid confusing the RSP
1806 CallOpc = ARMISD::CALL_NOLINK;
1808 CallOpc = isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL;
1811 std::vector<SDValue> Ops;
1812 Ops.push_back(Chain);
1813 Ops.push_back(Callee);
1815 // Add argument registers to the end of the list so that they are known live
1817 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1818 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1819 RegsToPass[i].second.getValueType()));
1821 // Add a register mask operand representing the call-preserved registers.
1823 const uint32_t *Mask;
1824 const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo();
1826 // For 'this' returns, use the R0-preserving mask if applicable
1827 Mask = ARI->getThisReturnPreservedMask(MF, CallConv);
1829 // Set isThisReturn to false if the calling convention is not one that
1830 // allows 'returned' to be modeled in this way, so LowerCallResult does
1831 // not try to pass 'this' straight through
1832 isThisReturn = false;
1833 Mask = ARI->getCallPreservedMask(MF, CallConv);
1836 Mask = ARI->getCallPreservedMask(MF, CallConv);
1838 assert(Mask && "Missing call preserved mask for calling convention");
1839 Ops.push_back(DAG.getRegisterMask(Mask));
1842 if (InFlag.getNode())
1843 Ops.push_back(InFlag);
1845 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1847 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, Ops);
1849 // Returns a chain and a flag for retval copy to use.
1850 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
1851 InFlag = Chain.getValue(1);
1853 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
1854 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
1856 InFlag = Chain.getValue(1);
1858 // Handle result values, copying them out of physregs into vregs that we
1860 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
1861 InVals, isThisReturn,
1862 isThisReturn ? OutVals[0] : SDValue());
1865 /// HandleByVal - Every parameter *after* a byval parameter is passed
1866 /// on the stack. Remember the next parameter register to allocate,
1867 /// and then confiscate the rest of the parameter registers to insure
1869 void ARMTargetLowering::HandleByVal(CCState *State, unsigned &Size,
1870 unsigned Align) const {
1871 assert((State->getCallOrPrologue() == Prologue ||
1872 State->getCallOrPrologue() == Call) &&
1873 "unhandled ParmContext");
1875 // Byval (as with any stack) slots are always at least 4 byte aligned.
1876 Align = std::max(Align, 4U);
1878 unsigned Reg = State->AllocateReg(GPRArgRegs);
1882 unsigned AlignInRegs = Align / 4;
1883 unsigned Waste = (ARM::R4 - Reg) % AlignInRegs;
1884 for (unsigned i = 0; i < Waste; ++i)
1885 Reg = State->AllocateReg(GPRArgRegs);
1890 unsigned Excess = 4 * (ARM::R4 - Reg);
1892 // Special case when NSAA != SP and parameter size greater than size of
1893 // all remained GPR regs. In that case we can't split parameter, we must
1894 // send it to stack. We also must set NCRN to R4, so waste all
1895 // remained registers.
1896 const unsigned NSAAOffset = State->getNextStackOffset();
1897 if (NSAAOffset != 0 && Size > Excess) {
1898 while (State->AllocateReg(GPRArgRegs))
1903 // First register for byval parameter is the first register that wasn't
1904 // allocated before this method call, so it would be "reg".
1905 // If parameter is small enough to be saved in range [reg, r4), then
1906 // the end (first after last) register would be reg + param-size-in-regs,
1907 // else parameter would be splitted between registers and stack,
1908 // end register would be r4 in this case.
1909 unsigned ByValRegBegin = Reg;
1910 unsigned ByValRegEnd = std::min<unsigned>(Reg + Size / 4, ARM::R4);
1911 State->addInRegsParamInfo(ByValRegBegin, ByValRegEnd);
1912 // Note, first register is allocated in the beginning of function already,
1913 // allocate remained amount of registers we need.
1914 for (unsigned i = Reg + 1; i != ByValRegEnd; ++i)
1915 State->AllocateReg(GPRArgRegs);
1916 // A byval parameter that is split between registers and memory needs its
1917 // size truncated here.
1918 // In the case where the entire structure fits in registers, we set the
1919 // size in memory to zero.
1920 Size = std::max<int>(Size - Excess, 0);
1924 /// MatchingStackOffset - Return true if the given stack call argument is
1925 /// already available in the same position (relatively) of the caller's
1926 /// incoming argument stack.
1928 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1929 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1930 const TargetInstrInfo *TII) {
1931 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
1933 if (Arg.getOpcode() == ISD::CopyFromReg) {
1934 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
1935 if (!TargetRegisterInfo::isVirtualRegister(VR))
1937 MachineInstr *Def = MRI->getVRegDef(VR);
1940 if (!Flags.isByVal()) {
1941 if (!TII->isLoadFromStackSlot(Def, FI))
1946 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
1947 if (Flags.isByVal())
1948 // ByVal argument is passed in as a pointer but it's now being
1949 // dereferenced. e.g.
1950 // define @foo(%struct.X* %A) {
1951 // tail call @bar(%struct.X* byval %A)
1954 SDValue Ptr = Ld->getBasePtr();
1955 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
1958 FI = FINode->getIndex();
1962 assert(FI != INT_MAX);
1963 if (!MFI->isFixedObjectIndex(FI))
1965 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
1968 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1969 /// for tail call optimization. Targets which want to do tail call
1970 /// optimization should implement this function.
1972 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1973 CallingConv::ID CalleeCC,
1975 bool isCalleeStructRet,
1976 bool isCallerStructRet,
1977 const SmallVectorImpl<ISD::OutputArg> &Outs,
1978 const SmallVectorImpl<SDValue> &OutVals,
1979 const SmallVectorImpl<ISD::InputArg> &Ins,
1980 SelectionDAG& DAG) const {
1981 const Function *CallerF = DAG.getMachineFunction().getFunction();
1982 CallingConv::ID CallerCC = CallerF->getCallingConv();
1983 bool CCMatch = CallerCC == CalleeCC;
1985 // Look for obvious safe cases to perform tail call optimization that do not
1986 // require ABI changes. This is what gcc calls sibcall.
1988 // Do not sibcall optimize vararg calls unless the call site is not passing
1990 if (isVarArg && !Outs.empty())
1993 // Exception-handling functions need a special set of instructions to indicate
1994 // a return to the hardware. Tail-calling another function would probably
1996 if (CallerF->hasFnAttribute("interrupt"))
1999 // Also avoid sibcall optimization if either caller or callee uses struct
2000 // return semantics.
2001 if (isCalleeStructRet || isCallerStructRet)
2004 // FIXME: Completely disable sibcall for Thumb1 since ThumbRegisterInfo::
2005 // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
2006 // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
2007 // support in the assembler and linker to be used. This would need to be
2008 // fixed to fully support tail calls in Thumb1.
2010 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
2011 // LR. This means if we need to reload LR, it takes an extra instructions,
2012 // which outweighs the value of the tail call; but here we don't know yet
2013 // whether LR is going to be used. Probably the right approach is to
2014 // generate the tail call here and turn it back into CALL/RET in
2015 // emitEpilogue if LR is used.
2017 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
2018 // but we need to make sure there are enough registers; the only valid
2019 // registers are the 4 used for parameters. We don't currently do this
2021 if (Subtarget->isThumb1Only())
2024 // Externally-defined functions with weak linkage should not be
2025 // tail-called on ARM when the OS does not support dynamic
2026 // pre-emption of symbols, as the AAELF spec requires normal calls
2027 // to undefined weak functions to be replaced with a NOP or jump to the
2028 // next instruction. The behaviour of branch instructions in this
2029 // situation (as used for tail calls) is implementation-defined, so we
2030 // cannot rely on the linker replacing the tail call with a return.
2031 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2032 const GlobalValue *GV = G->getGlobal();
2033 const Triple TT(getTargetMachine().getTargetTriple());
2034 if (GV->hasExternalWeakLinkage() &&
2035 (!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
2039 // If the calling conventions do not match, then we'd better make sure the
2040 // results are returned in the same way as what the caller expects.
2042 SmallVector<CCValAssign, 16> RVLocs1;
2043 ARMCCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
2044 *DAG.getContext(), Call);
2045 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
2047 SmallVector<CCValAssign, 16> RVLocs2;
2048 ARMCCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
2049 *DAG.getContext(), Call);
2050 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
2052 if (RVLocs1.size() != RVLocs2.size())
2054 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2055 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2057 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2059 if (RVLocs1[i].isRegLoc()) {
2060 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2063 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2069 // If Caller's vararg or byval argument has been split between registers and
2070 // stack, do not perform tail call, since part of the argument is in caller's
2072 const ARMFunctionInfo *AFI_Caller = DAG.getMachineFunction().
2073 getInfo<ARMFunctionInfo>();
2074 if (AFI_Caller->getArgRegsSaveSize())
2077 // If the callee takes no arguments then go on to check the results of the
2079 if (!Outs.empty()) {
2080 // Check if stack adjustment is needed. For now, do not do this if any
2081 // argument is passed on the stack.
2082 SmallVector<CCValAssign, 16> ArgLocs;
2083 ARMCCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2084 *DAG.getContext(), Call);
2085 CCInfo.AnalyzeCallOperands(Outs,
2086 CCAssignFnForNode(CalleeCC, false, isVarArg));
2087 if (CCInfo.getNextStackOffset()) {
2088 MachineFunction &MF = DAG.getMachineFunction();
2090 // Check if the arguments are already laid out in the right way as
2091 // the caller's fixed stack objects.
2092 MachineFrameInfo *MFI = MF.getFrameInfo();
2093 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2094 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
2095 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
2097 ++i, ++realArgIdx) {
2098 CCValAssign &VA = ArgLocs[i];
2099 EVT RegVT = VA.getLocVT();
2100 SDValue Arg = OutVals[realArgIdx];
2101 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2102 if (VA.getLocInfo() == CCValAssign::Indirect)
2104 if (VA.needsCustom()) {
2105 // f64 and vector types are split into multiple registers or
2106 // register/stack-slot combinations. The types will not match
2107 // the registers; give up on memory f64 refs until we figure
2108 // out what to do about this.
2111 if (!ArgLocs[++i].isRegLoc())
2113 if (RegVT == MVT::v2f64) {
2114 if (!ArgLocs[++i].isRegLoc())
2116 if (!ArgLocs[++i].isRegLoc())
2119 } else if (!VA.isRegLoc()) {
2120 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2132 ARMTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
2133 MachineFunction &MF, bool isVarArg,
2134 const SmallVectorImpl<ISD::OutputArg> &Outs,
2135 LLVMContext &Context) const {
2136 SmallVector<CCValAssign, 16> RVLocs;
2137 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2138 return CCInfo.CheckReturn(Outs, CCAssignFnForNode(CallConv, /*Return=*/true,
2142 static SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
2143 SDLoc DL, SelectionDAG &DAG) {
2144 const MachineFunction &MF = DAG.getMachineFunction();
2145 const Function *F = MF.getFunction();
2147 StringRef IntKind = F->getFnAttribute("interrupt").getValueAsString();
2149 // See ARM ARM v7 B1.8.3. On exception entry LR is set to a possibly offset
2150 // version of the "preferred return address". These offsets affect the return
2151 // instruction if this is a return from PL1 without hypervisor extensions.
2152 // IRQ/FIQ: +4 "subs pc, lr, #4"
2153 // SWI: 0 "subs pc, lr, #0"
2154 // ABORT: +4 "subs pc, lr, #4"
2155 // UNDEF: +4/+2 "subs pc, lr, #0"
2156 // UNDEF varies depending on where the exception came from ARM or Thumb
2157 // mode. Alongside GCC, we throw our hands up in disgust and pretend it's 0.
2160 if (IntKind == "" || IntKind == "IRQ" || IntKind == "FIQ" ||
2163 else if (IntKind == "SWI" || IntKind == "UNDEF")
2166 report_fatal_error("Unsupported interrupt attribute. If present, value "
2167 "must be one of: IRQ, FIQ, SWI, ABORT or UNDEF");
2169 RetOps.insert(RetOps.begin() + 1,
2170 DAG.getConstant(LROffset, DL, MVT::i32, false));
2172 return DAG.getNode(ARMISD::INTRET_FLAG, DL, MVT::Other, RetOps);
2176 ARMTargetLowering::LowerReturn(SDValue Chain,
2177 CallingConv::ID CallConv, bool isVarArg,
2178 const SmallVectorImpl<ISD::OutputArg> &Outs,
2179 const SmallVectorImpl<SDValue> &OutVals,
2180 SDLoc dl, SelectionDAG &DAG) const {
2182 // CCValAssign - represent the assignment of the return value to a location.
2183 SmallVector<CCValAssign, 16> RVLocs;
2185 // CCState - Info about the registers and stack slots.
2186 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2187 *DAG.getContext(), Call);
2189 // Analyze outgoing return values.
2190 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
2194 SmallVector<SDValue, 4> RetOps;
2195 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2196 bool isLittleEndian = Subtarget->isLittle();
2198 MachineFunction &MF = DAG.getMachineFunction();
2199 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2200 AFI->setReturnRegsCount(RVLocs.size());
2202 // Copy the result values into the output registers.
2203 for (unsigned i = 0, realRVLocIdx = 0;
2205 ++i, ++realRVLocIdx) {
2206 CCValAssign &VA = RVLocs[i];
2207 assert(VA.isRegLoc() && "Can only return in registers!");
2209 SDValue Arg = OutVals[realRVLocIdx];
2211 switch (VA.getLocInfo()) {
2212 default: llvm_unreachable("Unknown loc info!");
2213 case CCValAssign::Full: break;
2214 case CCValAssign::BCvt:
2215 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2219 if (VA.needsCustom()) {
2220 if (VA.getLocVT() == MVT::v2f64) {
2221 // Extract the first half and return it in two registers.
2222 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2223 DAG.getConstant(0, dl, MVT::i32));
2224 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
2225 DAG.getVTList(MVT::i32, MVT::i32), Half);
2227 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2228 HalfGPRs.getValue(isLittleEndian ? 0 : 1),
2230 Flag = Chain.getValue(1);
2231 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2232 VA = RVLocs[++i]; // skip ahead to next loc
2233 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2234 HalfGPRs.getValue(isLittleEndian ? 1 : 0),
2236 Flag = Chain.getValue(1);
2237 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2238 VA = RVLocs[++i]; // skip ahead to next loc
2240 // Extract the 2nd half and fall through to handle it as an f64 value.
2241 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2242 DAG.getConstant(1, dl, MVT::i32));
2244 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
2246 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
2247 DAG.getVTList(MVT::i32, MVT::i32), Arg);
2248 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2249 fmrrd.getValue(isLittleEndian ? 0 : 1),
2251 Flag = Chain.getValue(1);
2252 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2253 VA = RVLocs[++i]; // skip ahead to next loc
2254 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2255 fmrrd.getValue(isLittleEndian ? 1 : 0),
2258 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
2260 // Guarantee that all emitted copies are
2261 // stuck together, avoiding something bad.
2262 Flag = Chain.getValue(1);
2263 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2266 // Update chain and glue.
2269 RetOps.push_back(Flag);
2271 // CPUs which aren't M-class use a special sequence to return from
2272 // exceptions (roughly, any instruction setting pc and cpsr simultaneously,
2273 // though we use "subs pc, lr, #N").
2275 // M-class CPUs actually use a normal return sequence with a special
2276 // (hardware-provided) value in LR, so the normal code path works.
2277 if (DAG.getMachineFunction().getFunction()->hasFnAttribute("interrupt") &&
2278 !Subtarget->isMClass()) {
2279 if (Subtarget->isThumb1Only())
2280 report_fatal_error("interrupt attribute is not supported in Thumb1");
2281 return LowerInterruptReturn(RetOps, dl, DAG);
2284 return DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, RetOps);
2287 bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2288 if (N->getNumValues() != 1)
2290 if (!N->hasNUsesOfValue(1, 0))
2293 SDValue TCChain = Chain;
2294 SDNode *Copy = *N->use_begin();
2295 if (Copy->getOpcode() == ISD::CopyToReg) {
2296 // If the copy has a glue operand, we conservatively assume it isn't safe to
2297 // perform a tail call.
2298 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2300 TCChain = Copy->getOperand(0);
2301 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) {
2302 SDNode *VMov = Copy;
2303 // f64 returned in a pair of GPRs.
2304 SmallPtrSet<SDNode*, 2> Copies;
2305 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2307 if (UI->getOpcode() != ISD::CopyToReg)
2311 if (Copies.size() > 2)
2314 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2316 SDValue UseChain = UI->getOperand(0);
2317 if (Copies.count(UseChain.getNode()))
2321 // We are at the top of this chain.
2322 // If the copy has a glue operand, we conservatively assume it
2323 // isn't safe to perform a tail call.
2324 if (UI->getOperand(UI->getNumOperands()-1).getValueType() == MVT::Glue)
2330 } else if (Copy->getOpcode() == ISD::BITCAST) {
2331 // f32 returned in a single GPR.
2332 if (!Copy->hasOneUse())
2334 Copy = *Copy->use_begin();
2335 if (Copy->getOpcode() != ISD::CopyToReg || !Copy->hasNUsesOfValue(1, 0))
2337 // If the copy has a glue operand, we conservatively assume it isn't safe to
2338 // perform a tail call.
2339 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2341 TCChain = Copy->getOperand(0);
2346 bool HasRet = false;
2347 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2349 if (UI->getOpcode() != ARMISD::RET_FLAG &&
2350 UI->getOpcode() != ARMISD::INTRET_FLAG)
2362 bool ARMTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2363 if (!Subtarget->supportsTailCall())
2366 if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2369 return !Subtarget->isThumb1Only();
2372 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
2373 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
2374 // one of the above mentioned nodes. It has to be wrapped because otherwise
2375 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
2376 // be used to form addressing mode. These wrapped nodes will be selected
2378 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
2379 EVT PtrVT = Op.getValueType();
2380 // FIXME there is no actual debug info here
2382 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2384 if (CP->isMachineConstantPoolEntry())
2385 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
2386 CP->getAlignment());
2388 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
2389 CP->getAlignment());
2390 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
2393 unsigned ARMTargetLowering::getJumpTableEncoding() const {
2394 return MachineJumpTableInfo::EK_Inline;
2397 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
2398 SelectionDAG &DAG) const {
2399 MachineFunction &MF = DAG.getMachineFunction();
2400 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2401 unsigned ARMPCLabelIndex = 0;
2403 EVT PtrVT = getPointerTy();
2404 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
2405 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2407 if (RelocM == Reloc::Static) {
2408 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
2410 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2411 ARMPCLabelIndex = AFI->createPICLabelUId();
2412 ARMConstantPoolValue *CPV =
2413 ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex,
2414 ARMCP::CPBlockAddress, PCAdj);
2415 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2417 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
2418 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
2419 MachinePointerInfo::getConstantPool(),
2420 false, false, false, 0);
2421 if (RelocM == Reloc::Static)
2423 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, DL, MVT::i32);
2424 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
2427 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
2429 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
2430 SelectionDAG &DAG) const {
2432 EVT PtrVT = getPointerTy();
2433 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2434 MachineFunction &MF = DAG.getMachineFunction();
2435 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2436 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2437 ARMConstantPoolValue *CPV =
2438 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2439 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
2440 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2441 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
2442 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
2443 MachinePointerInfo::getConstantPool(),
2444 false, false, false, 0);
2445 SDValue Chain = Argument.getValue(1);
2447 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2448 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
2450 // call __tls_get_addr.
2453 Entry.Node = Argument;
2454 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
2455 Args.push_back(Entry);
2457 // FIXME: is there useful debug info available here?
2458 TargetLowering::CallLoweringInfo CLI(DAG);
2459 CLI.setDebugLoc(dl).setChain(Chain)
2460 .setCallee(CallingConv::C, Type::getInt32Ty(*DAG.getContext()),
2461 DAG.getExternalSymbol("__tls_get_addr", PtrVT), std::move(Args),
2464 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2465 return CallResult.first;
2468 // Lower ISD::GlobalTLSAddress using the "initial exec" or
2469 // "local exec" model.
2471 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
2473 TLSModel::Model model) const {
2474 const GlobalValue *GV = GA->getGlobal();
2477 SDValue Chain = DAG.getEntryNode();
2478 EVT PtrVT = getPointerTy();
2479 // Get the Thread Pointer
2480 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2482 if (model == TLSModel::InitialExec) {
2483 MachineFunction &MF = DAG.getMachineFunction();
2484 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2485 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2486 // Initial exec model.
2487 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2488 ARMConstantPoolValue *CPV =
2489 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2490 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF,
2492 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2493 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2494 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2495 MachinePointerInfo::getConstantPool(),
2496 false, false, false, 0);
2497 Chain = Offset.getValue(1);
2499 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2500 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
2502 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2503 MachinePointerInfo::getConstantPool(),
2504 false, false, false, 0);
2507 assert(model == TLSModel::LocalExec);
2508 ARMConstantPoolValue *CPV =
2509 ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF);
2510 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2511 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2512 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2513 MachinePointerInfo::getConstantPool(),
2514 false, false, false, 0);
2517 // The address of the thread local variable is the add of the thread
2518 // pointer with the offset of the variable.
2519 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
2523 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
2524 // TODO: implement the "local dynamic" model
2525 assert(Subtarget->isTargetELF() &&
2526 "TLS not implemented for non-ELF targets");
2527 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2529 TLSModel::Model model = getTargetMachine().getTLSModel(GA->getGlobal());
2532 case TLSModel::GeneralDynamic:
2533 case TLSModel::LocalDynamic:
2534 return LowerToTLSGeneralDynamicModel(GA, DAG);
2535 case TLSModel::InitialExec:
2536 case TLSModel::LocalExec:
2537 return LowerToTLSExecModels(GA, DAG, model);
2539 llvm_unreachable("bogus TLS model");
2542 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
2543 SelectionDAG &DAG) const {
2544 EVT PtrVT = getPointerTy();
2546 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2547 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2548 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
2549 ARMConstantPoolValue *CPV =
2550 ARMConstantPoolConstant::Create(GV,
2551 UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
2552 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2553 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2554 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
2556 MachinePointerInfo::getConstantPool(),
2557 false, false, false, 0);
2558 SDValue Chain = Result.getValue(1);
2559 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
2560 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
2562 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
2563 MachinePointerInfo::getGOT(),
2564 false, false, false, 0);
2568 // If we have T2 ops, we can materialize the address directly via movt/movw
2569 // pair. This is always cheaper.
2570 if (Subtarget->useMovt(DAG.getMachineFunction())) {
2572 // FIXME: Once remat is capable of dealing with instructions with register
2573 // operands, expand this into two nodes.
2574 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2575 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2577 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
2578 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2579 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2580 MachinePointerInfo::getConstantPool(),
2581 false, false, false, 0);
2585 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
2586 SelectionDAG &DAG) const {
2587 EVT PtrVT = getPointerTy();
2589 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2590 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2592 if (Subtarget->useMovt(DAG.getMachineFunction()))
2595 // FIXME: Once remat is capable of dealing with instructions with register
2596 // operands, expand this into multiple nodes
2598 RelocM == Reloc::PIC_ ? ARMISD::WrapperPIC : ARMISD::Wrapper;
2600 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_NONLAZY);
2601 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT, G);
2603 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
2604 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
2605 MachinePointerInfo::getGOT(), false, false, false, 0);
2609 SDValue ARMTargetLowering::LowerGlobalAddressWindows(SDValue Op,
2610 SelectionDAG &DAG) const {
2611 assert(Subtarget->isTargetWindows() && "non-Windows COFF is not supported");
2612 assert(Subtarget->useMovt(DAG.getMachineFunction()) &&
2613 "Windows on ARM expects to use movw/movt");
2615 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2616 const ARMII::TOF TargetFlags =
2617 (GV->hasDLLImportStorageClass() ? ARMII::MO_DLLIMPORT : ARMII::MO_NO_FLAG);
2618 EVT PtrVT = getPointerTy();
2624 // FIXME: Once remat is capable of dealing with instructions with register
2625 // operands, expand this into two nodes.
2626 Result = DAG.getNode(ARMISD::Wrapper, DL, PtrVT,
2627 DAG.getTargetGlobalAddress(GV, DL, PtrVT, /*Offset=*/0,
2629 if (GV->hasDLLImportStorageClass())
2630 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
2631 MachinePointerInfo::getGOT(), false, false, false, 0);
2635 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
2636 SelectionDAG &DAG) const {
2637 assert(Subtarget->isTargetELF() &&
2638 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
2639 MachineFunction &MF = DAG.getMachineFunction();
2640 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2641 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2642 EVT PtrVT = getPointerTy();
2644 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2645 ARMConstantPoolValue *CPV =
2646 ARMConstantPoolSymbol::Create(*DAG.getContext(), "_GLOBAL_OFFSET_TABLE_",
2647 ARMPCLabelIndex, PCAdj);
2648 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2649 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2650 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2651 MachinePointerInfo::getConstantPool(),
2652 false, false, false, 0);
2653 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2654 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2658 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
2660 SDValue Val = DAG.getConstant(0, dl, MVT::i32);
2661 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl,
2662 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
2663 Op.getOperand(1), Val);
2667 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
2669 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
2670 Op.getOperand(1), DAG.getConstant(0, dl, MVT::i32));
2674 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
2675 const ARMSubtarget *Subtarget) const {
2676 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2679 default: return SDValue(); // Don't custom lower most intrinsics.
2680 case Intrinsic::arm_rbit: {
2681 assert(Op.getOperand(1).getValueType() == MVT::i32 &&
2682 "RBIT intrinsic must have i32 type!");
2683 return DAG.getNode(ARMISD::RBIT, dl, MVT::i32, Op.getOperand(1));
2685 case Intrinsic::arm_thread_pointer: {
2686 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2687 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2689 case Intrinsic::eh_sjlj_lsda: {
2690 MachineFunction &MF = DAG.getMachineFunction();
2691 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2692 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2693 EVT PtrVT = getPointerTy();
2694 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2696 unsigned PCAdj = (RelocM != Reloc::PIC_)
2697 ? 0 : (Subtarget->isThumb() ? 4 : 8);
2698 ARMConstantPoolValue *CPV =
2699 ARMConstantPoolConstant::Create(MF.getFunction(), ARMPCLabelIndex,
2700 ARMCP::CPLSDA, PCAdj);
2701 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2702 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2704 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2705 MachinePointerInfo::getConstantPool(),
2706 false, false, false, 0);
2708 if (RelocM == Reloc::PIC_) {
2709 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2710 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2714 case Intrinsic::arm_neon_vmulls:
2715 case Intrinsic::arm_neon_vmullu: {
2716 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
2717 ? ARMISD::VMULLs : ARMISD::VMULLu;
2718 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
2719 Op.getOperand(1), Op.getOperand(2));
2724 static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
2725 const ARMSubtarget *Subtarget) {
2726 // FIXME: handle "fence singlethread" more efficiently.
2728 if (!Subtarget->hasDataBarrier()) {
2729 // Some ARMv6 cpus can support data barriers with an mcr instruction.
2730 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
2732 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&
2733 "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!");
2734 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2735 DAG.getConstant(0, dl, MVT::i32));
2738 ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1));
2739 AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue());
2740 ARM_MB::MemBOpt Domain = ARM_MB::ISH;
2741 if (Subtarget->isMClass()) {
2742 // Only a full system barrier exists in the M-class architectures.
2743 Domain = ARM_MB::SY;
2744 } else if (Subtarget->isSwift() && Ord == Release) {
2745 // Swift happens to implement ISHST barriers in a way that's compatible with
2746 // Release semantics but weaker than ISH so we'd be fools not to use
2747 // it. Beware: other processors probably don't!
2748 Domain = ARM_MB::ISHST;
2751 return DAG.getNode(ISD::INTRINSIC_VOID, dl, MVT::Other, Op.getOperand(0),
2752 DAG.getConstant(Intrinsic::arm_dmb, dl, MVT::i32),
2753 DAG.getConstant(Domain, dl, MVT::i32));
2756 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
2757 const ARMSubtarget *Subtarget) {
2758 // ARM pre v5TE and Thumb1 does not have preload instructions.
2759 if (!(Subtarget->isThumb2() ||
2760 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
2761 // Just preserve the chain.
2762 return Op.getOperand(0);
2765 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
2767 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
2768 // ARMv7 with MP extension has PLDW.
2769 return Op.getOperand(0);
2771 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
2772 if (Subtarget->isThumb()) {
2774 isRead = ~isRead & 1;
2775 isData = ~isData & 1;
2778 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
2779 Op.getOperand(1), DAG.getConstant(isRead, dl, MVT::i32),
2780 DAG.getConstant(isData, dl, MVT::i32));
2783 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
2784 MachineFunction &MF = DAG.getMachineFunction();
2785 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
2787 // vastart just stores the address of the VarArgsFrameIndex slot into the
2788 // memory location argument.
2790 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2791 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2792 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2793 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2794 MachinePointerInfo(SV), false, false, 0);
2798 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
2799 SDValue &Root, SelectionDAG &DAG,
2801 MachineFunction &MF = DAG.getMachineFunction();
2802 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2804 const TargetRegisterClass *RC;
2805 if (AFI->isThumb1OnlyFunction())
2806 RC = &ARM::tGPRRegClass;
2808 RC = &ARM::GPRRegClass;
2810 // Transform the arguments stored in physical registers into virtual ones.
2811 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2812 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2815 if (NextVA.isMemLoc()) {
2816 MachineFrameInfo *MFI = MF.getFrameInfo();
2817 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
2819 // Create load node to retrieve arguments from the stack.
2820 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2821 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
2822 MachinePointerInfo::getFixedStack(FI),
2823 false, false, false, 0);
2825 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2826 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2828 if (!Subtarget->isLittle())
2829 std::swap (ArgValue, ArgValue2);
2830 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
2833 // The remaining GPRs hold either the beginning of variable-argument
2834 // data, or the beginning of an aggregate passed by value (usually
2835 // byval). Either way, we allocate stack slots adjacent to the data
2836 // provided by our caller, and store the unallocated registers there.
2837 // If this is a variadic function, the va_list pointer will begin with
2838 // these values; otherwise, this reassembles a (byval) structure that
2839 // was split between registers and memory.
2840 // Return: The frame index registers were stored into.
2842 ARMTargetLowering::StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
2843 SDLoc dl, SDValue &Chain,
2844 const Value *OrigArg,
2845 unsigned InRegsParamRecordIdx,
2847 unsigned ArgSize) const {
2848 // Currently, two use-cases possible:
2849 // Case #1. Non-var-args function, and we meet first byval parameter.
2850 // Setup first unallocated register as first byval register;
2851 // eat all remained registers
2852 // (these two actions are performed by HandleByVal method).
2853 // Then, here, we initialize stack frame with
2854 // "store-reg" instructions.
2855 // Case #2. Var-args function, that doesn't contain byval parameters.
2856 // The same: eat all remained unallocated registers,
2857 // initialize stack frame.
2859 MachineFunction &MF = DAG.getMachineFunction();
2860 MachineFrameInfo *MFI = MF.getFrameInfo();
2861 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2862 unsigned RBegin, REnd;
2863 if (InRegsParamRecordIdx < CCInfo.getInRegsParamsCount()) {
2864 CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd);
2866 unsigned RBeginIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
2867 RBegin = RBeginIdx == 4 ? (unsigned)ARM::R4 : GPRArgRegs[RBeginIdx];
2872 ArgOffset = -4 * (ARM::R4 - RBegin);
2874 int FrameIndex = MFI->CreateFixedObject(ArgSize, ArgOffset, false);
2875 SDValue FIN = DAG.getFrameIndex(FrameIndex, getPointerTy());
2877 SmallVector<SDValue, 4> MemOps;
2878 const TargetRegisterClass *RC =
2879 AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
2881 for (unsigned Reg = RBegin, i = 0; Reg < REnd; ++Reg, ++i) {
2882 unsigned VReg = MF.addLiveIn(Reg, RC);
2883 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2885 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2886 MachinePointerInfo(OrigArg, 4 * i), false, false, 0);
2887 MemOps.push_back(Store);
2888 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
2889 DAG.getConstant(4, dl, getPointerTy()));
2892 if (!MemOps.empty())
2893 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2897 // Setup stack frame, the va_list pointer will start from.
2899 ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
2900 SDLoc dl, SDValue &Chain,
2902 unsigned TotalArgRegsSaveSize,
2903 bool ForceMutable) const {
2904 MachineFunction &MF = DAG.getMachineFunction();
2905 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2907 // Try to store any remaining integer argument regs
2908 // to their spots on the stack so that they may be loaded by deferencing
2909 // the result of va_next.
2910 // If there is no regs to be stored, just point address after last
2911 // argument passed via stack.
2912 int FrameIndex = StoreByValRegs(CCInfo, DAG, dl, Chain, nullptr,
2913 CCInfo.getInRegsParamsCount(),
2914 CCInfo.getNextStackOffset(), 4);
2915 AFI->setVarArgsFrameIndex(FrameIndex);
2919 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
2920 CallingConv::ID CallConv, bool isVarArg,
2921 const SmallVectorImpl<ISD::InputArg>
2923 SDLoc dl, SelectionDAG &DAG,
2924 SmallVectorImpl<SDValue> &InVals)
2926 MachineFunction &MF = DAG.getMachineFunction();
2927 MachineFrameInfo *MFI = MF.getFrameInfo();
2929 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2931 // Assign locations to all of the incoming arguments.
2932 SmallVector<CCValAssign, 16> ArgLocs;
2933 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2934 *DAG.getContext(), Prologue);
2935 CCInfo.AnalyzeFormalArguments(Ins,
2936 CCAssignFnForNode(CallConv, /* Return*/ false,
2939 SmallVector<SDValue, 16> ArgValues;
2941 Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin();
2942 unsigned CurArgIdx = 0;
2944 // Initially ArgRegsSaveSize is zero.
2945 // Then we increase this value each time we meet byval parameter.
2946 // We also increase this value in case of varargs function.
2947 AFI->setArgRegsSaveSize(0);
2949 // Calculate the amount of stack space that we need to allocate to store
2950 // byval and variadic arguments that are passed in registers.
2951 // We need to know this before we allocate the first byval or variadic
2952 // argument, as they will be allocated a stack slot below the CFA (Canonical
2953 // Frame Address, the stack pointer at entry to the function).
2954 unsigned ArgRegBegin = ARM::R4;
2955 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2956 if (CCInfo.getInRegsParamsProcessed() >= CCInfo.getInRegsParamsCount())
2959 CCValAssign &VA = ArgLocs[i];
2960 unsigned Index = VA.getValNo();
2961 ISD::ArgFlagsTy Flags = Ins[Index].Flags;
2962 if (!Flags.isByVal())
2965 assert(VA.isMemLoc() && "unexpected byval pointer in reg");
2966 unsigned RBegin, REnd;
2967 CCInfo.getInRegsParamInfo(CCInfo.getInRegsParamsProcessed(), RBegin, REnd);
2968 ArgRegBegin = std::min(ArgRegBegin, RBegin);
2970 CCInfo.nextInRegsParam();
2972 CCInfo.rewindByValRegsInfo();
2974 int lastInsIndex = -1;
2975 if (isVarArg && MFI->hasVAStart()) {
2976 unsigned RegIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
2977 if (RegIdx != array_lengthof(GPRArgRegs))
2978 ArgRegBegin = std::min(ArgRegBegin, (unsigned)GPRArgRegs[RegIdx]);
2981 unsigned TotalArgRegsSaveSize = 4 * (ARM::R4 - ArgRegBegin);
2982 AFI->setArgRegsSaveSize(TotalArgRegsSaveSize);
2984 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2985 CCValAssign &VA = ArgLocs[i];
2986 if (Ins[VA.getValNo()].isOrigArg()) {
2987 std::advance(CurOrigArg,
2988 Ins[VA.getValNo()].getOrigArgIndex() - CurArgIdx);
2989 CurArgIdx = Ins[VA.getValNo()].getOrigArgIndex();
2991 // Arguments stored in registers.
2992 if (VA.isRegLoc()) {
2993 EVT RegVT = VA.getLocVT();
2995 if (VA.needsCustom()) {
2996 // f64 and vector types are split up into multiple registers or
2997 // combinations of registers and stack slots.
2998 if (VA.getLocVT() == MVT::v2f64) {
2999 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
3001 VA = ArgLocs[++i]; // skip ahead to next loc
3003 if (VA.isMemLoc()) {
3004 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
3005 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
3006 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
3007 MachinePointerInfo::getFixedStack(FI),
3008 false, false, false, 0);
3010 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
3013 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
3014 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
3015 ArgValue, ArgValue1,
3016 DAG.getIntPtrConstant(0, dl));
3017 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
3018 ArgValue, ArgValue2,
3019 DAG.getIntPtrConstant(1, dl));
3021 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
3024 const TargetRegisterClass *RC;
3026 if (RegVT == MVT::f32)
3027 RC = &ARM::SPRRegClass;
3028 else if (RegVT == MVT::f64)
3029 RC = &ARM::DPRRegClass;
3030 else if (RegVT == MVT::v2f64)
3031 RC = &ARM::QPRRegClass;
3032 else if (RegVT == MVT::i32)
3033 RC = AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass
3034 : &ARM::GPRRegClass;
3036 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
3038 // Transform the arguments in physical registers into virtual ones.
3039 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3040 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
3043 // If this is an 8 or 16-bit value, it is really passed promoted
3044 // to 32 bits. Insert an assert[sz]ext to capture this, then
3045 // truncate to the right size.
3046 switch (VA.getLocInfo()) {
3047 default: llvm_unreachable("Unknown loc info!");
3048 case CCValAssign::Full: break;
3049 case CCValAssign::BCvt:
3050 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
3052 case CCValAssign::SExt:
3053 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
3054 DAG.getValueType(VA.getValVT()));
3055 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3057 case CCValAssign::ZExt:
3058 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
3059 DAG.getValueType(VA.getValVT()));
3060 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3064 InVals.push_back(ArgValue);
3066 } else { // VA.isRegLoc()
3069 assert(VA.isMemLoc());
3070 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
3072 int index = VA.getValNo();
3074 // Some Ins[] entries become multiple ArgLoc[] entries.
3075 // Process them only once.
3076 if (index != lastInsIndex)
3078 ISD::ArgFlagsTy Flags = Ins[index].Flags;
3079 // FIXME: For now, all byval parameter objects are marked mutable.
3080 // This can be changed with more analysis.
3081 // In case of tail call optimization mark all arguments mutable.
3082 // Since they could be overwritten by lowering of arguments in case of
3084 if (Flags.isByVal()) {
3085 assert(Ins[index].isOrigArg() &&
3086 "Byval arguments cannot be implicit");
3087 unsigned CurByValIndex = CCInfo.getInRegsParamsProcessed();
3089 int FrameIndex = StoreByValRegs(CCInfo, DAG, dl, Chain, CurOrigArg,
3090 CurByValIndex, VA.getLocMemOffset(),
3091 Flags.getByValSize());
3092 InVals.push_back(DAG.getFrameIndex(FrameIndex, getPointerTy()));
3093 CCInfo.nextInRegsParam();
3095 unsigned FIOffset = VA.getLocMemOffset();
3096 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
3099 // Create load nodes to retrieve arguments from the stack.
3100 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
3101 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
3102 MachinePointerInfo::getFixedStack(FI),
3103 false, false, false, 0));
3105 lastInsIndex = index;
3111 if (isVarArg && MFI->hasVAStart())
3112 VarArgStyleRegisters(CCInfo, DAG, dl, Chain,
3113 CCInfo.getNextStackOffset(),
3114 TotalArgRegsSaveSize);
3116 AFI->setArgumentStackSize(CCInfo.getNextStackOffset());
3121 /// isFloatingPointZero - Return true if this is +0.0.
3122 static bool isFloatingPointZero(SDValue Op) {
3123 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
3124 return CFP->getValueAPF().isPosZero();
3125 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
3126 // Maybe this has already been legalized into the constant pool?
3127 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
3128 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
3129 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
3130 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
3131 return CFP->getValueAPF().isPosZero();
3133 } else if (Op->getOpcode() == ISD::BITCAST &&
3134 Op->getValueType(0) == MVT::f64) {
3135 // Handle (ISD::BITCAST (ARMISD::VMOVIMM (ISD::TargetConstant 0)) MVT::f64)
3136 // created by LowerConstantFP().
3137 SDValue BitcastOp = Op->getOperand(0);
3138 if (BitcastOp->getOpcode() == ARMISD::VMOVIMM) {
3139 SDValue MoveOp = BitcastOp->getOperand(0);
3140 if (MoveOp->getOpcode() == ISD::TargetConstant &&
3141 cast<ConstantSDNode>(MoveOp)->getZExtValue() == 0) {
3149 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
3150 /// the given operands.
3152 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
3153 SDValue &ARMcc, SelectionDAG &DAG,
3155 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
3156 unsigned C = RHSC->getZExtValue();
3157 if (!isLegalICmpImmediate(C)) {
3158 // Constant does not fit, try adjusting it by one?
3163 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
3164 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
3165 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
3170 if (C != 0 && isLegalICmpImmediate(C-1)) {
3171 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
3172 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
3177 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
3178 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
3179 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
3184 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
3185 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
3186 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
3193 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3194 ARMISD::NodeType CompareType;
3197 CompareType = ARMISD::CMP;
3202 CompareType = ARMISD::CMPZ;
3205 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
3206 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
3209 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
3211 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
3213 assert(!Subtarget->isFPOnlySP() || RHS.getValueType() != MVT::f64);
3215 if (!isFloatingPointZero(RHS))
3216 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS);
3218 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS);
3219 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
3222 /// duplicateCmp - Glue values can have only one use, so this function
3223 /// duplicates a comparison node.
3225 ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
3226 unsigned Opc = Cmp.getOpcode();
3228 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
3229 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
3231 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation");
3232 Cmp = Cmp.getOperand(0);
3233 Opc = Cmp.getOpcode();
3234 if (Opc == ARMISD::CMPFP)
3235 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
3237 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT");
3238 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0));
3240 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
3243 std::pair<SDValue, SDValue>
3244 ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG,
3245 SDValue &ARMcc) const {
3246 assert(Op.getValueType() == MVT::i32 && "Unsupported value type");
3248 SDValue Value, OverflowCmp;
3249 SDValue LHS = Op.getOperand(0);
3250 SDValue RHS = Op.getOperand(1);
3253 // FIXME: We are currently always generating CMPs because we don't support
3254 // generating CMN through the backend. This is not as good as the natural
3255 // CMP case because it causes a register dependency and cannot be folded
3258 switch (Op.getOpcode()) {
3260 llvm_unreachable("Unknown overflow instruction!");
3262 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
3263 Value = DAG.getNode(ISD::ADD, dl, Op.getValueType(), LHS, RHS);
3264 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
3267 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
3268 Value = DAG.getNode(ISD::ADD, dl, Op.getValueType(), LHS, RHS);
3269 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
3272 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
3273 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
3274 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
3277 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
3278 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
3279 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
3283 return std::make_pair(Value, OverflowCmp);
3288 ARMTargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
3289 // Let legalize expand this if it isn't a legal type yet.
3290 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
3293 SDValue Value, OverflowCmp;
3295 std::tie(Value, OverflowCmp) = getARMXALUOOp(Op, DAG, ARMcc);
3296 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3298 // We use 0 and 1 as false and true values.
3299 SDValue TVal = DAG.getConstant(1, dl, MVT::i32);
3300 SDValue FVal = DAG.getConstant(0, dl, MVT::i32);
3301 EVT VT = Op.getValueType();
3303 SDValue Overflow = DAG.getNode(ARMISD::CMOV, dl, VT, TVal, FVal,
3304 ARMcc, CCR, OverflowCmp);
3306 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
3307 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
3311 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
3312 SDValue Cond = Op.getOperand(0);
3313 SDValue SelectTrue = Op.getOperand(1);
3314 SDValue SelectFalse = Op.getOperand(2);
3316 unsigned Opc = Cond.getOpcode();
3318 if (Cond.getResNo() == 1 &&
3319 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3320 Opc == ISD::USUBO)) {
3321 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
3324 SDValue Value, OverflowCmp;
3326 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
3327 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3328 EVT VT = Op.getValueType();
3330 return getCMOV(dl, VT, SelectTrue, SelectFalse, ARMcc, CCR,
3336 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
3337 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
3339 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
3340 const ConstantSDNode *CMOVTrue =
3341 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
3342 const ConstantSDNode *CMOVFalse =
3343 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
3345 if (CMOVTrue && CMOVFalse) {
3346 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
3347 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
3351 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
3353 False = SelectFalse;
3354 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
3359 if (True.getNode() && False.getNode()) {
3360 EVT VT = Op.getValueType();
3361 SDValue ARMcc = Cond.getOperand(2);
3362 SDValue CCR = Cond.getOperand(3);
3363 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
3364 assert(True.getValueType() == VT);
3365 return getCMOV(dl, VT, True, False, ARMcc, CCR, Cmp, DAG);
3370 // ARM's BooleanContents value is UndefinedBooleanContent. Mask out the
3371 // undefined bits before doing a full-word comparison with zero.
3372 Cond = DAG.getNode(ISD::AND, dl, Cond.getValueType(), Cond,
3373 DAG.getConstant(1, dl, Cond.getValueType()));
3375 return DAG.getSelectCC(dl, Cond,
3376 DAG.getConstant(0, dl, Cond.getValueType()),
3377 SelectTrue, SelectFalse, ISD::SETNE);
3380 static ISD::CondCode getInverseCCForVSEL(ISD::CondCode CC) {
3381 if (CC == ISD::SETNE)
3383 return ISD::getSetCCInverse(CC, true);
3386 static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
3387 bool &swpCmpOps, bool &swpVselOps) {
3388 // Start by selecting the GE condition code for opcodes that return true for
3390 if (CC == ISD::SETUGE || CC == ISD::SETOGE || CC == ISD::SETOLE ||
3392 CondCode = ARMCC::GE;
3394 // and GT for opcodes that return false for 'equality'.
3395 else if (CC == ISD::SETUGT || CC == ISD::SETOGT || CC == ISD::SETOLT ||
3397 CondCode = ARMCC::GT;
3399 // Since we are constrained to GE/GT, if the opcode contains 'less', we need
3400 // to swap the compare operands.
3401 if (CC == ISD::SETOLE || CC == ISD::SETULE || CC == ISD::SETOLT ||
3405 // Both GT and GE are ordered comparisons, and return false for 'unordered'.
3406 // If we have an unordered opcode, we need to swap the operands to the VSEL
3407 // instruction (effectively negating the condition).
3409 // This also has the effect of swapping which one of 'less' or 'greater'
3410 // returns true, so we also swap the compare operands. It also switches
3411 // whether we return true for 'equality', so we compensate by picking the
3412 // opposite condition code to our original choice.
3413 if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE ||
3414 CC == ISD::SETUGT) {
3415 swpCmpOps = !swpCmpOps;
3416 swpVselOps = !swpVselOps;
3417 CondCode = CondCode == ARMCC::GT ? ARMCC::GE : ARMCC::GT;
3420 // 'ordered' is 'anything but unordered', so use the VS condition code and
3421 // swap the VSEL operands.
3422 if (CC == ISD::SETO) {
3423 CondCode = ARMCC::VS;
3427 // 'unordered or not equal' is 'anything but equal', so use the EQ condition
3428 // code and swap the VSEL operands.
3429 if (CC == ISD::SETUNE) {
3430 CondCode = ARMCC::EQ;
3435 SDValue ARMTargetLowering::getCMOV(SDLoc dl, EVT VT, SDValue FalseVal,
3436 SDValue TrueVal, SDValue ARMcc, SDValue CCR,
3437 SDValue Cmp, SelectionDAG &DAG) const {
3438 if (Subtarget->isFPOnlySP() && VT == MVT::f64) {
3439 FalseVal = DAG.getNode(ARMISD::VMOVRRD, dl,
3440 DAG.getVTList(MVT::i32, MVT::i32), FalseVal);
3441 TrueVal = DAG.getNode(ARMISD::VMOVRRD, dl,
3442 DAG.getVTList(MVT::i32, MVT::i32), TrueVal);
3444 SDValue TrueLow = TrueVal.getValue(0);
3445 SDValue TrueHigh = TrueVal.getValue(1);
3446 SDValue FalseLow = FalseVal.getValue(0);
3447 SDValue FalseHigh = FalseVal.getValue(1);
3449 SDValue Low = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseLow, TrueLow,
3451 SDValue High = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseHigh, TrueHigh,
3452 ARMcc, CCR, duplicateCmp(Cmp, DAG));
3454 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Low, High);
3456 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,
3461 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
3462 EVT VT = Op.getValueType();
3463 SDValue LHS = Op.getOperand(0);
3464 SDValue RHS = Op.getOperand(1);
3465 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3466 SDValue TrueVal = Op.getOperand(2);
3467 SDValue FalseVal = Op.getOperand(3);
3470 if (Subtarget->isFPOnlySP() && LHS.getValueType() == MVT::f64) {
3471 DAG.getTargetLoweringInfo().softenSetCCOperands(DAG, MVT::f64, LHS, RHS, CC,
3474 // If softenSetCCOperands only returned one value, we should compare it to
3476 if (!RHS.getNode()) {
3477 RHS = DAG.getConstant(0, dl, LHS.getValueType());
3482 if (LHS.getValueType() == MVT::i32) {
3483 // Try to generate VSEL on ARMv8.
3484 // The VSEL instruction can't use all the usual ARM condition
3485 // codes: it only has two bits to select the condition code, so it's
3486 // constrained to use only GE, GT, VS and EQ.
3488 // To implement all the various ISD::SETXXX opcodes, we sometimes need to
3489 // swap the operands of the previous compare instruction (effectively
3490 // inverting the compare condition, swapping 'less' and 'greater') and
3491 // sometimes need to swap the operands to the VSEL (which inverts the
3492 // condition in the sense of firing whenever the previous condition didn't)
3493 if (Subtarget->hasFPARMv8() && (TrueVal.getValueType() == MVT::f32 ||
3494 TrueVal.getValueType() == MVT::f64)) {
3495 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3496 if (CondCode == ARMCC::LT || CondCode == ARMCC::LE ||
3497 CondCode == ARMCC::VC || CondCode == ARMCC::NE) {
3498 CC = getInverseCCForVSEL(CC);
3499 std::swap(TrueVal, FalseVal);
3504 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3505 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3506 return getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
3509 ARMCC::CondCodes CondCode, CondCode2;
3510 FPCCToARMCC(CC, CondCode, CondCode2);
3512 // Try to generate VMAXNM/VMINNM on ARMv8.
3513 if (Subtarget->hasFPARMv8() && (TrueVal.getValueType() == MVT::f32 ||
3514 TrueVal.getValueType() == MVT::f64)) {
3515 // We can use VMAXNM/VMINNM for a compare followed by a select with the
3516 // same operands, as follows:
3517 // c = fcmp [?gt, ?ge, ?lt, ?le] a, b
3519 // In NoNaNsFPMath the CC will have been changed from, e.g., 'ogt' to 'gt'.
3520 // We only do this transformation in UnsafeFPMath and for no-NaNs
3521 // comparisons, because signed zeros and NaNs are handled differently than
3522 // the original code sequence.
3523 // FIXME: There are more cases that can be transformed even with NaNs,
3524 // signed zeroes and safe math. E.g. in the following, the result will be
3525 // FalseVal if a is a NaN or -0./0. and that's what vmaxnm will give, too.
3526 // c = fcmp ogt, a, 0. ; select c, a, 0. => vmaxnm a, 0.
3527 // FIXME: There is similar code that allows some extensions in
3528 // AArch64TargetLowering::LowerSELECT_CC that should be shared with this
3530 if (getTargetMachine().Options.UnsafeFPMath) {
3531 if (LHS == TrueVal && RHS == FalseVal) {
3532 if (CC == ISD::SETGT || CC == ISD::SETGE)
3533 return DAG.getNode(ARMISD::VMAXNM, dl, VT, TrueVal, FalseVal);
3534 if (CC == ISD::SETLT || CC == ISD::SETLE)
3535 return DAG.getNode(ARMISD::VMINNM, dl, VT, TrueVal, FalseVal);
3536 } else if (LHS == FalseVal && RHS == TrueVal) {
3537 if (CC == ISD::SETLT || CC == ISD::SETLE)
3538 return DAG.getNode(ARMISD::VMAXNM, dl, VT, TrueVal, FalseVal);
3539 if (CC == ISD::SETGT || CC == ISD::SETGE)
3540 return DAG.getNode(ARMISD::VMINNM, dl, VT, TrueVal, FalseVal);
3544 bool swpCmpOps = false;
3545 bool swpVselOps = false;
3546 checkVSELConstraints(CC, CondCode, swpCmpOps, swpVselOps);
3548 if (CondCode == ARMCC::GT || CondCode == ARMCC::GE ||
3549 CondCode == ARMCC::VS || CondCode == ARMCC::EQ) {
3551 std::swap(LHS, RHS);
3553 std::swap(TrueVal, FalseVal);
3557 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
3558 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
3559 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3560 SDValue Result = getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
3561 if (CondCode2 != ARMCC::AL) {
3562 SDValue ARMcc2 = DAG.getConstant(CondCode2, dl, MVT::i32);
3563 // FIXME: Needs another CMP because flag can have but one use.
3564 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
3565 Result = getCMOV(dl, VT, Result, TrueVal, ARMcc2, CCR, Cmp2, DAG);
3570 /// canChangeToInt - Given the fp compare operand, return true if it is suitable
3571 /// to morph to an integer compare sequence.
3572 static bool canChangeToInt(SDValue Op, bool &SeenZero,
3573 const ARMSubtarget *Subtarget) {
3574 SDNode *N = Op.getNode();
3575 if (!N->hasOneUse())
3576 // Otherwise it requires moving the value from fp to integer registers.
3578 if (!N->getNumValues())
3580 EVT VT = Op.getValueType();
3581 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
3582 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
3583 // vmrs are very slow, e.g. cortex-a8.
3586 if (isFloatingPointZero(Op)) {
3590 return ISD::isNormalLoad(N);
3593 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
3594 if (isFloatingPointZero(Op))
3595 return DAG.getConstant(0, SDLoc(Op), MVT::i32);
3597 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
3598 return DAG.getLoad(MVT::i32, SDLoc(Op),
3599 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(),
3600 Ld->isVolatile(), Ld->isNonTemporal(),
3601 Ld->isInvariant(), Ld->getAlignment());
3603 llvm_unreachable("Unknown VFP cmp argument!");
3606 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
3607 SDValue &RetVal1, SDValue &RetVal2) {
3610 if (isFloatingPointZero(Op)) {
3611 RetVal1 = DAG.getConstant(0, dl, MVT::i32);
3612 RetVal2 = DAG.getConstant(0, dl, MVT::i32);
3616 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
3617 SDValue Ptr = Ld->getBasePtr();
3618 RetVal1 = DAG.getLoad(MVT::i32, dl,
3619 Ld->getChain(), Ptr,
3620 Ld->getPointerInfo(),
3621 Ld->isVolatile(), Ld->isNonTemporal(),
3622 Ld->isInvariant(), Ld->getAlignment());
3624 EVT PtrType = Ptr.getValueType();
3625 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
3626 SDValue NewPtr = DAG.getNode(ISD::ADD, dl,
3627 PtrType, Ptr, DAG.getConstant(4, dl, PtrType));
3628 RetVal2 = DAG.getLoad(MVT::i32, dl,
3629 Ld->getChain(), NewPtr,
3630 Ld->getPointerInfo().getWithOffset(4),
3631 Ld->isVolatile(), Ld->isNonTemporal(),
3632 Ld->isInvariant(), NewAlign);
3636 llvm_unreachable("Unknown VFP cmp argument!");
3639 /// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
3640 /// f32 and even f64 comparisons to integer ones.
3642 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
3643 SDValue Chain = Op.getOperand(0);
3644 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3645 SDValue LHS = Op.getOperand(2);
3646 SDValue RHS = Op.getOperand(3);
3647 SDValue Dest = Op.getOperand(4);
3650 bool LHSSeenZero = false;
3651 bool LHSOk = canChangeToInt(LHS, LHSSeenZero, Subtarget);
3652 bool RHSSeenZero = false;
3653 bool RHSOk = canChangeToInt(RHS, RHSSeenZero, Subtarget);
3654 if (LHSOk && RHSOk && (LHSSeenZero || RHSSeenZero)) {
3655 // If unsafe fp math optimization is enabled and there are no other uses of
3656 // the CMP operands, and the condition code is EQ or NE, we can optimize it
3657 // to an integer comparison.
3658 if (CC == ISD::SETOEQ)
3660 else if (CC == ISD::SETUNE)
3663 SDValue Mask = DAG.getConstant(0x7fffffff, dl, MVT::i32);
3665 if (LHS.getValueType() == MVT::f32) {
3666 LHS = DAG.getNode(ISD::AND, dl, MVT::i32,
3667 bitcastf32Toi32(LHS, DAG), Mask);
3668 RHS = DAG.getNode(ISD::AND, dl, MVT::i32,
3669 bitcastf32Toi32(RHS, DAG), Mask);
3670 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3671 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3672 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
3673 Chain, Dest, ARMcc, CCR, Cmp);
3678 expandf64Toi32(LHS, DAG, LHS1, LHS2);
3679 expandf64Toi32(RHS, DAG, RHS1, RHS2);
3680 LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask);
3681 RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask);
3682 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3683 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
3684 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
3685 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
3686 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops);
3692 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
3693 SDValue Chain = Op.getOperand(0);
3694 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3695 SDValue LHS = Op.getOperand(2);
3696 SDValue RHS = Op.getOperand(3);
3697 SDValue Dest = Op.getOperand(4);
3700 if (Subtarget->isFPOnlySP() && LHS.getValueType() == MVT::f64) {
3701 DAG.getTargetLoweringInfo().softenSetCCOperands(DAG, MVT::f64, LHS, RHS, CC,
3704 // If softenSetCCOperands only returned one value, we should compare it to
3706 if (!RHS.getNode()) {
3707 RHS = DAG.getConstant(0, dl, LHS.getValueType());
3712 if (LHS.getValueType() == MVT::i32) {
3714 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3715 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3716 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
3717 Chain, Dest, ARMcc, CCR, Cmp);
3720 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3722 if (getTargetMachine().Options.UnsafeFPMath &&
3723 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
3724 CC == ISD::SETNE || CC == ISD::SETUNE)) {
3725 SDValue Result = OptimizeVFPBrcond(Op, DAG);
3726 if (Result.getNode())
3730 ARMCC::CondCodes CondCode, CondCode2;
3731 FPCCToARMCC(CC, CondCode, CondCode2);
3733 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
3734 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
3735 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3736 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
3737 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
3738 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
3739 if (CondCode2 != ARMCC::AL) {
3740 ARMcc = DAG.getConstant(CondCode2, dl, MVT::i32);
3741 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
3742 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
3747 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
3748 SDValue Chain = Op.getOperand(0);
3749 SDValue Table = Op.getOperand(1);
3750 SDValue Index = Op.getOperand(2);
3753 EVT PTy = getPointerTy();
3754 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
3755 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
3756 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), dl, PTy);
3757 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
3758 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
3759 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, dl, PTy));
3760 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
3761 if (Subtarget->isThumb2()) {
3762 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
3763 // which does another jump to the destination. This also makes it easier
3764 // to translate it to TBB / TBH later.
3765 // FIXME: This might not work if the function is extremely large.
3766 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
3767 Addr, Op.getOperand(2), JTI, UId);
3769 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
3770 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
3771 MachinePointerInfo::getJumpTable(),
3772 false, false, false, 0);
3773 Chain = Addr.getValue(1);
3774 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
3775 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
3777 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
3778 MachinePointerInfo::getJumpTable(),
3779 false, false, false, 0);
3780 Chain = Addr.getValue(1);
3781 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
3785 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
3786 EVT VT = Op.getValueType();
3789 if (Op.getValueType().getVectorElementType() == MVT::i32) {
3790 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32)
3792 return DAG.UnrollVectorOp(Op.getNode());
3795 assert(Op.getOperand(0).getValueType() == MVT::v4f32 &&
3796 "Invalid type for custom lowering!");
3797 if (VT != MVT::v4i16)
3798 return DAG.UnrollVectorOp(Op.getNode());
3800 Op = DAG.getNode(Op.getOpcode(), dl, MVT::v4i32, Op.getOperand(0));
3801 return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
3804 SDValue ARMTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const {
3805 EVT VT = Op.getValueType();
3807 return LowerVectorFP_TO_INT(Op, DAG);
3808 if (Subtarget->isFPOnlySP() && Op.getOperand(0).getValueType() == MVT::f64) {
3810 if (Op.getOpcode() == ISD::FP_TO_SINT)
3811 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(),
3814 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(),
3816 return makeLibCall(DAG, LC, Op.getValueType(), &Op.getOperand(0), 1,
3817 /*isSigned*/ false, SDLoc(Op)).first;
3823 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
3824 EVT VT = Op.getValueType();
3827 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) {
3828 if (VT.getVectorElementType() == MVT::f32)
3830 return DAG.UnrollVectorOp(Op.getNode());
3833 assert(Op.getOperand(0).getValueType() == MVT::v4i16 &&
3834 "Invalid type for custom lowering!");
3835 if (VT != MVT::v4f32)
3836 return DAG.UnrollVectorOp(Op.getNode());
3840 switch (Op.getOpcode()) {
3841 default: llvm_unreachable("Invalid opcode!");
3842 case ISD::SINT_TO_FP:
3843 CastOpc = ISD::SIGN_EXTEND;
3844 Opc = ISD::SINT_TO_FP;
3846 case ISD::UINT_TO_FP:
3847 CastOpc = ISD::ZERO_EXTEND;
3848 Opc = ISD::UINT_TO_FP;
3852 Op = DAG.getNode(CastOpc, dl, MVT::v4i32, Op.getOperand(0));
3853 return DAG.getNode(Opc, dl, VT, Op);
3856 SDValue ARMTargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const {
3857 EVT VT = Op.getValueType();
3859 return LowerVectorINT_TO_FP(Op, DAG);
3860 if (Subtarget->isFPOnlySP() && Op.getValueType() == MVT::f64) {
3862 if (Op.getOpcode() == ISD::SINT_TO_FP)
3863 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(),
3866 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(),
3868 return makeLibCall(DAG, LC, Op.getValueType(), &Op.getOperand(0), 1,
3869 /*isSigned*/ false, SDLoc(Op)).first;
3875 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
3876 // Implement fcopysign with a fabs and a conditional fneg.
3877 SDValue Tmp0 = Op.getOperand(0);
3878 SDValue Tmp1 = Op.getOperand(1);
3880 EVT VT = Op.getValueType();
3881 EVT SrcVT = Tmp1.getValueType();
3882 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
3883 Tmp0.getOpcode() == ARMISD::VMOVDRR;
3884 bool UseNEON = !InGPR && Subtarget->hasNEON();
3887 // Use VBSL to copy the sign bit.
3888 unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80);
3889 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
3890 DAG.getTargetConstant(EncodedVal, dl, MVT::i32));
3891 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
3893 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT,
3894 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
3895 DAG.getConstant(32, dl, MVT::i32));
3896 else /*if (VT == MVT::f32)*/
3897 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
3898 if (SrcVT == MVT::f32) {
3899 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
3901 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT,
3902 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
3903 DAG.getConstant(32, dl, MVT::i32));
3904 } else if (VT == MVT::f32)
3905 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64,
3906 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
3907 DAG.getConstant(32, dl, MVT::i32));
3908 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
3909 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
3911 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff),
3913 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
3914 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
3915 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
3917 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
3918 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
3919 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
3920 if (VT == MVT::f32) {
3921 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
3922 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
3923 DAG.getConstant(0, dl, MVT::i32));
3925 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
3931 // Bitcast operand 1 to i32.
3932 if (SrcVT == MVT::f64)
3933 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
3935 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
3937 // Or in the signbit with integer operations.
3938 SDValue Mask1 = DAG.getConstant(0x80000000, dl, MVT::i32);
3939 SDValue Mask2 = DAG.getConstant(0x7fffffff, dl, MVT::i32);
3940 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
3941 if (VT == MVT::f32) {
3942 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
3943 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
3944 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3945 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
3948 // f64: Or the high part with signbit and then combine two parts.
3949 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
3951 SDValue Lo = Tmp0.getValue(0);
3952 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
3953 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
3954 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
3957 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
3958 MachineFunction &MF = DAG.getMachineFunction();
3959 MachineFrameInfo *MFI = MF.getFrameInfo();
3960 MFI->setReturnAddressIsTaken(true);
3962 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
3965 EVT VT = Op.getValueType();
3967 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3969 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
3970 SDValue Offset = DAG.getConstant(4, dl, MVT::i32);
3971 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
3972 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
3973 MachinePointerInfo(), false, false, false, 0);
3976 // Return LR, which contains the return address. Mark it an implicit live-in.
3977 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
3978 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
3981 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
3982 const ARMBaseRegisterInfo &ARI =
3983 *static_cast<const ARMBaseRegisterInfo*>(RegInfo);
3984 MachineFunction &MF = DAG.getMachineFunction();
3985 MachineFrameInfo *MFI = MF.getFrameInfo();
3986 MFI->setFrameAddressIsTaken(true);
3988 EVT VT = Op.getValueType();
3989 SDLoc dl(Op); // FIXME probably not meaningful
3990 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3991 unsigned FrameReg = ARI.getFrameRegister(MF);
3992 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
3994 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
3995 MachinePointerInfo(),
3996 false, false, false, 0);
4000 // FIXME? Maybe this could be a TableGen attribute on some registers and
4001 // this table could be generated automatically from RegInfo.
4002 unsigned ARMTargetLowering::getRegisterByName(const char* RegName,
4004 unsigned Reg = StringSwitch<unsigned>(RegName)
4005 .Case("sp", ARM::SP)
4009 report_fatal_error("Invalid register name global variable");
4012 /// ExpandBITCAST - If the target supports VFP, this function is called to
4013 /// expand a bit convert where either the source or destination type is i64 to
4014 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
4015 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
4016 /// vectors), since the legalizer won't know what to do with that.
4017 static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) {
4018 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4020 SDValue Op = N->getOperand(0);
4022 // This function is only supposed to be called for i64 types, either as the
4023 // source or destination of the bit convert.
4024 EVT SrcVT = Op.getValueType();
4025 EVT DstVT = N->getValueType(0);
4026 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
4027 "ExpandBITCAST called for non-i64 type");
4029 // Turn i64->f64 into VMOVDRR.
4030 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
4031 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
4032 DAG.getConstant(0, dl, MVT::i32));
4033 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
4034 DAG.getConstant(1, dl, MVT::i32));
4035 return DAG.getNode(ISD::BITCAST, dl, DstVT,
4036 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
4039 // Turn f64->i64 into VMOVRRD.
4040 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
4042 if (TLI.isBigEndian() && SrcVT.isVector() &&
4043 SrcVT.getVectorNumElements() > 1)
4044 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
4045 DAG.getVTList(MVT::i32, MVT::i32),
4046 DAG.getNode(ARMISD::VREV64, dl, SrcVT, Op));
4048 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
4049 DAG.getVTList(MVT::i32, MVT::i32), Op);
4050 // Merge the pieces into a single i64 value.
4051 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
4057 /// getZeroVector - Returns a vector of specified type with all zero elements.
4058 /// Zero vectors are used to represent vector negation and in those cases
4059 /// will be implemented with the NEON VNEG instruction. However, VNEG does
4060 /// not support i64 elements, so sometimes the zero vectors will need to be
4061 /// explicitly constructed. Regardless, use a canonical VMOV to create the
4063 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, SDLoc dl) {
4064 assert(VT.isVector() && "Expected a vector type");
4065 // The canonical modified immediate encoding of a zero vector is....0!
4066 SDValue EncodedVal = DAG.getTargetConstant(0, dl, MVT::i32);
4067 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
4068 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
4069 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
4072 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
4073 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
4074 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
4075 SelectionDAG &DAG) const {
4076 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4077 EVT VT = Op.getValueType();
4078 unsigned VTBits = VT.getSizeInBits();
4080 SDValue ShOpLo = Op.getOperand(0);
4081 SDValue ShOpHi = Op.getOperand(1);
4082 SDValue ShAmt = Op.getOperand(2);
4084 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
4086 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
4088 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
4089 DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
4090 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
4091 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
4092 DAG.getConstant(VTBits, dl, MVT::i32));
4093 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
4094 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4095 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
4097 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4098 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
4099 ISD::SETGE, ARMcc, DAG, dl);
4100 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
4101 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
4104 SDValue Ops[2] = { Lo, Hi };
4105 return DAG.getMergeValues(Ops, dl);
4108 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
4109 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
4110 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
4111 SelectionDAG &DAG) const {
4112 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4113 EVT VT = Op.getValueType();
4114 unsigned VTBits = VT.getSizeInBits();
4116 SDValue ShOpLo = Op.getOperand(0);
4117 SDValue ShOpHi = Op.getOperand(1);
4118 SDValue ShAmt = Op.getOperand(2);
4121 assert(Op.getOpcode() == ISD::SHL_PARTS);
4122 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
4123 DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
4124 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
4125 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
4126 DAG.getConstant(VTBits, dl, MVT::i32));
4127 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
4128 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
4130 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4131 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4132 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
4133 ISD::SETGE, ARMcc, DAG, dl);
4134 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
4135 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
4138 SDValue Ops[2] = { Lo, Hi };
4139 return DAG.getMergeValues(Ops, dl);
4142 SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
4143 SelectionDAG &DAG) const {
4144 // The rounding mode is in bits 23:22 of the FPSCR.
4145 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
4146 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
4147 // so that the shift + and get folded into a bitfield extract.
4149 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
4150 DAG.getConstant(Intrinsic::arm_get_fpscr, dl,
4152 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
4153 DAG.getConstant(1U << 22, dl, MVT::i32));
4154 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
4155 DAG.getConstant(22, dl, MVT::i32));
4156 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
4157 DAG.getConstant(3, dl, MVT::i32));
4160 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
4161 const ARMSubtarget *ST) {
4162 EVT VT = N->getValueType(0);
4165 if (!ST->hasV6T2Ops())
4168 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
4169 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
4172 /// getCTPOP16BitCounts - Returns a v8i8/v16i8 vector containing the bit-count
4173 /// for each 16-bit element from operand, repeated. The basic idea is to
4174 /// leverage vcnt to get the 8-bit counts, gather and add the results.
4176 /// Trace for v4i16:
4177 /// input = [v0 v1 v2 v3 ] (vi 16-bit element)
4178 /// cast: N0 = [w0 w1 w2 w3 w4 w5 w6 w7] (v0 = [w0 w1], wi 8-bit element)
4179 /// vcnt: N1 = [b0 b1 b2 b3 b4 b5 b6 b7] (bi = bit-count of 8-bit element wi)
4180 /// vrev: N2 = [b1 b0 b3 b2 b5 b4 b7 b6]
4181 /// [b0 b1 b2 b3 b4 b5 b6 b7]
4182 /// +[b1 b0 b3 b2 b5 b4 b7 b6]
4183 /// N3=N1+N2 = [k0 k0 k1 k1 k2 k2 k3 k3] (k0 = b0+b1 = bit-count of 16-bit v0,
4184 /// vuzp: = [k0 k1 k2 k3 k0 k1 k2 k3] each ki is 8-bits)
4185 static SDValue getCTPOP16BitCounts(SDNode *N, SelectionDAG &DAG) {
4186 EVT VT = N->getValueType(0);
4189 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8;
4190 SDValue N0 = DAG.getNode(ISD::BITCAST, DL, VT8Bit, N->getOperand(0));
4191 SDValue N1 = DAG.getNode(ISD::CTPOP, DL, VT8Bit, N0);
4192 SDValue N2 = DAG.getNode(ARMISD::VREV16, DL, VT8Bit, N1);
4193 SDValue N3 = DAG.getNode(ISD::ADD, DL, VT8Bit, N1, N2);
4194 return DAG.getNode(ARMISD::VUZP, DL, VT8Bit, N3, N3);
4197 /// lowerCTPOP16BitElements - Returns a v4i16/v8i16 vector containing the
4198 /// bit-count for each 16-bit element from the operand. We need slightly
4199 /// different sequencing for v4i16 and v8i16 to stay within NEON's available
4200 /// 64/128-bit registers.
4202 /// Trace for v4i16:
4203 /// input = [v0 v1 v2 v3 ] (vi 16-bit element)
4204 /// v8i8: BitCounts = [k0 k1 k2 k3 k0 k1 k2 k3 ] (ki is the bit-count of vi)
4205 /// v8i16:Extended = [k0 k1 k2 k3 k0 k1 k2 k3 ]
4206 /// v4i16:Extracted = [k0 k1 k2 k3 ]
4207 static SDValue lowerCTPOP16BitElements(SDNode *N, SelectionDAG &DAG) {
4208 EVT VT = N->getValueType(0);
4211 SDValue BitCounts = getCTPOP16BitCounts(N, DAG);
4212 if (VT.is64BitVector()) {
4213 SDValue Extended = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v8i16, BitCounts);
4214 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, Extended,
4215 DAG.getIntPtrConstant(0, DL));
4217 SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v8i8,
4218 BitCounts, DAG.getIntPtrConstant(0, DL));
4219 return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v8i16, Extracted);
4223 /// lowerCTPOP32BitElements - Returns a v2i32/v4i32 vector containing the
4224 /// bit-count for each 32-bit element from the operand. The idea here is
4225 /// to split the vector into 16-bit elements, leverage the 16-bit count
4226 /// routine, and then combine the results.
4228 /// Trace for v2i32 (v4i32 similar with Extracted/Extended exchanged):
4229 /// input = [v0 v1 ] (vi: 32-bit elements)
4230 /// Bitcast = [w0 w1 w2 w3 ] (wi: 16-bit elements, v0 = [w0 w1])
4231 /// Counts16 = [k0 k1 k2 k3 ] (ki: 16-bit elements, bit-count of wi)
4232 /// vrev: N0 = [k1 k0 k3 k2 ]
4234 /// N1 =+[k1 k0 k3 k2 ]
4236 /// N2 =+[k1 k3 k0 k2 ]
4238 /// Extended =+[k1 k3 k0 k2 ]
4240 /// Extracted=+[k1 k3 ]
4242 static SDValue lowerCTPOP32BitElements(SDNode *N, SelectionDAG &DAG) {
4243 EVT VT = N->getValueType(0);
4246 EVT VT16Bit = VT.is64BitVector() ? MVT::v4i16 : MVT::v8i16;
4248 SDValue Bitcast = DAG.getNode(ISD::BITCAST, DL, VT16Bit, N->getOperand(0));
4249 SDValue Counts16 = lowerCTPOP16BitElements(Bitcast.getNode(), DAG);
4250 SDValue N0 = DAG.getNode(ARMISD::VREV32, DL, VT16Bit, Counts16);
4251 SDValue N1 = DAG.getNode(ISD::ADD, DL, VT16Bit, Counts16, N0);
4252 SDValue N2 = DAG.getNode(ARMISD::VUZP, DL, VT16Bit, N1, N1);
4254 if (VT.is64BitVector()) {
4255 SDValue Extended = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v4i32, N2);
4256 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i32, Extended,
4257 DAG.getIntPtrConstant(0, DL));
4259 SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, N2,
4260 DAG.getIntPtrConstant(0, DL));
4261 return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v4i32, Extracted);
4265 static SDValue LowerCTPOP(SDNode *N, SelectionDAG &DAG,
4266 const ARMSubtarget *ST) {
4267 EVT VT = N->getValueType(0);
4269 assert(ST->hasNEON() && "Custom ctpop lowering requires NEON.");
4270 assert((VT == MVT::v2i32 || VT == MVT::v4i32 ||
4271 VT == MVT::v4i16 || VT == MVT::v8i16) &&
4272 "Unexpected type for custom ctpop lowering");
4274 if (VT.getVectorElementType() == MVT::i32)
4275 return lowerCTPOP32BitElements(N, DAG);
4277 return lowerCTPOP16BitElements(N, DAG);
4280 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
4281 const ARMSubtarget *ST) {
4282 EVT VT = N->getValueType(0);
4288 // Lower vector shifts on NEON to use VSHL.
4289 assert(ST->hasNEON() && "unexpected vector shift");
4291 // Left shifts translate directly to the vshiftu intrinsic.
4292 if (N->getOpcode() == ISD::SHL)
4293 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
4294 DAG.getConstant(Intrinsic::arm_neon_vshiftu, dl,
4296 N->getOperand(0), N->getOperand(1));
4298 assert((N->getOpcode() == ISD::SRA ||
4299 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
4301 // NEON uses the same intrinsics for both left and right shifts. For
4302 // right shifts, the shift amounts are negative, so negate the vector of
4304 EVT ShiftVT = N->getOperand(1).getValueType();
4305 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
4306 getZeroVector(ShiftVT, DAG, dl),
4308 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
4309 Intrinsic::arm_neon_vshifts :
4310 Intrinsic::arm_neon_vshiftu);
4311 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
4312 DAG.getConstant(vshiftInt, dl, MVT::i32),
4313 N->getOperand(0), NegatedCount);
4316 static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
4317 const ARMSubtarget *ST) {
4318 EVT VT = N->getValueType(0);
4321 // We can get here for a node like i32 = ISD::SHL i32, i64
4325 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
4326 "Unknown shift to lower!");
4328 // We only lower SRA, SRL of 1 here, all others use generic lowering.
4329 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
4330 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
4333 // If we are in thumb mode, we don't have RRX.
4334 if (ST->isThumb1Only()) return SDValue();
4336 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
4337 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
4338 DAG.getConstant(0, dl, MVT::i32));
4339 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
4340 DAG.getConstant(1, dl, MVT::i32));
4342 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
4343 // captures the result into a carry flag.
4344 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
4345 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), Hi);
4347 // The low part is an ARMISD::RRX operand, which shifts the carry in.
4348 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
4350 // Merge the pieces into a single i64 value.
4351 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
4354 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
4355 SDValue TmpOp0, TmpOp1;
4356 bool Invert = false;
4360 SDValue Op0 = Op.getOperand(0);
4361 SDValue Op1 = Op.getOperand(1);
4362 SDValue CC = Op.getOperand(2);
4363 EVT CmpVT = Op0.getValueType().changeVectorElementTypeToInteger();
4364 EVT VT = Op.getValueType();
4365 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
4368 if (Op1.getValueType().isFloatingPoint()) {
4369 switch (SetCCOpcode) {
4370 default: llvm_unreachable("Illegal FP comparison");
4372 case ISD::SETNE: Invert = true; // Fallthrough
4374 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
4376 case ISD::SETLT: Swap = true; // Fallthrough
4378 case ISD::SETGT: Opc = ARMISD::VCGT; break;
4380 case ISD::SETLE: Swap = true; // Fallthrough
4382 case ISD::SETGE: Opc = ARMISD::VCGE; break;
4383 case ISD::SETUGE: Swap = true; // Fallthrough
4384 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
4385 case ISD::SETUGT: Swap = true; // Fallthrough
4386 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
4387 case ISD::SETUEQ: Invert = true; // Fallthrough
4389 // Expand this to (OLT | OGT).
4393 Op0 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp1, TmpOp0);
4394 Op1 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp0, TmpOp1);
4396 case ISD::SETUO: Invert = true; // Fallthrough
4398 // Expand this to (OLT | OGE).
4402 Op0 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp1, TmpOp0);
4403 Op1 = DAG.getNode(ARMISD::VCGE, dl, CmpVT, TmpOp0, TmpOp1);
4407 // Integer comparisons.
4408 switch (SetCCOpcode) {
4409 default: llvm_unreachable("Illegal integer comparison");
4410 case ISD::SETNE: Invert = true;
4411 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
4412 case ISD::SETLT: Swap = true;
4413 case ISD::SETGT: Opc = ARMISD::VCGT; break;
4414 case ISD::SETLE: Swap = true;
4415 case ISD::SETGE: Opc = ARMISD::VCGE; break;
4416 case ISD::SETULT: Swap = true;
4417 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
4418 case ISD::SETULE: Swap = true;
4419 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
4422 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
4423 if (Opc == ARMISD::VCEQ) {
4426 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
4428 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
4431 // Ignore bitconvert.
4432 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST)
4433 AndOp = AndOp.getOperand(0);
4435 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
4437 Op0 = DAG.getNode(ISD::BITCAST, dl, CmpVT, AndOp.getOperand(0));
4438 Op1 = DAG.getNode(ISD::BITCAST, dl, CmpVT, AndOp.getOperand(1));
4445 std::swap(Op0, Op1);
4447 // If one of the operands is a constant vector zero, attempt to fold the
4448 // comparison to a specialized compare-against-zero form.
4450 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
4452 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) {
4453 if (Opc == ARMISD::VCGE)
4454 Opc = ARMISD::VCLEZ;
4455 else if (Opc == ARMISD::VCGT)
4456 Opc = ARMISD::VCLTZ;
4461 if (SingleOp.getNode()) {
4464 Result = DAG.getNode(ARMISD::VCEQZ, dl, CmpVT, SingleOp); break;
4466 Result = DAG.getNode(ARMISD::VCGEZ, dl, CmpVT, SingleOp); break;
4468 Result = DAG.getNode(ARMISD::VCLEZ, dl, CmpVT, SingleOp); break;
4470 Result = DAG.getNode(ARMISD::VCGTZ, dl, CmpVT, SingleOp); break;
4472 Result = DAG.getNode(ARMISD::VCLTZ, dl, CmpVT, SingleOp); break;
4474 Result = DAG.getNode(Opc, dl, CmpVT, Op0, Op1);
4477 Result = DAG.getNode(Opc, dl, CmpVT, Op0, Op1);
4480 Result = DAG.getSExtOrTrunc(Result, dl, VT);
4483 Result = DAG.getNOT(dl, Result, VT);
4488 /// isNEONModifiedImm - Check if the specified splat value corresponds to a
4489 /// valid vector constant for a NEON instruction with a "modified immediate"
4490 /// operand (e.g., VMOV). If so, return the encoded value.
4491 static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
4492 unsigned SplatBitSize, SelectionDAG &DAG,
4493 SDLoc dl, EVT &VT, bool is128Bits,
4494 NEONModImmType type) {
4495 unsigned OpCmode, Imm;
4497 // SplatBitSize is set to the smallest size that splats the vector, so a
4498 // zero vector will always have SplatBitSize == 8. However, NEON modified
4499 // immediate instructions others than VMOV do not support the 8-bit encoding
4500 // of a zero vector, and the default encoding of zero is supposed to be the
4505 switch (SplatBitSize) {
4507 if (type != VMOVModImm)
4509 // Any 1-byte value is OK. Op=0, Cmode=1110.
4510 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
4513 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
4517 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
4518 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
4519 if ((SplatBits & ~0xff) == 0) {
4520 // Value = 0x00nn: Op=x, Cmode=100x.
4525 if ((SplatBits & ~0xff00) == 0) {
4526 // Value = 0xnn00: Op=x, Cmode=101x.
4528 Imm = SplatBits >> 8;
4534 // NEON's 32-bit VMOV supports splat values where:
4535 // * only one byte is nonzero, or
4536 // * the least significant byte is 0xff and the second byte is nonzero, or
4537 // * the least significant 2 bytes are 0xff and the third is nonzero.
4538 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
4539 if ((SplatBits & ~0xff) == 0) {
4540 // Value = 0x000000nn: Op=x, Cmode=000x.
4545 if ((SplatBits & ~0xff00) == 0) {
4546 // Value = 0x0000nn00: Op=x, Cmode=001x.
4548 Imm = SplatBits >> 8;
4551 if ((SplatBits & ~0xff0000) == 0) {
4552 // Value = 0x00nn0000: Op=x, Cmode=010x.
4554 Imm = SplatBits >> 16;
4557 if ((SplatBits & ~0xff000000) == 0) {
4558 // Value = 0xnn000000: Op=x, Cmode=011x.
4560 Imm = SplatBits >> 24;
4564 // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC
4565 if (type == OtherModImm) return SDValue();
4567 if ((SplatBits & ~0xffff) == 0 &&
4568 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
4569 // Value = 0x0000nnff: Op=x, Cmode=1100.
4571 Imm = SplatBits >> 8;
4575 if ((SplatBits & ~0xffffff) == 0 &&
4576 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
4577 // Value = 0x00nnffff: Op=x, Cmode=1101.
4579 Imm = SplatBits >> 16;
4583 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
4584 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
4585 // VMOV.I32. A (very) minor optimization would be to replicate the value
4586 // and fall through here to test for a valid 64-bit splat. But, then the
4587 // caller would also need to check and handle the change in size.
4591 if (type != VMOVModImm)
4593 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
4594 uint64_t BitMask = 0xff;
4596 unsigned ImmMask = 1;
4598 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
4599 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
4602 } else if ((SplatBits & BitMask) != 0) {
4609 if (DAG.getTargetLoweringInfo().isBigEndian())
4610 // swap higher and lower 32 bit word
4611 Imm = ((Imm & 0xf) << 4) | ((Imm & 0xf0) >> 4);
4613 // Op=1, Cmode=1110.
4615 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
4620 llvm_unreachable("unexpected size for isNEONModifiedImm");
4623 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
4624 return DAG.getTargetConstant(EncodedVal, dl, MVT::i32);
4627 SDValue ARMTargetLowering::LowerConstantFP(SDValue Op, SelectionDAG &DAG,
4628 const ARMSubtarget *ST) const {
4632 bool IsDouble = Op.getValueType() == MVT::f64;
4633 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Op);
4635 // Use the default (constant pool) lowering for double constants when we have
4637 if (IsDouble && Subtarget->isFPOnlySP())
4640 // Try splatting with a VMOV.f32...
4641 APFloat FPVal = CFP->getValueAPF();
4642 int ImmVal = IsDouble ? ARM_AM::getFP64Imm(FPVal) : ARM_AM::getFP32Imm(FPVal);
4645 if (IsDouble || !ST->useNEONForSinglePrecisionFP()) {
4646 // We have code in place to select a valid ConstantFP already, no need to
4651 // It's a float and we are trying to use NEON operations where
4652 // possible. Lower it to a splat followed by an extract.
4654 SDValue NewVal = DAG.getTargetConstant(ImmVal, DL, MVT::i32);
4655 SDValue VecConstant = DAG.getNode(ARMISD::VMOVFPIMM, DL, MVT::v2f32,
4657 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecConstant,
4658 DAG.getConstant(0, DL, MVT::i32));
4661 // The rest of our options are NEON only, make sure that's allowed before
4663 if (!ST->hasNEON() || (!IsDouble && !ST->useNEONForSinglePrecisionFP()))
4667 uint64_t iVal = FPVal.bitcastToAPInt().getZExtValue();
4669 // It wouldn't really be worth bothering for doubles except for one very
4670 // important value, which does happen to match: 0.0. So make sure we don't do
4672 if (IsDouble && (iVal & 0xffffffff) != (iVal >> 32))
4675 // Try a VMOV.i32 (FIXME: i8, i16, or i64 could work too).
4676 SDValue NewVal = isNEONModifiedImm(iVal & 0xffffffffU, 0, 32, DAG, SDLoc(Op),
4677 VMovVT, false, VMOVModImm);
4678 if (NewVal != SDValue()) {
4680 SDValue VecConstant = DAG.getNode(ARMISD::VMOVIMM, DL, VMovVT,
4683 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant);
4685 // It's a float: cast and extract a vector element.
4686 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32,
4688 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant,
4689 DAG.getConstant(0, DL, MVT::i32));
4692 // Finally, try a VMVN.i32
4693 NewVal = isNEONModifiedImm(~iVal & 0xffffffffU, 0, 32, DAG, SDLoc(Op), VMovVT,
4695 if (NewVal != SDValue()) {
4697 SDValue VecConstant = DAG.getNode(ARMISD::VMVNIMM, DL, VMovVT, NewVal);
4700 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant);
4702 // It's a float: cast and extract a vector element.
4703 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32,
4705 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant,
4706 DAG.getConstant(0, DL, MVT::i32));
4712 // check if an VEXT instruction can handle the shuffle mask when the
4713 // vector sources of the shuffle are the same.
4714 static bool isSingletonVEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
4715 unsigned NumElts = VT.getVectorNumElements();
4717 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4723 // If this is a VEXT shuffle, the immediate value is the index of the first
4724 // element. The other shuffle indices must be the successive elements after
4726 unsigned ExpectedElt = Imm;
4727 for (unsigned i = 1; i < NumElts; ++i) {
4728 // Increment the expected index. If it wraps around, just follow it
4729 // back to index zero and keep going.
4731 if (ExpectedElt == NumElts)
4734 if (M[i] < 0) continue; // ignore UNDEF indices
4735 if (ExpectedElt != static_cast<unsigned>(M[i]))
4743 static bool isVEXTMask(ArrayRef<int> M, EVT VT,
4744 bool &ReverseVEXT, unsigned &Imm) {
4745 unsigned NumElts = VT.getVectorNumElements();
4746 ReverseVEXT = false;
4748 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4754 // If this is a VEXT shuffle, the immediate value is the index of the first
4755 // element. The other shuffle indices must be the successive elements after
4757 unsigned ExpectedElt = Imm;
4758 for (unsigned i = 1; i < NumElts; ++i) {
4759 // Increment the expected index. If it wraps around, it may still be
4760 // a VEXT but the source vectors must be swapped.
4762 if (ExpectedElt == NumElts * 2) {
4767 if (M[i] < 0) continue; // ignore UNDEF indices
4768 if (ExpectedElt != static_cast<unsigned>(M[i]))
4772 // Adjust the index value if the source operands will be swapped.
4779 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
4780 /// instruction with the specified blocksize. (The order of the elements
4781 /// within each block of the vector is reversed.)
4782 static bool isVREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
4783 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
4784 "Only possible block sizes for VREV are: 16, 32, 64");
4786 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4790 unsigned NumElts = VT.getVectorNumElements();
4791 unsigned BlockElts = M[0] + 1;
4792 // If the first shuffle index is UNDEF, be optimistic.
4794 BlockElts = BlockSize / EltSz;
4796 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
4799 for (unsigned i = 0; i < NumElts; ++i) {
4800 if (M[i] < 0) continue; // ignore UNDEF indices
4801 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
4808 static bool isVTBLMask(ArrayRef<int> M, EVT VT) {
4809 // We can handle <8 x i8> vector shuffles. If the index in the mask is out of
4810 // range, then 0 is placed into the resulting vector. So pretty much any mask
4811 // of 8 elements can work here.
4812 return VT == MVT::v8i8 && M.size() == 8;
4815 static bool isVTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4816 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4820 unsigned NumElts = VT.getVectorNumElements();
4821 WhichResult = (M[0] == 0 ? 0 : 1);
4822 for (unsigned i = 0; i < NumElts; i += 2) {
4823 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
4824 (M[i+1] >= 0 && (unsigned) M[i+1] != i + NumElts + WhichResult))
4830 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
4831 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4832 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
4833 static bool isVTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
4834 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4838 unsigned NumElts = VT.getVectorNumElements();
4839 WhichResult = (M[0] == 0 ? 0 : 1);
4840 for (unsigned i = 0; i < NumElts; i += 2) {
4841 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
4842 (M[i+1] >= 0 && (unsigned) M[i+1] != i + WhichResult))
4848 static bool isVUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4849 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4853 unsigned NumElts = VT.getVectorNumElements();
4854 WhichResult = (M[0] == 0 ? 0 : 1);
4855 for (unsigned i = 0; i != NumElts; ++i) {
4856 if (M[i] < 0) continue; // ignore UNDEF indices
4857 if ((unsigned) M[i] != 2 * i + WhichResult)
4861 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
4862 if (VT.is64BitVector() && EltSz == 32)
4868 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
4869 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4870 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
4871 static bool isVUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
4872 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4876 unsigned Half = VT.getVectorNumElements() / 2;
4877 WhichResult = (M[0] == 0 ? 0 : 1);
4878 for (unsigned j = 0; j != 2; ++j) {
4879 unsigned Idx = WhichResult;
4880 for (unsigned i = 0; i != Half; ++i) {
4881 int MIdx = M[i + j * Half];
4882 if (MIdx >= 0 && (unsigned) MIdx != Idx)
4888 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
4889 if (VT.is64BitVector() && EltSz == 32)
4895 static bool isVZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4896 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4900 unsigned NumElts = VT.getVectorNumElements();
4901 WhichResult = (M[0] == 0 ? 0 : 1);
4902 unsigned Idx = WhichResult * NumElts / 2;
4903 for (unsigned i = 0; i != NumElts; i += 2) {
4904 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
4905 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts))
4910 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
4911 if (VT.is64BitVector() && EltSz == 32)
4917 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
4918 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4919 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
4920 static bool isVZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
4921 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4925 unsigned NumElts = VT.getVectorNumElements();
4926 WhichResult = (M[0] == 0 ? 0 : 1);
4927 unsigned Idx = WhichResult * NumElts / 2;
4928 for (unsigned i = 0; i != NumElts; i += 2) {
4929 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
4930 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx))
4935 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
4936 if (VT.is64BitVector() && EltSz == 32)
4942 /// \return true if this is a reverse operation on an vector.
4943 static bool isReverseMask(ArrayRef<int> M, EVT VT) {
4944 unsigned NumElts = VT.getVectorNumElements();
4945 // Make sure the mask has the right size.
4946 if (NumElts != M.size())
4949 // Look for <15, ..., 3, -1, 1, 0>.
4950 for (unsigned i = 0; i != NumElts; ++i)
4951 if (M[i] >= 0 && M[i] != (int) (NumElts - 1 - i))
4957 // If N is an integer constant that can be moved into a register in one
4958 // instruction, return an SDValue of such a constant (will become a MOV
4959 // instruction). Otherwise return null.
4960 static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG,
4961 const ARMSubtarget *ST, SDLoc dl) {
4963 if (!isa<ConstantSDNode>(N))
4965 Val = cast<ConstantSDNode>(N)->getZExtValue();
4967 if (ST->isThumb1Only()) {
4968 if (Val <= 255 || ~Val <= 255)
4969 return DAG.getConstant(Val, dl, MVT::i32);
4971 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1)
4972 return DAG.getConstant(Val, dl, MVT::i32);
4977 // If this is a case we can't handle, return null and let the default
4978 // expansion code take care of it.
4979 SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
4980 const ARMSubtarget *ST) const {
4981 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
4983 EVT VT = Op.getValueType();
4985 APInt SplatBits, SplatUndef;
4986 unsigned SplatBitSize;
4988 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
4989 if (SplatBitSize <= 64) {
4990 // Check if an immediate VMOV works.
4992 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
4993 SplatUndef.getZExtValue(), SplatBitSize,
4994 DAG, dl, VmovVT, VT.is128BitVector(),
4996 if (Val.getNode()) {
4997 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
4998 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
5001 // Try an immediate VMVN.
5002 uint64_t NegatedImm = (~SplatBits).getZExtValue();
5003 Val = isNEONModifiedImm(NegatedImm,
5004 SplatUndef.getZExtValue(), SplatBitSize,
5005 DAG, dl, VmovVT, VT.is128BitVector(),
5007 if (Val.getNode()) {
5008 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
5009 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
5012 // Use vmov.f32 to materialize other v2f32 and v4f32 splats.
5013 if ((VT == MVT::v2f32 || VT == MVT::v4f32) && SplatBitSize == 32) {
5014 int ImmVal = ARM_AM::getFP32Imm(SplatBits);
5016 SDValue Val = DAG.getTargetConstant(ImmVal, dl, MVT::i32);
5017 return DAG.getNode(ARMISD::VMOVFPIMM, dl, VT, Val);
5023 // Scan through the operands to see if only one value is used.
5025 // As an optimisation, even if more than one value is used it may be more
5026 // profitable to splat with one value then change some lanes.
5028 // Heuristically we decide to do this if the vector has a "dominant" value,
5029 // defined as splatted to more than half of the lanes.
5030 unsigned NumElts = VT.getVectorNumElements();
5031 bool isOnlyLowElement = true;
5032 bool usesOnlyOneValue = true;
5033 bool hasDominantValue = false;
5034 bool isConstant = true;
5036 // Map of the number of times a particular SDValue appears in the
5038 DenseMap<SDValue, unsigned> ValueCounts;
5040 for (unsigned i = 0; i < NumElts; ++i) {
5041 SDValue V = Op.getOperand(i);
5042 if (V.getOpcode() == ISD::UNDEF)
5045 isOnlyLowElement = false;
5046 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
5049 ValueCounts.insert(std::make_pair(V, 0));
5050 unsigned &Count = ValueCounts[V];
5052 // Is this value dominant? (takes up more than half of the lanes)
5053 if (++Count > (NumElts / 2)) {
5054 hasDominantValue = true;
5058 if (ValueCounts.size() != 1)
5059 usesOnlyOneValue = false;
5060 if (!Value.getNode() && ValueCounts.size() > 0)
5061 Value = ValueCounts.begin()->first;
5063 if (ValueCounts.size() == 0)
5064 return DAG.getUNDEF(VT);
5066 // Loads are better lowered with insert_vector_elt/ARMISD::BUILD_VECTOR.
5067 // Keep going if we are hitting this case.
5068 if (isOnlyLowElement && !ISD::isNormalLoad(Value.getNode()))
5069 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
5071 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5073 // Use VDUP for non-constant splats. For f32 constant splats, reduce to
5074 // i32 and try again.
5075 if (hasDominantValue && EltSize <= 32) {
5079 // If we are VDUPing a value that comes directly from a vector, that will
5080 // cause an unnecessary move to and from a GPR, where instead we could
5081 // just use VDUPLANE. We can only do this if the lane being extracted
5082 // is at a constant index, as the VDUP from lane instructions only have
5083 // constant-index forms.
5084 if (Value->getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5085 isa<ConstantSDNode>(Value->getOperand(1))) {
5086 // We need to create a new undef vector to use for the VDUPLANE if the
5087 // size of the vector from which we get the value is different than the
5088 // size of the vector that we need to create. We will insert the element
5089 // such that the register coalescer will remove unnecessary copies.
5090 if (VT != Value->getOperand(0).getValueType()) {
5091 ConstantSDNode *constIndex;
5092 constIndex = dyn_cast<ConstantSDNode>(Value->getOperand(1));
5093 assert(constIndex && "The index is not a constant!");
5094 unsigned index = constIndex->getAPIntValue().getLimitedValue() %
5095 VT.getVectorNumElements();
5096 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT,
5097 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DAG.getUNDEF(VT),
5098 Value, DAG.getConstant(index, dl, MVT::i32)),
5099 DAG.getConstant(index, dl, MVT::i32));
5101 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT,
5102 Value->getOperand(0), Value->getOperand(1));
5104 N = DAG.getNode(ARMISD::VDUP, dl, VT, Value);
5106 if (!usesOnlyOneValue) {
5107 // The dominant value was splatted as 'N', but we now have to insert
5108 // all differing elements.
5109 for (unsigned I = 0; I < NumElts; ++I) {
5110 if (Op.getOperand(I) == Value)
5112 SmallVector<SDValue, 3> Ops;
5114 Ops.push_back(Op.getOperand(I));
5115 Ops.push_back(DAG.getConstant(I, dl, MVT::i32));
5116 N = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Ops);
5121 if (VT.getVectorElementType().isFloatingPoint()) {
5122 SmallVector<SDValue, 8> Ops;
5123 for (unsigned i = 0; i < NumElts; ++i)
5124 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32,
5126 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
5127 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
5128 Val = LowerBUILD_VECTOR(Val, DAG, ST);
5130 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5132 if (usesOnlyOneValue) {
5133 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
5134 if (isConstant && Val.getNode())
5135 return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
5139 // If all elements are constants and the case above didn't get hit, fall back
5140 // to the default expansion, which will generate a load from the constant
5145 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
5147 SDValue shuffle = ReconstructShuffle(Op, DAG);
5148 if (shuffle != SDValue())
5152 // Vectors with 32- or 64-bit elements can be built by directly assigning
5153 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
5154 // will be legalized.
5155 if (EltSize >= 32) {
5156 // Do the expansion with floating-point types, since that is what the VFP
5157 // registers are defined to use, and since i64 is not legal.
5158 EVT EltVT = EVT::getFloatingPointVT(EltSize);
5159 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
5160 SmallVector<SDValue, 8> Ops;
5161 for (unsigned i = 0; i < NumElts; ++i)
5162 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i)));
5163 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops);
5164 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5167 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
5168 // know the default expansion would otherwise fall back on something even
5169 // worse. For a vector with one or two non-undef values, that's
5170 // scalar_to_vector for the elements followed by a shuffle (provided the
5171 // shuffle is valid for the target) and materialization element by element
5172 // on the stack followed by a load for everything else.
5173 if (!isConstant && !usesOnlyOneValue) {
5174 SDValue Vec = DAG.getUNDEF(VT);
5175 for (unsigned i = 0 ; i < NumElts; ++i) {
5176 SDValue V = Op.getOperand(i);
5177 if (V.getOpcode() == ISD::UNDEF)
5179 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i32);
5180 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
5188 // Gather data to see if the operation can be modelled as a
5189 // shuffle in combination with VEXTs.
5190 SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
5191 SelectionDAG &DAG) const {
5193 EVT VT = Op.getValueType();
5194 unsigned NumElts = VT.getVectorNumElements();
5196 SmallVector<SDValue, 2> SourceVecs;
5197 SmallVector<unsigned, 2> MinElts;
5198 SmallVector<unsigned, 2> MaxElts;
5200 for (unsigned i = 0; i < NumElts; ++i) {
5201 SDValue V = Op.getOperand(i);
5202 if (V.getOpcode() == ISD::UNDEF)
5204 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
5205 // A shuffle can only come from building a vector from various
5206 // elements of other vectors.
5208 } else if (V.getOperand(0).getValueType().getVectorElementType() !=
5209 VT.getVectorElementType()) {
5210 // This code doesn't know how to handle shuffles where the vector
5211 // element types do not match (this happens because type legalization
5212 // promotes the return type of EXTRACT_VECTOR_ELT).
5213 // FIXME: It might be appropriate to extend this code to handle
5214 // mismatched types.
5218 // Record this extraction against the appropriate vector if possible...
5219 SDValue SourceVec = V.getOperand(0);
5220 // If the element number isn't a constant, we can't effectively
5221 // analyze what's going on.
5222 if (!isa<ConstantSDNode>(V.getOperand(1)))
5224 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
5225 bool FoundSource = false;
5226 for (unsigned j = 0; j < SourceVecs.size(); ++j) {
5227 if (SourceVecs[j] == SourceVec) {
5228 if (MinElts[j] > EltNo)
5230 if (MaxElts[j] < EltNo)
5237 // Or record a new source if not...
5239 SourceVecs.push_back(SourceVec);
5240 MinElts.push_back(EltNo);
5241 MaxElts.push_back(EltNo);
5245 // Currently only do something sane when at most two source vectors
5247 if (SourceVecs.size() > 2)
5250 SDValue ShuffleSrcs[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT) };
5251 int VEXTOffsets[2] = {0, 0};
5253 // This loop extracts the usage patterns of the source vectors
5254 // and prepares appropriate SDValues for a shuffle if possible.
5255 for (unsigned i = 0; i < SourceVecs.size(); ++i) {
5256 if (SourceVecs[i].getValueType() == VT) {
5257 // No VEXT necessary
5258 ShuffleSrcs[i] = SourceVecs[i];
5261 } else if (SourceVecs[i].getValueType().getVectorNumElements() < NumElts) {
5262 // It probably isn't worth padding out a smaller vector just to
5263 // break it down again in a shuffle.
5267 // Since only 64-bit and 128-bit vectors are legal on ARM and
5268 // we've eliminated the other cases...
5269 assert(SourceVecs[i].getValueType().getVectorNumElements() == 2*NumElts &&
5270 "unexpected vector sizes in ReconstructShuffle");
5272 if (MaxElts[i] - MinElts[i] >= NumElts) {
5273 // Span too large for a VEXT to cope
5277 if (MinElts[i] >= NumElts) {
5278 // The extraction can just take the second half
5279 VEXTOffsets[i] = NumElts;
5280 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
5282 DAG.getIntPtrConstant(NumElts, dl));
5283 } else if (MaxElts[i] < NumElts) {
5284 // The extraction can just take the first half
5286 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
5288 DAG.getIntPtrConstant(0, dl));
5290 // An actual VEXT is needed
5291 VEXTOffsets[i] = MinElts[i];
5292 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
5294 DAG.getIntPtrConstant(0, dl));
5295 SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
5297 DAG.getIntPtrConstant(NumElts, dl));
5298 ShuffleSrcs[i] = DAG.getNode(ARMISD::VEXT, dl, VT, VEXTSrc1, VEXTSrc2,
5299 DAG.getConstant(VEXTOffsets[i], dl,
5304 SmallVector<int, 8> Mask;
5306 for (unsigned i = 0; i < NumElts; ++i) {
5307 SDValue Entry = Op.getOperand(i);
5308 if (Entry.getOpcode() == ISD::UNDEF) {
5313 SDValue ExtractVec = Entry.getOperand(0);
5314 int ExtractElt = cast<ConstantSDNode>(Op.getOperand(i)
5315 .getOperand(1))->getSExtValue();
5316 if (ExtractVec == SourceVecs[0]) {
5317 Mask.push_back(ExtractElt - VEXTOffsets[0]);
5319 Mask.push_back(ExtractElt + NumElts - VEXTOffsets[1]);
5323 // Final check before we try to produce nonsense...
5324 if (isShuffleMaskLegal(Mask, VT))
5325 return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1],
5331 /// isShuffleMaskLegal - Targets can use this to indicate that they only
5332 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
5333 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
5334 /// are assumed to be legal.
5336 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
5338 if (VT.getVectorNumElements() == 4 &&
5339 (VT.is128BitVector() || VT.is64BitVector())) {
5340 unsigned PFIndexes[4];
5341 for (unsigned i = 0; i != 4; ++i) {
5345 PFIndexes[i] = M[i];
5348 // Compute the index in the perfect shuffle table.
5349 unsigned PFTableIndex =
5350 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5351 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5352 unsigned Cost = (PFEntry >> 30);
5359 unsigned Imm, WhichResult;
5361 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5362 return (EltSize >= 32 ||
5363 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
5364 isVREVMask(M, VT, 64) ||
5365 isVREVMask(M, VT, 32) ||
5366 isVREVMask(M, VT, 16) ||
5367 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
5368 isVTBLMask(M, VT) ||
5369 isVTRNMask(M, VT, WhichResult) ||
5370 isVUZPMask(M, VT, WhichResult) ||
5371 isVZIPMask(M, VT, WhichResult) ||
5372 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
5373 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
5374 isVZIP_v_undef_Mask(M, VT, WhichResult) ||
5375 ((VT == MVT::v8i16 || VT == MVT::v16i8) && isReverseMask(M, VT)));
5378 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5379 /// the specified operations to build the shuffle.
5380 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5381 SDValue RHS, SelectionDAG &DAG,
5383 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5384 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5385 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5388 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5397 OP_VUZPL, // VUZP, left result
5398 OP_VUZPR, // VUZP, right result
5399 OP_VZIPL, // VZIP, left result
5400 OP_VZIPR, // VZIP, right result
5401 OP_VTRNL, // VTRN, left result
5402 OP_VTRNR // VTRN, right result
5405 if (OpNum == OP_COPY) {
5406 if (LHSID == (1*9+2)*9+3) return LHS;
5407 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5411 SDValue OpLHS, OpRHS;
5412 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5413 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5414 EVT VT = OpLHS.getValueType();
5417 default: llvm_unreachable("Unknown shuffle opcode!");
5419 // VREV divides the vector in half and swaps within the half.
5420 if (VT.getVectorElementType() == MVT::i32 ||
5421 VT.getVectorElementType() == MVT::f32)
5422 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
5423 // vrev <4 x i16> -> VREV32
5424 if (VT.getVectorElementType() == MVT::i16)
5425 return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS);
5426 // vrev <4 x i8> -> VREV16
5427 assert(VT.getVectorElementType() == MVT::i8);
5428 return DAG.getNode(ARMISD::VREV16, dl, VT, OpLHS);
5433 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
5434 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, dl, MVT::i32));
5438 return DAG.getNode(ARMISD::VEXT, dl, VT,
5440 DAG.getConstant(OpNum - OP_VEXT1 + 1, dl, MVT::i32));
5443 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
5444 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
5447 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
5448 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
5451 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
5452 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
5456 static SDValue LowerVECTOR_SHUFFLEv8i8(SDValue Op,
5457 ArrayRef<int> ShuffleMask,
5458 SelectionDAG &DAG) {
5459 // Check to see if we can use the VTBL instruction.
5460 SDValue V1 = Op.getOperand(0);
5461 SDValue V2 = Op.getOperand(1);
5464 SmallVector<SDValue, 8> VTBLMask;
5465 for (ArrayRef<int>::iterator
5466 I = ShuffleMask.begin(), E = ShuffleMask.end(); I != E; ++I)
5467 VTBLMask.push_back(DAG.getConstant(*I, DL, MVT::i32));
5469 if (V2.getNode()->getOpcode() == ISD::UNDEF)
5470 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1,
5471 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, VTBLMask));
5473 return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2,
5474 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, VTBLMask));
5477 static SDValue LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(SDValue Op,
5478 SelectionDAG &DAG) {
5480 SDValue OpLHS = Op.getOperand(0);
5481 EVT VT = OpLHS.getValueType();
5483 assert((VT == MVT::v8i16 || VT == MVT::v16i8) &&
5484 "Expect an v8i16/v16i8 type");
5485 OpLHS = DAG.getNode(ARMISD::VREV64, DL, VT, OpLHS);
5486 // For a v16i8 type: After the VREV, we have got <8, ...15, 8, ..., 0>. Now,
5487 // extract the first 8 bytes into the top double word and the last 8 bytes
5488 // into the bottom double word. The v8i16 case is similar.
5489 unsigned ExtractNum = (VT == MVT::v16i8) ? 8 : 4;
5490 return DAG.getNode(ARMISD::VEXT, DL, VT, OpLHS, OpLHS,
5491 DAG.getConstant(ExtractNum, DL, MVT::i32));
5494 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
5495 SDValue V1 = Op.getOperand(0);
5496 SDValue V2 = Op.getOperand(1);
5498 EVT VT = Op.getValueType();
5499 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
5501 // Convert shuffles that are directly supported on NEON to target-specific
5502 // DAG nodes, instead of keeping them as shuffles and matching them again
5503 // during code selection. This is more efficient and avoids the possibility
5504 // of inconsistencies between legalization and selection.
5505 // FIXME: floating-point vectors should be canonicalized to integer vectors
5506 // of the same time so that they get CSEd properly.
5507 ArrayRef<int> ShuffleMask = SVN->getMask();
5509 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5510 if (EltSize <= 32) {
5511 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
5512 int Lane = SVN->getSplatIndex();
5513 // If this is undef splat, generate it via "just" vdup, if possible.
5514 if (Lane == -1) Lane = 0;
5516 // Test if V1 is a SCALAR_TO_VECTOR.
5517 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5518 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
5520 // Test if V1 is a BUILD_VECTOR which is equivalent to a SCALAR_TO_VECTOR
5521 // (and probably will turn into a SCALAR_TO_VECTOR once legalization
5523 if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
5524 !isa<ConstantSDNode>(V1.getOperand(0))) {
5525 bool IsScalarToVector = true;
5526 for (unsigned i = 1, e = V1.getNumOperands(); i != e; ++i)
5527 if (V1.getOperand(i).getOpcode() != ISD::UNDEF) {
5528 IsScalarToVector = false;
5531 if (IsScalarToVector)
5532 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
5534 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
5535 DAG.getConstant(Lane, dl, MVT::i32));
5540 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
5543 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
5544 DAG.getConstant(Imm, dl, MVT::i32));
5547 if (isVREVMask(ShuffleMask, VT, 64))
5548 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
5549 if (isVREVMask(ShuffleMask, VT, 32))
5550 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
5551 if (isVREVMask(ShuffleMask, VT, 16))
5552 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
5554 if (V2->getOpcode() == ISD::UNDEF &&
5555 isSingletonVEXTMask(ShuffleMask, VT, Imm)) {
5556 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V1,
5557 DAG.getConstant(Imm, dl, MVT::i32));
5560 // Check for Neon shuffles that modify both input vectors in place.
5561 // If both results are used, i.e., if there are two shuffles with the same
5562 // source operands and with masks corresponding to both results of one of
5563 // these operations, DAG memoization will ensure that a single node is
5564 // used for both shuffles.
5565 unsigned WhichResult;
5566 if (isVTRNMask(ShuffleMask, VT, WhichResult))
5567 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
5568 V1, V2).getValue(WhichResult);
5569 if (isVUZPMask(ShuffleMask, VT, WhichResult))
5570 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
5571 V1, V2).getValue(WhichResult);
5572 if (isVZIPMask(ShuffleMask, VT, WhichResult))
5573 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
5574 V1, V2).getValue(WhichResult);
5576 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
5577 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
5578 V1, V1).getValue(WhichResult);
5579 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
5580 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
5581 V1, V1).getValue(WhichResult);
5582 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
5583 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
5584 V1, V1).getValue(WhichResult);
5587 // If the shuffle is not directly supported and it has 4 elements, use
5588 // the PerfectShuffle-generated table to synthesize it from other shuffles.
5589 unsigned NumElts = VT.getVectorNumElements();
5591 unsigned PFIndexes[4];
5592 for (unsigned i = 0; i != 4; ++i) {
5593 if (ShuffleMask[i] < 0)
5596 PFIndexes[i] = ShuffleMask[i];
5599 // Compute the index in the perfect shuffle table.
5600 unsigned PFTableIndex =
5601 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5602 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5603 unsigned Cost = (PFEntry >> 30);
5606 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5609 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
5610 if (EltSize >= 32) {
5611 // Do the expansion with floating-point types, since that is what the VFP
5612 // registers are defined to use, and since i64 is not legal.
5613 EVT EltVT = EVT::getFloatingPointVT(EltSize);
5614 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
5615 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1);
5616 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2);
5617 SmallVector<SDValue, 8> Ops;
5618 for (unsigned i = 0; i < NumElts; ++i) {
5619 if (ShuffleMask[i] < 0)
5620 Ops.push_back(DAG.getUNDEF(EltVT));
5622 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
5623 ShuffleMask[i] < (int)NumElts ? V1 : V2,
5624 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
5627 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops);
5628 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5631 if ((VT == MVT::v8i16 || VT == MVT::v16i8) && isReverseMask(ShuffleMask, VT))
5632 return LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(Op, DAG);
5634 if (VT == MVT::v8i8) {
5635 SDValue NewOp = LowerVECTOR_SHUFFLEv8i8(Op, ShuffleMask, DAG);
5636 if (NewOp.getNode())
5643 static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
5644 // INSERT_VECTOR_ELT is legal only for immediate indexes.
5645 SDValue Lane = Op.getOperand(2);
5646 if (!isa<ConstantSDNode>(Lane))
5652 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
5653 // EXTRACT_VECTOR_ELT is legal only for immediate indexes.
5654 SDValue Lane = Op.getOperand(1);
5655 if (!isa<ConstantSDNode>(Lane))
5658 SDValue Vec = Op.getOperand(0);
5659 if (Op.getValueType() == MVT::i32 &&
5660 Vec.getValueType().getVectorElementType().getSizeInBits() < 32) {
5662 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
5668 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5669 // The only time a CONCAT_VECTORS operation can have legal types is when
5670 // two 64-bit vectors are concatenated to a 128-bit vector.
5671 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
5672 "unexpected CONCAT_VECTORS");
5674 SDValue Val = DAG.getUNDEF(MVT::v2f64);
5675 SDValue Op0 = Op.getOperand(0);
5676 SDValue Op1 = Op.getOperand(1);
5677 if (Op0.getOpcode() != ISD::UNDEF)
5678 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
5679 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0),
5680 DAG.getIntPtrConstant(0, dl));
5681 if (Op1.getOpcode() != ISD::UNDEF)
5682 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
5683 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1),
5684 DAG.getIntPtrConstant(1, dl));
5685 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val);
5688 /// isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each
5689 /// element has been zero/sign-extended, depending on the isSigned parameter,
5690 /// from an integer type half its size.
5691 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
5693 // A v2i64 BUILD_VECTOR will have been legalized to a BITCAST from v4i32.
5694 EVT VT = N->getValueType(0);
5695 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) {
5696 SDNode *BVN = N->getOperand(0).getNode();
5697 if (BVN->getValueType(0) != MVT::v4i32 ||
5698 BVN->getOpcode() != ISD::BUILD_VECTOR)
5700 unsigned LoElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
5701 unsigned HiElt = 1 - LoElt;
5702 ConstantSDNode *Lo0 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt));
5703 ConstantSDNode *Hi0 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt));
5704 ConstantSDNode *Lo1 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt+2));
5705 ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2));
5706 if (!Lo0 || !Hi0 || !Lo1 || !Hi1)
5709 if (Hi0->getSExtValue() == Lo0->getSExtValue() >> 32 &&
5710 Hi1->getSExtValue() == Lo1->getSExtValue() >> 32)
5713 if (Hi0->isNullValue() && Hi1->isNullValue())
5719 if (N->getOpcode() != ISD::BUILD_VECTOR)
5722 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
5723 SDNode *Elt = N->getOperand(i).getNode();
5724 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
5725 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5726 unsigned HalfSize = EltSize / 2;
5728 if (!isIntN(HalfSize, C->getSExtValue()))
5731 if (!isUIntN(HalfSize, C->getZExtValue()))
5742 /// isSignExtended - Check if a node is a vector value that is sign-extended
5743 /// or a constant BUILD_VECTOR with sign-extended elements.
5744 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
5745 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N))
5747 if (isExtendedBUILD_VECTOR(N, DAG, true))
5752 /// isZeroExtended - Check if a node is a vector value that is zero-extended
5753 /// or a constant BUILD_VECTOR with zero-extended elements.
5754 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
5755 if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N))
5757 if (isExtendedBUILD_VECTOR(N, DAG, false))
5762 static EVT getExtensionTo64Bits(const EVT &OrigVT) {
5763 if (OrigVT.getSizeInBits() >= 64)
5766 assert(OrigVT.isSimple() && "Expecting a simple value type");
5768 MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy;
5769 switch (OrigSimpleTy) {
5770 default: llvm_unreachable("Unexpected Vector Type");
5779 /// AddRequiredExtensionForVMULL - Add a sign/zero extension to extend the total
5780 /// value size to 64 bits. We need a 64-bit D register as an operand to VMULL.
5781 /// We insert the required extension here to get the vector to fill a D register.
5782 static SDValue AddRequiredExtensionForVMULL(SDValue N, SelectionDAG &DAG,
5785 unsigned ExtOpcode) {
5786 // The vector originally had a size of OrigTy. It was then extended to ExtTy.
5787 // We expect the ExtTy to be 128-bits total. If the OrigTy is less than
5788 // 64-bits we need to insert a new extension so that it will be 64-bits.
5789 assert(ExtTy.is128BitVector() && "Unexpected extension size");
5790 if (OrigTy.getSizeInBits() >= 64)
5793 // Must extend size to at least 64 bits to be used as an operand for VMULL.
5794 EVT NewVT = getExtensionTo64Bits(OrigTy);
5796 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N);
5799 /// SkipLoadExtensionForVMULL - return a load of the original vector size that
5800 /// does not do any sign/zero extension. If the original vector is less
5801 /// than 64 bits, an appropriate extension will be added after the load to
5802 /// reach a total size of 64 bits. We have to add the extension separately
5803 /// because ARM does not have a sign/zero extending load for vectors.
5804 static SDValue SkipLoadExtensionForVMULL(LoadSDNode *LD, SelectionDAG& DAG) {
5805 EVT ExtendedTy = getExtensionTo64Bits(LD->getMemoryVT());
5807 // The load already has the right type.
5808 if (ExtendedTy == LD->getMemoryVT())
5809 return DAG.getLoad(LD->getMemoryVT(), SDLoc(LD), LD->getChain(),
5810 LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(),
5811 LD->isNonTemporal(), LD->isInvariant(),
5812 LD->getAlignment());
5814 // We need to create a zextload/sextload. We cannot just create a load
5815 // followed by a zext/zext node because LowerMUL is also run during normal
5816 // operation legalization where we can't create illegal types.
5817 return DAG.getExtLoad(LD->getExtensionType(), SDLoc(LD), ExtendedTy,
5818 LD->getChain(), LD->getBasePtr(), LD->getPointerInfo(),
5819 LD->getMemoryVT(), LD->isVolatile(), LD->isInvariant(),
5820 LD->isNonTemporal(), LD->getAlignment());
5823 /// SkipExtensionForVMULL - For a node that is a SIGN_EXTEND, ZERO_EXTEND,
5824 /// extending load, or BUILD_VECTOR with extended elements, return the
5825 /// unextended value. The unextended vector should be 64 bits so that it can
5826 /// be used as an operand to a VMULL instruction. If the original vector size
5827 /// before extension is less than 64 bits we add a an extension to resize
5828 /// the vector to 64 bits.
5829 static SDValue SkipExtensionForVMULL(SDNode *N, SelectionDAG &DAG) {
5830 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
5831 return AddRequiredExtensionForVMULL(N->getOperand(0), DAG,
5832 N->getOperand(0)->getValueType(0),
5836 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
5837 return SkipLoadExtensionForVMULL(LD, DAG);
5839 // Otherwise, the value must be a BUILD_VECTOR. For v2i64, it will
5840 // have been legalized as a BITCAST from v4i32.
5841 if (N->getOpcode() == ISD::BITCAST) {
5842 SDNode *BVN = N->getOperand(0).getNode();
5843 assert(BVN->getOpcode() == ISD::BUILD_VECTOR &&
5844 BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR");
5845 unsigned LowElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
5846 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), MVT::v2i32,
5847 BVN->getOperand(LowElt), BVN->getOperand(LowElt+2));
5849 // Construct a new BUILD_VECTOR with elements truncated to half the size.
5850 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
5851 EVT VT = N->getValueType(0);
5852 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
5853 unsigned NumElts = VT.getVectorNumElements();
5854 MVT TruncVT = MVT::getIntegerVT(EltSize);
5855 SmallVector<SDValue, 8> Ops;
5857 for (unsigned i = 0; i != NumElts; ++i) {
5858 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
5859 const APInt &CInt = C->getAPIntValue();
5860 // Element types smaller than 32 bits are not legal, so use i32 elements.
5861 // The values are implicitly truncated so sext vs. zext doesn't matter.
5862 Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), dl, MVT::i32));
5864 return DAG.getNode(ISD::BUILD_VECTOR, dl,
5865 MVT::getVectorVT(TruncVT, NumElts), Ops);
5868 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
5869 unsigned Opcode = N->getOpcode();
5870 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
5871 SDNode *N0 = N->getOperand(0).getNode();
5872 SDNode *N1 = N->getOperand(1).getNode();
5873 return N0->hasOneUse() && N1->hasOneUse() &&
5874 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
5879 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
5880 unsigned Opcode = N->getOpcode();
5881 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
5882 SDNode *N0 = N->getOperand(0).getNode();
5883 SDNode *N1 = N->getOperand(1).getNode();
5884 return N0->hasOneUse() && N1->hasOneUse() &&
5885 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
5890 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
5891 // Multiplications are only custom-lowered for 128-bit vectors so that
5892 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
5893 EVT VT = Op.getValueType();
5894 assert(VT.is128BitVector() && VT.isInteger() &&
5895 "unexpected type for custom-lowering ISD::MUL");
5896 SDNode *N0 = Op.getOperand(0).getNode();
5897 SDNode *N1 = Op.getOperand(1).getNode();
5898 unsigned NewOpc = 0;
5900 bool isN0SExt = isSignExtended(N0, DAG);
5901 bool isN1SExt = isSignExtended(N1, DAG);
5902 if (isN0SExt && isN1SExt)
5903 NewOpc = ARMISD::VMULLs;
5905 bool isN0ZExt = isZeroExtended(N0, DAG);
5906 bool isN1ZExt = isZeroExtended(N1, DAG);
5907 if (isN0ZExt && isN1ZExt)
5908 NewOpc = ARMISD::VMULLu;
5909 else if (isN1SExt || isN1ZExt) {
5910 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
5911 // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
5912 if (isN1SExt && isAddSubSExt(N0, DAG)) {
5913 NewOpc = ARMISD::VMULLs;
5915 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
5916 NewOpc = ARMISD::VMULLu;
5918 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
5920 NewOpc = ARMISD::VMULLu;
5926 if (VT == MVT::v2i64)
5927 // Fall through to expand this. It is not legal.
5930 // Other vector multiplications are legal.
5935 // Legalize to a VMULL instruction.
5938 SDValue Op1 = SkipExtensionForVMULL(N1, DAG);
5940 Op0 = SkipExtensionForVMULL(N0, DAG);
5941 assert(Op0.getValueType().is64BitVector() &&
5942 Op1.getValueType().is64BitVector() &&
5943 "unexpected types for extended operands to VMULL");
5944 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
5947 // Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during
5948 // isel lowering to take advantage of no-stall back to back vmul + vmla.
5955 SDValue N00 = SkipExtensionForVMULL(N0->getOperand(0).getNode(), DAG);
5956 SDValue N01 = SkipExtensionForVMULL(N0->getOperand(1).getNode(), DAG);
5957 EVT Op1VT = Op1.getValueType();
5958 return DAG.getNode(N0->getOpcode(), DL, VT,
5959 DAG.getNode(NewOpc, DL, VT,
5960 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
5961 DAG.getNode(NewOpc, DL, VT,
5962 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
5966 LowerSDIV_v4i8(SDValue X, SDValue Y, SDLoc dl, SelectionDAG &DAG) {
5968 // float4 xf = vcvt_f32_s32(vmovl_s16(a.lo));
5969 // float4 yf = vcvt_f32_s32(vmovl_s16(b.lo));
5970 X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X);
5971 Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y);
5972 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X);
5973 Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y);
5974 // Get reciprocal estimate.
5975 // float4 recip = vrecpeq_f32(yf);
5976 Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
5977 DAG.getConstant(Intrinsic::arm_neon_vrecpe, dl, MVT::i32),
5979 // Because char has a smaller range than uchar, we can actually get away
5980 // without any newton steps. This requires that we use a weird bias
5981 // of 0xb000, however (again, this has been exhaustively tested).
5982 // float4 result = as_float4(as_int4(xf*recip) + 0xb000);
5983 X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y);
5984 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X);
5985 Y = DAG.getConstant(0xb000, dl, MVT::i32);
5986 Y = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Y, Y, Y, Y);
5987 X = DAG.getNode(ISD::ADD, dl, MVT::v4i32, X, Y);
5988 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X);
5989 // Convert back to short.
5990 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X);
5991 X = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, X);
5996 LowerSDIV_v4i16(SDValue N0, SDValue N1, SDLoc dl, SelectionDAG &DAG) {
5998 // Convert to float.
5999 // float4 yf = vcvt_f32_s32(vmovl_s16(y));
6000 // float4 xf = vcvt_f32_s32(vmovl_s16(x));
6001 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0);
6002 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1);
6003 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
6004 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
6006 // Use reciprocal estimate and one refinement step.
6007 // float4 recip = vrecpeq_f32(yf);
6008 // recip *= vrecpsq_f32(yf, recip);
6009 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6010 DAG.getConstant(Intrinsic::arm_neon_vrecpe, dl, MVT::i32),
6012 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6013 DAG.getConstant(Intrinsic::arm_neon_vrecps, dl, MVT::i32),
6015 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
6016 // Because short has a smaller range than ushort, we can actually get away
6017 // with only a single newton step. This requires that we use a weird bias
6018 // of 89, however (again, this has been exhaustively tested).
6019 // float4 result = as_float4(as_int4(xf*recip) + 0x89);
6020 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
6021 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
6022 N1 = DAG.getConstant(0x89, dl, MVT::i32);
6023 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
6024 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
6025 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
6026 // Convert back to integer and return.
6027 // return vmovn_s32(vcvt_s32_f32(result));
6028 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
6029 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
6033 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
6034 EVT VT = Op.getValueType();
6035 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
6036 "unexpected type for custom-lowering ISD::SDIV");
6039 SDValue N0 = Op.getOperand(0);
6040 SDValue N1 = Op.getOperand(1);
6043 if (VT == MVT::v8i8) {
6044 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0);
6045 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1);
6047 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
6048 DAG.getIntPtrConstant(4, dl));
6049 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
6050 DAG.getIntPtrConstant(4, dl));
6051 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
6052 DAG.getIntPtrConstant(0, dl));
6053 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
6054 DAG.getIntPtrConstant(0, dl));
6056 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16
6057 N2 = LowerSDIV_v4i8(N2, N3, dl, DAG); // v4i16
6059 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
6060 N0 = LowerCONCAT_VECTORS(N0, DAG);
6062 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0);
6065 return LowerSDIV_v4i16(N0, N1, dl, DAG);
6068 static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG) {
6069 EVT VT = Op.getValueType();
6070 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
6071 "unexpected type for custom-lowering ISD::UDIV");
6074 SDValue N0 = Op.getOperand(0);
6075 SDValue N1 = Op.getOperand(1);
6078 if (VT == MVT::v8i8) {
6079 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0);
6080 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1);
6082 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
6083 DAG.getIntPtrConstant(4, dl));
6084 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
6085 DAG.getIntPtrConstant(4, dl));
6086 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
6087 DAG.getIntPtrConstant(0, dl));
6088 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
6089 DAG.getIntPtrConstant(0, dl));
6091 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16
6092 N2 = LowerSDIV_v4i16(N2, N3, dl, DAG); // v4i16
6094 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
6095 N0 = LowerCONCAT_VECTORS(N0, DAG);
6097 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8,
6098 DAG.getConstant(Intrinsic::arm_neon_vqmovnsu, dl,
6104 // v4i16 sdiv ... Convert to float.
6105 // float4 yf = vcvt_f32_s32(vmovl_u16(y));
6106 // float4 xf = vcvt_f32_s32(vmovl_u16(x));
6107 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0);
6108 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1);
6109 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
6110 SDValue BN1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
6112 // Use reciprocal estimate and two refinement steps.
6113 // float4 recip = vrecpeq_f32(yf);
6114 // recip *= vrecpsq_f32(yf, recip);
6115 // recip *= vrecpsq_f32(yf, recip);
6116 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6117 DAG.getConstant(Intrinsic::arm_neon_vrecpe, dl, MVT::i32),
6119 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6120 DAG.getConstant(Intrinsic::arm_neon_vrecps, dl, MVT::i32),
6122 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
6123 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6124 DAG.getConstant(Intrinsic::arm_neon_vrecps, dl, MVT::i32),
6126 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
6127 // Simply multiplying by the reciprocal estimate can leave us a few ulps
6128 // too low, so we add 2 ulps (exhaustive testing shows that this is enough,
6129 // and that it will never cause us to return an answer too large).
6130 // float4 result = as_float4(as_int4(xf*recip) + 2);
6131 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
6132 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
6133 N1 = DAG.getConstant(2, dl, MVT::i32);
6134 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
6135 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
6136 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
6137 // Convert back to integer and return.
6138 // return vmovn_u32(vcvt_s32_f32(result));
6139 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
6140 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
6144 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
6145 EVT VT = Op.getNode()->getValueType(0);
6146 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
6149 bool ExtraOp = false;
6150 switch (Op.getOpcode()) {
6151 default: llvm_unreachable("Invalid code");
6152 case ISD::ADDC: Opc = ARMISD::ADDC; break;
6153 case ISD::ADDE: Opc = ARMISD::ADDE; ExtraOp = true; break;
6154 case ISD::SUBC: Opc = ARMISD::SUBC; break;
6155 case ISD::SUBE: Opc = ARMISD::SUBE; ExtraOp = true; break;
6159 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
6161 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
6162 Op.getOperand(1), Op.getOperand(2));
6165 SDValue ARMTargetLowering::LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const {
6166 assert(Subtarget->isTargetDarwin());
6168 // For iOS, we want to call an alternative entry point: __sincos_stret,
6169 // return values are passed via sret.
6171 SDValue Arg = Op.getOperand(0);
6172 EVT ArgVT = Arg.getValueType();
6173 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
6175 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6176 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6178 // Pair of floats / doubles used to pass the result.
6179 StructType *RetTy = StructType::get(ArgTy, ArgTy, nullptr);
6181 // Create stack object for sret.
6182 const uint64_t ByteSize = TLI.getDataLayout()->getTypeAllocSize(RetTy);
6183 const unsigned StackAlign = TLI.getDataLayout()->getPrefTypeAlignment(RetTy);
6184 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign, false);
6185 SDValue SRet = DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
6191 Entry.Ty = RetTy->getPointerTo();
6192 Entry.isSExt = false;
6193 Entry.isZExt = false;
6194 Entry.isSRet = true;
6195 Args.push_back(Entry);
6199 Entry.isSExt = false;
6200 Entry.isZExt = false;
6201 Args.push_back(Entry);
6203 const char *LibcallName = (ArgVT == MVT::f64)
6204 ? "__sincos_stret" : "__sincosf_stret";
6205 SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy());
6207 TargetLowering::CallLoweringInfo CLI(DAG);
6208 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
6209 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()), Callee,
6211 .setDiscardResult();
6213 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
6215 SDValue LoadSin = DAG.getLoad(ArgVT, dl, CallResult.second, SRet,
6216 MachinePointerInfo(), false, false, false, 0);
6218 // Address of cos field.
6219 SDValue Add = DAG.getNode(ISD::ADD, dl, getPointerTy(), SRet,
6220 DAG.getIntPtrConstant(ArgVT.getStoreSize(), dl));
6221 SDValue LoadCos = DAG.getLoad(ArgVT, dl, LoadSin.getValue(1), Add,
6222 MachinePointerInfo(), false, false, false, 0);
6224 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
6225 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys,
6226 LoadSin.getValue(0), LoadCos.getValue(0));
6229 static SDValue LowerAtomicLoadStore(SDValue Op, SelectionDAG &DAG) {
6230 // Monotonic load/store is legal for all targets
6231 if (cast<AtomicSDNode>(Op)->getOrdering() <= Monotonic)
6234 // Acquire/Release load/store is not legal for targets without a
6235 // dmb or equivalent available.
6239 static void ReplaceREADCYCLECOUNTER(SDNode *N,
6240 SmallVectorImpl<SDValue> &Results,
6242 const ARMSubtarget *Subtarget) {
6244 SDValue Cycles32, OutChain;
6246 if (Subtarget->hasPerfMon()) {
6247 // Under Power Management extensions, the cycle-count is:
6248 // mrc p15, #0, <Rt>, c9, c13, #0
6249 SDValue Ops[] = { N->getOperand(0), // Chain
6250 DAG.getConstant(Intrinsic::arm_mrc, DL, MVT::i32),
6251 DAG.getConstant(15, DL, MVT::i32),
6252 DAG.getConstant(0, DL, MVT::i32),
6253 DAG.getConstant(9, DL, MVT::i32),
6254 DAG.getConstant(13, DL, MVT::i32),
6255 DAG.getConstant(0, DL, MVT::i32)
6258 Cycles32 = DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL,
6259 DAG.getVTList(MVT::i32, MVT::Other), Ops);
6260 OutChain = Cycles32.getValue(1);
6262 // Intrinsic is defined to return 0 on unsupported platforms. Technically
6263 // there are older ARM CPUs that have implementation-specific ways of
6264 // obtaining this information (FIXME!).
6265 Cycles32 = DAG.getConstant(0, DL, MVT::i32);
6266 OutChain = DAG.getEntryNode();
6270 SDValue Cycles64 = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64,
6271 Cycles32, DAG.getConstant(0, DL, MVT::i32));
6272 Results.push_back(Cycles64);
6273 Results.push_back(OutChain);
6276 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6277 switch (Op.getOpcode()) {
6278 default: llvm_unreachable("Don't know how to custom lower this!");
6279 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6280 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
6281 case ISD::GlobalAddress:
6282 switch (Subtarget->getTargetTriple().getObjectFormat()) {
6283 default: llvm_unreachable("unknown object format");
6285 return LowerGlobalAddressWindows(Op, DAG);
6287 return LowerGlobalAddressELF(Op, DAG);
6289 return LowerGlobalAddressDarwin(Op, DAG);
6291 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6292 case ISD::SELECT: return LowerSELECT(Op, DAG);
6293 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
6294 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
6295 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
6296 case ISD::VASTART: return LowerVASTART(Op, DAG);
6297 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG, Subtarget);
6298 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget);
6299 case ISD::SINT_TO_FP:
6300 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
6301 case ISD::FP_TO_SINT:
6302 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
6303 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
6304 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6305 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6306 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
6307 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
6308 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
6309 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
6311 case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG);
6314 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
6315 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
6316 case ISD::SRL_PARTS:
6317 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
6318 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
6319 case ISD::CTPOP: return LowerCTPOP(Op.getNode(), DAG, Subtarget);
6320 case ISD::SETCC: return LowerVSETCC(Op, DAG);
6321 case ISD::ConstantFP: return LowerConstantFP(Op, DAG, Subtarget);
6322 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
6323 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6324 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
6325 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
6326 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
6327 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6328 case ISD::MUL: return LowerMUL(Op, DAG);
6329 case ISD::SDIV: return LowerSDIV(Op, DAG);
6330 case ISD::UDIV: return LowerUDIV(Op, DAG);
6334 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
6339 return LowerXALUO(Op, DAG);
6340 case ISD::ATOMIC_LOAD:
6341 case ISD::ATOMIC_STORE: return LowerAtomicLoadStore(Op, DAG);
6342 case ISD::FSINCOS: return LowerFSINCOS(Op, DAG);
6344 case ISD::UDIVREM: return LowerDivRem(Op, DAG);
6345 case ISD::DYNAMIC_STACKALLOC:
6346 if (Subtarget->getTargetTriple().isWindowsItaniumEnvironment())
6347 return LowerDYNAMIC_STACKALLOC(Op, DAG);
6348 llvm_unreachable("Don't know how to custom lower this!");
6349 case ISD::FP_ROUND: return LowerFP_ROUND(Op, DAG);
6350 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
6354 /// ReplaceNodeResults - Replace the results of node with an illegal result
6355 /// type with new values built out of custom code.
6356 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
6357 SmallVectorImpl<SDValue>&Results,
6358 SelectionDAG &DAG) const {
6360 switch (N->getOpcode()) {
6362 llvm_unreachable("Don't know how to custom expand this!");
6364 Res = ExpandBITCAST(N, DAG);
6368 Res = Expand64BitShift(N, DAG, Subtarget);
6370 case ISD::READCYCLECOUNTER:
6371 ReplaceREADCYCLECOUNTER(N, Results, DAG, Subtarget);
6375 Results.push_back(Res);
6378 //===----------------------------------------------------------------------===//
6379 // ARM Scheduler Hooks
6380 //===----------------------------------------------------------------------===//
6382 /// SetupEntryBlockForSjLj - Insert code into the entry block that creates and
6383 /// registers the function context.
6384 void ARMTargetLowering::
6385 SetupEntryBlockForSjLj(MachineInstr *MI, MachineBasicBlock *MBB,
6386 MachineBasicBlock *DispatchBB, int FI) const {
6387 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
6388 DebugLoc dl = MI->getDebugLoc();
6389 MachineFunction *MF = MBB->getParent();
6390 MachineRegisterInfo *MRI = &MF->getRegInfo();
6391 MachineConstantPool *MCP = MF->getConstantPool();
6392 ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>();
6393 const Function *F = MF->getFunction();
6395 bool isThumb = Subtarget->isThumb();
6396 bool isThumb2 = Subtarget->isThumb2();
6398 unsigned PCLabelId = AFI->createPICLabelUId();
6399 unsigned PCAdj = (isThumb || isThumb2) ? 4 : 8;
6400 ARMConstantPoolValue *CPV =
6401 ARMConstantPoolMBB::Create(F->getContext(), DispatchBB, PCLabelId, PCAdj);
6402 unsigned CPI = MCP->getConstantPoolIndex(CPV, 4);
6404 const TargetRegisterClass *TRC = isThumb ? &ARM::tGPRRegClass
6405 : &ARM::GPRRegClass;
6407 // Grab constant pool and fixed stack memory operands.
6408 MachineMemOperand *CPMMO =
6409 MF->getMachineMemOperand(MachinePointerInfo::getConstantPool(),
6410 MachineMemOperand::MOLoad, 4, 4);
6412 MachineMemOperand *FIMMOSt =
6413 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
6414 MachineMemOperand::MOStore, 4, 4);
6416 // Load the address of the dispatch MBB into the jump buffer.
6418 // Incoming value: jbuf
6419 // ldr.n r5, LCPI1_1
6422 // str r5, [$jbuf, #+4] ; &jbuf[1]
6423 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6424 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2LDRpci), NewVReg1)
6425 .addConstantPoolIndex(CPI)
6426 .addMemOperand(CPMMO));
6427 // Set the low bit because of thumb mode.
6428 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6430 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2ORRri), NewVReg2)
6431 .addReg(NewVReg1, RegState::Kill)
6433 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6434 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg3)
6435 .addReg(NewVReg2, RegState::Kill)
6437 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2STRi12))
6438 .addReg(NewVReg3, RegState::Kill)
6440 .addImm(36) // &jbuf[1] :: pc
6441 .addMemOperand(FIMMOSt));
6442 } else if (isThumb) {
6443 // Incoming value: jbuf
6444 // ldr.n r1, LCPI1_4
6448 // add r2, $jbuf, #+4 ; &jbuf[1]
6450 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6451 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tLDRpci), NewVReg1)
6452 .addConstantPoolIndex(CPI)
6453 .addMemOperand(CPMMO));
6454 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6455 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg2)
6456 .addReg(NewVReg1, RegState::Kill)
6458 // Set the low bit because of thumb mode.
6459 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6460 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tMOVi8), NewVReg3)
6461 .addReg(ARM::CPSR, RegState::Define)
6463 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
6464 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tORR), NewVReg4)
6465 .addReg(ARM::CPSR, RegState::Define)
6466 .addReg(NewVReg2, RegState::Kill)
6467 .addReg(NewVReg3, RegState::Kill));
6468 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
6469 BuildMI(*MBB, MI, dl, TII->get(ARM::tADDframe), NewVReg5)
6471 .addImm(36); // &jbuf[1] :: pc
6472 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tSTRi))
6473 .addReg(NewVReg4, RegState::Kill)
6474 .addReg(NewVReg5, RegState::Kill)
6476 .addMemOperand(FIMMOSt));
6478 // Incoming value: jbuf
6481 // str r1, [$jbuf, #+4] ; &jbuf[1]
6482 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6483 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::LDRi12), NewVReg1)
6484 .addConstantPoolIndex(CPI)
6486 .addMemOperand(CPMMO));
6487 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6488 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::PICADD), NewVReg2)
6489 .addReg(NewVReg1, RegState::Kill)
6490 .addImm(PCLabelId));
6491 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::STRi12))
6492 .addReg(NewVReg2, RegState::Kill)
6494 .addImm(36) // &jbuf[1] :: pc
6495 .addMemOperand(FIMMOSt));
6499 void ARMTargetLowering::EmitSjLjDispatchBlock(MachineInstr *MI,
6500 MachineBasicBlock *MBB) const {
6501 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
6502 DebugLoc dl = MI->getDebugLoc();
6503 MachineFunction *MF = MBB->getParent();
6504 MachineRegisterInfo *MRI = &MF->getRegInfo();
6505 ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>();
6506 MachineFrameInfo *MFI = MF->getFrameInfo();
6507 int FI = MFI->getFunctionContextIndex();
6509 const TargetRegisterClass *TRC = Subtarget->isThumb() ? &ARM::tGPRRegClass
6510 : &ARM::GPRnopcRegClass;
6512 // Get a mapping of the call site numbers to all of the landing pads they're
6514 DenseMap<unsigned, SmallVector<MachineBasicBlock*, 2> > CallSiteNumToLPad;
6515 unsigned MaxCSNum = 0;
6516 MachineModuleInfo &MMI = MF->getMMI();
6517 for (MachineFunction::iterator BB = MF->begin(), E = MF->end(); BB != E;
6519 if (!BB->isLandingPad()) continue;
6521 // FIXME: We should assert that the EH_LABEL is the first MI in the landing
6523 for (MachineBasicBlock::iterator
6524 II = BB->begin(), IE = BB->end(); II != IE; ++II) {
6525 if (!II->isEHLabel()) continue;
6527 MCSymbol *Sym = II->getOperand(0).getMCSymbol();
6528 if (!MMI.hasCallSiteLandingPad(Sym)) continue;
6530 SmallVectorImpl<unsigned> &CallSiteIdxs = MMI.getCallSiteLandingPad(Sym);
6531 for (SmallVectorImpl<unsigned>::iterator
6532 CSI = CallSiteIdxs.begin(), CSE = CallSiteIdxs.end();
6533 CSI != CSE; ++CSI) {
6534 CallSiteNumToLPad[*CSI].push_back(BB);
6535 MaxCSNum = std::max(MaxCSNum, *CSI);
6541 // Get an ordered list of the machine basic blocks for the jump table.
6542 std::vector<MachineBasicBlock*> LPadList;
6543 SmallPtrSet<MachineBasicBlock*, 64> InvokeBBs;
6544 LPadList.reserve(CallSiteNumToLPad.size());
6545 for (unsigned I = 1; I <= MaxCSNum; ++I) {
6546 SmallVectorImpl<MachineBasicBlock*> &MBBList = CallSiteNumToLPad[I];
6547 for (SmallVectorImpl<MachineBasicBlock*>::iterator
6548 II = MBBList.begin(), IE = MBBList.end(); II != IE; ++II) {
6549 LPadList.push_back(*II);
6550 InvokeBBs.insert((*II)->pred_begin(), (*II)->pred_end());
6554 assert(!LPadList.empty() &&
6555 "No landing pad destinations for the dispatch jump table!");
6557 // Create the jump table and associated information.
6558 MachineJumpTableInfo *JTI =
6559 MF->getOrCreateJumpTableInfo(MachineJumpTableInfo::EK_Inline);
6560 unsigned MJTI = JTI->createJumpTableIndex(LPadList);
6561 unsigned UId = AFI->createJumpTableUId();
6562 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
6564 // Create the MBBs for the dispatch code.
6566 // Shove the dispatch's address into the return slot in the function context.
6567 MachineBasicBlock *DispatchBB = MF->CreateMachineBasicBlock();
6568 DispatchBB->setIsLandingPad();
6570 MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock();
6571 unsigned trap_opcode;
6572 if (Subtarget->isThumb())
6573 trap_opcode = ARM::tTRAP;
6575 trap_opcode = Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP;
6577 BuildMI(TrapBB, dl, TII->get(trap_opcode));
6578 DispatchBB->addSuccessor(TrapBB);
6580 MachineBasicBlock *DispContBB = MF->CreateMachineBasicBlock();
6581 DispatchBB->addSuccessor(DispContBB);
6584 MF->insert(MF->end(), DispatchBB);
6585 MF->insert(MF->end(), DispContBB);
6586 MF->insert(MF->end(), TrapBB);
6588 // Insert code into the entry block that creates and registers the function
6590 SetupEntryBlockForSjLj(MI, MBB, DispatchBB, FI);
6592 MachineMemOperand *FIMMOLd =
6593 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
6594 MachineMemOperand::MOLoad |
6595 MachineMemOperand::MOVolatile, 4, 4);
6597 MachineInstrBuilder MIB;
6598 MIB = BuildMI(DispatchBB, dl, TII->get(ARM::Int_eh_sjlj_dispatchsetup));
6600 const ARMBaseInstrInfo *AII = static_cast<const ARMBaseInstrInfo*>(TII);
6601 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
6603 // Add a register mask with no preserved registers. This results in all
6604 // registers being marked as clobbered.
6605 MIB.addRegMask(RI.getNoPreservedMask());
6607 unsigned NumLPads = LPadList.size();
6608 if (Subtarget->isThumb2()) {
6609 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6610 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2LDRi12), NewVReg1)
6613 .addMemOperand(FIMMOLd));
6615 if (NumLPads < 256) {
6616 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPri))
6618 .addImm(LPadList.size()));
6620 unsigned VReg1 = MRI->createVirtualRegister(TRC);
6621 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVi16), VReg1)
6622 .addImm(NumLPads & 0xFFFF));
6624 unsigned VReg2 = VReg1;
6625 if ((NumLPads & 0xFFFF0000) != 0) {
6626 VReg2 = MRI->createVirtualRegister(TRC);
6627 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVTi16), VReg2)
6629 .addImm(NumLPads >> 16));
6632 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPrr))
6637 BuildMI(DispatchBB, dl, TII->get(ARM::t2Bcc))
6642 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6643 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::t2LEApcrelJT),NewVReg3)
6644 .addJumpTableIndex(MJTI)
6647 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
6650 BuildMI(DispContBB, dl, TII->get(ARM::t2ADDrs), NewVReg4)
6651 .addReg(NewVReg3, RegState::Kill)
6653 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))));
6655 BuildMI(DispContBB, dl, TII->get(ARM::t2BR_JT))
6656 .addReg(NewVReg4, RegState::Kill)
6658 .addJumpTableIndex(MJTI)
6660 } else if (Subtarget->isThumb()) {
6661 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6662 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRspi), NewVReg1)
6665 .addMemOperand(FIMMOLd));
6667 if (NumLPads < 256) {
6668 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPi8))
6672 MachineConstantPool *ConstantPool = MF->getConstantPool();
6673 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
6674 const Constant *C = ConstantInt::get(Int32Ty, NumLPads);
6676 // MachineConstantPool wants an explicit alignment.
6677 unsigned Align = getDataLayout()->getPrefTypeAlignment(Int32Ty);
6679 Align = getDataLayout()->getTypeAllocSize(C->getType());
6680 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
6682 unsigned VReg1 = MRI->createVirtualRegister(TRC);
6683 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRpci))
6684 .addReg(VReg1, RegState::Define)
6685 .addConstantPoolIndex(Idx));
6686 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPr))
6691 BuildMI(DispatchBB, dl, TII->get(ARM::tBcc))
6696 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6697 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLSLri), NewVReg2)
6698 .addReg(ARM::CPSR, RegState::Define)
6702 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6703 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLEApcrelJT), NewVReg3)
6704 .addJumpTableIndex(MJTI)
6707 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
6708 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg4)
6709 .addReg(ARM::CPSR, RegState::Define)
6710 .addReg(NewVReg2, RegState::Kill)
6713 MachineMemOperand *JTMMOLd =
6714 MF->getMachineMemOperand(MachinePointerInfo::getJumpTable(),
6715 MachineMemOperand::MOLoad, 4, 4);
6717 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
6718 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLDRi), NewVReg5)
6719 .addReg(NewVReg4, RegState::Kill)
6721 .addMemOperand(JTMMOLd));
6723 unsigned NewVReg6 = NewVReg5;
6724 if (RelocM == Reloc::PIC_) {
6725 NewVReg6 = MRI->createVirtualRegister(TRC);
6726 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg6)
6727 .addReg(ARM::CPSR, RegState::Define)
6728 .addReg(NewVReg5, RegState::Kill)
6732 BuildMI(DispContBB, dl, TII->get(ARM::tBR_JTr))
6733 .addReg(NewVReg6, RegState::Kill)
6734 .addJumpTableIndex(MJTI)
6737 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6738 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRi12), NewVReg1)
6741 .addMemOperand(FIMMOLd));
6743 if (NumLPads < 256) {
6744 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPri))
6747 } else if (Subtarget->hasV6T2Ops() && isUInt<16>(NumLPads)) {
6748 unsigned VReg1 = MRI->createVirtualRegister(TRC);
6749 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVi16), VReg1)
6750 .addImm(NumLPads & 0xFFFF));
6752 unsigned VReg2 = VReg1;
6753 if ((NumLPads & 0xFFFF0000) != 0) {
6754 VReg2 = MRI->createVirtualRegister(TRC);
6755 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVTi16), VReg2)
6757 .addImm(NumLPads >> 16));
6760 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
6764 MachineConstantPool *ConstantPool = MF->getConstantPool();
6765 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
6766 const Constant *C = ConstantInt::get(Int32Ty, NumLPads);
6768 // MachineConstantPool wants an explicit alignment.
6769 unsigned Align = getDataLayout()->getPrefTypeAlignment(Int32Ty);
6771 Align = getDataLayout()->getTypeAllocSize(C->getType());
6772 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
6774 unsigned VReg1 = MRI->createVirtualRegister(TRC);
6775 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRcp))
6776 .addReg(VReg1, RegState::Define)
6777 .addConstantPoolIndex(Idx)
6779 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
6781 .addReg(VReg1, RegState::Kill));
6784 BuildMI(DispatchBB, dl, TII->get(ARM::Bcc))
6789 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6791 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::MOVsi), NewVReg3)
6793 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))));
6794 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
6795 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::LEApcrelJT), NewVReg4)
6796 .addJumpTableIndex(MJTI)
6799 MachineMemOperand *JTMMOLd =
6800 MF->getMachineMemOperand(MachinePointerInfo::getJumpTable(),
6801 MachineMemOperand::MOLoad, 4, 4);
6802 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
6804 BuildMI(DispContBB, dl, TII->get(ARM::LDRrs), NewVReg5)
6805 .addReg(NewVReg3, RegState::Kill)
6808 .addMemOperand(JTMMOLd));
6810 if (RelocM == Reloc::PIC_) {
6811 BuildMI(DispContBB, dl, TII->get(ARM::BR_JTadd))
6812 .addReg(NewVReg5, RegState::Kill)
6814 .addJumpTableIndex(MJTI)
6817 BuildMI(DispContBB, dl, TII->get(ARM::BR_JTr))
6818 .addReg(NewVReg5, RegState::Kill)
6819 .addJumpTableIndex(MJTI)
6824 // Add the jump table entries as successors to the MBB.
6825 SmallPtrSet<MachineBasicBlock*, 8> SeenMBBs;
6826 for (std::vector<MachineBasicBlock*>::iterator
6827 I = LPadList.begin(), E = LPadList.end(); I != E; ++I) {
6828 MachineBasicBlock *CurMBB = *I;
6829 if (SeenMBBs.insert(CurMBB).second)
6830 DispContBB->addSuccessor(CurMBB);
6833 // N.B. the order the invoke BBs are processed in doesn't matter here.
6834 const MCPhysReg *SavedRegs = RI.getCalleeSavedRegs(MF);
6835 SmallVector<MachineBasicBlock*, 64> MBBLPads;
6836 for (MachineBasicBlock *BB : InvokeBBs) {
6838 // Remove the landing pad successor from the invoke block and replace it
6839 // with the new dispatch block.
6840 SmallVector<MachineBasicBlock*, 4> Successors(BB->succ_begin(),
6842 while (!Successors.empty()) {
6843 MachineBasicBlock *SMBB = Successors.pop_back_val();
6844 if (SMBB->isLandingPad()) {
6845 BB->removeSuccessor(SMBB);
6846 MBBLPads.push_back(SMBB);
6850 BB->addSuccessor(DispatchBB);
6852 // Find the invoke call and mark all of the callee-saved registers as
6853 // 'implicit defined' so that they're spilled. This prevents code from
6854 // moving instructions to before the EH block, where they will never be
6856 for (MachineBasicBlock::reverse_iterator
6857 II = BB->rbegin(), IE = BB->rend(); II != IE; ++II) {
6858 if (!II->isCall()) continue;
6860 DenseMap<unsigned, bool> DefRegs;
6861 for (MachineInstr::mop_iterator
6862 OI = II->operands_begin(), OE = II->operands_end();
6864 if (!OI->isReg()) continue;
6865 DefRegs[OI->getReg()] = true;
6868 MachineInstrBuilder MIB(*MF, &*II);
6870 for (unsigned i = 0; SavedRegs[i] != 0; ++i) {
6871 unsigned Reg = SavedRegs[i];
6872 if (Subtarget->isThumb2() &&
6873 !ARM::tGPRRegClass.contains(Reg) &&
6874 !ARM::hGPRRegClass.contains(Reg))
6876 if (Subtarget->isThumb1Only() && !ARM::tGPRRegClass.contains(Reg))
6878 if (!Subtarget->isThumb() && !ARM::GPRRegClass.contains(Reg))
6881 MIB.addReg(Reg, RegState::ImplicitDefine | RegState::Dead);
6888 // Mark all former landing pads as non-landing pads. The dispatch is the only
6890 for (SmallVectorImpl<MachineBasicBlock*>::iterator
6891 I = MBBLPads.begin(), E = MBBLPads.end(); I != E; ++I)
6892 (*I)->setIsLandingPad(false);
6894 // The instruction is gone now.
6895 MI->eraseFromParent();
6899 MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
6900 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
6901 E = MBB->succ_end(); I != E; ++I)
6904 llvm_unreachable("Expecting a BB with two successors!");
6907 /// Return the load opcode for a given load size. If load size >= 8,
6908 /// neon opcode will be returned.
6909 static unsigned getLdOpcode(unsigned LdSize, bool IsThumb1, bool IsThumb2) {
6911 return LdSize == 16 ? ARM::VLD1q32wb_fixed
6912 : LdSize == 8 ? ARM::VLD1d32wb_fixed : 0;
6914 return LdSize == 4 ? ARM::tLDRi
6915 : LdSize == 2 ? ARM::tLDRHi
6916 : LdSize == 1 ? ARM::tLDRBi : 0;
6918 return LdSize == 4 ? ARM::t2LDR_POST
6919 : LdSize == 2 ? ARM::t2LDRH_POST
6920 : LdSize == 1 ? ARM::t2LDRB_POST : 0;
6921 return LdSize == 4 ? ARM::LDR_POST_IMM
6922 : LdSize == 2 ? ARM::LDRH_POST
6923 : LdSize == 1 ? ARM::LDRB_POST_IMM : 0;
6926 /// Return the store opcode for a given store size. If store size >= 8,
6927 /// neon opcode will be returned.
6928 static unsigned getStOpcode(unsigned StSize, bool IsThumb1, bool IsThumb2) {
6930 return StSize == 16 ? ARM::VST1q32wb_fixed
6931 : StSize == 8 ? ARM::VST1d32wb_fixed : 0;
6933 return StSize == 4 ? ARM::tSTRi
6934 : StSize == 2 ? ARM::tSTRHi
6935 : StSize == 1 ? ARM::tSTRBi : 0;
6937 return StSize == 4 ? ARM::t2STR_POST
6938 : StSize == 2 ? ARM::t2STRH_POST
6939 : StSize == 1 ? ARM::t2STRB_POST : 0;
6940 return StSize == 4 ? ARM::STR_POST_IMM
6941 : StSize == 2 ? ARM::STRH_POST
6942 : StSize == 1 ? ARM::STRB_POST_IMM : 0;
6945 /// Emit a post-increment load operation with given size. The instructions
6946 /// will be added to BB at Pos.
6947 static void emitPostLd(MachineBasicBlock *BB, MachineInstr *Pos,
6948 const TargetInstrInfo *TII, DebugLoc dl,
6949 unsigned LdSize, unsigned Data, unsigned AddrIn,
6950 unsigned AddrOut, bool IsThumb1, bool IsThumb2) {
6951 unsigned LdOpc = getLdOpcode(LdSize, IsThumb1, IsThumb2);
6952 assert(LdOpc != 0 && "Should have a load opcode");
6954 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
6955 .addReg(AddrOut, RegState::Define).addReg(AddrIn)
6957 } else if (IsThumb1) {
6958 // load + update AddrIn
6959 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
6960 .addReg(AddrIn).addImm(0));
6961 MachineInstrBuilder MIB =
6962 BuildMI(*BB, Pos, dl, TII->get(ARM::tADDi8), AddrOut);
6963 MIB = AddDefaultT1CC(MIB);
6964 MIB.addReg(AddrIn).addImm(LdSize);
6965 AddDefaultPred(MIB);
6966 } else if (IsThumb2) {
6967 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
6968 .addReg(AddrOut, RegState::Define).addReg(AddrIn)
6971 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
6972 .addReg(AddrOut, RegState::Define).addReg(AddrIn)
6973 .addReg(0).addImm(LdSize));
6977 /// Emit a post-increment store operation with given size. The instructions
6978 /// will be added to BB at Pos.
6979 static void emitPostSt(MachineBasicBlock *BB, MachineInstr *Pos,
6980 const TargetInstrInfo *TII, DebugLoc dl,
6981 unsigned StSize, unsigned Data, unsigned AddrIn,
6982 unsigned AddrOut, bool IsThumb1, bool IsThumb2) {
6983 unsigned StOpc = getStOpcode(StSize, IsThumb1, IsThumb2);
6984 assert(StOpc != 0 && "Should have a store opcode");
6986 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
6987 .addReg(AddrIn).addImm(0).addReg(Data));
6988 } else if (IsThumb1) {
6989 // store + update AddrIn
6990 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc)).addReg(Data)
6991 .addReg(AddrIn).addImm(0));
6992 MachineInstrBuilder MIB =
6993 BuildMI(*BB, Pos, dl, TII->get(ARM::tADDi8), AddrOut);
6994 MIB = AddDefaultT1CC(MIB);
6995 MIB.addReg(AddrIn).addImm(StSize);
6996 AddDefaultPred(MIB);
6997 } else if (IsThumb2) {
6998 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
6999 .addReg(Data).addReg(AddrIn).addImm(StSize));
7001 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
7002 .addReg(Data).addReg(AddrIn).addReg(0)
7008 ARMTargetLowering::EmitStructByval(MachineInstr *MI,
7009 MachineBasicBlock *BB) const {
7010 // This pseudo instruction has 3 operands: dst, src, size
7011 // We expand it to a loop if size > Subtarget->getMaxInlineSizeThreshold().
7012 // Otherwise, we will generate unrolled scalar copies.
7013 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
7014 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7015 MachineFunction::iterator It = BB;
7018 unsigned dest = MI->getOperand(0).getReg();
7019 unsigned src = MI->getOperand(1).getReg();
7020 unsigned SizeVal = MI->getOperand(2).getImm();
7021 unsigned Align = MI->getOperand(3).getImm();
7022 DebugLoc dl = MI->getDebugLoc();
7024 MachineFunction *MF = BB->getParent();
7025 MachineRegisterInfo &MRI = MF->getRegInfo();
7026 unsigned UnitSize = 0;
7027 const TargetRegisterClass *TRC = nullptr;
7028 const TargetRegisterClass *VecTRC = nullptr;
7030 bool IsThumb1 = Subtarget->isThumb1Only();
7031 bool IsThumb2 = Subtarget->isThumb2();
7035 } else if (Align & 2) {
7038 // Check whether we can use NEON instructions.
7039 if (!MF->getFunction()->hasFnAttribute(Attribute::NoImplicitFloat) &&
7040 Subtarget->hasNEON()) {
7041 if ((Align % 16 == 0) && SizeVal >= 16)
7043 else if ((Align % 8 == 0) && SizeVal >= 8)
7046 // Can't use NEON instructions.
7051 // Select the correct opcode and register class for unit size load/store
7052 bool IsNeon = UnitSize >= 8;
7053 TRC = (IsThumb1 || IsThumb2) ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
7055 VecTRC = UnitSize == 16 ? &ARM::DPairRegClass
7056 : UnitSize == 8 ? &ARM::DPRRegClass
7059 unsigned BytesLeft = SizeVal % UnitSize;
7060 unsigned LoopSize = SizeVal - BytesLeft;
7062 if (SizeVal <= Subtarget->getMaxInlineSizeThreshold()) {
7063 // Use LDR and STR to copy.
7064 // [scratch, srcOut] = LDR_POST(srcIn, UnitSize)
7065 // [destOut] = STR_POST(scratch, destIn, UnitSize)
7066 unsigned srcIn = src;
7067 unsigned destIn = dest;
7068 for (unsigned i = 0; i < LoopSize; i+=UnitSize) {
7069 unsigned srcOut = MRI.createVirtualRegister(TRC);
7070 unsigned destOut = MRI.createVirtualRegister(TRC);
7071 unsigned scratch = MRI.createVirtualRegister(IsNeon ? VecTRC : TRC);
7072 emitPostLd(BB, MI, TII, dl, UnitSize, scratch, srcIn, srcOut,
7073 IsThumb1, IsThumb2);
7074 emitPostSt(BB, MI, TII, dl, UnitSize, scratch, destIn, destOut,
7075 IsThumb1, IsThumb2);
7080 // Handle the leftover bytes with LDRB and STRB.
7081 // [scratch, srcOut] = LDRB_POST(srcIn, 1)
7082 // [destOut] = STRB_POST(scratch, destIn, 1)
7083 for (unsigned i = 0; i < BytesLeft; i++) {
7084 unsigned srcOut = MRI.createVirtualRegister(TRC);
7085 unsigned destOut = MRI.createVirtualRegister(TRC);
7086 unsigned scratch = MRI.createVirtualRegister(TRC);
7087 emitPostLd(BB, MI, TII, dl, 1, scratch, srcIn, srcOut,
7088 IsThumb1, IsThumb2);
7089 emitPostSt(BB, MI, TII, dl, 1, scratch, destIn, destOut,
7090 IsThumb1, IsThumb2);
7094 MI->eraseFromParent(); // The instruction is gone now.
7098 // Expand the pseudo op to a loop.
7101 // movw varEnd, # --> with thumb2
7103 // ldrcp varEnd, idx --> without thumb2
7104 // fallthrough --> loopMBB
7106 // PHI varPhi, varEnd, varLoop
7107 // PHI srcPhi, src, srcLoop
7108 // PHI destPhi, dst, destLoop
7109 // [scratch, srcLoop] = LDR_POST(srcPhi, UnitSize)
7110 // [destLoop] = STR_POST(scratch, destPhi, UnitSize)
7111 // subs varLoop, varPhi, #UnitSize
7113 // fallthrough --> exitMBB
7115 // epilogue to handle left-over bytes
7116 // [scratch, srcOut] = LDRB_POST(srcLoop, 1)
7117 // [destOut] = STRB_POST(scratch, destLoop, 1)
7118 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
7119 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
7120 MF->insert(It, loopMBB);
7121 MF->insert(It, exitMBB);
7123 // Transfer the remainder of BB and its successor edges to exitMBB.
7124 exitMBB->splice(exitMBB->begin(), BB,
7125 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7126 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7128 // Load an immediate to varEnd.
7129 unsigned varEnd = MRI.createVirtualRegister(TRC);
7130 if (Subtarget->useMovt(*MF)) {
7131 unsigned Vtmp = varEnd;
7132 if ((LoopSize & 0xFFFF0000) != 0)
7133 Vtmp = MRI.createVirtualRegister(TRC);
7134 AddDefaultPred(BuildMI(BB, dl,
7135 TII->get(IsThumb2 ? ARM::t2MOVi16 : ARM::MOVi16),
7136 Vtmp).addImm(LoopSize & 0xFFFF));
7138 if ((LoopSize & 0xFFFF0000) != 0)
7139 AddDefaultPred(BuildMI(BB, dl,
7140 TII->get(IsThumb2 ? ARM::t2MOVTi16 : ARM::MOVTi16),
7143 .addImm(LoopSize >> 16));
7145 MachineConstantPool *ConstantPool = MF->getConstantPool();
7146 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
7147 const Constant *C = ConstantInt::get(Int32Ty, LoopSize);
7149 // MachineConstantPool wants an explicit alignment.
7150 unsigned Align = getDataLayout()->getPrefTypeAlignment(Int32Ty);
7152 Align = getDataLayout()->getTypeAllocSize(C->getType());
7153 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
7156 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(ARM::tLDRpci)).addReg(
7157 varEnd, RegState::Define).addConstantPoolIndex(Idx));
7159 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(ARM::LDRcp)).addReg(
7160 varEnd, RegState::Define).addConstantPoolIndex(Idx).addImm(0));
7162 BB->addSuccessor(loopMBB);
7164 // Generate the loop body:
7165 // varPhi = PHI(varLoop, varEnd)
7166 // srcPhi = PHI(srcLoop, src)
7167 // destPhi = PHI(destLoop, dst)
7168 MachineBasicBlock *entryBB = BB;
7170 unsigned varLoop = MRI.createVirtualRegister(TRC);
7171 unsigned varPhi = MRI.createVirtualRegister(TRC);
7172 unsigned srcLoop = MRI.createVirtualRegister(TRC);
7173 unsigned srcPhi = MRI.createVirtualRegister(TRC);
7174 unsigned destLoop = MRI.createVirtualRegister(TRC);
7175 unsigned destPhi = MRI.createVirtualRegister(TRC);
7177 BuildMI(*BB, BB->begin(), dl, TII->get(ARM::PHI), varPhi)
7178 .addReg(varLoop).addMBB(loopMBB)
7179 .addReg(varEnd).addMBB(entryBB);
7180 BuildMI(BB, dl, TII->get(ARM::PHI), srcPhi)
7181 .addReg(srcLoop).addMBB(loopMBB)
7182 .addReg(src).addMBB(entryBB);
7183 BuildMI(BB, dl, TII->get(ARM::PHI), destPhi)
7184 .addReg(destLoop).addMBB(loopMBB)
7185 .addReg(dest).addMBB(entryBB);
7187 // [scratch, srcLoop] = LDR_POST(srcPhi, UnitSize)
7188 // [destLoop] = STR_POST(scratch, destPhi, UnitSiz)
7189 unsigned scratch = MRI.createVirtualRegister(IsNeon ? VecTRC : TRC);
7190 emitPostLd(BB, BB->end(), TII, dl, UnitSize, scratch, srcPhi, srcLoop,
7191 IsThumb1, IsThumb2);
7192 emitPostSt(BB, BB->end(), TII, dl, UnitSize, scratch, destPhi, destLoop,
7193 IsThumb1, IsThumb2);
7195 // Decrement loop variable by UnitSize.
7197 MachineInstrBuilder MIB =
7198 BuildMI(*BB, BB->end(), dl, TII->get(ARM::tSUBi8), varLoop);
7199 MIB = AddDefaultT1CC(MIB);
7200 MIB.addReg(varPhi).addImm(UnitSize);
7201 AddDefaultPred(MIB);
7203 MachineInstrBuilder MIB =
7204 BuildMI(*BB, BB->end(), dl,
7205 TII->get(IsThumb2 ? ARM::t2SUBri : ARM::SUBri), varLoop);
7206 AddDefaultCC(AddDefaultPred(MIB.addReg(varPhi).addImm(UnitSize)));
7207 MIB->getOperand(5).setReg(ARM::CPSR);
7208 MIB->getOperand(5).setIsDef(true);
7210 BuildMI(*BB, BB->end(), dl,
7211 TII->get(IsThumb1 ? ARM::tBcc : IsThumb2 ? ARM::t2Bcc : ARM::Bcc))
7212 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
7214 // loopMBB can loop back to loopMBB or fall through to exitMBB.
7215 BB->addSuccessor(loopMBB);
7216 BB->addSuccessor(exitMBB);
7218 // Add epilogue to handle BytesLeft.
7220 MachineInstr *StartOfExit = exitMBB->begin();
7222 // [scratch, srcOut] = LDRB_POST(srcLoop, 1)
7223 // [destOut] = STRB_POST(scratch, destLoop, 1)
7224 unsigned srcIn = srcLoop;
7225 unsigned destIn = destLoop;
7226 for (unsigned i = 0; i < BytesLeft; i++) {
7227 unsigned srcOut = MRI.createVirtualRegister(TRC);
7228 unsigned destOut = MRI.createVirtualRegister(TRC);
7229 unsigned scratch = MRI.createVirtualRegister(TRC);
7230 emitPostLd(BB, StartOfExit, TII, dl, 1, scratch, srcIn, srcOut,
7231 IsThumb1, IsThumb2);
7232 emitPostSt(BB, StartOfExit, TII, dl, 1, scratch, destIn, destOut,
7233 IsThumb1, IsThumb2);
7238 MI->eraseFromParent(); // The instruction is gone now.
7243 ARMTargetLowering::EmitLowered__chkstk(MachineInstr *MI,
7244 MachineBasicBlock *MBB) const {
7245 const TargetMachine &TM = getTargetMachine();
7246 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
7247 DebugLoc DL = MI->getDebugLoc();
7249 assert(Subtarget->isTargetWindows() &&
7250 "__chkstk is only supported on Windows");
7251 assert(Subtarget->isThumb2() && "Windows on ARM requires Thumb-2 mode");
7253 // __chkstk takes the number of words to allocate on the stack in R4, and
7254 // returns the stack adjustment in number of bytes in R4. This will not
7255 // clober any other registers (other than the obvious lr).
7257 // Although, technically, IP should be considered a register which may be
7258 // clobbered, the call itself will not touch it. Windows on ARM is a pure
7259 // thumb-2 environment, so there is no interworking required. As a result, we
7260 // do not expect a veneer to be emitted by the linker, clobbering IP.
7262 // Each module receives its own copy of __chkstk, so no import thunk is
7263 // required, again, ensuring that IP is not clobbered.
7265 // Finally, although some linkers may theoretically provide a trampoline for
7266 // out of range calls (which is quite common due to a 32M range limitation of
7267 // branches for Thumb), we can generate the long-call version via
7268 // -mcmodel=large, alleviating the need for the trampoline which may clobber
7271 switch (TM.getCodeModel()) {
7272 case CodeModel::Small:
7273 case CodeModel::Medium:
7274 case CodeModel::Default:
7275 case CodeModel::Kernel:
7276 BuildMI(*MBB, MI, DL, TII.get(ARM::tBL))
7277 .addImm((unsigned)ARMCC::AL).addReg(0)
7278 .addExternalSymbol("__chkstk")
7279 .addReg(ARM::R4, RegState::Implicit | RegState::Kill)
7280 .addReg(ARM::R4, RegState::Implicit | RegState::Define)
7281 .addReg(ARM::R12, RegState::Implicit | RegState::Define | RegState::Dead);
7283 case CodeModel::Large:
7284 case CodeModel::JITDefault: {
7285 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
7286 unsigned Reg = MRI.createVirtualRegister(&ARM::rGPRRegClass);
7288 BuildMI(*MBB, MI, DL, TII.get(ARM::t2MOVi32imm), Reg)
7289 .addExternalSymbol("__chkstk");
7290 BuildMI(*MBB, MI, DL, TII.get(ARM::tBLXr))
7291 .addImm((unsigned)ARMCC::AL).addReg(0)
7292 .addReg(Reg, RegState::Kill)
7293 .addReg(ARM::R4, RegState::Implicit | RegState::Kill)
7294 .addReg(ARM::R4, RegState::Implicit | RegState::Define)
7295 .addReg(ARM::R12, RegState::Implicit | RegState::Define | RegState::Dead);
7300 AddDefaultCC(AddDefaultPred(BuildMI(*MBB, MI, DL, TII.get(ARM::t2SUBrr),
7302 .addReg(ARM::SP).addReg(ARM::R4)));
7304 MI->eraseFromParent();
7309 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
7310 MachineBasicBlock *BB) const {
7311 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
7312 DebugLoc dl = MI->getDebugLoc();
7313 bool isThumb2 = Subtarget->isThumb2();
7314 switch (MI->getOpcode()) {
7317 llvm_unreachable("Unexpected instr type to insert");
7319 // The Thumb2 pre-indexed stores have the same MI operands, they just
7320 // define them differently in the .td files from the isel patterns, so
7321 // they need pseudos.
7322 case ARM::t2STR_preidx:
7323 MI->setDesc(TII->get(ARM::t2STR_PRE));
7325 case ARM::t2STRB_preidx:
7326 MI->setDesc(TII->get(ARM::t2STRB_PRE));
7328 case ARM::t2STRH_preidx:
7329 MI->setDesc(TII->get(ARM::t2STRH_PRE));
7332 case ARM::STRi_preidx:
7333 case ARM::STRBi_preidx: {
7334 unsigned NewOpc = MI->getOpcode() == ARM::STRi_preidx ?
7335 ARM::STR_PRE_IMM : ARM::STRB_PRE_IMM;
7336 // Decode the offset.
7337 unsigned Offset = MI->getOperand(4).getImm();
7338 bool isSub = ARM_AM::getAM2Op(Offset) == ARM_AM::sub;
7339 Offset = ARM_AM::getAM2Offset(Offset);
7343 MachineMemOperand *MMO = *MI->memoperands_begin();
7344 BuildMI(*BB, MI, dl, TII->get(NewOpc))
7345 .addOperand(MI->getOperand(0)) // Rn_wb
7346 .addOperand(MI->getOperand(1)) // Rt
7347 .addOperand(MI->getOperand(2)) // Rn
7348 .addImm(Offset) // offset (skip GPR==zero_reg)
7349 .addOperand(MI->getOperand(5)) // pred
7350 .addOperand(MI->getOperand(6))
7351 .addMemOperand(MMO);
7352 MI->eraseFromParent();
7355 case ARM::STRr_preidx:
7356 case ARM::STRBr_preidx:
7357 case ARM::STRH_preidx: {
7359 switch (MI->getOpcode()) {
7360 default: llvm_unreachable("unexpected opcode!");
7361 case ARM::STRr_preidx: NewOpc = ARM::STR_PRE_REG; break;
7362 case ARM::STRBr_preidx: NewOpc = ARM::STRB_PRE_REG; break;
7363 case ARM::STRH_preidx: NewOpc = ARM::STRH_PRE; break;
7365 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc));
7366 for (unsigned i = 0; i < MI->getNumOperands(); ++i)
7367 MIB.addOperand(MI->getOperand(i));
7368 MI->eraseFromParent();
7372 case ARM::tMOVCCr_pseudo: {
7373 // To "insert" a SELECT_CC instruction, we actually have to insert the
7374 // diamond control-flow pattern. The incoming instruction knows the
7375 // destination vreg to set, the condition code register to branch on, the
7376 // true/false values to select between, and a branch opcode to use.
7377 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7378 MachineFunction::iterator It = BB;
7384 // cmpTY ccX, r1, r2
7386 // fallthrough --> copy0MBB
7387 MachineBasicBlock *thisMBB = BB;
7388 MachineFunction *F = BB->getParent();
7389 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7390 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7391 F->insert(It, copy0MBB);
7392 F->insert(It, sinkMBB);
7394 // Transfer the remainder of BB and its successor edges to sinkMBB.
7395 sinkMBB->splice(sinkMBB->begin(), BB,
7396 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7397 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
7399 BB->addSuccessor(copy0MBB);
7400 BB->addSuccessor(sinkMBB);
7402 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
7403 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
7406 // %FalseValue = ...
7407 // # fallthrough to sinkMBB
7410 // Update machine-CFG edges
7411 BB->addSuccessor(sinkMBB);
7414 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7417 BuildMI(*BB, BB->begin(), dl,
7418 TII->get(ARM::PHI), MI->getOperand(0).getReg())
7419 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
7420 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7422 MI->eraseFromParent(); // The pseudo instruction is gone now.
7427 case ARM::BCCZi64: {
7428 // If there is an unconditional branch to the other successor, remove it.
7429 BB->erase(std::next(MachineBasicBlock::iterator(MI)), BB->end());
7431 // Compare both parts that make up the double comparison separately for
7433 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
7435 unsigned LHS1 = MI->getOperand(1).getReg();
7436 unsigned LHS2 = MI->getOperand(2).getReg();
7438 AddDefaultPred(BuildMI(BB, dl,
7439 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
7440 .addReg(LHS1).addImm(0));
7441 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
7442 .addReg(LHS2).addImm(0)
7443 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
7445 unsigned RHS1 = MI->getOperand(3).getReg();
7446 unsigned RHS2 = MI->getOperand(4).getReg();
7447 AddDefaultPred(BuildMI(BB, dl,
7448 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
7449 .addReg(LHS1).addReg(RHS1));
7450 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
7451 .addReg(LHS2).addReg(RHS2)
7452 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
7455 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB();
7456 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
7457 if (MI->getOperand(0).getImm() == ARMCC::NE)
7458 std::swap(destMBB, exitMBB);
7460 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
7461 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
7463 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2B)).addMBB(exitMBB));
7465 BuildMI(BB, dl, TII->get(ARM::B)) .addMBB(exitMBB);
7467 MI->eraseFromParent(); // The pseudo instruction is gone now.
7471 case ARM::Int_eh_sjlj_setjmp:
7472 case ARM::Int_eh_sjlj_setjmp_nofp:
7473 case ARM::tInt_eh_sjlj_setjmp:
7474 case ARM::t2Int_eh_sjlj_setjmp:
7475 case ARM::t2Int_eh_sjlj_setjmp_nofp:
7476 EmitSjLjDispatchBlock(MI, BB);
7481 // To insert an ABS instruction, we have to insert the
7482 // diamond control-flow pattern. The incoming instruction knows the
7483 // source vreg to test against 0, the destination vreg to set,
7484 // the condition code register to branch on, the
7485 // true/false values to select between, and a branch opcode to use.
7490 // BCC (branch to SinkBB if V0 >= 0)
7491 // RSBBB: V3 = RSBri V2, 0 (compute ABS if V2 < 0)
7492 // SinkBB: V1 = PHI(V2, V3)
7493 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7494 MachineFunction::iterator BBI = BB;
7496 MachineFunction *Fn = BB->getParent();
7497 MachineBasicBlock *RSBBB = Fn->CreateMachineBasicBlock(LLVM_BB);
7498 MachineBasicBlock *SinkBB = Fn->CreateMachineBasicBlock(LLVM_BB);
7499 Fn->insert(BBI, RSBBB);
7500 Fn->insert(BBI, SinkBB);
7502 unsigned int ABSSrcReg = MI->getOperand(1).getReg();
7503 unsigned int ABSDstReg = MI->getOperand(0).getReg();
7504 bool ABSSrcKIll = MI->getOperand(1).isKill();
7505 bool isThumb2 = Subtarget->isThumb2();
7506 MachineRegisterInfo &MRI = Fn->getRegInfo();
7507 // In Thumb mode S must not be specified if source register is the SP or
7508 // PC and if destination register is the SP, so restrict register class
7509 unsigned NewRsbDstReg =
7510 MRI.createVirtualRegister(isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass);
7512 // Transfer the remainder of BB and its successor edges to sinkMBB.
7513 SinkBB->splice(SinkBB->begin(), BB,
7514 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7515 SinkBB->transferSuccessorsAndUpdatePHIs(BB);
7517 BB->addSuccessor(RSBBB);
7518 BB->addSuccessor(SinkBB);
7520 // fall through to SinkMBB
7521 RSBBB->addSuccessor(SinkBB);
7523 // insert a cmp at the end of BB
7524 AddDefaultPred(BuildMI(BB, dl,
7525 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
7526 .addReg(ABSSrcReg).addImm(0));
7528 // insert a bcc with opposite CC to ARMCC::MI at the end of BB
7530 TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)).addMBB(SinkBB)
7531 .addImm(ARMCC::getOppositeCondition(ARMCC::MI)).addReg(ARM::CPSR);
7533 // insert rsbri in RSBBB
7534 // Note: BCC and rsbri will be converted into predicated rsbmi
7535 // by if-conversion pass
7536 BuildMI(*RSBBB, RSBBB->begin(), dl,
7537 TII->get(isThumb2 ? ARM::t2RSBri : ARM::RSBri), NewRsbDstReg)
7538 .addReg(ABSSrcReg, ABSSrcKIll ? RegState::Kill : 0)
7539 .addImm(0).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
7541 // insert PHI in SinkBB,
7542 // reuse ABSDstReg to not change uses of ABS instruction
7543 BuildMI(*SinkBB, SinkBB->begin(), dl,
7544 TII->get(ARM::PHI), ABSDstReg)
7545 .addReg(NewRsbDstReg).addMBB(RSBBB)
7546 .addReg(ABSSrcReg).addMBB(BB);
7548 // remove ABS instruction
7549 MI->eraseFromParent();
7551 // return last added BB
7554 case ARM::COPY_STRUCT_BYVAL_I32:
7556 return EmitStructByval(MI, BB);
7557 case ARM::WIN__CHKSTK:
7558 return EmitLowered__chkstk(MI, BB);
7562 void ARMTargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
7563 SDNode *Node) const {
7564 const MCInstrDesc *MCID = &MI->getDesc();
7565 // Adjust potentially 's' setting instructions after isel, i.e. ADC, SBC, RSB,
7566 // RSC. Coming out of isel, they have an implicit CPSR def, but the optional
7567 // operand is still set to noreg. If needed, set the optional operand's
7568 // register to CPSR, and remove the redundant implicit def.
7570 // e.g. ADCS (..., CPSR<imp-def>) -> ADC (... opt:CPSR<def>).
7572 // Rename pseudo opcodes.
7573 unsigned NewOpc = convertAddSubFlagsOpcode(MI->getOpcode());
7575 const ARMBaseInstrInfo *TII = Subtarget->getInstrInfo();
7576 MCID = &TII->get(NewOpc);
7578 assert(MCID->getNumOperands() == MI->getDesc().getNumOperands() + 1 &&
7579 "converted opcode should be the same except for cc_out");
7583 // Add the optional cc_out operand
7584 MI->addOperand(MachineOperand::CreateReg(0, /*isDef=*/true));
7586 unsigned ccOutIdx = MCID->getNumOperands() - 1;
7588 // Any ARM instruction that sets the 's' bit should specify an optional
7589 // "cc_out" operand in the last operand position.
7590 if (!MI->hasOptionalDef() || !MCID->OpInfo[ccOutIdx].isOptionalDef()) {
7591 assert(!NewOpc && "Optional cc_out operand required");
7594 // Look for an implicit def of CPSR added by MachineInstr ctor. Remove it
7595 // since we already have an optional CPSR def.
7596 bool definesCPSR = false;
7597 bool deadCPSR = false;
7598 for (unsigned i = MCID->getNumOperands(), e = MI->getNumOperands();
7600 const MachineOperand &MO = MI->getOperand(i);
7601 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) {
7605 MI->RemoveOperand(i);
7610 assert(!NewOpc && "Optional cc_out operand required");
7613 assert(deadCPSR == !Node->hasAnyUseOfValue(1) && "inconsistent dead flag");
7615 assert(!MI->getOperand(ccOutIdx).getReg() &&
7616 "expect uninitialized optional cc_out operand");
7620 // If this instruction was defined with an optional CPSR def and its dag node
7621 // had a live implicit CPSR def, then activate the optional CPSR def.
7622 MachineOperand &MO = MI->getOperand(ccOutIdx);
7623 MO.setReg(ARM::CPSR);
7627 //===----------------------------------------------------------------------===//
7628 // ARM Optimization Hooks
7629 //===----------------------------------------------------------------------===//
7631 // Helper function that checks if N is a null or all ones constant.
7632 static inline bool isZeroOrAllOnes(SDValue N, bool AllOnes) {
7633 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
7636 return AllOnes ? C->isAllOnesValue() : C->isNullValue();
7639 // Return true if N is conditionally 0 or all ones.
7640 // Detects these expressions where cc is an i1 value:
7642 // (select cc 0, y) [AllOnes=0]
7643 // (select cc y, 0) [AllOnes=0]
7644 // (zext cc) [AllOnes=0]
7645 // (sext cc) [AllOnes=0/1]
7646 // (select cc -1, y) [AllOnes=1]
7647 // (select cc y, -1) [AllOnes=1]
7649 // Invert is set when N is the null/all ones constant when CC is false.
7650 // OtherOp is set to the alternative value of N.
7651 static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes,
7652 SDValue &CC, bool &Invert,
7654 SelectionDAG &DAG) {
7655 switch (N->getOpcode()) {
7656 default: return false;
7658 CC = N->getOperand(0);
7659 SDValue N1 = N->getOperand(1);
7660 SDValue N2 = N->getOperand(2);
7661 if (isZeroOrAllOnes(N1, AllOnes)) {
7666 if (isZeroOrAllOnes(N2, AllOnes)) {
7673 case ISD::ZERO_EXTEND:
7674 // (zext cc) can never be the all ones value.
7678 case ISD::SIGN_EXTEND: {
7680 EVT VT = N->getValueType(0);
7681 CC = N->getOperand(0);
7682 if (CC.getValueType() != MVT::i1)
7686 // When looking for an AllOnes constant, N is an sext, and the 'other'
7688 OtherOp = DAG.getConstant(0, dl, VT);
7689 else if (N->getOpcode() == ISD::ZERO_EXTEND)
7690 // When looking for a 0 constant, N can be zext or sext.
7691 OtherOp = DAG.getConstant(1, dl, VT);
7693 OtherOp = DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), dl,
7700 // Combine a constant select operand into its use:
7702 // (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
7703 // (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
7704 // (and (select cc, -1, c), x) -> (select cc, x, (and, x, c)) [AllOnes=1]
7705 // (or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
7706 // (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
7708 // The transform is rejected if the select doesn't have a constant operand that
7709 // is null, or all ones when AllOnes is set.
7711 // Also recognize sext/zext from i1:
7713 // (add (zext cc), x) -> (select cc (add x, 1), x)
7714 // (add (sext cc), x) -> (select cc (add x, -1), x)
7716 // These transformations eventually create predicated instructions.
7718 // @param N The node to transform.
7719 // @param Slct The N operand that is a select.
7720 // @param OtherOp The other N operand (x above).
7721 // @param DCI Context.
7722 // @param AllOnes Require the select constant to be all ones instead of null.
7723 // @returns The new node, or SDValue() on failure.
7725 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
7726 TargetLowering::DAGCombinerInfo &DCI,
7727 bool AllOnes = false) {
7728 SelectionDAG &DAG = DCI.DAG;
7729 EVT VT = N->getValueType(0);
7730 SDValue NonConstantVal;
7733 if (!isConditionalZeroOrAllOnes(Slct.getNode(), AllOnes, CCOp, SwapSelectOps,
7734 NonConstantVal, DAG))
7737 // Slct is now know to be the desired identity constant when CC is true.
7738 SDValue TrueVal = OtherOp;
7739 SDValue FalseVal = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
7740 OtherOp, NonConstantVal);
7741 // Unless SwapSelectOps says CC should be false.
7743 std::swap(TrueVal, FalseVal);
7745 return DAG.getNode(ISD::SELECT, SDLoc(N), VT,
7746 CCOp, TrueVal, FalseVal);
7749 // Attempt combineSelectAndUse on each operand of a commutative operator N.
7751 SDValue combineSelectAndUseCommutative(SDNode *N, bool AllOnes,
7752 TargetLowering::DAGCombinerInfo &DCI) {
7753 SDValue N0 = N->getOperand(0);
7754 SDValue N1 = N->getOperand(1);
7755 if (N0.getNode()->hasOneUse()) {
7756 SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes);
7757 if (Result.getNode())
7760 if (N1.getNode()->hasOneUse()) {
7761 SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes);
7762 if (Result.getNode())
7768 // AddCombineToVPADDL- For pair-wise add on neon, use the vpaddl instruction
7769 // (only after legalization).
7770 static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1,
7771 TargetLowering::DAGCombinerInfo &DCI,
7772 const ARMSubtarget *Subtarget) {
7774 // Only perform optimization if after legalize, and if NEON is available. We
7775 // also expected both operands to be BUILD_VECTORs.
7776 if (DCI.isBeforeLegalize() || !Subtarget->hasNEON()
7777 || N0.getOpcode() != ISD::BUILD_VECTOR
7778 || N1.getOpcode() != ISD::BUILD_VECTOR)
7781 // Check output type since VPADDL operand elements can only be 8, 16, or 32.
7782 EVT VT = N->getValueType(0);
7783 if (!VT.isInteger() || VT.getVectorElementType() == MVT::i64)
7786 // Check that the vector operands are of the right form.
7787 // N0 and N1 are BUILD_VECTOR nodes with N number of EXTRACT_VECTOR
7788 // operands, where N is the size of the formed vector.
7789 // Each EXTRACT_VECTOR should have the same input vector and odd or even
7790 // index such that we have a pair wise add pattern.
7792 // Grab the vector that all EXTRACT_VECTOR nodes should be referencing.
7793 if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
7795 SDValue Vec = N0->getOperand(0)->getOperand(0);
7796 SDNode *V = Vec.getNode();
7797 unsigned nextIndex = 0;
7799 // For each operands to the ADD which are BUILD_VECTORs,
7800 // check to see if each of their operands are an EXTRACT_VECTOR with
7801 // the same vector and appropriate index.
7802 for (unsigned i = 0, e = N0->getNumOperands(); i != e; ++i) {
7803 if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT
7804 && N1->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
7806 SDValue ExtVec0 = N0->getOperand(i);
7807 SDValue ExtVec1 = N1->getOperand(i);
7809 // First operand is the vector, verify its the same.
7810 if (V != ExtVec0->getOperand(0).getNode() ||
7811 V != ExtVec1->getOperand(0).getNode())
7814 // Second is the constant, verify its correct.
7815 ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(ExtVec0->getOperand(1));
7816 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(ExtVec1->getOperand(1));
7818 // For the constant, we want to see all the even or all the odd.
7819 if (!C0 || !C1 || C0->getZExtValue() != nextIndex
7820 || C1->getZExtValue() != nextIndex+1)
7829 // Create VPADDL node.
7830 SelectionDAG &DAG = DCI.DAG;
7831 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7835 // Build operand list.
7836 SmallVector<SDValue, 8> Ops;
7837 Ops.push_back(DAG.getConstant(Intrinsic::arm_neon_vpaddls, dl,
7838 TLI.getPointerTy()));
7840 // Input is the vector.
7843 // Get widened type and narrowed type.
7845 unsigned numElem = VT.getVectorNumElements();
7847 EVT inputLaneType = Vec.getValueType().getVectorElementType();
7848 switch (inputLaneType.getSimpleVT().SimpleTy) {
7849 case MVT::i8: widenType = MVT::getVectorVT(MVT::i16, numElem); break;
7850 case MVT::i16: widenType = MVT::getVectorVT(MVT::i32, numElem); break;
7851 case MVT::i32: widenType = MVT::getVectorVT(MVT::i64, numElem); break;
7853 llvm_unreachable("Invalid vector element type for padd optimization.");
7856 SDValue tmp = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, widenType, Ops);
7857 unsigned ExtOp = VT.bitsGT(tmp.getValueType()) ? ISD::ANY_EXTEND : ISD::TRUNCATE;
7858 return DAG.getNode(ExtOp, dl, VT, tmp);
7861 static SDValue findMUL_LOHI(SDValue V) {
7862 if (V->getOpcode() == ISD::UMUL_LOHI ||
7863 V->getOpcode() == ISD::SMUL_LOHI)
7868 static SDValue AddCombineTo64bitMLAL(SDNode *AddcNode,
7869 TargetLowering::DAGCombinerInfo &DCI,
7870 const ARMSubtarget *Subtarget) {
7872 if (Subtarget->isThumb1Only()) return SDValue();
7874 // Only perform the checks after legalize when the pattern is available.
7875 if (DCI.isBeforeLegalize()) return SDValue();
7877 // Look for multiply add opportunities.
7878 // The pattern is a ISD::UMUL_LOHI followed by two add nodes, where
7879 // each add nodes consumes a value from ISD::UMUL_LOHI and there is
7880 // a glue link from the first add to the second add.
7881 // If we find this pattern, we can replace the U/SMUL_LOHI, ADDC, and ADDE by
7882 // a S/UMLAL instruction.
7885 // \ / \ [no multiline comment]
7891 assert(AddcNode->getOpcode() == ISD::ADDC && "Expect an ADDC");
7892 SDValue AddcOp0 = AddcNode->getOperand(0);
7893 SDValue AddcOp1 = AddcNode->getOperand(1);
7895 // Check if the two operands are from the same mul_lohi node.
7896 if (AddcOp0.getNode() == AddcOp1.getNode())
7899 assert(AddcNode->getNumValues() == 2 &&
7900 AddcNode->getValueType(0) == MVT::i32 &&
7901 "Expect ADDC with two result values. First: i32");
7903 // Check that we have a glued ADDC node.
7904 if (AddcNode->getValueType(1) != MVT::Glue)
7907 // Check that the ADDC adds the low result of the S/UMUL_LOHI.
7908 if (AddcOp0->getOpcode() != ISD::UMUL_LOHI &&
7909 AddcOp0->getOpcode() != ISD::SMUL_LOHI &&
7910 AddcOp1->getOpcode() != ISD::UMUL_LOHI &&
7911 AddcOp1->getOpcode() != ISD::SMUL_LOHI)
7914 // Look for the glued ADDE.
7915 SDNode* AddeNode = AddcNode->getGluedUser();
7919 // Make sure it is really an ADDE.
7920 if (AddeNode->getOpcode() != ISD::ADDE)
7923 assert(AddeNode->getNumOperands() == 3 &&
7924 AddeNode->getOperand(2).getValueType() == MVT::Glue &&
7925 "ADDE node has the wrong inputs");
7927 // Check for the triangle shape.
7928 SDValue AddeOp0 = AddeNode->getOperand(0);
7929 SDValue AddeOp1 = AddeNode->getOperand(1);
7931 // Make sure that the ADDE operands are not coming from the same node.
7932 if (AddeOp0.getNode() == AddeOp1.getNode())
7935 // Find the MUL_LOHI node walking up ADDE's operands.
7936 bool IsLeftOperandMUL = false;
7937 SDValue MULOp = findMUL_LOHI(AddeOp0);
7938 if (MULOp == SDValue())
7939 MULOp = findMUL_LOHI(AddeOp1);
7941 IsLeftOperandMUL = true;
7942 if (MULOp == SDValue())
7945 // Figure out the right opcode.
7946 unsigned Opc = MULOp->getOpcode();
7947 unsigned FinalOpc = (Opc == ISD::SMUL_LOHI) ? ARMISD::SMLAL : ARMISD::UMLAL;
7949 // Figure out the high and low input values to the MLAL node.
7950 SDValue* HiAdd = nullptr;
7951 SDValue* LoMul = nullptr;
7952 SDValue* LowAdd = nullptr;
7954 // Ensure that ADDE is from high result of ISD::SMUL_LOHI.
7955 if ((AddeOp0 != MULOp.getValue(1)) && (AddeOp1 != MULOp.getValue(1)))
7958 if (IsLeftOperandMUL)
7964 // Ensure that LoMul and LowAdd are taken from correct ISD::SMUL_LOHI node
7965 // whose low result is fed to the ADDC we are checking.
7967 if (AddcOp0 == MULOp.getValue(0)) {
7971 if (AddcOp1 == MULOp.getValue(0)) {
7979 // Create the merged node.
7980 SelectionDAG &DAG = DCI.DAG;
7982 // Build operand list.
7983 SmallVector<SDValue, 8> Ops;
7984 Ops.push_back(LoMul->getOperand(0));
7985 Ops.push_back(LoMul->getOperand(1));
7986 Ops.push_back(*LowAdd);
7987 Ops.push_back(*HiAdd);
7989 SDValue MLALNode = DAG.getNode(FinalOpc, SDLoc(AddcNode),
7990 DAG.getVTList(MVT::i32, MVT::i32), Ops);
7992 // Replace the ADDs' nodes uses by the MLA node's values.
7993 SDValue HiMLALResult(MLALNode.getNode(), 1);
7994 DAG.ReplaceAllUsesOfValueWith(SDValue(AddeNode, 0), HiMLALResult);
7996 SDValue LoMLALResult(MLALNode.getNode(), 0);
7997 DAG.ReplaceAllUsesOfValueWith(SDValue(AddcNode, 0), LoMLALResult);
7999 // Return original node to notify the driver to stop replacing.
8000 SDValue resNode(AddcNode, 0);
8004 /// PerformADDCCombine - Target-specific dag combine transform from
8005 /// ISD::ADDC, ISD::ADDE, and ISD::MUL_LOHI to MLAL.
8006 static SDValue PerformADDCCombine(SDNode *N,
8007 TargetLowering::DAGCombinerInfo &DCI,
8008 const ARMSubtarget *Subtarget) {
8010 return AddCombineTo64bitMLAL(N, DCI, Subtarget);
8014 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
8015 /// operands N0 and N1. This is a helper for PerformADDCombine that is
8016 /// called with the default operands, and if that fails, with commuted
8018 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
8019 TargetLowering::DAGCombinerInfo &DCI,
8020 const ARMSubtarget *Subtarget){
8022 // Attempt to create vpaddl for this add.
8023 SDValue Result = AddCombineToVPADDL(N, N0, N1, DCI, Subtarget);
8024 if (Result.getNode())
8027 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
8028 if (N0.getNode()->hasOneUse()) {
8029 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
8030 if (Result.getNode()) return Result;
8035 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
8037 static SDValue PerformADDCombine(SDNode *N,
8038 TargetLowering::DAGCombinerInfo &DCI,
8039 const ARMSubtarget *Subtarget) {
8040 SDValue N0 = N->getOperand(0);
8041 SDValue N1 = N->getOperand(1);
8043 // First try with the default operand order.
8044 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget);
8045 if (Result.getNode())
8048 // If that didn't work, try again with the operands commuted.
8049 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget);
8052 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
8054 static SDValue PerformSUBCombine(SDNode *N,
8055 TargetLowering::DAGCombinerInfo &DCI) {
8056 SDValue N0 = N->getOperand(0);
8057 SDValue N1 = N->getOperand(1);
8059 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
8060 if (N1.getNode()->hasOneUse()) {
8061 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
8062 if (Result.getNode()) return Result;
8068 /// PerformVMULCombine
8069 /// Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the
8070 /// special multiplier accumulator forwarding.
8076 // However, for (A + B) * (A + B),
8083 static SDValue PerformVMULCombine(SDNode *N,
8084 TargetLowering::DAGCombinerInfo &DCI,
8085 const ARMSubtarget *Subtarget) {
8086 if (!Subtarget->hasVMLxForwarding())
8089 SelectionDAG &DAG = DCI.DAG;
8090 SDValue N0 = N->getOperand(0);
8091 SDValue N1 = N->getOperand(1);
8092 unsigned Opcode = N0.getOpcode();
8093 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
8094 Opcode != ISD::FADD && Opcode != ISD::FSUB) {
8095 Opcode = N1.getOpcode();
8096 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
8097 Opcode != ISD::FADD && Opcode != ISD::FSUB)
8105 EVT VT = N->getValueType(0);
8107 SDValue N00 = N0->getOperand(0);
8108 SDValue N01 = N0->getOperand(1);
8109 return DAG.getNode(Opcode, DL, VT,
8110 DAG.getNode(ISD::MUL, DL, VT, N00, N1),
8111 DAG.getNode(ISD::MUL, DL, VT, N01, N1));
8114 static SDValue PerformMULCombine(SDNode *N,
8115 TargetLowering::DAGCombinerInfo &DCI,
8116 const ARMSubtarget *Subtarget) {
8117 SelectionDAG &DAG = DCI.DAG;
8119 if (Subtarget->isThumb1Only())
8122 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
8125 EVT VT = N->getValueType(0);
8126 if (VT.is64BitVector() || VT.is128BitVector())
8127 return PerformVMULCombine(N, DCI, Subtarget);
8131 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
8135 int64_t MulAmt = C->getSExtValue();
8136 unsigned ShiftAmt = countTrailingZeros<uint64_t>(MulAmt);
8138 ShiftAmt = ShiftAmt & (32 - 1);
8139 SDValue V = N->getOperand(0);
8143 MulAmt >>= ShiftAmt;
8146 if (isPowerOf2_32(MulAmt - 1)) {
8147 // (mul x, 2^N + 1) => (add (shl x, N), x)
8148 Res = DAG.getNode(ISD::ADD, DL, VT,
8150 DAG.getNode(ISD::SHL, DL, VT,
8152 DAG.getConstant(Log2_32(MulAmt - 1), DL,
8154 } else if (isPowerOf2_32(MulAmt + 1)) {
8155 // (mul x, 2^N - 1) => (sub (shl x, N), x)
8156 Res = DAG.getNode(ISD::SUB, DL, VT,
8157 DAG.getNode(ISD::SHL, DL, VT,
8159 DAG.getConstant(Log2_32(MulAmt + 1), DL,
8165 uint64_t MulAmtAbs = -MulAmt;
8166 if (isPowerOf2_32(MulAmtAbs + 1)) {
8167 // (mul x, -(2^N - 1)) => (sub x, (shl x, N))
8168 Res = DAG.getNode(ISD::SUB, DL, VT,
8170 DAG.getNode(ISD::SHL, DL, VT,
8172 DAG.getConstant(Log2_32(MulAmtAbs + 1), DL,
8174 } else if (isPowerOf2_32(MulAmtAbs - 1)) {
8175 // (mul x, -(2^N + 1)) => - (add (shl x, N), x)
8176 Res = DAG.getNode(ISD::ADD, DL, VT,
8178 DAG.getNode(ISD::SHL, DL, VT,
8180 DAG.getConstant(Log2_32(MulAmtAbs - 1), DL,
8182 Res = DAG.getNode(ISD::SUB, DL, VT,
8183 DAG.getConstant(0, DL, MVT::i32), Res);
8190 Res = DAG.getNode(ISD::SHL, DL, VT,
8191 Res, DAG.getConstant(ShiftAmt, DL, MVT::i32));
8193 // Do not add new nodes to DAG combiner worklist.
8194 DCI.CombineTo(N, Res, false);
8198 static SDValue PerformANDCombine(SDNode *N,
8199 TargetLowering::DAGCombinerInfo &DCI,
8200 const ARMSubtarget *Subtarget) {
8202 // Attempt to use immediate-form VBIC
8203 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
8205 EVT VT = N->getValueType(0);
8206 SelectionDAG &DAG = DCI.DAG;
8208 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
8211 APInt SplatBits, SplatUndef;
8212 unsigned SplatBitSize;
8215 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
8216 if (SplatBitSize <= 64) {
8218 SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(),
8219 SplatUndef.getZExtValue(), SplatBitSize,
8220 DAG, dl, VbicVT, VT.is128BitVector(),
8222 if (Val.getNode()) {
8224 DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0));
8225 SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val);
8226 return DAG.getNode(ISD::BITCAST, dl, VT, Vbic);
8231 if (!Subtarget->isThumb1Only()) {
8232 // fold (and (select cc, -1, c), x) -> (select cc, x, (and, x, c))
8233 SDValue Result = combineSelectAndUseCommutative(N, true, DCI);
8234 if (Result.getNode())
8241 /// PerformORCombine - Target-specific dag combine xforms for ISD::OR
8242 static SDValue PerformORCombine(SDNode *N,
8243 TargetLowering::DAGCombinerInfo &DCI,
8244 const ARMSubtarget *Subtarget) {
8245 // Attempt to use immediate-form VORR
8246 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
8248 EVT VT = N->getValueType(0);
8249 SelectionDAG &DAG = DCI.DAG;
8251 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
8254 APInt SplatBits, SplatUndef;
8255 unsigned SplatBitSize;
8257 if (BVN && Subtarget->hasNEON() &&
8258 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
8259 if (SplatBitSize <= 64) {
8261 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
8262 SplatUndef.getZExtValue(), SplatBitSize,
8263 DAG, dl, VorrVT, VT.is128BitVector(),
8265 if (Val.getNode()) {
8267 DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0));
8268 SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val);
8269 return DAG.getNode(ISD::BITCAST, dl, VT, Vorr);
8274 if (!Subtarget->isThumb1Only()) {
8275 // fold (or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
8276 SDValue Result = combineSelectAndUseCommutative(N, false, DCI);
8277 if (Result.getNode())
8281 // The code below optimizes (or (and X, Y), Z).
8282 // The AND operand needs to have a single user to make these optimizations
8284 SDValue N0 = N->getOperand(0);
8285 if (N0.getOpcode() != ISD::AND || !N0.hasOneUse())
8287 SDValue N1 = N->getOperand(1);
8289 // (or (and B, A), (and C, ~A)) => (VBSL A, B, C) when A is a constant.
8290 if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() &&
8291 DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
8293 unsigned SplatBitSize;
8296 APInt SplatBits0, SplatBits1;
8297 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1));
8298 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(1));
8299 // Ensure that the second operand of both ands are constants
8300 if (BVN0 && BVN0->isConstantSplat(SplatBits0, SplatUndef, SplatBitSize,
8301 HasAnyUndefs) && !HasAnyUndefs) {
8302 if (BVN1 && BVN1->isConstantSplat(SplatBits1, SplatUndef, SplatBitSize,
8303 HasAnyUndefs) && !HasAnyUndefs) {
8304 // Ensure that the bit width of the constants are the same and that
8305 // the splat arguments are logical inverses as per the pattern we
8306 // are trying to simplify.
8307 if (SplatBits0.getBitWidth() == SplatBits1.getBitWidth() &&
8308 SplatBits0 == ~SplatBits1) {
8309 // Canonicalize the vector type to make instruction selection
8311 EVT CanonicalVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
8312 SDValue Result = DAG.getNode(ARMISD::VBSL, dl, CanonicalVT,
8316 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
8322 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when
8325 // BFI is only available on V6T2+
8326 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops())
8330 // 1) or (and A, mask), val => ARMbfi A, val, mask
8331 // iff (val & mask) == val
8333 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
8334 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2)
8335 // && mask == ~mask2
8336 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2)
8337 // && ~mask == mask2
8338 // (i.e., copy a bitfield value into another bitfield of the same width)
8343 SDValue N00 = N0.getOperand(0);
8345 // The value and the mask need to be constants so we can verify this is
8346 // actually a bitfield set. If the mask is 0xffff, we can do better
8347 // via a movt instruction, so don't use BFI in that case.
8348 SDValue MaskOp = N0.getOperand(1);
8349 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(MaskOp);
8352 unsigned Mask = MaskC->getZExtValue();
8356 // Case (1): or (and A, mask), val => ARMbfi A, val, mask
8357 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
8359 unsigned Val = N1C->getZExtValue();
8360 if ((Val & ~Mask) != Val)
8363 if (ARM::isBitFieldInvertedMask(Mask)) {
8364 Val >>= countTrailingZeros(~Mask);
8366 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00,
8367 DAG.getConstant(Val, DL, MVT::i32),
8368 DAG.getConstant(Mask, DL, MVT::i32));
8370 // Do not add new nodes to DAG combiner worklist.
8371 DCI.CombineTo(N, Res, false);
8374 } else if (N1.getOpcode() == ISD::AND) {
8375 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
8376 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
8379 unsigned Mask2 = N11C->getZExtValue();
8381 // Mask and ~Mask2 (or reverse) must be equivalent for the BFI pattern
8383 if (ARM::isBitFieldInvertedMask(Mask) &&
8385 // The pack halfword instruction works better for masks that fit it,
8386 // so use that when it's available.
8387 if (Subtarget->hasT2ExtractPack() &&
8388 (Mask == 0xffff || Mask == 0xffff0000))
8391 unsigned amt = countTrailingZeros(Mask2);
8392 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
8393 DAG.getConstant(amt, DL, MVT::i32));
8394 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res,
8395 DAG.getConstant(Mask, DL, MVT::i32));
8396 // Do not add new nodes to DAG combiner worklist.
8397 DCI.CombineTo(N, Res, false);
8399 } else if (ARM::isBitFieldInvertedMask(~Mask) &&
8401 // The pack halfword instruction works better for masks that fit it,
8402 // so use that when it's available.
8403 if (Subtarget->hasT2ExtractPack() &&
8404 (Mask2 == 0xffff || Mask2 == 0xffff0000))
8407 unsigned lsb = countTrailingZeros(Mask);
8408 Res = DAG.getNode(ISD::SRL, DL, VT, N00,
8409 DAG.getConstant(lsb, DL, MVT::i32));
8410 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
8411 DAG.getConstant(Mask2, DL, MVT::i32));
8412 // Do not add new nodes to DAG combiner worklist.
8413 DCI.CombineTo(N, Res, false);
8418 if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) &&
8419 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) &&
8420 ARM::isBitFieldInvertedMask(~Mask)) {
8421 // Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask
8422 // where lsb(mask) == #shamt and masked bits of B are known zero.
8423 SDValue ShAmt = N00.getOperand(1);
8424 unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue();
8425 unsigned LSB = countTrailingZeros(Mask);
8429 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0),
8430 DAG.getConstant(~Mask, DL, MVT::i32));
8432 // Do not add new nodes to DAG combiner worklist.
8433 DCI.CombineTo(N, Res, false);
8439 static SDValue PerformXORCombine(SDNode *N,
8440 TargetLowering::DAGCombinerInfo &DCI,
8441 const ARMSubtarget *Subtarget) {
8442 EVT VT = N->getValueType(0);
8443 SelectionDAG &DAG = DCI.DAG;
8445 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
8448 if (!Subtarget->isThumb1Only()) {
8449 // fold (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
8450 SDValue Result = combineSelectAndUseCommutative(N, false, DCI);
8451 if (Result.getNode())
8458 /// PerformBFICombine - (bfi A, (and B, Mask1), Mask2) -> (bfi A, B, Mask2) iff
8459 /// the bits being cleared by the AND are not demanded by the BFI.
8460 static SDValue PerformBFICombine(SDNode *N,
8461 TargetLowering::DAGCombinerInfo &DCI) {
8462 SDValue N1 = N->getOperand(1);
8463 if (N1.getOpcode() == ISD::AND) {
8464 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
8467 unsigned InvMask = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
8468 unsigned LSB = countTrailingZeros(~InvMask);
8469 unsigned Width = (32 - countLeadingZeros(~InvMask)) - LSB;
8471 static_cast<unsigned>(std::numeric_limits<unsigned>::digits) &&
8472 "undefined behavior");
8473 unsigned Mask = (1u << Width) - 1;
8474 unsigned Mask2 = N11C->getZExtValue();
8475 if ((Mask & (~Mask2)) == 0)
8476 return DCI.DAG.getNode(ARMISD::BFI, SDLoc(N), N->getValueType(0),
8477 N->getOperand(0), N1.getOperand(0),
8483 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
8484 /// ARMISD::VMOVRRD.
8485 static SDValue PerformVMOVRRDCombine(SDNode *N,
8486 TargetLowering::DAGCombinerInfo &DCI,
8487 const ARMSubtarget *Subtarget) {
8488 // vmovrrd(vmovdrr x, y) -> x,y
8489 SDValue InDouble = N->getOperand(0);
8490 if (InDouble.getOpcode() == ARMISD::VMOVDRR && !Subtarget->isFPOnlySP())
8491 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
8493 // vmovrrd(load f64) -> (load i32), (load i32)
8494 SDNode *InNode = InDouble.getNode();
8495 if (ISD::isNormalLoad(InNode) && InNode->hasOneUse() &&
8496 InNode->getValueType(0) == MVT::f64 &&
8497 InNode->getOperand(1).getOpcode() == ISD::FrameIndex &&
8498 !cast<LoadSDNode>(InNode)->isVolatile()) {
8499 // TODO: Should this be done for non-FrameIndex operands?
8500 LoadSDNode *LD = cast<LoadSDNode>(InNode);
8502 SelectionDAG &DAG = DCI.DAG;
8504 SDValue BasePtr = LD->getBasePtr();
8505 SDValue NewLD1 = DAG.getLoad(MVT::i32, DL, LD->getChain(), BasePtr,
8506 LD->getPointerInfo(), LD->isVolatile(),
8507 LD->isNonTemporal(), LD->isInvariant(),
8508 LD->getAlignment());
8510 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
8511 DAG.getConstant(4, DL, MVT::i32));
8512 SDValue NewLD2 = DAG.getLoad(MVT::i32, DL, NewLD1.getValue(1), OffsetPtr,
8513 LD->getPointerInfo(), LD->isVolatile(),
8514 LD->isNonTemporal(), LD->isInvariant(),
8515 std::min(4U, LD->getAlignment() / 2));
8517 DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), NewLD2.getValue(1));
8518 if (DCI.DAG.getTargetLoweringInfo().isBigEndian())
8519 std::swap (NewLD1, NewLD2);
8520 SDValue Result = DCI.CombineTo(N, NewLD1, NewLD2);
8527 /// PerformVMOVDRRCombine - Target-specific dag combine xforms for
8528 /// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands.
8529 static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) {
8530 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X)
8531 SDValue Op0 = N->getOperand(0);
8532 SDValue Op1 = N->getOperand(1);
8533 if (Op0.getOpcode() == ISD::BITCAST)
8534 Op0 = Op0.getOperand(0);
8535 if (Op1.getOpcode() == ISD::BITCAST)
8536 Op1 = Op1.getOperand(0);
8537 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
8538 Op0.getNode() == Op1.getNode() &&
8539 Op0.getResNo() == 0 && Op1.getResNo() == 1)
8540 return DAG.getNode(ISD::BITCAST, SDLoc(N),
8541 N->getValueType(0), Op0.getOperand(0));
8545 /// hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node
8546 /// are normal, non-volatile loads. If so, it is profitable to bitcast an
8547 /// i64 vector to have f64 elements, since the value can then be loaded
8548 /// directly into a VFP register.
8549 static bool hasNormalLoadOperand(SDNode *N) {
8550 unsigned NumElts = N->getValueType(0).getVectorNumElements();
8551 for (unsigned i = 0; i < NumElts; ++i) {
8552 SDNode *Elt = N->getOperand(i).getNode();
8553 if (ISD::isNormalLoad(Elt) && !cast<LoadSDNode>(Elt)->isVolatile())
8559 /// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for
8560 /// ISD::BUILD_VECTOR.
8561 static SDValue PerformBUILD_VECTORCombine(SDNode *N,
8562 TargetLowering::DAGCombinerInfo &DCI,
8563 const ARMSubtarget *Subtarget) {
8564 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X):
8565 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value
8566 // into a pair of GPRs, which is fine when the value is used as a scalar,
8567 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD.
8568 SelectionDAG &DAG = DCI.DAG;
8569 if (N->getNumOperands() == 2) {
8570 SDValue RV = PerformVMOVDRRCombine(N, DAG);
8575 // Load i64 elements as f64 values so that type legalization does not split
8576 // them up into i32 values.
8577 EVT VT = N->getValueType(0);
8578 if (VT.getVectorElementType() != MVT::i64 || !hasNormalLoadOperand(N))
8581 SmallVector<SDValue, 8> Ops;
8582 unsigned NumElts = VT.getVectorNumElements();
8583 for (unsigned i = 0; i < NumElts; ++i) {
8584 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(i));
8586 // Make the DAGCombiner fold the bitcast.
8587 DCI.AddToWorklist(V.getNode());
8589 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, NumElts);
8590 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, FloatVT, Ops);
8591 return DAG.getNode(ISD::BITCAST, dl, VT, BV);
8594 /// \brief Target-specific dag combine xforms for ARMISD::BUILD_VECTOR.
8596 PerformARMBUILD_VECTORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
8597 // ARMISD::BUILD_VECTOR is introduced when legalizing ISD::BUILD_VECTOR.
8598 // At that time, we may have inserted bitcasts from integer to float.
8599 // If these bitcasts have survived DAGCombine, change the lowering of this
8600 // BUILD_VECTOR in something more vector friendly, i.e., that does not
8601 // force to use floating point types.
8603 // Make sure we can change the type of the vector.
8604 // This is possible iff:
8605 // 1. The vector is only used in a bitcast to a integer type. I.e.,
8606 // 1.1. Vector is used only once.
8607 // 1.2. Use is a bit convert to an integer type.
8608 // 2. The size of its operands are 32-bits (64-bits are not legal).
8609 EVT VT = N->getValueType(0);
8610 EVT EltVT = VT.getVectorElementType();
8612 // Check 1.1. and 2.
8613 if (EltVT.getSizeInBits() != 32 || !N->hasOneUse())
8616 // By construction, the input type must be float.
8617 assert(EltVT == MVT::f32 && "Unexpected type!");
8620 SDNode *Use = *N->use_begin();
8621 if (Use->getOpcode() != ISD::BITCAST ||
8622 Use->getValueType(0).isFloatingPoint())
8625 // Check profitability.
8626 // Model is, if more than half of the relevant operands are bitcast from
8627 // i32, turn the build_vector into a sequence of insert_vector_elt.
8628 // Relevant operands are everything that is not statically
8629 // (i.e., at compile time) bitcasted.
8630 unsigned NumOfBitCastedElts = 0;
8631 unsigned NumElts = VT.getVectorNumElements();
8632 unsigned NumOfRelevantElts = NumElts;
8633 for (unsigned Idx = 0; Idx < NumElts; ++Idx) {
8634 SDValue Elt = N->getOperand(Idx);
8635 if (Elt->getOpcode() == ISD::BITCAST) {
8636 // Assume only bit cast to i32 will go away.
8637 if (Elt->getOperand(0).getValueType() == MVT::i32)
8638 ++NumOfBitCastedElts;
8639 } else if (Elt.getOpcode() == ISD::UNDEF || isa<ConstantSDNode>(Elt))
8640 // Constants are statically casted, thus do not count them as
8641 // relevant operands.
8642 --NumOfRelevantElts;
8645 // Check if more than half of the elements require a non-free bitcast.
8646 if (NumOfBitCastedElts <= NumOfRelevantElts / 2)
8649 SelectionDAG &DAG = DCI.DAG;
8650 // Create the new vector type.
8651 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
8652 // Check if the type is legal.
8653 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8654 if (!TLI.isTypeLegal(VecVT))
8658 // ARMISD::BUILD_VECTOR E1, E2, ..., EN.
8659 // => BITCAST INSERT_VECTOR_ELT
8660 // (INSERT_VECTOR_ELT (...), (BITCAST EN-1), N-1),
8662 SDValue Vec = DAG.getUNDEF(VecVT);
8664 for (unsigned Idx = 0 ; Idx < NumElts; ++Idx) {
8665 SDValue V = N->getOperand(Idx);
8666 if (V.getOpcode() == ISD::UNDEF)
8668 if (V.getOpcode() == ISD::BITCAST &&
8669 V->getOperand(0).getValueType() == MVT::i32)
8670 // Fold obvious case.
8671 V = V.getOperand(0);
8673 V = DAG.getNode(ISD::BITCAST, SDLoc(V), MVT::i32, V);
8674 // Make the DAGCombiner fold the bitcasts.
8675 DCI.AddToWorklist(V.getNode());
8677 SDValue LaneIdx = DAG.getConstant(Idx, dl, MVT::i32);
8678 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecVT, Vec, V, LaneIdx);
8680 Vec = DAG.getNode(ISD::BITCAST, dl, VT, Vec);
8681 // Make the DAGCombiner fold the bitcasts.
8682 DCI.AddToWorklist(Vec.getNode());
8686 /// PerformInsertEltCombine - Target-specific dag combine xforms for
8687 /// ISD::INSERT_VECTOR_ELT.
8688 static SDValue PerformInsertEltCombine(SDNode *N,
8689 TargetLowering::DAGCombinerInfo &DCI) {
8690 // Bitcast an i64 load inserted into a vector to f64.
8691 // Otherwise, the i64 value will be legalized to a pair of i32 values.
8692 EVT VT = N->getValueType(0);
8693 SDNode *Elt = N->getOperand(1).getNode();
8694 if (VT.getVectorElementType() != MVT::i64 ||
8695 !ISD::isNormalLoad(Elt) || cast<LoadSDNode>(Elt)->isVolatile())
8698 SelectionDAG &DAG = DCI.DAG;
8700 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
8701 VT.getVectorNumElements());
8702 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, N->getOperand(0));
8703 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(1));
8704 // Make the DAGCombiner fold the bitcasts.
8705 DCI.AddToWorklist(Vec.getNode());
8706 DCI.AddToWorklist(V.getNode());
8707 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT,
8708 Vec, V, N->getOperand(2));
8709 return DAG.getNode(ISD::BITCAST, dl, VT, InsElt);
8712 /// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for
8713 /// ISD::VECTOR_SHUFFLE.
8714 static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) {
8715 // The LLVM shufflevector instruction does not require the shuffle mask
8716 // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does
8717 // have that requirement. When translating to ISD::VECTOR_SHUFFLE, if the
8718 // operands do not match the mask length, they are extended by concatenating
8719 // them with undef vectors. That is probably the right thing for other
8720 // targets, but for NEON it is better to concatenate two double-register
8721 // size vector operands into a single quad-register size vector. Do that
8722 // transformation here:
8723 // shuffle(concat(v1, undef), concat(v2, undef)) ->
8724 // shuffle(concat(v1, v2), undef)
8725 SDValue Op0 = N->getOperand(0);
8726 SDValue Op1 = N->getOperand(1);
8727 if (Op0.getOpcode() != ISD::CONCAT_VECTORS ||
8728 Op1.getOpcode() != ISD::CONCAT_VECTORS ||
8729 Op0.getNumOperands() != 2 ||
8730 Op1.getNumOperands() != 2)
8732 SDValue Concat0Op1 = Op0.getOperand(1);
8733 SDValue Concat1Op1 = Op1.getOperand(1);
8734 if (Concat0Op1.getOpcode() != ISD::UNDEF ||
8735 Concat1Op1.getOpcode() != ISD::UNDEF)
8737 // Skip the transformation if any of the types are illegal.
8738 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8739 EVT VT = N->getValueType(0);
8740 if (!TLI.isTypeLegal(VT) ||
8741 !TLI.isTypeLegal(Concat0Op1.getValueType()) ||
8742 !TLI.isTypeLegal(Concat1Op1.getValueType()))
8745 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT,
8746 Op0.getOperand(0), Op1.getOperand(0));
8747 // Translate the shuffle mask.
8748 SmallVector<int, 16> NewMask;
8749 unsigned NumElts = VT.getVectorNumElements();
8750 unsigned HalfElts = NumElts/2;
8751 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
8752 for (unsigned n = 0; n < NumElts; ++n) {
8753 int MaskElt = SVN->getMaskElt(n);
8755 if (MaskElt < (int)HalfElts)
8757 else if (MaskElt >= (int)NumElts && MaskElt < (int)(NumElts + HalfElts))
8758 NewElt = HalfElts + MaskElt - NumElts;
8759 NewMask.push_back(NewElt);
8761 return DAG.getVectorShuffle(VT, SDLoc(N), NewConcat,
8762 DAG.getUNDEF(VT), NewMask.data());
8765 /// CombineBaseUpdate - Target-specific DAG combine function for VLDDUP,
8766 /// NEON load/store intrinsics, and generic vector load/stores, to merge
8767 /// base address updates.
8768 /// For generic load/stores, the memory type is assumed to be a vector.
8769 /// The caller is assumed to have checked legality.
8770 static SDValue CombineBaseUpdate(SDNode *N,
8771 TargetLowering::DAGCombinerInfo &DCI) {
8772 SelectionDAG &DAG = DCI.DAG;
8773 const bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID ||
8774 N->getOpcode() == ISD::INTRINSIC_W_CHAIN);
8775 const bool isStore = N->getOpcode() == ISD::STORE;
8776 const unsigned AddrOpIdx = ((isIntrinsic || isStore) ? 2 : 1);
8777 SDValue Addr = N->getOperand(AddrOpIdx);
8778 MemSDNode *MemN = cast<MemSDNode>(N);
8781 // Search for a use of the address operand that is an increment.
8782 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
8783 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
8785 if (User->getOpcode() != ISD::ADD ||
8786 UI.getUse().getResNo() != Addr.getResNo())
8789 // Check that the add is independent of the load/store. Otherwise, folding
8790 // it would create a cycle.
8791 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
8794 // Find the new opcode for the updating load/store.
8795 bool isLoadOp = true;
8796 bool isLaneOp = false;
8797 unsigned NewOpc = 0;
8798 unsigned NumVecs = 0;
8800 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
8802 default: llvm_unreachable("unexpected intrinsic for Neon base update");
8803 case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD;
8805 case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD;
8807 case Intrinsic::arm_neon_vld3: NewOpc = ARMISD::VLD3_UPD;
8809 case Intrinsic::arm_neon_vld4: NewOpc = ARMISD::VLD4_UPD;
8811 case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD;
8812 NumVecs = 2; isLaneOp = true; break;
8813 case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD;
8814 NumVecs = 3; isLaneOp = true; break;
8815 case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD;
8816 NumVecs = 4; isLaneOp = true; break;
8817 case Intrinsic::arm_neon_vst1: NewOpc = ARMISD::VST1_UPD;
8818 NumVecs = 1; isLoadOp = false; break;
8819 case Intrinsic::arm_neon_vst2: NewOpc = ARMISD::VST2_UPD;
8820 NumVecs = 2; isLoadOp = false; break;
8821 case Intrinsic::arm_neon_vst3: NewOpc = ARMISD::VST3_UPD;
8822 NumVecs = 3; isLoadOp = false; break;
8823 case Intrinsic::arm_neon_vst4: NewOpc = ARMISD::VST4_UPD;
8824 NumVecs = 4; isLoadOp = false; break;
8825 case Intrinsic::arm_neon_vst2lane: NewOpc = ARMISD::VST2LN_UPD;
8826 NumVecs = 2; isLoadOp = false; isLaneOp = true; break;
8827 case Intrinsic::arm_neon_vst3lane: NewOpc = ARMISD::VST3LN_UPD;
8828 NumVecs = 3; isLoadOp = false; isLaneOp = true; break;
8829 case Intrinsic::arm_neon_vst4lane: NewOpc = ARMISD::VST4LN_UPD;
8830 NumVecs = 4; isLoadOp = false; isLaneOp = true; break;
8834 switch (N->getOpcode()) {
8835 default: llvm_unreachable("unexpected opcode for Neon base update");
8836 case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break;
8837 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break;
8838 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break;
8839 case ISD::LOAD: NewOpc = ARMISD::VLD1_UPD;
8840 NumVecs = 1; isLaneOp = false; break;
8841 case ISD::STORE: NewOpc = ARMISD::VST1_UPD;
8842 NumVecs = 1; isLaneOp = false; isLoadOp = false; break;
8846 // Find the size of memory referenced by the load/store.
8849 VecTy = N->getValueType(0);
8850 } else if (isIntrinsic) {
8851 VecTy = N->getOperand(AddrOpIdx+1).getValueType();
8853 assert(isStore && "Node has to be a load, a store, or an intrinsic!");
8854 VecTy = N->getOperand(1).getValueType();
8857 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
8859 NumBytes /= VecTy.getVectorNumElements();
8861 // If the increment is a constant, it must match the memory ref size.
8862 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
8863 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
8864 uint64_t IncVal = CInc->getZExtValue();
8865 if (IncVal != NumBytes)
8867 } else if (NumBytes >= 3 * 16) {
8868 // VLD3/4 and VST3/4 for 128-bit vectors are implemented with two
8869 // separate instructions that make it harder to use a non-constant update.
8873 // OK, we found an ADD we can fold into the base update.
8874 // Now, create a _UPD node, taking care of not breaking alignment.
8876 EVT AlignedVecTy = VecTy;
8877 unsigned Alignment = MemN->getAlignment();
8879 // If this is a less-than-standard-aligned load/store, change the type to
8880 // match the standard alignment.
8881 // The alignment is overlooked when selecting _UPD variants; and it's
8882 // easier to introduce bitcasts here than fix that.
8883 // There are 3 ways to get to this base-update combine:
8884 // - intrinsics: they are assumed to be properly aligned (to the standard
8885 // alignment of the memory type), so we don't need to do anything.
8886 // - ARMISD::VLDx nodes: they are only generated from the aforementioned
8887 // intrinsics, so, likewise, there's nothing to do.
8888 // - generic load/store instructions: the alignment is specified as an
8889 // explicit operand, rather than implicitly as the standard alignment
8890 // of the memory type (like the intrisics). We need to change the
8891 // memory type to match the explicit alignment. That way, we don't
8892 // generate non-standard-aligned ARMISD::VLDx nodes.
8893 if (isa<LSBaseSDNode>(N)) {
8896 if (Alignment < VecTy.getScalarSizeInBits() / 8) {
8897 MVT EltTy = MVT::getIntegerVT(Alignment * 8);
8898 assert(NumVecs == 1 && "Unexpected multi-element generic load/store.");
8899 assert(!isLaneOp && "Unexpected generic load/store lane.");
8900 unsigned NumElts = NumBytes / (EltTy.getSizeInBits() / 8);
8901 AlignedVecTy = MVT::getVectorVT(EltTy, NumElts);
8903 // Don't set an explicit alignment on regular load/stores that we want
8904 // to transform to VLD/VST 1_UPD nodes.
8905 // This matches the behavior of regular load/stores, which only get an
8906 // explicit alignment if the MMO alignment is larger than the standard
8907 // alignment of the memory type.
8908 // Intrinsics, however, always get an explicit alignment, set to the
8909 // alignment of the MMO.
8913 // Create the new updating load/store node.
8914 // First, create an SDVTList for the new updating node's results.
8916 unsigned NumResultVecs = (isLoadOp ? NumVecs : 0);
8918 for (n = 0; n < NumResultVecs; ++n)
8919 Tys[n] = AlignedVecTy;
8920 Tys[n++] = MVT::i32;
8921 Tys[n] = MVT::Other;
8922 SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumResultVecs+2));
8924 // Then, gather the new node's operands.
8925 SmallVector<SDValue, 8> Ops;
8926 Ops.push_back(N->getOperand(0)); // incoming chain
8927 Ops.push_back(N->getOperand(AddrOpIdx));
8930 if (StoreSDNode *StN = dyn_cast<StoreSDNode>(N)) {
8931 // Try to match the intrinsic's signature
8932 Ops.push_back(StN->getValue());
8934 // Loads (and of course intrinsics) match the intrinsics' signature,
8935 // so just add all but the alignment operand.
8936 for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands() - 1; ++i)
8937 Ops.push_back(N->getOperand(i));
8940 // For all node types, the alignment operand is always the last one.
8941 Ops.push_back(DAG.getConstant(Alignment, dl, MVT::i32));
8943 // If this is a non-standard-aligned STORE, the penultimate operand is the
8944 // stored value. Bitcast it to the aligned type.
8945 if (AlignedVecTy != VecTy && N->getOpcode() == ISD::STORE) {
8946 SDValue &StVal = Ops[Ops.size()-2];
8947 StVal = DAG.getNode(ISD::BITCAST, dl, AlignedVecTy, StVal);
8950 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, dl, SDTys,
8952 MemN->getMemOperand());
8955 SmallVector<SDValue, 5> NewResults;
8956 for (unsigned i = 0; i < NumResultVecs; ++i)
8957 NewResults.push_back(SDValue(UpdN.getNode(), i));
8959 // If this is an non-standard-aligned LOAD, the first result is the loaded
8960 // value. Bitcast it to the expected result type.
8961 if (AlignedVecTy != VecTy && N->getOpcode() == ISD::LOAD) {
8962 SDValue &LdVal = NewResults[0];
8963 LdVal = DAG.getNode(ISD::BITCAST, dl, VecTy, LdVal);
8966 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs+1)); // chain
8967 DCI.CombineTo(N, NewResults);
8968 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
8975 static SDValue PerformVLDCombine(SDNode *N,
8976 TargetLowering::DAGCombinerInfo &DCI) {
8977 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
8980 return CombineBaseUpdate(N, DCI);
8983 /// CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a
8984 /// vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic
8985 /// are also VDUPLANEs. If so, combine them to a vldN-dup operation and
8987 static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
8988 SelectionDAG &DAG = DCI.DAG;
8989 EVT VT = N->getValueType(0);
8990 // vldN-dup instructions only support 64-bit vectors for N > 1.
8991 if (!VT.is64BitVector())
8994 // Check if the VDUPLANE operand is a vldN-dup intrinsic.
8995 SDNode *VLD = N->getOperand(0).getNode();
8996 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN)
8998 unsigned NumVecs = 0;
8999 unsigned NewOpc = 0;
9000 unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue();
9001 if (IntNo == Intrinsic::arm_neon_vld2lane) {
9003 NewOpc = ARMISD::VLD2DUP;
9004 } else if (IntNo == Intrinsic::arm_neon_vld3lane) {
9006 NewOpc = ARMISD::VLD3DUP;
9007 } else if (IntNo == Intrinsic::arm_neon_vld4lane) {
9009 NewOpc = ARMISD::VLD4DUP;
9014 // First check that all the vldN-lane uses are VDUPLANEs and that the lane
9015 // numbers match the load.
9016 unsigned VLDLaneNo =
9017 cast<ConstantSDNode>(VLD->getOperand(NumVecs+3))->getZExtValue();
9018 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
9020 // Ignore uses of the chain result.
9021 if (UI.getUse().getResNo() == NumVecs)
9024 if (User->getOpcode() != ARMISD::VDUPLANE ||
9025 VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue())
9029 // Create the vldN-dup node.
9032 for (n = 0; n < NumVecs; ++n)
9034 Tys[n] = MVT::Other;
9035 SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumVecs+1));
9036 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) };
9037 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD);
9038 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, SDLoc(VLD), SDTys,
9039 Ops, VLDMemInt->getMemoryVT(),
9040 VLDMemInt->getMemOperand());
9043 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
9045 unsigned ResNo = UI.getUse().getResNo();
9046 // Ignore uses of the chain result.
9047 if (ResNo == NumVecs)
9050 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo));
9053 // Now the vldN-lane intrinsic is dead except for its chain result.
9054 // Update uses of the chain.
9055 std::vector<SDValue> VLDDupResults;
9056 for (unsigned n = 0; n < NumVecs; ++n)
9057 VLDDupResults.push_back(SDValue(VLDDup.getNode(), n));
9058 VLDDupResults.push_back(SDValue(VLDDup.getNode(), NumVecs));
9059 DCI.CombineTo(VLD, VLDDupResults);
9064 /// PerformVDUPLANECombine - Target-specific dag combine xforms for
9065 /// ARMISD::VDUPLANE.
9066 static SDValue PerformVDUPLANECombine(SDNode *N,
9067 TargetLowering::DAGCombinerInfo &DCI) {
9068 SDValue Op = N->getOperand(0);
9070 // If the source is a vldN-lane (N > 1) intrinsic, and all the other uses
9071 // of that intrinsic are also VDUPLANEs, combine them to a vldN-dup operation.
9072 if (CombineVLDDUP(N, DCI))
9073 return SDValue(N, 0);
9075 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
9076 // redundant. Ignore bit_converts for now; element sizes are checked below.
9077 while (Op.getOpcode() == ISD::BITCAST)
9078 Op = Op.getOperand(0);
9079 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
9082 // Make sure the VMOV element size is not bigger than the VDUPLANE elements.
9083 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits();
9084 // The canonical VMOV for a zero vector uses a 32-bit element size.
9085 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9087 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
9089 EVT VT = N->getValueType(0);
9090 if (EltSize > VT.getVectorElementType().getSizeInBits())
9093 return DCI.DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
9096 static SDValue PerformLOADCombine(SDNode *N,
9097 TargetLowering::DAGCombinerInfo &DCI) {
9098 EVT VT = N->getValueType(0);
9100 // If this is a legal vector load, try to combine it into a VLD1_UPD.
9101 if (ISD::isNormalLoad(N) && VT.isVector() &&
9102 DCI.DAG.getTargetLoweringInfo().isTypeLegal(VT))
9103 return CombineBaseUpdate(N, DCI);
9108 /// PerformSTORECombine - Target-specific dag combine xforms for
9110 static SDValue PerformSTORECombine(SDNode *N,
9111 TargetLowering::DAGCombinerInfo &DCI) {
9112 StoreSDNode *St = cast<StoreSDNode>(N);
9113 if (St->isVolatile())
9116 // Optimize trunc store (of multiple scalars) to shuffle and store. First,
9117 // pack all of the elements in one place. Next, store to memory in fewer
9119 SDValue StVal = St->getValue();
9120 EVT VT = StVal.getValueType();
9121 if (St->isTruncatingStore() && VT.isVector()) {
9122 SelectionDAG &DAG = DCI.DAG;
9123 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9124 EVT StVT = St->getMemoryVT();
9125 unsigned NumElems = VT.getVectorNumElements();
9126 assert(StVT != VT && "Cannot truncate to the same type");
9127 unsigned FromEltSz = VT.getVectorElementType().getSizeInBits();
9128 unsigned ToEltSz = StVT.getVectorElementType().getSizeInBits();
9130 // From, To sizes and ElemCount must be pow of two
9131 if (!isPowerOf2_32(NumElems * FromEltSz * ToEltSz)) return SDValue();
9133 // We are going to use the original vector elt for storing.
9134 // Accumulated smaller vector elements must be a multiple of the store size.
9135 if (0 != (NumElems * FromEltSz) % ToEltSz) return SDValue();
9137 unsigned SizeRatio = FromEltSz / ToEltSz;
9138 assert(SizeRatio * NumElems * ToEltSz == VT.getSizeInBits());
9140 // Create a type on which we perform the shuffle.
9141 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), StVT.getScalarType(),
9142 NumElems*SizeRatio);
9143 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
9146 SDValue WideVec = DAG.getNode(ISD::BITCAST, DL, WideVecVT, StVal);
9147 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
9148 for (unsigned i = 0; i < NumElems; ++i)
9149 ShuffleVec[i] = TLI.isBigEndian() ? (i+1) * SizeRatio - 1 : i * SizeRatio;
9151 // Can't shuffle using an illegal type.
9152 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
9154 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, DL, WideVec,
9155 DAG.getUNDEF(WideVec.getValueType()),
9157 // At this point all of the data is stored at the bottom of the
9158 // register. We now need to save it to mem.
9160 // Find the largest store unit
9161 MVT StoreType = MVT::i8;
9162 for (MVT Tp : MVT::integer_valuetypes()) {
9163 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToEltSz)
9166 // Didn't find a legal store type.
9167 if (!TLI.isTypeLegal(StoreType))
9170 // Bitcast the original vector into a vector of store-size units
9171 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
9172 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
9173 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
9174 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, DL, StoreVecVT, Shuff);
9175 SmallVector<SDValue, 8> Chains;
9176 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8, DL,
9177 TLI.getPointerTy());
9178 SDValue BasePtr = St->getBasePtr();
9180 // Perform one or more big stores into memory.
9181 unsigned E = (ToEltSz*NumElems)/StoreType.getSizeInBits();
9182 for (unsigned I = 0; I < E; I++) {
9183 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
9184 StoreType, ShuffWide,
9185 DAG.getIntPtrConstant(I, DL));
9186 SDValue Ch = DAG.getStore(St->getChain(), DL, SubVec, BasePtr,
9187 St->getPointerInfo(), St->isVolatile(),
9188 St->isNonTemporal(), St->getAlignment());
9189 BasePtr = DAG.getNode(ISD::ADD, DL, BasePtr.getValueType(), BasePtr,
9191 Chains.push_back(Ch);
9193 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
9196 if (!ISD::isNormalStore(St))
9199 // Split a store of a VMOVDRR into two integer stores to avoid mixing NEON and
9200 // ARM stores of arguments in the same cache line.
9201 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR &&
9202 StVal.getNode()->hasOneUse()) {
9203 SelectionDAG &DAG = DCI.DAG;
9204 bool isBigEndian = DAG.getTargetLoweringInfo().isBigEndian();
9206 SDValue BasePtr = St->getBasePtr();
9207 SDValue NewST1 = DAG.getStore(St->getChain(), DL,
9208 StVal.getNode()->getOperand(isBigEndian ? 1 : 0 ),
9209 BasePtr, St->getPointerInfo(), St->isVolatile(),
9210 St->isNonTemporal(), St->getAlignment());
9212 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
9213 DAG.getConstant(4, DL, MVT::i32));
9214 return DAG.getStore(NewST1.getValue(0), DL,
9215 StVal.getNode()->getOperand(isBigEndian ? 0 : 1),
9216 OffsetPtr, St->getPointerInfo(), St->isVolatile(),
9217 St->isNonTemporal(),
9218 std::min(4U, St->getAlignment() / 2));
9221 if (StVal.getValueType() == MVT::i64 &&
9222 StVal.getNode()->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
9224 // Bitcast an i64 store extracted from a vector to f64.
9225 // Otherwise, the i64 value will be legalized to a pair of i32 values.
9226 SelectionDAG &DAG = DCI.DAG;
9228 SDValue IntVec = StVal.getOperand(0);
9229 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
9230 IntVec.getValueType().getVectorNumElements());
9231 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec);
9232 SDValue ExtElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
9233 Vec, StVal.getOperand(1));
9235 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt);
9236 // Make the DAGCombiner fold the bitcasts.
9237 DCI.AddToWorklist(Vec.getNode());
9238 DCI.AddToWorklist(ExtElt.getNode());
9239 DCI.AddToWorklist(V.getNode());
9240 return DAG.getStore(St->getChain(), dl, V, St->getBasePtr(),
9241 St->getPointerInfo(), St->isVolatile(),
9242 St->isNonTemporal(), St->getAlignment(),
9246 // If this is a legal vector store, try to combine it into a VST1_UPD.
9247 if (ISD::isNormalStore(N) && VT.isVector() &&
9248 DCI.DAG.getTargetLoweringInfo().isTypeLegal(VT))
9249 return CombineBaseUpdate(N, DCI);
9254 // isConstVecPow2 - Return true if each vector element is a power of 2, all
9255 // elements are the same constant, C, and Log2(C) ranges from 1 to 32.
9256 static bool isConstVecPow2(SDValue ConstVec, bool isSigned, uint64_t &C)
9260 for (unsigned I = 0, E = ConstVec.getValueType().getVectorNumElements();
9262 ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(ConstVec.getOperand(I));
9267 APFloat APF = C->getValueAPF();
9268 if (APF.convertToInteger(&cN, 64, isSigned, APFloat::rmTowardZero, &isExact)
9269 != APFloat::opOK || !isExact)
9272 c0 = (I == 0) ? cN : c0;
9273 if (!isPowerOf2_64(cN) || c0 != cN || Log2_64(c0) < 1 || Log2_64(c0) > 32)
9280 /// PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD)
9281 /// can replace combinations of VMUL and VCVT (floating-point to integer)
9282 /// when the VMUL has a constant operand that is a power of 2.
9284 /// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
9285 /// vmul.f32 d16, d17, d16
9286 /// vcvt.s32.f32 d16, d16
9288 /// vcvt.s32.f32 d16, d16, #3
9289 static SDValue PerformVCVTCombine(SDNode *N,
9290 TargetLowering::DAGCombinerInfo &DCI,
9291 const ARMSubtarget *Subtarget) {
9292 SelectionDAG &DAG = DCI.DAG;
9293 SDValue Op = N->getOperand(0);
9295 if (!Subtarget->hasNEON() || !Op.getValueType().isVector() ||
9296 Op.getOpcode() != ISD::FMUL)
9300 SDValue N0 = Op->getOperand(0);
9301 SDValue ConstVec = Op->getOperand(1);
9302 bool isSigned = N->getOpcode() == ISD::FP_TO_SINT;
9304 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
9305 !isConstVecPow2(ConstVec, isSigned, C))
9308 MVT FloatTy = Op.getSimpleValueType().getVectorElementType();
9309 MVT IntTy = N->getSimpleValueType(0).getVectorElementType();
9310 unsigned NumLanes = Op.getValueType().getVectorNumElements();
9311 if (FloatTy.getSizeInBits() != 32 || IntTy.getSizeInBits() > 32 ||
9313 // These instructions only exist converting from f32 to i32. We can handle
9314 // smaller integers by generating an extra truncate, but larger ones would
9315 // be lossy. We also can't handle more then 4 lanes, since these intructions
9316 // only support v2i32/v4i32 types.
9321 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfp2fxs :
9322 Intrinsic::arm_neon_vcvtfp2fxu;
9323 SDValue FixConv = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl,
9324 NumLanes == 2 ? MVT::v2i32 : MVT::v4i32,
9325 DAG.getConstant(IntrinsicOpcode, dl, MVT::i32),
9327 DAG.getConstant(Log2_64(C), dl, MVT::i32));
9329 if (IntTy.getSizeInBits() < FloatTy.getSizeInBits())
9330 FixConv = DAG.getNode(ISD::TRUNCATE, dl, N->getValueType(0), FixConv);
9335 /// PerformVDIVCombine - VCVT (fixed-point to floating-point, Advanced SIMD)
9336 /// can replace combinations of VCVT (integer to floating-point) and VDIV
9337 /// when the VDIV has a constant operand that is a power of 2.
9339 /// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
9340 /// vcvt.f32.s32 d16, d16
9341 /// vdiv.f32 d16, d17, d16
9343 /// vcvt.f32.s32 d16, d16, #3
9344 static SDValue PerformVDIVCombine(SDNode *N,
9345 TargetLowering::DAGCombinerInfo &DCI,
9346 const ARMSubtarget *Subtarget) {
9347 SelectionDAG &DAG = DCI.DAG;
9348 SDValue Op = N->getOperand(0);
9349 unsigned OpOpcode = Op.getNode()->getOpcode();
9351 if (!Subtarget->hasNEON() || !N->getValueType(0).isVector() ||
9352 (OpOpcode != ISD::SINT_TO_FP && OpOpcode != ISD::UINT_TO_FP))
9356 SDValue ConstVec = N->getOperand(1);
9357 bool isSigned = OpOpcode == ISD::SINT_TO_FP;
9359 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
9360 !isConstVecPow2(ConstVec, isSigned, C))
9363 MVT FloatTy = N->getSimpleValueType(0).getVectorElementType();
9364 MVT IntTy = Op.getOperand(0).getSimpleValueType().getVectorElementType();
9365 if (FloatTy.getSizeInBits() != 32 || IntTy.getSizeInBits() > 32) {
9366 // These instructions only exist converting from i32 to f32. We can handle
9367 // smaller integers by generating an extra extend, but larger ones would
9373 SDValue ConvInput = Op.getOperand(0);
9374 unsigned NumLanes = Op.getValueType().getVectorNumElements();
9375 if (IntTy.getSizeInBits() < FloatTy.getSizeInBits())
9376 ConvInput = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
9377 dl, NumLanes == 2 ? MVT::v2i32 : MVT::v4i32,
9380 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfxs2fp :
9381 Intrinsic::arm_neon_vcvtfxu2fp;
9382 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl,
9384 DAG.getConstant(IntrinsicOpcode, dl, MVT::i32),
9385 ConvInput, DAG.getConstant(Log2_64(C), dl, MVT::i32));
9388 /// Getvshiftimm - Check if this is a valid build_vector for the immediate
9389 /// operand of a vector shift operation, where all the elements of the
9390 /// build_vector must have the same constant integer value.
9391 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
9392 // Ignore bit_converts.
9393 while (Op.getOpcode() == ISD::BITCAST)
9394 Op = Op.getOperand(0);
9395 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
9396 APInt SplatBits, SplatUndef;
9397 unsigned SplatBitSize;
9399 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
9400 HasAnyUndefs, ElementBits) ||
9401 SplatBitSize > ElementBits)
9403 Cnt = SplatBits.getSExtValue();
9407 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
9408 /// operand of a vector shift left operation. That value must be in the range:
9409 /// 0 <= Value < ElementBits for a left shift; or
9410 /// 0 <= Value <= ElementBits for a long left shift.
9411 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
9412 assert(VT.isVector() && "vector shift count is not a vector type");
9413 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
9414 if (! getVShiftImm(Op, ElementBits, Cnt))
9416 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
9419 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
9420 /// operand of a vector shift right operation. For a shift opcode, the value
9421 /// is positive, but for an intrinsic the value count must be negative. The
9422 /// absolute value must be in the range:
9423 /// 1 <= |Value| <= ElementBits for a right shift; or
9424 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
9425 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
9427 assert(VT.isVector() && "vector shift count is not a vector type");
9428 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
9429 if (! getVShiftImm(Op, ElementBits, Cnt))
9433 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
9436 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
9437 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
9438 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
9441 // Don't do anything for most intrinsics.
9444 // Vector shifts: check for immediate versions and lower them.
9445 // Note: This is done during DAG combining instead of DAG legalizing because
9446 // the build_vectors for 64-bit vector element shift counts are generally
9447 // not legal, and it is hard to see their values after they get legalized to
9448 // loads from a constant pool.
9449 case Intrinsic::arm_neon_vshifts:
9450 case Intrinsic::arm_neon_vshiftu:
9451 case Intrinsic::arm_neon_vrshifts:
9452 case Intrinsic::arm_neon_vrshiftu:
9453 case Intrinsic::arm_neon_vrshiftn:
9454 case Intrinsic::arm_neon_vqshifts:
9455 case Intrinsic::arm_neon_vqshiftu:
9456 case Intrinsic::arm_neon_vqshiftsu:
9457 case Intrinsic::arm_neon_vqshiftns:
9458 case Intrinsic::arm_neon_vqshiftnu:
9459 case Intrinsic::arm_neon_vqshiftnsu:
9460 case Intrinsic::arm_neon_vqrshiftns:
9461 case Intrinsic::arm_neon_vqrshiftnu:
9462 case Intrinsic::arm_neon_vqrshiftnsu: {
9463 EVT VT = N->getOperand(1).getValueType();
9465 unsigned VShiftOpc = 0;
9468 case Intrinsic::arm_neon_vshifts:
9469 case Intrinsic::arm_neon_vshiftu:
9470 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
9471 VShiftOpc = ARMISD::VSHL;
9474 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
9475 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
9476 ARMISD::VSHRs : ARMISD::VSHRu);
9481 case Intrinsic::arm_neon_vrshifts:
9482 case Intrinsic::arm_neon_vrshiftu:
9483 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
9487 case Intrinsic::arm_neon_vqshifts:
9488 case Intrinsic::arm_neon_vqshiftu:
9489 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
9493 case Intrinsic::arm_neon_vqshiftsu:
9494 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
9496 llvm_unreachable("invalid shift count for vqshlu intrinsic");
9498 case Intrinsic::arm_neon_vrshiftn:
9499 case Intrinsic::arm_neon_vqshiftns:
9500 case Intrinsic::arm_neon_vqshiftnu:
9501 case Intrinsic::arm_neon_vqshiftnsu:
9502 case Intrinsic::arm_neon_vqrshiftns:
9503 case Intrinsic::arm_neon_vqrshiftnu:
9504 case Intrinsic::arm_neon_vqrshiftnsu:
9505 // Narrowing shifts require an immediate right shift.
9506 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
9508 llvm_unreachable("invalid shift count for narrowing vector shift "
9512 llvm_unreachable("unhandled vector shift");
9516 case Intrinsic::arm_neon_vshifts:
9517 case Intrinsic::arm_neon_vshiftu:
9518 // Opcode already set above.
9520 case Intrinsic::arm_neon_vrshifts:
9521 VShiftOpc = ARMISD::VRSHRs; break;
9522 case Intrinsic::arm_neon_vrshiftu:
9523 VShiftOpc = ARMISD::VRSHRu; break;
9524 case Intrinsic::arm_neon_vrshiftn:
9525 VShiftOpc = ARMISD::VRSHRN; break;
9526 case Intrinsic::arm_neon_vqshifts:
9527 VShiftOpc = ARMISD::VQSHLs; break;
9528 case Intrinsic::arm_neon_vqshiftu:
9529 VShiftOpc = ARMISD::VQSHLu; break;
9530 case Intrinsic::arm_neon_vqshiftsu:
9531 VShiftOpc = ARMISD::VQSHLsu; break;
9532 case Intrinsic::arm_neon_vqshiftns:
9533 VShiftOpc = ARMISD::VQSHRNs; break;
9534 case Intrinsic::arm_neon_vqshiftnu:
9535 VShiftOpc = ARMISD::VQSHRNu; break;
9536 case Intrinsic::arm_neon_vqshiftnsu:
9537 VShiftOpc = ARMISD::VQSHRNsu; break;
9538 case Intrinsic::arm_neon_vqrshiftns:
9539 VShiftOpc = ARMISD::VQRSHRNs; break;
9540 case Intrinsic::arm_neon_vqrshiftnu:
9541 VShiftOpc = ARMISD::VQRSHRNu; break;
9542 case Intrinsic::arm_neon_vqrshiftnsu:
9543 VShiftOpc = ARMISD::VQRSHRNsu; break;
9547 return DAG.getNode(VShiftOpc, dl, N->getValueType(0),
9548 N->getOperand(1), DAG.getConstant(Cnt, dl, MVT::i32));
9551 case Intrinsic::arm_neon_vshiftins: {
9552 EVT VT = N->getOperand(1).getValueType();
9554 unsigned VShiftOpc = 0;
9556 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
9557 VShiftOpc = ARMISD::VSLI;
9558 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
9559 VShiftOpc = ARMISD::VSRI;
9561 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
9565 return DAG.getNode(VShiftOpc, dl, N->getValueType(0),
9566 N->getOperand(1), N->getOperand(2),
9567 DAG.getConstant(Cnt, dl, MVT::i32));
9570 case Intrinsic::arm_neon_vqrshifts:
9571 case Intrinsic::arm_neon_vqrshiftu:
9572 // No immediate versions of these to check for.
9579 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
9580 /// lowers them. As with the vector shift intrinsics, this is done during DAG
9581 /// combining instead of DAG legalizing because the build_vectors for 64-bit
9582 /// vector element shift counts are generally not legal, and it is hard to see
9583 /// their values after they get legalized to loads from a constant pool.
9584 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
9585 const ARMSubtarget *ST) {
9586 EVT VT = N->getValueType(0);
9587 if (N->getOpcode() == ISD::SRL && VT == MVT::i32 && ST->hasV6Ops()) {
9588 // Canonicalize (srl (bswap x), 16) to (rotr (bswap x), 16) if the high
9589 // 16-bits of x is zero. This optimizes rev + lsr 16 to rev16.
9590 SDValue N1 = N->getOperand(1);
9591 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
9592 SDValue N0 = N->getOperand(0);
9593 if (C->getZExtValue() == 16 && N0.getOpcode() == ISD::BSWAP &&
9594 DAG.MaskedValueIsZero(N0.getOperand(0),
9595 APInt::getHighBitsSet(32, 16)))
9596 return DAG.getNode(ISD::ROTR, SDLoc(N), VT, N0, N1);
9600 // Nothing to be done for scalar shifts.
9601 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9602 if (!VT.isVector() || !TLI.isTypeLegal(VT))
9605 assert(ST->hasNEON() && "unexpected vector shift");
9608 switch (N->getOpcode()) {
9609 default: llvm_unreachable("unexpected shift opcode");
9612 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt)) {
9614 return DAG.getNode(ARMISD::VSHL, dl, VT, N->getOperand(0),
9615 DAG.getConstant(Cnt, dl, MVT::i32));
9621 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
9622 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
9623 ARMISD::VSHRs : ARMISD::VSHRu);
9625 return DAG.getNode(VShiftOpc, dl, VT, N->getOperand(0),
9626 DAG.getConstant(Cnt, dl, MVT::i32));
9632 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
9633 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
9634 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
9635 const ARMSubtarget *ST) {
9636 SDValue N0 = N->getOperand(0);
9638 // Check for sign- and zero-extensions of vector extract operations of 8-
9639 // and 16-bit vector elements. NEON supports these directly. They are
9640 // handled during DAG combining because type legalization will promote them
9641 // to 32-bit types and it is messy to recognize the operations after that.
9642 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
9643 SDValue Vec = N0.getOperand(0);
9644 SDValue Lane = N0.getOperand(1);
9645 EVT VT = N->getValueType(0);
9646 EVT EltVT = N0.getValueType();
9647 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9649 if (VT == MVT::i32 &&
9650 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
9651 TLI.isTypeLegal(Vec.getValueType()) &&
9652 isa<ConstantSDNode>(Lane)) {
9655 switch (N->getOpcode()) {
9656 default: llvm_unreachable("unexpected opcode");
9657 case ISD::SIGN_EXTEND:
9658 Opc = ARMISD::VGETLANEs;
9660 case ISD::ZERO_EXTEND:
9661 case ISD::ANY_EXTEND:
9662 Opc = ARMISD::VGETLANEu;
9665 return DAG.getNode(Opc, SDLoc(N), VT, Vec, Lane);
9672 /// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
9673 /// to match f32 max/min patterns to use NEON vmax/vmin instructions.
9674 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
9675 const ARMSubtarget *ST) {
9676 // If the target supports NEON, try to use vmax/vmin instructions for f32
9677 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set,
9678 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
9679 // a NaN; only do the transformation when it matches that behavior.
9681 // For now only do this when using NEON for FP operations; if using VFP, it
9682 // is not obvious that the benefit outweighs the cost of switching to the
9684 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
9685 N->getValueType(0) != MVT::f32)
9688 SDValue CondLHS = N->getOperand(0);
9689 SDValue CondRHS = N->getOperand(1);
9690 SDValue LHS = N->getOperand(2);
9691 SDValue RHS = N->getOperand(3);
9692 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
9694 unsigned Opcode = 0;
9696 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
9697 IsReversed = false; // x CC y ? x : y
9698 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
9699 IsReversed = true ; // x CC y ? y : x
9713 // If LHS is NaN, an ordered comparison will be false and the result will
9714 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
9715 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
9716 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
9717 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
9719 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
9720 // will return -0, so vmin can only be used for unsafe math or if one of
9721 // the operands is known to be nonzero.
9722 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
9723 !DAG.getTarget().Options.UnsafeFPMath &&
9724 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
9726 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
9735 // If LHS is NaN, an ordered comparison will be false and the result will
9736 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
9737 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
9738 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
9739 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
9741 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
9742 // will return +0, so vmax can only be used for unsafe math or if one of
9743 // the operands is known to be nonzero.
9744 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
9745 !DAG.getTarget().Options.UnsafeFPMath &&
9746 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
9748 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
9754 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), LHS, RHS);
9757 /// PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV.
9759 ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const {
9760 SDValue Cmp = N->getOperand(4);
9761 if (Cmp.getOpcode() != ARMISD::CMPZ)
9762 // Only looking at EQ and NE cases.
9765 EVT VT = N->getValueType(0);
9767 SDValue LHS = Cmp.getOperand(0);
9768 SDValue RHS = Cmp.getOperand(1);
9769 SDValue FalseVal = N->getOperand(0);
9770 SDValue TrueVal = N->getOperand(1);
9771 SDValue ARMcc = N->getOperand(2);
9772 ARMCC::CondCodes CC =
9773 (ARMCC::CondCodes)cast<ConstantSDNode>(ARMcc)->getZExtValue();
9791 /// FIXME: Turn this into a target neutral optimization?
9793 if (CC == ARMCC::NE && FalseVal == RHS && FalseVal != LHS) {
9794 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, TrueVal, ARMcc,
9795 N->getOperand(3), Cmp);
9796 } else if (CC == ARMCC::EQ && TrueVal == RHS) {
9798 SDValue NewCmp = getARMCmp(LHS, RHS, ISD::SETNE, ARMcc, DAG, dl);
9799 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, FalseVal, ARMcc,
9800 N->getOperand(3), NewCmp);
9803 if (Res.getNode()) {
9804 APInt KnownZero, KnownOne;
9805 DAG.computeKnownBits(SDValue(N,0), KnownZero, KnownOne);
9806 // Capture demanded bits information that would be otherwise lost.
9807 if (KnownZero == 0xfffffffe)
9808 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
9809 DAG.getValueType(MVT::i1));
9810 else if (KnownZero == 0xffffff00)
9811 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
9812 DAG.getValueType(MVT::i8));
9813 else if (KnownZero == 0xffff0000)
9814 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
9815 DAG.getValueType(MVT::i16));
9821 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
9822 DAGCombinerInfo &DCI) const {
9823 switch (N->getOpcode()) {
9825 case ISD::ADDC: return PerformADDCCombine(N, DCI, Subtarget);
9826 case ISD::ADD: return PerformADDCombine(N, DCI, Subtarget);
9827 case ISD::SUB: return PerformSUBCombine(N, DCI);
9828 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
9829 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
9830 case ISD::XOR: return PerformXORCombine(N, DCI, Subtarget);
9831 case ISD::AND: return PerformANDCombine(N, DCI, Subtarget);
9832 case ARMISD::BFI: return PerformBFICombine(N, DCI);
9833 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI, Subtarget);
9834 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
9835 case ISD::STORE: return PerformSTORECombine(N, DCI);
9836 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI, Subtarget);
9837 case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI);
9838 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
9839 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
9840 case ISD::FP_TO_SINT:
9841 case ISD::FP_TO_UINT: return PerformVCVTCombine(N, DCI, Subtarget);
9842 case ISD::FDIV: return PerformVDIVCombine(N, DCI, Subtarget);
9843 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
9846 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
9847 case ISD::SIGN_EXTEND:
9848 case ISD::ZERO_EXTEND:
9849 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
9850 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
9851 case ARMISD::CMOV: return PerformCMOVCombine(N, DCI.DAG);
9852 case ISD::LOAD: return PerformLOADCombine(N, DCI);
9853 case ARMISD::VLD2DUP:
9854 case ARMISD::VLD3DUP:
9855 case ARMISD::VLD4DUP:
9856 return PerformVLDCombine(N, DCI);
9857 case ARMISD::BUILD_VECTOR:
9858 return PerformARMBUILD_VECTORCombine(N, DCI);
9859 case ISD::INTRINSIC_VOID:
9860 case ISD::INTRINSIC_W_CHAIN:
9861 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9862 case Intrinsic::arm_neon_vld1:
9863 case Intrinsic::arm_neon_vld2:
9864 case Intrinsic::arm_neon_vld3:
9865 case Intrinsic::arm_neon_vld4:
9866 case Intrinsic::arm_neon_vld2lane:
9867 case Intrinsic::arm_neon_vld3lane:
9868 case Intrinsic::arm_neon_vld4lane:
9869 case Intrinsic::arm_neon_vst1:
9870 case Intrinsic::arm_neon_vst2:
9871 case Intrinsic::arm_neon_vst3:
9872 case Intrinsic::arm_neon_vst4:
9873 case Intrinsic::arm_neon_vst2lane:
9874 case Intrinsic::arm_neon_vst3lane:
9875 case Intrinsic::arm_neon_vst4lane:
9876 return PerformVLDCombine(N, DCI);
9884 bool ARMTargetLowering::isDesirableToTransformToIntegerOp(unsigned Opc,
9886 return (VT == MVT::f32) && (Opc == ISD::LOAD || Opc == ISD::STORE);
9889 bool ARMTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
9893 // The AllowsUnaliged flag models the SCTLR.A setting in ARM cpus
9894 bool AllowsUnaligned = Subtarget->allowsUnalignedMem();
9896 switch (VT.getSimpleVT().SimpleTy) {
9902 // Unaligned access can use (for example) LRDB, LRDH, LDR
9903 if (AllowsUnaligned) {
9905 *Fast = Subtarget->hasV7Ops();
9912 // For any little-endian targets with neon, we can support unaligned ld/st
9913 // of D and Q (e.g. {D0,D1}) registers by using vld1.i8/vst1.i8.
9914 // A big-endian target may also explicitly support unaligned accesses
9915 if (Subtarget->hasNEON() && (AllowsUnaligned || isLittleEndian())) {
9925 static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign,
9926 unsigned AlignCheck) {
9927 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) &&
9928 (DstAlign == 0 || DstAlign % AlignCheck == 0));
9931 EVT ARMTargetLowering::getOptimalMemOpType(uint64_t Size,
9932 unsigned DstAlign, unsigned SrcAlign,
9933 bool IsMemset, bool ZeroMemset,
9935 MachineFunction &MF) const {
9936 const Function *F = MF.getFunction();
9938 // See if we can use NEON instructions for this...
9939 if ((!IsMemset || ZeroMemset) && Subtarget->hasNEON() &&
9940 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
9943 (memOpAlign(SrcAlign, DstAlign, 16) ||
9944 (allowsMisalignedMemoryAccesses(MVT::v2f64, 0, 1, &Fast) && Fast))) {
9946 } else if (Size >= 8 &&
9947 (memOpAlign(SrcAlign, DstAlign, 8) ||
9948 (allowsMisalignedMemoryAccesses(MVT::f64, 0, 1, &Fast) &&
9954 // Lowering to i32/i16 if the size permits.
9960 // Let the target-independent logic figure it out.
9964 bool ARMTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
9965 if (Val.getOpcode() != ISD::LOAD)
9968 EVT VT1 = Val.getValueType();
9969 if (!VT1.isSimple() || !VT1.isInteger() ||
9970 !VT2.isSimple() || !VT2.isInteger())
9973 switch (VT1.getSimpleVT().SimpleTy) {
9978 // 8-bit and 16-bit loads implicitly zero-extend to 32-bits.
9985 bool ARMTargetLowering::isVectorLoadExtDesirable(SDValue ExtVal) const {
9986 EVT VT = ExtVal.getValueType();
9988 if (!isTypeLegal(VT))
9991 // Don't create a loadext if we can fold the extension into a wide/long
9993 // If there's more than one user instruction, the loadext is desirable no
9994 // matter what. There can be two uses by the same instruction.
9995 if (ExtVal->use_empty() ||
9996 !ExtVal->use_begin()->isOnlyUserOf(ExtVal.getNode()))
9999 SDNode *U = *ExtVal->use_begin();
10000 if ((U->getOpcode() == ISD::ADD || U->getOpcode() == ISD::SUB ||
10001 U->getOpcode() == ISD::SHL || U->getOpcode() == ARMISD::VSHL))
10007 bool ARMTargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
10008 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
10011 if (!isTypeLegal(EVT::getEVT(Ty1)))
10014 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
10016 // Assuming the caller doesn't have a zeroext or signext return parameter,
10017 // truncation all the way down to i1 is valid.
10022 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
10026 unsigned Scale = 1;
10027 switch (VT.getSimpleVT().SimpleTy) {
10028 default: return false;
10043 if ((V & (Scale - 1)) != 0)
10046 return V == (V & ((1LL << 5) - 1));
10049 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
10050 const ARMSubtarget *Subtarget) {
10051 bool isNeg = false;
10057 switch (VT.getSimpleVT().SimpleTy) {
10058 default: return false;
10063 // + imm12 or - imm8
10065 return V == (V & ((1LL << 8) - 1));
10066 return V == (V & ((1LL << 12) - 1));
10069 // Same as ARM mode. FIXME: NEON?
10070 if (!Subtarget->hasVFP2())
10075 return V == (V & ((1LL << 8) - 1));
10079 /// isLegalAddressImmediate - Return true if the integer value can be used
10080 /// as the offset of the target addressing mode for load / store of the
10082 static bool isLegalAddressImmediate(int64_t V, EVT VT,
10083 const ARMSubtarget *Subtarget) {
10087 if (!VT.isSimple())
10090 if (Subtarget->isThumb1Only())
10091 return isLegalT1AddressImmediate(V, VT);
10092 else if (Subtarget->isThumb2())
10093 return isLegalT2AddressImmediate(V, VT, Subtarget);
10098 switch (VT.getSimpleVT().SimpleTy) {
10099 default: return false;
10104 return V == (V & ((1LL << 12) - 1));
10107 return V == (V & ((1LL << 8) - 1));
10110 if (!Subtarget->hasVFP2()) // FIXME: NEON?
10115 return V == (V & ((1LL << 8) - 1));
10119 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
10121 int Scale = AM.Scale;
10125 switch (VT.getSimpleVT().SimpleTy) {
10126 default: return false;
10134 Scale = Scale & ~1;
10135 return Scale == 2 || Scale == 4 || Scale == 8;
10138 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
10142 // Note, we allow "void" uses (basically, uses that aren't loads or
10143 // stores), because arm allows folding a scale into many arithmetic
10144 // operations. This should be made more precise and revisited later.
10146 // Allow r << imm, but the imm has to be a multiple of two.
10147 if (Scale & 1) return false;
10148 return isPowerOf2_32(Scale);
10152 /// isLegalAddressingMode - Return true if the addressing mode represented
10153 /// by AM is legal for this target, for a load/store of the specified type.
10154 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
10156 EVT VT = getValueType(Ty, true);
10157 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
10160 // Can never fold addr of global into load/store.
10164 switch (AM.Scale) {
10165 case 0: // no scale reg, must be "r+i" or "r", or "i".
10168 if (Subtarget->isThumb1Only())
10172 // ARM doesn't support any R+R*scale+imm addr modes.
10176 if (!VT.isSimple())
10179 if (Subtarget->isThumb2())
10180 return isLegalT2ScaledAddressingMode(AM, VT);
10182 int Scale = AM.Scale;
10183 switch (VT.getSimpleVT().SimpleTy) {
10184 default: return false;
10188 if (Scale < 0) Scale = -Scale;
10192 return isPowerOf2_32(Scale & ~1);
10196 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
10201 // Note, we allow "void" uses (basically, uses that aren't loads or
10202 // stores), because arm allows folding a scale into many arithmetic
10203 // operations. This should be made more precise and revisited later.
10205 // Allow r << imm, but the imm has to be a multiple of two.
10206 if (Scale & 1) return false;
10207 return isPowerOf2_32(Scale);
10213 /// isLegalICmpImmediate - Return true if the specified immediate is legal
10214 /// icmp immediate, that is the target has icmp instructions which can compare
10215 /// a register against the immediate without having to materialize the
10216 /// immediate into a register.
10217 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
10218 // Thumb2 and ARM modes can use cmn for negative immediates.
10219 if (!Subtarget->isThumb())
10220 return ARM_AM::getSOImmVal(std::abs(Imm)) != -1;
10221 if (Subtarget->isThumb2())
10222 return ARM_AM::getT2SOImmVal(std::abs(Imm)) != -1;
10223 // Thumb1 doesn't have cmn, and only 8-bit immediates.
10224 return Imm >= 0 && Imm <= 255;
10227 /// isLegalAddImmediate - Return true if the specified immediate is a legal add
10228 /// *or sub* immediate, that is the target has add or sub instructions which can
10229 /// add a register with the immediate without having to materialize the
10230 /// immediate into a register.
10231 bool ARMTargetLowering::isLegalAddImmediate(int64_t Imm) const {
10232 // Same encoding for add/sub, just flip the sign.
10233 int64_t AbsImm = std::abs(Imm);
10234 if (!Subtarget->isThumb())
10235 return ARM_AM::getSOImmVal(AbsImm) != -1;
10236 if (Subtarget->isThumb2())
10237 return ARM_AM::getT2SOImmVal(AbsImm) != -1;
10238 // Thumb1 only has 8-bit unsigned immediate.
10239 return AbsImm >= 0 && AbsImm <= 255;
10242 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
10243 bool isSEXTLoad, SDValue &Base,
10244 SDValue &Offset, bool &isInc,
10245 SelectionDAG &DAG) {
10246 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
10249 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
10250 // AddressingMode 3
10251 Base = Ptr->getOperand(0);
10252 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
10253 int RHSC = (int)RHS->getZExtValue();
10254 if (RHSC < 0 && RHSC > -256) {
10255 assert(Ptr->getOpcode() == ISD::ADD);
10257 Offset = DAG.getConstant(-RHSC, SDLoc(Ptr), RHS->getValueType(0));
10261 isInc = (Ptr->getOpcode() == ISD::ADD);
10262 Offset = Ptr->getOperand(1);
10264 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
10265 // AddressingMode 2
10266 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
10267 int RHSC = (int)RHS->getZExtValue();
10268 if (RHSC < 0 && RHSC > -0x1000) {
10269 assert(Ptr->getOpcode() == ISD::ADD);
10271 Offset = DAG.getConstant(-RHSC, SDLoc(Ptr), RHS->getValueType(0));
10272 Base = Ptr->getOperand(0);
10277 if (Ptr->getOpcode() == ISD::ADD) {
10279 ARM_AM::ShiftOpc ShOpcVal=
10280 ARM_AM::getShiftOpcForNode(Ptr->getOperand(0).getOpcode());
10281 if (ShOpcVal != ARM_AM::no_shift) {
10282 Base = Ptr->getOperand(1);
10283 Offset = Ptr->getOperand(0);
10285 Base = Ptr->getOperand(0);
10286 Offset = Ptr->getOperand(1);
10291 isInc = (Ptr->getOpcode() == ISD::ADD);
10292 Base = Ptr->getOperand(0);
10293 Offset = Ptr->getOperand(1);
10297 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
10301 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
10302 bool isSEXTLoad, SDValue &Base,
10303 SDValue &Offset, bool &isInc,
10304 SelectionDAG &DAG) {
10305 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
10308 Base = Ptr->getOperand(0);
10309 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
10310 int RHSC = (int)RHS->getZExtValue();
10311 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
10312 assert(Ptr->getOpcode() == ISD::ADD);
10314 Offset = DAG.getConstant(-RHSC, SDLoc(Ptr), RHS->getValueType(0));
10316 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
10317 isInc = Ptr->getOpcode() == ISD::ADD;
10318 Offset = DAG.getConstant(RHSC, SDLoc(Ptr), RHS->getValueType(0));
10326 /// getPreIndexedAddressParts - returns true by value, base pointer and
10327 /// offset pointer and addressing mode by reference if the node's address
10328 /// can be legally represented as pre-indexed load / store address.
10330 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
10332 ISD::MemIndexedMode &AM,
10333 SelectionDAG &DAG) const {
10334 if (Subtarget->isThumb1Only())
10339 bool isSEXTLoad = false;
10340 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
10341 Ptr = LD->getBasePtr();
10342 VT = LD->getMemoryVT();
10343 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
10344 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
10345 Ptr = ST->getBasePtr();
10346 VT = ST->getMemoryVT();
10351 bool isLegal = false;
10352 if (Subtarget->isThumb2())
10353 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
10354 Offset, isInc, DAG);
10356 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
10357 Offset, isInc, DAG);
10361 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
10365 /// getPostIndexedAddressParts - returns true by value, base pointer and
10366 /// offset pointer and addressing mode by reference if this node can be
10367 /// combined with a load / store to form a post-indexed load / store.
10368 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
10371 ISD::MemIndexedMode &AM,
10372 SelectionDAG &DAG) const {
10373 if (Subtarget->isThumb1Only())
10378 bool isSEXTLoad = false;
10379 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
10380 VT = LD->getMemoryVT();
10381 Ptr = LD->getBasePtr();
10382 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
10383 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
10384 VT = ST->getMemoryVT();
10385 Ptr = ST->getBasePtr();
10390 bool isLegal = false;
10391 if (Subtarget->isThumb2())
10392 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
10395 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
10401 // Swap base ptr and offset to catch more post-index load / store when
10402 // it's legal. In Thumb2 mode, offset must be an immediate.
10403 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
10404 !Subtarget->isThumb2())
10405 std::swap(Base, Offset);
10407 // Post-indexed load / store update the base pointer.
10412 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
10416 void ARMTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
10419 const SelectionDAG &DAG,
10420 unsigned Depth) const {
10421 unsigned BitWidth = KnownOne.getBitWidth();
10422 KnownZero = KnownOne = APInt(BitWidth, 0);
10423 switch (Op.getOpcode()) {
10429 // These nodes' second result is a boolean
10430 if (Op.getResNo() == 0)
10432 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
10434 case ARMISD::CMOV: {
10435 // Bits are known zero/one if known on the LHS and RHS.
10436 DAG.computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1);
10437 if (KnownZero == 0 && KnownOne == 0) return;
10439 APInt KnownZeroRHS, KnownOneRHS;
10440 DAG.computeKnownBits(Op.getOperand(1), KnownZeroRHS, KnownOneRHS, Depth+1);
10441 KnownZero &= KnownZeroRHS;
10442 KnownOne &= KnownOneRHS;
10445 case ISD::INTRINSIC_W_CHAIN: {
10446 ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
10447 Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
10450 case Intrinsic::arm_ldaex:
10451 case Intrinsic::arm_ldrex: {
10452 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();
10453 unsigned MemBits = VT.getScalarType().getSizeInBits();
10454 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
10462 //===----------------------------------------------------------------------===//
10463 // ARM Inline Assembly Support
10464 //===----------------------------------------------------------------------===//
10466 bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const {
10467 // Looking for "rev" which is V6+.
10468 if (!Subtarget->hasV6Ops())
10471 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
10472 std::string AsmStr = IA->getAsmString();
10473 SmallVector<StringRef, 4> AsmPieces;
10474 SplitString(AsmStr, AsmPieces, ";\n");
10476 switch (AsmPieces.size()) {
10477 default: return false;
10479 AsmStr = AsmPieces[0];
10481 SplitString(AsmStr, AsmPieces, " \t,");
10484 if (AsmPieces.size() == 3 &&
10485 AsmPieces[0] == "rev" && AsmPieces[1] == "$0" && AsmPieces[2] == "$1" &&
10486 IA->getConstraintString().compare(0, 4, "=l,l") == 0) {
10487 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
10488 if (Ty && Ty->getBitWidth() == 32)
10489 return IntrinsicLowering::LowerToByteSwap(CI);
10497 /// getConstraintType - Given a constraint letter, return the type of
10498 /// constraint it is for this target.
10499 ARMTargetLowering::ConstraintType
10500 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
10501 if (Constraint.size() == 1) {
10502 switch (Constraint[0]) {
10504 case 'l': return C_RegisterClass;
10505 case 'w': return C_RegisterClass;
10506 case 'h': return C_RegisterClass;
10507 case 'x': return C_RegisterClass;
10508 case 't': return C_RegisterClass;
10509 case 'j': return C_Other; // Constant for movw.
10510 // An address with a single base register. Due to the way we
10511 // currently handle addresses it is the same as an 'r' memory constraint.
10512 case 'Q': return C_Memory;
10514 } else if (Constraint.size() == 2) {
10515 switch (Constraint[0]) {
10517 // All 'U+' constraints are addresses.
10518 case 'U': return C_Memory;
10521 return TargetLowering::getConstraintType(Constraint);
10524 /// Examine constraint type and operand type and determine a weight value.
10525 /// This object must already have been set up with the operand type
10526 /// and the current alternative constraint selected.
10527 TargetLowering::ConstraintWeight
10528 ARMTargetLowering::getSingleConstraintMatchWeight(
10529 AsmOperandInfo &info, const char *constraint) const {
10530 ConstraintWeight weight = CW_Invalid;
10531 Value *CallOperandVal = info.CallOperandVal;
10532 // If we don't have a value, we can't do a match,
10533 // but allow it at the lowest weight.
10534 if (!CallOperandVal)
10536 Type *type = CallOperandVal->getType();
10537 // Look at the constraint type.
10538 switch (*constraint) {
10540 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
10543 if (type->isIntegerTy()) {
10544 if (Subtarget->isThumb())
10545 weight = CW_SpecificReg;
10547 weight = CW_Register;
10551 if (type->isFloatingPointTy())
10552 weight = CW_Register;
10558 typedef std::pair<unsigned, const TargetRegisterClass*> RCPair;
10560 ARMTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
10561 const std::string &Constraint,
10563 if (Constraint.size() == 1) {
10564 // GCC ARM Constraint Letters
10565 switch (Constraint[0]) {
10566 case 'l': // Low regs or general regs.
10567 if (Subtarget->isThumb())
10568 return RCPair(0U, &ARM::tGPRRegClass);
10569 return RCPair(0U, &ARM::GPRRegClass);
10570 case 'h': // High regs or no regs.
10571 if (Subtarget->isThumb())
10572 return RCPair(0U, &ARM::hGPRRegClass);
10575 if (Subtarget->isThumb1Only())
10576 return RCPair(0U, &ARM::tGPRRegClass);
10577 return RCPair(0U, &ARM::GPRRegClass);
10579 if (VT == MVT::Other)
10581 if (VT == MVT::f32)
10582 return RCPair(0U, &ARM::SPRRegClass);
10583 if (VT.getSizeInBits() == 64)
10584 return RCPair(0U, &ARM::DPRRegClass);
10585 if (VT.getSizeInBits() == 128)
10586 return RCPair(0U, &ARM::QPRRegClass);
10589 if (VT == MVT::Other)
10591 if (VT == MVT::f32)
10592 return RCPair(0U, &ARM::SPR_8RegClass);
10593 if (VT.getSizeInBits() == 64)
10594 return RCPair(0U, &ARM::DPR_8RegClass);
10595 if (VT.getSizeInBits() == 128)
10596 return RCPair(0U, &ARM::QPR_8RegClass);
10599 if (VT == MVT::f32)
10600 return RCPair(0U, &ARM::SPRRegClass);
10604 if (StringRef("{cc}").equals_lower(Constraint))
10605 return std::make_pair(unsigned(ARM::CPSR), &ARM::CCRRegClass);
10607 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
10610 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
10611 /// vector. If it is invalid, don't add anything to Ops.
10612 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
10613 std::string &Constraint,
10614 std::vector<SDValue>&Ops,
10615 SelectionDAG &DAG) const {
10618 // Currently only support length 1 constraints.
10619 if (Constraint.length() != 1) return;
10621 char ConstraintLetter = Constraint[0];
10622 switch (ConstraintLetter) {
10625 case 'I': case 'J': case 'K': case 'L':
10626 case 'M': case 'N': case 'O':
10627 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
10631 int64_t CVal64 = C->getSExtValue();
10632 int CVal = (int) CVal64;
10633 // None of these constraints allow values larger than 32 bits. Check
10634 // that the value fits in an int.
10635 if (CVal != CVal64)
10638 switch (ConstraintLetter) {
10640 // Constant suitable for movw, must be between 0 and
10642 if (Subtarget->hasV6T2Ops())
10643 if (CVal >= 0 && CVal <= 65535)
10647 if (Subtarget->isThumb1Only()) {
10648 // This must be a constant between 0 and 255, for ADD
10650 if (CVal >= 0 && CVal <= 255)
10652 } else if (Subtarget->isThumb2()) {
10653 // A constant that can be used as an immediate value in a
10654 // data-processing instruction.
10655 if (ARM_AM::getT2SOImmVal(CVal) != -1)
10658 // A constant that can be used as an immediate value in a
10659 // data-processing instruction.
10660 if (ARM_AM::getSOImmVal(CVal) != -1)
10666 if (Subtarget->isThumb()) { // FIXME thumb2
10667 // This must be a constant between -255 and -1, for negated ADD
10668 // immediates. This can be used in GCC with an "n" modifier that
10669 // prints the negated value, for use with SUB instructions. It is
10670 // not useful otherwise but is implemented for compatibility.
10671 if (CVal >= -255 && CVal <= -1)
10674 // This must be a constant between -4095 and 4095. It is not clear
10675 // what this constraint is intended for. Implemented for
10676 // compatibility with GCC.
10677 if (CVal >= -4095 && CVal <= 4095)
10683 if (Subtarget->isThumb1Only()) {
10684 // A 32-bit value where only one byte has a nonzero value. Exclude
10685 // zero to match GCC. This constraint is used by GCC internally for
10686 // constants that can be loaded with a move/shift combination.
10687 // It is not useful otherwise but is implemented for compatibility.
10688 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
10690 } else if (Subtarget->isThumb2()) {
10691 // A constant whose bitwise inverse can be used as an immediate
10692 // value in a data-processing instruction. This can be used in GCC
10693 // with a "B" modifier that prints the inverted value, for use with
10694 // BIC and MVN instructions. It is not useful otherwise but is
10695 // implemented for compatibility.
10696 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
10699 // A constant whose bitwise inverse can be used as an immediate
10700 // value in a data-processing instruction. This can be used in GCC
10701 // with a "B" modifier that prints the inverted value, for use with
10702 // BIC and MVN instructions. It is not useful otherwise but is
10703 // implemented for compatibility.
10704 if (ARM_AM::getSOImmVal(~CVal) != -1)
10710 if (Subtarget->isThumb1Only()) {
10711 // This must be a constant between -7 and 7,
10712 // for 3-operand ADD/SUB immediate instructions.
10713 if (CVal >= -7 && CVal < 7)
10715 } else if (Subtarget->isThumb2()) {
10716 // A constant whose negation can be used as an immediate value in a
10717 // data-processing instruction. This can be used in GCC with an "n"
10718 // modifier that prints the negated value, for use with SUB
10719 // instructions. It is not useful otherwise but is implemented for
10721 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
10724 // A constant whose negation can be used as an immediate value in a
10725 // data-processing instruction. This can be used in GCC with an "n"
10726 // modifier that prints the negated value, for use with SUB
10727 // instructions. It is not useful otherwise but is implemented for
10729 if (ARM_AM::getSOImmVal(-CVal) != -1)
10735 if (Subtarget->isThumb()) { // FIXME thumb2
10736 // This must be a multiple of 4 between 0 and 1020, for
10737 // ADD sp + immediate.
10738 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
10741 // A power of two or a constant between 0 and 32. This is used in
10742 // GCC for the shift amount on shifted register operands, but it is
10743 // useful in general for any shift amounts.
10744 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
10750 if (Subtarget->isThumb()) { // FIXME thumb2
10751 // This must be a constant between 0 and 31, for shift amounts.
10752 if (CVal >= 0 && CVal <= 31)
10758 if (Subtarget->isThumb()) { // FIXME thumb2
10759 // This must be a multiple of 4 between -508 and 508, for
10760 // ADD/SUB sp = sp + immediate.
10761 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
10766 Result = DAG.getTargetConstant(CVal, SDLoc(Op), Op.getValueType());
10770 if (Result.getNode()) {
10771 Ops.push_back(Result);
10774 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
10777 SDValue ARMTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const {
10778 assert(Subtarget->isTargetAEABI() && "Register-based DivRem lowering only");
10779 unsigned Opcode = Op->getOpcode();
10780 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
10781 "Invalid opcode for Div/Rem lowering");
10782 bool isSigned = (Opcode == ISD::SDIVREM);
10783 EVT VT = Op->getValueType(0);
10784 Type *Ty = VT.getTypeForEVT(*DAG.getContext());
10787 switch (VT.getSimpleVT().SimpleTy) {
10788 default: llvm_unreachable("Unexpected request for libcall!");
10789 case MVT::i8: LC = isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
10790 case MVT::i16: LC = isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
10791 case MVT::i32: LC = isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
10792 case MVT::i64: LC = isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
10795 SDValue InChain = DAG.getEntryNode();
10797 TargetLowering::ArgListTy Args;
10798 TargetLowering::ArgListEntry Entry;
10799 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
10800 EVT ArgVT = Op->getOperand(i).getValueType();
10801 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
10802 Entry.Node = Op->getOperand(i);
10804 Entry.isSExt = isSigned;
10805 Entry.isZExt = !isSigned;
10806 Args.push_back(Entry);
10809 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
10812 Type *RetTy = (Type*)StructType::get(Ty, Ty, nullptr);
10815 TargetLowering::CallLoweringInfo CLI(DAG);
10816 CLI.setDebugLoc(dl).setChain(InChain)
10817 .setCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
10818 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
10820 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
10821 return CallInfo.first;
10825 ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const {
10826 assert(Subtarget->isTargetWindows() && "unsupported target platform");
10830 SDValue Chain = Op.getOperand(0);
10831 SDValue Size = Op.getOperand(1);
10833 SDValue Words = DAG.getNode(ISD::SRL, DL, MVT::i32, Size,
10834 DAG.getConstant(2, DL, MVT::i32));
10837 Chain = DAG.getCopyToReg(Chain, DL, ARM::R4, Words, Flag);
10838 Flag = Chain.getValue(1);
10840 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
10841 Chain = DAG.getNode(ARMISD::WIN__CHKSTK, DL, NodeTys, Chain, Flag);
10843 SDValue NewSP = DAG.getCopyFromReg(Chain, DL, ARM::SP, MVT::i32);
10844 Chain = NewSP.getValue(1);
10846 SDValue Ops[2] = { NewSP, Chain };
10847 return DAG.getMergeValues(Ops, DL);
10850 SDValue ARMTargetLowering::LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const {
10851 assert(Op.getValueType() == MVT::f64 && Subtarget->isFPOnlySP() &&
10852 "Unexpected type for custom-lowering FP_EXTEND");
10855 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType());
10857 SDValue SrcVal = Op.getOperand(0);
10858 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
10859 /*isSigned*/ false, SDLoc(Op)).first;
10862 SDValue ARMTargetLowering::LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const {
10863 assert(Op.getOperand(0).getValueType() == MVT::f64 &&
10864 Subtarget->isFPOnlySP() &&
10865 "Unexpected type for custom-lowering FP_ROUND");
10868 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
10870 SDValue SrcVal = Op.getOperand(0);
10871 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
10872 /*isSigned*/ false, SDLoc(Op)).first;
10876 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
10877 // The ARM target isn't yet aware of offsets.
10881 bool ARM::isBitFieldInvertedMask(unsigned v) {
10882 if (v == 0xffffffff)
10885 // there can be 1's on either or both "outsides", all the "inside"
10886 // bits must be 0's
10887 return isShiftedMask_32(~v);
10890 /// isFPImmLegal - Returns true if the target can instruction select the
10891 /// specified FP immediate natively. If false, the legalizer will
10892 /// materialize the FP immediate as a load from a constant pool.
10893 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
10894 if (!Subtarget->hasVFP3())
10896 if (VT == MVT::f32)
10897 return ARM_AM::getFP32Imm(Imm) != -1;
10898 if (VT == MVT::f64 && !Subtarget->isFPOnlySP())
10899 return ARM_AM::getFP64Imm(Imm) != -1;
10903 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
10904 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
10905 /// specified in the intrinsic calls.
10906 bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
10908 unsigned Intrinsic) const {
10909 switch (Intrinsic) {
10910 case Intrinsic::arm_neon_vld1:
10911 case Intrinsic::arm_neon_vld2:
10912 case Intrinsic::arm_neon_vld3:
10913 case Intrinsic::arm_neon_vld4:
10914 case Intrinsic::arm_neon_vld2lane:
10915 case Intrinsic::arm_neon_vld3lane:
10916 case Intrinsic::arm_neon_vld4lane: {
10917 Info.opc = ISD::INTRINSIC_W_CHAIN;
10918 // Conservatively set memVT to the entire set of vectors loaded.
10919 uint64_t NumElts = getDataLayout()->getTypeAllocSize(I.getType()) / 8;
10920 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
10921 Info.ptrVal = I.getArgOperand(0);
10923 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
10924 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
10925 Info.vol = false; // volatile loads with NEON intrinsics not supported
10926 Info.readMem = true;
10927 Info.writeMem = false;
10930 case Intrinsic::arm_neon_vst1:
10931 case Intrinsic::arm_neon_vst2:
10932 case Intrinsic::arm_neon_vst3:
10933 case Intrinsic::arm_neon_vst4:
10934 case Intrinsic::arm_neon_vst2lane:
10935 case Intrinsic::arm_neon_vst3lane:
10936 case Intrinsic::arm_neon_vst4lane: {
10937 Info.opc = ISD::INTRINSIC_VOID;
10938 // Conservatively set memVT to the entire set of vectors stored.
10939 unsigned NumElts = 0;
10940 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
10941 Type *ArgTy = I.getArgOperand(ArgI)->getType();
10942 if (!ArgTy->isVectorTy())
10944 NumElts += getDataLayout()->getTypeAllocSize(ArgTy) / 8;
10946 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
10947 Info.ptrVal = I.getArgOperand(0);
10949 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
10950 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
10951 Info.vol = false; // volatile stores with NEON intrinsics not supported
10952 Info.readMem = false;
10953 Info.writeMem = true;
10956 case Intrinsic::arm_ldaex:
10957 case Intrinsic::arm_ldrex: {
10958 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
10959 Info.opc = ISD::INTRINSIC_W_CHAIN;
10960 Info.memVT = MVT::getVT(PtrTy->getElementType());
10961 Info.ptrVal = I.getArgOperand(0);
10963 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
10965 Info.readMem = true;
10966 Info.writeMem = false;
10969 case Intrinsic::arm_stlex:
10970 case Intrinsic::arm_strex: {
10971 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
10972 Info.opc = ISD::INTRINSIC_W_CHAIN;
10973 Info.memVT = MVT::getVT(PtrTy->getElementType());
10974 Info.ptrVal = I.getArgOperand(1);
10976 Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
10978 Info.readMem = false;
10979 Info.writeMem = true;
10982 case Intrinsic::arm_stlexd:
10983 case Intrinsic::arm_strexd: {
10984 Info.opc = ISD::INTRINSIC_W_CHAIN;
10985 Info.memVT = MVT::i64;
10986 Info.ptrVal = I.getArgOperand(2);
10990 Info.readMem = false;
10991 Info.writeMem = true;
10994 case Intrinsic::arm_ldaexd:
10995 case Intrinsic::arm_ldrexd: {
10996 Info.opc = ISD::INTRINSIC_W_CHAIN;
10997 Info.memVT = MVT::i64;
10998 Info.ptrVal = I.getArgOperand(0);
11002 Info.readMem = true;
11003 Info.writeMem = false;
11013 /// \brief Returns true if it is beneficial to convert a load of a constant
11014 /// to just the constant itself.
11015 bool ARMTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
11017 assert(Ty->isIntegerTy());
11019 unsigned Bits = Ty->getPrimitiveSizeInBits();
11020 if (Bits == 0 || Bits > 32)
11025 bool ARMTargetLowering::hasLoadLinkedStoreConditional() const { return true; }
11027 Instruction* ARMTargetLowering::makeDMB(IRBuilder<> &Builder,
11028 ARM_MB::MemBOpt Domain) const {
11029 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
11031 // First, if the target has no DMB, see what fallback we can use.
11032 if (!Subtarget->hasDataBarrier()) {
11033 // Some ARMv6 cpus can support data barriers with an mcr instruction.
11034 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
11036 if (Subtarget->hasV6Ops() && !Subtarget->isThumb()) {
11037 Function *MCR = llvm::Intrinsic::getDeclaration(M, Intrinsic::arm_mcr);
11038 Value* args[6] = {Builder.getInt32(15), Builder.getInt32(0),
11039 Builder.getInt32(0), Builder.getInt32(7),
11040 Builder.getInt32(10), Builder.getInt32(5)};
11041 return Builder.CreateCall(MCR, args);
11043 // Instead of using barriers, atomic accesses on these subtargets use
11045 llvm_unreachable("makeDMB on a target so old that it has no barriers");
11048 Function *DMB = llvm::Intrinsic::getDeclaration(M, Intrinsic::arm_dmb);
11049 // Only a full system barrier exists in the M-class architectures.
11050 Domain = Subtarget->isMClass() ? ARM_MB::SY : Domain;
11051 Constant *CDomain = Builder.getInt32(Domain);
11052 return Builder.CreateCall(DMB, CDomain);
11056 // Based on http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
11057 Instruction* ARMTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
11058 AtomicOrdering Ord, bool IsStore,
11059 bool IsLoad) const {
11060 if (!getInsertFencesForAtomic())
11066 llvm_unreachable("Invalid fence: unordered/non-atomic");
11069 return nullptr; // Nothing to do
11070 case SequentiallyConsistent:
11072 return nullptr; // Nothing to do
11075 case AcquireRelease:
11076 if (Subtarget->isSwift())
11077 return makeDMB(Builder, ARM_MB::ISHST);
11078 // FIXME: add a comment with a link to documentation justifying this.
11080 return makeDMB(Builder, ARM_MB::ISH);
11082 llvm_unreachable("Unknown fence ordering in emitLeadingFence");
11085 Instruction* ARMTargetLowering::emitTrailingFence(IRBuilder<> &Builder,
11086 AtomicOrdering Ord, bool IsStore,
11087 bool IsLoad) const {
11088 if (!getInsertFencesForAtomic())
11094 llvm_unreachable("Invalid fence: unordered/not-atomic");
11097 return nullptr; // Nothing to do
11099 case AcquireRelease:
11100 case SequentiallyConsistent:
11101 return makeDMB(Builder, ARM_MB::ISH);
11103 llvm_unreachable("Unknown fence ordering in emitTrailingFence");
11106 // Loads and stores less than 64-bits are already atomic; ones above that
11107 // are doomed anyway, so defer to the default libcall and blame the OS when
11108 // things go wrong. Cortex M doesn't have ldrexd/strexd though, so don't emit
11109 // anything for those.
11110 bool ARMTargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
11111 unsigned Size = SI->getValueOperand()->getType()->getPrimitiveSizeInBits();
11112 return (Size == 64) && !Subtarget->isMClass();
11115 // Loads and stores less than 64-bits are already atomic; ones above that
11116 // are doomed anyway, so defer to the default libcall and blame the OS when
11117 // things go wrong. Cortex M doesn't have ldrexd/strexd though, so don't emit
11118 // anything for those.
11119 // FIXME: ldrd and strd are atomic if the CPU has LPAE (e.g. A15 has that
11120 // guarantee, see DDI0406C ARM architecture reference manual,
11121 // sections A8.8.72-74 LDRD)
11122 bool ARMTargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
11123 unsigned Size = LI->getType()->getPrimitiveSizeInBits();
11124 return (Size == 64) && !Subtarget->isMClass();
11127 // For the real atomic operations, we have ldrex/strex up to 32 bits,
11128 // and up to 64 bits on the non-M profiles
11129 TargetLoweringBase::AtomicRMWExpansionKind
11130 ARMTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
11131 unsigned Size = AI->getType()->getPrimitiveSizeInBits();
11132 return (Size <= (Subtarget->isMClass() ? 32U : 64U))
11133 ? AtomicRMWExpansionKind::LLSC
11134 : AtomicRMWExpansionKind::None;
11137 // This has so far only been implemented for MachO.
11138 bool ARMTargetLowering::useLoadStackGuardNode() const {
11139 return Subtarget->isTargetMachO();
11142 bool ARMTargetLowering::canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
11143 unsigned &Cost) const {
11144 // If we do not have NEON, vector types are not natively supported.
11145 if (!Subtarget->hasNEON())
11148 // Floating point values and vector values map to the same register file.
11149 // Therefore, althought we could do a store extract of a vector type, this is
11150 // better to leave at float as we have more freedom in the addressing mode for
11152 if (VectorTy->isFPOrFPVectorTy())
11155 // If the index is unknown at compile time, this is very expensive to lower
11156 // and it is not possible to combine the store with the extract.
11157 if (!isa<ConstantInt>(Idx))
11160 assert(VectorTy->isVectorTy() && "VectorTy is not a vector type");
11161 unsigned BitWidth = cast<VectorType>(VectorTy)->getBitWidth();
11162 // We can do a store + vector extract on any vector that fits perfectly in a D
11164 if (BitWidth == 64 || BitWidth == 128) {
11171 Value *ARMTargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
11172 AtomicOrdering Ord) const {
11173 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
11174 Type *ValTy = cast<PointerType>(Addr->getType())->getElementType();
11175 bool IsAcquire = isAtLeastAcquire(Ord);
11177 // Since i64 isn't legal and intrinsics don't get type-lowered, the ldrexd
11178 // intrinsic must return {i32, i32} and we have to recombine them into a
11179 // single i64 here.
11180 if (ValTy->getPrimitiveSizeInBits() == 64) {
11181 Intrinsic::ID Int =
11182 IsAcquire ? Intrinsic::arm_ldaexd : Intrinsic::arm_ldrexd;
11183 Function *Ldrex = llvm::Intrinsic::getDeclaration(M, Int);
11185 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
11186 Value *LoHi = Builder.CreateCall(Ldrex, Addr, "lohi");
11188 Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo");
11189 Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi");
11190 if (!Subtarget->isLittle())
11191 std::swap (Lo, Hi);
11192 Lo = Builder.CreateZExt(Lo, ValTy, "lo64");
11193 Hi = Builder.CreateZExt(Hi, ValTy, "hi64");
11194 return Builder.CreateOr(
11195 Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 32)), "val64");
11198 Type *Tys[] = { Addr->getType() };
11199 Intrinsic::ID Int = IsAcquire ? Intrinsic::arm_ldaex : Intrinsic::arm_ldrex;
11200 Function *Ldrex = llvm::Intrinsic::getDeclaration(M, Int, Tys);
11202 return Builder.CreateTruncOrBitCast(
11203 Builder.CreateCall(Ldrex, Addr),
11204 cast<PointerType>(Addr->getType())->getElementType());
11207 Value *ARMTargetLowering::emitStoreConditional(IRBuilder<> &Builder, Value *Val,
11209 AtomicOrdering Ord) const {
11210 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
11211 bool IsRelease = isAtLeastRelease(Ord);
11213 // Since the intrinsics must have legal type, the i64 intrinsics take two
11214 // parameters: "i32, i32". We must marshal Val into the appropriate form
11215 // before the call.
11216 if (Val->getType()->getPrimitiveSizeInBits() == 64) {
11217 Intrinsic::ID Int =
11218 IsRelease ? Intrinsic::arm_stlexd : Intrinsic::arm_strexd;
11219 Function *Strex = Intrinsic::getDeclaration(M, Int);
11220 Type *Int32Ty = Type::getInt32Ty(M->getContext());
11222 Value *Lo = Builder.CreateTrunc(Val, Int32Ty, "lo");
11223 Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 32), Int32Ty, "hi");
11224 if (!Subtarget->isLittle())
11225 std::swap (Lo, Hi);
11226 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
11227 return Builder.CreateCall3(Strex, Lo, Hi, Addr);
11230 Intrinsic::ID Int = IsRelease ? Intrinsic::arm_stlex : Intrinsic::arm_strex;
11231 Type *Tys[] = { Addr->getType() };
11232 Function *Strex = Intrinsic::getDeclaration(M, Int, Tys);
11234 return Builder.CreateCall2(
11235 Strex, Builder.CreateZExtOrBitCast(
11236 Val, Strex->getFunctionType()->getParamType(0)),
11248 static bool isHomogeneousAggregate(Type *Ty, HABaseType &Base,
11249 uint64_t &Members) {
11250 if (const StructType *ST = dyn_cast<StructType>(Ty)) {
11251 for (unsigned i = 0; i < ST->getNumElements(); ++i) {
11252 uint64_t SubMembers = 0;
11253 if (!isHomogeneousAggregate(ST->getElementType(i), Base, SubMembers))
11255 Members += SubMembers;
11257 } else if (const ArrayType *AT = dyn_cast<ArrayType>(Ty)) {
11258 uint64_t SubMembers = 0;
11259 if (!isHomogeneousAggregate(AT->getElementType(), Base, SubMembers))
11261 Members += SubMembers * AT->getNumElements();
11262 } else if (Ty->isFloatTy()) {
11263 if (Base != HA_UNKNOWN && Base != HA_FLOAT)
11267 } else if (Ty->isDoubleTy()) {
11268 if (Base != HA_UNKNOWN && Base != HA_DOUBLE)
11272 } else if (const VectorType *VT = dyn_cast<VectorType>(Ty)) {
11279 return VT->getBitWidth() == 64;
11281 return VT->getBitWidth() == 128;
11283 switch (VT->getBitWidth()) {
11296 return (Members > 0 && Members <= 4);
11299 /// \brief Return true if a type is an AAPCS-VFP homogeneous aggregate or one of
11300 /// [N x i32] or [N x i64]. This allows front-ends to skip emitting padding when
11301 /// passing according to AAPCS rules.
11302 bool ARMTargetLowering::functionArgumentNeedsConsecutiveRegisters(
11303 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const {
11304 if (getEffectiveCallingConv(CallConv, isVarArg) !=
11305 CallingConv::ARM_AAPCS_VFP)
11308 HABaseType Base = HA_UNKNOWN;
11309 uint64_t Members = 0;
11310 bool IsHA = isHomogeneousAggregate(Ty, Base, Members);
11311 DEBUG(dbgs() << "isHA: " << IsHA << " "; Ty->dump());
11313 bool IsIntArray = Ty->isArrayTy() && Ty->getArrayElementType()->isIntegerTy();
11314 return IsHA || IsIntArray;