1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "arm-isel"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMISelLowering.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMPerfectShuffle.h"
22 #include "ARMRegisterInfo.h"
23 #include "ARMSubtarget.h"
24 #include "ARMTargetMachine.h"
25 #include "ARMTargetObjectFile.h"
26 #include "llvm/CallingConv.h"
27 #include "llvm/Constants.h"
28 #include "llvm/Function.h"
29 #include "llvm/GlobalValue.h"
30 #include "llvm/Instruction.h"
31 #include "llvm/Intrinsics.h"
32 #include "llvm/Type.h"
33 #include "llvm/CodeGen/CallingConvLower.h"
34 #include "llvm/CodeGen/MachineBasicBlock.h"
35 #include "llvm/CodeGen/MachineFrameInfo.h"
36 #include "llvm/CodeGen/MachineFunction.h"
37 #include "llvm/CodeGen/MachineInstrBuilder.h"
38 #include "llvm/CodeGen/MachineRegisterInfo.h"
39 #include "llvm/CodeGen/PseudoSourceValue.h"
40 #include "llvm/CodeGen/SelectionDAG.h"
41 #include "llvm/MC/MCSectionMachO.h"
42 #include "llvm/Target/TargetOptions.h"
43 #include "llvm/ADT/VectorExtras.h"
44 #include "llvm/ADT/Statistic.h"
45 #include "llvm/Support/CommandLine.h"
46 #include "llvm/Support/ErrorHandling.h"
47 #include "llvm/Support/MathExtras.h"
48 #include "llvm/Support/raw_ostream.h"
52 STATISTIC(NumTailCalls, "Number of tail calls");
54 // This option should go away when tail calls fully work.
56 EnableARMTailCalls("arm-tail-calls", cl::Hidden,
57 cl::desc("Generate tail calls (TEMPORARY OPTION)."),
61 EnableARMLongCalls("arm-long-calls", cl::Hidden,
62 cl::desc("Generate calls via indirect call instructions."),
66 ARMInterworking("arm-interworking", cl::Hidden,
67 cl::desc("Enable / disable ARM interworking (for debugging only)"),
70 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
71 CCValAssign::LocInfo &LocInfo,
72 ISD::ArgFlagsTy &ArgFlags,
74 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
75 CCValAssign::LocInfo &LocInfo,
76 ISD::ArgFlagsTy &ArgFlags,
78 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
79 CCValAssign::LocInfo &LocInfo,
80 ISD::ArgFlagsTy &ArgFlags,
82 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
83 CCValAssign::LocInfo &LocInfo,
84 ISD::ArgFlagsTy &ArgFlags,
87 void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
88 EVT PromotedBitwiseVT) {
89 if (VT != PromotedLdStVT) {
90 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
91 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
92 PromotedLdStVT.getSimpleVT());
94 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
95 AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
96 PromotedLdStVT.getSimpleVT());
99 EVT ElemTy = VT.getVectorElementType();
100 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
101 setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
102 if (ElemTy == MVT::i8 || ElemTy == MVT::i16)
103 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
104 if (ElemTy != MVT::i32) {
105 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
106 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand);
107 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand);
108 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand);
110 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
111 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
112 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
113 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Expand);
114 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
115 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
116 if (VT.isInteger()) {
117 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
118 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
119 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
122 // Promote all bit-wise operations.
123 if (VT.isInteger() && VT != PromotedBitwiseVT) {
124 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
125 AddPromotedToType (ISD::AND, VT.getSimpleVT(),
126 PromotedBitwiseVT.getSimpleVT());
127 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
128 AddPromotedToType (ISD::OR, VT.getSimpleVT(),
129 PromotedBitwiseVT.getSimpleVT());
130 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
131 AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
132 PromotedBitwiseVT.getSimpleVT());
135 // Neon does not support vector divide/remainder operations.
136 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
137 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
138 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand);
139 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
140 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
141 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
144 void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
145 addRegisterClass(VT, ARM::DPRRegisterClass);
146 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
149 void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
150 addRegisterClass(VT, ARM::QPRRegisterClass);
151 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
154 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
155 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
156 return new TargetLoweringObjectFileMachO();
158 return new ARMElfTargetObjectFile();
161 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
162 : TargetLowering(TM, createTLOF(TM)) {
163 Subtarget = &TM.getSubtarget<ARMSubtarget>();
165 if (Subtarget->isTargetDarwin()) {
166 // Uses VFP for Thumb libfuncs if available.
167 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
168 // Single-precision floating-point arithmetic.
169 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
170 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
171 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
172 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
174 // Double-precision floating-point arithmetic.
175 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
176 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
177 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
178 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
180 // Single-precision comparisons.
181 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
182 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
183 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
184 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
185 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
186 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
187 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
188 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
190 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
191 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
192 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
193 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
194 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
195 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
196 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
197 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
199 // Double-precision comparisons.
200 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
201 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
202 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
203 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
204 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
205 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
206 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
207 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
209 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
210 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
211 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
212 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
213 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
214 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
215 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
216 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
218 // Floating-point to integer conversions.
219 // i64 conversions are done via library routines even when generating VFP
220 // instructions, so use the same ones.
221 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
222 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
223 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
224 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
226 // Conversions between floating types.
227 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
228 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
230 // Integer to floating-point conversions.
231 // i64 conversions are done via library routines even when generating VFP
232 // instructions, so use the same ones.
233 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
234 // e.g., __floatunsidf vs. __floatunssidfvfp.
235 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
236 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
237 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
238 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
242 // These libcalls are not available in 32-bit.
243 setLibcallName(RTLIB::SHL_I128, 0);
244 setLibcallName(RTLIB::SRL_I128, 0);
245 setLibcallName(RTLIB::SRA_I128, 0);
247 // Libcalls should use the AAPCS base standard ABI, even if hard float
248 // is in effect, as per the ARM RTABI specification, section 4.1.2.
249 if (Subtarget->isAAPCS_ABI()) {
250 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
251 setLibcallCallingConv(static_cast<RTLIB::Libcall>(i),
252 CallingConv::ARM_AAPCS);
256 if (Subtarget->isThumb1Only())
257 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
259 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
260 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
261 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
262 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
264 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
267 if (Subtarget->hasNEON()) {
268 addDRTypeForNEON(MVT::v2f32);
269 addDRTypeForNEON(MVT::v8i8);
270 addDRTypeForNEON(MVT::v4i16);
271 addDRTypeForNEON(MVT::v2i32);
272 addDRTypeForNEON(MVT::v1i64);
274 addQRTypeForNEON(MVT::v4f32);
275 addQRTypeForNEON(MVT::v2f64);
276 addQRTypeForNEON(MVT::v16i8);
277 addQRTypeForNEON(MVT::v8i16);
278 addQRTypeForNEON(MVT::v4i32);
279 addQRTypeForNEON(MVT::v2i64);
281 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
282 // neither Neon nor VFP support any arithmetic operations on it.
283 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
284 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
285 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
286 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
287 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
288 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
289 setOperationAction(ISD::VSETCC, MVT::v2f64, Expand);
290 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
291 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
292 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
293 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
294 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
295 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
296 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
297 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
298 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
299 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
300 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
301 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
302 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
303 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
304 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
305 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
306 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
308 // Neon does not support some operations on v1i64 and v2i64 types.
309 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
310 setOperationAction(ISD::MUL, MVT::v2i64, Expand);
311 setOperationAction(ISD::VSETCC, MVT::v1i64, Expand);
312 setOperationAction(ISD::VSETCC, MVT::v2i64, Expand);
314 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
315 setTargetDAGCombine(ISD::SHL);
316 setTargetDAGCombine(ISD::SRL);
317 setTargetDAGCombine(ISD::SRA);
318 setTargetDAGCombine(ISD::SIGN_EXTEND);
319 setTargetDAGCombine(ISD::ZERO_EXTEND);
320 setTargetDAGCombine(ISD::ANY_EXTEND);
321 setTargetDAGCombine(ISD::SELECT_CC);
324 computeRegisterProperties();
326 // ARM does not have f32 extending load.
327 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
329 // ARM does not have i1 sign extending load.
330 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
332 // ARM supports all 4 flavors of integer indexed load / store.
333 if (!Subtarget->isThumb1Only()) {
334 for (unsigned im = (unsigned)ISD::PRE_INC;
335 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
336 setIndexedLoadAction(im, MVT::i1, Legal);
337 setIndexedLoadAction(im, MVT::i8, Legal);
338 setIndexedLoadAction(im, MVT::i16, Legal);
339 setIndexedLoadAction(im, MVT::i32, Legal);
340 setIndexedStoreAction(im, MVT::i1, Legal);
341 setIndexedStoreAction(im, MVT::i8, Legal);
342 setIndexedStoreAction(im, MVT::i16, Legal);
343 setIndexedStoreAction(im, MVT::i32, Legal);
347 // i64 operation support.
348 if (Subtarget->isThumb1Only()) {
349 setOperationAction(ISD::MUL, MVT::i64, Expand);
350 setOperationAction(ISD::MULHU, MVT::i32, Expand);
351 setOperationAction(ISD::MULHS, MVT::i32, Expand);
352 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
353 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
355 setOperationAction(ISD::MUL, MVT::i64, Expand);
356 setOperationAction(ISD::MULHU, MVT::i32, Expand);
357 if (!Subtarget->hasV6Ops())
358 setOperationAction(ISD::MULHS, MVT::i32, Expand);
360 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
361 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
362 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
363 setOperationAction(ISD::SRL, MVT::i64, Custom);
364 setOperationAction(ISD::SRA, MVT::i64, Custom);
366 // ARM does not have ROTL.
367 setOperationAction(ISD::ROTL, MVT::i32, Expand);
368 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
369 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
370 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
371 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
373 // Only ARMv6 has BSWAP.
374 if (!Subtarget->hasV6Ops())
375 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
377 // These are expanded into libcalls.
378 if (!Subtarget->hasDivide()) {
379 // v7M has a hardware divider
380 setOperationAction(ISD::SDIV, MVT::i32, Expand);
381 setOperationAction(ISD::UDIV, MVT::i32, Expand);
383 setOperationAction(ISD::SREM, MVT::i32, Expand);
384 setOperationAction(ISD::UREM, MVT::i32, Expand);
385 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
386 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
388 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
389 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
390 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
391 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
392 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
394 setOperationAction(ISD::TRAP, MVT::Other, Legal);
396 // Use the default implementation.
397 setOperationAction(ISD::VASTART, MVT::Other, Custom);
398 setOperationAction(ISD::VAARG, MVT::Other, Expand);
399 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
400 setOperationAction(ISD::VAEND, MVT::Other, Expand);
401 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
402 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
403 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
404 // FIXME: Shouldn't need this, since no register is used, but the legalizer
405 // doesn't yet know how to not do that for SjLj.
406 setExceptionSelectorRegister(ARM::R0);
407 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
408 // Handle atomics directly for ARMv[67] (except for Thumb1), otherwise
409 // use the default expansion.
410 bool canHandleAtomics =
411 (Subtarget->hasV7Ops() ||
412 (Subtarget->hasV6Ops() && !Subtarget->isThumb1Only()));
413 if (canHandleAtomics) {
414 // membarrier needs custom lowering; the rest are legal and handled
416 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
418 // Set them all for expansion, which will force libcalls.
419 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
420 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Expand);
421 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Expand);
422 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
423 setOperationAction(ISD::ATOMIC_SWAP, MVT::i8, Expand);
424 setOperationAction(ISD::ATOMIC_SWAP, MVT::i16, Expand);
425 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
426 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i8, Expand);
427 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i16, Expand);
428 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
429 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Expand);
430 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Expand);
431 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
432 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i8, Expand);
433 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i16, Expand);
434 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
435 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i8, Expand);
436 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i16, Expand);
437 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
438 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i8, Expand);
439 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i16, Expand);
440 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
441 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i8, Expand);
442 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i16, Expand);
443 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
444 // Since the libcalls include locking, fold in the fences
445 setShouldFoldAtomicFences(true);
447 // 64-bit versions are always libcalls (for now)
448 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Expand);
449 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Expand);
450 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Expand);
451 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Expand);
452 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Expand);
453 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Expand);
454 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Expand);
455 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Expand);
457 // If the subtarget does not have extract instructions, sign_extend_inreg
458 // needs to be expanded. Extract is available in ARM mode on v6 and up,
459 // and on most Thumb2 implementations.
460 if (!Subtarget->hasV6Ops()
461 || (Subtarget->isThumb2() && !Subtarget->hasT2ExtractPack())) {
462 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
463 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
465 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
467 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only())
468 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
469 // iff target supports vfp2.
470 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
472 // We want to custom lower some of our intrinsics.
473 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
475 setOperationAction(ISD::SETCC, MVT::i32, Expand);
476 setOperationAction(ISD::SETCC, MVT::f32, Expand);
477 setOperationAction(ISD::SETCC, MVT::f64, Expand);
478 setOperationAction(ISD::SELECT, MVT::i32, Expand);
479 setOperationAction(ISD::SELECT, MVT::f32, Expand);
480 setOperationAction(ISD::SELECT, MVT::f64, Expand);
481 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
482 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
483 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
485 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
486 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
487 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
488 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
489 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
491 // We don't support sin/cos/fmod/copysign/pow
492 setOperationAction(ISD::FSIN, MVT::f64, Expand);
493 setOperationAction(ISD::FSIN, MVT::f32, Expand);
494 setOperationAction(ISD::FCOS, MVT::f32, Expand);
495 setOperationAction(ISD::FCOS, MVT::f64, Expand);
496 setOperationAction(ISD::FREM, MVT::f64, Expand);
497 setOperationAction(ISD::FREM, MVT::f32, Expand);
498 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
499 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
500 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
502 setOperationAction(ISD::FPOW, MVT::f64, Expand);
503 setOperationAction(ISD::FPOW, MVT::f32, Expand);
505 // Various VFP goodness
506 if (!UseSoftFloat && !Subtarget->isThumb1Only()) {
507 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
508 if (Subtarget->hasVFP2()) {
509 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
510 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
511 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
512 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
514 // Special handling for half-precision FP.
515 if (!Subtarget->hasFP16()) {
516 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
517 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand);
521 // We have target-specific dag combine patterns for the following nodes:
522 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
523 setTargetDAGCombine(ISD::ADD);
524 setTargetDAGCombine(ISD::SUB);
525 setTargetDAGCombine(ISD::MUL);
527 setStackPointerRegisterToSaveRestore(ARM::SP);
529 if (UseSoftFloat || Subtarget->isThumb1Only() || !Subtarget->hasVFP2())
530 setSchedulingPreference(Sched::RegPressure);
532 setSchedulingPreference(Sched::Hybrid);
534 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
535 // Do not enable CodePlacementOpt for now: it currently runs after the
536 // ARMConstantIslandPass and messes up branch relaxation and placement
537 // of constant islands.
538 // benefitFromCodePlacementOpt = true;
541 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
544 case ARMISD::Wrapper: return "ARMISD::Wrapper";
545 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
546 case ARMISD::CALL: return "ARMISD::CALL";
547 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
548 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
549 case ARMISD::tCALL: return "ARMISD::tCALL";
550 case ARMISD::BRCOND: return "ARMISD::BRCOND";
551 case ARMISD::BR_JT: return "ARMISD::BR_JT";
552 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
553 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
554 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
555 case ARMISD::CMP: return "ARMISD::CMP";
556 case ARMISD::CMPZ: return "ARMISD::CMPZ";
557 case ARMISD::CMPFP: return "ARMISD::CMPFP";
558 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
559 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
560 case ARMISD::CMOV: return "ARMISD::CMOV";
561 case ARMISD::CNEG: return "ARMISD::CNEG";
563 case ARMISD::RBIT: return "ARMISD::RBIT";
565 case ARMISD::FTOSI: return "ARMISD::FTOSI";
566 case ARMISD::FTOUI: return "ARMISD::FTOUI";
567 case ARMISD::SITOF: return "ARMISD::SITOF";
568 case ARMISD::UITOF: return "ARMISD::UITOF";
570 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
571 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
572 case ARMISD::RRX: return "ARMISD::RRX";
574 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
575 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
577 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
578 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
580 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
582 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
584 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
586 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER";
587 case ARMISD::SYNCBARRIER: return "ARMISD::SYNCBARRIER";
589 case ARMISD::VCEQ: return "ARMISD::VCEQ";
590 case ARMISD::VCGE: return "ARMISD::VCGE";
591 case ARMISD::VCGEU: return "ARMISD::VCGEU";
592 case ARMISD::VCGT: return "ARMISD::VCGT";
593 case ARMISD::VCGTU: return "ARMISD::VCGTU";
594 case ARMISD::VTST: return "ARMISD::VTST";
596 case ARMISD::VSHL: return "ARMISD::VSHL";
597 case ARMISD::VSHRs: return "ARMISD::VSHRs";
598 case ARMISD::VSHRu: return "ARMISD::VSHRu";
599 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
600 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
601 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
602 case ARMISD::VSHRN: return "ARMISD::VSHRN";
603 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
604 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
605 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
606 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
607 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
608 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
609 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
610 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
611 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
612 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
613 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
614 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
615 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
616 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
617 case ARMISD::VDUP: return "ARMISD::VDUP";
618 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
619 case ARMISD::VEXT: return "ARMISD::VEXT";
620 case ARMISD::VREV64: return "ARMISD::VREV64";
621 case ARMISD::VREV32: return "ARMISD::VREV32";
622 case ARMISD::VREV16: return "ARMISD::VREV16";
623 case ARMISD::VZIP: return "ARMISD::VZIP";
624 case ARMISD::VUZP: return "ARMISD::VUZP";
625 case ARMISD::VTRN: return "ARMISD::VTRN";
626 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
627 case ARMISD::FMAX: return "ARMISD::FMAX";
628 case ARMISD::FMIN: return "ARMISD::FMIN";
632 /// getRegClassFor - Return the register class that should be used for the
633 /// specified value type.
634 TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const {
635 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
636 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
637 // load / store 4 to 8 consecutive D registers.
638 if (Subtarget->hasNEON()) {
639 if (VT == MVT::v4i64)
640 return ARM::QQPRRegisterClass;
641 else if (VT == MVT::v8i64)
642 return ARM::QQQQPRRegisterClass;
644 return TargetLowering::getRegClassFor(VT);
647 /// getFunctionAlignment - Return the Log2 alignment of this function.
648 unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
649 return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 0 : 1;
652 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
653 unsigned NumVals = N->getNumValues();
655 return Sched::RegPressure;
657 for (unsigned i = 0; i != NumVals; ++i) {
658 EVT VT = N->getValueType(i);
659 if (VT.isFloatingPoint() || VT.isVector())
660 return Sched::Latency;
663 if (!N->isMachineOpcode())
664 return Sched::RegPressure;
666 // Load are scheduled for latency even if there instruction itinerary
668 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
669 const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
671 return Sched::Latency;
673 const InstrItineraryData &Itins = getTargetMachine().getInstrItineraryData();
674 if (!Itins.isEmpty() && Itins.getStageLatency(TID.getSchedClass()) > 2)
675 return Sched::Latency;
676 return Sched::RegPressure;
679 //===----------------------------------------------------------------------===//
681 //===----------------------------------------------------------------------===//
683 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
684 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
686 default: llvm_unreachable("Unknown condition code!");
687 case ISD::SETNE: return ARMCC::NE;
688 case ISD::SETEQ: return ARMCC::EQ;
689 case ISD::SETGT: return ARMCC::GT;
690 case ISD::SETGE: return ARMCC::GE;
691 case ISD::SETLT: return ARMCC::LT;
692 case ISD::SETLE: return ARMCC::LE;
693 case ISD::SETUGT: return ARMCC::HI;
694 case ISD::SETUGE: return ARMCC::HS;
695 case ISD::SETULT: return ARMCC::LO;
696 case ISD::SETULE: return ARMCC::LS;
700 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
701 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
702 ARMCC::CondCodes &CondCode2) {
703 CondCode2 = ARMCC::AL;
705 default: llvm_unreachable("Unknown FP condition!");
707 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
709 case ISD::SETOGT: CondCode = ARMCC::GT; break;
711 case ISD::SETOGE: CondCode = ARMCC::GE; break;
712 case ISD::SETOLT: CondCode = ARMCC::MI; break;
713 case ISD::SETOLE: CondCode = ARMCC::LS; break;
714 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
715 case ISD::SETO: CondCode = ARMCC::VC; break;
716 case ISD::SETUO: CondCode = ARMCC::VS; break;
717 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
718 case ISD::SETUGT: CondCode = ARMCC::HI; break;
719 case ISD::SETUGE: CondCode = ARMCC::PL; break;
721 case ISD::SETULT: CondCode = ARMCC::LT; break;
723 case ISD::SETULE: CondCode = ARMCC::LE; break;
725 case ISD::SETUNE: CondCode = ARMCC::NE; break;
729 //===----------------------------------------------------------------------===//
730 // Calling Convention Implementation
731 //===----------------------------------------------------------------------===//
733 #include "ARMGenCallingConv.inc"
735 // APCS f64 is in register pairs, possibly split to stack
736 static bool f64AssignAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
737 CCValAssign::LocInfo &LocInfo,
738 CCState &State, bool CanFail) {
739 static const unsigned RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
741 // Try to get the first register.
742 if (unsigned Reg = State.AllocateReg(RegList, 4))
743 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
745 // For the 2nd half of a v2f64, do not fail.
749 // Put the whole thing on the stack.
750 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
751 State.AllocateStack(8, 4),
756 // Try to get the second register.
757 if (unsigned Reg = State.AllocateReg(RegList, 4))
758 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
760 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
761 State.AllocateStack(4, 4),
766 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
767 CCValAssign::LocInfo &LocInfo,
768 ISD::ArgFlagsTy &ArgFlags,
770 if (!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
772 if (LocVT == MVT::v2f64 &&
773 !f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
775 return true; // we handled it
778 // AAPCS f64 is in aligned register pairs
779 static bool f64AssignAAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
780 CCValAssign::LocInfo &LocInfo,
781 CCState &State, bool CanFail) {
782 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
783 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
785 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
787 // For the 2nd half of a v2f64, do not just fail.
791 // Put the whole thing on the stack.
792 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
793 State.AllocateStack(8, 8),
799 for (i = 0; i < 2; ++i)
800 if (HiRegList[i] == Reg)
803 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
804 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
809 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
810 CCValAssign::LocInfo &LocInfo,
811 ISD::ArgFlagsTy &ArgFlags,
813 if (!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
815 if (LocVT == MVT::v2f64 &&
816 !f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
818 return true; // we handled it
821 static bool f64RetAssign(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
822 CCValAssign::LocInfo &LocInfo, CCState &State) {
823 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
824 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
826 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
828 return false; // we didn't handle it
831 for (i = 0; i < 2; ++i)
832 if (HiRegList[i] == Reg)
835 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
836 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
841 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
842 CCValAssign::LocInfo &LocInfo,
843 ISD::ArgFlagsTy &ArgFlags,
845 if (!f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
847 if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
849 return true; // we handled it
852 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
853 CCValAssign::LocInfo &LocInfo,
854 ISD::ArgFlagsTy &ArgFlags,
856 return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags,
860 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
861 /// given CallingConvention value.
862 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
864 bool isVarArg) const {
867 llvm_unreachable("Unsupported calling convention");
869 case CallingConv::Fast:
870 // Use target triple & subtarget features to do actual dispatch.
871 if (Subtarget->isAAPCS_ABI()) {
872 if (Subtarget->hasVFP2() &&
873 FloatABIType == FloatABI::Hard && !isVarArg)
874 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
876 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
878 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
879 case CallingConv::ARM_AAPCS_VFP:
880 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
881 case CallingConv::ARM_AAPCS:
882 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
883 case CallingConv::ARM_APCS:
884 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
888 /// LowerCallResult - Lower the result values of a call into the
889 /// appropriate copies out of appropriate physical registers.
891 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
892 CallingConv::ID CallConv, bool isVarArg,
893 const SmallVectorImpl<ISD::InputArg> &Ins,
894 DebugLoc dl, SelectionDAG &DAG,
895 SmallVectorImpl<SDValue> &InVals) const {
897 // Assign locations to each value returned by this call.
898 SmallVector<CCValAssign, 16> RVLocs;
899 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
900 RVLocs, *DAG.getContext());
901 CCInfo.AnalyzeCallResult(Ins,
902 CCAssignFnForNode(CallConv, /* Return*/ true,
905 // Copy all of the result registers out of their specified physreg.
906 for (unsigned i = 0; i != RVLocs.size(); ++i) {
907 CCValAssign VA = RVLocs[i];
910 if (VA.needsCustom()) {
911 // Handle f64 or half of a v2f64.
912 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
914 Chain = Lo.getValue(1);
915 InFlag = Lo.getValue(2);
916 VA = RVLocs[++i]; // skip ahead to next loc
917 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
919 Chain = Hi.getValue(1);
920 InFlag = Hi.getValue(2);
921 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
923 if (VA.getLocVT() == MVT::v2f64) {
924 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
925 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
926 DAG.getConstant(0, MVT::i32));
928 VA = RVLocs[++i]; // skip ahead to next loc
929 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
930 Chain = Lo.getValue(1);
931 InFlag = Lo.getValue(2);
932 VA = RVLocs[++i]; // skip ahead to next loc
933 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
934 Chain = Hi.getValue(1);
935 InFlag = Hi.getValue(2);
936 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
937 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
938 DAG.getConstant(1, MVT::i32));
941 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
943 Chain = Val.getValue(1);
944 InFlag = Val.getValue(2);
947 switch (VA.getLocInfo()) {
948 default: llvm_unreachable("Unknown loc info!");
949 case CCValAssign::Full: break;
950 case CCValAssign::BCvt:
951 Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val);
955 InVals.push_back(Val);
961 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
962 /// by "Src" to address "Dst" of size "Size". Alignment information is
963 /// specified by the specific parameter attribute. The copy will be passed as
964 /// a byval function parameter.
965 /// Sometimes what we are copying is the end of a larger object, the part that
966 /// does not fit in registers.
968 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
969 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
971 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
972 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
973 /*isVolatile=*/false, /*AlwaysInline=*/false,
977 /// LowerMemOpCallTo - Store the argument to the stack.
979 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
980 SDValue StackPtr, SDValue Arg,
981 DebugLoc dl, SelectionDAG &DAG,
982 const CCValAssign &VA,
983 ISD::ArgFlagsTy Flags) const {
984 unsigned LocMemOffset = VA.getLocMemOffset();
985 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
986 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
987 if (Flags.isByVal()) {
988 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
990 return DAG.getStore(Chain, dl, Arg, PtrOff,
991 PseudoSourceValue::getStack(), LocMemOffset,
995 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
996 SDValue Chain, SDValue &Arg,
997 RegsToPassVector &RegsToPass,
998 CCValAssign &VA, CCValAssign &NextVA,
1000 SmallVector<SDValue, 8> &MemOpChains,
1001 ISD::ArgFlagsTy Flags) const {
1003 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1004 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1005 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
1007 if (NextVA.isRegLoc())
1008 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
1010 assert(NextVA.isMemLoc());
1011 if (StackPtr.getNode() == 0)
1012 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1014 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
1020 /// LowerCall - Lowering a call into a callseq_start <-
1021 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1024 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1025 CallingConv::ID CallConv, bool isVarArg,
1027 const SmallVectorImpl<ISD::OutputArg> &Outs,
1028 const SmallVectorImpl<ISD::InputArg> &Ins,
1029 DebugLoc dl, SelectionDAG &DAG,
1030 SmallVectorImpl<SDValue> &InVals) const {
1031 MachineFunction &MF = DAG.getMachineFunction();
1032 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1033 bool IsSibCall = false;
1034 // Temporarily disable tail calls so things don't break.
1035 if (!EnableARMTailCalls)
1038 // Check if it's really possible to do a tail call.
1039 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1040 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1042 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1043 // detected sibcalls.
1050 // Analyze operands of the call, assigning locations to each operand.
1051 SmallVector<CCValAssign, 16> ArgLocs;
1052 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1054 CCInfo.AnalyzeCallOperands(Outs,
1055 CCAssignFnForNode(CallConv, /* Return*/ false,
1058 // Get a count of how many bytes are to be pushed on the stack.
1059 unsigned NumBytes = CCInfo.getNextStackOffset();
1061 // For tail calls, memory operands are available in our caller's stack.
1065 // Adjust the stack pointer for the new arguments...
1066 // These operations are automatically eliminated by the prolog/epilog pass
1068 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1070 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1072 RegsToPassVector RegsToPass;
1073 SmallVector<SDValue, 8> MemOpChains;
1075 // Walk the register/memloc assignments, inserting copies/loads. In the case
1076 // of tail call optimization, arguments are handled later.
1077 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1079 ++i, ++realArgIdx) {
1080 CCValAssign &VA = ArgLocs[i];
1081 SDValue Arg = Outs[realArgIdx].Val;
1082 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1084 // Promote the value if needed.
1085 switch (VA.getLocInfo()) {
1086 default: llvm_unreachable("Unknown loc info!");
1087 case CCValAssign::Full: break;
1088 case CCValAssign::SExt:
1089 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1091 case CCValAssign::ZExt:
1092 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1094 case CCValAssign::AExt:
1095 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1097 case CCValAssign::BCvt:
1098 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1102 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1103 if (VA.needsCustom()) {
1104 if (VA.getLocVT() == MVT::v2f64) {
1105 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1106 DAG.getConstant(0, MVT::i32));
1107 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1108 DAG.getConstant(1, MVT::i32));
1110 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1111 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1113 VA = ArgLocs[++i]; // skip ahead to next loc
1114 if (VA.isRegLoc()) {
1115 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1116 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1118 assert(VA.isMemLoc());
1120 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1121 dl, DAG, VA, Flags));
1124 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1125 StackPtr, MemOpChains, Flags);
1127 } else if (VA.isRegLoc()) {
1128 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1129 } else if (!IsSibCall) {
1130 assert(VA.isMemLoc());
1132 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1133 dl, DAG, VA, Flags));
1137 if (!MemOpChains.empty())
1138 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1139 &MemOpChains[0], MemOpChains.size());
1141 // Build a sequence of copy-to-reg nodes chained together with token chain
1142 // and flag operands which copy the outgoing args into the appropriate regs.
1144 // Tail call byval lowering might overwrite argument registers so in case of
1145 // tail call optimization the copies to registers are lowered later.
1147 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1148 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1149 RegsToPass[i].second, InFlag);
1150 InFlag = Chain.getValue(1);
1153 // For tail calls lower the arguments to the 'real' stack slot.
1155 // Force all the incoming stack arguments to be loaded from the stack
1156 // before any new outgoing arguments are stored to the stack, because the
1157 // outgoing stack slots may alias the incoming argument stack slots, and
1158 // the alias isn't otherwise explicit. This is slightly more conservative
1159 // than necessary, because it means that each store effectively depends
1160 // on every argument instead of just those arguments it would clobber.
1162 // Do not flag preceeding copytoreg stuff together with the following stuff.
1164 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1165 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1166 RegsToPass[i].second, InFlag);
1167 InFlag = Chain.getValue(1);
1172 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1173 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1174 // node so that legalize doesn't hack it.
1175 bool isDirect = false;
1176 bool isARMFunc = false;
1177 bool isLocalARMFunc = false;
1178 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1180 if (EnableARMLongCalls) {
1181 assert (getTargetMachine().getRelocationModel() == Reloc::Static
1182 && "long-calls with non-static relocation model!");
1183 // Handle a global address or an external symbol. If it's not one of
1184 // those, the target's already in a register, so we don't need to do
1186 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1187 const GlobalValue *GV = G->getGlobal();
1188 // Create a constant pool entry for the callee address
1189 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1190 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1193 // Get the address of the callee into a register
1194 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1195 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1196 Callee = DAG.getLoad(getPointerTy(), dl,
1197 DAG.getEntryNode(), CPAddr,
1198 PseudoSourceValue::getConstantPool(), 0,
1200 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1201 const char *Sym = S->getSymbol();
1203 // Create a constant pool entry for the callee address
1204 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1205 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1206 Sym, ARMPCLabelIndex, 0);
1207 // Get the address of the callee into a register
1208 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1209 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1210 Callee = DAG.getLoad(getPointerTy(), dl,
1211 DAG.getEntryNode(), CPAddr,
1212 PseudoSourceValue::getConstantPool(), 0,
1215 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1216 const GlobalValue *GV = G->getGlobal();
1218 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1219 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
1220 getTargetMachine().getRelocationModel() != Reloc::Static;
1221 isARMFunc = !Subtarget->isThumb() || isStub;
1222 // ARM call to a local ARM function is predicable.
1223 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
1224 // tBX takes a register source operand.
1225 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1226 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1227 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1230 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1231 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1232 Callee = DAG.getLoad(getPointerTy(), dl,
1233 DAG.getEntryNode(), CPAddr,
1234 PseudoSourceValue::getConstantPool(), 0,
1236 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1237 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1238 getPointerTy(), Callee, PICLabel);
1240 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy());
1241 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1243 bool isStub = Subtarget->isTargetDarwin() &&
1244 getTargetMachine().getRelocationModel() != Reloc::Static;
1245 isARMFunc = !Subtarget->isThumb() || isStub;
1246 // tBX takes a register source operand.
1247 const char *Sym = S->getSymbol();
1248 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1249 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1250 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1251 Sym, ARMPCLabelIndex, 4);
1252 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1253 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1254 Callee = DAG.getLoad(getPointerTy(), dl,
1255 DAG.getEntryNode(), CPAddr,
1256 PseudoSourceValue::getConstantPool(), 0,
1258 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1259 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1260 getPointerTy(), Callee, PICLabel);
1262 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
1265 // FIXME: handle tail calls differently.
1267 if (Subtarget->isThumb()) {
1268 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1269 CallOpc = ARMISD::CALL_NOLINK;
1271 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1273 CallOpc = (isDirect || Subtarget->hasV5TOps())
1274 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
1275 : ARMISD::CALL_NOLINK;
1277 if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb1Only()) {
1278 // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK
1279 Chain = DAG.getCopyToReg(Chain, dl, ARM::LR, DAG.getUNDEF(MVT::i32),InFlag);
1280 InFlag = Chain.getValue(1);
1283 std::vector<SDValue> Ops;
1284 Ops.push_back(Chain);
1285 Ops.push_back(Callee);
1287 // Add argument registers to the end of the list so that they are known live
1289 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1290 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1291 RegsToPass[i].second.getValueType()));
1293 if (InFlag.getNode())
1294 Ops.push_back(InFlag);
1296 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1298 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
1300 // Returns a chain and a flag for retval copy to use.
1301 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
1302 InFlag = Chain.getValue(1);
1304 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1305 DAG.getIntPtrConstant(0, true), InFlag);
1307 InFlag = Chain.getValue(1);
1309 // Handle result values, copying them out of physregs into vregs that we
1311 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1315 /// MatchingStackOffset - Return true if the given stack call argument is
1316 /// already available in the same position (relatively) of the caller's
1317 /// incoming argument stack.
1319 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1320 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1321 const ARMInstrInfo *TII) {
1322 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
1324 if (Arg.getOpcode() == ISD::CopyFromReg) {
1325 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
1326 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR))
1328 MachineInstr *Def = MRI->getVRegDef(VR);
1331 if (!Flags.isByVal()) {
1332 if (!TII->isLoadFromStackSlot(Def, FI))
1335 // unsigned Opcode = Def->getOpcode();
1336 // if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) &&
1337 // Def->getOperand(1).isFI()) {
1338 // FI = Def->getOperand(1).getIndex();
1339 // Bytes = Flags.getByValSize();
1343 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
1344 if (Flags.isByVal())
1345 // ByVal argument is passed in as a pointer but it's now being
1346 // dereferenced. e.g.
1347 // define @foo(%struct.X* %A) {
1348 // tail call @bar(%struct.X* byval %A)
1351 SDValue Ptr = Ld->getBasePtr();
1352 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
1355 FI = FINode->getIndex();
1359 assert(FI != INT_MAX);
1360 if (!MFI->isFixedObjectIndex(FI))
1362 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
1365 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1366 /// for tail call optimization. Targets which want to do tail call
1367 /// optimization should implement this function.
1369 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1370 CallingConv::ID CalleeCC,
1372 bool isCalleeStructRet,
1373 bool isCallerStructRet,
1374 const SmallVectorImpl<ISD::OutputArg> &Outs,
1375 const SmallVectorImpl<ISD::InputArg> &Ins,
1376 SelectionDAG& DAG) const {
1377 const Function *CallerF = DAG.getMachineFunction().getFunction();
1378 CallingConv::ID CallerCC = CallerF->getCallingConv();
1379 bool CCMatch = CallerCC == CalleeCC;
1381 // Look for obvious safe cases to perform tail call optimization that do not
1382 // require ABI changes. This is what gcc calls sibcall.
1384 // Do not sibcall optimize vararg calls unless the call site is not passing
1386 if (isVarArg && !Outs.empty())
1389 // Also avoid sibcall optimization if either caller or callee uses struct
1390 // return semantics.
1391 if (isCalleeStructRet || isCallerStructRet)
1394 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
1395 // emitEpilogue is not ready for them.
1396 if (Subtarget->isThumb1Only())
1399 // For the moment, we can only do this to functions defined in this
1400 // compilation, or to indirect calls. A Thumb B to an ARM function,
1401 // or vice versa, is not easily fixed up in the linker unlike BL.
1402 // (We could do this by loading the address of the callee into a register;
1403 // that is an extra instruction over the direct call and burns a register
1404 // as well, so is not likely to be a win.)
1405 if (isa<ExternalSymbolSDNode>(Callee))
1408 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1409 const GlobalValue *GV = G->getGlobal();
1410 if (GV->isDeclaration() || GV->isWeakForLinker())
1414 // If the calling conventions do not match, then we'd better make sure the
1415 // results are returned in the same way as what the caller expects.
1417 SmallVector<CCValAssign, 16> RVLocs1;
1418 CCState CCInfo1(CalleeCC, false, getTargetMachine(),
1419 RVLocs1, *DAG.getContext());
1420 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
1422 SmallVector<CCValAssign, 16> RVLocs2;
1423 CCState CCInfo2(CallerCC, false, getTargetMachine(),
1424 RVLocs2, *DAG.getContext());
1425 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
1427 if (RVLocs1.size() != RVLocs2.size())
1429 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
1430 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
1432 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
1434 if (RVLocs1[i].isRegLoc()) {
1435 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
1438 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
1444 // If the callee takes no arguments then go on to check the results of the
1446 if (!Outs.empty()) {
1447 // Check if stack adjustment is needed. For now, do not do this if any
1448 // argument is passed on the stack.
1449 SmallVector<CCValAssign, 16> ArgLocs;
1450 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
1451 ArgLocs, *DAG.getContext());
1452 CCInfo.AnalyzeCallOperands(Outs,
1453 CCAssignFnForNode(CalleeCC, false, isVarArg));
1454 if (CCInfo.getNextStackOffset()) {
1455 MachineFunction &MF = DAG.getMachineFunction();
1457 // Check if the arguments are already laid out in the right way as
1458 // the caller's fixed stack objects.
1459 MachineFrameInfo *MFI = MF.getFrameInfo();
1460 const MachineRegisterInfo *MRI = &MF.getRegInfo();
1461 const ARMInstrInfo *TII =
1462 ((ARMTargetMachine&)getTargetMachine()).getInstrInfo();
1463 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1465 ++i, ++realArgIdx) {
1466 CCValAssign &VA = ArgLocs[i];
1467 EVT RegVT = VA.getLocVT();
1468 SDValue Arg = Outs[realArgIdx].Val;
1469 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1470 if (VA.getLocInfo() == CCValAssign::Indirect)
1472 if (VA.needsCustom()) {
1473 // f64 and vector types are split into multiple registers or
1474 // register/stack-slot combinations. The types will not match
1475 // the registers; give up on memory f64 refs until we figure
1476 // out what to do about this.
1479 if (!ArgLocs[++i].isRegLoc())
1481 if (RegVT == MVT::v2f64) {
1482 if (!ArgLocs[++i].isRegLoc())
1484 if (!ArgLocs[++i].isRegLoc())
1487 } else if (!VA.isRegLoc()) {
1488 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
1500 ARMTargetLowering::LowerReturn(SDValue Chain,
1501 CallingConv::ID CallConv, bool isVarArg,
1502 const SmallVectorImpl<ISD::OutputArg> &Outs,
1503 DebugLoc dl, SelectionDAG &DAG) const {
1505 // CCValAssign - represent the assignment of the return value to a location.
1506 SmallVector<CCValAssign, 16> RVLocs;
1508 // CCState - Info about the registers and stack slots.
1509 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
1512 // Analyze outgoing return values.
1513 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1516 // If this is the first return lowered for this function, add
1517 // the regs to the liveout set for the function.
1518 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1519 for (unsigned i = 0; i != RVLocs.size(); ++i)
1520 if (RVLocs[i].isRegLoc())
1521 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1526 // Copy the result values into the output registers.
1527 for (unsigned i = 0, realRVLocIdx = 0;
1529 ++i, ++realRVLocIdx) {
1530 CCValAssign &VA = RVLocs[i];
1531 assert(VA.isRegLoc() && "Can only return in registers!");
1533 SDValue Arg = Outs[realRVLocIdx].Val;
1535 switch (VA.getLocInfo()) {
1536 default: llvm_unreachable("Unknown loc info!");
1537 case CCValAssign::Full: break;
1538 case CCValAssign::BCvt:
1539 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1543 if (VA.needsCustom()) {
1544 if (VA.getLocVT() == MVT::v2f64) {
1545 // Extract the first half and return it in two registers.
1546 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1547 DAG.getConstant(0, MVT::i32));
1548 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
1549 DAG.getVTList(MVT::i32, MVT::i32), Half);
1551 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1552 Flag = Chain.getValue(1);
1553 VA = RVLocs[++i]; // skip ahead to next loc
1554 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1555 HalfGPRs.getValue(1), Flag);
1556 Flag = Chain.getValue(1);
1557 VA = RVLocs[++i]; // skip ahead to next loc
1559 // Extract the 2nd half and fall through to handle it as an f64 value.
1560 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1561 DAG.getConstant(1, MVT::i32));
1563 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1565 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1566 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1567 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1568 Flag = Chain.getValue(1);
1569 VA = RVLocs[++i]; // skip ahead to next loc
1570 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1573 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1575 // Guarantee that all emitted copies are
1576 // stuck together, avoiding something bad.
1577 Flag = Chain.getValue(1);
1582 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1584 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1589 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1590 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1591 // one of the above mentioned nodes. It has to be wrapped because otherwise
1592 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1593 // be used to form addressing mode. These wrapped nodes will be selected
1595 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1596 EVT PtrVT = Op.getValueType();
1597 // FIXME there is no actual debug info here
1598 DebugLoc dl = Op.getDebugLoc();
1599 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1601 if (CP->isMachineConstantPoolEntry())
1602 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1603 CP->getAlignment());
1605 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1606 CP->getAlignment());
1607 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1610 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
1611 SelectionDAG &DAG) const {
1612 MachineFunction &MF = DAG.getMachineFunction();
1613 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1614 unsigned ARMPCLabelIndex = 0;
1615 DebugLoc DL = Op.getDebugLoc();
1616 EVT PtrVT = getPointerTy();
1617 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1618 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1620 if (RelocM == Reloc::Static) {
1621 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
1623 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1624 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1625 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(BA, ARMPCLabelIndex,
1626 ARMCP::CPBlockAddress,
1628 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1630 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
1631 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
1632 PseudoSourceValue::getConstantPool(), 0,
1634 if (RelocM == Reloc::Static)
1636 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1637 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
1640 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
1642 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1643 SelectionDAG &DAG) const {
1644 DebugLoc dl = GA->getDebugLoc();
1645 EVT PtrVT = getPointerTy();
1646 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1647 MachineFunction &MF = DAG.getMachineFunction();
1648 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1649 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1650 ARMConstantPoolValue *CPV =
1651 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1652 ARMCP::CPValue, PCAdj, "tlsgd", true);
1653 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1654 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
1655 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
1656 PseudoSourceValue::getConstantPool(), 0,
1658 SDValue Chain = Argument.getValue(1);
1660 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1661 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
1663 // call __tls_get_addr.
1666 Entry.Node = Argument;
1667 Entry.Ty = (const Type *) Type::getInt32Ty(*DAG.getContext());
1668 Args.push_back(Entry);
1669 // FIXME: is there useful debug info available here?
1670 std::pair<SDValue, SDValue> CallResult =
1671 LowerCallTo(Chain, (const Type *) Type::getInt32Ty(*DAG.getContext()),
1672 false, false, false, false,
1673 0, CallingConv::C, false, /*isReturnValueUsed=*/true,
1674 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
1675 return CallResult.first;
1678 // Lower ISD::GlobalTLSAddress using the "initial exec" or
1679 // "local exec" model.
1681 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
1682 SelectionDAG &DAG) const {
1683 const GlobalValue *GV = GA->getGlobal();
1684 DebugLoc dl = GA->getDebugLoc();
1686 SDValue Chain = DAG.getEntryNode();
1687 EVT PtrVT = getPointerTy();
1688 // Get the Thread Pointer
1689 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1691 if (GV->isDeclaration()) {
1692 MachineFunction &MF = DAG.getMachineFunction();
1693 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1694 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1695 // Initial exec model.
1696 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1697 ARMConstantPoolValue *CPV =
1698 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1699 ARMCP::CPValue, PCAdj, "gottpoff", true);
1700 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1701 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1702 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1703 PseudoSourceValue::getConstantPool(), 0,
1705 Chain = Offset.getValue(1);
1707 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1708 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
1710 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1711 PseudoSourceValue::getConstantPool(), 0,
1715 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, "tpoff");
1716 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1717 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1718 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1719 PseudoSourceValue::getConstantPool(), 0,
1723 // The address of the thread local variable is the add of the thread
1724 // pointer with the offset of the variable.
1725 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
1729 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
1730 // TODO: implement the "local dynamic" model
1731 assert(Subtarget->isTargetELF() &&
1732 "TLS not implemented for non-ELF targets");
1733 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1734 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
1735 // otherwise use the "Local Exec" TLS Model
1736 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
1737 return LowerToTLSGeneralDynamicModel(GA, DAG);
1739 return LowerToTLSExecModels(GA, DAG);
1742 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
1743 SelectionDAG &DAG) const {
1744 EVT PtrVT = getPointerTy();
1745 DebugLoc dl = Op.getDebugLoc();
1746 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1747 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1748 if (RelocM == Reloc::PIC_) {
1749 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
1750 ARMConstantPoolValue *CPV =
1751 new ARMConstantPoolValue(GV, UseGOTOFF ? "GOTOFF" : "GOT");
1752 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1753 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1754 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1756 PseudoSourceValue::getConstantPool(), 0,
1758 SDValue Chain = Result.getValue(1);
1759 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1760 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
1762 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
1763 PseudoSourceValue::getGOT(), 0,
1767 // If we have T2 ops, we can materialize the address directly via movt/movw
1768 // pair. This is always cheaper.
1769 if (Subtarget->useMovt()) {
1770 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
1771 DAG.getTargetGlobalAddress(GV, PtrVT));
1773 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1774 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1775 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1776 PseudoSourceValue::getConstantPool(), 0,
1782 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
1783 SelectionDAG &DAG) const {
1784 MachineFunction &MF = DAG.getMachineFunction();
1785 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1786 unsigned ARMPCLabelIndex = 0;
1787 EVT PtrVT = getPointerTy();
1788 DebugLoc dl = Op.getDebugLoc();
1789 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1790 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1792 if (RelocM == Reloc::Static)
1793 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1795 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1796 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8);
1797 ARMConstantPoolValue *CPV =
1798 new ARMConstantPoolValue(GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj);
1799 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1801 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1803 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1804 PseudoSourceValue::getConstantPool(), 0,
1806 SDValue Chain = Result.getValue(1);
1808 if (RelocM == Reloc::PIC_) {
1809 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1810 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1813 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
1814 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
1815 PseudoSourceValue::getGOT(), 0,
1821 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
1822 SelectionDAG &DAG) const {
1823 assert(Subtarget->isTargetELF() &&
1824 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
1825 MachineFunction &MF = DAG.getMachineFunction();
1826 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1827 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1828 EVT PtrVT = getPointerTy();
1829 DebugLoc dl = Op.getDebugLoc();
1830 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1831 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1832 "_GLOBAL_OFFSET_TABLE_",
1833 ARMPCLabelIndex, PCAdj);
1834 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1835 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1836 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1837 PseudoSourceValue::getConstantPool(), 0,
1839 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1840 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1844 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
1845 DebugLoc dl = Op.getDebugLoc();
1846 SDValue Val = DAG.getConstant(0, MVT::i32);
1847 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(0),
1848 Op.getOperand(1), Val);
1852 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
1853 DebugLoc dl = Op.getDebugLoc();
1854 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
1855 Op.getOperand(1), DAG.getConstant(0, MVT::i32));
1859 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
1860 const ARMSubtarget *Subtarget) const {
1861 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1862 DebugLoc dl = Op.getDebugLoc();
1864 default: return SDValue(); // Don't custom lower most intrinsics.
1865 case Intrinsic::arm_thread_pointer: {
1866 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1867 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1869 case Intrinsic::eh_sjlj_lsda: {
1870 MachineFunction &MF = DAG.getMachineFunction();
1871 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1872 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1873 EVT PtrVT = getPointerTy();
1874 DebugLoc dl = Op.getDebugLoc();
1875 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1877 unsigned PCAdj = (RelocM != Reloc::PIC_)
1878 ? 0 : (Subtarget->isThumb() ? 4 : 8);
1879 ARMConstantPoolValue *CPV =
1880 new ARMConstantPoolValue(MF.getFunction(), ARMPCLabelIndex,
1881 ARMCP::CPLSDA, PCAdj);
1882 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1883 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1885 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1886 PseudoSourceValue::getConstantPool(), 0,
1888 SDValue Chain = Result.getValue(1);
1890 if (RelocM == Reloc::PIC_) {
1891 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1892 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1899 static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG,
1900 const ARMSubtarget *Subtarget) {
1901 DebugLoc dl = Op.getDebugLoc();
1902 SDValue Op5 = Op.getOperand(5);
1903 unsigned isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue();
1904 // v6 and v7 can both handle barriers directly, but need handled a bit
1905 // differently. Thumb1 and pre-v6 ARM mode use a libcall instead and should
1907 unsigned Opc = isDeviceBarrier ? ARMISD::SYNCBARRIER : ARMISD::MEMBARRIER;
1908 if (Subtarget->hasV7Ops())
1909 return DAG.getNode(Opc, dl, MVT::Other, Op.getOperand(0));
1910 else if (Subtarget->hasV6Ops() && !Subtarget->isThumb1Only())
1911 return DAG.getNode(Opc, dl, MVT::Other, Op.getOperand(0),
1912 DAG.getConstant(0, MVT::i32));
1913 assert(0 && "Unexpected ISD::MEMBARRIER encountered. Should be libcall!");
1917 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
1918 MachineFunction &MF = DAG.getMachineFunction();
1919 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
1921 // vastart just stores the address of the VarArgsFrameIndex slot into the
1922 // memory location argument.
1923 DebugLoc dl = Op.getDebugLoc();
1924 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1925 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1926 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1927 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0,
1932 ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
1933 SelectionDAG &DAG) const {
1934 SDNode *Node = Op.getNode();
1935 DebugLoc dl = Node->getDebugLoc();
1936 EVT VT = Node->getValueType(0);
1937 SDValue Chain = Op.getOperand(0);
1938 SDValue Size = Op.getOperand(1);
1939 SDValue Align = Op.getOperand(2);
1941 // Chain the dynamic stack allocation so that it doesn't modify the stack
1942 // pointer when other instructions are using the stack.
1943 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1945 unsigned AlignVal = cast<ConstantSDNode>(Align)->getZExtValue();
1946 unsigned StackAlign = getTargetMachine().getFrameInfo()->getStackAlignment();
1947 if (AlignVal > StackAlign)
1948 // Do this now since selection pass cannot introduce new target
1949 // independent node.
1950 Align = DAG.getConstant(-(uint64_t)AlignVal, VT);
1952 // In Thumb1 mode, there isn't a "sub r, sp, r" instruction, we will end up
1953 // using a "add r, sp, r" instead. Negate the size now so we don't have to
1954 // do even more horrible hack later.
1955 MachineFunction &MF = DAG.getMachineFunction();
1956 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1957 if (AFI->isThumb1OnlyFunction()) {
1959 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Size);
1961 uint32_t Val = C->getZExtValue();
1962 if (Val <= 508 && ((Val & 3) == 0))
1966 Size = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, VT), Size);
1969 SDVTList VTList = DAG.getVTList(VT, MVT::Other);
1970 SDValue Ops1[] = { Chain, Size, Align };
1971 SDValue Res = DAG.getNode(ARMISD::DYN_ALLOC, dl, VTList, Ops1, 3);
1972 Chain = Res.getValue(1);
1973 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1974 DAG.getIntPtrConstant(0, true), SDValue());
1975 SDValue Ops2[] = { Res, Chain };
1976 return DAG.getMergeValues(Ops2, 2, dl);
1980 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
1981 SDValue &Root, SelectionDAG &DAG,
1982 DebugLoc dl) const {
1983 MachineFunction &MF = DAG.getMachineFunction();
1984 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1986 TargetRegisterClass *RC;
1987 if (AFI->isThumb1OnlyFunction())
1988 RC = ARM::tGPRRegisterClass;
1990 RC = ARM::GPRRegisterClass;
1992 // Transform the arguments stored in physical registers into virtual ones.
1993 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1994 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
1997 if (NextVA.isMemLoc()) {
1998 MachineFrameInfo *MFI = MF.getFrameInfo();
1999 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true, false);
2001 // Create load node to retrieve arguments from the stack.
2002 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2003 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
2004 PseudoSourceValue::getFixedStack(FI), 0,
2007 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2008 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2011 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
2015 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
2016 CallingConv::ID CallConv, bool isVarArg,
2017 const SmallVectorImpl<ISD::InputArg>
2019 DebugLoc dl, SelectionDAG &DAG,
2020 SmallVectorImpl<SDValue> &InVals)
2023 MachineFunction &MF = DAG.getMachineFunction();
2024 MachineFrameInfo *MFI = MF.getFrameInfo();
2026 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2028 // Assign locations to all of the incoming arguments.
2029 SmallVector<CCValAssign, 16> ArgLocs;
2030 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
2032 CCInfo.AnalyzeFormalArguments(Ins,
2033 CCAssignFnForNode(CallConv, /* Return*/ false,
2036 SmallVector<SDValue, 16> ArgValues;
2038 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2039 CCValAssign &VA = ArgLocs[i];
2041 // Arguments stored in registers.
2042 if (VA.isRegLoc()) {
2043 EVT RegVT = VA.getLocVT();
2046 if (VA.needsCustom()) {
2047 // f64 and vector types are split up into multiple registers or
2048 // combinations of registers and stack slots.
2049 if (VA.getLocVT() == MVT::v2f64) {
2050 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
2052 VA = ArgLocs[++i]; // skip ahead to next loc
2054 if (VA.isMemLoc()) {
2055 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(),
2057 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2058 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
2059 PseudoSourceValue::getFixedStack(FI), 0,
2062 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
2065 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2066 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2067 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
2068 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2069 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
2071 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
2074 TargetRegisterClass *RC;
2076 if (RegVT == MVT::f32)
2077 RC = ARM::SPRRegisterClass;
2078 else if (RegVT == MVT::f64)
2079 RC = ARM::DPRRegisterClass;
2080 else if (RegVT == MVT::v2f64)
2081 RC = ARM::QPRRegisterClass;
2082 else if (RegVT == MVT::i32)
2083 RC = (AFI->isThumb1OnlyFunction() ?
2084 ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
2086 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2088 // Transform the arguments in physical registers into virtual ones.
2089 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2090 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2093 // If this is an 8 or 16-bit value, it is really passed promoted
2094 // to 32 bits. Insert an assert[sz]ext to capture this, then
2095 // truncate to the right size.
2096 switch (VA.getLocInfo()) {
2097 default: llvm_unreachable("Unknown loc info!");
2098 case CCValAssign::Full: break;
2099 case CCValAssign::BCvt:
2100 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
2102 case CCValAssign::SExt:
2103 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2104 DAG.getValueType(VA.getValVT()));
2105 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2107 case CCValAssign::ZExt:
2108 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2109 DAG.getValueType(VA.getValVT()));
2110 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2114 InVals.push_back(ArgValue);
2116 } else { // VA.isRegLoc()
2119 assert(VA.isMemLoc());
2120 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
2122 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
2123 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2126 // Create load nodes to retrieve arguments from the stack.
2127 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2128 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2129 PseudoSourceValue::getFixedStack(FI), 0,
2136 static const unsigned GPRArgRegs[] = {
2137 ARM::R0, ARM::R1, ARM::R2, ARM::R3
2140 unsigned NumGPRs = CCInfo.getFirstUnallocated
2141 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
2143 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
2144 unsigned VARegSize = (4 - NumGPRs) * 4;
2145 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
2146 unsigned ArgOffset = CCInfo.getNextStackOffset();
2147 if (VARegSaveSize) {
2148 // If this function is vararg, store any remaining integer argument regs
2149 // to their spots on the stack so that they may be loaded by deferencing
2150 // the result of va_next.
2151 AFI->setVarArgsRegSaveSize(VARegSaveSize);
2152 AFI->setVarArgsFrameIndex(
2153 MFI->CreateFixedObject(VARegSaveSize,
2154 ArgOffset + VARegSaveSize - VARegSize,
2156 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(),
2159 SmallVector<SDValue, 4> MemOps;
2160 for (; NumGPRs < 4; ++NumGPRs) {
2161 TargetRegisterClass *RC;
2162 if (AFI->isThumb1OnlyFunction())
2163 RC = ARM::tGPRRegisterClass;
2165 RC = ARM::GPRRegisterClass;
2167 unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
2168 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2170 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2171 PseudoSourceValue::getFixedStack(AFI->getVarArgsFrameIndex()),
2172 0, false, false, 0);
2173 MemOps.push_back(Store);
2174 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
2175 DAG.getConstant(4, getPointerTy()));
2177 if (!MemOps.empty())
2178 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2179 &MemOps[0], MemOps.size());
2181 // This will point to the next argument passed via stack.
2182 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset,
2189 /// isFloatingPointZero - Return true if this is +0.0.
2190 static bool isFloatingPointZero(SDValue Op) {
2191 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
2192 return CFP->getValueAPF().isPosZero();
2193 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
2194 // Maybe this has already been legalized into the constant pool?
2195 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
2196 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
2197 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
2198 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
2199 return CFP->getValueAPF().isPosZero();
2205 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
2206 /// the given operands.
2208 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2209 SDValue &ARMCC, SelectionDAG &DAG,
2210 DebugLoc dl) const {
2211 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
2212 unsigned C = RHSC->getZExtValue();
2213 if (!isLegalICmpImmediate(C)) {
2214 // Constant does not fit, try adjusting it by one?
2219 if (isLegalICmpImmediate(C-1)) {
2220 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
2221 RHS = DAG.getConstant(C-1, MVT::i32);
2226 if (C > 0 && isLegalICmpImmediate(C-1)) {
2227 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
2228 RHS = DAG.getConstant(C-1, MVT::i32);
2233 if (isLegalICmpImmediate(C+1)) {
2234 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
2235 RHS = DAG.getConstant(C+1, MVT::i32);
2240 if (C < 0xffffffff && isLegalICmpImmediate(C+1)) {
2241 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2242 RHS = DAG.getConstant(C+1, MVT::i32);
2249 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2250 ARMISD::NodeType CompareType;
2253 CompareType = ARMISD::CMP;
2258 CompareType = ARMISD::CMPZ;
2261 ARMCC = DAG.getConstant(CondCode, MVT::i32);
2262 return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS);
2265 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
2266 static SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
2269 if (!isFloatingPointZero(RHS))
2270 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS);
2272 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS);
2273 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp);
2276 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
2277 EVT VT = Op.getValueType();
2278 SDValue LHS = Op.getOperand(0);
2279 SDValue RHS = Op.getOperand(1);
2280 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2281 SDValue TrueVal = Op.getOperand(2);
2282 SDValue FalseVal = Op.getOperand(3);
2283 DebugLoc dl = Op.getDebugLoc();
2285 if (LHS.getValueType() == MVT::i32) {
2287 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2288 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, dl);
2289 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC, CCR,Cmp);
2292 ARMCC::CondCodes CondCode, CondCode2;
2293 FPCCToARMCC(CC, CondCode, CondCode2);
2295 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
2296 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2297 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2298 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
2300 if (CondCode2 != ARMCC::AL) {
2301 SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
2302 // FIXME: Needs another CMP because flag can have but one use.
2303 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
2304 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
2305 Result, TrueVal, ARMCC2, CCR, Cmp2);
2310 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2311 SDValue Chain = Op.getOperand(0);
2312 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2313 SDValue LHS = Op.getOperand(2);
2314 SDValue RHS = Op.getOperand(3);
2315 SDValue Dest = Op.getOperand(4);
2316 DebugLoc dl = Op.getDebugLoc();
2318 if (LHS.getValueType() == MVT::i32) {
2320 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2321 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, dl);
2322 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2323 Chain, Dest, ARMCC, CCR,Cmp);
2326 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
2327 ARMCC::CondCodes CondCode, CondCode2;
2328 FPCCToARMCC(CC, CondCode, CondCode2);
2330 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2331 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
2332 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2333 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
2334 SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp };
2335 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2336 if (CondCode2 != ARMCC::AL) {
2337 ARMCC = DAG.getConstant(CondCode2, MVT::i32);
2338 SDValue Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) };
2339 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2344 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
2345 SDValue Chain = Op.getOperand(0);
2346 SDValue Table = Op.getOperand(1);
2347 SDValue Index = Op.getOperand(2);
2348 DebugLoc dl = Op.getDebugLoc();
2350 EVT PTy = getPointerTy();
2351 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
2352 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
2353 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
2354 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
2355 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
2356 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
2357 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2358 if (Subtarget->isThumb2()) {
2359 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
2360 // which does another jump to the destination. This also makes it easier
2361 // to translate it to TBB / TBH later.
2362 // FIXME: This might not work if the function is extremely large.
2363 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
2364 Addr, Op.getOperand(2), JTI, UId);
2366 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2367 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
2368 PseudoSourceValue::getJumpTable(), 0,
2370 Chain = Addr.getValue(1);
2371 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
2372 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2374 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
2375 PseudoSourceValue::getJumpTable(), 0, false, false, 0);
2376 Chain = Addr.getValue(1);
2377 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2381 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
2382 DebugLoc dl = Op.getDebugLoc();
2385 switch (Op.getOpcode()) {
2387 assert(0 && "Invalid opcode!");
2388 case ISD::FP_TO_SINT:
2389 Opc = ARMISD::FTOSI;
2391 case ISD::FP_TO_UINT:
2392 Opc = ARMISD::FTOUI;
2395 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
2396 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
2399 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
2400 EVT VT = Op.getValueType();
2401 DebugLoc dl = Op.getDebugLoc();
2404 switch (Op.getOpcode()) {
2406 assert(0 && "Invalid opcode!");
2407 case ISD::SINT_TO_FP:
2408 Opc = ARMISD::SITOF;
2410 case ISD::UINT_TO_FP:
2411 Opc = ARMISD::UITOF;
2415 Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
2416 return DAG.getNode(Opc, dl, VT, Op);
2419 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
2420 // Implement fcopysign with a fabs and a conditional fneg.
2421 SDValue Tmp0 = Op.getOperand(0);
2422 SDValue Tmp1 = Op.getOperand(1);
2423 DebugLoc dl = Op.getDebugLoc();
2424 EVT VT = Op.getValueType();
2425 EVT SrcVT = Tmp1.getValueType();
2426 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
2427 SDValue Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG, dl);
2428 SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
2429 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2430 return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp);
2433 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
2434 MachineFunction &MF = DAG.getMachineFunction();
2435 MachineFrameInfo *MFI = MF.getFrameInfo();
2436 MFI->setReturnAddressIsTaken(true);
2438 EVT VT = Op.getValueType();
2439 DebugLoc dl = Op.getDebugLoc();
2440 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2442 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
2443 SDValue Offset = DAG.getConstant(4, MVT::i32);
2444 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
2445 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
2446 NULL, 0, false, false, 0);
2449 // Return LR, which contains the return address. Mark it an implicit live-in.
2450 unsigned Reg = MF.addLiveIn(ARM::LR, ARM::GPRRegisterClass);
2451 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
2454 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2455 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2456 MFI->setFrameAddressIsTaken(true);
2458 EVT VT = Op.getValueType();
2459 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
2460 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2461 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
2462 ? ARM::R7 : ARM::R11;
2463 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
2465 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0,
2470 /// ExpandBIT_CONVERT - If the target supports VFP, this function is called to
2471 /// expand a bit convert where either the source or destination type is i64 to
2472 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
2473 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
2474 /// vectors), since the legalizer won't know what to do with that.
2475 static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
2476 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2477 DebugLoc dl = N->getDebugLoc();
2478 SDValue Op = N->getOperand(0);
2480 // This function is only supposed to be called for i64 types, either as the
2481 // source or destination of the bit convert.
2482 EVT SrcVT = Op.getValueType();
2483 EVT DstVT = N->getValueType(0);
2484 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
2485 "ExpandBIT_CONVERT called for non-i64 type");
2487 // Turn i64->f64 into VMOVDRR.
2488 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
2489 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2490 DAG.getConstant(0, MVT::i32));
2491 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2492 DAG.getConstant(1, MVT::i32));
2493 return DAG.getNode(ISD::BIT_CONVERT, dl, DstVT,
2494 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
2497 // Turn f64->i64 into VMOVRRD.
2498 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
2499 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
2500 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
2501 // Merge the pieces into a single i64 value.
2502 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
2508 /// getZeroVector - Returns a vector of specified type with all zero elements.
2510 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2511 assert(VT.isVector() && "Expected a vector type");
2513 // Zero vectors are used to represent vector negation and in those cases
2514 // will be implemented with the NEON VNEG instruction. However, VNEG does
2515 // not support i64 elements, so sometimes the zero vectors will need to be
2516 // explicitly constructed. For those cases, and potentially other uses in
2517 // the future, always build zero vectors as <16 x i8> or <8 x i8> bitcasted
2518 // to their dest type. This ensures they get CSE'd.
2520 SDValue Cst = DAG.getTargetConstant(0, MVT::i8);
2521 SmallVector<SDValue, 8> Ops;
2524 if (VT.getSizeInBits() == 64) {
2525 Ops.assign(8, Cst); TVT = MVT::v8i8;
2527 Ops.assign(16, Cst); TVT = MVT::v16i8;
2529 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, TVT, &Ops[0], Ops.size());
2531 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2534 /// getOnesVector - Returns a vector of specified type with all bits set.
2536 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2537 assert(VT.isVector() && "Expected a vector type");
2539 // Always build ones vectors as <16 x i8> or <8 x i8> bitcasted to their
2540 // dest type. This ensures they get CSE'd.
2542 SDValue Cst = DAG.getTargetConstant(0xFF, MVT::i8);
2543 SmallVector<SDValue, 8> Ops;
2546 if (VT.getSizeInBits() == 64) {
2547 Ops.assign(8, Cst); TVT = MVT::v8i8;
2549 Ops.assign(16, Cst); TVT = MVT::v16i8;
2551 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, TVT, &Ops[0], Ops.size());
2553 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2556 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
2557 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2558 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
2559 SelectionDAG &DAG) const {
2560 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2561 EVT VT = Op.getValueType();
2562 unsigned VTBits = VT.getSizeInBits();
2563 DebugLoc dl = Op.getDebugLoc();
2564 SDValue ShOpLo = Op.getOperand(0);
2565 SDValue ShOpHi = Op.getOperand(1);
2566 SDValue ShAmt = Op.getOperand(2);
2568 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
2570 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
2572 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2573 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2574 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
2575 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2576 DAG.getConstant(VTBits, MVT::i32));
2577 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
2578 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2579 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
2581 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2582 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
2584 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
2585 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC,
2588 SDValue Ops[2] = { Lo, Hi };
2589 return DAG.getMergeValues(Ops, 2, dl);
2592 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
2593 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2594 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
2595 SelectionDAG &DAG) const {
2596 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2597 EVT VT = Op.getValueType();
2598 unsigned VTBits = VT.getSizeInBits();
2599 DebugLoc dl = Op.getDebugLoc();
2600 SDValue ShOpLo = Op.getOperand(0);
2601 SDValue ShOpHi = Op.getOperand(1);
2602 SDValue ShAmt = Op.getOperand(2);
2605 assert(Op.getOpcode() == ISD::SHL_PARTS);
2606 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2607 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2608 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
2609 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2610 DAG.getConstant(VTBits, MVT::i32));
2611 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
2612 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
2614 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2615 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2616 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
2618 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
2619 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMCC,
2622 SDValue Ops[2] = { Lo, Hi };
2623 return DAG.getMergeValues(Ops, 2, dl);
2626 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
2627 const ARMSubtarget *ST) {
2628 EVT VT = N->getValueType(0);
2629 DebugLoc dl = N->getDebugLoc();
2631 if (!ST->hasV6T2Ops())
2634 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
2635 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
2638 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
2639 const ARMSubtarget *ST) {
2640 EVT VT = N->getValueType(0);
2641 DebugLoc dl = N->getDebugLoc();
2643 // Lower vector shifts on NEON to use VSHL.
2644 if (VT.isVector()) {
2645 assert(ST->hasNEON() && "unexpected vector shift");
2647 // Left shifts translate directly to the vshiftu intrinsic.
2648 if (N->getOpcode() == ISD::SHL)
2649 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2650 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
2651 N->getOperand(0), N->getOperand(1));
2653 assert((N->getOpcode() == ISD::SRA ||
2654 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
2656 // NEON uses the same intrinsics for both left and right shifts. For
2657 // right shifts, the shift amounts are negative, so negate the vector of
2659 EVT ShiftVT = N->getOperand(1).getValueType();
2660 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
2661 getZeroVector(ShiftVT, DAG, dl),
2663 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
2664 Intrinsic::arm_neon_vshifts :
2665 Intrinsic::arm_neon_vshiftu);
2666 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2667 DAG.getConstant(vshiftInt, MVT::i32),
2668 N->getOperand(0), NegatedCount);
2671 // We can get here for a node like i32 = ISD::SHL i32, i64
2675 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
2676 "Unknown shift to lower!");
2678 // We only lower SRA, SRL of 1 here, all others use generic lowering.
2679 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
2680 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
2683 // If we are in thumb mode, we don't have RRX.
2684 if (ST->isThumb1Only()) return SDValue();
2686 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
2687 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2688 DAG.getConstant(0, MVT::i32));
2689 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2690 DAG.getConstant(1, MVT::i32));
2692 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
2693 // captures the result into a carry flag.
2694 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
2695 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
2697 // The low part is an ARMISD::RRX operand, which shifts the carry in.
2698 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
2700 // Merge the pieces into a single i64 value.
2701 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
2704 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
2705 SDValue TmpOp0, TmpOp1;
2706 bool Invert = false;
2710 SDValue Op0 = Op.getOperand(0);
2711 SDValue Op1 = Op.getOperand(1);
2712 SDValue CC = Op.getOperand(2);
2713 EVT VT = Op.getValueType();
2714 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
2715 DebugLoc dl = Op.getDebugLoc();
2717 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
2718 switch (SetCCOpcode) {
2719 default: llvm_unreachable("Illegal FP comparison"); break;
2721 case ISD::SETNE: Invert = true; // Fallthrough
2723 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2725 case ISD::SETLT: Swap = true; // Fallthrough
2727 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2729 case ISD::SETLE: Swap = true; // Fallthrough
2731 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2732 case ISD::SETUGE: Swap = true; // Fallthrough
2733 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
2734 case ISD::SETUGT: Swap = true; // Fallthrough
2735 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
2736 case ISD::SETUEQ: Invert = true; // Fallthrough
2738 // Expand this to (OLT | OGT).
2742 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2743 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
2745 case ISD::SETUO: Invert = true; // Fallthrough
2747 // Expand this to (OLT | OGE).
2751 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2752 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
2756 // Integer comparisons.
2757 switch (SetCCOpcode) {
2758 default: llvm_unreachable("Illegal integer comparison"); break;
2759 case ISD::SETNE: Invert = true;
2760 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2761 case ISD::SETLT: Swap = true;
2762 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2763 case ISD::SETLE: Swap = true;
2764 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2765 case ISD::SETULT: Swap = true;
2766 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
2767 case ISD::SETULE: Swap = true;
2768 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
2771 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
2772 if (Opc == ARMISD::VCEQ) {
2775 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
2777 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
2780 // Ignore bitconvert.
2781 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BIT_CONVERT)
2782 AndOp = AndOp.getOperand(0);
2784 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
2786 Op0 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(0));
2787 Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(1));
2794 std::swap(Op0, Op1);
2796 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
2799 Result = DAG.getNOT(dl, Result, VT);
2804 /// isNEONModifiedImm - Check if the specified splat value corresponds to a
2805 /// valid vector constant for a NEON instruction with a "modified immediate"
2806 /// operand (e.g., VMOV). If so, return either the constant being
2807 /// splatted or the encoded value, depending on the DoEncode parameter. The
2808 /// format of the encoded value is: bit12=Op, bits11-8=Cmode,
2809 /// bits7-0=Immediate.
2810 static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
2811 unsigned SplatBitSize, SelectionDAG &DAG,
2812 bool isVMOV, bool DoEncode) {
2813 unsigned Op, Cmode, Imm;
2816 // SplatBitSize is set to the smallest size that splats the vector, so a
2817 // zero vector will always have SplatBitSize == 8. However, NEON modified
2818 // immediate instructions others than VMOV do not support the 8-bit encoding
2819 // of a zero vector, and the default encoding of zero is supposed to be the
2825 switch (SplatBitSize) {
2827 // Any 1-byte value is OK. Op=0, Cmode=1110.
2828 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
2835 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
2837 if ((SplatBits & ~0xff) == 0) {
2838 // Value = 0x00nn: Op=x, Cmode=100x.
2843 if ((SplatBits & ~0xff00) == 0) {
2844 // Value = 0xnn00: Op=x, Cmode=101x.
2846 Imm = SplatBits >> 8;
2852 // NEON's 32-bit VMOV supports splat values where:
2853 // * only one byte is nonzero, or
2854 // * the least significant byte is 0xff and the second byte is nonzero, or
2855 // * the least significant 2 bytes are 0xff and the third is nonzero.
2857 if ((SplatBits & ~0xff) == 0) {
2858 // Value = 0x000000nn: Op=x, Cmode=000x.
2863 if ((SplatBits & ~0xff00) == 0) {
2864 // Value = 0x0000nn00: Op=x, Cmode=001x.
2866 Imm = SplatBits >> 8;
2869 if ((SplatBits & ~0xff0000) == 0) {
2870 // Value = 0x00nn0000: Op=x, Cmode=010x.
2872 Imm = SplatBits >> 16;
2875 if ((SplatBits & ~0xff000000) == 0) {
2876 // Value = 0xnn000000: Op=x, Cmode=011x.
2878 Imm = SplatBits >> 24;
2882 if ((SplatBits & ~0xffff) == 0 &&
2883 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
2884 // Value = 0x0000nnff: Op=x, Cmode=1100.
2886 Imm = SplatBits >> 8;
2891 if ((SplatBits & ~0xffffff) == 0 &&
2892 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
2893 // Value = 0x00nnffff: Op=x, Cmode=1101.
2895 Imm = SplatBits >> 16;
2896 SplatBits |= 0xffff;
2900 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
2901 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
2902 // VMOV.I32. A (very) minor optimization would be to replicate the value
2903 // and fall through here to test for a valid 64-bit splat. But, then the
2904 // caller would also need to check and handle the change in size.
2908 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
2911 uint64_t BitMask = 0xff;
2913 unsigned ImmMask = 1;
2915 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
2916 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
2919 } else if ((SplatBits & BitMask) != 0) {
2925 // Op=1, Cmode=1110.
2934 llvm_unreachable("unexpected size for isNEONModifiedImm");
2939 return DAG.getTargetConstant((Op << 12) | (Cmode << 8) | Imm, MVT::i32);
2940 return DAG.getTargetConstant(SplatBits, VT);
2944 /// getNEONModImm - If this is a valid vector constant for a NEON instruction
2945 /// with a "modified immediate" operand (e.g., VMOV) of the specified element
2946 /// size, return the encoded value for that immediate. The ByteSize field
2947 /// indicates the number of bytes of each element [1248].
2948 SDValue ARM::getNEONModImm(SDNode *N, unsigned ByteSize, bool isVMOV,
2949 SelectionDAG &DAG) {
2950 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N);
2951 APInt SplatBits, SplatUndef;
2952 unsigned SplatBitSize;
2954 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
2955 HasAnyUndefs, ByteSize * 8))
2958 if (SplatBitSize > ByteSize * 8)
2961 return isNEONModifiedImm(SplatBits.getZExtValue(), SplatUndef.getZExtValue(),
2962 SplatBitSize, DAG, isVMOV, true);
2965 static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT,
2966 bool &ReverseVEXT, unsigned &Imm) {
2967 unsigned NumElts = VT.getVectorNumElements();
2968 ReverseVEXT = false;
2971 // If this is a VEXT shuffle, the immediate value is the index of the first
2972 // element. The other shuffle indices must be the successive elements after
2974 unsigned ExpectedElt = Imm;
2975 for (unsigned i = 1; i < NumElts; ++i) {
2976 // Increment the expected index. If it wraps around, it may still be
2977 // a VEXT but the source vectors must be swapped.
2979 if (ExpectedElt == NumElts * 2) {
2984 if (ExpectedElt != static_cast<unsigned>(M[i]))
2988 // Adjust the index value if the source operands will be swapped.
2995 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
2996 /// instruction with the specified blocksize. (The order of the elements
2997 /// within each block of the vector is reversed.)
2998 static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT,
2999 unsigned BlockSize) {
3000 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
3001 "Only possible block sizes for VREV are: 16, 32, 64");
3003 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3007 unsigned NumElts = VT.getVectorNumElements();
3008 unsigned BlockElts = M[0] + 1;
3010 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
3013 for (unsigned i = 0; i < NumElts; ++i) {
3014 if ((unsigned) M[i] !=
3015 (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
3022 static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT,
3023 unsigned &WhichResult) {
3024 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3028 unsigned NumElts = VT.getVectorNumElements();
3029 WhichResult = (M[0] == 0 ? 0 : 1);
3030 for (unsigned i = 0; i < NumElts; i += 2) {
3031 if ((unsigned) M[i] != i + WhichResult ||
3032 (unsigned) M[i+1] != i + NumElts + WhichResult)
3038 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
3039 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3040 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
3041 static bool isVTRN_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3042 unsigned &WhichResult) {
3043 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3047 unsigned NumElts = VT.getVectorNumElements();
3048 WhichResult = (M[0] == 0 ? 0 : 1);
3049 for (unsigned i = 0; i < NumElts; i += 2) {
3050 if ((unsigned) M[i] != i + WhichResult ||
3051 (unsigned) M[i+1] != i + WhichResult)
3057 static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT,
3058 unsigned &WhichResult) {
3059 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3063 unsigned NumElts = VT.getVectorNumElements();
3064 WhichResult = (M[0] == 0 ? 0 : 1);
3065 for (unsigned i = 0; i != NumElts; ++i) {
3066 if ((unsigned) M[i] != 2 * i + WhichResult)
3070 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3071 if (VT.is64BitVector() && EltSz == 32)
3077 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
3078 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3079 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
3080 static bool isVUZP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3081 unsigned &WhichResult) {
3082 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3086 unsigned Half = VT.getVectorNumElements() / 2;
3087 WhichResult = (M[0] == 0 ? 0 : 1);
3088 for (unsigned j = 0; j != 2; ++j) {
3089 unsigned Idx = WhichResult;
3090 for (unsigned i = 0; i != Half; ++i) {
3091 if ((unsigned) M[i + j * Half] != Idx)
3097 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3098 if (VT.is64BitVector() && EltSz == 32)
3104 static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT,
3105 unsigned &WhichResult) {
3106 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3110 unsigned NumElts = VT.getVectorNumElements();
3111 WhichResult = (M[0] == 0 ? 0 : 1);
3112 unsigned Idx = WhichResult * NumElts / 2;
3113 for (unsigned i = 0; i != NumElts; i += 2) {
3114 if ((unsigned) M[i] != Idx ||
3115 (unsigned) M[i+1] != Idx + NumElts)
3120 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3121 if (VT.is64BitVector() && EltSz == 32)
3127 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
3128 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3129 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
3130 static bool isVZIP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3131 unsigned &WhichResult) {
3132 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3136 unsigned NumElts = VT.getVectorNumElements();
3137 WhichResult = (M[0] == 0 ? 0 : 1);
3138 unsigned Idx = WhichResult * NumElts / 2;
3139 for (unsigned i = 0; i != NumElts; i += 2) {
3140 if ((unsigned) M[i] != Idx ||
3141 (unsigned) M[i+1] != Idx)
3146 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3147 if (VT.is64BitVector() && EltSz == 32)
3154 static SDValue BuildSplat(SDValue Val, EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3155 // Canonicalize all-zeros and all-ones vectors.
3156 ConstantSDNode *ConstVal = cast<ConstantSDNode>(Val.getNode());
3157 if (ConstVal->isNullValue())
3158 return getZeroVector(VT, DAG, dl);
3159 if (ConstVal->isAllOnesValue())
3160 return getOnesVector(VT, DAG, dl);
3163 if (VT.is64BitVector()) {
3164 switch (Val.getValueType().getSizeInBits()) {
3165 case 8: CanonicalVT = MVT::v8i8; break;
3166 case 16: CanonicalVT = MVT::v4i16; break;
3167 case 32: CanonicalVT = MVT::v2i32; break;
3168 case 64: CanonicalVT = MVT::v1i64; break;
3169 default: llvm_unreachable("unexpected splat element type"); break;
3172 assert(VT.is128BitVector() && "unknown splat vector size");
3173 switch (Val.getValueType().getSizeInBits()) {
3174 case 8: CanonicalVT = MVT::v16i8; break;
3175 case 16: CanonicalVT = MVT::v8i16; break;
3176 case 32: CanonicalVT = MVT::v4i32; break;
3177 case 64: CanonicalVT = MVT::v2i64; break;
3178 default: llvm_unreachable("unexpected splat element type"); break;
3182 // Build a canonical splat for this value.
3183 SmallVector<SDValue, 8> Ops;
3184 Ops.assign(CanonicalVT.getVectorNumElements(), Val);
3185 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, &Ops[0],
3187 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Res);
3190 // If this is a case we can't handle, return null and let the default
3191 // expansion code take care of it.
3192 static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3193 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
3194 DebugLoc dl = Op.getDebugLoc();
3195 EVT VT = Op.getValueType();
3197 APInt SplatBits, SplatUndef;
3198 unsigned SplatBitSize;
3200 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
3201 if (SplatBitSize <= 64) {
3202 // Check if an immediate VMOV works.
3203 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
3204 SplatUndef.getZExtValue(),
3205 SplatBitSize, DAG, true, false);
3207 return BuildSplat(Val, VT, DAG, dl);
3211 // Scan through the operands to see if only one value is used.
3212 unsigned NumElts = VT.getVectorNumElements();
3213 bool isOnlyLowElement = true;
3214 bool usesOnlyOneValue = true;
3215 bool isConstant = true;
3217 for (unsigned i = 0; i < NumElts; ++i) {
3218 SDValue V = Op.getOperand(i);
3219 if (V.getOpcode() == ISD::UNDEF)
3222 isOnlyLowElement = false;
3223 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
3226 if (!Value.getNode())
3228 else if (V != Value)
3229 usesOnlyOneValue = false;
3232 if (!Value.getNode())
3233 return DAG.getUNDEF(VT);
3235 if (isOnlyLowElement)
3236 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
3238 // If all elements are constants, fall back to the default expansion, which
3239 // will generate a load from the constant pool.
3243 // Use VDUP for non-constant splats.
3244 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3245 if (usesOnlyOneValue && EltSize <= 32)
3246 return DAG.getNode(ARMISD::VDUP, dl, VT, Value);
3248 // Vectors with 32- or 64-bit elements can be built by directly assigning
3249 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
3250 // will be legalized.
3251 if (EltSize >= 32) {
3252 // Do the expansion with floating-point types, since that is what the VFP
3253 // registers are defined to use, and since i64 is not legal.
3254 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3255 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3256 SmallVector<SDValue, 8> Ops;
3257 for (unsigned i = 0; i < NumElts; ++i)
3258 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, EltVT, Op.getOperand(i)));
3259 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
3260 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val);
3266 /// isShuffleMaskLegal - Targets can use this to indicate that they only
3267 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
3268 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
3269 /// are assumed to be legal.
3271 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
3273 if (VT.getVectorNumElements() == 4 &&
3274 (VT.is128BitVector() || VT.is64BitVector())) {
3275 unsigned PFIndexes[4];
3276 for (unsigned i = 0; i != 4; ++i) {
3280 PFIndexes[i] = M[i];
3283 // Compute the index in the perfect shuffle table.
3284 unsigned PFTableIndex =
3285 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3286 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3287 unsigned Cost = (PFEntry >> 30);
3294 unsigned Imm, WhichResult;
3296 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3297 return (EltSize >= 32 ||
3298 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
3299 isVREVMask(M, VT, 64) ||
3300 isVREVMask(M, VT, 32) ||
3301 isVREVMask(M, VT, 16) ||
3302 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
3303 isVTRNMask(M, VT, WhichResult) ||
3304 isVUZPMask(M, VT, WhichResult) ||
3305 isVZIPMask(M, VT, WhichResult) ||
3306 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
3307 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
3308 isVZIP_v_undef_Mask(M, VT, WhichResult));
3311 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
3312 /// the specified operations to build the shuffle.
3313 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
3314 SDValue RHS, SelectionDAG &DAG,
3316 unsigned OpNum = (PFEntry >> 26) & 0x0F;
3317 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
3318 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
3321 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
3330 OP_VUZPL, // VUZP, left result
3331 OP_VUZPR, // VUZP, right result
3332 OP_VZIPL, // VZIP, left result
3333 OP_VZIPR, // VZIP, right result
3334 OP_VTRNL, // VTRN, left result
3335 OP_VTRNR // VTRN, right result
3338 if (OpNum == OP_COPY) {
3339 if (LHSID == (1*9+2)*9+3) return LHS;
3340 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
3344 SDValue OpLHS, OpRHS;
3345 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
3346 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
3347 EVT VT = OpLHS.getValueType();
3350 default: llvm_unreachable("Unknown shuffle opcode!");
3352 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
3357 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
3358 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
3362 return DAG.getNode(ARMISD::VEXT, dl, VT,
3364 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
3367 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3368 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
3371 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3372 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
3375 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3376 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
3380 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
3381 SDValue V1 = Op.getOperand(0);
3382 SDValue V2 = Op.getOperand(1);
3383 DebugLoc dl = Op.getDebugLoc();
3384 EVT VT = Op.getValueType();
3385 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
3386 SmallVector<int, 8> ShuffleMask;
3388 // Convert shuffles that are directly supported on NEON to target-specific
3389 // DAG nodes, instead of keeping them as shuffles and matching them again
3390 // during code selection. This is more efficient and avoids the possibility
3391 // of inconsistencies between legalization and selection.
3392 // FIXME: floating-point vectors should be canonicalized to integer vectors
3393 // of the same time so that they get CSEd properly.
3394 SVN->getMask(ShuffleMask);
3396 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3397 if (EltSize <= 32) {
3398 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
3399 int Lane = SVN->getSplatIndex();
3400 // If this is undef splat, generate it via "just" vdup, if possible.
3401 if (Lane == -1) Lane = 0;
3403 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
3404 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
3406 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
3407 DAG.getConstant(Lane, MVT::i32));
3412 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
3415 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
3416 DAG.getConstant(Imm, MVT::i32));
3419 if (isVREVMask(ShuffleMask, VT, 64))
3420 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
3421 if (isVREVMask(ShuffleMask, VT, 32))
3422 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
3423 if (isVREVMask(ShuffleMask, VT, 16))
3424 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
3426 // Check for Neon shuffles that modify both input vectors in place.
3427 // If both results are used, i.e., if there are two shuffles with the same
3428 // source operands and with masks corresponding to both results of one of
3429 // these operations, DAG memoization will ensure that a single node is
3430 // used for both shuffles.
3431 unsigned WhichResult;
3432 if (isVTRNMask(ShuffleMask, VT, WhichResult))
3433 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3434 V1, V2).getValue(WhichResult);
3435 if (isVUZPMask(ShuffleMask, VT, WhichResult))
3436 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3437 V1, V2).getValue(WhichResult);
3438 if (isVZIPMask(ShuffleMask, VT, WhichResult))
3439 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3440 V1, V2).getValue(WhichResult);
3442 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
3443 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3444 V1, V1).getValue(WhichResult);
3445 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
3446 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3447 V1, V1).getValue(WhichResult);
3448 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
3449 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3450 V1, V1).getValue(WhichResult);
3453 // If the shuffle is not directly supported and it has 4 elements, use
3454 // the PerfectShuffle-generated table to synthesize it from other shuffles.
3455 unsigned NumElts = VT.getVectorNumElements();
3457 unsigned PFIndexes[4];
3458 for (unsigned i = 0; i != 4; ++i) {
3459 if (ShuffleMask[i] < 0)
3462 PFIndexes[i] = ShuffleMask[i];
3465 // Compute the index in the perfect shuffle table.
3466 unsigned PFTableIndex =
3467 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3468 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3469 unsigned Cost = (PFEntry >> 30);
3472 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
3475 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
3476 if (EltSize >= 32) {
3477 // Do the expansion with floating-point types, since that is what the VFP
3478 // registers are defined to use, and since i64 is not legal.
3479 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3480 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3481 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, V1);
3482 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, V2);
3483 SmallVector<SDValue, 8> Ops;
3484 for (unsigned i = 0; i < NumElts; ++i) {
3485 if (ShuffleMask[i] < 0)
3486 Ops.push_back(DAG.getUNDEF(EltVT));
3488 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3489 ShuffleMask[i] < (int)NumElts ? V1 : V2,
3490 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
3493 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
3494 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val);
3500 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
3501 EVT VT = Op.getValueType();
3502 DebugLoc dl = Op.getDebugLoc();
3503 SDValue Vec = Op.getOperand(0);
3504 SDValue Lane = Op.getOperand(1);
3505 assert(VT == MVT::i32 &&
3506 Vec.getValueType().getVectorElementType().getSizeInBits() < 32 &&
3507 "unexpected type for custom-lowering vector extract");
3508 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
3511 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
3512 // The only time a CONCAT_VECTORS operation can have legal types is when
3513 // two 64-bit vectors are concatenated to a 128-bit vector.
3514 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
3515 "unexpected CONCAT_VECTORS");
3516 DebugLoc dl = Op.getDebugLoc();
3517 SDValue Val = DAG.getUNDEF(MVT::v2f64);
3518 SDValue Op0 = Op.getOperand(0);
3519 SDValue Op1 = Op.getOperand(1);
3520 if (Op0.getOpcode() != ISD::UNDEF)
3521 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
3522 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op0),
3523 DAG.getIntPtrConstant(0));
3524 if (Op1.getOpcode() != ISD::UNDEF)
3525 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
3526 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op1),
3527 DAG.getIntPtrConstant(1));
3528 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Val);
3531 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
3532 switch (Op.getOpcode()) {
3533 default: llvm_unreachable("Don't know how to custom lower this!");
3534 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3535 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
3536 case ISD::GlobalAddress:
3537 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
3538 LowerGlobalAddressELF(Op, DAG);
3539 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
3540 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
3541 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
3542 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
3543 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
3544 case ISD::VASTART: return LowerVASTART(Op, DAG);
3545 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget);
3546 case ISD::SINT_TO_FP:
3547 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
3548 case ISD::FP_TO_SINT:
3549 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
3550 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
3551 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
3552 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
3553 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
3554 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
3555 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
3556 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
3558 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(Op.getNode(), DAG);
3561 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
3562 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
3563 case ISD::SRL_PARTS:
3564 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
3565 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
3566 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
3567 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
3568 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
3569 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
3570 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
3575 /// ReplaceNodeResults - Replace the results of node with an illegal result
3576 /// type with new values built out of custom code.
3577 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
3578 SmallVectorImpl<SDValue>&Results,
3579 SelectionDAG &DAG) const {
3581 switch (N->getOpcode()) {
3583 llvm_unreachable("Don't know how to custom expand this!");
3585 case ISD::BIT_CONVERT:
3586 Res = ExpandBIT_CONVERT(N, DAG);
3590 Res = LowerShift(N, DAG, Subtarget);
3594 Results.push_back(Res);
3597 //===----------------------------------------------------------------------===//
3598 // ARM Scheduler Hooks
3599 //===----------------------------------------------------------------------===//
3602 ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
3603 MachineBasicBlock *BB,
3604 unsigned Size) const {
3605 unsigned dest = MI->getOperand(0).getReg();
3606 unsigned ptr = MI->getOperand(1).getReg();
3607 unsigned oldval = MI->getOperand(2).getReg();
3608 unsigned newval = MI->getOperand(3).getReg();
3609 unsigned scratch = BB->getParent()->getRegInfo()
3610 .createVirtualRegister(ARM::GPRRegisterClass);
3611 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3612 DebugLoc dl = MI->getDebugLoc();
3613 bool isThumb2 = Subtarget->isThumb2();
3615 unsigned ldrOpc, strOpc;
3617 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
3619 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
3620 strOpc = isThumb2 ? ARM::t2LDREXB : ARM::STREXB;
3623 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
3624 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
3627 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
3628 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
3632 MachineFunction *MF = BB->getParent();
3633 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3634 MachineFunction::iterator It = BB;
3635 ++It; // insert the new blocks after the current block
3637 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
3638 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
3639 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3640 MF->insert(It, loop1MBB);
3641 MF->insert(It, loop2MBB);
3642 MF->insert(It, exitMBB);
3643 exitMBB->transferSuccessors(BB);
3647 // fallthrough --> loop1MBB
3648 BB->addSuccessor(loop1MBB);
3651 // ldrex dest, [ptr]
3655 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
3656 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
3657 .addReg(dest).addReg(oldval));
3658 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3659 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
3660 BB->addSuccessor(loop2MBB);
3661 BB->addSuccessor(exitMBB);
3664 // strex scratch, newval, [ptr]
3668 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval)
3670 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
3671 .addReg(scratch).addImm(0));
3672 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3673 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
3674 BB->addSuccessor(loop1MBB);
3675 BB->addSuccessor(exitMBB);
3681 MF->DeleteMachineInstr(MI); // The instruction is gone now.
3687 ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
3688 unsigned Size, unsigned BinOpcode) const {
3689 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
3690 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3692 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3693 MachineFunction *MF = BB->getParent();
3694 MachineFunction::iterator It = BB;
3697 unsigned dest = MI->getOperand(0).getReg();
3698 unsigned ptr = MI->getOperand(1).getReg();
3699 unsigned incr = MI->getOperand(2).getReg();
3700 DebugLoc dl = MI->getDebugLoc();
3702 bool isThumb2 = Subtarget->isThumb2();
3703 unsigned ldrOpc, strOpc;
3705 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
3707 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
3708 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
3711 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
3712 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
3715 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
3716 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
3720 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3721 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3722 MF->insert(It, loopMBB);
3723 MF->insert(It, exitMBB);
3724 exitMBB->transferSuccessors(BB);
3726 MachineRegisterInfo &RegInfo = MF->getRegInfo();
3727 unsigned scratch = RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
3728 unsigned scratch2 = (!BinOpcode) ? incr :
3729 RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
3733 // fallthrough --> loopMBB
3734 BB->addSuccessor(loopMBB);
3738 // <binop> scratch2, dest, incr
3739 // strex scratch, scratch2, ptr
3742 // fallthrough --> exitMBB
3744 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
3746 // operand order needs to go the other way for NAND
3747 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr)
3748 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
3749 addReg(incr).addReg(dest)).addReg(0);
3751 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
3752 addReg(dest).addReg(incr)).addReg(0);
3755 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2)
3757 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
3758 .addReg(scratch).addImm(0));
3759 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3760 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
3762 BB->addSuccessor(loopMBB);
3763 BB->addSuccessor(exitMBB);
3769 MF->DeleteMachineInstr(MI); // The instruction is gone now.
3775 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
3776 MachineBasicBlock *BB) const {
3777 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3778 DebugLoc dl = MI->getDebugLoc();
3779 bool isThumb2 = Subtarget->isThumb2();
3780 switch (MI->getOpcode()) {
3783 llvm_unreachable("Unexpected instr type to insert");
3785 case ARM::ATOMIC_LOAD_ADD_I8:
3786 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
3787 case ARM::ATOMIC_LOAD_ADD_I16:
3788 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
3789 case ARM::ATOMIC_LOAD_ADD_I32:
3790 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
3792 case ARM::ATOMIC_LOAD_AND_I8:
3793 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
3794 case ARM::ATOMIC_LOAD_AND_I16:
3795 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
3796 case ARM::ATOMIC_LOAD_AND_I32:
3797 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
3799 case ARM::ATOMIC_LOAD_OR_I8:
3800 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
3801 case ARM::ATOMIC_LOAD_OR_I16:
3802 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
3803 case ARM::ATOMIC_LOAD_OR_I32:
3804 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
3806 case ARM::ATOMIC_LOAD_XOR_I8:
3807 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
3808 case ARM::ATOMIC_LOAD_XOR_I16:
3809 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
3810 case ARM::ATOMIC_LOAD_XOR_I32:
3811 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
3813 case ARM::ATOMIC_LOAD_NAND_I8:
3814 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
3815 case ARM::ATOMIC_LOAD_NAND_I16:
3816 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
3817 case ARM::ATOMIC_LOAD_NAND_I32:
3818 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
3820 case ARM::ATOMIC_LOAD_SUB_I8:
3821 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
3822 case ARM::ATOMIC_LOAD_SUB_I16:
3823 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
3824 case ARM::ATOMIC_LOAD_SUB_I32:
3825 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
3827 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0);
3828 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0);
3829 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0);
3831 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1);
3832 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
3833 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
3835 case ARM::tMOVCCr_pseudo: {
3836 // To "insert" a SELECT_CC instruction, we actually have to insert the
3837 // diamond control-flow pattern. The incoming instruction knows the
3838 // destination vreg to set, the condition code register to branch on, the
3839 // true/false values to select between, and a branch opcode to use.
3840 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3841 MachineFunction::iterator It = BB;
3847 // cmpTY ccX, r1, r2
3849 // fallthrough --> copy0MBB
3850 MachineBasicBlock *thisMBB = BB;
3851 MachineFunction *F = BB->getParent();
3852 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
3853 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
3854 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
3855 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
3856 F->insert(It, copy0MBB);
3857 F->insert(It, sinkMBB);
3858 // Update machine-CFG edges by first adding all successors of the current
3859 // block to the new block which will contain the Phi node for the select.
3860 for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
3861 E = BB->succ_end(); I != E; ++I)
3862 sinkMBB->addSuccessor(*I);
3863 // Next, remove all successors of the current block, and add the true
3864 // and fallthrough blocks as its successors.
3865 while (!BB->succ_empty())
3866 BB->removeSuccessor(BB->succ_begin());
3867 BB->addSuccessor(copy0MBB);
3868 BB->addSuccessor(sinkMBB);
3871 // %FalseValue = ...
3872 // # fallthrough to sinkMBB
3875 // Update machine-CFG edges
3876 BB->addSuccessor(sinkMBB);
3879 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
3882 BuildMI(BB, dl, TII->get(ARM::PHI), MI->getOperand(0).getReg())
3883 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
3884 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
3886 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
3893 case ARM::t2SUBrSPi_:
3894 case ARM::t2SUBrSPi12_:
3895 case ARM::t2SUBrSPs_: {
3896 MachineFunction *MF = BB->getParent();
3897 unsigned DstReg = MI->getOperand(0).getReg();
3898 unsigned SrcReg = MI->getOperand(1).getReg();
3899 bool DstIsDead = MI->getOperand(0).isDead();
3900 bool SrcIsKill = MI->getOperand(1).isKill();
3902 if (SrcReg != ARM::SP) {
3903 // Copy the source to SP from virtual register.
3904 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(SrcReg);
3905 unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
3906 ? ARM::tMOVtgpr2gpr : ARM::tMOVgpr2gpr;
3907 BuildMI(BB, dl, TII->get(CopyOpc), ARM::SP)
3908 .addReg(SrcReg, getKillRegState(SrcIsKill));
3912 bool NeedPred = false, NeedCC = false, NeedOp3 = false;
3913 switch (MI->getOpcode()) {
3915 llvm_unreachable("Unexpected pseudo instruction!");
3921 OpOpc = ARM::tADDspr;
3924 OpOpc = ARM::tSUBspi;
3926 case ARM::t2SUBrSPi_:
3927 OpOpc = ARM::t2SUBrSPi;
3928 NeedPred = true; NeedCC = true;
3930 case ARM::t2SUBrSPi12_:
3931 OpOpc = ARM::t2SUBrSPi12;
3934 case ARM::t2SUBrSPs_:
3935 OpOpc = ARM::t2SUBrSPs;
3936 NeedPred = true; NeedCC = true; NeedOp3 = true;
3939 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(OpOpc), ARM::SP);
3940 if (OpOpc == ARM::tAND)
3941 AddDefaultT1CC(MIB);
3942 MIB.addReg(ARM::SP);
3943 MIB.addOperand(MI->getOperand(2));
3945 MIB.addOperand(MI->getOperand(3));
3947 AddDefaultPred(MIB);
3951 // Copy the result from SP to virtual register.
3952 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(DstReg);
3953 unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
3954 ? ARM::tMOVgpr2tgpr : ARM::tMOVgpr2gpr;
3955 BuildMI(BB, dl, TII->get(CopyOpc))
3956 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead))
3958 MF->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
3964 //===----------------------------------------------------------------------===//
3965 // ARM Optimization Hooks
3966 //===----------------------------------------------------------------------===//
3969 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
3970 TargetLowering::DAGCombinerInfo &DCI) {
3971 SelectionDAG &DAG = DCI.DAG;
3972 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3973 EVT VT = N->getValueType(0);
3974 unsigned Opc = N->getOpcode();
3975 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
3976 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
3977 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
3978 ISD::CondCode CC = ISD::SETCC_INVALID;
3981 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
3983 SDValue CCOp = Slct.getOperand(0);
3984 if (CCOp.getOpcode() == ISD::SETCC)
3985 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
3988 bool DoXform = false;
3990 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
3993 if (LHS.getOpcode() == ISD::Constant &&
3994 cast<ConstantSDNode>(LHS)->isNullValue()) {
3996 } else if (CC != ISD::SETCC_INVALID &&
3997 RHS.getOpcode() == ISD::Constant &&
3998 cast<ConstantSDNode>(RHS)->isNullValue()) {
3999 std::swap(LHS, RHS);
4000 SDValue Op0 = Slct.getOperand(0);
4001 EVT OpVT = isSlctCC ? Op0.getValueType() :
4002 Op0.getOperand(0).getValueType();
4003 bool isInt = OpVT.isInteger();
4004 CC = ISD::getSetCCInverse(CC, isInt);
4006 if (!TLI.isCondCodeLegal(CC, OpVT))
4007 return SDValue(); // Inverse operator isn't legal.
4014 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
4016 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
4017 Slct.getOperand(0), Slct.getOperand(1), CC);
4018 SDValue CCOp = Slct.getOperand(0);
4020 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
4021 CCOp.getOperand(0), CCOp.getOperand(1), CC);
4022 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
4023 CCOp, OtherOp, Result);
4028 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
4029 static SDValue PerformADDCombine(SDNode *N,
4030 TargetLowering::DAGCombinerInfo &DCI) {
4031 // added by evan in r37685 with no testcase.
4032 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
4034 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
4035 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
4036 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
4037 if (Result.getNode()) return Result;
4039 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
4040 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
4041 if (Result.getNode()) return Result;
4047 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
4048 static SDValue PerformSUBCombine(SDNode *N,
4049 TargetLowering::DAGCombinerInfo &DCI) {
4050 // added by evan in r37685 with no testcase.
4051 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
4053 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
4054 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
4055 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
4056 if (Result.getNode()) return Result;
4062 static SDValue PerformMULCombine(SDNode *N,
4063 TargetLowering::DAGCombinerInfo &DCI,
4064 const ARMSubtarget *Subtarget) {
4065 SelectionDAG &DAG = DCI.DAG;
4067 if (Subtarget->isThumb1Only())
4070 if (DAG.getMachineFunction().
4071 getFunction()->hasFnAttr(Attribute::OptimizeForSize))
4074 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
4077 EVT VT = N->getValueType(0);
4081 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
4085 uint64_t MulAmt = C->getZExtValue();
4086 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt);
4087 ShiftAmt = ShiftAmt & (32 - 1);
4088 SDValue V = N->getOperand(0);
4089 DebugLoc DL = N->getDebugLoc();
4092 MulAmt >>= ShiftAmt;
4093 if (isPowerOf2_32(MulAmt - 1)) {
4094 // (mul x, 2^N + 1) => (add (shl x, N), x)
4095 Res = DAG.getNode(ISD::ADD, DL, VT,
4096 V, DAG.getNode(ISD::SHL, DL, VT,
4097 V, DAG.getConstant(Log2_32(MulAmt-1),
4099 } else if (isPowerOf2_32(MulAmt + 1)) {
4100 // (mul x, 2^N - 1) => (sub (shl x, N), x)
4101 Res = DAG.getNode(ISD::SUB, DL, VT,
4102 DAG.getNode(ISD::SHL, DL, VT,
4103 V, DAG.getConstant(Log2_32(MulAmt+1),
4110 Res = DAG.getNode(ISD::SHL, DL, VT, Res,
4111 DAG.getConstant(ShiftAmt, MVT::i32));
4113 // Do not add new nodes to DAG combiner worklist.
4114 DCI.CombineTo(N, Res, false);
4118 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
4119 /// ARMISD::VMOVRRD.
4120 static SDValue PerformVMOVRRDCombine(SDNode *N,
4121 TargetLowering::DAGCombinerInfo &DCI) {
4122 // fmrrd(fmdrr x, y) -> x,y
4123 SDValue InDouble = N->getOperand(0);
4124 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
4125 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
4129 /// getVShiftImm - Check if this is a valid build_vector for the immediate
4130 /// operand of a vector shift operation, where all the elements of the
4131 /// build_vector must have the same constant integer value.
4132 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
4133 // Ignore bit_converts.
4134 while (Op.getOpcode() == ISD::BIT_CONVERT)
4135 Op = Op.getOperand(0);
4136 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
4137 APInt SplatBits, SplatUndef;
4138 unsigned SplatBitSize;
4140 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
4141 HasAnyUndefs, ElementBits) ||
4142 SplatBitSize > ElementBits)
4144 Cnt = SplatBits.getSExtValue();
4148 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
4149 /// operand of a vector shift left operation. That value must be in the range:
4150 /// 0 <= Value < ElementBits for a left shift; or
4151 /// 0 <= Value <= ElementBits for a long left shift.
4152 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
4153 assert(VT.isVector() && "vector shift count is not a vector type");
4154 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
4155 if (! getVShiftImm(Op, ElementBits, Cnt))
4157 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
4160 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
4161 /// operand of a vector shift right operation. For a shift opcode, the value
4162 /// is positive, but for an intrinsic the value count must be negative. The
4163 /// absolute value must be in the range:
4164 /// 1 <= |Value| <= ElementBits for a right shift; or
4165 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
4166 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
4168 assert(VT.isVector() && "vector shift count is not a vector type");
4169 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
4170 if (! getVShiftImm(Op, ElementBits, Cnt))
4174 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
4177 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
4178 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
4179 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
4182 // Don't do anything for most intrinsics.
4185 // Vector shifts: check for immediate versions and lower them.
4186 // Note: This is done during DAG combining instead of DAG legalizing because
4187 // the build_vectors for 64-bit vector element shift counts are generally
4188 // not legal, and it is hard to see their values after they get legalized to
4189 // loads from a constant pool.
4190 case Intrinsic::arm_neon_vshifts:
4191 case Intrinsic::arm_neon_vshiftu:
4192 case Intrinsic::arm_neon_vshiftls:
4193 case Intrinsic::arm_neon_vshiftlu:
4194 case Intrinsic::arm_neon_vshiftn:
4195 case Intrinsic::arm_neon_vrshifts:
4196 case Intrinsic::arm_neon_vrshiftu:
4197 case Intrinsic::arm_neon_vrshiftn:
4198 case Intrinsic::arm_neon_vqshifts:
4199 case Intrinsic::arm_neon_vqshiftu:
4200 case Intrinsic::arm_neon_vqshiftsu:
4201 case Intrinsic::arm_neon_vqshiftns:
4202 case Intrinsic::arm_neon_vqshiftnu:
4203 case Intrinsic::arm_neon_vqshiftnsu:
4204 case Intrinsic::arm_neon_vqrshiftns:
4205 case Intrinsic::arm_neon_vqrshiftnu:
4206 case Intrinsic::arm_neon_vqrshiftnsu: {
4207 EVT VT = N->getOperand(1).getValueType();
4209 unsigned VShiftOpc = 0;
4212 case Intrinsic::arm_neon_vshifts:
4213 case Intrinsic::arm_neon_vshiftu:
4214 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
4215 VShiftOpc = ARMISD::VSHL;
4218 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
4219 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
4220 ARMISD::VSHRs : ARMISD::VSHRu);
4225 case Intrinsic::arm_neon_vshiftls:
4226 case Intrinsic::arm_neon_vshiftlu:
4227 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
4229 llvm_unreachable("invalid shift count for vshll intrinsic");
4231 case Intrinsic::arm_neon_vrshifts:
4232 case Intrinsic::arm_neon_vrshiftu:
4233 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
4237 case Intrinsic::arm_neon_vqshifts:
4238 case Intrinsic::arm_neon_vqshiftu:
4239 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
4243 case Intrinsic::arm_neon_vqshiftsu:
4244 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
4246 llvm_unreachable("invalid shift count for vqshlu intrinsic");
4248 case Intrinsic::arm_neon_vshiftn:
4249 case Intrinsic::arm_neon_vrshiftn:
4250 case Intrinsic::arm_neon_vqshiftns:
4251 case Intrinsic::arm_neon_vqshiftnu:
4252 case Intrinsic::arm_neon_vqshiftnsu:
4253 case Intrinsic::arm_neon_vqrshiftns:
4254 case Intrinsic::arm_neon_vqrshiftnu:
4255 case Intrinsic::arm_neon_vqrshiftnsu:
4256 // Narrowing shifts require an immediate right shift.
4257 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
4259 llvm_unreachable("invalid shift count for narrowing vector shift "
4263 llvm_unreachable("unhandled vector shift");
4267 case Intrinsic::arm_neon_vshifts:
4268 case Intrinsic::arm_neon_vshiftu:
4269 // Opcode already set above.
4271 case Intrinsic::arm_neon_vshiftls:
4272 case Intrinsic::arm_neon_vshiftlu:
4273 if (Cnt == VT.getVectorElementType().getSizeInBits())
4274 VShiftOpc = ARMISD::VSHLLi;
4276 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
4277 ARMISD::VSHLLs : ARMISD::VSHLLu);
4279 case Intrinsic::arm_neon_vshiftn:
4280 VShiftOpc = ARMISD::VSHRN; break;
4281 case Intrinsic::arm_neon_vrshifts:
4282 VShiftOpc = ARMISD::VRSHRs; break;
4283 case Intrinsic::arm_neon_vrshiftu:
4284 VShiftOpc = ARMISD::VRSHRu; break;
4285 case Intrinsic::arm_neon_vrshiftn:
4286 VShiftOpc = ARMISD::VRSHRN; break;
4287 case Intrinsic::arm_neon_vqshifts:
4288 VShiftOpc = ARMISD::VQSHLs; break;
4289 case Intrinsic::arm_neon_vqshiftu:
4290 VShiftOpc = ARMISD::VQSHLu; break;
4291 case Intrinsic::arm_neon_vqshiftsu:
4292 VShiftOpc = ARMISD::VQSHLsu; break;
4293 case Intrinsic::arm_neon_vqshiftns:
4294 VShiftOpc = ARMISD::VQSHRNs; break;
4295 case Intrinsic::arm_neon_vqshiftnu:
4296 VShiftOpc = ARMISD::VQSHRNu; break;
4297 case Intrinsic::arm_neon_vqshiftnsu:
4298 VShiftOpc = ARMISD::VQSHRNsu; break;
4299 case Intrinsic::arm_neon_vqrshiftns:
4300 VShiftOpc = ARMISD::VQRSHRNs; break;
4301 case Intrinsic::arm_neon_vqrshiftnu:
4302 VShiftOpc = ARMISD::VQRSHRNu; break;
4303 case Intrinsic::arm_neon_vqrshiftnsu:
4304 VShiftOpc = ARMISD::VQRSHRNsu; break;
4307 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
4308 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
4311 case Intrinsic::arm_neon_vshiftins: {
4312 EVT VT = N->getOperand(1).getValueType();
4314 unsigned VShiftOpc = 0;
4316 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
4317 VShiftOpc = ARMISD::VSLI;
4318 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
4319 VShiftOpc = ARMISD::VSRI;
4321 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
4324 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
4325 N->getOperand(1), N->getOperand(2),
4326 DAG.getConstant(Cnt, MVT::i32));
4329 case Intrinsic::arm_neon_vqrshifts:
4330 case Intrinsic::arm_neon_vqrshiftu:
4331 // No immediate versions of these to check for.
4338 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
4339 /// lowers them. As with the vector shift intrinsics, this is done during DAG
4340 /// combining instead of DAG legalizing because the build_vectors for 64-bit
4341 /// vector element shift counts are generally not legal, and it is hard to see
4342 /// their values after they get legalized to loads from a constant pool.
4343 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
4344 const ARMSubtarget *ST) {
4345 EVT VT = N->getValueType(0);
4347 // Nothing to be done for scalar shifts.
4348 if (! VT.isVector())
4351 assert(ST->hasNEON() && "unexpected vector shift");
4354 switch (N->getOpcode()) {
4355 default: llvm_unreachable("unexpected shift opcode");
4358 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
4359 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
4360 DAG.getConstant(Cnt, MVT::i32));
4365 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
4366 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
4367 ARMISD::VSHRs : ARMISD::VSHRu);
4368 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
4369 DAG.getConstant(Cnt, MVT::i32));
4375 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
4376 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
4377 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
4378 const ARMSubtarget *ST) {
4379 SDValue N0 = N->getOperand(0);
4381 // Check for sign- and zero-extensions of vector extract operations of 8-
4382 // and 16-bit vector elements. NEON supports these directly. They are
4383 // handled during DAG combining because type legalization will promote them
4384 // to 32-bit types and it is messy to recognize the operations after that.
4385 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
4386 SDValue Vec = N0.getOperand(0);
4387 SDValue Lane = N0.getOperand(1);
4388 EVT VT = N->getValueType(0);
4389 EVT EltVT = N0.getValueType();
4390 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4392 if (VT == MVT::i32 &&
4393 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
4394 TLI.isTypeLegal(Vec.getValueType())) {
4397 switch (N->getOpcode()) {
4398 default: llvm_unreachable("unexpected opcode");
4399 case ISD::SIGN_EXTEND:
4400 Opc = ARMISD::VGETLANEs;
4402 case ISD::ZERO_EXTEND:
4403 case ISD::ANY_EXTEND:
4404 Opc = ARMISD::VGETLANEu;
4407 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
4414 /// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
4415 /// to match f32 max/min patterns to use NEON vmax/vmin instructions.
4416 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
4417 const ARMSubtarget *ST) {
4418 // If the target supports NEON, try to use vmax/vmin instructions for f32
4419 // selects like "x < y ? x : y". Unless the FiniteOnlyFPMath option is set,
4420 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
4421 // a NaN; only do the transformation when it matches that behavior.
4423 // For now only do this when using NEON for FP operations; if using VFP, it
4424 // is not obvious that the benefit outweighs the cost of switching to the
4426 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
4427 N->getValueType(0) != MVT::f32)
4430 SDValue CondLHS = N->getOperand(0);
4431 SDValue CondRHS = N->getOperand(1);
4432 SDValue LHS = N->getOperand(2);
4433 SDValue RHS = N->getOperand(3);
4434 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
4436 unsigned Opcode = 0;
4438 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
4439 IsReversed = false; // x CC y ? x : y
4440 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
4441 IsReversed = true ; // x CC y ? y : x
4455 // If LHS is NaN, an ordered comparison will be false and the result will
4456 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
4457 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
4458 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
4459 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
4461 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
4462 // will return -0, so vmin can only be used for unsafe math or if one of
4463 // the operands is known to be nonzero.
4464 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
4466 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
4468 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
4477 // If LHS is NaN, an ordered comparison will be false and the result will
4478 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
4479 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
4480 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
4481 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
4483 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
4484 // will return +0, so vmax can only be used for unsafe math or if one of
4485 // the operands is known to be nonzero.
4486 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
4488 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
4490 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
4496 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS);
4499 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
4500 DAGCombinerInfo &DCI) const {
4501 switch (N->getOpcode()) {
4503 case ISD::ADD: return PerformADDCombine(N, DCI);
4504 case ISD::SUB: return PerformSUBCombine(N, DCI);
4505 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
4506 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
4507 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
4510 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
4511 case ISD::SIGN_EXTEND:
4512 case ISD::ZERO_EXTEND:
4513 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
4514 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
4519 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
4520 if (!Subtarget->hasV6Ops())
4521 // Pre-v6 does not support unaligned mem access.
4524 // v6+ may or may not support unaligned mem access depending on the system
4526 // FIXME: This is pretty conservative. Should we provide cmdline option to
4527 // control the behaviour?
4528 if (!Subtarget->isTargetDarwin())
4531 switch (VT.getSimpleVT().SimpleTy) {
4538 // FIXME: VLD1 etc with standard alignment is legal.
4542 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
4547 switch (VT.getSimpleVT().SimpleTy) {
4548 default: return false;
4563 if ((V & (Scale - 1)) != 0)
4566 return V == (V & ((1LL << 5) - 1));
4569 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
4570 const ARMSubtarget *Subtarget) {
4577 switch (VT.getSimpleVT().SimpleTy) {
4578 default: return false;
4583 // + imm12 or - imm8
4585 return V == (V & ((1LL << 8) - 1));
4586 return V == (V & ((1LL << 12) - 1));
4589 // Same as ARM mode. FIXME: NEON?
4590 if (!Subtarget->hasVFP2())
4595 return V == (V & ((1LL << 8) - 1));
4599 /// isLegalAddressImmediate - Return true if the integer value can be used
4600 /// as the offset of the target addressing mode for load / store of the
4602 static bool isLegalAddressImmediate(int64_t V, EVT VT,
4603 const ARMSubtarget *Subtarget) {
4610 if (Subtarget->isThumb1Only())
4611 return isLegalT1AddressImmediate(V, VT);
4612 else if (Subtarget->isThumb2())
4613 return isLegalT2AddressImmediate(V, VT, Subtarget);
4618 switch (VT.getSimpleVT().SimpleTy) {
4619 default: return false;
4624 return V == (V & ((1LL << 12) - 1));
4627 return V == (V & ((1LL << 8) - 1));
4630 if (!Subtarget->hasVFP2()) // FIXME: NEON?
4635 return V == (V & ((1LL << 8) - 1));
4639 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
4641 int Scale = AM.Scale;
4645 switch (VT.getSimpleVT().SimpleTy) {
4646 default: return false;
4655 return Scale == 2 || Scale == 4 || Scale == 8;
4658 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
4662 // Note, we allow "void" uses (basically, uses that aren't loads or
4663 // stores), because arm allows folding a scale into many arithmetic
4664 // operations. This should be made more precise and revisited later.
4666 // Allow r << imm, but the imm has to be a multiple of two.
4667 if (Scale & 1) return false;
4668 return isPowerOf2_32(Scale);
4672 /// isLegalAddressingMode - Return true if the addressing mode represented
4673 /// by AM is legal for this target, for a load/store of the specified type.
4674 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
4675 const Type *Ty) const {
4676 EVT VT = getValueType(Ty, true);
4677 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
4680 // Can never fold addr of global into load/store.
4685 case 0: // no scale reg, must be "r+i" or "r", or "i".
4688 if (Subtarget->isThumb1Only())
4692 // ARM doesn't support any R+R*scale+imm addr modes.
4699 if (Subtarget->isThumb2())
4700 return isLegalT2ScaledAddressingMode(AM, VT);
4702 int Scale = AM.Scale;
4703 switch (VT.getSimpleVT().SimpleTy) {
4704 default: return false;
4708 if (Scale < 0) Scale = -Scale;
4712 return isPowerOf2_32(Scale & ~1);
4716 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
4721 // Note, we allow "void" uses (basically, uses that aren't loads or
4722 // stores), because arm allows folding a scale into many arithmetic
4723 // operations. This should be made more precise and revisited later.
4725 // Allow r << imm, but the imm has to be a multiple of two.
4726 if (Scale & 1) return false;
4727 return isPowerOf2_32(Scale);
4734 /// isLegalICmpImmediate - Return true if the specified immediate is legal
4735 /// icmp immediate, that is the target has icmp instructions which can compare
4736 /// a register against the immediate without having to materialize the
4737 /// immediate into a register.
4738 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
4739 if (!Subtarget->isThumb())
4740 return ARM_AM::getSOImmVal(Imm) != -1;
4741 if (Subtarget->isThumb2())
4742 return ARM_AM::getT2SOImmVal(Imm) != -1;
4743 return Imm >= 0 && Imm <= 255;
4746 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
4747 bool isSEXTLoad, SDValue &Base,
4748 SDValue &Offset, bool &isInc,
4749 SelectionDAG &DAG) {
4750 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
4753 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
4755 Base = Ptr->getOperand(0);
4756 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
4757 int RHSC = (int)RHS->getZExtValue();
4758 if (RHSC < 0 && RHSC > -256) {
4759 assert(Ptr->getOpcode() == ISD::ADD);
4761 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
4765 isInc = (Ptr->getOpcode() == ISD::ADD);
4766 Offset = Ptr->getOperand(1);
4768 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
4770 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
4771 int RHSC = (int)RHS->getZExtValue();
4772 if (RHSC < 0 && RHSC > -0x1000) {
4773 assert(Ptr->getOpcode() == ISD::ADD);
4775 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
4776 Base = Ptr->getOperand(0);
4781 if (Ptr->getOpcode() == ISD::ADD) {
4783 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
4784 if (ShOpcVal != ARM_AM::no_shift) {
4785 Base = Ptr->getOperand(1);
4786 Offset = Ptr->getOperand(0);
4788 Base = Ptr->getOperand(0);
4789 Offset = Ptr->getOperand(1);
4794 isInc = (Ptr->getOpcode() == ISD::ADD);
4795 Base = Ptr->getOperand(0);
4796 Offset = Ptr->getOperand(1);
4800 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
4804 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
4805 bool isSEXTLoad, SDValue &Base,
4806 SDValue &Offset, bool &isInc,
4807 SelectionDAG &DAG) {
4808 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
4811 Base = Ptr->getOperand(0);
4812 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
4813 int RHSC = (int)RHS->getZExtValue();
4814 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
4815 assert(Ptr->getOpcode() == ISD::ADD);
4817 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
4819 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
4820 isInc = Ptr->getOpcode() == ISD::ADD;
4821 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
4829 /// getPreIndexedAddressParts - returns true by value, base pointer and
4830 /// offset pointer and addressing mode by reference if the node's address
4831 /// can be legally represented as pre-indexed load / store address.
4833 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
4835 ISD::MemIndexedMode &AM,
4836 SelectionDAG &DAG) const {
4837 if (Subtarget->isThumb1Only())
4842 bool isSEXTLoad = false;
4843 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4844 Ptr = LD->getBasePtr();
4845 VT = LD->getMemoryVT();
4846 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
4847 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4848 Ptr = ST->getBasePtr();
4849 VT = ST->getMemoryVT();
4854 bool isLegal = false;
4855 if (Subtarget->isThumb2())
4856 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
4857 Offset, isInc, DAG);
4859 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
4860 Offset, isInc, DAG);
4864 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
4868 /// getPostIndexedAddressParts - returns true by value, base pointer and
4869 /// offset pointer and addressing mode by reference if this node can be
4870 /// combined with a load / store to form a post-indexed load / store.
4871 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
4874 ISD::MemIndexedMode &AM,
4875 SelectionDAG &DAG) const {
4876 if (Subtarget->isThumb1Only())
4881 bool isSEXTLoad = false;
4882 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
4883 VT = LD->getMemoryVT();
4884 Ptr = LD->getBasePtr();
4885 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
4886 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
4887 VT = ST->getMemoryVT();
4888 Ptr = ST->getBasePtr();
4893 bool isLegal = false;
4894 if (Subtarget->isThumb2())
4895 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
4898 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
4904 // Swap base ptr and offset to catch more post-index load / store when
4905 // it's legal. In Thumb2 mode, offset must be an immediate.
4906 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
4907 !Subtarget->isThumb2())
4908 std::swap(Base, Offset);
4910 // Post-indexed load / store update the base pointer.
4915 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
4919 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
4923 const SelectionDAG &DAG,
4924 unsigned Depth) const {
4925 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
4926 switch (Op.getOpcode()) {
4928 case ARMISD::CMOV: {
4929 // Bits are known zero/one if known on the LHS and RHS.
4930 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
4931 if (KnownZero == 0 && KnownOne == 0) return;
4933 APInt KnownZeroRHS, KnownOneRHS;
4934 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
4935 KnownZeroRHS, KnownOneRHS, Depth+1);
4936 KnownZero &= KnownZeroRHS;
4937 KnownOne &= KnownOneRHS;
4943 //===----------------------------------------------------------------------===//
4944 // ARM Inline Assembly Support
4945 //===----------------------------------------------------------------------===//
4947 /// getConstraintType - Given a constraint letter, return the type of
4948 /// constraint it is for this target.
4949 ARMTargetLowering::ConstraintType
4950 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
4951 if (Constraint.size() == 1) {
4952 switch (Constraint[0]) {
4954 case 'l': return C_RegisterClass;
4955 case 'w': return C_RegisterClass;
4958 return TargetLowering::getConstraintType(Constraint);
4961 std::pair<unsigned, const TargetRegisterClass*>
4962 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
4964 if (Constraint.size() == 1) {
4965 // GCC ARM Constraint Letters
4966 switch (Constraint[0]) {
4968 if (Subtarget->isThumb())
4969 return std::make_pair(0U, ARM::tGPRRegisterClass);
4971 return std::make_pair(0U, ARM::GPRRegisterClass);
4973 return std::make_pair(0U, ARM::GPRRegisterClass);
4976 return std::make_pair(0U, ARM::SPRRegisterClass);
4977 if (VT.getSizeInBits() == 64)
4978 return std::make_pair(0U, ARM::DPRRegisterClass);
4979 if (VT.getSizeInBits() == 128)
4980 return std::make_pair(0U, ARM::QPRRegisterClass);
4984 if (StringRef("{cc}").equals_lower(Constraint))
4985 return std::make_pair(unsigned(ARM::CPSR), ARM::CCRRegisterClass);
4987 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
4990 std::vector<unsigned> ARMTargetLowering::
4991 getRegClassForInlineAsmConstraint(const std::string &Constraint,
4993 if (Constraint.size() != 1)
4994 return std::vector<unsigned>();
4996 switch (Constraint[0]) { // GCC ARM Constraint Letters
4999 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
5000 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
5003 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
5004 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
5005 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
5006 ARM::R12, ARM::LR, 0);
5009 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
5010 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
5011 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
5012 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
5013 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
5014 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
5015 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
5016 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
5017 if (VT.getSizeInBits() == 64)
5018 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
5019 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
5020 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
5021 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
5022 if (VT.getSizeInBits() == 128)
5023 return make_vector<unsigned>(ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
5024 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 0);
5028 return std::vector<unsigned>();
5031 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
5032 /// vector. If it is invalid, don't add anything to Ops.
5033 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
5035 std::vector<SDValue>&Ops,
5036 SelectionDAG &DAG) const {
5037 SDValue Result(0, 0);
5039 switch (Constraint) {
5041 case 'I': case 'J': case 'K': case 'L':
5042 case 'M': case 'N': case 'O':
5043 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
5047 int64_t CVal64 = C->getSExtValue();
5048 int CVal = (int) CVal64;
5049 // None of these constraints allow values larger than 32 bits. Check
5050 // that the value fits in an int.
5054 switch (Constraint) {
5056 if (Subtarget->isThumb1Only()) {
5057 // This must be a constant between 0 and 255, for ADD
5059 if (CVal >= 0 && CVal <= 255)
5061 } else if (Subtarget->isThumb2()) {
5062 // A constant that can be used as an immediate value in a
5063 // data-processing instruction.
5064 if (ARM_AM::getT2SOImmVal(CVal) != -1)
5067 // A constant that can be used as an immediate value in a
5068 // data-processing instruction.
5069 if (ARM_AM::getSOImmVal(CVal) != -1)
5075 if (Subtarget->isThumb()) { // FIXME thumb2
5076 // This must be a constant between -255 and -1, for negated ADD
5077 // immediates. This can be used in GCC with an "n" modifier that
5078 // prints the negated value, for use with SUB instructions. It is
5079 // not useful otherwise but is implemented for compatibility.
5080 if (CVal >= -255 && CVal <= -1)
5083 // This must be a constant between -4095 and 4095. It is not clear
5084 // what this constraint is intended for. Implemented for
5085 // compatibility with GCC.
5086 if (CVal >= -4095 && CVal <= 4095)
5092 if (Subtarget->isThumb1Only()) {
5093 // A 32-bit value where only one byte has a nonzero value. Exclude
5094 // zero to match GCC. This constraint is used by GCC internally for
5095 // constants that can be loaded with a move/shift combination.
5096 // It is not useful otherwise but is implemented for compatibility.
5097 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
5099 } else if (Subtarget->isThumb2()) {
5100 // A constant whose bitwise inverse can be used as an immediate
5101 // value in a data-processing instruction. This can be used in GCC
5102 // with a "B" modifier that prints the inverted value, for use with
5103 // BIC and MVN instructions. It is not useful otherwise but is
5104 // implemented for compatibility.
5105 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
5108 // A constant whose bitwise inverse can be used as an immediate
5109 // value in a data-processing instruction. This can be used in GCC
5110 // with a "B" modifier that prints the inverted value, for use with
5111 // BIC and MVN instructions. It is not useful otherwise but is
5112 // implemented for compatibility.
5113 if (ARM_AM::getSOImmVal(~CVal) != -1)
5119 if (Subtarget->isThumb1Only()) {
5120 // This must be a constant between -7 and 7,
5121 // for 3-operand ADD/SUB immediate instructions.
5122 if (CVal >= -7 && CVal < 7)
5124 } else if (Subtarget->isThumb2()) {
5125 // A constant whose negation can be used as an immediate value in a
5126 // data-processing instruction. This can be used in GCC with an "n"
5127 // modifier that prints the negated value, for use with SUB
5128 // instructions. It is not useful otherwise but is implemented for
5130 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
5133 // A constant whose negation can be used as an immediate value in a
5134 // data-processing instruction. This can be used in GCC with an "n"
5135 // modifier that prints the negated value, for use with SUB
5136 // instructions. It is not useful otherwise but is implemented for
5138 if (ARM_AM::getSOImmVal(-CVal) != -1)
5144 if (Subtarget->isThumb()) { // FIXME thumb2
5145 // This must be a multiple of 4 between 0 and 1020, for
5146 // ADD sp + immediate.
5147 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
5150 // A power of two or a constant between 0 and 32. This is used in
5151 // GCC for the shift amount on shifted register operands, but it is
5152 // useful in general for any shift amounts.
5153 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
5159 if (Subtarget->isThumb()) { // FIXME thumb2
5160 // This must be a constant between 0 and 31, for shift amounts.
5161 if (CVal >= 0 && CVal <= 31)
5167 if (Subtarget->isThumb()) { // FIXME thumb2
5168 // This must be a multiple of 4 between -508 and 508, for
5169 // ADD/SUB sp = sp + immediate.
5170 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
5175 Result = DAG.getTargetConstant(CVal, Op.getValueType());
5179 if (Result.getNode()) {
5180 Ops.push_back(Result);
5183 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
5187 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
5188 // The ARM target isn't yet aware of offsets.
5192 int ARM::getVFPf32Imm(const APFloat &FPImm) {
5193 APInt Imm = FPImm.bitcastToAPInt();
5194 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
5195 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127
5196 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits
5198 // We can handle 4 bits of mantissa.
5199 // mantissa = (16+UInt(e:f:g:h))/16.
5200 if (Mantissa & 0x7ffff)
5203 if ((Mantissa & 0xf) != Mantissa)
5206 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
5207 if (Exp < -3 || Exp > 4)
5209 Exp = ((Exp+3) & 0x7) ^ 4;
5211 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
5214 int ARM::getVFPf64Imm(const APFloat &FPImm) {
5215 APInt Imm = FPImm.bitcastToAPInt();
5216 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
5217 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
5218 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffLL;
5220 // We can handle 4 bits of mantissa.
5221 // mantissa = (16+UInt(e:f:g:h))/16.
5222 if (Mantissa & 0xffffffffffffLL)
5225 if ((Mantissa & 0xf) != Mantissa)
5228 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
5229 if (Exp < -3 || Exp > 4)
5231 Exp = ((Exp+3) & 0x7) ^ 4;
5233 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
5236 /// isFPImmLegal - Returns true if the target can instruction select the
5237 /// specified FP immediate natively. If false, the legalizer will
5238 /// materialize the FP immediate as a load from a constant pool.
5239 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
5240 if (!Subtarget->hasVFP3())
5243 return ARM::getVFPf32Imm(Imm) != -1;
5245 return ARM::getVFPf64Imm(Imm) != -1;