1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #include "ARMISelLowering.h"
16 #include "ARMCallingConv.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMPerfectShuffle.h"
20 #include "ARMSubtarget.h"
21 #include "ARMTargetMachine.h"
22 #include "ARMTargetObjectFile.h"
23 #include "MCTargetDesc/ARMAddressingModes.h"
24 #include "llvm/ADT/Statistic.h"
25 #include "llvm/ADT/StringExtras.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/CodeGen/CallingConvLower.h"
28 #include "llvm/CodeGen/IntrinsicLowering.h"
29 #include "llvm/CodeGen/MachineBasicBlock.h"
30 #include "llvm/CodeGen/MachineFrameInfo.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineInstrBuilder.h"
33 #include "llvm/CodeGen/MachineJumpTableInfo.h"
34 #include "llvm/CodeGen/MachineModuleInfo.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/SelectionDAG.h"
37 #include "llvm/IR/CallingConv.h"
38 #include "llvm/IR/Constants.h"
39 #include "llvm/IR/Function.h"
40 #include "llvm/IR/GlobalValue.h"
41 #include "llvm/IR/IRBuilder.h"
42 #include "llvm/IR/Instruction.h"
43 #include "llvm/IR/Instructions.h"
44 #include "llvm/IR/IntrinsicInst.h"
45 #include "llvm/IR/Intrinsics.h"
46 #include "llvm/IR/Type.h"
47 #include "llvm/MC/MCSectionMachO.h"
48 #include "llvm/Support/CommandLine.h"
49 #include "llvm/Support/Debug.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Support/raw_ostream.h"
53 #include "llvm/Target/TargetOptions.h"
57 #define DEBUG_TYPE "arm-isel"
59 STATISTIC(NumTailCalls, "Number of tail calls");
60 STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt");
61 STATISTIC(NumLoopByVals, "Number of loops generated for byval arguments");
64 ARMInterworking("arm-interworking", cl::Hidden,
65 cl::desc("Enable / disable ARM interworking (for debugging only)"),
69 class ARMCCState : public CCState {
71 ARMCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
72 SmallVectorImpl<CCValAssign> &locs, LLVMContext &C,
74 : CCState(CC, isVarArg, MF, locs, C) {
75 assert(((PC == Call) || (PC == Prologue)) &&
76 "ARMCCState users must specify whether their context is call"
77 "or prologue generation.");
83 // The APCS parameter registers.
84 static const MCPhysReg GPRArgRegs[] = {
85 ARM::R0, ARM::R1, ARM::R2, ARM::R3
88 void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT,
89 MVT PromotedBitwiseVT) {
90 if (VT != PromotedLdStVT) {
91 setOperationAction(ISD::LOAD, VT, Promote);
92 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
94 setOperationAction(ISD::STORE, VT, Promote);
95 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
98 MVT ElemTy = VT.getVectorElementType();
99 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
100 setOperationAction(ISD::SETCC, VT, Custom);
101 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
102 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
103 if (ElemTy == MVT::i32) {
104 setOperationAction(ISD::SINT_TO_FP, VT, Custom);
105 setOperationAction(ISD::UINT_TO_FP, VT, Custom);
106 setOperationAction(ISD::FP_TO_SINT, VT, Custom);
107 setOperationAction(ISD::FP_TO_UINT, VT, Custom);
109 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
110 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
111 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
112 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
114 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
115 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
116 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
117 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
118 setOperationAction(ISD::SELECT, VT, Expand);
119 setOperationAction(ISD::SELECT_CC, VT, Expand);
120 setOperationAction(ISD::VSELECT, VT, Expand);
121 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
122 if (VT.isInteger()) {
123 setOperationAction(ISD::SHL, VT, Custom);
124 setOperationAction(ISD::SRA, VT, Custom);
125 setOperationAction(ISD::SRL, VT, Custom);
128 // Promote all bit-wise operations.
129 if (VT.isInteger() && VT != PromotedBitwiseVT) {
130 setOperationAction(ISD::AND, VT, Promote);
131 AddPromotedToType (ISD::AND, VT, PromotedBitwiseVT);
132 setOperationAction(ISD::OR, VT, Promote);
133 AddPromotedToType (ISD::OR, VT, PromotedBitwiseVT);
134 setOperationAction(ISD::XOR, VT, Promote);
135 AddPromotedToType (ISD::XOR, VT, PromotedBitwiseVT);
138 // Neon does not support vector divide/remainder operations.
139 setOperationAction(ISD::SDIV, VT, Expand);
140 setOperationAction(ISD::UDIV, VT, Expand);
141 setOperationAction(ISD::FDIV, VT, Expand);
142 setOperationAction(ISD::SREM, VT, Expand);
143 setOperationAction(ISD::UREM, VT, Expand);
144 setOperationAction(ISD::FREM, VT, Expand);
146 if (VT.isInteger()) {
147 setOperationAction(ISD::SABSDIFF, VT, Legal);
148 setOperationAction(ISD::UABSDIFF, VT, Legal);
152 void ARMTargetLowering::addDRTypeForNEON(MVT VT) {
153 addRegisterClass(VT, &ARM::DPRRegClass);
154 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
157 void ARMTargetLowering::addQRTypeForNEON(MVT VT) {
158 addRegisterClass(VT, &ARM::DPairRegClass);
159 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
162 ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
163 const ARMSubtarget &STI)
164 : TargetLowering(TM), Subtarget(&STI) {
165 RegInfo = Subtarget->getRegisterInfo();
166 Itins = Subtarget->getInstrItineraryData();
168 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
170 if (Subtarget->isTargetMachO()) {
171 // Uses VFP for Thumb libfuncs if available.
172 if (Subtarget->isThumb() && Subtarget->hasVFP2() &&
173 Subtarget->hasARMOps() && !Subtarget->useSoftFloat()) {
174 // Single-precision floating-point arithmetic.
175 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
176 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
177 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
178 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
180 // Double-precision floating-point arithmetic.
181 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
182 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
183 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
184 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
186 // Single-precision comparisons.
187 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
188 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
189 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
190 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
191 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
192 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
193 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
194 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
196 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
197 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
198 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
199 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
200 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
201 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
202 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
203 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
205 // Double-precision comparisons.
206 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
207 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
208 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
209 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
210 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
211 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
212 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
213 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
215 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
216 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
217 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
218 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
219 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
220 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
221 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
222 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
224 // Floating-point to integer conversions.
225 // i64 conversions are done via library routines even when generating VFP
226 // instructions, so use the same ones.
227 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
228 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
229 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
230 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
232 // Conversions between floating types.
233 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
234 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
236 // Integer to floating-point conversions.
237 // i64 conversions are done via library routines even when generating VFP
238 // instructions, so use the same ones.
239 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
240 // e.g., __floatunsidf vs. __floatunssidfvfp.
241 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
242 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
243 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
244 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
248 // These libcalls are not available in 32-bit.
249 setLibcallName(RTLIB::SHL_I128, nullptr);
250 setLibcallName(RTLIB::SRL_I128, nullptr);
251 setLibcallName(RTLIB::SRA_I128, nullptr);
253 if (Subtarget->isAAPCS_ABI() && !Subtarget->isTargetMachO() &&
254 !Subtarget->isTargetWindows()) {
255 static const struct {
256 const RTLIB::Libcall Op;
257 const char * const Name;
258 const CallingConv::ID CC;
259 const ISD::CondCode Cond;
261 // Double-precision floating-point arithmetic helper functions
262 // RTABI chapter 4.1.2, Table 2
263 { RTLIB::ADD_F64, "__aeabi_dadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
264 { RTLIB::DIV_F64, "__aeabi_ddiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
265 { RTLIB::MUL_F64, "__aeabi_dmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
266 { RTLIB::SUB_F64, "__aeabi_dsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
268 // Double-precision floating-point comparison helper functions
269 // RTABI chapter 4.1.2, Table 3
270 { RTLIB::OEQ_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
271 { RTLIB::UNE_F64, "__aeabi_dcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
272 { RTLIB::OLT_F64, "__aeabi_dcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
273 { RTLIB::OLE_F64, "__aeabi_dcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
274 { RTLIB::OGE_F64, "__aeabi_dcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
275 { RTLIB::OGT_F64, "__aeabi_dcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
276 { RTLIB::UO_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
277 { RTLIB::O_F64, "__aeabi_dcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ },
279 // Single-precision floating-point arithmetic helper functions
280 // RTABI chapter 4.1.2, Table 4
281 { RTLIB::ADD_F32, "__aeabi_fadd", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
282 { RTLIB::DIV_F32, "__aeabi_fdiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
283 { RTLIB::MUL_F32, "__aeabi_fmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
284 { RTLIB::SUB_F32, "__aeabi_fsub", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
286 // Single-precision floating-point comparison helper functions
287 // RTABI chapter 4.1.2, Table 5
288 { RTLIB::OEQ_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETNE },
289 { RTLIB::UNE_F32, "__aeabi_fcmpeq", CallingConv::ARM_AAPCS, ISD::SETEQ },
290 { RTLIB::OLT_F32, "__aeabi_fcmplt", CallingConv::ARM_AAPCS, ISD::SETNE },
291 { RTLIB::OLE_F32, "__aeabi_fcmple", CallingConv::ARM_AAPCS, ISD::SETNE },
292 { RTLIB::OGE_F32, "__aeabi_fcmpge", CallingConv::ARM_AAPCS, ISD::SETNE },
293 { RTLIB::OGT_F32, "__aeabi_fcmpgt", CallingConv::ARM_AAPCS, ISD::SETNE },
294 { RTLIB::UO_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETNE },
295 { RTLIB::O_F32, "__aeabi_fcmpun", CallingConv::ARM_AAPCS, ISD::SETEQ },
297 // Floating-point to integer conversions.
298 // RTABI chapter 4.1.2, Table 6
299 { RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
300 { RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
301 { RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
302 { RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
303 { RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
304 { RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
305 { RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
306 { RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
308 // Conversions between floating types.
309 // RTABI chapter 4.1.2, Table 7
310 { RTLIB::FPROUND_F64_F32, "__aeabi_d2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
311 { RTLIB::FPROUND_F64_F16, "__aeabi_d2h", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
312 { RTLIB::FPEXT_F32_F64, "__aeabi_f2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
314 // Integer to floating-point conversions.
315 // RTABI chapter 4.1.2, Table 8
316 { RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
317 { RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
318 { RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
319 { RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
320 { RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
321 { RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
322 { RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
323 { RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
325 // Long long helper functions
326 // RTABI chapter 4.2, Table 9
327 { RTLIB::MUL_I64, "__aeabi_lmul", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
328 { RTLIB::SHL_I64, "__aeabi_llsl", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
329 { RTLIB::SRL_I64, "__aeabi_llsr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
330 { RTLIB::SRA_I64, "__aeabi_lasr", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
332 // Integer division functions
333 // RTABI chapter 4.3.1
334 { RTLIB::SDIV_I8, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
335 { RTLIB::SDIV_I16, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
336 { RTLIB::SDIV_I32, "__aeabi_idiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
337 { RTLIB::SDIV_I64, "__aeabi_ldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
338 { RTLIB::UDIV_I8, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
339 { RTLIB::UDIV_I16, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
340 { RTLIB::UDIV_I32, "__aeabi_uidiv", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
341 { RTLIB::UDIV_I64, "__aeabi_uldivmod", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
344 // RTABI chapter 4.3.4
345 { RTLIB::MEMCPY, "__aeabi_memcpy", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
346 { RTLIB::MEMMOVE, "__aeabi_memmove", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
347 { RTLIB::MEMSET, "__aeabi_memset", CallingConv::ARM_AAPCS, ISD::SETCC_INVALID },
350 for (const auto &LC : LibraryCalls) {
351 setLibcallName(LC.Op, LC.Name);
352 setLibcallCallingConv(LC.Op, LC.CC);
353 if (LC.Cond != ISD::SETCC_INVALID)
354 setCmpLibcallCC(LC.Op, LC.Cond);
358 if (Subtarget->isTargetWindows()) {
359 static const struct {
360 const RTLIB::Libcall Op;
361 const char * const Name;
362 const CallingConv::ID CC;
364 { RTLIB::FPTOSINT_F32_I64, "__stoi64", CallingConv::ARM_AAPCS_VFP },
365 { RTLIB::FPTOSINT_F64_I64, "__dtoi64", CallingConv::ARM_AAPCS_VFP },
366 { RTLIB::FPTOUINT_F32_I64, "__stou64", CallingConv::ARM_AAPCS_VFP },
367 { RTLIB::FPTOUINT_F64_I64, "__dtou64", CallingConv::ARM_AAPCS_VFP },
368 { RTLIB::SINTTOFP_I64_F32, "__i64tos", CallingConv::ARM_AAPCS_VFP },
369 { RTLIB::SINTTOFP_I64_F64, "__i64tod", CallingConv::ARM_AAPCS_VFP },
370 { RTLIB::UINTTOFP_I64_F32, "__u64tos", CallingConv::ARM_AAPCS_VFP },
371 { RTLIB::UINTTOFP_I64_F64, "__u64tod", CallingConv::ARM_AAPCS_VFP },
374 for (const auto &LC : LibraryCalls) {
375 setLibcallName(LC.Op, LC.Name);
376 setLibcallCallingConv(LC.Op, LC.CC);
380 // Use divmod compiler-rt calls for iOS 5.0 and later.
381 if (Subtarget->getTargetTriple().isiOS() &&
382 !Subtarget->getTargetTriple().isOSVersionLT(5, 0)) {
383 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
384 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
387 // The half <-> float conversion functions are always soft-float, but are
388 // needed for some targets which use a hard-float calling convention by
390 if (Subtarget->isAAPCS_ABI()) {
391 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_AAPCS);
392 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_AAPCS);
393 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_AAPCS);
395 setLibcallCallingConv(RTLIB::FPROUND_F32_F16, CallingConv::ARM_APCS);
396 setLibcallCallingConv(RTLIB::FPROUND_F64_F16, CallingConv::ARM_APCS);
397 setLibcallCallingConv(RTLIB::FPEXT_F16_F32, CallingConv::ARM_APCS);
400 if (Subtarget->isThumb1Only())
401 addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
403 addRegisterClass(MVT::i32, &ARM::GPRRegClass);
404 if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2() &&
405 !Subtarget->isThumb1Only()) {
406 addRegisterClass(MVT::f32, &ARM::SPRRegClass);
407 addRegisterClass(MVT::f64, &ARM::DPRRegClass);
410 for (MVT VT : MVT::vector_valuetypes()) {
411 for (MVT InnerVT : MVT::vector_valuetypes()) {
412 setTruncStoreAction(VT, InnerVT, Expand);
413 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
414 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
415 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
418 setOperationAction(ISD::MULHS, VT, Expand);
419 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
420 setOperationAction(ISD::MULHU, VT, Expand);
421 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
423 setOperationAction(ISD::BSWAP, VT, Expand);
426 setOperationAction(ISD::ConstantFP, MVT::f32, Custom);
427 setOperationAction(ISD::ConstantFP, MVT::f64, Custom);
429 setOperationAction(ISD::READ_REGISTER, MVT::i64, Custom);
430 setOperationAction(ISD::WRITE_REGISTER, MVT::i64, Custom);
432 if (Subtarget->hasNEON()) {
433 addDRTypeForNEON(MVT::v2f32);
434 addDRTypeForNEON(MVT::v8i8);
435 addDRTypeForNEON(MVT::v4i16);
436 addDRTypeForNEON(MVT::v2i32);
437 addDRTypeForNEON(MVT::v1i64);
439 addQRTypeForNEON(MVT::v4f32);
440 addQRTypeForNEON(MVT::v2f64);
441 addQRTypeForNEON(MVT::v16i8);
442 addQRTypeForNEON(MVT::v8i16);
443 addQRTypeForNEON(MVT::v4i32);
444 addQRTypeForNEON(MVT::v2i64);
446 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
447 // neither Neon nor VFP support any arithmetic operations on it.
448 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
449 // supported for v4f32.
450 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
451 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
452 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
453 // FIXME: Code duplication: FDIV and FREM are expanded always, see
454 // ARMTargetLowering::addTypeForNEON method for details.
455 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
456 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
457 // FIXME: Create unittest.
458 // In another words, find a way when "copysign" appears in DAG with vector
460 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
461 // FIXME: Code duplication: SETCC has custom operation action, see
462 // ARMTargetLowering::addTypeForNEON method for details.
463 setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
464 // FIXME: Create unittest for FNEG and for FABS.
465 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
466 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
467 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
468 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
469 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
470 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
471 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
472 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
473 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
474 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
475 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
476 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
477 // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR.
478 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
479 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
480 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
481 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
482 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
483 setOperationAction(ISD::FMA, MVT::v2f64, Expand);
485 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
486 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
487 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
488 setOperationAction(ISD::FPOWI, MVT::v4f32, Expand);
489 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
490 setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
491 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
492 setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
493 setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
494 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
495 setOperationAction(ISD::FCEIL, MVT::v4f32, Expand);
496 setOperationAction(ISD::FTRUNC, MVT::v4f32, Expand);
497 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
498 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
499 setOperationAction(ISD::FFLOOR, MVT::v4f32, Expand);
501 // Mark v2f32 intrinsics.
502 setOperationAction(ISD::FSQRT, MVT::v2f32, Expand);
503 setOperationAction(ISD::FSIN, MVT::v2f32, Expand);
504 setOperationAction(ISD::FCOS, MVT::v2f32, Expand);
505 setOperationAction(ISD::FPOWI, MVT::v2f32, Expand);
506 setOperationAction(ISD::FPOW, MVT::v2f32, Expand);
507 setOperationAction(ISD::FLOG, MVT::v2f32, Expand);
508 setOperationAction(ISD::FLOG2, MVT::v2f32, Expand);
509 setOperationAction(ISD::FLOG10, MVT::v2f32, Expand);
510 setOperationAction(ISD::FEXP, MVT::v2f32, Expand);
511 setOperationAction(ISD::FEXP2, MVT::v2f32, Expand);
512 setOperationAction(ISD::FCEIL, MVT::v2f32, Expand);
513 setOperationAction(ISD::FTRUNC, MVT::v2f32, Expand);
514 setOperationAction(ISD::FRINT, MVT::v2f32, Expand);
515 setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Expand);
516 setOperationAction(ISD::FFLOOR, MVT::v2f32, Expand);
518 // Neon does not support some operations on v1i64 and v2i64 types.
519 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
520 // Custom handling for some quad-vector types to detect VMULL.
521 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
522 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
523 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
524 // Custom handling for some vector types to avoid expensive expansions
525 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
526 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
527 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
528 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
529 setOperationAction(ISD::SETCC, MVT::v1i64, Expand);
530 setOperationAction(ISD::SETCC, MVT::v2i64, Expand);
531 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
532 // a destination type that is wider than the source, and nor does
533 // it have a FP_TO_[SU]INT instruction with a narrower destination than
535 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
536 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
537 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
538 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
540 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
541 setOperationAction(ISD::FP_EXTEND, MVT::v2f64, Expand);
543 // NEON does not have single instruction CTPOP for vectors with element
544 // types wider than 8-bits. However, custom lowering can leverage the
545 // v8i8/v16i8 vcnt instruction.
546 setOperationAction(ISD::CTPOP, MVT::v2i32, Custom);
547 setOperationAction(ISD::CTPOP, MVT::v4i32, Custom);
548 setOperationAction(ISD::CTPOP, MVT::v4i16, Custom);
549 setOperationAction(ISD::CTPOP, MVT::v8i16, Custom);
551 // NEON does not have single instruction CTTZ for vectors.
552 setOperationAction(ISD::CTTZ, MVT::v8i8, Custom);
553 setOperationAction(ISD::CTTZ, MVT::v4i16, Custom);
554 setOperationAction(ISD::CTTZ, MVT::v2i32, Custom);
555 setOperationAction(ISD::CTTZ, MVT::v1i64, Custom);
557 setOperationAction(ISD::CTTZ, MVT::v16i8, Custom);
558 setOperationAction(ISD::CTTZ, MVT::v8i16, Custom);
559 setOperationAction(ISD::CTTZ, MVT::v4i32, Custom);
560 setOperationAction(ISD::CTTZ, MVT::v2i64, Custom);
562 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i8, Custom);
563 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i16, Custom);
564 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i32, Custom);
565 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v1i64, Custom);
567 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v16i8, Custom);
568 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v8i16, Custom);
569 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v4i32, Custom);
570 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
572 // NEON only has FMA instructions as of VFP4.
573 if (!Subtarget->hasVFP4()) {
574 setOperationAction(ISD::FMA, MVT::v2f32, Expand);
575 setOperationAction(ISD::FMA, MVT::v4f32, Expand);
578 setTargetDAGCombine(ISD::INTRINSIC_VOID);
579 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
580 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
581 setTargetDAGCombine(ISD::SHL);
582 setTargetDAGCombine(ISD::SRL);
583 setTargetDAGCombine(ISD::SRA);
584 setTargetDAGCombine(ISD::SIGN_EXTEND);
585 setTargetDAGCombine(ISD::ZERO_EXTEND);
586 setTargetDAGCombine(ISD::ANY_EXTEND);
587 setTargetDAGCombine(ISD::SELECT_CC);
588 setTargetDAGCombine(ISD::BUILD_VECTOR);
589 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
590 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
591 setTargetDAGCombine(ISD::STORE);
592 setTargetDAGCombine(ISD::FP_TO_SINT);
593 setTargetDAGCombine(ISD::FP_TO_UINT);
594 setTargetDAGCombine(ISD::FDIV);
595 setTargetDAGCombine(ISD::LOAD);
597 // It is legal to extload from v4i8 to v4i16 or v4i32.
598 for (MVT Ty : {MVT::v8i8, MVT::v4i8, MVT::v2i8, MVT::v4i16, MVT::v2i16,
600 for (MVT VT : MVT::integer_vector_valuetypes()) {
601 setLoadExtAction(ISD::EXTLOAD, VT, Ty, Legal);
602 setLoadExtAction(ISD::ZEXTLOAD, VT, Ty, Legal);
603 setLoadExtAction(ISD::SEXTLOAD, VT, Ty, Legal);
608 // ARM and Thumb2 support UMLAL/SMLAL.
609 if (!Subtarget->isThumb1Only())
610 setTargetDAGCombine(ISD::ADDC);
612 if (Subtarget->isFPOnlySP()) {
613 // When targetting a floating-point unit with only single-precision
614 // operations, f64 is legal for the few double-precision instructions which
615 // are present However, no double-precision operations other than moves,
616 // loads and stores are provided by the hardware.
617 setOperationAction(ISD::FADD, MVT::f64, Expand);
618 setOperationAction(ISD::FSUB, MVT::f64, Expand);
619 setOperationAction(ISD::FMUL, MVT::f64, Expand);
620 setOperationAction(ISD::FMA, MVT::f64, Expand);
621 setOperationAction(ISD::FDIV, MVT::f64, Expand);
622 setOperationAction(ISD::FREM, MVT::f64, Expand);
623 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
624 setOperationAction(ISD::FGETSIGN, MVT::f64, Expand);
625 setOperationAction(ISD::FNEG, MVT::f64, Expand);
626 setOperationAction(ISD::FABS, MVT::f64, Expand);
627 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
628 setOperationAction(ISD::FSIN, MVT::f64, Expand);
629 setOperationAction(ISD::FCOS, MVT::f64, Expand);
630 setOperationAction(ISD::FPOWI, MVT::f64, Expand);
631 setOperationAction(ISD::FPOW, MVT::f64, Expand);
632 setOperationAction(ISD::FLOG, MVT::f64, Expand);
633 setOperationAction(ISD::FLOG2, MVT::f64, Expand);
634 setOperationAction(ISD::FLOG10, MVT::f64, Expand);
635 setOperationAction(ISD::FEXP, MVT::f64, Expand);
636 setOperationAction(ISD::FEXP2, MVT::f64, Expand);
637 setOperationAction(ISD::FCEIL, MVT::f64, Expand);
638 setOperationAction(ISD::FTRUNC, MVT::f64, Expand);
639 setOperationAction(ISD::FRINT, MVT::f64, Expand);
640 setOperationAction(ISD::FNEARBYINT, MVT::f64, Expand);
641 setOperationAction(ISD::FFLOOR, MVT::f64, Expand);
642 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
643 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
644 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
645 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
646 setOperationAction(ISD::FP_TO_SINT, MVT::f64, Custom);
647 setOperationAction(ISD::FP_TO_UINT, MVT::f64, Custom);
648 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom);
649 setOperationAction(ISD::FP_EXTEND, MVT::f64, Custom);
652 computeRegisterProperties(Subtarget->getRegisterInfo());
654 // ARM does not have floating-point extending loads.
655 for (MVT VT : MVT::fp_valuetypes()) {
656 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
657 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f16, Expand);
660 // ... or truncating stores
661 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
662 setTruncStoreAction(MVT::f32, MVT::f16, Expand);
663 setTruncStoreAction(MVT::f64, MVT::f16, Expand);
665 // ARM does not have i1 sign extending load.
666 for (MVT VT : MVT::integer_valuetypes())
667 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
669 // ARM supports all 4 flavors of integer indexed load / store.
670 if (!Subtarget->isThumb1Only()) {
671 for (unsigned im = (unsigned)ISD::PRE_INC;
672 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
673 setIndexedLoadAction(im, MVT::i1, Legal);
674 setIndexedLoadAction(im, MVT::i8, Legal);
675 setIndexedLoadAction(im, MVT::i16, Legal);
676 setIndexedLoadAction(im, MVT::i32, Legal);
677 setIndexedStoreAction(im, MVT::i1, Legal);
678 setIndexedStoreAction(im, MVT::i8, Legal);
679 setIndexedStoreAction(im, MVT::i16, Legal);
680 setIndexedStoreAction(im, MVT::i32, Legal);
684 setOperationAction(ISD::SADDO, MVT::i32, Custom);
685 setOperationAction(ISD::UADDO, MVT::i32, Custom);
686 setOperationAction(ISD::SSUBO, MVT::i32, Custom);
687 setOperationAction(ISD::USUBO, MVT::i32, Custom);
689 // i64 operation support.
690 setOperationAction(ISD::MUL, MVT::i64, Expand);
691 setOperationAction(ISD::MULHU, MVT::i32, Expand);
692 if (Subtarget->isThumb1Only()) {
693 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
694 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
696 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
697 || (Subtarget->isThumb2() && !Subtarget->hasThumb2DSP()))
698 setOperationAction(ISD::MULHS, MVT::i32, Expand);
700 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
701 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
702 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
703 setOperationAction(ISD::SRL, MVT::i64, Custom);
704 setOperationAction(ISD::SRA, MVT::i64, Custom);
706 if (!Subtarget->isThumb1Only()) {
707 // FIXME: We should do this for Thumb1 as well.
708 setOperationAction(ISD::ADDC, MVT::i32, Custom);
709 setOperationAction(ISD::ADDE, MVT::i32, Custom);
710 setOperationAction(ISD::SUBC, MVT::i32, Custom);
711 setOperationAction(ISD::SUBE, MVT::i32, Custom);
714 // ARM does not have ROTL.
715 setOperationAction(ISD::ROTL, MVT::i32, Expand);
716 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
717 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
718 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
719 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
721 // These just redirect to CTTZ and CTLZ on ARM.
722 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i32 , Expand);
723 setOperationAction(ISD::CTLZ_ZERO_UNDEF , MVT::i32 , Expand);
725 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
727 // Only ARMv6 has BSWAP.
728 if (!Subtarget->hasV6Ops())
729 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
731 if (!(Subtarget->hasDivide() && Subtarget->isThumb2()) &&
732 !(Subtarget->hasDivideInARMMode() && !Subtarget->isThumb())) {
733 // These are expanded into libcalls if the cpu doesn't have HW divider.
734 setOperationAction(ISD::SDIV, MVT::i32, Expand);
735 setOperationAction(ISD::UDIV, MVT::i32, Expand);
738 // FIXME: Also set divmod for SREM on EABI
739 setOperationAction(ISD::SREM, MVT::i32, Expand);
740 setOperationAction(ISD::UREM, MVT::i32, Expand);
741 // Register based DivRem for AEABI (RTABI 4.2)
742 if (Subtarget->isTargetAEABI()) {
743 setLibcallName(RTLIB::SDIVREM_I8, "__aeabi_idivmod");
744 setLibcallName(RTLIB::SDIVREM_I16, "__aeabi_idivmod");
745 setLibcallName(RTLIB::SDIVREM_I32, "__aeabi_idivmod");
746 setLibcallName(RTLIB::SDIVREM_I64, "__aeabi_ldivmod");
747 setLibcallName(RTLIB::UDIVREM_I8, "__aeabi_uidivmod");
748 setLibcallName(RTLIB::UDIVREM_I16, "__aeabi_uidivmod");
749 setLibcallName(RTLIB::UDIVREM_I32, "__aeabi_uidivmod");
750 setLibcallName(RTLIB::UDIVREM_I64, "__aeabi_uldivmod");
752 setLibcallCallingConv(RTLIB::SDIVREM_I8, CallingConv::ARM_AAPCS);
753 setLibcallCallingConv(RTLIB::SDIVREM_I16, CallingConv::ARM_AAPCS);
754 setLibcallCallingConv(RTLIB::SDIVREM_I32, CallingConv::ARM_AAPCS);
755 setLibcallCallingConv(RTLIB::SDIVREM_I64, CallingConv::ARM_AAPCS);
756 setLibcallCallingConv(RTLIB::UDIVREM_I8, CallingConv::ARM_AAPCS);
757 setLibcallCallingConv(RTLIB::UDIVREM_I16, CallingConv::ARM_AAPCS);
758 setLibcallCallingConv(RTLIB::UDIVREM_I32, CallingConv::ARM_AAPCS);
759 setLibcallCallingConv(RTLIB::UDIVREM_I64, CallingConv::ARM_AAPCS);
761 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
762 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
764 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
765 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
768 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
769 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
770 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
771 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
772 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
774 setOperationAction(ISD::TRAP, MVT::Other, Legal);
776 // Use the default implementation.
777 setOperationAction(ISD::VASTART, MVT::Other, Custom);
778 setOperationAction(ISD::VAARG, MVT::Other, Expand);
779 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
780 setOperationAction(ISD::VAEND, MVT::Other, Expand);
781 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
782 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
784 if (!Subtarget->isTargetMachO()) {
785 // Non-MachO platforms may return values in these registers via the
786 // personality function.
787 setExceptionPointerRegister(ARM::R0);
788 setExceptionSelectorRegister(ARM::R1);
791 if (Subtarget->getTargetTriple().isWindowsItaniumEnvironment())
792 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
794 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
796 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
797 // the default expansion. If we are targeting a single threaded system,
798 // then set them all for expand so we can lower them later into their
800 if (TM.Options.ThreadModel == ThreadModel::Single)
801 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
802 else if (Subtarget->hasAnyDataBarrier() && !Subtarget->isThumb1Only()) {
803 // ATOMIC_FENCE needs custom lowering; the others should have been expanded
804 // to ldrex/strex loops already.
805 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
807 // On v8, we have particularly efficient implementations of atomic fences
808 // if they can be combined with nearby atomic loads and stores.
809 if (!Subtarget->hasV8Ops()) {
810 // Automatically insert fences (dmb ish) around ATOMIC_SWAP etc.
811 setInsertFencesForAtomic(true);
814 // If there's anything we can use as a barrier, go through custom lowering
816 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other,
817 Subtarget->hasAnyDataBarrier() ? Custom : Expand);
819 // Set them all for expansion, which will force libcalls.
820 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
821 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
822 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
823 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
824 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
825 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
826 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
827 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
828 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
829 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
830 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
831 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
832 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the
833 // Unordered/Monotonic case.
834 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
835 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
838 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
840 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
841 if (!Subtarget->hasV6Ops()) {
842 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
843 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
845 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
847 if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2() &&
848 !Subtarget->isThumb1Only()) {
849 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
850 // iff target supports vfp2.
851 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
852 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
855 // We want to custom lower some of our intrinsics.
856 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
857 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
858 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
859 setOperationAction(ISD::EH_SJLJ_SETUP_DISPATCH, MVT::Other, Custom);
860 if (Subtarget->isTargetDarwin())
861 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
863 setOperationAction(ISD::SETCC, MVT::i32, Expand);
864 setOperationAction(ISD::SETCC, MVT::f32, Expand);
865 setOperationAction(ISD::SETCC, MVT::f64, Expand);
866 setOperationAction(ISD::SELECT, MVT::i32, Custom);
867 setOperationAction(ISD::SELECT, MVT::f32, Custom);
868 setOperationAction(ISD::SELECT, MVT::f64, Custom);
869 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
870 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
871 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
873 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
874 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
875 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
876 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
877 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
879 // We don't support sin/cos/fmod/copysign/pow
880 setOperationAction(ISD::FSIN, MVT::f64, Expand);
881 setOperationAction(ISD::FSIN, MVT::f32, Expand);
882 setOperationAction(ISD::FCOS, MVT::f32, Expand);
883 setOperationAction(ISD::FCOS, MVT::f64, Expand);
884 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
885 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
886 setOperationAction(ISD::FREM, MVT::f64, Expand);
887 setOperationAction(ISD::FREM, MVT::f32, Expand);
888 if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2() &&
889 !Subtarget->isThumb1Only()) {
890 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
891 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
893 setOperationAction(ISD::FPOW, MVT::f64, Expand);
894 setOperationAction(ISD::FPOW, MVT::f32, Expand);
896 if (!Subtarget->hasVFP4()) {
897 setOperationAction(ISD::FMA, MVT::f64, Expand);
898 setOperationAction(ISD::FMA, MVT::f32, Expand);
901 // Various VFP goodness
902 if (!Subtarget->useSoftFloat() && !Subtarget->isThumb1Only()) {
903 // FP-ARMv8 adds f64 <-> f16 conversion. Before that it should be expanded.
904 if (!Subtarget->hasFPARMv8() || Subtarget->isFPOnlySP()) {
905 setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);
906 setOperationAction(ISD::FP_TO_FP16, MVT::f64, Expand);
909 // fp16 is a special v7 extension that adds f16 <-> f32 conversions.
910 if (!Subtarget->hasFP16()) {
911 setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);
912 setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);
916 // Combine sin / cos into one node or libcall if possible.
917 if (Subtarget->hasSinCos()) {
918 setLibcallName(RTLIB::SINCOS_F32, "sincosf");
919 setLibcallName(RTLIB::SINCOS_F64, "sincos");
920 if (Subtarget->getTargetTriple().isiOS()) {
921 // For iOS, we don't want to the normal expansion of a libcall to
922 // sincos. We want to issue a libcall to __sincos_stret.
923 setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
924 setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
928 // FP-ARMv8 implements a lot of rounding-like FP operations.
929 if (Subtarget->hasFPARMv8()) {
930 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
931 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
932 setOperationAction(ISD::FROUND, MVT::f32, Legal);
933 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
934 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
935 setOperationAction(ISD::FRINT, MVT::f32, Legal);
936 if (!Subtarget->isFPOnlySP()) {
937 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
938 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
939 setOperationAction(ISD::FROUND, MVT::f64, Legal);
940 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
941 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
942 setOperationAction(ISD::FRINT, MVT::f64, Legal);
945 // We have target-specific dag combine patterns for the following nodes:
946 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
947 setTargetDAGCombine(ISD::ADD);
948 setTargetDAGCombine(ISD::SUB);
949 setTargetDAGCombine(ISD::MUL);
950 setTargetDAGCombine(ISD::AND);
951 setTargetDAGCombine(ISD::OR);
952 setTargetDAGCombine(ISD::XOR);
954 if (Subtarget->hasV6Ops())
955 setTargetDAGCombine(ISD::SRL);
957 setStackPointerRegisterToSaveRestore(ARM::SP);
959 if (Subtarget->useSoftFloat() || Subtarget->isThumb1Only() ||
960 !Subtarget->hasVFP2())
961 setSchedulingPreference(Sched::RegPressure);
963 setSchedulingPreference(Sched::Hybrid);
965 //// temporary - rewrite interface to use type
966 MaxStoresPerMemset = 8;
967 MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
968 MaxStoresPerMemcpy = 4; // For @llvm.memcpy -> sequence of stores
969 MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 4 : 2;
970 MaxStoresPerMemmove = 4; // For @llvm.memmove -> sequence of stores
971 MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 4 : 2;
973 // On ARM arguments smaller than 4 bytes are extended, so all arguments
974 // are at least 4 bytes aligned.
975 setMinStackArgumentAlignment(4);
977 // Prefer likely predicted branches to selects on out-of-order cores.
978 PredictableSelectIsExpensive = Subtarget->isLikeA9();
980 setMinFunctionAlignment(Subtarget->isThumb() ? 1 : 2);
983 bool ARMTargetLowering::useSoftFloat() const {
984 return Subtarget->useSoftFloat();
987 // FIXME: It might make sense to define the representative register class as the
988 // nearest super-register that has a non-null superset. For example, DPR_VFP2 is
989 // a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
990 // SPR's representative would be DPR_VFP2. This should work well if register
991 // pressure tracking were modified such that a register use would increment the
992 // pressure of the register class's representative and all of it's super
993 // classes' representatives transitively. We have not implemented this because
994 // of the difficulty prior to coalescing of modeling operand register classes
995 // due to the common occurrence of cross class copies and subregister insertions
997 std::pair<const TargetRegisterClass *, uint8_t>
998 ARMTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
1000 const TargetRegisterClass *RRC = nullptr;
1002 switch (VT.SimpleTy) {
1004 return TargetLowering::findRepresentativeClass(TRI, VT);
1005 // Use DPR as representative register class for all floating point
1006 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
1007 // the cost is 1 for both f32 and f64.
1008 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
1009 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
1010 RRC = &ARM::DPRRegClass;
1011 // When NEON is used for SP, only half of the register file is available
1012 // because operations that define both SP and DP results will be constrained
1013 // to the VFP2 class (D0-D15). We currently model this constraint prior to
1014 // coalescing by double-counting the SP regs. See the FIXME above.
1015 if (Subtarget->useNEONForSinglePrecisionFP())
1018 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
1019 case MVT::v4f32: case MVT::v2f64:
1020 RRC = &ARM::DPRRegClass;
1024 RRC = &ARM::DPRRegClass;
1028 RRC = &ARM::DPRRegClass;
1032 return std::make_pair(RRC, Cost);
1035 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
1036 switch ((ARMISD::NodeType)Opcode) {
1037 case ARMISD::FIRST_NUMBER: break;
1038 case ARMISD::Wrapper: return "ARMISD::Wrapper";
1039 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
1040 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
1041 case ARMISD::COPY_STRUCT_BYVAL: return "ARMISD::COPY_STRUCT_BYVAL";
1042 case ARMISD::CALL: return "ARMISD::CALL";
1043 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
1044 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
1045 case ARMISD::tCALL: return "ARMISD::tCALL";
1046 case ARMISD::BRCOND: return "ARMISD::BRCOND";
1047 case ARMISD::BR_JT: return "ARMISD::BR_JT";
1048 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
1049 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
1050 case ARMISD::INTRET_FLAG: return "ARMISD::INTRET_FLAG";
1051 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
1052 case ARMISD::CMP: return "ARMISD::CMP";
1053 case ARMISD::CMN: return "ARMISD::CMN";
1054 case ARMISD::CMPZ: return "ARMISD::CMPZ";
1055 case ARMISD::CMPFP: return "ARMISD::CMPFP";
1056 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
1057 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
1058 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
1060 case ARMISD::CMOV: return "ARMISD::CMOV";
1062 case ARMISD::RBIT: return "ARMISD::RBIT";
1064 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
1065 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
1066 case ARMISD::RRX: return "ARMISD::RRX";
1068 case ARMISD::ADDC: return "ARMISD::ADDC";
1069 case ARMISD::ADDE: return "ARMISD::ADDE";
1070 case ARMISD::SUBC: return "ARMISD::SUBC";
1071 case ARMISD::SUBE: return "ARMISD::SUBE";
1073 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
1074 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
1076 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
1077 case ARMISD::EH_SJLJ_LONGJMP: return "ARMISD::EH_SJLJ_LONGJMP";
1078 case ARMISD::EH_SJLJ_SETUP_DISPATCH: return "ARMISD::EH_SJLJ_SETUP_DISPATCH";
1080 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
1082 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
1084 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
1086 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
1088 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
1090 case ARMISD::WIN__CHKSTK: return "ARMISD:::WIN__CHKSTK";
1092 case ARMISD::VCEQ: return "ARMISD::VCEQ";
1093 case ARMISD::VCEQZ: return "ARMISD::VCEQZ";
1094 case ARMISD::VCGE: return "ARMISD::VCGE";
1095 case ARMISD::VCGEZ: return "ARMISD::VCGEZ";
1096 case ARMISD::VCLEZ: return "ARMISD::VCLEZ";
1097 case ARMISD::VCGEU: return "ARMISD::VCGEU";
1098 case ARMISD::VCGT: return "ARMISD::VCGT";
1099 case ARMISD::VCGTZ: return "ARMISD::VCGTZ";
1100 case ARMISD::VCLTZ: return "ARMISD::VCLTZ";
1101 case ARMISD::VCGTU: return "ARMISD::VCGTU";
1102 case ARMISD::VTST: return "ARMISD::VTST";
1104 case ARMISD::VSHL: return "ARMISD::VSHL";
1105 case ARMISD::VSHRs: return "ARMISD::VSHRs";
1106 case ARMISD::VSHRu: return "ARMISD::VSHRu";
1107 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
1108 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
1109 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
1110 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
1111 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
1112 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
1113 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
1114 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
1115 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
1116 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
1117 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
1118 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
1119 case ARMISD::VSLI: return "ARMISD::VSLI";
1120 case ARMISD::VSRI: return "ARMISD::VSRI";
1121 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
1122 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
1123 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
1124 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
1125 case ARMISD::VMOVFPIMM: return "ARMISD::VMOVFPIMM";
1126 case ARMISD::VDUP: return "ARMISD::VDUP";
1127 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
1128 case ARMISD::VEXT: return "ARMISD::VEXT";
1129 case ARMISD::VREV64: return "ARMISD::VREV64";
1130 case ARMISD::VREV32: return "ARMISD::VREV32";
1131 case ARMISD::VREV16: return "ARMISD::VREV16";
1132 case ARMISD::VZIP: return "ARMISD::VZIP";
1133 case ARMISD::VUZP: return "ARMISD::VUZP";
1134 case ARMISD::VTRN: return "ARMISD::VTRN";
1135 case ARMISD::VTBL1: return "ARMISD::VTBL1";
1136 case ARMISD::VTBL2: return "ARMISD::VTBL2";
1137 case ARMISD::VMULLs: return "ARMISD::VMULLs";
1138 case ARMISD::VMULLu: return "ARMISD::VMULLu";
1139 case ARMISD::UMLAL: return "ARMISD::UMLAL";
1140 case ARMISD::SMLAL: return "ARMISD::SMLAL";
1141 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
1142 case ARMISD::FMAX: return "ARMISD::FMAX";
1143 case ARMISD::FMIN: return "ARMISD::FMIN";
1144 case ARMISD::VMAXNM: return "ARMISD::VMAX";
1145 case ARMISD::VMINNM: return "ARMISD::VMIN";
1146 case ARMISD::BFI: return "ARMISD::BFI";
1147 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
1148 case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
1149 case ARMISD::VBSL: return "ARMISD::VBSL";
1150 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
1151 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
1152 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
1153 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD";
1154 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD";
1155 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD";
1156 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD";
1157 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD";
1158 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD";
1159 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD";
1160 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD";
1161 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD";
1162 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD";
1163 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD";
1164 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD";
1165 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD";
1166 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD";
1167 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD";
1168 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD";
1169 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD";
1174 EVT ARMTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
1177 return getPointerTy(DL);
1178 return VT.changeVectorElementTypeToInteger();
1181 /// getRegClassFor - Return the register class that should be used for the
1182 /// specified value type.
1183 const TargetRegisterClass *ARMTargetLowering::getRegClassFor(MVT VT) const {
1184 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
1185 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
1186 // load / store 4 to 8 consecutive D registers.
1187 if (Subtarget->hasNEON()) {
1188 if (VT == MVT::v4i64)
1189 return &ARM::QQPRRegClass;
1190 if (VT == MVT::v8i64)
1191 return &ARM::QQQQPRRegClass;
1193 return TargetLowering::getRegClassFor(VT);
1196 // memcpy, and other memory intrinsics, typically tries to use LDM/STM if the
1197 // source/dest is aligned and the copy size is large enough. We therefore want
1198 // to align such objects passed to memory intrinsics.
1199 bool ARMTargetLowering::shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
1200 unsigned &PrefAlign) const {
1201 if (!isa<MemIntrinsic>(CI))
1204 // On ARM11 onwards (excluding M class) 8-byte aligned LDM is typically 1
1205 // cycle faster than 4-byte aligned LDM.
1206 PrefAlign = (Subtarget->hasV6Ops() && !Subtarget->isMClass() ? 8 : 4);
1210 // Create a fast isel object.
1212 ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
1213 const TargetLibraryInfo *libInfo) const {
1214 return ARM::createFastISel(funcInfo, libInfo);
1217 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
1218 unsigned NumVals = N->getNumValues();
1220 return Sched::RegPressure;
1222 for (unsigned i = 0; i != NumVals; ++i) {
1223 EVT VT = N->getValueType(i);
1224 if (VT == MVT::Glue || VT == MVT::Other)
1226 if (VT.isFloatingPoint() || VT.isVector())
1230 if (!N->isMachineOpcode())
1231 return Sched::RegPressure;
1233 // Load are scheduled for latency even if there instruction itinerary
1234 // is not available.
1235 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
1236 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1238 if (MCID.getNumDefs() == 0)
1239 return Sched::RegPressure;
1240 if (!Itins->isEmpty() &&
1241 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
1244 return Sched::RegPressure;
1247 //===----------------------------------------------------------------------===//
1249 //===----------------------------------------------------------------------===//
1251 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
1252 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
1254 default: llvm_unreachable("Unknown condition code!");
1255 case ISD::SETNE: return ARMCC::NE;
1256 case ISD::SETEQ: return ARMCC::EQ;
1257 case ISD::SETGT: return ARMCC::GT;
1258 case ISD::SETGE: return ARMCC::GE;
1259 case ISD::SETLT: return ARMCC::LT;
1260 case ISD::SETLE: return ARMCC::LE;
1261 case ISD::SETUGT: return ARMCC::HI;
1262 case ISD::SETUGE: return ARMCC::HS;
1263 case ISD::SETULT: return ARMCC::LO;
1264 case ISD::SETULE: return ARMCC::LS;
1268 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
1269 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
1270 ARMCC::CondCodes &CondCode2) {
1271 CondCode2 = ARMCC::AL;
1273 default: llvm_unreachable("Unknown FP condition!");
1275 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
1277 case ISD::SETOGT: CondCode = ARMCC::GT; break;
1279 case ISD::SETOGE: CondCode = ARMCC::GE; break;
1280 case ISD::SETOLT: CondCode = ARMCC::MI; break;
1281 case ISD::SETOLE: CondCode = ARMCC::LS; break;
1282 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
1283 case ISD::SETO: CondCode = ARMCC::VC; break;
1284 case ISD::SETUO: CondCode = ARMCC::VS; break;
1285 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
1286 case ISD::SETUGT: CondCode = ARMCC::HI; break;
1287 case ISD::SETUGE: CondCode = ARMCC::PL; break;
1289 case ISD::SETULT: CondCode = ARMCC::LT; break;
1291 case ISD::SETULE: CondCode = ARMCC::LE; break;
1293 case ISD::SETUNE: CondCode = ARMCC::NE; break;
1297 //===----------------------------------------------------------------------===//
1298 // Calling Convention Implementation
1299 //===----------------------------------------------------------------------===//
1301 #include "ARMGenCallingConv.inc"
1303 /// getEffectiveCallingConv - Get the effective calling convention, taking into
1304 /// account presence of floating point hardware and calling convention
1305 /// limitations, such as support for variadic functions.
1307 ARMTargetLowering::getEffectiveCallingConv(CallingConv::ID CC,
1308 bool isVarArg) const {
1311 llvm_unreachable("Unsupported calling convention");
1312 case CallingConv::ARM_AAPCS:
1313 case CallingConv::ARM_APCS:
1314 case CallingConv::GHC:
1316 case CallingConv::ARM_AAPCS_VFP:
1317 return isVarArg ? CallingConv::ARM_AAPCS : CallingConv::ARM_AAPCS_VFP;
1318 case CallingConv::C:
1319 if (!Subtarget->isAAPCS_ABI())
1320 return CallingConv::ARM_APCS;
1321 else if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() &&
1322 getTargetMachine().Options.FloatABIType == FloatABI::Hard &&
1324 return CallingConv::ARM_AAPCS_VFP;
1326 return CallingConv::ARM_AAPCS;
1327 case CallingConv::Fast:
1328 if (!Subtarget->isAAPCS_ABI()) {
1329 if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() && !isVarArg)
1330 return CallingConv::Fast;
1331 return CallingConv::ARM_APCS;
1332 } else if (Subtarget->hasVFP2() && !Subtarget->isThumb1Only() && !isVarArg)
1333 return CallingConv::ARM_AAPCS_VFP;
1335 return CallingConv::ARM_AAPCS;
1339 /// CCAssignFnForNode - Selects the correct CCAssignFn for the given
1340 /// CallingConvention.
1341 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
1343 bool isVarArg) const {
1344 switch (getEffectiveCallingConv(CC, isVarArg)) {
1346 llvm_unreachable("Unsupported calling convention");
1347 case CallingConv::ARM_APCS:
1348 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1349 case CallingConv::ARM_AAPCS:
1350 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1351 case CallingConv::ARM_AAPCS_VFP:
1352 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1353 case CallingConv::Fast:
1354 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1355 case CallingConv::GHC:
1356 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC);
1360 /// LowerCallResult - Lower the result values of a call into the
1361 /// appropriate copies out of appropriate physical registers.
1363 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1364 CallingConv::ID CallConv, bool isVarArg,
1365 const SmallVectorImpl<ISD::InputArg> &Ins,
1366 SDLoc dl, SelectionDAG &DAG,
1367 SmallVectorImpl<SDValue> &InVals,
1368 bool isThisReturn, SDValue ThisVal) const {
1370 // Assign locations to each value returned by this call.
1371 SmallVector<CCValAssign, 16> RVLocs;
1372 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1373 *DAG.getContext(), Call);
1374 CCInfo.AnalyzeCallResult(Ins,
1375 CCAssignFnForNode(CallConv, /* Return*/ true,
1378 // Copy all of the result registers out of their specified physreg.
1379 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1380 CCValAssign VA = RVLocs[i];
1382 // Pass 'this' value directly from the argument to return value, to avoid
1383 // reg unit interference
1384 if (i == 0 && isThisReturn) {
1385 assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&
1386 "unexpected return calling convention register assignment");
1387 InVals.push_back(ThisVal);
1392 if (VA.needsCustom()) {
1393 // Handle f64 or half of a v2f64.
1394 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1396 Chain = Lo.getValue(1);
1397 InFlag = Lo.getValue(2);
1398 VA = RVLocs[++i]; // skip ahead to next loc
1399 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1401 Chain = Hi.getValue(1);
1402 InFlag = Hi.getValue(2);
1403 if (!Subtarget->isLittle())
1405 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1407 if (VA.getLocVT() == MVT::v2f64) {
1408 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1409 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1410 DAG.getConstant(0, dl, MVT::i32));
1412 VA = RVLocs[++i]; // skip ahead to next loc
1413 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1414 Chain = Lo.getValue(1);
1415 InFlag = Lo.getValue(2);
1416 VA = RVLocs[++i]; // skip ahead to next loc
1417 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1418 Chain = Hi.getValue(1);
1419 InFlag = Hi.getValue(2);
1420 if (!Subtarget->isLittle())
1422 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1423 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1424 DAG.getConstant(1, dl, MVT::i32));
1427 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1429 Chain = Val.getValue(1);
1430 InFlag = Val.getValue(2);
1433 switch (VA.getLocInfo()) {
1434 default: llvm_unreachable("Unknown loc info!");
1435 case CCValAssign::Full: break;
1436 case CCValAssign::BCvt:
1437 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1441 InVals.push_back(Val);
1447 /// LowerMemOpCallTo - Store the argument to the stack.
1449 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
1450 SDValue StackPtr, SDValue Arg,
1451 SDLoc dl, SelectionDAG &DAG,
1452 const CCValAssign &VA,
1453 ISD::ArgFlagsTy Flags) const {
1454 unsigned LocMemOffset = VA.getLocMemOffset();
1455 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
1456 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(DAG.getDataLayout()),
1458 return DAG.getStore(Chain, dl, Arg, PtrOff,
1459 MachinePointerInfo::getStack(LocMemOffset),
1463 void ARMTargetLowering::PassF64ArgInRegs(SDLoc dl, SelectionDAG &DAG,
1464 SDValue Chain, SDValue &Arg,
1465 RegsToPassVector &RegsToPass,
1466 CCValAssign &VA, CCValAssign &NextVA,
1468 SmallVectorImpl<SDValue> &MemOpChains,
1469 ISD::ArgFlagsTy Flags) const {
1471 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1472 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1473 unsigned id = Subtarget->isLittle() ? 0 : 1;
1474 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(id)));
1476 if (NextVA.isRegLoc())
1477 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1-id)));
1479 assert(NextVA.isMemLoc());
1480 if (!StackPtr.getNode())
1481 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP,
1482 getPointerTy(DAG.getDataLayout()));
1484 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1-id),
1490 /// LowerCall - Lowering a call into a callseq_start <-
1491 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1494 ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1495 SmallVectorImpl<SDValue> &InVals) const {
1496 SelectionDAG &DAG = CLI.DAG;
1498 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1499 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1500 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1501 SDValue Chain = CLI.Chain;
1502 SDValue Callee = CLI.Callee;
1503 bool &isTailCall = CLI.IsTailCall;
1504 CallingConv::ID CallConv = CLI.CallConv;
1505 bool doesNotRet = CLI.DoesNotReturn;
1506 bool isVarArg = CLI.IsVarArg;
1508 MachineFunction &MF = DAG.getMachineFunction();
1509 bool isStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1510 bool isThisReturn = false;
1511 bool isSibCall = false;
1512 auto Attr = MF.getFunction()->getFnAttribute("disable-tail-calls");
1514 // Disable tail calls if they're not supported.
1515 if (!Subtarget->supportsTailCall() || Attr.getValueAsString() == "true")
1519 // Check if it's really possible to do a tail call.
1520 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1521 isVarArg, isStructRet, MF.getFunction()->hasStructRetAttr(),
1522 Outs, OutVals, Ins, DAG);
1523 if (!isTailCall && CLI.CS && CLI.CS->isMustTailCall())
1524 report_fatal_error("failed to perform tail call elimination on a call "
1525 "site marked musttail");
1526 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1527 // detected sibcalls.
1534 // Analyze operands of the call, assigning locations to each operand.
1535 SmallVector<CCValAssign, 16> ArgLocs;
1536 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1537 *DAG.getContext(), Call);
1538 CCInfo.AnalyzeCallOperands(Outs,
1539 CCAssignFnForNode(CallConv, /* Return*/ false,
1542 // Get a count of how many bytes are to be pushed on the stack.
1543 unsigned NumBytes = CCInfo.getNextStackOffset();
1545 // For tail calls, memory operands are available in our caller's stack.
1549 // Adjust the stack pointer for the new arguments...
1550 // These operations are automatically eliminated by the prolog/epilog pass
1552 Chain = DAG.getCALLSEQ_START(Chain,
1553 DAG.getIntPtrConstant(NumBytes, dl, true), dl);
1556 DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy(DAG.getDataLayout()));
1558 RegsToPassVector RegsToPass;
1559 SmallVector<SDValue, 8> MemOpChains;
1561 // Walk the register/memloc assignments, inserting copies/loads. In the case
1562 // of tail call optimization, arguments are handled later.
1563 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1565 ++i, ++realArgIdx) {
1566 CCValAssign &VA = ArgLocs[i];
1567 SDValue Arg = OutVals[realArgIdx];
1568 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1569 bool isByVal = Flags.isByVal();
1571 // Promote the value if needed.
1572 switch (VA.getLocInfo()) {
1573 default: llvm_unreachable("Unknown loc info!");
1574 case CCValAssign::Full: break;
1575 case CCValAssign::SExt:
1576 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1578 case CCValAssign::ZExt:
1579 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1581 case CCValAssign::AExt:
1582 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1584 case CCValAssign::BCvt:
1585 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1589 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1590 if (VA.needsCustom()) {
1591 if (VA.getLocVT() == MVT::v2f64) {
1592 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1593 DAG.getConstant(0, dl, MVT::i32));
1594 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1595 DAG.getConstant(1, dl, MVT::i32));
1597 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1598 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1600 VA = ArgLocs[++i]; // skip ahead to next loc
1601 if (VA.isRegLoc()) {
1602 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1603 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1605 assert(VA.isMemLoc());
1607 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1608 dl, DAG, VA, Flags));
1611 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1612 StackPtr, MemOpChains, Flags);
1614 } else if (VA.isRegLoc()) {
1615 if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i32) {
1616 assert(VA.getLocVT() == MVT::i32 &&
1617 "unexpected calling convention register assignment");
1618 assert(!Ins.empty() && Ins[0].VT == MVT::i32 &&
1619 "unexpected use of 'returned'");
1620 isThisReturn = true;
1622 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1623 } else if (isByVal) {
1624 assert(VA.isMemLoc());
1625 unsigned offset = 0;
1627 // True if this byval aggregate will be split between registers
1629 unsigned ByValArgsCount = CCInfo.getInRegsParamsCount();
1630 unsigned CurByValIdx = CCInfo.getInRegsParamsProcessed();
1632 if (CurByValIdx < ByValArgsCount) {
1634 unsigned RegBegin, RegEnd;
1635 CCInfo.getInRegsParamInfo(CurByValIdx, RegBegin, RegEnd);
1638 DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
1640 for (i = 0, j = RegBegin; j < RegEnd; i++, j++) {
1641 SDValue Const = DAG.getConstant(4*i, dl, MVT::i32);
1642 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
1643 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
1644 MachinePointerInfo(),
1645 false, false, false,
1646 DAG.InferPtrAlignment(AddArg));
1647 MemOpChains.push_back(Load.getValue(1));
1648 RegsToPass.push_back(std::make_pair(j, Load));
1651 // If parameter size outsides register area, "offset" value
1652 // helps us to calculate stack slot for remained part properly.
1653 offset = RegEnd - RegBegin;
1655 CCInfo.nextInRegsParam();
1658 if (Flags.getByValSize() > 4*offset) {
1659 auto PtrVT = getPointerTy(DAG.getDataLayout());
1660 unsigned LocMemOffset = VA.getLocMemOffset();
1661 SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
1662 SDValue Dst = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, StkPtrOff);
1663 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset, dl);
1664 SDValue Src = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, SrcOffset);
1665 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset, dl,
1667 SDValue AlignNode = DAG.getConstant(Flags.getByValAlign(), dl,
1670 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
1671 SDValue Ops[] = { Chain, Dst, Src, SizeNode, AlignNode};
1672 MemOpChains.push_back(DAG.getNode(ARMISD::COPY_STRUCT_BYVAL, dl, VTs,
1675 } else if (!isSibCall) {
1676 assert(VA.isMemLoc());
1678 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1679 dl, DAG, VA, Flags));
1683 if (!MemOpChains.empty())
1684 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
1686 // Build a sequence of copy-to-reg nodes chained together with token chain
1687 // and flag operands which copy the outgoing args into the appropriate regs.
1689 // Tail call byval lowering might overwrite argument registers so in case of
1690 // tail call optimization the copies to registers are lowered later.
1692 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1693 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1694 RegsToPass[i].second, InFlag);
1695 InFlag = Chain.getValue(1);
1698 // For tail calls lower the arguments to the 'real' stack slot.
1700 // Force all the incoming stack arguments to be loaded from the stack
1701 // before any new outgoing arguments are stored to the stack, because the
1702 // outgoing stack slots may alias the incoming argument stack slots, and
1703 // the alias isn't otherwise explicit. This is slightly more conservative
1704 // than necessary, because it means that each store effectively depends
1705 // on every argument instead of just those arguments it would clobber.
1707 // Do not flag preceding copytoreg stuff together with the following stuff.
1709 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1710 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1711 RegsToPass[i].second, InFlag);
1712 InFlag = Chain.getValue(1);
1717 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1718 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1719 // node so that legalize doesn't hack it.
1720 bool isDirect = false;
1721 bool isARMFunc = false;
1722 bool isLocalARMFunc = false;
1723 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1724 auto PtrVt = getPointerTy(DAG.getDataLayout());
1726 if (Subtarget->genLongCalls()) {
1727 assert((Subtarget->isTargetWindows() ||
1728 getTargetMachine().getRelocationModel() == Reloc::Static) &&
1729 "long-calls with non-static relocation model!");
1730 // Handle a global address or an external symbol. If it's not one of
1731 // those, the target's already in a register, so we don't need to do
1733 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1734 const GlobalValue *GV = G->getGlobal();
1735 // Create a constant pool entry for the callee address
1736 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1737 ARMConstantPoolValue *CPV =
1738 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0);
1740 // Get the address of the callee into a register
1741 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4);
1742 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1743 Callee = DAG.getLoad(PtrVt, dl, DAG.getEntryNode(), CPAddr,
1744 MachinePointerInfo::getConstantPool(), false, false,
1746 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1747 const char *Sym = S->getSymbol();
1749 // Create a constant pool entry for the callee address
1750 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1751 ARMConstantPoolValue *CPV =
1752 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
1753 ARMPCLabelIndex, 0);
1754 // Get the address of the callee into a register
1755 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4);
1756 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1757 Callee = DAG.getLoad(PtrVt, dl, DAG.getEntryNode(), CPAddr,
1758 MachinePointerInfo::getConstantPool(), false, false,
1761 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1762 const GlobalValue *GV = G->getGlobal();
1764 bool isDef = GV->isStrongDefinitionForLinker();
1765 bool isStub = (!isDef && Subtarget->isTargetMachO()) &&
1766 getTargetMachine().getRelocationModel() != Reloc::Static;
1767 isARMFunc = !Subtarget->isThumb() || (isStub && !Subtarget->isMClass());
1768 // ARM call to a local ARM function is predicable.
1769 isLocalARMFunc = !Subtarget->isThumb() && (isDef || !ARMInterworking);
1770 // tBX takes a register source operand.
1771 if (isStub && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1772 assert(Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?");
1773 Callee = DAG.getNode(
1774 ARMISD::WrapperPIC, dl, PtrVt,
1775 DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, ARMII::MO_NONLAZY));
1776 Callee = DAG.getLoad(PtrVt, dl, DAG.getEntryNode(), Callee,
1777 MachinePointerInfo::getGOT(), false, false, true, 0);
1778 } else if (Subtarget->isTargetCOFF()) {
1779 assert(Subtarget->isTargetWindows() &&
1780 "Windows is the only supported COFF target");
1781 unsigned TargetFlags = GV->hasDLLImportStorageClass()
1782 ? ARMII::MO_DLLIMPORT
1783 : ARMII::MO_NO_FLAG;
1785 DAG.getTargetGlobalAddress(GV, dl, PtrVt, /*Offset=*/0, TargetFlags);
1786 if (GV->hasDLLImportStorageClass())
1788 DAG.getLoad(PtrVt, dl, DAG.getEntryNode(),
1789 DAG.getNode(ARMISD::Wrapper, dl, PtrVt, Callee),
1790 MachinePointerInfo::getGOT(), false, false, false, 0);
1792 // On ELF targets for PIC code, direct calls should go through the PLT
1793 unsigned OpFlags = 0;
1794 if (Subtarget->isTargetELF() &&
1795 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1796 OpFlags = ARMII::MO_PLT;
1797 Callee = DAG.getTargetGlobalAddress(GV, dl, PtrVt, 0, OpFlags);
1799 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1801 bool isStub = Subtarget->isTargetMachO() &&
1802 getTargetMachine().getRelocationModel() != Reloc::Static;
1803 isARMFunc = !Subtarget->isThumb() || (isStub && !Subtarget->isMClass());
1804 // tBX takes a register source operand.
1805 const char *Sym = S->getSymbol();
1806 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1807 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1808 ARMConstantPoolValue *CPV =
1809 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
1810 ARMPCLabelIndex, 4);
1811 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVt, 4);
1812 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1813 Callee = DAG.getLoad(PtrVt, dl, DAG.getEntryNode(), CPAddr,
1814 MachinePointerInfo::getConstantPool(), false, false,
1816 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
1817 Callee = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVt, Callee, PICLabel);
1819 unsigned OpFlags = 0;
1820 // On ELF targets for PIC code, direct calls should go through the PLT
1821 if (Subtarget->isTargetELF() &&
1822 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1823 OpFlags = ARMII::MO_PLT;
1824 Callee = DAG.getTargetExternalSymbol(Sym, PtrVt, OpFlags);
1828 // FIXME: handle tail calls differently.
1830 bool HasMinSizeAttr = MF.getFunction()->hasFnAttribute(Attribute::MinSize);
1831 if (Subtarget->isThumb()) {
1832 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1833 CallOpc = ARMISD::CALL_NOLINK;
1835 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1837 if (!isDirect && !Subtarget->hasV5TOps())
1838 CallOpc = ARMISD::CALL_NOLINK;
1839 else if (doesNotRet && isDirect && Subtarget->hasRAS() &&
1840 // Emit regular call when code size is the priority
1842 // "mov lr, pc; b _foo" to avoid confusing the RSP
1843 CallOpc = ARMISD::CALL_NOLINK;
1845 CallOpc = isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL;
1848 std::vector<SDValue> Ops;
1849 Ops.push_back(Chain);
1850 Ops.push_back(Callee);
1852 // Add argument registers to the end of the list so that they are known live
1854 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1855 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1856 RegsToPass[i].second.getValueType()));
1858 // Add a register mask operand representing the call-preserved registers.
1860 const uint32_t *Mask;
1861 const ARMBaseRegisterInfo *ARI = Subtarget->getRegisterInfo();
1863 // For 'this' returns, use the R0-preserving mask if applicable
1864 Mask = ARI->getThisReturnPreservedMask(MF, CallConv);
1866 // Set isThisReturn to false if the calling convention is not one that
1867 // allows 'returned' to be modeled in this way, so LowerCallResult does
1868 // not try to pass 'this' straight through
1869 isThisReturn = false;
1870 Mask = ARI->getCallPreservedMask(MF, CallConv);
1873 Mask = ARI->getCallPreservedMask(MF, CallConv);
1875 assert(Mask && "Missing call preserved mask for calling convention");
1876 Ops.push_back(DAG.getRegisterMask(Mask));
1879 if (InFlag.getNode())
1880 Ops.push_back(InFlag);
1882 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1884 MF.getFrameInfo()->setHasTailCall();
1885 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, Ops);
1888 // Returns a chain and a flag for retval copy to use.
1889 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
1890 InFlag = Chain.getValue(1);
1892 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
1893 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
1895 InFlag = Chain.getValue(1);
1897 // Handle result values, copying them out of physregs into vregs that we
1899 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
1900 InVals, isThisReturn,
1901 isThisReturn ? OutVals[0] : SDValue());
1904 /// HandleByVal - Every parameter *after* a byval parameter is passed
1905 /// on the stack. Remember the next parameter register to allocate,
1906 /// and then confiscate the rest of the parameter registers to insure
1908 void ARMTargetLowering::HandleByVal(CCState *State, unsigned &Size,
1909 unsigned Align) const {
1910 assert((State->getCallOrPrologue() == Prologue ||
1911 State->getCallOrPrologue() == Call) &&
1912 "unhandled ParmContext");
1914 // Byval (as with any stack) slots are always at least 4 byte aligned.
1915 Align = std::max(Align, 4U);
1917 unsigned Reg = State->AllocateReg(GPRArgRegs);
1921 unsigned AlignInRegs = Align / 4;
1922 unsigned Waste = (ARM::R4 - Reg) % AlignInRegs;
1923 for (unsigned i = 0; i < Waste; ++i)
1924 Reg = State->AllocateReg(GPRArgRegs);
1929 unsigned Excess = 4 * (ARM::R4 - Reg);
1931 // Special case when NSAA != SP and parameter size greater than size of
1932 // all remained GPR regs. In that case we can't split parameter, we must
1933 // send it to stack. We also must set NCRN to R4, so waste all
1934 // remained registers.
1935 const unsigned NSAAOffset = State->getNextStackOffset();
1936 if (NSAAOffset != 0 && Size > Excess) {
1937 while (State->AllocateReg(GPRArgRegs))
1942 // First register for byval parameter is the first register that wasn't
1943 // allocated before this method call, so it would be "reg".
1944 // If parameter is small enough to be saved in range [reg, r4), then
1945 // the end (first after last) register would be reg + param-size-in-regs,
1946 // else parameter would be splitted between registers and stack,
1947 // end register would be r4 in this case.
1948 unsigned ByValRegBegin = Reg;
1949 unsigned ByValRegEnd = std::min<unsigned>(Reg + Size / 4, ARM::R4);
1950 State->addInRegsParamInfo(ByValRegBegin, ByValRegEnd);
1951 // Note, first register is allocated in the beginning of function already,
1952 // allocate remained amount of registers we need.
1953 for (unsigned i = Reg + 1; i != ByValRegEnd; ++i)
1954 State->AllocateReg(GPRArgRegs);
1955 // A byval parameter that is split between registers and memory needs its
1956 // size truncated here.
1957 // In the case where the entire structure fits in registers, we set the
1958 // size in memory to zero.
1959 Size = std::max<int>(Size - Excess, 0);
1962 /// MatchingStackOffset - Return true if the given stack call argument is
1963 /// already available in the same position (relatively) of the caller's
1964 /// incoming argument stack.
1966 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1967 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1968 const TargetInstrInfo *TII) {
1969 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
1971 if (Arg.getOpcode() == ISD::CopyFromReg) {
1972 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
1973 if (!TargetRegisterInfo::isVirtualRegister(VR))
1975 MachineInstr *Def = MRI->getVRegDef(VR);
1978 if (!Flags.isByVal()) {
1979 if (!TII->isLoadFromStackSlot(Def, FI))
1984 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
1985 if (Flags.isByVal())
1986 // ByVal argument is passed in as a pointer but it's now being
1987 // dereferenced. e.g.
1988 // define @foo(%struct.X* %A) {
1989 // tail call @bar(%struct.X* byval %A)
1992 SDValue Ptr = Ld->getBasePtr();
1993 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
1996 FI = FINode->getIndex();
2000 assert(FI != INT_MAX);
2001 if (!MFI->isFixedObjectIndex(FI))
2003 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
2006 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2007 /// for tail call optimization. Targets which want to do tail call
2008 /// optimization should implement this function.
2010 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2011 CallingConv::ID CalleeCC,
2013 bool isCalleeStructRet,
2014 bool isCallerStructRet,
2015 const SmallVectorImpl<ISD::OutputArg> &Outs,
2016 const SmallVectorImpl<SDValue> &OutVals,
2017 const SmallVectorImpl<ISD::InputArg> &Ins,
2018 SelectionDAG& DAG) const {
2019 const Function *CallerF = DAG.getMachineFunction().getFunction();
2020 CallingConv::ID CallerCC = CallerF->getCallingConv();
2021 bool CCMatch = CallerCC == CalleeCC;
2023 // Look for obvious safe cases to perform tail call optimization that do not
2024 // require ABI changes. This is what gcc calls sibcall.
2026 // Do not sibcall optimize vararg calls unless the call site is not passing
2028 if (isVarArg && !Outs.empty())
2031 // Exception-handling functions need a special set of instructions to indicate
2032 // a return to the hardware. Tail-calling another function would probably
2034 if (CallerF->hasFnAttribute("interrupt"))
2037 // Also avoid sibcall optimization if either caller or callee uses struct
2038 // return semantics.
2039 if (isCalleeStructRet || isCallerStructRet)
2042 // FIXME: Completely disable sibcall for Thumb1 since ThumbRegisterInfo::
2043 // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
2044 // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
2045 // support in the assembler and linker to be used. This would need to be
2046 // fixed to fully support tail calls in Thumb1.
2048 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
2049 // LR. This means if we need to reload LR, it takes an extra instructions,
2050 // which outweighs the value of the tail call; but here we don't know yet
2051 // whether LR is going to be used. Probably the right approach is to
2052 // generate the tail call here and turn it back into CALL/RET in
2053 // emitEpilogue if LR is used.
2055 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
2056 // but we need to make sure there are enough registers; the only valid
2057 // registers are the 4 used for parameters. We don't currently do this
2059 if (Subtarget->isThumb1Only())
2062 // Externally-defined functions with weak linkage should not be
2063 // tail-called on ARM when the OS does not support dynamic
2064 // pre-emption of symbols, as the AAELF spec requires normal calls
2065 // to undefined weak functions to be replaced with a NOP or jump to the
2066 // next instruction. The behaviour of branch instructions in this
2067 // situation (as used for tail calls) is implementation-defined, so we
2068 // cannot rely on the linker replacing the tail call with a return.
2069 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2070 const GlobalValue *GV = G->getGlobal();
2071 const Triple &TT = getTargetMachine().getTargetTriple();
2072 if (GV->hasExternalWeakLinkage() &&
2073 (!TT.isOSWindows() || TT.isOSBinFormatELF() || TT.isOSBinFormatMachO()))
2077 // If the calling conventions do not match, then we'd better make sure the
2078 // results are returned in the same way as what the caller expects.
2080 SmallVector<CCValAssign, 16> RVLocs1;
2081 ARMCCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), RVLocs1,
2082 *DAG.getContext(), Call);
2083 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
2085 SmallVector<CCValAssign, 16> RVLocs2;
2086 ARMCCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), RVLocs2,
2087 *DAG.getContext(), Call);
2088 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
2090 if (RVLocs1.size() != RVLocs2.size())
2092 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
2093 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
2095 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
2097 if (RVLocs1[i].isRegLoc()) {
2098 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
2101 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
2107 // If Caller's vararg or byval argument has been split between registers and
2108 // stack, do not perform tail call, since part of the argument is in caller's
2110 const ARMFunctionInfo *AFI_Caller = DAG.getMachineFunction().
2111 getInfo<ARMFunctionInfo>();
2112 if (AFI_Caller->getArgRegsSaveSize())
2115 // If the callee takes no arguments then go on to check the results of the
2117 if (!Outs.empty()) {
2118 // Check if stack adjustment is needed. For now, do not do this if any
2119 // argument is passed on the stack.
2120 SmallVector<CCValAssign, 16> ArgLocs;
2121 ARMCCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), ArgLocs,
2122 *DAG.getContext(), Call);
2123 CCInfo.AnalyzeCallOperands(Outs,
2124 CCAssignFnForNode(CalleeCC, false, isVarArg));
2125 if (CCInfo.getNextStackOffset()) {
2126 MachineFunction &MF = DAG.getMachineFunction();
2128 // Check if the arguments are already laid out in the right way as
2129 // the caller's fixed stack objects.
2130 MachineFrameInfo *MFI = MF.getFrameInfo();
2131 const MachineRegisterInfo *MRI = &MF.getRegInfo();
2132 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
2133 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
2135 ++i, ++realArgIdx) {
2136 CCValAssign &VA = ArgLocs[i];
2137 EVT RegVT = VA.getLocVT();
2138 SDValue Arg = OutVals[realArgIdx];
2139 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
2140 if (VA.getLocInfo() == CCValAssign::Indirect)
2142 if (VA.needsCustom()) {
2143 // f64 and vector types are split into multiple registers or
2144 // register/stack-slot combinations. The types will not match
2145 // the registers; give up on memory f64 refs until we figure
2146 // out what to do about this.
2149 if (!ArgLocs[++i].isRegLoc())
2151 if (RegVT == MVT::v2f64) {
2152 if (!ArgLocs[++i].isRegLoc())
2154 if (!ArgLocs[++i].isRegLoc())
2157 } else if (!VA.isRegLoc()) {
2158 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2170 ARMTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
2171 MachineFunction &MF, bool isVarArg,
2172 const SmallVectorImpl<ISD::OutputArg> &Outs,
2173 LLVMContext &Context) const {
2174 SmallVector<CCValAssign, 16> RVLocs;
2175 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
2176 return CCInfo.CheckReturn(Outs, CCAssignFnForNode(CallConv, /*Return=*/true,
2180 static SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
2181 SDLoc DL, SelectionDAG &DAG) {
2182 const MachineFunction &MF = DAG.getMachineFunction();
2183 const Function *F = MF.getFunction();
2185 StringRef IntKind = F->getFnAttribute("interrupt").getValueAsString();
2187 // See ARM ARM v7 B1.8.3. On exception entry LR is set to a possibly offset
2188 // version of the "preferred return address". These offsets affect the return
2189 // instruction if this is a return from PL1 without hypervisor extensions.
2190 // IRQ/FIQ: +4 "subs pc, lr, #4"
2191 // SWI: 0 "subs pc, lr, #0"
2192 // ABORT: +4 "subs pc, lr, #4"
2193 // UNDEF: +4/+2 "subs pc, lr, #0"
2194 // UNDEF varies depending on where the exception came from ARM or Thumb
2195 // mode. Alongside GCC, we throw our hands up in disgust and pretend it's 0.
2198 if (IntKind == "" || IntKind == "IRQ" || IntKind == "FIQ" ||
2201 else if (IntKind == "SWI" || IntKind == "UNDEF")
2204 report_fatal_error("Unsupported interrupt attribute. If present, value "
2205 "must be one of: IRQ, FIQ, SWI, ABORT or UNDEF");
2207 RetOps.insert(RetOps.begin() + 1,
2208 DAG.getConstant(LROffset, DL, MVT::i32, false));
2210 return DAG.getNode(ARMISD::INTRET_FLAG, DL, MVT::Other, RetOps);
2214 ARMTargetLowering::LowerReturn(SDValue Chain,
2215 CallingConv::ID CallConv, bool isVarArg,
2216 const SmallVectorImpl<ISD::OutputArg> &Outs,
2217 const SmallVectorImpl<SDValue> &OutVals,
2218 SDLoc dl, SelectionDAG &DAG) const {
2220 // CCValAssign - represent the assignment of the return value to a location.
2221 SmallVector<CCValAssign, 16> RVLocs;
2223 // CCState - Info about the registers and stack slots.
2224 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
2225 *DAG.getContext(), Call);
2227 // Analyze outgoing return values.
2228 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
2232 SmallVector<SDValue, 4> RetOps;
2233 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2234 bool isLittleEndian = Subtarget->isLittle();
2236 MachineFunction &MF = DAG.getMachineFunction();
2237 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2238 AFI->setReturnRegsCount(RVLocs.size());
2240 // Copy the result values into the output registers.
2241 for (unsigned i = 0, realRVLocIdx = 0;
2243 ++i, ++realRVLocIdx) {
2244 CCValAssign &VA = RVLocs[i];
2245 assert(VA.isRegLoc() && "Can only return in registers!");
2247 SDValue Arg = OutVals[realRVLocIdx];
2249 switch (VA.getLocInfo()) {
2250 default: llvm_unreachable("Unknown loc info!");
2251 case CCValAssign::Full: break;
2252 case CCValAssign::BCvt:
2253 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2257 if (VA.needsCustom()) {
2258 if (VA.getLocVT() == MVT::v2f64) {
2259 // Extract the first half and return it in two registers.
2260 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2261 DAG.getConstant(0, dl, MVT::i32));
2262 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
2263 DAG.getVTList(MVT::i32, MVT::i32), Half);
2265 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2266 HalfGPRs.getValue(isLittleEndian ? 0 : 1),
2268 Flag = Chain.getValue(1);
2269 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2270 VA = RVLocs[++i]; // skip ahead to next loc
2271 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2272 HalfGPRs.getValue(isLittleEndian ? 1 : 0),
2274 Flag = Chain.getValue(1);
2275 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2276 VA = RVLocs[++i]; // skip ahead to next loc
2278 // Extract the 2nd half and fall through to handle it as an f64 value.
2279 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2280 DAG.getConstant(1, dl, MVT::i32));
2282 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
2284 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
2285 DAG.getVTList(MVT::i32, MVT::i32), Arg);
2286 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2287 fmrrd.getValue(isLittleEndian ? 0 : 1),
2289 Flag = Chain.getValue(1);
2290 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2291 VA = RVLocs[++i]; // skip ahead to next loc
2292 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2293 fmrrd.getValue(isLittleEndian ? 1 : 0),
2296 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
2298 // Guarantee that all emitted copies are
2299 // stuck together, avoiding something bad.
2300 Flag = Chain.getValue(1);
2301 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2304 // Update chain and glue.
2307 RetOps.push_back(Flag);
2309 // CPUs which aren't M-class use a special sequence to return from
2310 // exceptions (roughly, any instruction setting pc and cpsr simultaneously,
2311 // though we use "subs pc, lr, #N").
2313 // M-class CPUs actually use a normal return sequence with a special
2314 // (hardware-provided) value in LR, so the normal code path works.
2315 if (DAG.getMachineFunction().getFunction()->hasFnAttribute("interrupt") &&
2316 !Subtarget->isMClass()) {
2317 if (Subtarget->isThumb1Only())
2318 report_fatal_error("interrupt attribute is not supported in Thumb1");
2319 return LowerInterruptReturn(RetOps, dl, DAG);
2322 return DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, RetOps);
2325 bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2326 if (N->getNumValues() != 1)
2328 if (!N->hasNUsesOfValue(1, 0))
2331 SDValue TCChain = Chain;
2332 SDNode *Copy = *N->use_begin();
2333 if (Copy->getOpcode() == ISD::CopyToReg) {
2334 // If the copy has a glue operand, we conservatively assume it isn't safe to
2335 // perform a tail call.
2336 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2338 TCChain = Copy->getOperand(0);
2339 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) {
2340 SDNode *VMov = Copy;
2341 // f64 returned in a pair of GPRs.
2342 SmallPtrSet<SDNode*, 2> Copies;
2343 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2345 if (UI->getOpcode() != ISD::CopyToReg)
2349 if (Copies.size() > 2)
2352 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2354 SDValue UseChain = UI->getOperand(0);
2355 if (Copies.count(UseChain.getNode()))
2359 // We are at the top of this chain.
2360 // If the copy has a glue operand, we conservatively assume it
2361 // isn't safe to perform a tail call.
2362 if (UI->getOperand(UI->getNumOperands()-1).getValueType() == MVT::Glue)
2368 } else if (Copy->getOpcode() == ISD::BITCAST) {
2369 // f32 returned in a single GPR.
2370 if (!Copy->hasOneUse())
2372 Copy = *Copy->use_begin();
2373 if (Copy->getOpcode() != ISD::CopyToReg || !Copy->hasNUsesOfValue(1, 0))
2375 // If the copy has a glue operand, we conservatively assume it isn't safe to
2376 // perform a tail call.
2377 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2379 TCChain = Copy->getOperand(0);
2384 bool HasRet = false;
2385 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2387 if (UI->getOpcode() != ARMISD::RET_FLAG &&
2388 UI->getOpcode() != ARMISD::INTRET_FLAG)
2400 bool ARMTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2401 if (!Subtarget->supportsTailCall())
2405 CI->getParent()->getParent()->getFnAttribute("disable-tail-calls");
2406 if (!CI->isTailCall() || Attr.getValueAsString() == "true")
2409 return !Subtarget->isThumb1Only();
2412 // Trying to write a 64 bit value so need to split into two 32 bit values first,
2413 // and pass the lower and high parts through.
2414 static SDValue LowerWRITE_REGISTER(SDValue Op, SelectionDAG &DAG) {
2416 SDValue WriteValue = Op->getOperand(2);
2418 // This function is only supposed to be called for i64 type argument.
2419 assert(WriteValue.getValueType() == MVT::i64
2420 && "LowerWRITE_REGISTER called for non-i64 type argument.");
2422 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
2423 DAG.getConstant(0, DL, MVT::i32));
2424 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, WriteValue,
2425 DAG.getConstant(1, DL, MVT::i32));
2426 SDValue Ops[] = { Op->getOperand(0), Op->getOperand(1), Lo, Hi };
2427 return DAG.getNode(ISD::WRITE_REGISTER, DL, MVT::Other, Ops);
2430 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
2431 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
2432 // one of the above mentioned nodes. It has to be wrapped because otherwise
2433 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
2434 // be used to form addressing mode. These wrapped nodes will be selected
2436 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
2437 EVT PtrVT = Op.getValueType();
2438 // FIXME there is no actual debug info here
2440 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2442 if (CP->isMachineConstantPoolEntry())
2443 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
2444 CP->getAlignment());
2446 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
2447 CP->getAlignment());
2448 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
2451 unsigned ARMTargetLowering::getJumpTableEncoding() const {
2452 return MachineJumpTableInfo::EK_Inline;
2455 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
2456 SelectionDAG &DAG) const {
2457 MachineFunction &MF = DAG.getMachineFunction();
2458 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2459 unsigned ARMPCLabelIndex = 0;
2461 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2462 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
2463 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2465 if (RelocM == Reloc::Static) {
2466 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
2468 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2469 ARMPCLabelIndex = AFI->createPICLabelUId();
2470 ARMConstantPoolValue *CPV =
2471 ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex,
2472 ARMCP::CPBlockAddress, PCAdj);
2473 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2475 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
2476 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
2477 MachinePointerInfo::getConstantPool(),
2478 false, false, false, 0);
2479 if (RelocM == Reloc::Static)
2481 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, DL, MVT::i32);
2482 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
2485 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
2487 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
2488 SelectionDAG &DAG) const {
2490 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2491 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2492 MachineFunction &MF = DAG.getMachineFunction();
2493 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2494 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2495 ARMConstantPoolValue *CPV =
2496 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2497 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
2498 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2499 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
2500 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
2501 MachinePointerInfo::getConstantPool(),
2502 false, false, false, 0);
2503 SDValue Chain = Argument.getValue(1);
2505 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2506 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
2508 // call __tls_get_addr.
2511 Entry.Node = Argument;
2512 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
2513 Args.push_back(Entry);
2515 // FIXME: is there useful debug info available here?
2516 TargetLowering::CallLoweringInfo CLI(DAG);
2517 CLI.setDebugLoc(dl).setChain(Chain)
2518 .setCallee(CallingConv::C, Type::getInt32Ty(*DAG.getContext()),
2519 DAG.getExternalSymbol("__tls_get_addr", PtrVT), std::move(Args),
2522 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2523 return CallResult.first;
2526 // Lower ISD::GlobalTLSAddress using the "initial exec" or
2527 // "local exec" model.
2529 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
2531 TLSModel::Model model) const {
2532 const GlobalValue *GV = GA->getGlobal();
2535 SDValue Chain = DAG.getEntryNode();
2536 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2537 // Get the Thread Pointer
2538 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2540 if (model == TLSModel::InitialExec) {
2541 MachineFunction &MF = DAG.getMachineFunction();
2542 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2543 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2544 // Initial exec model.
2545 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2546 ARMConstantPoolValue *CPV =
2547 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2548 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF,
2550 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2551 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2552 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2553 MachinePointerInfo::getConstantPool(),
2554 false, false, false, 0);
2555 Chain = Offset.getValue(1);
2557 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2558 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
2560 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2561 MachinePointerInfo::getConstantPool(),
2562 false, false, false, 0);
2565 assert(model == TLSModel::LocalExec);
2566 ARMConstantPoolValue *CPV =
2567 ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF);
2568 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2569 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2570 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2571 MachinePointerInfo::getConstantPool(),
2572 false, false, false, 0);
2575 // The address of the thread local variable is the add of the thread
2576 // pointer with the offset of the variable.
2577 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
2581 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
2582 // TODO: implement the "local dynamic" model
2583 assert(Subtarget->isTargetELF() &&
2584 "TLS not implemented for non-ELF targets");
2585 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2586 if (DAG.getTarget().Options.EmulatedTLS)
2587 return LowerToTLSEmulatedModel(GA, DAG);
2589 TLSModel::Model model = getTargetMachine().getTLSModel(GA->getGlobal());
2592 case TLSModel::GeneralDynamic:
2593 case TLSModel::LocalDynamic:
2594 return LowerToTLSGeneralDynamicModel(GA, DAG);
2595 case TLSModel::InitialExec:
2596 case TLSModel::LocalExec:
2597 return LowerToTLSExecModels(GA, DAG, model);
2599 llvm_unreachable("bogus TLS model");
2602 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
2603 SelectionDAG &DAG) const {
2604 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2606 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2607 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2608 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
2609 ARMConstantPoolValue *CPV =
2610 ARMConstantPoolConstant::Create(GV,
2611 UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
2612 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2613 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2614 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
2616 MachinePointerInfo::getConstantPool(),
2617 false, false, false, 0);
2618 SDValue Chain = Result.getValue(1);
2619 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
2620 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
2622 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
2623 MachinePointerInfo::getGOT(),
2624 false, false, false, 0);
2628 // If we have T2 ops, we can materialize the address directly via movt/movw
2629 // pair. This is always cheaper.
2630 if (Subtarget->useMovt(DAG.getMachineFunction())) {
2632 // FIXME: Once remat is capable of dealing with instructions with register
2633 // operands, expand this into two nodes.
2634 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2635 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2637 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
2638 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2639 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2640 MachinePointerInfo::getConstantPool(),
2641 false, false, false, 0);
2645 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
2646 SelectionDAG &DAG) const {
2647 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2649 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2650 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2652 if (Subtarget->useMovt(DAG.getMachineFunction()))
2655 // FIXME: Once remat is capable of dealing with instructions with register
2656 // operands, expand this into multiple nodes
2658 RelocM == Reloc::PIC_ ? ARMISD::WrapperPIC : ARMISD::Wrapper;
2660 SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_NONLAZY);
2661 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT, G);
2663 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
2664 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
2665 MachinePointerInfo::getGOT(), false, false, false, 0);
2669 SDValue ARMTargetLowering::LowerGlobalAddressWindows(SDValue Op,
2670 SelectionDAG &DAG) const {
2671 assert(Subtarget->isTargetWindows() && "non-Windows COFF is not supported");
2672 assert(Subtarget->useMovt(DAG.getMachineFunction()) &&
2673 "Windows on ARM expects to use movw/movt");
2675 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2676 const ARMII::TOF TargetFlags =
2677 (GV->hasDLLImportStorageClass() ? ARMII::MO_DLLIMPORT : ARMII::MO_NO_FLAG);
2678 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2684 // FIXME: Once remat is capable of dealing with instructions with register
2685 // operands, expand this into two nodes.
2686 Result = DAG.getNode(ARMISD::Wrapper, DL, PtrVT,
2687 DAG.getTargetGlobalAddress(GV, DL, PtrVT, /*Offset=*/0,
2689 if (GV->hasDLLImportStorageClass())
2690 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
2691 MachinePointerInfo::getGOT(), false, false, false, 0);
2695 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
2696 SelectionDAG &DAG) const {
2697 assert(Subtarget->isTargetELF() &&
2698 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
2699 MachineFunction &MF = DAG.getMachineFunction();
2700 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2701 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2702 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2704 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2705 ARMConstantPoolValue *CPV =
2706 ARMConstantPoolSymbol::Create(*DAG.getContext(), "_GLOBAL_OFFSET_TABLE_",
2707 ARMPCLabelIndex, PCAdj);
2708 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2709 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2710 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2711 MachinePointerInfo::getConstantPool(),
2712 false, false, false, 0);
2713 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2714 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2718 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
2720 SDValue Val = DAG.getConstant(0, dl, MVT::i32);
2721 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl,
2722 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
2723 Op.getOperand(1), Val);
2727 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
2729 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
2730 Op.getOperand(1), DAG.getConstant(0, dl, MVT::i32));
2733 SDValue ARMTargetLowering::LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op,
2734 SelectionDAG &DAG) const {
2736 return DAG.getNode(ARMISD::EH_SJLJ_SETUP_DISPATCH, dl, MVT::Other,
2741 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
2742 const ARMSubtarget *Subtarget) const {
2743 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2746 default: return SDValue(); // Don't custom lower most intrinsics.
2747 case Intrinsic::arm_rbit: {
2748 assert(Op.getOperand(1).getValueType() == MVT::i32 &&
2749 "RBIT intrinsic must have i32 type!");
2750 return DAG.getNode(ARMISD::RBIT, dl, MVT::i32, Op.getOperand(1));
2752 case Intrinsic::arm_thread_pointer: {
2753 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2754 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2756 case Intrinsic::eh_sjlj_lsda: {
2757 MachineFunction &MF = DAG.getMachineFunction();
2758 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2759 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2760 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2761 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2763 unsigned PCAdj = (RelocM != Reloc::PIC_)
2764 ? 0 : (Subtarget->isThumb() ? 4 : 8);
2765 ARMConstantPoolValue *CPV =
2766 ARMConstantPoolConstant::Create(MF.getFunction(), ARMPCLabelIndex,
2767 ARMCP::CPLSDA, PCAdj);
2768 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2769 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2771 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2772 MachinePointerInfo::getConstantPool(),
2773 false, false, false, 0);
2775 if (RelocM == Reloc::PIC_) {
2776 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, dl, MVT::i32);
2777 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2781 case Intrinsic::arm_neon_vmulls:
2782 case Intrinsic::arm_neon_vmullu: {
2783 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
2784 ? ARMISD::VMULLs : ARMISD::VMULLu;
2785 return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
2786 Op.getOperand(1), Op.getOperand(2));
2791 static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
2792 const ARMSubtarget *Subtarget) {
2793 // FIXME: handle "fence singlethread" more efficiently.
2795 if (!Subtarget->hasDataBarrier()) {
2796 // Some ARMv6 cpus can support data barriers with an mcr instruction.
2797 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
2799 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&
2800 "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!");
2801 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2802 DAG.getConstant(0, dl, MVT::i32));
2805 ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1));
2806 AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue());
2807 ARM_MB::MemBOpt Domain = ARM_MB::ISH;
2808 if (Subtarget->isMClass()) {
2809 // Only a full system barrier exists in the M-class architectures.
2810 Domain = ARM_MB::SY;
2811 } else if (Subtarget->isSwift() && Ord == Release) {
2812 // Swift happens to implement ISHST barriers in a way that's compatible with
2813 // Release semantics but weaker than ISH so we'd be fools not to use
2814 // it. Beware: other processors probably don't!
2815 Domain = ARM_MB::ISHST;
2818 return DAG.getNode(ISD::INTRINSIC_VOID, dl, MVT::Other, Op.getOperand(0),
2819 DAG.getConstant(Intrinsic::arm_dmb, dl, MVT::i32),
2820 DAG.getConstant(Domain, dl, MVT::i32));
2823 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
2824 const ARMSubtarget *Subtarget) {
2825 // ARM pre v5TE and Thumb1 does not have preload instructions.
2826 if (!(Subtarget->isThumb2() ||
2827 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
2828 // Just preserve the chain.
2829 return Op.getOperand(0);
2832 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
2834 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
2835 // ARMv7 with MP extension has PLDW.
2836 return Op.getOperand(0);
2838 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
2839 if (Subtarget->isThumb()) {
2841 isRead = ~isRead & 1;
2842 isData = ~isData & 1;
2845 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
2846 Op.getOperand(1), DAG.getConstant(isRead, dl, MVT::i32),
2847 DAG.getConstant(isData, dl, MVT::i32));
2850 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
2851 MachineFunction &MF = DAG.getMachineFunction();
2852 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
2854 // vastart just stores the address of the VarArgsFrameIndex slot into the
2855 // memory location argument.
2857 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
2858 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2859 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2860 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2861 MachinePointerInfo(SV), false, false, 0);
2865 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
2866 SDValue &Root, SelectionDAG &DAG,
2868 MachineFunction &MF = DAG.getMachineFunction();
2869 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2871 const TargetRegisterClass *RC;
2872 if (AFI->isThumb1OnlyFunction())
2873 RC = &ARM::tGPRRegClass;
2875 RC = &ARM::GPRRegClass;
2877 // Transform the arguments stored in physical registers into virtual ones.
2878 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2879 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2882 if (NextVA.isMemLoc()) {
2883 MachineFrameInfo *MFI = MF.getFrameInfo();
2884 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
2886 // Create load node to retrieve arguments from the stack.
2887 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
2888 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
2889 MachinePointerInfo::getFixedStack(FI),
2890 false, false, false, 0);
2892 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2893 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2895 if (!Subtarget->isLittle())
2896 std::swap (ArgValue, ArgValue2);
2897 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
2900 // The remaining GPRs hold either the beginning of variable-argument
2901 // data, or the beginning of an aggregate passed by value (usually
2902 // byval). Either way, we allocate stack slots adjacent to the data
2903 // provided by our caller, and store the unallocated registers there.
2904 // If this is a variadic function, the va_list pointer will begin with
2905 // these values; otherwise, this reassembles a (byval) structure that
2906 // was split between registers and memory.
2907 // Return: The frame index registers were stored into.
2909 ARMTargetLowering::StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
2910 SDLoc dl, SDValue &Chain,
2911 const Value *OrigArg,
2912 unsigned InRegsParamRecordIdx,
2914 unsigned ArgSize) const {
2915 // Currently, two use-cases possible:
2916 // Case #1. Non-var-args function, and we meet first byval parameter.
2917 // Setup first unallocated register as first byval register;
2918 // eat all remained registers
2919 // (these two actions are performed by HandleByVal method).
2920 // Then, here, we initialize stack frame with
2921 // "store-reg" instructions.
2922 // Case #2. Var-args function, that doesn't contain byval parameters.
2923 // The same: eat all remained unallocated registers,
2924 // initialize stack frame.
2926 MachineFunction &MF = DAG.getMachineFunction();
2927 MachineFrameInfo *MFI = MF.getFrameInfo();
2928 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2929 unsigned RBegin, REnd;
2930 if (InRegsParamRecordIdx < CCInfo.getInRegsParamsCount()) {
2931 CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd);
2933 unsigned RBeginIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
2934 RBegin = RBeginIdx == 4 ? (unsigned)ARM::R4 : GPRArgRegs[RBeginIdx];
2939 ArgOffset = -4 * (ARM::R4 - RBegin);
2941 auto PtrVT = getPointerTy(DAG.getDataLayout());
2942 int FrameIndex = MFI->CreateFixedObject(ArgSize, ArgOffset, false);
2943 SDValue FIN = DAG.getFrameIndex(FrameIndex, PtrVT);
2945 SmallVector<SDValue, 4> MemOps;
2946 const TargetRegisterClass *RC =
2947 AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
2949 for (unsigned Reg = RBegin, i = 0; Reg < REnd; ++Reg, ++i) {
2950 unsigned VReg = MF.addLiveIn(Reg, RC);
2951 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2953 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2954 MachinePointerInfo(OrigArg, 4 * i), false, false, 0);
2955 MemOps.push_back(Store);
2956 FIN = DAG.getNode(ISD::ADD, dl, PtrVT, FIN, DAG.getConstant(4, dl, PtrVT));
2959 if (!MemOps.empty())
2960 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2964 // Setup stack frame, the va_list pointer will start from.
2966 ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
2967 SDLoc dl, SDValue &Chain,
2969 unsigned TotalArgRegsSaveSize,
2970 bool ForceMutable) const {
2971 MachineFunction &MF = DAG.getMachineFunction();
2972 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2974 // Try to store any remaining integer argument regs
2975 // to their spots on the stack so that they may be loaded by deferencing
2976 // the result of va_next.
2977 // If there is no regs to be stored, just point address after last
2978 // argument passed via stack.
2979 int FrameIndex = StoreByValRegs(CCInfo, DAG, dl, Chain, nullptr,
2980 CCInfo.getInRegsParamsCount(),
2981 CCInfo.getNextStackOffset(), 4);
2982 AFI->setVarArgsFrameIndex(FrameIndex);
2986 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
2987 CallingConv::ID CallConv, bool isVarArg,
2988 const SmallVectorImpl<ISD::InputArg>
2990 SDLoc dl, SelectionDAG &DAG,
2991 SmallVectorImpl<SDValue> &InVals)
2993 MachineFunction &MF = DAG.getMachineFunction();
2994 MachineFrameInfo *MFI = MF.getFrameInfo();
2996 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2998 // Assign locations to all of the incoming arguments.
2999 SmallVector<CCValAssign, 16> ArgLocs;
3000 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
3001 *DAG.getContext(), Prologue);
3002 CCInfo.AnalyzeFormalArguments(Ins,
3003 CCAssignFnForNode(CallConv, /* Return*/ false,
3006 SmallVector<SDValue, 16> ArgValues;
3008 Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin();
3009 unsigned CurArgIdx = 0;
3011 // Initially ArgRegsSaveSize is zero.
3012 // Then we increase this value each time we meet byval parameter.
3013 // We also increase this value in case of varargs function.
3014 AFI->setArgRegsSaveSize(0);
3016 // Calculate the amount of stack space that we need to allocate to store
3017 // byval and variadic arguments that are passed in registers.
3018 // We need to know this before we allocate the first byval or variadic
3019 // argument, as they will be allocated a stack slot below the CFA (Canonical
3020 // Frame Address, the stack pointer at entry to the function).
3021 unsigned ArgRegBegin = ARM::R4;
3022 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3023 if (CCInfo.getInRegsParamsProcessed() >= CCInfo.getInRegsParamsCount())
3026 CCValAssign &VA = ArgLocs[i];
3027 unsigned Index = VA.getValNo();
3028 ISD::ArgFlagsTy Flags = Ins[Index].Flags;
3029 if (!Flags.isByVal())
3032 assert(VA.isMemLoc() && "unexpected byval pointer in reg");
3033 unsigned RBegin, REnd;
3034 CCInfo.getInRegsParamInfo(CCInfo.getInRegsParamsProcessed(), RBegin, REnd);
3035 ArgRegBegin = std::min(ArgRegBegin, RBegin);
3037 CCInfo.nextInRegsParam();
3039 CCInfo.rewindByValRegsInfo();
3041 int lastInsIndex = -1;
3042 if (isVarArg && MFI->hasVAStart()) {
3043 unsigned RegIdx = CCInfo.getFirstUnallocated(GPRArgRegs);
3044 if (RegIdx != array_lengthof(GPRArgRegs))
3045 ArgRegBegin = std::min(ArgRegBegin, (unsigned)GPRArgRegs[RegIdx]);
3048 unsigned TotalArgRegsSaveSize = 4 * (ARM::R4 - ArgRegBegin);
3049 AFI->setArgRegsSaveSize(TotalArgRegsSaveSize);
3050 auto PtrVT = getPointerTy(DAG.getDataLayout());
3052 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
3053 CCValAssign &VA = ArgLocs[i];
3054 if (Ins[VA.getValNo()].isOrigArg()) {
3055 std::advance(CurOrigArg,
3056 Ins[VA.getValNo()].getOrigArgIndex() - CurArgIdx);
3057 CurArgIdx = Ins[VA.getValNo()].getOrigArgIndex();
3059 // Arguments stored in registers.
3060 if (VA.isRegLoc()) {
3061 EVT RegVT = VA.getLocVT();
3063 if (VA.needsCustom()) {
3064 // f64 and vector types are split up into multiple registers or
3065 // combinations of registers and stack slots.
3066 if (VA.getLocVT() == MVT::v2f64) {
3067 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
3069 VA = ArgLocs[++i]; // skip ahead to next loc
3071 if (VA.isMemLoc()) {
3072 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
3073 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3074 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
3075 MachinePointerInfo::getFixedStack(FI),
3076 false, false, false, 0);
3078 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
3081 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
3082 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
3083 ArgValue, ArgValue1,
3084 DAG.getIntPtrConstant(0, dl));
3085 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
3086 ArgValue, ArgValue2,
3087 DAG.getIntPtrConstant(1, dl));
3089 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
3092 const TargetRegisterClass *RC;
3094 if (RegVT == MVT::f32)
3095 RC = &ARM::SPRRegClass;
3096 else if (RegVT == MVT::f64)
3097 RC = &ARM::DPRRegClass;
3098 else if (RegVT == MVT::v2f64)
3099 RC = &ARM::QPRRegClass;
3100 else if (RegVT == MVT::i32)
3101 RC = AFI->isThumb1OnlyFunction() ? &ARM::tGPRRegClass
3102 : &ARM::GPRRegClass;
3104 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
3106 // Transform the arguments in physical registers into virtual ones.
3107 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
3108 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
3111 // If this is an 8 or 16-bit value, it is really passed promoted
3112 // to 32 bits. Insert an assert[sz]ext to capture this, then
3113 // truncate to the right size.
3114 switch (VA.getLocInfo()) {
3115 default: llvm_unreachable("Unknown loc info!");
3116 case CCValAssign::Full: break;
3117 case CCValAssign::BCvt:
3118 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
3120 case CCValAssign::SExt:
3121 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
3122 DAG.getValueType(VA.getValVT()));
3123 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3125 case CCValAssign::ZExt:
3126 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
3127 DAG.getValueType(VA.getValVT()));
3128 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
3132 InVals.push_back(ArgValue);
3134 } else { // VA.isRegLoc()
3137 assert(VA.isMemLoc());
3138 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
3140 int index = VA.getValNo();
3142 // Some Ins[] entries become multiple ArgLoc[] entries.
3143 // Process them only once.
3144 if (index != lastInsIndex)
3146 ISD::ArgFlagsTy Flags = Ins[index].Flags;
3147 // FIXME: For now, all byval parameter objects are marked mutable.
3148 // This can be changed with more analysis.
3149 // In case of tail call optimization mark all arguments mutable.
3150 // Since they could be overwritten by lowering of arguments in case of
3152 if (Flags.isByVal()) {
3153 assert(Ins[index].isOrigArg() &&
3154 "Byval arguments cannot be implicit");
3155 unsigned CurByValIndex = CCInfo.getInRegsParamsProcessed();
3157 int FrameIndex = StoreByValRegs(CCInfo, DAG, dl, Chain, CurOrigArg,
3158 CurByValIndex, VA.getLocMemOffset(),
3159 Flags.getByValSize());
3160 InVals.push_back(DAG.getFrameIndex(FrameIndex, PtrVT));
3161 CCInfo.nextInRegsParam();
3163 unsigned FIOffset = VA.getLocMemOffset();
3164 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
3167 // Create load nodes to retrieve arguments from the stack.
3168 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3169 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
3170 MachinePointerInfo::getFixedStack(FI),
3171 false, false, false, 0));
3173 lastInsIndex = index;
3179 if (isVarArg && MFI->hasVAStart())
3180 VarArgStyleRegisters(CCInfo, DAG, dl, Chain,
3181 CCInfo.getNextStackOffset(),
3182 TotalArgRegsSaveSize);
3184 AFI->setArgumentStackSize(CCInfo.getNextStackOffset());
3189 /// isFloatingPointZero - Return true if this is +0.0.
3190 static bool isFloatingPointZero(SDValue Op) {
3191 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
3192 return CFP->getValueAPF().isPosZero();
3193 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
3194 // Maybe this has already been legalized into the constant pool?
3195 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
3196 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
3197 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
3198 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
3199 return CFP->getValueAPF().isPosZero();
3201 } else if (Op->getOpcode() == ISD::BITCAST &&
3202 Op->getValueType(0) == MVT::f64) {
3203 // Handle (ISD::BITCAST (ARMISD::VMOVIMM (ISD::TargetConstant 0)) MVT::f64)
3204 // created by LowerConstantFP().
3205 SDValue BitcastOp = Op->getOperand(0);
3206 if (BitcastOp->getOpcode() == ARMISD::VMOVIMM) {
3207 SDValue MoveOp = BitcastOp->getOperand(0);
3208 if (MoveOp->getOpcode() == ISD::TargetConstant &&
3209 cast<ConstantSDNode>(MoveOp)->getZExtValue() == 0) {
3217 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
3218 /// the given operands.
3220 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
3221 SDValue &ARMcc, SelectionDAG &DAG,
3223 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
3224 unsigned C = RHSC->getZExtValue();
3225 if (!isLegalICmpImmediate(C)) {
3226 // Constant does not fit, try adjusting it by one?
3231 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
3232 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
3233 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
3238 if (C != 0 && isLegalICmpImmediate(C-1)) {
3239 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
3240 RHS = DAG.getConstant(C - 1, dl, MVT::i32);
3245 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
3246 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
3247 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
3252 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
3253 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
3254 RHS = DAG.getConstant(C + 1, dl, MVT::i32);
3261 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3262 ARMISD::NodeType CompareType;
3265 CompareType = ARMISD::CMP;
3270 CompareType = ARMISD::CMPZ;
3273 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
3274 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
3277 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
3279 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
3281 assert(!Subtarget->isFPOnlySP() || RHS.getValueType() != MVT::f64);
3283 if (!isFloatingPointZero(RHS))
3284 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS);
3286 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS);
3287 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
3290 /// duplicateCmp - Glue values can have only one use, so this function
3291 /// duplicates a comparison node.
3293 ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
3294 unsigned Opc = Cmp.getOpcode();
3296 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
3297 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
3299 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation");
3300 Cmp = Cmp.getOperand(0);
3301 Opc = Cmp.getOpcode();
3302 if (Opc == ARMISD::CMPFP)
3303 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
3305 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT");
3306 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0));
3308 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
3311 std::pair<SDValue, SDValue>
3312 ARMTargetLowering::getARMXALUOOp(SDValue Op, SelectionDAG &DAG,
3313 SDValue &ARMcc) const {
3314 assert(Op.getValueType() == MVT::i32 && "Unsupported value type");
3316 SDValue Value, OverflowCmp;
3317 SDValue LHS = Op.getOperand(0);
3318 SDValue RHS = Op.getOperand(1);
3321 // FIXME: We are currently always generating CMPs because we don't support
3322 // generating CMN through the backend. This is not as good as the natural
3323 // CMP case because it causes a register dependency and cannot be folded
3326 switch (Op.getOpcode()) {
3328 llvm_unreachable("Unknown overflow instruction!");
3330 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
3331 Value = DAG.getNode(ISD::ADD, dl, Op.getValueType(), LHS, RHS);
3332 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
3335 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
3336 Value = DAG.getNode(ISD::ADD, dl, Op.getValueType(), LHS, RHS);
3337 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, Value, LHS);
3340 ARMcc = DAG.getConstant(ARMCC::VC, dl, MVT::i32);
3341 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
3342 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
3345 ARMcc = DAG.getConstant(ARMCC::HS, dl, MVT::i32);
3346 Value = DAG.getNode(ISD::SUB, dl, Op.getValueType(), LHS, RHS);
3347 OverflowCmp = DAG.getNode(ARMISD::CMP, dl, MVT::Glue, LHS, RHS);
3351 return std::make_pair(Value, OverflowCmp);
3356 ARMTargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
3357 // Let legalize expand this if it isn't a legal type yet.
3358 if (!DAG.getTargetLoweringInfo().isTypeLegal(Op.getValueType()))
3361 SDValue Value, OverflowCmp;
3363 std::tie(Value, OverflowCmp) = getARMXALUOOp(Op, DAG, ARMcc);
3364 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3366 // We use 0 and 1 as false and true values.
3367 SDValue TVal = DAG.getConstant(1, dl, MVT::i32);
3368 SDValue FVal = DAG.getConstant(0, dl, MVT::i32);
3369 EVT VT = Op.getValueType();
3371 SDValue Overflow = DAG.getNode(ARMISD::CMOV, dl, VT, TVal, FVal,
3372 ARMcc, CCR, OverflowCmp);
3374 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);
3375 return DAG.getNode(ISD::MERGE_VALUES, dl, VTs, Value, Overflow);
3379 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
3380 SDValue Cond = Op.getOperand(0);
3381 SDValue SelectTrue = Op.getOperand(1);
3382 SDValue SelectFalse = Op.getOperand(2);
3384 unsigned Opc = Cond.getOpcode();
3386 if (Cond.getResNo() == 1 &&
3387 (Opc == ISD::SADDO || Opc == ISD::UADDO || Opc == ISD::SSUBO ||
3388 Opc == ISD::USUBO)) {
3389 if (!DAG.getTargetLoweringInfo().isTypeLegal(Cond->getValueType(0)))
3392 SDValue Value, OverflowCmp;
3394 std::tie(Value, OverflowCmp) = getARMXALUOOp(Cond, DAG, ARMcc);
3395 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3396 EVT VT = Op.getValueType();
3398 return getCMOV(dl, VT, SelectTrue, SelectFalse, ARMcc, CCR,
3404 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
3405 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
3407 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
3408 const ConstantSDNode *CMOVTrue =
3409 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
3410 const ConstantSDNode *CMOVFalse =
3411 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
3413 if (CMOVTrue && CMOVFalse) {
3414 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
3415 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
3419 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
3421 False = SelectFalse;
3422 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
3427 if (True.getNode() && False.getNode()) {
3428 EVT VT = Op.getValueType();
3429 SDValue ARMcc = Cond.getOperand(2);
3430 SDValue CCR = Cond.getOperand(3);
3431 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
3432 assert(True.getValueType() == VT);
3433 return getCMOV(dl, VT, True, False, ARMcc, CCR, Cmp, DAG);
3438 // ARM's BooleanContents value is UndefinedBooleanContent. Mask out the
3439 // undefined bits before doing a full-word comparison with zero.
3440 Cond = DAG.getNode(ISD::AND, dl, Cond.getValueType(), Cond,
3441 DAG.getConstant(1, dl, Cond.getValueType()));
3443 return DAG.getSelectCC(dl, Cond,
3444 DAG.getConstant(0, dl, Cond.getValueType()),
3445 SelectTrue, SelectFalse, ISD::SETNE);
3448 static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
3449 bool &swpCmpOps, bool &swpVselOps) {
3450 // Start by selecting the GE condition code for opcodes that return true for
3452 if (CC == ISD::SETUGE || CC == ISD::SETOGE || CC == ISD::SETOLE ||
3454 CondCode = ARMCC::GE;
3456 // and GT for opcodes that return false for 'equality'.
3457 else if (CC == ISD::SETUGT || CC == ISD::SETOGT || CC == ISD::SETOLT ||
3459 CondCode = ARMCC::GT;
3461 // Since we are constrained to GE/GT, if the opcode contains 'less', we need
3462 // to swap the compare operands.
3463 if (CC == ISD::SETOLE || CC == ISD::SETULE || CC == ISD::SETOLT ||
3467 // Both GT and GE are ordered comparisons, and return false for 'unordered'.
3468 // If we have an unordered opcode, we need to swap the operands to the VSEL
3469 // instruction (effectively negating the condition).
3471 // This also has the effect of swapping which one of 'less' or 'greater'
3472 // returns true, so we also swap the compare operands. It also switches
3473 // whether we return true for 'equality', so we compensate by picking the
3474 // opposite condition code to our original choice.
3475 if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE ||
3476 CC == ISD::SETUGT) {
3477 swpCmpOps = !swpCmpOps;
3478 swpVselOps = !swpVselOps;
3479 CondCode = CondCode == ARMCC::GT ? ARMCC::GE : ARMCC::GT;
3482 // 'ordered' is 'anything but unordered', so use the VS condition code and
3483 // swap the VSEL operands.
3484 if (CC == ISD::SETO) {
3485 CondCode = ARMCC::VS;
3489 // 'unordered or not equal' is 'anything but equal', so use the EQ condition
3490 // code and swap the VSEL operands.
3491 if (CC == ISD::SETUNE) {
3492 CondCode = ARMCC::EQ;
3497 SDValue ARMTargetLowering::getCMOV(SDLoc dl, EVT VT, SDValue FalseVal,
3498 SDValue TrueVal, SDValue ARMcc, SDValue CCR,
3499 SDValue Cmp, SelectionDAG &DAG) const {
3500 if (Subtarget->isFPOnlySP() && VT == MVT::f64) {
3501 FalseVal = DAG.getNode(ARMISD::VMOVRRD, dl,
3502 DAG.getVTList(MVT::i32, MVT::i32), FalseVal);
3503 TrueVal = DAG.getNode(ARMISD::VMOVRRD, dl,
3504 DAG.getVTList(MVT::i32, MVT::i32), TrueVal);
3506 SDValue TrueLow = TrueVal.getValue(0);
3507 SDValue TrueHigh = TrueVal.getValue(1);
3508 SDValue FalseLow = FalseVal.getValue(0);
3509 SDValue FalseHigh = FalseVal.getValue(1);
3511 SDValue Low = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseLow, TrueLow,
3513 SDValue High = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseHigh, TrueHigh,
3514 ARMcc, CCR, duplicateCmp(Cmp, DAG));
3516 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Low, High);
3518 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,
3523 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
3524 EVT VT = Op.getValueType();
3525 SDValue LHS = Op.getOperand(0);
3526 SDValue RHS = Op.getOperand(1);
3527 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3528 SDValue TrueVal = Op.getOperand(2);
3529 SDValue FalseVal = Op.getOperand(3);
3532 if (Subtarget->isFPOnlySP() && LHS.getValueType() == MVT::f64) {
3533 DAG.getTargetLoweringInfo().softenSetCCOperands(DAG, MVT::f64, LHS, RHS, CC,
3536 // If softenSetCCOperands only returned one value, we should compare it to
3538 if (!RHS.getNode()) {
3539 RHS = DAG.getConstant(0, dl, LHS.getValueType());
3544 if (LHS.getValueType() == MVT::i32) {
3545 // Try to generate VSEL on ARMv8.
3546 // The VSEL instruction can't use all the usual ARM condition
3547 // codes: it only has two bits to select the condition code, so it's
3548 // constrained to use only GE, GT, VS and EQ.
3550 // To implement all the various ISD::SETXXX opcodes, we sometimes need to
3551 // swap the operands of the previous compare instruction (effectively
3552 // inverting the compare condition, swapping 'less' and 'greater') and
3553 // sometimes need to swap the operands to the VSEL (which inverts the
3554 // condition in the sense of firing whenever the previous condition didn't)
3555 if (Subtarget->hasFPARMv8() && (TrueVal.getValueType() == MVT::f32 ||
3556 TrueVal.getValueType() == MVT::f64)) {
3557 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3558 if (CondCode == ARMCC::LT || CondCode == ARMCC::LE ||
3559 CondCode == ARMCC::VC || CondCode == ARMCC::NE) {
3560 CC = ISD::getSetCCInverse(CC, true);
3561 std::swap(TrueVal, FalseVal);
3566 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3567 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3568 return getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
3571 ARMCC::CondCodes CondCode, CondCode2;
3572 FPCCToARMCC(CC, CondCode, CondCode2);
3574 // Try to generate VMAXNM/VMINNM on ARMv8.
3575 if (Subtarget->hasFPARMv8() && (TrueVal.getValueType() == MVT::f32 ||
3576 TrueVal.getValueType() == MVT::f64)) {
3577 // We can use VMAXNM/VMINNM for a compare followed by a select with the
3578 // same operands, as follows:
3579 // c = fcmp [?gt, ?ge, ?lt, ?le] a, b
3581 // In NoNaNsFPMath the CC will have been changed from, e.g., 'ogt' to 'gt'.
3582 bool swapSides = false;
3583 if (!getTargetMachine().Options.NoNaNsFPMath) {
3584 // transformability may depend on which way around we compare
3592 // the non-NaN should be RHS
3593 swapSides = DAG.isKnownNeverNaN(LHS) && !DAG.isKnownNeverNaN(RHS);
3599 // the non-NaN should be LHS
3600 swapSides = DAG.isKnownNeverNaN(RHS) && !DAG.isKnownNeverNaN(LHS);
3604 swapSides = swapSides || (LHS == FalseVal && RHS == TrueVal);
3606 CC = ISD::getSetCCSwappedOperands(CC);
3607 std::swap(LHS, RHS);
3609 if (LHS == TrueVal && RHS == FalseVal) {
3610 bool canTransform = true;
3611 // FIXME: FastMathFlags::noSignedZeros() doesn't appear reachable from here
3612 if (!getTargetMachine().Options.UnsafeFPMath &&
3613 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) {
3614 const ConstantFPSDNode *Zero;
3621 // RHS must not be -0
3622 canTransform = (Zero = dyn_cast<ConstantFPSDNode>(RHS)) &&
3623 !Zero->isNegative();
3628 // LHS must not be -0
3629 canTransform = (Zero = dyn_cast<ConstantFPSDNode>(LHS)) &&
3630 !Zero->isNegative();
3635 // RHS must not be +0
3636 canTransform = (Zero = dyn_cast<ConstantFPSDNode>(RHS)) &&
3642 // LHS must not be +0
3643 canTransform = (Zero = dyn_cast<ConstantFPSDNode>(LHS)) &&
3649 // Note: If one of the elements in a pair is a number and the other
3650 // element is NaN, the corresponding result element is the number.
3651 // This is consistent with the IEEE 754-2008 standard.
3652 // Therefore, a > b ? a : b <=> vmax(a,b), if b is constant and a is NaN
3658 if (!DAG.isKnownNeverNaN(RHS))
3660 return DAG.getNode(ARMISD::VMAXNM, dl, VT, LHS, RHS);
3663 if (!DAG.isKnownNeverNaN(LHS))
3667 return DAG.getNode(ARMISD::VMAXNM, dl, VT, LHS, RHS);
3670 if (!DAG.isKnownNeverNaN(RHS))
3672 return DAG.getNode(ARMISD::VMINNM, dl, VT, LHS, RHS);
3675 if (!DAG.isKnownNeverNaN(LHS))
3679 return DAG.getNode(ARMISD::VMINNM, dl, VT, LHS, RHS);
3684 bool swpCmpOps = false;
3685 bool swpVselOps = false;
3686 checkVSELConstraints(CC, CondCode, swpCmpOps, swpVselOps);
3688 if (CondCode == ARMCC::GT || CondCode == ARMCC::GE ||
3689 CondCode == ARMCC::VS || CondCode == ARMCC::EQ) {
3691 std::swap(LHS, RHS);
3693 std::swap(TrueVal, FalseVal);
3697 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
3698 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
3699 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3700 SDValue Result = getCMOV(dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp, DAG);
3701 if (CondCode2 != ARMCC::AL) {
3702 SDValue ARMcc2 = DAG.getConstant(CondCode2, dl, MVT::i32);
3703 // FIXME: Needs another CMP because flag can have but one use.
3704 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
3705 Result = getCMOV(dl, VT, Result, TrueVal, ARMcc2, CCR, Cmp2, DAG);
3710 /// canChangeToInt - Given the fp compare operand, return true if it is suitable
3711 /// to morph to an integer compare sequence.
3712 static bool canChangeToInt(SDValue Op, bool &SeenZero,
3713 const ARMSubtarget *Subtarget) {
3714 SDNode *N = Op.getNode();
3715 if (!N->hasOneUse())
3716 // Otherwise it requires moving the value from fp to integer registers.
3718 if (!N->getNumValues())
3720 EVT VT = Op.getValueType();
3721 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
3722 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
3723 // vmrs are very slow, e.g. cortex-a8.
3726 if (isFloatingPointZero(Op)) {
3730 return ISD::isNormalLoad(N);
3733 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
3734 if (isFloatingPointZero(Op))
3735 return DAG.getConstant(0, SDLoc(Op), MVT::i32);
3737 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
3738 return DAG.getLoad(MVT::i32, SDLoc(Op),
3739 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(),
3740 Ld->isVolatile(), Ld->isNonTemporal(),
3741 Ld->isInvariant(), Ld->getAlignment());
3743 llvm_unreachable("Unknown VFP cmp argument!");
3746 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
3747 SDValue &RetVal1, SDValue &RetVal2) {
3750 if (isFloatingPointZero(Op)) {
3751 RetVal1 = DAG.getConstant(0, dl, MVT::i32);
3752 RetVal2 = DAG.getConstant(0, dl, MVT::i32);
3756 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
3757 SDValue Ptr = Ld->getBasePtr();
3758 RetVal1 = DAG.getLoad(MVT::i32, dl,
3759 Ld->getChain(), Ptr,
3760 Ld->getPointerInfo(),
3761 Ld->isVolatile(), Ld->isNonTemporal(),
3762 Ld->isInvariant(), Ld->getAlignment());
3764 EVT PtrType = Ptr.getValueType();
3765 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
3766 SDValue NewPtr = DAG.getNode(ISD::ADD, dl,
3767 PtrType, Ptr, DAG.getConstant(4, dl, PtrType));
3768 RetVal2 = DAG.getLoad(MVT::i32, dl,
3769 Ld->getChain(), NewPtr,
3770 Ld->getPointerInfo().getWithOffset(4),
3771 Ld->isVolatile(), Ld->isNonTemporal(),
3772 Ld->isInvariant(), NewAlign);
3776 llvm_unreachable("Unknown VFP cmp argument!");
3779 /// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
3780 /// f32 and even f64 comparisons to integer ones.
3782 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
3783 SDValue Chain = Op.getOperand(0);
3784 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3785 SDValue LHS = Op.getOperand(2);
3786 SDValue RHS = Op.getOperand(3);
3787 SDValue Dest = Op.getOperand(4);
3790 bool LHSSeenZero = false;
3791 bool LHSOk = canChangeToInt(LHS, LHSSeenZero, Subtarget);
3792 bool RHSSeenZero = false;
3793 bool RHSOk = canChangeToInt(RHS, RHSSeenZero, Subtarget);
3794 if (LHSOk && RHSOk && (LHSSeenZero || RHSSeenZero)) {
3795 // If unsafe fp math optimization is enabled and there are no other uses of
3796 // the CMP operands, and the condition code is EQ or NE, we can optimize it
3797 // to an integer comparison.
3798 if (CC == ISD::SETOEQ)
3800 else if (CC == ISD::SETUNE)
3803 SDValue Mask = DAG.getConstant(0x7fffffff, dl, MVT::i32);
3805 if (LHS.getValueType() == MVT::f32) {
3806 LHS = DAG.getNode(ISD::AND, dl, MVT::i32,
3807 bitcastf32Toi32(LHS, DAG), Mask);
3808 RHS = DAG.getNode(ISD::AND, dl, MVT::i32,
3809 bitcastf32Toi32(RHS, DAG), Mask);
3810 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3811 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3812 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
3813 Chain, Dest, ARMcc, CCR, Cmp);
3818 expandf64Toi32(LHS, DAG, LHS1, LHS2);
3819 expandf64Toi32(RHS, DAG, RHS1, RHS2);
3820 LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask);
3821 RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask);
3822 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3823 ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
3824 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
3825 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
3826 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops);
3832 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
3833 SDValue Chain = Op.getOperand(0);
3834 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3835 SDValue LHS = Op.getOperand(2);
3836 SDValue RHS = Op.getOperand(3);
3837 SDValue Dest = Op.getOperand(4);
3840 if (Subtarget->isFPOnlySP() && LHS.getValueType() == MVT::f64) {
3841 DAG.getTargetLoweringInfo().softenSetCCOperands(DAG, MVT::f64, LHS, RHS, CC,
3844 // If softenSetCCOperands only returned one value, we should compare it to
3846 if (!RHS.getNode()) {
3847 RHS = DAG.getConstant(0, dl, LHS.getValueType());
3852 if (LHS.getValueType() == MVT::i32) {
3854 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3855 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3856 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
3857 Chain, Dest, ARMcc, CCR, Cmp);
3860 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3862 if (getTargetMachine().Options.UnsafeFPMath &&
3863 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
3864 CC == ISD::SETNE || CC == ISD::SETUNE)) {
3865 SDValue Result = OptimizeVFPBrcond(Op, DAG);
3866 if (Result.getNode())
3870 ARMCC::CondCodes CondCode, CondCode2;
3871 FPCCToARMCC(CC, CondCode, CondCode2);
3873 SDValue ARMcc = DAG.getConstant(CondCode, dl, MVT::i32);
3874 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
3875 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3876 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
3877 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
3878 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
3879 if (CondCode2 != ARMCC::AL) {
3880 ARMcc = DAG.getConstant(CondCode2, dl, MVT::i32);
3881 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
3882 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops);
3887 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
3888 SDValue Chain = Op.getOperand(0);
3889 SDValue Table = Op.getOperand(1);
3890 SDValue Index = Op.getOperand(2);
3893 EVT PTy = getPointerTy(DAG.getDataLayout());
3894 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
3895 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
3896 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI);
3897 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, dl, PTy));
3898 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
3899 if (Subtarget->isThumb2()) {
3900 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
3901 // which does another jump to the destination. This also makes it easier
3902 // to translate it to TBB / TBH later.
3903 // FIXME: This might not work if the function is extremely large.
3904 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
3905 Addr, Op.getOperand(2), JTI);
3907 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
3908 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
3909 MachinePointerInfo::getJumpTable(),
3910 false, false, false, 0);
3911 Chain = Addr.getValue(1);
3912 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
3913 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
3915 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
3916 MachinePointerInfo::getJumpTable(),
3917 false, false, false, 0);
3918 Chain = Addr.getValue(1);
3919 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI);
3923 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
3924 EVT VT = Op.getValueType();
3927 if (Op.getValueType().getVectorElementType() == MVT::i32) {
3928 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32)
3930 return DAG.UnrollVectorOp(Op.getNode());
3933 assert(Op.getOperand(0).getValueType() == MVT::v4f32 &&
3934 "Invalid type for custom lowering!");
3935 if (VT != MVT::v4i16)
3936 return DAG.UnrollVectorOp(Op.getNode());
3938 Op = DAG.getNode(Op.getOpcode(), dl, MVT::v4i32, Op.getOperand(0));
3939 return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
3942 SDValue ARMTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const {
3943 EVT VT = Op.getValueType();
3945 return LowerVectorFP_TO_INT(Op, DAG);
3946 if (Subtarget->isFPOnlySP() && Op.getOperand(0).getValueType() == MVT::f64) {
3948 if (Op.getOpcode() == ISD::FP_TO_SINT)
3949 LC = RTLIB::getFPTOSINT(Op.getOperand(0).getValueType(),
3952 LC = RTLIB::getFPTOUINT(Op.getOperand(0).getValueType(),
3954 return makeLibCall(DAG, LC, Op.getValueType(), &Op.getOperand(0), 1,
3955 /*isSigned*/ false, SDLoc(Op)).first;
3961 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
3962 EVT VT = Op.getValueType();
3965 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) {
3966 if (VT.getVectorElementType() == MVT::f32)
3968 return DAG.UnrollVectorOp(Op.getNode());
3971 assert(Op.getOperand(0).getValueType() == MVT::v4i16 &&
3972 "Invalid type for custom lowering!");
3973 if (VT != MVT::v4f32)
3974 return DAG.UnrollVectorOp(Op.getNode());
3978 switch (Op.getOpcode()) {
3979 default: llvm_unreachable("Invalid opcode!");
3980 case ISD::SINT_TO_FP:
3981 CastOpc = ISD::SIGN_EXTEND;
3982 Opc = ISD::SINT_TO_FP;
3984 case ISD::UINT_TO_FP:
3985 CastOpc = ISD::ZERO_EXTEND;
3986 Opc = ISD::UINT_TO_FP;
3990 Op = DAG.getNode(CastOpc, dl, MVT::v4i32, Op.getOperand(0));
3991 return DAG.getNode(Opc, dl, VT, Op);
3994 SDValue ARMTargetLowering::LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const {
3995 EVT VT = Op.getValueType();
3997 return LowerVectorINT_TO_FP(Op, DAG);
3998 if (Subtarget->isFPOnlySP() && Op.getValueType() == MVT::f64) {
4000 if (Op.getOpcode() == ISD::SINT_TO_FP)
4001 LC = RTLIB::getSINTTOFP(Op.getOperand(0).getValueType(),
4004 LC = RTLIB::getUINTTOFP(Op.getOperand(0).getValueType(),
4006 return makeLibCall(DAG, LC, Op.getValueType(), &Op.getOperand(0), 1,
4007 /*isSigned*/ false, SDLoc(Op)).first;
4013 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
4014 // Implement fcopysign with a fabs and a conditional fneg.
4015 SDValue Tmp0 = Op.getOperand(0);
4016 SDValue Tmp1 = Op.getOperand(1);
4018 EVT VT = Op.getValueType();
4019 EVT SrcVT = Tmp1.getValueType();
4020 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
4021 Tmp0.getOpcode() == ARMISD::VMOVDRR;
4022 bool UseNEON = !InGPR && Subtarget->hasNEON();
4025 // Use VBSL to copy the sign bit.
4026 unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80);
4027 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
4028 DAG.getTargetConstant(EncodedVal, dl, MVT::i32));
4029 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
4031 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT,
4032 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
4033 DAG.getConstant(32, dl, MVT::i32));
4034 else /*if (VT == MVT::f32)*/
4035 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
4036 if (SrcVT == MVT::f32) {
4037 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
4039 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT,
4040 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
4041 DAG.getConstant(32, dl, MVT::i32));
4042 } else if (VT == MVT::f32)
4043 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64,
4044 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
4045 DAG.getConstant(32, dl, MVT::i32));
4046 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
4047 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
4049 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff),
4051 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
4052 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
4053 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
4055 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
4056 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
4057 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
4058 if (VT == MVT::f32) {
4059 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
4060 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
4061 DAG.getConstant(0, dl, MVT::i32));
4063 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
4069 // Bitcast operand 1 to i32.
4070 if (SrcVT == MVT::f64)
4071 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
4073 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
4075 // Or in the signbit with integer operations.
4076 SDValue Mask1 = DAG.getConstant(0x80000000, dl, MVT::i32);
4077 SDValue Mask2 = DAG.getConstant(0x7fffffff, dl, MVT::i32);
4078 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
4079 if (VT == MVT::f32) {
4080 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
4081 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
4082 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
4083 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
4086 // f64: Or the high part with signbit and then combine two parts.
4087 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
4089 SDValue Lo = Tmp0.getValue(0);
4090 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
4091 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
4092 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
4095 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
4096 MachineFunction &MF = DAG.getMachineFunction();
4097 MachineFrameInfo *MFI = MF.getFrameInfo();
4098 MFI->setReturnAddressIsTaken(true);
4100 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
4103 EVT VT = Op.getValueType();
4105 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4107 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
4108 SDValue Offset = DAG.getConstant(4, dl, MVT::i32);
4109 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
4110 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
4111 MachinePointerInfo(), false, false, false, 0);
4114 // Return LR, which contains the return address. Mark it an implicit live-in.
4115 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
4116 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
4119 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
4120 const ARMBaseRegisterInfo &ARI =
4121 *static_cast<const ARMBaseRegisterInfo*>(RegInfo);
4122 MachineFunction &MF = DAG.getMachineFunction();
4123 MachineFrameInfo *MFI = MF.getFrameInfo();
4124 MFI->setFrameAddressIsTaken(true);
4126 EVT VT = Op.getValueType();
4127 SDLoc dl(Op); // FIXME probably not meaningful
4128 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4129 unsigned FrameReg = ARI.getFrameRegister(MF);
4130 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
4132 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
4133 MachinePointerInfo(),
4134 false, false, false, 0);
4138 // FIXME? Maybe this could be a TableGen attribute on some registers and
4139 // this table could be generated automatically from RegInfo.
4140 unsigned ARMTargetLowering::getRegisterByName(const char* RegName, EVT VT,
4141 SelectionDAG &DAG) const {
4142 unsigned Reg = StringSwitch<unsigned>(RegName)
4143 .Case("sp", ARM::SP)
4147 report_fatal_error(Twine("Invalid register name \""
4148 + StringRef(RegName) + "\"."));
4151 // Result is 64 bit value so split into two 32 bit values and return as a
4153 static void ExpandREAD_REGISTER(SDNode *N, SmallVectorImpl<SDValue> &Results,
4154 SelectionDAG &DAG) {
4157 // This function is only supposed to be called for i64 type destination.
4158 assert(N->getValueType(0) == MVT::i64
4159 && "ExpandREAD_REGISTER called for non-i64 type result.");
4161 SDValue Read = DAG.getNode(ISD::READ_REGISTER, DL,
4162 DAG.getVTList(MVT::i32, MVT::i32, MVT::Other),
4166 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Read.getValue(0),
4168 Results.push_back(Read.getOperand(0));
4171 /// ExpandBITCAST - If the target supports VFP, this function is called to
4172 /// expand a bit convert where either the source or destination type is i64 to
4173 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
4174 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
4175 /// vectors), since the legalizer won't know what to do with that.
4176 static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) {
4177 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4179 SDValue Op = N->getOperand(0);
4181 // This function is only supposed to be called for i64 types, either as the
4182 // source or destination of the bit convert.
4183 EVT SrcVT = Op.getValueType();
4184 EVT DstVT = N->getValueType(0);
4185 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
4186 "ExpandBITCAST called for non-i64 type");
4188 // Turn i64->f64 into VMOVDRR.
4189 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
4190 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
4191 DAG.getConstant(0, dl, MVT::i32));
4192 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
4193 DAG.getConstant(1, dl, MVT::i32));
4194 return DAG.getNode(ISD::BITCAST, dl, DstVT,
4195 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
4198 // Turn f64->i64 into VMOVRRD.
4199 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
4201 if (DAG.getDataLayout().isBigEndian() && SrcVT.isVector() &&
4202 SrcVT.getVectorNumElements() > 1)
4203 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
4204 DAG.getVTList(MVT::i32, MVT::i32),
4205 DAG.getNode(ARMISD::VREV64, dl, SrcVT, Op));
4207 Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
4208 DAG.getVTList(MVT::i32, MVT::i32), Op);
4209 // Merge the pieces into a single i64 value.
4210 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
4216 /// getZeroVector - Returns a vector of specified type with all zero elements.
4217 /// Zero vectors are used to represent vector negation and in those cases
4218 /// will be implemented with the NEON VNEG instruction. However, VNEG does
4219 /// not support i64 elements, so sometimes the zero vectors will need to be
4220 /// explicitly constructed. Regardless, use a canonical VMOV to create the
4222 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, SDLoc dl) {
4223 assert(VT.isVector() && "Expected a vector type");
4224 // The canonical modified immediate encoding of a zero vector is....0!
4225 SDValue EncodedVal = DAG.getTargetConstant(0, dl, MVT::i32);
4226 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
4227 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
4228 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
4231 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
4232 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
4233 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
4234 SelectionDAG &DAG) const {
4235 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4236 EVT VT = Op.getValueType();
4237 unsigned VTBits = VT.getSizeInBits();
4239 SDValue ShOpLo = Op.getOperand(0);
4240 SDValue ShOpHi = Op.getOperand(1);
4241 SDValue ShAmt = Op.getOperand(2);
4243 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
4245 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
4247 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
4248 DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
4249 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
4250 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
4251 DAG.getConstant(VTBits, dl, MVT::i32));
4252 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
4253 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4254 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
4256 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4257 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
4258 ISD::SETGE, ARMcc, DAG, dl);
4259 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
4260 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
4263 SDValue Ops[2] = { Lo, Hi };
4264 return DAG.getMergeValues(Ops, dl);
4267 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
4268 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
4269 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
4270 SelectionDAG &DAG) const {
4271 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
4272 EVT VT = Op.getValueType();
4273 unsigned VTBits = VT.getSizeInBits();
4275 SDValue ShOpLo = Op.getOperand(0);
4276 SDValue ShOpHi = Op.getOperand(1);
4277 SDValue ShAmt = Op.getOperand(2);
4280 assert(Op.getOpcode() == ISD::SHL_PARTS);
4281 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
4282 DAG.getConstant(VTBits, dl, MVT::i32), ShAmt);
4283 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
4284 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
4285 DAG.getConstant(VTBits, dl, MVT::i32));
4286 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
4287 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
4289 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
4290 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
4291 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, dl, MVT::i32),
4292 ISD::SETGE, ARMcc, DAG, dl);
4293 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
4294 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
4297 SDValue Ops[2] = { Lo, Hi };
4298 return DAG.getMergeValues(Ops, dl);
4301 SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
4302 SelectionDAG &DAG) const {
4303 // The rounding mode is in bits 23:22 of the FPSCR.
4304 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
4305 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
4306 // so that the shift + and get folded into a bitfield extract.
4308 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
4309 DAG.getConstant(Intrinsic::arm_get_fpscr, dl,
4311 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
4312 DAG.getConstant(1U << 22, dl, MVT::i32));
4313 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
4314 DAG.getConstant(22, dl, MVT::i32));
4315 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
4316 DAG.getConstant(3, dl, MVT::i32));
4319 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
4320 const ARMSubtarget *ST) {
4322 EVT VT = N->getValueType(0);
4323 if (VT.isVector()) {
4324 assert(ST->hasNEON());
4326 // Compute the least significant set bit: LSB = X & -X
4327 SDValue X = N->getOperand(0);
4328 SDValue NX = DAG.getNode(ISD::SUB, dl, VT, getZeroVector(VT, DAG, dl), X);
4329 SDValue LSB = DAG.getNode(ISD::AND, dl, VT, X, NX);
4331 EVT ElemTy = VT.getVectorElementType();
4333 if (ElemTy == MVT::i8) {
4334 // Compute with: cttz(x) = ctpop(lsb - 1)
4335 SDValue One = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
4336 DAG.getTargetConstant(1, dl, ElemTy));
4337 SDValue Bits = DAG.getNode(ISD::SUB, dl, VT, LSB, One);
4338 return DAG.getNode(ISD::CTPOP, dl, VT, Bits);
4341 if ((ElemTy == MVT::i16 || ElemTy == MVT::i32) &&
4342 (N->getOpcode() == ISD::CTTZ_ZERO_UNDEF)) {
4343 // Compute with: cttz(x) = (width - 1) - ctlz(lsb), if x != 0
4344 unsigned NumBits = ElemTy.getSizeInBits();
4345 SDValue WidthMinus1 =
4346 DAG.getNode(ARMISD::VMOVIMM, dl, VT,
4347 DAG.getTargetConstant(NumBits - 1, dl, ElemTy));
4348 SDValue CTLZ = DAG.getNode(ISD::CTLZ, dl, VT, LSB);
4349 return DAG.getNode(ISD::SUB, dl, VT, WidthMinus1, CTLZ);
4352 // Compute with: cttz(x) = ctpop(lsb - 1)
4354 // Since we can only compute the number of bits in a byte with vcnt.8, we
4355 // have to gather the result with pairwise addition (vpaddl) for i16, i32,
4360 if (ElemTy == MVT::i64) {
4361 // Load constant 0xffff'ffff'ffff'ffff to register.
4362 SDValue FF = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
4363 DAG.getTargetConstant(0x1eff, dl, MVT::i32));
4364 Bits = DAG.getNode(ISD::ADD, dl, VT, LSB, FF);
4366 SDValue One = DAG.getNode(ARMISD::VMOVIMM, dl, VT,
4367 DAG.getTargetConstant(1, dl, ElemTy));
4368 Bits = DAG.getNode(ISD::SUB, dl, VT, LSB, One);
4371 // Count #bits with vcnt.8.
4372 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8;
4373 SDValue BitsVT8 = DAG.getNode(ISD::BITCAST, dl, VT8Bit, Bits);
4374 SDValue Cnt8 = DAG.getNode(ISD::CTPOP, dl, VT8Bit, BitsVT8);
4376 // Gather the #bits with vpaddl (pairwise add.)
4377 EVT VT16Bit = VT.is64BitVector() ? MVT::v4i16 : MVT::v8i16;
4378 SDValue Cnt16 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT16Bit,
4379 DAG.getTargetConstant(Intrinsic::arm_neon_vpaddlu, dl, MVT::i32),
4381 if (ElemTy == MVT::i16)
4384 EVT VT32Bit = VT.is64BitVector() ? MVT::v2i32 : MVT::v4i32;
4385 SDValue Cnt32 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT32Bit,
4386 DAG.getTargetConstant(Intrinsic::arm_neon_vpaddlu, dl, MVT::i32),
4388 if (ElemTy == MVT::i32)
4391 assert(ElemTy == MVT::i64);
4392 SDValue Cnt64 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
4393 DAG.getTargetConstant(Intrinsic::arm_neon_vpaddlu, dl, MVT::i32),
4398 if (!ST->hasV6T2Ops())
4401 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
4402 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
4405 /// getCTPOP16BitCounts - Returns a v8i8/v16i8 vector containing the bit-count
4406 /// for each 16-bit element from operand, repeated. The basic idea is to
4407 /// leverage vcnt to get the 8-bit counts, gather and add the results.
4409 /// Trace for v4i16:
4410 /// input = [v0 v1 v2 v3 ] (vi 16-bit element)
4411 /// cast: N0 = [w0 w1 w2 w3 w4 w5 w6 w7] (v0 = [w0 w1], wi 8-bit element)
4412 /// vcnt: N1 = [b0 b1 b2 b3 b4 b5 b6 b7] (bi = bit-count of 8-bit element wi)
4413 /// vrev: N2 = [b1 b0 b3 b2 b5 b4 b7 b6]
4414 /// [b0 b1 b2 b3 b4 b5 b6 b7]
4415 /// +[b1 b0 b3 b2 b5 b4 b7 b6]
4416 /// N3=N1+N2 = [k0 k0 k1 k1 k2 k2 k3 k3] (k0 = b0+b1 = bit-count of 16-bit v0,
4417 /// vuzp: = [k0 k1 k2 k3 k0 k1 k2 k3] each ki is 8-bits)
4418 static SDValue getCTPOP16BitCounts(SDNode *N, SelectionDAG &DAG) {
4419 EVT VT = N->getValueType(0);
4422 EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8;
4423 SDValue N0 = DAG.getNode(ISD::BITCAST, DL, VT8Bit, N->getOperand(0));
4424 SDValue N1 = DAG.getNode(ISD::CTPOP, DL, VT8Bit, N0);
4425 SDValue N2 = DAG.getNode(ARMISD::VREV16, DL, VT8Bit, N1);
4426 SDValue N3 = DAG.getNode(ISD::ADD, DL, VT8Bit, N1, N2);
4427 return DAG.getNode(ARMISD::VUZP, DL, VT8Bit, N3, N3);
4430 /// lowerCTPOP16BitElements - Returns a v4i16/v8i16 vector containing the
4431 /// bit-count for each 16-bit element from the operand. We need slightly
4432 /// different sequencing for v4i16 and v8i16 to stay within NEON's available
4433 /// 64/128-bit registers.
4435 /// Trace for v4i16:
4436 /// input = [v0 v1 v2 v3 ] (vi 16-bit element)
4437 /// v8i8: BitCounts = [k0 k1 k2 k3 k0 k1 k2 k3 ] (ki is the bit-count of vi)
4438 /// v8i16:Extended = [k0 k1 k2 k3 k0 k1 k2 k3 ]
4439 /// v4i16:Extracted = [k0 k1 k2 k3 ]
4440 static SDValue lowerCTPOP16BitElements(SDNode *N, SelectionDAG &DAG) {
4441 EVT VT = N->getValueType(0);
4444 SDValue BitCounts = getCTPOP16BitCounts(N, DAG);
4445 if (VT.is64BitVector()) {
4446 SDValue Extended = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v8i16, BitCounts);
4447 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, Extended,
4448 DAG.getIntPtrConstant(0, DL));
4450 SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v8i8,
4451 BitCounts, DAG.getIntPtrConstant(0, DL));
4452 return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v8i16, Extracted);
4456 /// lowerCTPOP32BitElements - Returns a v2i32/v4i32 vector containing the
4457 /// bit-count for each 32-bit element from the operand. The idea here is
4458 /// to split the vector into 16-bit elements, leverage the 16-bit count
4459 /// routine, and then combine the results.
4461 /// Trace for v2i32 (v4i32 similar with Extracted/Extended exchanged):
4462 /// input = [v0 v1 ] (vi: 32-bit elements)
4463 /// Bitcast = [w0 w1 w2 w3 ] (wi: 16-bit elements, v0 = [w0 w1])
4464 /// Counts16 = [k0 k1 k2 k3 ] (ki: 16-bit elements, bit-count of wi)
4465 /// vrev: N0 = [k1 k0 k3 k2 ]
4467 /// N1 =+[k1 k0 k3 k2 ]
4469 /// N2 =+[k1 k3 k0 k2 ]
4471 /// Extended =+[k1 k3 k0 k2 ]
4473 /// Extracted=+[k1 k3 ]
4475 static SDValue lowerCTPOP32BitElements(SDNode *N, SelectionDAG &DAG) {
4476 EVT VT = N->getValueType(0);
4479 EVT VT16Bit = VT.is64BitVector() ? MVT::v4i16 : MVT::v8i16;
4481 SDValue Bitcast = DAG.getNode(ISD::BITCAST, DL, VT16Bit, N->getOperand(0));
4482 SDValue Counts16 = lowerCTPOP16BitElements(Bitcast.getNode(), DAG);
4483 SDValue N0 = DAG.getNode(ARMISD::VREV32, DL, VT16Bit, Counts16);
4484 SDValue N1 = DAG.getNode(ISD::ADD, DL, VT16Bit, Counts16, N0);
4485 SDValue N2 = DAG.getNode(ARMISD::VUZP, DL, VT16Bit, N1, N1);
4487 if (VT.is64BitVector()) {
4488 SDValue Extended = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v4i32, N2);
4489 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i32, Extended,
4490 DAG.getIntPtrConstant(0, DL));
4492 SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, N2,
4493 DAG.getIntPtrConstant(0, DL));
4494 return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v4i32, Extracted);
4498 static SDValue LowerCTPOP(SDNode *N, SelectionDAG &DAG,
4499 const ARMSubtarget *ST) {
4500 EVT VT = N->getValueType(0);
4502 assert(ST->hasNEON() && "Custom ctpop lowering requires NEON.");
4503 assert((VT == MVT::v2i32 || VT == MVT::v4i32 ||
4504 VT == MVT::v4i16 || VT == MVT::v8i16) &&
4505 "Unexpected type for custom ctpop lowering");
4507 if (VT.getVectorElementType() == MVT::i32)
4508 return lowerCTPOP32BitElements(N, DAG);
4510 return lowerCTPOP16BitElements(N, DAG);
4513 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
4514 const ARMSubtarget *ST) {
4515 EVT VT = N->getValueType(0);
4521 // Lower vector shifts on NEON to use VSHL.
4522 assert(ST->hasNEON() && "unexpected vector shift");
4524 // Left shifts translate directly to the vshiftu intrinsic.
4525 if (N->getOpcode() == ISD::SHL)
4526 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
4527 DAG.getConstant(Intrinsic::arm_neon_vshiftu, dl,
4529 N->getOperand(0), N->getOperand(1));
4531 assert((N->getOpcode() == ISD::SRA ||
4532 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
4534 // NEON uses the same intrinsics for both left and right shifts. For
4535 // right shifts, the shift amounts are negative, so negate the vector of
4537 EVT ShiftVT = N->getOperand(1).getValueType();
4538 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
4539 getZeroVector(ShiftVT, DAG, dl),
4541 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
4542 Intrinsic::arm_neon_vshifts :
4543 Intrinsic::arm_neon_vshiftu);
4544 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
4545 DAG.getConstant(vshiftInt, dl, MVT::i32),
4546 N->getOperand(0), NegatedCount);
4549 static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
4550 const ARMSubtarget *ST) {
4551 EVT VT = N->getValueType(0);
4554 // We can get here for a node like i32 = ISD::SHL i32, i64
4558 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
4559 "Unknown shift to lower!");
4561 // We only lower SRA, SRL of 1 here, all others use generic lowering.
4562 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
4563 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
4566 // If we are in thumb mode, we don't have RRX.
4567 if (ST->isThumb1Only()) return SDValue();
4569 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
4570 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
4571 DAG.getConstant(0, dl, MVT::i32));
4572 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
4573 DAG.getConstant(1, dl, MVT::i32));
4575 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
4576 // captures the result into a carry flag.
4577 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
4578 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), Hi);
4580 // The low part is an ARMISD::RRX operand, which shifts the carry in.
4581 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
4583 // Merge the pieces into a single i64 value.
4584 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
4587 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
4588 SDValue TmpOp0, TmpOp1;
4589 bool Invert = false;
4593 SDValue Op0 = Op.getOperand(0);
4594 SDValue Op1 = Op.getOperand(1);
4595 SDValue CC = Op.getOperand(2);
4596 EVT CmpVT = Op0.getValueType().changeVectorElementTypeToInteger();
4597 EVT VT = Op.getValueType();
4598 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
4601 if (Op1.getValueType().isFloatingPoint()) {
4602 switch (SetCCOpcode) {
4603 default: llvm_unreachable("Illegal FP comparison");
4605 case ISD::SETNE: Invert = true; // Fallthrough
4607 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
4609 case ISD::SETLT: Swap = true; // Fallthrough
4611 case ISD::SETGT: Opc = ARMISD::VCGT; break;
4613 case ISD::SETLE: Swap = true; // Fallthrough
4615 case ISD::SETGE: Opc = ARMISD::VCGE; break;
4616 case ISD::SETUGE: Swap = true; // Fallthrough
4617 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
4618 case ISD::SETUGT: Swap = true; // Fallthrough
4619 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
4620 case ISD::SETUEQ: Invert = true; // Fallthrough
4622 // Expand this to (OLT | OGT).
4626 Op0 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp1, TmpOp0);
4627 Op1 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp0, TmpOp1);
4629 case ISD::SETUO: Invert = true; // Fallthrough
4631 // Expand this to (OLT | OGE).
4635 Op0 = DAG.getNode(ARMISD::VCGT, dl, CmpVT, TmpOp1, TmpOp0);
4636 Op1 = DAG.getNode(ARMISD::VCGE, dl, CmpVT, TmpOp0, TmpOp1);
4640 // Integer comparisons.
4641 switch (SetCCOpcode) {
4642 default: llvm_unreachable("Illegal integer comparison");
4643 case ISD::SETNE: Invert = true;
4644 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
4645 case ISD::SETLT: Swap = true;
4646 case ISD::SETGT: Opc = ARMISD::VCGT; break;
4647 case ISD::SETLE: Swap = true;
4648 case ISD::SETGE: Opc = ARMISD::VCGE; break;
4649 case ISD::SETULT: Swap = true;
4650 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
4651 case ISD::SETULE: Swap = true;
4652 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
4655 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
4656 if (Opc == ARMISD::VCEQ) {
4659 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
4661 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
4664 // Ignore bitconvert.
4665 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST)
4666 AndOp = AndOp.getOperand(0);
4668 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
4670 Op0 = DAG.getNode(ISD::BITCAST, dl, CmpVT, AndOp.getOperand(0));
4671 Op1 = DAG.getNode(ISD::BITCAST, dl, CmpVT, AndOp.getOperand(1));
4678 std::swap(Op0, Op1);
4680 // If one of the operands is a constant vector zero, attempt to fold the
4681 // comparison to a specialized compare-against-zero form.
4683 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
4685 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) {
4686 if (Opc == ARMISD::VCGE)
4687 Opc = ARMISD::VCLEZ;
4688 else if (Opc == ARMISD::VCGT)
4689 Opc = ARMISD::VCLTZ;
4694 if (SingleOp.getNode()) {
4697 Result = DAG.getNode(ARMISD::VCEQZ, dl, CmpVT, SingleOp); break;
4699 Result = DAG.getNode(ARMISD::VCGEZ, dl, CmpVT, SingleOp); break;
4701 Result = DAG.getNode(ARMISD::VCLEZ, dl, CmpVT, SingleOp); break;
4703 Result = DAG.getNode(ARMISD::VCGTZ, dl, CmpVT, SingleOp); break;
4705 Result = DAG.getNode(ARMISD::VCLTZ, dl, CmpVT, SingleOp); break;
4707 Result = DAG.getNode(Opc, dl, CmpVT, Op0, Op1);
4710 Result = DAG.getNode(Opc, dl, CmpVT, Op0, Op1);
4713 Result = DAG.getSExtOrTrunc(Result, dl, VT);
4716 Result = DAG.getNOT(dl, Result, VT);
4721 /// isNEONModifiedImm - Check if the specified splat value corresponds to a
4722 /// valid vector constant for a NEON instruction with a "modified immediate"
4723 /// operand (e.g., VMOV). If so, return the encoded value.
4724 static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
4725 unsigned SplatBitSize, SelectionDAG &DAG,
4726 SDLoc dl, EVT &VT, bool is128Bits,
4727 NEONModImmType type) {
4728 unsigned OpCmode, Imm;
4730 // SplatBitSize is set to the smallest size that splats the vector, so a
4731 // zero vector will always have SplatBitSize == 8. However, NEON modified
4732 // immediate instructions others than VMOV do not support the 8-bit encoding
4733 // of a zero vector, and the default encoding of zero is supposed to be the
4738 switch (SplatBitSize) {
4740 if (type != VMOVModImm)
4742 // Any 1-byte value is OK. Op=0, Cmode=1110.
4743 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
4746 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
4750 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
4751 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
4752 if ((SplatBits & ~0xff) == 0) {
4753 // Value = 0x00nn: Op=x, Cmode=100x.
4758 if ((SplatBits & ~0xff00) == 0) {
4759 // Value = 0xnn00: Op=x, Cmode=101x.
4761 Imm = SplatBits >> 8;
4767 // NEON's 32-bit VMOV supports splat values where:
4768 // * only one byte is nonzero, or
4769 // * the least significant byte is 0xff and the second byte is nonzero, or
4770 // * the least significant 2 bytes are 0xff and the third is nonzero.
4771 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
4772 if ((SplatBits & ~0xff) == 0) {
4773 // Value = 0x000000nn: Op=x, Cmode=000x.
4778 if ((SplatBits & ~0xff00) == 0) {
4779 // Value = 0x0000nn00: Op=x, Cmode=001x.
4781 Imm = SplatBits >> 8;
4784 if ((SplatBits & ~0xff0000) == 0) {
4785 // Value = 0x00nn0000: Op=x, Cmode=010x.
4787 Imm = SplatBits >> 16;
4790 if ((SplatBits & ~0xff000000) == 0) {
4791 // Value = 0xnn000000: Op=x, Cmode=011x.
4793 Imm = SplatBits >> 24;
4797 // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC
4798 if (type == OtherModImm) return SDValue();
4800 if ((SplatBits & ~0xffff) == 0 &&
4801 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
4802 // Value = 0x0000nnff: Op=x, Cmode=1100.
4804 Imm = SplatBits >> 8;
4808 if ((SplatBits & ~0xffffff) == 0 &&
4809 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
4810 // Value = 0x00nnffff: Op=x, Cmode=1101.
4812 Imm = SplatBits >> 16;
4816 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
4817 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
4818 // VMOV.I32. A (very) minor optimization would be to replicate the value
4819 // and fall through here to test for a valid 64-bit splat. But, then the
4820 // caller would also need to check and handle the change in size.
4824 if (type != VMOVModImm)
4826 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
4827 uint64_t BitMask = 0xff;
4829 unsigned ImmMask = 1;
4831 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
4832 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
4835 } else if ((SplatBits & BitMask) != 0) {
4842 if (DAG.getDataLayout().isBigEndian())
4843 // swap higher and lower 32 bit word
4844 Imm = ((Imm & 0xf) << 4) | ((Imm & 0xf0) >> 4);
4846 // Op=1, Cmode=1110.
4848 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
4853 llvm_unreachable("unexpected size for isNEONModifiedImm");
4856 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
4857 return DAG.getTargetConstant(EncodedVal, dl, MVT::i32);
4860 SDValue ARMTargetLowering::LowerConstantFP(SDValue Op, SelectionDAG &DAG,
4861 const ARMSubtarget *ST) const {
4865 bool IsDouble = Op.getValueType() == MVT::f64;
4866 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Op);
4868 // Use the default (constant pool) lowering for double constants when we have
4870 if (IsDouble && Subtarget->isFPOnlySP())
4873 // Try splatting with a VMOV.f32...
4874 APFloat FPVal = CFP->getValueAPF();
4875 int ImmVal = IsDouble ? ARM_AM::getFP64Imm(FPVal) : ARM_AM::getFP32Imm(FPVal);
4878 if (IsDouble || !ST->useNEONForSinglePrecisionFP()) {
4879 // We have code in place to select a valid ConstantFP already, no need to
4884 // It's a float and we are trying to use NEON operations where
4885 // possible. Lower it to a splat followed by an extract.
4887 SDValue NewVal = DAG.getTargetConstant(ImmVal, DL, MVT::i32);
4888 SDValue VecConstant = DAG.getNode(ARMISD::VMOVFPIMM, DL, MVT::v2f32,
4890 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecConstant,
4891 DAG.getConstant(0, DL, MVT::i32));
4894 // The rest of our options are NEON only, make sure that's allowed before
4896 if (!ST->hasNEON() || (!IsDouble && !ST->useNEONForSinglePrecisionFP()))
4900 uint64_t iVal = FPVal.bitcastToAPInt().getZExtValue();
4902 // It wouldn't really be worth bothering for doubles except for one very
4903 // important value, which does happen to match: 0.0. So make sure we don't do
4905 if (IsDouble && (iVal & 0xffffffff) != (iVal >> 32))
4908 // Try a VMOV.i32 (FIXME: i8, i16, or i64 could work too).
4909 SDValue NewVal = isNEONModifiedImm(iVal & 0xffffffffU, 0, 32, DAG, SDLoc(Op),
4910 VMovVT, false, VMOVModImm);
4911 if (NewVal != SDValue()) {
4913 SDValue VecConstant = DAG.getNode(ARMISD::VMOVIMM, DL, VMovVT,
4916 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant);
4918 // It's a float: cast and extract a vector element.
4919 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32,
4921 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant,
4922 DAG.getConstant(0, DL, MVT::i32));
4925 // Finally, try a VMVN.i32
4926 NewVal = isNEONModifiedImm(~iVal & 0xffffffffU, 0, 32, DAG, SDLoc(Op), VMovVT,
4928 if (NewVal != SDValue()) {
4930 SDValue VecConstant = DAG.getNode(ARMISD::VMVNIMM, DL, VMovVT, NewVal);
4933 return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant);
4935 // It's a float: cast and extract a vector element.
4936 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32,
4938 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant,
4939 DAG.getConstant(0, DL, MVT::i32));
4945 // check if an VEXT instruction can handle the shuffle mask when the
4946 // vector sources of the shuffle are the same.
4947 static bool isSingletonVEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
4948 unsigned NumElts = VT.getVectorNumElements();
4950 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4956 // If this is a VEXT shuffle, the immediate value is the index of the first
4957 // element. The other shuffle indices must be the successive elements after
4959 unsigned ExpectedElt = Imm;
4960 for (unsigned i = 1; i < NumElts; ++i) {
4961 // Increment the expected index. If it wraps around, just follow it
4962 // back to index zero and keep going.
4964 if (ExpectedElt == NumElts)
4967 if (M[i] < 0) continue; // ignore UNDEF indices
4968 if (ExpectedElt != static_cast<unsigned>(M[i]))
4976 static bool isVEXTMask(ArrayRef<int> M, EVT VT,
4977 bool &ReverseVEXT, unsigned &Imm) {
4978 unsigned NumElts = VT.getVectorNumElements();
4979 ReverseVEXT = false;
4981 // Assume that the first shuffle index is not UNDEF. Fail if it is.
4987 // If this is a VEXT shuffle, the immediate value is the index of the first
4988 // element. The other shuffle indices must be the successive elements after
4990 unsigned ExpectedElt = Imm;
4991 for (unsigned i = 1; i < NumElts; ++i) {
4992 // Increment the expected index. If it wraps around, it may still be
4993 // a VEXT but the source vectors must be swapped.
4995 if (ExpectedElt == NumElts * 2) {
5000 if (M[i] < 0) continue; // ignore UNDEF indices
5001 if (ExpectedElt != static_cast<unsigned>(M[i]))
5005 // Adjust the index value if the source operands will be swapped.
5012 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
5013 /// instruction with the specified blocksize. (The order of the elements
5014 /// within each block of the vector is reversed.)
5015 static bool isVREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
5016 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
5017 "Only possible block sizes for VREV are: 16, 32, 64");
5019 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
5023 unsigned NumElts = VT.getVectorNumElements();
5024 unsigned BlockElts = M[0] + 1;
5025 // If the first shuffle index is UNDEF, be optimistic.
5027 BlockElts = BlockSize / EltSz;
5029 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
5032 for (unsigned i = 0; i < NumElts; ++i) {
5033 if (M[i] < 0) continue; // ignore UNDEF indices
5034 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
5041 static bool isVTBLMask(ArrayRef<int> M, EVT VT) {
5042 // We can handle <8 x i8> vector shuffles. If the index in the mask is out of
5043 // range, then 0 is placed into the resulting vector. So pretty much any mask
5044 // of 8 elements can work here.
5045 return VT == MVT::v8i8 && M.size() == 8;
5048 // Checks whether the shuffle mask represents a vector transpose (VTRN) by
5049 // checking that pairs of elements in the shuffle mask represent the same index
5050 // in each vector, incrementing the expected index by 2 at each step.
5051 // e.g. For v1,v2 of type v4i32 a valid shuffle mask is: [0, 4, 2, 6]
5052 // v1={a,b,c,d} => x=shufflevector v1, v2 shufflemask => x={a,e,c,g}
5054 // WhichResult gives the offset for each element in the mask based on which
5055 // of the two results it belongs to.
5057 // The transpose can be represented either as:
5058 // result1 = shufflevector v1, v2, result1_shuffle_mask
5059 // result2 = shufflevector v1, v2, result2_shuffle_mask
5060 // where v1/v2 and the shuffle masks have the same number of elements
5061 // (here WhichResult (see below) indicates which result is being checked)
5064 // results = shufflevector v1, v2, shuffle_mask
5065 // where both results are returned in one vector and the shuffle mask has twice
5066 // as many elements as v1/v2 (here WhichResult will always be 0 if true) here we
5067 // want to check the low half and high half of the shuffle mask as if it were
5069 static bool isVTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5070 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
5074 unsigned NumElts = VT.getVectorNumElements();
5075 if (M.size() != NumElts && M.size() != NumElts*2)
5078 // If the mask is twice as long as the result then we need to check the upper
5079 // and lower parts of the mask
5080 for (unsigned i = 0; i < M.size(); i += NumElts) {
5081 WhichResult = M[i] == 0 ? 0 : 1;
5082 for (unsigned j = 0; j < NumElts; j += 2) {
5083 if ((M[i+j] >= 0 && (unsigned) M[i+j] != j + WhichResult) ||
5084 (M[i+j+1] >= 0 && (unsigned) M[i+j+1] != j + NumElts + WhichResult))
5089 if (M.size() == NumElts*2)
5095 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
5096 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
5097 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
5098 static bool isVTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
5099 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
5103 unsigned NumElts = VT.getVectorNumElements();
5104 if (M.size() != NumElts && M.size() != NumElts*2)
5107 for (unsigned i = 0; i < M.size(); i += NumElts) {
5108 WhichResult = M[i] == 0 ? 0 : 1;
5109 for (unsigned j = 0; j < NumElts; j += 2) {
5110 if ((M[i+j] >= 0 && (unsigned) M[i+j] != j + WhichResult) ||
5111 (M[i+j+1] >= 0 && (unsigned) M[i+j+1] != j + WhichResult))
5116 if (M.size() == NumElts*2)
5122 // Checks whether the shuffle mask represents a vector unzip (VUZP) by checking
5123 // that the mask elements are either all even and in steps of size 2 or all odd
5124 // and in steps of size 2.
5125 // e.g. For v1,v2 of type v4i32 a valid shuffle mask is: [0, 2, 4, 6]
5126 // v1={a,b,c,d} => x=shufflevector v1, v2 shufflemask => x={a,c,e,g}
5128 // Requires similar checks to that of isVTRNMask with
5129 // respect the how results are returned.
5130 static bool isVUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5131 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
5135 unsigned NumElts = VT.getVectorNumElements();
5136 if (M.size() != NumElts && M.size() != NumElts*2)
5139 for (unsigned i = 0; i < M.size(); i += NumElts) {
5140 WhichResult = M[i] == 0 ? 0 : 1;
5141 for (unsigned j = 0; j < NumElts; ++j) {
5142 if (M[i+j] >= 0 && (unsigned) M[i+j] != 2 * j + WhichResult)
5147 if (M.size() == NumElts*2)
5150 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
5151 if (VT.is64BitVector() && EltSz == 32)
5157 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
5158 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
5159 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
5160 static bool isVUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
5161 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
5165 unsigned NumElts = VT.getVectorNumElements();
5166 if (M.size() != NumElts && M.size() != NumElts*2)
5169 unsigned Half = NumElts / 2;
5170 for (unsigned i = 0; i < M.size(); i += NumElts) {
5171 WhichResult = M[i] == 0 ? 0 : 1;
5172 for (unsigned j = 0; j < NumElts; j += Half) {
5173 unsigned Idx = WhichResult;
5174 for (unsigned k = 0; k < Half; ++k) {
5175 int MIdx = M[i + j + k];
5176 if (MIdx >= 0 && (unsigned) MIdx != Idx)
5183 if (M.size() == NumElts*2)
5186 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
5187 if (VT.is64BitVector() && EltSz == 32)
5193 // Checks whether the shuffle mask represents a vector zip (VZIP) by checking
5194 // that pairs of elements of the shufflemask represent the same index in each
5195 // vector incrementing sequentially through the vectors.
5196 // e.g. For v1,v2 of type v4i32 a valid shuffle mask is: [0, 4, 1, 5]
5197 // v1={a,b,c,d} => x=shufflevector v1, v2 shufflemask => x={a,e,b,f}
5199 // Requires similar checks to that of isVTRNMask with respect the how results
5201 static bool isVZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
5202 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
5206 unsigned NumElts = VT.getVectorNumElements();
5207 if (M.size() != NumElts && M.size() != NumElts*2)
5210 for (unsigned i = 0; i < M.size(); i += NumElts) {
5211 WhichResult = M[i] == 0 ? 0 : 1;
5212 unsigned Idx = WhichResult * NumElts / 2;
5213 for (unsigned j = 0; j < NumElts; j += 2) {
5214 if ((M[i+j] >= 0 && (unsigned) M[i+j] != Idx) ||
5215 (M[i+j+1] >= 0 && (unsigned) M[i+j+1] != Idx + NumElts))
5221 if (M.size() == NumElts*2)
5224 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
5225 if (VT.is64BitVector() && EltSz == 32)
5231 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
5232 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
5233 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
5234 static bool isVZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
5235 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
5239 unsigned NumElts = VT.getVectorNumElements();
5240 if (M.size() != NumElts && M.size() != NumElts*2)
5243 for (unsigned i = 0; i < M.size(); i += NumElts) {
5244 WhichResult = M[i] == 0 ? 0 : 1;
5245 unsigned Idx = WhichResult * NumElts / 2;
5246 for (unsigned j = 0; j < NumElts; j += 2) {
5247 if ((M[i+j] >= 0 && (unsigned) M[i+j] != Idx) ||
5248 (M[i+j+1] >= 0 && (unsigned) M[i+j+1] != Idx))
5254 if (M.size() == NumElts*2)
5257 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
5258 if (VT.is64BitVector() && EltSz == 32)
5264 /// Check if \p ShuffleMask is a NEON two-result shuffle (VZIP, VUZP, VTRN),
5265 /// and return the corresponding ARMISD opcode if it is, or 0 if it isn't.
5266 static unsigned isNEONTwoResultShuffleMask(ArrayRef<int> ShuffleMask, EVT VT,
5267 unsigned &WhichResult,
5270 if (isVTRNMask(ShuffleMask, VT, WhichResult))
5271 return ARMISD::VTRN;
5272 if (isVUZPMask(ShuffleMask, VT, WhichResult))
5273 return ARMISD::VUZP;
5274 if (isVZIPMask(ShuffleMask, VT, WhichResult))
5275 return ARMISD::VZIP;
5278 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
5279 return ARMISD::VTRN;
5280 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
5281 return ARMISD::VUZP;
5282 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
5283 return ARMISD::VZIP;
5288 /// \return true if this is a reverse operation on an vector.
5289 static bool isReverseMask(ArrayRef<int> M, EVT VT) {
5290 unsigned NumElts = VT.getVectorNumElements();
5291 // Make sure the mask has the right size.
5292 if (NumElts != M.size())
5295 // Look for <15, ..., 3, -1, 1, 0>.
5296 for (unsigned i = 0; i != NumElts; ++i)
5297 if (M[i] >= 0 && M[i] != (int) (NumElts - 1 - i))
5303 // If N is an integer constant that can be moved into a register in one
5304 // instruction, return an SDValue of such a constant (will become a MOV
5305 // instruction). Otherwise return null.
5306 static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG,
5307 const ARMSubtarget *ST, SDLoc dl) {
5309 if (!isa<ConstantSDNode>(N))
5311 Val = cast<ConstantSDNode>(N)->getZExtValue();
5313 if (ST->isThumb1Only()) {
5314 if (Val <= 255 || ~Val <= 255)
5315 return DAG.getConstant(Val, dl, MVT::i32);
5317 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1)
5318 return DAG.getConstant(Val, dl, MVT::i32);
5323 // If this is a case we can't handle, return null and let the default
5324 // expansion code take care of it.
5325 SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
5326 const ARMSubtarget *ST) const {
5327 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
5329 EVT VT = Op.getValueType();
5331 APInt SplatBits, SplatUndef;
5332 unsigned SplatBitSize;
5334 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5335 if (SplatBitSize <= 64) {
5336 // Check if an immediate VMOV works.
5338 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
5339 SplatUndef.getZExtValue(), SplatBitSize,
5340 DAG, dl, VmovVT, VT.is128BitVector(),
5342 if (Val.getNode()) {
5343 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
5344 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
5347 // Try an immediate VMVN.
5348 uint64_t NegatedImm = (~SplatBits).getZExtValue();
5349 Val = isNEONModifiedImm(NegatedImm,
5350 SplatUndef.getZExtValue(), SplatBitSize,
5351 DAG, dl, VmovVT, VT.is128BitVector(),
5353 if (Val.getNode()) {
5354 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
5355 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
5358 // Use vmov.f32 to materialize other v2f32 and v4f32 splats.
5359 if ((VT == MVT::v2f32 || VT == MVT::v4f32) && SplatBitSize == 32) {
5360 int ImmVal = ARM_AM::getFP32Imm(SplatBits);
5362 SDValue Val = DAG.getTargetConstant(ImmVal, dl, MVT::i32);
5363 return DAG.getNode(ARMISD::VMOVFPIMM, dl, VT, Val);
5369 // Scan through the operands to see if only one value is used.
5371 // As an optimisation, even if more than one value is used it may be more
5372 // profitable to splat with one value then change some lanes.
5374 // Heuristically we decide to do this if the vector has a "dominant" value,
5375 // defined as splatted to more than half of the lanes.
5376 unsigned NumElts = VT.getVectorNumElements();
5377 bool isOnlyLowElement = true;
5378 bool usesOnlyOneValue = true;
5379 bool hasDominantValue = false;
5380 bool isConstant = true;
5382 // Map of the number of times a particular SDValue appears in the
5384 DenseMap<SDValue, unsigned> ValueCounts;
5386 for (unsigned i = 0; i < NumElts; ++i) {
5387 SDValue V = Op.getOperand(i);
5388 if (V.getOpcode() == ISD::UNDEF)
5391 isOnlyLowElement = false;
5392 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
5395 ValueCounts.insert(std::make_pair(V, 0));
5396 unsigned &Count = ValueCounts[V];
5398 // Is this value dominant? (takes up more than half of the lanes)
5399 if (++Count > (NumElts / 2)) {
5400 hasDominantValue = true;
5404 if (ValueCounts.size() != 1)
5405 usesOnlyOneValue = false;
5406 if (!Value.getNode() && ValueCounts.size() > 0)
5407 Value = ValueCounts.begin()->first;
5409 if (ValueCounts.size() == 0)
5410 return DAG.getUNDEF(VT);
5412 // Loads are better lowered with insert_vector_elt/ARMISD::BUILD_VECTOR.
5413 // Keep going if we are hitting this case.
5414 if (isOnlyLowElement && !ISD::isNormalLoad(Value.getNode()))
5415 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
5417 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5419 // Use VDUP for non-constant splats. For f32 constant splats, reduce to
5420 // i32 and try again.
5421 if (hasDominantValue && EltSize <= 32) {
5425 // If we are VDUPing a value that comes directly from a vector, that will
5426 // cause an unnecessary move to and from a GPR, where instead we could
5427 // just use VDUPLANE. We can only do this if the lane being extracted
5428 // is at a constant index, as the VDUP from lane instructions only have
5429 // constant-index forms.
5430 if (Value->getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
5431 isa<ConstantSDNode>(Value->getOperand(1))) {
5432 // We need to create a new undef vector to use for the VDUPLANE if the
5433 // size of the vector from which we get the value is different than the
5434 // size of the vector that we need to create. We will insert the element
5435 // such that the register coalescer will remove unnecessary copies.
5436 if (VT != Value->getOperand(0).getValueType()) {
5437 ConstantSDNode *constIndex;
5438 constIndex = dyn_cast<ConstantSDNode>(Value->getOperand(1));
5439 assert(constIndex && "The index is not a constant!");
5440 unsigned index = constIndex->getAPIntValue().getLimitedValue() %
5441 VT.getVectorNumElements();
5442 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT,
5443 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DAG.getUNDEF(VT),
5444 Value, DAG.getConstant(index, dl, MVT::i32)),
5445 DAG.getConstant(index, dl, MVT::i32));
5447 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT,
5448 Value->getOperand(0), Value->getOperand(1));
5450 N = DAG.getNode(ARMISD::VDUP, dl, VT, Value);
5452 if (!usesOnlyOneValue) {
5453 // The dominant value was splatted as 'N', but we now have to insert
5454 // all differing elements.
5455 for (unsigned I = 0; I < NumElts; ++I) {
5456 if (Op.getOperand(I) == Value)
5458 SmallVector<SDValue, 3> Ops;
5460 Ops.push_back(Op.getOperand(I));
5461 Ops.push_back(DAG.getConstant(I, dl, MVT::i32));
5462 N = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Ops);
5467 if (VT.getVectorElementType().isFloatingPoint()) {
5468 SmallVector<SDValue, 8> Ops;
5469 for (unsigned i = 0; i < NumElts; ++i)
5470 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32,
5472 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
5473 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, Ops);
5474 Val = LowerBUILD_VECTOR(Val, DAG, ST);
5476 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5478 if (usesOnlyOneValue) {
5479 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
5480 if (isConstant && Val.getNode())
5481 return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
5485 // If all elements are constants and the case above didn't get hit, fall back
5486 // to the default expansion, which will generate a load from the constant
5491 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
5493 SDValue shuffle = ReconstructShuffle(Op, DAG);
5494 if (shuffle != SDValue())
5498 // Vectors with 32- or 64-bit elements can be built by directly assigning
5499 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
5500 // will be legalized.
5501 if (EltSize >= 32) {
5502 // Do the expansion with floating-point types, since that is what the VFP
5503 // registers are defined to use, and since i64 is not legal.
5504 EVT EltVT = EVT::getFloatingPointVT(EltSize);
5505 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
5506 SmallVector<SDValue, 8> Ops;
5507 for (unsigned i = 0; i < NumElts; ++i)
5508 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i)));
5509 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops);
5510 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5513 // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
5514 // know the default expansion would otherwise fall back on something even
5515 // worse. For a vector with one or two non-undef values, that's
5516 // scalar_to_vector for the elements followed by a shuffle (provided the
5517 // shuffle is valid for the target) and materialization element by element
5518 // on the stack followed by a load for everything else.
5519 if (!isConstant && !usesOnlyOneValue) {
5520 SDValue Vec = DAG.getUNDEF(VT);
5521 for (unsigned i = 0 ; i < NumElts; ++i) {
5522 SDValue V = Op.getOperand(i);
5523 if (V.getOpcode() == ISD::UNDEF)
5525 SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i32);
5526 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
5534 // Gather data to see if the operation can be modelled as a
5535 // shuffle in combination with VEXTs.
5536 SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
5537 SelectionDAG &DAG) const {
5539 EVT VT = Op.getValueType();
5540 unsigned NumElts = VT.getVectorNumElements();
5542 SmallVector<SDValue, 2> SourceVecs;
5543 SmallVector<unsigned, 2> MinElts;
5544 SmallVector<unsigned, 2> MaxElts;
5546 for (unsigned i = 0; i < NumElts; ++i) {
5547 SDValue V = Op.getOperand(i);
5548 if (V.getOpcode() == ISD::UNDEF)
5550 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
5551 // A shuffle can only come from building a vector from various
5552 // elements of other vectors.
5554 } else if (V.getOperand(0).getValueType().getVectorElementType() !=
5555 VT.getVectorElementType()) {
5556 // This code doesn't know how to handle shuffles where the vector
5557 // element types do not match (this happens because type legalization
5558 // promotes the return type of EXTRACT_VECTOR_ELT).
5559 // FIXME: It might be appropriate to extend this code to handle
5560 // mismatched types.
5564 // Record this extraction against the appropriate vector if possible...
5565 SDValue SourceVec = V.getOperand(0);
5566 // If the element number isn't a constant, we can't effectively
5567 // analyze what's going on.
5568 if (!isa<ConstantSDNode>(V.getOperand(1)))
5570 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
5571 bool FoundSource = false;
5572 for (unsigned j = 0; j < SourceVecs.size(); ++j) {
5573 if (SourceVecs[j] == SourceVec) {
5574 if (MinElts[j] > EltNo)
5576 if (MaxElts[j] < EltNo)
5583 // Or record a new source if not...
5585 SourceVecs.push_back(SourceVec);
5586 MinElts.push_back(EltNo);
5587 MaxElts.push_back(EltNo);
5591 // Currently only do something sane when at most two source vectors
5593 if (SourceVecs.size() > 2)
5596 SDValue ShuffleSrcs[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT) };
5597 int VEXTOffsets[2] = {0, 0};
5599 // This loop extracts the usage patterns of the source vectors
5600 // and prepares appropriate SDValues for a shuffle if possible.
5601 for (unsigned i = 0; i < SourceVecs.size(); ++i) {
5602 if (SourceVecs[i].getValueType() == VT) {
5603 // No VEXT necessary
5604 ShuffleSrcs[i] = SourceVecs[i];
5607 } else if (SourceVecs[i].getValueType().getVectorNumElements() < NumElts) {
5608 // It probably isn't worth padding out a smaller vector just to
5609 // break it down again in a shuffle.
5613 // Since only 64-bit and 128-bit vectors are legal on ARM and
5614 // we've eliminated the other cases...
5615 assert(SourceVecs[i].getValueType().getVectorNumElements() == 2*NumElts &&
5616 "unexpected vector sizes in ReconstructShuffle");
5618 if (MaxElts[i] - MinElts[i] >= NumElts) {
5619 // Span too large for a VEXT to cope
5623 if (MinElts[i] >= NumElts) {
5624 // The extraction can just take the second half
5625 VEXTOffsets[i] = NumElts;
5626 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
5628 DAG.getIntPtrConstant(NumElts, dl));
5629 } else if (MaxElts[i] < NumElts) {
5630 // The extraction can just take the first half
5632 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
5634 DAG.getIntPtrConstant(0, dl));
5636 // An actual VEXT is needed
5637 VEXTOffsets[i] = MinElts[i];
5638 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
5640 DAG.getIntPtrConstant(0, dl));
5641 SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
5643 DAG.getIntPtrConstant(NumElts, dl));
5644 ShuffleSrcs[i] = DAG.getNode(ARMISD::VEXT, dl, VT, VEXTSrc1, VEXTSrc2,
5645 DAG.getConstant(VEXTOffsets[i], dl,
5650 SmallVector<int, 8> Mask;
5652 for (unsigned i = 0; i < NumElts; ++i) {
5653 SDValue Entry = Op.getOperand(i);
5654 if (Entry.getOpcode() == ISD::UNDEF) {
5659 SDValue ExtractVec = Entry.getOperand(0);
5660 int ExtractElt = cast<ConstantSDNode>(Op.getOperand(i)
5661 .getOperand(1))->getSExtValue();
5662 if (ExtractVec == SourceVecs[0]) {
5663 Mask.push_back(ExtractElt - VEXTOffsets[0]);
5665 Mask.push_back(ExtractElt + NumElts - VEXTOffsets[1]);
5669 // Final check before we try to produce nonsense...
5670 if (isShuffleMaskLegal(Mask, VT))
5671 return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1],
5677 /// isShuffleMaskLegal - Targets can use this to indicate that they only
5678 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
5679 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
5680 /// are assumed to be legal.
5682 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
5684 if (VT.getVectorNumElements() == 4 &&
5685 (VT.is128BitVector() || VT.is64BitVector())) {
5686 unsigned PFIndexes[4];
5687 for (unsigned i = 0; i != 4; ++i) {
5691 PFIndexes[i] = M[i];
5694 // Compute the index in the perfect shuffle table.
5695 unsigned PFTableIndex =
5696 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5697 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5698 unsigned Cost = (PFEntry >> 30);
5704 bool ReverseVEXT, isV_UNDEF;
5705 unsigned Imm, WhichResult;
5707 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5708 return (EltSize >= 32 ||
5709 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
5710 isVREVMask(M, VT, 64) ||
5711 isVREVMask(M, VT, 32) ||
5712 isVREVMask(M, VT, 16) ||
5713 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
5714 isVTBLMask(M, VT) ||
5715 isNEONTwoResultShuffleMask(M, VT, WhichResult, isV_UNDEF) ||
5716 ((VT == MVT::v8i16 || VT == MVT::v16i8) && isReverseMask(M, VT)));
5719 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5720 /// the specified operations to build the shuffle.
5721 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5722 SDValue RHS, SelectionDAG &DAG,
5724 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5725 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5726 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5729 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5738 OP_VUZPL, // VUZP, left result
5739 OP_VUZPR, // VUZP, right result
5740 OP_VZIPL, // VZIP, left result
5741 OP_VZIPR, // VZIP, right result
5742 OP_VTRNL, // VTRN, left result
5743 OP_VTRNR // VTRN, right result
5746 if (OpNum == OP_COPY) {
5747 if (LHSID == (1*9+2)*9+3) return LHS;
5748 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5752 SDValue OpLHS, OpRHS;
5753 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5754 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5755 EVT VT = OpLHS.getValueType();
5758 default: llvm_unreachable("Unknown shuffle opcode!");
5760 // VREV divides the vector in half and swaps within the half.
5761 if (VT.getVectorElementType() == MVT::i32 ||
5762 VT.getVectorElementType() == MVT::f32)
5763 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
5764 // vrev <4 x i16> -> VREV32
5765 if (VT.getVectorElementType() == MVT::i16)
5766 return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS);
5767 // vrev <4 x i8> -> VREV16
5768 assert(VT.getVectorElementType() == MVT::i8);
5769 return DAG.getNode(ARMISD::VREV16, dl, VT, OpLHS);
5774 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
5775 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, dl, MVT::i32));
5779 return DAG.getNode(ARMISD::VEXT, dl, VT,
5781 DAG.getConstant(OpNum - OP_VEXT1 + 1, dl, MVT::i32));
5784 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
5785 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
5788 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
5789 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
5792 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
5793 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
5797 static SDValue LowerVECTOR_SHUFFLEv8i8(SDValue Op,
5798 ArrayRef<int> ShuffleMask,
5799 SelectionDAG &DAG) {
5800 // Check to see if we can use the VTBL instruction.
5801 SDValue V1 = Op.getOperand(0);
5802 SDValue V2 = Op.getOperand(1);
5805 SmallVector<SDValue, 8> VTBLMask;
5806 for (ArrayRef<int>::iterator
5807 I = ShuffleMask.begin(), E = ShuffleMask.end(); I != E; ++I)
5808 VTBLMask.push_back(DAG.getConstant(*I, DL, MVT::i32));
5810 if (V2.getNode()->getOpcode() == ISD::UNDEF)
5811 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1,
5812 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, VTBLMask));
5814 return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2,
5815 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8, VTBLMask));
5818 static SDValue LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(SDValue Op,
5819 SelectionDAG &DAG) {
5821 SDValue OpLHS = Op.getOperand(0);
5822 EVT VT = OpLHS.getValueType();
5824 assert((VT == MVT::v8i16 || VT == MVT::v16i8) &&
5825 "Expect an v8i16/v16i8 type");
5826 OpLHS = DAG.getNode(ARMISD::VREV64, DL, VT, OpLHS);
5827 // For a v16i8 type: After the VREV, we have got <8, ...15, 8, ..., 0>. Now,
5828 // extract the first 8 bytes into the top double word and the last 8 bytes
5829 // into the bottom double word. The v8i16 case is similar.
5830 unsigned ExtractNum = (VT == MVT::v16i8) ? 8 : 4;
5831 return DAG.getNode(ARMISD::VEXT, DL, VT, OpLHS, OpLHS,
5832 DAG.getConstant(ExtractNum, DL, MVT::i32));
5835 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
5836 SDValue V1 = Op.getOperand(0);
5837 SDValue V2 = Op.getOperand(1);
5839 EVT VT = Op.getValueType();
5840 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
5842 // Convert shuffles that are directly supported on NEON to target-specific
5843 // DAG nodes, instead of keeping them as shuffles and matching them again
5844 // during code selection. This is more efficient and avoids the possibility
5845 // of inconsistencies between legalization and selection.
5846 // FIXME: floating-point vectors should be canonicalized to integer vectors
5847 // of the same time so that they get CSEd properly.
5848 ArrayRef<int> ShuffleMask = SVN->getMask();
5850 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5851 if (EltSize <= 32) {
5852 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
5853 int Lane = SVN->getSplatIndex();
5854 // If this is undef splat, generate it via "just" vdup, if possible.
5855 if (Lane == -1) Lane = 0;
5857 // Test if V1 is a SCALAR_TO_VECTOR.
5858 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5859 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
5861 // Test if V1 is a BUILD_VECTOR which is equivalent to a SCALAR_TO_VECTOR
5862 // (and probably will turn into a SCALAR_TO_VECTOR once legalization
5864 if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
5865 !isa<ConstantSDNode>(V1.getOperand(0))) {
5866 bool IsScalarToVector = true;
5867 for (unsigned i = 1, e = V1.getNumOperands(); i != e; ++i)
5868 if (V1.getOperand(i).getOpcode() != ISD::UNDEF) {
5869 IsScalarToVector = false;
5872 if (IsScalarToVector)
5873 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
5875 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
5876 DAG.getConstant(Lane, dl, MVT::i32));
5881 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
5884 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
5885 DAG.getConstant(Imm, dl, MVT::i32));
5888 if (isVREVMask(ShuffleMask, VT, 64))
5889 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
5890 if (isVREVMask(ShuffleMask, VT, 32))
5891 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
5892 if (isVREVMask(ShuffleMask, VT, 16))
5893 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
5895 if (V2->getOpcode() == ISD::UNDEF &&
5896 isSingletonVEXTMask(ShuffleMask, VT, Imm)) {
5897 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V1,
5898 DAG.getConstant(Imm, dl, MVT::i32));
5901 // Check for Neon shuffles that modify both input vectors in place.
5902 // If both results are used, i.e., if there are two shuffles with the same
5903 // source operands and with masks corresponding to both results of one of
5904 // these operations, DAG memoization will ensure that a single node is
5905 // used for both shuffles.
5906 unsigned WhichResult;
5908 if (unsigned ShuffleOpc = isNEONTwoResultShuffleMask(
5909 ShuffleMask, VT, WhichResult, isV_UNDEF)) {
5912 return DAG.getNode(ShuffleOpc, dl, DAG.getVTList(VT, VT), V1, V2)
5913 .getValue(WhichResult);
5916 // Also check for these shuffles through CONCAT_VECTORS: we canonicalize
5917 // shuffles that produce a result larger than their operands with:
5918 // shuffle(concat(v1, undef), concat(v2, undef))
5920 // shuffle(concat(v1, v2), undef)
5921 // because we can access quad vectors (see PerformVECTOR_SHUFFLECombine).
5923 // This is useful in the general case, but there are special cases where
5924 // native shuffles produce larger results: the two-result ops.
5926 // Look through the concat when lowering them:
5927 // shuffle(concat(v1, v2), undef)
5929 // concat(VZIP(v1, v2):0, :1)
5931 if (V1->getOpcode() == ISD::CONCAT_VECTORS &&
5932 V2->getOpcode() == ISD::UNDEF) {
5933 SDValue SubV1 = V1->getOperand(0);
5934 SDValue SubV2 = V1->getOperand(1);
5935 EVT SubVT = SubV1.getValueType();
5937 // We expect these to have been canonicalized to -1.
5938 assert(std::all_of(ShuffleMask.begin(), ShuffleMask.end(), [&](int i) {
5939 return i < (int)VT.getVectorNumElements();
5940 }) && "Unexpected shuffle index into UNDEF operand!");
5942 if (unsigned ShuffleOpc = isNEONTwoResultShuffleMask(
5943 ShuffleMask, SubVT, WhichResult, isV_UNDEF)) {
5946 assert((WhichResult == 0) &&
5947 "In-place shuffle of concat can only have one result!");
5948 SDValue Res = DAG.getNode(ShuffleOpc, dl, DAG.getVTList(SubVT, SubVT),
5950 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, Res.getValue(0),
5956 // If the shuffle is not directly supported and it has 4 elements, use
5957 // the PerfectShuffle-generated table to synthesize it from other shuffles.
5958 unsigned NumElts = VT.getVectorNumElements();
5960 unsigned PFIndexes[4];
5961 for (unsigned i = 0; i != 4; ++i) {
5962 if (ShuffleMask[i] < 0)
5965 PFIndexes[i] = ShuffleMask[i];
5968 // Compute the index in the perfect shuffle table.
5969 unsigned PFTableIndex =
5970 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5971 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5972 unsigned Cost = (PFEntry >> 30);
5975 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5978 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
5979 if (EltSize >= 32) {
5980 // Do the expansion with floating-point types, since that is what the VFP
5981 // registers are defined to use, and since i64 is not legal.
5982 EVT EltVT = EVT::getFloatingPointVT(EltSize);
5983 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
5984 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1);
5985 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2);
5986 SmallVector<SDValue, 8> Ops;
5987 for (unsigned i = 0; i < NumElts; ++i) {
5988 if (ShuffleMask[i] < 0)
5989 Ops.push_back(DAG.getUNDEF(EltVT));
5991 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
5992 ShuffleMask[i] < (int)NumElts ? V1 : V2,
5993 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
5996 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, Ops);
5997 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
6000 if ((VT == MVT::v8i16 || VT == MVT::v16i8) && isReverseMask(ShuffleMask, VT))
6001 return LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(Op, DAG);
6003 if (VT == MVT::v8i8) {
6004 SDValue NewOp = LowerVECTOR_SHUFFLEv8i8(Op, ShuffleMask, DAG);
6005 if (NewOp.getNode())
6012 static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
6013 // INSERT_VECTOR_ELT is legal only for immediate indexes.
6014 SDValue Lane = Op.getOperand(2);
6015 if (!isa<ConstantSDNode>(Lane))
6021 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
6022 // EXTRACT_VECTOR_ELT is legal only for immediate indexes.
6023 SDValue Lane = Op.getOperand(1);
6024 if (!isa<ConstantSDNode>(Lane))
6027 SDValue Vec = Op.getOperand(0);
6028 if (Op.getValueType() == MVT::i32 &&
6029 Vec.getValueType().getVectorElementType().getSizeInBits() < 32) {
6031 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
6037 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
6038 // The only time a CONCAT_VECTORS operation can have legal types is when
6039 // two 64-bit vectors are concatenated to a 128-bit vector.
6040 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
6041 "unexpected CONCAT_VECTORS");
6043 SDValue Val = DAG.getUNDEF(MVT::v2f64);
6044 SDValue Op0 = Op.getOperand(0);
6045 SDValue Op1 = Op.getOperand(1);
6046 if (Op0.getOpcode() != ISD::UNDEF)
6047 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
6048 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0),
6049 DAG.getIntPtrConstant(0, dl));
6050 if (Op1.getOpcode() != ISD::UNDEF)
6051 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
6052 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1),
6053 DAG.getIntPtrConstant(1, dl));
6054 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val);
6057 /// isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each
6058 /// element has been zero/sign-extended, depending on the isSigned parameter,
6059 /// from an integer type half its size.
6060 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
6062 // A v2i64 BUILD_VECTOR will have been legalized to a BITCAST from v4i32.
6063 EVT VT = N->getValueType(0);
6064 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) {
6065 SDNode *BVN = N->getOperand(0).getNode();
6066 if (BVN->getValueType(0) != MVT::v4i32 ||
6067 BVN->getOpcode() != ISD::BUILD_VECTOR)
6069 unsigned LoElt = DAG.getDataLayout().isBigEndian() ? 1 : 0;
6070 unsigned HiElt = 1 - LoElt;
6071 ConstantSDNode *Lo0 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt));
6072 ConstantSDNode *Hi0 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt));
6073 ConstantSDNode *Lo1 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt+2));
6074 ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2));
6075 if (!Lo0 || !Hi0 || !Lo1 || !Hi1)
6078 if (Hi0->getSExtValue() == Lo0->getSExtValue() >> 32 &&
6079 Hi1->getSExtValue() == Lo1->getSExtValue() >> 32)
6082 if (Hi0->isNullValue() && Hi1->isNullValue())
6088 if (N->getOpcode() != ISD::BUILD_VECTOR)
6091 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
6092 SDNode *Elt = N->getOperand(i).getNode();
6093 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
6094 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
6095 unsigned HalfSize = EltSize / 2;
6097 if (!isIntN(HalfSize, C->getSExtValue()))
6100 if (!isUIntN(HalfSize, C->getZExtValue()))
6111 /// isSignExtended - Check if a node is a vector value that is sign-extended
6112 /// or a constant BUILD_VECTOR with sign-extended elements.
6113 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
6114 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N))
6116 if (isExtendedBUILD_VECTOR(N, DAG, true))
6121 /// isZeroExtended - Check if a node is a vector value that is zero-extended
6122 /// or a constant BUILD_VECTOR with zero-extended elements.
6123 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
6124 if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N))
6126 if (isExtendedBUILD_VECTOR(N, DAG, false))
6131 static EVT getExtensionTo64Bits(const EVT &OrigVT) {
6132 if (OrigVT.getSizeInBits() >= 64)
6135 assert(OrigVT.isSimple() && "Expecting a simple value type");
6137 MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy;
6138 switch (OrigSimpleTy) {
6139 default: llvm_unreachable("Unexpected Vector Type");
6148 /// AddRequiredExtensionForVMULL - Add a sign/zero extension to extend the total
6149 /// value size to 64 bits. We need a 64-bit D register as an operand to VMULL.
6150 /// We insert the required extension here to get the vector to fill a D register.
6151 static SDValue AddRequiredExtensionForVMULL(SDValue N, SelectionDAG &DAG,
6154 unsigned ExtOpcode) {
6155 // The vector originally had a size of OrigTy. It was then extended to ExtTy.
6156 // We expect the ExtTy to be 128-bits total. If the OrigTy is less than
6157 // 64-bits we need to insert a new extension so that it will be 64-bits.
6158 assert(ExtTy.is128BitVector() && "Unexpected extension size");
6159 if (OrigTy.getSizeInBits() >= 64)
6162 // Must extend size to at least 64 bits to be used as an operand for VMULL.
6163 EVT NewVT = getExtensionTo64Bits(OrigTy);
6165 return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N);
6168 /// SkipLoadExtensionForVMULL - return a load of the original vector size that
6169 /// does not do any sign/zero extension. If the original vector is less
6170 /// than 64 bits, an appropriate extension will be added after the load to
6171 /// reach a total size of 64 bits. We have to add the extension separately
6172 /// because ARM does not have a sign/zero extending load for vectors.
6173 static SDValue SkipLoadExtensionForVMULL(LoadSDNode *LD, SelectionDAG& DAG) {
6174 EVT ExtendedTy = getExtensionTo64Bits(LD->getMemoryVT());
6176 // The load already has the right type.
6177 if (ExtendedTy == LD->getMemoryVT())
6178 return DAG.getLoad(LD->getMemoryVT(), SDLoc(LD), LD->getChain(),
6179 LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(),
6180 LD->isNonTemporal(), LD->isInvariant(),
6181 LD->getAlignment());
6183 // We need to create a zextload/sextload. We cannot just create a load
6184 // followed by a zext/zext node because LowerMUL is also run during normal
6185 // operation legalization where we can't create illegal types.
6186 return DAG.getExtLoad(LD->getExtensionType(), SDLoc(LD), ExtendedTy,
6187 LD->getChain(), LD->getBasePtr(), LD->getPointerInfo(),
6188 LD->getMemoryVT(), LD->isVolatile(), LD->isInvariant(),
6189 LD->isNonTemporal(), LD->getAlignment());
6192 /// SkipExtensionForVMULL - For a node that is a SIGN_EXTEND, ZERO_EXTEND,
6193 /// extending load, or BUILD_VECTOR with extended elements, return the
6194 /// unextended value. The unextended vector should be 64 bits so that it can
6195 /// be used as an operand to a VMULL instruction. If the original vector size
6196 /// before extension is less than 64 bits we add a an extension to resize
6197 /// the vector to 64 bits.
6198 static SDValue SkipExtensionForVMULL(SDNode *N, SelectionDAG &DAG) {
6199 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
6200 return AddRequiredExtensionForVMULL(N->getOperand(0), DAG,
6201 N->getOperand(0)->getValueType(0),
6205 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
6206 return SkipLoadExtensionForVMULL(LD, DAG);
6208 // Otherwise, the value must be a BUILD_VECTOR. For v2i64, it will
6209 // have been legalized as a BITCAST from v4i32.
6210 if (N->getOpcode() == ISD::BITCAST) {
6211 SDNode *BVN = N->getOperand(0).getNode();
6212 assert(BVN->getOpcode() == ISD::BUILD_VECTOR &&
6213 BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR");
6214 unsigned LowElt = DAG.getDataLayout().isBigEndian() ? 1 : 0;
6215 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), MVT::v2i32,
6216 BVN->getOperand(LowElt), BVN->getOperand(LowElt+2));
6218 // Construct a new BUILD_VECTOR with elements truncated to half the size.
6219 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
6220 EVT VT = N->getValueType(0);
6221 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
6222 unsigned NumElts = VT.getVectorNumElements();
6223 MVT TruncVT = MVT::getIntegerVT(EltSize);
6224 SmallVector<SDValue, 8> Ops;
6226 for (unsigned i = 0; i != NumElts; ++i) {
6227 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
6228 const APInt &CInt = C->getAPIntValue();
6229 // Element types smaller than 32 bits are not legal, so use i32 elements.
6230 // The values are implicitly truncated so sext vs. zext doesn't matter.
6231 Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), dl, MVT::i32));
6233 return DAG.getNode(ISD::BUILD_VECTOR, dl,
6234 MVT::getVectorVT(TruncVT, NumElts), Ops);
6237 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
6238 unsigned Opcode = N->getOpcode();
6239 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
6240 SDNode *N0 = N->getOperand(0).getNode();
6241 SDNode *N1 = N->getOperand(1).getNode();
6242 return N0->hasOneUse() && N1->hasOneUse() &&
6243 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
6248 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
6249 unsigned Opcode = N->getOpcode();
6250 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
6251 SDNode *N0 = N->getOperand(0).getNode();
6252 SDNode *N1 = N->getOperand(1).getNode();
6253 return N0->hasOneUse() && N1->hasOneUse() &&
6254 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
6259 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
6260 // Multiplications are only custom-lowered for 128-bit vectors so that
6261 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
6262 EVT VT = Op.getValueType();
6263 assert(VT.is128BitVector() && VT.isInteger() &&
6264 "unexpected type for custom-lowering ISD::MUL");
6265 SDNode *N0 = Op.getOperand(0).getNode();
6266 SDNode *N1 = Op.getOperand(1).getNode();
6267 unsigned NewOpc = 0;
6269 bool isN0SExt = isSignExtended(N0, DAG);
6270 bool isN1SExt = isSignExtended(N1, DAG);
6271 if (isN0SExt && isN1SExt)
6272 NewOpc = ARMISD::VMULLs;
6274 bool isN0ZExt = isZeroExtended(N0, DAG);
6275 bool isN1ZExt = isZeroExtended(N1, DAG);
6276 if (isN0ZExt && isN1ZExt)
6277 NewOpc = ARMISD::VMULLu;
6278 else if (isN1SExt || isN1ZExt) {
6279 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
6280 // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
6281 if (isN1SExt && isAddSubSExt(N0, DAG)) {
6282 NewOpc = ARMISD::VMULLs;
6284 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
6285 NewOpc = ARMISD::VMULLu;
6287 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
6289 NewOpc = ARMISD::VMULLu;
6295 if (VT == MVT::v2i64)
6296 // Fall through to expand this. It is not legal.
6299 // Other vector multiplications are legal.
6304 // Legalize to a VMULL instruction.
6307 SDValue Op1 = SkipExtensionForVMULL(N1, DAG);
6309 Op0 = SkipExtensionForVMULL(N0, DAG);
6310 assert(Op0.getValueType().is64BitVector() &&
6311 Op1.getValueType().is64BitVector() &&
6312 "unexpected types for extended operands to VMULL");
6313 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
6316 // Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during
6317 // isel lowering to take advantage of no-stall back to back vmul + vmla.
6324 SDValue N00 = SkipExtensionForVMULL(N0->getOperand(0).getNode(), DAG);
6325 SDValue N01 = SkipExtensionForVMULL(N0->getOperand(1).getNode(), DAG);
6326 EVT Op1VT = Op1.getValueType();
6327 return DAG.getNode(N0->getOpcode(), DL, VT,
6328 DAG.getNode(NewOpc, DL, VT,
6329 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
6330 DAG.getNode(NewOpc, DL, VT,
6331 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
6335 LowerSDIV_v4i8(SDValue X, SDValue Y, SDLoc dl, SelectionDAG &DAG) {
6337 // float4 xf = vcvt_f32_s32(vmovl_s16(a.lo));
6338 // float4 yf = vcvt_f32_s32(vmovl_s16(b.lo));
6339 X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X);
6340 Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y);
6341 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X);
6342 Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y);
6343 // Get reciprocal estimate.
6344 // float4 recip = vrecpeq_f32(yf);
6345 Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6346 DAG.getConstant(Intrinsic::arm_neon_vrecpe, dl, MVT::i32),
6348 // Because char has a smaller range than uchar, we can actually get away
6349 // without any newton steps. This requires that we use a weird bias
6350 // of 0xb000, however (again, this has been exhaustively tested).
6351 // float4 result = as_float4(as_int4(xf*recip) + 0xb000);
6352 X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y);
6353 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X);
6354 Y = DAG.getConstant(0xb000, dl, MVT::i32);
6355 Y = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Y, Y, Y, Y);
6356 X = DAG.getNode(ISD::ADD, dl, MVT::v4i32, X, Y);
6357 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X);
6358 // Convert back to short.
6359 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X);
6360 X = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, X);
6365 LowerSDIV_v4i16(SDValue N0, SDValue N1, SDLoc dl, SelectionDAG &DAG) {
6367 // Convert to float.
6368 // float4 yf = vcvt_f32_s32(vmovl_s16(y));
6369 // float4 xf = vcvt_f32_s32(vmovl_s16(x));
6370 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0);
6371 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1);
6372 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
6373 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
6375 // Use reciprocal estimate and one refinement step.
6376 // float4 recip = vrecpeq_f32(yf);
6377 // recip *= vrecpsq_f32(yf, recip);
6378 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6379 DAG.getConstant(Intrinsic::arm_neon_vrecpe, dl, MVT::i32),
6381 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6382 DAG.getConstant(Intrinsic::arm_neon_vrecps, dl, MVT::i32),
6384 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
6385 // Because short has a smaller range than ushort, we can actually get away
6386 // with only a single newton step. This requires that we use a weird bias
6387 // of 89, however (again, this has been exhaustively tested).
6388 // float4 result = as_float4(as_int4(xf*recip) + 0x89);
6389 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
6390 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
6391 N1 = DAG.getConstant(0x89, dl, MVT::i32);
6392 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
6393 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
6394 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
6395 // Convert back to integer and return.
6396 // return vmovn_s32(vcvt_s32_f32(result));
6397 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
6398 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
6402 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
6403 EVT VT = Op.getValueType();
6404 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
6405 "unexpected type for custom-lowering ISD::SDIV");
6408 SDValue N0 = Op.getOperand(0);
6409 SDValue N1 = Op.getOperand(1);
6412 if (VT == MVT::v8i8) {
6413 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0);
6414 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1);
6416 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
6417 DAG.getIntPtrConstant(4, dl));
6418 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
6419 DAG.getIntPtrConstant(4, dl));
6420 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
6421 DAG.getIntPtrConstant(0, dl));
6422 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
6423 DAG.getIntPtrConstant(0, dl));
6425 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16
6426 N2 = LowerSDIV_v4i8(N2, N3, dl, DAG); // v4i16
6428 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
6429 N0 = LowerCONCAT_VECTORS(N0, DAG);
6431 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0);
6434 return LowerSDIV_v4i16(N0, N1, dl, DAG);
6437 static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG) {
6438 EVT VT = Op.getValueType();
6439 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
6440 "unexpected type for custom-lowering ISD::UDIV");
6443 SDValue N0 = Op.getOperand(0);
6444 SDValue N1 = Op.getOperand(1);
6447 if (VT == MVT::v8i8) {
6448 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0);
6449 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1);
6451 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
6452 DAG.getIntPtrConstant(4, dl));
6453 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
6454 DAG.getIntPtrConstant(4, dl));
6455 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
6456 DAG.getIntPtrConstant(0, dl));
6457 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
6458 DAG.getIntPtrConstant(0, dl));
6460 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16
6461 N2 = LowerSDIV_v4i16(N2, N3, dl, DAG); // v4i16
6463 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
6464 N0 = LowerCONCAT_VECTORS(N0, DAG);
6466 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8,
6467 DAG.getConstant(Intrinsic::arm_neon_vqmovnsu, dl,
6473 // v4i16 sdiv ... Convert to float.
6474 // float4 yf = vcvt_f32_s32(vmovl_u16(y));
6475 // float4 xf = vcvt_f32_s32(vmovl_u16(x));
6476 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0);
6477 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1);
6478 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
6479 SDValue BN1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
6481 // Use reciprocal estimate and two refinement steps.
6482 // float4 recip = vrecpeq_f32(yf);
6483 // recip *= vrecpsq_f32(yf, recip);
6484 // recip *= vrecpsq_f32(yf, recip);
6485 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6486 DAG.getConstant(Intrinsic::arm_neon_vrecpe, dl, MVT::i32),
6488 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6489 DAG.getConstant(Intrinsic::arm_neon_vrecps, dl, MVT::i32),
6491 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
6492 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
6493 DAG.getConstant(Intrinsic::arm_neon_vrecps, dl, MVT::i32),
6495 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
6496 // Simply multiplying by the reciprocal estimate can leave us a few ulps
6497 // too low, so we add 2 ulps (exhaustive testing shows that this is enough,
6498 // and that it will never cause us to return an answer too large).
6499 // float4 result = as_float4(as_int4(xf*recip) + 2);
6500 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
6501 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
6502 N1 = DAG.getConstant(2, dl, MVT::i32);
6503 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
6504 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
6505 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
6506 // Convert back to integer and return.
6507 // return vmovn_u32(vcvt_s32_f32(result));
6508 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
6509 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
6513 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
6514 EVT VT = Op.getNode()->getValueType(0);
6515 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
6518 bool ExtraOp = false;
6519 switch (Op.getOpcode()) {
6520 default: llvm_unreachable("Invalid code");
6521 case ISD::ADDC: Opc = ARMISD::ADDC; break;
6522 case ISD::ADDE: Opc = ARMISD::ADDE; ExtraOp = true; break;
6523 case ISD::SUBC: Opc = ARMISD::SUBC; break;
6524 case ISD::SUBE: Opc = ARMISD::SUBE; ExtraOp = true; break;
6528 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
6530 return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
6531 Op.getOperand(1), Op.getOperand(2));
6534 SDValue ARMTargetLowering::LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const {
6535 assert(Subtarget->isTargetDarwin());
6537 // For iOS, we want to call an alternative entry point: __sincos_stret,
6538 // return values are passed via sret.
6540 SDValue Arg = Op.getOperand(0);
6541 EVT ArgVT = Arg.getValueType();
6542 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
6543 auto PtrVT = getPointerTy(DAG.getDataLayout());
6545 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6547 // Pair of floats / doubles used to pass the result.
6548 StructType *RetTy = StructType::get(ArgTy, ArgTy, nullptr);
6550 // Create stack object for sret.
6551 auto &DL = DAG.getDataLayout();
6552 const uint64_t ByteSize = DL.getTypeAllocSize(RetTy);
6553 const unsigned StackAlign = DL.getPrefTypeAlignment(RetTy);
6554 int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign, false);
6555 SDValue SRet = DAG.getFrameIndex(FrameIdx, getPointerTy(DL));
6561 Entry.Ty = RetTy->getPointerTo();
6562 Entry.isSExt = false;
6563 Entry.isZExt = false;
6564 Entry.isSRet = true;
6565 Args.push_back(Entry);
6569 Entry.isSExt = false;
6570 Entry.isZExt = false;
6571 Args.push_back(Entry);
6573 const char *LibcallName = (ArgVT == MVT::f64)
6574 ? "__sincos_stret" : "__sincosf_stret";
6575 SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy(DL));
6577 TargetLowering::CallLoweringInfo CLI(DAG);
6578 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
6579 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()), Callee,
6581 .setDiscardResult();
6583 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
6585 SDValue LoadSin = DAG.getLoad(ArgVT, dl, CallResult.second, SRet,
6586 MachinePointerInfo(), false, false, false, 0);
6588 // Address of cos field.
6589 SDValue Add = DAG.getNode(ISD::ADD, dl, PtrVT, SRet,
6590 DAG.getIntPtrConstant(ArgVT.getStoreSize(), dl));
6591 SDValue LoadCos = DAG.getLoad(ArgVT, dl, LoadSin.getValue(1), Add,
6592 MachinePointerInfo(), false, false, false, 0);
6594 SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
6595 return DAG.getNode(ISD::MERGE_VALUES, dl, Tys,
6596 LoadSin.getValue(0), LoadCos.getValue(0));
6599 static SDValue LowerAtomicLoadStore(SDValue Op, SelectionDAG &DAG) {
6600 // Monotonic load/store is legal for all targets
6601 if (cast<AtomicSDNode>(Op)->getOrdering() <= Monotonic)
6604 // Acquire/Release load/store is not legal for targets without a
6605 // dmb or equivalent available.
6609 static void ReplaceREADCYCLECOUNTER(SDNode *N,
6610 SmallVectorImpl<SDValue> &Results,
6612 const ARMSubtarget *Subtarget) {
6614 SDValue Cycles32, OutChain;
6616 if (Subtarget->hasPerfMon()) {
6617 // Under Power Management extensions, the cycle-count is:
6618 // mrc p15, #0, <Rt>, c9, c13, #0
6619 SDValue Ops[] = { N->getOperand(0), // Chain
6620 DAG.getConstant(Intrinsic::arm_mrc, DL, MVT::i32),
6621 DAG.getConstant(15, DL, MVT::i32),
6622 DAG.getConstant(0, DL, MVT::i32),
6623 DAG.getConstant(9, DL, MVT::i32),
6624 DAG.getConstant(13, DL, MVT::i32),
6625 DAG.getConstant(0, DL, MVT::i32)
6628 Cycles32 = DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL,
6629 DAG.getVTList(MVT::i32, MVT::Other), Ops);
6630 OutChain = Cycles32.getValue(1);
6632 // Intrinsic is defined to return 0 on unsupported platforms. Technically
6633 // there are older ARM CPUs that have implementation-specific ways of
6634 // obtaining this information (FIXME!).
6635 Cycles32 = DAG.getConstant(0, DL, MVT::i32);
6636 OutChain = DAG.getEntryNode();
6640 SDValue Cycles64 = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64,
6641 Cycles32, DAG.getConstant(0, DL, MVT::i32));
6642 Results.push_back(Cycles64);
6643 Results.push_back(OutChain);
6646 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6647 switch (Op.getOpcode()) {
6648 default: llvm_unreachable("Don't know how to custom lower this!");
6649 case ISD::WRITE_REGISTER: return LowerWRITE_REGISTER(Op, DAG);
6650 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6651 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
6652 case ISD::GlobalAddress:
6653 switch (Subtarget->getTargetTriple().getObjectFormat()) {
6654 default: llvm_unreachable("unknown object format");
6656 return LowerGlobalAddressWindows(Op, DAG);
6658 return LowerGlobalAddressELF(Op, DAG);
6660 return LowerGlobalAddressDarwin(Op, DAG);
6662 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6663 case ISD::SELECT: return LowerSELECT(Op, DAG);
6664 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
6665 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
6666 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
6667 case ISD::VASTART: return LowerVASTART(Op, DAG);
6668 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG, Subtarget);
6669 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget);
6670 case ISD::SINT_TO_FP:
6671 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
6672 case ISD::FP_TO_SINT:
6673 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
6674 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
6675 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6676 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6677 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
6678 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
6679 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
6680 case ISD::EH_SJLJ_SETUP_DISPATCH: return LowerEH_SJLJ_SETUP_DISPATCH(Op, DAG);
6681 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
6683 case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG);
6686 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
6687 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
6688 case ISD::SRL_PARTS:
6689 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
6691 case ISD::CTTZ_ZERO_UNDEF: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
6692 case ISD::CTPOP: return LowerCTPOP(Op.getNode(), DAG, Subtarget);
6693 case ISD::SETCC: return LowerVSETCC(Op, DAG);
6694 case ISD::ConstantFP: return LowerConstantFP(Op, DAG, Subtarget);
6695 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
6696 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6697 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
6698 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
6699 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
6700 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6701 case ISD::MUL: return LowerMUL(Op, DAG);
6702 case ISD::SDIV: return LowerSDIV(Op, DAG);
6703 case ISD::UDIV: return LowerUDIV(Op, DAG);
6707 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
6712 return LowerXALUO(Op, DAG);
6713 case ISD::ATOMIC_LOAD:
6714 case ISD::ATOMIC_STORE: return LowerAtomicLoadStore(Op, DAG);
6715 case ISD::FSINCOS: return LowerFSINCOS(Op, DAG);
6717 case ISD::UDIVREM: return LowerDivRem(Op, DAG);
6718 case ISD::DYNAMIC_STACKALLOC:
6719 if (Subtarget->getTargetTriple().isWindowsItaniumEnvironment())
6720 return LowerDYNAMIC_STACKALLOC(Op, DAG);
6721 llvm_unreachable("Don't know how to custom lower this!");
6722 case ISD::FP_ROUND: return LowerFP_ROUND(Op, DAG);
6723 case ISD::FP_EXTEND: return LowerFP_EXTEND(Op, DAG);
6727 /// ReplaceNodeResults - Replace the results of node with an illegal result
6728 /// type with new values built out of custom code.
6729 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
6730 SmallVectorImpl<SDValue>&Results,
6731 SelectionDAG &DAG) const {
6733 switch (N->getOpcode()) {
6735 llvm_unreachable("Don't know how to custom expand this!");
6736 case ISD::READ_REGISTER:
6737 ExpandREAD_REGISTER(N, Results, DAG);
6740 Res = ExpandBITCAST(N, DAG);
6744 Res = Expand64BitShift(N, DAG, Subtarget);
6746 case ISD::READCYCLECOUNTER:
6747 ReplaceREADCYCLECOUNTER(N, Results, DAG, Subtarget);
6751 Results.push_back(Res);
6754 //===----------------------------------------------------------------------===//
6755 // ARM Scheduler Hooks
6756 //===----------------------------------------------------------------------===//
6758 /// SetupEntryBlockForSjLj - Insert code into the entry block that creates and
6759 /// registers the function context.
6760 void ARMTargetLowering::
6761 SetupEntryBlockForSjLj(MachineInstr *MI, MachineBasicBlock *MBB,
6762 MachineBasicBlock *DispatchBB, int FI) const {
6763 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
6764 DebugLoc dl = MI->getDebugLoc();
6765 MachineFunction *MF = MBB->getParent();
6766 MachineRegisterInfo *MRI = &MF->getRegInfo();
6767 MachineConstantPool *MCP = MF->getConstantPool();
6768 ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>();
6769 const Function *F = MF->getFunction();
6771 bool isThumb = Subtarget->isThumb();
6772 bool isThumb2 = Subtarget->isThumb2();
6774 unsigned PCLabelId = AFI->createPICLabelUId();
6775 unsigned PCAdj = (isThumb || isThumb2) ? 4 : 8;
6776 ARMConstantPoolValue *CPV =
6777 ARMConstantPoolMBB::Create(F->getContext(), DispatchBB, PCLabelId, PCAdj);
6778 unsigned CPI = MCP->getConstantPoolIndex(CPV, 4);
6780 const TargetRegisterClass *TRC = isThumb ? &ARM::tGPRRegClass
6781 : &ARM::GPRRegClass;
6783 // Grab constant pool and fixed stack memory operands.
6784 MachineMemOperand *CPMMO =
6785 MF->getMachineMemOperand(MachinePointerInfo::getConstantPool(),
6786 MachineMemOperand::MOLoad, 4, 4);
6788 MachineMemOperand *FIMMOSt =
6789 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
6790 MachineMemOperand::MOStore, 4, 4);
6792 // Load the address of the dispatch MBB into the jump buffer.
6794 // Incoming value: jbuf
6795 // ldr.n r5, LCPI1_1
6798 // str r5, [$jbuf, #+4] ; &jbuf[1]
6799 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6800 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2LDRpci), NewVReg1)
6801 .addConstantPoolIndex(CPI)
6802 .addMemOperand(CPMMO));
6803 // Set the low bit because of thumb mode.
6804 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6806 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2ORRri), NewVReg2)
6807 .addReg(NewVReg1, RegState::Kill)
6809 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6810 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg3)
6811 .addReg(NewVReg2, RegState::Kill)
6813 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2STRi12))
6814 .addReg(NewVReg3, RegState::Kill)
6816 .addImm(36) // &jbuf[1] :: pc
6817 .addMemOperand(FIMMOSt));
6818 } else if (isThumb) {
6819 // Incoming value: jbuf
6820 // ldr.n r1, LCPI1_4
6824 // add r2, $jbuf, #+4 ; &jbuf[1]
6826 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6827 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tLDRpci), NewVReg1)
6828 .addConstantPoolIndex(CPI)
6829 .addMemOperand(CPMMO));
6830 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6831 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg2)
6832 .addReg(NewVReg1, RegState::Kill)
6834 // Set the low bit because of thumb mode.
6835 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6836 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tMOVi8), NewVReg3)
6837 .addReg(ARM::CPSR, RegState::Define)
6839 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
6840 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tORR), NewVReg4)
6841 .addReg(ARM::CPSR, RegState::Define)
6842 .addReg(NewVReg2, RegState::Kill)
6843 .addReg(NewVReg3, RegState::Kill));
6844 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
6845 BuildMI(*MBB, MI, dl, TII->get(ARM::tADDframe), NewVReg5)
6847 .addImm(36); // &jbuf[1] :: pc
6848 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tSTRi))
6849 .addReg(NewVReg4, RegState::Kill)
6850 .addReg(NewVReg5, RegState::Kill)
6852 .addMemOperand(FIMMOSt));
6854 // Incoming value: jbuf
6857 // str r1, [$jbuf, #+4] ; &jbuf[1]
6858 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6859 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::LDRi12), NewVReg1)
6860 .addConstantPoolIndex(CPI)
6862 .addMemOperand(CPMMO));
6863 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6864 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::PICADD), NewVReg2)
6865 .addReg(NewVReg1, RegState::Kill)
6866 .addImm(PCLabelId));
6867 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::STRi12))
6868 .addReg(NewVReg2, RegState::Kill)
6870 .addImm(36) // &jbuf[1] :: pc
6871 .addMemOperand(FIMMOSt));
6875 void ARMTargetLowering::EmitSjLjDispatchBlock(MachineInstr *MI,
6876 MachineBasicBlock *MBB) const {
6877 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
6878 DebugLoc dl = MI->getDebugLoc();
6879 MachineFunction *MF = MBB->getParent();
6880 MachineRegisterInfo *MRI = &MF->getRegInfo();
6881 MachineFrameInfo *MFI = MF->getFrameInfo();
6882 int FI = MFI->getFunctionContextIndex();
6884 const TargetRegisterClass *TRC = Subtarget->isThumb() ? &ARM::tGPRRegClass
6885 : &ARM::GPRnopcRegClass;
6887 // Get a mapping of the call site numbers to all of the landing pads they're
6889 DenseMap<unsigned, SmallVector<MachineBasicBlock*, 2> > CallSiteNumToLPad;
6890 unsigned MaxCSNum = 0;
6891 MachineModuleInfo &MMI = MF->getMMI();
6892 for (MachineFunction::iterator BB = MF->begin(), E = MF->end(); BB != E;
6894 if (!BB->isLandingPad()) continue;
6896 // FIXME: We should assert that the EH_LABEL is the first MI in the landing
6898 for (MachineBasicBlock::iterator
6899 II = BB->begin(), IE = BB->end(); II != IE; ++II) {
6900 if (!II->isEHLabel()) continue;
6902 MCSymbol *Sym = II->getOperand(0).getMCSymbol();
6903 if (!MMI.hasCallSiteLandingPad(Sym)) continue;
6905 SmallVectorImpl<unsigned> &CallSiteIdxs = MMI.getCallSiteLandingPad(Sym);
6906 for (SmallVectorImpl<unsigned>::iterator
6907 CSI = CallSiteIdxs.begin(), CSE = CallSiteIdxs.end();
6908 CSI != CSE; ++CSI) {
6909 CallSiteNumToLPad[*CSI].push_back(BB);
6910 MaxCSNum = std::max(MaxCSNum, *CSI);
6916 // Get an ordered list of the machine basic blocks for the jump table.
6917 std::vector<MachineBasicBlock*> LPadList;
6918 SmallPtrSet<MachineBasicBlock*, 64> InvokeBBs;
6919 LPadList.reserve(CallSiteNumToLPad.size());
6920 for (unsigned I = 1; I <= MaxCSNum; ++I) {
6921 SmallVectorImpl<MachineBasicBlock*> &MBBList = CallSiteNumToLPad[I];
6922 for (SmallVectorImpl<MachineBasicBlock*>::iterator
6923 II = MBBList.begin(), IE = MBBList.end(); II != IE; ++II) {
6924 LPadList.push_back(*II);
6925 InvokeBBs.insert((*II)->pred_begin(), (*II)->pred_end());
6929 assert(!LPadList.empty() &&
6930 "No landing pad destinations for the dispatch jump table!");
6932 // Create the jump table and associated information.
6933 MachineJumpTableInfo *JTI =
6934 MF->getOrCreateJumpTableInfo(MachineJumpTableInfo::EK_Inline);
6935 unsigned MJTI = JTI->createJumpTableIndex(LPadList);
6936 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
6938 // Create the MBBs for the dispatch code.
6940 // Shove the dispatch's address into the return slot in the function context.
6941 MachineBasicBlock *DispatchBB = MF->CreateMachineBasicBlock();
6942 DispatchBB->setIsLandingPad();
6944 MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock();
6945 unsigned trap_opcode;
6946 if (Subtarget->isThumb())
6947 trap_opcode = ARM::tTRAP;
6949 trap_opcode = Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP;
6951 BuildMI(TrapBB, dl, TII->get(trap_opcode));
6952 DispatchBB->addSuccessor(TrapBB);
6954 MachineBasicBlock *DispContBB = MF->CreateMachineBasicBlock();
6955 DispatchBB->addSuccessor(DispContBB);
6958 MF->insert(MF->end(), DispatchBB);
6959 MF->insert(MF->end(), DispContBB);
6960 MF->insert(MF->end(), TrapBB);
6962 // Insert code into the entry block that creates and registers the function
6964 SetupEntryBlockForSjLj(MI, MBB, DispatchBB, FI);
6966 MachineMemOperand *FIMMOLd =
6967 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
6968 MachineMemOperand::MOLoad |
6969 MachineMemOperand::MOVolatile, 4, 4);
6971 MachineInstrBuilder MIB;
6972 MIB = BuildMI(DispatchBB, dl, TII->get(ARM::Int_eh_sjlj_dispatchsetup));
6974 const ARMBaseInstrInfo *AII = static_cast<const ARMBaseInstrInfo*>(TII);
6975 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
6977 // Add a register mask with no preserved registers. This results in all
6978 // registers being marked as clobbered.
6979 MIB.addRegMask(RI.getNoPreservedMask());
6981 unsigned NumLPads = LPadList.size();
6982 if (Subtarget->isThumb2()) {
6983 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6984 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2LDRi12), NewVReg1)
6987 .addMemOperand(FIMMOLd));
6989 if (NumLPads < 256) {
6990 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPri))
6992 .addImm(LPadList.size()));
6994 unsigned VReg1 = MRI->createVirtualRegister(TRC);
6995 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVi16), VReg1)
6996 .addImm(NumLPads & 0xFFFF));
6998 unsigned VReg2 = VReg1;
6999 if ((NumLPads & 0xFFFF0000) != 0) {
7000 VReg2 = MRI->createVirtualRegister(TRC);
7001 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVTi16), VReg2)
7003 .addImm(NumLPads >> 16));
7006 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPrr))
7011 BuildMI(DispatchBB, dl, TII->get(ARM::t2Bcc))
7016 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
7017 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::t2LEApcrelJT),NewVReg3)
7018 .addJumpTableIndex(MJTI));
7020 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
7023 BuildMI(DispContBB, dl, TII->get(ARM::t2ADDrs), NewVReg4)
7024 .addReg(NewVReg3, RegState::Kill)
7026 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))));
7028 BuildMI(DispContBB, dl, TII->get(ARM::t2BR_JT))
7029 .addReg(NewVReg4, RegState::Kill)
7031 .addJumpTableIndex(MJTI);
7032 } else if (Subtarget->isThumb()) {
7033 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
7034 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRspi), NewVReg1)
7037 .addMemOperand(FIMMOLd));
7039 if (NumLPads < 256) {
7040 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPi8))
7044 MachineConstantPool *ConstantPool = MF->getConstantPool();
7045 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
7046 const Constant *C = ConstantInt::get(Int32Ty, NumLPads);
7048 // MachineConstantPool wants an explicit alignment.
7049 unsigned Align = MF->getDataLayout().getPrefTypeAlignment(Int32Ty);
7051 Align = MF->getDataLayout().getTypeAllocSize(C->getType());
7052 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
7054 unsigned VReg1 = MRI->createVirtualRegister(TRC);
7055 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRpci))
7056 .addReg(VReg1, RegState::Define)
7057 .addConstantPoolIndex(Idx));
7058 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPr))
7063 BuildMI(DispatchBB, dl, TII->get(ARM::tBcc))
7068 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
7069 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLSLri), NewVReg2)
7070 .addReg(ARM::CPSR, RegState::Define)
7074 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
7075 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLEApcrelJT), NewVReg3)
7076 .addJumpTableIndex(MJTI));
7078 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
7079 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg4)
7080 .addReg(ARM::CPSR, RegState::Define)
7081 .addReg(NewVReg2, RegState::Kill)
7084 MachineMemOperand *JTMMOLd =
7085 MF->getMachineMemOperand(MachinePointerInfo::getJumpTable(),
7086 MachineMemOperand::MOLoad, 4, 4);
7088 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
7089 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLDRi), NewVReg5)
7090 .addReg(NewVReg4, RegState::Kill)
7092 .addMemOperand(JTMMOLd));
7094 unsigned NewVReg6 = NewVReg5;
7095 if (RelocM == Reloc::PIC_) {
7096 NewVReg6 = MRI->createVirtualRegister(TRC);
7097 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg6)
7098 .addReg(ARM::CPSR, RegState::Define)
7099 .addReg(NewVReg5, RegState::Kill)
7103 BuildMI(DispContBB, dl, TII->get(ARM::tBR_JTr))
7104 .addReg(NewVReg6, RegState::Kill)
7105 .addJumpTableIndex(MJTI);
7107 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
7108 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRi12), NewVReg1)
7111 .addMemOperand(FIMMOLd));
7113 if (NumLPads < 256) {
7114 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPri))
7117 } else if (Subtarget->hasV6T2Ops() && isUInt<16>(NumLPads)) {
7118 unsigned VReg1 = MRI->createVirtualRegister(TRC);
7119 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVi16), VReg1)
7120 .addImm(NumLPads & 0xFFFF));
7122 unsigned VReg2 = VReg1;
7123 if ((NumLPads & 0xFFFF0000) != 0) {
7124 VReg2 = MRI->createVirtualRegister(TRC);
7125 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVTi16), VReg2)
7127 .addImm(NumLPads >> 16));
7130 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
7134 MachineConstantPool *ConstantPool = MF->getConstantPool();
7135 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
7136 const Constant *C = ConstantInt::get(Int32Ty, NumLPads);
7138 // MachineConstantPool wants an explicit alignment.
7139 unsigned Align = MF->getDataLayout().getPrefTypeAlignment(Int32Ty);
7141 Align = MF->getDataLayout().getTypeAllocSize(C->getType());
7142 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
7144 unsigned VReg1 = MRI->createVirtualRegister(TRC);
7145 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRcp))
7146 .addReg(VReg1, RegState::Define)
7147 .addConstantPoolIndex(Idx)
7149 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
7151 .addReg(VReg1, RegState::Kill));
7154 BuildMI(DispatchBB, dl, TII->get(ARM::Bcc))
7159 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
7161 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::MOVsi), NewVReg3)
7163 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))));
7164 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
7165 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::LEApcrelJT), NewVReg4)
7166 .addJumpTableIndex(MJTI));
7168 MachineMemOperand *JTMMOLd =
7169 MF->getMachineMemOperand(MachinePointerInfo::getJumpTable(),
7170 MachineMemOperand::MOLoad, 4, 4);
7171 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
7173 BuildMI(DispContBB, dl, TII->get(ARM::LDRrs), NewVReg5)
7174 .addReg(NewVReg3, RegState::Kill)
7177 .addMemOperand(JTMMOLd));
7179 if (RelocM == Reloc::PIC_) {
7180 BuildMI(DispContBB, dl, TII->get(ARM::BR_JTadd))
7181 .addReg(NewVReg5, RegState::Kill)
7183 .addJumpTableIndex(MJTI);
7185 BuildMI(DispContBB, dl, TII->get(ARM::BR_JTr))
7186 .addReg(NewVReg5, RegState::Kill)
7187 .addJumpTableIndex(MJTI);
7191 // Add the jump table entries as successors to the MBB.
7192 SmallPtrSet<MachineBasicBlock*, 8> SeenMBBs;
7193 for (std::vector<MachineBasicBlock*>::iterator
7194 I = LPadList.begin(), E = LPadList.end(); I != E; ++I) {
7195 MachineBasicBlock *CurMBB = *I;
7196 if (SeenMBBs.insert(CurMBB).second)
7197 DispContBB->addSuccessor(CurMBB);
7200 // N.B. the order the invoke BBs are processed in doesn't matter here.
7201 const MCPhysReg *SavedRegs = RI.getCalleeSavedRegs(MF);
7202 SmallVector<MachineBasicBlock*, 64> MBBLPads;
7203 for (MachineBasicBlock *BB : InvokeBBs) {
7205 // Remove the landing pad successor from the invoke block and replace it
7206 // with the new dispatch block.
7207 SmallVector<MachineBasicBlock*, 4> Successors(BB->succ_begin(),
7209 while (!Successors.empty()) {
7210 MachineBasicBlock *SMBB = Successors.pop_back_val();
7211 if (SMBB->isLandingPad()) {
7212 BB->removeSuccessor(SMBB);
7213 MBBLPads.push_back(SMBB);
7217 BB->addSuccessor(DispatchBB);
7219 // Find the invoke call and mark all of the callee-saved registers as
7220 // 'implicit defined' so that they're spilled. This prevents code from
7221 // moving instructions to before the EH block, where they will never be
7223 for (MachineBasicBlock::reverse_iterator
7224 II = BB->rbegin(), IE = BB->rend(); II != IE; ++II) {
7225 if (!II->isCall()) continue;
7227 DenseMap<unsigned, bool> DefRegs;
7228 for (MachineInstr::mop_iterator
7229 OI = II->operands_begin(), OE = II->operands_end();
7231 if (!OI->isReg()) continue;
7232 DefRegs[OI->getReg()] = true;
7235 MachineInstrBuilder MIB(*MF, &*II);
7237 for (unsigned i = 0; SavedRegs[i] != 0; ++i) {
7238 unsigned Reg = SavedRegs[i];
7239 if (Subtarget->isThumb2() &&
7240 !ARM::tGPRRegClass.contains(Reg) &&
7241 !ARM::hGPRRegClass.contains(Reg))
7243 if (Subtarget->isThumb1Only() && !ARM::tGPRRegClass.contains(Reg))
7245 if (!Subtarget->isThumb() && !ARM::GPRRegClass.contains(Reg))
7248 MIB.addReg(Reg, RegState::ImplicitDefine | RegState::Dead);
7255 // Mark all former landing pads as non-landing pads. The dispatch is the only
7257 for (SmallVectorImpl<MachineBasicBlock*>::iterator
7258 I = MBBLPads.begin(), E = MBBLPads.end(); I != E; ++I)
7259 (*I)->setIsLandingPad(false);
7261 // The instruction is gone now.
7262 MI->eraseFromParent();
7266 MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
7267 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
7268 E = MBB->succ_end(); I != E; ++I)
7271 llvm_unreachable("Expecting a BB with two successors!");
7274 /// Return the load opcode for a given load size. If load size >= 8,
7275 /// neon opcode will be returned.
7276 static unsigned getLdOpcode(unsigned LdSize, bool IsThumb1, bool IsThumb2) {
7278 return LdSize == 16 ? ARM::VLD1q32wb_fixed
7279 : LdSize == 8 ? ARM::VLD1d32wb_fixed : 0;
7281 return LdSize == 4 ? ARM::tLDRi
7282 : LdSize == 2 ? ARM::tLDRHi
7283 : LdSize == 1 ? ARM::tLDRBi : 0;
7285 return LdSize == 4 ? ARM::t2LDR_POST
7286 : LdSize == 2 ? ARM::t2LDRH_POST
7287 : LdSize == 1 ? ARM::t2LDRB_POST : 0;
7288 return LdSize == 4 ? ARM::LDR_POST_IMM
7289 : LdSize == 2 ? ARM::LDRH_POST
7290 : LdSize == 1 ? ARM::LDRB_POST_IMM : 0;
7293 /// Return the store opcode for a given store size. If store size >= 8,
7294 /// neon opcode will be returned.
7295 static unsigned getStOpcode(unsigned StSize, bool IsThumb1, bool IsThumb2) {
7297 return StSize == 16 ? ARM::VST1q32wb_fixed
7298 : StSize == 8 ? ARM::VST1d32wb_fixed : 0;
7300 return StSize == 4 ? ARM::tSTRi
7301 : StSize == 2 ? ARM::tSTRHi
7302 : StSize == 1 ? ARM::tSTRBi : 0;
7304 return StSize == 4 ? ARM::t2STR_POST
7305 : StSize == 2 ? ARM::t2STRH_POST
7306 : StSize == 1 ? ARM::t2STRB_POST : 0;
7307 return StSize == 4 ? ARM::STR_POST_IMM
7308 : StSize == 2 ? ARM::STRH_POST
7309 : StSize == 1 ? ARM::STRB_POST_IMM : 0;
7312 /// Emit a post-increment load operation with given size. The instructions
7313 /// will be added to BB at Pos.
7314 static void emitPostLd(MachineBasicBlock *BB, MachineInstr *Pos,
7315 const TargetInstrInfo *TII, DebugLoc dl,
7316 unsigned LdSize, unsigned Data, unsigned AddrIn,
7317 unsigned AddrOut, bool IsThumb1, bool IsThumb2) {
7318 unsigned LdOpc = getLdOpcode(LdSize, IsThumb1, IsThumb2);
7319 assert(LdOpc != 0 && "Should have a load opcode");
7321 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
7322 .addReg(AddrOut, RegState::Define).addReg(AddrIn)
7324 } else if (IsThumb1) {
7325 // load + update AddrIn
7326 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
7327 .addReg(AddrIn).addImm(0));
7328 MachineInstrBuilder MIB =
7329 BuildMI(*BB, Pos, dl, TII->get(ARM::tADDi8), AddrOut);
7330 MIB = AddDefaultT1CC(MIB);
7331 MIB.addReg(AddrIn).addImm(LdSize);
7332 AddDefaultPred(MIB);
7333 } else if (IsThumb2) {
7334 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
7335 .addReg(AddrOut, RegState::Define).addReg(AddrIn)
7338 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
7339 .addReg(AddrOut, RegState::Define).addReg(AddrIn)
7340 .addReg(0).addImm(LdSize));
7344 /// Emit a post-increment store operation with given size. The instructions
7345 /// will be added to BB at Pos.
7346 static void emitPostSt(MachineBasicBlock *BB, MachineInstr *Pos,
7347 const TargetInstrInfo *TII, DebugLoc dl,
7348 unsigned StSize, unsigned Data, unsigned AddrIn,
7349 unsigned AddrOut, bool IsThumb1, bool IsThumb2) {
7350 unsigned StOpc = getStOpcode(StSize, IsThumb1, IsThumb2);
7351 assert(StOpc != 0 && "Should have a store opcode");
7353 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
7354 .addReg(AddrIn).addImm(0).addReg(Data));
7355 } else if (IsThumb1) {
7356 // store + update AddrIn
7357 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc)).addReg(Data)
7358 .addReg(AddrIn).addImm(0));
7359 MachineInstrBuilder MIB =
7360 BuildMI(*BB, Pos, dl, TII->get(ARM::tADDi8), AddrOut);
7361 MIB = AddDefaultT1CC(MIB);
7362 MIB.addReg(AddrIn).addImm(StSize);
7363 AddDefaultPred(MIB);
7364 } else if (IsThumb2) {
7365 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
7366 .addReg(Data).addReg(AddrIn).addImm(StSize));
7368 AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
7369 .addReg(Data).addReg(AddrIn).addReg(0)
7375 ARMTargetLowering::EmitStructByval(MachineInstr *MI,
7376 MachineBasicBlock *BB) const {
7377 // This pseudo instruction has 3 operands: dst, src, size
7378 // We expand it to a loop if size > Subtarget->getMaxInlineSizeThreshold().
7379 // Otherwise, we will generate unrolled scalar copies.
7380 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
7381 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7382 MachineFunction::iterator It = BB;
7385 unsigned dest = MI->getOperand(0).getReg();
7386 unsigned src = MI->getOperand(1).getReg();
7387 unsigned SizeVal = MI->getOperand(2).getImm();
7388 unsigned Align = MI->getOperand(3).getImm();
7389 DebugLoc dl = MI->getDebugLoc();
7391 MachineFunction *MF = BB->getParent();
7392 MachineRegisterInfo &MRI = MF->getRegInfo();
7393 unsigned UnitSize = 0;
7394 const TargetRegisterClass *TRC = nullptr;
7395 const TargetRegisterClass *VecTRC = nullptr;
7397 bool IsThumb1 = Subtarget->isThumb1Only();
7398 bool IsThumb2 = Subtarget->isThumb2();
7402 } else if (Align & 2) {
7405 // Check whether we can use NEON instructions.
7406 if (!MF->getFunction()->hasFnAttribute(Attribute::NoImplicitFloat) &&
7407 Subtarget->hasNEON()) {
7408 if ((Align % 16 == 0) && SizeVal >= 16)
7410 else if ((Align % 8 == 0) && SizeVal >= 8)
7413 // Can't use NEON instructions.
7418 // Select the correct opcode and register class for unit size load/store
7419 bool IsNeon = UnitSize >= 8;
7420 TRC = (IsThumb1 || IsThumb2) ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
7422 VecTRC = UnitSize == 16 ? &ARM::DPairRegClass
7423 : UnitSize == 8 ? &ARM::DPRRegClass
7426 unsigned BytesLeft = SizeVal % UnitSize;
7427 unsigned LoopSize = SizeVal - BytesLeft;
7429 if (SizeVal <= Subtarget->getMaxInlineSizeThreshold()) {
7430 // Use LDR and STR to copy.
7431 // [scratch, srcOut] = LDR_POST(srcIn, UnitSize)
7432 // [destOut] = STR_POST(scratch, destIn, UnitSize)
7433 unsigned srcIn = src;
7434 unsigned destIn = dest;
7435 for (unsigned i = 0; i < LoopSize; i+=UnitSize) {
7436 unsigned srcOut = MRI.createVirtualRegister(TRC);
7437 unsigned destOut = MRI.createVirtualRegister(TRC);
7438 unsigned scratch = MRI.createVirtualRegister(IsNeon ? VecTRC : TRC);
7439 emitPostLd(BB, MI, TII, dl, UnitSize, scratch, srcIn, srcOut,
7440 IsThumb1, IsThumb2);
7441 emitPostSt(BB, MI, TII, dl, UnitSize, scratch, destIn, destOut,
7442 IsThumb1, IsThumb2);
7447 // Handle the leftover bytes with LDRB and STRB.
7448 // [scratch, srcOut] = LDRB_POST(srcIn, 1)
7449 // [destOut] = STRB_POST(scratch, destIn, 1)
7450 for (unsigned i = 0; i < BytesLeft; i++) {
7451 unsigned srcOut = MRI.createVirtualRegister(TRC);
7452 unsigned destOut = MRI.createVirtualRegister(TRC);
7453 unsigned scratch = MRI.createVirtualRegister(TRC);
7454 emitPostLd(BB, MI, TII, dl, 1, scratch, srcIn, srcOut,
7455 IsThumb1, IsThumb2);
7456 emitPostSt(BB, MI, TII, dl, 1, scratch, destIn, destOut,
7457 IsThumb1, IsThumb2);
7461 MI->eraseFromParent(); // The instruction is gone now.
7465 // Expand the pseudo op to a loop.
7468 // movw varEnd, # --> with thumb2
7470 // ldrcp varEnd, idx --> without thumb2
7471 // fallthrough --> loopMBB
7473 // PHI varPhi, varEnd, varLoop
7474 // PHI srcPhi, src, srcLoop
7475 // PHI destPhi, dst, destLoop
7476 // [scratch, srcLoop] = LDR_POST(srcPhi, UnitSize)
7477 // [destLoop] = STR_POST(scratch, destPhi, UnitSize)
7478 // subs varLoop, varPhi, #UnitSize
7480 // fallthrough --> exitMBB
7482 // epilogue to handle left-over bytes
7483 // [scratch, srcOut] = LDRB_POST(srcLoop, 1)
7484 // [destOut] = STRB_POST(scratch, destLoop, 1)
7485 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
7486 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
7487 MF->insert(It, loopMBB);
7488 MF->insert(It, exitMBB);
7490 // Transfer the remainder of BB and its successor edges to exitMBB.
7491 exitMBB->splice(exitMBB->begin(), BB,
7492 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7493 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7495 // Load an immediate to varEnd.
7496 unsigned varEnd = MRI.createVirtualRegister(TRC);
7497 if (Subtarget->useMovt(*MF)) {
7498 unsigned Vtmp = varEnd;
7499 if ((LoopSize & 0xFFFF0000) != 0)
7500 Vtmp = MRI.createVirtualRegister(TRC);
7501 AddDefaultPred(BuildMI(BB, dl,
7502 TII->get(IsThumb2 ? ARM::t2MOVi16 : ARM::MOVi16),
7503 Vtmp).addImm(LoopSize & 0xFFFF));
7505 if ((LoopSize & 0xFFFF0000) != 0)
7506 AddDefaultPred(BuildMI(BB, dl,
7507 TII->get(IsThumb2 ? ARM::t2MOVTi16 : ARM::MOVTi16),
7510 .addImm(LoopSize >> 16));
7512 MachineConstantPool *ConstantPool = MF->getConstantPool();
7513 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
7514 const Constant *C = ConstantInt::get(Int32Ty, LoopSize);
7516 // MachineConstantPool wants an explicit alignment.
7517 unsigned Align = MF->getDataLayout().getPrefTypeAlignment(Int32Ty);
7519 Align = MF->getDataLayout().getTypeAllocSize(C->getType());
7520 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
7523 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(ARM::tLDRpci)).addReg(
7524 varEnd, RegState::Define).addConstantPoolIndex(Idx));
7526 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(ARM::LDRcp)).addReg(
7527 varEnd, RegState::Define).addConstantPoolIndex(Idx).addImm(0));
7529 BB->addSuccessor(loopMBB);
7531 // Generate the loop body:
7532 // varPhi = PHI(varLoop, varEnd)
7533 // srcPhi = PHI(srcLoop, src)
7534 // destPhi = PHI(destLoop, dst)
7535 MachineBasicBlock *entryBB = BB;
7537 unsigned varLoop = MRI.createVirtualRegister(TRC);
7538 unsigned varPhi = MRI.createVirtualRegister(TRC);
7539 unsigned srcLoop = MRI.createVirtualRegister(TRC);
7540 unsigned srcPhi = MRI.createVirtualRegister(TRC);
7541 unsigned destLoop = MRI.createVirtualRegister(TRC);
7542 unsigned destPhi = MRI.createVirtualRegister(TRC);
7544 BuildMI(*BB, BB->begin(), dl, TII->get(ARM::PHI), varPhi)
7545 .addReg(varLoop).addMBB(loopMBB)
7546 .addReg(varEnd).addMBB(entryBB);
7547 BuildMI(BB, dl, TII->get(ARM::PHI), srcPhi)
7548 .addReg(srcLoop).addMBB(loopMBB)
7549 .addReg(src).addMBB(entryBB);
7550 BuildMI(BB, dl, TII->get(ARM::PHI), destPhi)
7551 .addReg(destLoop).addMBB(loopMBB)
7552 .addReg(dest).addMBB(entryBB);
7554 // [scratch, srcLoop] = LDR_POST(srcPhi, UnitSize)
7555 // [destLoop] = STR_POST(scratch, destPhi, UnitSiz)
7556 unsigned scratch = MRI.createVirtualRegister(IsNeon ? VecTRC : TRC);
7557 emitPostLd(BB, BB->end(), TII, dl, UnitSize, scratch, srcPhi, srcLoop,
7558 IsThumb1, IsThumb2);
7559 emitPostSt(BB, BB->end(), TII, dl, UnitSize, scratch, destPhi, destLoop,
7560 IsThumb1, IsThumb2);
7562 // Decrement loop variable by UnitSize.
7564 MachineInstrBuilder MIB =
7565 BuildMI(*BB, BB->end(), dl, TII->get(ARM::tSUBi8), varLoop);
7566 MIB = AddDefaultT1CC(MIB);
7567 MIB.addReg(varPhi).addImm(UnitSize);
7568 AddDefaultPred(MIB);
7570 MachineInstrBuilder MIB =
7571 BuildMI(*BB, BB->end(), dl,
7572 TII->get(IsThumb2 ? ARM::t2SUBri : ARM::SUBri), varLoop);
7573 AddDefaultCC(AddDefaultPred(MIB.addReg(varPhi).addImm(UnitSize)));
7574 MIB->getOperand(5).setReg(ARM::CPSR);
7575 MIB->getOperand(5).setIsDef(true);
7577 BuildMI(*BB, BB->end(), dl,
7578 TII->get(IsThumb1 ? ARM::tBcc : IsThumb2 ? ARM::t2Bcc : ARM::Bcc))
7579 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
7581 // loopMBB can loop back to loopMBB or fall through to exitMBB.
7582 BB->addSuccessor(loopMBB);
7583 BB->addSuccessor(exitMBB);
7585 // Add epilogue to handle BytesLeft.
7587 MachineInstr *StartOfExit = exitMBB->begin();
7589 // [scratch, srcOut] = LDRB_POST(srcLoop, 1)
7590 // [destOut] = STRB_POST(scratch, destLoop, 1)
7591 unsigned srcIn = srcLoop;
7592 unsigned destIn = destLoop;
7593 for (unsigned i = 0; i < BytesLeft; i++) {
7594 unsigned srcOut = MRI.createVirtualRegister(TRC);
7595 unsigned destOut = MRI.createVirtualRegister(TRC);
7596 unsigned scratch = MRI.createVirtualRegister(TRC);
7597 emitPostLd(BB, StartOfExit, TII, dl, 1, scratch, srcIn, srcOut,
7598 IsThumb1, IsThumb2);
7599 emitPostSt(BB, StartOfExit, TII, dl, 1, scratch, destIn, destOut,
7600 IsThumb1, IsThumb2);
7605 MI->eraseFromParent(); // The instruction is gone now.
7610 ARMTargetLowering::EmitLowered__chkstk(MachineInstr *MI,
7611 MachineBasicBlock *MBB) const {
7612 const TargetMachine &TM = getTargetMachine();
7613 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
7614 DebugLoc DL = MI->getDebugLoc();
7616 assert(Subtarget->isTargetWindows() &&
7617 "__chkstk is only supported on Windows");
7618 assert(Subtarget->isThumb2() && "Windows on ARM requires Thumb-2 mode");
7620 // __chkstk takes the number of words to allocate on the stack in R4, and
7621 // returns the stack adjustment in number of bytes in R4. This will not
7622 // clober any other registers (other than the obvious lr).
7624 // Although, technically, IP should be considered a register which may be
7625 // clobbered, the call itself will not touch it. Windows on ARM is a pure
7626 // thumb-2 environment, so there is no interworking required. As a result, we
7627 // do not expect a veneer to be emitted by the linker, clobbering IP.
7629 // Each module receives its own copy of __chkstk, so no import thunk is
7630 // required, again, ensuring that IP is not clobbered.
7632 // Finally, although some linkers may theoretically provide a trampoline for
7633 // out of range calls (which is quite common due to a 32M range limitation of
7634 // branches for Thumb), we can generate the long-call version via
7635 // -mcmodel=large, alleviating the need for the trampoline which may clobber
7638 switch (TM.getCodeModel()) {
7639 case CodeModel::Small:
7640 case CodeModel::Medium:
7641 case CodeModel::Default:
7642 case CodeModel::Kernel:
7643 BuildMI(*MBB, MI, DL, TII.get(ARM::tBL))
7644 .addImm((unsigned)ARMCC::AL).addReg(0)
7645 .addExternalSymbol("__chkstk")
7646 .addReg(ARM::R4, RegState::Implicit | RegState::Kill)
7647 .addReg(ARM::R4, RegState::Implicit | RegState::Define)
7648 .addReg(ARM::R12, RegState::Implicit | RegState::Define | RegState::Dead);
7650 case CodeModel::Large:
7651 case CodeModel::JITDefault: {
7652 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
7653 unsigned Reg = MRI.createVirtualRegister(&ARM::rGPRRegClass);
7655 BuildMI(*MBB, MI, DL, TII.get(ARM::t2MOVi32imm), Reg)
7656 .addExternalSymbol("__chkstk");
7657 BuildMI(*MBB, MI, DL, TII.get(ARM::tBLXr))
7658 .addImm((unsigned)ARMCC::AL).addReg(0)
7659 .addReg(Reg, RegState::Kill)
7660 .addReg(ARM::R4, RegState::Implicit | RegState::Kill)
7661 .addReg(ARM::R4, RegState::Implicit | RegState::Define)
7662 .addReg(ARM::R12, RegState::Implicit | RegState::Define | RegState::Dead);
7667 AddDefaultCC(AddDefaultPred(BuildMI(*MBB, MI, DL, TII.get(ARM::t2SUBrr),
7669 .addReg(ARM::SP).addReg(ARM::R4)));
7671 MI->eraseFromParent();
7676 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
7677 MachineBasicBlock *BB) const {
7678 const TargetInstrInfo *TII = Subtarget->getInstrInfo();
7679 DebugLoc dl = MI->getDebugLoc();
7680 bool isThumb2 = Subtarget->isThumb2();
7681 switch (MI->getOpcode()) {
7684 llvm_unreachable("Unexpected instr type to insert");
7686 // The Thumb2 pre-indexed stores have the same MI operands, they just
7687 // define them differently in the .td files from the isel patterns, so
7688 // they need pseudos.
7689 case ARM::t2STR_preidx:
7690 MI->setDesc(TII->get(ARM::t2STR_PRE));
7692 case ARM::t2STRB_preidx:
7693 MI->setDesc(TII->get(ARM::t2STRB_PRE));
7695 case ARM::t2STRH_preidx:
7696 MI->setDesc(TII->get(ARM::t2STRH_PRE));
7699 case ARM::STRi_preidx:
7700 case ARM::STRBi_preidx: {
7701 unsigned NewOpc = MI->getOpcode() == ARM::STRi_preidx ?
7702 ARM::STR_PRE_IMM : ARM::STRB_PRE_IMM;
7703 // Decode the offset.
7704 unsigned Offset = MI->getOperand(4).getImm();
7705 bool isSub = ARM_AM::getAM2Op(Offset) == ARM_AM::sub;
7706 Offset = ARM_AM::getAM2Offset(Offset);
7710 MachineMemOperand *MMO = *MI->memoperands_begin();
7711 BuildMI(*BB, MI, dl, TII->get(NewOpc))
7712 .addOperand(MI->getOperand(0)) // Rn_wb
7713 .addOperand(MI->getOperand(1)) // Rt
7714 .addOperand(MI->getOperand(2)) // Rn
7715 .addImm(Offset) // offset (skip GPR==zero_reg)
7716 .addOperand(MI->getOperand(5)) // pred
7717 .addOperand(MI->getOperand(6))
7718 .addMemOperand(MMO);
7719 MI->eraseFromParent();
7722 case ARM::STRr_preidx:
7723 case ARM::STRBr_preidx:
7724 case ARM::STRH_preidx: {
7726 switch (MI->getOpcode()) {
7727 default: llvm_unreachable("unexpected opcode!");
7728 case ARM::STRr_preidx: NewOpc = ARM::STR_PRE_REG; break;
7729 case ARM::STRBr_preidx: NewOpc = ARM::STRB_PRE_REG; break;
7730 case ARM::STRH_preidx: NewOpc = ARM::STRH_PRE; break;
7732 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc));
7733 for (unsigned i = 0; i < MI->getNumOperands(); ++i)
7734 MIB.addOperand(MI->getOperand(i));
7735 MI->eraseFromParent();
7739 case ARM::tMOVCCr_pseudo: {
7740 // To "insert" a SELECT_CC instruction, we actually have to insert the
7741 // diamond control-flow pattern. The incoming instruction knows the
7742 // destination vreg to set, the condition code register to branch on, the
7743 // true/false values to select between, and a branch opcode to use.
7744 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7745 MachineFunction::iterator It = BB;
7751 // cmpTY ccX, r1, r2
7753 // fallthrough --> copy0MBB
7754 MachineBasicBlock *thisMBB = BB;
7755 MachineFunction *F = BB->getParent();
7756 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7757 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7758 F->insert(It, copy0MBB);
7759 F->insert(It, sinkMBB);
7761 // Transfer the remainder of BB and its successor edges to sinkMBB.
7762 sinkMBB->splice(sinkMBB->begin(), BB,
7763 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7764 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
7766 BB->addSuccessor(copy0MBB);
7767 BB->addSuccessor(sinkMBB);
7769 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
7770 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
7773 // %FalseValue = ...
7774 // # fallthrough to sinkMBB
7777 // Update machine-CFG edges
7778 BB->addSuccessor(sinkMBB);
7781 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7784 BuildMI(*BB, BB->begin(), dl,
7785 TII->get(ARM::PHI), MI->getOperand(0).getReg())
7786 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
7787 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7789 MI->eraseFromParent(); // The pseudo instruction is gone now.
7794 case ARM::BCCZi64: {
7795 // If there is an unconditional branch to the other successor, remove it.
7796 BB->erase(std::next(MachineBasicBlock::iterator(MI)), BB->end());
7798 // Compare both parts that make up the double comparison separately for
7800 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
7802 unsigned LHS1 = MI->getOperand(1).getReg();
7803 unsigned LHS2 = MI->getOperand(2).getReg();
7805 AddDefaultPred(BuildMI(BB, dl,
7806 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
7807 .addReg(LHS1).addImm(0));
7808 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
7809 .addReg(LHS2).addImm(0)
7810 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
7812 unsigned RHS1 = MI->getOperand(3).getReg();
7813 unsigned RHS2 = MI->getOperand(4).getReg();
7814 AddDefaultPred(BuildMI(BB, dl,
7815 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
7816 .addReg(LHS1).addReg(RHS1));
7817 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
7818 .addReg(LHS2).addReg(RHS2)
7819 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
7822 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB();
7823 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
7824 if (MI->getOperand(0).getImm() == ARMCC::NE)
7825 std::swap(destMBB, exitMBB);
7827 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
7828 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
7830 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2B)).addMBB(exitMBB));
7832 BuildMI(BB, dl, TII->get(ARM::B)) .addMBB(exitMBB);
7834 MI->eraseFromParent(); // The pseudo instruction is gone now.
7838 case ARM::Int_eh_sjlj_setjmp:
7839 case ARM::Int_eh_sjlj_setjmp_nofp:
7840 case ARM::tInt_eh_sjlj_setjmp:
7841 case ARM::t2Int_eh_sjlj_setjmp:
7842 case ARM::t2Int_eh_sjlj_setjmp_nofp:
7845 case ARM::Int_eh_sjlj_setup_dispatch:
7846 EmitSjLjDispatchBlock(MI, BB);
7851 // To insert an ABS instruction, we have to insert the
7852 // diamond control-flow pattern. The incoming instruction knows the
7853 // source vreg to test against 0, the destination vreg to set,
7854 // the condition code register to branch on, the
7855 // true/false values to select between, and a branch opcode to use.
7860 // BCC (branch to SinkBB if V0 >= 0)
7861 // RSBBB: V3 = RSBri V2, 0 (compute ABS if V2 < 0)
7862 // SinkBB: V1 = PHI(V2, V3)
7863 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7864 MachineFunction::iterator BBI = BB;
7866 MachineFunction *Fn = BB->getParent();
7867 MachineBasicBlock *RSBBB = Fn->CreateMachineBasicBlock(LLVM_BB);
7868 MachineBasicBlock *SinkBB = Fn->CreateMachineBasicBlock(LLVM_BB);
7869 Fn->insert(BBI, RSBBB);
7870 Fn->insert(BBI, SinkBB);
7872 unsigned int ABSSrcReg = MI->getOperand(1).getReg();
7873 unsigned int ABSDstReg = MI->getOperand(0).getReg();
7874 bool ABSSrcKIll = MI->getOperand(1).isKill();
7875 bool isThumb2 = Subtarget->isThumb2();
7876 MachineRegisterInfo &MRI = Fn->getRegInfo();
7877 // In Thumb mode S must not be specified if source register is the SP or
7878 // PC and if destination register is the SP, so restrict register class
7879 unsigned NewRsbDstReg =
7880 MRI.createVirtualRegister(isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass);
7882 // Transfer the remainder of BB and its successor edges to sinkMBB.
7883 SinkBB->splice(SinkBB->begin(), BB,
7884 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7885 SinkBB->transferSuccessorsAndUpdatePHIs(BB);
7887 BB->addSuccessor(RSBBB);
7888 BB->addSuccessor(SinkBB);
7890 // fall through to SinkMBB
7891 RSBBB->addSuccessor(SinkBB);
7893 // insert a cmp at the end of BB
7894 AddDefaultPred(BuildMI(BB, dl,
7895 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
7896 .addReg(ABSSrcReg).addImm(0));
7898 // insert a bcc with opposite CC to ARMCC::MI at the end of BB
7900 TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)).addMBB(SinkBB)
7901 .addImm(ARMCC::getOppositeCondition(ARMCC::MI)).addReg(ARM::CPSR);
7903 // insert rsbri in RSBBB
7904 // Note: BCC and rsbri will be converted into predicated rsbmi
7905 // by if-conversion pass
7906 BuildMI(*RSBBB, RSBBB->begin(), dl,
7907 TII->get(isThumb2 ? ARM::t2RSBri : ARM::RSBri), NewRsbDstReg)
7908 .addReg(ABSSrcReg, ABSSrcKIll ? RegState::Kill : 0)
7909 .addImm(0).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
7911 // insert PHI in SinkBB,
7912 // reuse ABSDstReg to not change uses of ABS instruction
7913 BuildMI(*SinkBB, SinkBB->begin(), dl,
7914 TII->get(ARM::PHI), ABSDstReg)
7915 .addReg(NewRsbDstReg).addMBB(RSBBB)
7916 .addReg(ABSSrcReg).addMBB(BB);
7918 // remove ABS instruction
7919 MI->eraseFromParent();
7921 // return last added BB
7924 case ARM::COPY_STRUCT_BYVAL_I32:
7926 return EmitStructByval(MI, BB);
7927 case ARM::WIN__CHKSTK:
7928 return EmitLowered__chkstk(MI, BB);
7932 void ARMTargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
7933 SDNode *Node) const {
7934 const MCInstrDesc *MCID = &MI->getDesc();
7935 // Adjust potentially 's' setting instructions after isel, i.e. ADC, SBC, RSB,
7936 // RSC. Coming out of isel, they have an implicit CPSR def, but the optional
7937 // operand is still set to noreg. If needed, set the optional operand's
7938 // register to CPSR, and remove the redundant implicit def.
7940 // e.g. ADCS (..., CPSR<imp-def>) -> ADC (... opt:CPSR<def>).
7942 // Rename pseudo opcodes.
7943 unsigned NewOpc = convertAddSubFlagsOpcode(MI->getOpcode());
7945 const ARMBaseInstrInfo *TII = Subtarget->getInstrInfo();
7946 MCID = &TII->get(NewOpc);
7948 assert(MCID->getNumOperands() == MI->getDesc().getNumOperands() + 1 &&
7949 "converted opcode should be the same except for cc_out");
7953 // Add the optional cc_out operand
7954 MI->addOperand(MachineOperand::CreateReg(0, /*isDef=*/true));
7956 unsigned ccOutIdx = MCID->getNumOperands() - 1;
7958 // Any ARM instruction that sets the 's' bit should specify an optional
7959 // "cc_out" operand in the last operand position.
7960 if (!MI->hasOptionalDef() || !MCID->OpInfo[ccOutIdx].isOptionalDef()) {
7961 assert(!NewOpc && "Optional cc_out operand required");
7964 // Look for an implicit def of CPSR added by MachineInstr ctor. Remove it
7965 // since we already have an optional CPSR def.
7966 bool definesCPSR = false;
7967 bool deadCPSR = false;
7968 for (unsigned i = MCID->getNumOperands(), e = MI->getNumOperands();
7970 const MachineOperand &MO = MI->getOperand(i);
7971 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) {
7975 MI->RemoveOperand(i);
7980 assert(!NewOpc && "Optional cc_out operand required");
7983 assert(deadCPSR == !Node->hasAnyUseOfValue(1) && "inconsistent dead flag");
7985 assert(!MI->getOperand(ccOutIdx).getReg() &&
7986 "expect uninitialized optional cc_out operand");
7990 // If this instruction was defined with an optional CPSR def and its dag node
7991 // had a live implicit CPSR def, then activate the optional CPSR def.
7992 MachineOperand &MO = MI->getOperand(ccOutIdx);
7993 MO.setReg(ARM::CPSR);
7997 //===----------------------------------------------------------------------===//
7998 // ARM Optimization Hooks
7999 //===----------------------------------------------------------------------===//
8001 // Helper function that checks if N is a null or all ones constant.
8002 static inline bool isZeroOrAllOnes(SDValue N, bool AllOnes) {
8003 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
8006 return AllOnes ? C->isAllOnesValue() : C->isNullValue();
8009 // Return true if N is conditionally 0 or all ones.
8010 // Detects these expressions where cc is an i1 value:
8012 // (select cc 0, y) [AllOnes=0]
8013 // (select cc y, 0) [AllOnes=0]
8014 // (zext cc) [AllOnes=0]
8015 // (sext cc) [AllOnes=0/1]
8016 // (select cc -1, y) [AllOnes=1]
8017 // (select cc y, -1) [AllOnes=1]
8019 // Invert is set when N is the null/all ones constant when CC is false.
8020 // OtherOp is set to the alternative value of N.
8021 static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes,
8022 SDValue &CC, bool &Invert,
8024 SelectionDAG &DAG) {
8025 switch (N->getOpcode()) {
8026 default: return false;
8028 CC = N->getOperand(0);
8029 SDValue N1 = N->getOperand(1);
8030 SDValue N2 = N->getOperand(2);
8031 if (isZeroOrAllOnes(N1, AllOnes)) {
8036 if (isZeroOrAllOnes(N2, AllOnes)) {
8043 case ISD::ZERO_EXTEND:
8044 // (zext cc) can never be the all ones value.
8048 case ISD::SIGN_EXTEND: {
8050 EVT VT = N->getValueType(0);
8051 CC = N->getOperand(0);
8052 if (CC.getValueType() != MVT::i1)
8056 // When looking for an AllOnes constant, N is an sext, and the 'other'
8058 OtherOp = DAG.getConstant(0, dl, VT);
8059 else if (N->getOpcode() == ISD::ZERO_EXTEND)
8060 // When looking for a 0 constant, N can be zext or sext.
8061 OtherOp = DAG.getConstant(1, dl, VT);
8063 OtherOp = DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), dl,
8070 // Combine a constant select operand into its use:
8072 // (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
8073 // (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
8074 // (and (select cc, -1, c), x) -> (select cc, x, (and, x, c)) [AllOnes=1]
8075 // (or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
8076 // (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
8078 // The transform is rejected if the select doesn't have a constant operand that
8079 // is null, or all ones when AllOnes is set.
8081 // Also recognize sext/zext from i1:
8083 // (add (zext cc), x) -> (select cc (add x, 1), x)
8084 // (add (sext cc), x) -> (select cc (add x, -1), x)
8086 // These transformations eventually create predicated instructions.
8088 // @param N The node to transform.
8089 // @param Slct The N operand that is a select.
8090 // @param OtherOp The other N operand (x above).
8091 // @param DCI Context.
8092 // @param AllOnes Require the select constant to be all ones instead of null.
8093 // @returns The new node, or SDValue() on failure.
8095 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
8096 TargetLowering::DAGCombinerInfo &DCI,
8097 bool AllOnes = false) {
8098 SelectionDAG &DAG = DCI.DAG;
8099 EVT VT = N->getValueType(0);
8100 SDValue NonConstantVal;
8103 if (!isConditionalZeroOrAllOnes(Slct.getNode(), AllOnes, CCOp, SwapSelectOps,
8104 NonConstantVal, DAG))
8107 // Slct is now know to be the desired identity constant when CC is true.
8108 SDValue TrueVal = OtherOp;
8109 SDValue FalseVal = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
8110 OtherOp, NonConstantVal);
8111 // Unless SwapSelectOps says CC should be false.
8113 std::swap(TrueVal, FalseVal);
8115 return DAG.getNode(ISD::SELECT, SDLoc(N), VT,
8116 CCOp, TrueVal, FalseVal);
8119 // Attempt combineSelectAndUse on each operand of a commutative operator N.
8121 SDValue combineSelectAndUseCommutative(SDNode *N, bool AllOnes,
8122 TargetLowering::DAGCombinerInfo &DCI) {
8123 SDValue N0 = N->getOperand(0);
8124 SDValue N1 = N->getOperand(1);
8125 if (N0.getNode()->hasOneUse()) {
8126 SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes);
8127 if (Result.getNode())
8130 if (N1.getNode()->hasOneUse()) {
8131 SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes);
8132 if (Result.getNode())
8138 // AddCombineToVPADDL- For pair-wise add on neon, use the vpaddl instruction
8139 // (only after legalization).
8140 static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1,
8141 TargetLowering::DAGCombinerInfo &DCI,
8142 const ARMSubtarget *Subtarget) {
8144 // Only perform optimization if after legalize, and if NEON is available. We
8145 // also expected both operands to be BUILD_VECTORs.
8146 if (DCI.isBeforeLegalize() || !Subtarget->hasNEON()
8147 || N0.getOpcode() != ISD::BUILD_VECTOR
8148 || N1.getOpcode() != ISD::BUILD_VECTOR)
8151 // Check output type since VPADDL operand elements can only be 8, 16, or 32.
8152 EVT VT = N->getValueType(0);
8153 if (!VT.isInteger() || VT.getVectorElementType() == MVT::i64)
8156 // Check that the vector operands are of the right form.
8157 // N0 and N1 are BUILD_VECTOR nodes with N number of EXTRACT_VECTOR
8158 // operands, where N is the size of the formed vector.
8159 // Each EXTRACT_VECTOR should have the same input vector and odd or even
8160 // index such that we have a pair wise add pattern.
8162 // Grab the vector that all EXTRACT_VECTOR nodes should be referencing.
8163 if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
8165 SDValue Vec = N0->getOperand(0)->getOperand(0);
8166 SDNode *V = Vec.getNode();
8167 unsigned nextIndex = 0;
8169 // For each operands to the ADD which are BUILD_VECTORs,
8170 // check to see if each of their operands are an EXTRACT_VECTOR with
8171 // the same vector and appropriate index.
8172 for (unsigned i = 0, e = N0->getNumOperands(); i != e; ++i) {
8173 if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT
8174 && N1->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
8176 SDValue ExtVec0 = N0->getOperand(i);
8177 SDValue ExtVec1 = N1->getOperand(i);
8179 // First operand is the vector, verify its the same.
8180 if (V != ExtVec0->getOperand(0).getNode() ||
8181 V != ExtVec1->getOperand(0).getNode())
8184 // Second is the constant, verify its correct.
8185 ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(ExtVec0->getOperand(1));
8186 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(ExtVec1->getOperand(1));
8188 // For the constant, we want to see all the even or all the odd.
8189 if (!C0 || !C1 || C0->getZExtValue() != nextIndex
8190 || C1->getZExtValue() != nextIndex+1)
8199 // Create VPADDL node.
8200 SelectionDAG &DAG = DCI.DAG;
8201 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8205 // Build operand list.
8206 SmallVector<SDValue, 8> Ops;
8207 Ops.push_back(DAG.getConstant(Intrinsic::arm_neon_vpaddls, dl,
8208 TLI.getPointerTy(DAG.getDataLayout())));
8210 // Input is the vector.
8213 // Get widened type and narrowed type.
8215 unsigned numElem = VT.getVectorNumElements();
8217 EVT inputLaneType = Vec.getValueType().getVectorElementType();
8218 switch (inputLaneType.getSimpleVT().SimpleTy) {
8219 case MVT::i8: widenType = MVT::getVectorVT(MVT::i16, numElem); break;
8220 case MVT::i16: widenType = MVT::getVectorVT(MVT::i32, numElem); break;
8221 case MVT::i32: widenType = MVT::getVectorVT(MVT::i64, numElem); break;
8223 llvm_unreachable("Invalid vector element type for padd optimization.");
8226 SDValue tmp = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, widenType, Ops);
8227 unsigned ExtOp = VT.bitsGT(tmp.getValueType()) ? ISD::ANY_EXTEND : ISD::TRUNCATE;
8228 return DAG.getNode(ExtOp, dl, VT, tmp);
8231 static SDValue findMUL_LOHI(SDValue V) {
8232 if (V->getOpcode() == ISD::UMUL_LOHI ||
8233 V->getOpcode() == ISD::SMUL_LOHI)
8238 static SDValue AddCombineTo64bitMLAL(SDNode *AddcNode,
8239 TargetLowering::DAGCombinerInfo &DCI,
8240 const ARMSubtarget *Subtarget) {
8242 if (Subtarget->isThumb1Only()) return SDValue();
8244 // Only perform the checks after legalize when the pattern is available.
8245 if (DCI.isBeforeLegalize()) return SDValue();
8247 // Look for multiply add opportunities.
8248 // The pattern is a ISD::UMUL_LOHI followed by two add nodes, where
8249 // each add nodes consumes a value from ISD::UMUL_LOHI and there is
8250 // a glue link from the first add to the second add.
8251 // If we find this pattern, we can replace the U/SMUL_LOHI, ADDC, and ADDE by
8252 // a S/UMLAL instruction.
8255 // / \ [no multiline comment]
8261 assert(AddcNode->getOpcode() == ISD::ADDC && "Expect an ADDC");
8262 SDValue AddcOp0 = AddcNode->getOperand(0);
8263 SDValue AddcOp1 = AddcNode->getOperand(1);
8265 // Check if the two operands are from the same mul_lohi node.
8266 if (AddcOp0.getNode() == AddcOp1.getNode())
8269 assert(AddcNode->getNumValues() == 2 &&
8270 AddcNode->getValueType(0) == MVT::i32 &&
8271 "Expect ADDC with two result values. First: i32");
8273 // Check that we have a glued ADDC node.
8274 if (AddcNode->getValueType(1) != MVT::Glue)
8277 // Check that the ADDC adds the low result of the S/UMUL_LOHI.
8278 if (AddcOp0->getOpcode() != ISD::UMUL_LOHI &&
8279 AddcOp0->getOpcode() != ISD::SMUL_LOHI &&
8280 AddcOp1->getOpcode() != ISD::UMUL_LOHI &&
8281 AddcOp1->getOpcode() != ISD::SMUL_LOHI)
8284 // Look for the glued ADDE.
8285 SDNode* AddeNode = AddcNode->getGluedUser();
8289 // Make sure it is really an ADDE.
8290 if (AddeNode->getOpcode() != ISD::ADDE)
8293 assert(AddeNode->getNumOperands() == 3 &&
8294 AddeNode->getOperand(2).getValueType() == MVT::Glue &&
8295 "ADDE node has the wrong inputs");
8297 // Check for the triangle shape.
8298 SDValue AddeOp0 = AddeNode->getOperand(0);
8299 SDValue AddeOp1 = AddeNode->getOperand(1);
8301 // Make sure that the ADDE operands are not coming from the same node.
8302 if (AddeOp0.getNode() == AddeOp1.getNode())
8305 // Find the MUL_LOHI node walking up ADDE's operands.
8306 bool IsLeftOperandMUL = false;
8307 SDValue MULOp = findMUL_LOHI(AddeOp0);
8308 if (MULOp == SDValue())
8309 MULOp = findMUL_LOHI(AddeOp1);
8311 IsLeftOperandMUL = true;
8312 if (MULOp == SDValue())
8315 // Figure out the right opcode.
8316 unsigned Opc = MULOp->getOpcode();
8317 unsigned FinalOpc = (Opc == ISD::SMUL_LOHI) ? ARMISD::SMLAL : ARMISD::UMLAL;
8319 // Figure out the high and low input values to the MLAL node.
8320 SDValue* HiAdd = nullptr;
8321 SDValue* LoMul = nullptr;
8322 SDValue* LowAdd = nullptr;
8324 // Ensure that ADDE is from high result of ISD::SMUL_LOHI.
8325 if ((AddeOp0 != MULOp.getValue(1)) && (AddeOp1 != MULOp.getValue(1)))
8328 if (IsLeftOperandMUL)
8334 // Ensure that LoMul and LowAdd are taken from correct ISD::SMUL_LOHI node
8335 // whose low result is fed to the ADDC we are checking.
8337 if (AddcOp0 == MULOp.getValue(0)) {
8341 if (AddcOp1 == MULOp.getValue(0)) {
8349 // Create the merged node.
8350 SelectionDAG &DAG = DCI.DAG;
8352 // Build operand list.
8353 SmallVector<SDValue, 8> Ops;
8354 Ops.push_back(LoMul->getOperand(0));
8355 Ops.push_back(LoMul->getOperand(1));
8356 Ops.push_back(*LowAdd);
8357 Ops.push_back(*HiAdd);
8359 SDValue MLALNode = DAG.getNode(FinalOpc, SDLoc(AddcNode),
8360 DAG.getVTList(MVT::i32, MVT::i32), Ops);
8362 // Replace the ADDs' nodes uses by the MLA node's values.
8363 SDValue HiMLALResult(MLALNode.getNode(), 1);
8364 DAG.ReplaceAllUsesOfValueWith(SDValue(AddeNode, 0), HiMLALResult);
8366 SDValue LoMLALResult(MLALNode.getNode(), 0);
8367 DAG.ReplaceAllUsesOfValueWith(SDValue(AddcNode, 0), LoMLALResult);
8369 // Return original node to notify the driver to stop replacing.
8370 SDValue resNode(AddcNode, 0);
8374 /// PerformADDCCombine - Target-specific dag combine transform from
8375 /// ISD::ADDC, ISD::ADDE, and ISD::MUL_LOHI to MLAL.
8376 static SDValue PerformADDCCombine(SDNode *N,
8377 TargetLowering::DAGCombinerInfo &DCI,
8378 const ARMSubtarget *Subtarget) {
8380 return AddCombineTo64bitMLAL(N, DCI, Subtarget);
8384 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
8385 /// operands N0 and N1. This is a helper for PerformADDCombine that is
8386 /// called with the default operands, and if that fails, with commuted
8388 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
8389 TargetLowering::DAGCombinerInfo &DCI,
8390 const ARMSubtarget *Subtarget){
8392 // Attempt to create vpaddl for this add.
8393 SDValue Result = AddCombineToVPADDL(N, N0, N1, DCI, Subtarget);
8394 if (Result.getNode())
8397 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
8398 if (N0.getNode()->hasOneUse()) {
8399 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
8400 if (Result.getNode()) return Result;
8405 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
8407 static SDValue PerformADDCombine(SDNode *N,
8408 TargetLowering::DAGCombinerInfo &DCI,
8409 const ARMSubtarget *Subtarget) {
8410 SDValue N0 = N->getOperand(0);
8411 SDValue N1 = N->getOperand(1);
8413 // First try with the default operand order.
8414 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget);
8415 if (Result.getNode())
8418 // If that didn't work, try again with the operands commuted.
8419 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget);
8422 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
8424 static SDValue PerformSUBCombine(SDNode *N,
8425 TargetLowering::DAGCombinerInfo &DCI) {
8426 SDValue N0 = N->getOperand(0);
8427 SDValue N1 = N->getOperand(1);
8429 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
8430 if (N1.getNode()->hasOneUse()) {
8431 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
8432 if (Result.getNode()) return Result;
8438 /// PerformVMULCombine
8439 /// Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the
8440 /// special multiplier accumulator forwarding.
8446 // However, for (A + B) * (A + B),
8453 static SDValue PerformVMULCombine(SDNode *N,
8454 TargetLowering::DAGCombinerInfo &DCI,
8455 const ARMSubtarget *Subtarget) {
8456 if (!Subtarget->hasVMLxForwarding())
8459 SelectionDAG &DAG = DCI.DAG;
8460 SDValue N0 = N->getOperand(0);
8461 SDValue N1 = N->getOperand(1);
8462 unsigned Opcode = N0.getOpcode();
8463 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
8464 Opcode != ISD::FADD && Opcode != ISD::FSUB) {
8465 Opcode = N1.getOpcode();
8466 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
8467 Opcode != ISD::FADD && Opcode != ISD::FSUB)
8475 EVT VT = N->getValueType(0);
8477 SDValue N00 = N0->getOperand(0);
8478 SDValue N01 = N0->getOperand(1);
8479 return DAG.getNode(Opcode, DL, VT,
8480 DAG.getNode(ISD::MUL, DL, VT, N00, N1),
8481 DAG.getNode(ISD::MUL, DL, VT, N01, N1));
8484 static SDValue PerformMULCombine(SDNode *N,
8485 TargetLowering::DAGCombinerInfo &DCI,
8486 const ARMSubtarget *Subtarget) {
8487 SelectionDAG &DAG = DCI.DAG;
8489 if (Subtarget->isThumb1Only())
8492 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
8495 EVT VT = N->getValueType(0);
8496 if (VT.is64BitVector() || VT.is128BitVector())
8497 return PerformVMULCombine(N, DCI, Subtarget);
8501 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
8505 int64_t MulAmt = C->getSExtValue();
8506 unsigned ShiftAmt = countTrailingZeros<uint64_t>(MulAmt);
8508 ShiftAmt = ShiftAmt & (32 - 1);
8509 SDValue V = N->getOperand(0);
8513 MulAmt >>= ShiftAmt;
8516 if (isPowerOf2_32(MulAmt - 1)) {
8517 // (mul x, 2^N + 1) => (add (shl x, N), x)
8518 Res = DAG.getNode(ISD::ADD, DL, VT,
8520 DAG.getNode(ISD::SHL, DL, VT,
8522 DAG.getConstant(Log2_32(MulAmt - 1), DL,
8524 } else if (isPowerOf2_32(MulAmt + 1)) {
8525 // (mul x, 2^N - 1) => (sub (shl x, N), x)
8526 Res = DAG.getNode(ISD::SUB, DL, VT,
8527 DAG.getNode(ISD::SHL, DL, VT,
8529 DAG.getConstant(Log2_32(MulAmt + 1), DL,
8535 uint64_t MulAmtAbs = -MulAmt;
8536 if (isPowerOf2_32(MulAmtAbs + 1)) {
8537 // (mul x, -(2^N - 1)) => (sub x, (shl x, N))
8538 Res = DAG.getNode(ISD::SUB, DL, VT,
8540 DAG.getNode(ISD::SHL, DL, VT,
8542 DAG.getConstant(Log2_32(MulAmtAbs + 1), DL,
8544 } else if (isPowerOf2_32(MulAmtAbs - 1)) {
8545 // (mul x, -(2^N + 1)) => - (add (shl x, N), x)
8546 Res = DAG.getNode(ISD::ADD, DL, VT,
8548 DAG.getNode(ISD::SHL, DL, VT,
8550 DAG.getConstant(Log2_32(MulAmtAbs - 1), DL,
8552 Res = DAG.getNode(ISD::SUB, DL, VT,
8553 DAG.getConstant(0, DL, MVT::i32), Res);
8560 Res = DAG.getNode(ISD::SHL, DL, VT,
8561 Res, DAG.getConstant(ShiftAmt, DL, MVT::i32));
8563 // Do not add new nodes to DAG combiner worklist.
8564 DCI.CombineTo(N, Res, false);
8568 static SDValue PerformANDCombine(SDNode *N,
8569 TargetLowering::DAGCombinerInfo &DCI,
8570 const ARMSubtarget *Subtarget) {
8572 // Attempt to use immediate-form VBIC
8573 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
8575 EVT VT = N->getValueType(0);
8576 SelectionDAG &DAG = DCI.DAG;
8578 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
8581 APInt SplatBits, SplatUndef;
8582 unsigned SplatBitSize;
8585 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
8586 if (SplatBitSize <= 64) {
8588 SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(),
8589 SplatUndef.getZExtValue(), SplatBitSize,
8590 DAG, dl, VbicVT, VT.is128BitVector(),
8592 if (Val.getNode()) {
8594 DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0));
8595 SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val);
8596 return DAG.getNode(ISD::BITCAST, dl, VT, Vbic);
8601 if (!Subtarget->isThumb1Only()) {
8602 // fold (and (select cc, -1, c), x) -> (select cc, x, (and, x, c))
8603 SDValue Result = combineSelectAndUseCommutative(N, true, DCI);
8604 if (Result.getNode())
8611 /// PerformORCombine - Target-specific dag combine xforms for ISD::OR
8612 static SDValue PerformORCombine(SDNode *N,
8613 TargetLowering::DAGCombinerInfo &DCI,
8614 const ARMSubtarget *Subtarget) {
8615 // Attempt to use immediate-form VORR
8616 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
8618 EVT VT = N->getValueType(0);
8619 SelectionDAG &DAG = DCI.DAG;
8621 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
8624 APInt SplatBits, SplatUndef;
8625 unsigned SplatBitSize;
8627 if (BVN && Subtarget->hasNEON() &&
8628 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
8629 if (SplatBitSize <= 64) {
8631 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
8632 SplatUndef.getZExtValue(), SplatBitSize,
8633 DAG, dl, VorrVT, VT.is128BitVector(),
8635 if (Val.getNode()) {
8637 DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0));
8638 SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val);
8639 return DAG.getNode(ISD::BITCAST, dl, VT, Vorr);
8644 if (!Subtarget->isThumb1Only()) {
8645 // fold (or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
8646 SDValue Result = combineSelectAndUseCommutative(N, false, DCI);
8647 if (Result.getNode())
8651 // The code below optimizes (or (and X, Y), Z).
8652 // The AND operand needs to have a single user to make these optimizations
8654 SDValue N0 = N->getOperand(0);
8655 if (N0.getOpcode() != ISD::AND || !N0.hasOneUse())
8657 SDValue N1 = N->getOperand(1);
8659 // (or (and B, A), (and C, ~A)) => (VBSL A, B, C) when A is a constant.
8660 if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() &&
8661 DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
8663 unsigned SplatBitSize;
8666 APInt SplatBits0, SplatBits1;
8667 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1));
8668 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(1));
8669 // Ensure that the second operand of both ands are constants
8670 if (BVN0 && BVN0->isConstantSplat(SplatBits0, SplatUndef, SplatBitSize,
8671 HasAnyUndefs) && !HasAnyUndefs) {
8672 if (BVN1 && BVN1->isConstantSplat(SplatBits1, SplatUndef, SplatBitSize,
8673 HasAnyUndefs) && !HasAnyUndefs) {
8674 // Ensure that the bit width of the constants are the same and that
8675 // the splat arguments are logical inverses as per the pattern we
8676 // are trying to simplify.
8677 if (SplatBits0.getBitWidth() == SplatBits1.getBitWidth() &&
8678 SplatBits0 == ~SplatBits1) {
8679 // Canonicalize the vector type to make instruction selection
8681 EVT CanonicalVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
8682 SDValue Result = DAG.getNode(ARMISD::VBSL, dl, CanonicalVT,
8686 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
8692 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when
8695 // BFI is only available on V6T2+
8696 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops())
8700 // 1) or (and A, mask), val => ARMbfi A, val, mask
8701 // iff (val & mask) == val
8703 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
8704 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2)
8705 // && mask == ~mask2
8706 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2)
8707 // && ~mask == mask2
8708 // (i.e., copy a bitfield value into another bitfield of the same width)
8713 SDValue N00 = N0.getOperand(0);
8715 // The value and the mask need to be constants so we can verify this is
8716 // actually a bitfield set. If the mask is 0xffff, we can do better
8717 // via a movt instruction, so don't use BFI in that case.
8718 SDValue MaskOp = N0.getOperand(1);
8719 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(MaskOp);
8722 unsigned Mask = MaskC->getZExtValue();
8726 // Case (1): or (and A, mask), val => ARMbfi A, val, mask
8727 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
8729 unsigned Val = N1C->getZExtValue();
8730 if ((Val & ~Mask) != Val)
8733 if (ARM::isBitFieldInvertedMask(Mask)) {
8734 Val >>= countTrailingZeros(~Mask);
8736 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00,
8737 DAG.getConstant(Val, DL, MVT::i32),
8738 DAG.getConstant(Mask, DL, MVT::i32));
8740 // Do not add new nodes to DAG combiner worklist.
8741 DCI.CombineTo(N, Res, false);
8744 } else if (N1.getOpcode() == ISD::AND) {
8745 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
8746 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
8749 unsigned Mask2 = N11C->getZExtValue();
8751 // Mask and ~Mask2 (or reverse) must be equivalent for the BFI pattern
8753 if (ARM::isBitFieldInvertedMask(Mask) &&
8755 // The pack halfword instruction works better for masks that fit it,
8756 // so use that when it's available.
8757 if (Subtarget->hasT2ExtractPack() &&
8758 (Mask == 0xffff || Mask == 0xffff0000))
8761 unsigned amt = countTrailingZeros(Mask2);
8762 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
8763 DAG.getConstant(amt, DL, MVT::i32));
8764 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res,
8765 DAG.getConstant(Mask, DL, MVT::i32));
8766 // Do not add new nodes to DAG combiner worklist.
8767 DCI.CombineTo(N, Res, false);
8769 } else if (ARM::isBitFieldInvertedMask(~Mask) &&
8771 // The pack halfword instruction works better for masks that fit it,
8772 // so use that when it's available.
8773 if (Subtarget->hasT2ExtractPack() &&
8774 (Mask2 == 0xffff || Mask2 == 0xffff0000))
8777 unsigned lsb = countTrailingZeros(Mask);
8778 Res = DAG.getNode(ISD::SRL, DL, VT, N00,
8779 DAG.getConstant(lsb, DL, MVT::i32));
8780 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
8781 DAG.getConstant(Mask2, DL, MVT::i32));
8782 // Do not add new nodes to DAG combiner worklist.
8783 DCI.CombineTo(N, Res, false);
8788 if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) &&
8789 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) &&
8790 ARM::isBitFieldInvertedMask(~Mask)) {
8791 // Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask
8792 // where lsb(mask) == #shamt and masked bits of B are known zero.
8793 SDValue ShAmt = N00.getOperand(1);
8794 unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue();
8795 unsigned LSB = countTrailingZeros(Mask);
8799 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0),
8800 DAG.getConstant(~Mask, DL, MVT::i32));
8802 // Do not add new nodes to DAG combiner worklist.
8803 DCI.CombineTo(N, Res, false);
8809 static SDValue PerformXORCombine(SDNode *N,
8810 TargetLowering::DAGCombinerInfo &DCI,
8811 const ARMSubtarget *Subtarget) {
8812 EVT VT = N->getValueType(0);
8813 SelectionDAG &DAG = DCI.DAG;
8815 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
8818 if (!Subtarget->isThumb1Only()) {
8819 // fold (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
8820 SDValue Result = combineSelectAndUseCommutative(N, false, DCI);
8821 if (Result.getNode())
8828 /// PerformBFICombine - (bfi A, (and B, Mask1), Mask2) -> (bfi A, B, Mask2) iff
8829 /// the bits being cleared by the AND are not demanded by the BFI.
8830 static SDValue PerformBFICombine(SDNode *N,
8831 TargetLowering::DAGCombinerInfo &DCI) {
8832 SDValue N1 = N->getOperand(1);
8833 if (N1.getOpcode() == ISD::AND) {
8834 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
8837 unsigned InvMask = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
8838 unsigned LSB = countTrailingZeros(~InvMask);
8839 unsigned Width = (32 - countLeadingZeros(~InvMask)) - LSB;
8841 static_cast<unsigned>(std::numeric_limits<unsigned>::digits) &&
8842 "undefined behavior");
8843 unsigned Mask = (1u << Width) - 1;
8844 unsigned Mask2 = N11C->getZExtValue();
8845 if ((Mask & (~Mask2)) == 0)
8846 return DCI.DAG.getNode(ARMISD::BFI, SDLoc(N), N->getValueType(0),
8847 N->getOperand(0), N1.getOperand(0),
8853 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
8854 /// ARMISD::VMOVRRD.
8855 static SDValue PerformVMOVRRDCombine(SDNode *N,
8856 TargetLowering::DAGCombinerInfo &DCI,
8857 const ARMSubtarget *Subtarget) {
8858 // vmovrrd(vmovdrr x, y) -> x,y
8859 SDValue InDouble = N->getOperand(0);
8860 if (InDouble.getOpcode() == ARMISD::VMOVDRR && !Subtarget->isFPOnlySP())
8861 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
8863 // vmovrrd(load f64) -> (load i32), (load i32)
8864 SDNode *InNode = InDouble.getNode();
8865 if (ISD::isNormalLoad(InNode) && InNode->hasOneUse() &&
8866 InNode->getValueType(0) == MVT::f64 &&
8867 InNode->getOperand(1).getOpcode() == ISD::FrameIndex &&
8868 !cast<LoadSDNode>(InNode)->isVolatile()) {
8869 // TODO: Should this be done for non-FrameIndex operands?
8870 LoadSDNode *LD = cast<LoadSDNode>(InNode);
8872 SelectionDAG &DAG = DCI.DAG;
8874 SDValue BasePtr = LD->getBasePtr();
8875 SDValue NewLD1 = DAG.getLoad(MVT::i32, DL, LD->getChain(), BasePtr,
8876 LD->getPointerInfo(), LD->isVolatile(),
8877 LD->isNonTemporal(), LD->isInvariant(),
8878 LD->getAlignment());
8880 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
8881 DAG.getConstant(4, DL, MVT::i32));
8882 SDValue NewLD2 = DAG.getLoad(MVT::i32, DL, NewLD1.getValue(1), OffsetPtr,
8883 LD->getPointerInfo(), LD->isVolatile(),
8884 LD->isNonTemporal(), LD->isInvariant(),
8885 std::min(4U, LD->getAlignment() / 2));
8887 DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), NewLD2.getValue(1));
8888 if (DCI.DAG.getDataLayout().isBigEndian())
8889 std::swap (NewLD1, NewLD2);
8890 SDValue Result = DCI.CombineTo(N, NewLD1, NewLD2);
8897 /// PerformVMOVDRRCombine - Target-specific dag combine xforms for
8898 /// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands.
8899 static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) {
8900 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X)
8901 SDValue Op0 = N->getOperand(0);
8902 SDValue Op1 = N->getOperand(1);
8903 if (Op0.getOpcode() == ISD::BITCAST)
8904 Op0 = Op0.getOperand(0);
8905 if (Op1.getOpcode() == ISD::BITCAST)
8906 Op1 = Op1.getOperand(0);
8907 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
8908 Op0.getNode() == Op1.getNode() &&
8909 Op0.getResNo() == 0 && Op1.getResNo() == 1)
8910 return DAG.getNode(ISD::BITCAST, SDLoc(N),
8911 N->getValueType(0), Op0.getOperand(0));
8915 /// hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node
8916 /// are normal, non-volatile loads. If so, it is profitable to bitcast an
8917 /// i64 vector to have f64 elements, since the value can then be loaded
8918 /// directly into a VFP register.
8919 static bool hasNormalLoadOperand(SDNode *N) {
8920 unsigned NumElts = N->getValueType(0).getVectorNumElements();
8921 for (unsigned i = 0; i < NumElts; ++i) {
8922 SDNode *Elt = N->getOperand(i).getNode();
8923 if (ISD::isNormalLoad(Elt) && !cast<LoadSDNode>(Elt)->isVolatile())
8929 /// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for
8930 /// ISD::BUILD_VECTOR.
8931 static SDValue PerformBUILD_VECTORCombine(SDNode *N,
8932 TargetLowering::DAGCombinerInfo &DCI,
8933 const ARMSubtarget *Subtarget) {
8934 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X):
8935 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value
8936 // into a pair of GPRs, which is fine when the value is used as a scalar,
8937 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD.
8938 SelectionDAG &DAG = DCI.DAG;
8939 if (N->getNumOperands() == 2) {
8940 SDValue RV = PerformVMOVDRRCombine(N, DAG);
8945 // Load i64 elements as f64 values so that type legalization does not split
8946 // them up into i32 values.
8947 EVT VT = N->getValueType(0);
8948 if (VT.getVectorElementType() != MVT::i64 || !hasNormalLoadOperand(N))
8951 SmallVector<SDValue, 8> Ops;
8952 unsigned NumElts = VT.getVectorNumElements();
8953 for (unsigned i = 0; i < NumElts; ++i) {
8954 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(i));
8956 // Make the DAGCombiner fold the bitcast.
8957 DCI.AddToWorklist(V.getNode());
8959 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, NumElts);
8960 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, FloatVT, Ops);
8961 return DAG.getNode(ISD::BITCAST, dl, VT, BV);
8964 /// \brief Target-specific dag combine xforms for ARMISD::BUILD_VECTOR.
8966 PerformARMBUILD_VECTORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
8967 // ARMISD::BUILD_VECTOR is introduced when legalizing ISD::BUILD_VECTOR.
8968 // At that time, we may have inserted bitcasts from integer to float.
8969 // If these bitcasts have survived DAGCombine, change the lowering of this
8970 // BUILD_VECTOR in something more vector friendly, i.e., that does not
8971 // force to use floating point types.
8973 // Make sure we can change the type of the vector.
8974 // This is possible iff:
8975 // 1. The vector is only used in a bitcast to a integer type. I.e.,
8976 // 1.1. Vector is used only once.
8977 // 1.2. Use is a bit convert to an integer type.
8978 // 2. The size of its operands are 32-bits (64-bits are not legal).
8979 EVT VT = N->getValueType(0);
8980 EVT EltVT = VT.getVectorElementType();
8982 // Check 1.1. and 2.
8983 if (EltVT.getSizeInBits() != 32 || !N->hasOneUse())
8986 // By construction, the input type must be float.
8987 assert(EltVT == MVT::f32 && "Unexpected type!");
8990 SDNode *Use = *N->use_begin();
8991 if (Use->getOpcode() != ISD::BITCAST ||
8992 Use->getValueType(0).isFloatingPoint())
8995 // Check profitability.
8996 // Model is, if more than half of the relevant operands are bitcast from
8997 // i32, turn the build_vector into a sequence of insert_vector_elt.
8998 // Relevant operands are everything that is not statically
8999 // (i.e., at compile time) bitcasted.
9000 unsigned NumOfBitCastedElts = 0;
9001 unsigned NumElts = VT.getVectorNumElements();
9002 unsigned NumOfRelevantElts = NumElts;
9003 for (unsigned Idx = 0; Idx < NumElts; ++Idx) {
9004 SDValue Elt = N->getOperand(Idx);
9005 if (Elt->getOpcode() == ISD::BITCAST) {
9006 // Assume only bit cast to i32 will go away.
9007 if (Elt->getOperand(0).getValueType() == MVT::i32)
9008 ++NumOfBitCastedElts;
9009 } else if (Elt.getOpcode() == ISD::UNDEF || isa<ConstantSDNode>(Elt))
9010 // Constants are statically casted, thus do not count them as
9011 // relevant operands.
9012 --NumOfRelevantElts;
9015 // Check if more than half of the elements require a non-free bitcast.
9016 if (NumOfBitCastedElts <= NumOfRelevantElts / 2)
9019 SelectionDAG &DAG = DCI.DAG;
9020 // Create the new vector type.
9021 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
9022 // Check if the type is legal.
9023 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9024 if (!TLI.isTypeLegal(VecVT))
9028 // ARMISD::BUILD_VECTOR E1, E2, ..., EN.
9029 // => BITCAST INSERT_VECTOR_ELT
9030 // (INSERT_VECTOR_ELT (...), (BITCAST EN-1), N-1),
9032 SDValue Vec = DAG.getUNDEF(VecVT);
9034 for (unsigned Idx = 0 ; Idx < NumElts; ++Idx) {
9035 SDValue V = N->getOperand(Idx);
9036 if (V.getOpcode() == ISD::UNDEF)
9038 if (V.getOpcode() == ISD::BITCAST &&
9039 V->getOperand(0).getValueType() == MVT::i32)
9040 // Fold obvious case.
9041 V = V.getOperand(0);
9043 V = DAG.getNode(ISD::BITCAST, SDLoc(V), MVT::i32, V);
9044 // Make the DAGCombiner fold the bitcasts.
9045 DCI.AddToWorklist(V.getNode());
9047 SDValue LaneIdx = DAG.getConstant(Idx, dl, MVT::i32);
9048 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecVT, Vec, V, LaneIdx);
9050 Vec = DAG.getNode(ISD::BITCAST, dl, VT, Vec);
9051 // Make the DAGCombiner fold the bitcasts.
9052 DCI.AddToWorklist(Vec.getNode());
9056 /// PerformInsertEltCombine - Target-specific dag combine xforms for
9057 /// ISD::INSERT_VECTOR_ELT.
9058 static SDValue PerformInsertEltCombine(SDNode *N,
9059 TargetLowering::DAGCombinerInfo &DCI) {
9060 // Bitcast an i64 load inserted into a vector to f64.
9061 // Otherwise, the i64 value will be legalized to a pair of i32 values.
9062 EVT VT = N->getValueType(0);
9063 SDNode *Elt = N->getOperand(1).getNode();
9064 if (VT.getVectorElementType() != MVT::i64 ||
9065 !ISD::isNormalLoad(Elt) || cast<LoadSDNode>(Elt)->isVolatile())
9068 SelectionDAG &DAG = DCI.DAG;
9070 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
9071 VT.getVectorNumElements());
9072 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, N->getOperand(0));
9073 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(1));
9074 // Make the DAGCombiner fold the bitcasts.
9075 DCI.AddToWorklist(Vec.getNode());
9076 DCI.AddToWorklist(V.getNode());
9077 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT,
9078 Vec, V, N->getOperand(2));
9079 return DAG.getNode(ISD::BITCAST, dl, VT, InsElt);
9082 /// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for
9083 /// ISD::VECTOR_SHUFFLE.
9084 static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) {
9085 // The LLVM shufflevector instruction does not require the shuffle mask
9086 // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does
9087 // have that requirement. When translating to ISD::VECTOR_SHUFFLE, if the
9088 // operands do not match the mask length, they are extended by concatenating
9089 // them with undef vectors. That is probably the right thing for other
9090 // targets, but for NEON it is better to concatenate two double-register
9091 // size vector operands into a single quad-register size vector. Do that
9092 // transformation here:
9093 // shuffle(concat(v1, undef), concat(v2, undef)) ->
9094 // shuffle(concat(v1, v2), undef)
9095 SDValue Op0 = N->getOperand(0);
9096 SDValue Op1 = N->getOperand(1);
9097 if (Op0.getOpcode() != ISD::CONCAT_VECTORS ||
9098 Op1.getOpcode() != ISD::CONCAT_VECTORS ||
9099 Op0.getNumOperands() != 2 ||
9100 Op1.getNumOperands() != 2)
9102 SDValue Concat0Op1 = Op0.getOperand(1);
9103 SDValue Concat1Op1 = Op1.getOperand(1);
9104 if (Concat0Op1.getOpcode() != ISD::UNDEF ||
9105 Concat1Op1.getOpcode() != ISD::UNDEF)
9107 // Skip the transformation if any of the types are illegal.
9108 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9109 EVT VT = N->getValueType(0);
9110 if (!TLI.isTypeLegal(VT) ||
9111 !TLI.isTypeLegal(Concat0Op1.getValueType()) ||
9112 !TLI.isTypeLegal(Concat1Op1.getValueType()))
9115 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT,
9116 Op0.getOperand(0), Op1.getOperand(0));
9117 // Translate the shuffle mask.
9118 SmallVector<int, 16> NewMask;
9119 unsigned NumElts = VT.getVectorNumElements();
9120 unsigned HalfElts = NumElts/2;
9121 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
9122 for (unsigned n = 0; n < NumElts; ++n) {
9123 int MaskElt = SVN->getMaskElt(n);
9125 if (MaskElt < (int)HalfElts)
9127 else if (MaskElt >= (int)NumElts && MaskElt < (int)(NumElts + HalfElts))
9128 NewElt = HalfElts + MaskElt - NumElts;
9129 NewMask.push_back(NewElt);
9131 return DAG.getVectorShuffle(VT, SDLoc(N), NewConcat,
9132 DAG.getUNDEF(VT), NewMask.data());
9135 /// CombineBaseUpdate - Target-specific DAG combine function for VLDDUP,
9136 /// NEON load/store intrinsics, and generic vector load/stores, to merge
9137 /// base address updates.
9138 /// For generic load/stores, the memory type is assumed to be a vector.
9139 /// The caller is assumed to have checked legality.
9140 static SDValue CombineBaseUpdate(SDNode *N,
9141 TargetLowering::DAGCombinerInfo &DCI) {
9142 SelectionDAG &DAG = DCI.DAG;
9143 const bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID ||
9144 N->getOpcode() == ISD::INTRINSIC_W_CHAIN);
9145 const bool isStore = N->getOpcode() == ISD::STORE;
9146 const unsigned AddrOpIdx = ((isIntrinsic || isStore) ? 2 : 1);
9147 SDValue Addr = N->getOperand(AddrOpIdx);
9148 MemSDNode *MemN = cast<MemSDNode>(N);
9151 // Search for a use of the address operand that is an increment.
9152 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
9153 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
9155 if (User->getOpcode() != ISD::ADD ||
9156 UI.getUse().getResNo() != Addr.getResNo())
9159 // Check that the add is independent of the load/store. Otherwise, folding
9160 // it would create a cycle.
9161 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
9164 // Find the new opcode for the updating load/store.
9165 bool isLoadOp = true;
9166 bool isLaneOp = false;
9167 unsigned NewOpc = 0;
9168 unsigned NumVecs = 0;
9170 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
9172 default: llvm_unreachable("unexpected intrinsic for Neon base update");
9173 case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD;
9175 case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD;
9177 case Intrinsic::arm_neon_vld3: NewOpc = ARMISD::VLD3_UPD;
9179 case Intrinsic::arm_neon_vld4: NewOpc = ARMISD::VLD4_UPD;
9181 case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD;
9182 NumVecs = 2; isLaneOp = true; break;
9183 case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD;
9184 NumVecs = 3; isLaneOp = true; break;
9185 case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD;
9186 NumVecs = 4; isLaneOp = true; break;
9187 case Intrinsic::arm_neon_vst1: NewOpc = ARMISD::VST1_UPD;
9188 NumVecs = 1; isLoadOp = false; break;
9189 case Intrinsic::arm_neon_vst2: NewOpc = ARMISD::VST2_UPD;
9190 NumVecs = 2; isLoadOp = false; break;
9191 case Intrinsic::arm_neon_vst3: NewOpc = ARMISD::VST3_UPD;
9192 NumVecs = 3; isLoadOp = false; break;
9193 case Intrinsic::arm_neon_vst4: NewOpc = ARMISD::VST4_UPD;
9194 NumVecs = 4; isLoadOp = false; break;
9195 case Intrinsic::arm_neon_vst2lane: NewOpc = ARMISD::VST2LN_UPD;
9196 NumVecs = 2; isLoadOp = false; isLaneOp = true; break;
9197 case Intrinsic::arm_neon_vst3lane: NewOpc = ARMISD::VST3LN_UPD;
9198 NumVecs = 3; isLoadOp = false; isLaneOp = true; break;
9199 case Intrinsic::arm_neon_vst4lane: NewOpc = ARMISD::VST4LN_UPD;
9200 NumVecs = 4; isLoadOp = false; isLaneOp = true; break;
9204 switch (N->getOpcode()) {
9205 default: llvm_unreachable("unexpected opcode for Neon base update");
9206 case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break;
9207 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break;
9208 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break;
9209 case ISD::LOAD: NewOpc = ARMISD::VLD1_UPD;
9210 NumVecs = 1; isLaneOp = false; break;
9211 case ISD::STORE: NewOpc = ARMISD::VST1_UPD;
9212 NumVecs = 1; isLaneOp = false; isLoadOp = false; break;
9216 // Find the size of memory referenced by the load/store.
9219 VecTy = N->getValueType(0);
9220 } else if (isIntrinsic) {
9221 VecTy = N->getOperand(AddrOpIdx+1).getValueType();
9223 assert(isStore && "Node has to be a load, a store, or an intrinsic!");
9224 VecTy = N->getOperand(1).getValueType();
9227 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
9229 NumBytes /= VecTy.getVectorNumElements();
9231 // If the increment is a constant, it must match the memory ref size.
9232 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
9233 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
9234 uint64_t IncVal = CInc->getZExtValue();
9235 if (IncVal != NumBytes)
9237 } else if (NumBytes >= 3 * 16) {
9238 // VLD3/4 and VST3/4 for 128-bit vectors are implemented with two
9239 // separate instructions that make it harder to use a non-constant update.
9243 // OK, we found an ADD we can fold into the base update.
9244 // Now, create a _UPD node, taking care of not breaking alignment.
9246 EVT AlignedVecTy = VecTy;
9247 unsigned Alignment = MemN->getAlignment();
9249 // If this is a less-than-standard-aligned load/store, change the type to
9250 // match the standard alignment.
9251 // The alignment is overlooked when selecting _UPD variants; and it's
9252 // easier to introduce bitcasts here than fix that.
9253 // There are 3 ways to get to this base-update combine:
9254 // - intrinsics: they are assumed to be properly aligned (to the standard
9255 // alignment of the memory type), so we don't need to do anything.
9256 // - ARMISD::VLDx nodes: they are only generated from the aforementioned
9257 // intrinsics, so, likewise, there's nothing to do.
9258 // - generic load/store instructions: the alignment is specified as an
9259 // explicit operand, rather than implicitly as the standard alignment
9260 // of the memory type (like the intrisics). We need to change the
9261 // memory type to match the explicit alignment. That way, we don't
9262 // generate non-standard-aligned ARMISD::VLDx nodes.
9263 if (isa<LSBaseSDNode>(N)) {
9266 if (Alignment < VecTy.getScalarSizeInBits() / 8) {
9267 MVT EltTy = MVT::getIntegerVT(Alignment * 8);
9268 assert(NumVecs == 1 && "Unexpected multi-element generic load/store.");
9269 assert(!isLaneOp && "Unexpected generic load/store lane.");
9270 unsigned NumElts = NumBytes / (EltTy.getSizeInBits() / 8);
9271 AlignedVecTy = MVT::getVectorVT(EltTy, NumElts);
9273 // Don't set an explicit alignment on regular load/stores that we want
9274 // to transform to VLD/VST 1_UPD nodes.
9275 // This matches the behavior of regular load/stores, which only get an
9276 // explicit alignment if the MMO alignment is larger than the standard
9277 // alignment of the memory type.
9278 // Intrinsics, however, always get an explicit alignment, set to the
9279 // alignment of the MMO.
9283 // Create the new updating load/store node.
9284 // First, create an SDVTList for the new updating node's results.
9286 unsigned NumResultVecs = (isLoadOp ? NumVecs : 0);
9288 for (n = 0; n < NumResultVecs; ++n)
9289 Tys[n] = AlignedVecTy;
9290 Tys[n++] = MVT::i32;
9291 Tys[n] = MVT::Other;
9292 SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumResultVecs+2));
9294 // Then, gather the new node's operands.
9295 SmallVector<SDValue, 8> Ops;
9296 Ops.push_back(N->getOperand(0)); // incoming chain
9297 Ops.push_back(N->getOperand(AddrOpIdx));
9300 if (StoreSDNode *StN = dyn_cast<StoreSDNode>(N)) {
9301 // Try to match the intrinsic's signature
9302 Ops.push_back(StN->getValue());
9304 // Loads (and of course intrinsics) match the intrinsics' signature,
9305 // so just add all but the alignment operand.
9306 for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands() - 1; ++i)
9307 Ops.push_back(N->getOperand(i));
9310 // For all node types, the alignment operand is always the last one.
9311 Ops.push_back(DAG.getConstant(Alignment, dl, MVT::i32));
9313 // If this is a non-standard-aligned STORE, the penultimate operand is the
9314 // stored value. Bitcast it to the aligned type.
9315 if (AlignedVecTy != VecTy && N->getOpcode() == ISD::STORE) {
9316 SDValue &StVal = Ops[Ops.size()-2];
9317 StVal = DAG.getNode(ISD::BITCAST, dl, AlignedVecTy, StVal);
9320 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, dl, SDTys,
9322 MemN->getMemOperand());
9325 SmallVector<SDValue, 5> NewResults;
9326 for (unsigned i = 0; i < NumResultVecs; ++i)
9327 NewResults.push_back(SDValue(UpdN.getNode(), i));
9329 // If this is an non-standard-aligned LOAD, the first result is the loaded
9330 // value. Bitcast it to the expected result type.
9331 if (AlignedVecTy != VecTy && N->getOpcode() == ISD::LOAD) {
9332 SDValue &LdVal = NewResults[0];
9333 LdVal = DAG.getNode(ISD::BITCAST, dl, VecTy, LdVal);
9336 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs+1)); // chain
9337 DCI.CombineTo(N, NewResults);
9338 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
9345 static SDValue PerformVLDCombine(SDNode *N,
9346 TargetLowering::DAGCombinerInfo &DCI) {
9347 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
9350 return CombineBaseUpdate(N, DCI);
9353 /// CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a
9354 /// vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic
9355 /// are also VDUPLANEs. If so, combine them to a vldN-dup operation and
9357 static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
9358 SelectionDAG &DAG = DCI.DAG;
9359 EVT VT = N->getValueType(0);
9360 // vldN-dup instructions only support 64-bit vectors for N > 1.
9361 if (!VT.is64BitVector())
9364 // Check if the VDUPLANE operand is a vldN-dup intrinsic.
9365 SDNode *VLD = N->getOperand(0).getNode();
9366 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN)
9368 unsigned NumVecs = 0;
9369 unsigned NewOpc = 0;
9370 unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue();
9371 if (IntNo == Intrinsic::arm_neon_vld2lane) {
9373 NewOpc = ARMISD::VLD2DUP;
9374 } else if (IntNo == Intrinsic::arm_neon_vld3lane) {
9376 NewOpc = ARMISD::VLD3DUP;
9377 } else if (IntNo == Intrinsic::arm_neon_vld4lane) {
9379 NewOpc = ARMISD::VLD4DUP;
9384 // First check that all the vldN-lane uses are VDUPLANEs and that the lane
9385 // numbers match the load.
9386 unsigned VLDLaneNo =
9387 cast<ConstantSDNode>(VLD->getOperand(NumVecs+3))->getZExtValue();
9388 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
9390 // Ignore uses of the chain result.
9391 if (UI.getUse().getResNo() == NumVecs)
9394 if (User->getOpcode() != ARMISD::VDUPLANE ||
9395 VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue())
9399 // Create the vldN-dup node.
9402 for (n = 0; n < NumVecs; ++n)
9404 Tys[n] = MVT::Other;
9405 SDVTList SDTys = DAG.getVTList(makeArrayRef(Tys, NumVecs+1));
9406 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) };
9407 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD);
9408 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, SDLoc(VLD), SDTys,
9409 Ops, VLDMemInt->getMemoryVT(),
9410 VLDMemInt->getMemOperand());
9413 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
9415 unsigned ResNo = UI.getUse().getResNo();
9416 // Ignore uses of the chain result.
9417 if (ResNo == NumVecs)
9420 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo));
9423 // Now the vldN-lane intrinsic is dead except for its chain result.
9424 // Update uses of the chain.
9425 std::vector<SDValue> VLDDupResults;
9426 for (unsigned n = 0; n < NumVecs; ++n)
9427 VLDDupResults.push_back(SDValue(VLDDup.getNode(), n));
9428 VLDDupResults.push_back(SDValue(VLDDup.getNode(), NumVecs));
9429 DCI.CombineTo(VLD, VLDDupResults);
9434 /// PerformVDUPLANECombine - Target-specific dag combine xforms for
9435 /// ARMISD::VDUPLANE.
9436 static SDValue PerformVDUPLANECombine(SDNode *N,
9437 TargetLowering::DAGCombinerInfo &DCI) {
9438 SDValue Op = N->getOperand(0);
9440 // If the source is a vldN-lane (N > 1) intrinsic, and all the other uses
9441 // of that intrinsic are also VDUPLANEs, combine them to a vldN-dup operation.
9442 if (CombineVLDDUP(N, DCI))
9443 return SDValue(N, 0);
9445 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
9446 // redundant. Ignore bit_converts for now; element sizes are checked below.
9447 while (Op.getOpcode() == ISD::BITCAST)
9448 Op = Op.getOperand(0);
9449 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
9452 // Make sure the VMOV element size is not bigger than the VDUPLANE elements.
9453 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits();
9454 // The canonical VMOV for a zero vector uses a 32-bit element size.
9455 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9457 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
9459 EVT VT = N->getValueType(0);
9460 if (EltSize > VT.getVectorElementType().getSizeInBits())
9463 return DCI.DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
9466 static SDValue PerformLOADCombine(SDNode *N,
9467 TargetLowering::DAGCombinerInfo &DCI) {
9468 EVT VT = N->getValueType(0);
9470 // If this is a legal vector load, try to combine it into a VLD1_UPD.
9471 if (ISD::isNormalLoad(N) && VT.isVector() &&
9472 DCI.DAG.getTargetLoweringInfo().isTypeLegal(VT))
9473 return CombineBaseUpdate(N, DCI);
9478 /// PerformSTORECombine - Target-specific dag combine xforms for
9480 static SDValue PerformSTORECombine(SDNode *N,
9481 TargetLowering::DAGCombinerInfo &DCI) {
9482 StoreSDNode *St = cast<StoreSDNode>(N);
9483 if (St->isVolatile())
9486 // Optimize trunc store (of multiple scalars) to shuffle and store. First,
9487 // pack all of the elements in one place. Next, store to memory in fewer
9489 SDValue StVal = St->getValue();
9490 EVT VT = StVal.getValueType();
9491 if (St->isTruncatingStore() && VT.isVector()) {
9492 SelectionDAG &DAG = DCI.DAG;
9493 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9494 EVT StVT = St->getMemoryVT();
9495 unsigned NumElems = VT.getVectorNumElements();
9496 assert(StVT != VT && "Cannot truncate to the same type");
9497 unsigned FromEltSz = VT.getVectorElementType().getSizeInBits();
9498 unsigned ToEltSz = StVT.getVectorElementType().getSizeInBits();
9500 // From, To sizes and ElemCount must be pow of two
9501 if (!isPowerOf2_32(NumElems * FromEltSz * ToEltSz)) return SDValue();
9503 // We are going to use the original vector elt for storing.
9504 // Accumulated smaller vector elements must be a multiple of the store size.
9505 if (0 != (NumElems * FromEltSz) % ToEltSz) return SDValue();
9507 unsigned SizeRatio = FromEltSz / ToEltSz;
9508 assert(SizeRatio * NumElems * ToEltSz == VT.getSizeInBits());
9510 // Create a type on which we perform the shuffle.
9511 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), StVT.getScalarType(),
9512 NumElems*SizeRatio);
9513 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
9516 SDValue WideVec = DAG.getNode(ISD::BITCAST, DL, WideVecVT, StVal);
9517 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
9518 for (unsigned i = 0; i < NumElems; ++i)
9519 ShuffleVec[i] = DAG.getDataLayout().isBigEndian()
9520 ? (i + 1) * SizeRatio - 1
9523 // Can't shuffle using an illegal type.
9524 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
9526 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, DL, WideVec,
9527 DAG.getUNDEF(WideVec.getValueType()),
9529 // At this point all of the data is stored at the bottom of the
9530 // register. We now need to save it to mem.
9532 // Find the largest store unit
9533 MVT StoreType = MVT::i8;
9534 for (MVT Tp : MVT::integer_valuetypes()) {
9535 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToEltSz)
9538 // Didn't find a legal store type.
9539 if (!TLI.isTypeLegal(StoreType))
9542 // Bitcast the original vector into a vector of store-size units
9543 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
9544 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
9545 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
9546 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, DL, StoreVecVT, Shuff);
9547 SmallVector<SDValue, 8> Chains;
9548 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits() / 8, DL,
9549 TLI.getPointerTy(DAG.getDataLayout()));
9550 SDValue BasePtr = St->getBasePtr();
9552 // Perform one or more big stores into memory.
9553 unsigned E = (ToEltSz*NumElems)/StoreType.getSizeInBits();
9554 for (unsigned I = 0; I < E; I++) {
9555 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
9556 StoreType, ShuffWide,
9557 DAG.getIntPtrConstant(I, DL));
9558 SDValue Ch = DAG.getStore(St->getChain(), DL, SubVec, BasePtr,
9559 St->getPointerInfo(), St->isVolatile(),
9560 St->isNonTemporal(), St->getAlignment());
9561 BasePtr = DAG.getNode(ISD::ADD, DL, BasePtr.getValueType(), BasePtr,
9563 Chains.push_back(Ch);
9565 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
9568 if (!ISD::isNormalStore(St))
9571 // Split a store of a VMOVDRR into two integer stores to avoid mixing NEON and
9572 // ARM stores of arguments in the same cache line.
9573 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR &&
9574 StVal.getNode()->hasOneUse()) {
9575 SelectionDAG &DAG = DCI.DAG;
9576 bool isBigEndian = DAG.getDataLayout().isBigEndian();
9578 SDValue BasePtr = St->getBasePtr();
9579 SDValue NewST1 = DAG.getStore(St->getChain(), DL,
9580 StVal.getNode()->getOperand(isBigEndian ? 1 : 0 ),
9581 BasePtr, St->getPointerInfo(), St->isVolatile(),
9582 St->isNonTemporal(), St->getAlignment());
9584 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
9585 DAG.getConstant(4, DL, MVT::i32));
9586 return DAG.getStore(NewST1.getValue(0), DL,
9587 StVal.getNode()->getOperand(isBigEndian ? 0 : 1),
9588 OffsetPtr, St->getPointerInfo(), St->isVolatile(),
9589 St->isNonTemporal(),
9590 std::min(4U, St->getAlignment() / 2));
9593 if (StVal.getValueType() == MVT::i64 &&
9594 StVal.getNode()->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
9596 // Bitcast an i64 store extracted from a vector to f64.
9597 // Otherwise, the i64 value will be legalized to a pair of i32 values.
9598 SelectionDAG &DAG = DCI.DAG;
9600 SDValue IntVec = StVal.getOperand(0);
9601 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
9602 IntVec.getValueType().getVectorNumElements());
9603 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec);
9604 SDValue ExtElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
9605 Vec, StVal.getOperand(1));
9607 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt);
9608 // Make the DAGCombiner fold the bitcasts.
9609 DCI.AddToWorklist(Vec.getNode());
9610 DCI.AddToWorklist(ExtElt.getNode());
9611 DCI.AddToWorklist(V.getNode());
9612 return DAG.getStore(St->getChain(), dl, V, St->getBasePtr(),
9613 St->getPointerInfo(), St->isVolatile(),
9614 St->isNonTemporal(), St->getAlignment(),
9618 // If this is a legal vector store, try to combine it into a VST1_UPD.
9619 if (ISD::isNormalStore(N) && VT.isVector() &&
9620 DCI.DAG.getTargetLoweringInfo().isTypeLegal(VT))
9621 return CombineBaseUpdate(N, DCI);
9626 // isConstVecPow2 - Return true if each vector element is a power of 2, all
9627 // elements are the same constant, C, and Log2(C) ranges from 1 to 32.
9628 static bool isConstVecPow2(SDValue ConstVec, bool isSigned, uint64_t &C)
9632 for (unsigned I = 0, E = ConstVec.getValueType().getVectorNumElements();
9634 ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(ConstVec.getOperand(I));
9639 APFloat APF = C->getValueAPF();
9640 if (APF.convertToInteger(&cN, 64, isSigned, APFloat::rmTowardZero, &isExact)
9641 != APFloat::opOK || !isExact)
9644 c0 = (I == 0) ? cN : c0;
9645 if (!isPowerOf2_64(cN) || c0 != cN || Log2_64(c0) < 1 || Log2_64(c0) > 32)
9652 /// PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD)
9653 /// can replace combinations of VMUL and VCVT (floating-point to integer)
9654 /// when the VMUL has a constant operand that is a power of 2.
9656 /// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
9657 /// vmul.f32 d16, d17, d16
9658 /// vcvt.s32.f32 d16, d16
9660 /// vcvt.s32.f32 d16, d16, #3
9661 static SDValue PerformVCVTCombine(SDNode *N,
9662 TargetLowering::DAGCombinerInfo &DCI,
9663 const ARMSubtarget *Subtarget) {
9664 SelectionDAG &DAG = DCI.DAG;
9665 SDValue Op = N->getOperand(0);
9667 if (!Subtarget->hasNEON() || !Op.getValueType().isVector() ||
9668 Op.getOpcode() != ISD::FMUL)
9672 SDValue N0 = Op->getOperand(0);
9673 SDValue ConstVec = Op->getOperand(1);
9674 bool isSigned = N->getOpcode() == ISD::FP_TO_SINT;
9676 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
9677 !isConstVecPow2(ConstVec, isSigned, C))
9680 MVT FloatTy = Op.getSimpleValueType().getVectorElementType();
9681 MVT IntTy = N->getSimpleValueType(0).getVectorElementType();
9682 unsigned NumLanes = Op.getValueType().getVectorNumElements();
9683 if (FloatTy.getSizeInBits() != 32 || IntTy.getSizeInBits() > 32 ||
9685 // These instructions only exist converting from f32 to i32. We can handle
9686 // smaller integers by generating an extra truncate, but larger ones would
9687 // be lossy. We also can't handle more then 4 lanes, since these intructions
9688 // only support v2i32/v4i32 types.
9693 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfp2fxs :
9694 Intrinsic::arm_neon_vcvtfp2fxu;
9695 SDValue FixConv = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl,
9696 NumLanes == 2 ? MVT::v2i32 : MVT::v4i32,
9697 DAG.getConstant(IntrinsicOpcode, dl, MVT::i32),
9699 DAG.getConstant(Log2_64(C), dl, MVT::i32));
9701 if (IntTy.getSizeInBits() < FloatTy.getSizeInBits())
9702 FixConv = DAG.getNode(ISD::TRUNCATE, dl, N->getValueType(0), FixConv);
9707 /// PerformVDIVCombine - VCVT (fixed-point to floating-point, Advanced SIMD)
9708 /// can replace combinations of VCVT (integer to floating-point) and VDIV
9709 /// when the VDIV has a constant operand that is a power of 2.
9711 /// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
9712 /// vcvt.f32.s32 d16, d16
9713 /// vdiv.f32 d16, d17, d16
9715 /// vcvt.f32.s32 d16, d16, #3
9716 static SDValue PerformVDIVCombine(SDNode *N,
9717 TargetLowering::DAGCombinerInfo &DCI,
9718 const ARMSubtarget *Subtarget) {
9719 SelectionDAG &DAG = DCI.DAG;
9720 SDValue Op = N->getOperand(0);
9721 unsigned OpOpcode = Op.getNode()->getOpcode();
9723 if (!Subtarget->hasNEON() || !N->getValueType(0).isVector() ||
9724 (OpOpcode != ISD::SINT_TO_FP && OpOpcode != ISD::UINT_TO_FP))
9728 SDValue ConstVec = N->getOperand(1);
9729 bool isSigned = OpOpcode == ISD::SINT_TO_FP;
9731 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
9732 !isConstVecPow2(ConstVec, isSigned, C))
9735 MVT FloatTy = N->getSimpleValueType(0).getVectorElementType();
9736 MVT IntTy = Op.getOperand(0).getSimpleValueType().getVectorElementType();
9737 if (FloatTy.getSizeInBits() != 32 || IntTy.getSizeInBits() > 32) {
9738 // These instructions only exist converting from i32 to f32. We can handle
9739 // smaller integers by generating an extra extend, but larger ones would
9745 SDValue ConvInput = Op.getOperand(0);
9746 unsigned NumLanes = Op.getValueType().getVectorNumElements();
9747 if (IntTy.getSizeInBits() < FloatTy.getSizeInBits())
9748 ConvInput = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
9749 dl, NumLanes == 2 ? MVT::v2i32 : MVT::v4i32,
9752 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfxs2fp :
9753 Intrinsic::arm_neon_vcvtfxu2fp;
9754 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl,
9756 DAG.getConstant(IntrinsicOpcode, dl, MVT::i32),
9757 ConvInput, DAG.getConstant(Log2_64(C), dl, MVT::i32));
9760 /// Getvshiftimm - Check if this is a valid build_vector for the immediate
9761 /// operand of a vector shift operation, where all the elements of the
9762 /// build_vector must have the same constant integer value.
9763 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
9764 // Ignore bit_converts.
9765 while (Op.getOpcode() == ISD::BITCAST)
9766 Op = Op.getOperand(0);
9767 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
9768 APInt SplatBits, SplatUndef;
9769 unsigned SplatBitSize;
9771 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
9772 HasAnyUndefs, ElementBits) ||
9773 SplatBitSize > ElementBits)
9775 Cnt = SplatBits.getSExtValue();
9779 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
9780 /// operand of a vector shift left operation. That value must be in the range:
9781 /// 0 <= Value < ElementBits for a left shift; or
9782 /// 0 <= Value <= ElementBits for a long left shift.
9783 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
9784 assert(VT.isVector() && "vector shift count is not a vector type");
9785 int64_t ElementBits = VT.getVectorElementType().getSizeInBits();
9786 if (! getVShiftImm(Op, ElementBits, Cnt))
9788 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
9791 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
9792 /// operand of a vector shift right operation. For a shift opcode, the value
9793 /// is positive, but for an intrinsic the value count must be negative. The
9794 /// absolute value must be in the range:
9795 /// 1 <= |Value| <= ElementBits for a right shift; or
9796 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
9797 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
9799 assert(VT.isVector() && "vector shift count is not a vector type");
9800 int64_t ElementBits = VT.getVectorElementType().getSizeInBits();
9801 if (! getVShiftImm(Op, ElementBits, Cnt))
9804 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
9805 if (Cnt >= -(isNarrow ? ElementBits/2 : ElementBits) && Cnt <= -1) {
9812 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
9813 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
9814 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
9817 // Don't do anything for most intrinsics.
9820 case Intrinsic::arm_neon_vabds:
9821 if (!N->getValueType(0).isInteger())
9823 return DAG.getNode(ISD::SABSDIFF, SDLoc(N), N->getValueType(0),
9824 N->getOperand(1), N->getOperand(2));
9825 case Intrinsic::arm_neon_vabdu:
9826 return DAG.getNode(ISD::UABSDIFF, SDLoc(N), N->getValueType(0),
9827 N->getOperand(1), N->getOperand(2));
9829 // Vector shifts: check for immediate versions and lower them.
9830 // Note: This is done during DAG combining instead of DAG legalizing because
9831 // the build_vectors for 64-bit vector element shift counts are generally
9832 // not legal, and it is hard to see their values after they get legalized to
9833 // loads from a constant pool.
9834 case Intrinsic::arm_neon_vshifts:
9835 case Intrinsic::arm_neon_vshiftu:
9836 case Intrinsic::arm_neon_vrshifts:
9837 case Intrinsic::arm_neon_vrshiftu:
9838 case Intrinsic::arm_neon_vrshiftn:
9839 case Intrinsic::arm_neon_vqshifts:
9840 case Intrinsic::arm_neon_vqshiftu:
9841 case Intrinsic::arm_neon_vqshiftsu:
9842 case Intrinsic::arm_neon_vqshiftns:
9843 case Intrinsic::arm_neon_vqshiftnu:
9844 case Intrinsic::arm_neon_vqshiftnsu:
9845 case Intrinsic::arm_neon_vqrshiftns:
9846 case Intrinsic::arm_neon_vqrshiftnu:
9847 case Intrinsic::arm_neon_vqrshiftnsu: {
9848 EVT VT = N->getOperand(1).getValueType();
9850 unsigned VShiftOpc = 0;
9853 case Intrinsic::arm_neon_vshifts:
9854 case Intrinsic::arm_neon_vshiftu:
9855 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
9856 VShiftOpc = ARMISD::VSHL;
9859 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
9860 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
9861 ARMISD::VSHRs : ARMISD::VSHRu);
9866 case Intrinsic::arm_neon_vrshifts:
9867 case Intrinsic::arm_neon_vrshiftu:
9868 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
9872 case Intrinsic::arm_neon_vqshifts:
9873 case Intrinsic::arm_neon_vqshiftu:
9874 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
9878 case Intrinsic::arm_neon_vqshiftsu:
9879 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
9881 llvm_unreachable("invalid shift count for vqshlu intrinsic");
9883 case Intrinsic::arm_neon_vrshiftn:
9884 case Intrinsic::arm_neon_vqshiftns:
9885 case Intrinsic::arm_neon_vqshiftnu:
9886 case Intrinsic::arm_neon_vqshiftnsu:
9887 case Intrinsic::arm_neon_vqrshiftns:
9888 case Intrinsic::arm_neon_vqrshiftnu:
9889 case Intrinsic::arm_neon_vqrshiftnsu:
9890 // Narrowing shifts require an immediate right shift.
9891 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
9893 llvm_unreachable("invalid shift count for narrowing vector shift "
9897 llvm_unreachable("unhandled vector shift");
9901 case Intrinsic::arm_neon_vshifts:
9902 case Intrinsic::arm_neon_vshiftu:
9903 // Opcode already set above.
9905 case Intrinsic::arm_neon_vrshifts:
9906 VShiftOpc = ARMISD::VRSHRs; break;
9907 case Intrinsic::arm_neon_vrshiftu:
9908 VShiftOpc = ARMISD::VRSHRu; break;
9909 case Intrinsic::arm_neon_vrshiftn:
9910 VShiftOpc = ARMISD::VRSHRN; break;
9911 case Intrinsic::arm_neon_vqshifts:
9912 VShiftOpc = ARMISD::VQSHLs; break;
9913 case Intrinsic::arm_neon_vqshiftu:
9914 VShiftOpc = ARMISD::VQSHLu; break;
9915 case Intrinsic::arm_neon_vqshiftsu:
9916 VShiftOpc = ARMISD::VQSHLsu; break;
9917 case Intrinsic::arm_neon_vqshiftns:
9918 VShiftOpc = ARMISD::VQSHRNs; break;
9919 case Intrinsic::arm_neon_vqshiftnu:
9920 VShiftOpc = ARMISD::VQSHRNu; break;
9921 case Intrinsic::arm_neon_vqshiftnsu:
9922 VShiftOpc = ARMISD::VQSHRNsu; break;
9923 case Intrinsic::arm_neon_vqrshiftns:
9924 VShiftOpc = ARMISD::VQRSHRNs; break;
9925 case Intrinsic::arm_neon_vqrshiftnu:
9926 VShiftOpc = ARMISD::VQRSHRNu; break;
9927 case Intrinsic::arm_neon_vqrshiftnsu:
9928 VShiftOpc = ARMISD::VQRSHRNsu; break;
9932 return DAG.getNode(VShiftOpc, dl, N->getValueType(0),
9933 N->getOperand(1), DAG.getConstant(Cnt, dl, MVT::i32));
9936 case Intrinsic::arm_neon_vshiftins: {
9937 EVT VT = N->getOperand(1).getValueType();
9939 unsigned VShiftOpc = 0;
9941 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
9942 VShiftOpc = ARMISD::VSLI;
9943 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
9944 VShiftOpc = ARMISD::VSRI;
9946 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
9950 return DAG.getNode(VShiftOpc, dl, N->getValueType(0),
9951 N->getOperand(1), N->getOperand(2),
9952 DAG.getConstant(Cnt, dl, MVT::i32));
9955 case Intrinsic::arm_neon_vqrshifts:
9956 case Intrinsic::arm_neon_vqrshiftu:
9957 // No immediate versions of these to check for.
9964 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
9965 /// lowers them. As with the vector shift intrinsics, this is done during DAG
9966 /// combining instead of DAG legalizing because the build_vectors for 64-bit
9967 /// vector element shift counts are generally not legal, and it is hard to see
9968 /// their values after they get legalized to loads from a constant pool.
9969 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
9970 const ARMSubtarget *ST) {
9971 EVT VT = N->getValueType(0);
9972 if (N->getOpcode() == ISD::SRL && VT == MVT::i32 && ST->hasV6Ops()) {
9973 // Canonicalize (srl (bswap x), 16) to (rotr (bswap x), 16) if the high
9974 // 16-bits of x is zero. This optimizes rev + lsr 16 to rev16.
9975 SDValue N1 = N->getOperand(1);
9976 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
9977 SDValue N0 = N->getOperand(0);
9978 if (C->getZExtValue() == 16 && N0.getOpcode() == ISD::BSWAP &&
9979 DAG.MaskedValueIsZero(N0.getOperand(0),
9980 APInt::getHighBitsSet(32, 16)))
9981 return DAG.getNode(ISD::ROTR, SDLoc(N), VT, N0, N1);
9985 // Nothing to be done for scalar shifts.
9986 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9987 if (!VT.isVector() || !TLI.isTypeLegal(VT))
9990 assert(ST->hasNEON() && "unexpected vector shift");
9993 switch (N->getOpcode()) {
9994 default: llvm_unreachable("unexpected shift opcode");
9997 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt)) {
9999 return DAG.getNode(ARMISD::VSHL, dl, VT, N->getOperand(0),
10000 DAG.getConstant(Cnt, dl, MVT::i32));
10006 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
10007 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
10008 ARMISD::VSHRs : ARMISD::VSHRu);
10010 return DAG.getNode(VShiftOpc, dl, VT, N->getOperand(0),
10011 DAG.getConstant(Cnt, dl, MVT::i32));
10017 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
10018 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
10019 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
10020 const ARMSubtarget *ST) {
10021 SDValue N0 = N->getOperand(0);
10023 // Check for sign- and zero-extensions of vector extract operations of 8-
10024 // and 16-bit vector elements. NEON supports these directly. They are
10025 // handled during DAG combining because type legalization will promote them
10026 // to 32-bit types and it is messy to recognize the operations after that.
10027 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
10028 SDValue Vec = N0.getOperand(0);
10029 SDValue Lane = N0.getOperand(1);
10030 EVT VT = N->getValueType(0);
10031 EVT EltVT = N0.getValueType();
10032 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
10034 if (VT == MVT::i32 &&
10035 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
10036 TLI.isTypeLegal(Vec.getValueType()) &&
10037 isa<ConstantSDNode>(Lane)) {
10040 switch (N->getOpcode()) {
10041 default: llvm_unreachable("unexpected opcode");
10042 case ISD::SIGN_EXTEND:
10043 Opc = ARMISD::VGETLANEs;
10045 case ISD::ZERO_EXTEND:
10046 case ISD::ANY_EXTEND:
10047 Opc = ARMISD::VGETLANEu;
10050 return DAG.getNode(Opc, SDLoc(N), VT, Vec, Lane);
10057 /// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
10058 /// to match f32 max/min patterns to use NEON vmax/vmin instructions.
10059 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
10060 const ARMSubtarget *ST) {
10061 // If the target supports NEON, try to use vmax/vmin instructions for f32
10062 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set,
10063 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
10064 // a NaN; only do the transformation when it matches that behavior.
10066 // For now only do this when using NEON for FP operations; if using VFP, it
10067 // is not obvious that the benefit outweighs the cost of switching to the
10069 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
10070 N->getValueType(0) != MVT::f32)
10073 SDValue CondLHS = N->getOperand(0);
10074 SDValue CondRHS = N->getOperand(1);
10075 SDValue LHS = N->getOperand(2);
10076 SDValue RHS = N->getOperand(3);
10077 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
10079 unsigned Opcode = 0;
10081 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
10082 IsReversed = false; // x CC y ? x : y
10083 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
10084 IsReversed = true ; // x CC y ? y : x
10098 // If LHS is NaN, an ordered comparison will be false and the result will
10099 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
10100 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
10101 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
10102 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
10104 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
10105 // will return -0, so vmin can only be used for unsafe math or if one of
10106 // the operands is known to be nonzero.
10107 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
10108 !DAG.getTarget().Options.UnsafeFPMath &&
10109 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
10111 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
10120 // If LHS is NaN, an ordered comparison will be false and the result will
10121 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
10122 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
10123 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
10124 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
10126 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
10127 // will return +0, so vmax can only be used for unsafe math or if one of
10128 // the operands is known to be nonzero.
10129 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
10130 !DAG.getTarget().Options.UnsafeFPMath &&
10131 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
10133 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
10139 return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), LHS, RHS);
10142 /// PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV.
10144 ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const {
10145 SDValue Cmp = N->getOperand(4);
10146 if (Cmp.getOpcode() != ARMISD::CMPZ)
10147 // Only looking at EQ and NE cases.
10150 EVT VT = N->getValueType(0);
10152 SDValue LHS = Cmp.getOperand(0);
10153 SDValue RHS = Cmp.getOperand(1);
10154 SDValue FalseVal = N->getOperand(0);
10155 SDValue TrueVal = N->getOperand(1);
10156 SDValue ARMcc = N->getOperand(2);
10157 ARMCC::CondCodes CC =
10158 (ARMCC::CondCodes)cast<ConstantSDNode>(ARMcc)->getZExtValue();
10176 /// FIXME: Turn this into a target neutral optimization?
10178 if (CC == ARMCC::NE && FalseVal == RHS && FalseVal != LHS) {
10179 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, TrueVal, ARMcc,
10180 N->getOperand(3), Cmp);
10181 } else if (CC == ARMCC::EQ && TrueVal == RHS) {
10183 SDValue NewCmp = getARMCmp(LHS, RHS, ISD::SETNE, ARMcc, DAG, dl);
10184 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, FalseVal, ARMcc,
10185 N->getOperand(3), NewCmp);
10188 if (Res.getNode()) {
10189 APInt KnownZero, KnownOne;
10190 DAG.computeKnownBits(SDValue(N,0), KnownZero, KnownOne);
10191 // Capture demanded bits information that would be otherwise lost.
10192 if (KnownZero == 0xfffffffe)
10193 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
10194 DAG.getValueType(MVT::i1));
10195 else if (KnownZero == 0xffffff00)
10196 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
10197 DAG.getValueType(MVT::i8));
10198 else if (KnownZero == 0xffff0000)
10199 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
10200 DAG.getValueType(MVT::i16));
10206 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
10207 DAGCombinerInfo &DCI) const {
10208 switch (N->getOpcode()) {
10210 case ISD::ADDC: return PerformADDCCombine(N, DCI, Subtarget);
10211 case ISD::ADD: return PerformADDCombine(N, DCI, Subtarget);
10212 case ISD::SUB: return PerformSUBCombine(N, DCI);
10213 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
10214 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
10215 case ISD::XOR: return PerformXORCombine(N, DCI, Subtarget);
10216 case ISD::AND: return PerformANDCombine(N, DCI, Subtarget);
10217 case ARMISD::BFI: return PerformBFICombine(N, DCI);
10218 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI, Subtarget);
10219 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
10220 case ISD::STORE: return PerformSTORECombine(N, DCI);
10221 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI, Subtarget);
10222 case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI);
10223 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
10224 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
10225 case ISD::FP_TO_SINT:
10226 case ISD::FP_TO_UINT: return PerformVCVTCombine(N, DCI, Subtarget);
10227 case ISD::FDIV: return PerformVDIVCombine(N, DCI, Subtarget);
10228 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
10231 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
10232 case ISD::SIGN_EXTEND:
10233 case ISD::ZERO_EXTEND:
10234 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
10235 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
10236 case ARMISD::CMOV: return PerformCMOVCombine(N, DCI.DAG);
10237 case ISD::LOAD: return PerformLOADCombine(N, DCI);
10238 case ARMISD::VLD2DUP:
10239 case ARMISD::VLD3DUP:
10240 case ARMISD::VLD4DUP:
10241 return PerformVLDCombine(N, DCI);
10242 case ARMISD::BUILD_VECTOR:
10243 return PerformARMBUILD_VECTORCombine(N, DCI);
10244 case ISD::INTRINSIC_VOID:
10245 case ISD::INTRINSIC_W_CHAIN:
10246 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
10247 case Intrinsic::arm_neon_vld1:
10248 case Intrinsic::arm_neon_vld2:
10249 case Intrinsic::arm_neon_vld3:
10250 case Intrinsic::arm_neon_vld4:
10251 case Intrinsic::arm_neon_vld2lane:
10252 case Intrinsic::arm_neon_vld3lane:
10253 case Intrinsic::arm_neon_vld4lane:
10254 case Intrinsic::arm_neon_vst1:
10255 case Intrinsic::arm_neon_vst2:
10256 case Intrinsic::arm_neon_vst3:
10257 case Intrinsic::arm_neon_vst4:
10258 case Intrinsic::arm_neon_vst2lane:
10259 case Intrinsic::arm_neon_vst3lane:
10260 case Intrinsic::arm_neon_vst4lane:
10261 return PerformVLDCombine(N, DCI);
10269 bool ARMTargetLowering::isDesirableToTransformToIntegerOp(unsigned Opc,
10271 return (VT == MVT::f32) && (Opc == ISD::LOAD || Opc == ISD::STORE);
10274 bool ARMTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
10277 bool *Fast) const {
10278 // The AllowsUnaliged flag models the SCTLR.A setting in ARM cpus
10279 bool AllowsUnaligned = Subtarget->allowsUnalignedMem();
10281 switch (VT.getSimpleVT().SimpleTy) {
10287 // Unaligned access can use (for example) LRDB, LRDH, LDR
10288 if (AllowsUnaligned) {
10290 *Fast = Subtarget->hasV7Ops();
10297 // For any little-endian targets with neon, we can support unaligned ld/st
10298 // of D and Q (e.g. {D0,D1}) registers by using vld1.i8/vst1.i8.
10299 // A big-endian target may also explicitly support unaligned accesses
10300 if (Subtarget->hasNEON() && (AllowsUnaligned || Subtarget->isLittle())) {
10310 static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign,
10311 unsigned AlignCheck) {
10312 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) &&
10313 (DstAlign == 0 || DstAlign % AlignCheck == 0));
10316 EVT ARMTargetLowering::getOptimalMemOpType(uint64_t Size,
10317 unsigned DstAlign, unsigned SrcAlign,
10318 bool IsMemset, bool ZeroMemset,
10320 MachineFunction &MF) const {
10321 const Function *F = MF.getFunction();
10323 // See if we can use NEON instructions for this...
10324 if ((!IsMemset || ZeroMemset) && Subtarget->hasNEON() &&
10325 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
10328 (memOpAlign(SrcAlign, DstAlign, 16) ||
10329 (allowsMisalignedMemoryAccesses(MVT::v2f64, 0, 1, &Fast) && Fast))) {
10331 } else if (Size >= 8 &&
10332 (memOpAlign(SrcAlign, DstAlign, 8) ||
10333 (allowsMisalignedMemoryAccesses(MVT::f64, 0, 1, &Fast) &&
10339 // Lowering to i32/i16 if the size permits.
10342 else if (Size >= 2)
10345 // Let the target-independent logic figure it out.
10349 bool ARMTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
10350 if (Val.getOpcode() != ISD::LOAD)
10353 EVT VT1 = Val.getValueType();
10354 if (!VT1.isSimple() || !VT1.isInteger() ||
10355 !VT2.isSimple() || !VT2.isInteger())
10358 switch (VT1.getSimpleVT().SimpleTy) {
10363 // 8-bit and 16-bit loads implicitly zero-extend to 32-bits.
10370 bool ARMTargetLowering::isVectorLoadExtDesirable(SDValue ExtVal) const {
10371 EVT VT = ExtVal.getValueType();
10373 if (!isTypeLegal(VT))
10376 // Don't create a loadext if we can fold the extension into a wide/long
10378 // If there's more than one user instruction, the loadext is desirable no
10379 // matter what. There can be two uses by the same instruction.
10380 if (ExtVal->use_empty() ||
10381 !ExtVal->use_begin()->isOnlyUserOf(ExtVal.getNode()))
10384 SDNode *U = *ExtVal->use_begin();
10385 if ((U->getOpcode() == ISD::ADD || U->getOpcode() == ISD::SUB ||
10386 U->getOpcode() == ISD::SHL || U->getOpcode() == ARMISD::VSHL))
10392 bool ARMTargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
10393 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
10396 if (!isTypeLegal(EVT::getEVT(Ty1)))
10399 assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
10401 // Assuming the caller doesn't have a zeroext or signext return parameter,
10402 // truncation all the way down to i1 is valid.
10407 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
10411 unsigned Scale = 1;
10412 switch (VT.getSimpleVT().SimpleTy) {
10413 default: return false;
10428 if ((V & (Scale - 1)) != 0)
10431 return V == (V & ((1LL << 5) - 1));
10434 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
10435 const ARMSubtarget *Subtarget) {
10436 bool isNeg = false;
10442 switch (VT.getSimpleVT().SimpleTy) {
10443 default: return false;
10448 // + imm12 or - imm8
10450 return V == (V & ((1LL << 8) - 1));
10451 return V == (V & ((1LL << 12) - 1));
10454 // Same as ARM mode. FIXME: NEON?
10455 if (!Subtarget->hasVFP2())
10460 return V == (V & ((1LL << 8) - 1));
10464 /// isLegalAddressImmediate - Return true if the integer value can be used
10465 /// as the offset of the target addressing mode for load / store of the
10467 static bool isLegalAddressImmediate(int64_t V, EVT VT,
10468 const ARMSubtarget *Subtarget) {
10472 if (!VT.isSimple())
10475 if (Subtarget->isThumb1Only())
10476 return isLegalT1AddressImmediate(V, VT);
10477 else if (Subtarget->isThumb2())
10478 return isLegalT2AddressImmediate(V, VT, Subtarget);
10483 switch (VT.getSimpleVT().SimpleTy) {
10484 default: return false;
10489 return V == (V & ((1LL << 12) - 1));
10492 return V == (V & ((1LL << 8) - 1));
10495 if (!Subtarget->hasVFP2()) // FIXME: NEON?
10500 return V == (V & ((1LL << 8) - 1));
10504 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
10506 int Scale = AM.Scale;
10510 switch (VT.getSimpleVT().SimpleTy) {
10511 default: return false;
10519 Scale = Scale & ~1;
10520 return Scale == 2 || Scale == 4 || Scale == 8;
10523 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
10527 // Note, we allow "void" uses (basically, uses that aren't loads or
10528 // stores), because arm allows folding a scale into many arithmetic
10529 // operations. This should be made more precise and revisited later.
10531 // Allow r << imm, but the imm has to be a multiple of two.
10532 if (Scale & 1) return false;
10533 return isPowerOf2_32(Scale);
10537 /// isLegalAddressingMode - Return true if the addressing mode represented
10538 /// by AM is legal for this target, for a load/store of the specified type.
10539 bool ARMTargetLowering::isLegalAddressingMode(const DataLayout &DL,
10540 const AddrMode &AM, Type *Ty,
10541 unsigned AS) const {
10542 EVT VT = getValueType(DL, Ty, true);
10543 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
10546 // Can never fold addr of global into load/store.
10550 switch (AM.Scale) {
10551 case 0: // no scale reg, must be "r+i" or "r", or "i".
10554 if (Subtarget->isThumb1Only())
10558 // ARM doesn't support any R+R*scale+imm addr modes.
10562 if (!VT.isSimple())
10565 if (Subtarget->isThumb2())
10566 return isLegalT2ScaledAddressingMode(AM, VT);
10568 int Scale = AM.Scale;
10569 switch (VT.getSimpleVT().SimpleTy) {
10570 default: return false;
10574 if (Scale < 0) Scale = -Scale;
10578 return isPowerOf2_32(Scale & ~1);
10582 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
10587 // Note, we allow "void" uses (basically, uses that aren't loads or
10588 // stores), because arm allows folding a scale into many arithmetic
10589 // operations. This should be made more precise and revisited later.
10591 // Allow r << imm, but the imm has to be a multiple of two.
10592 if (Scale & 1) return false;
10593 return isPowerOf2_32(Scale);
10599 /// isLegalICmpImmediate - Return true if the specified immediate is legal
10600 /// icmp immediate, that is the target has icmp instructions which can compare
10601 /// a register against the immediate without having to materialize the
10602 /// immediate into a register.
10603 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
10604 // Thumb2 and ARM modes can use cmn for negative immediates.
10605 if (!Subtarget->isThumb())
10606 return ARM_AM::getSOImmVal(std::abs(Imm)) != -1;
10607 if (Subtarget->isThumb2())
10608 return ARM_AM::getT2SOImmVal(std::abs(Imm)) != -1;
10609 // Thumb1 doesn't have cmn, and only 8-bit immediates.
10610 return Imm >= 0 && Imm <= 255;
10613 /// isLegalAddImmediate - Return true if the specified immediate is a legal add
10614 /// *or sub* immediate, that is the target has add or sub instructions which can
10615 /// add a register with the immediate without having to materialize the
10616 /// immediate into a register.
10617 bool ARMTargetLowering::isLegalAddImmediate(int64_t Imm) const {
10618 // Same encoding for add/sub, just flip the sign.
10619 int64_t AbsImm = std::abs(Imm);
10620 if (!Subtarget->isThumb())
10621 return ARM_AM::getSOImmVal(AbsImm) != -1;
10622 if (Subtarget->isThumb2())
10623 return ARM_AM::getT2SOImmVal(AbsImm) != -1;
10624 // Thumb1 only has 8-bit unsigned immediate.
10625 return AbsImm >= 0 && AbsImm <= 255;
10628 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
10629 bool isSEXTLoad, SDValue &Base,
10630 SDValue &Offset, bool &isInc,
10631 SelectionDAG &DAG) {
10632 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
10635 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
10636 // AddressingMode 3
10637 Base = Ptr->getOperand(0);
10638 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
10639 int RHSC = (int)RHS->getZExtValue();
10640 if (RHSC < 0 && RHSC > -256) {
10641 assert(Ptr->getOpcode() == ISD::ADD);
10643 Offset = DAG.getConstant(-RHSC, SDLoc(Ptr), RHS->getValueType(0));
10647 isInc = (Ptr->getOpcode() == ISD::ADD);
10648 Offset = Ptr->getOperand(1);
10650 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
10651 // AddressingMode 2
10652 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
10653 int RHSC = (int)RHS->getZExtValue();
10654 if (RHSC < 0 && RHSC > -0x1000) {
10655 assert(Ptr->getOpcode() == ISD::ADD);
10657 Offset = DAG.getConstant(-RHSC, SDLoc(Ptr), RHS->getValueType(0));
10658 Base = Ptr->getOperand(0);
10663 if (Ptr->getOpcode() == ISD::ADD) {
10665 ARM_AM::ShiftOpc ShOpcVal=
10666 ARM_AM::getShiftOpcForNode(Ptr->getOperand(0).getOpcode());
10667 if (ShOpcVal != ARM_AM::no_shift) {
10668 Base = Ptr->getOperand(1);
10669 Offset = Ptr->getOperand(0);
10671 Base = Ptr->getOperand(0);
10672 Offset = Ptr->getOperand(1);
10677 isInc = (Ptr->getOpcode() == ISD::ADD);
10678 Base = Ptr->getOperand(0);
10679 Offset = Ptr->getOperand(1);
10683 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
10687 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
10688 bool isSEXTLoad, SDValue &Base,
10689 SDValue &Offset, bool &isInc,
10690 SelectionDAG &DAG) {
10691 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
10694 Base = Ptr->getOperand(0);
10695 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
10696 int RHSC = (int)RHS->getZExtValue();
10697 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
10698 assert(Ptr->getOpcode() == ISD::ADD);
10700 Offset = DAG.getConstant(-RHSC, SDLoc(Ptr), RHS->getValueType(0));
10702 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
10703 isInc = Ptr->getOpcode() == ISD::ADD;
10704 Offset = DAG.getConstant(RHSC, SDLoc(Ptr), RHS->getValueType(0));
10712 /// getPreIndexedAddressParts - returns true by value, base pointer and
10713 /// offset pointer and addressing mode by reference if the node's address
10714 /// can be legally represented as pre-indexed load / store address.
10716 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
10718 ISD::MemIndexedMode &AM,
10719 SelectionDAG &DAG) const {
10720 if (Subtarget->isThumb1Only())
10725 bool isSEXTLoad = false;
10726 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
10727 Ptr = LD->getBasePtr();
10728 VT = LD->getMemoryVT();
10729 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
10730 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
10731 Ptr = ST->getBasePtr();
10732 VT = ST->getMemoryVT();
10737 bool isLegal = false;
10738 if (Subtarget->isThumb2())
10739 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
10740 Offset, isInc, DAG);
10742 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
10743 Offset, isInc, DAG);
10747 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
10751 /// getPostIndexedAddressParts - returns true by value, base pointer and
10752 /// offset pointer and addressing mode by reference if this node can be
10753 /// combined with a load / store to form a post-indexed load / store.
10754 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
10757 ISD::MemIndexedMode &AM,
10758 SelectionDAG &DAG) const {
10759 if (Subtarget->isThumb1Only())
10764 bool isSEXTLoad = false;
10765 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
10766 VT = LD->getMemoryVT();
10767 Ptr = LD->getBasePtr();
10768 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
10769 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
10770 VT = ST->getMemoryVT();
10771 Ptr = ST->getBasePtr();
10776 bool isLegal = false;
10777 if (Subtarget->isThumb2())
10778 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
10781 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
10787 // Swap base ptr and offset to catch more post-index load / store when
10788 // it's legal. In Thumb2 mode, offset must be an immediate.
10789 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
10790 !Subtarget->isThumb2())
10791 std::swap(Base, Offset);
10793 // Post-indexed load / store update the base pointer.
10798 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
10802 void ARMTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
10805 const SelectionDAG &DAG,
10806 unsigned Depth) const {
10807 unsigned BitWidth = KnownOne.getBitWidth();
10808 KnownZero = KnownOne = APInt(BitWidth, 0);
10809 switch (Op.getOpcode()) {
10815 // These nodes' second result is a boolean
10816 if (Op.getResNo() == 0)
10818 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
10820 case ARMISD::CMOV: {
10821 // Bits are known zero/one if known on the LHS and RHS.
10822 DAG.computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1);
10823 if (KnownZero == 0 && KnownOne == 0) return;
10825 APInt KnownZeroRHS, KnownOneRHS;
10826 DAG.computeKnownBits(Op.getOperand(1), KnownZeroRHS, KnownOneRHS, Depth+1);
10827 KnownZero &= KnownZeroRHS;
10828 KnownOne &= KnownOneRHS;
10831 case ISD::INTRINSIC_W_CHAIN: {
10832 ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
10833 Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
10836 case Intrinsic::arm_ldaex:
10837 case Intrinsic::arm_ldrex: {
10838 EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();
10839 unsigned MemBits = VT.getScalarType().getSizeInBits();
10840 KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
10848 //===----------------------------------------------------------------------===//
10849 // ARM Inline Assembly Support
10850 //===----------------------------------------------------------------------===//
10852 bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const {
10853 // Looking for "rev" which is V6+.
10854 if (!Subtarget->hasV6Ops())
10857 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
10858 std::string AsmStr = IA->getAsmString();
10859 SmallVector<StringRef, 4> AsmPieces;
10860 SplitString(AsmStr, AsmPieces, ";\n");
10862 switch (AsmPieces.size()) {
10863 default: return false;
10865 AsmStr = AsmPieces[0];
10867 SplitString(AsmStr, AsmPieces, " \t,");
10870 if (AsmPieces.size() == 3 &&
10871 AsmPieces[0] == "rev" && AsmPieces[1] == "$0" && AsmPieces[2] == "$1" &&
10872 IA->getConstraintString().compare(0, 4, "=l,l") == 0) {
10873 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
10874 if (Ty && Ty->getBitWidth() == 32)
10875 return IntrinsicLowering::LowerToByteSwap(CI);
10883 /// getConstraintType - Given a constraint letter, return the type of
10884 /// constraint it is for this target.
10885 ARMTargetLowering::ConstraintType
10886 ARMTargetLowering::getConstraintType(StringRef Constraint) const {
10887 if (Constraint.size() == 1) {
10888 switch (Constraint[0]) {
10890 case 'l': return C_RegisterClass;
10891 case 'w': return C_RegisterClass;
10892 case 'h': return C_RegisterClass;
10893 case 'x': return C_RegisterClass;
10894 case 't': return C_RegisterClass;
10895 case 'j': return C_Other; // Constant for movw.
10896 // An address with a single base register. Due to the way we
10897 // currently handle addresses it is the same as an 'r' memory constraint.
10898 case 'Q': return C_Memory;
10900 } else if (Constraint.size() == 2) {
10901 switch (Constraint[0]) {
10903 // All 'U+' constraints are addresses.
10904 case 'U': return C_Memory;
10907 return TargetLowering::getConstraintType(Constraint);
10910 /// Examine constraint type and operand type and determine a weight value.
10911 /// This object must already have been set up with the operand type
10912 /// and the current alternative constraint selected.
10913 TargetLowering::ConstraintWeight
10914 ARMTargetLowering::getSingleConstraintMatchWeight(
10915 AsmOperandInfo &info, const char *constraint) const {
10916 ConstraintWeight weight = CW_Invalid;
10917 Value *CallOperandVal = info.CallOperandVal;
10918 // If we don't have a value, we can't do a match,
10919 // but allow it at the lowest weight.
10920 if (!CallOperandVal)
10922 Type *type = CallOperandVal->getType();
10923 // Look at the constraint type.
10924 switch (*constraint) {
10926 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
10929 if (type->isIntegerTy()) {
10930 if (Subtarget->isThumb())
10931 weight = CW_SpecificReg;
10933 weight = CW_Register;
10937 if (type->isFloatingPointTy())
10938 weight = CW_Register;
10944 typedef std::pair<unsigned, const TargetRegisterClass*> RCPair;
10945 RCPair ARMTargetLowering::getRegForInlineAsmConstraint(
10946 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
10947 if (Constraint.size() == 1) {
10948 // GCC ARM Constraint Letters
10949 switch (Constraint[0]) {
10950 case 'l': // Low regs or general regs.
10951 if (Subtarget->isThumb())
10952 return RCPair(0U, &ARM::tGPRRegClass);
10953 return RCPair(0U, &ARM::GPRRegClass);
10954 case 'h': // High regs or no regs.
10955 if (Subtarget->isThumb())
10956 return RCPair(0U, &ARM::hGPRRegClass);
10959 if (Subtarget->isThumb1Only())
10960 return RCPair(0U, &ARM::tGPRRegClass);
10961 return RCPair(0U, &ARM::GPRRegClass);
10963 if (VT == MVT::Other)
10965 if (VT == MVT::f32)
10966 return RCPair(0U, &ARM::SPRRegClass);
10967 if (VT.getSizeInBits() == 64)
10968 return RCPair(0U, &ARM::DPRRegClass);
10969 if (VT.getSizeInBits() == 128)
10970 return RCPair(0U, &ARM::QPRRegClass);
10973 if (VT == MVT::Other)
10975 if (VT == MVT::f32)
10976 return RCPair(0U, &ARM::SPR_8RegClass);
10977 if (VT.getSizeInBits() == 64)
10978 return RCPair(0U, &ARM::DPR_8RegClass);
10979 if (VT.getSizeInBits() == 128)
10980 return RCPair(0U, &ARM::QPR_8RegClass);
10983 if (VT == MVT::f32)
10984 return RCPair(0U, &ARM::SPRRegClass);
10988 if (StringRef("{cc}").equals_lower(Constraint))
10989 return std::make_pair(unsigned(ARM::CPSR), &ARM::CCRRegClass);
10991 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
10994 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
10995 /// vector. If it is invalid, don't add anything to Ops.
10996 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
10997 std::string &Constraint,
10998 std::vector<SDValue>&Ops,
10999 SelectionDAG &DAG) const {
11002 // Currently only support length 1 constraints.
11003 if (Constraint.length() != 1) return;
11005 char ConstraintLetter = Constraint[0];
11006 switch (ConstraintLetter) {
11009 case 'I': case 'J': case 'K': case 'L':
11010 case 'M': case 'N': case 'O':
11011 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
11015 int64_t CVal64 = C->getSExtValue();
11016 int CVal = (int) CVal64;
11017 // None of these constraints allow values larger than 32 bits. Check
11018 // that the value fits in an int.
11019 if (CVal != CVal64)
11022 switch (ConstraintLetter) {
11024 // Constant suitable for movw, must be between 0 and
11026 if (Subtarget->hasV6T2Ops())
11027 if (CVal >= 0 && CVal <= 65535)
11031 if (Subtarget->isThumb1Only()) {
11032 // This must be a constant between 0 and 255, for ADD
11034 if (CVal >= 0 && CVal <= 255)
11036 } else if (Subtarget->isThumb2()) {
11037 // A constant that can be used as an immediate value in a
11038 // data-processing instruction.
11039 if (ARM_AM::getT2SOImmVal(CVal) != -1)
11042 // A constant that can be used as an immediate value in a
11043 // data-processing instruction.
11044 if (ARM_AM::getSOImmVal(CVal) != -1)
11050 if (Subtarget->isThumb()) { // FIXME thumb2
11051 // This must be a constant between -255 and -1, for negated ADD
11052 // immediates. This can be used in GCC with an "n" modifier that
11053 // prints the negated value, for use with SUB instructions. It is
11054 // not useful otherwise but is implemented for compatibility.
11055 if (CVal >= -255 && CVal <= -1)
11058 // This must be a constant between -4095 and 4095. It is not clear
11059 // what this constraint is intended for. Implemented for
11060 // compatibility with GCC.
11061 if (CVal >= -4095 && CVal <= 4095)
11067 if (Subtarget->isThumb1Only()) {
11068 // A 32-bit value where only one byte has a nonzero value. Exclude
11069 // zero to match GCC. This constraint is used by GCC internally for
11070 // constants that can be loaded with a move/shift combination.
11071 // It is not useful otherwise but is implemented for compatibility.
11072 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
11074 } else if (Subtarget->isThumb2()) {
11075 // A constant whose bitwise inverse can be used as an immediate
11076 // value in a data-processing instruction. This can be used in GCC
11077 // with a "B" modifier that prints the inverted value, for use with
11078 // BIC and MVN instructions. It is not useful otherwise but is
11079 // implemented for compatibility.
11080 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
11083 // A constant whose bitwise inverse can be used as an immediate
11084 // value in a data-processing instruction. This can be used in GCC
11085 // with a "B" modifier that prints the inverted value, for use with
11086 // BIC and MVN instructions. It is not useful otherwise but is
11087 // implemented for compatibility.
11088 if (ARM_AM::getSOImmVal(~CVal) != -1)
11094 if (Subtarget->isThumb1Only()) {
11095 // This must be a constant between -7 and 7,
11096 // for 3-operand ADD/SUB immediate instructions.
11097 if (CVal >= -7 && CVal < 7)
11099 } else if (Subtarget->isThumb2()) {
11100 // A constant whose negation can be used as an immediate value in a
11101 // data-processing instruction. This can be used in GCC with an "n"
11102 // modifier that prints the negated value, for use with SUB
11103 // instructions. It is not useful otherwise but is implemented for
11105 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
11108 // A constant whose negation can be used as an immediate value in a
11109 // data-processing instruction. This can be used in GCC with an "n"
11110 // modifier that prints the negated value, for use with SUB
11111 // instructions. It is not useful otherwise but is implemented for
11113 if (ARM_AM::getSOImmVal(-CVal) != -1)
11119 if (Subtarget->isThumb()) { // FIXME thumb2
11120 // This must be a multiple of 4 between 0 and 1020, for
11121 // ADD sp + immediate.
11122 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
11125 // A power of two or a constant between 0 and 32. This is used in
11126 // GCC for the shift amount on shifted register operands, but it is
11127 // useful in general for any shift amounts.
11128 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
11134 if (Subtarget->isThumb()) { // FIXME thumb2
11135 // This must be a constant between 0 and 31, for shift amounts.
11136 if (CVal >= 0 && CVal <= 31)
11142 if (Subtarget->isThumb()) { // FIXME thumb2
11143 // This must be a multiple of 4 between -508 and 508, for
11144 // ADD/SUB sp = sp + immediate.
11145 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
11150 Result = DAG.getTargetConstant(CVal, SDLoc(Op), Op.getValueType());
11154 if (Result.getNode()) {
11155 Ops.push_back(Result);
11158 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
11161 SDValue ARMTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const {
11162 assert(Subtarget->isTargetAEABI() && "Register-based DivRem lowering only");
11163 unsigned Opcode = Op->getOpcode();
11164 assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
11165 "Invalid opcode for Div/Rem lowering");
11166 bool isSigned = (Opcode == ISD::SDIVREM);
11167 EVT VT = Op->getValueType(0);
11168 Type *Ty = VT.getTypeForEVT(*DAG.getContext());
11171 switch (VT.getSimpleVT().SimpleTy) {
11172 default: llvm_unreachable("Unexpected request for libcall!");
11173 case MVT::i8: LC = isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break;
11174 case MVT::i16: LC = isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
11175 case MVT::i32: LC = isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
11176 case MVT::i64: LC = isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
11179 SDValue InChain = DAG.getEntryNode();
11181 TargetLowering::ArgListTy Args;
11182 TargetLowering::ArgListEntry Entry;
11183 for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
11184 EVT ArgVT = Op->getOperand(i).getValueType();
11185 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
11186 Entry.Node = Op->getOperand(i);
11188 Entry.isSExt = isSigned;
11189 Entry.isZExt = !isSigned;
11190 Args.push_back(Entry);
11193 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
11194 getPointerTy(DAG.getDataLayout()));
11196 Type *RetTy = (Type*)StructType::get(Ty, Ty, nullptr);
11199 TargetLowering::CallLoweringInfo CLI(DAG);
11200 CLI.setDebugLoc(dl).setChain(InChain)
11201 .setCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args), 0)
11202 .setInRegister().setSExtResult(isSigned).setZExtResult(!isSigned);
11204 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
11205 return CallInfo.first;
11209 ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const {
11210 assert(Subtarget->isTargetWindows() && "unsupported target platform");
11214 SDValue Chain = Op.getOperand(0);
11215 SDValue Size = Op.getOperand(1);
11217 SDValue Words = DAG.getNode(ISD::SRL, DL, MVT::i32, Size,
11218 DAG.getConstant(2, DL, MVT::i32));
11221 Chain = DAG.getCopyToReg(Chain, DL, ARM::R4, Words, Flag);
11222 Flag = Chain.getValue(1);
11224 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
11225 Chain = DAG.getNode(ARMISD::WIN__CHKSTK, DL, NodeTys, Chain, Flag);
11227 SDValue NewSP = DAG.getCopyFromReg(Chain, DL, ARM::SP, MVT::i32);
11228 Chain = NewSP.getValue(1);
11230 SDValue Ops[2] = { NewSP, Chain };
11231 return DAG.getMergeValues(Ops, DL);
11234 SDValue ARMTargetLowering::LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const {
11235 assert(Op.getValueType() == MVT::f64 && Subtarget->isFPOnlySP() &&
11236 "Unexpected type for custom-lowering FP_EXTEND");
11239 LC = RTLIB::getFPEXT(Op.getOperand(0).getValueType(), Op.getValueType());
11241 SDValue SrcVal = Op.getOperand(0);
11242 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
11243 /*isSigned*/ false, SDLoc(Op)).first;
11246 SDValue ARMTargetLowering::LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const {
11247 assert(Op.getOperand(0).getValueType() == MVT::f64 &&
11248 Subtarget->isFPOnlySP() &&
11249 "Unexpected type for custom-lowering FP_ROUND");
11252 LC = RTLIB::getFPROUND(Op.getOperand(0).getValueType(), Op.getValueType());
11254 SDValue SrcVal = Op.getOperand(0);
11255 return makeLibCall(DAG, LC, Op.getValueType(), &SrcVal, 1,
11256 /*isSigned*/ false, SDLoc(Op)).first;
11260 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
11261 // The ARM target isn't yet aware of offsets.
11265 bool ARM::isBitFieldInvertedMask(unsigned v) {
11266 if (v == 0xffffffff)
11269 // there can be 1's on either or both "outsides", all the "inside"
11270 // bits must be 0's
11271 return isShiftedMask_32(~v);
11274 /// isFPImmLegal - Returns true if the target can instruction select the
11275 /// specified FP immediate natively. If false, the legalizer will
11276 /// materialize the FP immediate as a load from a constant pool.
11277 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
11278 if (!Subtarget->hasVFP3())
11280 if (VT == MVT::f32)
11281 return ARM_AM::getFP32Imm(Imm) != -1;
11282 if (VT == MVT::f64 && !Subtarget->isFPOnlySP())
11283 return ARM_AM::getFP64Imm(Imm) != -1;
11287 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
11288 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
11289 /// specified in the intrinsic calls.
11290 bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
11292 unsigned Intrinsic) const {
11293 switch (Intrinsic) {
11294 case Intrinsic::arm_neon_vld1:
11295 case Intrinsic::arm_neon_vld2:
11296 case Intrinsic::arm_neon_vld3:
11297 case Intrinsic::arm_neon_vld4:
11298 case Intrinsic::arm_neon_vld2lane:
11299 case Intrinsic::arm_neon_vld3lane:
11300 case Intrinsic::arm_neon_vld4lane: {
11301 Info.opc = ISD::INTRINSIC_W_CHAIN;
11302 // Conservatively set memVT to the entire set of vectors loaded.
11303 auto &DL = I.getCalledFunction()->getParent()->getDataLayout();
11304 uint64_t NumElts = DL.getTypeAllocSize(I.getType()) / 8;
11305 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
11306 Info.ptrVal = I.getArgOperand(0);
11308 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
11309 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
11310 Info.vol = false; // volatile loads with NEON intrinsics not supported
11311 Info.readMem = true;
11312 Info.writeMem = false;
11315 case Intrinsic::arm_neon_vst1:
11316 case Intrinsic::arm_neon_vst2:
11317 case Intrinsic::arm_neon_vst3:
11318 case Intrinsic::arm_neon_vst4:
11319 case Intrinsic::arm_neon_vst2lane:
11320 case Intrinsic::arm_neon_vst3lane:
11321 case Intrinsic::arm_neon_vst4lane: {
11322 Info.opc = ISD::INTRINSIC_VOID;
11323 // Conservatively set memVT to the entire set of vectors stored.
11324 auto &DL = I.getCalledFunction()->getParent()->getDataLayout();
11325 unsigned NumElts = 0;
11326 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
11327 Type *ArgTy = I.getArgOperand(ArgI)->getType();
11328 if (!ArgTy->isVectorTy())
11330 NumElts += DL.getTypeAllocSize(ArgTy) / 8;
11332 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
11333 Info.ptrVal = I.getArgOperand(0);
11335 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
11336 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
11337 Info.vol = false; // volatile stores with NEON intrinsics not supported
11338 Info.readMem = false;
11339 Info.writeMem = true;
11342 case Intrinsic::arm_ldaex:
11343 case Intrinsic::arm_ldrex: {
11344 auto &DL = I.getCalledFunction()->getParent()->getDataLayout();
11345 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
11346 Info.opc = ISD::INTRINSIC_W_CHAIN;
11347 Info.memVT = MVT::getVT(PtrTy->getElementType());
11348 Info.ptrVal = I.getArgOperand(0);
11350 Info.align = DL.getABITypeAlignment(PtrTy->getElementType());
11352 Info.readMem = true;
11353 Info.writeMem = false;
11356 case Intrinsic::arm_stlex:
11357 case Intrinsic::arm_strex: {
11358 auto &DL = I.getCalledFunction()->getParent()->getDataLayout();
11359 PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
11360 Info.opc = ISD::INTRINSIC_W_CHAIN;
11361 Info.memVT = MVT::getVT(PtrTy->getElementType());
11362 Info.ptrVal = I.getArgOperand(1);
11364 Info.align = DL.getABITypeAlignment(PtrTy->getElementType());
11366 Info.readMem = false;
11367 Info.writeMem = true;
11370 case Intrinsic::arm_stlexd:
11371 case Intrinsic::arm_strexd: {
11372 Info.opc = ISD::INTRINSIC_W_CHAIN;
11373 Info.memVT = MVT::i64;
11374 Info.ptrVal = I.getArgOperand(2);
11378 Info.readMem = false;
11379 Info.writeMem = true;
11382 case Intrinsic::arm_ldaexd:
11383 case Intrinsic::arm_ldrexd: {
11384 Info.opc = ISD::INTRINSIC_W_CHAIN;
11385 Info.memVT = MVT::i64;
11386 Info.ptrVal = I.getArgOperand(0);
11390 Info.readMem = true;
11391 Info.writeMem = false;
11401 /// \brief Returns true if it is beneficial to convert a load of a constant
11402 /// to just the constant itself.
11403 bool ARMTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
11405 assert(Ty->isIntegerTy());
11407 unsigned Bits = Ty->getPrimitiveSizeInBits();
11408 if (Bits == 0 || Bits > 32)
11413 bool ARMTargetLowering::hasLoadLinkedStoreConditional() const { return true; }
11415 Instruction* ARMTargetLowering::makeDMB(IRBuilder<> &Builder,
11416 ARM_MB::MemBOpt Domain) const {
11417 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
11419 // First, if the target has no DMB, see what fallback we can use.
11420 if (!Subtarget->hasDataBarrier()) {
11421 // Some ARMv6 cpus can support data barriers with an mcr instruction.
11422 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
11424 if (Subtarget->hasV6Ops() && !Subtarget->isThumb()) {
11425 Function *MCR = llvm::Intrinsic::getDeclaration(M, Intrinsic::arm_mcr);
11426 Value* args[6] = {Builder.getInt32(15), Builder.getInt32(0),
11427 Builder.getInt32(0), Builder.getInt32(7),
11428 Builder.getInt32(10), Builder.getInt32(5)};
11429 return Builder.CreateCall(MCR, args);
11431 // Instead of using barriers, atomic accesses on these subtargets use
11433 llvm_unreachable("makeDMB on a target so old that it has no barriers");
11436 Function *DMB = llvm::Intrinsic::getDeclaration(M, Intrinsic::arm_dmb);
11437 // Only a full system barrier exists in the M-class architectures.
11438 Domain = Subtarget->isMClass() ? ARM_MB::SY : Domain;
11439 Constant *CDomain = Builder.getInt32(Domain);
11440 return Builder.CreateCall(DMB, CDomain);
11444 // Based on http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
11445 Instruction* ARMTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
11446 AtomicOrdering Ord, bool IsStore,
11447 bool IsLoad) const {
11448 if (!getInsertFencesForAtomic())
11454 llvm_unreachable("Invalid fence: unordered/non-atomic");
11457 return nullptr; // Nothing to do
11458 case SequentiallyConsistent:
11460 return nullptr; // Nothing to do
11463 case AcquireRelease:
11464 if (Subtarget->isSwift())
11465 return makeDMB(Builder, ARM_MB::ISHST);
11466 // FIXME: add a comment with a link to documentation justifying this.
11468 return makeDMB(Builder, ARM_MB::ISH);
11470 llvm_unreachable("Unknown fence ordering in emitLeadingFence");
11473 Instruction* ARMTargetLowering::emitTrailingFence(IRBuilder<> &Builder,
11474 AtomicOrdering Ord, bool IsStore,
11475 bool IsLoad) const {
11476 if (!getInsertFencesForAtomic())
11482 llvm_unreachable("Invalid fence: unordered/not-atomic");
11485 return nullptr; // Nothing to do
11487 case AcquireRelease:
11488 case SequentiallyConsistent:
11489 return makeDMB(Builder, ARM_MB::ISH);
11491 llvm_unreachable("Unknown fence ordering in emitTrailingFence");
11494 // Loads and stores less than 64-bits are already atomic; ones above that
11495 // are doomed anyway, so defer to the default libcall and blame the OS when
11496 // things go wrong. Cortex M doesn't have ldrexd/strexd though, so don't emit
11497 // anything for those.
11498 bool ARMTargetLowering::shouldExpandAtomicStoreInIR(StoreInst *SI) const {
11499 unsigned Size = SI->getValueOperand()->getType()->getPrimitiveSizeInBits();
11500 return (Size == 64) && !Subtarget->isMClass();
11503 // Loads and stores less than 64-bits are already atomic; ones above that
11504 // are doomed anyway, so defer to the default libcall and blame the OS when
11505 // things go wrong. Cortex M doesn't have ldrexd/strexd though, so don't emit
11506 // anything for those.
11507 // FIXME: ldrd and strd are atomic if the CPU has LPAE (e.g. A15 has that
11508 // guarantee, see DDI0406C ARM architecture reference manual,
11509 // sections A8.8.72-74 LDRD)
11510 bool ARMTargetLowering::shouldExpandAtomicLoadInIR(LoadInst *LI) const {
11511 unsigned Size = LI->getType()->getPrimitiveSizeInBits();
11512 return (Size == 64) && !Subtarget->isMClass();
11515 // For the real atomic operations, we have ldrex/strex up to 32 bits,
11516 // and up to 64 bits on the non-M profiles
11517 TargetLoweringBase::AtomicRMWExpansionKind
11518 ARMTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
11519 unsigned Size = AI->getType()->getPrimitiveSizeInBits();
11520 return (Size <= (Subtarget->isMClass() ? 32U : 64U))
11521 ? AtomicRMWExpansionKind::LLSC
11522 : AtomicRMWExpansionKind::None;
11525 // This has so far only been implemented for MachO.
11526 bool ARMTargetLowering::useLoadStackGuardNode() const {
11527 return Subtarget->isTargetMachO();
11530 bool ARMTargetLowering::canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
11531 unsigned &Cost) const {
11532 // If we do not have NEON, vector types are not natively supported.
11533 if (!Subtarget->hasNEON())
11536 // Floating point values and vector values map to the same register file.
11537 // Therefore, althought we could do a store extract of a vector type, this is
11538 // better to leave at float as we have more freedom in the addressing mode for
11540 if (VectorTy->isFPOrFPVectorTy())
11543 // If the index is unknown at compile time, this is very expensive to lower
11544 // and it is not possible to combine the store with the extract.
11545 if (!isa<ConstantInt>(Idx))
11548 assert(VectorTy->isVectorTy() && "VectorTy is not a vector type");
11549 unsigned BitWidth = cast<VectorType>(VectorTy)->getBitWidth();
11550 // We can do a store + vector extract on any vector that fits perfectly in a D
11552 if (BitWidth == 64 || BitWidth == 128) {
11559 Value *ARMTargetLowering::emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
11560 AtomicOrdering Ord) const {
11561 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
11562 Type *ValTy = cast<PointerType>(Addr->getType())->getElementType();
11563 bool IsAcquire = isAtLeastAcquire(Ord);
11565 // Since i64 isn't legal and intrinsics don't get type-lowered, the ldrexd
11566 // intrinsic must return {i32, i32} and we have to recombine them into a
11567 // single i64 here.
11568 if (ValTy->getPrimitiveSizeInBits() == 64) {
11569 Intrinsic::ID Int =
11570 IsAcquire ? Intrinsic::arm_ldaexd : Intrinsic::arm_ldrexd;
11571 Function *Ldrex = llvm::Intrinsic::getDeclaration(M, Int);
11573 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
11574 Value *LoHi = Builder.CreateCall(Ldrex, Addr, "lohi");
11576 Value *Lo = Builder.CreateExtractValue(LoHi, 0, "lo");
11577 Value *Hi = Builder.CreateExtractValue(LoHi, 1, "hi");
11578 if (!Subtarget->isLittle())
11579 std::swap (Lo, Hi);
11580 Lo = Builder.CreateZExt(Lo, ValTy, "lo64");
11581 Hi = Builder.CreateZExt(Hi, ValTy, "hi64");
11582 return Builder.CreateOr(
11583 Lo, Builder.CreateShl(Hi, ConstantInt::get(ValTy, 32)), "val64");
11586 Type *Tys[] = { Addr->getType() };
11587 Intrinsic::ID Int = IsAcquire ? Intrinsic::arm_ldaex : Intrinsic::arm_ldrex;
11588 Function *Ldrex = llvm::Intrinsic::getDeclaration(M, Int, Tys);
11590 return Builder.CreateTruncOrBitCast(
11591 Builder.CreateCall(Ldrex, Addr),
11592 cast<PointerType>(Addr->getType())->getElementType());
11595 Value *ARMTargetLowering::emitStoreConditional(IRBuilder<> &Builder, Value *Val,
11597 AtomicOrdering Ord) const {
11598 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
11599 bool IsRelease = isAtLeastRelease(Ord);
11601 // Since the intrinsics must have legal type, the i64 intrinsics take two
11602 // parameters: "i32, i32". We must marshal Val into the appropriate form
11603 // before the call.
11604 if (Val->getType()->getPrimitiveSizeInBits() == 64) {
11605 Intrinsic::ID Int =
11606 IsRelease ? Intrinsic::arm_stlexd : Intrinsic::arm_strexd;
11607 Function *Strex = Intrinsic::getDeclaration(M, Int);
11608 Type *Int32Ty = Type::getInt32Ty(M->getContext());
11610 Value *Lo = Builder.CreateTrunc(Val, Int32Ty, "lo");
11611 Value *Hi = Builder.CreateTrunc(Builder.CreateLShr(Val, 32), Int32Ty, "hi");
11612 if (!Subtarget->isLittle())
11613 std::swap (Lo, Hi);
11614 Addr = Builder.CreateBitCast(Addr, Type::getInt8PtrTy(M->getContext()));
11615 return Builder.CreateCall(Strex, {Lo, Hi, Addr});
11618 Intrinsic::ID Int = IsRelease ? Intrinsic::arm_stlex : Intrinsic::arm_strex;
11619 Type *Tys[] = { Addr->getType() };
11620 Function *Strex = Intrinsic::getDeclaration(M, Int, Tys);
11622 return Builder.CreateCall(
11623 Strex, {Builder.CreateZExtOrBitCast(
11624 Val, Strex->getFunctionType()->getParamType(0)),
11628 /// \brief Lower an interleaved load into a vldN intrinsic.
11630 /// E.g. Lower an interleaved load (Factor = 2):
11631 /// %wide.vec = load <8 x i32>, <8 x i32>* %ptr, align 4
11632 /// %v0 = shuffle %wide.vec, undef, <0, 2, 4, 6> ; Extract even elements
11633 /// %v1 = shuffle %wide.vec, undef, <1, 3, 5, 7> ; Extract odd elements
11636 /// %vld2 = { <4 x i32>, <4 x i32> } call llvm.arm.neon.vld2(%ptr, 4)
11637 /// %vec0 = extractelement { <4 x i32>, <4 x i32> } %vld2, i32 0
11638 /// %vec1 = extractelement { <4 x i32>, <4 x i32> } %vld2, i32 1
11639 bool ARMTargetLowering::lowerInterleavedLoad(
11640 LoadInst *LI, ArrayRef<ShuffleVectorInst *> Shuffles,
11641 ArrayRef<unsigned> Indices, unsigned Factor) const {
11642 assert(Factor >= 2 && Factor <= getMaxSupportedInterleaveFactor() &&
11643 "Invalid interleave factor");
11644 assert(!Shuffles.empty() && "Empty shufflevector input");
11645 assert(Shuffles.size() == Indices.size() &&
11646 "Unmatched number of shufflevectors and indices");
11648 VectorType *VecTy = Shuffles[0]->getType();
11649 Type *EltTy = VecTy->getVectorElementType();
11651 const DataLayout &DL = LI->getModule()->getDataLayout();
11652 unsigned VecSize = DL.getTypeAllocSizeInBits(VecTy);
11653 bool EltIs64Bits = DL.getTypeAllocSizeInBits(EltTy) == 64;
11655 // Skip illegal vector types and vector types of i64/f64 element (vldN doesn't
11656 // support i64/f64 element).
11657 if ((VecSize != 64 && VecSize != 128) || EltIs64Bits)
11660 // A pointer vector can not be the return type of the ldN intrinsics. Need to
11661 // load integer vectors first and then convert to pointer vectors.
11662 if (EltTy->isPointerTy())
11664 VectorType::get(DL.getIntPtrType(EltTy), VecTy->getVectorNumElements());
11666 static const Intrinsic::ID LoadInts[3] = {Intrinsic::arm_neon_vld2,
11667 Intrinsic::arm_neon_vld3,
11668 Intrinsic::arm_neon_vld4};
11670 Function *VldnFunc =
11671 Intrinsic::getDeclaration(LI->getModule(), LoadInts[Factor - 2], VecTy);
11673 IRBuilder<> Builder(LI);
11674 SmallVector<Value *, 2> Ops;
11676 Type *Int8Ptr = Builder.getInt8PtrTy(LI->getPointerAddressSpace());
11677 Ops.push_back(Builder.CreateBitCast(LI->getPointerOperand(), Int8Ptr));
11678 Ops.push_back(Builder.getInt32(LI->getAlignment()));
11680 CallInst *VldN = Builder.CreateCall(VldnFunc, Ops, "vldN");
11682 // Replace uses of each shufflevector with the corresponding vector loaded
11684 for (unsigned i = 0; i < Shuffles.size(); i++) {
11685 ShuffleVectorInst *SV = Shuffles[i];
11686 unsigned Index = Indices[i];
11688 Value *SubVec = Builder.CreateExtractValue(VldN, Index);
11690 // Convert the integer vector to pointer vector if the element is pointer.
11691 if (EltTy->isPointerTy())
11692 SubVec = Builder.CreateIntToPtr(SubVec, SV->getType());
11694 SV->replaceAllUsesWith(SubVec);
11700 /// \brief Get a mask consisting of sequential integers starting from \p Start.
11702 /// I.e. <Start, Start + 1, ..., Start + NumElts - 1>
11703 static Constant *getSequentialMask(IRBuilder<> &Builder, unsigned Start,
11704 unsigned NumElts) {
11705 SmallVector<Constant *, 16> Mask;
11706 for (unsigned i = 0; i < NumElts; i++)
11707 Mask.push_back(Builder.getInt32(Start + i));
11709 return ConstantVector::get(Mask);
11712 /// \brief Lower an interleaved store into a vstN intrinsic.
11714 /// E.g. Lower an interleaved store (Factor = 3):
11715 /// %i.vec = shuffle <8 x i32> %v0, <8 x i32> %v1,
11716 /// <0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11>
11717 /// store <12 x i32> %i.vec, <12 x i32>* %ptr, align 4
11720 /// %sub.v0 = shuffle <8 x i32> %v0, <8 x i32> v1, <0, 1, 2, 3>
11721 /// %sub.v1 = shuffle <8 x i32> %v0, <8 x i32> v1, <4, 5, 6, 7>
11722 /// %sub.v2 = shuffle <8 x i32> %v0, <8 x i32> v1, <8, 9, 10, 11>
11723 /// call void llvm.arm.neon.vst3(%ptr, %sub.v0, %sub.v1, %sub.v2, 4)
11725 /// Note that the new shufflevectors will be removed and we'll only generate one
11726 /// vst3 instruction in CodeGen.
11727 bool ARMTargetLowering::lowerInterleavedStore(StoreInst *SI,
11728 ShuffleVectorInst *SVI,
11729 unsigned Factor) const {
11730 assert(Factor >= 2 && Factor <= getMaxSupportedInterleaveFactor() &&
11731 "Invalid interleave factor");
11733 VectorType *VecTy = SVI->getType();
11734 assert(VecTy->getVectorNumElements() % Factor == 0 &&
11735 "Invalid interleaved store");
11737 unsigned NumSubElts = VecTy->getVectorNumElements() / Factor;
11738 Type *EltTy = VecTy->getVectorElementType();
11739 VectorType *SubVecTy = VectorType::get(EltTy, NumSubElts);
11741 const DataLayout &DL = SI->getModule()->getDataLayout();
11742 unsigned SubVecSize = DL.getTypeAllocSizeInBits(SubVecTy);
11743 bool EltIs64Bits = DL.getTypeAllocSizeInBits(EltTy) == 64;
11745 // Skip illegal sub vector types and vector types of i64/f64 element (vstN
11746 // doesn't support i64/f64 element).
11747 if ((SubVecSize != 64 && SubVecSize != 128) || EltIs64Bits)
11750 Value *Op0 = SVI->getOperand(0);
11751 Value *Op1 = SVI->getOperand(1);
11752 IRBuilder<> Builder(SI);
11754 // StN intrinsics don't support pointer vectors as arguments. Convert pointer
11755 // vectors to integer vectors.
11756 if (EltTy->isPointerTy()) {
11757 Type *IntTy = DL.getIntPtrType(EltTy);
11759 // Convert to the corresponding integer vector.
11761 VectorType::get(IntTy, Op0->getType()->getVectorNumElements());
11762 Op0 = Builder.CreatePtrToInt(Op0, IntVecTy);
11763 Op1 = Builder.CreatePtrToInt(Op1, IntVecTy);
11765 SubVecTy = VectorType::get(IntTy, NumSubElts);
11768 static Intrinsic::ID StoreInts[3] = {Intrinsic::arm_neon_vst2,
11769 Intrinsic::arm_neon_vst3,
11770 Intrinsic::arm_neon_vst4};
11771 Function *VstNFunc = Intrinsic::getDeclaration(
11772 SI->getModule(), StoreInts[Factor - 2], SubVecTy);
11774 SmallVector<Value *, 6> Ops;
11776 Type *Int8Ptr = Builder.getInt8PtrTy(SI->getPointerAddressSpace());
11777 Ops.push_back(Builder.CreateBitCast(SI->getPointerOperand(), Int8Ptr));
11779 // Split the shufflevector operands into sub vectors for the new vstN call.
11780 for (unsigned i = 0; i < Factor; i++)
11781 Ops.push_back(Builder.CreateShuffleVector(
11782 Op0, Op1, getSequentialMask(Builder, NumSubElts * i, NumSubElts)));
11784 Ops.push_back(Builder.getInt32(SI->getAlignment()));
11785 Builder.CreateCall(VstNFunc, Ops);
11797 static bool isHomogeneousAggregate(Type *Ty, HABaseType &Base,
11798 uint64_t &Members) {
11799 if (const StructType *ST = dyn_cast<StructType>(Ty)) {
11800 for (unsigned i = 0; i < ST->getNumElements(); ++i) {
11801 uint64_t SubMembers = 0;
11802 if (!isHomogeneousAggregate(ST->getElementType(i), Base, SubMembers))
11804 Members += SubMembers;
11806 } else if (const ArrayType *AT = dyn_cast<ArrayType>(Ty)) {
11807 uint64_t SubMembers = 0;
11808 if (!isHomogeneousAggregate(AT->getElementType(), Base, SubMembers))
11810 Members += SubMembers * AT->getNumElements();
11811 } else if (Ty->isFloatTy()) {
11812 if (Base != HA_UNKNOWN && Base != HA_FLOAT)
11816 } else if (Ty->isDoubleTy()) {
11817 if (Base != HA_UNKNOWN && Base != HA_DOUBLE)
11821 } else if (const VectorType *VT = dyn_cast<VectorType>(Ty)) {
11828 return VT->getBitWidth() == 64;
11830 return VT->getBitWidth() == 128;
11832 switch (VT->getBitWidth()) {
11845 return (Members > 0 && Members <= 4);
11848 /// \brief Return true if a type is an AAPCS-VFP homogeneous aggregate or one of
11849 /// [N x i32] or [N x i64]. This allows front-ends to skip emitting padding when
11850 /// passing according to AAPCS rules.
11851 bool ARMTargetLowering::functionArgumentNeedsConsecutiveRegisters(
11852 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const {
11853 if (getEffectiveCallingConv(CallConv, isVarArg) !=
11854 CallingConv::ARM_AAPCS_VFP)
11857 HABaseType Base = HA_UNKNOWN;
11858 uint64_t Members = 0;
11859 bool IsHA = isHomogeneousAggregate(Ty, Base, Members);
11860 DEBUG(dbgs() << "isHA: " << IsHA << " "; Ty->dump());
11862 bool IsIntArray = Ty->isArrayTy() && Ty->getArrayElementType()->isIntegerTy();
11863 return IsHA || IsIntArray;