1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "ARMAddressingModes.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMISelLowering.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMRegisterInfo.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "ARMTargetObjectFile.h"
24 #include "llvm/CallingConv.h"
25 #include "llvm/Constants.h"
26 #include "llvm/Function.h"
27 #include "llvm/Instruction.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/GlobalValue.h"
30 #include "llvm/CodeGen/CallingConvLower.h"
31 #include "llvm/CodeGen/MachineBasicBlock.h"
32 #include "llvm/CodeGen/MachineFrameInfo.h"
33 #include "llvm/CodeGen/MachineFunction.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineRegisterInfo.h"
36 #include "llvm/CodeGen/PseudoSourceValue.h"
37 #include "llvm/CodeGen/SelectionDAG.h"
38 #include "llvm/Target/TargetOptions.h"
39 #include "llvm/ADT/VectorExtras.h"
40 #include "llvm/Support/ErrorHandling.h"
41 #include "llvm/Support/MathExtras.h"
44 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
45 CCValAssign::LocInfo &LocInfo,
46 ISD::ArgFlagsTy &ArgFlags,
48 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
49 CCValAssign::LocInfo &LocInfo,
50 ISD::ArgFlagsTy &ArgFlags,
52 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
53 CCValAssign::LocInfo &LocInfo,
54 ISD::ArgFlagsTy &ArgFlags,
56 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
57 CCValAssign::LocInfo &LocInfo,
58 ISD::ArgFlagsTy &ArgFlags,
61 void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
62 EVT PromotedBitwiseVT) {
63 if (VT != PromotedLdStVT) {
64 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
65 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
66 PromotedLdStVT.getSimpleVT());
68 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
69 AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
70 PromotedLdStVT.getSimpleVT());
73 EVT ElemTy = VT.getVectorElementType();
74 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
75 setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
76 if (ElemTy == MVT::i8 || ElemTy == MVT::i16)
77 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
78 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
79 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
80 setOperationAction(ISD::SCALAR_TO_VECTOR, VT.getSimpleVT(), Custom);
81 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Custom);
83 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
84 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
85 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
88 // Promote all bit-wise operations.
89 if (VT.isInteger() && VT != PromotedBitwiseVT) {
90 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
91 AddPromotedToType (ISD::AND, VT.getSimpleVT(),
92 PromotedBitwiseVT.getSimpleVT());
93 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
94 AddPromotedToType (ISD::OR, VT.getSimpleVT(),
95 PromotedBitwiseVT.getSimpleVT());
96 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
97 AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
98 PromotedBitwiseVT.getSimpleVT());
102 void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
103 addRegisterClass(VT, ARM::DPRRegisterClass);
104 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
107 void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
108 addRegisterClass(VT, ARM::QPRRegisterClass);
109 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
112 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
113 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
114 return new TargetLoweringObjectFileMachO();
115 return new ARMElfTargetObjectFile();
118 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
119 : TargetLowering(TM, createTLOF(TM)), ARMPCLabelIndex(0) {
120 Subtarget = &TM.getSubtarget<ARMSubtarget>();
122 if (Subtarget->isTargetDarwin()) {
123 // Uses VFP for Thumb libfuncs if available.
124 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
125 // Single-precision floating-point arithmetic.
126 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
127 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
128 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
129 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
131 // Double-precision floating-point arithmetic.
132 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
133 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
134 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
135 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
137 // Single-precision comparisons.
138 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
139 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
140 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
141 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
142 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
143 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
144 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
145 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
147 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
148 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
149 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
150 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
151 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
152 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
153 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
154 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
156 // Double-precision comparisons.
157 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
158 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
159 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
160 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
161 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
162 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
163 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
164 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
166 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
167 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
168 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
169 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
170 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
171 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
172 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
173 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
175 // Floating-point to integer conversions.
176 // i64 conversions are done via library routines even when generating VFP
177 // instructions, so use the same ones.
178 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
179 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
180 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
181 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
183 // Conversions between floating types.
184 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
185 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
187 // Integer to floating-point conversions.
188 // i64 conversions are done via library routines even when generating VFP
189 // instructions, so use the same ones.
190 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
191 // e.g., __floatunsidf vs. __floatunssidfvfp.
192 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
193 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
194 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
195 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
199 // These libcalls are not available in 32-bit.
200 setLibcallName(RTLIB::SHL_I128, 0);
201 setLibcallName(RTLIB::SRL_I128, 0);
202 setLibcallName(RTLIB::SRA_I128, 0);
204 if (Subtarget->isThumb1Only())
205 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
207 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
208 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
209 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
210 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
212 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
215 if (Subtarget->hasNEON()) {
216 addDRTypeForNEON(MVT::v2f32);
217 addDRTypeForNEON(MVT::v8i8);
218 addDRTypeForNEON(MVT::v4i16);
219 addDRTypeForNEON(MVT::v2i32);
220 addDRTypeForNEON(MVT::v1i64);
222 addQRTypeForNEON(MVT::v4f32);
223 addQRTypeForNEON(MVT::v2f64);
224 addQRTypeForNEON(MVT::v16i8);
225 addQRTypeForNEON(MVT::v8i16);
226 addQRTypeForNEON(MVT::v4i32);
227 addQRTypeForNEON(MVT::v2i64);
229 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
230 setTargetDAGCombine(ISD::SHL);
231 setTargetDAGCombine(ISD::SRL);
232 setTargetDAGCombine(ISD::SRA);
233 setTargetDAGCombine(ISD::SIGN_EXTEND);
234 setTargetDAGCombine(ISD::ZERO_EXTEND);
235 setTargetDAGCombine(ISD::ANY_EXTEND);
238 computeRegisterProperties();
240 // ARM does not have f32 extending load.
241 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
243 // ARM does not have i1 sign extending load.
244 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
246 // ARM supports all 4 flavors of integer indexed load / store.
247 if (!Subtarget->isThumb1Only()) {
248 for (unsigned im = (unsigned)ISD::PRE_INC;
249 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
250 setIndexedLoadAction(im, MVT::i1, Legal);
251 setIndexedLoadAction(im, MVT::i8, Legal);
252 setIndexedLoadAction(im, MVT::i16, Legal);
253 setIndexedLoadAction(im, MVT::i32, Legal);
254 setIndexedStoreAction(im, MVT::i1, Legal);
255 setIndexedStoreAction(im, MVT::i8, Legal);
256 setIndexedStoreAction(im, MVT::i16, Legal);
257 setIndexedStoreAction(im, MVT::i32, Legal);
261 // i64 operation support.
262 if (Subtarget->isThumb1Only()) {
263 setOperationAction(ISD::MUL, MVT::i64, Expand);
264 setOperationAction(ISD::MULHU, MVT::i32, Expand);
265 setOperationAction(ISD::MULHS, MVT::i32, Expand);
266 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
267 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
269 setOperationAction(ISD::MUL, MVT::i64, Expand);
270 setOperationAction(ISD::MULHU, MVT::i32, Expand);
271 if (!Subtarget->hasV6Ops())
272 setOperationAction(ISD::MULHS, MVT::i32, Expand);
274 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
275 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
276 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
277 setOperationAction(ISD::SRL, MVT::i64, Custom);
278 setOperationAction(ISD::SRA, MVT::i64, Custom);
280 // ARM does not have ROTL.
281 setOperationAction(ISD::ROTL, MVT::i32, Expand);
282 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
283 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
284 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
285 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
287 // Only ARMv6 has BSWAP.
288 if (!Subtarget->hasV6Ops())
289 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
291 // These are expanded into libcalls.
292 setOperationAction(ISD::SDIV, MVT::i32, Expand);
293 setOperationAction(ISD::UDIV, MVT::i32, Expand);
294 setOperationAction(ISD::SREM, MVT::i32, Expand);
295 setOperationAction(ISD::UREM, MVT::i32, Expand);
296 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
297 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
299 // Support label based line numbers.
300 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
301 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
303 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
304 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
305 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
306 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
308 // Use the default implementation.
309 setOperationAction(ISD::VASTART, MVT::Other, Custom);
310 setOperationAction(ISD::VAARG, MVT::Other, Expand);
311 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
312 setOperationAction(ISD::VAEND, MVT::Other, Expand);
313 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
314 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
315 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
316 // FIXME: Shouldn't need this, since no register is used, but the legalizer
317 // doesn't yet know how to not do that for SjLj.
318 setExceptionSelectorRegister(ARM::R0);
319 if (Subtarget->isThumb())
320 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
322 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
323 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
325 if (!Subtarget->hasV6Ops() && !Subtarget->isThumb2()) {
326 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
327 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
329 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
331 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only())
332 // Turn f64->i64 into FMRRD, i64 -> f64 to FMDRR iff target supports vfp2.
333 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
335 // We want to custom lower some of our intrinsics.
336 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
337 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
338 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
340 setOperationAction(ISD::SETCC, MVT::i32, Expand);
341 setOperationAction(ISD::SETCC, MVT::f32, Expand);
342 setOperationAction(ISD::SETCC, MVT::f64, Expand);
343 setOperationAction(ISD::SELECT, MVT::i32, Expand);
344 setOperationAction(ISD::SELECT, MVT::f32, Expand);
345 setOperationAction(ISD::SELECT, MVT::f64, Expand);
346 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
347 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
348 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
350 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
351 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
352 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
353 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
354 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
356 // We don't support sin/cos/fmod/copysign/pow
357 setOperationAction(ISD::FSIN, MVT::f64, Expand);
358 setOperationAction(ISD::FSIN, MVT::f32, Expand);
359 setOperationAction(ISD::FCOS, MVT::f32, Expand);
360 setOperationAction(ISD::FCOS, MVT::f64, Expand);
361 setOperationAction(ISD::FREM, MVT::f64, Expand);
362 setOperationAction(ISD::FREM, MVT::f32, Expand);
363 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
364 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
365 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
367 setOperationAction(ISD::FPOW, MVT::f64, Expand);
368 setOperationAction(ISD::FPOW, MVT::f32, Expand);
370 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
371 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
372 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
373 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
374 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
375 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
378 // We have target-specific dag combine patterns for the following nodes:
379 // ARMISD::FMRRD - No need to call setTargetDAGCombine
380 setTargetDAGCombine(ISD::ADD);
381 setTargetDAGCombine(ISD::SUB);
383 setStackPointerRegisterToSaveRestore(ARM::SP);
384 setSchedulingPreference(SchedulingForRegPressure);
385 setIfCvtBlockSizeLimit(Subtarget->isThumb() ? 0 : 10);
386 setIfCvtDupBlockSizeLimit(Subtarget->isThumb() ? 0 : 2);
388 if (!Subtarget->isThumb()) {
389 // Use branch latency information to determine if-conversion limits.
390 // FIXME: If-converter should use instruction latency of the branch being
391 // eliminated to compute the threshold. For ARMv6, the branch "latency"
392 // varies depending on whether it's dynamically or statically predicted
393 // and on whether the destination is in the prefetch buffer.
394 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
395 const InstrItineraryData &InstrItins = Subtarget->getInstrItineraryData();
396 unsigned Latency= InstrItins.getLatency(TII->get(ARM::Bcc).getSchedClass());
398 setIfCvtBlockSizeLimit(Latency-1);
400 setIfCvtDupBlockSizeLimit(Latency-2);
402 setIfCvtBlockSizeLimit(10);
403 setIfCvtDupBlockSizeLimit(2);
407 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
408 // Do not enable CodePlacementOpt for now: it currently runs after the
409 // ARMConstantIslandPass and messes up branch relaxation and placement
410 // of constant islands.
411 // benefitFromCodePlacementOpt = true;
414 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
417 case ARMISD::Wrapper: return "ARMISD::Wrapper";
418 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
419 case ARMISD::CALL: return "ARMISD::CALL";
420 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
421 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
422 case ARMISD::tCALL: return "ARMISD::tCALL";
423 case ARMISD::BRCOND: return "ARMISD::BRCOND";
424 case ARMISD::BR_JT: return "ARMISD::BR_JT";
425 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
426 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
427 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
428 case ARMISD::CMP: return "ARMISD::CMP";
429 case ARMISD::CMPZ: return "ARMISD::CMPZ";
430 case ARMISD::CMPFP: return "ARMISD::CMPFP";
431 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
432 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
433 case ARMISD::CMOV: return "ARMISD::CMOV";
434 case ARMISD::CNEG: return "ARMISD::CNEG";
436 case ARMISD::FTOSI: return "ARMISD::FTOSI";
437 case ARMISD::FTOUI: return "ARMISD::FTOUI";
438 case ARMISD::SITOF: return "ARMISD::SITOF";
439 case ARMISD::UITOF: return "ARMISD::UITOF";
441 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
442 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
443 case ARMISD::RRX: return "ARMISD::RRX";
445 case ARMISD::FMRRD: return "ARMISD::FMRRD";
446 case ARMISD::FMDRR: return "ARMISD::FMDRR";
448 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
450 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
452 case ARMISD::VCEQ: return "ARMISD::VCEQ";
453 case ARMISD::VCGE: return "ARMISD::VCGE";
454 case ARMISD::VCGEU: return "ARMISD::VCGEU";
455 case ARMISD::VCGT: return "ARMISD::VCGT";
456 case ARMISD::VCGTU: return "ARMISD::VCGTU";
457 case ARMISD::VTST: return "ARMISD::VTST";
459 case ARMISD::VSHL: return "ARMISD::VSHL";
460 case ARMISD::VSHRs: return "ARMISD::VSHRs";
461 case ARMISD::VSHRu: return "ARMISD::VSHRu";
462 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
463 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
464 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
465 case ARMISD::VSHRN: return "ARMISD::VSHRN";
466 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
467 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
468 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
469 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
470 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
471 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
472 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
473 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
474 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
475 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
476 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
477 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
478 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
479 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
480 case ARMISD::VDUPLANEQ: return "ARMISD::VDUPLANEQ";
481 case ARMISD::VLD2D: return "ARMISD::VLD2D";
482 case ARMISD::VLD3D: return "ARMISD::VLD3D";
483 case ARMISD::VLD4D: return "ARMISD::VLD4D";
484 case ARMISD::VST2D: return "ARMISD::VST2D";
485 case ARMISD::VST3D: return "ARMISD::VST3D";
486 case ARMISD::VST4D: return "ARMISD::VST4D";
487 case ARMISD::VREV64: return "ARMISD::VREV64";
488 case ARMISD::VREV32: return "ARMISD::VREV32";
489 case ARMISD::VREV16: return "ARMISD::VREV16";
490 case ARMISD::VSPLAT0: return "ARMISD::VSPLAT0";
494 /// getFunctionAlignment - Return the Log2 alignment of this function.
495 unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
496 return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 1 : 2;
499 //===----------------------------------------------------------------------===//
501 //===----------------------------------------------------------------------===//
503 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
504 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
506 default: llvm_unreachable("Unknown condition code!");
507 case ISD::SETNE: return ARMCC::NE;
508 case ISD::SETEQ: return ARMCC::EQ;
509 case ISD::SETGT: return ARMCC::GT;
510 case ISD::SETGE: return ARMCC::GE;
511 case ISD::SETLT: return ARMCC::LT;
512 case ISD::SETLE: return ARMCC::LE;
513 case ISD::SETUGT: return ARMCC::HI;
514 case ISD::SETUGE: return ARMCC::HS;
515 case ISD::SETULT: return ARMCC::LO;
516 case ISD::SETULE: return ARMCC::LS;
520 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. It
521 /// returns true if the operands should be inverted to form the proper
523 static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
524 ARMCC::CondCodes &CondCode2) {
526 CondCode2 = ARMCC::AL;
528 default: llvm_unreachable("Unknown FP condition!");
530 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
532 case ISD::SETOGT: CondCode = ARMCC::GT; break;
534 case ISD::SETOGE: CondCode = ARMCC::GE; break;
535 case ISD::SETOLT: CondCode = ARMCC::MI; break;
536 case ISD::SETOLE: CondCode = ARMCC::GT; Invert = true; break;
537 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
538 case ISD::SETO: CondCode = ARMCC::VC; break;
539 case ISD::SETUO: CondCode = ARMCC::VS; break;
540 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
541 case ISD::SETUGT: CondCode = ARMCC::HI; break;
542 case ISD::SETUGE: CondCode = ARMCC::PL; break;
544 case ISD::SETULT: CondCode = ARMCC::LT; break;
546 case ISD::SETULE: CondCode = ARMCC::LE; break;
548 case ISD::SETUNE: CondCode = ARMCC::NE; break;
553 //===----------------------------------------------------------------------===//
554 // Calling Convention Implementation
555 //===----------------------------------------------------------------------===//
557 #include "ARMGenCallingConv.inc"
559 // APCS f64 is in register pairs, possibly split to stack
560 static bool f64AssignAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
561 CCValAssign::LocInfo &LocInfo,
562 CCState &State, bool CanFail) {
563 static const unsigned RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
565 // Try to get the first register.
566 if (unsigned Reg = State.AllocateReg(RegList, 4))
567 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
569 // For the 2nd half of a v2f64, do not fail.
573 // Put the whole thing on the stack.
574 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
575 State.AllocateStack(8, 4),
580 // Try to get the second register.
581 if (unsigned Reg = State.AllocateReg(RegList, 4))
582 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
584 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
585 State.AllocateStack(4, 4),
590 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
591 CCValAssign::LocInfo &LocInfo,
592 ISD::ArgFlagsTy &ArgFlags,
594 if (!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
596 if (LocVT == MVT::v2f64 &&
597 !f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
599 return true; // we handled it
602 // AAPCS f64 is in aligned register pairs
603 static bool f64AssignAAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
604 CCValAssign::LocInfo &LocInfo,
605 CCState &State, bool CanFail) {
606 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
607 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
609 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
611 // For the 2nd half of a v2f64, do not just fail.
615 // Put the whole thing on the stack.
616 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
617 State.AllocateStack(8, 8),
623 for (i = 0; i < 2; ++i)
624 if (HiRegList[i] == Reg)
627 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
628 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
633 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
634 CCValAssign::LocInfo &LocInfo,
635 ISD::ArgFlagsTy &ArgFlags,
637 if (!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
639 if (LocVT == MVT::v2f64 &&
640 !f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
642 return true; // we handled it
645 static bool f64RetAssign(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
646 CCValAssign::LocInfo &LocInfo, CCState &State) {
647 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
648 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
650 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
652 return false; // we didn't handle it
655 for (i = 0; i < 2; ++i)
656 if (HiRegList[i] == Reg)
659 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
660 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
665 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
666 CCValAssign::LocInfo &LocInfo,
667 ISD::ArgFlagsTy &ArgFlags,
669 if (!f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
671 if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
673 return true; // we handled it
676 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
677 CCValAssign::LocInfo &LocInfo,
678 ISD::ArgFlagsTy &ArgFlags,
680 return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags,
684 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
685 /// given CallingConvention value.
686 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(unsigned CC,
688 bool isVarArg) const {
691 llvm_unreachable("Unsupported calling convention");
693 case CallingConv::Fast:
694 // Use target triple & subtarget features to do actual dispatch.
695 if (Subtarget->isAAPCS_ABI()) {
696 if (Subtarget->hasVFP2() &&
697 FloatABIType == FloatABI::Hard && !isVarArg)
698 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
700 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
702 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
703 case CallingConv::ARM_AAPCS_VFP:
704 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
705 case CallingConv::ARM_AAPCS:
706 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
707 case CallingConv::ARM_APCS:
708 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
712 /// LowerCallResult - Lower the result values of a call into the
713 /// appropriate copies out of appropriate physical registers.
715 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
716 unsigned CallConv, bool isVarArg,
717 const SmallVectorImpl<ISD::InputArg> &Ins,
718 DebugLoc dl, SelectionDAG &DAG,
719 SmallVectorImpl<SDValue> &InVals) {
721 // Assign locations to each value returned by this call.
722 SmallVector<CCValAssign, 16> RVLocs;
723 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
724 RVLocs, *DAG.getContext());
725 CCInfo.AnalyzeCallResult(Ins,
726 CCAssignFnForNode(CallConv, /* Return*/ true,
729 // Copy all of the result registers out of their specified physreg.
730 for (unsigned i = 0; i != RVLocs.size(); ++i) {
731 CCValAssign VA = RVLocs[i];
734 if (VA.needsCustom()) {
735 // Handle f64 or half of a v2f64.
736 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
738 Chain = Lo.getValue(1);
739 InFlag = Lo.getValue(2);
740 VA = RVLocs[++i]; // skip ahead to next loc
741 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
743 Chain = Hi.getValue(1);
744 InFlag = Hi.getValue(2);
745 Val = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
747 if (VA.getLocVT() == MVT::v2f64) {
748 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
749 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
750 DAG.getConstant(0, MVT::i32));
752 VA = RVLocs[++i]; // skip ahead to next loc
753 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
754 Chain = Lo.getValue(1);
755 InFlag = Lo.getValue(2);
756 VA = RVLocs[++i]; // skip ahead to next loc
757 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
758 Chain = Hi.getValue(1);
759 InFlag = Hi.getValue(2);
760 Val = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
761 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
762 DAG.getConstant(1, MVT::i32));
765 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
767 Chain = Val.getValue(1);
768 InFlag = Val.getValue(2);
771 switch (VA.getLocInfo()) {
772 default: llvm_unreachable("Unknown loc info!");
773 case CCValAssign::Full: break;
774 case CCValAssign::BCvt:
775 Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val);
779 InVals.push_back(Val);
785 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
786 /// by "Src" to address "Dst" of size "Size". Alignment information is
787 /// specified by the specific parameter attribute. The copy will be passed as
788 /// a byval function parameter.
789 /// Sometimes what we are copying is the end of a larger object, the part that
790 /// does not fit in registers.
792 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
793 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
795 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
796 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
797 /*AlwaysInline=*/false, NULL, 0, NULL, 0);
800 /// LowerMemOpCallTo - Store the argument to the stack.
802 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
803 SDValue StackPtr, SDValue Arg,
804 DebugLoc dl, SelectionDAG &DAG,
805 const CCValAssign &VA,
806 ISD::ArgFlagsTy Flags) {
807 unsigned LocMemOffset = VA.getLocMemOffset();
808 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
809 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
810 if (Flags.isByVal()) {
811 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
813 return DAG.getStore(Chain, dl, Arg, PtrOff,
814 PseudoSourceValue::getStack(), LocMemOffset);
817 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
818 SDValue Chain, SDValue &Arg,
819 RegsToPassVector &RegsToPass,
820 CCValAssign &VA, CCValAssign &NextVA,
822 SmallVector<SDValue, 8> &MemOpChains,
823 ISD::ArgFlagsTy Flags) {
825 SDValue fmrrd = DAG.getNode(ARMISD::FMRRD, dl,
826 DAG.getVTList(MVT::i32, MVT::i32), Arg);
827 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
829 if (NextVA.isRegLoc())
830 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
832 assert(NextVA.isMemLoc());
833 if (StackPtr.getNode() == 0)
834 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
836 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
842 /// LowerCall - Lowering a call into a callseq_start <-
843 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
846 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
847 unsigned CallConv, bool isVarArg,
849 const SmallVectorImpl<ISD::OutputArg> &Outs,
850 const SmallVectorImpl<ISD::InputArg> &Ins,
851 DebugLoc dl, SelectionDAG &DAG,
852 SmallVectorImpl<SDValue> &InVals) {
854 // Analyze operands of the call, assigning locations to each operand.
855 SmallVector<CCValAssign, 16> ArgLocs;
856 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
858 CCInfo.AnalyzeCallOperands(Outs,
859 CCAssignFnForNode(CallConv, /* Return*/ false,
862 // Get a count of how many bytes are to be pushed on the stack.
863 unsigned NumBytes = CCInfo.getNextStackOffset();
865 // Adjust the stack pointer for the new arguments...
866 // These operations are automatically eliminated by the prolog/epilog pass
867 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
869 SDValue StackPtr = DAG.getRegister(ARM::SP, MVT::i32);
871 RegsToPassVector RegsToPass;
872 SmallVector<SDValue, 8> MemOpChains;
874 // Walk the register/memloc assignments, inserting copies/loads. In the case
875 // of tail call optimization, arguments are handled later.
876 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
879 CCValAssign &VA = ArgLocs[i];
880 SDValue Arg = Outs[realArgIdx].Val;
881 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
883 // Promote the value if needed.
884 switch (VA.getLocInfo()) {
885 default: llvm_unreachable("Unknown loc info!");
886 case CCValAssign::Full: break;
887 case CCValAssign::SExt:
888 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
890 case CCValAssign::ZExt:
891 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
893 case CCValAssign::AExt:
894 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
896 case CCValAssign::BCvt:
897 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
901 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
902 if (VA.needsCustom()) {
903 if (VA.getLocVT() == MVT::v2f64) {
904 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
905 DAG.getConstant(0, MVT::i32));
906 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
907 DAG.getConstant(1, MVT::i32));
909 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
910 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
912 VA = ArgLocs[++i]; // skip ahead to next loc
914 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
915 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
917 assert(VA.isMemLoc());
918 if (StackPtr.getNode() == 0)
919 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
921 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
922 dl, DAG, VA, Flags));
925 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
926 StackPtr, MemOpChains, Flags);
928 } else if (VA.isRegLoc()) {
929 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
931 assert(VA.isMemLoc());
932 if (StackPtr.getNode() == 0)
933 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
935 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
936 dl, DAG, VA, Flags));
940 if (!MemOpChains.empty())
941 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
942 &MemOpChains[0], MemOpChains.size());
944 // Build a sequence of copy-to-reg nodes chained together with token chain
945 // and flag operands which copy the outgoing args into the appropriate regs.
947 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
948 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
949 RegsToPass[i].second, InFlag);
950 InFlag = Chain.getValue(1);
953 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
954 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
955 // node so that legalize doesn't hack it.
956 bool isDirect = false;
957 bool isARMFunc = false;
958 bool isLocalARMFunc = false;
959 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
960 GlobalValue *GV = G->getGlobal();
962 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
963 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
964 getTargetMachine().getRelocationModel() != Reloc::Static;
965 isARMFunc = !Subtarget->isThumb() || isStub;
966 // ARM call to a local ARM function is predicable.
967 isLocalARMFunc = !Subtarget->isThumb() && !isExt;
968 // tBX takes a register source operand.
969 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
970 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
972 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
973 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
974 Callee = DAG.getLoad(getPointerTy(), dl,
975 DAG.getEntryNode(), CPAddr, NULL, 0);
976 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
977 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
978 getPointerTy(), Callee, PICLabel);
980 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy());
981 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
983 bool isStub = Subtarget->isTargetDarwin() &&
984 getTargetMachine().getRelocationModel() != Reloc::Static;
985 isARMFunc = !Subtarget->isThumb() || isStub;
986 // tBX takes a register source operand.
987 const char *Sym = S->getSymbol();
988 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
989 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(Sym, ARMPCLabelIndex,
991 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
992 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
993 Callee = DAG.getLoad(getPointerTy(), dl,
994 DAG.getEntryNode(), CPAddr, NULL, 0);
995 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
996 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
997 getPointerTy(), Callee, PICLabel);
999 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
1002 // FIXME: handle tail calls differently.
1004 if (Subtarget->isThumb()) {
1005 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1006 CallOpc = ARMISD::CALL_NOLINK;
1008 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1010 CallOpc = (isDirect || Subtarget->hasV5TOps())
1011 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
1012 : ARMISD::CALL_NOLINK;
1014 if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb1Only()) {
1015 // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK
1016 Chain = DAG.getCopyToReg(Chain, dl, ARM::LR, DAG.getUNDEF(MVT::i32),InFlag);
1017 InFlag = Chain.getValue(1);
1020 std::vector<SDValue> Ops;
1021 Ops.push_back(Chain);
1022 Ops.push_back(Callee);
1024 // Add argument registers to the end of the list so that they are known live
1026 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1027 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1028 RegsToPass[i].second.getValueType()));
1030 if (InFlag.getNode())
1031 Ops.push_back(InFlag);
1032 // Returns a chain and a flag for retval copy to use.
1033 Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(MVT::Other, MVT::Flag),
1034 &Ops[0], Ops.size());
1035 InFlag = Chain.getValue(1);
1037 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1038 DAG.getIntPtrConstant(0, true), InFlag);
1040 InFlag = Chain.getValue(1);
1042 // Handle result values, copying them out of physregs into vregs that we
1044 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1049 ARMTargetLowering::LowerReturn(SDValue Chain,
1050 unsigned CallConv, bool isVarArg,
1051 const SmallVectorImpl<ISD::OutputArg> &Outs,
1052 DebugLoc dl, SelectionDAG &DAG) {
1054 // CCValAssign - represent the assignment of the return value to a location.
1055 SmallVector<CCValAssign, 16> RVLocs;
1057 // CCState - Info about the registers and stack slots.
1058 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
1061 // Analyze outgoing return values.
1062 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1065 // If this is the first return lowered for this function, add
1066 // the regs to the liveout set for the function.
1067 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1068 for (unsigned i = 0; i != RVLocs.size(); ++i)
1069 if (RVLocs[i].isRegLoc())
1070 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1075 // Copy the result values into the output registers.
1076 for (unsigned i = 0, realRVLocIdx = 0;
1078 ++i, ++realRVLocIdx) {
1079 CCValAssign &VA = RVLocs[i];
1080 assert(VA.isRegLoc() && "Can only return in registers!");
1082 SDValue Arg = Outs[realRVLocIdx].Val;
1084 switch (VA.getLocInfo()) {
1085 default: llvm_unreachable("Unknown loc info!");
1086 case CCValAssign::Full: break;
1087 case CCValAssign::BCvt:
1088 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1092 if (VA.needsCustom()) {
1093 if (VA.getLocVT() == MVT::v2f64) {
1094 // Extract the first half and return it in two registers.
1095 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1096 DAG.getConstant(0, MVT::i32));
1097 SDValue HalfGPRs = DAG.getNode(ARMISD::FMRRD, dl,
1098 DAG.getVTList(MVT::i32, MVT::i32), Half);
1100 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1101 Flag = Chain.getValue(1);
1102 VA = RVLocs[++i]; // skip ahead to next loc
1103 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1104 HalfGPRs.getValue(1), Flag);
1105 Flag = Chain.getValue(1);
1106 VA = RVLocs[++i]; // skip ahead to next loc
1108 // Extract the 2nd half and fall through to handle it as an f64 value.
1109 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1110 DAG.getConstant(1, MVT::i32));
1112 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1114 SDValue fmrrd = DAG.getNode(ARMISD::FMRRD, dl,
1115 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1116 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1117 Flag = Chain.getValue(1);
1118 VA = RVLocs[++i]; // skip ahead to next loc
1119 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1122 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1124 // Guarantee that all emitted copies are
1125 // stuck together, avoiding something bad.
1126 Flag = Chain.getValue(1);
1131 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1133 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1138 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1139 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1140 // one of the above mentioned nodes. It has to be wrapped because otherwise
1141 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1142 // be used to form addressing mode. These wrapped nodes will be selected
1144 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1145 EVT PtrVT = Op.getValueType();
1146 // FIXME there is no actual debug info here
1147 DebugLoc dl = Op.getDebugLoc();
1148 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1150 if (CP->isMachineConstantPoolEntry())
1151 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1152 CP->getAlignment());
1154 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1155 CP->getAlignment());
1156 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1159 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
1161 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1162 SelectionDAG &DAG) {
1163 DebugLoc dl = GA->getDebugLoc();
1164 EVT PtrVT = getPointerTy();
1165 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1166 ARMConstantPoolValue *CPV =
1167 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
1168 PCAdj, "tlsgd", true);
1169 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1170 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
1171 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument, NULL, 0);
1172 SDValue Chain = Argument.getValue(1);
1174 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1175 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
1177 // call __tls_get_addr.
1180 Entry.Node = Argument;
1181 Entry.Ty = (const Type *) Type::Int32Ty;
1182 Args.push_back(Entry);
1183 // FIXME: is there useful debug info available here?
1184 std::pair<SDValue, SDValue> CallResult =
1185 LowerCallTo(Chain, (const Type *) Type::Int32Ty, false, false, false, false,
1186 0, CallingConv::C, false, /*isReturnValueUsed=*/true,
1187 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
1188 return CallResult.first;
1191 // Lower ISD::GlobalTLSAddress using the "initial exec" or
1192 // "local exec" model.
1194 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
1195 SelectionDAG &DAG) {
1196 GlobalValue *GV = GA->getGlobal();
1197 DebugLoc dl = GA->getDebugLoc();
1199 SDValue Chain = DAG.getEntryNode();
1200 EVT PtrVT = getPointerTy();
1201 // Get the Thread Pointer
1202 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1204 if (GV->isDeclaration()) {
1205 // initial exec model
1206 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1207 ARMConstantPoolValue *CPV =
1208 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
1209 PCAdj, "gottpoff", true);
1210 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1211 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1212 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
1213 Chain = Offset.getValue(1);
1215 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1216 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
1218 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
1221 ARMConstantPoolValue *CPV =
1222 new ARMConstantPoolValue(GV, ARMCP::CPValue, "tpoff");
1223 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1224 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1225 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
1228 // The address of the thread local variable is the add of the thread
1229 // pointer with the offset of the variable.
1230 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
1234 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
1235 // TODO: implement the "local dynamic" model
1236 assert(Subtarget->isTargetELF() &&
1237 "TLS not implemented for non-ELF targets");
1238 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1239 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
1240 // otherwise use the "Local Exec" TLS Model
1241 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
1242 return LowerToTLSGeneralDynamicModel(GA, DAG);
1244 return LowerToTLSExecModels(GA, DAG);
1247 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
1248 SelectionDAG &DAG) {
1249 EVT PtrVT = getPointerTy();
1250 DebugLoc dl = Op.getDebugLoc();
1251 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1252 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1253 if (RelocM == Reloc::PIC_) {
1254 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
1255 ARMConstantPoolValue *CPV =
1256 new ARMConstantPoolValue(GV, ARMCP::CPValue, UseGOTOFF ? "GOTOFF":"GOT");
1257 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1258 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1259 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1261 SDValue Chain = Result.getValue(1);
1262 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1263 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
1265 Result = DAG.getLoad(PtrVT, dl, Chain, Result, NULL, 0);
1268 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1269 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1270 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
1274 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol
1275 /// even in non-static mode.
1276 static bool GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model RelocM) {
1277 // If symbol visibility is hidden, the extra load is not needed if
1278 // the symbol is definitely defined in the current translation unit.
1279 bool isDecl = GV->isDeclaration() || GV->hasAvailableExternallyLinkage();
1280 if (GV->hasHiddenVisibility() && (!isDecl && !GV->hasCommonLinkage()))
1282 return RelocM != Reloc::Static && (isDecl || GV->isWeakForLinker());
1285 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
1286 SelectionDAG &DAG) {
1287 EVT PtrVT = getPointerTy();
1288 DebugLoc dl = Op.getDebugLoc();
1289 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1290 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1291 bool IsIndirect = GVIsIndirectSymbol(GV, RelocM);
1293 if (RelocM == Reloc::Static)
1294 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1296 unsigned PCAdj = (RelocM != Reloc::PIC_)
1297 ? 0 : (Subtarget->isThumb() ? 4 : 8);
1298 ARMCP::ARMCPKind Kind = IsIndirect ? ARMCP::CPNonLazyPtr
1300 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
1302 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1304 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1306 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
1307 SDValue Chain = Result.getValue(1);
1309 if (RelocM == Reloc::PIC_) {
1310 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1311 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1314 Result = DAG.getLoad(PtrVT, dl, Chain, Result, NULL, 0);
1319 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
1321 assert(Subtarget->isTargetELF() &&
1322 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
1323 EVT PtrVT = getPointerTy();
1324 DebugLoc dl = Op.getDebugLoc();
1325 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1326 ARMConstantPoolValue *CPV = new ARMConstantPoolValue("_GLOBAL_OFFSET_TABLE_",
1328 ARMCP::CPValue, PCAdj);
1329 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1330 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1331 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
1332 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1333 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1336 static SDValue LowerNeonVLDIntrinsic(SDValue Op, SelectionDAG &DAG,
1338 SDNode *Node = Op.getNode();
1339 EVT VT = Node->getValueType(0);
1340 DebugLoc dl = Op.getDebugLoc();
1342 if (!VT.is64BitVector())
1343 return SDValue(); // unimplemented
1345 SDValue Ops[] = { Node->getOperand(0),
1346 Node->getOperand(2) };
1347 return DAG.getNode(Opcode, dl, Node->getVTList(), Ops, 2);
1350 static SDValue LowerNeonVSTIntrinsic(SDValue Op, SelectionDAG &DAG,
1351 unsigned Opcode, unsigned NumVecs) {
1352 SDNode *Node = Op.getNode();
1353 EVT VT = Node->getOperand(3).getValueType();
1354 DebugLoc dl = Op.getDebugLoc();
1356 if (!VT.is64BitVector())
1357 return SDValue(); // unimplemented
1359 SmallVector<SDValue, 6> Ops;
1360 Ops.push_back(Node->getOperand(0));
1361 Ops.push_back(Node->getOperand(2));
1362 for (unsigned N = 0; N < NumVecs; ++N)
1363 Ops.push_back(Node->getOperand(N + 3));
1364 return DAG.getNode(Opcode, dl, MVT::Other, Ops.data(), Ops.size());
1368 ARMTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) {
1369 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1371 case Intrinsic::arm_neon_vld2:
1372 return LowerNeonVLDIntrinsic(Op, DAG, ARMISD::VLD2D);
1373 case Intrinsic::arm_neon_vld3:
1374 return LowerNeonVLDIntrinsic(Op, DAG, ARMISD::VLD3D);
1375 case Intrinsic::arm_neon_vld4:
1376 return LowerNeonVLDIntrinsic(Op, DAG, ARMISD::VLD4D);
1377 case Intrinsic::arm_neon_vst2:
1378 return LowerNeonVSTIntrinsic(Op, DAG, ARMISD::VST2D, 2);
1379 case Intrinsic::arm_neon_vst3:
1380 return LowerNeonVSTIntrinsic(Op, DAG, ARMISD::VST3D, 3);
1381 case Intrinsic::arm_neon_vst4:
1382 return LowerNeonVSTIntrinsic(Op, DAG, ARMISD::VST4D, 4);
1383 default: return SDValue(); // Don't custom lower most intrinsics.
1388 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
1389 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1390 DebugLoc dl = Op.getDebugLoc();
1392 default: return SDValue(); // Don't custom lower most intrinsics.
1393 case Intrinsic::arm_thread_pointer: {
1394 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1395 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1397 case Intrinsic::eh_sjlj_lsda: {
1398 // blah. horrible, horrible hack with the forced magic name.
1399 // really need to clean this up. It belongs in the target-independent
1400 // layer somehow that doesn't require the coupling with the asm
1402 MachineFunction &MF = DAG.getMachineFunction();
1403 EVT PtrVT = getPointerTy();
1404 DebugLoc dl = Op.getDebugLoc();
1405 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1407 unsigned PCAdj = (RelocM != Reloc::PIC_)
1408 ? 0 : (Subtarget->isThumb() ? 4 : 8);
1409 ARMCP::ARMCPKind Kind = ARMCP::CPValue;
1410 // Save off the LSDA name for the AsmPrinter to use when it's time
1411 // to emit the table
1412 std::string LSDAName = "L_lsda_";
1413 LSDAName += MF.getFunction()->getName();
1414 ARMConstantPoolValue *CPV =
1415 new ARMConstantPoolValue(LSDAName.c_str(), ARMPCLabelIndex, Kind, PCAdj);
1416 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1417 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1419 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
1420 SDValue Chain = Result.getValue(1);
1422 if (RelocM == Reloc::PIC_) {
1423 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1424 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1428 case Intrinsic::eh_sjlj_setjmp:
1429 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(1));
1433 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
1434 unsigned VarArgsFrameIndex) {
1435 // vastart just stores the address of the VarArgsFrameIndex slot into the
1436 // memory location argument.
1437 DebugLoc dl = Op.getDebugLoc();
1438 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1439 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1440 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1441 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
1445 ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) {
1446 SDNode *Node = Op.getNode();
1447 DebugLoc dl = Node->getDebugLoc();
1448 EVT VT = Node->getValueType(0);
1449 SDValue Chain = Op.getOperand(0);
1450 SDValue Size = Op.getOperand(1);
1451 SDValue Align = Op.getOperand(2);
1453 // Chain the dynamic stack allocation so that it doesn't modify the stack
1454 // pointer when other instructions are using the stack.
1455 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1457 unsigned AlignVal = cast<ConstantSDNode>(Align)->getZExtValue();
1458 unsigned StackAlign = getTargetMachine().getFrameInfo()->getStackAlignment();
1459 if (AlignVal > StackAlign)
1460 // Do this now since selection pass cannot introduce new target
1461 // independent node.
1462 Align = DAG.getConstant(-(uint64_t)AlignVal, VT);
1464 // In Thumb1 mode, there isn't a "sub r, sp, r" instruction, we will end up
1465 // using a "add r, sp, r" instead. Negate the size now so we don't have to
1466 // do even more horrible hack later.
1467 MachineFunction &MF = DAG.getMachineFunction();
1468 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1469 if (AFI->isThumb1OnlyFunction()) {
1471 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Size);
1473 uint32_t Val = C->getZExtValue();
1474 if (Val <= 508 && ((Val & 3) == 0))
1478 Size = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, VT), Size);
1481 SDVTList VTList = DAG.getVTList(VT, MVT::Other);
1482 SDValue Ops1[] = { Chain, Size, Align };
1483 SDValue Res = DAG.getNode(ARMISD::DYN_ALLOC, dl, VTList, Ops1, 3);
1484 Chain = Res.getValue(1);
1485 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1486 DAG.getIntPtrConstant(0, true), SDValue());
1487 SDValue Ops2[] = { Res, Chain };
1488 return DAG.getMergeValues(Ops2, 2, dl);
1492 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
1493 SDValue &Root, SelectionDAG &DAG,
1495 MachineFunction &MF = DAG.getMachineFunction();
1496 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1498 TargetRegisterClass *RC;
1499 if (AFI->isThumb1OnlyFunction())
1500 RC = ARM::tGPRRegisterClass;
1502 RC = ARM::GPRRegisterClass;
1504 // Transform the arguments stored in physical registers into virtual ones.
1505 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1506 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
1509 if (NextVA.isMemLoc()) {
1510 unsigned ArgSize = NextVA.getLocVT().getSizeInBits()/8;
1511 MachineFrameInfo *MFI = MF.getFrameInfo();
1512 int FI = MFI->CreateFixedObject(ArgSize, NextVA.getLocMemOffset());
1514 // Create load node to retrieve arguments from the stack.
1515 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1516 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN, NULL, 0);
1518 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
1519 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
1522 return DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, ArgValue, ArgValue2);
1526 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
1527 unsigned CallConv, bool isVarArg,
1528 const SmallVectorImpl<ISD::InputArg>
1530 DebugLoc dl, SelectionDAG &DAG,
1531 SmallVectorImpl<SDValue> &InVals) {
1533 MachineFunction &MF = DAG.getMachineFunction();
1534 MachineFrameInfo *MFI = MF.getFrameInfo();
1536 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1538 // Assign locations to all of the incoming arguments.
1539 SmallVector<CCValAssign, 16> ArgLocs;
1540 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1542 CCInfo.AnalyzeFormalArguments(Ins,
1543 CCAssignFnForNode(CallConv, /* Return*/ false,
1546 SmallVector<SDValue, 16> ArgValues;
1548 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1549 CCValAssign &VA = ArgLocs[i];
1551 // Arguments stored in registers.
1552 if (VA.isRegLoc()) {
1553 EVT RegVT = VA.getLocVT();
1556 if (VA.needsCustom()) {
1557 // f64 and vector types are split up into multiple registers or
1558 // combinations of registers and stack slots.
1561 if (VA.getLocVT() == MVT::v2f64) {
1562 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
1564 VA = ArgLocs[++i]; // skip ahead to next loc
1565 SDValue ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
1567 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1568 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
1569 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
1570 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
1571 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
1573 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
1576 TargetRegisterClass *RC;
1578 if (RegVT == MVT::f32)
1579 RC = ARM::SPRRegisterClass;
1580 else if (RegVT == MVT::f64)
1581 RC = ARM::DPRRegisterClass;
1582 else if (RegVT == MVT::v2f64)
1583 RC = ARM::QPRRegisterClass;
1584 else if (RegVT == MVT::i32)
1585 RC = (AFI->isThumb1OnlyFunction() ?
1586 ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
1588 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
1590 // Transform the arguments in physical registers into virtual ones.
1591 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1592 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1595 // If this is an 8 or 16-bit value, it is really passed promoted
1596 // to 32 bits. Insert an assert[sz]ext to capture this, then
1597 // truncate to the right size.
1598 switch (VA.getLocInfo()) {
1599 default: llvm_unreachable("Unknown loc info!");
1600 case CCValAssign::Full: break;
1601 case CCValAssign::BCvt:
1602 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1604 case CCValAssign::SExt:
1605 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1606 DAG.getValueType(VA.getValVT()));
1607 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1609 case CCValAssign::ZExt:
1610 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1611 DAG.getValueType(VA.getValVT()));
1612 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1616 InVals.push_back(ArgValue);
1618 } else { // VA.isRegLoc()
1621 assert(VA.isMemLoc());
1622 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
1624 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
1625 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset());
1627 // Create load nodes to retrieve arguments from the stack.
1628 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1629 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, NULL, 0));
1635 static const unsigned GPRArgRegs[] = {
1636 ARM::R0, ARM::R1, ARM::R2, ARM::R3
1639 unsigned NumGPRs = CCInfo.getFirstUnallocated
1640 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
1642 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1643 unsigned VARegSize = (4 - NumGPRs) * 4;
1644 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
1645 unsigned ArgOffset = 0;
1646 if (VARegSaveSize) {
1647 // If this function is vararg, store any remaining integer argument regs
1648 // to their spots on the stack so that they may be loaded by deferencing
1649 // the result of va_next.
1650 AFI->setVarArgsRegSaveSize(VARegSaveSize);
1651 ArgOffset = CCInfo.getNextStackOffset();
1652 VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset +
1653 VARegSaveSize - VARegSize);
1654 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
1656 SmallVector<SDValue, 4> MemOps;
1657 for (; NumGPRs < 4; ++NumGPRs) {
1658 TargetRegisterClass *RC;
1659 if (AFI->isThumb1OnlyFunction())
1660 RC = ARM::tGPRRegisterClass;
1662 RC = ARM::GPRRegisterClass;
1664 unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
1665 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
1666 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
1667 MemOps.push_back(Store);
1668 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
1669 DAG.getConstant(4, getPointerTy()));
1671 if (!MemOps.empty())
1672 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1673 &MemOps[0], MemOps.size());
1675 // This will point to the next argument passed via stack.
1676 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
1682 /// isFloatingPointZero - Return true if this is +0.0.
1683 static bool isFloatingPointZero(SDValue Op) {
1684 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1685 return CFP->getValueAPF().isPosZero();
1686 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1687 // Maybe this has already been legalized into the constant pool?
1688 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
1689 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
1690 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
1691 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1692 return CFP->getValueAPF().isPosZero();
1698 static bool isLegalCmpImmediate(unsigned C, bool isThumb1Only) {
1699 return ( isThumb1Only && (C & ~255U) == 0) ||
1700 (!isThumb1Only && ARM_AM::getSOImmVal(C) != -1);
1703 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
1704 /// the given operands.
1705 static SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1706 SDValue &ARMCC, SelectionDAG &DAG, bool isThumb1Only,
1708 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1709 unsigned C = RHSC->getZExtValue();
1710 if (!isLegalCmpImmediate(C, isThumb1Only)) {
1711 // Constant does not fit, try adjusting it by one?
1716 if (isLegalCmpImmediate(C-1, isThumb1Only)) {
1717 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1718 RHS = DAG.getConstant(C-1, MVT::i32);
1723 if (C > 0 && isLegalCmpImmediate(C-1, isThumb1Only)) {
1724 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1725 RHS = DAG.getConstant(C-1, MVT::i32);
1730 if (isLegalCmpImmediate(C+1, isThumb1Only)) {
1731 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1732 RHS = DAG.getConstant(C+1, MVT::i32);
1737 if (C < 0xffffffff && isLegalCmpImmediate(C+1, isThumb1Only)) {
1738 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1739 RHS = DAG.getConstant(C+1, MVT::i32);
1746 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
1747 ARMISD::NodeType CompareType;
1750 CompareType = ARMISD::CMP;
1755 CompareType = ARMISD::CMPZ;
1758 ARMCC = DAG.getConstant(CondCode, MVT::i32);
1759 return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS);
1762 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
1763 static SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
1766 if (!isFloatingPointZero(RHS))
1767 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS);
1769 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS);
1770 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp);
1773 static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
1774 const ARMSubtarget *ST) {
1775 EVT VT = Op.getValueType();
1776 SDValue LHS = Op.getOperand(0);
1777 SDValue RHS = Op.getOperand(1);
1778 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1779 SDValue TrueVal = Op.getOperand(2);
1780 SDValue FalseVal = Op.getOperand(3);
1781 DebugLoc dl = Op.getDebugLoc();
1783 if (LHS.getValueType() == MVT::i32) {
1785 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1786 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb1Only(), dl);
1787 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC, CCR,Cmp);
1790 ARMCC::CondCodes CondCode, CondCode2;
1791 if (FPCCToARMCC(CC, CondCode, CondCode2))
1792 std::swap(TrueVal, FalseVal);
1794 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
1795 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1796 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
1797 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
1799 if (CondCode2 != ARMCC::AL) {
1800 SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
1801 // FIXME: Needs another CMP because flag can have but one use.
1802 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
1803 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
1804 Result, TrueVal, ARMCC2, CCR, Cmp2);
1809 static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
1810 const ARMSubtarget *ST) {
1811 SDValue Chain = Op.getOperand(0);
1812 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1813 SDValue LHS = Op.getOperand(2);
1814 SDValue RHS = Op.getOperand(3);
1815 SDValue Dest = Op.getOperand(4);
1816 DebugLoc dl = Op.getDebugLoc();
1818 if (LHS.getValueType() == MVT::i32) {
1820 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1821 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb1Only(), dl);
1822 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
1823 Chain, Dest, ARMCC, CCR,Cmp);
1826 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
1827 ARMCC::CondCodes CondCode, CondCode2;
1828 if (FPCCToARMCC(CC, CondCode, CondCode2))
1829 // Swap the LHS/RHS of the comparison if needed.
1830 std::swap(LHS, RHS);
1832 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
1833 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
1834 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1835 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
1836 SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp };
1837 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
1838 if (CondCode2 != ARMCC::AL) {
1839 ARMCC = DAG.getConstant(CondCode2, MVT::i32);
1840 SDValue Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) };
1841 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
1846 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) {
1847 SDValue Chain = Op.getOperand(0);
1848 SDValue Table = Op.getOperand(1);
1849 SDValue Index = Op.getOperand(2);
1850 DebugLoc dl = Op.getDebugLoc();
1852 EVT PTy = getPointerTy();
1853 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
1854 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
1855 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
1856 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
1857 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
1858 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
1859 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
1860 if (Subtarget->isThumb2()) {
1861 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
1862 // which does another jump to the destination. This also makes it easier
1863 // to translate it to TBB / TBH later.
1864 // FIXME: This might not work if the function is extremely large.
1865 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
1866 Addr, Op.getOperand(2), JTI, UId);
1868 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1869 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr, NULL, 0);
1870 Chain = Addr.getValue(1);
1871 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
1872 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
1874 Addr = DAG.getLoad(PTy, dl, Chain, Addr, NULL, 0);
1875 Chain = Addr.getValue(1);
1876 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
1880 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1881 DebugLoc dl = Op.getDebugLoc();
1883 Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI;
1884 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
1885 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
1888 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1889 EVT VT = Op.getValueType();
1890 DebugLoc dl = Op.getDebugLoc();
1892 Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF;
1894 Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
1895 return DAG.getNode(Opc, dl, VT, Op);
1898 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
1899 // Implement fcopysign with a fabs and a conditional fneg.
1900 SDValue Tmp0 = Op.getOperand(0);
1901 SDValue Tmp1 = Op.getOperand(1);
1902 DebugLoc dl = Op.getDebugLoc();
1903 EVT VT = Op.getValueType();
1904 EVT SrcVT = Tmp1.getValueType();
1905 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
1906 SDValue Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG, dl);
1907 SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
1908 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1909 return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp);
1912 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
1913 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1914 MFI->setFrameAddressIsTaken(true);
1915 EVT VT = Op.getValueType();
1916 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
1917 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1918 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
1919 ? ARM::R7 : ARM::R11;
1920 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
1922 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0);
1927 ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
1929 SDValue Dst, SDValue Src,
1930 SDValue Size, unsigned Align,
1932 const Value *DstSV, uint64_t DstSVOff,
1933 const Value *SrcSV, uint64_t SrcSVOff){
1934 // Do repeated 4-byte loads and stores. To be improved.
1935 // This requires 4-byte alignment.
1936 if ((Align & 3) != 0)
1938 // This requires the copy size to be a constant, preferrably
1939 // within a subtarget-specific limit.
1940 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
1943 uint64_t SizeVal = ConstantSize->getZExtValue();
1944 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
1947 unsigned BytesLeft = SizeVal & 3;
1948 unsigned NumMemOps = SizeVal >> 2;
1949 unsigned EmittedNumMemOps = 0;
1951 unsigned VTSize = 4;
1953 const unsigned MAX_LOADS_IN_LDM = 6;
1954 SDValue TFOps[MAX_LOADS_IN_LDM];
1955 SDValue Loads[MAX_LOADS_IN_LDM];
1956 uint64_t SrcOff = 0, DstOff = 0;
1958 // Emit up to MAX_LOADS_IN_LDM loads, then a TokenFactor barrier, then the
1959 // same number of stores. The loads and stores will get combined into
1960 // ldm/stm later on.
1961 while (EmittedNumMemOps < NumMemOps) {
1963 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
1964 Loads[i] = DAG.getLoad(VT, dl, Chain,
1965 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
1966 DAG.getConstant(SrcOff, MVT::i32)),
1967 SrcSV, SrcSVOff + SrcOff);
1968 TFOps[i] = Loads[i].getValue(1);
1971 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
1974 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
1975 TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
1976 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
1977 DAG.getConstant(DstOff, MVT::i32)),
1978 DstSV, DstSVOff + DstOff);
1981 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
1983 EmittedNumMemOps += i;
1989 // Issue loads / stores for the trailing (1 - 3) bytes.
1990 unsigned BytesLeftSave = BytesLeft;
1993 if (BytesLeft >= 2) {
2001 Loads[i] = DAG.getLoad(VT, dl, Chain,
2002 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
2003 DAG.getConstant(SrcOff, MVT::i32)),
2004 SrcSV, SrcSVOff + SrcOff);
2005 TFOps[i] = Loads[i].getValue(1);
2008 BytesLeft -= VTSize;
2010 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
2013 BytesLeft = BytesLeftSave;
2015 if (BytesLeft >= 2) {
2023 TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
2024 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
2025 DAG.getConstant(DstOff, MVT::i32)),
2026 DstSV, DstSVOff + DstOff);
2029 BytesLeft -= VTSize;
2031 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
2034 static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
2035 SDValue Op = N->getOperand(0);
2036 DebugLoc dl = N->getDebugLoc();
2037 if (N->getValueType(0) == MVT::f64) {
2038 // Turn i64->f64 into FMDRR.
2039 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2040 DAG.getConstant(0, MVT::i32));
2041 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2042 DAG.getConstant(1, MVT::i32));
2043 return DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
2046 // Turn f64->i64 into FMRRD.
2047 SDValue Cvt = DAG.getNode(ARMISD::FMRRD, dl,
2048 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
2050 // Merge the pieces into a single i64 value.
2051 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
2054 /// getZeroVector - Returns a vector of specified type with all zero elements.
2056 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2057 assert(VT.isVector() && "Expected a vector type");
2059 // Zero vectors are used to represent vector negation and in those cases
2060 // will be implemented with the NEON VNEG instruction. However, VNEG does
2061 // not support i64 elements, so sometimes the zero vectors will need to be
2062 // explicitly constructed. For those cases, and potentially other uses in
2063 // the future, always build zero vectors as <4 x i32> or <2 x i32> bitcasted
2064 // to their dest type. This ensures they get CSE'd.
2066 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
2067 if (VT.getSizeInBits() == 64)
2068 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
2070 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
2072 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2075 /// getOnesVector - Returns a vector of specified type with all bits set.
2077 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2078 assert(VT.isVector() && "Expected a vector type");
2080 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2081 // type. This ensures they get CSE'd.
2083 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
2084 if (VT.getSizeInBits() == 64)
2085 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
2087 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
2089 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2092 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
2093 const ARMSubtarget *ST) {
2094 EVT VT = N->getValueType(0);
2095 DebugLoc dl = N->getDebugLoc();
2097 // Lower vector shifts on NEON to use VSHL.
2098 if (VT.isVector()) {
2099 assert(ST->hasNEON() && "unexpected vector shift");
2101 // Left shifts translate directly to the vshiftu intrinsic.
2102 if (N->getOpcode() == ISD::SHL)
2103 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2104 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
2105 N->getOperand(0), N->getOperand(1));
2107 assert((N->getOpcode() == ISD::SRA ||
2108 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
2110 // NEON uses the same intrinsics for both left and right shifts. For
2111 // right shifts, the shift amounts are negative, so negate the vector of
2113 EVT ShiftVT = N->getOperand(1).getValueType();
2114 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
2115 getZeroVector(ShiftVT, DAG, dl),
2117 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
2118 Intrinsic::arm_neon_vshifts :
2119 Intrinsic::arm_neon_vshiftu);
2120 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2121 DAG.getConstant(vshiftInt, MVT::i32),
2122 N->getOperand(0), NegatedCount);
2125 assert(VT == MVT::i64 &&
2126 (N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
2127 "Unknown shift to lower!");
2129 // We only lower SRA, SRL of 1 here, all others use generic lowering.
2130 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
2131 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
2134 // If we are in thumb mode, we don't have RRX.
2135 if (ST->isThumb1Only()) return SDValue();
2137 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
2138 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2139 DAG.getConstant(0, MVT::i32));
2140 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2141 DAG.getConstant(1, MVT::i32));
2143 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
2144 // captures the result into a carry flag.
2145 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
2146 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
2148 // The low part is an ARMISD::RRX operand, which shifts the carry in.
2149 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
2151 // Merge the pieces into a single i64 value.
2152 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
2155 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
2156 SDValue TmpOp0, TmpOp1;
2157 bool Invert = false;
2161 SDValue Op0 = Op.getOperand(0);
2162 SDValue Op1 = Op.getOperand(1);
2163 SDValue CC = Op.getOperand(2);
2164 EVT VT = Op.getValueType();
2165 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
2166 DebugLoc dl = Op.getDebugLoc();
2168 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
2169 switch (SetCCOpcode) {
2170 default: llvm_unreachable("Illegal FP comparison"); break;
2172 case ISD::SETNE: Invert = true; // Fallthrough
2174 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2176 case ISD::SETLT: Swap = true; // Fallthrough
2178 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2180 case ISD::SETLE: Swap = true; // Fallthrough
2182 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2183 case ISD::SETUGE: Swap = true; // Fallthrough
2184 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
2185 case ISD::SETUGT: Swap = true; // Fallthrough
2186 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
2187 case ISD::SETUEQ: Invert = true; // Fallthrough
2189 // Expand this to (OLT | OGT).
2193 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2194 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
2196 case ISD::SETUO: Invert = true; // Fallthrough
2198 // Expand this to (OLT | OGE).
2202 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2203 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
2207 // Integer comparisons.
2208 switch (SetCCOpcode) {
2209 default: llvm_unreachable("Illegal integer comparison"); break;
2210 case ISD::SETNE: Invert = true;
2211 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2212 case ISD::SETLT: Swap = true;
2213 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2214 case ISD::SETLE: Swap = true;
2215 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2216 case ISD::SETULT: Swap = true;
2217 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
2218 case ISD::SETULE: Swap = true;
2219 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
2222 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
2223 if (Opc == ARMISD::VCEQ) {
2226 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
2228 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
2231 // Ignore bitconvert.
2232 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BIT_CONVERT)
2233 AndOp = AndOp.getOperand(0);
2235 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
2237 Op0 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(0));
2238 Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(1));
2245 std::swap(Op0, Op1);
2247 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
2250 Result = DAG.getNOT(dl, Result, VT);
2255 /// isVMOVSplat - Check if the specified splat value corresponds to an immediate
2256 /// VMOV instruction, and if so, return the constant being splatted.
2257 static SDValue isVMOVSplat(uint64_t SplatBits, uint64_t SplatUndef,
2258 unsigned SplatBitSize, SelectionDAG &DAG) {
2259 switch (SplatBitSize) {
2261 // Any 1-byte value is OK.
2262 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
2263 return DAG.getTargetConstant(SplatBits, MVT::i8);
2266 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
2267 if ((SplatBits & ~0xff) == 0 ||
2268 (SplatBits & ~0xff00) == 0)
2269 return DAG.getTargetConstant(SplatBits, MVT::i16);
2273 // NEON's 32-bit VMOV supports splat values where:
2274 // * only one byte is nonzero, or
2275 // * the least significant byte is 0xff and the second byte is nonzero, or
2276 // * the least significant 2 bytes are 0xff and the third is nonzero.
2277 if ((SplatBits & ~0xff) == 0 ||
2278 (SplatBits & ~0xff00) == 0 ||
2279 (SplatBits & ~0xff0000) == 0 ||
2280 (SplatBits & ~0xff000000) == 0)
2281 return DAG.getTargetConstant(SplatBits, MVT::i32);
2283 if ((SplatBits & ~0xffff) == 0 &&
2284 ((SplatBits | SplatUndef) & 0xff) == 0xff)
2285 return DAG.getTargetConstant(SplatBits | 0xff, MVT::i32);
2287 if ((SplatBits & ~0xffffff) == 0 &&
2288 ((SplatBits | SplatUndef) & 0xffff) == 0xffff)
2289 return DAG.getTargetConstant(SplatBits | 0xffff, MVT::i32);
2291 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
2292 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
2293 // VMOV.I32. A (very) minor optimization would be to replicate the value
2294 // and fall through here to test for a valid 64-bit splat. But, then the
2295 // caller would also need to check and handle the change in size.
2299 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
2300 uint64_t BitMask = 0xff;
2302 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
2303 if (((SplatBits | SplatUndef) & BitMask) == BitMask)
2305 else if ((SplatBits & BitMask) != 0)
2309 return DAG.getTargetConstant(Val, MVT::i64);
2313 llvm_unreachable("unexpected size for isVMOVSplat");
2320 /// getVMOVImm - If this is a build_vector of constants which can be
2321 /// formed by using a VMOV instruction of the specified element size,
2322 /// return the constant being splatted. The ByteSize field indicates the
2323 /// number of bytes of each element [1248].
2324 SDValue ARM::getVMOVImm(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
2325 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N);
2326 APInt SplatBits, SplatUndef;
2327 unsigned SplatBitSize;
2329 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
2330 HasAnyUndefs, ByteSize * 8))
2333 if (SplatBitSize > ByteSize * 8)
2336 return isVMOVSplat(SplatBits.getZExtValue(), SplatUndef.getZExtValue(),
2340 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
2341 /// instruction with the specified blocksize. (The order of the elements
2342 /// within each block of the vector is reversed.)
2343 static bool isVREVMask(ShuffleVectorSDNode *N, unsigned BlockSize) {
2344 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
2345 "Only possible block sizes for VREV are: 16, 32, 64");
2347 EVT VT = N->getValueType(0);
2348 unsigned NumElts = VT.getVectorNumElements();
2349 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2350 unsigned BlockElts = N->getMaskElt(0) + 1;
2352 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
2355 for (unsigned i = 0; i < NumElts; ++i) {
2356 if ((unsigned) N->getMaskElt(i) !=
2357 (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
2364 static SDValue BuildSplat(SDValue Val, EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2365 // Canonicalize all-zeros and all-ones vectors.
2366 ConstantSDNode *ConstVal = dyn_cast<ConstantSDNode>(Val.getNode());
2367 if (ConstVal->isNullValue())
2368 return getZeroVector(VT, DAG, dl);
2369 if (ConstVal->isAllOnesValue())
2370 return getOnesVector(VT, DAG, dl);
2373 if (VT.is64BitVector()) {
2374 switch (Val.getValueType().getSizeInBits()) {
2375 case 8: CanonicalVT = MVT::v8i8; break;
2376 case 16: CanonicalVT = MVT::v4i16; break;
2377 case 32: CanonicalVT = MVT::v2i32; break;
2378 case 64: CanonicalVT = MVT::v1i64; break;
2379 default: llvm_unreachable("unexpected splat element type"); break;
2382 assert(VT.is128BitVector() && "unknown splat vector size");
2383 switch (Val.getValueType().getSizeInBits()) {
2384 case 8: CanonicalVT = MVT::v16i8; break;
2385 case 16: CanonicalVT = MVT::v8i16; break;
2386 case 32: CanonicalVT = MVT::v4i32; break;
2387 case 64: CanonicalVT = MVT::v2i64; break;
2388 default: llvm_unreachable("unexpected splat element type"); break;
2392 // Build a canonical splat for this value.
2393 SmallVector<SDValue, 8> Ops;
2394 Ops.assign(CanonicalVT.getVectorNumElements(), Val);
2395 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, &Ops[0],
2397 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Res);
2400 // If this is a case we can't handle, return null and let the default
2401 // expansion code take care of it.
2402 static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
2403 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
2404 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
2405 DebugLoc dl = Op.getDebugLoc();
2406 EVT VT = Op.getValueType();
2408 APInt SplatBits, SplatUndef;
2409 unsigned SplatBitSize;
2411 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
2412 SDValue Val = isVMOVSplat(SplatBits.getZExtValue(),
2413 SplatUndef.getZExtValue(), SplatBitSize, DAG);
2415 return BuildSplat(Val, VT, DAG, dl);
2418 // If there are only 2 elements in a 128-bit vector, insert them into an
2419 // undef vector. This handles the common case for 128-bit vector argument
2420 // passing, where the insertions should be translated to subreg accesses
2421 // with no real instructions.
2422 if (VT.is128BitVector() && Op.getNumOperands() == 2) {
2423 SDValue Val = DAG.getUNDEF(VT);
2424 SDValue Op0 = Op.getOperand(0);
2425 SDValue Op1 = Op.getOperand(1);
2426 if (Op0.getOpcode() != ISD::UNDEF)
2427 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, Op0,
2428 DAG.getIntPtrConstant(0));
2429 if (Op1.getOpcode() != ISD::UNDEF)
2430 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, Op1,
2431 DAG.getIntPtrConstant(1));
2438 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
2439 ShuffleVectorSDNode *SVN = dyn_cast<ShuffleVectorSDNode>(Op.getNode());
2440 assert(SVN != 0 && "Expected a ShuffleVectorSDNode in LowerVECTOR_SHUFFLE");
2441 DebugLoc dl = Op.getDebugLoc();
2442 EVT VT = Op.getValueType();
2444 if (SVN->isSplat() && SVN->getSplatIndex() == 0)
2445 return DAG.getNode(ARMISD::VSPLAT0, dl, VT, SVN->getOperand(0));
2446 if (isVREVMask(SVN, 64))
2447 return DAG.getNode(ARMISD::VREV64, dl, VT, SVN->getOperand(0));
2448 if (isVREVMask(SVN, 32))
2449 return DAG.getNode(ARMISD::VREV32, dl, VT, SVN->getOperand(0));
2450 if (isVREVMask(SVN, 16))
2451 return DAG.getNode(ARMISD::VREV16, dl, VT, SVN->getOperand(0));
2456 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
2460 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
2461 EVT VT = Op.getValueType();
2462 DebugLoc dl = Op.getDebugLoc();
2463 assert((VT == MVT::i8 || VT == MVT::i16) &&
2464 "unexpected type for custom-lowering vector extract");
2465 SDValue Vec = Op.getOperand(0);
2466 SDValue Lane = Op.getOperand(1);
2467 Op = DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
2468 Op = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Op, DAG.getValueType(VT));
2469 return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
2472 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
2473 // The only time a CONCAT_VECTORS operation can have legal types is when
2474 // two 64-bit vectors are concatenated to a 128-bit vector.
2475 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
2476 "unexpected CONCAT_VECTORS");
2477 DebugLoc dl = Op.getDebugLoc();
2478 SDValue Val = DAG.getUNDEF(MVT::v2f64);
2479 SDValue Op0 = Op.getOperand(0);
2480 SDValue Op1 = Op.getOperand(1);
2481 if (Op0.getOpcode() != ISD::UNDEF)
2482 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
2483 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op0),
2484 DAG.getIntPtrConstant(0));
2485 if (Op1.getOpcode() != ISD::UNDEF)
2486 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
2487 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op1),
2488 DAG.getIntPtrConstant(1));
2489 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Val);
2492 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
2493 switch (Op.getOpcode()) {
2494 default: llvm_unreachable("Don't know how to custom lower this!");
2495 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2496 case ISD::GlobalAddress:
2497 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
2498 LowerGlobalAddressELF(Op, DAG);
2499 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
2500 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, Subtarget);
2501 case ISD::BR_CC: return LowerBR_CC(Op, DAG, Subtarget);
2502 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
2503 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
2504 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex);
2505 case ISD::SINT_TO_FP:
2506 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
2507 case ISD::FP_TO_SINT:
2508 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
2509 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
2510 case ISD::RETURNADDR: break;
2511 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
2512 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
2513 case ISD::INTRINSIC_VOID:
2514 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
2515 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2516 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(Op.getNode(), DAG);
2519 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
2520 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
2521 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
2522 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
2523 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
2524 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
2525 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
2530 /// ReplaceNodeResults - Replace the results of node with an illegal result
2531 /// type with new values built out of custom code.
2532 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
2533 SmallVectorImpl<SDValue>&Results,
2534 SelectionDAG &DAG) {
2535 switch (N->getOpcode()) {
2537 llvm_unreachable("Don't know how to custom expand this!");
2539 case ISD::BIT_CONVERT:
2540 Results.push_back(ExpandBIT_CONVERT(N, DAG));
2544 SDValue Res = LowerShift(N, DAG, Subtarget);
2546 Results.push_back(Res);
2552 //===----------------------------------------------------------------------===//
2553 // ARM Scheduler Hooks
2554 //===----------------------------------------------------------------------===//
2557 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
2558 MachineBasicBlock *BB) const {
2559 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2560 DebugLoc dl = MI->getDebugLoc();
2561 switch (MI->getOpcode()) {
2563 llvm_unreachable("Unexpected instr type to insert");
2564 case ARM::tMOVCCr_pseudo: {
2565 // To "insert" a SELECT_CC instruction, we actually have to insert the
2566 // diamond control-flow pattern. The incoming instruction knows the
2567 // destination vreg to set, the condition code register to branch on, the
2568 // true/false values to select between, and a branch opcode to use.
2569 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2570 MachineFunction::iterator It = BB;
2576 // cmpTY ccX, r1, r2
2578 // fallthrough --> copy0MBB
2579 MachineBasicBlock *thisMBB = BB;
2580 MachineFunction *F = BB->getParent();
2581 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
2582 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
2583 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
2584 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
2585 F->insert(It, copy0MBB);
2586 F->insert(It, sinkMBB);
2587 // Update machine-CFG edges by first adding all successors of the current
2588 // block to the new block which will contain the Phi node for the select.
2589 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
2590 e = BB->succ_end(); i != e; ++i)
2591 sinkMBB->addSuccessor(*i);
2592 // Next, remove all successors of the current block, and add the true
2593 // and fallthrough blocks as its successors.
2594 while(!BB->succ_empty())
2595 BB->removeSuccessor(BB->succ_begin());
2596 BB->addSuccessor(copy0MBB);
2597 BB->addSuccessor(sinkMBB);
2600 // %FalseValue = ...
2601 // # fallthrough to sinkMBB
2604 // Update machine-CFG edges
2605 BB->addSuccessor(sinkMBB);
2608 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
2611 BuildMI(BB, dl, TII->get(ARM::PHI), MI->getOperand(0).getReg())
2612 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
2613 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
2615 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
2622 case ARM::t2SUBrSPi_:
2623 case ARM::t2SUBrSPi12_:
2624 case ARM::t2SUBrSPs_: {
2625 MachineFunction *MF = BB->getParent();
2626 unsigned DstReg = MI->getOperand(0).getReg();
2627 unsigned SrcReg = MI->getOperand(1).getReg();
2628 bool DstIsDead = MI->getOperand(0).isDead();
2629 bool SrcIsKill = MI->getOperand(1).isKill();
2631 if (SrcReg != ARM::SP) {
2632 // Copy the source to SP from virtual register.
2633 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(SrcReg);
2634 unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
2635 ? ARM::tMOVtgpr2gpr : ARM::tMOVgpr2gpr;
2636 BuildMI(BB, dl, TII->get(CopyOpc), ARM::SP)
2637 .addReg(SrcReg, getKillRegState(SrcIsKill));
2641 bool NeedPred = false, NeedCC = false, NeedOp3 = false;
2642 switch (MI->getOpcode()) {
2644 llvm_unreachable("Unexpected pseudo instruction!");
2650 OpOpc = ARM::tADDspr;
2653 OpOpc = ARM::tSUBspi;
2655 case ARM::t2SUBrSPi_:
2656 OpOpc = ARM::t2SUBrSPi;
2657 NeedPred = true; NeedCC = true;
2659 case ARM::t2SUBrSPi12_:
2660 OpOpc = ARM::t2SUBrSPi12;
2663 case ARM::t2SUBrSPs_:
2664 OpOpc = ARM::t2SUBrSPs;
2665 NeedPred = true; NeedCC = true; NeedOp3 = true;
2668 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(OpOpc), ARM::SP);
2669 if (OpOpc == ARM::tAND)
2670 AddDefaultT1CC(MIB);
2671 MIB.addReg(ARM::SP);
2672 MIB.addOperand(MI->getOperand(2));
2674 MIB.addOperand(MI->getOperand(3));
2676 AddDefaultPred(MIB);
2680 // Copy the result from SP to virtual register.
2681 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(DstReg);
2682 unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
2683 ? ARM::tMOVgpr2tgpr : ARM::tMOVgpr2gpr;
2684 BuildMI(BB, dl, TII->get(CopyOpc))
2685 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead))
2687 MF->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
2693 //===----------------------------------------------------------------------===//
2694 // ARM Optimization Hooks
2695 //===----------------------------------------------------------------------===//
2698 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
2699 TargetLowering::DAGCombinerInfo &DCI) {
2700 SelectionDAG &DAG = DCI.DAG;
2701 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2702 EVT VT = N->getValueType(0);
2703 unsigned Opc = N->getOpcode();
2704 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
2705 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
2706 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
2707 ISD::CondCode CC = ISD::SETCC_INVALID;
2710 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
2712 SDValue CCOp = Slct.getOperand(0);
2713 if (CCOp.getOpcode() == ISD::SETCC)
2714 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
2717 bool DoXform = false;
2719 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
2722 if (LHS.getOpcode() == ISD::Constant &&
2723 cast<ConstantSDNode>(LHS)->isNullValue()) {
2725 } else if (CC != ISD::SETCC_INVALID &&
2726 RHS.getOpcode() == ISD::Constant &&
2727 cast<ConstantSDNode>(RHS)->isNullValue()) {
2728 std::swap(LHS, RHS);
2729 SDValue Op0 = Slct.getOperand(0);
2730 EVT OpVT = isSlctCC ? Op0.getValueType() :
2731 Op0.getOperand(0).getValueType();
2732 bool isInt = OpVT.isInteger();
2733 CC = ISD::getSetCCInverse(CC, isInt);
2735 if (!TLI.isCondCodeLegal(CC, OpVT))
2736 return SDValue(); // Inverse operator isn't legal.
2743 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
2745 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
2746 Slct.getOperand(0), Slct.getOperand(1), CC);
2747 SDValue CCOp = Slct.getOperand(0);
2749 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
2750 CCOp.getOperand(0), CCOp.getOperand(1), CC);
2751 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
2752 CCOp, OtherOp, Result);
2757 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
2758 static SDValue PerformADDCombine(SDNode *N,
2759 TargetLowering::DAGCombinerInfo &DCI) {
2760 // added by evan in r37685 with no testcase.
2761 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2763 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
2764 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
2765 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
2766 if (Result.getNode()) return Result;
2768 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
2769 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
2770 if (Result.getNode()) return Result;
2776 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
2777 static SDValue PerformSUBCombine(SDNode *N,
2778 TargetLowering::DAGCombinerInfo &DCI) {
2779 // added by evan in r37685 with no testcase.
2780 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2782 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
2783 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
2784 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
2785 if (Result.getNode()) return Result;
2792 /// PerformFMRRDCombine - Target-specific dag combine xforms for ARMISD::FMRRD.
2793 static SDValue PerformFMRRDCombine(SDNode *N,
2794 TargetLowering::DAGCombinerInfo &DCI) {
2795 // fmrrd(fmdrr x, y) -> x,y
2796 SDValue InDouble = N->getOperand(0);
2797 if (InDouble.getOpcode() == ARMISD::FMDRR)
2798 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
2802 /// getVShiftImm - Check if this is a valid build_vector for the immediate
2803 /// operand of a vector shift operation, where all the elements of the
2804 /// build_vector must have the same constant integer value.
2805 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
2806 // Ignore bit_converts.
2807 while (Op.getOpcode() == ISD::BIT_CONVERT)
2808 Op = Op.getOperand(0);
2809 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
2810 APInt SplatBits, SplatUndef;
2811 unsigned SplatBitSize;
2813 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
2814 HasAnyUndefs, ElementBits) ||
2815 SplatBitSize > ElementBits)
2817 Cnt = SplatBits.getSExtValue();
2821 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
2822 /// operand of a vector shift left operation. That value must be in the range:
2823 /// 0 <= Value < ElementBits for a left shift; or
2824 /// 0 <= Value <= ElementBits for a long left shift.
2825 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
2826 assert(VT.isVector() && "vector shift count is not a vector type");
2827 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
2828 if (! getVShiftImm(Op, ElementBits, Cnt))
2830 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
2833 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
2834 /// operand of a vector shift right operation. For a shift opcode, the value
2835 /// is positive, but for an intrinsic the value count must be negative. The
2836 /// absolute value must be in the range:
2837 /// 1 <= |Value| <= ElementBits for a right shift; or
2838 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
2839 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
2841 assert(VT.isVector() && "vector shift count is not a vector type");
2842 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
2843 if (! getVShiftImm(Op, ElementBits, Cnt))
2847 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
2850 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
2851 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
2852 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
2855 // Don't do anything for most intrinsics.
2858 // Vector shifts: check for immediate versions and lower them.
2859 // Note: This is done during DAG combining instead of DAG legalizing because
2860 // the build_vectors for 64-bit vector element shift counts are generally
2861 // not legal, and it is hard to see their values after they get legalized to
2862 // loads from a constant pool.
2863 case Intrinsic::arm_neon_vshifts:
2864 case Intrinsic::arm_neon_vshiftu:
2865 case Intrinsic::arm_neon_vshiftls:
2866 case Intrinsic::arm_neon_vshiftlu:
2867 case Intrinsic::arm_neon_vshiftn:
2868 case Intrinsic::arm_neon_vrshifts:
2869 case Intrinsic::arm_neon_vrshiftu:
2870 case Intrinsic::arm_neon_vrshiftn:
2871 case Intrinsic::arm_neon_vqshifts:
2872 case Intrinsic::arm_neon_vqshiftu:
2873 case Intrinsic::arm_neon_vqshiftsu:
2874 case Intrinsic::arm_neon_vqshiftns:
2875 case Intrinsic::arm_neon_vqshiftnu:
2876 case Intrinsic::arm_neon_vqshiftnsu:
2877 case Intrinsic::arm_neon_vqrshiftns:
2878 case Intrinsic::arm_neon_vqrshiftnu:
2879 case Intrinsic::arm_neon_vqrshiftnsu: {
2880 EVT VT = N->getOperand(1).getValueType();
2882 unsigned VShiftOpc = 0;
2885 case Intrinsic::arm_neon_vshifts:
2886 case Intrinsic::arm_neon_vshiftu:
2887 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
2888 VShiftOpc = ARMISD::VSHL;
2891 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
2892 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
2893 ARMISD::VSHRs : ARMISD::VSHRu);
2898 case Intrinsic::arm_neon_vshiftls:
2899 case Intrinsic::arm_neon_vshiftlu:
2900 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
2902 llvm_unreachable("invalid shift count for vshll intrinsic");
2904 case Intrinsic::arm_neon_vrshifts:
2905 case Intrinsic::arm_neon_vrshiftu:
2906 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
2910 case Intrinsic::arm_neon_vqshifts:
2911 case Intrinsic::arm_neon_vqshiftu:
2912 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
2916 case Intrinsic::arm_neon_vqshiftsu:
2917 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
2919 llvm_unreachable("invalid shift count for vqshlu intrinsic");
2921 case Intrinsic::arm_neon_vshiftn:
2922 case Intrinsic::arm_neon_vrshiftn:
2923 case Intrinsic::arm_neon_vqshiftns:
2924 case Intrinsic::arm_neon_vqshiftnu:
2925 case Intrinsic::arm_neon_vqshiftnsu:
2926 case Intrinsic::arm_neon_vqrshiftns:
2927 case Intrinsic::arm_neon_vqrshiftnu:
2928 case Intrinsic::arm_neon_vqrshiftnsu:
2929 // Narrowing shifts require an immediate right shift.
2930 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
2932 llvm_unreachable("invalid shift count for narrowing vector shift intrinsic");
2935 llvm_unreachable("unhandled vector shift");
2939 case Intrinsic::arm_neon_vshifts:
2940 case Intrinsic::arm_neon_vshiftu:
2941 // Opcode already set above.
2943 case Intrinsic::arm_neon_vshiftls:
2944 case Intrinsic::arm_neon_vshiftlu:
2945 if (Cnt == VT.getVectorElementType().getSizeInBits())
2946 VShiftOpc = ARMISD::VSHLLi;
2948 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
2949 ARMISD::VSHLLs : ARMISD::VSHLLu);
2951 case Intrinsic::arm_neon_vshiftn:
2952 VShiftOpc = ARMISD::VSHRN; break;
2953 case Intrinsic::arm_neon_vrshifts:
2954 VShiftOpc = ARMISD::VRSHRs; break;
2955 case Intrinsic::arm_neon_vrshiftu:
2956 VShiftOpc = ARMISD::VRSHRu; break;
2957 case Intrinsic::arm_neon_vrshiftn:
2958 VShiftOpc = ARMISD::VRSHRN; break;
2959 case Intrinsic::arm_neon_vqshifts:
2960 VShiftOpc = ARMISD::VQSHLs; break;
2961 case Intrinsic::arm_neon_vqshiftu:
2962 VShiftOpc = ARMISD::VQSHLu; break;
2963 case Intrinsic::arm_neon_vqshiftsu:
2964 VShiftOpc = ARMISD::VQSHLsu; break;
2965 case Intrinsic::arm_neon_vqshiftns:
2966 VShiftOpc = ARMISD::VQSHRNs; break;
2967 case Intrinsic::arm_neon_vqshiftnu:
2968 VShiftOpc = ARMISD::VQSHRNu; break;
2969 case Intrinsic::arm_neon_vqshiftnsu:
2970 VShiftOpc = ARMISD::VQSHRNsu; break;
2971 case Intrinsic::arm_neon_vqrshiftns:
2972 VShiftOpc = ARMISD::VQRSHRNs; break;
2973 case Intrinsic::arm_neon_vqrshiftnu:
2974 VShiftOpc = ARMISD::VQRSHRNu; break;
2975 case Intrinsic::arm_neon_vqrshiftnsu:
2976 VShiftOpc = ARMISD::VQRSHRNsu; break;
2979 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
2980 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
2983 case Intrinsic::arm_neon_vshiftins: {
2984 EVT VT = N->getOperand(1).getValueType();
2986 unsigned VShiftOpc = 0;
2988 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
2989 VShiftOpc = ARMISD::VSLI;
2990 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
2991 VShiftOpc = ARMISD::VSRI;
2993 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
2996 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
2997 N->getOperand(1), N->getOperand(2),
2998 DAG.getConstant(Cnt, MVT::i32));
3001 case Intrinsic::arm_neon_vqrshifts:
3002 case Intrinsic::arm_neon_vqrshiftu:
3003 // No immediate versions of these to check for.
3010 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
3011 /// lowers them. As with the vector shift intrinsics, this is done during DAG
3012 /// combining instead of DAG legalizing because the build_vectors for 64-bit
3013 /// vector element shift counts are generally not legal, and it is hard to see
3014 /// their values after they get legalized to loads from a constant pool.
3015 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
3016 const ARMSubtarget *ST) {
3017 EVT VT = N->getValueType(0);
3019 // Nothing to be done for scalar shifts.
3020 if (! VT.isVector())
3023 assert(ST->hasNEON() && "unexpected vector shift");
3026 switch (N->getOpcode()) {
3027 default: llvm_unreachable("unexpected shift opcode");
3030 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
3031 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
3032 DAG.getConstant(Cnt, MVT::i32));
3037 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
3038 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
3039 ARMISD::VSHRs : ARMISD::VSHRu);
3040 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
3041 DAG.getConstant(Cnt, MVT::i32));
3047 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
3048 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
3049 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
3050 const ARMSubtarget *ST) {
3051 SDValue N0 = N->getOperand(0);
3053 // Check for sign- and zero-extensions of vector extract operations of 8-
3054 // and 16-bit vector elements. NEON supports these directly. They are
3055 // handled during DAG combining because type legalization will promote them
3056 // to 32-bit types and it is messy to recognize the operations after that.
3057 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
3058 SDValue Vec = N0.getOperand(0);
3059 SDValue Lane = N0.getOperand(1);
3060 EVT VT = N->getValueType(0);
3061 EVT EltVT = N0.getValueType();
3062 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3064 if (VT == MVT::i32 &&
3065 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
3066 TLI.isTypeLegal(Vec.getValueType())) {
3069 switch (N->getOpcode()) {
3070 default: llvm_unreachable("unexpected opcode");
3071 case ISD::SIGN_EXTEND:
3072 Opc = ARMISD::VGETLANEs;
3074 case ISD::ZERO_EXTEND:
3075 case ISD::ANY_EXTEND:
3076 Opc = ARMISD::VGETLANEu;
3079 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
3086 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
3087 DAGCombinerInfo &DCI) const {
3088 switch (N->getOpcode()) {
3090 case ISD::ADD: return PerformADDCombine(N, DCI);
3091 case ISD::SUB: return PerformSUBCombine(N, DCI);
3092 case ARMISD::FMRRD: return PerformFMRRDCombine(N, DCI);
3093 case ISD::INTRINSIC_WO_CHAIN:
3094 return PerformIntrinsicCombine(N, DCI.DAG);
3098 return PerformShiftCombine(N, DCI.DAG, Subtarget);
3099 case ISD::SIGN_EXTEND:
3100 case ISD::ZERO_EXTEND:
3101 case ISD::ANY_EXTEND:
3102 return PerformExtendCombine(N, DCI.DAG, Subtarget);
3107 /// isLegalAddressImmediate - Return true if the integer value can be used
3108 /// as the offset of the target addressing mode for load / store of the
3110 static bool isLegalAddressImmediate(int64_t V, EVT VT,
3111 const ARMSubtarget *Subtarget) {
3118 if (Subtarget->isThumb()) { // FIXME for thumb2
3123 switch (VT.getSimpleVT().SimpleTy) {
3124 default: return false;
3139 if ((V & (Scale - 1)) != 0)
3142 return V == (V & ((1LL << 5) - 1));
3147 switch (VT.getSimpleVT().SimpleTy) {
3148 default: return false;
3153 return V == (V & ((1LL << 12) - 1));
3156 return V == (V & ((1LL << 8) - 1));
3159 if (!Subtarget->hasVFP2())
3164 return V == (V & ((1LL << 8) - 1));
3168 /// isLegalAddressingMode - Return true if the addressing mode represented
3169 /// by AM is legal for this target, for a load/store of the specified type.
3170 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
3171 const Type *Ty) const {
3172 EVT VT = getValueType(Ty, true);
3173 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
3176 // Can never fold addr of global into load/store.
3181 case 0: // no scale reg, must be "r+i" or "r", or "i".
3184 if (Subtarget->isThumb()) // FIXME for thumb2
3188 // ARM doesn't support any R+R*scale+imm addr modes.
3195 int Scale = AM.Scale;
3196 switch (VT.getSimpleVT().SimpleTy) {
3197 default: return false;
3202 // This assumes i64 is legalized to a pair of i32. If not (i.e.
3203 // ldrd / strd are used, then its address mode is same as i16.
3205 if (Scale < 0) Scale = -Scale;
3209 return isPowerOf2_32(Scale & ~1);
3212 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
3217 // Note, we allow "void" uses (basically, uses that aren't loads or
3218 // stores), because arm allows folding a scale into many arithmetic
3219 // operations. This should be made more precise and revisited later.
3221 // Allow r << imm, but the imm has to be a multiple of two.
3222 if (AM.Scale & 1) return false;
3223 return isPowerOf2_32(AM.Scale);
3230 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
3231 bool isSEXTLoad, SDValue &Base,
3232 SDValue &Offset, bool &isInc,
3233 SelectionDAG &DAG) {
3234 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
3237 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
3239 Base = Ptr->getOperand(0);
3240 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
3241 int RHSC = (int)RHS->getZExtValue();
3242 if (RHSC < 0 && RHSC > -256) {
3243 assert(Ptr->getOpcode() == ISD::ADD);
3245 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
3249 isInc = (Ptr->getOpcode() == ISD::ADD);
3250 Offset = Ptr->getOperand(1);
3252 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
3254 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
3255 int RHSC = (int)RHS->getZExtValue();
3256 if (RHSC < 0 && RHSC > -0x1000) {
3257 assert(Ptr->getOpcode() == ISD::ADD);
3259 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
3260 Base = Ptr->getOperand(0);
3265 if (Ptr->getOpcode() == ISD::ADD) {
3267 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
3268 if (ShOpcVal != ARM_AM::no_shift) {
3269 Base = Ptr->getOperand(1);
3270 Offset = Ptr->getOperand(0);
3272 Base = Ptr->getOperand(0);
3273 Offset = Ptr->getOperand(1);
3278 isInc = (Ptr->getOpcode() == ISD::ADD);
3279 Base = Ptr->getOperand(0);
3280 Offset = Ptr->getOperand(1);
3284 // FIXME: Use FLDM / FSTM to emulate indexed FP load / store.
3288 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
3289 bool isSEXTLoad, SDValue &Base,
3290 SDValue &Offset, bool &isInc,
3291 SelectionDAG &DAG) {
3292 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
3295 Base = Ptr->getOperand(0);
3296 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
3297 int RHSC = (int)RHS->getZExtValue();
3298 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
3299 assert(Ptr->getOpcode() == ISD::ADD);
3301 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
3303 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
3304 isInc = Ptr->getOpcode() == ISD::ADD;
3305 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
3313 /// getPreIndexedAddressParts - returns true by value, base pointer and
3314 /// offset pointer and addressing mode by reference if the node's address
3315 /// can be legally represented as pre-indexed load / store address.
3317 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
3319 ISD::MemIndexedMode &AM,
3320 SelectionDAG &DAG) const {
3321 if (Subtarget->isThumb1Only())
3326 bool isSEXTLoad = false;
3327 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3328 Ptr = LD->getBasePtr();
3329 VT = LD->getMemoryVT();
3330 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
3331 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3332 Ptr = ST->getBasePtr();
3333 VT = ST->getMemoryVT();
3338 bool isLegal = false;
3339 if (Subtarget->isThumb() && Subtarget->hasThumb2())
3340 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
3341 Offset, isInc, DAG);
3343 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
3344 Offset, isInc, DAG);
3348 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
3352 /// getPostIndexedAddressParts - returns true by value, base pointer and
3353 /// offset pointer and addressing mode by reference if this node can be
3354 /// combined with a load / store to form a post-indexed load / store.
3355 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
3358 ISD::MemIndexedMode &AM,
3359 SelectionDAG &DAG) const {
3360 if (Subtarget->isThumb1Only())
3365 bool isSEXTLoad = false;
3366 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3367 VT = LD->getMemoryVT();
3368 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
3369 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3370 VT = ST->getMemoryVT();
3375 bool isLegal = false;
3376 if (Subtarget->isThumb() && Subtarget->hasThumb2())
3377 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
3380 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
3385 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
3389 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
3393 const SelectionDAG &DAG,
3394 unsigned Depth) const {
3395 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
3396 switch (Op.getOpcode()) {
3398 case ARMISD::CMOV: {
3399 // Bits are known zero/one if known on the LHS and RHS.
3400 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
3401 if (KnownZero == 0 && KnownOne == 0) return;
3403 APInt KnownZeroRHS, KnownOneRHS;
3404 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
3405 KnownZeroRHS, KnownOneRHS, Depth+1);
3406 KnownZero &= KnownZeroRHS;
3407 KnownOne &= KnownOneRHS;
3413 //===----------------------------------------------------------------------===//
3414 // ARM Inline Assembly Support
3415 //===----------------------------------------------------------------------===//
3417 /// getConstraintType - Given a constraint letter, return the type of
3418 /// constraint it is for this target.
3419 ARMTargetLowering::ConstraintType
3420 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
3421 if (Constraint.size() == 1) {
3422 switch (Constraint[0]) {
3424 case 'l': return C_RegisterClass;
3425 case 'w': return C_RegisterClass;
3428 return TargetLowering::getConstraintType(Constraint);
3431 std::pair<unsigned, const TargetRegisterClass*>
3432 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
3434 if (Constraint.size() == 1) {
3435 // GCC RS6000 Constraint Letters
3436 switch (Constraint[0]) {
3438 if (Subtarget->isThumb1Only())
3439 return std::make_pair(0U, ARM::tGPRRegisterClass);
3441 return std::make_pair(0U, ARM::GPRRegisterClass);
3443 return std::make_pair(0U, ARM::GPRRegisterClass);
3446 return std::make_pair(0U, ARM::SPRRegisterClass);
3448 return std::make_pair(0U, ARM::DPRRegisterClass);
3452 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3455 std::vector<unsigned> ARMTargetLowering::
3456 getRegClassForInlineAsmConstraint(const std::string &Constraint,
3458 if (Constraint.size() != 1)
3459 return std::vector<unsigned>();
3461 switch (Constraint[0]) { // GCC ARM Constraint Letters
3464 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
3465 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
3468 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
3469 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
3470 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
3471 ARM::R12, ARM::LR, 0);
3474 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
3475 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
3476 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
3477 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
3478 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
3479 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
3480 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
3481 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
3483 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
3484 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
3485 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
3486 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
3490 return std::vector<unsigned>();
3493 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3494 /// vector. If it is invalid, don't add anything to Ops.
3495 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
3498 std::vector<SDValue>&Ops,
3499 SelectionDAG &DAG) const {
3500 SDValue Result(0, 0);
3502 switch (Constraint) {
3504 case 'I': case 'J': case 'K': case 'L':
3505 case 'M': case 'N': case 'O':
3506 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3510 int64_t CVal64 = C->getSExtValue();
3511 int CVal = (int) CVal64;
3512 // None of these constraints allow values larger than 32 bits. Check
3513 // that the value fits in an int.
3517 switch (Constraint) {
3519 if (Subtarget->isThumb1Only()) {
3520 // This must be a constant between 0 and 255, for ADD
3522 if (CVal >= 0 && CVal <= 255)
3524 } else if (Subtarget->isThumb2()) {
3525 // A constant that can be used as an immediate value in a
3526 // data-processing instruction.
3527 if (ARM_AM::getT2SOImmVal(CVal) != -1)
3530 // A constant that can be used as an immediate value in a
3531 // data-processing instruction.
3532 if (ARM_AM::getSOImmVal(CVal) != -1)
3538 if (Subtarget->isThumb()) { // FIXME thumb2
3539 // This must be a constant between -255 and -1, for negated ADD
3540 // immediates. This can be used in GCC with an "n" modifier that
3541 // prints the negated value, for use with SUB instructions. It is
3542 // not useful otherwise but is implemented for compatibility.
3543 if (CVal >= -255 && CVal <= -1)
3546 // This must be a constant between -4095 and 4095. It is not clear
3547 // what this constraint is intended for. Implemented for
3548 // compatibility with GCC.
3549 if (CVal >= -4095 && CVal <= 4095)
3555 if (Subtarget->isThumb1Only()) {
3556 // A 32-bit value where only one byte has a nonzero value. Exclude
3557 // zero to match GCC. This constraint is used by GCC internally for
3558 // constants that can be loaded with a move/shift combination.
3559 // It is not useful otherwise but is implemented for compatibility.
3560 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
3562 } else if (Subtarget->isThumb2()) {
3563 // A constant whose bitwise inverse can be used as an immediate
3564 // value in a data-processing instruction. This can be used in GCC
3565 // with a "B" modifier that prints the inverted value, for use with
3566 // BIC and MVN instructions. It is not useful otherwise but is
3567 // implemented for compatibility.
3568 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
3571 // A constant whose bitwise inverse can be used as an immediate
3572 // value in a data-processing instruction. This can be used in GCC
3573 // with a "B" modifier that prints the inverted value, for use with
3574 // BIC and MVN instructions. It is not useful otherwise but is
3575 // implemented for compatibility.
3576 if (ARM_AM::getSOImmVal(~CVal) != -1)
3582 if (Subtarget->isThumb1Only()) {
3583 // This must be a constant between -7 and 7,
3584 // for 3-operand ADD/SUB immediate instructions.
3585 if (CVal >= -7 && CVal < 7)
3587 } else if (Subtarget->isThumb2()) {
3588 // A constant whose negation can be used as an immediate value in a
3589 // data-processing instruction. This can be used in GCC with an "n"
3590 // modifier that prints the negated value, for use with SUB
3591 // instructions. It is not useful otherwise but is implemented for
3593 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
3596 // A constant whose negation can be used as an immediate value in a
3597 // data-processing instruction. This can be used in GCC with an "n"
3598 // modifier that prints the negated value, for use with SUB
3599 // instructions. It is not useful otherwise but is implemented for
3601 if (ARM_AM::getSOImmVal(-CVal) != -1)
3607 if (Subtarget->isThumb()) { // FIXME thumb2
3608 // This must be a multiple of 4 between 0 and 1020, for
3609 // ADD sp + immediate.
3610 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
3613 // A power of two or a constant between 0 and 32. This is used in
3614 // GCC for the shift amount on shifted register operands, but it is
3615 // useful in general for any shift amounts.
3616 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
3622 if (Subtarget->isThumb()) { // FIXME thumb2
3623 // This must be a constant between 0 and 31, for shift amounts.
3624 if (CVal >= 0 && CVal <= 31)
3630 if (Subtarget->isThumb()) { // FIXME thumb2
3631 // This must be a multiple of 4 between -508 and 508, for
3632 // ADD/SUB sp = sp + immediate.
3633 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
3638 Result = DAG.getTargetConstant(CVal, Op.getValueType());
3642 if (Result.getNode()) {
3643 Ops.push_back(Result);
3646 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,