1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "arm-isel"
17 #include "ARMAddressingModes.h"
18 #include "ARMCallingConv.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMISelLowering.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMPerfectShuffle.h"
23 #include "ARMRegisterInfo.h"
24 #include "ARMSubtarget.h"
25 #include "ARMTargetMachine.h"
26 #include "ARMTargetObjectFile.h"
27 #include "llvm/CallingConv.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Function.h"
30 #include "llvm/GlobalValue.h"
31 #include "llvm/Instruction.h"
32 #include "llvm/Instructions.h"
33 #include "llvm/Intrinsics.h"
34 #include "llvm/Type.h"
35 #include "llvm/CodeGen/CallingConvLower.h"
36 #include "llvm/CodeGen/MachineBasicBlock.h"
37 #include "llvm/CodeGen/MachineFrameInfo.h"
38 #include "llvm/CodeGen/MachineFunction.h"
39 #include "llvm/CodeGen/MachineInstrBuilder.h"
40 #include "llvm/CodeGen/MachineRegisterInfo.h"
41 #include "llvm/CodeGen/PseudoSourceValue.h"
42 #include "llvm/CodeGen/SelectionDAG.h"
43 #include "llvm/MC/MCSectionMachO.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/ADT/VectorExtras.h"
46 #include "llvm/ADT/Statistic.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Support/raw_ostream.h"
54 STATISTIC(NumTailCalls, "Number of tail calls");
56 // This option should go away when tail calls fully work.
58 EnableARMTailCalls("arm-tail-calls", cl::Hidden,
59 cl::desc("Generate tail calls (TEMPORARY OPTION)."),
63 EnableARMLongCalls("arm-long-calls", cl::Hidden,
64 cl::desc("Generate calls via indirect call instructions"),
68 ARMInterworking("arm-interworking", cl::Hidden,
69 cl::desc("Enable / disable ARM interworking (for debugging only)"),
72 void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
73 EVT PromotedBitwiseVT) {
74 if (VT != PromotedLdStVT) {
75 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
76 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
77 PromotedLdStVT.getSimpleVT());
79 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
80 AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
81 PromotedLdStVT.getSimpleVT());
84 EVT ElemTy = VT.getVectorElementType();
85 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
86 setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
87 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
88 if (ElemTy != MVT::i32) {
89 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
90 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand);
91 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand);
92 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand);
94 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
95 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
96 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
97 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Expand);
98 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
99 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
100 if (VT.isInteger()) {
101 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
102 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
103 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
104 setLoadExtAction(ISD::SEXTLOAD, VT.getSimpleVT(), Expand);
105 setLoadExtAction(ISD::ZEXTLOAD, VT.getSimpleVT(), Expand);
106 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
107 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
108 setTruncStoreAction(VT.getSimpleVT(),
109 (MVT::SimpleValueType)InnerVT, Expand);
111 setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand);
113 // Promote all bit-wise operations.
114 if (VT.isInteger() && VT != PromotedBitwiseVT) {
115 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
116 AddPromotedToType (ISD::AND, VT.getSimpleVT(),
117 PromotedBitwiseVT.getSimpleVT());
118 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
119 AddPromotedToType (ISD::OR, VT.getSimpleVT(),
120 PromotedBitwiseVT.getSimpleVT());
121 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
122 AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
123 PromotedBitwiseVT.getSimpleVT());
126 // Neon does not support vector divide/remainder operations.
127 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
128 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
129 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand);
130 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
131 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
132 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
135 void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
136 addRegisterClass(VT, ARM::DPRRegisterClass);
137 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
140 void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
141 addRegisterClass(VT, ARM::QPRRegisterClass);
142 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
145 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
146 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
147 return new TargetLoweringObjectFileMachO();
149 return new ARMElfTargetObjectFile();
152 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
153 : TargetLowering(TM, createTLOF(TM)) {
154 Subtarget = &TM.getSubtarget<ARMSubtarget>();
155 RegInfo = TM.getRegisterInfo();
156 Itins = TM.getInstrItineraryData();
158 if (Subtarget->isTargetDarwin()) {
159 // Uses VFP for Thumb libfuncs if available.
160 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
161 // Single-precision floating-point arithmetic.
162 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
163 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
164 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
165 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
167 // Double-precision floating-point arithmetic.
168 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
169 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
170 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
171 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
173 // Single-precision comparisons.
174 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
175 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
176 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
177 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
178 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
179 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
180 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
181 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
183 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
184 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
185 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
186 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
187 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
188 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
189 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
190 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
192 // Double-precision comparisons.
193 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
194 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
195 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
196 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
197 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
198 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
199 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
200 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
202 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
203 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
204 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
205 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
206 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
207 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
208 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
209 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
211 // Floating-point to integer conversions.
212 // i64 conversions are done via library routines even when generating VFP
213 // instructions, so use the same ones.
214 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
215 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
216 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
217 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
219 // Conversions between floating types.
220 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
221 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
223 // Integer to floating-point conversions.
224 // i64 conversions are done via library routines even when generating VFP
225 // instructions, so use the same ones.
226 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
227 // e.g., __floatunsidf vs. __floatunssidfvfp.
228 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
229 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
230 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
231 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
235 // These libcalls are not available in 32-bit.
236 setLibcallName(RTLIB::SHL_I128, 0);
237 setLibcallName(RTLIB::SRL_I128, 0);
238 setLibcallName(RTLIB::SRA_I128, 0);
240 if (Subtarget->isAAPCS_ABI()) {
241 // Double-precision floating-point arithmetic helper functions
242 // RTABI chapter 4.1.2, Table 2
243 setLibcallName(RTLIB::ADD_F64, "__aeabi_dadd");
244 setLibcallName(RTLIB::DIV_F64, "__aeabi_ddiv");
245 setLibcallName(RTLIB::MUL_F64, "__aeabi_dmul");
246 setLibcallName(RTLIB::SUB_F64, "__aeabi_dsub");
247 setLibcallCallingConv(RTLIB::ADD_F64, CallingConv::ARM_AAPCS);
248 setLibcallCallingConv(RTLIB::DIV_F64, CallingConv::ARM_AAPCS);
249 setLibcallCallingConv(RTLIB::MUL_F64, CallingConv::ARM_AAPCS);
250 setLibcallCallingConv(RTLIB::SUB_F64, CallingConv::ARM_AAPCS);
252 // Double-precision floating-point comparison helper functions
253 // RTABI chapter 4.1.2, Table 3
254 setLibcallName(RTLIB::OEQ_F64, "__aeabi_dcmpeq");
255 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
256 setLibcallName(RTLIB::UNE_F64, "__aeabi_dcmpeq");
257 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETEQ);
258 setLibcallName(RTLIB::OLT_F64, "__aeabi_dcmplt");
259 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
260 setLibcallName(RTLIB::OLE_F64, "__aeabi_dcmple");
261 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
262 setLibcallName(RTLIB::OGE_F64, "__aeabi_dcmpge");
263 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
264 setLibcallName(RTLIB::OGT_F64, "__aeabi_dcmpgt");
265 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
266 setLibcallName(RTLIB::UO_F64, "__aeabi_dcmpun");
267 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
268 setLibcallName(RTLIB::O_F64, "__aeabi_dcmpun");
269 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
270 setLibcallCallingConv(RTLIB::OEQ_F64, CallingConv::ARM_AAPCS);
271 setLibcallCallingConv(RTLIB::UNE_F64, CallingConv::ARM_AAPCS);
272 setLibcallCallingConv(RTLIB::OLT_F64, CallingConv::ARM_AAPCS);
273 setLibcallCallingConv(RTLIB::OLE_F64, CallingConv::ARM_AAPCS);
274 setLibcallCallingConv(RTLIB::OGE_F64, CallingConv::ARM_AAPCS);
275 setLibcallCallingConv(RTLIB::OGT_F64, CallingConv::ARM_AAPCS);
276 setLibcallCallingConv(RTLIB::UO_F64, CallingConv::ARM_AAPCS);
277 setLibcallCallingConv(RTLIB::O_F64, CallingConv::ARM_AAPCS);
279 // Single-precision floating-point arithmetic helper functions
280 // RTABI chapter 4.1.2, Table 4
281 setLibcallName(RTLIB::ADD_F32, "__aeabi_fadd");
282 setLibcallName(RTLIB::DIV_F32, "__aeabi_fdiv");
283 setLibcallName(RTLIB::MUL_F32, "__aeabi_fmul");
284 setLibcallName(RTLIB::SUB_F32, "__aeabi_fsub");
285 setLibcallCallingConv(RTLIB::ADD_F32, CallingConv::ARM_AAPCS);
286 setLibcallCallingConv(RTLIB::DIV_F32, CallingConv::ARM_AAPCS);
287 setLibcallCallingConv(RTLIB::MUL_F32, CallingConv::ARM_AAPCS);
288 setLibcallCallingConv(RTLIB::SUB_F32, CallingConv::ARM_AAPCS);
290 // Single-precision floating-point comparison helper functions
291 // RTABI chapter 4.1.2, Table 5
292 setLibcallName(RTLIB::OEQ_F32, "__aeabi_fcmpeq");
293 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
294 setLibcallName(RTLIB::UNE_F32, "__aeabi_fcmpeq");
295 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETEQ);
296 setLibcallName(RTLIB::OLT_F32, "__aeabi_fcmplt");
297 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
298 setLibcallName(RTLIB::OLE_F32, "__aeabi_fcmple");
299 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
300 setLibcallName(RTLIB::OGE_F32, "__aeabi_fcmpge");
301 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
302 setLibcallName(RTLIB::OGT_F32, "__aeabi_fcmpgt");
303 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
304 setLibcallName(RTLIB::UO_F32, "__aeabi_fcmpun");
305 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
306 setLibcallName(RTLIB::O_F32, "__aeabi_fcmpun");
307 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
308 setLibcallCallingConv(RTLIB::OEQ_F32, CallingConv::ARM_AAPCS);
309 setLibcallCallingConv(RTLIB::UNE_F32, CallingConv::ARM_AAPCS);
310 setLibcallCallingConv(RTLIB::OLT_F32, CallingConv::ARM_AAPCS);
311 setLibcallCallingConv(RTLIB::OLE_F32, CallingConv::ARM_AAPCS);
312 setLibcallCallingConv(RTLIB::OGE_F32, CallingConv::ARM_AAPCS);
313 setLibcallCallingConv(RTLIB::OGT_F32, CallingConv::ARM_AAPCS);
314 setLibcallCallingConv(RTLIB::UO_F32, CallingConv::ARM_AAPCS);
315 setLibcallCallingConv(RTLIB::O_F32, CallingConv::ARM_AAPCS);
317 // Floating-point to integer conversions.
318 // RTABI chapter 4.1.2, Table 6
319 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz");
320 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz");
321 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz");
322 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz");
323 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz");
324 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz");
325 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz");
326 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz");
327 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I32, CallingConv::ARM_AAPCS);
328 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I32, CallingConv::ARM_AAPCS);
329 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I64, CallingConv::ARM_AAPCS);
330 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::ARM_AAPCS);
331 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I32, CallingConv::ARM_AAPCS);
332 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I32, CallingConv::ARM_AAPCS);
333 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I64, CallingConv::ARM_AAPCS);
334 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::ARM_AAPCS);
336 // Conversions between floating types.
337 // RTABI chapter 4.1.2, Table 7
338 setLibcallName(RTLIB::FPROUND_F64_F32, "__aeabi_d2f");
339 setLibcallName(RTLIB::FPEXT_F32_F64, "__aeabi_f2d");
340 setLibcallCallingConv(RTLIB::FPROUND_F64_F32, CallingConv::ARM_AAPCS);
341 setLibcallCallingConv(RTLIB::FPEXT_F32_F64, CallingConv::ARM_AAPCS);
343 // Integer to floating-point conversions.
344 // RTABI chapter 4.1.2, Table 8
345 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d");
346 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d");
347 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d");
348 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d");
349 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f");
350 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f");
351 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f");
352 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f");
353 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
354 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
355 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
356 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
357 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
358 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
359 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
360 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
362 // Long long helper functions
363 // RTABI chapter 4.2, Table 9
364 setLibcallName(RTLIB::MUL_I64, "__aeabi_lmul");
365 setLibcallName(RTLIB::SDIV_I64, "__aeabi_ldivmod");
366 setLibcallName(RTLIB::UDIV_I64, "__aeabi_uldivmod");
367 setLibcallName(RTLIB::SHL_I64, "__aeabi_llsl");
368 setLibcallName(RTLIB::SRL_I64, "__aeabi_llsr");
369 setLibcallName(RTLIB::SRA_I64, "__aeabi_lasr");
370 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::ARM_AAPCS);
371 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::ARM_AAPCS);
372 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::ARM_AAPCS);
373 setLibcallCallingConv(RTLIB::SHL_I64, CallingConv::ARM_AAPCS);
374 setLibcallCallingConv(RTLIB::SRL_I64, CallingConv::ARM_AAPCS);
375 setLibcallCallingConv(RTLIB::SRA_I64, CallingConv::ARM_AAPCS);
377 // Integer division functions
378 // RTABI chapter 4.3.1
379 setLibcallName(RTLIB::SDIV_I8, "__aeabi_idiv");
380 setLibcallName(RTLIB::SDIV_I16, "__aeabi_idiv");
381 setLibcallName(RTLIB::SDIV_I32, "__aeabi_idiv");
382 setLibcallName(RTLIB::UDIV_I8, "__aeabi_uidiv");
383 setLibcallName(RTLIB::UDIV_I16, "__aeabi_uidiv");
384 setLibcallName(RTLIB::UDIV_I32, "__aeabi_uidiv");
385 setLibcallCallingConv(RTLIB::SDIV_I8, CallingConv::ARM_AAPCS);
386 setLibcallCallingConv(RTLIB::SDIV_I16, CallingConv::ARM_AAPCS);
387 setLibcallCallingConv(RTLIB::SDIV_I32, CallingConv::ARM_AAPCS);
388 setLibcallCallingConv(RTLIB::UDIV_I8, CallingConv::ARM_AAPCS);
389 setLibcallCallingConv(RTLIB::UDIV_I16, CallingConv::ARM_AAPCS);
390 setLibcallCallingConv(RTLIB::UDIV_I32, CallingConv::ARM_AAPCS);
393 if (Subtarget->isThumb1Only())
394 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
396 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
397 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
398 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
399 if (!Subtarget->isFPOnlySP())
400 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
402 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
405 if (Subtarget->hasNEON()) {
406 addDRTypeForNEON(MVT::v2f32);
407 addDRTypeForNEON(MVT::v8i8);
408 addDRTypeForNEON(MVT::v4i16);
409 addDRTypeForNEON(MVT::v2i32);
410 addDRTypeForNEON(MVT::v1i64);
412 addQRTypeForNEON(MVT::v4f32);
413 addQRTypeForNEON(MVT::v2f64);
414 addQRTypeForNEON(MVT::v16i8);
415 addQRTypeForNEON(MVT::v8i16);
416 addQRTypeForNEON(MVT::v4i32);
417 addQRTypeForNEON(MVT::v2i64);
419 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
420 // neither Neon nor VFP support any arithmetic operations on it.
421 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
422 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
423 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
424 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
425 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
426 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
427 setOperationAction(ISD::VSETCC, MVT::v2f64, Expand);
428 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
429 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
430 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
431 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
432 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
433 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
434 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
435 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
436 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
437 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
438 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
439 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
440 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
441 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
442 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
443 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
444 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
446 setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand);
448 // Neon does not support some operations on v1i64 and v2i64 types.
449 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
450 // Custom handling for some quad-vector types to detect VMULL.
451 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
452 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
453 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
454 setOperationAction(ISD::VSETCC, MVT::v1i64, Expand);
455 setOperationAction(ISD::VSETCC, MVT::v2i64, Expand);
457 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
458 setTargetDAGCombine(ISD::SHL);
459 setTargetDAGCombine(ISD::SRL);
460 setTargetDAGCombine(ISD::SRA);
461 setTargetDAGCombine(ISD::SIGN_EXTEND);
462 setTargetDAGCombine(ISD::ZERO_EXTEND);
463 setTargetDAGCombine(ISD::ANY_EXTEND);
464 setTargetDAGCombine(ISD::SELECT_CC);
465 setTargetDAGCombine(ISD::BUILD_VECTOR);
466 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
469 computeRegisterProperties();
471 // ARM does not have f32 extending load.
472 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
474 // ARM does not have i1 sign extending load.
475 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
477 // ARM supports all 4 flavors of integer indexed load / store.
478 if (!Subtarget->isThumb1Only()) {
479 for (unsigned im = (unsigned)ISD::PRE_INC;
480 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
481 setIndexedLoadAction(im, MVT::i1, Legal);
482 setIndexedLoadAction(im, MVT::i8, Legal);
483 setIndexedLoadAction(im, MVT::i16, Legal);
484 setIndexedLoadAction(im, MVT::i32, Legal);
485 setIndexedStoreAction(im, MVT::i1, Legal);
486 setIndexedStoreAction(im, MVT::i8, Legal);
487 setIndexedStoreAction(im, MVT::i16, Legal);
488 setIndexedStoreAction(im, MVT::i32, Legal);
492 // i64 operation support.
493 if (Subtarget->isThumb1Only()) {
494 setOperationAction(ISD::MUL, MVT::i64, Expand);
495 setOperationAction(ISD::MULHU, MVT::i32, Expand);
496 setOperationAction(ISD::MULHS, MVT::i32, Expand);
497 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
498 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
500 setOperationAction(ISD::MUL, MVT::i64, Expand);
501 setOperationAction(ISD::MULHU, MVT::i32, Expand);
502 if (!Subtarget->hasV6Ops())
503 setOperationAction(ISD::MULHS, MVT::i32, Expand);
505 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
506 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
507 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
508 setOperationAction(ISD::SRL, MVT::i64, Custom);
509 setOperationAction(ISD::SRA, MVT::i64, Custom);
511 // ARM does not have ROTL.
512 setOperationAction(ISD::ROTL, MVT::i32, Expand);
513 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
514 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
515 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
516 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
518 // Only ARMv6 has BSWAP.
519 if (!Subtarget->hasV6Ops())
520 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
522 // These are expanded into libcalls.
523 if (!Subtarget->hasDivide()) {
524 // v7M has a hardware divider
525 setOperationAction(ISD::SDIV, MVT::i32, Expand);
526 setOperationAction(ISD::UDIV, MVT::i32, Expand);
528 setOperationAction(ISD::SREM, MVT::i32, Expand);
529 setOperationAction(ISD::UREM, MVT::i32, Expand);
530 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
531 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
533 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
534 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
535 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
536 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
537 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
539 setOperationAction(ISD::TRAP, MVT::Other, Legal);
541 // Use the default implementation.
542 setOperationAction(ISD::VASTART, MVT::Other, Custom);
543 setOperationAction(ISD::VAARG, MVT::Other, Expand);
544 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
545 setOperationAction(ISD::VAEND, MVT::Other, Expand);
546 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
547 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
548 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
549 // FIXME: Shouldn't need this, since no register is used, but the legalizer
550 // doesn't yet know how to not do that for SjLj.
551 setExceptionSelectorRegister(ARM::R0);
552 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
553 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
554 // the default expansion.
555 if (Subtarget->hasDataBarrier() ||
556 (Subtarget->hasV6Ops() && !Subtarget->isThumb1Only())) {
557 // membarrier needs custom lowering; the rest are legal and handled
559 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
561 // Set them all for expansion, which will force libcalls.
562 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
563 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Expand);
564 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Expand);
565 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
566 setOperationAction(ISD::ATOMIC_SWAP, MVT::i8, Expand);
567 setOperationAction(ISD::ATOMIC_SWAP, MVT::i16, Expand);
568 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
569 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i8, Expand);
570 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i16, Expand);
571 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
572 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Expand);
573 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Expand);
574 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
575 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i8, Expand);
576 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i16, Expand);
577 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
578 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i8, Expand);
579 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i16, Expand);
580 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
581 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i8, Expand);
582 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i16, Expand);
583 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
584 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i8, Expand);
585 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i16, Expand);
586 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
587 // Since the libcalls include locking, fold in the fences
588 setShouldFoldAtomicFences(true);
590 // 64-bit versions are always libcalls (for now)
591 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Expand);
592 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Expand);
593 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Expand);
594 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Expand);
595 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Expand);
596 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Expand);
597 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Expand);
598 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Expand);
600 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
602 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
603 if (!Subtarget->hasV6Ops()) {
604 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
605 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
607 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
609 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
610 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
611 // iff target supports vfp2.
612 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
613 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
616 // We want to custom lower some of our intrinsics.
617 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
618 if (Subtarget->isTargetDarwin()) {
619 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
620 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
621 setOperationAction(ISD::EH_SJLJ_DISPATCHSETUP, MVT::Other, Custom);
624 setOperationAction(ISD::SETCC, MVT::i32, Expand);
625 setOperationAction(ISD::SETCC, MVT::f32, Expand);
626 setOperationAction(ISD::SETCC, MVT::f64, Expand);
627 setOperationAction(ISD::SELECT, MVT::i32, Custom);
628 setOperationAction(ISD::SELECT, MVT::f32, Custom);
629 setOperationAction(ISD::SELECT, MVT::f64, Custom);
630 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
631 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
632 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
634 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
635 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
636 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
637 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
638 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
640 // We don't support sin/cos/fmod/copysign/pow
641 setOperationAction(ISD::FSIN, MVT::f64, Expand);
642 setOperationAction(ISD::FSIN, MVT::f32, Expand);
643 setOperationAction(ISD::FCOS, MVT::f32, Expand);
644 setOperationAction(ISD::FCOS, MVT::f64, Expand);
645 setOperationAction(ISD::FREM, MVT::f64, Expand);
646 setOperationAction(ISD::FREM, MVT::f32, Expand);
647 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
648 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
649 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
651 setOperationAction(ISD::FPOW, MVT::f64, Expand);
652 setOperationAction(ISD::FPOW, MVT::f32, Expand);
654 // Various VFP goodness
655 if (!UseSoftFloat && !Subtarget->isThumb1Only()) {
656 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
657 if (Subtarget->hasVFP2()) {
658 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
659 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
660 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
661 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
663 // Special handling for half-precision FP.
664 if (!Subtarget->hasFP16()) {
665 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
666 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand);
670 // We have target-specific dag combine patterns for the following nodes:
671 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
672 setTargetDAGCombine(ISD::ADD);
673 setTargetDAGCombine(ISD::SUB);
674 setTargetDAGCombine(ISD::MUL);
676 if (Subtarget->hasV6T2Ops() || Subtarget->hasNEON())
677 setTargetDAGCombine(ISD::OR);
678 if (Subtarget->hasNEON())
679 setTargetDAGCombine(ISD::AND);
681 setStackPointerRegisterToSaveRestore(ARM::SP);
683 if (UseSoftFloat || Subtarget->isThumb1Only() || !Subtarget->hasVFP2())
684 setSchedulingPreference(Sched::RegPressure);
686 setSchedulingPreference(Sched::Hybrid);
688 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
690 // On ARM arguments smaller than 4 bytes are extended, so all arguments
691 // are at least 4 bytes aligned.
692 setMinStackArgumentAlignment(4);
694 benefitFromCodePlacementOpt = true;
697 std::pair<const TargetRegisterClass*, uint8_t>
698 ARMTargetLowering::findRepresentativeClass(EVT VT) const{
699 const TargetRegisterClass *RRC = 0;
701 switch (VT.getSimpleVT().SimpleTy) {
703 return TargetLowering::findRepresentativeClass(VT);
704 // Use DPR as representative register class for all floating point
705 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
706 // the cost is 1 for both f32 and f64.
707 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
708 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
709 RRC = ARM::DPRRegisterClass;
711 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
712 case MVT::v4f32: case MVT::v2f64:
713 RRC = ARM::DPRRegisterClass;
717 RRC = ARM::DPRRegisterClass;
721 RRC = ARM::DPRRegisterClass;
725 return std::make_pair(RRC, Cost);
728 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
731 case ARMISD::Wrapper: return "ARMISD::Wrapper";
732 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
733 case ARMISD::CALL: return "ARMISD::CALL";
734 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
735 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
736 case ARMISD::tCALL: return "ARMISD::tCALL";
737 case ARMISD::BRCOND: return "ARMISD::BRCOND";
738 case ARMISD::BR_JT: return "ARMISD::BR_JT";
739 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
740 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
741 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
742 case ARMISD::CMP: return "ARMISD::CMP";
743 case ARMISD::CMPZ: return "ARMISD::CMPZ";
744 case ARMISD::CMPFP: return "ARMISD::CMPFP";
745 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
746 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
747 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
748 case ARMISD::CMOV: return "ARMISD::CMOV";
749 case ARMISD::CNEG: return "ARMISD::CNEG";
751 case ARMISD::RBIT: return "ARMISD::RBIT";
753 case ARMISD::FTOSI: return "ARMISD::FTOSI";
754 case ARMISD::FTOUI: return "ARMISD::FTOUI";
755 case ARMISD::SITOF: return "ARMISD::SITOF";
756 case ARMISD::UITOF: return "ARMISD::UITOF";
758 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
759 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
760 case ARMISD::RRX: return "ARMISD::RRX";
762 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
763 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
765 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
766 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
767 case ARMISD::EH_SJLJ_DISPATCHSETUP:return "ARMISD::EH_SJLJ_DISPATCHSETUP";
769 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
771 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
773 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
775 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER";
776 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
778 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
780 case ARMISD::VCEQ: return "ARMISD::VCEQ";
781 case ARMISD::VCGE: return "ARMISD::VCGE";
782 case ARMISD::VCGEU: return "ARMISD::VCGEU";
783 case ARMISD::VCGT: return "ARMISD::VCGT";
784 case ARMISD::VCGTU: return "ARMISD::VCGTU";
785 case ARMISD::VTST: return "ARMISD::VTST";
787 case ARMISD::VSHL: return "ARMISD::VSHL";
788 case ARMISD::VSHRs: return "ARMISD::VSHRs";
789 case ARMISD::VSHRu: return "ARMISD::VSHRu";
790 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
791 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
792 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
793 case ARMISD::VSHRN: return "ARMISD::VSHRN";
794 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
795 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
796 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
797 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
798 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
799 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
800 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
801 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
802 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
803 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
804 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
805 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
806 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
807 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
808 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
809 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
810 case ARMISD::VDUP: return "ARMISD::VDUP";
811 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
812 case ARMISD::VEXT: return "ARMISD::VEXT";
813 case ARMISD::VREV64: return "ARMISD::VREV64";
814 case ARMISD::VREV32: return "ARMISD::VREV32";
815 case ARMISD::VREV16: return "ARMISD::VREV16";
816 case ARMISD::VZIP: return "ARMISD::VZIP";
817 case ARMISD::VUZP: return "ARMISD::VUZP";
818 case ARMISD::VTRN: return "ARMISD::VTRN";
819 case ARMISD::VMULLs: return "ARMISD::VMULLs";
820 case ARMISD::VMULLu: return "ARMISD::VMULLu";
821 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
822 case ARMISD::FMAX: return "ARMISD::FMAX";
823 case ARMISD::FMIN: return "ARMISD::FMIN";
824 case ARMISD::BFI: return "ARMISD::BFI";
825 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
829 /// getRegClassFor - Return the register class that should be used for the
830 /// specified value type.
831 TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const {
832 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
833 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
834 // load / store 4 to 8 consecutive D registers.
835 if (Subtarget->hasNEON()) {
836 if (VT == MVT::v4i64)
837 return ARM::QQPRRegisterClass;
838 else if (VT == MVT::v8i64)
839 return ARM::QQQQPRRegisterClass;
841 return TargetLowering::getRegClassFor(VT);
844 // Create a fast isel object.
846 ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
847 return ARM::createFastISel(funcInfo);
850 /// getFunctionAlignment - Return the Log2 alignment of this function.
851 unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
852 return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 1 : 2;
855 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
856 /// be used for loads / stores from the global.
857 unsigned ARMTargetLowering::getMaximalGlobalOffset() const {
858 return (Subtarget->isThumb1Only() ? 127 : 4095);
861 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
862 unsigned NumVals = N->getNumValues();
864 return Sched::RegPressure;
866 for (unsigned i = 0; i != NumVals; ++i) {
867 EVT VT = N->getValueType(i);
868 if (VT == MVT::Flag || VT == MVT::Other)
870 if (VT.isFloatingPoint() || VT.isVector())
871 return Sched::Latency;
874 if (!N->isMachineOpcode())
875 return Sched::RegPressure;
877 // Load are scheduled for latency even if there instruction itinerary
879 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
880 const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
882 if (TID.getNumDefs() == 0)
883 return Sched::RegPressure;
884 if (!Itins->isEmpty() &&
885 Itins->getOperandCycle(TID.getSchedClass(), 0) > 2)
886 return Sched::Latency;
888 return Sched::RegPressure;
892 ARMTargetLowering::getRegPressureLimit(const TargetRegisterClass *RC,
893 MachineFunction &MF) const {
894 switch (RC->getID()) {
897 case ARM::tGPRRegClassID:
898 return RegInfo->hasFP(MF) ? 4 : 5;
899 case ARM::GPRRegClassID: {
900 unsigned FP = RegInfo->hasFP(MF) ? 1 : 0;
901 return 10 - FP - (Subtarget->isR9Reserved() ? 1 : 0);
903 case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
904 case ARM::DPRRegClassID:
909 //===----------------------------------------------------------------------===//
911 //===----------------------------------------------------------------------===//
913 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
914 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
916 default: llvm_unreachable("Unknown condition code!");
917 case ISD::SETNE: return ARMCC::NE;
918 case ISD::SETEQ: return ARMCC::EQ;
919 case ISD::SETGT: return ARMCC::GT;
920 case ISD::SETGE: return ARMCC::GE;
921 case ISD::SETLT: return ARMCC::LT;
922 case ISD::SETLE: return ARMCC::LE;
923 case ISD::SETUGT: return ARMCC::HI;
924 case ISD::SETUGE: return ARMCC::HS;
925 case ISD::SETULT: return ARMCC::LO;
926 case ISD::SETULE: return ARMCC::LS;
930 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
931 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
932 ARMCC::CondCodes &CondCode2) {
933 CondCode2 = ARMCC::AL;
935 default: llvm_unreachable("Unknown FP condition!");
937 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
939 case ISD::SETOGT: CondCode = ARMCC::GT; break;
941 case ISD::SETOGE: CondCode = ARMCC::GE; break;
942 case ISD::SETOLT: CondCode = ARMCC::MI; break;
943 case ISD::SETOLE: CondCode = ARMCC::LS; break;
944 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
945 case ISD::SETO: CondCode = ARMCC::VC; break;
946 case ISD::SETUO: CondCode = ARMCC::VS; break;
947 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
948 case ISD::SETUGT: CondCode = ARMCC::HI; break;
949 case ISD::SETUGE: CondCode = ARMCC::PL; break;
951 case ISD::SETULT: CondCode = ARMCC::LT; break;
953 case ISD::SETULE: CondCode = ARMCC::LE; break;
955 case ISD::SETUNE: CondCode = ARMCC::NE; break;
959 //===----------------------------------------------------------------------===//
960 // Calling Convention Implementation
961 //===----------------------------------------------------------------------===//
963 #include "ARMGenCallingConv.inc"
965 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
966 /// given CallingConvention value.
967 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
969 bool isVarArg) const {
972 llvm_unreachable("Unsupported calling convention");
973 case CallingConv::Fast:
974 if (Subtarget->hasVFP2() && !isVarArg) {
975 if (!Subtarget->isAAPCS_ABI())
976 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
977 // For AAPCS ABI targets, just use VFP variant of the calling convention.
978 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
981 case CallingConv::C: {
982 // Use target triple & subtarget features to do actual dispatch.
983 if (!Subtarget->isAAPCS_ABI())
984 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
985 else if (Subtarget->hasVFP2() &&
986 FloatABIType == FloatABI::Hard && !isVarArg)
987 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
988 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
990 case CallingConv::ARM_AAPCS_VFP:
991 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
992 case CallingConv::ARM_AAPCS:
993 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
994 case CallingConv::ARM_APCS:
995 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
999 /// LowerCallResult - Lower the result values of a call into the
1000 /// appropriate copies out of appropriate physical registers.
1002 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1003 CallingConv::ID CallConv, bool isVarArg,
1004 const SmallVectorImpl<ISD::InputArg> &Ins,
1005 DebugLoc dl, SelectionDAG &DAG,
1006 SmallVectorImpl<SDValue> &InVals) const {
1008 // Assign locations to each value returned by this call.
1009 SmallVector<CCValAssign, 16> RVLocs;
1010 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1011 RVLocs, *DAG.getContext());
1012 CCInfo.AnalyzeCallResult(Ins,
1013 CCAssignFnForNode(CallConv, /* Return*/ true,
1016 // Copy all of the result registers out of their specified physreg.
1017 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1018 CCValAssign VA = RVLocs[i];
1021 if (VA.needsCustom()) {
1022 // Handle f64 or half of a v2f64.
1023 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1025 Chain = Lo.getValue(1);
1026 InFlag = Lo.getValue(2);
1027 VA = RVLocs[++i]; // skip ahead to next loc
1028 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1030 Chain = Hi.getValue(1);
1031 InFlag = Hi.getValue(2);
1032 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1034 if (VA.getLocVT() == MVT::v2f64) {
1035 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1036 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1037 DAG.getConstant(0, MVT::i32));
1039 VA = RVLocs[++i]; // skip ahead to next loc
1040 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1041 Chain = Lo.getValue(1);
1042 InFlag = Lo.getValue(2);
1043 VA = RVLocs[++i]; // skip ahead to next loc
1044 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1045 Chain = Hi.getValue(1);
1046 InFlag = Hi.getValue(2);
1047 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1048 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1049 DAG.getConstant(1, MVT::i32));
1052 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1054 Chain = Val.getValue(1);
1055 InFlag = Val.getValue(2);
1058 switch (VA.getLocInfo()) {
1059 default: llvm_unreachable("Unknown loc info!");
1060 case CCValAssign::Full: break;
1061 case CCValAssign::BCvt:
1062 Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val);
1066 InVals.push_back(Val);
1072 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1073 /// by "Src" to address "Dst" of size "Size". Alignment information is
1074 /// specified by the specific parameter attribute. The copy will be passed as
1075 /// a byval function parameter.
1076 /// Sometimes what we are copying is the end of a larger object, the part that
1077 /// does not fit in registers.
1079 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1080 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1082 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1083 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1084 /*isVolatile=*/false, /*AlwaysInline=*/false,
1085 MachinePointerInfo(0), MachinePointerInfo(0));
1088 /// LowerMemOpCallTo - Store the argument to the stack.
1090 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
1091 SDValue StackPtr, SDValue Arg,
1092 DebugLoc dl, SelectionDAG &DAG,
1093 const CCValAssign &VA,
1094 ISD::ArgFlagsTy Flags) const {
1095 unsigned LocMemOffset = VA.getLocMemOffset();
1096 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1097 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1098 if (Flags.isByVal())
1099 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1101 return DAG.getStore(Chain, dl, Arg, PtrOff,
1102 MachinePointerInfo::getStack(LocMemOffset),
1106 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
1107 SDValue Chain, SDValue &Arg,
1108 RegsToPassVector &RegsToPass,
1109 CCValAssign &VA, CCValAssign &NextVA,
1111 SmallVector<SDValue, 8> &MemOpChains,
1112 ISD::ArgFlagsTy Flags) const {
1114 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1115 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1116 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
1118 if (NextVA.isRegLoc())
1119 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
1121 assert(NextVA.isMemLoc());
1122 if (StackPtr.getNode() == 0)
1123 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1125 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
1131 /// LowerCall - Lowering a call into a callseq_start <-
1132 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1135 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1136 CallingConv::ID CallConv, bool isVarArg,
1138 const SmallVectorImpl<ISD::OutputArg> &Outs,
1139 const SmallVectorImpl<SDValue> &OutVals,
1140 const SmallVectorImpl<ISD::InputArg> &Ins,
1141 DebugLoc dl, SelectionDAG &DAG,
1142 SmallVectorImpl<SDValue> &InVals) const {
1143 MachineFunction &MF = DAG.getMachineFunction();
1144 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1145 bool IsSibCall = false;
1146 // Temporarily disable tail calls so things don't break.
1147 if (!EnableARMTailCalls)
1150 // Check if it's really possible to do a tail call.
1151 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1152 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1153 Outs, OutVals, Ins, DAG);
1154 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1155 // detected sibcalls.
1162 // Analyze operands of the call, assigning locations to each operand.
1163 SmallVector<CCValAssign, 16> ArgLocs;
1164 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1166 CCInfo.AnalyzeCallOperands(Outs,
1167 CCAssignFnForNode(CallConv, /* Return*/ false,
1170 // Get a count of how many bytes are to be pushed on the stack.
1171 unsigned NumBytes = CCInfo.getNextStackOffset();
1173 // For tail calls, memory operands are available in our caller's stack.
1177 // Adjust the stack pointer for the new arguments...
1178 // These operations are automatically eliminated by the prolog/epilog pass
1180 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1182 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1184 RegsToPassVector RegsToPass;
1185 SmallVector<SDValue, 8> MemOpChains;
1187 // Walk the register/memloc assignments, inserting copies/loads. In the case
1188 // of tail call optimization, arguments are handled later.
1189 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1191 ++i, ++realArgIdx) {
1192 CCValAssign &VA = ArgLocs[i];
1193 SDValue Arg = OutVals[realArgIdx];
1194 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1196 // Promote the value if needed.
1197 switch (VA.getLocInfo()) {
1198 default: llvm_unreachable("Unknown loc info!");
1199 case CCValAssign::Full: break;
1200 case CCValAssign::SExt:
1201 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1203 case CCValAssign::ZExt:
1204 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1206 case CCValAssign::AExt:
1207 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1209 case CCValAssign::BCvt:
1210 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1214 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1215 if (VA.needsCustom()) {
1216 if (VA.getLocVT() == MVT::v2f64) {
1217 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1218 DAG.getConstant(0, MVT::i32));
1219 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1220 DAG.getConstant(1, MVT::i32));
1222 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1223 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1225 VA = ArgLocs[++i]; // skip ahead to next loc
1226 if (VA.isRegLoc()) {
1227 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1228 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1230 assert(VA.isMemLoc());
1232 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1233 dl, DAG, VA, Flags));
1236 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1237 StackPtr, MemOpChains, Flags);
1239 } else if (VA.isRegLoc()) {
1240 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1241 } else if (!IsSibCall) {
1242 assert(VA.isMemLoc());
1244 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1245 dl, DAG, VA, Flags));
1249 if (!MemOpChains.empty())
1250 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1251 &MemOpChains[0], MemOpChains.size());
1253 // Build a sequence of copy-to-reg nodes chained together with token chain
1254 // and flag operands which copy the outgoing args into the appropriate regs.
1256 // Tail call byval lowering might overwrite argument registers so in case of
1257 // tail call optimization the copies to registers are lowered later.
1259 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1260 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1261 RegsToPass[i].second, InFlag);
1262 InFlag = Chain.getValue(1);
1265 // For tail calls lower the arguments to the 'real' stack slot.
1267 // Force all the incoming stack arguments to be loaded from the stack
1268 // before any new outgoing arguments are stored to the stack, because the
1269 // outgoing stack slots may alias the incoming argument stack slots, and
1270 // the alias isn't otherwise explicit. This is slightly more conservative
1271 // than necessary, because it means that each store effectively depends
1272 // on every argument instead of just those arguments it would clobber.
1274 // Do not flag preceeding copytoreg stuff together with the following stuff.
1276 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1277 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1278 RegsToPass[i].second, InFlag);
1279 InFlag = Chain.getValue(1);
1284 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1285 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1286 // node so that legalize doesn't hack it.
1287 bool isDirect = false;
1288 bool isARMFunc = false;
1289 bool isLocalARMFunc = false;
1290 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1292 if (EnableARMLongCalls) {
1293 assert (getTargetMachine().getRelocationModel() == Reloc::Static
1294 && "long-calls with non-static relocation model!");
1295 // Handle a global address or an external symbol. If it's not one of
1296 // those, the target's already in a register, so we don't need to do
1298 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1299 const GlobalValue *GV = G->getGlobal();
1300 // Create a constant pool entry for the callee address
1301 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1302 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1305 // Get the address of the callee into a register
1306 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1307 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1308 Callee = DAG.getLoad(getPointerTy(), dl,
1309 DAG.getEntryNode(), CPAddr,
1310 MachinePointerInfo::getConstantPool(),
1312 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1313 const char *Sym = S->getSymbol();
1315 // Create a constant pool entry for the callee address
1316 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1317 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1318 Sym, ARMPCLabelIndex, 0);
1319 // Get the address of the callee into a register
1320 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1321 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1322 Callee = DAG.getLoad(getPointerTy(), dl,
1323 DAG.getEntryNode(), CPAddr,
1324 MachinePointerInfo::getConstantPool(),
1327 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1328 const GlobalValue *GV = G->getGlobal();
1330 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1331 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
1332 getTargetMachine().getRelocationModel() != Reloc::Static;
1333 isARMFunc = !Subtarget->isThumb() || isStub;
1334 // ARM call to a local ARM function is predicable.
1335 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
1336 // tBX takes a register source operand.
1337 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1338 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1339 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1342 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1343 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1344 Callee = DAG.getLoad(getPointerTy(), dl,
1345 DAG.getEntryNode(), CPAddr,
1346 MachinePointerInfo::getConstantPool(),
1348 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1349 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1350 getPointerTy(), Callee, PICLabel);
1352 // On ELF targets for PIC code, direct calls should go through the PLT
1353 unsigned OpFlags = 0;
1354 if (Subtarget->isTargetELF() &&
1355 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1356 OpFlags = ARMII::MO_PLT;
1357 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
1359 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1361 bool isStub = Subtarget->isTargetDarwin() &&
1362 getTargetMachine().getRelocationModel() != Reloc::Static;
1363 isARMFunc = !Subtarget->isThumb() || isStub;
1364 // tBX takes a register source operand.
1365 const char *Sym = S->getSymbol();
1366 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1367 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1368 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1369 Sym, ARMPCLabelIndex, 4);
1370 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1371 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1372 Callee = DAG.getLoad(getPointerTy(), dl,
1373 DAG.getEntryNode(), CPAddr,
1374 MachinePointerInfo::getConstantPool(),
1376 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1377 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1378 getPointerTy(), Callee, PICLabel);
1380 unsigned OpFlags = 0;
1381 // On ELF targets for PIC code, direct calls should go through the PLT
1382 if (Subtarget->isTargetELF() &&
1383 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1384 OpFlags = ARMII::MO_PLT;
1385 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags);
1389 // FIXME: handle tail calls differently.
1391 if (Subtarget->isThumb()) {
1392 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1393 CallOpc = ARMISD::CALL_NOLINK;
1395 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1397 CallOpc = (isDirect || Subtarget->hasV5TOps())
1398 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
1399 : ARMISD::CALL_NOLINK;
1402 std::vector<SDValue> Ops;
1403 Ops.push_back(Chain);
1404 Ops.push_back(Callee);
1406 // Add argument registers to the end of the list so that they are known live
1408 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1409 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1410 RegsToPass[i].second.getValueType()));
1412 if (InFlag.getNode())
1413 Ops.push_back(InFlag);
1415 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1417 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
1419 // Returns a chain and a flag for retval copy to use.
1420 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
1421 InFlag = Chain.getValue(1);
1423 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1424 DAG.getIntPtrConstant(0, true), InFlag);
1426 InFlag = Chain.getValue(1);
1428 // Handle result values, copying them out of physregs into vregs that we
1430 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1434 /// MatchingStackOffset - Return true if the given stack call argument is
1435 /// already available in the same position (relatively) of the caller's
1436 /// incoming argument stack.
1438 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1439 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1440 const ARMInstrInfo *TII) {
1441 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
1443 if (Arg.getOpcode() == ISD::CopyFromReg) {
1444 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
1445 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR))
1447 MachineInstr *Def = MRI->getVRegDef(VR);
1450 if (!Flags.isByVal()) {
1451 if (!TII->isLoadFromStackSlot(Def, FI))
1456 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
1457 if (Flags.isByVal())
1458 // ByVal argument is passed in as a pointer but it's now being
1459 // dereferenced. e.g.
1460 // define @foo(%struct.X* %A) {
1461 // tail call @bar(%struct.X* byval %A)
1464 SDValue Ptr = Ld->getBasePtr();
1465 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
1468 FI = FINode->getIndex();
1472 assert(FI != INT_MAX);
1473 if (!MFI->isFixedObjectIndex(FI))
1475 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
1478 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1479 /// for tail call optimization. Targets which want to do tail call
1480 /// optimization should implement this function.
1482 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1483 CallingConv::ID CalleeCC,
1485 bool isCalleeStructRet,
1486 bool isCallerStructRet,
1487 const SmallVectorImpl<ISD::OutputArg> &Outs,
1488 const SmallVectorImpl<SDValue> &OutVals,
1489 const SmallVectorImpl<ISD::InputArg> &Ins,
1490 SelectionDAG& DAG) const {
1491 const Function *CallerF = DAG.getMachineFunction().getFunction();
1492 CallingConv::ID CallerCC = CallerF->getCallingConv();
1493 bool CCMatch = CallerCC == CalleeCC;
1495 // Look for obvious safe cases to perform tail call optimization that do not
1496 // require ABI changes. This is what gcc calls sibcall.
1498 // Do not sibcall optimize vararg calls unless the call site is not passing
1500 if (isVarArg && !Outs.empty())
1503 // Also avoid sibcall optimization if either caller or callee uses struct
1504 // return semantics.
1505 if (isCalleeStructRet || isCallerStructRet)
1508 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
1509 // emitEpilogue is not ready for them.
1510 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
1511 // LR. This means if we need to reload LR, it takes an extra instructions,
1512 // which outweighs the value of the tail call; but here we don't know yet
1513 // whether LR is going to be used. Probably the right approach is to
1514 // generate the tail call here and turn it back into CALL/RET in
1515 // emitEpilogue if LR is used.
1516 if (Subtarget->isThumb1Only())
1519 // For the moment, we can only do this to functions defined in this
1520 // compilation, or to indirect calls. A Thumb B to an ARM function,
1521 // or vice versa, is not easily fixed up in the linker unlike BL.
1522 // (We could do this by loading the address of the callee into a register;
1523 // that is an extra instruction over the direct call and burns a register
1524 // as well, so is not likely to be a win.)
1526 // It might be safe to remove this restriction on non-Darwin.
1528 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
1529 // but we need to make sure there are enough registers; the only valid
1530 // registers are the 4 used for parameters. We don't currently do this
1532 if (isa<ExternalSymbolSDNode>(Callee))
1535 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1536 const GlobalValue *GV = G->getGlobal();
1537 if (GV->isDeclaration() || GV->isWeakForLinker())
1541 // If the calling conventions do not match, then we'd better make sure the
1542 // results are returned in the same way as what the caller expects.
1544 SmallVector<CCValAssign, 16> RVLocs1;
1545 CCState CCInfo1(CalleeCC, false, getTargetMachine(),
1546 RVLocs1, *DAG.getContext());
1547 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
1549 SmallVector<CCValAssign, 16> RVLocs2;
1550 CCState CCInfo2(CallerCC, false, getTargetMachine(),
1551 RVLocs2, *DAG.getContext());
1552 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
1554 if (RVLocs1.size() != RVLocs2.size())
1556 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
1557 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
1559 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
1561 if (RVLocs1[i].isRegLoc()) {
1562 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
1565 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
1571 // If the callee takes no arguments then go on to check the results of the
1573 if (!Outs.empty()) {
1574 // Check if stack adjustment is needed. For now, do not do this if any
1575 // argument is passed on the stack.
1576 SmallVector<CCValAssign, 16> ArgLocs;
1577 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
1578 ArgLocs, *DAG.getContext());
1579 CCInfo.AnalyzeCallOperands(Outs,
1580 CCAssignFnForNode(CalleeCC, false, isVarArg));
1581 if (CCInfo.getNextStackOffset()) {
1582 MachineFunction &MF = DAG.getMachineFunction();
1584 // Check if the arguments are already laid out in the right way as
1585 // the caller's fixed stack objects.
1586 MachineFrameInfo *MFI = MF.getFrameInfo();
1587 const MachineRegisterInfo *MRI = &MF.getRegInfo();
1588 const ARMInstrInfo *TII =
1589 ((ARMTargetMachine&)getTargetMachine()).getInstrInfo();
1590 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1592 ++i, ++realArgIdx) {
1593 CCValAssign &VA = ArgLocs[i];
1594 EVT RegVT = VA.getLocVT();
1595 SDValue Arg = OutVals[realArgIdx];
1596 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1597 if (VA.getLocInfo() == CCValAssign::Indirect)
1599 if (VA.needsCustom()) {
1600 // f64 and vector types are split into multiple registers or
1601 // register/stack-slot combinations. The types will not match
1602 // the registers; give up on memory f64 refs until we figure
1603 // out what to do about this.
1606 if (!ArgLocs[++i].isRegLoc())
1608 if (RegVT == MVT::v2f64) {
1609 if (!ArgLocs[++i].isRegLoc())
1611 if (!ArgLocs[++i].isRegLoc())
1614 } else if (!VA.isRegLoc()) {
1615 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
1627 ARMTargetLowering::LowerReturn(SDValue Chain,
1628 CallingConv::ID CallConv, bool isVarArg,
1629 const SmallVectorImpl<ISD::OutputArg> &Outs,
1630 const SmallVectorImpl<SDValue> &OutVals,
1631 DebugLoc dl, SelectionDAG &DAG) const {
1633 // CCValAssign - represent the assignment of the return value to a location.
1634 SmallVector<CCValAssign, 16> RVLocs;
1636 // CCState - Info about the registers and stack slots.
1637 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
1640 // Analyze outgoing return values.
1641 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1644 // If this is the first return lowered for this function, add
1645 // the regs to the liveout set for the function.
1646 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1647 for (unsigned i = 0; i != RVLocs.size(); ++i)
1648 if (RVLocs[i].isRegLoc())
1649 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1654 // Copy the result values into the output registers.
1655 for (unsigned i = 0, realRVLocIdx = 0;
1657 ++i, ++realRVLocIdx) {
1658 CCValAssign &VA = RVLocs[i];
1659 assert(VA.isRegLoc() && "Can only return in registers!");
1661 SDValue Arg = OutVals[realRVLocIdx];
1663 switch (VA.getLocInfo()) {
1664 default: llvm_unreachable("Unknown loc info!");
1665 case CCValAssign::Full: break;
1666 case CCValAssign::BCvt:
1667 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1671 if (VA.needsCustom()) {
1672 if (VA.getLocVT() == MVT::v2f64) {
1673 // Extract the first half and return it in two registers.
1674 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1675 DAG.getConstant(0, MVT::i32));
1676 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
1677 DAG.getVTList(MVT::i32, MVT::i32), Half);
1679 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1680 Flag = Chain.getValue(1);
1681 VA = RVLocs[++i]; // skip ahead to next loc
1682 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1683 HalfGPRs.getValue(1), Flag);
1684 Flag = Chain.getValue(1);
1685 VA = RVLocs[++i]; // skip ahead to next loc
1687 // Extract the 2nd half and fall through to handle it as an f64 value.
1688 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1689 DAG.getConstant(1, MVT::i32));
1691 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1693 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1694 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1695 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1696 Flag = Chain.getValue(1);
1697 VA = RVLocs[++i]; // skip ahead to next loc
1698 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1701 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1703 // Guarantee that all emitted copies are
1704 // stuck together, avoiding something bad.
1705 Flag = Chain.getValue(1);
1710 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1712 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1717 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1718 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1719 // one of the above mentioned nodes. It has to be wrapped because otherwise
1720 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1721 // be used to form addressing mode. These wrapped nodes will be selected
1723 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1724 EVT PtrVT = Op.getValueType();
1725 // FIXME there is no actual debug info here
1726 DebugLoc dl = Op.getDebugLoc();
1727 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1729 if (CP->isMachineConstantPoolEntry())
1730 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1731 CP->getAlignment());
1733 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1734 CP->getAlignment());
1735 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1738 unsigned ARMTargetLowering::getJumpTableEncoding() const {
1739 return MachineJumpTableInfo::EK_Inline;
1742 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
1743 SelectionDAG &DAG) const {
1744 MachineFunction &MF = DAG.getMachineFunction();
1745 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1746 unsigned ARMPCLabelIndex = 0;
1747 DebugLoc DL = Op.getDebugLoc();
1748 EVT PtrVT = getPointerTy();
1749 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1750 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1752 if (RelocM == Reloc::Static) {
1753 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
1755 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1756 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1757 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(BA, ARMPCLabelIndex,
1758 ARMCP::CPBlockAddress,
1760 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1762 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
1763 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
1764 MachinePointerInfo::getConstantPool(),
1766 if (RelocM == Reloc::Static)
1768 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1769 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
1772 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
1774 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1775 SelectionDAG &DAG) const {
1776 DebugLoc dl = GA->getDebugLoc();
1777 EVT PtrVT = getPointerTy();
1778 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1779 MachineFunction &MF = DAG.getMachineFunction();
1780 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1781 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1782 ARMConstantPoolValue *CPV =
1783 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1784 ARMCP::CPValue, PCAdj, "tlsgd", true);
1785 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1786 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
1787 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
1788 MachinePointerInfo::getConstantPool(),
1790 SDValue Chain = Argument.getValue(1);
1792 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1793 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
1795 // call __tls_get_addr.
1798 Entry.Node = Argument;
1799 Entry.Ty = (const Type *) Type::getInt32Ty(*DAG.getContext());
1800 Args.push_back(Entry);
1801 // FIXME: is there useful debug info available here?
1802 std::pair<SDValue, SDValue> CallResult =
1803 LowerCallTo(Chain, (const Type *) Type::getInt32Ty(*DAG.getContext()),
1804 false, false, false, false,
1805 0, CallingConv::C, false, /*isReturnValueUsed=*/true,
1806 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
1807 return CallResult.first;
1810 // Lower ISD::GlobalTLSAddress using the "initial exec" or
1811 // "local exec" model.
1813 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
1814 SelectionDAG &DAG) const {
1815 const GlobalValue *GV = GA->getGlobal();
1816 DebugLoc dl = GA->getDebugLoc();
1818 SDValue Chain = DAG.getEntryNode();
1819 EVT PtrVT = getPointerTy();
1820 // Get the Thread Pointer
1821 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1823 if (GV->isDeclaration()) {
1824 MachineFunction &MF = DAG.getMachineFunction();
1825 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1826 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1827 // Initial exec model.
1828 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1829 ARMConstantPoolValue *CPV =
1830 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1831 ARMCP::CPValue, PCAdj, "gottpoff", true);
1832 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1833 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1834 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1835 MachinePointerInfo::getConstantPool(),
1837 Chain = Offset.getValue(1);
1839 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1840 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
1842 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1843 MachinePointerInfo::getConstantPool(),
1847 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, "tpoff");
1848 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1849 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1850 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1851 MachinePointerInfo::getConstantPool(),
1855 // The address of the thread local variable is the add of the thread
1856 // pointer with the offset of the variable.
1857 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
1861 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
1862 // TODO: implement the "local dynamic" model
1863 assert(Subtarget->isTargetELF() &&
1864 "TLS not implemented for non-ELF targets");
1865 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1866 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
1867 // otherwise use the "Local Exec" TLS Model
1868 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
1869 return LowerToTLSGeneralDynamicModel(GA, DAG);
1871 return LowerToTLSExecModels(GA, DAG);
1874 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
1875 SelectionDAG &DAG) const {
1876 EVT PtrVT = getPointerTy();
1877 DebugLoc dl = Op.getDebugLoc();
1878 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1879 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1880 if (RelocM == Reloc::PIC_) {
1881 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
1882 ARMConstantPoolValue *CPV =
1883 new ARMConstantPoolValue(GV, UseGOTOFF ? "GOTOFF" : "GOT");
1884 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1885 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1886 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1888 MachinePointerInfo::getConstantPool(),
1890 SDValue Chain = Result.getValue(1);
1891 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1892 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
1894 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
1895 MachinePointerInfo::getGOT(), false, false, 0);
1898 // If we have T2 ops, we can materialize the address directly via movt/movw
1899 // pair. This is always cheaper.
1900 if (Subtarget->useMovt()) {
1901 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
1902 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
1904 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1905 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1906 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1907 MachinePointerInfo::getConstantPool(),
1913 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
1914 SelectionDAG &DAG) const {
1915 MachineFunction &MF = DAG.getMachineFunction();
1916 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1917 unsigned ARMPCLabelIndex = 0;
1918 EVT PtrVT = getPointerTy();
1919 DebugLoc dl = Op.getDebugLoc();
1920 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1921 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1923 if (RelocM == Reloc::Static)
1924 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1926 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1927 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8);
1928 ARMConstantPoolValue *CPV =
1929 new ARMConstantPoolValue(GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj);
1930 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1932 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1934 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1935 MachinePointerInfo::getConstantPool(),
1937 SDValue Chain = Result.getValue(1);
1939 if (RelocM == Reloc::PIC_) {
1940 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1941 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1944 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
1945 Result = DAG.getLoad(PtrVT, dl, Chain, Result, MachinePointerInfo::getGOT(),
1951 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
1952 SelectionDAG &DAG) const {
1953 assert(Subtarget->isTargetELF() &&
1954 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
1955 MachineFunction &MF = DAG.getMachineFunction();
1956 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1957 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1958 EVT PtrVT = getPointerTy();
1959 DebugLoc dl = Op.getDebugLoc();
1960 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1961 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1962 "_GLOBAL_OFFSET_TABLE_",
1963 ARMPCLabelIndex, PCAdj);
1964 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1965 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1966 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1967 MachinePointerInfo::getConstantPool(),
1969 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1970 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1974 ARMTargetLowering::LowerEH_SJLJ_DISPATCHSETUP(SDValue Op, SelectionDAG &DAG)
1976 DebugLoc dl = Op.getDebugLoc();
1977 return DAG.getNode(ARMISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other,
1978 Op.getOperand(0), Op.getOperand(1));
1982 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
1983 DebugLoc dl = Op.getDebugLoc();
1984 SDValue Val = DAG.getConstant(0, MVT::i32);
1985 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(0),
1986 Op.getOperand(1), Val);
1990 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
1991 DebugLoc dl = Op.getDebugLoc();
1992 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
1993 Op.getOperand(1), DAG.getConstant(0, MVT::i32));
1997 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
1998 const ARMSubtarget *Subtarget) const {
1999 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2000 DebugLoc dl = Op.getDebugLoc();
2002 default: return SDValue(); // Don't custom lower most intrinsics.
2003 case Intrinsic::arm_thread_pointer: {
2004 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2005 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2007 case Intrinsic::eh_sjlj_lsda: {
2008 MachineFunction &MF = DAG.getMachineFunction();
2009 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2010 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
2011 EVT PtrVT = getPointerTy();
2012 DebugLoc dl = Op.getDebugLoc();
2013 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2015 unsigned PCAdj = (RelocM != Reloc::PIC_)
2016 ? 0 : (Subtarget->isThumb() ? 4 : 8);
2017 ARMConstantPoolValue *CPV =
2018 new ARMConstantPoolValue(MF.getFunction(), ARMPCLabelIndex,
2019 ARMCP::CPLSDA, PCAdj);
2020 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2021 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2023 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2024 MachinePointerInfo::getConstantPool(),
2027 if (RelocM == Reloc::PIC_) {
2028 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2029 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2036 static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG,
2037 const ARMSubtarget *Subtarget) {
2038 DebugLoc dl = Op.getDebugLoc();
2039 if (!Subtarget->hasDataBarrier()) {
2040 // Some ARMv6 cpus can support data barriers with an mcr instruction.
2041 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
2043 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb1Only() &&
2044 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!");
2045 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2046 DAG.getConstant(0, MVT::i32));
2049 SDValue Op5 = Op.getOperand(5);
2050 bool isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue() != 0;
2051 unsigned isLL = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
2052 unsigned isLS = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
2053 bool isOnlyStoreBarrier = (isLL == 0 && isLS == 0);
2055 ARM_MB::MemBOpt DMBOpt;
2056 if (isDeviceBarrier)
2057 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ST : ARM_MB::SY;
2059 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ISHST : ARM_MB::ISH;
2060 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
2061 DAG.getConstant(DMBOpt, MVT::i32));
2064 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
2065 const ARMSubtarget *Subtarget) {
2066 // ARM pre v5TE and Thumb1 does not have preload instructions.
2067 if (!(Subtarget->isThumb2() ||
2068 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
2069 // Just preserve the chain.
2070 return Op.getOperand(0);
2072 DebugLoc dl = Op.getDebugLoc();
2073 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
2075 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
2076 // ARMv7 with MP extension has PLDW.
2077 return Op.getOperand(0);
2079 if (Subtarget->isThumb())
2081 isRead = ~isRead & 1;
2082 unsigned isData = Subtarget->isThumb() ? 0 : 1;
2084 // Currently there is no intrinsic that matches pli.
2085 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
2086 Op.getOperand(1), DAG.getConstant(isRead, MVT::i32),
2087 DAG.getConstant(isData, MVT::i32));
2090 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
2091 MachineFunction &MF = DAG.getMachineFunction();
2092 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
2094 // vastart just stores the address of the VarArgsFrameIndex slot into the
2095 // memory location argument.
2096 DebugLoc dl = Op.getDebugLoc();
2097 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2098 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2099 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2100 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2101 MachinePointerInfo(SV), false, false, 0);
2105 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
2106 SDValue &Root, SelectionDAG &DAG,
2107 DebugLoc dl) const {
2108 MachineFunction &MF = DAG.getMachineFunction();
2109 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2111 TargetRegisterClass *RC;
2112 if (AFI->isThumb1OnlyFunction())
2113 RC = ARM::tGPRRegisterClass;
2115 RC = ARM::GPRRegisterClass;
2117 // Transform the arguments stored in physical registers into virtual ones.
2118 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2119 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2122 if (NextVA.isMemLoc()) {
2123 MachineFrameInfo *MFI = MF.getFrameInfo();
2124 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
2126 // Create load node to retrieve arguments from the stack.
2127 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2128 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
2129 MachinePointerInfo::getFixedStack(FI),
2132 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2133 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2136 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
2140 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
2141 CallingConv::ID CallConv, bool isVarArg,
2142 const SmallVectorImpl<ISD::InputArg>
2144 DebugLoc dl, SelectionDAG &DAG,
2145 SmallVectorImpl<SDValue> &InVals)
2148 MachineFunction &MF = DAG.getMachineFunction();
2149 MachineFrameInfo *MFI = MF.getFrameInfo();
2151 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2153 // Assign locations to all of the incoming arguments.
2154 SmallVector<CCValAssign, 16> ArgLocs;
2155 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
2157 CCInfo.AnalyzeFormalArguments(Ins,
2158 CCAssignFnForNode(CallConv, /* Return*/ false,
2161 SmallVector<SDValue, 16> ArgValues;
2163 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2164 CCValAssign &VA = ArgLocs[i];
2166 // Arguments stored in registers.
2167 if (VA.isRegLoc()) {
2168 EVT RegVT = VA.getLocVT();
2171 if (VA.needsCustom()) {
2172 // f64 and vector types are split up into multiple registers or
2173 // combinations of registers and stack slots.
2174 if (VA.getLocVT() == MVT::v2f64) {
2175 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
2177 VA = ArgLocs[++i]; // skip ahead to next loc
2179 if (VA.isMemLoc()) {
2180 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
2181 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2182 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
2183 MachinePointerInfo::getFixedStack(FI),
2186 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
2189 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2190 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2191 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
2192 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2193 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
2195 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
2198 TargetRegisterClass *RC;
2200 if (RegVT == MVT::f32)
2201 RC = ARM::SPRRegisterClass;
2202 else if (RegVT == MVT::f64)
2203 RC = ARM::DPRRegisterClass;
2204 else if (RegVT == MVT::v2f64)
2205 RC = ARM::QPRRegisterClass;
2206 else if (RegVT == MVT::i32)
2207 RC = (AFI->isThumb1OnlyFunction() ?
2208 ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
2210 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2212 // Transform the arguments in physical registers into virtual ones.
2213 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2214 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2217 // If this is an 8 or 16-bit value, it is really passed promoted
2218 // to 32 bits. Insert an assert[sz]ext to capture this, then
2219 // truncate to the right size.
2220 switch (VA.getLocInfo()) {
2221 default: llvm_unreachable("Unknown loc info!");
2222 case CCValAssign::Full: break;
2223 case CCValAssign::BCvt:
2224 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
2226 case CCValAssign::SExt:
2227 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2228 DAG.getValueType(VA.getValVT()));
2229 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2231 case CCValAssign::ZExt:
2232 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2233 DAG.getValueType(VA.getValVT()));
2234 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2238 InVals.push_back(ArgValue);
2240 } else { // VA.isRegLoc()
2243 assert(VA.isMemLoc());
2244 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
2246 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
2247 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(), true);
2249 // Create load nodes to retrieve arguments from the stack.
2250 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2251 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2252 MachinePointerInfo::getFixedStack(FI),
2259 static const unsigned GPRArgRegs[] = {
2260 ARM::R0, ARM::R1, ARM::R2, ARM::R3
2263 unsigned NumGPRs = CCInfo.getFirstUnallocated
2264 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
2266 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
2267 unsigned VARegSize = (4 - NumGPRs) * 4;
2268 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
2269 unsigned ArgOffset = CCInfo.getNextStackOffset();
2270 if (VARegSaveSize) {
2271 // If this function is vararg, store any remaining integer argument regs
2272 // to their spots on the stack so that they may be loaded by deferencing
2273 // the result of va_next.
2274 AFI->setVarArgsRegSaveSize(VARegSaveSize);
2275 AFI->setVarArgsFrameIndex(
2276 MFI->CreateFixedObject(VARegSaveSize,
2277 ArgOffset + VARegSaveSize - VARegSize,
2279 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(),
2282 SmallVector<SDValue, 4> MemOps;
2283 for (; NumGPRs < 4; ++NumGPRs) {
2284 TargetRegisterClass *RC;
2285 if (AFI->isThumb1OnlyFunction())
2286 RC = ARM::tGPRRegisterClass;
2288 RC = ARM::GPRRegisterClass;
2290 unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
2291 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2293 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2294 MachinePointerInfo::getFixedStack(AFI->getVarArgsFrameIndex()),
2296 MemOps.push_back(Store);
2297 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
2298 DAG.getConstant(4, getPointerTy()));
2300 if (!MemOps.empty())
2301 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2302 &MemOps[0], MemOps.size());
2304 // This will point to the next argument passed via stack.
2305 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset, true));
2311 /// isFloatingPointZero - Return true if this is +0.0.
2312 static bool isFloatingPointZero(SDValue Op) {
2313 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
2314 return CFP->getValueAPF().isPosZero();
2315 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
2316 // Maybe this has already been legalized into the constant pool?
2317 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
2318 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
2319 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
2320 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
2321 return CFP->getValueAPF().isPosZero();
2327 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
2328 /// the given operands.
2330 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2331 SDValue &ARMcc, SelectionDAG &DAG,
2332 DebugLoc dl) const {
2333 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
2334 unsigned C = RHSC->getZExtValue();
2335 if (!isLegalICmpImmediate(C)) {
2336 // Constant does not fit, try adjusting it by one?
2341 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
2342 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
2343 RHS = DAG.getConstant(C-1, MVT::i32);
2348 if (C != 0 && isLegalICmpImmediate(C-1)) {
2349 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
2350 RHS = DAG.getConstant(C-1, MVT::i32);
2355 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
2356 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
2357 RHS = DAG.getConstant(C+1, MVT::i32);
2362 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
2363 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2364 RHS = DAG.getConstant(C+1, MVT::i32);
2371 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2372 ARMISD::NodeType CompareType;
2375 CompareType = ARMISD::CMP;
2380 CompareType = ARMISD::CMPZ;
2383 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2384 return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS);
2387 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
2389 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
2390 DebugLoc dl) const {
2392 if (!isFloatingPointZero(RHS))
2393 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS);
2395 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS);
2396 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp);
2399 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2400 SDValue Cond = Op.getOperand(0);
2401 SDValue SelectTrue = Op.getOperand(1);
2402 SDValue SelectFalse = Op.getOperand(2);
2403 DebugLoc dl = Op.getDebugLoc();
2407 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
2408 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
2410 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
2411 const ConstantSDNode *CMOVTrue =
2412 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
2413 const ConstantSDNode *CMOVFalse =
2414 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
2416 if (CMOVTrue && CMOVFalse) {
2417 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
2418 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
2422 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
2424 False = SelectFalse;
2425 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
2430 if (True.getNode() && False.getNode()) {
2431 EVT VT = Cond.getValueType();
2432 SDValue ARMcc = Cond.getOperand(2);
2433 SDValue CCR = Cond.getOperand(3);
2434 SDValue Cmp = Cond.getOperand(4);
2435 return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp);
2440 return DAG.getSelectCC(dl, Cond,
2441 DAG.getConstant(0, Cond.getValueType()),
2442 SelectTrue, SelectFalse, ISD::SETNE);
2445 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
2446 EVT VT = Op.getValueType();
2447 SDValue LHS = Op.getOperand(0);
2448 SDValue RHS = Op.getOperand(1);
2449 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2450 SDValue TrueVal = Op.getOperand(2);
2451 SDValue FalseVal = Op.getOperand(3);
2452 DebugLoc dl = Op.getDebugLoc();
2454 if (LHS.getValueType() == MVT::i32) {
2456 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2457 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2458 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,Cmp);
2461 ARMCC::CondCodes CondCode, CondCode2;
2462 FPCCToARMCC(CC, CondCode, CondCode2);
2464 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2465 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2466 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2467 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
2469 if (CondCode2 != ARMCC::AL) {
2470 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32);
2471 // FIXME: Needs another CMP because flag can have but one use.
2472 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
2473 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
2474 Result, TrueVal, ARMcc2, CCR, Cmp2);
2479 /// canChangeToInt - Given the fp compare operand, return true if it is suitable
2480 /// to morph to an integer compare sequence.
2481 static bool canChangeToInt(SDValue Op, bool &SeenZero,
2482 const ARMSubtarget *Subtarget) {
2483 SDNode *N = Op.getNode();
2484 if (!N->hasOneUse())
2485 // Otherwise it requires moving the value from fp to integer registers.
2487 if (!N->getNumValues())
2489 EVT VT = Op.getValueType();
2490 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
2491 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
2492 // vmrs are very slow, e.g. cortex-a8.
2495 if (isFloatingPointZero(Op)) {
2499 return ISD::isNormalLoad(N);
2502 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
2503 if (isFloatingPointZero(Op))
2504 return DAG.getConstant(0, MVT::i32);
2506 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
2507 return DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2508 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(),
2509 Ld->isVolatile(), Ld->isNonTemporal(),
2510 Ld->getAlignment());
2512 llvm_unreachable("Unknown VFP cmp argument!");
2515 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
2516 SDValue &RetVal1, SDValue &RetVal2) {
2517 if (isFloatingPointZero(Op)) {
2518 RetVal1 = DAG.getConstant(0, MVT::i32);
2519 RetVal2 = DAG.getConstant(0, MVT::i32);
2523 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
2524 SDValue Ptr = Ld->getBasePtr();
2525 RetVal1 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2526 Ld->getChain(), Ptr,
2527 Ld->getPointerInfo(),
2528 Ld->isVolatile(), Ld->isNonTemporal(),
2529 Ld->getAlignment());
2531 EVT PtrType = Ptr.getValueType();
2532 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
2533 SDValue NewPtr = DAG.getNode(ISD::ADD, Op.getDebugLoc(),
2534 PtrType, Ptr, DAG.getConstant(4, PtrType));
2535 RetVal2 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2536 Ld->getChain(), NewPtr,
2537 Ld->getPointerInfo().getWithOffset(4),
2538 Ld->isVolatile(), Ld->isNonTemporal(),
2543 llvm_unreachable("Unknown VFP cmp argument!");
2546 /// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
2547 /// f32 and even f64 comparisons to integer ones.
2549 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
2550 SDValue Chain = Op.getOperand(0);
2551 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2552 SDValue LHS = Op.getOperand(2);
2553 SDValue RHS = Op.getOperand(3);
2554 SDValue Dest = Op.getOperand(4);
2555 DebugLoc dl = Op.getDebugLoc();
2557 bool SeenZero = false;
2558 if (canChangeToInt(LHS, SeenZero, Subtarget) &&
2559 canChangeToInt(RHS, SeenZero, Subtarget) &&
2560 // If one of the operand is zero, it's safe to ignore the NaN case since
2561 // we only care about equality comparisons.
2562 (SeenZero || (DAG.isKnownNeverNaN(LHS) && DAG.isKnownNeverNaN(RHS)))) {
2563 // If unsafe fp math optimization is enabled and there are no othter uses of
2564 // the CMP operands, and the condition code is EQ oe NE, we can optimize it
2565 // to an integer comparison.
2566 if (CC == ISD::SETOEQ)
2568 else if (CC == ISD::SETUNE)
2572 if (LHS.getValueType() == MVT::f32) {
2573 LHS = bitcastf32Toi32(LHS, DAG);
2574 RHS = bitcastf32Toi32(RHS, DAG);
2575 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2576 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2577 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2578 Chain, Dest, ARMcc, CCR, Cmp);
2583 expandf64Toi32(LHS, DAG, LHS1, LHS2);
2584 expandf64Toi32(RHS, DAG, RHS1, RHS2);
2585 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2586 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2587 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
2588 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
2589 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7);
2595 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2596 SDValue Chain = Op.getOperand(0);
2597 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2598 SDValue LHS = Op.getOperand(2);
2599 SDValue RHS = Op.getOperand(3);
2600 SDValue Dest = Op.getOperand(4);
2601 DebugLoc dl = Op.getDebugLoc();
2603 if (LHS.getValueType() == MVT::i32) {
2605 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2606 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2607 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2608 Chain, Dest, ARMcc, CCR, Cmp);
2611 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
2614 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
2615 CC == ISD::SETNE || CC == ISD::SETUNE)) {
2616 SDValue Result = OptimizeVFPBrcond(Op, DAG);
2617 if (Result.getNode())
2621 ARMCC::CondCodes CondCode, CondCode2;
2622 FPCCToARMCC(CC, CondCode, CondCode2);
2624 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2625 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2626 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2627 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
2628 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
2629 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2630 if (CondCode2 != ARMCC::AL) {
2631 ARMcc = DAG.getConstant(CondCode2, MVT::i32);
2632 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
2633 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2638 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
2639 SDValue Chain = Op.getOperand(0);
2640 SDValue Table = Op.getOperand(1);
2641 SDValue Index = Op.getOperand(2);
2642 DebugLoc dl = Op.getDebugLoc();
2644 EVT PTy = getPointerTy();
2645 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
2646 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
2647 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
2648 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
2649 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
2650 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
2651 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2652 if (Subtarget->isThumb2()) {
2653 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
2654 // which does another jump to the destination. This also makes it easier
2655 // to translate it to TBB / TBH later.
2656 // FIXME: This might not work if the function is extremely large.
2657 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
2658 Addr, Op.getOperand(2), JTI, UId);
2660 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2661 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
2662 MachinePointerInfo::getJumpTable(),
2664 Chain = Addr.getValue(1);
2665 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
2666 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2668 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
2669 MachinePointerInfo::getJumpTable(), false, false, 0);
2670 Chain = Addr.getValue(1);
2671 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2675 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
2676 DebugLoc dl = Op.getDebugLoc();
2679 switch (Op.getOpcode()) {
2681 assert(0 && "Invalid opcode!");
2682 case ISD::FP_TO_SINT:
2683 Opc = ARMISD::FTOSI;
2685 case ISD::FP_TO_UINT:
2686 Opc = ARMISD::FTOUI;
2689 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
2690 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
2693 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
2694 EVT VT = Op.getValueType();
2695 DebugLoc dl = Op.getDebugLoc();
2698 switch (Op.getOpcode()) {
2700 assert(0 && "Invalid opcode!");
2701 case ISD::SINT_TO_FP:
2702 Opc = ARMISD::SITOF;
2704 case ISD::UINT_TO_FP:
2705 Opc = ARMISD::UITOF;
2709 Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
2710 return DAG.getNode(Opc, dl, VT, Op);
2713 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
2714 // Implement fcopysign with a fabs and a conditional fneg.
2715 SDValue Tmp0 = Op.getOperand(0);
2716 SDValue Tmp1 = Op.getOperand(1);
2717 DebugLoc dl = Op.getDebugLoc();
2718 EVT VT = Op.getValueType();
2719 EVT SrcVT = Tmp1.getValueType();
2720 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
2721 SDValue ARMcc = DAG.getConstant(ARMCC::LT, MVT::i32);
2722 SDValue FP0 = DAG.getConstantFP(0.0, SrcVT);
2723 SDValue Cmp = getVFPCmp(Tmp1, FP0, DAG, dl);
2724 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2725 return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMcc, CCR, Cmp);
2728 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
2729 MachineFunction &MF = DAG.getMachineFunction();
2730 MachineFrameInfo *MFI = MF.getFrameInfo();
2731 MFI->setReturnAddressIsTaken(true);
2733 EVT VT = Op.getValueType();
2734 DebugLoc dl = Op.getDebugLoc();
2735 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2737 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
2738 SDValue Offset = DAG.getConstant(4, MVT::i32);
2739 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
2740 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
2741 MachinePointerInfo(), false, false, 0);
2744 // Return LR, which contains the return address. Mark it an implicit live-in.
2745 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
2746 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
2749 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2750 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2751 MFI->setFrameAddressIsTaken(true);
2753 EVT VT = Op.getValueType();
2754 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
2755 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2756 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
2757 ? ARM::R7 : ARM::R11;
2758 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
2760 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
2761 MachinePointerInfo(),
2766 /// ExpandBIT_CONVERT - If the target supports VFP, this function is called to
2767 /// expand a bit convert where either the source or destination type is i64 to
2768 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
2769 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
2770 /// vectors), since the legalizer won't know what to do with that.
2771 static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
2772 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2773 DebugLoc dl = N->getDebugLoc();
2774 SDValue Op = N->getOperand(0);
2776 // This function is only supposed to be called for i64 types, either as the
2777 // source or destination of the bit convert.
2778 EVT SrcVT = Op.getValueType();
2779 EVT DstVT = N->getValueType(0);
2780 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
2781 "ExpandBIT_CONVERT called for non-i64 type");
2783 // Turn i64->f64 into VMOVDRR.
2784 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
2785 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2786 DAG.getConstant(0, MVT::i32));
2787 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2788 DAG.getConstant(1, MVT::i32));
2789 return DAG.getNode(ISD::BIT_CONVERT, dl, DstVT,
2790 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
2793 // Turn f64->i64 into VMOVRRD.
2794 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
2795 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
2796 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
2797 // Merge the pieces into a single i64 value.
2798 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
2804 /// getZeroVector - Returns a vector of specified type with all zero elements.
2805 /// Zero vectors are used to represent vector negation and in those cases
2806 /// will be implemented with the NEON VNEG instruction. However, VNEG does
2807 /// not support i64 elements, so sometimes the zero vectors will need to be
2808 /// explicitly constructed. Regardless, use a canonical VMOV to create the
2810 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2811 assert(VT.isVector() && "Expected a vector type");
2812 // The canonical modified immediate encoding of a zero vector is....0!
2813 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32);
2814 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
2815 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
2816 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov);
2819 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
2820 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2821 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
2822 SelectionDAG &DAG) const {
2823 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2824 EVT VT = Op.getValueType();
2825 unsigned VTBits = VT.getSizeInBits();
2826 DebugLoc dl = Op.getDebugLoc();
2827 SDValue ShOpLo = Op.getOperand(0);
2828 SDValue ShOpHi = Op.getOperand(1);
2829 SDValue ShAmt = Op.getOperand(2);
2831 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
2833 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
2835 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2836 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2837 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
2838 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2839 DAG.getConstant(VTBits, MVT::i32));
2840 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
2841 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2842 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
2844 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2845 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
2847 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
2848 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
2851 SDValue Ops[2] = { Lo, Hi };
2852 return DAG.getMergeValues(Ops, 2, dl);
2855 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
2856 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2857 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
2858 SelectionDAG &DAG) const {
2859 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2860 EVT VT = Op.getValueType();
2861 unsigned VTBits = VT.getSizeInBits();
2862 DebugLoc dl = Op.getDebugLoc();
2863 SDValue ShOpLo = Op.getOperand(0);
2864 SDValue ShOpHi = Op.getOperand(1);
2865 SDValue ShAmt = Op.getOperand(2);
2868 assert(Op.getOpcode() == ISD::SHL_PARTS);
2869 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2870 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2871 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
2872 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2873 DAG.getConstant(VTBits, MVT::i32));
2874 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
2875 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
2877 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2878 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2879 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
2881 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
2882 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
2885 SDValue Ops[2] = { Lo, Hi };
2886 return DAG.getMergeValues(Ops, 2, dl);
2889 SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
2890 SelectionDAG &DAG) const {
2891 // The rounding mode is in bits 23:22 of the FPSCR.
2892 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
2893 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
2894 // so that the shift + and get folded into a bitfield extract.
2895 DebugLoc dl = Op.getDebugLoc();
2896 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
2897 DAG.getConstant(Intrinsic::arm_get_fpscr,
2899 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
2900 DAG.getConstant(1U << 22, MVT::i32));
2901 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
2902 DAG.getConstant(22, MVT::i32));
2903 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
2904 DAG.getConstant(3, MVT::i32));
2907 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
2908 const ARMSubtarget *ST) {
2909 EVT VT = N->getValueType(0);
2910 DebugLoc dl = N->getDebugLoc();
2912 if (!ST->hasV6T2Ops())
2915 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
2916 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
2919 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
2920 const ARMSubtarget *ST) {
2921 EVT VT = N->getValueType(0);
2922 DebugLoc dl = N->getDebugLoc();
2924 // Lower vector shifts on NEON to use VSHL.
2925 if (VT.isVector()) {
2926 assert(ST->hasNEON() && "unexpected vector shift");
2928 // Left shifts translate directly to the vshiftu intrinsic.
2929 if (N->getOpcode() == ISD::SHL)
2930 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2931 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
2932 N->getOperand(0), N->getOperand(1));
2934 assert((N->getOpcode() == ISD::SRA ||
2935 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
2937 // NEON uses the same intrinsics for both left and right shifts. For
2938 // right shifts, the shift amounts are negative, so negate the vector of
2940 EVT ShiftVT = N->getOperand(1).getValueType();
2941 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
2942 getZeroVector(ShiftVT, DAG, dl),
2944 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
2945 Intrinsic::arm_neon_vshifts :
2946 Intrinsic::arm_neon_vshiftu);
2947 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2948 DAG.getConstant(vshiftInt, MVT::i32),
2949 N->getOperand(0), NegatedCount);
2952 // We can get here for a node like i32 = ISD::SHL i32, i64
2956 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
2957 "Unknown shift to lower!");
2959 // We only lower SRA, SRL of 1 here, all others use generic lowering.
2960 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
2961 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
2964 // If we are in thumb mode, we don't have RRX.
2965 if (ST->isThumb1Only()) return SDValue();
2967 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
2968 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2969 DAG.getConstant(0, MVT::i32));
2970 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2971 DAG.getConstant(1, MVT::i32));
2973 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
2974 // captures the result into a carry flag.
2975 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
2976 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
2978 // The low part is an ARMISD::RRX operand, which shifts the carry in.
2979 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
2981 // Merge the pieces into a single i64 value.
2982 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
2985 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
2986 SDValue TmpOp0, TmpOp1;
2987 bool Invert = false;
2991 SDValue Op0 = Op.getOperand(0);
2992 SDValue Op1 = Op.getOperand(1);
2993 SDValue CC = Op.getOperand(2);
2994 EVT VT = Op.getValueType();
2995 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
2996 DebugLoc dl = Op.getDebugLoc();
2998 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
2999 switch (SetCCOpcode) {
3000 default: llvm_unreachable("Illegal FP comparison"); break;
3002 case ISD::SETNE: Invert = true; // Fallthrough
3004 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3006 case ISD::SETLT: Swap = true; // Fallthrough
3008 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3010 case ISD::SETLE: Swap = true; // Fallthrough
3012 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3013 case ISD::SETUGE: Swap = true; // Fallthrough
3014 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
3015 case ISD::SETUGT: Swap = true; // Fallthrough
3016 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
3017 case ISD::SETUEQ: Invert = true; // Fallthrough
3019 // Expand this to (OLT | OGT).
3023 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3024 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
3026 case ISD::SETUO: Invert = true; // Fallthrough
3028 // Expand this to (OLT | OGE).
3032 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3033 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
3037 // Integer comparisons.
3038 switch (SetCCOpcode) {
3039 default: llvm_unreachable("Illegal integer comparison"); break;
3040 case ISD::SETNE: Invert = true;
3041 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3042 case ISD::SETLT: Swap = true;
3043 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3044 case ISD::SETLE: Swap = true;
3045 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3046 case ISD::SETULT: Swap = true;
3047 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
3048 case ISD::SETULE: Swap = true;
3049 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
3052 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
3053 if (Opc == ARMISD::VCEQ) {
3056 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
3058 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
3061 // Ignore bitconvert.
3062 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BIT_CONVERT)
3063 AndOp = AndOp.getOperand(0);
3065 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
3067 Op0 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(0));
3068 Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(1));
3075 std::swap(Op0, Op1);
3077 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3080 Result = DAG.getNOT(dl, Result, VT);
3085 /// isNEONModifiedImm - Check if the specified splat value corresponds to a
3086 /// valid vector constant for a NEON instruction with a "modified immediate"
3087 /// operand (e.g., VMOV). If so, return the encoded value.
3088 static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
3089 unsigned SplatBitSize, SelectionDAG &DAG,
3090 EVT &VT, bool is128Bits, NEONModImmType type) {
3091 unsigned OpCmode, Imm;
3093 // SplatBitSize is set to the smallest size that splats the vector, so a
3094 // zero vector will always have SplatBitSize == 8. However, NEON modified
3095 // immediate instructions others than VMOV do not support the 8-bit encoding
3096 // of a zero vector, and the default encoding of zero is supposed to be the
3101 switch (SplatBitSize) {
3103 if (type != VMOVModImm)
3105 // Any 1-byte value is OK. Op=0, Cmode=1110.
3106 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
3109 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
3113 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
3114 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
3115 if ((SplatBits & ~0xff) == 0) {
3116 // Value = 0x00nn: Op=x, Cmode=100x.
3121 if ((SplatBits & ~0xff00) == 0) {
3122 // Value = 0xnn00: Op=x, Cmode=101x.
3124 Imm = SplatBits >> 8;
3130 // NEON's 32-bit VMOV supports splat values where:
3131 // * only one byte is nonzero, or
3132 // * the least significant byte is 0xff and the second byte is nonzero, or
3133 // * the least significant 2 bytes are 0xff and the third is nonzero.
3134 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
3135 if ((SplatBits & ~0xff) == 0) {
3136 // Value = 0x000000nn: Op=x, Cmode=000x.
3141 if ((SplatBits & ~0xff00) == 0) {
3142 // Value = 0x0000nn00: Op=x, Cmode=001x.
3144 Imm = SplatBits >> 8;
3147 if ((SplatBits & ~0xff0000) == 0) {
3148 // Value = 0x00nn0000: Op=x, Cmode=010x.
3150 Imm = SplatBits >> 16;
3153 if ((SplatBits & ~0xff000000) == 0) {
3154 // Value = 0xnn000000: Op=x, Cmode=011x.
3156 Imm = SplatBits >> 24;
3160 // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC
3161 if (type == OtherModImm) return SDValue();
3163 if ((SplatBits & ~0xffff) == 0 &&
3164 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
3165 // Value = 0x0000nnff: Op=x, Cmode=1100.
3167 Imm = SplatBits >> 8;
3172 if ((SplatBits & ~0xffffff) == 0 &&
3173 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
3174 // Value = 0x00nnffff: Op=x, Cmode=1101.
3176 Imm = SplatBits >> 16;
3177 SplatBits |= 0xffff;
3181 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
3182 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
3183 // VMOV.I32. A (very) minor optimization would be to replicate the value
3184 // and fall through here to test for a valid 64-bit splat. But, then the
3185 // caller would also need to check and handle the change in size.
3189 if (type != VMOVModImm)
3191 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
3192 uint64_t BitMask = 0xff;
3194 unsigned ImmMask = 1;
3196 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
3197 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
3200 } else if ((SplatBits & BitMask) != 0) {
3206 // Op=1, Cmode=1110.
3209 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
3214 llvm_unreachable("unexpected size for isNEONModifiedImm");
3218 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
3219 return DAG.getTargetConstant(EncodedVal, MVT::i32);
3222 static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT,
3223 bool &ReverseVEXT, unsigned &Imm) {
3224 unsigned NumElts = VT.getVectorNumElements();
3225 ReverseVEXT = false;
3227 // Assume that the first shuffle index is not UNDEF. Fail if it is.
3233 // If this is a VEXT shuffle, the immediate value is the index of the first
3234 // element. The other shuffle indices must be the successive elements after
3236 unsigned ExpectedElt = Imm;
3237 for (unsigned i = 1; i < NumElts; ++i) {
3238 // Increment the expected index. If it wraps around, it may still be
3239 // a VEXT but the source vectors must be swapped.
3241 if (ExpectedElt == NumElts * 2) {
3246 if (M[i] < 0) continue; // ignore UNDEF indices
3247 if (ExpectedElt != static_cast<unsigned>(M[i]))
3251 // Adjust the index value if the source operands will be swapped.
3258 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
3259 /// instruction with the specified blocksize. (The order of the elements
3260 /// within each block of the vector is reversed.)
3261 static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT,
3262 unsigned BlockSize) {
3263 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
3264 "Only possible block sizes for VREV are: 16, 32, 64");
3266 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3270 unsigned NumElts = VT.getVectorNumElements();
3271 unsigned BlockElts = M[0] + 1;
3272 // If the first shuffle index is UNDEF, be optimistic.
3274 BlockElts = BlockSize / EltSz;
3276 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
3279 for (unsigned i = 0; i < NumElts; ++i) {
3280 if (M[i] < 0) continue; // ignore UNDEF indices
3281 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
3288 static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT,
3289 unsigned &WhichResult) {
3290 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3294 unsigned NumElts = VT.getVectorNumElements();
3295 WhichResult = (M[0] == 0 ? 0 : 1);
3296 for (unsigned i = 0; i < NumElts; i += 2) {
3297 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3298 (M[i+1] >= 0 && (unsigned) M[i+1] != i + NumElts + WhichResult))
3304 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
3305 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3306 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
3307 static bool isVTRN_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3308 unsigned &WhichResult) {
3309 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3313 unsigned NumElts = VT.getVectorNumElements();
3314 WhichResult = (M[0] == 0 ? 0 : 1);
3315 for (unsigned i = 0; i < NumElts; i += 2) {
3316 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3317 (M[i+1] >= 0 && (unsigned) M[i+1] != i + WhichResult))
3323 static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT,
3324 unsigned &WhichResult) {
3325 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3329 unsigned NumElts = VT.getVectorNumElements();
3330 WhichResult = (M[0] == 0 ? 0 : 1);
3331 for (unsigned i = 0; i != NumElts; ++i) {
3332 if (M[i] < 0) continue; // ignore UNDEF indices
3333 if ((unsigned) M[i] != 2 * i + WhichResult)
3337 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3338 if (VT.is64BitVector() && EltSz == 32)
3344 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
3345 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3346 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
3347 static bool isVUZP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3348 unsigned &WhichResult) {
3349 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3353 unsigned Half = VT.getVectorNumElements() / 2;
3354 WhichResult = (M[0] == 0 ? 0 : 1);
3355 for (unsigned j = 0; j != 2; ++j) {
3356 unsigned Idx = WhichResult;
3357 for (unsigned i = 0; i != Half; ++i) {
3358 int MIdx = M[i + j * Half];
3359 if (MIdx >= 0 && (unsigned) MIdx != Idx)
3365 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3366 if (VT.is64BitVector() && EltSz == 32)
3372 static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT,
3373 unsigned &WhichResult) {
3374 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3378 unsigned NumElts = VT.getVectorNumElements();
3379 WhichResult = (M[0] == 0 ? 0 : 1);
3380 unsigned Idx = WhichResult * NumElts / 2;
3381 for (unsigned i = 0; i != NumElts; i += 2) {
3382 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3383 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts))
3388 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3389 if (VT.is64BitVector() && EltSz == 32)
3395 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
3396 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3397 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
3398 static bool isVZIP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3399 unsigned &WhichResult) {
3400 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3404 unsigned NumElts = VT.getVectorNumElements();
3405 WhichResult = (M[0] == 0 ? 0 : 1);
3406 unsigned Idx = WhichResult * NumElts / 2;
3407 for (unsigned i = 0; i != NumElts; i += 2) {
3408 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3409 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx))
3414 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3415 if (VT.is64BitVector() && EltSz == 32)
3421 // If N is an integer constant that can be moved into a register in one
3422 // instruction, return an SDValue of such a constant (will become a MOV
3423 // instruction). Otherwise return null.
3424 static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG,
3425 const ARMSubtarget *ST, DebugLoc dl) {
3427 if (!isa<ConstantSDNode>(N))
3429 Val = cast<ConstantSDNode>(N)->getZExtValue();
3431 if (ST->isThumb1Only()) {
3432 if (Val <= 255 || ~Val <= 255)
3433 return DAG.getConstant(Val, MVT::i32);
3435 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1)
3436 return DAG.getConstant(Val, MVT::i32);
3441 // If this is a case we can't handle, return null and let the default
3442 // expansion code take care of it.
3443 static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
3444 const ARMSubtarget *ST) {
3445 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
3446 DebugLoc dl = Op.getDebugLoc();
3447 EVT VT = Op.getValueType();
3449 APInt SplatBits, SplatUndef;
3450 unsigned SplatBitSize;
3452 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
3453 if (SplatBitSize <= 64) {
3454 // Check if an immediate VMOV works.
3456 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
3457 SplatUndef.getZExtValue(), SplatBitSize,
3458 DAG, VmovVT, VT.is128BitVector(),
3460 if (Val.getNode()) {
3461 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
3462 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov);
3465 // Try an immediate VMVN.
3466 uint64_t NegatedImm = (SplatBits.getZExtValue() ^
3467 ((1LL << SplatBitSize) - 1));
3468 Val = isNEONModifiedImm(NegatedImm,
3469 SplatUndef.getZExtValue(), SplatBitSize,
3470 DAG, VmovVT, VT.is128BitVector(),
3472 if (Val.getNode()) {
3473 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
3474 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov);
3479 // Scan through the operands to see if only one value is used.
3480 unsigned NumElts = VT.getVectorNumElements();
3481 bool isOnlyLowElement = true;
3482 bool usesOnlyOneValue = true;
3483 bool isConstant = true;
3485 for (unsigned i = 0; i < NumElts; ++i) {
3486 SDValue V = Op.getOperand(i);
3487 if (V.getOpcode() == ISD::UNDEF)
3490 isOnlyLowElement = false;
3491 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
3494 if (!Value.getNode())
3496 else if (V != Value)
3497 usesOnlyOneValue = false;
3500 if (!Value.getNode())
3501 return DAG.getUNDEF(VT);
3503 if (isOnlyLowElement)
3504 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
3506 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3508 // Use VDUP for non-constant splats. For f32 constant splats, reduce to
3509 // i32 and try again.
3510 if (usesOnlyOneValue && EltSize <= 32) {
3512 return DAG.getNode(ARMISD::VDUP, dl, VT, Value);
3513 if (VT.getVectorElementType().isFloatingPoint()) {
3514 SmallVector<SDValue, 8> Ops;
3515 for (unsigned i = 0; i < NumElts; ++i)
3516 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32,
3518 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &Ops[0],
3520 Val = LowerBUILD_VECTOR(Val, DAG, ST);
3522 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val);
3524 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
3526 return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
3529 // If all elements are constants and the case above didn't get hit, fall back
3530 // to the default expansion, which will generate a load from the constant
3535 // Vectors with 32- or 64-bit elements can be built by directly assigning
3536 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
3537 // will be legalized.
3538 if (EltSize >= 32) {
3539 // Do the expansion with floating-point types, since that is what the VFP
3540 // registers are defined to use, and since i64 is not legal.
3541 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3542 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3543 SmallVector<SDValue, 8> Ops;
3544 for (unsigned i = 0; i < NumElts; ++i)
3545 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, EltVT, Op.getOperand(i)));
3546 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
3547 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val);
3553 /// isShuffleMaskLegal - Targets can use this to indicate that they only
3554 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
3555 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
3556 /// are assumed to be legal.
3558 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
3560 if (VT.getVectorNumElements() == 4 &&
3561 (VT.is128BitVector() || VT.is64BitVector())) {
3562 unsigned PFIndexes[4];
3563 for (unsigned i = 0; i != 4; ++i) {
3567 PFIndexes[i] = M[i];
3570 // Compute the index in the perfect shuffle table.
3571 unsigned PFTableIndex =
3572 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3573 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3574 unsigned Cost = (PFEntry >> 30);
3581 unsigned Imm, WhichResult;
3583 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3584 return (EltSize >= 32 ||
3585 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
3586 isVREVMask(M, VT, 64) ||
3587 isVREVMask(M, VT, 32) ||
3588 isVREVMask(M, VT, 16) ||
3589 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
3590 isVTRNMask(M, VT, WhichResult) ||
3591 isVUZPMask(M, VT, WhichResult) ||
3592 isVZIPMask(M, VT, WhichResult) ||
3593 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
3594 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
3595 isVZIP_v_undef_Mask(M, VT, WhichResult));
3598 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
3599 /// the specified operations to build the shuffle.
3600 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
3601 SDValue RHS, SelectionDAG &DAG,
3603 unsigned OpNum = (PFEntry >> 26) & 0x0F;
3604 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
3605 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
3608 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
3617 OP_VUZPL, // VUZP, left result
3618 OP_VUZPR, // VUZP, right result
3619 OP_VZIPL, // VZIP, left result
3620 OP_VZIPR, // VZIP, right result
3621 OP_VTRNL, // VTRN, left result
3622 OP_VTRNR // VTRN, right result
3625 if (OpNum == OP_COPY) {
3626 if (LHSID == (1*9+2)*9+3) return LHS;
3627 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
3631 SDValue OpLHS, OpRHS;
3632 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
3633 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
3634 EVT VT = OpLHS.getValueType();
3637 default: llvm_unreachable("Unknown shuffle opcode!");
3639 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
3644 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
3645 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
3649 return DAG.getNode(ARMISD::VEXT, dl, VT,
3651 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
3654 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3655 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
3658 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3659 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
3662 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3663 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
3667 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
3668 SDValue V1 = Op.getOperand(0);
3669 SDValue V2 = Op.getOperand(1);
3670 DebugLoc dl = Op.getDebugLoc();
3671 EVT VT = Op.getValueType();
3672 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
3673 SmallVector<int, 8> ShuffleMask;
3675 // Convert shuffles that are directly supported on NEON to target-specific
3676 // DAG nodes, instead of keeping them as shuffles and matching them again
3677 // during code selection. This is more efficient and avoids the possibility
3678 // of inconsistencies between legalization and selection.
3679 // FIXME: floating-point vectors should be canonicalized to integer vectors
3680 // of the same time so that they get CSEd properly.
3681 SVN->getMask(ShuffleMask);
3683 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3684 if (EltSize <= 32) {
3685 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
3686 int Lane = SVN->getSplatIndex();
3687 // If this is undef splat, generate it via "just" vdup, if possible.
3688 if (Lane == -1) Lane = 0;
3690 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
3691 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
3693 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
3694 DAG.getConstant(Lane, MVT::i32));
3699 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
3702 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
3703 DAG.getConstant(Imm, MVT::i32));
3706 if (isVREVMask(ShuffleMask, VT, 64))
3707 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
3708 if (isVREVMask(ShuffleMask, VT, 32))
3709 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
3710 if (isVREVMask(ShuffleMask, VT, 16))
3711 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
3713 // Check for Neon shuffles that modify both input vectors in place.
3714 // If both results are used, i.e., if there are two shuffles with the same
3715 // source operands and with masks corresponding to both results of one of
3716 // these operations, DAG memoization will ensure that a single node is
3717 // used for both shuffles.
3718 unsigned WhichResult;
3719 if (isVTRNMask(ShuffleMask, VT, WhichResult))
3720 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3721 V1, V2).getValue(WhichResult);
3722 if (isVUZPMask(ShuffleMask, VT, WhichResult))
3723 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3724 V1, V2).getValue(WhichResult);
3725 if (isVZIPMask(ShuffleMask, VT, WhichResult))
3726 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3727 V1, V2).getValue(WhichResult);
3729 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
3730 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3731 V1, V1).getValue(WhichResult);
3732 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
3733 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3734 V1, V1).getValue(WhichResult);
3735 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
3736 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3737 V1, V1).getValue(WhichResult);
3740 // If the shuffle is not directly supported and it has 4 elements, use
3741 // the PerfectShuffle-generated table to synthesize it from other shuffles.
3742 unsigned NumElts = VT.getVectorNumElements();
3744 unsigned PFIndexes[4];
3745 for (unsigned i = 0; i != 4; ++i) {
3746 if (ShuffleMask[i] < 0)
3749 PFIndexes[i] = ShuffleMask[i];
3752 // Compute the index in the perfect shuffle table.
3753 unsigned PFTableIndex =
3754 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3755 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3756 unsigned Cost = (PFEntry >> 30);
3759 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
3762 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
3763 if (EltSize >= 32) {
3764 // Do the expansion with floating-point types, since that is what the VFP
3765 // registers are defined to use, and since i64 is not legal.
3766 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3767 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3768 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, V1);
3769 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, V2);
3770 SmallVector<SDValue, 8> Ops;
3771 for (unsigned i = 0; i < NumElts; ++i) {
3772 if (ShuffleMask[i] < 0)
3773 Ops.push_back(DAG.getUNDEF(EltVT));
3775 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3776 ShuffleMask[i] < (int)NumElts ? V1 : V2,
3777 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
3780 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
3781 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val);
3787 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
3788 // EXTRACT_VECTOR_ELT is legal only for immediate indexes.
3789 SDValue Lane = Op.getOperand(1);
3790 if (!isa<ConstantSDNode>(Lane))
3793 SDValue Vec = Op.getOperand(0);
3794 if (Op.getValueType() == MVT::i32 &&
3795 Vec.getValueType().getVectorElementType().getSizeInBits() < 32) {
3796 DebugLoc dl = Op.getDebugLoc();
3797 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
3803 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
3804 // The only time a CONCAT_VECTORS operation can have legal types is when
3805 // two 64-bit vectors are concatenated to a 128-bit vector.
3806 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
3807 "unexpected CONCAT_VECTORS");
3808 DebugLoc dl = Op.getDebugLoc();
3809 SDValue Val = DAG.getUNDEF(MVT::v2f64);
3810 SDValue Op0 = Op.getOperand(0);
3811 SDValue Op1 = Op.getOperand(1);
3812 if (Op0.getOpcode() != ISD::UNDEF)
3813 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
3814 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op0),
3815 DAG.getIntPtrConstant(0));
3816 if (Op1.getOpcode() != ISD::UNDEF)
3817 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
3818 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op1),
3819 DAG.getIntPtrConstant(1));
3820 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Val);
3823 /// SkipExtension - For a node that is either a SIGN_EXTEND, ZERO_EXTEND, or
3824 /// an extending load, return the unextended value.
3825 static SDValue SkipExtension(SDNode *N, SelectionDAG &DAG) {
3826 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
3827 return N->getOperand(0);
3828 LoadSDNode *LD = cast<LoadSDNode>(N);
3829 return DAG.getLoad(LD->getMemoryVT(), N->getDebugLoc(), LD->getChain(),
3830 LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(),
3831 LD->isNonTemporal(), LD->getAlignment());
3834 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
3835 // Multiplications are only custom-lowered for 128-bit vectors so that
3836 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
3837 EVT VT = Op.getValueType();
3838 assert(VT.is128BitVector() && "unexpected type for custom-lowering ISD::MUL");
3839 SDNode *N0 = Op.getOperand(0).getNode();
3840 SDNode *N1 = Op.getOperand(1).getNode();
3841 unsigned NewOpc = 0;
3842 if ((N0->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N0)) &&
3843 (N1->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N1))) {
3844 NewOpc = ARMISD::VMULLs;
3845 } else if ((N0->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N0)) &&
3846 (N1->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N1))) {
3847 NewOpc = ARMISD::VMULLu;
3848 } else if (VT == MVT::v2i64) {
3849 // Fall through to expand this. It is not legal.
3852 // Other vector multiplications are legal.
3856 // Legalize to a VMULL instruction.
3857 DebugLoc DL = Op.getDebugLoc();
3858 SDValue Op0 = SkipExtension(N0, DAG);
3859 SDValue Op1 = SkipExtension(N1, DAG);
3861 assert(Op0.getValueType().is64BitVector() &&
3862 Op1.getValueType().is64BitVector() &&
3863 "unexpected types for extended operands to VMULL");
3864 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
3867 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
3868 switch (Op.getOpcode()) {
3869 default: llvm_unreachable("Don't know how to custom lower this!");
3870 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3871 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
3872 case ISD::GlobalAddress:
3873 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
3874 LowerGlobalAddressELF(Op, DAG);
3875 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
3876 case ISD::SELECT: return LowerSELECT(Op, DAG);
3877 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
3878 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
3879 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
3880 case ISD::VASTART: return LowerVASTART(Op, DAG);
3881 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget);
3882 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget);
3883 case ISD::SINT_TO_FP:
3884 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
3885 case ISD::FP_TO_SINT:
3886 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
3887 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
3888 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
3889 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
3890 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
3891 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
3892 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
3893 case ISD::EH_SJLJ_DISPATCHSETUP: return LowerEH_SJLJ_DISPATCHSETUP(Op, DAG);
3894 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
3896 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(Op.getNode(), DAG);
3899 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
3900 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
3901 case ISD::SRL_PARTS:
3902 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
3903 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
3904 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
3905 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
3906 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
3907 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
3908 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
3909 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
3910 case ISD::MUL: return LowerMUL(Op, DAG);
3915 /// ReplaceNodeResults - Replace the results of node with an illegal result
3916 /// type with new values built out of custom code.
3917 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
3918 SmallVectorImpl<SDValue>&Results,
3919 SelectionDAG &DAG) const {
3921 switch (N->getOpcode()) {
3923 llvm_unreachable("Don't know how to custom expand this!");
3925 case ISD::BIT_CONVERT:
3926 Res = ExpandBIT_CONVERT(N, DAG);
3930 Res = LowerShift(N, DAG, Subtarget);
3934 Results.push_back(Res);
3937 //===----------------------------------------------------------------------===//
3938 // ARM Scheduler Hooks
3939 //===----------------------------------------------------------------------===//
3942 ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
3943 MachineBasicBlock *BB,
3944 unsigned Size) const {
3945 unsigned dest = MI->getOperand(0).getReg();
3946 unsigned ptr = MI->getOperand(1).getReg();
3947 unsigned oldval = MI->getOperand(2).getReg();
3948 unsigned newval = MI->getOperand(3).getReg();
3949 unsigned scratch = BB->getParent()->getRegInfo()
3950 .createVirtualRegister(ARM::GPRRegisterClass);
3951 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3952 DebugLoc dl = MI->getDebugLoc();
3953 bool isThumb2 = Subtarget->isThumb2();
3955 unsigned ldrOpc, strOpc;
3957 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
3959 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
3960 strOpc = isThumb2 ? ARM::t2LDREXB : ARM::STREXB;
3963 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
3964 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
3967 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
3968 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
3972 MachineFunction *MF = BB->getParent();
3973 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3974 MachineFunction::iterator It = BB;
3975 ++It; // insert the new blocks after the current block
3977 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
3978 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
3979 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3980 MF->insert(It, loop1MBB);
3981 MF->insert(It, loop2MBB);
3982 MF->insert(It, exitMBB);
3984 // Transfer the remainder of BB and its successor edges to exitMBB.
3985 exitMBB->splice(exitMBB->begin(), BB,
3986 llvm::next(MachineBasicBlock::iterator(MI)),
3988 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
3992 // fallthrough --> loop1MBB
3993 BB->addSuccessor(loop1MBB);
3996 // ldrex dest, [ptr]
4000 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
4001 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
4002 .addReg(dest).addReg(oldval));
4003 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4004 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
4005 BB->addSuccessor(loop2MBB);
4006 BB->addSuccessor(exitMBB);
4009 // strex scratch, newval, [ptr]
4013 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval)
4015 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4016 .addReg(scratch).addImm(0));
4017 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4018 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
4019 BB->addSuccessor(loop1MBB);
4020 BB->addSuccessor(exitMBB);
4026 MI->eraseFromParent(); // The instruction is gone now.
4032 ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
4033 unsigned Size, unsigned BinOpcode) const {
4034 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4035 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4037 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4038 MachineFunction *MF = BB->getParent();
4039 MachineFunction::iterator It = BB;
4042 unsigned dest = MI->getOperand(0).getReg();
4043 unsigned ptr = MI->getOperand(1).getReg();
4044 unsigned incr = MI->getOperand(2).getReg();
4045 DebugLoc dl = MI->getDebugLoc();
4047 bool isThumb2 = Subtarget->isThumb2();
4048 unsigned ldrOpc, strOpc;
4050 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
4052 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
4053 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
4056 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
4057 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
4060 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
4061 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
4065 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
4066 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
4067 MF->insert(It, loopMBB);
4068 MF->insert(It, exitMBB);
4070 // Transfer the remainder of BB and its successor edges to exitMBB.
4071 exitMBB->splice(exitMBB->begin(), BB,
4072 llvm::next(MachineBasicBlock::iterator(MI)),
4074 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4076 MachineRegisterInfo &RegInfo = MF->getRegInfo();
4077 unsigned scratch = RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
4078 unsigned scratch2 = (!BinOpcode) ? incr :
4079 RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
4083 // fallthrough --> loopMBB
4084 BB->addSuccessor(loopMBB);
4088 // <binop> scratch2, dest, incr
4089 // strex scratch, scratch2, ptr
4092 // fallthrough --> exitMBB
4094 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
4096 // operand order needs to go the other way for NAND
4097 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr)
4098 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
4099 addReg(incr).addReg(dest)).addReg(0);
4101 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
4102 addReg(dest).addReg(incr)).addReg(0);
4105 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2)
4107 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4108 .addReg(scratch).addImm(0));
4109 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4110 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
4112 BB->addSuccessor(loopMBB);
4113 BB->addSuccessor(exitMBB);
4119 MI->eraseFromParent(); // The instruction is gone now.
4125 MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
4126 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
4127 E = MBB->succ_end(); I != E; ++I)
4130 llvm_unreachable("Expecting a BB with two successors!");
4134 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4135 MachineBasicBlock *BB) const {
4136 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4137 DebugLoc dl = MI->getDebugLoc();
4138 bool isThumb2 = Subtarget->isThumb2();
4139 switch (MI->getOpcode()) {
4142 llvm_unreachable("Unexpected instr type to insert");
4144 case ARM::ATOMIC_LOAD_ADD_I8:
4145 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
4146 case ARM::ATOMIC_LOAD_ADD_I16:
4147 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
4148 case ARM::ATOMIC_LOAD_ADD_I32:
4149 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
4151 case ARM::ATOMIC_LOAD_AND_I8:
4152 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
4153 case ARM::ATOMIC_LOAD_AND_I16:
4154 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
4155 case ARM::ATOMIC_LOAD_AND_I32:
4156 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
4158 case ARM::ATOMIC_LOAD_OR_I8:
4159 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
4160 case ARM::ATOMIC_LOAD_OR_I16:
4161 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
4162 case ARM::ATOMIC_LOAD_OR_I32:
4163 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
4165 case ARM::ATOMIC_LOAD_XOR_I8:
4166 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
4167 case ARM::ATOMIC_LOAD_XOR_I16:
4168 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
4169 case ARM::ATOMIC_LOAD_XOR_I32:
4170 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
4172 case ARM::ATOMIC_LOAD_NAND_I8:
4173 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
4174 case ARM::ATOMIC_LOAD_NAND_I16:
4175 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
4176 case ARM::ATOMIC_LOAD_NAND_I32:
4177 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
4179 case ARM::ATOMIC_LOAD_SUB_I8:
4180 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
4181 case ARM::ATOMIC_LOAD_SUB_I16:
4182 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
4183 case ARM::ATOMIC_LOAD_SUB_I32:
4184 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
4186 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0);
4187 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0);
4188 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0);
4190 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1);
4191 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
4192 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
4194 case ARM::tMOVCCr_pseudo: {
4195 // To "insert" a SELECT_CC instruction, we actually have to insert the
4196 // diamond control-flow pattern. The incoming instruction knows the
4197 // destination vreg to set, the condition code register to branch on, the
4198 // true/false values to select between, and a branch opcode to use.
4199 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4200 MachineFunction::iterator It = BB;
4206 // cmpTY ccX, r1, r2
4208 // fallthrough --> copy0MBB
4209 MachineBasicBlock *thisMBB = BB;
4210 MachineFunction *F = BB->getParent();
4211 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4212 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
4213 F->insert(It, copy0MBB);
4214 F->insert(It, sinkMBB);
4216 // Transfer the remainder of BB and its successor edges to sinkMBB.
4217 sinkMBB->splice(sinkMBB->begin(), BB,
4218 llvm::next(MachineBasicBlock::iterator(MI)),
4220 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
4222 BB->addSuccessor(copy0MBB);
4223 BB->addSuccessor(sinkMBB);
4225 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
4226 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
4229 // %FalseValue = ...
4230 // # fallthrough to sinkMBB
4233 // Update machine-CFG edges
4234 BB->addSuccessor(sinkMBB);
4237 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
4240 BuildMI(*BB, BB->begin(), dl,
4241 TII->get(ARM::PHI), MI->getOperand(0).getReg())
4242 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
4243 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
4245 MI->eraseFromParent(); // The pseudo instruction is gone now.
4250 case ARM::BCCZi64: {
4251 // Compare both parts that make up the double comparison separately for
4253 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
4255 unsigned LHS1 = MI->getOperand(1).getReg();
4256 unsigned LHS2 = MI->getOperand(2).getReg();
4258 AddDefaultPred(BuildMI(BB, dl,
4259 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4260 .addReg(LHS1).addImm(0));
4261 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4262 .addReg(LHS2).addImm(0)
4263 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
4265 unsigned RHS1 = MI->getOperand(3).getReg();
4266 unsigned RHS2 = MI->getOperand(4).getReg();
4267 AddDefaultPred(BuildMI(BB, dl,
4268 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
4269 .addReg(LHS1).addReg(RHS1));
4270 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
4271 .addReg(LHS2).addReg(RHS2)
4272 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
4275 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB();
4276 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
4277 if (MI->getOperand(0).getImm() == ARMCC::NE)
4278 std::swap(destMBB, exitMBB);
4280 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4281 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
4282 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2B : ARM::B))
4285 MI->eraseFromParent(); // The pseudo instruction is gone now.
4291 //===----------------------------------------------------------------------===//
4292 // ARM Optimization Hooks
4293 //===----------------------------------------------------------------------===//
4296 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
4297 TargetLowering::DAGCombinerInfo &DCI) {
4298 SelectionDAG &DAG = DCI.DAG;
4299 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4300 EVT VT = N->getValueType(0);
4301 unsigned Opc = N->getOpcode();
4302 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
4303 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
4304 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
4305 ISD::CondCode CC = ISD::SETCC_INVALID;
4308 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
4310 SDValue CCOp = Slct.getOperand(0);
4311 if (CCOp.getOpcode() == ISD::SETCC)
4312 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
4315 bool DoXform = false;
4317 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
4320 if (LHS.getOpcode() == ISD::Constant &&
4321 cast<ConstantSDNode>(LHS)->isNullValue()) {
4323 } else if (CC != ISD::SETCC_INVALID &&
4324 RHS.getOpcode() == ISD::Constant &&
4325 cast<ConstantSDNode>(RHS)->isNullValue()) {
4326 std::swap(LHS, RHS);
4327 SDValue Op0 = Slct.getOperand(0);
4328 EVT OpVT = isSlctCC ? Op0.getValueType() :
4329 Op0.getOperand(0).getValueType();
4330 bool isInt = OpVT.isInteger();
4331 CC = ISD::getSetCCInverse(CC, isInt);
4333 if (!TLI.isCondCodeLegal(CC, OpVT))
4334 return SDValue(); // Inverse operator isn't legal.
4341 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
4343 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
4344 Slct.getOperand(0), Slct.getOperand(1), CC);
4345 SDValue CCOp = Slct.getOperand(0);
4347 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
4348 CCOp.getOperand(0), CCOp.getOperand(1), CC);
4349 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
4350 CCOp, OtherOp, Result);
4355 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
4356 /// operands N0 and N1. This is a helper for PerformADDCombine that is
4357 /// called with the default operands, and if that fails, with commuted
4359 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
4360 TargetLowering::DAGCombinerInfo &DCI) {
4361 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
4362 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
4363 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
4364 if (Result.getNode()) return Result;
4369 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
4371 static SDValue PerformADDCombine(SDNode *N,
4372 TargetLowering::DAGCombinerInfo &DCI) {
4373 SDValue N0 = N->getOperand(0);
4374 SDValue N1 = N->getOperand(1);
4376 // First try with the default operand order.
4377 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI);
4378 if (Result.getNode())
4381 // If that didn't work, try again with the operands commuted.
4382 return PerformADDCombineWithOperands(N, N1, N0, DCI);
4385 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
4387 static SDValue PerformSUBCombine(SDNode *N,
4388 TargetLowering::DAGCombinerInfo &DCI) {
4389 SDValue N0 = N->getOperand(0);
4390 SDValue N1 = N->getOperand(1);
4392 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
4393 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
4394 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
4395 if (Result.getNode()) return Result;
4401 static SDValue PerformMULCombine(SDNode *N,
4402 TargetLowering::DAGCombinerInfo &DCI,
4403 const ARMSubtarget *Subtarget) {
4404 SelectionDAG &DAG = DCI.DAG;
4406 if (Subtarget->isThumb1Only())
4409 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
4412 EVT VT = N->getValueType(0);
4416 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
4420 uint64_t MulAmt = C->getZExtValue();
4421 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt);
4422 ShiftAmt = ShiftAmt & (32 - 1);
4423 SDValue V = N->getOperand(0);
4424 DebugLoc DL = N->getDebugLoc();
4427 MulAmt >>= ShiftAmt;
4428 if (isPowerOf2_32(MulAmt - 1)) {
4429 // (mul x, 2^N + 1) => (add (shl x, N), x)
4430 Res = DAG.getNode(ISD::ADD, DL, VT,
4431 V, DAG.getNode(ISD::SHL, DL, VT,
4432 V, DAG.getConstant(Log2_32(MulAmt-1),
4434 } else if (isPowerOf2_32(MulAmt + 1)) {
4435 // (mul x, 2^N - 1) => (sub (shl x, N), x)
4436 Res = DAG.getNode(ISD::SUB, DL, VT,
4437 DAG.getNode(ISD::SHL, DL, VT,
4438 V, DAG.getConstant(Log2_32(MulAmt+1),
4445 Res = DAG.getNode(ISD::SHL, DL, VT, Res,
4446 DAG.getConstant(ShiftAmt, MVT::i32));
4448 // Do not add new nodes to DAG combiner worklist.
4449 DCI.CombineTo(N, Res, false);
4453 static SDValue PerformANDCombine(SDNode *N,
4454 TargetLowering::DAGCombinerInfo &DCI) {
4455 // Attempt to use immediate-form VBIC
4456 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
4457 DebugLoc dl = N->getDebugLoc();
4458 EVT VT = N->getValueType(0);
4459 SelectionDAG &DAG = DCI.DAG;
4461 APInt SplatBits, SplatUndef;
4462 unsigned SplatBitSize;
4465 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
4466 if (SplatBitSize <= 64) {
4468 SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(),
4469 SplatUndef.getZExtValue(), SplatBitSize,
4470 DAG, VbicVT, VT.is128BitVector(),
4472 if (Val.getNode()) {
4474 DAG.getNode(ISD::BIT_CONVERT, dl, VbicVT, N->getOperand(0));
4475 SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val);
4476 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vbic);
4484 /// PerformORCombine - Target-specific dag combine xforms for ISD::OR
4485 static SDValue PerformORCombine(SDNode *N,
4486 TargetLowering::DAGCombinerInfo &DCI,
4487 const ARMSubtarget *Subtarget) {
4488 // Attempt to use immediate-form VORR
4489 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
4490 DebugLoc dl = N->getDebugLoc();
4491 EVT VT = N->getValueType(0);
4492 SelectionDAG &DAG = DCI.DAG;
4494 APInt SplatBits, SplatUndef;
4495 unsigned SplatBitSize;
4497 if (BVN && Subtarget->hasNEON() &&
4498 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
4499 if (SplatBitSize <= 64) {
4501 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
4502 SplatUndef.getZExtValue(), SplatBitSize,
4503 DAG, VorrVT, VT.is128BitVector(),
4505 if (Val.getNode()) {
4507 DAG.getNode(ISD::BIT_CONVERT, dl, VorrVT, N->getOperand(0));
4508 SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val);
4509 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vorr);
4514 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when
4517 // BFI is only available on V6T2+
4518 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops())
4521 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
4522 DebugLoc DL = N->getDebugLoc();
4523 // 1) or (and A, mask), val => ARMbfi A, val, mask
4524 // iff (val & mask) == val
4526 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
4527 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2)
4528 // && CountPopulation_32(mask) == CountPopulation_32(~mask2)
4529 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2)
4530 // && CountPopulation_32(mask) == CountPopulation_32(~mask2)
4531 // (i.e., copy a bitfield value into another bitfield of the same width)
4532 if (N0.getOpcode() != ISD::AND)
4539 // The value and the mask need to be constants so we can verify this is
4540 // actually a bitfield set. If the mask is 0xffff, we can do better
4541 // via a movt instruction, so don't use BFI in that case.
4542 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
4545 unsigned Mask = C->getZExtValue();
4549 // Case (1): or (and A, mask), val => ARMbfi A, val, mask
4550 if ((C = dyn_cast<ConstantSDNode>(N1))) {
4551 unsigned Val = C->getZExtValue();
4552 if (!ARM::isBitFieldInvertedMask(Mask) || (Val & ~Mask) != Val)
4554 Val >>= CountTrailingZeros_32(~Mask);
4556 Res = DAG.getNode(ARMISD::BFI, DL, VT, N0.getOperand(0),
4557 DAG.getConstant(Val, MVT::i32),
4558 DAG.getConstant(Mask, MVT::i32));
4560 // Do not add new nodes to DAG combiner worklist.
4561 DCI.CombineTo(N, Res, false);
4562 } else if (N1.getOpcode() == ISD::AND) {
4563 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
4564 C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
4567 unsigned Mask2 = C->getZExtValue();
4569 if (ARM::isBitFieldInvertedMask(Mask) &&
4570 ARM::isBitFieldInvertedMask(~Mask2) &&
4571 (CountPopulation_32(Mask) == CountPopulation_32(~Mask2))) {
4572 // The pack halfword instruction works better for masks that fit it,
4573 // so use that when it's available.
4574 if (Subtarget->hasT2ExtractPack() &&
4575 (Mask == 0xffff || Mask == 0xffff0000))
4578 unsigned lsb = CountTrailingZeros_32(Mask2);
4579 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
4580 DAG.getConstant(lsb, MVT::i32));
4581 Res = DAG.getNode(ARMISD::BFI, DL, VT, N0.getOperand(0), Res,
4582 DAG.getConstant(Mask, MVT::i32));
4583 // Do not add new nodes to DAG combiner worklist.
4584 DCI.CombineTo(N, Res, false);
4585 } else if (ARM::isBitFieldInvertedMask(~Mask) &&
4586 ARM::isBitFieldInvertedMask(Mask2) &&
4587 (CountPopulation_32(~Mask) == CountPopulation_32(Mask2))) {
4588 // The pack halfword instruction works better for masks that fit it,
4589 // so use that when it's available.
4590 if (Subtarget->hasT2ExtractPack() &&
4591 (Mask2 == 0xffff || Mask2 == 0xffff0000))
4594 unsigned lsb = CountTrailingZeros_32(Mask);
4595 Res = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0),
4596 DAG.getConstant(lsb, MVT::i32));
4597 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
4598 DAG.getConstant(Mask2, MVT::i32));
4599 // Do not add new nodes to DAG combiner worklist.
4600 DCI.CombineTo(N, Res, false);
4607 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
4608 /// ARMISD::VMOVRRD.
4609 static SDValue PerformVMOVRRDCombine(SDNode *N,
4610 TargetLowering::DAGCombinerInfo &DCI) {
4611 // vmovrrd(vmovdrr x, y) -> x,y
4612 SDValue InDouble = N->getOperand(0);
4613 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
4614 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
4618 /// PerformVMOVDRRCombine - Target-specific dag combine xforms for
4619 /// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands.
4620 static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) {
4621 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X)
4622 SDValue Op0 = N->getOperand(0);
4623 SDValue Op1 = N->getOperand(1);
4624 if (Op0.getOpcode() == ISD::BIT_CONVERT)
4625 Op0 = Op0.getOperand(0);
4626 if (Op1.getOpcode() == ISD::BIT_CONVERT)
4627 Op1 = Op1.getOperand(0);
4628 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
4629 Op0.getNode() == Op1.getNode() &&
4630 Op0.getResNo() == 0 && Op1.getResNo() == 1)
4631 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
4632 N->getValueType(0), Op0.getOperand(0));
4636 /// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for
4637 /// ISD::BUILD_VECTOR.
4638 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG) {
4639 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X):
4640 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value
4641 // into a pair of GPRs, which is fine when the value is used as a scalar,
4642 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD.
4643 if (N->getNumOperands() == 2)
4644 return PerformVMOVDRRCombine(N, DAG);
4649 /// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for
4650 /// ISD::VECTOR_SHUFFLE.
4651 static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) {
4652 // The LLVM shufflevector instruction does not require the shuffle mask
4653 // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does
4654 // have that requirement. When translating to ISD::VECTOR_SHUFFLE, if the
4655 // operands do not match the mask length, they are extended by concatenating
4656 // them with undef vectors. That is probably the right thing for other
4657 // targets, but for NEON it is better to concatenate two double-register
4658 // size vector operands into a single quad-register size vector. Do that
4659 // transformation here:
4660 // shuffle(concat(v1, undef), concat(v2, undef)) ->
4661 // shuffle(concat(v1, v2), undef)
4662 SDValue Op0 = N->getOperand(0);
4663 SDValue Op1 = N->getOperand(1);
4664 if (Op0.getOpcode() != ISD::CONCAT_VECTORS ||
4665 Op1.getOpcode() != ISD::CONCAT_VECTORS ||
4666 Op0.getNumOperands() != 2 ||
4667 Op1.getNumOperands() != 2)
4669 SDValue Concat0Op1 = Op0.getOperand(1);
4670 SDValue Concat1Op1 = Op1.getOperand(1);
4671 if (Concat0Op1.getOpcode() != ISD::UNDEF ||
4672 Concat1Op1.getOpcode() != ISD::UNDEF)
4674 // Skip the transformation if any of the types are illegal.
4675 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4676 EVT VT = N->getValueType(0);
4677 if (!TLI.isTypeLegal(VT) ||
4678 !TLI.isTypeLegal(Concat0Op1.getValueType()) ||
4679 !TLI.isTypeLegal(Concat1Op1.getValueType()))
4682 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT,
4683 Op0.getOperand(0), Op1.getOperand(0));
4684 // Translate the shuffle mask.
4685 SmallVector<int, 16> NewMask;
4686 unsigned NumElts = VT.getVectorNumElements();
4687 unsigned HalfElts = NumElts/2;
4688 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
4689 for (unsigned n = 0; n < NumElts; ++n) {
4690 int MaskElt = SVN->getMaskElt(n);
4692 if (MaskElt < (int)HalfElts)
4694 else if (MaskElt >= (int)NumElts && MaskElt < (int)(NumElts + HalfElts))
4695 NewElt = HalfElts + MaskElt - NumElts;
4696 NewMask.push_back(NewElt);
4698 return DAG.getVectorShuffle(VT, N->getDebugLoc(), NewConcat,
4699 DAG.getUNDEF(VT), NewMask.data());
4702 /// PerformVDUPLANECombine - Target-specific dag combine xforms for
4703 /// ARMISD::VDUPLANE.
4704 static SDValue PerformVDUPLANECombine(SDNode *N, SelectionDAG &DAG) {
4705 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
4707 SDValue Op = N->getOperand(0);
4708 EVT VT = N->getValueType(0);
4710 // Ignore bit_converts.
4711 while (Op.getOpcode() == ISD::BIT_CONVERT)
4712 Op = Op.getOperand(0);
4713 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
4716 // Make sure the VMOV element size is not bigger than the VDUPLANE elements.
4717 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits();
4718 // The canonical VMOV for a zero vector uses a 32-bit element size.
4719 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4721 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
4723 if (EltSize > VT.getVectorElementType().getSizeInBits())
4726 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
4729 /// getVShiftImm - Check if this is a valid build_vector for the immediate
4730 /// operand of a vector shift operation, where all the elements of the
4731 /// build_vector must have the same constant integer value.
4732 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
4733 // Ignore bit_converts.
4734 while (Op.getOpcode() == ISD::BIT_CONVERT)
4735 Op = Op.getOperand(0);
4736 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
4737 APInt SplatBits, SplatUndef;
4738 unsigned SplatBitSize;
4740 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
4741 HasAnyUndefs, ElementBits) ||
4742 SplatBitSize > ElementBits)
4744 Cnt = SplatBits.getSExtValue();
4748 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
4749 /// operand of a vector shift left operation. That value must be in the range:
4750 /// 0 <= Value < ElementBits for a left shift; or
4751 /// 0 <= Value <= ElementBits for a long left shift.
4752 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
4753 assert(VT.isVector() && "vector shift count is not a vector type");
4754 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
4755 if (! getVShiftImm(Op, ElementBits, Cnt))
4757 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
4760 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
4761 /// operand of a vector shift right operation. For a shift opcode, the value
4762 /// is positive, but for an intrinsic the value count must be negative. The
4763 /// absolute value must be in the range:
4764 /// 1 <= |Value| <= ElementBits for a right shift; or
4765 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
4766 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
4768 assert(VT.isVector() && "vector shift count is not a vector type");
4769 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
4770 if (! getVShiftImm(Op, ElementBits, Cnt))
4774 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
4777 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
4778 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
4779 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
4782 // Don't do anything for most intrinsics.
4785 // Vector shifts: check for immediate versions and lower them.
4786 // Note: This is done during DAG combining instead of DAG legalizing because
4787 // the build_vectors for 64-bit vector element shift counts are generally
4788 // not legal, and it is hard to see their values after they get legalized to
4789 // loads from a constant pool.
4790 case Intrinsic::arm_neon_vshifts:
4791 case Intrinsic::arm_neon_vshiftu:
4792 case Intrinsic::arm_neon_vshiftls:
4793 case Intrinsic::arm_neon_vshiftlu:
4794 case Intrinsic::arm_neon_vshiftn:
4795 case Intrinsic::arm_neon_vrshifts:
4796 case Intrinsic::arm_neon_vrshiftu:
4797 case Intrinsic::arm_neon_vrshiftn:
4798 case Intrinsic::arm_neon_vqshifts:
4799 case Intrinsic::arm_neon_vqshiftu:
4800 case Intrinsic::arm_neon_vqshiftsu:
4801 case Intrinsic::arm_neon_vqshiftns:
4802 case Intrinsic::arm_neon_vqshiftnu:
4803 case Intrinsic::arm_neon_vqshiftnsu:
4804 case Intrinsic::arm_neon_vqrshiftns:
4805 case Intrinsic::arm_neon_vqrshiftnu:
4806 case Intrinsic::arm_neon_vqrshiftnsu: {
4807 EVT VT = N->getOperand(1).getValueType();
4809 unsigned VShiftOpc = 0;
4812 case Intrinsic::arm_neon_vshifts:
4813 case Intrinsic::arm_neon_vshiftu:
4814 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
4815 VShiftOpc = ARMISD::VSHL;
4818 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
4819 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
4820 ARMISD::VSHRs : ARMISD::VSHRu);
4825 case Intrinsic::arm_neon_vshiftls:
4826 case Intrinsic::arm_neon_vshiftlu:
4827 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
4829 llvm_unreachable("invalid shift count for vshll intrinsic");
4831 case Intrinsic::arm_neon_vrshifts:
4832 case Intrinsic::arm_neon_vrshiftu:
4833 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
4837 case Intrinsic::arm_neon_vqshifts:
4838 case Intrinsic::arm_neon_vqshiftu:
4839 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
4843 case Intrinsic::arm_neon_vqshiftsu:
4844 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
4846 llvm_unreachable("invalid shift count for vqshlu intrinsic");
4848 case Intrinsic::arm_neon_vshiftn:
4849 case Intrinsic::arm_neon_vrshiftn:
4850 case Intrinsic::arm_neon_vqshiftns:
4851 case Intrinsic::arm_neon_vqshiftnu:
4852 case Intrinsic::arm_neon_vqshiftnsu:
4853 case Intrinsic::arm_neon_vqrshiftns:
4854 case Intrinsic::arm_neon_vqrshiftnu:
4855 case Intrinsic::arm_neon_vqrshiftnsu:
4856 // Narrowing shifts require an immediate right shift.
4857 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
4859 llvm_unreachable("invalid shift count for narrowing vector shift "
4863 llvm_unreachable("unhandled vector shift");
4867 case Intrinsic::arm_neon_vshifts:
4868 case Intrinsic::arm_neon_vshiftu:
4869 // Opcode already set above.
4871 case Intrinsic::arm_neon_vshiftls:
4872 case Intrinsic::arm_neon_vshiftlu:
4873 if (Cnt == VT.getVectorElementType().getSizeInBits())
4874 VShiftOpc = ARMISD::VSHLLi;
4876 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
4877 ARMISD::VSHLLs : ARMISD::VSHLLu);
4879 case Intrinsic::arm_neon_vshiftn:
4880 VShiftOpc = ARMISD::VSHRN; break;
4881 case Intrinsic::arm_neon_vrshifts:
4882 VShiftOpc = ARMISD::VRSHRs; break;
4883 case Intrinsic::arm_neon_vrshiftu:
4884 VShiftOpc = ARMISD::VRSHRu; break;
4885 case Intrinsic::arm_neon_vrshiftn:
4886 VShiftOpc = ARMISD::VRSHRN; break;
4887 case Intrinsic::arm_neon_vqshifts:
4888 VShiftOpc = ARMISD::VQSHLs; break;
4889 case Intrinsic::arm_neon_vqshiftu:
4890 VShiftOpc = ARMISD::VQSHLu; break;
4891 case Intrinsic::arm_neon_vqshiftsu:
4892 VShiftOpc = ARMISD::VQSHLsu; break;
4893 case Intrinsic::arm_neon_vqshiftns:
4894 VShiftOpc = ARMISD::VQSHRNs; break;
4895 case Intrinsic::arm_neon_vqshiftnu:
4896 VShiftOpc = ARMISD::VQSHRNu; break;
4897 case Intrinsic::arm_neon_vqshiftnsu:
4898 VShiftOpc = ARMISD::VQSHRNsu; break;
4899 case Intrinsic::arm_neon_vqrshiftns:
4900 VShiftOpc = ARMISD::VQRSHRNs; break;
4901 case Intrinsic::arm_neon_vqrshiftnu:
4902 VShiftOpc = ARMISD::VQRSHRNu; break;
4903 case Intrinsic::arm_neon_vqrshiftnsu:
4904 VShiftOpc = ARMISD::VQRSHRNsu; break;
4907 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
4908 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
4911 case Intrinsic::arm_neon_vshiftins: {
4912 EVT VT = N->getOperand(1).getValueType();
4914 unsigned VShiftOpc = 0;
4916 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
4917 VShiftOpc = ARMISD::VSLI;
4918 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
4919 VShiftOpc = ARMISD::VSRI;
4921 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
4924 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
4925 N->getOperand(1), N->getOperand(2),
4926 DAG.getConstant(Cnt, MVT::i32));
4929 case Intrinsic::arm_neon_vqrshifts:
4930 case Intrinsic::arm_neon_vqrshiftu:
4931 // No immediate versions of these to check for.
4938 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
4939 /// lowers them. As with the vector shift intrinsics, this is done during DAG
4940 /// combining instead of DAG legalizing because the build_vectors for 64-bit
4941 /// vector element shift counts are generally not legal, and it is hard to see
4942 /// their values after they get legalized to loads from a constant pool.
4943 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
4944 const ARMSubtarget *ST) {
4945 EVT VT = N->getValueType(0);
4947 // Nothing to be done for scalar shifts.
4948 if (! VT.isVector())
4951 assert(ST->hasNEON() && "unexpected vector shift");
4954 switch (N->getOpcode()) {
4955 default: llvm_unreachable("unexpected shift opcode");
4958 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
4959 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
4960 DAG.getConstant(Cnt, MVT::i32));
4965 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
4966 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
4967 ARMISD::VSHRs : ARMISD::VSHRu);
4968 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
4969 DAG.getConstant(Cnt, MVT::i32));
4975 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
4976 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
4977 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
4978 const ARMSubtarget *ST) {
4979 SDValue N0 = N->getOperand(0);
4981 // Check for sign- and zero-extensions of vector extract operations of 8-
4982 // and 16-bit vector elements. NEON supports these directly. They are
4983 // handled during DAG combining because type legalization will promote them
4984 // to 32-bit types and it is messy to recognize the operations after that.
4985 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
4986 SDValue Vec = N0.getOperand(0);
4987 SDValue Lane = N0.getOperand(1);
4988 EVT VT = N->getValueType(0);
4989 EVT EltVT = N0.getValueType();
4990 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4992 if (VT == MVT::i32 &&
4993 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
4994 TLI.isTypeLegal(Vec.getValueType()) &&
4995 isa<ConstantSDNode>(Lane)) {
4998 switch (N->getOpcode()) {
4999 default: llvm_unreachable("unexpected opcode");
5000 case ISD::SIGN_EXTEND:
5001 Opc = ARMISD::VGETLANEs;
5003 case ISD::ZERO_EXTEND:
5004 case ISD::ANY_EXTEND:
5005 Opc = ARMISD::VGETLANEu;
5008 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
5015 /// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
5016 /// to match f32 max/min patterns to use NEON vmax/vmin instructions.
5017 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
5018 const ARMSubtarget *ST) {
5019 // If the target supports NEON, try to use vmax/vmin instructions for f32
5020 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set,
5021 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
5022 // a NaN; only do the transformation when it matches that behavior.
5024 // For now only do this when using NEON for FP operations; if using VFP, it
5025 // is not obvious that the benefit outweighs the cost of switching to the
5027 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
5028 N->getValueType(0) != MVT::f32)
5031 SDValue CondLHS = N->getOperand(0);
5032 SDValue CondRHS = N->getOperand(1);
5033 SDValue LHS = N->getOperand(2);
5034 SDValue RHS = N->getOperand(3);
5035 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
5037 unsigned Opcode = 0;
5039 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
5040 IsReversed = false; // x CC y ? x : y
5041 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
5042 IsReversed = true ; // x CC y ? y : x
5056 // If LHS is NaN, an ordered comparison will be false and the result will
5057 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
5058 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
5059 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
5060 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
5062 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
5063 // will return -0, so vmin can only be used for unsafe math or if one of
5064 // the operands is known to be nonzero.
5065 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
5067 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
5069 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
5078 // If LHS is NaN, an ordered comparison will be false and the result will
5079 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
5080 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
5081 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
5082 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
5084 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
5085 // will return +0, so vmax can only be used for unsafe math or if one of
5086 // the operands is known to be nonzero.
5087 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
5089 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
5091 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
5097 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS);
5100 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
5101 DAGCombinerInfo &DCI) const {
5102 switch (N->getOpcode()) {
5104 case ISD::ADD: return PerformADDCombine(N, DCI);
5105 case ISD::SUB: return PerformSUBCombine(N, DCI);
5106 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
5107 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
5108 case ISD::AND: return PerformANDCombine(N, DCI);
5109 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
5110 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
5111 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI.DAG);
5112 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
5113 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI.DAG);
5114 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
5117 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
5118 case ISD::SIGN_EXTEND:
5119 case ISD::ZERO_EXTEND:
5120 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
5121 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
5126 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
5127 if (!Subtarget->allowsUnalignedMem())
5130 switch (VT.getSimpleVT().SimpleTy) {
5137 // FIXME: VLD1 etc with standard alignment is legal.
5141 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
5146 switch (VT.getSimpleVT().SimpleTy) {
5147 default: return false;
5162 if ((V & (Scale - 1)) != 0)
5165 return V == (V & ((1LL << 5) - 1));
5168 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
5169 const ARMSubtarget *Subtarget) {
5176 switch (VT.getSimpleVT().SimpleTy) {
5177 default: return false;
5182 // + imm12 or - imm8
5184 return V == (V & ((1LL << 8) - 1));
5185 return V == (V & ((1LL << 12) - 1));
5188 // Same as ARM mode. FIXME: NEON?
5189 if (!Subtarget->hasVFP2())
5194 return V == (V & ((1LL << 8) - 1));
5198 /// isLegalAddressImmediate - Return true if the integer value can be used
5199 /// as the offset of the target addressing mode for load / store of the
5201 static bool isLegalAddressImmediate(int64_t V, EVT VT,
5202 const ARMSubtarget *Subtarget) {
5209 if (Subtarget->isThumb1Only())
5210 return isLegalT1AddressImmediate(V, VT);
5211 else if (Subtarget->isThumb2())
5212 return isLegalT2AddressImmediate(V, VT, Subtarget);
5217 switch (VT.getSimpleVT().SimpleTy) {
5218 default: return false;
5223 return V == (V & ((1LL << 12) - 1));
5226 return V == (V & ((1LL << 8) - 1));
5229 if (!Subtarget->hasVFP2()) // FIXME: NEON?
5234 return V == (V & ((1LL << 8) - 1));
5238 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
5240 int Scale = AM.Scale;
5244 switch (VT.getSimpleVT().SimpleTy) {
5245 default: return false;
5254 return Scale == 2 || Scale == 4 || Scale == 8;
5257 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
5261 // Note, we allow "void" uses (basically, uses that aren't loads or
5262 // stores), because arm allows folding a scale into many arithmetic
5263 // operations. This should be made more precise and revisited later.
5265 // Allow r << imm, but the imm has to be a multiple of two.
5266 if (Scale & 1) return false;
5267 return isPowerOf2_32(Scale);
5271 /// isLegalAddressingMode - Return true if the addressing mode represented
5272 /// by AM is legal for this target, for a load/store of the specified type.
5273 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
5274 const Type *Ty) const {
5275 EVT VT = getValueType(Ty, true);
5276 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
5279 // Can never fold addr of global into load/store.
5284 case 0: // no scale reg, must be "r+i" or "r", or "i".
5287 if (Subtarget->isThumb1Only())
5291 // ARM doesn't support any R+R*scale+imm addr modes.
5298 if (Subtarget->isThumb2())
5299 return isLegalT2ScaledAddressingMode(AM, VT);
5301 int Scale = AM.Scale;
5302 switch (VT.getSimpleVT().SimpleTy) {
5303 default: return false;
5307 if (Scale < 0) Scale = -Scale;
5311 return isPowerOf2_32(Scale & ~1);
5315 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
5320 // Note, we allow "void" uses (basically, uses that aren't loads or
5321 // stores), because arm allows folding a scale into many arithmetic
5322 // operations. This should be made more precise and revisited later.
5324 // Allow r << imm, but the imm has to be a multiple of two.
5325 if (Scale & 1) return false;
5326 return isPowerOf2_32(Scale);
5333 /// isLegalICmpImmediate - Return true if the specified immediate is legal
5334 /// icmp immediate, that is the target has icmp instructions which can compare
5335 /// a register against the immediate without having to materialize the
5336 /// immediate into a register.
5337 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
5338 if (!Subtarget->isThumb())
5339 return ARM_AM::getSOImmVal(Imm) != -1;
5340 if (Subtarget->isThumb2())
5341 return ARM_AM::getT2SOImmVal(Imm) != -1;
5342 return Imm >= 0 && Imm <= 255;
5345 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
5346 bool isSEXTLoad, SDValue &Base,
5347 SDValue &Offset, bool &isInc,
5348 SelectionDAG &DAG) {
5349 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
5352 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
5354 Base = Ptr->getOperand(0);
5355 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
5356 int RHSC = (int)RHS->getZExtValue();
5357 if (RHSC < 0 && RHSC > -256) {
5358 assert(Ptr->getOpcode() == ISD::ADD);
5360 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
5364 isInc = (Ptr->getOpcode() == ISD::ADD);
5365 Offset = Ptr->getOperand(1);
5367 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
5369 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
5370 int RHSC = (int)RHS->getZExtValue();
5371 if (RHSC < 0 && RHSC > -0x1000) {
5372 assert(Ptr->getOpcode() == ISD::ADD);
5374 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
5375 Base = Ptr->getOperand(0);
5380 if (Ptr->getOpcode() == ISD::ADD) {
5382 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
5383 if (ShOpcVal != ARM_AM::no_shift) {
5384 Base = Ptr->getOperand(1);
5385 Offset = Ptr->getOperand(0);
5387 Base = Ptr->getOperand(0);
5388 Offset = Ptr->getOperand(1);
5393 isInc = (Ptr->getOpcode() == ISD::ADD);
5394 Base = Ptr->getOperand(0);
5395 Offset = Ptr->getOperand(1);
5399 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
5403 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
5404 bool isSEXTLoad, SDValue &Base,
5405 SDValue &Offset, bool &isInc,
5406 SelectionDAG &DAG) {
5407 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
5410 Base = Ptr->getOperand(0);
5411 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
5412 int RHSC = (int)RHS->getZExtValue();
5413 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
5414 assert(Ptr->getOpcode() == ISD::ADD);
5416 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
5418 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
5419 isInc = Ptr->getOpcode() == ISD::ADD;
5420 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
5428 /// getPreIndexedAddressParts - returns true by value, base pointer and
5429 /// offset pointer and addressing mode by reference if the node's address
5430 /// can be legally represented as pre-indexed load / store address.
5432 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
5434 ISD::MemIndexedMode &AM,
5435 SelectionDAG &DAG) const {
5436 if (Subtarget->isThumb1Only())
5441 bool isSEXTLoad = false;
5442 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5443 Ptr = LD->getBasePtr();
5444 VT = LD->getMemoryVT();
5445 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
5446 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5447 Ptr = ST->getBasePtr();
5448 VT = ST->getMemoryVT();
5453 bool isLegal = false;
5454 if (Subtarget->isThumb2())
5455 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
5456 Offset, isInc, DAG);
5458 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
5459 Offset, isInc, DAG);
5463 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
5467 /// getPostIndexedAddressParts - returns true by value, base pointer and
5468 /// offset pointer and addressing mode by reference if this node can be
5469 /// combined with a load / store to form a post-indexed load / store.
5470 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
5473 ISD::MemIndexedMode &AM,
5474 SelectionDAG &DAG) const {
5475 if (Subtarget->isThumb1Only())
5480 bool isSEXTLoad = false;
5481 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5482 VT = LD->getMemoryVT();
5483 Ptr = LD->getBasePtr();
5484 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
5485 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5486 VT = ST->getMemoryVT();
5487 Ptr = ST->getBasePtr();
5492 bool isLegal = false;
5493 if (Subtarget->isThumb2())
5494 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
5497 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
5503 // Swap base ptr and offset to catch more post-index load / store when
5504 // it's legal. In Thumb2 mode, offset must be an immediate.
5505 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
5506 !Subtarget->isThumb2())
5507 std::swap(Base, Offset);
5509 // Post-indexed load / store update the base pointer.
5514 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
5518 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
5522 const SelectionDAG &DAG,
5523 unsigned Depth) const {
5524 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
5525 switch (Op.getOpcode()) {
5527 case ARMISD::CMOV: {
5528 // Bits are known zero/one if known on the LHS and RHS.
5529 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
5530 if (KnownZero == 0 && KnownOne == 0) return;
5532 APInt KnownZeroRHS, KnownOneRHS;
5533 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
5534 KnownZeroRHS, KnownOneRHS, Depth+1);
5535 KnownZero &= KnownZeroRHS;
5536 KnownOne &= KnownOneRHS;
5542 //===----------------------------------------------------------------------===//
5543 // ARM Inline Assembly Support
5544 //===----------------------------------------------------------------------===//
5546 /// getConstraintType - Given a constraint letter, return the type of
5547 /// constraint it is for this target.
5548 ARMTargetLowering::ConstraintType
5549 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
5550 if (Constraint.size() == 1) {
5551 switch (Constraint[0]) {
5553 case 'l': return C_RegisterClass;
5554 case 'w': return C_RegisterClass;
5557 return TargetLowering::getConstraintType(Constraint);
5560 /// Examine constraint type and operand type and determine a weight value.
5561 /// This object must already have been set up with the operand type
5562 /// and the current alternative constraint selected.
5563 TargetLowering::ConstraintWeight
5564 ARMTargetLowering::getSingleConstraintMatchWeight(
5565 AsmOperandInfo &info, const char *constraint) const {
5566 ConstraintWeight weight = CW_Invalid;
5567 Value *CallOperandVal = info.CallOperandVal;
5568 // If we don't have a value, we can't do a match,
5569 // but allow it at the lowest weight.
5570 if (CallOperandVal == NULL)
5572 const Type *type = CallOperandVal->getType();
5573 // Look at the constraint type.
5574 switch (*constraint) {
5576 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
5579 if (type->isIntegerTy()) {
5580 if (Subtarget->isThumb())
5581 weight = CW_SpecificReg;
5583 weight = CW_Register;
5587 if (type->isFloatingPointTy())
5588 weight = CW_Register;
5594 std::pair<unsigned, const TargetRegisterClass*>
5595 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
5597 if (Constraint.size() == 1) {
5598 // GCC ARM Constraint Letters
5599 switch (Constraint[0]) {
5601 if (Subtarget->isThumb())
5602 return std::make_pair(0U, ARM::tGPRRegisterClass);
5604 return std::make_pair(0U, ARM::GPRRegisterClass);
5606 return std::make_pair(0U, ARM::GPRRegisterClass);
5609 return std::make_pair(0U, ARM::SPRRegisterClass);
5610 if (VT.getSizeInBits() == 64)
5611 return std::make_pair(0U, ARM::DPRRegisterClass);
5612 if (VT.getSizeInBits() == 128)
5613 return std::make_pair(0U, ARM::QPRRegisterClass);
5617 if (StringRef("{cc}").equals_lower(Constraint))
5618 return std::make_pair(unsigned(ARM::CPSR), ARM::CCRRegisterClass);
5620 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
5623 std::vector<unsigned> ARMTargetLowering::
5624 getRegClassForInlineAsmConstraint(const std::string &Constraint,
5626 if (Constraint.size() != 1)
5627 return std::vector<unsigned>();
5629 switch (Constraint[0]) { // GCC ARM Constraint Letters
5632 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
5633 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
5636 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
5637 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
5638 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
5639 ARM::R12, ARM::LR, 0);
5642 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
5643 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
5644 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
5645 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
5646 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
5647 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
5648 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
5649 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
5650 if (VT.getSizeInBits() == 64)
5651 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
5652 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
5653 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
5654 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
5655 if (VT.getSizeInBits() == 128)
5656 return make_vector<unsigned>(ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
5657 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 0);
5661 return std::vector<unsigned>();
5664 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
5665 /// vector. If it is invalid, don't add anything to Ops.
5666 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
5668 std::vector<SDValue>&Ops,
5669 SelectionDAG &DAG) const {
5670 SDValue Result(0, 0);
5672 switch (Constraint) {
5674 case 'I': case 'J': case 'K': case 'L':
5675 case 'M': case 'N': case 'O':
5676 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
5680 int64_t CVal64 = C->getSExtValue();
5681 int CVal = (int) CVal64;
5682 // None of these constraints allow values larger than 32 bits. Check
5683 // that the value fits in an int.
5687 switch (Constraint) {
5689 if (Subtarget->isThumb1Only()) {
5690 // This must be a constant between 0 and 255, for ADD
5692 if (CVal >= 0 && CVal <= 255)
5694 } else if (Subtarget->isThumb2()) {
5695 // A constant that can be used as an immediate value in a
5696 // data-processing instruction.
5697 if (ARM_AM::getT2SOImmVal(CVal) != -1)
5700 // A constant that can be used as an immediate value in a
5701 // data-processing instruction.
5702 if (ARM_AM::getSOImmVal(CVal) != -1)
5708 if (Subtarget->isThumb()) { // FIXME thumb2
5709 // This must be a constant between -255 and -1, for negated ADD
5710 // immediates. This can be used in GCC with an "n" modifier that
5711 // prints the negated value, for use with SUB instructions. It is
5712 // not useful otherwise but is implemented for compatibility.
5713 if (CVal >= -255 && CVal <= -1)
5716 // This must be a constant between -4095 and 4095. It is not clear
5717 // what this constraint is intended for. Implemented for
5718 // compatibility with GCC.
5719 if (CVal >= -4095 && CVal <= 4095)
5725 if (Subtarget->isThumb1Only()) {
5726 // A 32-bit value where only one byte has a nonzero value. Exclude
5727 // zero to match GCC. This constraint is used by GCC internally for
5728 // constants that can be loaded with a move/shift combination.
5729 // It is not useful otherwise but is implemented for compatibility.
5730 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
5732 } else if (Subtarget->isThumb2()) {
5733 // A constant whose bitwise inverse can be used as an immediate
5734 // value in a data-processing instruction. This can be used in GCC
5735 // with a "B" modifier that prints the inverted value, for use with
5736 // BIC and MVN instructions. It is not useful otherwise but is
5737 // implemented for compatibility.
5738 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
5741 // A constant whose bitwise inverse can be used as an immediate
5742 // value in a data-processing instruction. This can be used in GCC
5743 // with a "B" modifier that prints the inverted value, for use with
5744 // BIC and MVN instructions. It is not useful otherwise but is
5745 // implemented for compatibility.
5746 if (ARM_AM::getSOImmVal(~CVal) != -1)
5752 if (Subtarget->isThumb1Only()) {
5753 // This must be a constant between -7 and 7,
5754 // for 3-operand ADD/SUB immediate instructions.
5755 if (CVal >= -7 && CVal < 7)
5757 } else if (Subtarget->isThumb2()) {
5758 // A constant whose negation can be used as an immediate value in a
5759 // data-processing instruction. This can be used in GCC with an "n"
5760 // modifier that prints the negated value, for use with SUB
5761 // instructions. It is not useful otherwise but is implemented for
5763 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
5766 // A constant whose negation can be used as an immediate value in a
5767 // data-processing instruction. This can be used in GCC with an "n"
5768 // modifier that prints the negated value, for use with SUB
5769 // instructions. It is not useful otherwise but is implemented for
5771 if (ARM_AM::getSOImmVal(-CVal) != -1)
5777 if (Subtarget->isThumb()) { // FIXME thumb2
5778 // This must be a multiple of 4 between 0 and 1020, for
5779 // ADD sp + immediate.
5780 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
5783 // A power of two or a constant between 0 and 32. This is used in
5784 // GCC for the shift amount on shifted register operands, but it is
5785 // useful in general for any shift amounts.
5786 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
5792 if (Subtarget->isThumb()) { // FIXME thumb2
5793 // This must be a constant between 0 and 31, for shift amounts.
5794 if (CVal >= 0 && CVal <= 31)
5800 if (Subtarget->isThumb()) { // FIXME thumb2
5801 // This must be a multiple of 4 between -508 and 508, for
5802 // ADD/SUB sp = sp + immediate.
5803 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
5808 Result = DAG.getTargetConstant(CVal, Op.getValueType());
5812 if (Result.getNode()) {
5813 Ops.push_back(Result);
5816 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
5820 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
5821 // The ARM target isn't yet aware of offsets.
5825 int ARM::getVFPf32Imm(const APFloat &FPImm) {
5826 APInt Imm = FPImm.bitcastToAPInt();
5827 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
5828 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127
5829 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits
5831 // We can handle 4 bits of mantissa.
5832 // mantissa = (16+UInt(e:f:g:h))/16.
5833 if (Mantissa & 0x7ffff)
5836 if ((Mantissa & 0xf) != Mantissa)
5839 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
5840 if (Exp < -3 || Exp > 4)
5842 Exp = ((Exp+3) & 0x7) ^ 4;
5844 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
5847 int ARM::getVFPf64Imm(const APFloat &FPImm) {
5848 APInt Imm = FPImm.bitcastToAPInt();
5849 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
5850 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
5851 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffLL;
5853 // We can handle 4 bits of mantissa.
5854 // mantissa = (16+UInt(e:f:g:h))/16.
5855 if (Mantissa & 0xffffffffffffLL)
5858 if ((Mantissa & 0xf) != Mantissa)
5861 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
5862 if (Exp < -3 || Exp > 4)
5864 Exp = ((Exp+3) & 0x7) ^ 4;
5866 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
5869 bool ARM::isBitFieldInvertedMask(unsigned v) {
5870 if (v == 0xffffffff)
5872 // there can be 1's on either or both "outsides", all the "inside"
5874 unsigned int lsb = 0, msb = 31;
5875 while (v & (1 << msb)) --msb;
5876 while (v & (1 << lsb)) ++lsb;
5877 for (unsigned int i = lsb; i <= msb; ++i) {
5884 /// isFPImmLegal - Returns true if the target can instruction select the
5885 /// specified FP immediate natively. If false, the legalizer will
5886 /// materialize the FP immediate as a load from a constant pool.
5887 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
5888 if (!Subtarget->hasVFP3())
5891 return ARM::getVFPf32Imm(Imm) != -1;
5893 return ARM::getVFPf64Imm(Imm) != -1;
5897 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
5898 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
5899 /// specified in the intrinsic calls.
5900 bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
5902 unsigned Intrinsic) const {
5903 switch (Intrinsic) {
5904 case Intrinsic::arm_neon_vld1:
5905 case Intrinsic::arm_neon_vld2:
5906 case Intrinsic::arm_neon_vld3:
5907 case Intrinsic::arm_neon_vld4:
5908 case Intrinsic::arm_neon_vld2lane:
5909 case Intrinsic::arm_neon_vld3lane:
5910 case Intrinsic::arm_neon_vld4lane: {
5911 Info.opc = ISD::INTRINSIC_W_CHAIN;
5912 // Conservatively set memVT to the entire set of vectors loaded.
5913 uint64_t NumElts = getTargetData()->getTypeAllocSize(I.getType()) / 8;
5914 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
5915 Info.ptrVal = I.getArgOperand(0);
5917 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
5918 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
5919 Info.vol = false; // volatile loads with NEON intrinsics not supported
5920 Info.readMem = true;
5921 Info.writeMem = false;
5924 case Intrinsic::arm_neon_vst1:
5925 case Intrinsic::arm_neon_vst2:
5926 case Intrinsic::arm_neon_vst3:
5927 case Intrinsic::arm_neon_vst4:
5928 case Intrinsic::arm_neon_vst2lane:
5929 case Intrinsic::arm_neon_vst3lane:
5930 case Intrinsic::arm_neon_vst4lane: {
5931 Info.opc = ISD::INTRINSIC_VOID;
5932 // Conservatively set memVT to the entire set of vectors stored.
5933 unsigned NumElts = 0;
5934 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
5935 const Type *ArgTy = I.getArgOperand(ArgI)->getType();
5936 if (!ArgTy->isVectorTy())
5938 NumElts += getTargetData()->getTypeAllocSize(ArgTy) / 8;
5940 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
5941 Info.ptrVal = I.getArgOperand(0);
5943 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
5944 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
5945 Info.vol = false; // volatile stores with NEON intrinsics not supported
5946 Info.readMem = false;
5947 Info.writeMem = true;