1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "arm-isel"
17 #include "ARMAddressingModes.h"
18 #include "ARMCallingConv.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMISelLowering.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMPerfectShuffle.h"
23 #include "ARMRegisterInfo.h"
24 #include "ARMSubtarget.h"
25 #include "ARMTargetMachine.h"
26 #include "ARMTargetObjectFile.h"
27 #include "llvm/CallingConv.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Function.h"
30 #include "llvm/GlobalValue.h"
31 #include "llvm/Instruction.h"
32 #include "llvm/Instructions.h"
33 #include "llvm/Intrinsics.h"
34 #include "llvm/Type.h"
35 #include "llvm/CodeGen/CallingConvLower.h"
36 #include "llvm/CodeGen/MachineBasicBlock.h"
37 #include "llvm/CodeGen/MachineFrameInfo.h"
38 #include "llvm/CodeGen/MachineFunction.h"
39 #include "llvm/CodeGen/MachineInstrBuilder.h"
40 #include "llvm/CodeGen/MachineRegisterInfo.h"
41 #include "llvm/CodeGen/PseudoSourceValue.h"
42 #include "llvm/CodeGen/SelectionDAG.h"
43 #include "llvm/MC/MCSectionMachO.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/ADT/VectorExtras.h"
46 #include "llvm/ADT/Statistic.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Support/raw_ostream.h"
54 STATISTIC(NumTailCalls, "Number of tail calls");
56 // This option should go away when tail calls fully work.
58 EnableARMTailCalls("arm-tail-calls", cl::Hidden,
59 cl::desc("Generate tail calls (TEMPORARY OPTION)."),
62 // This option should go away when Machine LICM is smart enough to hoist a
65 EnableARMVDUPsplat("arm-vdup-splat", cl::Hidden,
66 cl::desc("Generate VDUP for integer constant splats (TEMPORARY OPTION)."),
70 EnableARMLongCalls("arm-long-calls", cl::Hidden,
71 cl::desc("Generate calls via indirect call instructions"),
75 ARMInterworking("arm-interworking", cl::Hidden,
76 cl::desc("Enable / disable ARM interworking (for debugging only)"),
79 void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
80 EVT PromotedBitwiseVT) {
81 if (VT != PromotedLdStVT) {
82 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
83 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
84 PromotedLdStVT.getSimpleVT());
86 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
87 AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
88 PromotedLdStVT.getSimpleVT());
91 EVT ElemTy = VT.getVectorElementType();
92 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
93 setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
94 if (ElemTy == MVT::i8 || ElemTy == MVT::i16)
95 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
96 if (ElemTy != MVT::i32) {
97 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
98 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand);
99 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand);
100 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand);
102 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
103 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
104 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
105 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Expand);
106 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
107 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
108 if (VT.isInteger()) {
109 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
110 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
111 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
112 setLoadExtAction(ISD::SEXTLOAD, VT.getSimpleVT(), Expand);
113 setLoadExtAction(ISD::ZEXTLOAD, VT.getSimpleVT(), Expand);
115 setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand);
117 // Promote all bit-wise operations.
118 if (VT.isInteger() && VT != PromotedBitwiseVT) {
119 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
120 AddPromotedToType (ISD::AND, VT.getSimpleVT(),
121 PromotedBitwiseVT.getSimpleVT());
122 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
123 AddPromotedToType (ISD::OR, VT.getSimpleVT(),
124 PromotedBitwiseVT.getSimpleVT());
125 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
126 AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
127 PromotedBitwiseVT.getSimpleVT());
130 // Neon does not support vector divide/remainder operations.
131 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
132 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
133 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand);
134 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
135 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
136 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
139 void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
140 addRegisterClass(VT, ARM::DPRRegisterClass);
141 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
144 void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
145 addRegisterClass(VT, ARM::QPRRegisterClass);
146 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
149 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
150 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
151 return new TargetLoweringObjectFileMachO();
153 return new ARMElfTargetObjectFile();
156 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
157 : TargetLowering(TM, createTLOF(TM)) {
158 Subtarget = &TM.getSubtarget<ARMSubtarget>();
159 RegInfo = TM.getRegisterInfo();
160 Itins = TM.getInstrItineraryData();
162 if (Subtarget->isTargetDarwin()) {
163 // Uses VFP for Thumb libfuncs if available.
164 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
165 // Single-precision floating-point arithmetic.
166 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
167 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
168 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
169 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
171 // Double-precision floating-point arithmetic.
172 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
173 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
174 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
175 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
177 // Single-precision comparisons.
178 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
179 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
180 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
181 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
182 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
183 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
184 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
185 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
187 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
188 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
189 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
190 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
191 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
192 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
193 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
194 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
196 // Double-precision comparisons.
197 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
198 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
199 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
200 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
201 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
202 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
203 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
204 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
206 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
207 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
208 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
209 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
210 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
211 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
212 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
213 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
215 // Floating-point to integer conversions.
216 // i64 conversions are done via library routines even when generating VFP
217 // instructions, so use the same ones.
218 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
219 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
220 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
221 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
223 // Conversions between floating types.
224 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
225 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
227 // Integer to floating-point conversions.
228 // i64 conversions are done via library routines even when generating VFP
229 // instructions, so use the same ones.
230 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
231 // e.g., __floatunsidf vs. __floatunssidfvfp.
232 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
233 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
234 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
235 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
239 // These libcalls are not available in 32-bit.
240 setLibcallName(RTLIB::SHL_I128, 0);
241 setLibcallName(RTLIB::SRL_I128, 0);
242 setLibcallName(RTLIB::SRA_I128, 0);
244 // Libcalls should use the AAPCS base standard ABI, even if hard float
245 // is in effect, as per the ARM RTABI specification, section 4.1.2.
246 if (Subtarget->isAAPCS_ABI()) {
247 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
248 setLibcallCallingConv(static_cast<RTLIB::Libcall>(i),
249 CallingConv::ARM_AAPCS);
253 if (Subtarget->isThumb1Only())
254 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
256 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
257 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
258 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
259 if (!Subtarget->isFPOnlySP())
260 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
262 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
265 if (Subtarget->hasNEON()) {
266 addDRTypeForNEON(MVT::v2f32);
267 addDRTypeForNEON(MVT::v8i8);
268 addDRTypeForNEON(MVT::v4i16);
269 addDRTypeForNEON(MVT::v2i32);
270 addDRTypeForNEON(MVT::v1i64);
272 addQRTypeForNEON(MVT::v4f32);
273 addQRTypeForNEON(MVT::v2f64);
274 addQRTypeForNEON(MVT::v16i8);
275 addQRTypeForNEON(MVT::v8i16);
276 addQRTypeForNEON(MVT::v4i32);
277 addQRTypeForNEON(MVT::v2i64);
279 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
280 // neither Neon nor VFP support any arithmetic operations on it.
281 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
282 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
283 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
284 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
285 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
286 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
287 setOperationAction(ISD::VSETCC, MVT::v2f64, Expand);
288 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
289 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
290 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
291 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
292 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
293 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
294 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
295 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
296 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
297 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
298 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
299 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
300 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
301 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
302 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
303 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
304 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
306 setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand);
308 // Neon does not support some operations on v1i64 and v2i64 types.
309 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
310 // Custom handling for some quad-vector types to detect VMULL.
311 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
312 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
313 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
314 setOperationAction(ISD::VSETCC, MVT::v1i64, Expand);
315 setOperationAction(ISD::VSETCC, MVT::v2i64, Expand);
317 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
318 setTargetDAGCombine(ISD::SHL);
319 setTargetDAGCombine(ISD::SRL);
320 setTargetDAGCombine(ISD::SRA);
321 setTargetDAGCombine(ISD::SIGN_EXTEND);
322 setTargetDAGCombine(ISD::ZERO_EXTEND);
323 setTargetDAGCombine(ISD::ANY_EXTEND);
324 setTargetDAGCombine(ISD::SELECT_CC);
325 setTargetDAGCombine(ISD::BUILD_VECTOR);
328 computeRegisterProperties();
330 // ARM does not have f32 extending load.
331 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
333 // ARM does not have i1 sign extending load.
334 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
336 // ARM supports all 4 flavors of integer indexed load / store.
337 if (!Subtarget->isThumb1Only()) {
338 for (unsigned im = (unsigned)ISD::PRE_INC;
339 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
340 setIndexedLoadAction(im, MVT::i1, Legal);
341 setIndexedLoadAction(im, MVT::i8, Legal);
342 setIndexedLoadAction(im, MVT::i16, Legal);
343 setIndexedLoadAction(im, MVT::i32, Legal);
344 setIndexedStoreAction(im, MVT::i1, Legal);
345 setIndexedStoreAction(im, MVT::i8, Legal);
346 setIndexedStoreAction(im, MVT::i16, Legal);
347 setIndexedStoreAction(im, MVT::i32, Legal);
351 // i64 operation support.
352 if (Subtarget->isThumb1Only()) {
353 setOperationAction(ISD::MUL, MVT::i64, Expand);
354 setOperationAction(ISD::MULHU, MVT::i32, Expand);
355 setOperationAction(ISD::MULHS, MVT::i32, Expand);
356 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
357 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
359 setOperationAction(ISD::MUL, MVT::i64, Expand);
360 setOperationAction(ISD::MULHU, MVT::i32, Expand);
361 if (!Subtarget->hasV6Ops())
362 setOperationAction(ISD::MULHS, MVT::i32, Expand);
364 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
365 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
366 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
367 setOperationAction(ISD::SRL, MVT::i64, Custom);
368 setOperationAction(ISD::SRA, MVT::i64, Custom);
370 // ARM does not have ROTL.
371 setOperationAction(ISD::ROTL, MVT::i32, Expand);
372 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
373 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
374 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
375 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
377 // Only ARMv6 has BSWAP.
378 if (!Subtarget->hasV6Ops())
379 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
381 // These are expanded into libcalls.
382 if (!Subtarget->hasDivide()) {
383 // v7M has a hardware divider
384 setOperationAction(ISD::SDIV, MVT::i32, Expand);
385 setOperationAction(ISD::UDIV, MVT::i32, Expand);
387 setOperationAction(ISD::SREM, MVT::i32, Expand);
388 setOperationAction(ISD::UREM, MVT::i32, Expand);
389 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
390 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
392 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
393 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
394 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
395 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
396 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
398 setOperationAction(ISD::TRAP, MVT::Other, Legal);
400 // Use the default implementation.
401 setOperationAction(ISD::VASTART, MVT::Other, Custom);
402 setOperationAction(ISD::VAARG, MVT::Other, Expand);
403 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
404 setOperationAction(ISD::VAEND, MVT::Other, Expand);
405 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
406 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
407 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
408 // FIXME: Shouldn't need this, since no register is used, but the legalizer
409 // doesn't yet know how to not do that for SjLj.
410 setExceptionSelectorRegister(ARM::R0);
411 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
412 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
413 // the default expansion.
414 if (Subtarget->hasDataBarrier() ||
415 (Subtarget->hasV6Ops() && !Subtarget->isThumb1Only())) {
416 // membarrier needs custom lowering; the rest are legal and handled
418 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
420 // Set them all for expansion, which will force libcalls.
421 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
422 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Expand);
423 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Expand);
424 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
425 setOperationAction(ISD::ATOMIC_SWAP, MVT::i8, Expand);
426 setOperationAction(ISD::ATOMIC_SWAP, MVT::i16, Expand);
427 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
428 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i8, Expand);
429 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i16, Expand);
430 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
431 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Expand);
432 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Expand);
433 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
434 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i8, Expand);
435 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i16, Expand);
436 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
437 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i8, Expand);
438 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i16, Expand);
439 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
440 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i8, Expand);
441 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i16, Expand);
442 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
443 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i8, Expand);
444 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i16, Expand);
445 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
446 // Since the libcalls include locking, fold in the fences
447 setShouldFoldAtomicFences(true);
449 // 64-bit versions are always libcalls (for now)
450 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Expand);
451 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Expand);
452 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Expand);
453 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Expand);
454 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Expand);
455 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Expand);
456 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Expand);
457 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Expand);
459 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
460 if (!Subtarget->hasV6Ops()) {
461 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
462 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
464 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
466 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
467 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
468 // iff target supports vfp2.
469 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
470 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
473 // We want to custom lower some of our intrinsics.
474 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
475 if (Subtarget->isTargetDarwin()) {
476 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
477 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
480 setOperationAction(ISD::SETCC, MVT::i32, Expand);
481 setOperationAction(ISD::SETCC, MVT::f32, Expand);
482 setOperationAction(ISD::SETCC, MVT::f64, Expand);
483 setOperationAction(ISD::SELECT, MVT::i32, Custom);
484 setOperationAction(ISD::SELECT, MVT::f32, Custom);
485 setOperationAction(ISD::SELECT, MVT::f64, Custom);
486 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
487 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
488 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
490 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
491 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
492 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
493 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
494 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
496 // We don't support sin/cos/fmod/copysign/pow
497 setOperationAction(ISD::FSIN, MVT::f64, Expand);
498 setOperationAction(ISD::FSIN, MVT::f32, Expand);
499 setOperationAction(ISD::FCOS, MVT::f32, Expand);
500 setOperationAction(ISD::FCOS, MVT::f64, Expand);
501 setOperationAction(ISD::FREM, MVT::f64, Expand);
502 setOperationAction(ISD::FREM, MVT::f32, Expand);
503 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
504 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
505 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
507 setOperationAction(ISD::FPOW, MVT::f64, Expand);
508 setOperationAction(ISD::FPOW, MVT::f32, Expand);
510 // Various VFP goodness
511 if (!UseSoftFloat && !Subtarget->isThumb1Only()) {
512 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
513 if (Subtarget->hasVFP2()) {
514 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
515 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
516 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
517 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
519 // Special handling for half-precision FP.
520 if (!Subtarget->hasFP16()) {
521 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
522 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand);
526 // We have target-specific dag combine patterns for the following nodes:
527 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
528 setTargetDAGCombine(ISD::ADD);
529 setTargetDAGCombine(ISD::SUB);
530 setTargetDAGCombine(ISD::MUL);
532 if (Subtarget->hasV6T2Ops())
533 setTargetDAGCombine(ISD::OR);
535 setStackPointerRegisterToSaveRestore(ARM::SP);
537 if (UseSoftFloat || Subtarget->isThumb1Only() || !Subtarget->hasVFP2())
538 setSchedulingPreference(Sched::RegPressure);
540 setSchedulingPreference(Sched::Hybrid);
542 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
544 // On ARM arguments smaller than 4 bytes are extended, so all arguments
545 // are at least 4 bytes aligned.
546 setMinStackArgumentAlignment(4);
548 benefitFromCodePlacementOpt = true;
551 std::pair<const TargetRegisterClass*, uint8_t>
552 ARMTargetLowering::findRepresentativeClass(EVT VT) const{
553 const TargetRegisterClass *RRC = 0;
555 switch (VT.getSimpleVT().SimpleTy) {
557 return TargetLowering::findRepresentativeClass(VT);
558 // Use DPR as representative register class for all floating point
559 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
560 // the cost is 1 for both f32 and f64.
561 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
562 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
563 RRC = ARM::DPRRegisterClass;
565 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
566 case MVT::v4f32: case MVT::v2f64:
567 RRC = ARM::DPRRegisterClass;
571 RRC = ARM::DPRRegisterClass;
575 RRC = ARM::DPRRegisterClass;
579 return std::make_pair(RRC, Cost);
582 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
585 case ARMISD::Wrapper: return "ARMISD::Wrapper";
586 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
587 case ARMISD::CALL: return "ARMISD::CALL";
588 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
589 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
590 case ARMISD::tCALL: return "ARMISD::tCALL";
591 case ARMISD::BRCOND: return "ARMISD::BRCOND";
592 case ARMISD::BR_JT: return "ARMISD::BR_JT";
593 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
594 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
595 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
596 case ARMISD::AND: return "ARMISD::AND";
597 case ARMISD::CMP: return "ARMISD::CMP";
598 case ARMISD::CMPZ: return "ARMISD::CMPZ";
599 case ARMISD::CMPFP: return "ARMISD::CMPFP";
600 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
601 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
602 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
603 case ARMISD::CMOV: return "ARMISD::CMOV";
604 case ARMISD::CNEG: return "ARMISD::CNEG";
606 case ARMISD::RBIT: return "ARMISD::RBIT";
608 case ARMISD::FTOSI: return "ARMISD::FTOSI";
609 case ARMISD::FTOUI: return "ARMISD::FTOUI";
610 case ARMISD::SITOF: return "ARMISD::SITOF";
611 case ARMISD::UITOF: return "ARMISD::UITOF";
613 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
614 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
615 case ARMISD::RRX: return "ARMISD::RRX";
617 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
618 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
620 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
621 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
623 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
625 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
627 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
629 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER";
630 case ARMISD::SYNCBARRIER: return "ARMISD::SYNCBARRIER";
632 case ARMISD::VCEQ: return "ARMISD::VCEQ";
633 case ARMISD::VCGE: return "ARMISD::VCGE";
634 case ARMISD::VCGEU: return "ARMISD::VCGEU";
635 case ARMISD::VCGT: return "ARMISD::VCGT";
636 case ARMISD::VCGTU: return "ARMISD::VCGTU";
637 case ARMISD::VTST: return "ARMISD::VTST";
639 case ARMISD::VSHL: return "ARMISD::VSHL";
640 case ARMISD::VSHRs: return "ARMISD::VSHRs";
641 case ARMISD::VSHRu: return "ARMISD::VSHRu";
642 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
643 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
644 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
645 case ARMISD::VSHRN: return "ARMISD::VSHRN";
646 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
647 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
648 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
649 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
650 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
651 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
652 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
653 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
654 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
655 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
656 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
657 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
658 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
659 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
660 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
661 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
662 case ARMISD::VDUP: return "ARMISD::VDUP";
663 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
664 case ARMISD::VEXT: return "ARMISD::VEXT";
665 case ARMISD::VREV64: return "ARMISD::VREV64";
666 case ARMISD::VREV32: return "ARMISD::VREV32";
667 case ARMISD::VREV16: return "ARMISD::VREV16";
668 case ARMISD::VZIP: return "ARMISD::VZIP";
669 case ARMISD::VUZP: return "ARMISD::VUZP";
670 case ARMISD::VTRN: return "ARMISD::VTRN";
671 case ARMISD::VMULLs: return "ARMISD::VMULLs";
672 case ARMISD::VMULLu: return "ARMISD::VMULLu";
673 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
674 case ARMISD::FMAX: return "ARMISD::FMAX";
675 case ARMISD::FMIN: return "ARMISD::FMIN";
676 case ARMISD::BFI: return "ARMISD::BFI";
680 /// getRegClassFor - Return the register class that should be used for the
681 /// specified value type.
682 TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const {
683 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
684 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
685 // load / store 4 to 8 consecutive D registers.
686 if (Subtarget->hasNEON()) {
687 if (VT == MVT::v4i64)
688 return ARM::QQPRRegisterClass;
689 else if (VT == MVT::v8i64)
690 return ARM::QQQQPRRegisterClass;
692 return TargetLowering::getRegClassFor(VT);
695 // Create a fast isel object.
697 ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
698 return ARM::createFastISel(funcInfo);
701 /// getFunctionAlignment - Return the Log2 alignment of this function.
702 unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
703 return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 1 : 2;
706 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
707 /// be used for loads / stores from the global.
708 unsigned ARMTargetLowering::getMaximalGlobalOffset() const {
709 return (Subtarget->isThumb1Only() ? 127 : 4095);
712 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
713 unsigned NumVals = N->getNumValues();
715 return Sched::RegPressure;
717 for (unsigned i = 0; i != NumVals; ++i) {
718 EVT VT = N->getValueType(i);
719 if (VT.isFloatingPoint() || VT.isVector())
720 return Sched::Latency;
723 if (!N->isMachineOpcode())
724 return Sched::RegPressure;
726 // Load are scheduled for latency even if there instruction itinerary
728 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
729 const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
731 return Sched::Latency;
733 if (!Itins->isEmpty() && Itins->getStageLatency(TID.getSchedClass()) > 2)
734 return Sched::Latency;
735 return Sched::RegPressure;
739 ARMTargetLowering::getRegPressureLimit(const TargetRegisterClass *RC,
740 MachineFunction &MF) const {
741 switch (RC->getID()) {
744 case ARM::tGPRRegClassID:
745 return RegInfo->hasFP(MF) ? 4 : 5;
746 case ARM::GPRRegClassID: {
747 unsigned FP = RegInfo->hasFP(MF) ? 1 : 0;
748 return 10 - FP - (Subtarget->isR9Reserved() ? 1 : 0);
750 case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
751 case ARM::DPRRegClassID:
756 //===----------------------------------------------------------------------===//
758 //===----------------------------------------------------------------------===//
760 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
761 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
763 default: llvm_unreachable("Unknown condition code!");
764 case ISD::SETNE: return ARMCC::NE;
765 case ISD::SETEQ: return ARMCC::EQ;
766 case ISD::SETGT: return ARMCC::GT;
767 case ISD::SETGE: return ARMCC::GE;
768 case ISD::SETLT: return ARMCC::LT;
769 case ISD::SETLE: return ARMCC::LE;
770 case ISD::SETUGT: return ARMCC::HI;
771 case ISD::SETUGE: return ARMCC::HS;
772 case ISD::SETULT: return ARMCC::LO;
773 case ISD::SETULE: return ARMCC::LS;
777 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
778 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
779 ARMCC::CondCodes &CondCode2) {
780 CondCode2 = ARMCC::AL;
782 default: llvm_unreachable("Unknown FP condition!");
784 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
786 case ISD::SETOGT: CondCode = ARMCC::GT; break;
788 case ISD::SETOGE: CondCode = ARMCC::GE; break;
789 case ISD::SETOLT: CondCode = ARMCC::MI; break;
790 case ISD::SETOLE: CondCode = ARMCC::LS; break;
791 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
792 case ISD::SETO: CondCode = ARMCC::VC; break;
793 case ISD::SETUO: CondCode = ARMCC::VS; break;
794 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
795 case ISD::SETUGT: CondCode = ARMCC::HI; break;
796 case ISD::SETUGE: CondCode = ARMCC::PL; break;
798 case ISD::SETULT: CondCode = ARMCC::LT; break;
800 case ISD::SETULE: CondCode = ARMCC::LE; break;
802 case ISD::SETUNE: CondCode = ARMCC::NE; break;
806 //===----------------------------------------------------------------------===//
807 // Calling Convention Implementation
808 //===----------------------------------------------------------------------===//
810 #include "ARMGenCallingConv.inc"
812 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
813 /// given CallingConvention value.
814 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
816 bool isVarArg) const {
819 llvm_unreachable("Unsupported calling convention");
821 case CallingConv::Fast:
822 // Use target triple & subtarget features to do actual dispatch.
823 if (Subtarget->isAAPCS_ABI()) {
824 if (Subtarget->hasVFP2() &&
825 FloatABIType == FloatABI::Hard && !isVarArg)
826 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
828 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
830 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
831 case CallingConv::ARM_AAPCS_VFP:
832 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
833 case CallingConv::ARM_AAPCS:
834 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
835 case CallingConv::ARM_APCS:
836 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
840 /// LowerCallResult - Lower the result values of a call into the
841 /// appropriate copies out of appropriate physical registers.
843 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
844 CallingConv::ID CallConv, bool isVarArg,
845 const SmallVectorImpl<ISD::InputArg> &Ins,
846 DebugLoc dl, SelectionDAG &DAG,
847 SmallVectorImpl<SDValue> &InVals) const {
849 // Assign locations to each value returned by this call.
850 SmallVector<CCValAssign, 16> RVLocs;
851 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
852 RVLocs, *DAG.getContext());
853 CCInfo.AnalyzeCallResult(Ins,
854 CCAssignFnForNode(CallConv, /* Return*/ true,
857 // Copy all of the result registers out of their specified physreg.
858 for (unsigned i = 0; i != RVLocs.size(); ++i) {
859 CCValAssign VA = RVLocs[i];
862 if (VA.needsCustom()) {
863 // Handle f64 or half of a v2f64.
864 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
866 Chain = Lo.getValue(1);
867 InFlag = Lo.getValue(2);
868 VA = RVLocs[++i]; // skip ahead to next loc
869 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
871 Chain = Hi.getValue(1);
872 InFlag = Hi.getValue(2);
873 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
875 if (VA.getLocVT() == MVT::v2f64) {
876 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
877 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
878 DAG.getConstant(0, MVT::i32));
880 VA = RVLocs[++i]; // skip ahead to next loc
881 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
882 Chain = Lo.getValue(1);
883 InFlag = Lo.getValue(2);
884 VA = RVLocs[++i]; // skip ahead to next loc
885 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
886 Chain = Hi.getValue(1);
887 InFlag = Hi.getValue(2);
888 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
889 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
890 DAG.getConstant(1, MVT::i32));
893 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
895 Chain = Val.getValue(1);
896 InFlag = Val.getValue(2);
899 switch (VA.getLocInfo()) {
900 default: llvm_unreachable("Unknown loc info!");
901 case CCValAssign::Full: break;
902 case CCValAssign::BCvt:
903 Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val);
907 InVals.push_back(Val);
913 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
914 /// by "Src" to address "Dst" of size "Size". Alignment information is
915 /// specified by the specific parameter attribute. The copy will be passed as
916 /// a byval function parameter.
917 /// Sometimes what we are copying is the end of a larger object, the part that
918 /// does not fit in registers.
920 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
921 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
923 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
924 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
925 /*isVolatile=*/false, /*AlwaysInline=*/false,
926 MachinePointerInfo(0), MachinePointerInfo(0));
929 /// LowerMemOpCallTo - Store the argument to the stack.
931 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
932 SDValue StackPtr, SDValue Arg,
933 DebugLoc dl, SelectionDAG &DAG,
934 const CCValAssign &VA,
935 ISD::ArgFlagsTy Flags) const {
936 unsigned LocMemOffset = VA.getLocMemOffset();
937 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
938 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
940 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
942 return DAG.getStore(Chain, dl, Arg, PtrOff,
943 MachinePointerInfo::getStack(LocMemOffset),
947 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
948 SDValue Chain, SDValue &Arg,
949 RegsToPassVector &RegsToPass,
950 CCValAssign &VA, CCValAssign &NextVA,
952 SmallVector<SDValue, 8> &MemOpChains,
953 ISD::ArgFlagsTy Flags) const {
955 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
956 DAG.getVTList(MVT::i32, MVT::i32), Arg);
957 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
959 if (NextVA.isRegLoc())
960 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
962 assert(NextVA.isMemLoc());
963 if (StackPtr.getNode() == 0)
964 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
966 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
972 /// LowerCall - Lowering a call into a callseq_start <-
973 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
976 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
977 CallingConv::ID CallConv, bool isVarArg,
979 const SmallVectorImpl<ISD::OutputArg> &Outs,
980 const SmallVectorImpl<SDValue> &OutVals,
981 const SmallVectorImpl<ISD::InputArg> &Ins,
982 DebugLoc dl, SelectionDAG &DAG,
983 SmallVectorImpl<SDValue> &InVals) const {
984 MachineFunction &MF = DAG.getMachineFunction();
985 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
986 bool IsSibCall = false;
987 // Temporarily disable tail calls so things don't break.
988 if (!EnableARMTailCalls)
991 // Check if it's really possible to do a tail call.
992 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
993 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
994 Outs, OutVals, Ins, DAG);
995 // We don't support GuaranteedTailCallOpt for ARM, only automatically
996 // detected sibcalls.
1003 // Analyze operands of the call, assigning locations to each operand.
1004 SmallVector<CCValAssign, 16> ArgLocs;
1005 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1007 CCInfo.AnalyzeCallOperands(Outs,
1008 CCAssignFnForNode(CallConv, /* Return*/ false,
1011 // Get a count of how many bytes are to be pushed on the stack.
1012 unsigned NumBytes = CCInfo.getNextStackOffset();
1014 // For tail calls, memory operands are available in our caller's stack.
1018 // Adjust the stack pointer for the new arguments...
1019 // These operations are automatically eliminated by the prolog/epilog pass
1021 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1023 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1025 RegsToPassVector RegsToPass;
1026 SmallVector<SDValue, 8> MemOpChains;
1028 // Walk the register/memloc assignments, inserting copies/loads. In the case
1029 // of tail call optimization, arguments are handled later.
1030 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1032 ++i, ++realArgIdx) {
1033 CCValAssign &VA = ArgLocs[i];
1034 SDValue Arg = OutVals[realArgIdx];
1035 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1037 // Promote the value if needed.
1038 switch (VA.getLocInfo()) {
1039 default: llvm_unreachable("Unknown loc info!");
1040 case CCValAssign::Full: break;
1041 case CCValAssign::SExt:
1042 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1044 case CCValAssign::ZExt:
1045 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1047 case CCValAssign::AExt:
1048 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1050 case CCValAssign::BCvt:
1051 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1055 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1056 if (VA.needsCustom()) {
1057 if (VA.getLocVT() == MVT::v2f64) {
1058 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1059 DAG.getConstant(0, MVT::i32));
1060 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1061 DAG.getConstant(1, MVT::i32));
1063 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1064 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1066 VA = ArgLocs[++i]; // skip ahead to next loc
1067 if (VA.isRegLoc()) {
1068 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1069 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1071 assert(VA.isMemLoc());
1073 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1074 dl, DAG, VA, Flags));
1077 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1078 StackPtr, MemOpChains, Flags);
1080 } else if (VA.isRegLoc()) {
1081 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1082 } else if (!IsSibCall) {
1083 assert(VA.isMemLoc());
1085 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1086 dl, DAG, VA, Flags));
1090 if (!MemOpChains.empty())
1091 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1092 &MemOpChains[0], MemOpChains.size());
1094 // Build a sequence of copy-to-reg nodes chained together with token chain
1095 // and flag operands which copy the outgoing args into the appropriate regs.
1097 // Tail call byval lowering might overwrite argument registers so in case of
1098 // tail call optimization the copies to registers are lowered later.
1100 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1101 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1102 RegsToPass[i].second, InFlag);
1103 InFlag = Chain.getValue(1);
1106 // For tail calls lower the arguments to the 'real' stack slot.
1108 // Force all the incoming stack arguments to be loaded from the stack
1109 // before any new outgoing arguments are stored to the stack, because the
1110 // outgoing stack slots may alias the incoming argument stack slots, and
1111 // the alias isn't otherwise explicit. This is slightly more conservative
1112 // than necessary, because it means that each store effectively depends
1113 // on every argument instead of just those arguments it would clobber.
1115 // Do not flag preceeding copytoreg stuff together with the following stuff.
1117 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1118 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1119 RegsToPass[i].second, InFlag);
1120 InFlag = Chain.getValue(1);
1125 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1126 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1127 // node so that legalize doesn't hack it.
1128 bool isDirect = false;
1129 bool isARMFunc = false;
1130 bool isLocalARMFunc = false;
1131 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1133 if (EnableARMLongCalls) {
1134 assert (getTargetMachine().getRelocationModel() == Reloc::Static
1135 && "long-calls with non-static relocation model!");
1136 // Handle a global address or an external symbol. If it's not one of
1137 // those, the target's already in a register, so we don't need to do
1139 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1140 const GlobalValue *GV = G->getGlobal();
1141 // Create a constant pool entry for the callee address
1142 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1143 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1146 // Get the address of the callee into a register
1147 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1148 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1149 Callee = DAG.getLoad(getPointerTy(), dl,
1150 DAG.getEntryNode(), CPAddr,
1151 MachinePointerInfo::getConstantPool(),
1153 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1154 const char *Sym = S->getSymbol();
1156 // Create a constant pool entry for the callee address
1157 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1158 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1159 Sym, ARMPCLabelIndex, 0);
1160 // Get the address of the callee into a register
1161 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1162 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1163 Callee = DAG.getLoad(getPointerTy(), dl,
1164 DAG.getEntryNode(), CPAddr,
1165 MachinePointerInfo::getConstantPool(),
1168 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1169 const GlobalValue *GV = G->getGlobal();
1171 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1172 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
1173 getTargetMachine().getRelocationModel() != Reloc::Static;
1174 isARMFunc = !Subtarget->isThumb() || isStub;
1175 // ARM call to a local ARM function is predicable.
1176 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
1177 // tBX takes a register source operand.
1178 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1179 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1180 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1183 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1184 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1185 Callee = DAG.getLoad(getPointerTy(), dl,
1186 DAG.getEntryNode(), CPAddr,
1187 MachinePointerInfo::getConstantPool(),
1189 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1190 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1191 getPointerTy(), Callee, PICLabel);
1193 // On ELF targets for PIC code, direct calls should go through the PLT
1194 unsigned OpFlags = 0;
1195 if (Subtarget->isTargetELF() &&
1196 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1197 OpFlags = ARMII::MO_PLT;
1198 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
1200 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1202 bool isStub = Subtarget->isTargetDarwin() &&
1203 getTargetMachine().getRelocationModel() != Reloc::Static;
1204 isARMFunc = !Subtarget->isThumb() || isStub;
1205 // tBX takes a register source operand.
1206 const char *Sym = S->getSymbol();
1207 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1208 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1209 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1210 Sym, ARMPCLabelIndex, 4);
1211 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1212 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1213 Callee = DAG.getLoad(getPointerTy(), dl,
1214 DAG.getEntryNode(), CPAddr,
1215 MachinePointerInfo::getConstantPool(),
1217 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1218 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1219 getPointerTy(), Callee, PICLabel);
1221 unsigned OpFlags = 0;
1222 // On ELF targets for PIC code, direct calls should go through the PLT
1223 if (Subtarget->isTargetELF() &&
1224 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1225 OpFlags = ARMII::MO_PLT;
1226 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags);
1230 // FIXME: handle tail calls differently.
1232 if (Subtarget->isThumb()) {
1233 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1234 CallOpc = ARMISD::CALL_NOLINK;
1236 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1238 CallOpc = (isDirect || Subtarget->hasV5TOps())
1239 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
1240 : ARMISD::CALL_NOLINK;
1243 std::vector<SDValue> Ops;
1244 Ops.push_back(Chain);
1245 Ops.push_back(Callee);
1247 // Add argument registers to the end of the list so that they are known live
1249 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1250 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1251 RegsToPass[i].second.getValueType()));
1253 if (InFlag.getNode())
1254 Ops.push_back(InFlag);
1256 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1258 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
1260 // Returns a chain and a flag for retval copy to use.
1261 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
1262 InFlag = Chain.getValue(1);
1264 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1265 DAG.getIntPtrConstant(0, true), InFlag);
1267 InFlag = Chain.getValue(1);
1269 // Handle result values, copying them out of physregs into vregs that we
1271 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1275 /// MatchingStackOffset - Return true if the given stack call argument is
1276 /// already available in the same position (relatively) of the caller's
1277 /// incoming argument stack.
1279 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1280 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1281 const ARMInstrInfo *TII) {
1282 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
1284 if (Arg.getOpcode() == ISD::CopyFromReg) {
1285 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
1286 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR))
1288 MachineInstr *Def = MRI->getVRegDef(VR);
1291 if (!Flags.isByVal()) {
1292 if (!TII->isLoadFromStackSlot(Def, FI))
1297 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
1298 if (Flags.isByVal())
1299 // ByVal argument is passed in as a pointer but it's now being
1300 // dereferenced. e.g.
1301 // define @foo(%struct.X* %A) {
1302 // tail call @bar(%struct.X* byval %A)
1305 SDValue Ptr = Ld->getBasePtr();
1306 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
1309 FI = FINode->getIndex();
1313 assert(FI != INT_MAX);
1314 if (!MFI->isFixedObjectIndex(FI))
1316 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
1319 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1320 /// for tail call optimization. Targets which want to do tail call
1321 /// optimization should implement this function.
1323 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1324 CallingConv::ID CalleeCC,
1326 bool isCalleeStructRet,
1327 bool isCallerStructRet,
1328 const SmallVectorImpl<ISD::OutputArg> &Outs,
1329 const SmallVectorImpl<SDValue> &OutVals,
1330 const SmallVectorImpl<ISD::InputArg> &Ins,
1331 SelectionDAG& DAG) const {
1332 const Function *CallerF = DAG.getMachineFunction().getFunction();
1333 CallingConv::ID CallerCC = CallerF->getCallingConv();
1334 bool CCMatch = CallerCC == CalleeCC;
1336 // Look for obvious safe cases to perform tail call optimization that do not
1337 // require ABI changes. This is what gcc calls sibcall.
1339 // Do not sibcall optimize vararg calls unless the call site is not passing
1341 if (isVarArg && !Outs.empty())
1344 // Also avoid sibcall optimization if either caller or callee uses struct
1345 // return semantics.
1346 if (isCalleeStructRet || isCallerStructRet)
1349 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
1350 // emitEpilogue is not ready for them.
1351 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
1352 // LR. This means if we need to reload LR, it takes an extra instructions,
1353 // which outweighs the value of the tail call; but here we don't know yet
1354 // whether LR is going to be used. Probably the right approach is to
1355 // generate the tail call here and turn it back into CALL/RET in
1356 // emitEpilogue if LR is used.
1357 if (Subtarget->isThumb1Only())
1360 // For the moment, we can only do this to functions defined in this
1361 // compilation, or to indirect calls. A Thumb B to an ARM function,
1362 // or vice versa, is not easily fixed up in the linker unlike BL.
1363 // (We could do this by loading the address of the callee into a register;
1364 // that is an extra instruction over the direct call and burns a register
1365 // as well, so is not likely to be a win.)
1367 // It might be safe to remove this restriction on non-Darwin.
1369 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
1370 // but we need to make sure there are enough registers; the only valid
1371 // registers are the 4 used for parameters. We don't currently do this
1373 if (isa<ExternalSymbolSDNode>(Callee))
1376 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1377 const GlobalValue *GV = G->getGlobal();
1378 if (GV->isDeclaration() || GV->isWeakForLinker())
1382 // If the calling conventions do not match, then we'd better make sure the
1383 // results are returned in the same way as what the caller expects.
1385 SmallVector<CCValAssign, 16> RVLocs1;
1386 CCState CCInfo1(CalleeCC, false, getTargetMachine(),
1387 RVLocs1, *DAG.getContext());
1388 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
1390 SmallVector<CCValAssign, 16> RVLocs2;
1391 CCState CCInfo2(CallerCC, false, getTargetMachine(),
1392 RVLocs2, *DAG.getContext());
1393 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
1395 if (RVLocs1.size() != RVLocs2.size())
1397 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
1398 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
1400 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
1402 if (RVLocs1[i].isRegLoc()) {
1403 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
1406 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
1412 // If the callee takes no arguments then go on to check the results of the
1414 if (!Outs.empty()) {
1415 // Check if stack adjustment is needed. For now, do not do this if any
1416 // argument is passed on the stack.
1417 SmallVector<CCValAssign, 16> ArgLocs;
1418 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
1419 ArgLocs, *DAG.getContext());
1420 CCInfo.AnalyzeCallOperands(Outs,
1421 CCAssignFnForNode(CalleeCC, false, isVarArg));
1422 if (CCInfo.getNextStackOffset()) {
1423 MachineFunction &MF = DAG.getMachineFunction();
1425 // Check if the arguments are already laid out in the right way as
1426 // the caller's fixed stack objects.
1427 MachineFrameInfo *MFI = MF.getFrameInfo();
1428 const MachineRegisterInfo *MRI = &MF.getRegInfo();
1429 const ARMInstrInfo *TII =
1430 ((ARMTargetMachine&)getTargetMachine()).getInstrInfo();
1431 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1433 ++i, ++realArgIdx) {
1434 CCValAssign &VA = ArgLocs[i];
1435 EVT RegVT = VA.getLocVT();
1436 SDValue Arg = OutVals[realArgIdx];
1437 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1438 if (VA.getLocInfo() == CCValAssign::Indirect)
1440 if (VA.needsCustom()) {
1441 // f64 and vector types are split into multiple registers or
1442 // register/stack-slot combinations. The types will not match
1443 // the registers; give up on memory f64 refs until we figure
1444 // out what to do about this.
1447 if (!ArgLocs[++i].isRegLoc())
1449 if (RegVT == MVT::v2f64) {
1450 if (!ArgLocs[++i].isRegLoc())
1452 if (!ArgLocs[++i].isRegLoc())
1455 } else if (!VA.isRegLoc()) {
1456 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
1468 ARMTargetLowering::LowerReturn(SDValue Chain,
1469 CallingConv::ID CallConv, bool isVarArg,
1470 const SmallVectorImpl<ISD::OutputArg> &Outs,
1471 const SmallVectorImpl<SDValue> &OutVals,
1472 DebugLoc dl, SelectionDAG &DAG) const {
1474 // CCValAssign - represent the assignment of the return value to a location.
1475 SmallVector<CCValAssign, 16> RVLocs;
1477 // CCState - Info about the registers and stack slots.
1478 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
1481 // Analyze outgoing return values.
1482 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1485 // If this is the first return lowered for this function, add
1486 // the regs to the liveout set for the function.
1487 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1488 for (unsigned i = 0; i != RVLocs.size(); ++i)
1489 if (RVLocs[i].isRegLoc())
1490 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1495 // Copy the result values into the output registers.
1496 for (unsigned i = 0, realRVLocIdx = 0;
1498 ++i, ++realRVLocIdx) {
1499 CCValAssign &VA = RVLocs[i];
1500 assert(VA.isRegLoc() && "Can only return in registers!");
1502 SDValue Arg = OutVals[realRVLocIdx];
1504 switch (VA.getLocInfo()) {
1505 default: llvm_unreachable("Unknown loc info!");
1506 case CCValAssign::Full: break;
1507 case CCValAssign::BCvt:
1508 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1512 if (VA.needsCustom()) {
1513 if (VA.getLocVT() == MVT::v2f64) {
1514 // Extract the first half and return it in two registers.
1515 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1516 DAG.getConstant(0, MVT::i32));
1517 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
1518 DAG.getVTList(MVT::i32, MVT::i32), Half);
1520 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1521 Flag = Chain.getValue(1);
1522 VA = RVLocs[++i]; // skip ahead to next loc
1523 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1524 HalfGPRs.getValue(1), Flag);
1525 Flag = Chain.getValue(1);
1526 VA = RVLocs[++i]; // skip ahead to next loc
1528 // Extract the 2nd half and fall through to handle it as an f64 value.
1529 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1530 DAG.getConstant(1, MVT::i32));
1532 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1534 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1535 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1536 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1537 Flag = Chain.getValue(1);
1538 VA = RVLocs[++i]; // skip ahead to next loc
1539 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1542 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1544 // Guarantee that all emitted copies are
1545 // stuck together, avoiding something bad.
1546 Flag = Chain.getValue(1);
1551 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1553 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1558 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1559 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1560 // one of the above mentioned nodes. It has to be wrapped because otherwise
1561 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1562 // be used to form addressing mode. These wrapped nodes will be selected
1564 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1565 EVT PtrVT = Op.getValueType();
1566 // FIXME there is no actual debug info here
1567 DebugLoc dl = Op.getDebugLoc();
1568 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1570 if (CP->isMachineConstantPoolEntry())
1571 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1572 CP->getAlignment());
1574 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1575 CP->getAlignment());
1576 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1579 unsigned ARMTargetLowering::getJumpTableEncoding() const {
1580 return MachineJumpTableInfo::EK_Inline;
1583 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
1584 SelectionDAG &DAG) const {
1585 MachineFunction &MF = DAG.getMachineFunction();
1586 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1587 unsigned ARMPCLabelIndex = 0;
1588 DebugLoc DL = Op.getDebugLoc();
1589 EVT PtrVT = getPointerTy();
1590 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1591 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1593 if (RelocM == Reloc::Static) {
1594 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
1596 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1597 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1598 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(BA, ARMPCLabelIndex,
1599 ARMCP::CPBlockAddress,
1601 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1603 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
1604 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
1605 MachinePointerInfo::getConstantPool(),
1607 if (RelocM == Reloc::Static)
1609 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1610 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
1613 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
1615 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1616 SelectionDAG &DAG) const {
1617 DebugLoc dl = GA->getDebugLoc();
1618 EVT PtrVT = getPointerTy();
1619 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1620 MachineFunction &MF = DAG.getMachineFunction();
1621 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1622 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1623 ARMConstantPoolValue *CPV =
1624 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1625 ARMCP::CPValue, PCAdj, "tlsgd", true);
1626 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1627 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
1628 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
1629 MachinePointerInfo::getConstantPool(),
1631 SDValue Chain = Argument.getValue(1);
1633 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1634 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
1636 // call __tls_get_addr.
1639 Entry.Node = Argument;
1640 Entry.Ty = (const Type *) Type::getInt32Ty(*DAG.getContext());
1641 Args.push_back(Entry);
1642 // FIXME: is there useful debug info available here?
1643 std::pair<SDValue, SDValue> CallResult =
1644 LowerCallTo(Chain, (const Type *) Type::getInt32Ty(*DAG.getContext()),
1645 false, false, false, false,
1646 0, CallingConv::C, false, /*isReturnValueUsed=*/true,
1647 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
1648 return CallResult.first;
1651 // Lower ISD::GlobalTLSAddress using the "initial exec" or
1652 // "local exec" model.
1654 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
1655 SelectionDAG &DAG) const {
1656 const GlobalValue *GV = GA->getGlobal();
1657 DebugLoc dl = GA->getDebugLoc();
1659 SDValue Chain = DAG.getEntryNode();
1660 EVT PtrVT = getPointerTy();
1661 // Get the Thread Pointer
1662 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1664 if (GV->isDeclaration()) {
1665 MachineFunction &MF = DAG.getMachineFunction();
1666 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1667 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1668 // Initial exec model.
1669 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1670 ARMConstantPoolValue *CPV =
1671 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1672 ARMCP::CPValue, PCAdj, "gottpoff", true);
1673 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1674 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1675 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1676 MachinePointerInfo::getConstantPool(),
1678 Chain = Offset.getValue(1);
1680 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1681 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
1683 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1684 MachinePointerInfo::getConstantPool(),
1688 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, "tpoff");
1689 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1690 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1691 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1692 MachinePointerInfo::getConstantPool(),
1696 // The address of the thread local variable is the add of the thread
1697 // pointer with the offset of the variable.
1698 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
1702 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
1703 // TODO: implement the "local dynamic" model
1704 assert(Subtarget->isTargetELF() &&
1705 "TLS not implemented for non-ELF targets");
1706 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1707 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
1708 // otherwise use the "Local Exec" TLS Model
1709 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
1710 return LowerToTLSGeneralDynamicModel(GA, DAG);
1712 return LowerToTLSExecModels(GA, DAG);
1715 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
1716 SelectionDAG &DAG) const {
1717 EVT PtrVT = getPointerTy();
1718 DebugLoc dl = Op.getDebugLoc();
1719 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1720 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1721 if (RelocM == Reloc::PIC_) {
1722 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
1723 ARMConstantPoolValue *CPV =
1724 new ARMConstantPoolValue(GV, UseGOTOFF ? "GOTOFF" : "GOT");
1725 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1726 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1727 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1729 MachinePointerInfo::getConstantPool(),
1731 SDValue Chain = Result.getValue(1);
1732 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1733 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
1735 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
1736 MachinePointerInfo::getGOT(), false, false, 0);
1739 // If we have T2 ops, we can materialize the address directly via movt/movw
1740 // pair. This is always cheaper.
1741 if (Subtarget->useMovt()) {
1742 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
1743 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
1745 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1746 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1747 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1748 MachinePointerInfo::getConstantPool(),
1754 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
1755 SelectionDAG &DAG) const {
1756 MachineFunction &MF = DAG.getMachineFunction();
1757 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1758 unsigned ARMPCLabelIndex = 0;
1759 EVT PtrVT = getPointerTy();
1760 DebugLoc dl = Op.getDebugLoc();
1761 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1762 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1764 if (RelocM == Reloc::Static)
1765 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1767 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1768 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8);
1769 ARMConstantPoolValue *CPV =
1770 new ARMConstantPoolValue(GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj);
1771 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1773 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1775 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1776 MachinePointerInfo::getConstantPool(),
1778 SDValue Chain = Result.getValue(1);
1780 if (RelocM == Reloc::PIC_) {
1781 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1782 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1785 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
1786 Result = DAG.getLoad(PtrVT, dl, Chain, Result, MachinePointerInfo::getGOT(),
1792 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
1793 SelectionDAG &DAG) const {
1794 assert(Subtarget->isTargetELF() &&
1795 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
1796 MachineFunction &MF = DAG.getMachineFunction();
1797 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1798 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1799 EVT PtrVT = getPointerTy();
1800 DebugLoc dl = Op.getDebugLoc();
1801 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1802 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1803 "_GLOBAL_OFFSET_TABLE_",
1804 ARMPCLabelIndex, PCAdj);
1805 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1806 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1807 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1808 MachinePointerInfo::getConstantPool(),
1810 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1811 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1815 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
1816 DebugLoc dl = Op.getDebugLoc();
1817 SDValue Val = DAG.getConstant(0, MVT::i32);
1818 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(0),
1819 Op.getOperand(1), Val);
1823 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
1824 DebugLoc dl = Op.getDebugLoc();
1825 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
1826 Op.getOperand(1), DAG.getConstant(0, MVT::i32));
1830 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
1831 const ARMSubtarget *Subtarget) const {
1832 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1833 DebugLoc dl = Op.getDebugLoc();
1835 default: return SDValue(); // Don't custom lower most intrinsics.
1836 case Intrinsic::arm_thread_pointer: {
1837 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1838 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1840 case Intrinsic::eh_sjlj_lsda: {
1841 MachineFunction &MF = DAG.getMachineFunction();
1842 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1843 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1844 EVT PtrVT = getPointerTy();
1845 DebugLoc dl = Op.getDebugLoc();
1846 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1848 unsigned PCAdj = (RelocM != Reloc::PIC_)
1849 ? 0 : (Subtarget->isThumb() ? 4 : 8);
1850 ARMConstantPoolValue *CPV =
1851 new ARMConstantPoolValue(MF.getFunction(), ARMPCLabelIndex,
1852 ARMCP::CPLSDA, PCAdj);
1853 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1854 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1856 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1857 MachinePointerInfo::getConstantPool(),
1860 if (RelocM == Reloc::PIC_) {
1861 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1862 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1869 static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG,
1870 const ARMSubtarget *Subtarget) {
1871 DebugLoc dl = Op.getDebugLoc();
1872 SDValue Op5 = Op.getOperand(5);
1873 unsigned isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue();
1874 // Some subtargets which have dmb and dsb instructions can handle barriers
1875 // directly. Some ARMv6 cpus can support them with the help of mcr
1876 // instruction. Thumb1 and pre-v6 ARM mode use a libcall instead and should
1878 unsigned Opc = isDeviceBarrier ? ARMISD::SYNCBARRIER : ARMISD::MEMBARRIER;
1879 if (Subtarget->hasDataBarrier())
1880 return DAG.getNode(Opc, dl, MVT::Other, Op.getOperand(0));
1882 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb1Only() &&
1883 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!");
1884 return DAG.getNode(Opc, dl, MVT::Other, Op.getOperand(0),
1885 DAG.getConstant(0, MVT::i32));
1889 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
1890 MachineFunction &MF = DAG.getMachineFunction();
1891 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
1893 // vastart just stores the address of the VarArgsFrameIndex slot into the
1894 // memory location argument.
1895 DebugLoc dl = Op.getDebugLoc();
1896 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1897 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1898 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1899 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
1900 MachinePointerInfo(SV), false, false, 0);
1904 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
1905 SDValue &Root, SelectionDAG &DAG,
1906 DebugLoc dl) const {
1907 MachineFunction &MF = DAG.getMachineFunction();
1908 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1910 TargetRegisterClass *RC;
1911 if (AFI->isThumb1OnlyFunction())
1912 RC = ARM::tGPRRegisterClass;
1914 RC = ARM::GPRRegisterClass;
1916 // Transform the arguments stored in physical registers into virtual ones.
1917 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1918 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
1921 if (NextVA.isMemLoc()) {
1922 MachineFrameInfo *MFI = MF.getFrameInfo();
1923 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
1925 // Create load node to retrieve arguments from the stack.
1926 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1927 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
1928 MachinePointerInfo::getFixedStack(FI),
1931 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
1932 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
1935 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
1939 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
1940 CallingConv::ID CallConv, bool isVarArg,
1941 const SmallVectorImpl<ISD::InputArg>
1943 DebugLoc dl, SelectionDAG &DAG,
1944 SmallVectorImpl<SDValue> &InVals)
1947 MachineFunction &MF = DAG.getMachineFunction();
1948 MachineFrameInfo *MFI = MF.getFrameInfo();
1950 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1952 // Assign locations to all of the incoming arguments.
1953 SmallVector<CCValAssign, 16> ArgLocs;
1954 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1956 CCInfo.AnalyzeFormalArguments(Ins,
1957 CCAssignFnForNode(CallConv, /* Return*/ false,
1960 SmallVector<SDValue, 16> ArgValues;
1962 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1963 CCValAssign &VA = ArgLocs[i];
1965 // Arguments stored in registers.
1966 if (VA.isRegLoc()) {
1967 EVT RegVT = VA.getLocVT();
1970 if (VA.needsCustom()) {
1971 // f64 and vector types are split up into multiple registers or
1972 // combinations of registers and stack slots.
1973 if (VA.getLocVT() == MVT::v2f64) {
1974 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
1976 VA = ArgLocs[++i]; // skip ahead to next loc
1978 if (VA.isMemLoc()) {
1979 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
1980 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1981 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
1982 MachinePointerInfo::getFixedStack(FI),
1985 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
1988 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1989 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
1990 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
1991 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
1992 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
1994 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
1997 TargetRegisterClass *RC;
1999 if (RegVT == MVT::f32)
2000 RC = ARM::SPRRegisterClass;
2001 else if (RegVT == MVT::f64)
2002 RC = ARM::DPRRegisterClass;
2003 else if (RegVT == MVT::v2f64)
2004 RC = ARM::QPRRegisterClass;
2005 else if (RegVT == MVT::i32)
2006 RC = (AFI->isThumb1OnlyFunction() ?
2007 ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
2009 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2011 // Transform the arguments in physical registers into virtual ones.
2012 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2013 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2016 // If this is an 8 or 16-bit value, it is really passed promoted
2017 // to 32 bits. Insert an assert[sz]ext to capture this, then
2018 // truncate to the right size.
2019 switch (VA.getLocInfo()) {
2020 default: llvm_unreachable("Unknown loc info!");
2021 case CCValAssign::Full: break;
2022 case CCValAssign::BCvt:
2023 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
2025 case CCValAssign::SExt:
2026 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2027 DAG.getValueType(VA.getValVT()));
2028 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2030 case CCValAssign::ZExt:
2031 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2032 DAG.getValueType(VA.getValVT()));
2033 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2037 InVals.push_back(ArgValue);
2039 } else { // VA.isRegLoc()
2042 assert(VA.isMemLoc());
2043 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
2045 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
2046 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(), true);
2048 // Create load nodes to retrieve arguments from the stack.
2049 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2050 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2051 MachinePointerInfo::getFixedStack(FI),
2058 static const unsigned GPRArgRegs[] = {
2059 ARM::R0, ARM::R1, ARM::R2, ARM::R3
2062 unsigned NumGPRs = CCInfo.getFirstUnallocated
2063 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
2065 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
2066 unsigned VARegSize = (4 - NumGPRs) * 4;
2067 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
2068 unsigned ArgOffset = CCInfo.getNextStackOffset();
2069 if (VARegSaveSize) {
2070 // If this function is vararg, store any remaining integer argument regs
2071 // to their spots on the stack so that they may be loaded by deferencing
2072 // the result of va_next.
2073 AFI->setVarArgsRegSaveSize(VARegSaveSize);
2074 AFI->setVarArgsFrameIndex(
2075 MFI->CreateFixedObject(VARegSaveSize,
2076 ArgOffset + VARegSaveSize - VARegSize,
2078 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(),
2081 SmallVector<SDValue, 4> MemOps;
2082 for (; NumGPRs < 4; ++NumGPRs) {
2083 TargetRegisterClass *RC;
2084 if (AFI->isThumb1OnlyFunction())
2085 RC = ARM::tGPRRegisterClass;
2087 RC = ARM::GPRRegisterClass;
2089 unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
2090 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2092 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2093 MachinePointerInfo::getFixedStack(AFI->getVarArgsFrameIndex()),
2095 MemOps.push_back(Store);
2096 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
2097 DAG.getConstant(4, getPointerTy()));
2099 if (!MemOps.empty())
2100 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2101 &MemOps[0], MemOps.size());
2103 // This will point to the next argument passed via stack.
2104 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset, true));
2110 /// isFloatingPointZero - Return true if this is +0.0.
2111 static bool isFloatingPointZero(SDValue Op) {
2112 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
2113 return CFP->getValueAPF().isPosZero();
2114 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
2115 // Maybe this has already been legalized into the constant pool?
2116 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
2117 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
2118 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
2119 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
2120 return CFP->getValueAPF().isPosZero();
2126 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
2127 /// the given operands.
2129 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2130 SDValue &ARMcc, SelectionDAG &DAG,
2131 DebugLoc dl) const {
2132 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
2133 unsigned C = RHSC->getZExtValue();
2134 if (!isLegalICmpImmediate(C)) {
2135 // Constant does not fit, try adjusting it by one?
2140 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
2141 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
2142 RHS = DAG.getConstant(C-1, MVT::i32);
2147 if (C != 0 && isLegalICmpImmediate(C-1)) {
2148 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
2149 RHS = DAG.getConstant(C-1, MVT::i32);
2154 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
2155 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
2156 RHS = DAG.getConstant(C+1, MVT::i32);
2161 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
2162 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2163 RHS = DAG.getConstant(C+1, MVT::i32);
2170 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2171 ARMISD::NodeType CompareType;
2174 CompareType = ARMISD::CMP;
2179 CompareType = ARMISD::CMPZ;
2182 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2183 return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS);
2186 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
2188 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
2189 DebugLoc dl) const {
2191 if (!isFloatingPointZero(RHS))
2192 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS);
2194 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS);
2195 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp);
2198 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2199 SDValue Cond = Op.getOperand(0);
2200 SDValue SelectTrue = Op.getOperand(1);
2201 SDValue SelectFalse = Op.getOperand(2);
2202 DebugLoc dl = Op.getDebugLoc();
2206 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
2207 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
2209 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
2210 const ConstantSDNode *CMOVTrue =
2211 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
2212 const ConstantSDNode *CMOVFalse =
2213 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
2215 if (CMOVTrue && CMOVFalse) {
2216 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
2217 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
2221 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
2223 False = SelectFalse;
2224 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
2229 if (True.getNode() && False.getNode()) {
2230 EVT VT = Cond.getValueType();
2231 SDValue ARMcc = Cond.getOperand(2);
2232 SDValue CCR = Cond.getOperand(3);
2233 SDValue Cmp = Cond.getOperand(4);
2234 return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp);
2239 return DAG.getSelectCC(dl, Cond,
2240 DAG.getConstant(0, Cond.getValueType()),
2241 SelectTrue, SelectFalse, ISD::SETNE);
2244 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
2245 EVT VT = Op.getValueType();
2246 SDValue LHS = Op.getOperand(0);
2247 SDValue RHS = Op.getOperand(1);
2248 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2249 SDValue TrueVal = Op.getOperand(2);
2250 SDValue FalseVal = Op.getOperand(3);
2251 DebugLoc dl = Op.getDebugLoc();
2253 if (LHS.getValueType() == MVT::i32) {
2255 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2256 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2257 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,Cmp);
2260 ARMCC::CondCodes CondCode, CondCode2;
2261 FPCCToARMCC(CC, CondCode, CondCode2);
2263 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2264 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2265 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2266 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
2268 if (CondCode2 != ARMCC::AL) {
2269 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32);
2270 // FIXME: Needs another CMP because flag can have but one use.
2271 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
2272 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
2273 Result, TrueVal, ARMcc2, CCR, Cmp2);
2278 /// canChangeToInt - Given the fp compare operand, return true if it is suitable
2279 /// to morph to an integer compare sequence.
2280 static bool canChangeToInt(SDValue Op, bool &SeenZero,
2281 const ARMSubtarget *Subtarget) {
2282 SDNode *N = Op.getNode();
2283 if (!N->hasOneUse())
2284 // Otherwise it requires moving the value from fp to integer registers.
2286 if (!N->getNumValues())
2288 EVT VT = Op.getValueType();
2289 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
2290 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
2291 // vmrs are very slow, e.g. cortex-a8.
2294 if (isFloatingPointZero(Op)) {
2298 return ISD::isNormalLoad(N);
2301 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
2302 if (isFloatingPointZero(Op))
2303 return DAG.getConstant(0, MVT::i32);
2305 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
2306 return DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2307 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(),
2308 Ld->isVolatile(), Ld->isNonTemporal(),
2309 Ld->getAlignment());
2311 llvm_unreachable("Unknown VFP cmp argument!");
2314 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
2315 SDValue &RetVal1, SDValue &RetVal2) {
2316 if (isFloatingPointZero(Op)) {
2317 RetVal1 = DAG.getConstant(0, MVT::i32);
2318 RetVal2 = DAG.getConstant(0, MVT::i32);
2322 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
2323 SDValue Ptr = Ld->getBasePtr();
2324 RetVal1 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2325 Ld->getChain(), Ptr,
2326 Ld->getPointerInfo(),
2327 Ld->isVolatile(), Ld->isNonTemporal(),
2328 Ld->getAlignment());
2330 EVT PtrType = Ptr.getValueType();
2331 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
2332 SDValue NewPtr = DAG.getNode(ISD::ADD, Op.getDebugLoc(),
2333 PtrType, Ptr, DAG.getConstant(4, PtrType));
2334 RetVal2 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2335 Ld->getChain(), NewPtr,
2336 Ld->getPointerInfo().getWithOffset(4),
2337 Ld->isVolatile(), Ld->isNonTemporal(),
2342 llvm_unreachable("Unknown VFP cmp argument!");
2345 /// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
2346 /// f32 and even f64 comparisons to integer ones.
2348 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
2349 SDValue Chain = Op.getOperand(0);
2350 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2351 SDValue LHS = Op.getOperand(2);
2352 SDValue RHS = Op.getOperand(3);
2353 SDValue Dest = Op.getOperand(4);
2354 DebugLoc dl = Op.getDebugLoc();
2356 bool SeenZero = false;
2357 if (canChangeToInt(LHS, SeenZero, Subtarget) &&
2358 canChangeToInt(RHS, SeenZero, Subtarget) &&
2359 // If one of the operand is zero, it's safe to ignore the NaN case since
2360 // we only care about equality comparisons.
2361 (SeenZero || (DAG.isKnownNeverNaN(LHS) && DAG.isKnownNeverNaN(RHS)))) {
2362 // If unsafe fp math optimization is enabled and there are no othter uses of
2363 // the CMP operands, and the condition code is EQ oe NE, we can optimize it
2364 // to an integer comparison.
2365 if (CC == ISD::SETOEQ)
2367 else if (CC == ISD::SETUNE)
2371 if (LHS.getValueType() == MVT::f32) {
2372 LHS = bitcastf32Toi32(LHS, DAG);
2373 RHS = bitcastf32Toi32(RHS, DAG);
2374 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2375 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2376 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2377 Chain, Dest, ARMcc, CCR, Cmp);
2382 expandf64Toi32(LHS, DAG, LHS1, LHS2);
2383 expandf64Toi32(RHS, DAG, RHS1, RHS2);
2384 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2385 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2386 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
2387 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
2388 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7);
2394 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2395 SDValue Chain = Op.getOperand(0);
2396 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2397 SDValue LHS = Op.getOperand(2);
2398 SDValue RHS = Op.getOperand(3);
2399 SDValue Dest = Op.getOperand(4);
2400 DebugLoc dl = Op.getDebugLoc();
2402 if (LHS.getValueType() == MVT::i32) {
2404 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2405 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2406 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2407 Chain, Dest, ARMcc, CCR, Cmp);
2410 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
2413 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
2414 CC == ISD::SETNE || CC == ISD::SETUNE)) {
2415 SDValue Result = OptimizeVFPBrcond(Op, DAG);
2416 if (Result.getNode())
2420 ARMCC::CondCodes CondCode, CondCode2;
2421 FPCCToARMCC(CC, CondCode, CondCode2);
2423 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2424 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2425 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2426 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
2427 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
2428 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2429 if (CondCode2 != ARMCC::AL) {
2430 ARMcc = DAG.getConstant(CondCode2, MVT::i32);
2431 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
2432 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2437 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
2438 SDValue Chain = Op.getOperand(0);
2439 SDValue Table = Op.getOperand(1);
2440 SDValue Index = Op.getOperand(2);
2441 DebugLoc dl = Op.getDebugLoc();
2443 EVT PTy = getPointerTy();
2444 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
2445 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
2446 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
2447 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
2448 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
2449 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
2450 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2451 if (Subtarget->isThumb2()) {
2452 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
2453 // which does another jump to the destination. This also makes it easier
2454 // to translate it to TBB / TBH later.
2455 // FIXME: This might not work if the function is extremely large.
2456 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
2457 Addr, Op.getOperand(2), JTI, UId);
2459 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2460 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
2461 MachinePointerInfo::getJumpTable(),
2463 Chain = Addr.getValue(1);
2464 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
2465 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2467 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
2468 MachinePointerInfo::getJumpTable(), false, false, 0);
2469 Chain = Addr.getValue(1);
2470 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2474 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
2475 DebugLoc dl = Op.getDebugLoc();
2478 switch (Op.getOpcode()) {
2480 assert(0 && "Invalid opcode!");
2481 case ISD::FP_TO_SINT:
2482 Opc = ARMISD::FTOSI;
2484 case ISD::FP_TO_UINT:
2485 Opc = ARMISD::FTOUI;
2488 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
2489 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
2492 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
2493 EVT VT = Op.getValueType();
2494 DebugLoc dl = Op.getDebugLoc();
2497 switch (Op.getOpcode()) {
2499 assert(0 && "Invalid opcode!");
2500 case ISD::SINT_TO_FP:
2501 Opc = ARMISD::SITOF;
2503 case ISD::UINT_TO_FP:
2504 Opc = ARMISD::UITOF;
2508 Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
2509 return DAG.getNode(Opc, dl, VT, Op);
2512 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
2513 // Implement fcopysign with a fabs and a conditional fneg.
2514 SDValue Tmp0 = Op.getOperand(0);
2515 SDValue Tmp1 = Op.getOperand(1);
2516 DebugLoc dl = Op.getDebugLoc();
2517 EVT VT = Op.getValueType();
2518 EVT SrcVT = Tmp1.getValueType();
2519 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
2520 SDValue ARMcc = DAG.getConstant(ARMCC::LT, MVT::i32);
2521 SDValue FP0 = DAG.getConstantFP(0.0, SrcVT);
2522 SDValue Cmp = getVFPCmp(Tmp1, FP0, DAG, dl);
2523 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2524 return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMcc, CCR, Cmp);
2527 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
2528 MachineFunction &MF = DAG.getMachineFunction();
2529 MachineFrameInfo *MFI = MF.getFrameInfo();
2530 MFI->setReturnAddressIsTaken(true);
2532 EVT VT = Op.getValueType();
2533 DebugLoc dl = Op.getDebugLoc();
2534 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2536 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
2537 SDValue Offset = DAG.getConstant(4, MVT::i32);
2538 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
2539 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
2540 MachinePointerInfo(), false, false, 0);
2543 // Return LR, which contains the return address. Mark it an implicit live-in.
2544 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
2545 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
2548 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2549 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2550 MFI->setFrameAddressIsTaken(true);
2552 EVT VT = Op.getValueType();
2553 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
2554 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2555 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
2556 ? ARM::R7 : ARM::R11;
2557 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
2559 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
2560 MachinePointerInfo(),
2565 /// ExpandBIT_CONVERT - If the target supports VFP, this function is called to
2566 /// expand a bit convert where either the source or destination type is i64 to
2567 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
2568 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
2569 /// vectors), since the legalizer won't know what to do with that.
2570 static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
2571 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2572 DebugLoc dl = N->getDebugLoc();
2573 SDValue Op = N->getOperand(0);
2575 // This function is only supposed to be called for i64 types, either as the
2576 // source or destination of the bit convert.
2577 EVT SrcVT = Op.getValueType();
2578 EVT DstVT = N->getValueType(0);
2579 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
2580 "ExpandBIT_CONVERT called for non-i64 type");
2582 // Turn i64->f64 into VMOVDRR.
2583 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
2584 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2585 DAG.getConstant(0, MVT::i32));
2586 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2587 DAG.getConstant(1, MVT::i32));
2588 return DAG.getNode(ISD::BIT_CONVERT, dl, DstVT,
2589 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
2592 // Turn f64->i64 into VMOVRRD.
2593 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
2594 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
2595 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
2596 // Merge the pieces into a single i64 value.
2597 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
2603 /// getZeroVector - Returns a vector of specified type with all zero elements.
2604 /// Zero vectors are used to represent vector negation and in those cases
2605 /// will be implemented with the NEON VNEG instruction. However, VNEG does
2606 /// not support i64 elements, so sometimes the zero vectors will need to be
2607 /// explicitly constructed. Regardless, use a canonical VMOV to create the
2609 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2610 assert(VT.isVector() && "Expected a vector type");
2611 // The canonical modified immediate encoding of a zero vector is....0!
2612 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32);
2613 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
2614 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
2615 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov);
2618 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
2619 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2620 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
2621 SelectionDAG &DAG) const {
2622 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2623 EVT VT = Op.getValueType();
2624 unsigned VTBits = VT.getSizeInBits();
2625 DebugLoc dl = Op.getDebugLoc();
2626 SDValue ShOpLo = Op.getOperand(0);
2627 SDValue ShOpHi = Op.getOperand(1);
2628 SDValue ShAmt = Op.getOperand(2);
2630 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
2632 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
2634 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2635 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2636 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
2637 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2638 DAG.getConstant(VTBits, MVT::i32));
2639 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
2640 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2641 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
2643 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2644 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
2646 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
2647 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
2650 SDValue Ops[2] = { Lo, Hi };
2651 return DAG.getMergeValues(Ops, 2, dl);
2654 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
2655 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2656 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
2657 SelectionDAG &DAG) const {
2658 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2659 EVT VT = Op.getValueType();
2660 unsigned VTBits = VT.getSizeInBits();
2661 DebugLoc dl = Op.getDebugLoc();
2662 SDValue ShOpLo = Op.getOperand(0);
2663 SDValue ShOpHi = Op.getOperand(1);
2664 SDValue ShAmt = Op.getOperand(2);
2667 assert(Op.getOpcode() == ISD::SHL_PARTS);
2668 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2669 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2670 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
2671 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2672 DAG.getConstant(VTBits, MVT::i32));
2673 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
2674 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
2676 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2677 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2678 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
2680 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
2681 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
2684 SDValue Ops[2] = { Lo, Hi };
2685 return DAG.getMergeValues(Ops, 2, dl);
2688 SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
2689 SelectionDAG &DAG) const {
2690 // The rounding mode is in bits 23:22 of the FPSCR.
2691 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
2692 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
2693 // so that the shift + and get folded into a bitfield extract.
2694 DebugLoc dl = Op.getDebugLoc();
2695 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
2696 DAG.getConstant(Intrinsic::arm_get_fpscr,
2698 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
2699 DAG.getConstant(1U << 22, MVT::i32));
2700 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
2701 DAG.getConstant(22, MVT::i32));
2702 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
2703 DAG.getConstant(3, MVT::i32));
2706 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
2707 const ARMSubtarget *ST) {
2708 EVT VT = N->getValueType(0);
2709 DebugLoc dl = N->getDebugLoc();
2711 if (!ST->hasV6T2Ops())
2714 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
2715 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
2718 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
2719 const ARMSubtarget *ST) {
2720 EVT VT = N->getValueType(0);
2721 DebugLoc dl = N->getDebugLoc();
2723 // Lower vector shifts on NEON to use VSHL.
2724 if (VT.isVector()) {
2725 assert(ST->hasNEON() && "unexpected vector shift");
2727 // Left shifts translate directly to the vshiftu intrinsic.
2728 if (N->getOpcode() == ISD::SHL)
2729 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2730 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
2731 N->getOperand(0), N->getOperand(1));
2733 assert((N->getOpcode() == ISD::SRA ||
2734 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
2736 // NEON uses the same intrinsics for both left and right shifts. For
2737 // right shifts, the shift amounts are negative, so negate the vector of
2739 EVT ShiftVT = N->getOperand(1).getValueType();
2740 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
2741 getZeroVector(ShiftVT, DAG, dl),
2743 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
2744 Intrinsic::arm_neon_vshifts :
2745 Intrinsic::arm_neon_vshiftu);
2746 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2747 DAG.getConstant(vshiftInt, MVT::i32),
2748 N->getOperand(0), NegatedCount);
2751 // We can get here for a node like i32 = ISD::SHL i32, i64
2755 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
2756 "Unknown shift to lower!");
2758 // We only lower SRA, SRL of 1 here, all others use generic lowering.
2759 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
2760 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
2763 // If we are in thumb mode, we don't have RRX.
2764 if (ST->isThumb1Only()) return SDValue();
2766 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
2767 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2768 DAG.getConstant(0, MVT::i32));
2769 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2770 DAG.getConstant(1, MVT::i32));
2772 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
2773 // captures the result into a carry flag.
2774 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
2775 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
2777 // The low part is an ARMISD::RRX operand, which shifts the carry in.
2778 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
2780 // Merge the pieces into a single i64 value.
2781 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
2784 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
2785 SDValue TmpOp0, TmpOp1;
2786 bool Invert = false;
2790 SDValue Op0 = Op.getOperand(0);
2791 SDValue Op1 = Op.getOperand(1);
2792 SDValue CC = Op.getOperand(2);
2793 EVT VT = Op.getValueType();
2794 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
2795 DebugLoc dl = Op.getDebugLoc();
2797 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
2798 switch (SetCCOpcode) {
2799 default: llvm_unreachable("Illegal FP comparison"); break;
2801 case ISD::SETNE: Invert = true; // Fallthrough
2803 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2805 case ISD::SETLT: Swap = true; // Fallthrough
2807 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2809 case ISD::SETLE: Swap = true; // Fallthrough
2811 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2812 case ISD::SETUGE: Swap = true; // Fallthrough
2813 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
2814 case ISD::SETUGT: Swap = true; // Fallthrough
2815 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
2816 case ISD::SETUEQ: Invert = true; // Fallthrough
2818 // Expand this to (OLT | OGT).
2822 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2823 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
2825 case ISD::SETUO: Invert = true; // Fallthrough
2827 // Expand this to (OLT | OGE).
2831 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2832 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
2836 // Integer comparisons.
2837 switch (SetCCOpcode) {
2838 default: llvm_unreachable("Illegal integer comparison"); break;
2839 case ISD::SETNE: Invert = true;
2840 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2841 case ISD::SETLT: Swap = true;
2842 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2843 case ISD::SETLE: Swap = true;
2844 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2845 case ISD::SETULT: Swap = true;
2846 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
2847 case ISD::SETULE: Swap = true;
2848 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
2851 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
2852 if (Opc == ARMISD::VCEQ) {
2855 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
2857 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
2860 // Ignore bitconvert.
2861 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BIT_CONVERT)
2862 AndOp = AndOp.getOperand(0);
2864 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
2866 Op0 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(0));
2867 Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(1));
2874 std::swap(Op0, Op1);
2876 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
2879 Result = DAG.getNOT(dl, Result, VT);
2884 /// isNEONModifiedImm - Check if the specified splat value corresponds to a
2885 /// valid vector constant for a NEON instruction with a "modified immediate"
2886 /// operand (e.g., VMOV). If so, return the encoded value.
2887 static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
2888 unsigned SplatBitSize, SelectionDAG &DAG,
2889 EVT &VT, bool is128Bits, bool isVMOV) {
2890 unsigned OpCmode, Imm;
2892 // SplatBitSize is set to the smallest size that splats the vector, so a
2893 // zero vector will always have SplatBitSize == 8. However, NEON modified
2894 // immediate instructions others than VMOV do not support the 8-bit encoding
2895 // of a zero vector, and the default encoding of zero is supposed to be the
2900 switch (SplatBitSize) {
2904 // Any 1-byte value is OK. Op=0, Cmode=1110.
2905 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
2908 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
2912 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
2913 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
2914 if ((SplatBits & ~0xff) == 0) {
2915 // Value = 0x00nn: Op=x, Cmode=100x.
2920 if ((SplatBits & ~0xff00) == 0) {
2921 // Value = 0xnn00: Op=x, Cmode=101x.
2923 Imm = SplatBits >> 8;
2929 // NEON's 32-bit VMOV supports splat values where:
2930 // * only one byte is nonzero, or
2931 // * the least significant byte is 0xff and the second byte is nonzero, or
2932 // * the least significant 2 bytes are 0xff and the third is nonzero.
2933 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
2934 if ((SplatBits & ~0xff) == 0) {
2935 // Value = 0x000000nn: Op=x, Cmode=000x.
2940 if ((SplatBits & ~0xff00) == 0) {
2941 // Value = 0x0000nn00: Op=x, Cmode=001x.
2943 Imm = SplatBits >> 8;
2946 if ((SplatBits & ~0xff0000) == 0) {
2947 // Value = 0x00nn0000: Op=x, Cmode=010x.
2949 Imm = SplatBits >> 16;
2952 if ((SplatBits & ~0xff000000) == 0) {
2953 // Value = 0xnn000000: Op=x, Cmode=011x.
2955 Imm = SplatBits >> 24;
2959 if ((SplatBits & ~0xffff) == 0 &&
2960 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
2961 // Value = 0x0000nnff: Op=x, Cmode=1100.
2963 Imm = SplatBits >> 8;
2968 if ((SplatBits & ~0xffffff) == 0 &&
2969 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
2970 // Value = 0x00nnffff: Op=x, Cmode=1101.
2972 Imm = SplatBits >> 16;
2973 SplatBits |= 0xffff;
2977 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
2978 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
2979 // VMOV.I32. A (very) minor optimization would be to replicate the value
2980 // and fall through here to test for a valid 64-bit splat. But, then the
2981 // caller would also need to check and handle the change in size.
2987 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
2988 uint64_t BitMask = 0xff;
2990 unsigned ImmMask = 1;
2992 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
2993 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
2996 } else if ((SplatBits & BitMask) != 0) {
3002 // Op=1, Cmode=1110.
3005 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
3010 llvm_unreachable("unexpected size for isNEONModifiedImm");
3014 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
3015 return DAG.getTargetConstant(EncodedVal, MVT::i32);
3018 static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT,
3019 bool &ReverseVEXT, unsigned &Imm) {
3020 unsigned NumElts = VT.getVectorNumElements();
3021 ReverseVEXT = false;
3023 // Assume that the first shuffle index is not UNDEF. Fail if it is.
3029 // If this is a VEXT shuffle, the immediate value is the index of the first
3030 // element. The other shuffle indices must be the successive elements after
3032 unsigned ExpectedElt = Imm;
3033 for (unsigned i = 1; i < NumElts; ++i) {
3034 // Increment the expected index. If it wraps around, it may still be
3035 // a VEXT but the source vectors must be swapped.
3037 if (ExpectedElt == NumElts * 2) {
3042 if (M[i] < 0) continue; // ignore UNDEF indices
3043 if (ExpectedElt != static_cast<unsigned>(M[i]))
3047 // Adjust the index value if the source operands will be swapped.
3054 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
3055 /// instruction with the specified blocksize. (The order of the elements
3056 /// within each block of the vector is reversed.)
3057 static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT,
3058 unsigned BlockSize) {
3059 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
3060 "Only possible block sizes for VREV are: 16, 32, 64");
3062 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3066 unsigned NumElts = VT.getVectorNumElements();
3067 unsigned BlockElts = M[0] + 1;
3068 // If the first shuffle index is UNDEF, be optimistic.
3070 BlockElts = BlockSize / EltSz;
3072 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
3075 for (unsigned i = 0; i < NumElts; ++i) {
3076 if (M[i] < 0) continue; // ignore UNDEF indices
3077 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
3084 static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT,
3085 unsigned &WhichResult) {
3086 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3090 unsigned NumElts = VT.getVectorNumElements();
3091 WhichResult = (M[0] == 0 ? 0 : 1);
3092 for (unsigned i = 0; i < NumElts; i += 2) {
3093 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3094 (M[i+1] >= 0 && (unsigned) M[i+1] != i + NumElts + WhichResult))
3100 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
3101 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3102 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
3103 static bool isVTRN_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3104 unsigned &WhichResult) {
3105 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3109 unsigned NumElts = VT.getVectorNumElements();
3110 WhichResult = (M[0] == 0 ? 0 : 1);
3111 for (unsigned i = 0; i < NumElts; i += 2) {
3112 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3113 (M[i+1] >= 0 && (unsigned) M[i+1] != i + WhichResult))
3119 static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT,
3120 unsigned &WhichResult) {
3121 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3125 unsigned NumElts = VT.getVectorNumElements();
3126 WhichResult = (M[0] == 0 ? 0 : 1);
3127 for (unsigned i = 0; i != NumElts; ++i) {
3128 if (M[i] < 0) continue; // ignore UNDEF indices
3129 if ((unsigned) M[i] != 2 * i + WhichResult)
3133 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3134 if (VT.is64BitVector() && EltSz == 32)
3140 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
3141 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3142 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
3143 static bool isVUZP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3144 unsigned &WhichResult) {
3145 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3149 unsigned Half = VT.getVectorNumElements() / 2;
3150 WhichResult = (M[0] == 0 ? 0 : 1);
3151 for (unsigned j = 0; j != 2; ++j) {
3152 unsigned Idx = WhichResult;
3153 for (unsigned i = 0; i != Half; ++i) {
3154 int MIdx = M[i + j * Half];
3155 if (MIdx >= 0 && (unsigned) MIdx != Idx)
3161 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3162 if (VT.is64BitVector() && EltSz == 32)
3168 static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT,
3169 unsigned &WhichResult) {
3170 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3174 unsigned NumElts = VT.getVectorNumElements();
3175 WhichResult = (M[0] == 0 ? 0 : 1);
3176 unsigned Idx = WhichResult * NumElts / 2;
3177 for (unsigned i = 0; i != NumElts; i += 2) {
3178 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3179 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts))
3184 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3185 if (VT.is64BitVector() && EltSz == 32)
3191 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
3192 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3193 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
3194 static bool isVZIP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3195 unsigned &WhichResult) {
3196 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3200 unsigned NumElts = VT.getVectorNumElements();
3201 WhichResult = (M[0] == 0 ? 0 : 1);
3202 unsigned Idx = WhichResult * NumElts / 2;
3203 for (unsigned i = 0; i != NumElts; i += 2) {
3204 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3205 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx))
3210 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3211 if (VT.is64BitVector() && EltSz == 32)
3217 // If N is an integer constant that can be moved into a register in one
3218 // instruction, return an SDValue of such a constant (will become a MOV
3219 // instruction). Otherwise return null.
3220 static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG,
3221 const ARMSubtarget *ST, DebugLoc dl) {
3223 if (!isa<ConstantSDNode>(N))
3225 Val = cast<ConstantSDNode>(N)->getZExtValue();
3227 if (ST->isThumb1Only()) {
3228 if (Val <= 255 || ~Val <= 255)
3229 return DAG.getConstant(Val, MVT::i32);
3231 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1)
3232 return DAG.getConstant(Val, MVT::i32);
3237 // If this is a case we can't handle, return null and let the default
3238 // expansion code take care of it.
3239 static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
3240 const ARMSubtarget *ST) {
3241 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
3242 DebugLoc dl = Op.getDebugLoc();
3243 EVT VT = Op.getValueType();
3245 APInt SplatBits, SplatUndef;
3246 unsigned SplatBitSize;
3248 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
3249 if (SplatBitSize <= 64) {
3250 // Check if an immediate VMOV works.
3252 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
3253 SplatUndef.getZExtValue(), SplatBitSize,
3254 DAG, VmovVT, VT.is128BitVector(), true);
3255 if (Val.getNode()) {
3256 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
3257 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov);
3260 // Try an immediate VMVN.
3261 uint64_t NegatedImm = (SplatBits.getZExtValue() ^
3262 ((1LL << SplatBitSize) - 1));
3263 Val = isNEONModifiedImm(NegatedImm,
3264 SplatUndef.getZExtValue(), SplatBitSize,
3265 DAG, VmovVT, VT.is128BitVector(), false);
3266 if (Val.getNode()) {
3267 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
3268 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov);
3273 // Scan through the operands to see if only one value is used.
3274 unsigned NumElts = VT.getVectorNumElements();
3275 bool isOnlyLowElement = true;
3276 bool usesOnlyOneValue = true;
3277 bool isConstant = true;
3279 for (unsigned i = 0; i < NumElts; ++i) {
3280 SDValue V = Op.getOperand(i);
3281 if (V.getOpcode() == ISD::UNDEF)
3284 isOnlyLowElement = false;
3285 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
3288 if (!Value.getNode())
3290 else if (V != Value)
3291 usesOnlyOneValue = false;
3294 if (!Value.getNode())
3295 return DAG.getUNDEF(VT);
3297 if (isOnlyLowElement)
3298 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
3300 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3302 if (EnableARMVDUPsplat) {
3303 // Use VDUP for non-constant splats. For f32 constant splats, reduce to
3304 // i32 and try again.
3305 if (usesOnlyOneValue && EltSize <= 32) {
3307 return DAG.getNode(ARMISD::VDUP, dl, VT, Value);
3308 if (VT.getVectorElementType().isFloatingPoint()) {
3309 SmallVector<SDValue, 8> Ops;
3310 for (unsigned i = 0; i < NumElts; ++i)
3311 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32,
3313 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, &Ops[0],
3315 return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
3316 LowerBUILD_VECTOR(Val, DAG, ST));
3318 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
3320 return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
3324 // If all elements are constants and the case above didn't get hit, fall back
3325 // to the default expansion, which will generate a load from the constant
3330 if (!EnableARMVDUPsplat) {
3331 // Use VDUP for non-constant splats.
3332 if (usesOnlyOneValue && EltSize <= 32)
3333 return DAG.getNode(ARMISD::VDUP, dl, VT, Value);
3336 // Vectors with 32- or 64-bit elements can be built by directly assigning
3337 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
3338 // will be legalized.
3339 if (EltSize >= 32) {
3340 // Do the expansion with floating-point types, since that is what the VFP
3341 // registers are defined to use, and since i64 is not legal.
3342 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3343 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3344 SmallVector<SDValue, 8> Ops;
3345 for (unsigned i = 0; i < NumElts; ++i)
3346 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, EltVT, Op.getOperand(i)));
3347 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
3348 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val);
3354 /// isShuffleMaskLegal - Targets can use this to indicate that they only
3355 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
3356 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
3357 /// are assumed to be legal.
3359 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
3361 if (VT.getVectorNumElements() == 4 &&
3362 (VT.is128BitVector() || VT.is64BitVector())) {
3363 unsigned PFIndexes[4];
3364 for (unsigned i = 0; i != 4; ++i) {
3368 PFIndexes[i] = M[i];
3371 // Compute the index in the perfect shuffle table.
3372 unsigned PFTableIndex =
3373 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3374 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3375 unsigned Cost = (PFEntry >> 30);
3382 unsigned Imm, WhichResult;
3384 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3385 return (EltSize >= 32 ||
3386 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
3387 isVREVMask(M, VT, 64) ||
3388 isVREVMask(M, VT, 32) ||
3389 isVREVMask(M, VT, 16) ||
3390 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
3391 isVTRNMask(M, VT, WhichResult) ||
3392 isVUZPMask(M, VT, WhichResult) ||
3393 isVZIPMask(M, VT, WhichResult) ||
3394 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
3395 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
3396 isVZIP_v_undef_Mask(M, VT, WhichResult));
3399 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
3400 /// the specified operations to build the shuffle.
3401 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
3402 SDValue RHS, SelectionDAG &DAG,
3404 unsigned OpNum = (PFEntry >> 26) & 0x0F;
3405 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
3406 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
3409 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
3418 OP_VUZPL, // VUZP, left result
3419 OP_VUZPR, // VUZP, right result
3420 OP_VZIPL, // VZIP, left result
3421 OP_VZIPR, // VZIP, right result
3422 OP_VTRNL, // VTRN, left result
3423 OP_VTRNR // VTRN, right result
3426 if (OpNum == OP_COPY) {
3427 if (LHSID == (1*9+2)*9+3) return LHS;
3428 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
3432 SDValue OpLHS, OpRHS;
3433 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
3434 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
3435 EVT VT = OpLHS.getValueType();
3438 default: llvm_unreachable("Unknown shuffle opcode!");
3440 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
3445 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
3446 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
3450 return DAG.getNode(ARMISD::VEXT, dl, VT,
3452 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
3455 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3456 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
3459 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3460 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
3463 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3464 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
3468 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
3469 SDValue V1 = Op.getOperand(0);
3470 SDValue V2 = Op.getOperand(1);
3471 DebugLoc dl = Op.getDebugLoc();
3472 EVT VT = Op.getValueType();
3473 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
3474 SmallVector<int, 8> ShuffleMask;
3476 // Convert shuffles that are directly supported on NEON to target-specific
3477 // DAG nodes, instead of keeping them as shuffles and matching them again
3478 // during code selection. This is more efficient and avoids the possibility
3479 // of inconsistencies between legalization and selection.
3480 // FIXME: floating-point vectors should be canonicalized to integer vectors
3481 // of the same time so that they get CSEd properly.
3482 SVN->getMask(ShuffleMask);
3484 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3485 if (EltSize <= 32) {
3486 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
3487 int Lane = SVN->getSplatIndex();
3488 // If this is undef splat, generate it via "just" vdup, if possible.
3489 if (Lane == -1) Lane = 0;
3491 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
3492 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
3494 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
3495 DAG.getConstant(Lane, MVT::i32));
3500 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
3503 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
3504 DAG.getConstant(Imm, MVT::i32));
3507 if (isVREVMask(ShuffleMask, VT, 64))
3508 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
3509 if (isVREVMask(ShuffleMask, VT, 32))
3510 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
3511 if (isVREVMask(ShuffleMask, VT, 16))
3512 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
3514 // Check for Neon shuffles that modify both input vectors in place.
3515 // If both results are used, i.e., if there are two shuffles with the same
3516 // source operands and with masks corresponding to both results of one of
3517 // these operations, DAG memoization will ensure that a single node is
3518 // used for both shuffles.
3519 unsigned WhichResult;
3520 if (isVTRNMask(ShuffleMask, VT, WhichResult))
3521 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3522 V1, V2).getValue(WhichResult);
3523 if (isVUZPMask(ShuffleMask, VT, WhichResult))
3524 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3525 V1, V2).getValue(WhichResult);
3526 if (isVZIPMask(ShuffleMask, VT, WhichResult))
3527 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3528 V1, V2).getValue(WhichResult);
3530 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
3531 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3532 V1, V1).getValue(WhichResult);
3533 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
3534 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3535 V1, V1).getValue(WhichResult);
3536 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
3537 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3538 V1, V1).getValue(WhichResult);
3541 // If the shuffle is not directly supported and it has 4 elements, use
3542 // the PerfectShuffle-generated table to synthesize it from other shuffles.
3543 unsigned NumElts = VT.getVectorNumElements();
3545 unsigned PFIndexes[4];
3546 for (unsigned i = 0; i != 4; ++i) {
3547 if (ShuffleMask[i] < 0)
3550 PFIndexes[i] = ShuffleMask[i];
3553 // Compute the index in the perfect shuffle table.
3554 unsigned PFTableIndex =
3555 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3556 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3557 unsigned Cost = (PFEntry >> 30);
3560 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
3563 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
3564 if (EltSize >= 32) {
3565 // Do the expansion with floating-point types, since that is what the VFP
3566 // registers are defined to use, and since i64 is not legal.
3567 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3568 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3569 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, V1);
3570 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, V2);
3571 SmallVector<SDValue, 8> Ops;
3572 for (unsigned i = 0; i < NumElts; ++i) {
3573 if (ShuffleMask[i] < 0)
3574 Ops.push_back(DAG.getUNDEF(EltVT));
3576 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3577 ShuffleMask[i] < (int)NumElts ? V1 : V2,
3578 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
3581 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
3582 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val);
3588 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
3589 EVT VT = Op.getValueType();
3590 DebugLoc dl = Op.getDebugLoc();
3591 SDValue Vec = Op.getOperand(0);
3592 SDValue Lane = Op.getOperand(1);
3593 assert(VT == MVT::i32 &&
3594 Vec.getValueType().getVectorElementType().getSizeInBits() < 32 &&
3595 "unexpected type for custom-lowering vector extract");
3596 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
3599 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
3600 // The only time a CONCAT_VECTORS operation can have legal types is when
3601 // two 64-bit vectors are concatenated to a 128-bit vector.
3602 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
3603 "unexpected CONCAT_VECTORS");
3604 DebugLoc dl = Op.getDebugLoc();
3605 SDValue Val = DAG.getUNDEF(MVT::v2f64);
3606 SDValue Op0 = Op.getOperand(0);
3607 SDValue Op1 = Op.getOperand(1);
3608 if (Op0.getOpcode() != ISD::UNDEF)
3609 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
3610 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op0),
3611 DAG.getIntPtrConstant(0));
3612 if (Op1.getOpcode() != ISD::UNDEF)
3613 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
3614 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op1),
3615 DAG.getIntPtrConstant(1));
3616 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Val);
3619 /// SkipExtension - For a node that is either a SIGN_EXTEND, ZERO_EXTEND, or
3620 /// an extending load, return the unextended value.
3621 static SDValue SkipExtension(SDNode *N, SelectionDAG &DAG) {
3622 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
3623 return N->getOperand(0);
3624 LoadSDNode *LD = cast<LoadSDNode>(N);
3625 return DAG.getLoad(LD->getMemoryVT(), N->getDebugLoc(), LD->getChain(),
3626 LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(),
3627 LD->isNonTemporal(), LD->getAlignment());
3630 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
3631 // Multiplications are only custom-lowered for 128-bit vectors so that
3632 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
3633 EVT VT = Op.getValueType();
3634 assert(VT.is128BitVector() && "unexpected type for custom-lowering ISD::MUL");
3635 SDNode *N0 = Op.getOperand(0).getNode();
3636 SDNode *N1 = Op.getOperand(1).getNode();
3637 unsigned NewOpc = 0;
3638 if ((N0->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N0)) &&
3639 (N1->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N1))) {
3640 NewOpc = ARMISD::VMULLs;
3641 } else if ((N0->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N0)) &&
3642 (N1->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N1))) {
3643 NewOpc = ARMISD::VMULLu;
3644 } else if (VT.getSimpleVT().SimpleTy == MVT::v2i64) {
3645 // Fall through to expand this. It is not legal.
3648 // Other vector multiplications are legal.
3652 // Legalize to a VMULL instruction.
3653 DebugLoc DL = Op.getDebugLoc();
3654 SDValue Op0 = SkipExtension(N0, DAG);
3655 SDValue Op1 = SkipExtension(N1, DAG);
3657 assert(Op0.getValueType().is64BitVector() &&
3658 Op1.getValueType().is64BitVector() &&
3659 "unexpected types for extended operands to VMULL");
3660 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
3663 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
3664 switch (Op.getOpcode()) {
3665 default: llvm_unreachable("Don't know how to custom lower this!");
3666 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3667 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
3668 case ISD::GlobalAddress:
3669 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
3670 LowerGlobalAddressELF(Op, DAG);
3671 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
3672 case ISD::SELECT: return LowerSELECT(Op, DAG);
3673 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
3674 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
3675 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
3676 case ISD::VASTART: return LowerVASTART(Op, DAG);
3677 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget);
3678 case ISD::SINT_TO_FP:
3679 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
3680 case ISD::FP_TO_SINT:
3681 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
3682 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
3683 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
3684 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
3685 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
3686 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
3687 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
3688 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
3690 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(Op.getNode(), DAG);
3693 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
3694 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
3695 case ISD::SRL_PARTS:
3696 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
3697 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
3698 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
3699 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
3700 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
3701 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
3702 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
3703 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
3704 case ISD::MUL: return LowerMUL(Op, DAG);
3709 /// ReplaceNodeResults - Replace the results of node with an illegal result
3710 /// type with new values built out of custom code.
3711 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
3712 SmallVectorImpl<SDValue>&Results,
3713 SelectionDAG &DAG) const {
3715 switch (N->getOpcode()) {
3717 llvm_unreachable("Don't know how to custom expand this!");
3719 case ISD::BIT_CONVERT:
3720 Res = ExpandBIT_CONVERT(N, DAG);
3724 Res = LowerShift(N, DAG, Subtarget);
3728 Results.push_back(Res);
3731 //===----------------------------------------------------------------------===//
3732 // ARM Scheduler Hooks
3733 //===----------------------------------------------------------------------===//
3736 ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
3737 MachineBasicBlock *BB,
3738 unsigned Size) const {
3739 unsigned dest = MI->getOperand(0).getReg();
3740 unsigned ptr = MI->getOperand(1).getReg();
3741 unsigned oldval = MI->getOperand(2).getReg();
3742 unsigned newval = MI->getOperand(3).getReg();
3743 unsigned scratch = BB->getParent()->getRegInfo()
3744 .createVirtualRegister(ARM::GPRRegisterClass);
3745 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3746 DebugLoc dl = MI->getDebugLoc();
3747 bool isThumb2 = Subtarget->isThumb2();
3749 unsigned ldrOpc, strOpc;
3751 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
3753 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
3754 strOpc = isThumb2 ? ARM::t2LDREXB : ARM::STREXB;
3757 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
3758 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
3761 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
3762 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
3766 MachineFunction *MF = BB->getParent();
3767 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3768 MachineFunction::iterator It = BB;
3769 ++It; // insert the new blocks after the current block
3771 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
3772 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
3773 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3774 MF->insert(It, loop1MBB);
3775 MF->insert(It, loop2MBB);
3776 MF->insert(It, exitMBB);
3778 // Transfer the remainder of BB and its successor edges to exitMBB.
3779 exitMBB->splice(exitMBB->begin(), BB,
3780 llvm::next(MachineBasicBlock::iterator(MI)),
3782 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
3786 // fallthrough --> loop1MBB
3787 BB->addSuccessor(loop1MBB);
3790 // ldrex dest, [ptr]
3794 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
3795 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
3796 .addReg(dest).addReg(oldval));
3797 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3798 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
3799 BB->addSuccessor(loop2MBB);
3800 BB->addSuccessor(exitMBB);
3803 // strex scratch, newval, [ptr]
3807 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval)
3809 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
3810 .addReg(scratch).addImm(0));
3811 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3812 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
3813 BB->addSuccessor(loop1MBB);
3814 BB->addSuccessor(exitMBB);
3820 MI->eraseFromParent(); // The instruction is gone now.
3826 ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
3827 unsigned Size, unsigned BinOpcode) const {
3828 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
3829 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3831 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3832 MachineFunction *MF = BB->getParent();
3833 MachineFunction::iterator It = BB;
3836 unsigned dest = MI->getOperand(0).getReg();
3837 unsigned ptr = MI->getOperand(1).getReg();
3838 unsigned incr = MI->getOperand(2).getReg();
3839 DebugLoc dl = MI->getDebugLoc();
3841 bool isThumb2 = Subtarget->isThumb2();
3842 unsigned ldrOpc, strOpc;
3844 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
3846 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
3847 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
3850 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
3851 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
3854 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
3855 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
3859 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3860 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
3861 MF->insert(It, loopMBB);
3862 MF->insert(It, exitMBB);
3864 // Transfer the remainder of BB and its successor edges to exitMBB.
3865 exitMBB->splice(exitMBB->begin(), BB,
3866 llvm::next(MachineBasicBlock::iterator(MI)),
3868 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
3870 MachineRegisterInfo &RegInfo = MF->getRegInfo();
3871 unsigned scratch = RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
3872 unsigned scratch2 = (!BinOpcode) ? incr :
3873 RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
3877 // fallthrough --> loopMBB
3878 BB->addSuccessor(loopMBB);
3882 // <binop> scratch2, dest, incr
3883 // strex scratch, scratch2, ptr
3886 // fallthrough --> exitMBB
3888 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
3890 // operand order needs to go the other way for NAND
3891 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr)
3892 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
3893 addReg(incr).addReg(dest)).addReg(0);
3895 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
3896 addReg(dest).addReg(incr)).addReg(0);
3899 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2)
3901 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
3902 .addReg(scratch).addImm(0));
3903 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
3904 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
3906 BB->addSuccessor(loopMBB);
3907 BB->addSuccessor(exitMBB);
3913 MI->eraseFromParent(); // The instruction is gone now.
3919 MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
3920 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
3921 E = MBB->succ_end(); I != E; ++I)
3924 llvm_unreachable("Expecting a BB with two successors!");
3928 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
3929 MachineBasicBlock *BB) const {
3930 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3931 DebugLoc dl = MI->getDebugLoc();
3932 bool isThumb2 = Subtarget->isThumb2();
3933 switch (MI->getOpcode()) {
3936 llvm_unreachable("Unexpected instr type to insert");
3938 case ARM::ATOMIC_LOAD_ADD_I8:
3939 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
3940 case ARM::ATOMIC_LOAD_ADD_I16:
3941 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
3942 case ARM::ATOMIC_LOAD_ADD_I32:
3943 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
3945 case ARM::ATOMIC_LOAD_AND_I8:
3946 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
3947 case ARM::ATOMIC_LOAD_AND_I16:
3948 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
3949 case ARM::ATOMIC_LOAD_AND_I32:
3950 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
3952 case ARM::ATOMIC_LOAD_OR_I8:
3953 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
3954 case ARM::ATOMIC_LOAD_OR_I16:
3955 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
3956 case ARM::ATOMIC_LOAD_OR_I32:
3957 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
3959 case ARM::ATOMIC_LOAD_XOR_I8:
3960 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
3961 case ARM::ATOMIC_LOAD_XOR_I16:
3962 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
3963 case ARM::ATOMIC_LOAD_XOR_I32:
3964 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
3966 case ARM::ATOMIC_LOAD_NAND_I8:
3967 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
3968 case ARM::ATOMIC_LOAD_NAND_I16:
3969 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
3970 case ARM::ATOMIC_LOAD_NAND_I32:
3971 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
3973 case ARM::ATOMIC_LOAD_SUB_I8:
3974 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
3975 case ARM::ATOMIC_LOAD_SUB_I16:
3976 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
3977 case ARM::ATOMIC_LOAD_SUB_I32:
3978 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
3980 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0);
3981 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0);
3982 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0);
3984 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1);
3985 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
3986 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
3988 case ARM::tMOVCCr_pseudo: {
3989 // To "insert" a SELECT_CC instruction, we actually have to insert the
3990 // diamond control-flow pattern. The incoming instruction knows the
3991 // destination vreg to set, the condition code register to branch on, the
3992 // true/false values to select between, and a branch opcode to use.
3993 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3994 MachineFunction::iterator It = BB;
4000 // cmpTY ccX, r1, r2
4002 // fallthrough --> copy0MBB
4003 MachineBasicBlock *thisMBB = BB;
4004 MachineFunction *F = BB->getParent();
4005 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4006 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
4007 F->insert(It, copy0MBB);
4008 F->insert(It, sinkMBB);
4010 // Transfer the remainder of BB and its successor edges to sinkMBB.
4011 sinkMBB->splice(sinkMBB->begin(), BB,
4012 llvm::next(MachineBasicBlock::iterator(MI)),
4014 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
4016 BB->addSuccessor(copy0MBB);
4017 BB->addSuccessor(sinkMBB);
4019 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
4020 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
4023 // %FalseValue = ...
4024 // # fallthrough to sinkMBB
4027 // Update machine-CFG edges
4028 BB->addSuccessor(sinkMBB);
4031 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
4034 BuildMI(*BB, BB->begin(), dl,
4035 TII->get(ARM::PHI), MI->getOperand(0).getReg())
4036 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
4037 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
4039 MI->eraseFromParent(); // The pseudo instruction is gone now.
4044 case ARM::BCCZi64: {
4045 // Compare both parts that make up the double comparison separately for
4047 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
4049 unsigned LHS1 = MI->getOperand(1).getReg();
4050 unsigned LHS2 = MI->getOperand(2).getReg();
4052 AddDefaultPred(BuildMI(BB, dl,
4053 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4054 .addReg(LHS1).addImm(0));
4055 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4056 .addReg(LHS2).addImm(0)
4057 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
4059 unsigned RHS1 = MI->getOperand(3).getReg();
4060 unsigned RHS2 = MI->getOperand(4).getReg();
4061 AddDefaultPred(BuildMI(BB, dl,
4062 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
4063 .addReg(LHS1).addReg(RHS1));
4064 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
4065 .addReg(LHS2).addReg(RHS2)
4066 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
4069 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB();
4070 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
4071 if (MI->getOperand(0).getImm() == ARMCC::NE)
4072 std::swap(destMBB, exitMBB);
4074 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4075 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
4076 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2B : ARM::B))
4079 MI->eraseFromParent(); // The pseudo instruction is gone now.
4085 //===----------------------------------------------------------------------===//
4086 // ARM Optimization Hooks
4087 //===----------------------------------------------------------------------===//
4090 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
4091 TargetLowering::DAGCombinerInfo &DCI) {
4092 SelectionDAG &DAG = DCI.DAG;
4093 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4094 EVT VT = N->getValueType(0);
4095 unsigned Opc = N->getOpcode();
4096 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
4097 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
4098 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
4099 ISD::CondCode CC = ISD::SETCC_INVALID;
4102 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
4104 SDValue CCOp = Slct.getOperand(0);
4105 if (CCOp.getOpcode() == ISD::SETCC)
4106 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
4109 bool DoXform = false;
4111 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
4114 if (LHS.getOpcode() == ISD::Constant &&
4115 cast<ConstantSDNode>(LHS)->isNullValue()) {
4117 } else if (CC != ISD::SETCC_INVALID &&
4118 RHS.getOpcode() == ISD::Constant &&
4119 cast<ConstantSDNode>(RHS)->isNullValue()) {
4120 std::swap(LHS, RHS);
4121 SDValue Op0 = Slct.getOperand(0);
4122 EVT OpVT = isSlctCC ? Op0.getValueType() :
4123 Op0.getOperand(0).getValueType();
4124 bool isInt = OpVT.isInteger();
4125 CC = ISD::getSetCCInverse(CC, isInt);
4127 if (!TLI.isCondCodeLegal(CC, OpVT))
4128 return SDValue(); // Inverse operator isn't legal.
4135 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
4137 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
4138 Slct.getOperand(0), Slct.getOperand(1), CC);
4139 SDValue CCOp = Slct.getOperand(0);
4141 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
4142 CCOp.getOperand(0), CCOp.getOperand(1), CC);
4143 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
4144 CCOp, OtherOp, Result);
4149 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
4150 /// operands N0 and N1. This is a helper for PerformADDCombine that is
4151 /// called with the default operands, and if that fails, with commuted
4153 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
4154 TargetLowering::DAGCombinerInfo &DCI) {
4155 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
4156 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
4157 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
4158 if (Result.getNode()) return Result;
4163 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
4165 static SDValue PerformADDCombine(SDNode *N,
4166 TargetLowering::DAGCombinerInfo &DCI) {
4167 SDValue N0 = N->getOperand(0);
4168 SDValue N1 = N->getOperand(1);
4170 // First try with the default operand order.
4171 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI);
4172 if (Result.getNode())
4175 // If that didn't work, try again with the operands commuted.
4176 return PerformADDCombineWithOperands(N, N1, N0, DCI);
4179 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
4181 static SDValue PerformSUBCombine(SDNode *N,
4182 TargetLowering::DAGCombinerInfo &DCI) {
4183 SDValue N0 = N->getOperand(0);
4184 SDValue N1 = N->getOperand(1);
4186 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
4187 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
4188 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
4189 if (Result.getNode()) return Result;
4195 static SDValue PerformMULCombine(SDNode *N,
4196 TargetLowering::DAGCombinerInfo &DCI,
4197 const ARMSubtarget *Subtarget) {
4198 SelectionDAG &DAG = DCI.DAG;
4200 if (Subtarget->isThumb1Only())
4203 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
4206 EVT VT = N->getValueType(0);
4210 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
4214 uint64_t MulAmt = C->getZExtValue();
4215 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt);
4216 ShiftAmt = ShiftAmt & (32 - 1);
4217 SDValue V = N->getOperand(0);
4218 DebugLoc DL = N->getDebugLoc();
4221 MulAmt >>= ShiftAmt;
4222 if (isPowerOf2_32(MulAmt - 1)) {
4223 // (mul x, 2^N + 1) => (add (shl x, N), x)
4224 Res = DAG.getNode(ISD::ADD, DL, VT,
4225 V, DAG.getNode(ISD::SHL, DL, VT,
4226 V, DAG.getConstant(Log2_32(MulAmt-1),
4228 } else if (isPowerOf2_32(MulAmt + 1)) {
4229 // (mul x, 2^N - 1) => (sub (shl x, N), x)
4230 Res = DAG.getNode(ISD::SUB, DL, VT,
4231 DAG.getNode(ISD::SHL, DL, VT,
4232 V, DAG.getConstant(Log2_32(MulAmt+1),
4239 Res = DAG.getNode(ISD::SHL, DL, VT, Res,
4240 DAG.getConstant(ShiftAmt, MVT::i32));
4242 // Do not add new nodes to DAG combiner worklist.
4243 DCI.CombineTo(N, Res, false);
4247 /// PerformORCombine - Target-specific dag combine xforms for ISD::OR
4248 static SDValue PerformORCombine(SDNode *N,
4249 TargetLowering::DAGCombinerInfo &DCI,
4250 const ARMSubtarget *Subtarget) {
4251 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when
4254 // BFI is only available on V6T2+
4255 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops())
4258 SelectionDAG &DAG = DCI.DAG;
4259 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
4260 DebugLoc DL = N->getDebugLoc();
4261 // 1) or (and A, mask), val => ARMbfi A, val, mask
4262 // iff (val & mask) == val
4264 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
4265 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2)
4266 // && CountPopulation_32(mask) == CountPopulation_32(~mask2)
4267 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2)
4268 // && CountPopulation_32(mask) == CountPopulation_32(~mask2)
4269 // (i.e., copy a bitfield value into another bitfield of the same width)
4270 if (N0.getOpcode() != ISD::AND)
4273 EVT VT = N->getValueType(0);
4278 // The value and the mask need to be constants so we can verify this is
4279 // actually a bitfield set. If the mask is 0xffff, we can do better
4280 // via a movt instruction, so don't use BFI in that case.
4281 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
4284 unsigned Mask = C->getZExtValue();
4288 // Case (1): or (and A, mask), val => ARMbfi A, val, mask
4289 if ((C = dyn_cast<ConstantSDNode>(N1))) {
4290 unsigned Val = C->getZExtValue();
4291 if (!ARM::isBitFieldInvertedMask(Mask) || (Val & ~Mask) != Val)
4293 Val >>= CountTrailingZeros_32(~Mask);
4295 Res = DAG.getNode(ARMISD::BFI, DL, VT, N0.getOperand(0),
4296 DAG.getConstant(Val, MVT::i32),
4297 DAG.getConstant(Mask, MVT::i32));
4299 // Do not add new nodes to DAG combiner worklist.
4300 DCI.CombineTo(N, Res, false);
4301 } else if (N1.getOpcode() == ISD::AND) {
4302 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
4303 C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
4306 unsigned Mask2 = C->getZExtValue();
4308 if (ARM::isBitFieldInvertedMask(Mask) &&
4309 ARM::isBitFieldInvertedMask(~Mask2) &&
4310 (CountPopulation_32(Mask) == CountPopulation_32(~Mask2))) {
4311 // The pack halfword instruction works better for masks that fit it,
4312 // so use that when it's available.
4313 if (Subtarget->hasT2ExtractPack() &&
4314 (Mask == 0xffff || Mask == 0xffff0000))
4317 unsigned lsb = CountTrailingZeros_32(Mask2);
4318 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
4319 DAG.getConstant(lsb, MVT::i32));
4320 Res = DAG.getNode(ARMISD::BFI, DL, VT, N0.getOperand(0), Res,
4321 DAG.getConstant(Mask, MVT::i32));
4322 // Do not add new nodes to DAG combiner worklist.
4323 DCI.CombineTo(N, Res, false);
4324 } else if (ARM::isBitFieldInvertedMask(~Mask) &&
4325 ARM::isBitFieldInvertedMask(Mask2) &&
4326 (CountPopulation_32(~Mask) == CountPopulation_32(Mask2))) {
4327 // The pack halfword instruction works better for masks that fit it,
4328 // so use that when it's available.
4329 if (Subtarget->hasT2ExtractPack() &&
4330 (Mask2 == 0xffff || Mask2 == 0xffff0000))
4333 unsigned lsb = CountTrailingZeros_32(Mask);
4334 Res = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0),
4335 DAG.getConstant(lsb, MVT::i32));
4336 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
4337 DAG.getConstant(Mask2, MVT::i32));
4338 // Do not add new nodes to DAG combiner worklist.
4339 DCI.CombineTo(N, Res, false);
4346 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
4347 /// ARMISD::VMOVRRD.
4348 static SDValue PerformVMOVRRDCombine(SDNode *N,
4349 TargetLowering::DAGCombinerInfo &DCI) {
4350 // vmovrrd(vmovdrr x, y) -> x,y
4351 SDValue InDouble = N->getOperand(0);
4352 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
4353 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
4357 /// PerformVMOVDRRCombine - Target-specific dag combine xforms for
4358 /// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands.
4359 static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) {
4360 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X)
4361 SDValue Op0 = N->getOperand(0);
4362 SDValue Op1 = N->getOperand(1);
4363 if (Op0.getOpcode() == ISD::BIT_CONVERT)
4364 Op0 = Op0.getOperand(0);
4365 if (Op1.getOpcode() == ISD::BIT_CONVERT)
4366 Op1 = Op1.getOperand(0);
4367 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
4368 Op0.getNode() == Op1.getNode() &&
4369 Op0.getResNo() == 0 && Op1.getResNo() == 1)
4370 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
4371 N->getValueType(0), Op0.getOperand(0));
4375 /// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for
4376 /// ISD::BUILD_VECTOR.
4377 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG) {
4378 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X):
4379 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value
4380 // into a pair of GPRs, which is fine when the value is used as a scalar,
4381 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD.
4382 if (N->getNumOperands() == 2)
4383 return PerformVMOVDRRCombine(N, DAG);
4388 /// PerformVDUPLANECombine - Target-specific dag combine xforms for
4389 /// ARMISD::VDUPLANE.
4390 static SDValue PerformVDUPLANECombine(SDNode *N, SelectionDAG &DAG) {
4391 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
4393 SDValue Op = N->getOperand(0);
4394 EVT VT = N->getValueType(0);
4396 // Ignore bit_converts.
4397 while (Op.getOpcode() == ISD::BIT_CONVERT)
4398 Op = Op.getOperand(0);
4399 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
4402 // Make sure the VMOV element size is not bigger than the VDUPLANE elements.
4403 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits();
4404 // The canonical VMOV for a zero vector uses a 32-bit element size.
4405 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4407 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
4409 if (EltSize > VT.getVectorElementType().getSizeInBits())
4412 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
4415 /// getVShiftImm - Check if this is a valid build_vector for the immediate
4416 /// operand of a vector shift operation, where all the elements of the
4417 /// build_vector must have the same constant integer value.
4418 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
4419 // Ignore bit_converts.
4420 while (Op.getOpcode() == ISD::BIT_CONVERT)
4421 Op = Op.getOperand(0);
4422 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
4423 APInt SplatBits, SplatUndef;
4424 unsigned SplatBitSize;
4426 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
4427 HasAnyUndefs, ElementBits) ||
4428 SplatBitSize > ElementBits)
4430 Cnt = SplatBits.getSExtValue();
4434 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
4435 /// operand of a vector shift left operation. That value must be in the range:
4436 /// 0 <= Value < ElementBits for a left shift; or
4437 /// 0 <= Value <= ElementBits for a long left shift.
4438 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
4439 assert(VT.isVector() && "vector shift count is not a vector type");
4440 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
4441 if (! getVShiftImm(Op, ElementBits, Cnt))
4443 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
4446 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
4447 /// operand of a vector shift right operation. For a shift opcode, the value
4448 /// is positive, but for an intrinsic the value count must be negative. The
4449 /// absolute value must be in the range:
4450 /// 1 <= |Value| <= ElementBits for a right shift; or
4451 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
4452 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
4454 assert(VT.isVector() && "vector shift count is not a vector type");
4455 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
4456 if (! getVShiftImm(Op, ElementBits, Cnt))
4460 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
4463 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
4464 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
4465 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
4468 // Don't do anything for most intrinsics.
4471 // Vector shifts: check for immediate versions and lower them.
4472 // Note: This is done during DAG combining instead of DAG legalizing because
4473 // the build_vectors for 64-bit vector element shift counts are generally
4474 // not legal, and it is hard to see their values after they get legalized to
4475 // loads from a constant pool.
4476 case Intrinsic::arm_neon_vshifts:
4477 case Intrinsic::arm_neon_vshiftu:
4478 case Intrinsic::arm_neon_vshiftls:
4479 case Intrinsic::arm_neon_vshiftlu:
4480 case Intrinsic::arm_neon_vshiftn:
4481 case Intrinsic::arm_neon_vrshifts:
4482 case Intrinsic::arm_neon_vrshiftu:
4483 case Intrinsic::arm_neon_vrshiftn:
4484 case Intrinsic::arm_neon_vqshifts:
4485 case Intrinsic::arm_neon_vqshiftu:
4486 case Intrinsic::arm_neon_vqshiftsu:
4487 case Intrinsic::arm_neon_vqshiftns:
4488 case Intrinsic::arm_neon_vqshiftnu:
4489 case Intrinsic::arm_neon_vqshiftnsu:
4490 case Intrinsic::arm_neon_vqrshiftns:
4491 case Intrinsic::arm_neon_vqrshiftnu:
4492 case Intrinsic::arm_neon_vqrshiftnsu: {
4493 EVT VT = N->getOperand(1).getValueType();
4495 unsigned VShiftOpc = 0;
4498 case Intrinsic::arm_neon_vshifts:
4499 case Intrinsic::arm_neon_vshiftu:
4500 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
4501 VShiftOpc = ARMISD::VSHL;
4504 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
4505 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
4506 ARMISD::VSHRs : ARMISD::VSHRu);
4511 case Intrinsic::arm_neon_vshiftls:
4512 case Intrinsic::arm_neon_vshiftlu:
4513 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
4515 llvm_unreachable("invalid shift count for vshll intrinsic");
4517 case Intrinsic::arm_neon_vrshifts:
4518 case Intrinsic::arm_neon_vrshiftu:
4519 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
4523 case Intrinsic::arm_neon_vqshifts:
4524 case Intrinsic::arm_neon_vqshiftu:
4525 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
4529 case Intrinsic::arm_neon_vqshiftsu:
4530 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
4532 llvm_unreachable("invalid shift count for vqshlu intrinsic");
4534 case Intrinsic::arm_neon_vshiftn:
4535 case Intrinsic::arm_neon_vrshiftn:
4536 case Intrinsic::arm_neon_vqshiftns:
4537 case Intrinsic::arm_neon_vqshiftnu:
4538 case Intrinsic::arm_neon_vqshiftnsu:
4539 case Intrinsic::arm_neon_vqrshiftns:
4540 case Intrinsic::arm_neon_vqrshiftnu:
4541 case Intrinsic::arm_neon_vqrshiftnsu:
4542 // Narrowing shifts require an immediate right shift.
4543 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
4545 llvm_unreachable("invalid shift count for narrowing vector shift "
4549 llvm_unreachable("unhandled vector shift");
4553 case Intrinsic::arm_neon_vshifts:
4554 case Intrinsic::arm_neon_vshiftu:
4555 // Opcode already set above.
4557 case Intrinsic::arm_neon_vshiftls:
4558 case Intrinsic::arm_neon_vshiftlu:
4559 if (Cnt == VT.getVectorElementType().getSizeInBits())
4560 VShiftOpc = ARMISD::VSHLLi;
4562 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
4563 ARMISD::VSHLLs : ARMISD::VSHLLu);
4565 case Intrinsic::arm_neon_vshiftn:
4566 VShiftOpc = ARMISD::VSHRN; break;
4567 case Intrinsic::arm_neon_vrshifts:
4568 VShiftOpc = ARMISD::VRSHRs; break;
4569 case Intrinsic::arm_neon_vrshiftu:
4570 VShiftOpc = ARMISD::VRSHRu; break;
4571 case Intrinsic::arm_neon_vrshiftn:
4572 VShiftOpc = ARMISD::VRSHRN; break;
4573 case Intrinsic::arm_neon_vqshifts:
4574 VShiftOpc = ARMISD::VQSHLs; break;
4575 case Intrinsic::arm_neon_vqshiftu:
4576 VShiftOpc = ARMISD::VQSHLu; break;
4577 case Intrinsic::arm_neon_vqshiftsu:
4578 VShiftOpc = ARMISD::VQSHLsu; break;
4579 case Intrinsic::arm_neon_vqshiftns:
4580 VShiftOpc = ARMISD::VQSHRNs; break;
4581 case Intrinsic::arm_neon_vqshiftnu:
4582 VShiftOpc = ARMISD::VQSHRNu; break;
4583 case Intrinsic::arm_neon_vqshiftnsu:
4584 VShiftOpc = ARMISD::VQSHRNsu; break;
4585 case Intrinsic::arm_neon_vqrshiftns:
4586 VShiftOpc = ARMISD::VQRSHRNs; break;
4587 case Intrinsic::arm_neon_vqrshiftnu:
4588 VShiftOpc = ARMISD::VQRSHRNu; break;
4589 case Intrinsic::arm_neon_vqrshiftnsu:
4590 VShiftOpc = ARMISD::VQRSHRNsu; break;
4593 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
4594 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
4597 case Intrinsic::arm_neon_vshiftins: {
4598 EVT VT = N->getOperand(1).getValueType();
4600 unsigned VShiftOpc = 0;
4602 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
4603 VShiftOpc = ARMISD::VSLI;
4604 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
4605 VShiftOpc = ARMISD::VSRI;
4607 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
4610 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
4611 N->getOperand(1), N->getOperand(2),
4612 DAG.getConstant(Cnt, MVT::i32));
4615 case Intrinsic::arm_neon_vqrshifts:
4616 case Intrinsic::arm_neon_vqrshiftu:
4617 // No immediate versions of these to check for.
4624 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
4625 /// lowers them. As with the vector shift intrinsics, this is done during DAG
4626 /// combining instead of DAG legalizing because the build_vectors for 64-bit
4627 /// vector element shift counts are generally not legal, and it is hard to see
4628 /// their values after they get legalized to loads from a constant pool.
4629 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
4630 const ARMSubtarget *ST) {
4631 EVT VT = N->getValueType(0);
4633 // Nothing to be done for scalar shifts.
4634 if (! VT.isVector())
4637 assert(ST->hasNEON() && "unexpected vector shift");
4640 switch (N->getOpcode()) {
4641 default: llvm_unreachable("unexpected shift opcode");
4644 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
4645 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
4646 DAG.getConstant(Cnt, MVT::i32));
4651 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
4652 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
4653 ARMISD::VSHRs : ARMISD::VSHRu);
4654 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
4655 DAG.getConstant(Cnt, MVT::i32));
4661 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
4662 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
4663 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
4664 const ARMSubtarget *ST) {
4665 SDValue N0 = N->getOperand(0);
4667 // Check for sign- and zero-extensions of vector extract operations of 8-
4668 // and 16-bit vector elements. NEON supports these directly. They are
4669 // handled during DAG combining because type legalization will promote them
4670 // to 32-bit types and it is messy to recognize the operations after that.
4671 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
4672 SDValue Vec = N0.getOperand(0);
4673 SDValue Lane = N0.getOperand(1);
4674 EVT VT = N->getValueType(0);
4675 EVT EltVT = N0.getValueType();
4676 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4678 if (VT == MVT::i32 &&
4679 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
4680 TLI.isTypeLegal(Vec.getValueType())) {
4683 switch (N->getOpcode()) {
4684 default: llvm_unreachable("unexpected opcode");
4685 case ISD::SIGN_EXTEND:
4686 Opc = ARMISD::VGETLANEs;
4688 case ISD::ZERO_EXTEND:
4689 case ISD::ANY_EXTEND:
4690 Opc = ARMISD::VGETLANEu;
4693 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
4700 /// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
4701 /// to match f32 max/min patterns to use NEON vmax/vmin instructions.
4702 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
4703 const ARMSubtarget *ST) {
4704 // If the target supports NEON, try to use vmax/vmin instructions for f32
4705 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set,
4706 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
4707 // a NaN; only do the transformation when it matches that behavior.
4709 // For now only do this when using NEON for FP operations; if using VFP, it
4710 // is not obvious that the benefit outweighs the cost of switching to the
4712 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
4713 N->getValueType(0) != MVT::f32)
4716 SDValue CondLHS = N->getOperand(0);
4717 SDValue CondRHS = N->getOperand(1);
4718 SDValue LHS = N->getOperand(2);
4719 SDValue RHS = N->getOperand(3);
4720 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
4722 unsigned Opcode = 0;
4724 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
4725 IsReversed = false; // x CC y ? x : y
4726 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
4727 IsReversed = true ; // x CC y ? y : x
4741 // If LHS is NaN, an ordered comparison will be false and the result will
4742 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
4743 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
4744 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
4745 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
4747 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
4748 // will return -0, so vmin can only be used for unsafe math or if one of
4749 // the operands is known to be nonzero.
4750 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
4752 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
4754 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
4763 // If LHS is NaN, an ordered comparison will be false and the result will
4764 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
4765 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
4766 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
4767 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
4769 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
4770 // will return +0, so vmax can only be used for unsafe math or if one of
4771 // the operands is known to be nonzero.
4772 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
4774 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
4776 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
4782 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS);
4785 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
4786 DAGCombinerInfo &DCI) const {
4787 switch (N->getOpcode()) {
4789 case ISD::ADD: return PerformADDCombine(N, DCI);
4790 case ISD::SUB: return PerformSUBCombine(N, DCI);
4791 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
4792 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
4793 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
4794 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
4795 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI.DAG);
4796 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI.DAG);
4797 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
4800 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
4801 case ISD::SIGN_EXTEND:
4802 case ISD::ZERO_EXTEND:
4803 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
4804 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
4809 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
4810 if (!Subtarget->allowsUnalignedMem())
4813 switch (VT.getSimpleVT().SimpleTy) {
4820 // FIXME: VLD1 etc with standard alignment is legal.
4824 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
4829 switch (VT.getSimpleVT().SimpleTy) {
4830 default: return false;
4845 if ((V & (Scale - 1)) != 0)
4848 return V == (V & ((1LL << 5) - 1));
4851 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
4852 const ARMSubtarget *Subtarget) {
4859 switch (VT.getSimpleVT().SimpleTy) {
4860 default: return false;
4865 // + imm12 or - imm8
4867 return V == (V & ((1LL << 8) - 1));
4868 return V == (V & ((1LL << 12) - 1));
4871 // Same as ARM mode. FIXME: NEON?
4872 if (!Subtarget->hasVFP2())
4877 return V == (V & ((1LL << 8) - 1));
4881 /// isLegalAddressImmediate - Return true if the integer value can be used
4882 /// as the offset of the target addressing mode for load / store of the
4884 static bool isLegalAddressImmediate(int64_t V, EVT VT,
4885 const ARMSubtarget *Subtarget) {
4892 if (Subtarget->isThumb1Only())
4893 return isLegalT1AddressImmediate(V, VT);
4894 else if (Subtarget->isThumb2())
4895 return isLegalT2AddressImmediate(V, VT, Subtarget);
4900 switch (VT.getSimpleVT().SimpleTy) {
4901 default: return false;
4906 return V == (V & ((1LL << 12) - 1));
4909 return V == (V & ((1LL << 8) - 1));
4912 if (!Subtarget->hasVFP2()) // FIXME: NEON?
4917 return V == (V & ((1LL << 8) - 1));
4921 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
4923 int Scale = AM.Scale;
4927 switch (VT.getSimpleVT().SimpleTy) {
4928 default: return false;
4937 return Scale == 2 || Scale == 4 || Scale == 8;
4940 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
4944 // Note, we allow "void" uses (basically, uses that aren't loads or
4945 // stores), because arm allows folding a scale into many arithmetic
4946 // operations. This should be made more precise and revisited later.
4948 // Allow r << imm, but the imm has to be a multiple of two.
4949 if (Scale & 1) return false;
4950 return isPowerOf2_32(Scale);
4954 /// isLegalAddressingMode - Return true if the addressing mode represented
4955 /// by AM is legal for this target, for a load/store of the specified type.
4956 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
4957 const Type *Ty) const {
4958 EVT VT = getValueType(Ty, true);
4959 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
4962 // Can never fold addr of global into load/store.
4967 case 0: // no scale reg, must be "r+i" or "r", or "i".
4970 if (Subtarget->isThumb1Only())
4974 // ARM doesn't support any R+R*scale+imm addr modes.
4981 if (Subtarget->isThumb2())
4982 return isLegalT2ScaledAddressingMode(AM, VT);
4984 int Scale = AM.Scale;
4985 switch (VT.getSimpleVT().SimpleTy) {
4986 default: return false;
4990 if (Scale < 0) Scale = -Scale;
4994 return isPowerOf2_32(Scale & ~1);
4998 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
5003 // Note, we allow "void" uses (basically, uses that aren't loads or
5004 // stores), because arm allows folding a scale into many arithmetic
5005 // operations. This should be made more precise and revisited later.
5007 // Allow r << imm, but the imm has to be a multiple of two.
5008 if (Scale & 1) return false;
5009 return isPowerOf2_32(Scale);
5016 /// isLegalICmpImmediate - Return true if the specified immediate is legal
5017 /// icmp immediate, that is the target has icmp instructions which can compare
5018 /// a register against the immediate without having to materialize the
5019 /// immediate into a register.
5020 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
5021 if (!Subtarget->isThumb())
5022 return ARM_AM::getSOImmVal(Imm) != -1;
5023 if (Subtarget->isThumb2())
5024 return ARM_AM::getT2SOImmVal(Imm) != -1;
5025 return Imm >= 0 && Imm <= 255;
5028 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
5029 bool isSEXTLoad, SDValue &Base,
5030 SDValue &Offset, bool &isInc,
5031 SelectionDAG &DAG) {
5032 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
5035 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
5037 Base = Ptr->getOperand(0);
5038 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
5039 int RHSC = (int)RHS->getZExtValue();
5040 if (RHSC < 0 && RHSC > -256) {
5041 assert(Ptr->getOpcode() == ISD::ADD);
5043 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
5047 isInc = (Ptr->getOpcode() == ISD::ADD);
5048 Offset = Ptr->getOperand(1);
5050 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
5052 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
5053 int RHSC = (int)RHS->getZExtValue();
5054 if (RHSC < 0 && RHSC > -0x1000) {
5055 assert(Ptr->getOpcode() == ISD::ADD);
5057 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
5058 Base = Ptr->getOperand(0);
5063 if (Ptr->getOpcode() == ISD::ADD) {
5065 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
5066 if (ShOpcVal != ARM_AM::no_shift) {
5067 Base = Ptr->getOperand(1);
5068 Offset = Ptr->getOperand(0);
5070 Base = Ptr->getOperand(0);
5071 Offset = Ptr->getOperand(1);
5076 isInc = (Ptr->getOpcode() == ISD::ADD);
5077 Base = Ptr->getOperand(0);
5078 Offset = Ptr->getOperand(1);
5082 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
5086 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
5087 bool isSEXTLoad, SDValue &Base,
5088 SDValue &Offset, bool &isInc,
5089 SelectionDAG &DAG) {
5090 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
5093 Base = Ptr->getOperand(0);
5094 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
5095 int RHSC = (int)RHS->getZExtValue();
5096 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
5097 assert(Ptr->getOpcode() == ISD::ADD);
5099 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
5101 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
5102 isInc = Ptr->getOpcode() == ISD::ADD;
5103 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
5111 /// getPreIndexedAddressParts - returns true by value, base pointer and
5112 /// offset pointer and addressing mode by reference if the node's address
5113 /// can be legally represented as pre-indexed load / store address.
5115 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
5117 ISD::MemIndexedMode &AM,
5118 SelectionDAG &DAG) const {
5119 if (Subtarget->isThumb1Only())
5124 bool isSEXTLoad = false;
5125 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5126 Ptr = LD->getBasePtr();
5127 VT = LD->getMemoryVT();
5128 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
5129 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5130 Ptr = ST->getBasePtr();
5131 VT = ST->getMemoryVT();
5136 bool isLegal = false;
5137 if (Subtarget->isThumb2())
5138 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
5139 Offset, isInc, DAG);
5141 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
5142 Offset, isInc, DAG);
5146 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
5150 /// getPostIndexedAddressParts - returns true by value, base pointer and
5151 /// offset pointer and addressing mode by reference if this node can be
5152 /// combined with a load / store to form a post-indexed load / store.
5153 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
5156 ISD::MemIndexedMode &AM,
5157 SelectionDAG &DAG) const {
5158 if (Subtarget->isThumb1Only())
5163 bool isSEXTLoad = false;
5164 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5165 VT = LD->getMemoryVT();
5166 Ptr = LD->getBasePtr();
5167 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
5168 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5169 VT = ST->getMemoryVT();
5170 Ptr = ST->getBasePtr();
5175 bool isLegal = false;
5176 if (Subtarget->isThumb2())
5177 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
5180 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
5186 // Swap base ptr and offset to catch more post-index load / store when
5187 // it's legal. In Thumb2 mode, offset must be an immediate.
5188 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
5189 !Subtarget->isThumb2())
5190 std::swap(Base, Offset);
5192 // Post-indexed load / store update the base pointer.
5197 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
5201 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
5205 const SelectionDAG &DAG,
5206 unsigned Depth) const {
5207 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
5208 switch (Op.getOpcode()) {
5210 case ARMISD::CMOV: {
5211 // Bits are known zero/one if known on the LHS and RHS.
5212 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
5213 if (KnownZero == 0 && KnownOne == 0) return;
5215 APInt KnownZeroRHS, KnownOneRHS;
5216 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
5217 KnownZeroRHS, KnownOneRHS, Depth+1);
5218 KnownZero &= KnownZeroRHS;
5219 KnownOne &= KnownOneRHS;
5225 //===----------------------------------------------------------------------===//
5226 // ARM Inline Assembly Support
5227 //===----------------------------------------------------------------------===//
5229 /// getConstraintType - Given a constraint letter, return the type of
5230 /// constraint it is for this target.
5231 ARMTargetLowering::ConstraintType
5232 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
5233 if (Constraint.size() == 1) {
5234 switch (Constraint[0]) {
5236 case 'l': return C_RegisterClass;
5237 case 'w': return C_RegisterClass;
5240 return TargetLowering::getConstraintType(Constraint);
5243 std::pair<unsigned, const TargetRegisterClass*>
5244 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
5246 if (Constraint.size() == 1) {
5247 // GCC ARM Constraint Letters
5248 switch (Constraint[0]) {
5250 if (Subtarget->isThumb())
5251 return std::make_pair(0U, ARM::tGPRRegisterClass);
5253 return std::make_pair(0U, ARM::GPRRegisterClass);
5255 return std::make_pair(0U, ARM::GPRRegisterClass);
5258 return std::make_pair(0U, ARM::SPRRegisterClass);
5259 if (VT.getSizeInBits() == 64)
5260 return std::make_pair(0U, ARM::DPRRegisterClass);
5261 if (VT.getSizeInBits() == 128)
5262 return std::make_pair(0U, ARM::QPRRegisterClass);
5266 if (StringRef("{cc}").equals_lower(Constraint))
5267 return std::make_pair(unsigned(ARM::CPSR), ARM::CCRRegisterClass);
5269 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
5272 std::vector<unsigned> ARMTargetLowering::
5273 getRegClassForInlineAsmConstraint(const std::string &Constraint,
5275 if (Constraint.size() != 1)
5276 return std::vector<unsigned>();
5278 switch (Constraint[0]) { // GCC ARM Constraint Letters
5281 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
5282 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
5285 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
5286 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
5287 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
5288 ARM::R12, ARM::LR, 0);
5291 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
5292 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
5293 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
5294 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
5295 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
5296 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
5297 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
5298 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
5299 if (VT.getSizeInBits() == 64)
5300 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
5301 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
5302 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
5303 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
5304 if (VT.getSizeInBits() == 128)
5305 return make_vector<unsigned>(ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
5306 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 0);
5310 return std::vector<unsigned>();
5313 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
5314 /// vector. If it is invalid, don't add anything to Ops.
5315 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
5317 std::vector<SDValue>&Ops,
5318 SelectionDAG &DAG) const {
5319 SDValue Result(0, 0);
5321 switch (Constraint) {
5323 case 'I': case 'J': case 'K': case 'L':
5324 case 'M': case 'N': case 'O':
5325 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
5329 int64_t CVal64 = C->getSExtValue();
5330 int CVal = (int) CVal64;
5331 // None of these constraints allow values larger than 32 bits. Check
5332 // that the value fits in an int.
5336 switch (Constraint) {
5338 if (Subtarget->isThumb1Only()) {
5339 // This must be a constant between 0 and 255, for ADD
5341 if (CVal >= 0 && CVal <= 255)
5343 } else if (Subtarget->isThumb2()) {
5344 // A constant that can be used as an immediate value in a
5345 // data-processing instruction.
5346 if (ARM_AM::getT2SOImmVal(CVal) != -1)
5349 // A constant that can be used as an immediate value in a
5350 // data-processing instruction.
5351 if (ARM_AM::getSOImmVal(CVal) != -1)
5357 if (Subtarget->isThumb()) { // FIXME thumb2
5358 // This must be a constant between -255 and -1, for negated ADD
5359 // immediates. This can be used in GCC with an "n" modifier that
5360 // prints the negated value, for use with SUB instructions. It is
5361 // not useful otherwise but is implemented for compatibility.
5362 if (CVal >= -255 && CVal <= -1)
5365 // This must be a constant between -4095 and 4095. It is not clear
5366 // what this constraint is intended for. Implemented for
5367 // compatibility with GCC.
5368 if (CVal >= -4095 && CVal <= 4095)
5374 if (Subtarget->isThumb1Only()) {
5375 // A 32-bit value where only one byte has a nonzero value. Exclude
5376 // zero to match GCC. This constraint is used by GCC internally for
5377 // constants that can be loaded with a move/shift combination.
5378 // It is not useful otherwise but is implemented for compatibility.
5379 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
5381 } else if (Subtarget->isThumb2()) {
5382 // A constant whose bitwise inverse can be used as an immediate
5383 // value in a data-processing instruction. This can be used in GCC
5384 // with a "B" modifier that prints the inverted value, for use with
5385 // BIC and MVN instructions. It is not useful otherwise but is
5386 // implemented for compatibility.
5387 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
5390 // A constant whose bitwise inverse can be used as an immediate
5391 // value in a data-processing instruction. This can be used in GCC
5392 // with a "B" modifier that prints the inverted value, for use with
5393 // BIC and MVN instructions. It is not useful otherwise but is
5394 // implemented for compatibility.
5395 if (ARM_AM::getSOImmVal(~CVal) != -1)
5401 if (Subtarget->isThumb1Only()) {
5402 // This must be a constant between -7 and 7,
5403 // for 3-operand ADD/SUB immediate instructions.
5404 if (CVal >= -7 && CVal < 7)
5406 } else if (Subtarget->isThumb2()) {
5407 // A constant whose negation can be used as an immediate value in a
5408 // data-processing instruction. This can be used in GCC with an "n"
5409 // modifier that prints the negated value, for use with SUB
5410 // instructions. It is not useful otherwise but is implemented for
5412 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
5415 // A constant whose negation can be used as an immediate value in a
5416 // data-processing instruction. This can be used in GCC with an "n"
5417 // modifier that prints the negated value, for use with SUB
5418 // instructions. It is not useful otherwise but is implemented for
5420 if (ARM_AM::getSOImmVal(-CVal) != -1)
5426 if (Subtarget->isThumb()) { // FIXME thumb2
5427 // This must be a multiple of 4 between 0 and 1020, for
5428 // ADD sp + immediate.
5429 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
5432 // A power of two or a constant between 0 and 32. This is used in
5433 // GCC for the shift amount on shifted register operands, but it is
5434 // useful in general for any shift amounts.
5435 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
5441 if (Subtarget->isThumb()) { // FIXME thumb2
5442 // This must be a constant between 0 and 31, for shift amounts.
5443 if (CVal >= 0 && CVal <= 31)
5449 if (Subtarget->isThumb()) { // FIXME thumb2
5450 // This must be a multiple of 4 between -508 and 508, for
5451 // ADD/SUB sp = sp + immediate.
5452 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
5457 Result = DAG.getTargetConstant(CVal, Op.getValueType());
5461 if (Result.getNode()) {
5462 Ops.push_back(Result);
5465 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
5469 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
5470 // The ARM target isn't yet aware of offsets.
5474 int ARM::getVFPf32Imm(const APFloat &FPImm) {
5475 APInt Imm = FPImm.bitcastToAPInt();
5476 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
5477 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127
5478 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits
5480 // We can handle 4 bits of mantissa.
5481 // mantissa = (16+UInt(e:f:g:h))/16.
5482 if (Mantissa & 0x7ffff)
5485 if ((Mantissa & 0xf) != Mantissa)
5488 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
5489 if (Exp < -3 || Exp > 4)
5491 Exp = ((Exp+3) & 0x7) ^ 4;
5493 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
5496 int ARM::getVFPf64Imm(const APFloat &FPImm) {
5497 APInt Imm = FPImm.bitcastToAPInt();
5498 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
5499 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
5500 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffLL;
5502 // We can handle 4 bits of mantissa.
5503 // mantissa = (16+UInt(e:f:g:h))/16.
5504 if (Mantissa & 0xffffffffffffLL)
5507 if ((Mantissa & 0xf) != Mantissa)
5510 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
5511 if (Exp < -3 || Exp > 4)
5513 Exp = ((Exp+3) & 0x7) ^ 4;
5515 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
5518 bool ARM::isBitFieldInvertedMask(unsigned v) {
5519 if (v == 0xffffffff)
5521 // there can be 1's on either or both "outsides", all the "inside"
5523 unsigned int lsb = 0, msb = 31;
5524 while (v & (1 << msb)) --msb;
5525 while (v & (1 << lsb)) ++lsb;
5526 for (unsigned int i = lsb; i <= msb; ++i) {
5533 /// isFPImmLegal - Returns true if the target can instruction select the
5534 /// specified FP immediate natively. If false, the legalizer will
5535 /// materialize the FP immediate as a load from a constant pool.
5536 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
5537 if (!Subtarget->hasVFP3())
5540 return ARM::getVFPf32Imm(Imm) != -1;
5542 return ARM::getVFPf64Imm(Imm) != -1;
5546 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
5547 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
5548 /// specified in the intrinsic calls.
5549 bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
5551 unsigned Intrinsic) const {
5552 switch (Intrinsic) {
5553 case Intrinsic::arm_neon_vld1:
5554 case Intrinsic::arm_neon_vld2:
5555 case Intrinsic::arm_neon_vld3:
5556 case Intrinsic::arm_neon_vld4:
5557 case Intrinsic::arm_neon_vld2lane:
5558 case Intrinsic::arm_neon_vld3lane:
5559 case Intrinsic::arm_neon_vld4lane: {
5560 Info.opc = ISD::INTRINSIC_W_CHAIN;
5561 // Conservatively set memVT to the entire set of vectors loaded.
5562 uint64_t NumElts = getTargetData()->getTypeAllocSize(I.getType()) / 8;
5563 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
5564 Info.ptrVal = I.getArgOperand(0);
5566 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
5567 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
5568 Info.vol = false; // volatile loads with NEON intrinsics not supported
5569 Info.readMem = true;
5570 Info.writeMem = false;
5573 case Intrinsic::arm_neon_vst1:
5574 case Intrinsic::arm_neon_vst2:
5575 case Intrinsic::arm_neon_vst3:
5576 case Intrinsic::arm_neon_vst4:
5577 case Intrinsic::arm_neon_vst2lane:
5578 case Intrinsic::arm_neon_vst3lane:
5579 case Intrinsic::arm_neon_vst4lane: {
5580 Info.opc = ISD::INTRINSIC_VOID;
5581 // Conservatively set memVT to the entire set of vectors stored.
5582 unsigned NumElts = 0;
5583 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
5584 const Type *ArgTy = I.getArgOperand(ArgI)->getType();
5585 if (!ArgTy->isVectorTy())
5587 NumElts += getTargetData()->getTypeAllocSize(ArgTy) / 8;
5589 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
5590 Info.ptrVal = I.getArgOperand(0);
5592 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
5593 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
5594 Info.vol = false; // volatile stores with NEON intrinsics not supported
5595 Info.readMem = false;
5596 Info.writeMem = true;