1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "arm-isel"
16 #include "ARMISelLowering.h"
18 #include "ARMCallingConv.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMPerfectShuffle.h"
22 #include "ARMSubtarget.h"
23 #include "ARMTargetMachine.h"
24 #include "ARMTargetObjectFile.h"
25 #include "MCTargetDesc/ARMAddressingModes.h"
26 #include "llvm/CallingConv.h"
27 #include "llvm/Constants.h"
28 #include "llvm/Function.h"
29 #include "llvm/GlobalValue.h"
30 #include "llvm/Instruction.h"
31 #include "llvm/Instructions.h"
32 #include "llvm/Intrinsics.h"
33 #include "llvm/Type.h"
34 #include "llvm/CodeGen/CallingConvLower.h"
35 #include "llvm/CodeGen/IntrinsicLowering.h"
36 #include "llvm/CodeGen/MachineBasicBlock.h"
37 #include "llvm/CodeGen/MachineFrameInfo.h"
38 #include "llvm/CodeGen/MachineFunction.h"
39 #include "llvm/CodeGen/MachineInstrBuilder.h"
40 #include "llvm/CodeGen/MachineModuleInfo.h"
41 #include "llvm/CodeGen/MachineRegisterInfo.h"
42 #include "llvm/CodeGen/SelectionDAG.h"
43 #include "llvm/MC/MCSectionMachO.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/ADT/StringExtras.h"
46 #include "llvm/ADT/Statistic.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Support/raw_ostream.h"
53 STATISTIC(NumTailCalls, "Number of tail calls");
54 STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt");
55 STATISTIC(NumLoopByVals, "Number of loops generated for byval arguments");
57 // This option should go away when tail calls fully work.
59 EnableARMTailCalls("arm-tail-calls", cl::Hidden,
60 cl::desc("Generate tail calls (TEMPORARY OPTION)."),
64 EnableARMLongCalls("arm-long-calls", cl::Hidden,
65 cl::desc("Generate calls via indirect call instructions"),
69 ARMInterworking("arm-interworking", cl::Hidden,
70 cl::desc("Enable / disable ARM interworking (for debugging only)"),
74 class ARMCCState : public CCState {
76 ARMCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
77 const TargetMachine &TM, SmallVector<CCValAssign, 16> &locs,
78 LLVMContext &C, ParmContext PC)
79 : CCState(CC, isVarArg, MF, TM, locs, C) {
80 assert(((PC == Call) || (PC == Prologue)) &&
81 "ARMCCState users must specify whether their context is call"
82 "or prologue generation.");
88 // The APCS parameter registers.
89 static const uint16_t GPRArgRegs[] = {
90 ARM::R0, ARM::R1, ARM::R2, ARM::R3
93 void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT,
94 MVT PromotedBitwiseVT) {
95 if (VT != PromotedLdStVT) {
96 setOperationAction(ISD::LOAD, VT, Promote);
97 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
99 setOperationAction(ISD::STORE, VT, Promote);
100 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
103 MVT ElemTy = VT.getVectorElementType();
104 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
105 setOperationAction(ISD::SETCC, VT, Custom);
106 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
107 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
108 if (ElemTy == MVT::i32) {
109 setOperationAction(ISD::SINT_TO_FP, VT, Custom);
110 setOperationAction(ISD::UINT_TO_FP, VT, Custom);
111 setOperationAction(ISD::FP_TO_SINT, VT, Custom);
112 setOperationAction(ISD::FP_TO_UINT, VT, Custom);
114 setOperationAction(ISD::SINT_TO_FP, VT, Expand);
115 setOperationAction(ISD::UINT_TO_FP, VT, Expand);
116 setOperationAction(ISD::FP_TO_SINT, VT, Expand);
117 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
119 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
120 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
121 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal);
122 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
123 setOperationAction(ISD::SELECT, VT, Expand);
124 setOperationAction(ISD::SELECT_CC, VT, Expand);
125 setOperationAction(ISD::VSELECT, VT, Expand);
126 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
127 if (VT.isInteger()) {
128 setOperationAction(ISD::SHL, VT, Custom);
129 setOperationAction(ISD::SRA, VT, Custom);
130 setOperationAction(ISD::SRL, VT, Custom);
133 // Promote all bit-wise operations.
134 if (VT.isInteger() && VT != PromotedBitwiseVT) {
135 setOperationAction(ISD::AND, VT, Promote);
136 AddPromotedToType (ISD::AND, VT, PromotedBitwiseVT);
137 setOperationAction(ISD::OR, VT, Promote);
138 AddPromotedToType (ISD::OR, VT, PromotedBitwiseVT);
139 setOperationAction(ISD::XOR, VT, Promote);
140 AddPromotedToType (ISD::XOR, VT, PromotedBitwiseVT);
143 // Neon does not support vector divide/remainder operations.
144 setOperationAction(ISD::SDIV, VT, Expand);
145 setOperationAction(ISD::UDIV, VT, Expand);
146 setOperationAction(ISD::FDIV, VT, Expand);
147 setOperationAction(ISD::SREM, VT, Expand);
148 setOperationAction(ISD::UREM, VT, Expand);
149 setOperationAction(ISD::FREM, VT, Expand);
152 void ARMTargetLowering::addDRTypeForNEON(MVT VT) {
153 addRegisterClass(VT, &ARM::DPRRegClass);
154 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
157 void ARMTargetLowering::addQRTypeForNEON(MVT VT) {
158 addRegisterClass(VT, &ARM::QPRRegClass);
159 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
162 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
163 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
164 return new TargetLoweringObjectFileMachO();
166 return new ARMElfTargetObjectFile();
169 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
170 : TargetLowering(TM, createTLOF(TM)) {
171 Subtarget = &TM.getSubtarget<ARMSubtarget>();
172 RegInfo = TM.getRegisterInfo();
173 Itins = TM.getInstrItineraryData();
175 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
177 if (Subtarget->isTargetDarwin()) {
178 // Uses VFP for Thumb libfuncs if available.
179 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
180 // Single-precision floating-point arithmetic.
181 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
182 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
183 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
184 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
186 // Double-precision floating-point arithmetic.
187 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
188 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
189 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
190 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
192 // Single-precision comparisons.
193 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
194 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
195 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
196 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
197 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
198 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
199 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
200 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
202 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
203 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
204 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
205 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
206 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
207 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
208 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
209 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
211 // Double-precision comparisons.
212 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
213 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
214 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
215 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
216 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
217 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
218 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
219 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
221 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
222 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
223 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
224 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
225 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
226 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
227 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
228 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
230 // Floating-point to integer conversions.
231 // i64 conversions are done via library routines even when generating VFP
232 // instructions, so use the same ones.
233 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
234 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
235 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
236 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
238 // Conversions between floating types.
239 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
240 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
242 // Integer to floating-point conversions.
243 // i64 conversions are done via library routines even when generating VFP
244 // instructions, so use the same ones.
245 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
246 // e.g., __floatunsidf vs. __floatunssidfvfp.
247 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
248 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
249 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
250 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
254 // These libcalls are not available in 32-bit.
255 setLibcallName(RTLIB::SHL_I128, 0);
256 setLibcallName(RTLIB::SRL_I128, 0);
257 setLibcallName(RTLIB::SRA_I128, 0);
259 if (Subtarget->isAAPCS_ABI() && !Subtarget->isTargetDarwin()) {
260 // Double-precision floating-point arithmetic helper functions
261 // RTABI chapter 4.1.2, Table 2
262 setLibcallName(RTLIB::ADD_F64, "__aeabi_dadd");
263 setLibcallName(RTLIB::DIV_F64, "__aeabi_ddiv");
264 setLibcallName(RTLIB::MUL_F64, "__aeabi_dmul");
265 setLibcallName(RTLIB::SUB_F64, "__aeabi_dsub");
266 setLibcallCallingConv(RTLIB::ADD_F64, CallingConv::ARM_AAPCS);
267 setLibcallCallingConv(RTLIB::DIV_F64, CallingConv::ARM_AAPCS);
268 setLibcallCallingConv(RTLIB::MUL_F64, CallingConv::ARM_AAPCS);
269 setLibcallCallingConv(RTLIB::SUB_F64, CallingConv::ARM_AAPCS);
271 // Double-precision floating-point comparison helper functions
272 // RTABI chapter 4.1.2, Table 3
273 setLibcallName(RTLIB::OEQ_F64, "__aeabi_dcmpeq");
274 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
275 setLibcallName(RTLIB::UNE_F64, "__aeabi_dcmpeq");
276 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETEQ);
277 setLibcallName(RTLIB::OLT_F64, "__aeabi_dcmplt");
278 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
279 setLibcallName(RTLIB::OLE_F64, "__aeabi_dcmple");
280 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
281 setLibcallName(RTLIB::OGE_F64, "__aeabi_dcmpge");
282 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
283 setLibcallName(RTLIB::OGT_F64, "__aeabi_dcmpgt");
284 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
285 setLibcallName(RTLIB::UO_F64, "__aeabi_dcmpun");
286 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
287 setLibcallName(RTLIB::O_F64, "__aeabi_dcmpun");
288 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
289 setLibcallCallingConv(RTLIB::OEQ_F64, CallingConv::ARM_AAPCS);
290 setLibcallCallingConv(RTLIB::UNE_F64, CallingConv::ARM_AAPCS);
291 setLibcallCallingConv(RTLIB::OLT_F64, CallingConv::ARM_AAPCS);
292 setLibcallCallingConv(RTLIB::OLE_F64, CallingConv::ARM_AAPCS);
293 setLibcallCallingConv(RTLIB::OGE_F64, CallingConv::ARM_AAPCS);
294 setLibcallCallingConv(RTLIB::OGT_F64, CallingConv::ARM_AAPCS);
295 setLibcallCallingConv(RTLIB::UO_F64, CallingConv::ARM_AAPCS);
296 setLibcallCallingConv(RTLIB::O_F64, CallingConv::ARM_AAPCS);
298 // Single-precision floating-point arithmetic helper functions
299 // RTABI chapter 4.1.2, Table 4
300 setLibcallName(RTLIB::ADD_F32, "__aeabi_fadd");
301 setLibcallName(RTLIB::DIV_F32, "__aeabi_fdiv");
302 setLibcallName(RTLIB::MUL_F32, "__aeabi_fmul");
303 setLibcallName(RTLIB::SUB_F32, "__aeabi_fsub");
304 setLibcallCallingConv(RTLIB::ADD_F32, CallingConv::ARM_AAPCS);
305 setLibcallCallingConv(RTLIB::DIV_F32, CallingConv::ARM_AAPCS);
306 setLibcallCallingConv(RTLIB::MUL_F32, CallingConv::ARM_AAPCS);
307 setLibcallCallingConv(RTLIB::SUB_F32, CallingConv::ARM_AAPCS);
309 // Single-precision floating-point comparison helper functions
310 // RTABI chapter 4.1.2, Table 5
311 setLibcallName(RTLIB::OEQ_F32, "__aeabi_fcmpeq");
312 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
313 setLibcallName(RTLIB::UNE_F32, "__aeabi_fcmpeq");
314 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETEQ);
315 setLibcallName(RTLIB::OLT_F32, "__aeabi_fcmplt");
316 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
317 setLibcallName(RTLIB::OLE_F32, "__aeabi_fcmple");
318 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
319 setLibcallName(RTLIB::OGE_F32, "__aeabi_fcmpge");
320 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
321 setLibcallName(RTLIB::OGT_F32, "__aeabi_fcmpgt");
322 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
323 setLibcallName(RTLIB::UO_F32, "__aeabi_fcmpun");
324 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
325 setLibcallName(RTLIB::O_F32, "__aeabi_fcmpun");
326 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
327 setLibcallCallingConv(RTLIB::OEQ_F32, CallingConv::ARM_AAPCS);
328 setLibcallCallingConv(RTLIB::UNE_F32, CallingConv::ARM_AAPCS);
329 setLibcallCallingConv(RTLIB::OLT_F32, CallingConv::ARM_AAPCS);
330 setLibcallCallingConv(RTLIB::OLE_F32, CallingConv::ARM_AAPCS);
331 setLibcallCallingConv(RTLIB::OGE_F32, CallingConv::ARM_AAPCS);
332 setLibcallCallingConv(RTLIB::OGT_F32, CallingConv::ARM_AAPCS);
333 setLibcallCallingConv(RTLIB::UO_F32, CallingConv::ARM_AAPCS);
334 setLibcallCallingConv(RTLIB::O_F32, CallingConv::ARM_AAPCS);
336 // Floating-point to integer conversions.
337 // RTABI chapter 4.1.2, Table 6
338 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz");
339 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz");
340 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz");
341 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz");
342 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz");
343 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz");
344 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz");
345 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz");
346 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I32, CallingConv::ARM_AAPCS);
347 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I32, CallingConv::ARM_AAPCS);
348 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I64, CallingConv::ARM_AAPCS);
349 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::ARM_AAPCS);
350 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I32, CallingConv::ARM_AAPCS);
351 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I32, CallingConv::ARM_AAPCS);
352 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I64, CallingConv::ARM_AAPCS);
353 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::ARM_AAPCS);
355 // Conversions between floating types.
356 // RTABI chapter 4.1.2, Table 7
357 setLibcallName(RTLIB::FPROUND_F64_F32, "__aeabi_d2f");
358 setLibcallName(RTLIB::FPEXT_F32_F64, "__aeabi_f2d");
359 setLibcallCallingConv(RTLIB::FPROUND_F64_F32, CallingConv::ARM_AAPCS);
360 setLibcallCallingConv(RTLIB::FPEXT_F32_F64, CallingConv::ARM_AAPCS);
362 // Integer to floating-point conversions.
363 // RTABI chapter 4.1.2, Table 8
364 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d");
365 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d");
366 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d");
367 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d");
368 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f");
369 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f");
370 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f");
371 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f");
372 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
373 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
374 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
375 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
376 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
377 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
378 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
379 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
381 // Long long helper functions
382 // RTABI chapter 4.2, Table 9
383 setLibcallName(RTLIB::MUL_I64, "__aeabi_lmul");
384 setLibcallName(RTLIB::SHL_I64, "__aeabi_llsl");
385 setLibcallName(RTLIB::SRL_I64, "__aeabi_llsr");
386 setLibcallName(RTLIB::SRA_I64, "__aeabi_lasr");
387 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::ARM_AAPCS);
388 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::ARM_AAPCS);
389 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::ARM_AAPCS);
390 setLibcallCallingConv(RTLIB::SHL_I64, CallingConv::ARM_AAPCS);
391 setLibcallCallingConv(RTLIB::SRL_I64, CallingConv::ARM_AAPCS);
392 setLibcallCallingConv(RTLIB::SRA_I64, CallingConv::ARM_AAPCS);
394 // Integer division functions
395 // RTABI chapter 4.3.1
396 setLibcallName(RTLIB::SDIV_I8, "__aeabi_idiv");
397 setLibcallName(RTLIB::SDIV_I16, "__aeabi_idiv");
398 setLibcallName(RTLIB::SDIV_I32, "__aeabi_idiv");
399 setLibcallName(RTLIB::SDIV_I64, "__aeabi_ldivmod");
400 setLibcallName(RTLIB::UDIV_I8, "__aeabi_uidiv");
401 setLibcallName(RTLIB::UDIV_I16, "__aeabi_uidiv");
402 setLibcallName(RTLIB::UDIV_I32, "__aeabi_uidiv");
403 setLibcallName(RTLIB::UDIV_I64, "__aeabi_uldivmod");
404 setLibcallCallingConv(RTLIB::SDIV_I8, CallingConv::ARM_AAPCS);
405 setLibcallCallingConv(RTLIB::SDIV_I16, CallingConv::ARM_AAPCS);
406 setLibcallCallingConv(RTLIB::SDIV_I32, CallingConv::ARM_AAPCS);
407 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::ARM_AAPCS);
408 setLibcallCallingConv(RTLIB::UDIV_I8, CallingConv::ARM_AAPCS);
409 setLibcallCallingConv(RTLIB::UDIV_I16, CallingConv::ARM_AAPCS);
410 setLibcallCallingConv(RTLIB::UDIV_I32, CallingConv::ARM_AAPCS);
411 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::ARM_AAPCS);
414 // RTABI chapter 4.3.4
415 setLibcallName(RTLIB::MEMCPY, "__aeabi_memcpy");
416 setLibcallName(RTLIB::MEMMOVE, "__aeabi_memmove");
417 setLibcallName(RTLIB::MEMSET, "__aeabi_memset");
418 setLibcallCallingConv(RTLIB::MEMCPY, CallingConv::ARM_AAPCS);
419 setLibcallCallingConv(RTLIB::MEMMOVE, CallingConv::ARM_AAPCS);
420 setLibcallCallingConv(RTLIB::MEMSET, CallingConv::ARM_AAPCS);
423 // Use divmod compiler-rt calls for iOS 5.0 and later.
424 if (Subtarget->getTargetTriple().getOS() == Triple::IOS &&
425 !Subtarget->getTargetTriple().isOSVersionLT(5, 0)) {
426 setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
427 setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
430 if (Subtarget->isThumb1Only())
431 addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
433 addRegisterClass(MVT::i32, &ARM::GPRRegClass);
434 if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
435 !Subtarget->isThumb1Only()) {
436 addRegisterClass(MVT::f32, &ARM::SPRRegClass);
437 if (!Subtarget->isFPOnlySP())
438 addRegisterClass(MVT::f64, &ARM::DPRRegClass);
440 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
443 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
444 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
445 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
446 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
447 setTruncStoreAction((MVT::SimpleValueType)VT,
448 (MVT::SimpleValueType)InnerVT, Expand);
449 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
450 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
451 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
454 setOperationAction(ISD::ConstantFP, MVT::f32, Custom);
456 if (Subtarget->hasNEON()) {
457 addDRTypeForNEON(MVT::v2f32);
458 addDRTypeForNEON(MVT::v8i8);
459 addDRTypeForNEON(MVT::v4i16);
460 addDRTypeForNEON(MVT::v2i32);
461 addDRTypeForNEON(MVT::v1i64);
463 addQRTypeForNEON(MVT::v4f32);
464 addQRTypeForNEON(MVT::v2f64);
465 addQRTypeForNEON(MVT::v16i8);
466 addQRTypeForNEON(MVT::v8i16);
467 addQRTypeForNEON(MVT::v4i32);
468 addQRTypeForNEON(MVT::v2i64);
470 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
471 // neither Neon nor VFP support any arithmetic operations on it.
472 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
473 // supported for v4f32.
474 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
475 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
476 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
477 // FIXME: Code duplication: FDIV and FREM are expanded always, see
478 // ARMTargetLowering::addTypeForNEON method for details.
479 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
480 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
481 // FIXME: Create unittest.
482 // In another words, find a way when "copysign" appears in DAG with vector
484 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
485 // FIXME: Code duplication: SETCC has custom operation action, see
486 // ARMTargetLowering::addTypeForNEON method for details.
487 setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
488 // FIXME: Create unittest for FNEG and for FABS.
489 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
490 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
491 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
492 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
493 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
494 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
495 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
496 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
497 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
498 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
499 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
500 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
501 // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR.
502 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
503 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
504 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
505 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
506 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
508 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
509 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
510 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
511 setOperationAction(ISD::FPOWI, MVT::v4f32, Expand);
512 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
513 setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
514 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
515 setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
516 setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
517 setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
518 setOperationAction(ISD::FFLOOR, MVT::v4f32, Expand);
520 // Neon does not support some operations on v1i64 and v2i64 types.
521 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
522 // Custom handling for some quad-vector types to detect VMULL.
523 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
524 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
525 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
526 // Custom handling for some vector types to avoid expensive expansions
527 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
528 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
529 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
530 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
531 setOperationAction(ISD::SETCC, MVT::v1i64, Expand);
532 setOperationAction(ISD::SETCC, MVT::v2i64, Expand);
533 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
534 // a destination type that is wider than the source, and nor does
535 // it have a FP_TO_[SU]INT instruction with a narrower destination than
537 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
538 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
539 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
540 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
542 setTargetDAGCombine(ISD::INTRINSIC_VOID);
543 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
544 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
545 setTargetDAGCombine(ISD::SHL);
546 setTargetDAGCombine(ISD::SRL);
547 setTargetDAGCombine(ISD::SRA);
548 setTargetDAGCombine(ISD::SIGN_EXTEND);
549 setTargetDAGCombine(ISD::ZERO_EXTEND);
550 setTargetDAGCombine(ISD::ANY_EXTEND);
551 setTargetDAGCombine(ISD::SELECT_CC);
552 setTargetDAGCombine(ISD::BUILD_VECTOR);
553 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
554 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
555 setTargetDAGCombine(ISD::STORE);
556 setTargetDAGCombine(ISD::FP_TO_SINT);
557 setTargetDAGCombine(ISD::FP_TO_UINT);
558 setTargetDAGCombine(ISD::FDIV);
560 // It is legal to extload from v4i8 to v4i16 or v4i32.
561 MVT Tys[6] = {MVT::v8i8, MVT::v4i8, MVT::v2i8,
562 MVT::v4i16, MVT::v2i16,
564 for (unsigned i = 0; i < 6; ++i) {
565 setLoadExtAction(ISD::EXTLOAD, Tys[i], Legal);
566 setLoadExtAction(ISD::ZEXTLOAD, Tys[i], Legal);
567 setLoadExtAction(ISD::SEXTLOAD, Tys[i], Legal);
571 // ARM and Thumb2 support UMLAL/SMLAL.
572 if (!Subtarget->isThumb1Only())
573 setTargetDAGCombine(ISD::ADDC);
576 computeRegisterProperties();
578 // ARM does not have f32 extending load.
579 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
581 // ARM does not have i1 sign extending load.
582 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
584 // ARM supports all 4 flavors of integer indexed load / store.
585 if (!Subtarget->isThumb1Only()) {
586 for (unsigned im = (unsigned)ISD::PRE_INC;
587 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
588 setIndexedLoadAction(im, MVT::i1, Legal);
589 setIndexedLoadAction(im, MVT::i8, Legal);
590 setIndexedLoadAction(im, MVT::i16, Legal);
591 setIndexedLoadAction(im, MVT::i32, Legal);
592 setIndexedStoreAction(im, MVT::i1, Legal);
593 setIndexedStoreAction(im, MVT::i8, Legal);
594 setIndexedStoreAction(im, MVT::i16, Legal);
595 setIndexedStoreAction(im, MVT::i32, Legal);
599 // i64 operation support.
600 setOperationAction(ISD::MUL, MVT::i64, Expand);
601 setOperationAction(ISD::MULHU, MVT::i32, Expand);
602 if (Subtarget->isThumb1Only()) {
603 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
604 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
606 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
607 || (Subtarget->isThumb2() && !Subtarget->hasThumb2DSP()))
608 setOperationAction(ISD::MULHS, MVT::i32, Expand);
610 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
611 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
612 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
613 setOperationAction(ISD::SRL, MVT::i64, Custom);
614 setOperationAction(ISD::SRA, MVT::i64, Custom);
616 if (!Subtarget->isThumb1Only()) {
617 // FIXME: We should do this for Thumb1 as well.
618 setOperationAction(ISD::ADDC, MVT::i32, Custom);
619 setOperationAction(ISD::ADDE, MVT::i32, Custom);
620 setOperationAction(ISD::SUBC, MVT::i32, Custom);
621 setOperationAction(ISD::SUBE, MVT::i32, Custom);
624 // ARM does not have ROTL.
625 setOperationAction(ISD::ROTL, MVT::i32, Expand);
626 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
627 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
628 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
629 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
631 // These just redirect to CTTZ and CTLZ on ARM.
632 setOperationAction(ISD::CTTZ_ZERO_UNDEF , MVT::i32 , Expand);
633 setOperationAction(ISD::CTLZ_ZERO_UNDEF , MVT::i32 , Expand);
635 // Only ARMv6 has BSWAP.
636 if (!Subtarget->hasV6Ops())
637 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
639 if (!(Subtarget->hasDivide() && Subtarget->isThumb2()) &&
640 !(Subtarget->hasDivideInARMMode() && !Subtarget->isThumb())) {
641 // These are expanded into libcalls if the cpu doesn't have HW divider.
642 setOperationAction(ISD::SDIV, MVT::i32, Expand);
643 setOperationAction(ISD::UDIV, MVT::i32, Expand);
645 setOperationAction(ISD::SREM, MVT::i32, Expand);
646 setOperationAction(ISD::UREM, MVT::i32, Expand);
647 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
648 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
650 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
651 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
652 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
653 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
654 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
656 setOperationAction(ISD::TRAP, MVT::Other, Legal);
658 // Use the default implementation.
659 setOperationAction(ISD::VASTART, MVT::Other, Custom);
660 setOperationAction(ISD::VAARG, MVT::Other, Expand);
661 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
662 setOperationAction(ISD::VAEND, MVT::Other, Expand);
663 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
664 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
666 if (!Subtarget->isTargetDarwin()) {
667 // Non-Darwin platforms may return values in these registers via the
668 // personality function.
669 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
670 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
671 setExceptionPointerRegister(ARM::R0);
672 setExceptionSelectorRegister(ARM::R1);
675 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
676 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
677 // the default expansion.
678 // FIXME: This should be checking for v6k, not just v6.
679 if (Subtarget->hasDataBarrier() ||
680 (Subtarget->hasV6Ops() && !Subtarget->isThumb())) {
681 // membarrier needs custom lowering; the rest are legal and handled
683 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
684 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
685 // Custom lowering for 64-bit ops
686 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom);
687 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom);
688 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom);
689 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom);
690 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom);
691 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom);
692 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
693 // Automatically insert fences (dmb ist) around ATOMIC_SWAP etc.
694 setInsertFencesForAtomic(true);
696 // Set them all for expansion, which will force libcalls.
697 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
698 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
699 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
700 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
701 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
702 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
703 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
704 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
705 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
706 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
707 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
708 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
709 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
710 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
711 // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the
712 // Unordered/Monotonic case.
713 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
714 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
715 // Since the libcalls include locking, fold in the fences
716 setShouldFoldAtomicFences(true);
719 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
721 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
722 if (!Subtarget->hasV6Ops()) {
723 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
724 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
726 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
728 if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
729 !Subtarget->isThumb1Only()) {
730 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
731 // iff target supports vfp2.
732 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
733 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
736 // We want to custom lower some of our intrinsics.
737 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
738 if (Subtarget->isTargetDarwin()) {
739 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
740 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
741 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
744 setOperationAction(ISD::SETCC, MVT::i32, Expand);
745 setOperationAction(ISD::SETCC, MVT::f32, Expand);
746 setOperationAction(ISD::SETCC, MVT::f64, Expand);
747 setOperationAction(ISD::SELECT, MVT::i32, Custom);
748 setOperationAction(ISD::SELECT, MVT::f32, Custom);
749 setOperationAction(ISD::SELECT, MVT::f64, Custom);
750 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
751 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
752 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
754 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
755 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
756 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
757 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
758 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
760 // We don't support sin/cos/fmod/copysign/pow
761 setOperationAction(ISD::FSIN, MVT::f64, Expand);
762 setOperationAction(ISD::FSIN, MVT::f32, Expand);
763 setOperationAction(ISD::FCOS, MVT::f32, Expand);
764 setOperationAction(ISD::FCOS, MVT::f64, Expand);
765 setOperationAction(ISD::FREM, MVT::f64, Expand);
766 setOperationAction(ISD::FREM, MVT::f32, Expand);
767 if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
768 !Subtarget->isThumb1Only()) {
769 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
770 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
772 setOperationAction(ISD::FPOW, MVT::f64, Expand);
773 setOperationAction(ISD::FPOW, MVT::f32, Expand);
775 if (!Subtarget->hasVFP4()) {
776 setOperationAction(ISD::FMA, MVT::f64, Expand);
777 setOperationAction(ISD::FMA, MVT::f32, Expand);
780 // Various VFP goodness
781 if (!TM.Options.UseSoftFloat && !Subtarget->isThumb1Only()) {
782 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
783 if (Subtarget->hasVFP2()) {
784 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
785 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
786 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
787 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
789 // Special handling for half-precision FP.
790 if (!Subtarget->hasFP16()) {
791 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
792 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand);
796 // We have target-specific dag combine patterns for the following nodes:
797 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
798 setTargetDAGCombine(ISD::ADD);
799 setTargetDAGCombine(ISD::SUB);
800 setTargetDAGCombine(ISD::MUL);
801 setTargetDAGCombine(ISD::AND);
802 setTargetDAGCombine(ISD::OR);
803 setTargetDAGCombine(ISD::XOR);
805 if (Subtarget->hasV6Ops())
806 setTargetDAGCombine(ISD::SRL);
808 setStackPointerRegisterToSaveRestore(ARM::SP);
810 if (TM.Options.UseSoftFloat || Subtarget->isThumb1Only() ||
811 !Subtarget->hasVFP2())
812 setSchedulingPreference(Sched::RegPressure);
814 setSchedulingPreference(Sched::Hybrid);
816 //// temporary - rewrite interface to use type
817 maxStoresPerMemcpy = maxStoresPerMemcpyOptSize = 1;
818 maxStoresPerMemset = 16;
819 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
821 // On ARM arguments smaller than 4 bytes are extended, so all arguments
822 // are at least 4 bytes aligned.
823 setMinStackArgumentAlignment(4);
825 benefitFromCodePlacementOpt = true;
827 // Prefer likely predicted branches to selects on out-of-order cores.
828 predictableSelectIsExpensive = Subtarget->isLikeA9();
830 setMinFunctionAlignment(Subtarget->isThumb() ? 1 : 2);
833 // FIXME: It might make sense to define the representative register class as the
834 // nearest super-register that has a non-null superset. For example, DPR_VFP2 is
835 // a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
836 // SPR's representative would be DPR_VFP2. This should work well if register
837 // pressure tracking were modified such that a register use would increment the
838 // pressure of the register class's representative and all of it's super
839 // classes' representatives transitively. We have not implemented this because
840 // of the difficulty prior to coalescing of modeling operand register classes
841 // due to the common occurrence of cross class copies and subregister insertions
843 std::pair<const TargetRegisterClass*, uint8_t>
844 ARMTargetLowering::findRepresentativeClass(EVT VT) const{
845 const TargetRegisterClass *RRC = 0;
847 switch (VT.getSimpleVT().SimpleTy) {
849 return TargetLowering::findRepresentativeClass(VT);
850 // Use DPR as representative register class for all floating point
851 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
852 // the cost is 1 for both f32 and f64.
853 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
854 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
855 RRC = &ARM::DPRRegClass;
856 // When NEON is used for SP, only half of the register file is available
857 // because operations that define both SP and DP results will be constrained
858 // to the VFP2 class (D0-D15). We currently model this constraint prior to
859 // coalescing by double-counting the SP regs. See the FIXME above.
860 if (Subtarget->useNEONForSinglePrecisionFP())
863 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
864 case MVT::v4f32: case MVT::v2f64:
865 RRC = &ARM::DPRRegClass;
869 RRC = &ARM::DPRRegClass;
873 RRC = &ARM::DPRRegClass;
877 return std::make_pair(RRC, Cost);
880 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
883 case ARMISD::Wrapper: return "ARMISD::Wrapper";
884 case ARMISD::WrapperDYN: return "ARMISD::WrapperDYN";
885 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
886 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
887 case ARMISD::CALL: return "ARMISD::CALL";
888 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
889 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
890 case ARMISD::tCALL: return "ARMISD::tCALL";
891 case ARMISD::BRCOND: return "ARMISD::BRCOND";
892 case ARMISD::BR_JT: return "ARMISD::BR_JT";
893 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
894 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
895 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
896 case ARMISD::CMP: return "ARMISD::CMP";
897 case ARMISD::CMN: return "ARMISD::CMN";
898 case ARMISD::CMPZ: return "ARMISD::CMPZ";
899 case ARMISD::CMPFP: return "ARMISD::CMPFP";
900 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
901 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
902 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
904 case ARMISD::CMOV: return "ARMISD::CMOV";
906 case ARMISD::RBIT: return "ARMISD::RBIT";
908 case ARMISD::FTOSI: return "ARMISD::FTOSI";
909 case ARMISD::FTOUI: return "ARMISD::FTOUI";
910 case ARMISD::SITOF: return "ARMISD::SITOF";
911 case ARMISD::UITOF: return "ARMISD::UITOF";
913 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
914 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
915 case ARMISD::RRX: return "ARMISD::RRX";
917 case ARMISD::ADDC: return "ARMISD::ADDC";
918 case ARMISD::ADDE: return "ARMISD::ADDE";
919 case ARMISD::SUBC: return "ARMISD::SUBC";
920 case ARMISD::SUBE: return "ARMISD::SUBE";
922 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
923 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
925 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
926 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
928 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
930 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
932 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
934 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER";
935 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
937 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
939 case ARMISD::VCEQ: return "ARMISD::VCEQ";
940 case ARMISD::VCEQZ: return "ARMISD::VCEQZ";
941 case ARMISD::VCGE: return "ARMISD::VCGE";
942 case ARMISD::VCGEZ: return "ARMISD::VCGEZ";
943 case ARMISD::VCLEZ: return "ARMISD::VCLEZ";
944 case ARMISD::VCGEU: return "ARMISD::VCGEU";
945 case ARMISD::VCGT: return "ARMISD::VCGT";
946 case ARMISD::VCGTZ: return "ARMISD::VCGTZ";
947 case ARMISD::VCLTZ: return "ARMISD::VCLTZ";
948 case ARMISD::VCGTU: return "ARMISD::VCGTU";
949 case ARMISD::VTST: return "ARMISD::VTST";
951 case ARMISD::VSHL: return "ARMISD::VSHL";
952 case ARMISD::VSHRs: return "ARMISD::VSHRs";
953 case ARMISD::VSHRu: return "ARMISD::VSHRu";
954 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
955 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
956 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
957 case ARMISD::VSHRN: return "ARMISD::VSHRN";
958 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
959 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
960 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
961 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
962 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
963 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
964 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
965 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
966 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
967 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
968 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
969 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
970 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
971 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
972 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
973 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
974 case ARMISD::VMOVFPIMM: return "ARMISD::VMOVFPIMM";
975 case ARMISD::VDUP: return "ARMISD::VDUP";
976 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
977 case ARMISD::VEXT: return "ARMISD::VEXT";
978 case ARMISD::VREV64: return "ARMISD::VREV64";
979 case ARMISD::VREV32: return "ARMISD::VREV32";
980 case ARMISD::VREV16: return "ARMISD::VREV16";
981 case ARMISD::VZIP: return "ARMISD::VZIP";
982 case ARMISD::VUZP: return "ARMISD::VUZP";
983 case ARMISD::VTRN: return "ARMISD::VTRN";
984 case ARMISD::VTBL1: return "ARMISD::VTBL1";
985 case ARMISD::VTBL2: return "ARMISD::VTBL2";
986 case ARMISD::VMULLs: return "ARMISD::VMULLs";
987 case ARMISD::VMULLu: return "ARMISD::VMULLu";
988 case ARMISD::UMLAL: return "ARMISD::UMLAL";
989 case ARMISD::SMLAL: return "ARMISD::SMLAL";
990 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
991 case ARMISD::FMAX: return "ARMISD::FMAX";
992 case ARMISD::FMIN: return "ARMISD::FMIN";
993 case ARMISD::BFI: return "ARMISD::BFI";
994 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
995 case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
996 case ARMISD::VBSL: return "ARMISD::VBSL";
997 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
998 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
999 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
1000 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD";
1001 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD";
1002 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD";
1003 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD";
1004 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD";
1005 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD";
1006 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD";
1007 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD";
1008 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD";
1009 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD";
1010 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD";
1011 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD";
1012 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD";
1013 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD";
1014 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD";
1015 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD";
1016 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD";
1020 EVT ARMTargetLowering::getSetCCResultType(EVT VT) const {
1021 if (!VT.isVector()) return getPointerTy();
1022 return VT.changeVectorElementTypeToInteger();
1025 /// getRegClassFor - Return the register class that should be used for the
1026 /// specified value type.
1027 const TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const {
1028 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
1029 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
1030 // load / store 4 to 8 consecutive D registers.
1031 if (Subtarget->hasNEON()) {
1032 if (VT == MVT::v4i64)
1033 return &ARM::QQPRRegClass;
1034 if (VT == MVT::v8i64)
1035 return &ARM::QQQQPRRegClass;
1037 return TargetLowering::getRegClassFor(VT);
1040 // Create a fast isel object.
1042 ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
1043 const TargetLibraryInfo *libInfo) const {
1044 return ARM::createFastISel(funcInfo, libInfo);
1047 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
1048 /// be used for loads / stores from the global.
1049 unsigned ARMTargetLowering::getMaximalGlobalOffset() const {
1050 return (Subtarget->isThumb1Only() ? 127 : 4095);
1053 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
1054 unsigned NumVals = N->getNumValues();
1056 return Sched::RegPressure;
1058 for (unsigned i = 0; i != NumVals; ++i) {
1059 EVT VT = N->getValueType(i);
1060 if (VT == MVT::Glue || VT == MVT::Other)
1062 if (VT.isFloatingPoint() || VT.isVector())
1066 if (!N->isMachineOpcode())
1067 return Sched::RegPressure;
1069 // Load are scheduled for latency even if there instruction itinerary
1070 // is not available.
1071 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1072 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1074 if (MCID.getNumDefs() == 0)
1075 return Sched::RegPressure;
1076 if (!Itins->isEmpty() &&
1077 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
1080 return Sched::RegPressure;
1083 //===----------------------------------------------------------------------===//
1085 //===----------------------------------------------------------------------===//
1087 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
1088 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
1090 default: llvm_unreachable("Unknown condition code!");
1091 case ISD::SETNE: return ARMCC::NE;
1092 case ISD::SETEQ: return ARMCC::EQ;
1093 case ISD::SETGT: return ARMCC::GT;
1094 case ISD::SETGE: return ARMCC::GE;
1095 case ISD::SETLT: return ARMCC::LT;
1096 case ISD::SETLE: return ARMCC::LE;
1097 case ISD::SETUGT: return ARMCC::HI;
1098 case ISD::SETUGE: return ARMCC::HS;
1099 case ISD::SETULT: return ARMCC::LO;
1100 case ISD::SETULE: return ARMCC::LS;
1104 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
1105 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
1106 ARMCC::CondCodes &CondCode2) {
1107 CondCode2 = ARMCC::AL;
1109 default: llvm_unreachable("Unknown FP condition!");
1111 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
1113 case ISD::SETOGT: CondCode = ARMCC::GT; break;
1115 case ISD::SETOGE: CondCode = ARMCC::GE; break;
1116 case ISD::SETOLT: CondCode = ARMCC::MI; break;
1117 case ISD::SETOLE: CondCode = ARMCC::LS; break;
1118 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
1119 case ISD::SETO: CondCode = ARMCC::VC; break;
1120 case ISD::SETUO: CondCode = ARMCC::VS; break;
1121 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
1122 case ISD::SETUGT: CondCode = ARMCC::HI; break;
1123 case ISD::SETUGE: CondCode = ARMCC::PL; break;
1125 case ISD::SETULT: CondCode = ARMCC::LT; break;
1127 case ISD::SETULE: CondCode = ARMCC::LE; break;
1129 case ISD::SETUNE: CondCode = ARMCC::NE; break;
1133 //===----------------------------------------------------------------------===//
1134 // Calling Convention Implementation
1135 //===----------------------------------------------------------------------===//
1137 #include "ARMGenCallingConv.inc"
1139 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1140 /// given CallingConvention value.
1141 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
1143 bool isVarArg) const {
1146 llvm_unreachable("Unsupported calling convention");
1147 case CallingConv::Fast:
1148 if (Subtarget->hasVFP2() && !isVarArg) {
1149 if (!Subtarget->isAAPCS_ABI())
1150 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1151 // For AAPCS ABI targets, just use VFP variant of the calling convention.
1152 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1155 case CallingConv::C: {
1156 // Use target triple & subtarget features to do actual dispatch.
1157 if (!Subtarget->isAAPCS_ABI())
1158 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1159 else if (Subtarget->hasVFP2() &&
1160 getTargetMachine().Options.FloatABIType == FloatABI::Hard &&
1162 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1163 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1165 case CallingConv::ARM_AAPCS_VFP:
1167 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1169 case CallingConv::ARM_AAPCS:
1170 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1171 case CallingConv::ARM_APCS:
1172 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1173 case CallingConv::GHC:
1174 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC);
1178 /// LowerCallResult - Lower the result values of a call into the
1179 /// appropriate copies out of appropriate physical registers.
1181 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1182 CallingConv::ID CallConv, bool isVarArg,
1183 const SmallVectorImpl<ISD::InputArg> &Ins,
1184 DebugLoc dl, SelectionDAG &DAG,
1185 SmallVectorImpl<SDValue> &InVals) const {
1187 // Assign locations to each value returned by this call.
1188 SmallVector<CCValAssign, 16> RVLocs;
1189 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1190 getTargetMachine(), RVLocs, *DAG.getContext(), Call);
1191 CCInfo.AnalyzeCallResult(Ins,
1192 CCAssignFnForNode(CallConv, /* Return*/ true,
1195 // Copy all of the result registers out of their specified physreg.
1196 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1197 CCValAssign VA = RVLocs[i];
1200 if (VA.needsCustom()) {
1201 // Handle f64 or half of a v2f64.
1202 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1204 Chain = Lo.getValue(1);
1205 InFlag = Lo.getValue(2);
1206 VA = RVLocs[++i]; // skip ahead to next loc
1207 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1209 Chain = Hi.getValue(1);
1210 InFlag = Hi.getValue(2);
1211 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1213 if (VA.getLocVT() == MVT::v2f64) {
1214 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1215 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1216 DAG.getConstant(0, MVT::i32));
1218 VA = RVLocs[++i]; // skip ahead to next loc
1219 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1220 Chain = Lo.getValue(1);
1221 InFlag = Lo.getValue(2);
1222 VA = RVLocs[++i]; // skip ahead to next loc
1223 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1224 Chain = Hi.getValue(1);
1225 InFlag = Hi.getValue(2);
1226 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1227 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1228 DAG.getConstant(1, MVT::i32));
1231 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1233 Chain = Val.getValue(1);
1234 InFlag = Val.getValue(2);
1237 switch (VA.getLocInfo()) {
1238 default: llvm_unreachable("Unknown loc info!");
1239 case CCValAssign::Full: break;
1240 case CCValAssign::BCvt:
1241 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1245 InVals.push_back(Val);
1251 /// LowerMemOpCallTo - Store the argument to the stack.
1253 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
1254 SDValue StackPtr, SDValue Arg,
1255 DebugLoc dl, SelectionDAG &DAG,
1256 const CCValAssign &VA,
1257 ISD::ArgFlagsTy Flags) const {
1258 unsigned LocMemOffset = VA.getLocMemOffset();
1259 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1260 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1261 return DAG.getStore(Chain, dl, Arg, PtrOff,
1262 MachinePointerInfo::getStack(LocMemOffset),
1266 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
1267 SDValue Chain, SDValue &Arg,
1268 RegsToPassVector &RegsToPass,
1269 CCValAssign &VA, CCValAssign &NextVA,
1271 SmallVector<SDValue, 8> &MemOpChains,
1272 ISD::ArgFlagsTy Flags) const {
1274 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1275 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1276 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
1278 if (NextVA.isRegLoc())
1279 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
1281 assert(NextVA.isMemLoc());
1282 if (StackPtr.getNode() == 0)
1283 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1285 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
1291 /// LowerCall - Lowering a call into a callseq_start <-
1292 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1295 ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1296 SmallVectorImpl<SDValue> &InVals) const {
1297 SelectionDAG &DAG = CLI.DAG;
1298 DebugLoc &dl = CLI.DL;
1299 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
1300 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
1301 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
1302 SDValue Chain = CLI.Chain;
1303 SDValue Callee = CLI.Callee;
1304 bool &isTailCall = CLI.IsTailCall;
1305 CallingConv::ID CallConv = CLI.CallConv;
1306 bool doesNotRet = CLI.DoesNotReturn;
1307 bool isVarArg = CLI.IsVarArg;
1309 MachineFunction &MF = DAG.getMachineFunction();
1310 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1311 bool IsSibCall = false;
1312 // Disable tail calls if they're not supported.
1313 if (!EnableARMTailCalls && !Subtarget->supportsTailCall())
1316 // Check if it's really possible to do a tail call.
1317 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1318 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1319 Outs, OutVals, Ins, DAG);
1320 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1321 // detected sibcalls.
1328 // Analyze operands of the call, assigning locations to each operand.
1329 SmallVector<CCValAssign, 16> ArgLocs;
1330 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1331 getTargetMachine(), ArgLocs, *DAG.getContext(), Call);
1332 CCInfo.AnalyzeCallOperands(Outs,
1333 CCAssignFnForNode(CallConv, /* Return*/ false,
1336 // Get a count of how many bytes are to be pushed on the stack.
1337 unsigned NumBytes = CCInfo.getNextStackOffset();
1339 // For tail calls, memory operands are available in our caller's stack.
1343 // Adjust the stack pointer for the new arguments...
1344 // These operations are automatically eliminated by the prolog/epilog pass
1346 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1348 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1350 RegsToPassVector RegsToPass;
1351 SmallVector<SDValue, 8> MemOpChains;
1353 // Walk the register/memloc assignments, inserting copies/loads. In the case
1354 // of tail call optimization, arguments are handled later.
1355 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1357 ++i, ++realArgIdx) {
1358 CCValAssign &VA = ArgLocs[i];
1359 SDValue Arg = OutVals[realArgIdx];
1360 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1361 bool isByVal = Flags.isByVal();
1363 // Promote the value if needed.
1364 switch (VA.getLocInfo()) {
1365 default: llvm_unreachable("Unknown loc info!");
1366 case CCValAssign::Full: break;
1367 case CCValAssign::SExt:
1368 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1370 case CCValAssign::ZExt:
1371 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1373 case CCValAssign::AExt:
1374 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1376 case CCValAssign::BCvt:
1377 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1381 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1382 if (VA.needsCustom()) {
1383 if (VA.getLocVT() == MVT::v2f64) {
1384 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1385 DAG.getConstant(0, MVT::i32));
1386 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1387 DAG.getConstant(1, MVT::i32));
1389 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1390 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1392 VA = ArgLocs[++i]; // skip ahead to next loc
1393 if (VA.isRegLoc()) {
1394 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1395 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1397 assert(VA.isMemLoc());
1399 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1400 dl, DAG, VA, Flags));
1403 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1404 StackPtr, MemOpChains, Flags);
1406 } else if (VA.isRegLoc()) {
1407 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1408 } else if (isByVal) {
1409 assert(VA.isMemLoc());
1410 unsigned offset = 0;
1412 // True if this byval aggregate will be split between registers
1414 if (CCInfo.isFirstByValRegValid()) {
1415 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1417 for (i = 0, j = CCInfo.getFirstByValReg(); j < ARM::R4; i++, j++) {
1418 SDValue Const = DAG.getConstant(4*i, MVT::i32);
1419 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
1420 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
1421 MachinePointerInfo(),
1422 false, false, false, 0);
1423 MemOpChains.push_back(Load.getValue(1));
1424 RegsToPass.push_back(std::make_pair(j, Load));
1426 offset = ARM::R4 - CCInfo.getFirstByValReg();
1427 CCInfo.clearFirstByValReg();
1430 if (Flags.getByValSize() - 4*offset > 0) {
1431 unsigned LocMemOffset = VA.getLocMemOffset();
1432 SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset);
1433 SDValue Dst = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr,
1435 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset);
1436 SDValue Src = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg, SrcOffset);
1437 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset,
1439 SDValue AlignNode = DAG.getConstant(Flags.getByValAlign(), MVT::i32);
1441 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
1442 SDValue Ops[] = { Chain, Dst, Src, SizeNode, AlignNode};
1443 MemOpChains.push_back(DAG.getNode(ARMISD::COPY_STRUCT_BYVAL, dl, VTs,
1444 Ops, array_lengthof(Ops)));
1446 } else if (!IsSibCall) {
1447 assert(VA.isMemLoc());
1449 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1450 dl, DAG, VA, Flags));
1454 if (!MemOpChains.empty())
1455 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1456 &MemOpChains[0], MemOpChains.size());
1458 // Build a sequence of copy-to-reg nodes chained together with token chain
1459 // and flag operands which copy the outgoing args into the appropriate regs.
1461 // Tail call byval lowering might overwrite argument registers so in case of
1462 // tail call optimization the copies to registers are lowered later.
1464 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1465 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1466 RegsToPass[i].second, InFlag);
1467 InFlag = Chain.getValue(1);
1470 // For tail calls lower the arguments to the 'real' stack slot.
1472 // Force all the incoming stack arguments to be loaded from the stack
1473 // before any new outgoing arguments are stored to the stack, because the
1474 // outgoing stack slots may alias the incoming argument stack slots, and
1475 // the alias isn't otherwise explicit. This is slightly more conservative
1476 // than necessary, because it means that each store effectively depends
1477 // on every argument instead of just those arguments it would clobber.
1479 // Do not flag preceding copytoreg stuff together with the following stuff.
1481 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1482 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1483 RegsToPass[i].second, InFlag);
1484 InFlag = Chain.getValue(1);
1489 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1490 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1491 // node so that legalize doesn't hack it.
1492 bool isDirect = false;
1493 bool isARMFunc = false;
1494 bool isLocalARMFunc = false;
1495 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1497 if (EnableARMLongCalls) {
1498 assert (getTargetMachine().getRelocationModel() == Reloc::Static
1499 && "long-calls with non-static relocation model!");
1500 // Handle a global address or an external symbol. If it's not one of
1501 // those, the target's already in a register, so we don't need to do
1503 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1504 const GlobalValue *GV = G->getGlobal();
1505 // Create a constant pool entry for the callee address
1506 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1507 ARMConstantPoolValue *CPV =
1508 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0);
1510 // Get the address of the callee into a register
1511 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1512 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1513 Callee = DAG.getLoad(getPointerTy(), dl,
1514 DAG.getEntryNode(), CPAddr,
1515 MachinePointerInfo::getConstantPool(),
1516 false, false, false, 0);
1517 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1518 const char *Sym = S->getSymbol();
1520 // Create a constant pool entry for the callee address
1521 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1522 ARMConstantPoolValue *CPV =
1523 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
1524 ARMPCLabelIndex, 0);
1525 // Get the address of the callee into a register
1526 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1527 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1528 Callee = DAG.getLoad(getPointerTy(), dl,
1529 DAG.getEntryNode(), CPAddr,
1530 MachinePointerInfo::getConstantPool(),
1531 false, false, false, 0);
1533 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1534 const GlobalValue *GV = G->getGlobal();
1536 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1537 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
1538 getTargetMachine().getRelocationModel() != Reloc::Static;
1539 isARMFunc = !Subtarget->isThumb() || isStub;
1540 // ARM call to a local ARM function is predicable.
1541 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
1542 // tBX takes a register source operand.
1543 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1544 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1545 ARMConstantPoolValue *CPV =
1546 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 4);
1547 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1548 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1549 Callee = DAG.getLoad(getPointerTy(), dl,
1550 DAG.getEntryNode(), CPAddr,
1551 MachinePointerInfo::getConstantPool(),
1552 false, false, false, 0);
1553 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1554 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1555 getPointerTy(), Callee, PICLabel);
1557 // On ELF targets for PIC code, direct calls should go through the PLT
1558 unsigned OpFlags = 0;
1559 if (Subtarget->isTargetELF() &&
1560 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1561 OpFlags = ARMII::MO_PLT;
1562 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
1564 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1566 bool isStub = Subtarget->isTargetDarwin() &&
1567 getTargetMachine().getRelocationModel() != Reloc::Static;
1568 isARMFunc = !Subtarget->isThumb() || isStub;
1569 // tBX takes a register source operand.
1570 const char *Sym = S->getSymbol();
1571 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1572 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1573 ARMConstantPoolValue *CPV =
1574 ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
1575 ARMPCLabelIndex, 4);
1576 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1577 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1578 Callee = DAG.getLoad(getPointerTy(), dl,
1579 DAG.getEntryNode(), CPAddr,
1580 MachinePointerInfo::getConstantPool(),
1581 false, false, false, 0);
1582 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1583 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1584 getPointerTy(), Callee, PICLabel);
1586 unsigned OpFlags = 0;
1587 // On ELF targets for PIC code, direct calls should go through the PLT
1588 if (Subtarget->isTargetELF() &&
1589 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1590 OpFlags = ARMII::MO_PLT;
1591 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags);
1595 // FIXME: handle tail calls differently.
1597 if (Subtarget->isThumb()) {
1598 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1599 CallOpc = ARMISD::CALL_NOLINK;
1600 else if (doesNotRet && isDirect && !isARMFunc &&
1601 Subtarget->hasRAS() && !Subtarget->isThumb1Only())
1602 // "mov lr, pc; b _foo" to avoid confusing the RSP
1603 CallOpc = ARMISD::CALL_NOLINK;
1605 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1607 if (!isDirect && !Subtarget->hasV5TOps()) {
1608 CallOpc = ARMISD::CALL_NOLINK;
1609 } else if (doesNotRet && isDirect && Subtarget->hasRAS())
1610 // "mov lr, pc; b _foo" to avoid confusing the RSP
1611 CallOpc = ARMISD::CALL_NOLINK;
1613 CallOpc = isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL;
1616 std::vector<SDValue> Ops;
1617 Ops.push_back(Chain);
1618 Ops.push_back(Callee);
1620 // Add argument registers to the end of the list so that they are known live
1622 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1623 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1624 RegsToPass[i].second.getValueType()));
1626 // Add a register mask operand representing the call-preserved registers.
1627 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
1628 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
1629 assert(Mask && "Missing call preserved mask for calling convention");
1630 Ops.push_back(DAG.getRegisterMask(Mask));
1632 if (InFlag.getNode())
1633 Ops.push_back(InFlag);
1635 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1637 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
1639 // Returns a chain and a flag for retval copy to use.
1640 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
1641 InFlag = Chain.getValue(1);
1643 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1644 DAG.getIntPtrConstant(0, true), InFlag);
1646 InFlag = Chain.getValue(1);
1648 // Handle result values, copying them out of physregs into vregs that we
1650 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1654 /// HandleByVal - Every parameter *after* a byval parameter is passed
1655 /// on the stack. Remember the next parameter register to allocate,
1656 /// and then confiscate the rest of the parameter registers to insure
1659 ARMTargetLowering::HandleByVal(
1660 CCState *State, unsigned &size, unsigned Align) const {
1661 unsigned reg = State->AllocateReg(GPRArgRegs, 4);
1662 assert((State->getCallOrPrologue() == Prologue ||
1663 State->getCallOrPrologue() == Call) &&
1664 "unhandled ParmContext");
1665 if ((!State->isFirstByValRegValid()) &&
1666 (ARM::R0 <= reg) && (reg <= ARM::R3)) {
1667 if (Subtarget->isAAPCS_ABI() && Align > 4) {
1668 unsigned AlignInRegs = Align / 4;
1669 unsigned Waste = (ARM::R4 - reg) % AlignInRegs;
1670 for (unsigned i = 0; i < Waste; ++i)
1671 reg = State->AllocateReg(GPRArgRegs, 4);
1674 State->setFirstByValReg(reg);
1675 // At a call site, a byval parameter that is split between
1676 // registers and memory needs its size truncated here. In a
1677 // function prologue, such byval parameters are reassembled in
1678 // memory, and are not truncated.
1679 if (State->getCallOrPrologue() == Call) {
1680 unsigned excess = 4 * (ARM::R4 - reg);
1681 assert(size >= excess && "expected larger existing stack allocation");
1686 // Confiscate any remaining parameter registers to preclude their
1687 // assignment to subsequent parameters.
1688 while (State->AllocateReg(GPRArgRegs, 4))
1692 /// MatchingStackOffset - Return true if the given stack call argument is
1693 /// already available in the same position (relatively) of the caller's
1694 /// incoming argument stack.
1696 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1697 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1698 const TargetInstrInfo *TII) {
1699 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
1701 if (Arg.getOpcode() == ISD::CopyFromReg) {
1702 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
1703 if (!TargetRegisterInfo::isVirtualRegister(VR))
1705 MachineInstr *Def = MRI->getVRegDef(VR);
1708 if (!Flags.isByVal()) {
1709 if (!TII->isLoadFromStackSlot(Def, FI))
1714 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
1715 if (Flags.isByVal())
1716 // ByVal argument is passed in as a pointer but it's now being
1717 // dereferenced. e.g.
1718 // define @foo(%struct.X* %A) {
1719 // tail call @bar(%struct.X* byval %A)
1722 SDValue Ptr = Ld->getBasePtr();
1723 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
1726 FI = FINode->getIndex();
1730 assert(FI != INT_MAX);
1731 if (!MFI->isFixedObjectIndex(FI))
1733 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
1736 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1737 /// for tail call optimization. Targets which want to do tail call
1738 /// optimization should implement this function.
1740 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1741 CallingConv::ID CalleeCC,
1743 bool isCalleeStructRet,
1744 bool isCallerStructRet,
1745 const SmallVectorImpl<ISD::OutputArg> &Outs,
1746 const SmallVectorImpl<SDValue> &OutVals,
1747 const SmallVectorImpl<ISD::InputArg> &Ins,
1748 SelectionDAG& DAG) const {
1749 const Function *CallerF = DAG.getMachineFunction().getFunction();
1750 CallingConv::ID CallerCC = CallerF->getCallingConv();
1751 bool CCMatch = CallerCC == CalleeCC;
1753 // Look for obvious safe cases to perform tail call optimization that do not
1754 // require ABI changes. This is what gcc calls sibcall.
1756 // Do not sibcall optimize vararg calls unless the call site is not passing
1758 if (isVarArg && !Outs.empty())
1761 // Also avoid sibcall optimization if either caller or callee uses struct
1762 // return semantics.
1763 if (isCalleeStructRet || isCallerStructRet)
1766 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
1767 // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
1768 // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
1769 // support in the assembler and linker to be used. This would need to be
1770 // fixed to fully support tail calls in Thumb1.
1772 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
1773 // LR. This means if we need to reload LR, it takes an extra instructions,
1774 // which outweighs the value of the tail call; but here we don't know yet
1775 // whether LR is going to be used. Probably the right approach is to
1776 // generate the tail call here and turn it back into CALL/RET in
1777 // emitEpilogue if LR is used.
1779 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
1780 // but we need to make sure there are enough registers; the only valid
1781 // registers are the 4 used for parameters. We don't currently do this
1783 if (Subtarget->isThumb1Only())
1786 // If the calling conventions do not match, then we'd better make sure the
1787 // results are returned in the same way as what the caller expects.
1789 SmallVector<CCValAssign, 16> RVLocs1;
1790 ARMCCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
1791 getTargetMachine(), RVLocs1, *DAG.getContext(), Call);
1792 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
1794 SmallVector<CCValAssign, 16> RVLocs2;
1795 ARMCCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
1796 getTargetMachine(), RVLocs2, *DAG.getContext(), Call);
1797 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
1799 if (RVLocs1.size() != RVLocs2.size())
1801 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
1802 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
1804 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
1806 if (RVLocs1[i].isRegLoc()) {
1807 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
1810 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
1816 // If Caller's vararg or byval argument has been split between registers and
1817 // stack, do not perform tail call, since part of the argument is in caller's
1819 const ARMFunctionInfo *AFI_Caller = DAG.getMachineFunction().
1820 getInfo<ARMFunctionInfo>();
1821 if (AFI_Caller->getVarArgsRegSaveSize())
1824 // If the callee takes no arguments then go on to check the results of the
1826 if (!Outs.empty()) {
1827 // Check if stack adjustment is needed. For now, do not do this if any
1828 // argument is passed on the stack.
1829 SmallVector<CCValAssign, 16> ArgLocs;
1830 ARMCCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
1831 getTargetMachine(), ArgLocs, *DAG.getContext(), Call);
1832 CCInfo.AnalyzeCallOperands(Outs,
1833 CCAssignFnForNode(CalleeCC, false, isVarArg));
1834 if (CCInfo.getNextStackOffset()) {
1835 MachineFunction &MF = DAG.getMachineFunction();
1837 // Check if the arguments are already laid out in the right way as
1838 // the caller's fixed stack objects.
1839 MachineFrameInfo *MFI = MF.getFrameInfo();
1840 const MachineRegisterInfo *MRI = &MF.getRegInfo();
1841 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1842 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1844 ++i, ++realArgIdx) {
1845 CCValAssign &VA = ArgLocs[i];
1846 EVT RegVT = VA.getLocVT();
1847 SDValue Arg = OutVals[realArgIdx];
1848 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1849 if (VA.getLocInfo() == CCValAssign::Indirect)
1851 if (VA.needsCustom()) {
1852 // f64 and vector types are split into multiple registers or
1853 // register/stack-slot combinations. The types will not match
1854 // the registers; give up on memory f64 refs until we figure
1855 // out what to do about this.
1858 if (!ArgLocs[++i].isRegLoc())
1860 if (RegVT == MVT::v2f64) {
1861 if (!ArgLocs[++i].isRegLoc())
1863 if (!ArgLocs[++i].isRegLoc())
1866 } else if (!VA.isRegLoc()) {
1867 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
1879 ARMTargetLowering::LowerReturn(SDValue Chain,
1880 CallingConv::ID CallConv, bool isVarArg,
1881 const SmallVectorImpl<ISD::OutputArg> &Outs,
1882 const SmallVectorImpl<SDValue> &OutVals,
1883 DebugLoc dl, SelectionDAG &DAG) const {
1885 // CCValAssign - represent the assignment of the return value to a location.
1886 SmallVector<CCValAssign, 16> RVLocs;
1888 // CCState - Info about the registers and stack slots.
1889 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1890 getTargetMachine(), RVLocs, *DAG.getContext(), Call);
1892 // Analyze outgoing return values.
1893 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1896 // If this is the first return lowered for this function, add
1897 // the regs to the liveout set for the function.
1898 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1899 for (unsigned i = 0; i != RVLocs.size(); ++i)
1900 if (RVLocs[i].isRegLoc())
1901 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1906 // Copy the result values into the output registers.
1907 for (unsigned i = 0, realRVLocIdx = 0;
1909 ++i, ++realRVLocIdx) {
1910 CCValAssign &VA = RVLocs[i];
1911 assert(VA.isRegLoc() && "Can only return in registers!");
1913 SDValue Arg = OutVals[realRVLocIdx];
1915 switch (VA.getLocInfo()) {
1916 default: llvm_unreachable("Unknown loc info!");
1917 case CCValAssign::Full: break;
1918 case CCValAssign::BCvt:
1919 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1923 if (VA.needsCustom()) {
1924 if (VA.getLocVT() == MVT::v2f64) {
1925 // Extract the first half and return it in two registers.
1926 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1927 DAG.getConstant(0, MVT::i32));
1928 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
1929 DAG.getVTList(MVT::i32, MVT::i32), Half);
1931 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1932 Flag = Chain.getValue(1);
1933 VA = RVLocs[++i]; // skip ahead to next loc
1934 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1935 HalfGPRs.getValue(1), Flag);
1936 Flag = Chain.getValue(1);
1937 VA = RVLocs[++i]; // skip ahead to next loc
1939 // Extract the 2nd half and fall through to handle it as an f64 value.
1940 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1941 DAG.getConstant(1, MVT::i32));
1943 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1945 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1946 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1947 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1948 Flag = Chain.getValue(1);
1949 VA = RVLocs[++i]; // skip ahead to next loc
1950 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1953 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1955 // Guarantee that all emitted copies are
1956 // stuck together, avoiding something bad.
1957 Flag = Chain.getValue(1);
1962 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1964 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1969 bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
1970 if (N->getNumValues() != 1)
1972 if (!N->hasNUsesOfValue(1, 0))
1975 SDValue TCChain = Chain;
1976 SDNode *Copy = *N->use_begin();
1977 if (Copy->getOpcode() == ISD::CopyToReg) {
1978 // If the copy has a glue operand, we conservatively assume it isn't safe to
1979 // perform a tail call.
1980 if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
1982 TCChain = Copy->getOperand(0);
1983 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) {
1984 SDNode *VMov = Copy;
1985 // f64 returned in a pair of GPRs.
1986 SmallPtrSet<SDNode*, 2> Copies;
1987 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
1989 if (UI->getOpcode() != ISD::CopyToReg)
1993 if (Copies.size() > 2)
1996 for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
1998 SDValue UseChain = UI->getOperand(0);
1999 if (Copies.count(UseChain.getNode()))
2006 } else if (Copy->getOpcode() == ISD::BITCAST) {
2007 // f32 returned in a single GPR.
2008 if (!Copy->hasOneUse())
2010 Copy = *Copy->use_begin();
2011 if (Copy->getOpcode() != ISD::CopyToReg || !Copy->hasNUsesOfValue(1, 0))
2013 Chain = Copy->getOperand(0);
2018 bool HasRet = false;
2019 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2021 if (UI->getOpcode() != ARMISD::RET_FLAG)
2033 bool ARMTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2034 if (!EnableARMTailCalls && !Subtarget->supportsTailCall())
2037 if (!CI->isTailCall())
2040 return !Subtarget->isThumb1Only();
2043 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
2044 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
2045 // one of the above mentioned nodes. It has to be wrapped because otherwise
2046 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
2047 // be used to form addressing mode. These wrapped nodes will be selected
2049 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
2050 EVT PtrVT = Op.getValueType();
2051 // FIXME there is no actual debug info here
2052 DebugLoc dl = Op.getDebugLoc();
2053 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2055 if (CP->isMachineConstantPoolEntry())
2056 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
2057 CP->getAlignment());
2059 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
2060 CP->getAlignment());
2061 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
2064 unsigned ARMTargetLowering::getJumpTableEncoding() const {
2065 return MachineJumpTableInfo::EK_Inline;
2068 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
2069 SelectionDAG &DAG) const {
2070 MachineFunction &MF = DAG.getMachineFunction();
2071 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2072 unsigned ARMPCLabelIndex = 0;
2073 DebugLoc DL = Op.getDebugLoc();
2074 EVT PtrVT = getPointerTy();
2075 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
2076 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2078 if (RelocM == Reloc::Static) {
2079 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
2081 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2082 ARMPCLabelIndex = AFI->createPICLabelUId();
2083 ARMConstantPoolValue *CPV =
2084 ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex,
2085 ARMCP::CPBlockAddress, PCAdj);
2086 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2088 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
2089 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
2090 MachinePointerInfo::getConstantPool(),
2091 false, false, false, 0);
2092 if (RelocM == Reloc::Static)
2094 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2095 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
2098 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
2100 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
2101 SelectionDAG &DAG) const {
2102 DebugLoc dl = GA->getDebugLoc();
2103 EVT PtrVT = getPointerTy();
2104 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2105 MachineFunction &MF = DAG.getMachineFunction();
2106 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2107 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2108 ARMConstantPoolValue *CPV =
2109 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2110 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
2111 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2112 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
2113 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
2114 MachinePointerInfo::getConstantPool(),
2115 false, false, false, 0);
2116 SDValue Chain = Argument.getValue(1);
2118 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2119 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
2121 // call __tls_get_addr.
2124 Entry.Node = Argument;
2125 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
2126 Args.push_back(Entry);
2127 // FIXME: is there useful debug info available here?
2128 TargetLowering::CallLoweringInfo CLI(Chain,
2129 (Type *) Type::getInt32Ty(*DAG.getContext()),
2130 false, false, false, false,
2131 0, CallingConv::C, /*isTailCall=*/false,
2132 /*doesNotRet=*/false, /*isReturnValueUsed=*/true,
2133 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
2134 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2135 return CallResult.first;
2138 // Lower ISD::GlobalTLSAddress using the "initial exec" or
2139 // "local exec" model.
2141 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
2143 TLSModel::Model model) const {
2144 const GlobalValue *GV = GA->getGlobal();
2145 DebugLoc dl = GA->getDebugLoc();
2147 SDValue Chain = DAG.getEntryNode();
2148 EVT PtrVT = getPointerTy();
2149 // Get the Thread Pointer
2150 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2152 if (model == TLSModel::InitialExec) {
2153 MachineFunction &MF = DAG.getMachineFunction();
2154 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2155 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2156 // Initial exec model.
2157 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2158 ARMConstantPoolValue *CPV =
2159 ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2160 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF,
2162 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2163 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2164 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2165 MachinePointerInfo::getConstantPool(),
2166 false, false, false, 0);
2167 Chain = Offset.getValue(1);
2169 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2170 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
2172 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2173 MachinePointerInfo::getConstantPool(),
2174 false, false, false, 0);
2177 assert(model == TLSModel::LocalExec);
2178 ARMConstantPoolValue *CPV =
2179 ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF);
2180 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2181 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2182 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2183 MachinePointerInfo::getConstantPool(),
2184 false, false, false, 0);
2187 // The address of the thread local variable is the add of the thread
2188 // pointer with the offset of the variable.
2189 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
2193 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
2194 // TODO: implement the "local dynamic" model
2195 assert(Subtarget->isTargetELF() &&
2196 "TLS not implemented for non-ELF targets");
2197 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2199 TLSModel::Model model = getTargetMachine().getTLSModel(GA->getGlobal());
2202 case TLSModel::GeneralDynamic:
2203 case TLSModel::LocalDynamic:
2204 return LowerToTLSGeneralDynamicModel(GA, DAG);
2205 case TLSModel::InitialExec:
2206 case TLSModel::LocalExec:
2207 return LowerToTLSExecModels(GA, DAG, model);
2209 llvm_unreachable("bogus TLS model");
2212 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
2213 SelectionDAG &DAG) const {
2214 EVT PtrVT = getPointerTy();
2215 DebugLoc dl = Op.getDebugLoc();
2216 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2217 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2218 if (RelocM == Reloc::PIC_) {
2219 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
2220 ARMConstantPoolValue *CPV =
2221 ARMConstantPoolConstant::Create(GV,
2222 UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
2223 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2224 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2225 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
2227 MachinePointerInfo::getConstantPool(),
2228 false, false, false, 0);
2229 SDValue Chain = Result.getValue(1);
2230 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
2231 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
2233 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
2234 MachinePointerInfo::getGOT(),
2235 false, false, false, 0);
2239 // If we have T2 ops, we can materialize the address directly via movt/movw
2240 // pair. This is always cheaper.
2241 if (Subtarget->useMovt()) {
2243 // FIXME: Once remat is capable of dealing with instructions with register
2244 // operands, expand this into two nodes.
2245 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2246 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2248 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
2249 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2250 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2251 MachinePointerInfo::getConstantPool(),
2252 false, false, false, 0);
2256 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
2257 SelectionDAG &DAG) const {
2258 EVT PtrVT = getPointerTy();
2259 DebugLoc dl = Op.getDebugLoc();
2260 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2261 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2262 MachineFunction &MF = DAG.getMachineFunction();
2263 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2265 // FIXME: Enable this for static codegen when tool issues are fixed. Also
2266 // update ARMFastISel::ARMMaterializeGV.
2267 if (Subtarget->useMovt() && RelocM != Reloc::Static) {
2269 // FIXME: Once remat is capable of dealing with instructions with register
2270 // operands, expand this into two nodes.
2271 if (RelocM == Reloc::Static)
2272 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2273 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2275 unsigned Wrapper = (RelocM == Reloc::PIC_)
2276 ? ARMISD::WrapperPIC : ARMISD::WrapperDYN;
2277 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT,
2278 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2279 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
2280 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
2281 MachinePointerInfo::getGOT(),
2282 false, false, false, 0);
2286 unsigned ARMPCLabelIndex = 0;
2288 if (RelocM == Reloc::Static) {
2289 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
2291 ARMPCLabelIndex = AFI->createPICLabelUId();
2292 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8);
2293 ARMConstantPoolValue *CPV =
2294 ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue,
2296 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2298 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2300 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2301 MachinePointerInfo::getConstantPool(),
2302 false, false, false, 0);
2303 SDValue Chain = Result.getValue(1);
2305 if (RelocM == Reloc::PIC_) {
2306 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2307 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2310 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
2311 Result = DAG.getLoad(PtrVT, dl, Chain, Result, MachinePointerInfo::getGOT(),
2312 false, false, false, 0);
2317 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
2318 SelectionDAG &DAG) const {
2319 assert(Subtarget->isTargetELF() &&
2320 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
2321 MachineFunction &MF = DAG.getMachineFunction();
2322 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2323 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2324 EVT PtrVT = getPointerTy();
2325 DebugLoc dl = Op.getDebugLoc();
2326 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2327 ARMConstantPoolValue *CPV =
2328 ARMConstantPoolSymbol::Create(*DAG.getContext(), "_GLOBAL_OFFSET_TABLE_",
2329 ARMPCLabelIndex, PCAdj);
2330 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2331 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2332 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2333 MachinePointerInfo::getConstantPool(),
2334 false, false, false, 0);
2335 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2336 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2340 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
2341 DebugLoc dl = Op.getDebugLoc();
2342 SDValue Val = DAG.getConstant(0, MVT::i32);
2343 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl,
2344 DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
2345 Op.getOperand(1), Val);
2349 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
2350 DebugLoc dl = Op.getDebugLoc();
2351 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
2352 Op.getOperand(1), DAG.getConstant(0, MVT::i32));
2356 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
2357 const ARMSubtarget *Subtarget) const {
2358 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2359 DebugLoc dl = Op.getDebugLoc();
2361 default: return SDValue(); // Don't custom lower most intrinsics.
2362 case Intrinsic::arm_thread_pointer: {
2363 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2364 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2366 case Intrinsic::eh_sjlj_lsda: {
2367 MachineFunction &MF = DAG.getMachineFunction();
2368 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2369 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2370 EVT PtrVT = getPointerTy();
2371 DebugLoc dl = Op.getDebugLoc();
2372 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2374 unsigned PCAdj = (RelocM != Reloc::PIC_)
2375 ? 0 : (Subtarget->isThumb() ? 4 : 8);
2376 ARMConstantPoolValue *CPV =
2377 ARMConstantPoolConstant::Create(MF.getFunction(), ARMPCLabelIndex,
2378 ARMCP::CPLSDA, PCAdj);
2379 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2380 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2382 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2383 MachinePointerInfo::getConstantPool(),
2384 false, false, false, 0);
2386 if (RelocM == Reloc::PIC_) {
2387 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2388 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2392 case Intrinsic::arm_neon_vmulls:
2393 case Intrinsic::arm_neon_vmullu: {
2394 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
2395 ? ARMISD::VMULLs : ARMISD::VMULLu;
2396 return DAG.getNode(NewOpc, Op.getDebugLoc(), Op.getValueType(),
2397 Op.getOperand(1), Op.getOperand(2));
2402 static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG,
2403 const ARMSubtarget *Subtarget) {
2404 DebugLoc dl = Op.getDebugLoc();
2405 if (!Subtarget->hasDataBarrier()) {
2406 // Some ARMv6 cpus can support data barriers with an mcr instruction.
2407 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
2409 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&
2410 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!");
2411 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2412 DAG.getConstant(0, MVT::i32));
2415 SDValue Op5 = Op.getOperand(5);
2416 bool isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue() != 0;
2417 unsigned isLL = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
2418 unsigned isLS = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
2419 bool isOnlyStoreBarrier = (isLL == 0 && isLS == 0);
2421 ARM_MB::MemBOpt DMBOpt;
2422 if (isDeviceBarrier)
2423 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ST : ARM_MB::SY;
2425 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ISHST : ARM_MB::ISH;
2426 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
2427 DAG.getConstant(DMBOpt, MVT::i32));
2431 static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
2432 const ARMSubtarget *Subtarget) {
2433 // FIXME: handle "fence singlethread" more efficiently.
2434 DebugLoc dl = Op.getDebugLoc();
2435 if (!Subtarget->hasDataBarrier()) {
2436 // Some ARMv6 cpus can support data barriers with an mcr instruction.
2437 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
2439 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&
2440 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!");
2441 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2442 DAG.getConstant(0, MVT::i32));
2445 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
2446 DAG.getConstant(ARM_MB::ISH, MVT::i32));
2449 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
2450 const ARMSubtarget *Subtarget) {
2451 // ARM pre v5TE and Thumb1 does not have preload instructions.
2452 if (!(Subtarget->isThumb2() ||
2453 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
2454 // Just preserve the chain.
2455 return Op.getOperand(0);
2457 DebugLoc dl = Op.getDebugLoc();
2458 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
2460 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
2461 // ARMv7 with MP extension has PLDW.
2462 return Op.getOperand(0);
2464 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
2465 if (Subtarget->isThumb()) {
2467 isRead = ~isRead & 1;
2468 isData = ~isData & 1;
2471 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
2472 Op.getOperand(1), DAG.getConstant(isRead, MVT::i32),
2473 DAG.getConstant(isData, MVT::i32));
2476 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
2477 MachineFunction &MF = DAG.getMachineFunction();
2478 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
2480 // vastart just stores the address of the VarArgsFrameIndex slot into the
2481 // memory location argument.
2482 DebugLoc dl = Op.getDebugLoc();
2483 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2484 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2485 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2486 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2487 MachinePointerInfo(SV), false, false, 0);
2491 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
2492 SDValue &Root, SelectionDAG &DAG,
2493 DebugLoc dl) const {
2494 MachineFunction &MF = DAG.getMachineFunction();
2495 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2497 const TargetRegisterClass *RC;
2498 if (AFI->isThumb1OnlyFunction())
2499 RC = &ARM::tGPRRegClass;
2501 RC = &ARM::GPRRegClass;
2503 // Transform the arguments stored in physical registers into virtual ones.
2504 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2505 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2508 if (NextVA.isMemLoc()) {
2509 MachineFrameInfo *MFI = MF.getFrameInfo();
2510 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
2512 // Create load node to retrieve arguments from the stack.
2513 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2514 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
2515 MachinePointerInfo::getFixedStack(FI),
2516 false, false, false, 0);
2518 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2519 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2522 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
2526 ARMTargetLowering::computeRegArea(CCState &CCInfo, MachineFunction &MF,
2527 unsigned &VARegSize, unsigned &VARegSaveSize)
2530 if (CCInfo.isFirstByValRegValid())
2531 NumGPRs = ARM::R4 - CCInfo.getFirstByValReg();
2533 unsigned int firstUnalloced;
2534 firstUnalloced = CCInfo.getFirstUnallocated(GPRArgRegs,
2535 sizeof(GPRArgRegs) /
2536 sizeof(GPRArgRegs[0]));
2537 NumGPRs = (firstUnalloced <= 3) ? (4 - firstUnalloced) : 0;
2540 unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment();
2541 VARegSize = NumGPRs * 4;
2542 VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
2545 // The remaining GPRs hold either the beginning of variable-argument
2546 // data, or the beginning of an aggregate passed by value (usuall
2547 // byval). Either way, we allocate stack slots adjacent to the data
2548 // provided by our caller, and store the unallocated registers there.
2549 // If this is a variadic function, the va_list pointer will begin with
2550 // these values; otherwise, this reassembles a (byval) structure that
2551 // was split between registers and memory.
2553 ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
2554 DebugLoc dl, SDValue &Chain,
2555 const Value *OrigArg,
2556 unsigned OffsetFromOrigArg,
2558 bool ForceMutable) const {
2559 MachineFunction &MF = DAG.getMachineFunction();
2560 MachineFrameInfo *MFI = MF.getFrameInfo();
2561 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2562 unsigned firstRegToSaveIndex;
2563 if (CCInfo.isFirstByValRegValid())
2564 firstRegToSaveIndex = CCInfo.getFirstByValReg() - ARM::R0;
2566 firstRegToSaveIndex = CCInfo.getFirstUnallocated
2567 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
2570 unsigned VARegSize, VARegSaveSize;
2571 computeRegArea(CCInfo, MF, VARegSize, VARegSaveSize);
2572 if (VARegSaveSize) {
2573 // If this function is vararg, store any remaining integer argument regs
2574 // to their spots on the stack so that they may be loaded by deferencing
2575 // the result of va_next.
2576 AFI->setVarArgsRegSaveSize(VARegSaveSize);
2577 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(VARegSaveSize,
2578 ArgOffset + VARegSaveSize
2581 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(),
2584 SmallVector<SDValue, 4> MemOps;
2585 for (unsigned i = 0; firstRegToSaveIndex < 4; ++firstRegToSaveIndex, ++i) {
2586 const TargetRegisterClass *RC;
2587 if (AFI->isThumb1OnlyFunction())
2588 RC = &ARM::tGPRRegClass;
2590 RC = &ARM::GPRRegClass;
2592 unsigned VReg = MF.addLiveIn(GPRArgRegs[firstRegToSaveIndex], RC);
2593 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2595 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2596 MachinePointerInfo(OrigArg, OffsetFromOrigArg + 4*i),
2598 MemOps.push_back(Store);
2599 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
2600 DAG.getConstant(4, getPointerTy()));
2602 if (!MemOps.empty())
2603 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2604 &MemOps[0], MemOps.size());
2606 // This will point to the next argument passed via stack.
2607 AFI->setVarArgsFrameIndex(
2608 MFI->CreateFixedObject(4, ArgOffset, !ForceMutable));
2612 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
2613 CallingConv::ID CallConv, bool isVarArg,
2614 const SmallVectorImpl<ISD::InputArg>
2616 DebugLoc dl, SelectionDAG &DAG,
2617 SmallVectorImpl<SDValue> &InVals)
2619 MachineFunction &MF = DAG.getMachineFunction();
2620 MachineFrameInfo *MFI = MF.getFrameInfo();
2622 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2624 // Assign locations to all of the incoming arguments.
2625 SmallVector<CCValAssign, 16> ArgLocs;
2626 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2627 getTargetMachine(), ArgLocs, *DAG.getContext(), Prologue);
2628 CCInfo.AnalyzeFormalArguments(Ins,
2629 CCAssignFnForNode(CallConv, /* Return*/ false,
2632 SmallVector<SDValue, 16> ArgValues;
2633 int lastInsIndex = -1;
2635 Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin();
2636 unsigned CurArgIdx = 0;
2637 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2638 CCValAssign &VA = ArgLocs[i];
2639 std::advance(CurOrigArg, Ins[VA.getValNo()].OrigArgIndex - CurArgIdx);
2640 CurArgIdx = Ins[VA.getValNo()].OrigArgIndex;
2641 // Arguments stored in registers.
2642 if (VA.isRegLoc()) {
2643 EVT RegVT = VA.getLocVT();
2645 if (VA.needsCustom()) {
2646 // f64 and vector types are split up into multiple registers or
2647 // combinations of registers and stack slots.
2648 if (VA.getLocVT() == MVT::v2f64) {
2649 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
2651 VA = ArgLocs[++i]; // skip ahead to next loc
2653 if (VA.isMemLoc()) {
2654 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
2655 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2656 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
2657 MachinePointerInfo::getFixedStack(FI),
2658 false, false, false, 0);
2660 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
2663 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2664 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2665 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
2666 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2667 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
2669 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
2672 const TargetRegisterClass *RC;
2674 if (RegVT == MVT::f32)
2675 RC = &ARM::SPRRegClass;
2676 else if (RegVT == MVT::f64)
2677 RC = &ARM::DPRRegClass;
2678 else if (RegVT == MVT::v2f64)
2679 RC = &ARM::QPRRegClass;
2680 else if (RegVT == MVT::i32)
2681 RC = AFI->isThumb1OnlyFunction() ?
2682 (const TargetRegisterClass*)&ARM::tGPRRegClass :
2683 (const TargetRegisterClass*)&ARM::GPRRegClass;
2685 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2687 // Transform the arguments in physical registers into virtual ones.
2688 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2689 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2692 // If this is an 8 or 16-bit value, it is really passed promoted
2693 // to 32 bits. Insert an assert[sz]ext to capture this, then
2694 // truncate to the right size.
2695 switch (VA.getLocInfo()) {
2696 default: llvm_unreachable("Unknown loc info!");
2697 case CCValAssign::Full: break;
2698 case CCValAssign::BCvt:
2699 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2701 case CCValAssign::SExt:
2702 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2703 DAG.getValueType(VA.getValVT()));
2704 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2706 case CCValAssign::ZExt:
2707 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2708 DAG.getValueType(VA.getValVT()));
2709 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2713 InVals.push_back(ArgValue);
2715 } else { // VA.isRegLoc()
2718 assert(VA.isMemLoc());
2719 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
2721 int index = ArgLocs[i].getValNo();
2723 // Some Ins[] entries become multiple ArgLoc[] entries.
2724 // Process them only once.
2725 if (index != lastInsIndex)
2727 ISD::ArgFlagsTy Flags = Ins[index].Flags;
2728 // FIXME: For now, all byval parameter objects are marked mutable.
2729 // This can be changed with more analysis.
2730 // In case of tail call optimization mark all arguments mutable.
2731 // Since they could be overwritten by lowering of arguments in case of
2733 if (Flags.isByVal()) {
2734 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2735 if (!AFI->getVarArgsFrameIndex()) {
2736 VarArgStyleRegisters(CCInfo, DAG,
2737 dl, Chain, CurOrigArg,
2738 Ins[VA.getValNo()].PartOffset,
2739 VA.getLocMemOffset(),
2740 true /*force mutable frames*/);
2741 int VAFrameIndex = AFI->getVarArgsFrameIndex();
2742 InVals.push_back(DAG.getFrameIndex(VAFrameIndex, getPointerTy()));
2744 int FI = MFI->CreateFixedObject(Flags.getByValSize(),
2745 VA.getLocMemOffset(), false);
2746 InVals.push_back(DAG.getFrameIndex(FI, getPointerTy()));
2749 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
2750 VA.getLocMemOffset(), true);
2752 // Create load nodes to retrieve arguments from the stack.
2753 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2754 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2755 MachinePointerInfo::getFixedStack(FI),
2756 false, false, false, 0));
2758 lastInsIndex = index;
2765 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, 0, 0,
2766 CCInfo.getNextStackOffset());
2771 /// isFloatingPointZero - Return true if this is +0.0.
2772 static bool isFloatingPointZero(SDValue Op) {
2773 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
2774 return CFP->getValueAPF().isPosZero();
2775 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
2776 // Maybe this has already been legalized into the constant pool?
2777 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
2778 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
2779 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
2780 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
2781 return CFP->getValueAPF().isPosZero();
2787 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
2788 /// the given operands.
2790 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2791 SDValue &ARMcc, SelectionDAG &DAG,
2792 DebugLoc dl) const {
2793 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
2794 unsigned C = RHSC->getZExtValue();
2795 if (!isLegalICmpImmediate(C)) {
2796 // Constant does not fit, try adjusting it by one?
2801 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
2802 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
2803 RHS = DAG.getConstant(C-1, MVT::i32);
2808 if (C != 0 && isLegalICmpImmediate(C-1)) {
2809 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
2810 RHS = DAG.getConstant(C-1, MVT::i32);
2815 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
2816 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
2817 RHS = DAG.getConstant(C+1, MVT::i32);
2822 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
2823 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2824 RHS = DAG.getConstant(C+1, MVT::i32);
2831 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2832 ARMISD::NodeType CompareType;
2835 CompareType = ARMISD::CMP;
2840 CompareType = ARMISD::CMPZ;
2843 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2844 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
2847 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
2849 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
2850 DebugLoc dl) const {
2852 if (!isFloatingPointZero(RHS))
2853 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS);
2855 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS);
2856 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
2859 /// duplicateCmp - Glue values can have only one use, so this function
2860 /// duplicates a comparison node.
2862 ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
2863 unsigned Opc = Cmp.getOpcode();
2864 DebugLoc DL = Cmp.getDebugLoc();
2865 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
2866 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
2868 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation");
2869 Cmp = Cmp.getOperand(0);
2870 Opc = Cmp.getOpcode();
2871 if (Opc == ARMISD::CMPFP)
2872 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
2874 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT");
2875 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0));
2877 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
2880 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2881 SDValue Cond = Op.getOperand(0);
2882 SDValue SelectTrue = Op.getOperand(1);
2883 SDValue SelectFalse = Op.getOperand(2);
2884 DebugLoc dl = Op.getDebugLoc();
2888 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
2889 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
2891 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
2892 const ConstantSDNode *CMOVTrue =
2893 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
2894 const ConstantSDNode *CMOVFalse =
2895 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
2897 if (CMOVTrue && CMOVFalse) {
2898 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
2899 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
2903 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
2905 False = SelectFalse;
2906 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
2911 if (True.getNode() && False.getNode()) {
2912 EVT VT = Op.getValueType();
2913 SDValue ARMcc = Cond.getOperand(2);
2914 SDValue CCR = Cond.getOperand(3);
2915 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
2916 assert(True.getValueType() == VT);
2917 return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp);
2922 // ARM's BooleanContents value is UndefinedBooleanContent. Mask out the
2923 // undefined bits before doing a full-word comparison with zero.
2924 Cond = DAG.getNode(ISD::AND, dl, Cond.getValueType(), Cond,
2925 DAG.getConstant(1, Cond.getValueType()));
2927 return DAG.getSelectCC(dl, Cond,
2928 DAG.getConstant(0, Cond.getValueType()),
2929 SelectTrue, SelectFalse, ISD::SETNE);
2932 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
2933 EVT VT = Op.getValueType();
2934 SDValue LHS = Op.getOperand(0);
2935 SDValue RHS = Op.getOperand(1);
2936 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2937 SDValue TrueVal = Op.getOperand(2);
2938 SDValue FalseVal = Op.getOperand(3);
2939 DebugLoc dl = Op.getDebugLoc();
2941 if (LHS.getValueType() == MVT::i32) {
2943 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2944 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2945 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,Cmp);
2948 ARMCC::CondCodes CondCode, CondCode2;
2949 FPCCToARMCC(CC, CondCode, CondCode2);
2951 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2952 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2953 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2954 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
2956 if (CondCode2 != ARMCC::AL) {
2957 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32);
2958 // FIXME: Needs another CMP because flag can have but one use.
2959 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
2960 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
2961 Result, TrueVal, ARMcc2, CCR, Cmp2);
2966 /// canChangeToInt - Given the fp compare operand, return true if it is suitable
2967 /// to morph to an integer compare sequence.
2968 static bool canChangeToInt(SDValue Op, bool &SeenZero,
2969 const ARMSubtarget *Subtarget) {
2970 SDNode *N = Op.getNode();
2971 if (!N->hasOneUse())
2972 // Otherwise it requires moving the value from fp to integer registers.
2974 if (!N->getNumValues())
2976 EVT VT = Op.getValueType();
2977 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
2978 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
2979 // vmrs are very slow, e.g. cortex-a8.
2982 if (isFloatingPointZero(Op)) {
2986 return ISD::isNormalLoad(N);
2989 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
2990 if (isFloatingPointZero(Op))
2991 return DAG.getConstant(0, MVT::i32);
2993 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
2994 return DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2995 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(),
2996 Ld->isVolatile(), Ld->isNonTemporal(),
2997 Ld->isInvariant(), Ld->getAlignment());
2999 llvm_unreachable("Unknown VFP cmp argument!");
3002 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
3003 SDValue &RetVal1, SDValue &RetVal2) {
3004 if (isFloatingPointZero(Op)) {
3005 RetVal1 = DAG.getConstant(0, MVT::i32);
3006 RetVal2 = DAG.getConstant(0, MVT::i32);
3010 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
3011 SDValue Ptr = Ld->getBasePtr();
3012 RetVal1 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
3013 Ld->getChain(), Ptr,
3014 Ld->getPointerInfo(),
3015 Ld->isVolatile(), Ld->isNonTemporal(),
3016 Ld->isInvariant(), Ld->getAlignment());
3018 EVT PtrType = Ptr.getValueType();
3019 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
3020 SDValue NewPtr = DAG.getNode(ISD::ADD, Op.getDebugLoc(),
3021 PtrType, Ptr, DAG.getConstant(4, PtrType));
3022 RetVal2 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
3023 Ld->getChain(), NewPtr,
3024 Ld->getPointerInfo().getWithOffset(4),
3025 Ld->isVolatile(), Ld->isNonTemporal(),
3026 Ld->isInvariant(), NewAlign);
3030 llvm_unreachable("Unknown VFP cmp argument!");
3033 /// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
3034 /// f32 and even f64 comparisons to integer ones.
3036 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
3037 SDValue Chain = Op.getOperand(0);
3038 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3039 SDValue LHS = Op.getOperand(2);
3040 SDValue RHS = Op.getOperand(3);
3041 SDValue Dest = Op.getOperand(4);
3042 DebugLoc dl = Op.getDebugLoc();
3044 bool LHSSeenZero = false;
3045 bool LHSOk = canChangeToInt(LHS, LHSSeenZero, Subtarget);
3046 bool RHSSeenZero = false;
3047 bool RHSOk = canChangeToInt(RHS, RHSSeenZero, Subtarget);
3048 if (LHSOk && RHSOk && (LHSSeenZero || RHSSeenZero)) {
3049 // If unsafe fp math optimization is enabled and there are no other uses of
3050 // the CMP operands, and the condition code is EQ or NE, we can optimize it
3051 // to an integer comparison.
3052 if (CC == ISD::SETOEQ)
3054 else if (CC == ISD::SETUNE)
3057 SDValue Mask = DAG.getConstant(0x7fffffff, MVT::i32);
3059 if (LHS.getValueType() == MVT::f32) {
3060 LHS = DAG.getNode(ISD::AND, dl, MVT::i32,
3061 bitcastf32Toi32(LHS, DAG), Mask);
3062 RHS = DAG.getNode(ISD::AND, dl, MVT::i32,
3063 bitcastf32Toi32(RHS, DAG), Mask);
3064 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3065 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3066 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
3067 Chain, Dest, ARMcc, CCR, Cmp);
3072 expandf64Toi32(LHS, DAG, LHS1, LHS2);
3073 expandf64Toi32(RHS, DAG, RHS1, RHS2);
3074 LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask);
3075 RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask);
3076 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3077 ARMcc = DAG.getConstant(CondCode, MVT::i32);
3078 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
3079 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
3080 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7);
3086 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
3087 SDValue Chain = Op.getOperand(0);
3088 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3089 SDValue LHS = Op.getOperand(2);
3090 SDValue RHS = Op.getOperand(3);
3091 SDValue Dest = Op.getOperand(4);
3092 DebugLoc dl = Op.getDebugLoc();
3094 if (LHS.getValueType() == MVT::i32) {
3096 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3097 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3098 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
3099 Chain, Dest, ARMcc, CCR, Cmp);
3102 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3104 if (getTargetMachine().Options.UnsafeFPMath &&
3105 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
3106 CC == ISD::SETNE || CC == ISD::SETUNE)) {
3107 SDValue Result = OptimizeVFPBrcond(Op, DAG);
3108 if (Result.getNode())
3112 ARMCC::CondCodes CondCode, CondCode2;
3113 FPCCToARMCC(CC, CondCode, CondCode2);
3115 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
3116 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
3117 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3118 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
3119 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
3120 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
3121 if (CondCode2 != ARMCC::AL) {
3122 ARMcc = DAG.getConstant(CondCode2, MVT::i32);
3123 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
3124 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
3129 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
3130 SDValue Chain = Op.getOperand(0);
3131 SDValue Table = Op.getOperand(1);
3132 SDValue Index = Op.getOperand(2);
3133 DebugLoc dl = Op.getDebugLoc();
3135 EVT PTy = getPointerTy();
3136 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
3137 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
3138 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
3139 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
3140 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
3141 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
3142 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
3143 if (Subtarget->isThumb2()) {
3144 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
3145 // which does another jump to the destination. This also makes it easier
3146 // to translate it to TBB / TBH later.
3147 // FIXME: This might not work if the function is extremely large.
3148 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
3149 Addr, Op.getOperand(2), JTI, UId);
3151 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
3152 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
3153 MachinePointerInfo::getJumpTable(),
3154 false, false, false, 0);
3155 Chain = Addr.getValue(1);
3156 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
3157 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
3159 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
3160 MachinePointerInfo::getJumpTable(),
3161 false, false, false, 0);
3162 Chain = Addr.getValue(1);
3163 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
3167 static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
3168 EVT VT = Op.getValueType();
3169 DebugLoc dl = Op.getDebugLoc();
3171 if (Op.getValueType().getVectorElementType() == MVT::i32) {
3172 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32)
3174 return DAG.UnrollVectorOp(Op.getNode());
3177 assert(Op.getOperand(0).getValueType() == MVT::v4f32 &&
3178 "Invalid type for custom lowering!");
3179 if (VT != MVT::v4i16)
3180 return DAG.UnrollVectorOp(Op.getNode());
3182 Op = DAG.getNode(Op.getOpcode(), dl, MVT::v4i32, Op.getOperand(0));
3183 return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
3186 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
3187 EVT VT = Op.getValueType();
3189 return LowerVectorFP_TO_INT(Op, DAG);
3191 DebugLoc dl = Op.getDebugLoc();
3194 switch (Op.getOpcode()) {
3195 default: llvm_unreachable("Invalid opcode!");
3196 case ISD::FP_TO_SINT:
3197 Opc = ARMISD::FTOSI;
3199 case ISD::FP_TO_UINT:
3200 Opc = ARMISD::FTOUI;
3203 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
3204 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3207 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
3208 EVT VT = Op.getValueType();
3209 DebugLoc dl = Op.getDebugLoc();
3211 if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) {
3212 if (VT.getVectorElementType() == MVT::f32)
3214 return DAG.UnrollVectorOp(Op.getNode());
3217 assert(Op.getOperand(0).getValueType() == MVT::v4i16 &&
3218 "Invalid type for custom lowering!");
3219 if (VT != MVT::v4f32)
3220 return DAG.UnrollVectorOp(Op.getNode());
3224 switch (Op.getOpcode()) {
3225 default: llvm_unreachable("Invalid opcode!");
3226 case ISD::SINT_TO_FP:
3227 CastOpc = ISD::SIGN_EXTEND;
3228 Opc = ISD::SINT_TO_FP;
3230 case ISD::UINT_TO_FP:
3231 CastOpc = ISD::ZERO_EXTEND;
3232 Opc = ISD::UINT_TO_FP;
3236 Op = DAG.getNode(CastOpc, dl, MVT::v4i32, Op.getOperand(0));
3237 return DAG.getNode(Opc, dl, VT, Op);
3240 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
3241 EVT VT = Op.getValueType();
3243 return LowerVectorINT_TO_FP(Op, DAG);
3245 DebugLoc dl = Op.getDebugLoc();
3248 switch (Op.getOpcode()) {
3249 default: llvm_unreachable("Invalid opcode!");
3250 case ISD::SINT_TO_FP:
3251 Opc = ARMISD::SITOF;
3253 case ISD::UINT_TO_FP:
3254 Opc = ARMISD::UITOF;
3258 Op = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0));
3259 return DAG.getNode(Opc, dl, VT, Op);
3262 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
3263 // Implement fcopysign with a fabs and a conditional fneg.
3264 SDValue Tmp0 = Op.getOperand(0);
3265 SDValue Tmp1 = Op.getOperand(1);
3266 DebugLoc dl = Op.getDebugLoc();
3267 EVT VT = Op.getValueType();
3268 EVT SrcVT = Tmp1.getValueType();
3269 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
3270 Tmp0.getOpcode() == ARMISD::VMOVDRR;
3271 bool UseNEON = !InGPR && Subtarget->hasNEON();
3274 // Use VBSL to copy the sign bit.
3275 unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80);
3276 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
3277 DAG.getTargetConstant(EncodedVal, MVT::i32));
3278 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
3280 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT,
3281 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
3282 DAG.getConstant(32, MVT::i32));
3283 else /*if (VT == MVT::f32)*/
3284 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
3285 if (SrcVT == MVT::f32) {
3286 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
3288 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT,
3289 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
3290 DAG.getConstant(32, MVT::i32));
3291 } else if (VT == MVT::f32)
3292 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64,
3293 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
3294 DAG.getConstant(32, MVT::i32));
3295 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
3296 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
3298 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff),
3300 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
3301 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
3302 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
3304 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
3305 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
3306 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
3307 if (VT == MVT::f32) {
3308 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
3309 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
3310 DAG.getConstant(0, MVT::i32));
3312 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
3318 // Bitcast operand 1 to i32.
3319 if (SrcVT == MVT::f64)
3320 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
3321 &Tmp1, 1).getValue(1);
3322 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
3324 // Or in the signbit with integer operations.
3325 SDValue Mask1 = DAG.getConstant(0x80000000, MVT::i32);
3326 SDValue Mask2 = DAG.getConstant(0x7fffffff, MVT::i32);
3327 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
3328 if (VT == MVT::f32) {
3329 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
3330 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
3331 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3332 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
3335 // f64: Or the high part with signbit and then combine two parts.
3336 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
3338 SDValue Lo = Tmp0.getValue(0);
3339 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
3340 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
3341 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
3344 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
3345 MachineFunction &MF = DAG.getMachineFunction();
3346 MachineFrameInfo *MFI = MF.getFrameInfo();
3347 MFI->setReturnAddressIsTaken(true);
3349 EVT VT = Op.getValueType();
3350 DebugLoc dl = Op.getDebugLoc();
3351 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3353 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
3354 SDValue Offset = DAG.getConstant(4, MVT::i32);
3355 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
3356 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
3357 MachinePointerInfo(), false, false, false, 0);
3360 // Return LR, which contains the return address. Mark it an implicit live-in.
3361 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
3362 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
3365 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
3366 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3367 MFI->setFrameAddressIsTaken(true);
3369 EVT VT = Op.getValueType();
3370 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
3371 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3372 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
3373 ? ARM::R7 : ARM::R11;
3374 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
3376 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
3377 MachinePointerInfo(),
3378 false, false, false, 0);
3382 /// ExpandBITCAST - If the target supports VFP, this function is called to
3383 /// expand a bit convert where either the source or destination type is i64 to
3384 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
3385 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
3386 /// vectors), since the legalizer won't know what to do with that.
3387 static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) {
3388 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3389 DebugLoc dl = N->getDebugLoc();
3390 SDValue Op = N->getOperand(0);
3392 // This function is only supposed to be called for i64 types, either as the
3393 // source or destination of the bit convert.
3394 EVT SrcVT = Op.getValueType();
3395 EVT DstVT = N->getValueType(0);
3396 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
3397 "ExpandBITCAST called for non-i64 type");
3399 // Turn i64->f64 into VMOVDRR.
3400 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
3401 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
3402 DAG.getConstant(0, MVT::i32));
3403 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
3404 DAG.getConstant(1, MVT::i32));
3405 return DAG.getNode(ISD::BITCAST, dl, DstVT,
3406 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
3409 // Turn f64->i64 into VMOVRRD.
3410 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
3411 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
3412 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
3413 // Merge the pieces into a single i64 value.
3414 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
3420 /// getZeroVector - Returns a vector of specified type with all zero elements.
3421 /// Zero vectors are used to represent vector negation and in those cases
3422 /// will be implemented with the NEON VNEG instruction. However, VNEG does
3423 /// not support i64 elements, so sometimes the zero vectors will need to be
3424 /// explicitly constructed. Regardless, use a canonical VMOV to create the
3426 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3427 assert(VT.isVector() && "Expected a vector type");
3428 // The canonical modified immediate encoding of a zero vector is....0!
3429 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32);
3430 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
3431 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
3432 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3435 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
3436 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
3437 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
3438 SelectionDAG &DAG) const {
3439 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3440 EVT VT = Op.getValueType();
3441 unsigned VTBits = VT.getSizeInBits();
3442 DebugLoc dl = Op.getDebugLoc();
3443 SDValue ShOpLo = Op.getOperand(0);
3444 SDValue ShOpHi = Op.getOperand(1);
3445 SDValue ShAmt = Op.getOperand(2);
3447 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
3449 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
3451 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
3452 DAG.getConstant(VTBits, MVT::i32), ShAmt);
3453 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
3454 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
3455 DAG.getConstant(VTBits, MVT::i32));
3456 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
3457 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3458 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
3460 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3461 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
3463 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
3464 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
3467 SDValue Ops[2] = { Lo, Hi };
3468 return DAG.getMergeValues(Ops, 2, dl);
3471 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
3472 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
3473 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
3474 SelectionDAG &DAG) const {
3475 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3476 EVT VT = Op.getValueType();
3477 unsigned VTBits = VT.getSizeInBits();
3478 DebugLoc dl = Op.getDebugLoc();
3479 SDValue ShOpLo = Op.getOperand(0);
3480 SDValue ShOpHi = Op.getOperand(1);
3481 SDValue ShAmt = Op.getOperand(2);
3484 assert(Op.getOpcode() == ISD::SHL_PARTS);
3485 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
3486 DAG.getConstant(VTBits, MVT::i32), ShAmt);
3487 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
3488 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
3489 DAG.getConstant(VTBits, MVT::i32));
3490 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
3491 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
3493 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3494 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3495 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
3497 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
3498 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
3501 SDValue Ops[2] = { Lo, Hi };
3502 return DAG.getMergeValues(Ops, 2, dl);
3505 SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
3506 SelectionDAG &DAG) const {
3507 // The rounding mode is in bits 23:22 of the FPSCR.
3508 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
3509 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
3510 // so that the shift + and get folded into a bitfield extract.
3511 DebugLoc dl = Op.getDebugLoc();
3512 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
3513 DAG.getConstant(Intrinsic::arm_get_fpscr,
3515 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
3516 DAG.getConstant(1U << 22, MVT::i32));
3517 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
3518 DAG.getConstant(22, MVT::i32));
3519 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
3520 DAG.getConstant(3, MVT::i32));
3523 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
3524 const ARMSubtarget *ST) {
3525 EVT VT = N->getValueType(0);
3526 DebugLoc dl = N->getDebugLoc();
3528 if (!ST->hasV6T2Ops())
3531 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
3532 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
3535 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
3536 const ARMSubtarget *ST) {
3537 EVT VT = N->getValueType(0);
3538 DebugLoc dl = N->getDebugLoc();
3543 // Lower vector shifts on NEON to use VSHL.
3544 assert(ST->hasNEON() && "unexpected vector shift");
3546 // Left shifts translate directly to the vshiftu intrinsic.
3547 if (N->getOpcode() == ISD::SHL)
3548 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
3549 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
3550 N->getOperand(0), N->getOperand(1));
3552 assert((N->getOpcode() == ISD::SRA ||
3553 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
3555 // NEON uses the same intrinsics for both left and right shifts. For
3556 // right shifts, the shift amounts are negative, so negate the vector of
3558 EVT ShiftVT = N->getOperand(1).getValueType();
3559 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
3560 getZeroVector(ShiftVT, DAG, dl),
3562 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
3563 Intrinsic::arm_neon_vshifts :
3564 Intrinsic::arm_neon_vshiftu);
3565 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
3566 DAG.getConstant(vshiftInt, MVT::i32),
3567 N->getOperand(0), NegatedCount);
3570 static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
3571 const ARMSubtarget *ST) {
3572 EVT VT = N->getValueType(0);
3573 DebugLoc dl = N->getDebugLoc();
3575 // We can get here for a node like i32 = ISD::SHL i32, i64
3579 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
3580 "Unknown shift to lower!");
3582 // We only lower SRA, SRL of 1 here, all others use generic lowering.
3583 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
3584 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
3587 // If we are in thumb mode, we don't have RRX.
3588 if (ST->isThumb1Only()) return SDValue();
3590 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
3591 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
3592 DAG.getConstant(0, MVT::i32));
3593 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
3594 DAG.getConstant(1, MVT::i32));
3596 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
3597 // captures the result into a carry flag.
3598 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
3599 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), &Hi, 1);
3601 // The low part is an ARMISD::RRX operand, which shifts the carry in.
3602 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
3604 // Merge the pieces into a single i64 value.
3605 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
3608 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
3609 SDValue TmpOp0, TmpOp1;
3610 bool Invert = false;
3614 SDValue Op0 = Op.getOperand(0);
3615 SDValue Op1 = Op.getOperand(1);
3616 SDValue CC = Op.getOperand(2);
3617 EVT VT = Op.getValueType();
3618 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
3619 DebugLoc dl = Op.getDebugLoc();
3621 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
3622 switch (SetCCOpcode) {
3623 default: llvm_unreachable("Illegal FP comparison");
3625 case ISD::SETNE: Invert = true; // Fallthrough
3627 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3629 case ISD::SETLT: Swap = true; // Fallthrough
3631 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3633 case ISD::SETLE: Swap = true; // Fallthrough
3635 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3636 case ISD::SETUGE: Swap = true; // Fallthrough
3637 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
3638 case ISD::SETUGT: Swap = true; // Fallthrough
3639 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
3640 case ISD::SETUEQ: Invert = true; // Fallthrough
3642 // Expand this to (OLT | OGT).
3646 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3647 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
3649 case ISD::SETUO: Invert = true; // Fallthrough
3651 // Expand this to (OLT | OGE).
3655 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3656 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
3660 // Integer comparisons.
3661 switch (SetCCOpcode) {
3662 default: llvm_unreachable("Illegal integer comparison");
3663 case ISD::SETNE: Invert = true;
3664 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3665 case ISD::SETLT: Swap = true;
3666 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3667 case ISD::SETLE: Swap = true;
3668 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3669 case ISD::SETULT: Swap = true;
3670 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
3671 case ISD::SETULE: Swap = true;
3672 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
3675 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
3676 if (Opc == ARMISD::VCEQ) {
3679 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
3681 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
3684 // Ignore bitconvert.
3685 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST)
3686 AndOp = AndOp.getOperand(0);
3688 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
3690 Op0 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(0));
3691 Op1 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(1));
3698 std::swap(Op0, Op1);
3700 // If one of the operands is a constant vector zero, attempt to fold the
3701 // comparison to a specialized compare-against-zero form.
3703 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
3705 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) {
3706 if (Opc == ARMISD::VCGE)
3707 Opc = ARMISD::VCLEZ;
3708 else if (Opc == ARMISD::VCGT)
3709 Opc = ARMISD::VCLTZ;
3714 if (SingleOp.getNode()) {
3717 Result = DAG.getNode(ARMISD::VCEQZ, dl, VT, SingleOp); break;
3719 Result = DAG.getNode(ARMISD::VCGEZ, dl, VT, SingleOp); break;
3721 Result = DAG.getNode(ARMISD::VCLEZ, dl, VT, SingleOp); break;
3723 Result = DAG.getNode(ARMISD::VCGTZ, dl, VT, SingleOp); break;
3725 Result = DAG.getNode(ARMISD::VCLTZ, dl, VT, SingleOp); break;
3727 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3730 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3734 Result = DAG.getNOT(dl, Result, VT);
3739 /// isNEONModifiedImm - Check if the specified splat value corresponds to a
3740 /// valid vector constant for a NEON instruction with a "modified immediate"
3741 /// operand (e.g., VMOV). If so, return the encoded value.
3742 static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
3743 unsigned SplatBitSize, SelectionDAG &DAG,
3744 EVT &VT, bool is128Bits, NEONModImmType type) {
3745 unsigned OpCmode, Imm;
3747 // SplatBitSize is set to the smallest size that splats the vector, so a
3748 // zero vector will always have SplatBitSize == 8. However, NEON modified
3749 // immediate instructions others than VMOV do not support the 8-bit encoding
3750 // of a zero vector, and the default encoding of zero is supposed to be the
3755 switch (SplatBitSize) {
3757 if (type != VMOVModImm)
3759 // Any 1-byte value is OK. Op=0, Cmode=1110.
3760 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
3763 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
3767 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
3768 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
3769 if ((SplatBits & ~0xff) == 0) {
3770 // Value = 0x00nn: Op=x, Cmode=100x.
3775 if ((SplatBits & ~0xff00) == 0) {
3776 // Value = 0xnn00: Op=x, Cmode=101x.
3778 Imm = SplatBits >> 8;
3784 // NEON's 32-bit VMOV supports splat values where:
3785 // * only one byte is nonzero, or
3786 // * the least significant byte is 0xff and the second byte is nonzero, or
3787 // * the least significant 2 bytes are 0xff and the third is nonzero.
3788 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
3789 if ((SplatBits & ~0xff) == 0) {
3790 // Value = 0x000000nn: Op=x, Cmode=000x.
3795 if ((SplatBits & ~0xff00) == 0) {
3796 // Value = 0x0000nn00: Op=x, Cmode=001x.
3798 Imm = SplatBits >> 8;
3801 if ((SplatBits & ~0xff0000) == 0) {
3802 // Value = 0x00nn0000: Op=x, Cmode=010x.
3804 Imm = SplatBits >> 16;
3807 if ((SplatBits & ~0xff000000) == 0) {
3808 // Value = 0xnn000000: Op=x, Cmode=011x.
3810 Imm = SplatBits >> 24;
3814 // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC
3815 if (type == OtherModImm) return SDValue();
3817 if ((SplatBits & ~0xffff) == 0 &&
3818 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
3819 // Value = 0x0000nnff: Op=x, Cmode=1100.
3821 Imm = SplatBits >> 8;
3826 if ((SplatBits & ~0xffffff) == 0 &&
3827 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
3828 // Value = 0x00nnffff: Op=x, Cmode=1101.
3830 Imm = SplatBits >> 16;
3831 SplatBits |= 0xffff;
3835 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
3836 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
3837 // VMOV.I32. A (very) minor optimization would be to replicate the value
3838 // and fall through here to test for a valid 64-bit splat. But, then the
3839 // caller would also need to check and handle the change in size.
3843 if (type != VMOVModImm)
3845 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
3846 uint64_t BitMask = 0xff;
3848 unsigned ImmMask = 1;
3850 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
3851 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
3854 } else if ((SplatBits & BitMask) != 0) {
3860 // Op=1, Cmode=1110.
3863 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
3868 llvm_unreachable("unexpected size for isNEONModifiedImm");
3871 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
3872 return DAG.getTargetConstant(EncodedVal, MVT::i32);
3875 SDValue ARMTargetLowering::LowerConstantFP(SDValue Op, SelectionDAG &DAG,
3876 const ARMSubtarget *ST) const {
3877 if (!ST->useNEONForSinglePrecisionFP() || !ST->hasVFP3() || ST->hasD16())
3880 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Op);
3881 assert(Op.getValueType() == MVT::f32 &&
3882 "ConstantFP custom lowering should only occur for f32.");
3884 // Try splatting with a VMOV.f32...
3885 APFloat FPVal = CFP->getValueAPF();
3886 int ImmVal = ARM_AM::getFP32Imm(FPVal);
3888 DebugLoc DL = Op.getDebugLoc();
3889 SDValue NewVal = DAG.getTargetConstant(ImmVal, MVT::i32);
3890 SDValue VecConstant = DAG.getNode(ARMISD::VMOVFPIMM, DL, MVT::v2f32,
3892 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecConstant,
3893 DAG.getConstant(0, MVT::i32));
3896 // If that fails, try a VMOV.i32
3898 unsigned iVal = FPVal.bitcastToAPInt().getZExtValue();
3899 SDValue NewVal = isNEONModifiedImm(iVal, 0, 32, DAG, VMovVT, false,
3901 if (NewVal != SDValue()) {
3902 DebugLoc DL = Op.getDebugLoc();
3903 SDValue VecConstant = DAG.getNode(ARMISD::VMOVIMM, DL, VMovVT,
3905 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32,
3907 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant,
3908 DAG.getConstant(0, MVT::i32));
3911 // Finally, try a VMVN.i32
3912 NewVal = isNEONModifiedImm(~iVal & 0xffffffff, 0, 32, DAG, VMovVT, false,
3914 if (NewVal != SDValue()) {
3915 DebugLoc DL = Op.getDebugLoc();
3916 SDValue VecConstant = DAG.getNode(ARMISD::VMVNIMM, DL, VMovVT, NewVal);
3917 SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32,
3919 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant,
3920 DAG.getConstant(0, MVT::i32));
3927 static bool isVEXTMask(ArrayRef<int> M, EVT VT,
3928 bool &ReverseVEXT, unsigned &Imm) {
3929 unsigned NumElts = VT.getVectorNumElements();
3930 ReverseVEXT = false;
3932 // Assume that the first shuffle index is not UNDEF. Fail if it is.
3938 // If this is a VEXT shuffle, the immediate value is the index of the first
3939 // element. The other shuffle indices must be the successive elements after
3941 unsigned ExpectedElt = Imm;
3942 for (unsigned i = 1; i < NumElts; ++i) {
3943 // Increment the expected index. If it wraps around, it may still be
3944 // a VEXT but the source vectors must be swapped.
3946 if (ExpectedElt == NumElts * 2) {
3951 if (M[i] < 0) continue; // ignore UNDEF indices
3952 if (ExpectedElt != static_cast<unsigned>(M[i]))
3956 // Adjust the index value if the source operands will be swapped.
3963 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
3964 /// instruction with the specified blocksize. (The order of the elements
3965 /// within each block of the vector is reversed.)
3966 static bool isVREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
3967 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
3968 "Only possible block sizes for VREV are: 16, 32, 64");
3970 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3974 unsigned NumElts = VT.getVectorNumElements();
3975 unsigned BlockElts = M[0] + 1;
3976 // If the first shuffle index is UNDEF, be optimistic.
3978 BlockElts = BlockSize / EltSz;
3980 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
3983 for (unsigned i = 0; i < NumElts; ++i) {
3984 if (M[i] < 0) continue; // ignore UNDEF indices
3985 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
3992 static bool isVTBLMask(ArrayRef<int> M, EVT VT) {
3993 // We can handle <8 x i8> vector shuffles. If the index in the mask is out of
3994 // range, then 0 is placed into the resulting vector. So pretty much any mask
3995 // of 8 elements can work here.
3996 return VT == MVT::v8i8 && M.size() == 8;
3999 static bool isVTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4000 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4004 unsigned NumElts = VT.getVectorNumElements();
4005 WhichResult = (M[0] == 0 ? 0 : 1);
4006 for (unsigned i = 0; i < NumElts; i += 2) {
4007 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
4008 (M[i+1] >= 0 && (unsigned) M[i+1] != i + NumElts + WhichResult))
4014 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
4015 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4016 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
4017 static bool isVTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
4018 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4022 unsigned NumElts = VT.getVectorNumElements();
4023 WhichResult = (M[0] == 0 ? 0 : 1);
4024 for (unsigned i = 0; i < NumElts; i += 2) {
4025 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
4026 (M[i+1] >= 0 && (unsigned) M[i+1] != i + WhichResult))
4032 static bool isVUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4033 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4037 unsigned NumElts = VT.getVectorNumElements();
4038 WhichResult = (M[0] == 0 ? 0 : 1);
4039 for (unsigned i = 0; i != NumElts; ++i) {
4040 if (M[i] < 0) continue; // ignore UNDEF indices
4041 if ((unsigned) M[i] != 2 * i + WhichResult)
4045 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
4046 if (VT.is64BitVector() && EltSz == 32)
4052 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
4053 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4054 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
4055 static bool isVUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
4056 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4060 unsigned Half = VT.getVectorNumElements() / 2;
4061 WhichResult = (M[0] == 0 ? 0 : 1);
4062 for (unsigned j = 0; j != 2; ++j) {
4063 unsigned Idx = WhichResult;
4064 for (unsigned i = 0; i != Half; ++i) {
4065 int MIdx = M[i + j * Half];
4066 if (MIdx >= 0 && (unsigned) MIdx != Idx)
4072 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
4073 if (VT.is64BitVector() && EltSz == 32)
4079 static bool isVZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4080 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4084 unsigned NumElts = VT.getVectorNumElements();
4085 WhichResult = (M[0] == 0 ? 0 : 1);
4086 unsigned Idx = WhichResult * NumElts / 2;
4087 for (unsigned i = 0; i != NumElts; i += 2) {
4088 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
4089 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts))
4094 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
4095 if (VT.is64BitVector() && EltSz == 32)
4101 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
4102 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4103 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
4104 static bool isVZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
4105 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4109 unsigned NumElts = VT.getVectorNumElements();
4110 WhichResult = (M[0] == 0 ? 0 : 1);
4111 unsigned Idx = WhichResult * NumElts / 2;
4112 for (unsigned i = 0; i != NumElts; i += 2) {
4113 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
4114 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx))
4119 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
4120 if (VT.is64BitVector() && EltSz == 32)
4126 // If N is an integer constant that can be moved into a register in one
4127 // instruction, return an SDValue of such a constant (will become a MOV
4128 // instruction). Otherwise return null.
4129 static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG,
4130 const ARMSubtarget *ST, DebugLoc dl) {
4132 if (!isa<ConstantSDNode>(N))
4134 Val = cast<ConstantSDNode>(N)->getZExtValue();
4136 if (ST->isThumb1Only()) {
4137 if (Val <= 255 || ~Val <= 255)
4138 return DAG.getConstant(Val, MVT::i32);
4140 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1)
4141 return DAG.getConstant(Val, MVT::i32);
4146 // If this is a case we can't handle, return null and let the default
4147 // expansion code take care of it.
4148 SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
4149 const ARMSubtarget *ST) const {
4150 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
4151 DebugLoc dl = Op.getDebugLoc();
4152 EVT VT = Op.getValueType();
4154 APInt SplatBits, SplatUndef;
4155 unsigned SplatBitSize;
4157 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
4158 if (SplatBitSize <= 64) {
4159 // Check if an immediate VMOV works.
4161 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
4162 SplatUndef.getZExtValue(), SplatBitSize,
4163 DAG, VmovVT, VT.is128BitVector(),
4165 if (Val.getNode()) {
4166 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
4167 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
4170 // Try an immediate VMVN.
4171 uint64_t NegatedImm = (~SplatBits).getZExtValue();
4172 Val = isNEONModifiedImm(NegatedImm,
4173 SplatUndef.getZExtValue(), SplatBitSize,
4174 DAG, VmovVT, VT.is128BitVector(),
4176 if (Val.getNode()) {
4177 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
4178 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
4181 // Use vmov.f32 to materialize other v2f32 and v4f32 splats.
4182 if ((VT == MVT::v2f32 || VT == MVT::v4f32) && SplatBitSize == 32) {
4183 int ImmVal = ARM_AM::getFP32Imm(SplatBits);
4185 SDValue Val = DAG.getTargetConstant(ImmVal, MVT::i32);
4186 return DAG.getNode(ARMISD::VMOVFPIMM, dl, VT, Val);
4192 // Scan through the operands to see if only one value is used.
4194 // As an optimisation, even if more than one value is used it may be more
4195 // profitable to splat with one value then change some lanes.
4197 // Heuristically we decide to do this if the vector has a "dominant" value,
4198 // defined as splatted to more than half of the lanes.
4199 unsigned NumElts = VT.getVectorNumElements();
4200 bool isOnlyLowElement = true;
4201 bool usesOnlyOneValue = true;
4202 bool hasDominantValue = false;
4203 bool isConstant = true;
4205 // Map of the number of times a particular SDValue appears in the
4207 DenseMap<SDValue, unsigned> ValueCounts;
4209 for (unsigned i = 0; i < NumElts; ++i) {
4210 SDValue V = Op.getOperand(i);
4211 if (V.getOpcode() == ISD::UNDEF)
4214 isOnlyLowElement = false;
4215 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
4218 ValueCounts.insert(std::make_pair(V, 0));
4219 unsigned &Count = ValueCounts[V];
4221 // Is this value dominant? (takes up more than half of the lanes)
4222 if (++Count > (NumElts / 2)) {
4223 hasDominantValue = true;
4227 if (ValueCounts.size() != 1)
4228 usesOnlyOneValue = false;
4229 if (!Value.getNode() && ValueCounts.size() > 0)
4230 Value = ValueCounts.begin()->first;
4232 if (ValueCounts.size() == 0)
4233 return DAG.getUNDEF(VT);
4235 if (isOnlyLowElement)
4236 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
4238 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4240 // Use VDUP for non-constant splats. For f32 constant splats, reduce to
4241 // i32 and try again.
4242 if (hasDominantValue && EltSize <= 32) {
4246 // If we are VDUPing a value that comes directly from a vector, that will
4247 // cause an unnecessary move to and from a GPR, where instead we could
4248 // just use VDUPLANE.
4249 if (Value->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
4250 // We need to create a new undef vector to use for the VDUPLANE if the
4251 // size of the vector from which we get the value is different than the
4252 // size of the vector that we need to create. We will insert the element
4253 // such that the register coalescer will remove unnecessary copies.
4254 if (VT != Value->getOperand(0).getValueType()) {
4255 ConstantSDNode *constIndex;
4256 constIndex = dyn_cast<ConstantSDNode>(Value->getOperand(1));
4257 assert(constIndex && "The index is not a constant!");
4258 unsigned index = constIndex->getAPIntValue().getLimitedValue() %
4259 VT.getVectorNumElements();
4260 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT,
4261 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DAG.getUNDEF(VT),
4262 Value, DAG.getConstant(index, MVT::i32)),
4263 DAG.getConstant(index, MVT::i32));
4265 N = DAG.getNode(ARMISD::VDUPLANE, dl, VT,
4266 Value->getOperand(0), Value->getOperand(1));
4270 N = DAG.getNode(ARMISD::VDUP, dl, VT, Value);
4272 if (!usesOnlyOneValue) {
4273 // The dominant value was splatted as 'N', but we now have to insert
4274 // all differing elements.
4275 for (unsigned I = 0; I < NumElts; ++I) {
4276 if (Op.getOperand(I) == Value)
4278 SmallVector<SDValue, 3> Ops;
4280 Ops.push_back(Op.getOperand(I));
4281 Ops.push_back(DAG.getConstant(I, MVT::i32));
4282 N = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, &Ops[0], 3);
4287 if (VT.getVectorElementType().isFloatingPoint()) {
4288 SmallVector<SDValue, 8> Ops;
4289 for (unsigned i = 0; i < NumElts; ++i)
4290 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32,
4292 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
4293 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], NumElts);
4294 Val = LowerBUILD_VECTOR(Val, DAG, ST);
4296 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
4298 if (usesOnlyOneValue) {
4299 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
4300 if (isConstant && Val.getNode())
4301 return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
4305 // If all elements are constants and the case above didn't get hit, fall back
4306 // to the default expansion, which will generate a load from the constant
4311 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
4313 SDValue shuffle = ReconstructShuffle(Op, DAG);
4314 if (shuffle != SDValue())
4318 // Vectors with 32- or 64-bit elements can be built by directly assigning
4319 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
4320 // will be legalized.
4321 if (EltSize >= 32) {
4322 // Do the expansion with floating-point types, since that is what the VFP
4323 // registers are defined to use, and since i64 is not legal.
4324 EVT EltVT = EVT::getFloatingPointVT(EltSize);
4325 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
4326 SmallVector<SDValue, 8> Ops;
4327 for (unsigned i = 0; i < NumElts; ++i)
4328 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i)));
4329 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
4330 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
4336 // Gather data to see if the operation can be modelled as a
4337 // shuffle in combination with VEXTs.
4338 SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
4339 SelectionDAG &DAG) const {
4340 DebugLoc dl = Op.getDebugLoc();
4341 EVT VT = Op.getValueType();
4342 unsigned NumElts = VT.getVectorNumElements();
4344 SmallVector<SDValue, 2> SourceVecs;
4345 SmallVector<unsigned, 2> MinElts;
4346 SmallVector<unsigned, 2> MaxElts;
4348 for (unsigned i = 0; i < NumElts; ++i) {
4349 SDValue V = Op.getOperand(i);
4350 if (V.getOpcode() == ISD::UNDEF)
4352 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
4353 // A shuffle can only come from building a vector from various
4354 // elements of other vectors.
4356 } else if (V.getOperand(0).getValueType().getVectorElementType() !=
4357 VT.getVectorElementType()) {
4358 // This code doesn't know how to handle shuffles where the vector
4359 // element types do not match (this happens because type legalization
4360 // promotes the return type of EXTRACT_VECTOR_ELT).
4361 // FIXME: It might be appropriate to extend this code to handle
4362 // mismatched types.
4366 // Record this extraction against the appropriate vector if possible...
4367 SDValue SourceVec = V.getOperand(0);
4368 // If the element number isn't a constant, we can't effectively
4369 // analyze what's going on.
4370 if (!isa<ConstantSDNode>(V.getOperand(1)))
4372 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
4373 bool FoundSource = false;
4374 for (unsigned j = 0; j < SourceVecs.size(); ++j) {
4375 if (SourceVecs[j] == SourceVec) {
4376 if (MinElts[j] > EltNo)
4378 if (MaxElts[j] < EltNo)
4385 // Or record a new source if not...
4387 SourceVecs.push_back(SourceVec);
4388 MinElts.push_back(EltNo);
4389 MaxElts.push_back(EltNo);
4393 // Currently only do something sane when at most two source vectors
4395 if (SourceVecs.size() > 2)
4398 SDValue ShuffleSrcs[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT) };
4399 int VEXTOffsets[2] = {0, 0};
4401 // This loop extracts the usage patterns of the source vectors
4402 // and prepares appropriate SDValues for a shuffle if possible.
4403 for (unsigned i = 0; i < SourceVecs.size(); ++i) {
4404 if (SourceVecs[i].getValueType() == VT) {
4405 // No VEXT necessary
4406 ShuffleSrcs[i] = SourceVecs[i];
4409 } else if (SourceVecs[i].getValueType().getVectorNumElements() < NumElts) {
4410 // It probably isn't worth padding out a smaller vector just to
4411 // break it down again in a shuffle.
4415 // Since only 64-bit and 128-bit vectors are legal on ARM and
4416 // we've eliminated the other cases...
4417 assert(SourceVecs[i].getValueType().getVectorNumElements() == 2*NumElts &&
4418 "unexpected vector sizes in ReconstructShuffle");
4420 if (MaxElts[i] - MinElts[i] >= NumElts) {
4421 // Span too large for a VEXT to cope
4425 if (MinElts[i] >= NumElts) {
4426 // The extraction can just take the second half
4427 VEXTOffsets[i] = NumElts;
4428 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4430 DAG.getIntPtrConstant(NumElts));
4431 } else if (MaxElts[i] < NumElts) {
4432 // The extraction can just take the first half
4434 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4436 DAG.getIntPtrConstant(0));
4438 // An actual VEXT is needed
4439 VEXTOffsets[i] = MinElts[i];
4440 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4442 DAG.getIntPtrConstant(0));
4443 SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4445 DAG.getIntPtrConstant(NumElts));
4446 ShuffleSrcs[i] = DAG.getNode(ARMISD::VEXT, dl, VT, VEXTSrc1, VEXTSrc2,
4447 DAG.getConstant(VEXTOffsets[i], MVT::i32));
4451 SmallVector<int, 8> Mask;
4453 for (unsigned i = 0; i < NumElts; ++i) {
4454 SDValue Entry = Op.getOperand(i);
4455 if (Entry.getOpcode() == ISD::UNDEF) {
4460 SDValue ExtractVec = Entry.getOperand(0);
4461 int ExtractElt = cast<ConstantSDNode>(Op.getOperand(i)
4462 .getOperand(1))->getSExtValue();
4463 if (ExtractVec == SourceVecs[0]) {
4464 Mask.push_back(ExtractElt - VEXTOffsets[0]);
4466 Mask.push_back(ExtractElt + NumElts - VEXTOffsets[1]);
4470 // Final check before we try to produce nonsense...
4471 if (isShuffleMaskLegal(Mask, VT))
4472 return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1],
4478 /// isShuffleMaskLegal - Targets can use this to indicate that they only
4479 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
4480 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
4481 /// are assumed to be legal.
4483 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
4485 if (VT.getVectorNumElements() == 4 &&
4486 (VT.is128BitVector() || VT.is64BitVector())) {
4487 unsigned PFIndexes[4];
4488 for (unsigned i = 0; i != 4; ++i) {
4492 PFIndexes[i] = M[i];
4495 // Compute the index in the perfect shuffle table.
4496 unsigned PFTableIndex =
4497 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
4498 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4499 unsigned Cost = (PFEntry >> 30);
4506 unsigned Imm, WhichResult;
4508 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4509 return (EltSize >= 32 ||
4510 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
4511 isVREVMask(M, VT, 64) ||
4512 isVREVMask(M, VT, 32) ||
4513 isVREVMask(M, VT, 16) ||
4514 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
4515 isVTBLMask(M, VT) ||
4516 isVTRNMask(M, VT, WhichResult) ||
4517 isVUZPMask(M, VT, WhichResult) ||
4518 isVZIPMask(M, VT, WhichResult) ||
4519 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
4520 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
4521 isVZIP_v_undef_Mask(M, VT, WhichResult));
4524 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
4525 /// the specified operations to build the shuffle.
4526 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
4527 SDValue RHS, SelectionDAG &DAG,
4529 unsigned OpNum = (PFEntry >> 26) & 0x0F;
4530 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
4531 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
4534 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
4543 OP_VUZPL, // VUZP, left result
4544 OP_VUZPR, // VUZP, right result
4545 OP_VZIPL, // VZIP, left result
4546 OP_VZIPR, // VZIP, right result
4547 OP_VTRNL, // VTRN, left result
4548 OP_VTRNR // VTRN, right result
4551 if (OpNum == OP_COPY) {
4552 if (LHSID == (1*9+2)*9+3) return LHS;
4553 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
4557 SDValue OpLHS, OpRHS;
4558 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
4559 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
4560 EVT VT = OpLHS.getValueType();
4563 default: llvm_unreachable("Unknown shuffle opcode!");
4565 // VREV divides the vector in half and swaps within the half.
4566 if (VT.getVectorElementType() == MVT::i32 ||
4567 VT.getVectorElementType() == MVT::f32)
4568 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
4569 // vrev <4 x i16> -> VREV32
4570 if (VT.getVectorElementType() == MVT::i16)
4571 return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS);
4572 // vrev <4 x i8> -> VREV16
4573 assert(VT.getVectorElementType() == MVT::i8);
4574 return DAG.getNode(ARMISD::VREV16, dl, VT, OpLHS);
4579 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
4580 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
4584 return DAG.getNode(ARMISD::VEXT, dl, VT,
4586 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
4589 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4590 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
4593 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4594 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
4597 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4598 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
4602 static SDValue LowerVECTOR_SHUFFLEv8i8(SDValue Op,
4603 ArrayRef<int> ShuffleMask,
4604 SelectionDAG &DAG) {
4605 // Check to see if we can use the VTBL instruction.
4606 SDValue V1 = Op.getOperand(0);
4607 SDValue V2 = Op.getOperand(1);
4608 DebugLoc DL = Op.getDebugLoc();
4610 SmallVector<SDValue, 8> VTBLMask;
4611 for (ArrayRef<int>::iterator
4612 I = ShuffleMask.begin(), E = ShuffleMask.end(); I != E; ++I)
4613 VTBLMask.push_back(DAG.getConstant(*I, MVT::i32));
4615 if (V2.getNode()->getOpcode() == ISD::UNDEF)
4616 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1,
4617 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
4620 return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2,
4621 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
4625 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
4626 SDValue V1 = Op.getOperand(0);
4627 SDValue V2 = Op.getOperand(1);
4628 DebugLoc dl = Op.getDebugLoc();
4629 EVT VT = Op.getValueType();
4630 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
4632 // Convert shuffles that are directly supported on NEON to target-specific
4633 // DAG nodes, instead of keeping them as shuffles and matching them again
4634 // during code selection. This is more efficient and avoids the possibility
4635 // of inconsistencies between legalization and selection.
4636 // FIXME: floating-point vectors should be canonicalized to integer vectors
4637 // of the same time so that they get CSEd properly.
4638 ArrayRef<int> ShuffleMask = SVN->getMask();
4640 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4641 if (EltSize <= 32) {
4642 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
4643 int Lane = SVN->getSplatIndex();
4644 // If this is undef splat, generate it via "just" vdup, if possible.
4645 if (Lane == -1) Lane = 0;
4647 // Test if V1 is a SCALAR_TO_VECTOR.
4648 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4649 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
4651 // Test if V1 is a BUILD_VECTOR which is equivalent to a SCALAR_TO_VECTOR
4652 // (and probably will turn into a SCALAR_TO_VECTOR once legalization
4654 if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
4655 !isa<ConstantSDNode>(V1.getOperand(0))) {
4656 bool IsScalarToVector = true;
4657 for (unsigned i = 1, e = V1.getNumOperands(); i != e; ++i)
4658 if (V1.getOperand(i).getOpcode() != ISD::UNDEF) {
4659 IsScalarToVector = false;
4662 if (IsScalarToVector)
4663 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
4665 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
4666 DAG.getConstant(Lane, MVT::i32));
4671 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
4674 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
4675 DAG.getConstant(Imm, MVT::i32));
4678 if (isVREVMask(ShuffleMask, VT, 64))
4679 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
4680 if (isVREVMask(ShuffleMask, VT, 32))
4681 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
4682 if (isVREVMask(ShuffleMask, VT, 16))
4683 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
4685 // Check for Neon shuffles that modify both input vectors in place.
4686 // If both results are used, i.e., if there are two shuffles with the same
4687 // source operands and with masks corresponding to both results of one of
4688 // these operations, DAG memoization will ensure that a single node is
4689 // used for both shuffles.
4690 unsigned WhichResult;
4691 if (isVTRNMask(ShuffleMask, VT, WhichResult))
4692 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4693 V1, V2).getValue(WhichResult);
4694 if (isVUZPMask(ShuffleMask, VT, WhichResult))
4695 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4696 V1, V2).getValue(WhichResult);
4697 if (isVZIPMask(ShuffleMask, VT, WhichResult))
4698 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4699 V1, V2).getValue(WhichResult);
4701 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
4702 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4703 V1, V1).getValue(WhichResult);
4704 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
4705 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4706 V1, V1).getValue(WhichResult);
4707 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
4708 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4709 V1, V1).getValue(WhichResult);
4712 // If the shuffle is not directly supported and it has 4 elements, use
4713 // the PerfectShuffle-generated table to synthesize it from other shuffles.
4714 unsigned NumElts = VT.getVectorNumElements();
4716 unsigned PFIndexes[4];
4717 for (unsigned i = 0; i != 4; ++i) {
4718 if (ShuffleMask[i] < 0)
4721 PFIndexes[i] = ShuffleMask[i];
4724 // Compute the index in the perfect shuffle table.
4725 unsigned PFTableIndex =
4726 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
4727 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4728 unsigned Cost = (PFEntry >> 30);
4731 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
4734 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
4735 if (EltSize >= 32) {
4736 // Do the expansion with floating-point types, since that is what the VFP
4737 // registers are defined to use, and since i64 is not legal.
4738 EVT EltVT = EVT::getFloatingPointVT(EltSize);
4739 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
4740 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1);
4741 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2);
4742 SmallVector<SDValue, 8> Ops;
4743 for (unsigned i = 0; i < NumElts; ++i) {
4744 if (ShuffleMask[i] < 0)
4745 Ops.push_back(DAG.getUNDEF(EltVT));
4747 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
4748 ShuffleMask[i] < (int)NumElts ? V1 : V2,
4749 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
4752 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
4753 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
4756 if (VT == MVT::v8i8) {
4757 SDValue NewOp = LowerVECTOR_SHUFFLEv8i8(Op, ShuffleMask, DAG);
4758 if (NewOp.getNode())
4765 static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4766 // INSERT_VECTOR_ELT is legal only for immediate indexes.
4767 SDValue Lane = Op.getOperand(2);
4768 if (!isa<ConstantSDNode>(Lane))
4774 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4775 // EXTRACT_VECTOR_ELT is legal only for immediate indexes.
4776 SDValue Lane = Op.getOperand(1);
4777 if (!isa<ConstantSDNode>(Lane))
4780 SDValue Vec = Op.getOperand(0);
4781 if (Op.getValueType() == MVT::i32 &&
4782 Vec.getValueType().getVectorElementType().getSizeInBits() < 32) {
4783 DebugLoc dl = Op.getDebugLoc();
4784 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
4790 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
4791 // The only time a CONCAT_VECTORS operation can have legal types is when
4792 // two 64-bit vectors are concatenated to a 128-bit vector.
4793 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
4794 "unexpected CONCAT_VECTORS");
4795 DebugLoc dl = Op.getDebugLoc();
4796 SDValue Val = DAG.getUNDEF(MVT::v2f64);
4797 SDValue Op0 = Op.getOperand(0);
4798 SDValue Op1 = Op.getOperand(1);
4799 if (Op0.getOpcode() != ISD::UNDEF)
4800 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
4801 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0),
4802 DAG.getIntPtrConstant(0));
4803 if (Op1.getOpcode() != ISD::UNDEF)
4804 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
4805 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1),
4806 DAG.getIntPtrConstant(1));
4807 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val);
4810 /// isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each
4811 /// element has been zero/sign-extended, depending on the isSigned parameter,
4812 /// from an integer type half its size.
4813 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
4815 // A v2i64 BUILD_VECTOR will have been legalized to a BITCAST from v4i32.
4816 EVT VT = N->getValueType(0);
4817 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) {
4818 SDNode *BVN = N->getOperand(0).getNode();
4819 if (BVN->getValueType(0) != MVT::v4i32 ||
4820 BVN->getOpcode() != ISD::BUILD_VECTOR)
4822 unsigned LoElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
4823 unsigned HiElt = 1 - LoElt;
4824 ConstantSDNode *Lo0 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt));
4825 ConstantSDNode *Hi0 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt));
4826 ConstantSDNode *Lo1 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt+2));
4827 ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2));
4828 if (!Lo0 || !Hi0 || !Lo1 || !Hi1)
4831 if (Hi0->getSExtValue() == Lo0->getSExtValue() >> 32 &&
4832 Hi1->getSExtValue() == Lo1->getSExtValue() >> 32)
4835 if (Hi0->isNullValue() && Hi1->isNullValue())
4841 if (N->getOpcode() != ISD::BUILD_VECTOR)
4844 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
4845 SDNode *Elt = N->getOperand(i).getNode();
4846 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
4847 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4848 unsigned HalfSize = EltSize / 2;
4850 if (!isIntN(HalfSize, C->getSExtValue()))
4853 if (!isUIntN(HalfSize, C->getZExtValue()))
4864 /// isSignExtended - Check if a node is a vector value that is sign-extended
4865 /// or a constant BUILD_VECTOR with sign-extended elements.
4866 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
4867 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N))
4869 if (isExtendedBUILD_VECTOR(N, DAG, true))
4874 /// isZeroExtended - Check if a node is a vector value that is zero-extended
4875 /// or a constant BUILD_VECTOR with zero-extended elements.
4876 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
4877 if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N))
4879 if (isExtendedBUILD_VECTOR(N, DAG, false))
4884 /// SkipExtension - For a node that is a SIGN_EXTEND, ZERO_EXTEND, extending
4885 /// load, or BUILD_VECTOR with extended elements, return the unextended value.
4886 static SDValue SkipExtension(SDNode *N, SelectionDAG &DAG) {
4887 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
4888 return N->getOperand(0);
4889 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
4890 return DAG.getLoad(LD->getMemoryVT(), N->getDebugLoc(), LD->getChain(),
4891 LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(),
4892 LD->isNonTemporal(), LD->isInvariant(),
4893 LD->getAlignment());
4894 // Otherwise, the value must be a BUILD_VECTOR. For v2i64, it will
4895 // have been legalized as a BITCAST from v4i32.
4896 if (N->getOpcode() == ISD::BITCAST) {
4897 SDNode *BVN = N->getOperand(0).getNode();
4898 assert(BVN->getOpcode() == ISD::BUILD_VECTOR &&
4899 BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR");
4900 unsigned LowElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
4901 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), MVT::v2i32,
4902 BVN->getOperand(LowElt), BVN->getOperand(LowElt+2));
4904 // Construct a new BUILD_VECTOR with elements truncated to half the size.
4905 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
4906 EVT VT = N->getValueType(0);
4907 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
4908 unsigned NumElts = VT.getVectorNumElements();
4909 MVT TruncVT = MVT::getIntegerVT(EltSize);
4910 SmallVector<SDValue, 8> Ops;
4911 for (unsigned i = 0; i != NumElts; ++i) {
4912 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
4913 const APInt &CInt = C->getAPIntValue();
4914 // Element types smaller than 32 bits are not legal, so use i32 elements.
4915 // The values are implicitly truncated so sext vs. zext doesn't matter.
4916 Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), MVT::i32));
4918 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
4919 MVT::getVectorVT(TruncVT, NumElts), Ops.data(), NumElts);
4922 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
4923 unsigned Opcode = N->getOpcode();
4924 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
4925 SDNode *N0 = N->getOperand(0).getNode();
4926 SDNode *N1 = N->getOperand(1).getNode();
4927 return N0->hasOneUse() && N1->hasOneUse() &&
4928 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
4933 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
4934 unsigned Opcode = N->getOpcode();
4935 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
4936 SDNode *N0 = N->getOperand(0).getNode();
4937 SDNode *N1 = N->getOperand(1).getNode();
4938 return N0->hasOneUse() && N1->hasOneUse() &&
4939 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
4944 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
4945 // Multiplications are only custom-lowered for 128-bit vectors so that
4946 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
4947 EVT VT = Op.getValueType();
4948 assert(VT.is128BitVector() && "unexpected type for custom-lowering ISD::MUL");
4949 SDNode *N0 = Op.getOperand(0).getNode();
4950 SDNode *N1 = Op.getOperand(1).getNode();
4951 unsigned NewOpc = 0;
4953 bool isN0SExt = isSignExtended(N0, DAG);
4954 bool isN1SExt = isSignExtended(N1, DAG);
4955 if (isN0SExt && isN1SExt)
4956 NewOpc = ARMISD::VMULLs;
4958 bool isN0ZExt = isZeroExtended(N0, DAG);
4959 bool isN1ZExt = isZeroExtended(N1, DAG);
4960 if (isN0ZExt && isN1ZExt)
4961 NewOpc = ARMISD::VMULLu;
4962 else if (isN1SExt || isN1ZExt) {
4963 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
4964 // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
4965 if (isN1SExt && isAddSubSExt(N0, DAG)) {
4966 NewOpc = ARMISD::VMULLs;
4968 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
4969 NewOpc = ARMISD::VMULLu;
4971 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
4973 NewOpc = ARMISD::VMULLu;
4979 if (VT == MVT::v2i64)
4980 // Fall through to expand this. It is not legal.
4983 // Other vector multiplications are legal.
4988 // Legalize to a VMULL instruction.
4989 DebugLoc DL = Op.getDebugLoc();
4991 SDValue Op1 = SkipExtension(N1, DAG);
4993 Op0 = SkipExtension(N0, DAG);
4994 assert(Op0.getValueType().is64BitVector() &&
4995 Op1.getValueType().is64BitVector() &&
4996 "unexpected types for extended operands to VMULL");
4997 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
5000 // Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during
5001 // isel lowering to take advantage of no-stall back to back vmul + vmla.
5008 SDValue N00 = SkipExtension(N0->getOperand(0).getNode(), DAG);
5009 SDValue N01 = SkipExtension(N0->getOperand(1).getNode(), DAG);
5010 EVT Op1VT = Op1.getValueType();
5011 return DAG.getNode(N0->getOpcode(), DL, VT,
5012 DAG.getNode(NewOpc, DL, VT,
5013 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
5014 DAG.getNode(NewOpc, DL, VT,
5015 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
5019 LowerSDIV_v4i8(SDValue X, SDValue Y, DebugLoc dl, SelectionDAG &DAG) {
5021 // float4 xf = vcvt_f32_s32(vmovl_s16(a.lo));
5022 // float4 yf = vcvt_f32_s32(vmovl_s16(b.lo));
5023 X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X);
5024 Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y);
5025 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X);
5026 Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y);
5027 // Get reciprocal estimate.
5028 // float4 recip = vrecpeq_f32(yf);
5029 Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
5030 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), Y);
5031 // Because char has a smaller range than uchar, we can actually get away
5032 // without any newton steps. This requires that we use a weird bias
5033 // of 0xb000, however (again, this has been exhaustively tested).
5034 // float4 result = as_float4(as_int4(xf*recip) + 0xb000);
5035 X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y);
5036 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X);
5037 Y = DAG.getConstant(0xb000, MVT::i32);
5038 Y = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Y, Y, Y, Y);
5039 X = DAG.getNode(ISD::ADD, dl, MVT::v4i32, X, Y);
5040 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X);
5041 // Convert back to short.
5042 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X);
5043 X = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, X);
5048 LowerSDIV_v4i16(SDValue N0, SDValue N1, DebugLoc dl, SelectionDAG &DAG) {
5050 // Convert to float.
5051 // float4 yf = vcvt_f32_s32(vmovl_s16(y));
5052 // float4 xf = vcvt_f32_s32(vmovl_s16(x));
5053 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0);
5054 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1);
5055 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
5056 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
5058 // Use reciprocal estimate and one refinement step.
5059 // float4 recip = vrecpeq_f32(yf);
5060 // recip *= vrecpsq_f32(yf, recip);
5061 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
5062 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1);
5063 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
5064 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
5066 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
5067 // Because short has a smaller range than ushort, we can actually get away
5068 // with only a single newton step. This requires that we use a weird bias
5069 // of 89, however (again, this has been exhaustively tested).
5070 // float4 result = as_float4(as_int4(xf*recip) + 0x89);
5071 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
5072 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
5073 N1 = DAG.getConstant(0x89, MVT::i32);
5074 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
5075 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
5076 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
5077 // Convert back to integer and return.
5078 // return vmovn_s32(vcvt_s32_f32(result));
5079 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
5080 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
5084 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
5085 EVT VT = Op.getValueType();
5086 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
5087 "unexpected type for custom-lowering ISD::SDIV");
5089 DebugLoc dl = Op.getDebugLoc();
5090 SDValue N0 = Op.getOperand(0);
5091 SDValue N1 = Op.getOperand(1);
5094 if (VT == MVT::v8i8) {
5095 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0);
5096 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1);
5098 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
5099 DAG.getIntPtrConstant(4));
5100 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
5101 DAG.getIntPtrConstant(4));
5102 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
5103 DAG.getIntPtrConstant(0));
5104 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
5105 DAG.getIntPtrConstant(0));
5107 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16
5108 N2 = LowerSDIV_v4i8(N2, N3, dl, DAG); // v4i16
5110 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
5111 N0 = LowerCONCAT_VECTORS(N0, DAG);
5113 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0);
5116 return LowerSDIV_v4i16(N0, N1, dl, DAG);
5119 static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG) {
5120 EVT VT = Op.getValueType();
5121 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
5122 "unexpected type for custom-lowering ISD::UDIV");
5124 DebugLoc dl = Op.getDebugLoc();
5125 SDValue N0 = Op.getOperand(0);
5126 SDValue N1 = Op.getOperand(1);
5129 if (VT == MVT::v8i8) {
5130 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0);
5131 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1);
5133 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
5134 DAG.getIntPtrConstant(4));
5135 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
5136 DAG.getIntPtrConstant(4));
5137 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
5138 DAG.getIntPtrConstant(0));
5139 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
5140 DAG.getIntPtrConstant(0));
5142 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16
5143 N2 = LowerSDIV_v4i16(N2, N3, dl, DAG); // v4i16
5145 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
5146 N0 = LowerCONCAT_VECTORS(N0, DAG);
5148 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8,
5149 DAG.getConstant(Intrinsic::arm_neon_vqmovnsu, MVT::i32),
5154 // v4i16 sdiv ... Convert to float.
5155 // float4 yf = vcvt_f32_s32(vmovl_u16(y));
5156 // float4 xf = vcvt_f32_s32(vmovl_u16(x));
5157 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0);
5158 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1);
5159 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
5160 SDValue BN1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
5162 // Use reciprocal estimate and two refinement steps.
5163 // float4 recip = vrecpeq_f32(yf);
5164 // recip *= vrecpsq_f32(yf, recip);
5165 // recip *= vrecpsq_f32(yf, recip);
5166 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
5167 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), BN1);
5168 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
5169 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
5171 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
5172 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
5173 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
5175 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
5176 // Simply multiplying by the reciprocal estimate can leave us a few ulps
5177 // too low, so we add 2 ulps (exhaustive testing shows that this is enough,
5178 // and that it will never cause us to return an answer too large).
5179 // float4 result = as_float4(as_int4(xf*recip) + 2);
5180 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
5181 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
5182 N1 = DAG.getConstant(2, MVT::i32);
5183 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
5184 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
5185 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
5186 // Convert back to integer and return.
5187 // return vmovn_u32(vcvt_s32_f32(result));
5188 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
5189 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
5193 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
5194 EVT VT = Op.getNode()->getValueType(0);
5195 SDVTList VTs = DAG.getVTList(VT, MVT::i32);
5198 bool ExtraOp = false;
5199 switch (Op.getOpcode()) {
5200 default: llvm_unreachable("Invalid code");
5201 case ISD::ADDC: Opc = ARMISD::ADDC; break;
5202 case ISD::ADDE: Opc = ARMISD::ADDE; ExtraOp = true; break;
5203 case ISD::SUBC: Opc = ARMISD::SUBC; break;
5204 case ISD::SUBE: Opc = ARMISD::SUBE; ExtraOp = true; break;
5208 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
5210 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0),
5211 Op.getOperand(1), Op.getOperand(2));
5214 static SDValue LowerAtomicLoadStore(SDValue Op, SelectionDAG &DAG) {
5215 // Monotonic load/store is legal for all targets
5216 if (cast<AtomicSDNode>(Op)->getOrdering() <= Monotonic)
5219 // Aquire/Release load/store is not legal for targets without a
5220 // dmb or equivalent available.
5226 ReplaceATOMIC_OP_64(SDNode *Node, SmallVectorImpl<SDValue>& Results,
5227 SelectionDAG &DAG, unsigned NewOp) {
5228 DebugLoc dl = Node->getDebugLoc();
5229 assert (Node->getValueType(0) == MVT::i64 &&
5230 "Only know how to expand i64 atomics");
5232 SmallVector<SDValue, 6> Ops;
5233 Ops.push_back(Node->getOperand(0)); // Chain
5234 Ops.push_back(Node->getOperand(1)); // Ptr
5236 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5237 Node->getOperand(2), DAG.getIntPtrConstant(0)));
5238 // High part of Val1
5239 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5240 Node->getOperand(2), DAG.getIntPtrConstant(1)));
5241 if (NewOp == ARMISD::ATOMCMPXCHG64_DAG) {
5242 // High part of Val1
5243 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5244 Node->getOperand(3), DAG.getIntPtrConstant(0)));
5245 // High part of Val2
5246 Ops.push_back(DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
5247 Node->getOperand(3), DAG.getIntPtrConstant(1)));
5249 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
5251 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops.data(), Ops.size(), MVT::i64,
5252 cast<MemSDNode>(Node)->getMemOperand());
5253 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1) };
5254 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2));
5255 Results.push_back(Result.getValue(2));
5258 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
5259 switch (Op.getOpcode()) {
5260 default: llvm_unreachable("Don't know how to custom lower this!");
5261 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
5262 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
5263 case ISD::GlobalAddress:
5264 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
5265 LowerGlobalAddressELF(Op, DAG);
5266 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
5267 case ISD::SELECT: return LowerSELECT(Op, DAG);
5268 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
5269 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
5270 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
5271 case ISD::VASTART: return LowerVASTART(Op, DAG);
5272 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget);
5273 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG, Subtarget);
5274 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget);
5275 case ISD::SINT_TO_FP:
5276 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
5277 case ISD::FP_TO_SINT:
5278 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
5279 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
5280 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
5281 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
5282 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
5283 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
5284 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
5285 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
5287 case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG);
5290 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
5291 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
5292 case ISD::SRL_PARTS:
5293 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
5294 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
5295 case ISD::SETCC: return LowerVSETCC(Op, DAG);
5296 case ISD::ConstantFP: return LowerConstantFP(Op, DAG, Subtarget);
5297 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
5298 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
5299 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
5300 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
5301 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
5302 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
5303 case ISD::MUL: return LowerMUL(Op, DAG);
5304 case ISD::SDIV: return LowerSDIV(Op, DAG);
5305 case ISD::UDIV: return LowerUDIV(Op, DAG);
5309 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
5310 case ISD::ATOMIC_LOAD:
5311 case ISD::ATOMIC_STORE: return LowerAtomicLoadStore(Op, DAG);
5315 /// ReplaceNodeResults - Replace the results of node with an illegal result
5316 /// type with new values built out of custom code.
5317 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
5318 SmallVectorImpl<SDValue>&Results,
5319 SelectionDAG &DAG) const {
5321 switch (N->getOpcode()) {
5323 llvm_unreachable("Don't know how to custom expand this!");
5325 Res = ExpandBITCAST(N, DAG);
5329 Res = Expand64BitShift(N, DAG, Subtarget);
5331 case ISD::ATOMIC_LOAD_ADD:
5332 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMADD64_DAG);
5334 case ISD::ATOMIC_LOAD_AND:
5335 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMAND64_DAG);
5337 case ISD::ATOMIC_LOAD_NAND:
5338 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMNAND64_DAG);
5340 case ISD::ATOMIC_LOAD_OR:
5341 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMOR64_DAG);
5343 case ISD::ATOMIC_LOAD_SUB:
5344 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMSUB64_DAG);
5346 case ISD::ATOMIC_LOAD_XOR:
5347 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMXOR64_DAG);
5349 case ISD::ATOMIC_SWAP:
5350 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMSWAP64_DAG);
5352 case ISD::ATOMIC_CMP_SWAP:
5353 ReplaceATOMIC_OP_64(N, Results, DAG, ARMISD::ATOMCMPXCHG64_DAG);
5357 Results.push_back(Res);
5360 //===----------------------------------------------------------------------===//
5361 // ARM Scheduler Hooks
5362 //===----------------------------------------------------------------------===//
5365 ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
5366 MachineBasicBlock *BB,
5367 unsigned Size) const {
5368 unsigned dest = MI->getOperand(0).getReg();
5369 unsigned ptr = MI->getOperand(1).getReg();
5370 unsigned oldval = MI->getOperand(2).getReg();
5371 unsigned newval = MI->getOperand(3).getReg();
5372 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5373 DebugLoc dl = MI->getDebugLoc();
5374 bool isThumb2 = Subtarget->isThumb2();
5376 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
5377 unsigned scratch = MRI.createVirtualRegister(isThumb2 ?
5378 (const TargetRegisterClass*)&ARM::rGPRRegClass :
5379 (const TargetRegisterClass*)&ARM::GPRRegClass);
5382 MRI.constrainRegClass(dest, &ARM::rGPRRegClass);
5383 MRI.constrainRegClass(oldval, &ARM::rGPRRegClass);
5384 MRI.constrainRegClass(newval, &ARM::rGPRRegClass);
5387 unsigned ldrOpc, strOpc;
5389 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
5391 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
5392 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
5395 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
5396 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
5399 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
5400 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
5404 MachineFunction *MF = BB->getParent();
5405 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5406 MachineFunction::iterator It = BB;
5407 ++It; // insert the new blocks after the current block
5409 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
5410 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
5411 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5412 MF->insert(It, loop1MBB);
5413 MF->insert(It, loop2MBB);
5414 MF->insert(It, exitMBB);
5416 // Transfer the remainder of BB and its successor edges to exitMBB.
5417 exitMBB->splice(exitMBB->begin(), BB,
5418 llvm::next(MachineBasicBlock::iterator(MI)),
5420 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5424 // fallthrough --> loop1MBB
5425 BB->addSuccessor(loop1MBB);
5428 // ldrex dest, [ptr]
5432 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
5433 if (ldrOpc == ARM::t2LDREX)
5435 AddDefaultPred(MIB);
5436 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
5437 .addReg(dest).addReg(oldval));
5438 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5439 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5440 BB->addSuccessor(loop2MBB);
5441 BB->addSuccessor(exitMBB);
5444 // strex scratch, newval, [ptr]
5448 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval).addReg(ptr);
5449 if (strOpc == ARM::t2STREX)
5451 AddDefaultPred(MIB);
5452 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5453 .addReg(scratch).addImm(0));
5454 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5455 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5456 BB->addSuccessor(loop1MBB);
5457 BB->addSuccessor(exitMBB);
5463 MI->eraseFromParent(); // The instruction is gone now.
5469 ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
5470 unsigned Size, unsigned BinOpcode) const {
5471 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
5472 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5474 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5475 MachineFunction *MF = BB->getParent();
5476 MachineFunction::iterator It = BB;
5479 unsigned dest = MI->getOperand(0).getReg();
5480 unsigned ptr = MI->getOperand(1).getReg();
5481 unsigned incr = MI->getOperand(2).getReg();
5482 DebugLoc dl = MI->getDebugLoc();
5483 bool isThumb2 = Subtarget->isThumb2();
5485 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
5487 MRI.constrainRegClass(dest, &ARM::rGPRRegClass);
5488 MRI.constrainRegClass(ptr, &ARM::rGPRRegClass);
5491 unsigned ldrOpc, strOpc;
5493 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
5495 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
5496 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
5499 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
5500 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
5503 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
5504 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
5508 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5509 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5510 MF->insert(It, loopMBB);
5511 MF->insert(It, exitMBB);
5513 // Transfer the remainder of BB and its successor edges to exitMBB.
5514 exitMBB->splice(exitMBB->begin(), BB,
5515 llvm::next(MachineBasicBlock::iterator(MI)),
5517 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5519 const TargetRegisterClass *TRC = isThumb2 ?
5520 (const TargetRegisterClass*)&ARM::rGPRRegClass :
5521 (const TargetRegisterClass*)&ARM::GPRRegClass;
5522 unsigned scratch = MRI.createVirtualRegister(TRC);
5523 unsigned scratch2 = (!BinOpcode) ? incr : MRI.createVirtualRegister(TRC);
5527 // fallthrough --> loopMBB
5528 BB->addSuccessor(loopMBB);
5532 // <binop> scratch2, dest, incr
5533 // strex scratch, scratch2, ptr
5536 // fallthrough --> exitMBB
5538 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
5539 if (ldrOpc == ARM::t2LDREX)
5541 AddDefaultPred(MIB);
5543 // operand order needs to go the other way for NAND
5544 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr)
5545 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
5546 addReg(incr).addReg(dest)).addReg(0);
5548 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
5549 addReg(dest).addReg(incr)).addReg(0);
5552 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2).addReg(ptr);
5553 if (strOpc == ARM::t2STREX)
5555 AddDefaultPred(MIB);
5556 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5557 .addReg(scratch).addImm(0));
5558 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5559 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5561 BB->addSuccessor(loopMBB);
5562 BB->addSuccessor(exitMBB);
5568 MI->eraseFromParent(); // The instruction is gone now.
5574 ARMTargetLowering::EmitAtomicBinaryMinMax(MachineInstr *MI,
5575 MachineBasicBlock *BB,
5578 ARMCC::CondCodes Cond) const {
5579 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5581 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5582 MachineFunction *MF = BB->getParent();
5583 MachineFunction::iterator It = BB;
5586 unsigned dest = MI->getOperand(0).getReg();
5587 unsigned ptr = MI->getOperand(1).getReg();
5588 unsigned incr = MI->getOperand(2).getReg();
5589 unsigned oldval = dest;
5590 DebugLoc dl = MI->getDebugLoc();
5591 bool isThumb2 = Subtarget->isThumb2();
5593 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
5595 MRI.constrainRegClass(dest, &ARM::rGPRRegClass);
5596 MRI.constrainRegClass(ptr, &ARM::rGPRRegClass);
5599 unsigned ldrOpc, strOpc, extendOpc;
5601 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
5603 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
5604 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
5605 extendOpc = isThumb2 ? ARM::t2SXTB : ARM::SXTB;
5608 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
5609 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
5610 extendOpc = isThumb2 ? ARM::t2SXTH : ARM::SXTH;
5613 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
5614 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
5619 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5620 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5621 MF->insert(It, loopMBB);
5622 MF->insert(It, exitMBB);
5624 // Transfer the remainder of BB and its successor edges to exitMBB.
5625 exitMBB->splice(exitMBB->begin(), BB,
5626 llvm::next(MachineBasicBlock::iterator(MI)),
5628 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5630 const TargetRegisterClass *TRC = isThumb2 ?
5631 (const TargetRegisterClass*)&ARM::rGPRRegClass :
5632 (const TargetRegisterClass*)&ARM::GPRRegClass;
5633 unsigned scratch = MRI.createVirtualRegister(TRC);
5634 unsigned scratch2 = MRI.createVirtualRegister(TRC);
5638 // fallthrough --> loopMBB
5639 BB->addSuccessor(loopMBB);
5643 // (sign extend dest, if required)
5645 // cmov.cond scratch2, incr, dest
5646 // strex scratch, scratch2, ptr
5649 // fallthrough --> exitMBB
5651 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr);
5652 if (ldrOpc == ARM::t2LDREX)
5654 AddDefaultPred(MIB);
5656 // Sign extend the value, if necessary.
5657 if (signExtend && extendOpc) {
5658 oldval = MRI.createVirtualRegister(&ARM::GPRRegClass);
5659 AddDefaultPred(BuildMI(BB, dl, TII->get(extendOpc), oldval)
5664 // Build compare and cmov instructions.
5665 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
5666 .addReg(oldval).addReg(incr));
5667 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr), scratch2)
5668 .addReg(incr).addReg(oldval).addImm(Cond).addReg(ARM::CPSR);
5670 MIB = BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2).addReg(ptr);
5671 if (strOpc == ARM::t2STREX)
5673 AddDefaultPred(MIB);
5674 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5675 .addReg(scratch).addImm(0));
5676 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5677 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5679 BB->addSuccessor(loopMBB);
5680 BB->addSuccessor(exitMBB);
5686 MI->eraseFromParent(); // The instruction is gone now.
5692 ARMTargetLowering::EmitAtomicBinary64(MachineInstr *MI, MachineBasicBlock *BB,
5693 unsigned Op1, unsigned Op2,
5694 bool NeedsCarry, bool IsCmpxchg) const {
5695 // This also handles ATOMIC_SWAP, indicated by Op1==0.
5696 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5698 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5699 MachineFunction *MF = BB->getParent();
5700 MachineFunction::iterator It = BB;
5703 unsigned destlo = MI->getOperand(0).getReg();
5704 unsigned desthi = MI->getOperand(1).getReg();
5705 unsigned ptr = MI->getOperand(2).getReg();
5706 unsigned vallo = MI->getOperand(3).getReg();
5707 unsigned valhi = MI->getOperand(4).getReg();
5708 DebugLoc dl = MI->getDebugLoc();
5709 bool isThumb2 = Subtarget->isThumb2();
5711 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
5713 MRI.constrainRegClass(destlo, &ARM::rGPRRegClass);
5714 MRI.constrainRegClass(desthi, &ARM::rGPRRegClass);
5715 MRI.constrainRegClass(ptr, &ARM::rGPRRegClass);
5718 unsigned ldrOpc = isThumb2 ? ARM::t2LDREXD : ARM::LDREXD;
5719 unsigned strOpc = isThumb2 ? ARM::t2STREXD : ARM::STREXD;
5721 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5722 MachineBasicBlock *contBB = 0, *cont2BB = 0;
5724 contBB = MF->CreateMachineBasicBlock(LLVM_BB);
5725 cont2BB = MF->CreateMachineBasicBlock(LLVM_BB);
5727 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5728 MF->insert(It, loopMBB);
5730 MF->insert(It, contBB);
5731 MF->insert(It, cont2BB);
5733 MF->insert(It, exitMBB);
5735 // Transfer the remainder of BB and its successor edges to exitMBB.
5736 exitMBB->splice(exitMBB->begin(), BB,
5737 llvm::next(MachineBasicBlock::iterator(MI)),
5739 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5741 const TargetRegisterClass *TRC = isThumb2 ?
5742 (const TargetRegisterClass*)&ARM::tGPRRegClass :
5743 (const TargetRegisterClass*)&ARM::GPRRegClass;
5744 unsigned storesuccess = MRI.createVirtualRegister(TRC);
5748 // fallthrough --> loopMBB
5749 BB->addSuccessor(loopMBB);
5752 // ldrexd r2, r3, ptr
5753 // <binopa> r0, r2, incr
5754 // <binopb> r1, r3, incr
5755 // strexd storesuccess, r0, r1, ptr
5756 // cmp storesuccess, #0
5758 // fallthrough --> exitMBB
5760 // Note that the registers are explicitly specified because there is not any
5761 // way to force the register allocator to allocate a register pair.
5763 // FIXME: The hardcoded registers are not necessary for Thumb2, but we
5764 // need to properly enforce the restriction that the two output registers
5765 // for ldrexd must be different.
5768 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc))
5769 .addReg(ARM::R2, RegState::Define)
5770 .addReg(ARM::R3, RegState::Define).addReg(ptr));
5771 // Copy r2/r3 into dest. (This copy will normally be coalesced.)
5772 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), destlo).addReg(ARM::R2);
5773 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), desthi).addReg(ARM::R3);
5777 for (unsigned i = 0; i < 2; i++) {
5778 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr :
5780 .addReg(i == 0 ? destlo : desthi)
5781 .addReg(i == 0 ? vallo : valhi));
5782 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5783 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5784 BB->addSuccessor(exitMBB);
5785 BB->addSuccessor(i == 0 ? contBB : cont2BB);
5786 BB = (i == 0 ? contBB : cont2BB);
5789 // Copy to physregs for strexd
5790 unsigned setlo = MI->getOperand(5).getReg();
5791 unsigned sethi = MI->getOperand(6).getReg();
5792 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R0).addReg(setlo);
5793 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R1).addReg(sethi);
5795 // Perform binary operation
5796 AddDefaultPred(BuildMI(BB, dl, TII->get(Op1), ARM::R0)
5797 .addReg(destlo).addReg(vallo))
5798 .addReg(NeedsCarry ? ARM::CPSR : 0, getDefRegState(NeedsCarry));
5799 AddDefaultPred(BuildMI(BB, dl, TII->get(Op2), ARM::R1)
5800 .addReg(desthi).addReg(valhi)).addReg(0);
5802 // Copy to physregs for strexd
5803 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R0).addReg(vallo);
5804 BuildMI(BB, dl, TII->get(TargetOpcode::COPY), ARM::R1).addReg(valhi);
5808 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), storesuccess)
5809 .addReg(ARM::R0).addReg(ARM::R1).addReg(ptr));
5811 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5812 .addReg(storesuccess).addImm(0));
5813 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5814 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5816 BB->addSuccessor(loopMBB);
5817 BB->addSuccessor(exitMBB);
5823 MI->eraseFromParent(); // The instruction is gone now.
5828 /// SetupEntryBlockForSjLj - Insert code into the entry block that creates and
5829 /// registers the function context.
5830 void ARMTargetLowering::
5831 SetupEntryBlockForSjLj(MachineInstr *MI, MachineBasicBlock *MBB,
5832 MachineBasicBlock *DispatchBB, int FI) const {
5833 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5834 DebugLoc dl = MI->getDebugLoc();
5835 MachineFunction *MF = MBB->getParent();
5836 MachineRegisterInfo *MRI = &MF->getRegInfo();
5837 MachineConstantPool *MCP = MF->getConstantPool();
5838 ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>();
5839 const Function *F = MF->getFunction();
5841 bool isThumb = Subtarget->isThumb();
5842 bool isThumb2 = Subtarget->isThumb2();
5844 unsigned PCLabelId = AFI->createPICLabelUId();
5845 unsigned PCAdj = (isThumb || isThumb2) ? 4 : 8;
5846 ARMConstantPoolValue *CPV =
5847 ARMConstantPoolMBB::Create(F->getContext(), DispatchBB, PCLabelId, PCAdj);
5848 unsigned CPI = MCP->getConstantPoolIndex(CPV, 4);
5850 const TargetRegisterClass *TRC = isThumb ?
5851 (const TargetRegisterClass*)&ARM::tGPRRegClass :
5852 (const TargetRegisterClass*)&ARM::GPRRegClass;
5854 // Grab constant pool and fixed stack memory operands.
5855 MachineMemOperand *CPMMO =
5856 MF->getMachineMemOperand(MachinePointerInfo::getConstantPool(),
5857 MachineMemOperand::MOLoad, 4, 4);
5859 MachineMemOperand *FIMMOSt =
5860 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
5861 MachineMemOperand::MOStore, 4, 4);
5863 // Load the address of the dispatch MBB into the jump buffer.
5865 // Incoming value: jbuf
5866 // ldr.n r5, LCPI1_1
5869 // str r5, [$jbuf, #+4] ; &jbuf[1]
5870 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
5871 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2LDRpci), NewVReg1)
5872 .addConstantPoolIndex(CPI)
5873 .addMemOperand(CPMMO));
5874 // Set the low bit because of thumb mode.
5875 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
5877 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2ORRri), NewVReg2)
5878 .addReg(NewVReg1, RegState::Kill)
5880 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
5881 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg3)
5882 .addReg(NewVReg2, RegState::Kill)
5884 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2STRi12))
5885 .addReg(NewVReg3, RegState::Kill)
5887 .addImm(36) // &jbuf[1] :: pc
5888 .addMemOperand(FIMMOSt));
5889 } else if (isThumb) {
5890 // Incoming value: jbuf
5891 // ldr.n r1, LCPI1_4
5895 // add r2, $jbuf, #+4 ; &jbuf[1]
5897 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
5898 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tLDRpci), NewVReg1)
5899 .addConstantPoolIndex(CPI)
5900 .addMemOperand(CPMMO));
5901 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
5902 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg2)
5903 .addReg(NewVReg1, RegState::Kill)
5905 // Set the low bit because of thumb mode.
5906 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
5907 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tMOVi8), NewVReg3)
5908 .addReg(ARM::CPSR, RegState::Define)
5910 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
5911 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tORR), NewVReg4)
5912 .addReg(ARM::CPSR, RegState::Define)
5913 .addReg(NewVReg2, RegState::Kill)
5914 .addReg(NewVReg3, RegState::Kill));
5915 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
5916 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tADDrSPi), NewVReg5)
5918 .addImm(36)); // &jbuf[1] :: pc
5919 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tSTRi))
5920 .addReg(NewVReg4, RegState::Kill)
5921 .addReg(NewVReg5, RegState::Kill)
5923 .addMemOperand(FIMMOSt));
5925 // Incoming value: jbuf
5928 // str r1, [$jbuf, #+4] ; &jbuf[1]
5929 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
5930 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::LDRi12), NewVReg1)
5931 .addConstantPoolIndex(CPI)
5933 .addMemOperand(CPMMO));
5934 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
5935 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::PICADD), NewVReg2)
5936 .addReg(NewVReg1, RegState::Kill)
5937 .addImm(PCLabelId));
5938 AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::STRi12))
5939 .addReg(NewVReg2, RegState::Kill)
5941 .addImm(36) // &jbuf[1] :: pc
5942 .addMemOperand(FIMMOSt));
5946 MachineBasicBlock *ARMTargetLowering::
5947 EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const {
5948 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5949 DebugLoc dl = MI->getDebugLoc();
5950 MachineFunction *MF = MBB->getParent();
5951 MachineRegisterInfo *MRI = &MF->getRegInfo();
5952 ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>();
5953 MachineFrameInfo *MFI = MF->getFrameInfo();
5954 int FI = MFI->getFunctionContextIndex();
5956 const TargetRegisterClass *TRC = Subtarget->isThumb() ?
5957 (const TargetRegisterClass*)&ARM::tGPRRegClass :
5958 (const TargetRegisterClass*)&ARM::GPRnopcRegClass;
5960 // Get a mapping of the call site numbers to all of the landing pads they're
5962 DenseMap<unsigned, SmallVector<MachineBasicBlock*, 2> > CallSiteNumToLPad;
5963 unsigned MaxCSNum = 0;
5964 MachineModuleInfo &MMI = MF->getMMI();
5965 for (MachineFunction::iterator BB = MF->begin(), E = MF->end(); BB != E;
5967 if (!BB->isLandingPad()) continue;
5969 // FIXME: We should assert that the EH_LABEL is the first MI in the landing
5971 for (MachineBasicBlock::iterator
5972 II = BB->begin(), IE = BB->end(); II != IE; ++II) {
5973 if (!II->isEHLabel()) continue;
5975 MCSymbol *Sym = II->getOperand(0).getMCSymbol();
5976 if (!MMI.hasCallSiteLandingPad(Sym)) continue;
5978 SmallVectorImpl<unsigned> &CallSiteIdxs = MMI.getCallSiteLandingPad(Sym);
5979 for (SmallVectorImpl<unsigned>::iterator
5980 CSI = CallSiteIdxs.begin(), CSE = CallSiteIdxs.end();
5981 CSI != CSE; ++CSI) {
5982 CallSiteNumToLPad[*CSI].push_back(BB);
5983 MaxCSNum = std::max(MaxCSNum, *CSI);
5989 // Get an ordered list of the machine basic blocks for the jump table.
5990 std::vector<MachineBasicBlock*> LPadList;
5991 SmallPtrSet<MachineBasicBlock*, 64> InvokeBBs;
5992 LPadList.reserve(CallSiteNumToLPad.size());
5993 for (unsigned I = 1; I <= MaxCSNum; ++I) {
5994 SmallVectorImpl<MachineBasicBlock*> &MBBList = CallSiteNumToLPad[I];
5995 for (SmallVectorImpl<MachineBasicBlock*>::iterator
5996 II = MBBList.begin(), IE = MBBList.end(); II != IE; ++II) {
5997 LPadList.push_back(*II);
5998 InvokeBBs.insert((*II)->pred_begin(), (*II)->pred_end());
6002 assert(!LPadList.empty() &&
6003 "No landing pad destinations for the dispatch jump table!");
6005 // Create the jump table and associated information.
6006 MachineJumpTableInfo *JTI =
6007 MF->getOrCreateJumpTableInfo(MachineJumpTableInfo::EK_Inline);
6008 unsigned MJTI = JTI->createJumpTableIndex(LPadList);
6009 unsigned UId = AFI->createJumpTableUId();
6011 // Create the MBBs for the dispatch code.
6013 // Shove the dispatch's address into the return slot in the function context.
6014 MachineBasicBlock *DispatchBB = MF->CreateMachineBasicBlock();
6015 DispatchBB->setIsLandingPad();
6017 MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock();
6018 BuildMI(TrapBB, dl, TII->get(Subtarget->isThumb() ? ARM::tTRAP : ARM::TRAP));
6019 DispatchBB->addSuccessor(TrapBB);
6021 MachineBasicBlock *DispContBB = MF->CreateMachineBasicBlock();
6022 DispatchBB->addSuccessor(DispContBB);
6025 MF->insert(MF->end(), DispatchBB);
6026 MF->insert(MF->end(), DispContBB);
6027 MF->insert(MF->end(), TrapBB);
6029 // Insert code into the entry block that creates and registers the function
6031 SetupEntryBlockForSjLj(MI, MBB, DispatchBB, FI);
6033 MachineMemOperand *FIMMOLd =
6034 MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
6035 MachineMemOperand::MOLoad |
6036 MachineMemOperand::MOVolatile, 4, 4);
6038 if (AFI->isThumb1OnlyFunction())
6039 BuildMI(DispatchBB, dl, TII->get(ARM::tInt_eh_sjlj_dispatchsetup));
6040 else if (!Subtarget->hasVFP2())
6041 BuildMI(DispatchBB, dl, TII->get(ARM::Int_eh_sjlj_dispatchsetup_nofp));
6043 BuildMI(DispatchBB, dl, TII->get(ARM::Int_eh_sjlj_dispatchsetup));
6045 unsigned NumLPads = LPadList.size();
6046 if (Subtarget->isThumb2()) {
6047 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6048 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2LDRi12), NewVReg1)
6051 .addMemOperand(FIMMOLd));
6053 if (NumLPads < 256) {
6054 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPri))
6056 .addImm(LPadList.size()));
6058 unsigned VReg1 = MRI->createVirtualRegister(TRC);
6059 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVi16), VReg1)
6060 .addImm(NumLPads & 0xFFFF));
6062 unsigned VReg2 = VReg1;
6063 if ((NumLPads & 0xFFFF0000) != 0) {
6064 VReg2 = MRI->createVirtualRegister(TRC);
6065 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVTi16), VReg2)
6067 .addImm(NumLPads >> 16));
6070 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPrr))
6075 BuildMI(DispatchBB, dl, TII->get(ARM::t2Bcc))
6080 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6081 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::t2LEApcrelJT),NewVReg3)
6082 .addJumpTableIndex(MJTI)
6085 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
6088 BuildMI(DispContBB, dl, TII->get(ARM::t2ADDrs), NewVReg4)
6089 .addReg(NewVReg3, RegState::Kill)
6091 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))));
6093 BuildMI(DispContBB, dl, TII->get(ARM::t2BR_JT))
6094 .addReg(NewVReg4, RegState::Kill)
6096 .addJumpTableIndex(MJTI)
6098 } else if (Subtarget->isThumb()) {
6099 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6100 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRspi), NewVReg1)
6103 .addMemOperand(FIMMOLd));
6105 if (NumLPads < 256) {
6106 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPi8))
6110 MachineConstantPool *ConstantPool = MF->getConstantPool();
6111 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
6112 const Constant *C = ConstantInt::get(Int32Ty, NumLPads);
6114 // MachineConstantPool wants an explicit alignment.
6115 unsigned Align = getDataLayout()->getPrefTypeAlignment(Int32Ty);
6117 Align = getDataLayout()->getTypeAllocSize(C->getType());
6118 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
6120 unsigned VReg1 = MRI->createVirtualRegister(TRC);
6121 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRpci))
6122 .addReg(VReg1, RegState::Define)
6123 .addConstantPoolIndex(Idx));
6124 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPr))
6129 BuildMI(DispatchBB, dl, TII->get(ARM::tBcc))
6134 unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6135 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLSLri), NewVReg2)
6136 .addReg(ARM::CPSR, RegState::Define)
6140 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6141 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLEApcrelJT), NewVReg3)
6142 .addJumpTableIndex(MJTI)
6145 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
6146 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg4)
6147 .addReg(ARM::CPSR, RegState::Define)
6148 .addReg(NewVReg2, RegState::Kill)
6151 MachineMemOperand *JTMMOLd =
6152 MF->getMachineMemOperand(MachinePointerInfo::getJumpTable(),
6153 MachineMemOperand::MOLoad, 4, 4);
6155 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
6156 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLDRi), NewVReg5)
6157 .addReg(NewVReg4, RegState::Kill)
6159 .addMemOperand(JTMMOLd));
6161 unsigned NewVReg6 = MRI->createVirtualRegister(TRC);
6162 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg6)
6163 .addReg(ARM::CPSR, RegState::Define)
6164 .addReg(NewVReg5, RegState::Kill)
6167 BuildMI(DispContBB, dl, TII->get(ARM::tBR_JTr))
6168 .addReg(NewVReg6, RegState::Kill)
6169 .addJumpTableIndex(MJTI)
6172 unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6173 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRi12), NewVReg1)
6176 .addMemOperand(FIMMOLd));
6178 if (NumLPads < 256) {
6179 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPri))
6182 } else if (Subtarget->hasV6T2Ops() && isUInt<16>(NumLPads)) {
6183 unsigned VReg1 = MRI->createVirtualRegister(TRC);
6184 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVi16), VReg1)
6185 .addImm(NumLPads & 0xFFFF));
6187 unsigned VReg2 = VReg1;
6188 if ((NumLPads & 0xFFFF0000) != 0) {
6189 VReg2 = MRI->createVirtualRegister(TRC);
6190 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVTi16), VReg2)
6192 .addImm(NumLPads >> 16));
6195 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
6199 MachineConstantPool *ConstantPool = MF->getConstantPool();
6200 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
6201 const Constant *C = ConstantInt::get(Int32Ty, NumLPads);
6203 // MachineConstantPool wants an explicit alignment.
6204 unsigned Align = getDataLayout()->getPrefTypeAlignment(Int32Ty);
6206 Align = getDataLayout()->getTypeAllocSize(C->getType());
6207 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
6209 unsigned VReg1 = MRI->createVirtualRegister(TRC);
6210 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRcp))
6211 .addReg(VReg1, RegState::Define)
6212 .addConstantPoolIndex(Idx)
6214 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
6216 .addReg(VReg1, RegState::Kill));
6219 BuildMI(DispatchBB, dl, TII->get(ARM::Bcc))
6224 unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6226 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::MOVsi), NewVReg3)
6228 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))));
6229 unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
6230 AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::LEApcrelJT), NewVReg4)
6231 .addJumpTableIndex(MJTI)
6234 MachineMemOperand *JTMMOLd =
6235 MF->getMachineMemOperand(MachinePointerInfo::getJumpTable(),
6236 MachineMemOperand::MOLoad, 4, 4);
6237 unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
6239 BuildMI(DispContBB, dl, TII->get(ARM::LDRrs), NewVReg5)
6240 .addReg(NewVReg3, RegState::Kill)
6243 .addMemOperand(JTMMOLd));
6245 BuildMI(DispContBB, dl, TII->get(ARM::BR_JTadd))
6246 .addReg(NewVReg5, RegState::Kill)
6248 .addJumpTableIndex(MJTI)
6252 // Add the jump table entries as successors to the MBB.
6253 SmallPtrSet<MachineBasicBlock*, 8> SeenMBBs;
6254 for (std::vector<MachineBasicBlock*>::iterator
6255 I = LPadList.begin(), E = LPadList.end(); I != E; ++I) {
6256 MachineBasicBlock *CurMBB = *I;
6257 if (SeenMBBs.insert(CurMBB))
6258 DispContBB->addSuccessor(CurMBB);
6261 // N.B. the order the invoke BBs are processed in doesn't matter here.
6262 const ARMBaseInstrInfo *AII = static_cast<const ARMBaseInstrInfo*>(TII);
6263 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
6264 const uint16_t *SavedRegs = RI.getCalleeSavedRegs(MF);
6265 SmallVector<MachineBasicBlock*, 64> MBBLPads;
6266 for (SmallPtrSet<MachineBasicBlock*, 64>::iterator
6267 I = InvokeBBs.begin(), E = InvokeBBs.end(); I != E; ++I) {
6268 MachineBasicBlock *BB = *I;
6270 // Remove the landing pad successor from the invoke block and replace it
6271 // with the new dispatch block.
6272 SmallVector<MachineBasicBlock*, 4> Successors(BB->succ_begin(),
6274 while (!Successors.empty()) {
6275 MachineBasicBlock *SMBB = Successors.pop_back_val();
6276 if (SMBB->isLandingPad()) {
6277 BB->removeSuccessor(SMBB);
6278 MBBLPads.push_back(SMBB);
6282 BB->addSuccessor(DispatchBB);
6284 // Find the invoke call and mark all of the callee-saved registers as
6285 // 'implicit defined' so that they're spilled. This prevents code from
6286 // moving instructions to before the EH block, where they will never be
6288 for (MachineBasicBlock::reverse_iterator
6289 II = BB->rbegin(), IE = BB->rend(); II != IE; ++II) {
6290 if (!II->isCall()) continue;
6292 DenseMap<unsigned, bool> DefRegs;
6293 for (MachineInstr::mop_iterator
6294 OI = II->operands_begin(), OE = II->operands_end();
6296 if (!OI->isReg()) continue;
6297 DefRegs[OI->getReg()] = true;
6300 MachineInstrBuilder MIB(&*II);
6302 for (unsigned i = 0; SavedRegs[i] != 0; ++i) {
6303 unsigned Reg = SavedRegs[i];
6304 if (Subtarget->isThumb2() &&
6305 !ARM::tGPRRegClass.contains(Reg) &&
6306 !ARM::hGPRRegClass.contains(Reg))
6308 if (Subtarget->isThumb1Only() && !ARM::tGPRRegClass.contains(Reg))
6310 if (!Subtarget->isThumb() && !ARM::GPRRegClass.contains(Reg))
6313 MIB.addReg(Reg, RegState::ImplicitDefine | RegState::Dead);
6320 // Mark all former landing pads as non-landing pads. The dispatch is the only
6322 for (SmallVectorImpl<MachineBasicBlock*>::iterator
6323 I = MBBLPads.begin(), E = MBBLPads.end(); I != E; ++I)
6324 (*I)->setIsLandingPad(false);
6326 // The instruction is gone now.
6327 MI->eraseFromParent();
6333 MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
6334 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
6335 E = MBB->succ_end(); I != E; ++I)
6338 llvm_unreachable("Expecting a BB with two successors!");
6341 MachineBasicBlock *ARMTargetLowering::
6342 EmitStructByval(MachineInstr *MI, MachineBasicBlock *BB) const {
6343 // This pseudo instruction has 3 operands: dst, src, size
6344 // We expand it to a loop if size > Subtarget->getMaxInlineSizeThreshold().
6345 // Otherwise, we will generate unrolled scalar copies.
6346 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6347 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6348 MachineFunction::iterator It = BB;
6351 unsigned dest = MI->getOperand(0).getReg();
6352 unsigned src = MI->getOperand(1).getReg();
6353 unsigned SizeVal = MI->getOperand(2).getImm();
6354 unsigned Align = MI->getOperand(3).getImm();
6355 DebugLoc dl = MI->getDebugLoc();
6357 bool isThumb2 = Subtarget->isThumb2();
6358 MachineFunction *MF = BB->getParent();
6359 MachineRegisterInfo &MRI = MF->getRegInfo();
6360 unsigned ldrOpc, strOpc, UnitSize = 0;
6362 const TargetRegisterClass *TRC = isThumb2 ?
6363 (const TargetRegisterClass*)&ARM::tGPRRegClass :
6364 (const TargetRegisterClass*)&ARM::GPRRegClass;
6365 const TargetRegisterClass *TRC_Vec = 0;
6368 ldrOpc = isThumb2 ? ARM::t2LDRB_POST : ARM::LDRB_POST_IMM;
6369 strOpc = isThumb2 ? ARM::t2STRB_POST : ARM::STRB_POST_IMM;
6371 } else if (Align & 2) {
6372 ldrOpc = isThumb2 ? ARM::t2LDRH_POST : ARM::LDRH_POST;
6373 strOpc = isThumb2 ? ARM::t2STRH_POST : ARM::STRH_POST;
6376 // Check whether we can use NEON instructions.
6377 if (!MF->getFunction()->getFnAttributes().
6378 hasAttribute(Attributes::NoImplicitFloat) &&
6379 Subtarget->hasNEON()) {
6380 if ((Align % 16 == 0) && SizeVal >= 16) {
6381 ldrOpc = ARM::VLD1q32wb_fixed;
6382 strOpc = ARM::VST1q32wb_fixed;
6384 TRC_Vec = (const TargetRegisterClass*)&ARM::DPairRegClass;
6386 else if ((Align % 8 == 0) && SizeVal >= 8) {
6387 ldrOpc = ARM::VLD1d32wb_fixed;
6388 strOpc = ARM::VST1d32wb_fixed;
6390 TRC_Vec = (const TargetRegisterClass*)&ARM::DPRRegClass;
6393 // Can't use NEON instructions.
6394 if (UnitSize == 0) {
6395 ldrOpc = isThumb2 ? ARM::t2LDR_POST : ARM::LDR_POST_IMM;
6396 strOpc = isThumb2 ? ARM::t2STR_POST : ARM::STR_POST_IMM;
6401 unsigned BytesLeft = SizeVal % UnitSize;
6402 unsigned LoopSize = SizeVal - BytesLeft;
6404 if (SizeVal <= Subtarget->getMaxInlineSizeThreshold()) {
6405 // Use LDR and STR to copy.
6406 // [scratch, srcOut] = LDR_POST(srcIn, UnitSize)
6407 // [destOut] = STR_POST(scratch, destIn, UnitSize)
6408 unsigned srcIn = src;
6409 unsigned destIn = dest;
6410 for (unsigned i = 0; i < LoopSize; i+=UnitSize) {
6411 unsigned scratch = MRI.createVirtualRegister(UnitSize >= 8 ? TRC_Vec:TRC);
6412 unsigned srcOut = MRI.createVirtualRegister(TRC);
6413 unsigned destOut = MRI.createVirtualRegister(TRC);
6414 if (UnitSize >= 8) {
6415 AddDefaultPred(BuildMI(*BB, MI, dl,
6416 TII->get(ldrOpc), scratch)
6417 .addReg(srcOut, RegState::Define).addReg(srcIn).addImm(0));
6419 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(strOpc), destOut)
6420 .addReg(destIn).addImm(0).addReg(scratch));
6421 } else if (isThumb2) {
6422 AddDefaultPred(BuildMI(*BB, MI, dl,
6423 TII->get(ldrOpc), scratch)
6424 .addReg(srcOut, RegState::Define).addReg(srcIn).addImm(UnitSize));
6426 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(strOpc), destOut)
6427 .addReg(scratch).addReg(destIn)
6430 AddDefaultPred(BuildMI(*BB, MI, dl,
6431 TII->get(ldrOpc), scratch)
6432 .addReg(srcOut, RegState::Define).addReg(srcIn).addReg(0)
6435 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(strOpc), destOut)
6436 .addReg(scratch).addReg(destIn)
6437 .addReg(0).addImm(UnitSize));
6443 // Handle the leftover bytes with LDRB and STRB.
6444 // [scratch, srcOut] = LDRB_POST(srcIn, 1)
6445 // [destOut] = STRB_POST(scratch, destIn, 1)
6446 ldrOpc = isThumb2 ? ARM::t2LDRB_POST : ARM::LDRB_POST_IMM;
6447 strOpc = isThumb2 ? ARM::t2STRB_POST : ARM::STRB_POST_IMM;
6448 for (unsigned i = 0; i < BytesLeft; i++) {
6449 unsigned scratch = MRI.createVirtualRegister(TRC);
6450 unsigned srcOut = MRI.createVirtualRegister(TRC);
6451 unsigned destOut = MRI.createVirtualRegister(TRC);
6453 AddDefaultPred(BuildMI(*BB, MI, dl,
6454 TII->get(ldrOpc),scratch)
6455 .addReg(srcOut, RegState::Define).addReg(srcIn).addImm(1));
6457 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(strOpc), destOut)
6458 .addReg(scratch).addReg(destIn)
6459 .addReg(0).addImm(1));
6461 AddDefaultPred(BuildMI(*BB, MI, dl,
6462 TII->get(ldrOpc),scratch)
6463 .addReg(srcOut, RegState::Define).addReg(srcIn)
6464 .addReg(0).addImm(1));
6466 AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(strOpc), destOut)
6467 .addReg(scratch).addReg(destIn)
6468 .addReg(0).addImm(1));
6473 MI->eraseFromParent(); // The instruction is gone now.
6477 // Expand the pseudo op to a loop.
6480 // movw varEnd, # --> with thumb2
6482 // ldrcp varEnd, idx --> without thumb2
6483 // fallthrough --> loopMBB
6485 // PHI varPhi, varEnd, varLoop
6486 // PHI srcPhi, src, srcLoop
6487 // PHI destPhi, dst, destLoop
6488 // [scratch, srcLoop] = LDR_POST(srcPhi, UnitSize)
6489 // [destLoop] = STR_POST(scratch, destPhi, UnitSize)
6490 // subs varLoop, varPhi, #UnitSize
6492 // fallthrough --> exitMBB
6494 // epilogue to handle left-over bytes
6495 // [scratch, srcOut] = LDRB_POST(srcLoop, 1)
6496 // [destOut] = STRB_POST(scratch, destLoop, 1)
6497 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
6498 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
6499 MF->insert(It, loopMBB);
6500 MF->insert(It, exitMBB);
6502 // Transfer the remainder of BB and its successor edges to exitMBB.
6503 exitMBB->splice(exitMBB->begin(), BB,
6504 llvm::next(MachineBasicBlock::iterator(MI)),
6506 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6508 // Load an immediate to varEnd.
6509 unsigned varEnd = MRI.createVirtualRegister(TRC);
6511 unsigned VReg1 = varEnd;
6512 if ((LoopSize & 0xFFFF0000) != 0)
6513 VReg1 = MRI.createVirtualRegister(TRC);
6514 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2MOVi16), VReg1)
6515 .addImm(LoopSize & 0xFFFF));
6517 if ((LoopSize & 0xFFFF0000) != 0)
6518 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2MOVTi16), varEnd)
6520 .addImm(LoopSize >> 16));
6522 MachineConstantPool *ConstantPool = MF->getConstantPool();
6523 Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
6524 const Constant *C = ConstantInt::get(Int32Ty, LoopSize);
6526 // MachineConstantPool wants an explicit alignment.
6527 unsigned Align = getDataLayout()->getPrefTypeAlignment(Int32Ty);
6529 Align = getDataLayout()->getTypeAllocSize(C->getType());
6530 unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
6532 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::LDRcp))
6533 .addReg(varEnd, RegState::Define)
6534 .addConstantPoolIndex(Idx)
6537 BB->addSuccessor(loopMBB);
6539 // Generate the loop body:
6540 // varPhi = PHI(varLoop, varEnd)
6541 // srcPhi = PHI(srcLoop, src)
6542 // destPhi = PHI(destLoop, dst)
6543 MachineBasicBlock *entryBB = BB;
6545 unsigned varLoop = MRI.createVirtualRegister(TRC);
6546 unsigned varPhi = MRI.createVirtualRegister(TRC);
6547 unsigned srcLoop = MRI.createVirtualRegister(TRC);
6548 unsigned srcPhi = MRI.createVirtualRegister(TRC);
6549 unsigned destLoop = MRI.createVirtualRegister(TRC);
6550 unsigned destPhi = MRI.createVirtualRegister(TRC);
6552 BuildMI(*BB, BB->begin(), dl, TII->get(ARM::PHI), varPhi)
6553 .addReg(varLoop).addMBB(loopMBB)
6554 .addReg(varEnd).addMBB(entryBB);
6555 BuildMI(BB, dl, TII->get(ARM::PHI), srcPhi)
6556 .addReg(srcLoop).addMBB(loopMBB)
6557 .addReg(src).addMBB(entryBB);
6558 BuildMI(BB, dl, TII->get(ARM::PHI), destPhi)
6559 .addReg(destLoop).addMBB(loopMBB)
6560 .addReg(dest).addMBB(entryBB);
6562 // [scratch, srcLoop] = LDR_POST(srcPhi, UnitSize)
6563 // [destLoop] = STR_POST(scratch, destPhi, UnitSiz)
6564 unsigned scratch = MRI.createVirtualRegister(UnitSize >= 8 ? TRC_Vec:TRC);
6565 if (UnitSize >= 8) {
6566 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), scratch)
6567 .addReg(srcLoop, RegState::Define).addReg(srcPhi).addImm(0));
6569 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), destLoop)
6570 .addReg(destPhi).addImm(0).addReg(scratch));
6571 } else if (isThumb2) {
6572 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), scratch)
6573 .addReg(srcLoop, RegState::Define).addReg(srcPhi).addImm(UnitSize));
6575 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), destLoop)
6576 .addReg(scratch).addReg(destPhi)
6579 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), scratch)
6580 .addReg(srcLoop, RegState::Define).addReg(srcPhi).addReg(0)
6583 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), destLoop)
6584 .addReg(scratch).addReg(destPhi)
6585 .addReg(0).addImm(UnitSize));
6588 // Decrement loop variable by UnitSize.
6589 MachineInstrBuilder MIB = BuildMI(BB, dl,
6590 TII->get(isThumb2 ? ARM::t2SUBri : ARM::SUBri), varLoop);
6591 AddDefaultCC(AddDefaultPred(MIB.addReg(varPhi).addImm(UnitSize)));
6592 MIB->getOperand(5).setReg(ARM::CPSR);
6593 MIB->getOperand(5).setIsDef(true);
6595 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
6596 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
6598 // loopMBB can loop back to loopMBB or fall through to exitMBB.
6599 BB->addSuccessor(loopMBB);
6600 BB->addSuccessor(exitMBB);
6602 // Add epilogue to handle BytesLeft.
6604 MachineInstr *StartOfExit = exitMBB->begin();
6605 ldrOpc = isThumb2 ? ARM::t2LDRB_POST : ARM::LDRB_POST_IMM;
6606 strOpc = isThumb2 ? ARM::t2STRB_POST : ARM::STRB_POST_IMM;
6608 // [scratch, srcOut] = LDRB_POST(srcLoop, 1)
6609 // [destOut] = STRB_POST(scratch, destLoop, 1)
6610 unsigned srcIn = srcLoop;
6611 unsigned destIn = destLoop;
6612 for (unsigned i = 0; i < BytesLeft; i++) {
6613 unsigned scratch = MRI.createVirtualRegister(TRC);
6614 unsigned srcOut = MRI.createVirtualRegister(TRC);
6615 unsigned destOut = MRI.createVirtualRegister(TRC);
6617 AddDefaultPred(BuildMI(*BB, StartOfExit, dl,
6618 TII->get(ldrOpc),scratch)
6619 .addReg(srcOut, RegState::Define).addReg(srcIn).addImm(1));
6621 AddDefaultPred(BuildMI(*BB, StartOfExit, dl, TII->get(strOpc), destOut)
6622 .addReg(scratch).addReg(destIn)
6625 AddDefaultPred(BuildMI(*BB, StartOfExit, dl,
6626 TII->get(ldrOpc),scratch)
6627 .addReg(srcOut, RegState::Define).addReg(srcIn).addReg(0).addImm(1));
6629 AddDefaultPred(BuildMI(*BB, StartOfExit, dl, TII->get(strOpc), destOut)
6630 .addReg(scratch).addReg(destIn)
6631 .addReg(0).addImm(1));
6637 MI->eraseFromParent(); // The instruction is gone now.
6642 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
6643 MachineBasicBlock *BB) const {
6644 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6645 DebugLoc dl = MI->getDebugLoc();
6646 bool isThumb2 = Subtarget->isThumb2();
6647 switch (MI->getOpcode()) {
6650 llvm_unreachable("Unexpected instr type to insert");
6652 // The Thumb2 pre-indexed stores have the same MI operands, they just
6653 // define them differently in the .td files from the isel patterns, so
6654 // they need pseudos.
6655 case ARM::t2STR_preidx:
6656 MI->setDesc(TII->get(ARM::t2STR_PRE));
6658 case ARM::t2STRB_preidx:
6659 MI->setDesc(TII->get(ARM::t2STRB_PRE));
6661 case ARM::t2STRH_preidx:
6662 MI->setDesc(TII->get(ARM::t2STRH_PRE));
6665 case ARM::STRi_preidx:
6666 case ARM::STRBi_preidx: {
6667 unsigned NewOpc = MI->getOpcode() == ARM::STRi_preidx ?
6668 ARM::STR_PRE_IMM : ARM::STRB_PRE_IMM;
6669 // Decode the offset.
6670 unsigned Offset = MI->getOperand(4).getImm();
6671 bool isSub = ARM_AM::getAM2Op(Offset) == ARM_AM::sub;
6672 Offset = ARM_AM::getAM2Offset(Offset);
6676 MachineMemOperand *MMO = *MI->memoperands_begin();
6677 BuildMI(*BB, MI, dl, TII->get(NewOpc))
6678 .addOperand(MI->getOperand(0)) // Rn_wb
6679 .addOperand(MI->getOperand(1)) // Rt
6680 .addOperand(MI->getOperand(2)) // Rn
6681 .addImm(Offset) // offset (skip GPR==zero_reg)
6682 .addOperand(MI->getOperand(5)) // pred
6683 .addOperand(MI->getOperand(6))
6684 .addMemOperand(MMO);
6685 MI->eraseFromParent();
6688 case ARM::STRr_preidx:
6689 case ARM::STRBr_preidx:
6690 case ARM::STRH_preidx: {
6692 switch (MI->getOpcode()) {
6693 default: llvm_unreachable("unexpected opcode!");
6694 case ARM::STRr_preidx: NewOpc = ARM::STR_PRE_REG; break;
6695 case ARM::STRBr_preidx: NewOpc = ARM::STRB_PRE_REG; break;
6696 case ARM::STRH_preidx: NewOpc = ARM::STRH_PRE; break;
6698 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc));
6699 for (unsigned i = 0; i < MI->getNumOperands(); ++i)
6700 MIB.addOperand(MI->getOperand(i));
6701 MI->eraseFromParent();
6704 case ARM::ATOMIC_LOAD_ADD_I8:
6705 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
6706 case ARM::ATOMIC_LOAD_ADD_I16:
6707 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
6708 case ARM::ATOMIC_LOAD_ADD_I32:
6709 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
6711 case ARM::ATOMIC_LOAD_AND_I8:
6712 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
6713 case ARM::ATOMIC_LOAD_AND_I16:
6714 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
6715 case ARM::ATOMIC_LOAD_AND_I32:
6716 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
6718 case ARM::ATOMIC_LOAD_OR_I8:
6719 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
6720 case ARM::ATOMIC_LOAD_OR_I16:
6721 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
6722 case ARM::ATOMIC_LOAD_OR_I32:
6723 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
6725 case ARM::ATOMIC_LOAD_XOR_I8:
6726 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
6727 case ARM::ATOMIC_LOAD_XOR_I16:
6728 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
6729 case ARM::ATOMIC_LOAD_XOR_I32:
6730 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
6732 case ARM::ATOMIC_LOAD_NAND_I8:
6733 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
6734 case ARM::ATOMIC_LOAD_NAND_I16:
6735 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
6736 case ARM::ATOMIC_LOAD_NAND_I32:
6737 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
6739 case ARM::ATOMIC_LOAD_SUB_I8:
6740 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
6741 case ARM::ATOMIC_LOAD_SUB_I16:
6742 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
6743 case ARM::ATOMIC_LOAD_SUB_I32:
6744 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
6746 case ARM::ATOMIC_LOAD_MIN_I8:
6747 return EmitAtomicBinaryMinMax(MI, BB, 1, true, ARMCC::LT);
6748 case ARM::ATOMIC_LOAD_MIN_I16:
6749 return EmitAtomicBinaryMinMax(MI, BB, 2, true, ARMCC::LT);
6750 case ARM::ATOMIC_LOAD_MIN_I32:
6751 return EmitAtomicBinaryMinMax(MI, BB, 4, true, ARMCC::LT);
6753 case ARM::ATOMIC_LOAD_MAX_I8:
6754 return EmitAtomicBinaryMinMax(MI, BB, 1, true, ARMCC::GT);
6755 case ARM::ATOMIC_LOAD_MAX_I16:
6756 return EmitAtomicBinaryMinMax(MI, BB, 2, true, ARMCC::GT);
6757 case ARM::ATOMIC_LOAD_MAX_I32:
6758 return EmitAtomicBinaryMinMax(MI, BB, 4, true, ARMCC::GT);
6760 case ARM::ATOMIC_LOAD_UMIN_I8:
6761 return EmitAtomicBinaryMinMax(MI, BB, 1, false, ARMCC::LO);
6762 case ARM::ATOMIC_LOAD_UMIN_I16:
6763 return EmitAtomicBinaryMinMax(MI, BB, 2, false, ARMCC::LO);
6764 case ARM::ATOMIC_LOAD_UMIN_I32:
6765 return EmitAtomicBinaryMinMax(MI, BB, 4, false, ARMCC::LO);
6767 case ARM::ATOMIC_LOAD_UMAX_I8:
6768 return EmitAtomicBinaryMinMax(MI, BB, 1, false, ARMCC::HI);
6769 case ARM::ATOMIC_LOAD_UMAX_I16:
6770 return EmitAtomicBinaryMinMax(MI, BB, 2, false, ARMCC::HI);
6771 case ARM::ATOMIC_LOAD_UMAX_I32:
6772 return EmitAtomicBinaryMinMax(MI, BB, 4, false, ARMCC::HI);
6774 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0);
6775 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0);
6776 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0);
6778 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1);
6779 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
6780 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
6783 case ARM::ATOMADD6432:
6784 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr,
6785 isThumb2 ? ARM::t2ADCrr : ARM::ADCrr,
6786 /*NeedsCarry*/ true);
6787 case ARM::ATOMSUB6432:
6788 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr,
6789 isThumb2 ? ARM::t2SBCrr : ARM::SBCrr,
6790 /*NeedsCarry*/ true);
6791 case ARM::ATOMOR6432:
6792 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr,
6793 isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
6794 case ARM::ATOMXOR6432:
6795 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2EORrr : ARM::EORrr,
6796 isThumb2 ? ARM::t2EORrr : ARM::EORrr);
6797 case ARM::ATOMAND6432:
6798 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr,
6799 isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
6800 case ARM::ATOMSWAP6432:
6801 return EmitAtomicBinary64(MI, BB, 0, 0, false);
6802 case ARM::ATOMCMPXCHG6432:
6803 return EmitAtomicBinary64(MI, BB, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr,
6804 isThumb2 ? ARM::t2SBCrr : ARM::SBCrr,
6805 /*NeedsCarry*/ false, /*IsCmpxchg*/true);
6807 case ARM::tMOVCCr_pseudo: {
6808 // To "insert" a SELECT_CC instruction, we actually have to insert the
6809 // diamond control-flow pattern. The incoming instruction knows the
6810 // destination vreg to set, the condition code register to branch on, the
6811 // true/false values to select between, and a branch opcode to use.
6812 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6813 MachineFunction::iterator It = BB;
6819 // cmpTY ccX, r1, r2
6821 // fallthrough --> copy0MBB
6822 MachineBasicBlock *thisMBB = BB;
6823 MachineFunction *F = BB->getParent();
6824 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
6825 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
6826 F->insert(It, copy0MBB);
6827 F->insert(It, sinkMBB);
6829 // Transfer the remainder of BB and its successor edges to sinkMBB.
6830 sinkMBB->splice(sinkMBB->begin(), BB,
6831 llvm::next(MachineBasicBlock::iterator(MI)),
6833 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
6835 BB->addSuccessor(copy0MBB);
6836 BB->addSuccessor(sinkMBB);
6838 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
6839 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
6842 // %FalseValue = ...
6843 // # fallthrough to sinkMBB
6846 // Update machine-CFG edges
6847 BB->addSuccessor(sinkMBB);
6850 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
6853 BuildMI(*BB, BB->begin(), dl,
6854 TII->get(ARM::PHI), MI->getOperand(0).getReg())
6855 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
6856 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
6858 MI->eraseFromParent(); // The pseudo instruction is gone now.
6863 case ARM::BCCZi64: {
6864 // If there is an unconditional branch to the other successor, remove it.
6865 BB->erase(llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
6867 // Compare both parts that make up the double comparison separately for
6869 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
6871 unsigned LHS1 = MI->getOperand(1).getReg();
6872 unsigned LHS2 = MI->getOperand(2).getReg();
6874 AddDefaultPred(BuildMI(BB, dl,
6875 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
6876 .addReg(LHS1).addImm(0));
6877 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
6878 .addReg(LHS2).addImm(0)
6879 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
6881 unsigned RHS1 = MI->getOperand(3).getReg();
6882 unsigned RHS2 = MI->getOperand(4).getReg();
6883 AddDefaultPred(BuildMI(BB, dl,
6884 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
6885 .addReg(LHS1).addReg(RHS1));
6886 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
6887 .addReg(LHS2).addReg(RHS2)
6888 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
6891 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB();
6892 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
6893 if (MI->getOperand(0).getImm() == ARMCC::NE)
6894 std::swap(destMBB, exitMBB);
6896 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
6897 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
6899 AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2B)).addMBB(exitMBB));
6901 BuildMI(BB, dl, TII->get(ARM::B)) .addMBB(exitMBB);
6903 MI->eraseFromParent(); // The pseudo instruction is gone now.
6907 case ARM::Int_eh_sjlj_setjmp:
6908 case ARM::Int_eh_sjlj_setjmp_nofp:
6909 case ARM::tInt_eh_sjlj_setjmp:
6910 case ARM::t2Int_eh_sjlj_setjmp:
6911 case ARM::t2Int_eh_sjlj_setjmp_nofp:
6912 EmitSjLjDispatchBlock(MI, BB);
6917 // To insert an ABS instruction, we have to insert the
6918 // diamond control-flow pattern. The incoming instruction knows the
6919 // source vreg to test against 0, the destination vreg to set,
6920 // the condition code register to branch on, the
6921 // true/false values to select between, and a branch opcode to use.
6926 // BCC (branch to SinkBB if V0 >= 0)
6927 // RSBBB: V3 = RSBri V2, 0 (compute ABS if V2 < 0)
6928 // SinkBB: V1 = PHI(V2, V3)
6929 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6930 MachineFunction::iterator BBI = BB;
6932 MachineFunction *Fn = BB->getParent();
6933 MachineBasicBlock *RSBBB = Fn->CreateMachineBasicBlock(LLVM_BB);
6934 MachineBasicBlock *SinkBB = Fn->CreateMachineBasicBlock(LLVM_BB);
6935 Fn->insert(BBI, RSBBB);
6936 Fn->insert(BBI, SinkBB);
6938 unsigned int ABSSrcReg = MI->getOperand(1).getReg();
6939 unsigned int ABSDstReg = MI->getOperand(0).getReg();
6940 bool isThumb2 = Subtarget->isThumb2();
6941 MachineRegisterInfo &MRI = Fn->getRegInfo();
6942 // In Thumb mode S must not be specified if source register is the SP or
6943 // PC and if destination register is the SP, so restrict register class
6944 unsigned NewRsbDstReg = MRI.createVirtualRegister(isThumb2 ?
6945 (const TargetRegisterClass*)&ARM::rGPRRegClass :
6946 (const TargetRegisterClass*)&ARM::GPRRegClass);
6948 // Transfer the remainder of BB and its successor edges to sinkMBB.
6949 SinkBB->splice(SinkBB->begin(), BB,
6950 llvm::next(MachineBasicBlock::iterator(MI)),
6952 SinkBB->transferSuccessorsAndUpdatePHIs(BB);
6954 BB->addSuccessor(RSBBB);
6955 BB->addSuccessor(SinkBB);
6957 // fall through to SinkMBB
6958 RSBBB->addSuccessor(SinkBB);
6960 // insert a cmp at the end of BB
6961 AddDefaultPred(BuildMI(BB, dl,
6962 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
6963 .addReg(ABSSrcReg).addImm(0));
6965 // insert a bcc with opposite CC to ARMCC::MI at the end of BB
6967 TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)).addMBB(SinkBB)
6968 .addImm(ARMCC::getOppositeCondition(ARMCC::MI)).addReg(ARM::CPSR);
6970 // insert rsbri in RSBBB
6971 // Note: BCC and rsbri will be converted into predicated rsbmi
6972 // by if-conversion pass
6973 BuildMI(*RSBBB, RSBBB->begin(), dl,
6974 TII->get(isThumb2 ? ARM::t2RSBri : ARM::RSBri), NewRsbDstReg)
6975 .addReg(ABSSrcReg, RegState::Kill)
6976 .addImm(0).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
6978 // insert PHI in SinkBB,
6979 // reuse ABSDstReg to not change uses of ABS instruction
6980 BuildMI(*SinkBB, SinkBB->begin(), dl,
6981 TII->get(ARM::PHI), ABSDstReg)
6982 .addReg(NewRsbDstReg).addMBB(RSBBB)
6983 .addReg(ABSSrcReg).addMBB(BB);
6985 // remove ABS instruction
6986 MI->eraseFromParent();
6988 // return last added BB
6991 case ARM::COPY_STRUCT_BYVAL_I32:
6993 return EmitStructByval(MI, BB);
6997 void ARMTargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
6998 SDNode *Node) const {
6999 if (!MI->hasPostISelHook()) {
7000 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
7001 "Pseudo flag-setting opcodes must be marked with 'hasPostISelHook'");
7005 const MCInstrDesc *MCID = &MI->getDesc();
7006 // Adjust potentially 's' setting instructions after isel, i.e. ADC, SBC, RSB,
7007 // RSC. Coming out of isel, they have an implicit CPSR def, but the optional
7008 // operand is still set to noreg. If needed, set the optional operand's
7009 // register to CPSR, and remove the redundant implicit def.
7011 // e.g. ADCS (..., CPSR<imp-def>) -> ADC (... opt:CPSR<def>).
7013 // Rename pseudo opcodes.
7014 unsigned NewOpc = convertAddSubFlagsOpcode(MI->getOpcode());
7016 const ARMBaseInstrInfo *TII =
7017 static_cast<const ARMBaseInstrInfo*>(getTargetMachine().getInstrInfo());
7018 MCID = &TII->get(NewOpc);
7020 assert(MCID->getNumOperands() == MI->getDesc().getNumOperands() + 1 &&
7021 "converted opcode should be the same except for cc_out");
7025 // Add the optional cc_out operand
7026 MI->addOperand(MachineOperand::CreateReg(0, /*isDef=*/true));
7028 unsigned ccOutIdx = MCID->getNumOperands() - 1;
7030 // Any ARM instruction that sets the 's' bit should specify an optional
7031 // "cc_out" operand in the last operand position.
7032 if (!MI->hasOptionalDef() || !MCID->OpInfo[ccOutIdx].isOptionalDef()) {
7033 assert(!NewOpc && "Optional cc_out operand required");
7036 // Look for an implicit def of CPSR added by MachineInstr ctor. Remove it
7037 // since we already have an optional CPSR def.
7038 bool definesCPSR = false;
7039 bool deadCPSR = false;
7040 for (unsigned i = MCID->getNumOperands(), e = MI->getNumOperands();
7042 const MachineOperand &MO = MI->getOperand(i);
7043 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) {
7047 MI->RemoveOperand(i);
7052 assert(!NewOpc && "Optional cc_out operand required");
7055 assert(deadCPSR == !Node->hasAnyUseOfValue(1) && "inconsistent dead flag");
7057 assert(!MI->getOperand(ccOutIdx).getReg() &&
7058 "expect uninitialized optional cc_out operand");
7062 // If this instruction was defined with an optional CPSR def and its dag node
7063 // had a live implicit CPSR def, then activate the optional CPSR def.
7064 MachineOperand &MO = MI->getOperand(ccOutIdx);
7065 MO.setReg(ARM::CPSR);
7069 //===----------------------------------------------------------------------===//
7070 // ARM Optimization Hooks
7071 //===----------------------------------------------------------------------===//
7073 // Helper function that checks if N is a null or all ones constant.
7074 static inline bool isZeroOrAllOnes(SDValue N, bool AllOnes) {
7075 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
7078 return AllOnes ? C->isAllOnesValue() : C->isNullValue();
7081 // Return true if N is conditionally 0 or all ones.
7082 // Detects these expressions where cc is an i1 value:
7084 // (select cc 0, y) [AllOnes=0]
7085 // (select cc y, 0) [AllOnes=0]
7086 // (zext cc) [AllOnes=0]
7087 // (sext cc) [AllOnes=0/1]
7088 // (select cc -1, y) [AllOnes=1]
7089 // (select cc y, -1) [AllOnes=1]
7091 // Invert is set when N is the null/all ones constant when CC is false.
7092 // OtherOp is set to the alternative value of N.
7093 static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes,
7094 SDValue &CC, bool &Invert,
7096 SelectionDAG &DAG) {
7097 switch (N->getOpcode()) {
7098 default: return false;
7100 CC = N->getOperand(0);
7101 SDValue N1 = N->getOperand(1);
7102 SDValue N2 = N->getOperand(2);
7103 if (isZeroOrAllOnes(N1, AllOnes)) {
7108 if (isZeroOrAllOnes(N2, AllOnes)) {
7115 case ISD::ZERO_EXTEND:
7116 // (zext cc) can never be the all ones value.
7120 case ISD::SIGN_EXTEND: {
7121 EVT VT = N->getValueType(0);
7122 CC = N->getOperand(0);
7123 if (CC.getValueType() != MVT::i1)
7127 // When looking for an AllOnes constant, N is an sext, and the 'other'
7129 OtherOp = DAG.getConstant(0, VT);
7130 else if (N->getOpcode() == ISD::ZERO_EXTEND)
7131 // When looking for a 0 constant, N can be zext or sext.
7132 OtherOp = DAG.getConstant(1, VT);
7134 OtherOp = DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT);
7140 // Combine a constant select operand into its use:
7142 // (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
7143 // (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
7144 // (and (select cc, -1, c), x) -> (select cc, x, (and, x, c)) [AllOnes=1]
7145 // (or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
7146 // (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
7148 // The transform is rejected if the select doesn't have a constant operand that
7149 // is null, or all ones when AllOnes is set.
7151 // Also recognize sext/zext from i1:
7153 // (add (zext cc), x) -> (select cc (add x, 1), x)
7154 // (add (sext cc), x) -> (select cc (add x, -1), x)
7156 // These transformations eventually create predicated instructions.
7158 // @param N The node to transform.
7159 // @param Slct The N operand that is a select.
7160 // @param OtherOp The other N operand (x above).
7161 // @param DCI Context.
7162 // @param AllOnes Require the select constant to be all ones instead of null.
7163 // @returns The new node, or SDValue() on failure.
7165 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
7166 TargetLowering::DAGCombinerInfo &DCI,
7167 bool AllOnes = false) {
7168 SelectionDAG &DAG = DCI.DAG;
7169 EVT VT = N->getValueType(0);
7170 SDValue NonConstantVal;
7173 if (!isConditionalZeroOrAllOnes(Slct.getNode(), AllOnes, CCOp, SwapSelectOps,
7174 NonConstantVal, DAG))
7177 // Slct is now know to be the desired identity constant when CC is true.
7178 SDValue TrueVal = OtherOp;
7179 SDValue FalseVal = DAG.getNode(N->getOpcode(), N->getDebugLoc(), VT,
7180 OtherOp, NonConstantVal);
7181 // Unless SwapSelectOps says CC should be false.
7183 std::swap(TrueVal, FalseVal);
7185 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
7186 CCOp, TrueVal, FalseVal);
7189 // Attempt combineSelectAndUse on each operand of a commutative operator N.
7191 SDValue combineSelectAndUseCommutative(SDNode *N, bool AllOnes,
7192 TargetLowering::DAGCombinerInfo &DCI) {
7193 SDValue N0 = N->getOperand(0);
7194 SDValue N1 = N->getOperand(1);
7195 if (N0.getNode()->hasOneUse()) {
7196 SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes);
7197 if (Result.getNode())
7200 if (N1.getNode()->hasOneUse()) {
7201 SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes);
7202 if (Result.getNode())
7208 // AddCombineToVPADDL- For pair-wise add on neon, use the vpaddl instruction
7209 // (only after legalization).
7210 static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1,
7211 TargetLowering::DAGCombinerInfo &DCI,
7212 const ARMSubtarget *Subtarget) {
7214 // Only perform optimization if after legalize, and if NEON is available. We
7215 // also expected both operands to be BUILD_VECTORs.
7216 if (DCI.isBeforeLegalize() || !Subtarget->hasNEON()
7217 || N0.getOpcode() != ISD::BUILD_VECTOR
7218 || N1.getOpcode() != ISD::BUILD_VECTOR)
7221 // Check output type since VPADDL operand elements can only be 8, 16, or 32.
7222 EVT VT = N->getValueType(0);
7223 if (!VT.isInteger() || VT.getVectorElementType() == MVT::i64)
7226 // Check that the vector operands are of the right form.
7227 // N0 and N1 are BUILD_VECTOR nodes with N number of EXTRACT_VECTOR
7228 // operands, where N is the size of the formed vector.
7229 // Each EXTRACT_VECTOR should have the same input vector and odd or even
7230 // index such that we have a pair wise add pattern.
7232 // Grab the vector that all EXTRACT_VECTOR nodes should be referencing.
7233 if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
7235 SDValue Vec = N0->getOperand(0)->getOperand(0);
7236 SDNode *V = Vec.getNode();
7237 unsigned nextIndex = 0;
7239 // For each operands to the ADD which are BUILD_VECTORs,
7240 // check to see if each of their operands are an EXTRACT_VECTOR with
7241 // the same vector and appropriate index.
7242 for (unsigned i = 0, e = N0->getNumOperands(); i != e; ++i) {
7243 if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT
7244 && N1->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
7246 SDValue ExtVec0 = N0->getOperand(i);
7247 SDValue ExtVec1 = N1->getOperand(i);
7249 // First operand is the vector, verify its the same.
7250 if (V != ExtVec0->getOperand(0).getNode() ||
7251 V != ExtVec1->getOperand(0).getNode())
7254 // Second is the constant, verify its correct.
7255 ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(ExtVec0->getOperand(1));
7256 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(ExtVec1->getOperand(1));
7258 // For the constant, we want to see all the even or all the odd.
7259 if (!C0 || !C1 || C0->getZExtValue() != nextIndex
7260 || C1->getZExtValue() != nextIndex+1)
7269 // Create VPADDL node.
7270 SelectionDAG &DAG = DCI.DAG;
7271 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7273 // Build operand list.
7274 SmallVector<SDValue, 8> Ops;
7275 Ops.push_back(DAG.getConstant(Intrinsic::arm_neon_vpaddls,
7276 TLI.getPointerTy()));
7278 // Input is the vector.
7281 // Get widened type and narrowed type.
7283 unsigned numElem = VT.getVectorNumElements();
7284 switch (VT.getVectorElementType().getSimpleVT().SimpleTy) {
7285 case MVT::i8: widenType = MVT::getVectorVT(MVT::i16, numElem); break;
7286 case MVT::i16: widenType = MVT::getVectorVT(MVT::i32, numElem); break;
7287 case MVT::i32: widenType = MVT::getVectorVT(MVT::i64, numElem); break;
7289 llvm_unreachable("Invalid vector element type for padd optimization.");
7292 SDValue tmp = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(),
7293 widenType, &Ops[0], Ops.size());
7294 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, tmp);
7297 static SDValue findMUL_LOHI(SDValue V) {
7298 if (V->getOpcode() == ISD::UMUL_LOHI ||
7299 V->getOpcode() == ISD::SMUL_LOHI)
7304 static SDValue AddCombineTo64bitMLAL(SDNode *AddcNode,
7305 TargetLowering::DAGCombinerInfo &DCI,
7306 const ARMSubtarget *Subtarget) {
7308 if (Subtarget->isThumb1Only()) return SDValue();
7310 // Only perform the checks after legalize when the pattern is available.
7311 if (DCI.isBeforeLegalize()) return SDValue();
7313 // Look for multiply add opportunities.
7314 // The pattern is a ISD::UMUL_LOHI followed by two add nodes, where
7315 // each add nodes consumes a value from ISD::UMUL_LOHI and there is
7316 // a glue link from the first add to the second add.
7317 // If we find this pattern, we can replace the U/SMUL_LOHI, ADDC, and ADDE by
7318 // a S/UMLAL instruction.
7321 // \ / \ [no multiline comment]
7327 assert(AddcNode->getOpcode() == ISD::ADDC && "Expect an ADDC");
7328 SDValue AddcOp0 = AddcNode->getOperand(0);
7329 SDValue AddcOp1 = AddcNode->getOperand(1);
7331 // Check if the two operands are from the same mul_lohi node.
7332 if (AddcOp0.getNode() == AddcOp1.getNode())
7335 assert(AddcNode->getNumValues() == 2 &&
7336 AddcNode->getValueType(0) == MVT::i32 &&
7337 AddcNode->getValueType(1) == MVT::Glue &&
7338 "Expect ADDC with two result values: i32, glue");
7340 // Check that the ADDC adds the low result of the S/UMUL_LOHI.
7341 if (AddcOp0->getOpcode() != ISD::UMUL_LOHI &&
7342 AddcOp0->getOpcode() != ISD::SMUL_LOHI &&
7343 AddcOp1->getOpcode() != ISD::UMUL_LOHI &&
7344 AddcOp1->getOpcode() != ISD::SMUL_LOHI)
7347 // Look for the glued ADDE.
7348 SDNode* AddeNode = AddcNode->getGluedUser();
7349 if (AddeNode == NULL)
7352 // Make sure it is really an ADDE.
7353 if (AddeNode->getOpcode() != ISD::ADDE)
7356 assert(AddeNode->getNumOperands() == 3 &&
7357 AddeNode->getOperand(2).getValueType() == MVT::Glue &&
7358 "ADDE node has the wrong inputs");
7360 // Check for the triangle shape.
7361 SDValue AddeOp0 = AddeNode->getOperand(0);
7362 SDValue AddeOp1 = AddeNode->getOperand(1);
7364 // Make sure that the ADDE operands are not coming from the same node.
7365 if (AddeOp0.getNode() == AddeOp1.getNode())
7368 // Find the MUL_LOHI node walking up ADDE's operands.
7369 bool IsLeftOperandMUL = false;
7370 SDValue MULOp = findMUL_LOHI(AddeOp0);
7371 if (MULOp == SDValue())
7372 MULOp = findMUL_LOHI(AddeOp1);
7374 IsLeftOperandMUL = true;
7375 if (MULOp == SDValue())
7378 // Figure out the right opcode.
7379 unsigned Opc = MULOp->getOpcode();
7380 unsigned FinalOpc = (Opc == ISD::SMUL_LOHI) ? ARMISD::SMLAL : ARMISD::UMLAL;
7382 // Figure out the high and low input values to the MLAL node.
7383 SDValue* HiMul = &MULOp;
7384 SDValue* HiAdd = NULL;
7385 SDValue* LoMul = NULL;
7386 SDValue* LowAdd = NULL;
7388 if (IsLeftOperandMUL)
7394 if (AddcOp0->getOpcode() == Opc) {
7398 if (AddcOp1->getOpcode() == Opc) {
7406 if (LoMul->getNode() != HiMul->getNode())
7409 // Create the merged node.
7410 SelectionDAG &DAG = DCI.DAG;
7412 // Build operand list.
7413 SmallVector<SDValue, 8> Ops;
7414 Ops.push_back(LoMul->getOperand(0));
7415 Ops.push_back(LoMul->getOperand(1));
7416 Ops.push_back(*LowAdd);
7417 Ops.push_back(*HiAdd);
7419 SDValue MLALNode = DAG.getNode(FinalOpc, AddcNode->getDebugLoc(),
7420 DAG.getVTList(MVT::i32, MVT::i32),
7421 &Ops[0], Ops.size());
7423 // Replace the ADDs' nodes uses by the MLA node's values.
7424 SDValue HiMLALResult(MLALNode.getNode(), 1);
7425 DAG.ReplaceAllUsesOfValueWith(SDValue(AddeNode, 0), HiMLALResult);
7427 SDValue LoMLALResult(MLALNode.getNode(), 0);
7428 DAG.ReplaceAllUsesOfValueWith(SDValue(AddcNode, 0), LoMLALResult);
7430 // Return original node to notify the driver to stop replacing.
7431 SDValue resNode(AddcNode, 0);
7435 /// PerformADDCCombine - Target-specific dag combine transform from
7436 /// ISD::ADDC, ISD::ADDE, and ISD::MUL_LOHI to MLAL.
7437 static SDValue PerformADDCCombine(SDNode *N,
7438 TargetLowering::DAGCombinerInfo &DCI,
7439 const ARMSubtarget *Subtarget) {
7441 return AddCombineTo64bitMLAL(N, DCI, Subtarget);
7445 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
7446 /// operands N0 and N1. This is a helper for PerformADDCombine that is
7447 /// called with the default operands, and if that fails, with commuted
7449 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
7450 TargetLowering::DAGCombinerInfo &DCI,
7451 const ARMSubtarget *Subtarget){
7453 // Attempt to create vpaddl for this add.
7454 SDValue Result = AddCombineToVPADDL(N, N0, N1, DCI, Subtarget);
7455 if (Result.getNode())
7458 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
7459 if (N0.getNode()->hasOneUse()) {
7460 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
7461 if (Result.getNode()) return Result;
7466 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
7468 static SDValue PerformADDCombine(SDNode *N,
7469 TargetLowering::DAGCombinerInfo &DCI,
7470 const ARMSubtarget *Subtarget) {
7471 SDValue N0 = N->getOperand(0);
7472 SDValue N1 = N->getOperand(1);
7474 // First try with the default operand order.
7475 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget);
7476 if (Result.getNode())
7479 // If that didn't work, try again with the operands commuted.
7480 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget);
7483 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
7485 static SDValue PerformSUBCombine(SDNode *N,
7486 TargetLowering::DAGCombinerInfo &DCI) {
7487 SDValue N0 = N->getOperand(0);
7488 SDValue N1 = N->getOperand(1);
7490 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
7491 if (N1.getNode()->hasOneUse()) {
7492 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
7493 if (Result.getNode()) return Result;
7499 /// PerformVMULCombine
7500 /// Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the
7501 /// special multiplier accumulator forwarding.
7507 static SDValue PerformVMULCombine(SDNode *N,
7508 TargetLowering::DAGCombinerInfo &DCI,
7509 const ARMSubtarget *Subtarget) {
7510 if (!Subtarget->hasVMLxForwarding())
7513 SelectionDAG &DAG = DCI.DAG;
7514 SDValue N0 = N->getOperand(0);
7515 SDValue N1 = N->getOperand(1);
7516 unsigned Opcode = N0.getOpcode();
7517 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
7518 Opcode != ISD::FADD && Opcode != ISD::FSUB) {
7519 Opcode = N1.getOpcode();
7520 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
7521 Opcode != ISD::FADD && Opcode != ISD::FSUB)
7526 EVT VT = N->getValueType(0);
7527 DebugLoc DL = N->getDebugLoc();
7528 SDValue N00 = N0->getOperand(0);
7529 SDValue N01 = N0->getOperand(1);
7530 return DAG.getNode(Opcode, DL, VT,
7531 DAG.getNode(ISD::MUL, DL, VT, N00, N1),
7532 DAG.getNode(ISD::MUL, DL, VT, N01, N1));
7535 static SDValue PerformMULCombine(SDNode *N,
7536 TargetLowering::DAGCombinerInfo &DCI,
7537 const ARMSubtarget *Subtarget) {
7538 SelectionDAG &DAG = DCI.DAG;
7540 if (Subtarget->isThumb1Only())
7543 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
7546 EVT VT = N->getValueType(0);
7547 if (VT.is64BitVector() || VT.is128BitVector())
7548 return PerformVMULCombine(N, DCI, Subtarget);
7552 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
7556 int64_t MulAmt = C->getSExtValue();
7557 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt);
7559 ShiftAmt = ShiftAmt & (32 - 1);
7560 SDValue V = N->getOperand(0);
7561 DebugLoc DL = N->getDebugLoc();
7564 MulAmt >>= ShiftAmt;
7567 if (isPowerOf2_32(MulAmt - 1)) {
7568 // (mul x, 2^N + 1) => (add (shl x, N), x)
7569 Res = DAG.getNode(ISD::ADD, DL, VT,
7571 DAG.getNode(ISD::SHL, DL, VT,
7573 DAG.getConstant(Log2_32(MulAmt - 1),
7575 } else if (isPowerOf2_32(MulAmt + 1)) {
7576 // (mul x, 2^N - 1) => (sub (shl x, N), x)
7577 Res = DAG.getNode(ISD::SUB, DL, VT,
7578 DAG.getNode(ISD::SHL, DL, VT,
7580 DAG.getConstant(Log2_32(MulAmt + 1),
7586 uint64_t MulAmtAbs = -MulAmt;
7587 if (isPowerOf2_32(MulAmtAbs + 1)) {
7588 // (mul x, -(2^N - 1)) => (sub x, (shl x, N))
7589 Res = DAG.getNode(ISD::SUB, DL, VT,
7591 DAG.getNode(ISD::SHL, DL, VT,
7593 DAG.getConstant(Log2_32(MulAmtAbs + 1),
7595 } else if (isPowerOf2_32(MulAmtAbs - 1)) {
7596 // (mul x, -(2^N + 1)) => - (add (shl x, N), x)
7597 Res = DAG.getNode(ISD::ADD, DL, VT,
7599 DAG.getNode(ISD::SHL, DL, VT,
7601 DAG.getConstant(Log2_32(MulAmtAbs-1),
7603 Res = DAG.getNode(ISD::SUB, DL, VT,
7604 DAG.getConstant(0, MVT::i32),Res);
7611 Res = DAG.getNode(ISD::SHL, DL, VT,
7612 Res, DAG.getConstant(ShiftAmt, MVT::i32));
7614 // Do not add new nodes to DAG combiner worklist.
7615 DCI.CombineTo(N, Res, false);
7619 static SDValue PerformANDCombine(SDNode *N,
7620 TargetLowering::DAGCombinerInfo &DCI,
7621 const ARMSubtarget *Subtarget) {
7623 // Attempt to use immediate-form VBIC
7624 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
7625 DebugLoc dl = N->getDebugLoc();
7626 EVT VT = N->getValueType(0);
7627 SelectionDAG &DAG = DCI.DAG;
7629 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
7632 APInt SplatBits, SplatUndef;
7633 unsigned SplatBitSize;
7636 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
7637 if (SplatBitSize <= 64) {
7639 SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(),
7640 SplatUndef.getZExtValue(), SplatBitSize,
7641 DAG, VbicVT, VT.is128BitVector(),
7643 if (Val.getNode()) {
7645 DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0));
7646 SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val);
7647 return DAG.getNode(ISD::BITCAST, dl, VT, Vbic);
7652 if (!Subtarget->isThumb1Only()) {
7653 // fold (and (select cc, -1, c), x) -> (select cc, x, (and, x, c))
7654 SDValue Result = combineSelectAndUseCommutative(N, true, DCI);
7655 if (Result.getNode())
7662 /// PerformORCombine - Target-specific dag combine xforms for ISD::OR
7663 static SDValue PerformORCombine(SDNode *N,
7664 TargetLowering::DAGCombinerInfo &DCI,
7665 const ARMSubtarget *Subtarget) {
7666 // Attempt to use immediate-form VORR
7667 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
7668 DebugLoc dl = N->getDebugLoc();
7669 EVT VT = N->getValueType(0);
7670 SelectionDAG &DAG = DCI.DAG;
7672 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
7675 APInt SplatBits, SplatUndef;
7676 unsigned SplatBitSize;
7678 if (BVN && Subtarget->hasNEON() &&
7679 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
7680 if (SplatBitSize <= 64) {
7682 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
7683 SplatUndef.getZExtValue(), SplatBitSize,
7684 DAG, VorrVT, VT.is128BitVector(),
7686 if (Val.getNode()) {
7688 DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0));
7689 SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val);
7690 return DAG.getNode(ISD::BITCAST, dl, VT, Vorr);
7695 if (!Subtarget->isThumb1Only()) {
7696 // fold (or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
7697 SDValue Result = combineSelectAndUseCommutative(N, false, DCI);
7698 if (Result.getNode())
7702 // The code below optimizes (or (and X, Y), Z).
7703 // The AND operand needs to have a single user to make these optimizations
7705 SDValue N0 = N->getOperand(0);
7706 if (N0.getOpcode() != ISD::AND || !N0.hasOneUse())
7708 SDValue N1 = N->getOperand(1);
7710 // (or (and B, A), (and C, ~A)) => (VBSL A, B, C) when A is a constant.
7711 if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() &&
7712 DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
7714 unsigned SplatBitSize;
7717 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1));
7719 if (BVN0 && BVN0->isConstantSplat(SplatBits0, SplatUndef, SplatBitSize,
7720 HasAnyUndefs) && !HasAnyUndefs) {
7721 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(1));
7723 if (BVN1 && BVN1->isConstantSplat(SplatBits1, SplatUndef, SplatBitSize,
7724 HasAnyUndefs) && !HasAnyUndefs &&
7725 SplatBits0 == ~SplatBits1) {
7726 // Canonicalize the vector type to make instruction selection simpler.
7727 EVT CanonicalVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
7728 SDValue Result = DAG.getNode(ARMISD::VBSL, dl, CanonicalVT,
7729 N0->getOperand(1), N0->getOperand(0),
7731 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
7736 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when
7739 // BFI is only available on V6T2+
7740 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops())
7743 DebugLoc DL = N->getDebugLoc();
7744 // 1) or (and A, mask), val => ARMbfi A, val, mask
7745 // iff (val & mask) == val
7747 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
7748 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2)
7749 // && mask == ~mask2
7750 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2)
7751 // && ~mask == mask2
7752 // (i.e., copy a bitfield value into another bitfield of the same width)
7757 SDValue N00 = N0.getOperand(0);
7759 // The value and the mask need to be constants so we can verify this is
7760 // actually a bitfield set. If the mask is 0xffff, we can do better
7761 // via a movt instruction, so don't use BFI in that case.
7762 SDValue MaskOp = N0.getOperand(1);
7763 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(MaskOp);
7766 unsigned Mask = MaskC->getZExtValue();
7770 // Case (1): or (and A, mask), val => ARMbfi A, val, mask
7771 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
7773 unsigned Val = N1C->getZExtValue();
7774 if ((Val & ~Mask) != Val)
7777 if (ARM::isBitFieldInvertedMask(Mask)) {
7778 Val >>= CountTrailingZeros_32(~Mask);
7780 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00,
7781 DAG.getConstant(Val, MVT::i32),
7782 DAG.getConstant(Mask, MVT::i32));
7784 // Do not add new nodes to DAG combiner worklist.
7785 DCI.CombineTo(N, Res, false);
7788 } else if (N1.getOpcode() == ISD::AND) {
7789 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
7790 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
7793 unsigned Mask2 = N11C->getZExtValue();
7795 // Mask and ~Mask2 (or reverse) must be equivalent for the BFI pattern
7797 if (ARM::isBitFieldInvertedMask(Mask) &&
7799 // The pack halfword instruction works better for masks that fit it,
7800 // so use that when it's available.
7801 if (Subtarget->hasT2ExtractPack() &&
7802 (Mask == 0xffff || Mask == 0xffff0000))
7805 unsigned amt = CountTrailingZeros_32(Mask2);
7806 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
7807 DAG.getConstant(amt, MVT::i32));
7808 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res,
7809 DAG.getConstant(Mask, MVT::i32));
7810 // Do not add new nodes to DAG combiner worklist.
7811 DCI.CombineTo(N, Res, false);
7813 } else if (ARM::isBitFieldInvertedMask(~Mask) &&
7815 // The pack halfword instruction works better for masks that fit it,
7816 // so use that when it's available.
7817 if (Subtarget->hasT2ExtractPack() &&
7818 (Mask2 == 0xffff || Mask2 == 0xffff0000))
7821 unsigned lsb = CountTrailingZeros_32(Mask);
7822 Res = DAG.getNode(ISD::SRL, DL, VT, N00,
7823 DAG.getConstant(lsb, MVT::i32));
7824 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
7825 DAG.getConstant(Mask2, MVT::i32));
7826 // Do not add new nodes to DAG combiner worklist.
7827 DCI.CombineTo(N, Res, false);
7832 if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) &&
7833 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) &&
7834 ARM::isBitFieldInvertedMask(~Mask)) {
7835 // Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask
7836 // where lsb(mask) == #shamt and masked bits of B are known zero.
7837 SDValue ShAmt = N00.getOperand(1);
7838 unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue();
7839 unsigned LSB = CountTrailingZeros_32(Mask);
7843 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0),
7844 DAG.getConstant(~Mask, MVT::i32));
7846 // Do not add new nodes to DAG combiner worklist.
7847 DCI.CombineTo(N, Res, false);
7853 static SDValue PerformXORCombine(SDNode *N,
7854 TargetLowering::DAGCombinerInfo &DCI,
7855 const ARMSubtarget *Subtarget) {
7856 EVT VT = N->getValueType(0);
7857 SelectionDAG &DAG = DCI.DAG;
7859 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
7862 if (!Subtarget->isThumb1Only()) {
7863 // fold (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
7864 SDValue Result = combineSelectAndUseCommutative(N, false, DCI);
7865 if (Result.getNode())
7872 /// PerformBFICombine - (bfi A, (and B, Mask1), Mask2) -> (bfi A, B, Mask2) iff
7873 /// the bits being cleared by the AND are not demanded by the BFI.
7874 static SDValue PerformBFICombine(SDNode *N,
7875 TargetLowering::DAGCombinerInfo &DCI) {
7876 SDValue N1 = N->getOperand(1);
7877 if (N1.getOpcode() == ISD::AND) {
7878 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
7881 unsigned InvMask = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
7882 unsigned LSB = CountTrailingZeros_32(~InvMask);
7883 unsigned Width = (32 - CountLeadingZeros_32(~InvMask)) - LSB;
7884 unsigned Mask = (1 << Width)-1;
7885 unsigned Mask2 = N11C->getZExtValue();
7886 if ((Mask & (~Mask2)) == 0)
7887 return DCI.DAG.getNode(ARMISD::BFI, N->getDebugLoc(), N->getValueType(0),
7888 N->getOperand(0), N1.getOperand(0),
7894 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
7895 /// ARMISD::VMOVRRD.
7896 static SDValue PerformVMOVRRDCombine(SDNode *N,
7897 TargetLowering::DAGCombinerInfo &DCI) {
7898 // vmovrrd(vmovdrr x, y) -> x,y
7899 SDValue InDouble = N->getOperand(0);
7900 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
7901 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
7903 // vmovrrd(load f64) -> (load i32), (load i32)
7904 SDNode *InNode = InDouble.getNode();
7905 if (ISD::isNormalLoad(InNode) && InNode->hasOneUse() &&
7906 InNode->getValueType(0) == MVT::f64 &&
7907 InNode->getOperand(1).getOpcode() == ISD::FrameIndex &&
7908 !cast<LoadSDNode>(InNode)->isVolatile()) {
7909 // TODO: Should this be done for non-FrameIndex operands?
7910 LoadSDNode *LD = cast<LoadSDNode>(InNode);
7912 SelectionDAG &DAG = DCI.DAG;
7913 DebugLoc DL = LD->getDebugLoc();
7914 SDValue BasePtr = LD->getBasePtr();
7915 SDValue NewLD1 = DAG.getLoad(MVT::i32, DL, LD->getChain(), BasePtr,
7916 LD->getPointerInfo(), LD->isVolatile(),
7917 LD->isNonTemporal(), LD->isInvariant(),
7918 LD->getAlignment());
7920 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
7921 DAG.getConstant(4, MVT::i32));
7922 SDValue NewLD2 = DAG.getLoad(MVT::i32, DL, NewLD1.getValue(1), OffsetPtr,
7923 LD->getPointerInfo(), LD->isVolatile(),
7924 LD->isNonTemporal(), LD->isInvariant(),
7925 std::min(4U, LD->getAlignment() / 2));
7927 DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), NewLD2.getValue(1));
7928 SDValue Result = DCI.CombineTo(N, NewLD1, NewLD2);
7929 DCI.RemoveFromWorklist(LD);
7937 /// PerformVMOVDRRCombine - Target-specific dag combine xforms for
7938 /// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands.
7939 static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) {
7940 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X)
7941 SDValue Op0 = N->getOperand(0);
7942 SDValue Op1 = N->getOperand(1);
7943 if (Op0.getOpcode() == ISD::BITCAST)
7944 Op0 = Op0.getOperand(0);
7945 if (Op1.getOpcode() == ISD::BITCAST)
7946 Op1 = Op1.getOperand(0);
7947 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
7948 Op0.getNode() == Op1.getNode() &&
7949 Op0.getResNo() == 0 && Op1.getResNo() == 1)
7950 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
7951 N->getValueType(0), Op0.getOperand(0));
7955 /// PerformSTORECombine - Target-specific dag combine xforms for
7957 static SDValue PerformSTORECombine(SDNode *N,
7958 TargetLowering::DAGCombinerInfo &DCI) {
7959 StoreSDNode *St = cast<StoreSDNode>(N);
7960 if (St->isVolatile())
7963 // Optimize trunc store (of multiple scalars) to shuffle and store. First,
7964 // pack all of the elements in one place. Next, store to memory in fewer
7966 SDValue StVal = St->getValue();
7967 EVT VT = StVal.getValueType();
7968 if (St->isTruncatingStore() && VT.isVector()) {
7969 SelectionDAG &DAG = DCI.DAG;
7970 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7971 EVT StVT = St->getMemoryVT();
7972 unsigned NumElems = VT.getVectorNumElements();
7973 assert(StVT != VT && "Cannot truncate to the same type");
7974 unsigned FromEltSz = VT.getVectorElementType().getSizeInBits();
7975 unsigned ToEltSz = StVT.getVectorElementType().getSizeInBits();
7977 // From, To sizes and ElemCount must be pow of two
7978 if (!isPowerOf2_32(NumElems * FromEltSz * ToEltSz)) return SDValue();
7980 // We are going to use the original vector elt for storing.
7981 // Accumulated smaller vector elements must be a multiple of the store size.
7982 if (0 != (NumElems * FromEltSz) % ToEltSz) return SDValue();
7984 unsigned SizeRatio = FromEltSz / ToEltSz;
7985 assert(SizeRatio * NumElems * ToEltSz == VT.getSizeInBits());
7987 // Create a type on which we perform the shuffle.
7988 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), StVT.getScalarType(),
7989 NumElems*SizeRatio);
7990 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
7992 DebugLoc DL = St->getDebugLoc();
7993 SDValue WideVec = DAG.getNode(ISD::BITCAST, DL, WideVecVT, StVal);
7994 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
7995 for (unsigned i = 0; i < NumElems; ++i) ShuffleVec[i] = i * SizeRatio;
7997 // Can't shuffle using an illegal type.
7998 if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
8000 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, DL, WideVec,
8001 DAG.getUNDEF(WideVec.getValueType()),
8003 // At this point all of the data is stored at the bottom of the
8004 // register. We now need to save it to mem.
8006 // Find the largest store unit
8007 MVT StoreType = MVT::i8;
8008 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
8009 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
8010 MVT Tp = (MVT::SimpleValueType)tp;
8011 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToEltSz)
8014 // Didn't find a legal store type.
8015 if (!TLI.isTypeLegal(StoreType))
8018 // Bitcast the original vector into a vector of store-size units
8019 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
8020 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
8021 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
8022 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, DL, StoreVecVT, Shuff);
8023 SmallVector<SDValue, 8> Chains;
8024 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
8025 TLI.getPointerTy());
8026 SDValue BasePtr = St->getBasePtr();
8028 // Perform one or more big stores into memory.
8029 unsigned E = (ToEltSz*NumElems)/StoreType.getSizeInBits();
8030 for (unsigned I = 0; I < E; I++) {
8031 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
8032 StoreType, ShuffWide,
8033 DAG.getIntPtrConstant(I));
8034 SDValue Ch = DAG.getStore(St->getChain(), DL, SubVec, BasePtr,
8035 St->getPointerInfo(), St->isVolatile(),
8036 St->isNonTemporal(), St->getAlignment());
8037 BasePtr = DAG.getNode(ISD::ADD, DL, BasePtr.getValueType(), BasePtr,
8039 Chains.push_back(Ch);
8041 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, &Chains[0],
8045 if (!ISD::isNormalStore(St))
8048 // Split a store of a VMOVDRR into two integer stores to avoid mixing NEON and
8049 // ARM stores of arguments in the same cache line.
8050 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR &&
8051 StVal.getNode()->hasOneUse()) {
8052 SelectionDAG &DAG = DCI.DAG;
8053 DebugLoc DL = St->getDebugLoc();
8054 SDValue BasePtr = St->getBasePtr();
8055 SDValue NewST1 = DAG.getStore(St->getChain(), DL,
8056 StVal.getNode()->getOperand(0), BasePtr,
8057 St->getPointerInfo(), St->isVolatile(),
8058 St->isNonTemporal(), St->getAlignment());
8060 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
8061 DAG.getConstant(4, MVT::i32));
8062 return DAG.getStore(NewST1.getValue(0), DL, StVal.getNode()->getOperand(1),
8063 OffsetPtr, St->getPointerInfo(), St->isVolatile(),
8064 St->isNonTemporal(),
8065 std::min(4U, St->getAlignment() / 2));
8068 if (StVal.getValueType() != MVT::i64 ||
8069 StVal.getNode()->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
8072 // Bitcast an i64 store extracted from a vector to f64.
8073 // Otherwise, the i64 value will be legalized to a pair of i32 values.
8074 SelectionDAG &DAG = DCI.DAG;
8075 DebugLoc dl = StVal.getDebugLoc();
8076 SDValue IntVec = StVal.getOperand(0);
8077 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
8078 IntVec.getValueType().getVectorNumElements());
8079 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec);
8080 SDValue ExtElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8081 Vec, StVal.getOperand(1));
8082 dl = N->getDebugLoc();
8083 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt);
8084 // Make the DAGCombiner fold the bitcasts.
8085 DCI.AddToWorklist(Vec.getNode());
8086 DCI.AddToWorklist(ExtElt.getNode());
8087 DCI.AddToWorklist(V.getNode());
8088 return DAG.getStore(St->getChain(), dl, V, St->getBasePtr(),
8089 St->getPointerInfo(), St->isVolatile(),
8090 St->isNonTemporal(), St->getAlignment(),
8094 /// hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node
8095 /// are normal, non-volatile loads. If so, it is profitable to bitcast an
8096 /// i64 vector to have f64 elements, since the value can then be loaded
8097 /// directly into a VFP register.
8098 static bool hasNormalLoadOperand(SDNode *N) {
8099 unsigned NumElts = N->getValueType(0).getVectorNumElements();
8100 for (unsigned i = 0; i < NumElts; ++i) {
8101 SDNode *Elt = N->getOperand(i).getNode();
8102 if (ISD::isNormalLoad(Elt) && !cast<LoadSDNode>(Elt)->isVolatile())
8108 /// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for
8109 /// ISD::BUILD_VECTOR.
8110 static SDValue PerformBUILD_VECTORCombine(SDNode *N,
8111 TargetLowering::DAGCombinerInfo &DCI){
8112 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X):
8113 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value
8114 // into a pair of GPRs, which is fine when the value is used as a scalar,
8115 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD.
8116 SelectionDAG &DAG = DCI.DAG;
8117 if (N->getNumOperands() == 2) {
8118 SDValue RV = PerformVMOVDRRCombine(N, DAG);
8123 // Load i64 elements as f64 values so that type legalization does not split
8124 // them up into i32 values.
8125 EVT VT = N->getValueType(0);
8126 if (VT.getVectorElementType() != MVT::i64 || !hasNormalLoadOperand(N))
8128 DebugLoc dl = N->getDebugLoc();
8129 SmallVector<SDValue, 8> Ops;
8130 unsigned NumElts = VT.getVectorNumElements();
8131 for (unsigned i = 0; i < NumElts; ++i) {
8132 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(i));
8134 // Make the DAGCombiner fold the bitcast.
8135 DCI.AddToWorklist(V.getNode());
8137 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, NumElts);
8138 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, FloatVT, Ops.data(), NumElts);
8139 return DAG.getNode(ISD::BITCAST, dl, VT, BV);
8142 /// PerformInsertEltCombine - Target-specific dag combine xforms for
8143 /// ISD::INSERT_VECTOR_ELT.
8144 static SDValue PerformInsertEltCombine(SDNode *N,
8145 TargetLowering::DAGCombinerInfo &DCI) {
8146 // Bitcast an i64 load inserted into a vector to f64.
8147 // Otherwise, the i64 value will be legalized to a pair of i32 values.
8148 EVT VT = N->getValueType(0);
8149 SDNode *Elt = N->getOperand(1).getNode();
8150 if (VT.getVectorElementType() != MVT::i64 ||
8151 !ISD::isNormalLoad(Elt) || cast<LoadSDNode>(Elt)->isVolatile())
8154 SelectionDAG &DAG = DCI.DAG;
8155 DebugLoc dl = N->getDebugLoc();
8156 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
8157 VT.getVectorNumElements());
8158 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, N->getOperand(0));
8159 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(1));
8160 // Make the DAGCombiner fold the bitcasts.
8161 DCI.AddToWorklist(Vec.getNode());
8162 DCI.AddToWorklist(V.getNode());
8163 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT,
8164 Vec, V, N->getOperand(2));
8165 return DAG.getNode(ISD::BITCAST, dl, VT, InsElt);
8168 /// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for
8169 /// ISD::VECTOR_SHUFFLE.
8170 static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) {
8171 // The LLVM shufflevector instruction does not require the shuffle mask
8172 // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does
8173 // have that requirement. When translating to ISD::VECTOR_SHUFFLE, if the
8174 // operands do not match the mask length, they are extended by concatenating
8175 // them with undef vectors. That is probably the right thing for other
8176 // targets, but for NEON it is better to concatenate two double-register
8177 // size vector operands into a single quad-register size vector. Do that
8178 // transformation here:
8179 // shuffle(concat(v1, undef), concat(v2, undef)) ->
8180 // shuffle(concat(v1, v2), undef)
8181 SDValue Op0 = N->getOperand(0);
8182 SDValue Op1 = N->getOperand(1);
8183 if (Op0.getOpcode() != ISD::CONCAT_VECTORS ||
8184 Op1.getOpcode() != ISD::CONCAT_VECTORS ||
8185 Op0.getNumOperands() != 2 ||
8186 Op1.getNumOperands() != 2)
8188 SDValue Concat0Op1 = Op0.getOperand(1);
8189 SDValue Concat1Op1 = Op1.getOperand(1);
8190 if (Concat0Op1.getOpcode() != ISD::UNDEF ||
8191 Concat1Op1.getOpcode() != ISD::UNDEF)
8193 // Skip the transformation if any of the types are illegal.
8194 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8195 EVT VT = N->getValueType(0);
8196 if (!TLI.isTypeLegal(VT) ||
8197 !TLI.isTypeLegal(Concat0Op1.getValueType()) ||
8198 !TLI.isTypeLegal(Concat1Op1.getValueType()))
8201 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT,
8202 Op0.getOperand(0), Op1.getOperand(0));
8203 // Translate the shuffle mask.
8204 SmallVector<int, 16> NewMask;
8205 unsigned NumElts = VT.getVectorNumElements();
8206 unsigned HalfElts = NumElts/2;
8207 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
8208 for (unsigned n = 0; n < NumElts; ++n) {
8209 int MaskElt = SVN->getMaskElt(n);
8211 if (MaskElt < (int)HalfElts)
8213 else if (MaskElt >= (int)NumElts && MaskElt < (int)(NumElts + HalfElts))
8214 NewElt = HalfElts + MaskElt - NumElts;
8215 NewMask.push_back(NewElt);
8217 return DAG.getVectorShuffle(VT, N->getDebugLoc(), NewConcat,
8218 DAG.getUNDEF(VT), NewMask.data());
8221 /// CombineBaseUpdate - Target-specific DAG combine function for VLDDUP and
8222 /// NEON load/store intrinsics to merge base address updates.
8223 static SDValue CombineBaseUpdate(SDNode *N,
8224 TargetLowering::DAGCombinerInfo &DCI) {
8225 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
8228 SelectionDAG &DAG = DCI.DAG;
8229 bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID ||
8230 N->getOpcode() == ISD::INTRINSIC_W_CHAIN);
8231 unsigned AddrOpIdx = (isIntrinsic ? 2 : 1);
8232 SDValue Addr = N->getOperand(AddrOpIdx);
8234 // Search for a use of the address operand that is an increment.
8235 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
8236 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
8238 if (User->getOpcode() != ISD::ADD ||
8239 UI.getUse().getResNo() != Addr.getResNo())
8242 // Check that the add is independent of the load/store. Otherwise, folding
8243 // it would create a cycle.
8244 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
8247 // Find the new opcode for the updating load/store.
8249 bool isLaneOp = false;
8250 unsigned NewOpc = 0;
8251 unsigned NumVecs = 0;
8253 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
8255 default: llvm_unreachable("unexpected intrinsic for Neon base update");
8256 case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD;
8258 case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD;
8260 case Intrinsic::arm_neon_vld3: NewOpc = ARMISD::VLD3_UPD;
8262 case Intrinsic::arm_neon_vld4: NewOpc = ARMISD::VLD4_UPD;
8264 case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD;
8265 NumVecs = 2; isLaneOp = true; break;
8266 case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD;
8267 NumVecs = 3; isLaneOp = true; break;
8268 case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD;
8269 NumVecs = 4; isLaneOp = true; break;
8270 case Intrinsic::arm_neon_vst1: NewOpc = ARMISD::VST1_UPD;
8271 NumVecs = 1; isLoad = false; break;
8272 case Intrinsic::arm_neon_vst2: NewOpc = ARMISD::VST2_UPD;
8273 NumVecs = 2; isLoad = false; break;
8274 case Intrinsic::arm_neon_vst3: NewOpc = ARMISD::VST3_UPD;
8275 NumVecs = 3; isLoad = false; break;
8276 case Intrinsic::arm_neon_vst4: NewOpc = ARMISD::VST4_UPD;
8277 NumVecs = 4; isLoad = false; break;
8278 case Intrinsic::arm_neon_vst2lane: NewOpc = ARMISD::VST2LN_UPD;
8279 NumVecs = 2; isLoad = false; isLaneOp = true; break;
8280 case Intrinsic::arm_neon_vst3lane: NewOpc = ARMISD::VST3LN_UPD;
8281 NumVecs = 3; isLoad = false; isLaneOp = true; break;
8282 case Intrinsic::arm_neon_vst4lane: NewOpc = ARMISD::VST4LN_UPD;
8283 NumVecs = 4; isLoad = false; isLaneOp = true; break;
8287 switch (N->getOpcode()) {
8288 default: llvm_unreachable("unexpected opcode for Neon base update");
8289 case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break;
8290 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break;
8291 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break;
8295 // Find the size of memory referenced by the load/store.
8298 VecTy = N->getValueType(0);
8300 VecTy = N->getOperand(AddrOpIdx+1).getValueType();
8301 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
8303 NumBytes /= VecTy.getVectorNumElements();
8305 // If the increment is a constant, it must match the memory ref size.
8306 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
8307 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
8308 uint64_t IncVal = CInc->getZExtValue();
8309 if (IncVal != NumBytes)
8311 } else if (NumBytes >= 3 * 16) {
8312 // VLD3/4 and VST3/4 for 128-bit vectors are implemented with two
8313 // separate instructions that make it harder to use a non-constant update.
8317 // Create the new updating load/store node.
8319 unsigned NumResultVecs = (isLoad ? NumVecs : 0);
8321 for (n = 0; n < NumResultVecs; ++n)
8323 Tys[n++] = MVT::i32;
8324 Tys[n] = MVT::Other;
8325 SDVTList SDTys = DAG.getVTList(Tys, NumResultVecs+2);
8326 SmallVector<SDValue, 8> Ops;
8327 Ops.push_back(N->getOperand(0)); // incoming chain
8328 Ops.push_back(N->getOperand(AddrOpIdx));
8330 for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands(); ++i) {
8331 Ops.push_back(N->getOperand(i));
8333 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
8334 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, N->getDebugLoc(), SDTys,
8335 Ops.data(), Ops.size(),
8336 MemInt->getMemoryVT(),
8337 MemInt->getMemOperand());
8340 std::vector<SDValue> NewResults;
8341 for (unsigned i = 0; i < NumResultVecs; ++i) {
8342 NewResults.push_back(SDValue(UpdN.getNode(), i));
8344 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs+1)); // chain
8345 DCI.CombineTo(N, NewResults);
8346 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
8353 /// CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a
8354 /// vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic
8355 /// are also VDUPLANEs. If so, combine them to a vldN-dup operation and
8357 static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
8358 SelectionDAG &DAG = DCI.DAG;
8359 EVT VT = N->getValueType(0);
8360 // vldN-dup instructions only support 64-bit vectors for N > 1.
8361 if (!VT.is64BitVector())
8364 // Check if the VDUPLANE operand is a vldN-dup intrinsic.
8365 SDNode *VLD = N->getOperand(0).getNode();
8366 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN)
8368 unsigned NumVecs = 0;
8369 unsigned NewOpc = 0;
8370 unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue();
8371 if (IntNo == Intrinsic::arm_neon_vld2lane) {
8373 NewOpc = ARMISD::VLD2DUP;
8374 } else if (IntNo == Intrinsic::arm_neon_vld3lane) {
8376 NewOpc = ARMISD::VLD3DUP;
8377 } else if (IntNo == Intrinsic::arm_neon_vld4lane) {
8379 NewOpc = ARMISD::VLD4DUP;
8384 // First check that all the vldN-lane uses are VDUPLANEs and that the lane
8385 // numbers match the load.
8386 unsigned VLDLaneNo =
8387 cast<ConstantSDNode>(VLD->getOperand(NumVecs+3))->getZExtValue();
8388 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
8390 // Ignore uses of the chain result.
8391 if (UI.getUse().getResNo() == NumVecs)
8394 if (User->getOpcode() != ARMISD::VDUPLANE ||
8395 VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue())
8399 // Create the vldN-dup node.
8402 for (n = 0; n < NumVecs; ++n)
8404 Tys[n] = MVT::Other;
8405 SDVTList SDTys = DAG.getVTList(Tys, NumVecs+1);
8406 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) };
8407 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD);
8408 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, VLD->getDebugLoc(), SDTys,
8409 Ops, 2, VLDMemInt->getMemoryVT(),
8410 VLDMemInt->getMemOperand());
8413 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
8415 unsigned ResNo = UI.getUse().getResNo();
8416 // Ignore uses of the chain result.
8417 if (ResNo == NumVecs)
8420 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo));
8423 // Now the vldN-lane intrinsic is dead except for its chain result.
8424 // Update uses of the chain.
8425 std::vector<SDValue> VLDDupResults;
8426 for (unsigned n = 0; n < NumVecs; ++n)
8427 VLDDupResults.push_back(SDValue(VLDDup.getNode(), n));
8428 VLDDupResults.push_back(SDValue(VLDDup.getNode(), NumVecs));
8429 DCI.CombineTo(VLD, VLDDupResults);
8434 /// PerformVDUPLANECombine - Target-specific dag combine xforms for
8435 /// ARMISD::VDUPLANE.
8436 static SDValue PerformVDUPLANECombine(SDNode *N,
8437 TargetLowering::DAGCombinerInfo &DCI) {
8438 SDValue Op = N->getOperand(0);
8440 // If the source is a vldN-lane (N > 1) intrinsic, and all the other uses
8441 // of that intrinsic are also VDUPLANEs, combine them to a vldN-dup operation.
8442 if (CombineVLDDUP(N, DCI))
8443 return SDValue(N, 0);
8445 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
8446 // redundant. Ignore bit_converts for now; element sizes are checked below.
8447 while (Op.getOpcode() == ISD::BITCAST)
8448 Op = Op.getOperand(0);
8449 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
8452 // Make sure the VMOV element size is not bigger than the VDUPLANE elements.
8453 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits();
8454 // The canonical VMOV for a zero vector uses a 32-bit element size.
8455 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
8457 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
8459 EVT VT = N->getValueType(0);
8460 if (EltSize > VT.getVectorElementType().getSizeInBits())
8463 return DCI.DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
8466 // isConstVecPow2 - Return true if each vector element is a power of 2, all
8467 // elements are the same constant, C, and Log2(C) ranges from 1 to 32.
8468 static bool isConstVecPow2(SDValue ConstVec, bool isSigned, uint64_t &C)
8472 for (unsigned I = 0, E = ConstVec.getValueType().getVectorNumElements();
8474 ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(ConstVec.getOperand(I));
8479 APFloat APF = C->getValueAPF();
8480 if (APF.convertToInteger(&cN, 64, isSigned, APFloat::rmTowardZero, &isExact)
8481 != APFloat::opOK || !isExact)
8484 c0 = (I == 0) ? cN : c0;
8485 if (!isPowerOf2_64(cN) || c0 != cN || Log2_64(c0) < 1 || Log2_64(c0) > 32)
8492 /// PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD)
8493 /// can replace combinations of VMUL and VCVT (floating-point to integer)
8494 /// when the VMUL has a constant operand that is a power of 2.
8496 /// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
8497 /// vmul.f32 d16, d17, d16
8498 /// vcvt.s32.f32 d16, d16
8500 /// vcvt.s32.f32 d16, d16, #3
8501 static SDValue PerformVCVTCombine(SDNode *N,
8502 TargetLowering::DAGCombinerInfo &DCI,
8503 const ARMSubtarget *Subtarget) {
8504 SelectionDAG &DAG = DCI.DAG;
8505 SDValue Op = N->getOperand(0);
8507 if (!Subtarget->hasNEON() || !Op.getValueType().isVector() ||
8508 Op.getOpcode() != ISD::FMUL)
8512 SDValue N0 = Op->getOperand(0);
8513 SDValue ConstVec = Op->getOperand(1);
8514 bool isSigned = N->getOpcode() == ISD::FP_TO_SINT;
8516 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
8517 !isConstVecPow2(ConstVec, isSigned, C))
8520 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfp2fxs :
8521 Intrinsic::arm_neon_vcvtfp2fxu;
8522 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(),
8524 DAG.getConstant(IntrinsicOpcode, MVT::i32), N0,
8525 DAG.getConstant(Log2_64(C), MVT::i32));
8528 /// PerformVDIVCombine - VCVT (fixed-point to floating-point, Advanced SIMD)
8529 /// can replace combinations of VCVT (integer to floating-point) and VDIV
8530 /// when the VDIV has a constant operand that is a power of 2.
8532 /// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
8533 /// vcvt.f32.s32 d16, d16
8534 /// vdiv.f32 d16, d17, d16
8536 /// vcvt.f32.s32 d16, d16, #3
8537 static SDValue PerformVDIVCombine(SDNode *N,
8538 TargetLowering::DAGCombinerInfo &DCI,
8539 const ARMSubtarget *Subtarget) {
8540 SelectionDAG &DAG = DCI.DAG;
8541 SDValue Op = N->getOperand(0);
8542 unsigned OpOpcode = Op.getNode()->getOpcode();
8544 if (!Subtarget->hasNEON() || !N->getValueType(0).isVector() ||
8545 (OpOpcode != ISD::SINT_TO_FP && OpOpcode != ISD::UINT_TO_FP))
8549 SDValue ConstVec = N->getOperand(1);
8550 bool isSigned = OpOpcode == ISD::SINT_TO_FP;
8552 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
8553 !isConstVecPow2(ConstVec, isSigned, C))
8556 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfxs2fp :
8557 Intrinsic::arm_neon_vcvtfxu2fp;
8558 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(),
8560 DAG.getConstant(IntrinsicOpcode, MVT::i32),
8561 Op.getOperand(0), DAG.getConstant(Log2_64(C), MVT::i32));
8564 /// Getvshiftimm - Check if this is a valid build_vector for the immediate
8565 /// operand of a vector shift operation, where all the elements of the
8566 /// build_vector must have the same constant integer value.
8567 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
8568 // Ignore bit_converts.
8569 while (Op.getOpcode() == ISD::BITCAST)
8570 Op = Op.getOperand(0);
8571 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
8572 APInt SplatBits, SplatUndef;
8573 unsigned SplatBitSize;
8575 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
8576 HasAnyUndefs, ElementBits) ||
8577 SplatBitSize > ElementBits)
8579 Cnt = SplatBits.getSExtValue();
8583 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
8584 /// operand of a vector shift left operation. That value must be in the range:
8585 /// 0 <= Value < ElementBits for a left shift; or
8586 /// 0 <= Value <= ElementBits for a long left shift.
8587 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
8588 assert(VT.isVector() && "vector shift count is not a vector type");
8589 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
8590 if (! getVShiftImm(Op, ElementBits, Cnt))
8592 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
8595 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
8596 /// operand of a vector shift right operation. For a shift opcode, the value
8597 /// is positive, but for an intrinsic the value count must be negative. The
8598 /// absolute value must be in the range:
8599 /// 1 <= |Value| <= ElementBits for a right shift; or
8600 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
8601 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
8603 assert(VT.isVector() && "vector shift count is not a vector type");
8604 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
8605 if (! getVShiftImm(Op, ElementBits, Cnt))
8609 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
8612 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
8613 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
8614 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
8617 // Don't do anything for most intrinsics.
8620 // Vector shifts: check for immediate versions and lower them.
8621 // Note: This is done during DAG combining instead of DAG legalizing because
8622 // the build_vectors for 64-bit vector element shift counts are generally
8623 // not legal, and it is hard to see their values after they get legalized to
8624 // loads from a constant pool.
8625 case Intrinsic::arm_neon_vshifts:
8626 case Intrinsic::arm_neon_vshiftu:
8627 case Intrinsic::arm_neon_vshiftls:
8628 case Intrinsic::arm_neon_vshiftlu:
8629 case Intrinsic::arm_neon_vshiftn:
8630 case Intrinsic::arm_neon_vrshifts:
8631 case Intrinsic::arm_neon_vrshiftu:
8632 case Intrinsic::arm_neon_vrshiftn:
8633 case Intrinsic::arm_neon_vqshifts:
8634 case Intrinsic::arm_neon_vqshiftu:
8635 case Intrinsic::arm_neon_vqshiftsu:
8636 case Intrinsic::arm_neon_vqshiftns:
8637 case Intrinsic::arm_neon_vqshiftnu:
8638 case Intrinsic::arm_neon_vqshiftnsu:
8639 case Intrinsic::arm_neon_vqrshiftns:
8640 case Intrinsic::arm_neon_vqrshiftnu:
8641 case Intrinsic::arm_neon_vqrshiftnsu: {
8642 EVT VT = N->getOperand(1).getValueType();
8644 unsigned VShiftOpc = 0;
8647 case Intrinsic::arm_neon_vshifts:
8648 case Intrinsic::arm_neon_vshiftu:
8649 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
8650 VShiftOpc = ARMISD::VSHL;
8653 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
8654 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
8655 ARMISD::VSHRs : ARMISD::VSHRu);
8660 case Intrinsic::arm_neon_vshiftls:
8661 case Intrinsic::arm_neon_vshiftlu:
8662 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
8664 llvm_unreachable("invalid shift count for vshll intrinsic");
8666 case Intrinsic::arm_neon_vrshifts:
8667 case Intrinsic::arm_neon_vrshiftu:
8668 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
8672 case Intrinsic::arm_neon_vqshifts:
8673 case Intrinsic::arm_neon_vqshiftu:
8674 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
8678 case Intrinsic::arm_neon_vqshiftsu:
8679 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
8681 llvm_unreachable("invalid shift count for vqshlu intrinsic");
8683 case Intrinsic::arm_neon_vshiftn:
8684 case Intrinsic::arm_neon_vrshiftn:
8685 case Intrinsic::arm_neon_vqshiftns:
8686 case Intrinsic::arm_neon_vqshiftnu:
8687 case Intrinsic::arm_neon_vqshiftnsu:
8688 case Intrinsic::arm_neon_vqrshiftns:
8689 case Intrinsic::arm_neon_vqrshiftnu:
8690 case Intrinsic::arm_neon_vqrshiftnsu:
8691 // Narrowing shifts require an immediate right shift.
8692 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
8694 llvm_unreachable("invalid shift count for narrowing vector shift "
8698 llvm_unreachable("unhandled vector shift");
8702 case Intrinsic::arm_neon_vshifts:
8703 case Intrinsic::arm_neon_vshiftu:
8704 // Opcode already set above.
8706 case Intrinsic::arm_neon_vshiftls:
8707 case Intrinsic::arm_neon_vshiftlu:
8708 if (Cnt == VT.getVectorElementType().getSizeInBits())
8709 VShiftOpc = ARMISD::VSHLLi;
8711 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
8712 ARMISD::VSHLLs : ARMISD::VSHLLu);
8714 case Intrinsic::arm_neon_vshiftn:
8715 VShiftOpc = ARMISD::VSHRN; break;
8716 case Intrinsic::arm_neon_vrshifts:
8717 VShiftOpc = ARMISD::VRSHRs; break;
8718 case Intrinsic::arm_neon_vrshiftu:
8719 VShiftOpc = ARMISD::VRSHRu; break;
8720 case Intrinsic::arm_neon_vrshiftn:
8721 VShiftOpc = ARMISD::VRSHRN; break;
8722 case Intrinsic::arm_neon_vqshifts:
8723 VShiftOpc = ARMISD::VQSHLs; break;
8724 case Intrinsic::arm_neon_vqshiftu:
8725 VShiftOpc = ARMISD::VQSHLu; break;
8726 case Intrinsic::arm_neon_vqshiftsu:
8727 VShiftOpc = ARMISD::VQSHLsu; break;
8728 case Intrinsic::arm_neon_vqshiftns:
8729 VShiftOpc = ARMISD::VQSHRNs; break;
8730 case Intrinsic::arm_neon_vqshiftnu:
8731 VShiftOpc = ARMISD::VQSHRNu; break;
8732 case Intrinsic::arm_neon_vqshiftnsu:
8733 VShiftOpc = ARMISD::VQSHRNsu; break;
8734 case Intrinsic::arm_neon_vqrshiftns:
8735 VShiftOpc = ARMISD::VQRSHRNs; break;
8736 case Intrinsic::arm_neon_vqrshiftnu:
8737 VShiftOpc = ARMISD::VQRSHRNu; break;
8738 case Intrinsic::arm_neon_vqrshiftnsu:
8739 VShiftOpc = ARMISD::VQRSHRNsu; break;
8742 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
8743 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
8746 case Intrinsic::arm_neon_vshiftins: {
8747 EVT VT = N->getOperand(1).getValueType();
8749 unsigned VShiftOpc = 0;
8751 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
8752 VShiftOpc = ARMISD::VSLI;
8753 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
8754 VShiftOpc = ARMISD::VSRI;
8756 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
8759 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
8760 N->getOperand(1), N->getOperand(2),
8761 DAG.getConstant(Cnt, MVT::i32));
8764 case Intrinsic::arm_neon_vqrshifts:
8765 case Intrinsic::arm_neon_vqrshiftu:
8766 // No immediate versions of these to check for.
8773 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
8774 /// lowers them. As with the vector shift intrinsics, this is done during DAG
8775 /// combining instead of DAG legalizing because the build_vectors for 64-bit
8776 /// vector element shift counts are generally not legal, and it is hard to see
8777 /// their values after they get legalized to loads from a constant pool.
8778 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
8779 const ARMSubtarget *ST) {
8780 EVT VT = N->getValueType(0);
8781 if (N->getOpcode() == ISD::SRL && VT == MVT::i32 && ST->hasV6Ops()) {
8782 // Canonicalize (srl (bswap x), 16) to (rotr (bswap x), 16) if the high
8783 // 16-bits of x is zero. This optimizes rev + lsr 16 to rev16.
8784 SDValue N1 = N->getOperand(1);
8785 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
8786 SDValue N0 = N->getOperand(0);
8787 if (C->getZExtValue() == 16 && N0.getOpcode() == ISD::BSWAP &&
8788 DAG.MaskedValueIsZero(N0.getOperand(0),
8789 APInt::getHighBitsSet(32, 16)))
8790 return DAG.getNode(ISD::ROTR, N->getDebugLoc(), VT, N0, N1);
8794 // Nothing to be done for scalar shifts.
8795 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8796 if (!VT.isVector() || !TLI.isTypeLegal(VT))
8799 assert(ST->hasNEON() && "unexpected vector shift");
8802 switch (N->getOpcode()) {
8803 default: llvm_unreachable("unexpected shift opcode");
8806 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
8807 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
8808 DAG.getConstant(Cnt, MVT::i32));
8813 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
8814 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
8815 ARMISD::VSHRs : ARMISD::VSHRu);
8816 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
8817 DAG.getConstant(Cnt, MVT::i32));
8823 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
8824 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
8825 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
8826 const ARMSubtarget *ST) {
8827 SDValue N0 = N->getOperand(0);
8829 // Check for sign- and zero-extensions of vector extract operations of 8-
8830 // and 16-bit vector elements. NEON supports these directly. They are
8831 // handled during DAG combining because type legalization will promote them
8832 // to 32-bit types and it is messy to recognize the operations after that.
8833 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
8834 SDValue Vec = N0.getOperand(0);
8835 SDValue Lane = N0.getOperand(1);
8836 EVT VT = N->getValueType(0);
8837 EVT EltVT = N0.getValueType();
8838 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8840 if (VT == MVT::i32 &&
8841 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
8842 TLI.isTypeLegal(Vec.getValueType()) &&
8843 isa<ConstantSDNode>(Lane)) {
8846 switch (N->getOpcode()) {
8847 default: llvm_unreachable("unexpected opcode");
8848 case ISD::SIGN_EXTEND:
8849 Opc = ARMISD::VGETLANEs;
8851 case ISD::ZERO_EXTEND:
8852 case ISD::ANY_EXTEND:
8853 Opc = ARMISD::VGETLANEu;
8856 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
8863 /// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
8864 /// to match f32 max/min patterns to use NEON vmax/vmin instructions.
8865 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
8866 const ARMSubtarget *ST) {
8867 // If the target supports NEON, try to use vmax/vmin instructions for f32
8868 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set,
8869 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
8870 // a NaN; only do the transformation when it matches that behavior.
8872 // For now only do this when using NEON for FP operations; if using VFP, it
8873 // is not obvious that the benefit outweighs the cost of switching to the
8875 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
8876 N->getValueType(0) != MVT::f32)
8879 SDValue CondLHS = N->getOperand(0);
8880 SDValue CondRHS = N->getOperand(1);
8881 SDValue LHS = N->getOperand(2);
8882 SDValue RHS = N->getOperand(3);
8883 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
8885 unsigned Opcode = 0;
8887 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
8888 IsReversed = false; // x CC y ? x : y
8889 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
8890 IsReversed = true ; // x CC y ? y : x
8904 // If LHS is NaN, an ordered comparison will be false and the result will
8905 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
8906 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
8907 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
8908 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
8910 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
8911 // will return -0, so vmin can only be used for unsafe math or if one of
8912 // the operands is known to be nonzero.
8913 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
8914 !DAG.getTarget().Options.UnsafeFPMath &&
8915 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
8917 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
8926 // If LHS is NaN, an ordered comparison will be false and the result will
8927 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
8928 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
8929 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
8930 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
8932 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
8933 // will return +0, so vmax can only be used for unsafe math or if one of
8934 // the operands is known to be nonzero.
8935 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
8936 !DAG.getTarget().Options.UnsafeFPMath &&
8937 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
8939 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
8945 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS);
8948 /// PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV.
8950 ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const {
8951 SDValue Cmp = N->getOperand(4);
8952 if (Cmp.getOpcode() != ARMISD::CMPZ)
8953 // Only looking at EQ and NE cases.
8956 EVT VT = N->getValueType(0);
8957 DebugLoc dl = N->getDebugLoc();
8958 SDValue LHS = Cmp.getOperand(0);
8959 SDValue RHS = Cmp.getOperand(1);
8960 SDValue FalseVal = N->getOperand(0);
8961 SDValue TrueVal = N->getOperand(1);
8962 SDValue ARMcc = N->getOperand(2);
8963 ARMCC::CondCodes CC =
8964 (ARMCC::CondCodes)cast<ConstantSDNode>(ARMcc)->getZExtValue();
8982 /// FIXME: Turn this into a target neutral optimization?
8984 if (CC == ARMCC::NE && FalseVal == RHS && FalseVal != LHS) {
8985 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, TrueVal, ARMcc,
8986 N->getOperand(3), Cmp);
8987 } else if (CC == ARMCC::EQ && TrueVal == RHS) {
8989 SDValue NewCmp = getARMCmp(LHS, RHS, ISD::SETNE, ARMcc, DAG, dl);
8990 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, FalseVal, ARMcc,
8991 N->getOperand(3), NewCmp);
8994 if (Res.getNode()) {
8995 APInt KnownZero, KnownOne;
8996 DAG.ComputeMaskedBits(SDValue(N,0), KnownZero, KnownOne);
8997 // Capture demanded bits information that would be otherwise lost.
8998 if (KnownZero == 0xfffffffe)
8999 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
9000 DAG.getValueType(MVT::i1));
9001 else if (KnownZero == 0xffffff00)
9002 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
9003 DAG.getValueType(MVT::i8));
9004 else if (KnownZero == 0xffff0000)
9005 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
9006 DAG.getValueType(MVT::i16));
9012 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
9013 DAGCombinerInfo &DCI) const {
9014 switch (N->getOpcode()) {
9016 case ISD::ADDC: return PerformADDCCombine(N, DCI, Subtarget);
9017 case ISD::ADD: return PerformADDCombine(N, DCI, Subtarget);
9018 case ISD::SUB: return PerformSUBCombine(N, DCI);
9019 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
9020 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
9021 case ISD::XOR: return PerformXORCombine(N, DCI, Subtarget);
9022 case ISD::AND: return PerformANDCombine(N, DCI, Subtarget);
9023 case ARMISD::BFI: return PerformBFICombine(N, DCI);
9024 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
9025 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
9026 case ISD::STORE: return PerformSTORECombine(N, DCI);
9027 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI);
9028 case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI);
9029 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
9030 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
9031 case ISD::FP_TO_SINT:
9032 case ISD::FP_TO_UINT: return PerformVCVTCombine(N, DCI, Subtarget);
9033 case ISD::FDIV: return PerformVDIVCombine(N, DCI, Subtarget);
9034 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
9037 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
9038 case ISD::SIGN_EXTEND:
9039 case ISD::ZERO_EXTEND:
9040 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
9041 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
9042 case ARMISD::CMOV: return PerformCMOVCombine(N, DCI.DAG);
9043 case ARMISD::VLD2DUP:
9044 case ARMISD::VLD3DUP:
9045 case ARMISD::VLD4DUP:
9046 return CombineBaseUpdate(N, DCI);
9047 case ISD::INTRINSIC_VOID:
9048 case ISD::INTRINSIC_W_CHAIN:
9049 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9050 case Intrinsic::arm_neon_vld1:
9051 case Intrinsic::arm_neon_vld2:
9052 case Intrinsic::arm_neon_vld3:
9053 case Intrinsic::arm_neon_vld4:
9054 case Intrinsic::arm_neon_vld2lane:
9055 case Intrinsic::arm_neon_vld3lane:
9056 case Intrinsic::arm_neon_vld4lane:
9057 case Intrinsic::arm_neon_vst1:
9058 case Intrinsic::arm_neon_vst2:
9059 case Intrinsic::arm_neon_vst3:
9060 case Intrinsic::arm_neon_vst4:
9061 case Intrinsic::arm_neon_vst2lane:
9062 case Intrinsic::arm_neon_vst3lane:
9063 case Intrinsic::arm_neon_vst4lane:
9064 return CombineBaseUpdate(N, DCI);
9072 bool ARMTargetLowering::isDesirableToTransformToIntegerOp(unsigned Opc,
9074 return (VT == MVT::f32) && (Opc == ISD::LOAD || Opc == ISD::STORE);
9077 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
9078 // The AllowsUnaliged flag models the SCTLR.A setting in ARM cpus
9079 bool AllowsUnaligned = Subtarget->allowsUnalignedMem();
9081 switch (VT.getSimpleVT().SimpleTy) {
9087 // Unaligned access can use (for example) LRDB, LRDH, LDR
9088 return AllowsUnaligned;
9091 // For any little-endian targets with neon, we can support unaligned ld/st
9092 // of D and Q (e.g. {D0,D1}) registers by using vld1.i8/vst1.i8.
9093 // A big-endian target may also explictly support unaligned accesses
9094 return Subtarget->hasNEON() && (AllowsUnaligned || isLittleEndian());
9098 static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign,
9099 unsigned AlignCheck) {
9100 return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) &&
9101 (DstAlign == 0 || DstAlign % AlignCheck == 0));
9104 EVT ARMTargetLowering::getOptimalMemOpType(uint64_t Size,
9105 unsigned DstAlign, unsigned SrcAlign,
9108 MachineFunction &MF) const {
9109 const Function *F = MF.getFunction();
9111 // See if we can use NEON instructions for this...
9113 !F->getFnAttributes().hasAttribute(Attributes::NoImplicitFloat) &&
9114 Subtarget->hasNEON()) {
9115 if (memOpAlign(SrcAlign, DstAlign, 16) && Size >= 16) {
9117 } else if (memOpAlign(SrcAlign, DstAlign, 8) && Size >= 8) {
9122 // Lowering to i32/i16 if the size permits.
9125 } else if (Size >= 2) {
9129 // Let the target-independent logic figure it out.
9133 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
9138 switch (VT.getSimpleVT().SimpleTy) {
9139 default: return false;
9154 if ((V & (Scale - 1)) != 0)
9157 return V == (V & ((1LL << 5) - 1));
9160 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
9161 const ARMSubtarget *Subtarget) {
9168 switch (VT.getSimpleVT().SimpleTy) {
9169 default: return false;
9174 // + imm12 or - imm8
9176 return V == (V & ((1LL << 8) - 1));
9177 return V == (V & ((1LL << 12) - 1));
9180 // Same as ARM mode. FIXME: NEON?
9181 if (!Subtarget->hasVFP2())
9186 return V == (V & ((1LL << 8) - 1));
9190 /// isLegalAddressImmediate - Return true if the integer value can be used
9191 /// as the offset of the target addressing mode for load / store of the
9193 static bool isLegalAddressImmediate(int64_t V, EVT VT,
9194 const ARMSubtarget *Subtarget) {
9201 if (Subtarget->isThumb1Only())
9202 return isLegalT1AddressImmediate(V, VT);
9203 else if (Subtarget->isThumb2())
9204 return isLegalT2AddressImmediate(V, VT, Subtarget);
9209 switch (VT.getSimpleVT().SimpleTy) {
9210 default: return false;
9215 return V == (V & ((1LL << 12) - 1));
9218 return V == (V & ((1LL << 8) - 1));
9221 if (!Subtarget->hasVFP2()) // FIXME: NEON?
9226 return V == (V & ((1LL << 8) - 1));
9230 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
9232 int Scale = AM.Scale;
9236 switch (VT.getSimpleVT().SimpleTy) {
9237 default: return false;
9246 return Scale == 2 || Scale == 4 || Scale == 8;
9249 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
9253 // Note, we allow "void" uses (basically, uses that aren't loads or
9254 // stores), because arm allows folding a scale into many arithmetic
9255 // operations. This should be made more precise and revisited later.
9257 // Allow r << imm, but the imm has to be a multiple of two.
9258 if (Scale & 1) return false;
9259 return isPowerOf2_32(Scale);
9263 /// isLegalAddressingMode - Return true if the addressing mode represented
9264 /// by AM is legal for this target, for a load/store of the specified type.
9265 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
9267 EVT VT = getValueType(Ty, true);
9268 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
9271 // Can never fold addr of global into load/store.
9276 case 0: // no scale reg, must be "r+i" or "r", or "i".
9279 if (Subtarget->isThumb1Only())
9283 // ARM doesn't support any R+R*scale+imm addr modes.
9290 if (Subtarget->isThumb2())
9291 return isLegalT2ScaledAddressingMode(AM, VT);
9293 int Scale = AM.Scale;
9294 switch (VT.getSimpleVT().SimpleTy) {
9295 default: return false;
9299 if (Scale < 0) Scale = -Scale;
9303 return isPowerOf2_32(Scale & ~1);
9307 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
9312 // Note, we allow "void" uses (basically, uses that aren't loads or
9313 // stores), because arm allows folding a scale into many arithmetic
9314 // operations. This should be made more precise and revisited later.
9316 // Allow r << imm, but the imm has to be a multiple of two.
9317 if (Scale & 1) return false;
9318 return isPowerOf2_32(Scale);
9324 /// isLegalICmpImmediate - Return true if the specified immediate is legal
9325 /// icmp immediate, that is the target has icmp instructions which can compare
9326 /// a register against the immediate without having to materialize the
9327 /// immediate into a register.
9328 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
9329 // Thumb2 and ARM modes can use cmn for negative immediates.
9330 if (!Subtarget->isThumb())
9331 return ARM_AM::getSOImmVal(llvm::abs64(Imm)) != -1;
9332 if (Subtarget->isThumb2())
9333 return ARM_AM::getT2SOImmVal(llvm::abs64(Imm)) != -1;
9334 // Thumb1 doesn't have cmn, and only 8-bit immediates.
9335 return Imm >= 0 && Imm <= 255;
9338 /// isLegalAddImmediate - Return true if the specified immediate is a legal add
9339 /// *or sub* immediate, that is the target has add or sub instructions which can
9340 /// add a register with the immediate without having to materialize the
9341 /// immediate into a register.
9342 bool ARMTargetLowering::isLegalAddImmediate(int64_t Imm) const {
9343 // Same encoding for add/sub, just flip the sign.
9344 int64_t AbsImm = llvm::abs64(Imm);
9345 if (!Subtarget->isThumb())
9346 return ARM_AM::getSOImmVal(AbsImm) != -1;
9347 if (Subtarget->isThumb2())
9348 return ARM_AM::getT2SOImmVal(AbsImm) != -1;
9349 // Thumb1 only has 8-bit unsigned immediate.
9350 return AbsImm >= 0 && AbsImm <= 255;
9353 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
9354 bool isSEXTLoad, SDValue &Base,
9355 SDValue &Offset, bool &isInc,
9356 SelectionDAG &DAG) {
9357 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
9360 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
9362 Base = Ptr->getOperand(0);
9363 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
9364 int RHSC = (int)RHS->getZExtValue();
9365 if (RHSC < 0 && RHSC > -256) {
9366 assert(Ptr->getOpcode() == ISD::ADD);
9368 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
9372 isInc = (Ptr->getOpcode() == ISD::ADD);
9373 Offset = Ptr->getOperand(1);
9375 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
9377 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
9378 int RHSC = (int)RHS->getZExtValue();
9379 if (RHSC < 0 && RHSC > -0x1000) {
9380 assert(Ptr->getOpcode() == ISD::ADD);
9382 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
9383 Base = Ptr->getOperand(0);
9388 if (Ptr->getOpcode() == ISD::ADD) {
9390 ARM_AM::ShiftOpc ShOpcVal=
9391 ARM_AM::getShiftOpcForNode(Ptr->getOperand(0).getOpcode());
9392 if (ShOpcVal != ARM_AM::no_shift) {
9393 Base = Ptr->getOperand(1);
9394 Offset = Ptr->getOperand(0);
9396 Base = Ptr->getOperand(0);
9397 Offset = Ptr->getOperand(1);
9402 isInc = (Ptr->getOpcode() == ISD::ADD);
9403 Base = Ptr->getOperand(0);
9404 Offset = Ptr->getOperand(1);
9408 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
9412 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
9413 bool isSEXTLoad, SDValue &Base,
9414 SDValue &Offset, bool &isInc,
9415 SelectionDAG &DAG) {
9416 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
9419 Base = Ptr->getOperand(0);
9420 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
9421 int RHSC = (int)RHS->getZExtValue();
9422 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
9423 assert(Ptr->getOpcode() == ISD::ADD);
9425 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
9427 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
9428 isInc = Ptr->getOpcode() == ISD::ADD;
9429 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
9437 /// getPreIndexedAddressParts - returns true by value, base pointer and
9438 /// offset pointer and addressing mode by reference if the node's address
9439 /// can be legally represented as pre-indexed load / store address.
9441 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
9443 ISD::MemIndexedMode &AM,
9444 SelectionDAG &DAG) const {
9445 if (Subtarget->isThumb1Only())
9450 bool isSEXTLoad = false;
9451 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
9452 Ptr = LD->getBasePtr();
9453 VT = LD->getMemoryVT();
9454 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
9455 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
9456 Ptr = ST->getBasePtr();
9457 VT = ST->getMemoryVT();
9462 bool isLegal = false;
9463 if (Subtarget->isThumb2())
9464 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
9465 Offset, isInc, DAG);
9467 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
9468 Offset, isInc, DAG);
9472 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
9476 /// getPostIndexedAddressParts - returns true by value, base pointer and
9477 /// offset pointer and addressing mode by reference if this node can be
9478 /// combined with a load / store to form a post-indexed load / store.
9479 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
9482 ISD::MemIndexedMode &AM,
9483 SelectionDAG &DAG) const {
9484 if (Subtarget->isThumb1Only())
9489 bool isSEXTLoad = false;
9490 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
9491 VT = LD->getMemoryVT();
9492 Ptr = LD->getBasePtr();
9493 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
9494 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
9495 VT = ST->getMemoryVT();
9496 Ptr = ST->getBasePtr();
9501 bool isLegal = false;
9502 if (Subtarget->isThumb2())
9503 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
9506 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
9512 // Swap base ptr and offset to catch more post-index load / store when
9513 // it's legal. In Thumb2 mode, offset must be an immediate.
9514 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
9515 !Subtarget->isThumb2())
9516 std::swap(Base, Offset);
9518 // Post-indexed load / store update the base pointer.
9523 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
9527 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
9530 const SelectionDAG &DAG,
9531 unsigned Depth) const {
9532 KnownZero = KnownOne = APInt(KnownOne.getBitWidth(), 0);
9533 switch (Op.getOpcode()) {
9535 case ARMISD::CMOV: {
9536 // Bits are known zero/one if known on the LHS and RHS.
9537 DAG.ComputeMaskedBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1);
9538 if (KnownZero == 0 && KnownOne == 0) return;
9540 APInt KnownZeroRHS, KnownOneRHS;
9541 DAG.ComputeMaskedBits(Op.getOperand(1), KnownZeroRHS, KnownOneRHS, Depth+1);
9542 KnownZero &= KnownZeroRHS;
9543 KnownOne &= KnownOneRHS;
9549 //===----------------------------------------------------------------------===//
9550 // ARM Inline Assembly Support
9551 //===----------------------------------------------------------------------===//
9553 bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const {
9554 // Looking for "rev" which is V6+.
9555 if (!Subtarget->hasV6Ops())
9558 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
9559 std::string AsmStr = IA->getAsmString();
9560 SmallVector<StringRef, 4> AsmPieces;
9561 SplitString(AsmStr, AsmPieces, ";\n");
9563 switch (AsmPieces.size()) {
9564 default: return false;
9566 AsmStr = AsmPieces[0];
9568 SplitString(AsmStr, AsmPieces, " \t,");
9571 if (AsmPieces.size() == 3 &&
9572 AsmPieces[0] == "rev" && AsmPieces[1] == "$0" && AsmPieces[2] == "$1" &&
9573 IA->getConstraintString().compare(0, 4, "=l,l") == 0) {
9574 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
9575 if (Ty && Ty->getBitWidth() == 32)
9576 return IntrinsicLowering::LowerToByteSwap(CI);
9584 /// getConstraintType - Given a constraint letter, return the type of
9585 /// constraint it is for this target.
9586 ARMTargetLowering::ConstraintType
9587 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
9588 if (Constraint.size() == 1) {
9589 switch (Constraint[0]) {
9591 case 'l': return C_RegisterClass;
9592 case 'w': return C_RegisterClass;
9593 case 'h': return C_RegisterClass;
9594 case 'x': return C_RegisterClass;
9595 case 't': return C_RegisterClass;
9596 case 'j': return C_Other; // Constant for movw.
9597 // An address with a single base register. Due to the way we
9598 // currently handle addresses it is the same as an 'r' memory constraint.
9599 case 'Q': return C_Memory;
9601 } else if (Constraint.size() == 2) {
9602 switch (Constraint[0]) {
9604 // All 'U+' constraints are addresses.
9605 case 'U': return C_Memory;
9608 return TargetLowering::getConstraintType(Constraint);
9611 /// Examine constraint type and operand type and determine a weight value.
9612 /// This object must already have been set up with the operand type
9613 /// and the current alternative constraint selected.
9614 TargetLowering::ConstraintWeight
9615 ARMTargetLowering::getSingleConstraintMatchWeight(
9616 AsmOperandInfo &info, const char *constraint) const {
9617 ConstraintWeight weight = CW_Invalid;
9618 Value *CallOperandVal = info.CallOperandVal;
9619 // If we don't have a value, we can't do a match,
9620 // but allow it at the lowest weight.
9621 if (CallOperandVal == NULL)
9623 Type *type = CallOperandVal->getType();
9624 // Look at the constraint type.
9625 switch (*constraint) {
9627 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
9630 if (type->isIntegerTy()) {
9631 if (Subtarget->isThumb())
9632 weight = CW_SpecificReg;
9634 weight = CW_Register;
9638 if (type->isFloatingPointTy())
9639 weight = CW_Register;
9645 typedef std::pair<unsigned, const TargetRegisterClass*> RCPair;
9647 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
9649 if (Constraint.size() == 1) {
9650 // GCC ARM Constraint Letters
9651 switch (Constraint[0]) {
9652 case 'l': // Low regs or general regs.
9653 if (Subtarget->isThumb())
9654 return RCPair(0U, &ARM::tGPRRegClass);
9655 return RCPair(0U, &ARM::GPRRegClass);
9656 case 'h': // High regs or no regs.
9657 if (Subtarget->isThumb())
9658 return RCPair(0U, &ARM::hGPRRegClass);
9661 return RCPair(0U, &ARM::GPRRegClass);
9664 return RCPair(0U, &ARM::SPRRegClass);
9665 if (VT.getSizeInBits() == 64)
9666 return RCPair(0U, &ARM::DPRRegClass);
9667 if (VT.getSizeInBits() == 128)
9668 return RCPair(0U, &ARM::QPRRegClass);
9672 return RCPair(0U, &ARM::SPR_8RegClass);
9673 if (VT.getSizeInBits() == 64)
9674 return RCPair(0U, &ARM::DPR_8RegClass);
9675 if (VT.getSizeInBits() == 128)
9676 return RCPair(0U, &ARM::QPR_8RegClass);
9680 return RCPair(0U, &ARM::SPRRegClass);
9684 if (StringRef("{cc}").equals_lower(Constraint))
9685 return std::make_pair(unsigned(ARM::CPSR), &ARM::CCRRegClass);
9687 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
9690 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
9691 /// vector. If it is invalid, don't add anything to Ops.
9692 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
9693 std::string &Constraint,
9694 std::vector<SDValue>&Ops,
9695 SelectionDAG &DAG) const {
9696 SDValue Result(0, 0);
9698 // Currently only support length 1 constraints.
9699 if (Constraint.length() != 1) return;
9701 char ConstraintLetter = Constraint[0];
9702 switch (ConstraintLetter) {
9705 case 'I': case 'J': case 'K': case 'L':
9706 case 'M': case 'N': case 'O':
9707 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
9711 int64_t CVal64 = C->getSExtValue();
9712 int CVal = (int) CVal64;
9713 // None of these constraints allow values larger than 32 bits. Check
9714 // that the value fits in an int.
9718 switch (ConstraintLetter) {
9720 // Constant suitable for movw, must be between 0 and
9722 if (Subtarget->hasV6T2Ops())
9723 if (CVal >= 0 && CVal <= 65535)
9727 if (Subtarget->isThumb1Only()) {
9728 // This must be a constant between 0 and 255, for ADD
9730 if (CVal >= 0 && CVal <= 255)
9732 } else if (Subtarget->isThumb2()) {
9733 // A constant that can be used as an immediate value in a
9734 // data-processing instruction.
9735 if (ARM_AM::getT2SOImmVal(CVal) != -1)
9738 // A constant that can be used as an immediate value in a
9739 // data-processing instruction.
9740 if (ARM_AM::getSOImmVal(CVal) != -1)
9746 if (Subtarget->isThumb()) { // FIXME thumb2
9747 // This must be a constant between -255 and -1, for negated ADD
9748 // immediates. This can be used in GCC with an "n" modifier that
9749 // prints the negated value, for use with SUB instructions. It is
9750 // not useful otherwise but is implemented for compatibility.
9751 if (CVal >= -255 && CVal <= -1)
9754 // This must be a constant between -4095 and 4095. It is not clear
9755 // what this constraint is intended for. Implemented for
9756 // compatibility with GCC.
9757 if (CVal >= -4095 && CVal <= 4095)
9763 if (Subtarget->isThumb1Only()) {
9764 // A 32-bit value where only one byte has a nonzero value. Exclude
9765 // zero to match GCC. This constraint is used by GCC internally for
9766 // constants that can be loaded with a move/shift combination.
9767 // It is not useful otherwise but is implemented for compatibility.
9768 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
9770 } else if (Subtarget->isThumb2()) {
9771 // A constant whose bitwise inverse can be used as an immediate
9772 // value in a data-processing instruction. This can be used in GCC
9773 // with a "B" modifier that prints the inverted value, for use with
9774 // BIC and MVN instructions. It is not useful otherwise but is
9775 // implemented for compatibility.
9776 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
9779 // A constant whose bitwise inverse can be used as an immediate
9780 // value in a data-processing instruction. This can be used in GCC
9781 // with a "B" modifier that prints the inverted value, for use with
9782 // BIC and MVN instructions. It is not useful otherwise but is
9783 // implemented for compatibility.
9784 if (ARM_AM::getSOImmVal(~CVal) != -1)
9790 if (Subtarget->isThumb1Only()) {
9791 // This must be a constant between -7 and 7,
9792 // for 3-operand ADD/SUB immediate instructions.
9793 if (CVal >= -7 && CVal < 7)
9795 } else if (Subtarget->isThumb2()) {
9796 // A constant whose negation can be used as an immediate value in a
9797 // data-processing instruction. This can be used in GCC with an "n"
9798 // modifier that prints the negated value, for use with SUB
9799 // instructions. It is not useful otherwise but is implemented for
9801 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
9804 // A constant whose negation can be used as an immediate value in a
9805 // data-processing instruction. This can be used in GCC with an "n"
9806 // modifier that prints the negated value, for use with SUB
9807 // instructions. It is not useful otherwise but is implemented for
9809 if (ARM_AM::getSOImmVal(-CVal) != -1)
9815 if (Subtarget->isThumb()) { // FIXME thumb2
9816 // This must be a multiple of 4 between 0 and 1020, for
9817 // ADD sp + immediate.
9818 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
9821 // A power of two or a constant between 0 and 32. This is used in
9822 // GCC for the shift amount on shifted register operands, but it is
9823 // useful in general for any shift amounts.
9824 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
9830 if (Subtarget->isThumb()) { // FIXME thumb2
9831 // This must be a constant between 0 and 31, for shift amounts.
9832 if (CVal >= 0 && CVal <= 31)
9838 if (Subtarget->isThumb()) { // FIXME thumb2
9839 // This must be a multiple of 4 between -508 and 508, for
9840 // ADD/SUB sp = sp + immediate.
9841 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
9846 Result = DAG.getTargetConstant(CVal, Op.getValueType());
9850 if (Result.getNode()) {
9851 Ops.push_back(Result);
9854 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
9858 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
9859 // The ARM target isn't yet aware of offsets.
9863 bool ARM::isBitFieldInvertedMask(unsigned v) {
9864 if (v == 0xffffffff)
9866 // there can be 1's on either or both "outsides", all the "inside"
9868 unsigned int lsb = 0, msb = 31;
9869 while (v & (1 << msb)) --msb;
9870 while (v & (1 << lsb)) ++lsb;
9871 for (unsigned int i = lsb; i <= msb; ++i) {
9878 /// isFPImmLegal - Returns true if the target can instruction select the
9879 /// specified FP immediate natively. If false, the legalizer will
9880 /// materialize the FP immediate as a load from a constant pool.
9881 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
9882 if (!Subtarget->hasVFP3())
9885 return ARM_AM::getFP32Imm(Imm) != -1;
9887 return ARM_AM::getFP64Imm(Imm) != -1;
9891 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
9892 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
9893 /// specified in the intrinsic calls.
9894 bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
9896 unsigned Intrinsic) const {
9897 switch (Intrinsic) {
9898 case Intrinsic::arm_neon_vld1:
9899 case Intrinsic::arm_neon_vld2:
9900 case Intrinsic::arm_neon_vld3:
9901 case Intrinsic::arm_neon_vld4:
9902 case Intrinsic::arm_neon_vld2lane:
9903 case Intrinsic::arm_neon_vld3lane:
9904 case Intrinsic::arm_neon_vld4lane: {
9905 Info.opc = ISD::INTRINSIC_W_CHAIN;
9906 // Conservatively set memVT to the entire set of vectors loaded.
9907 uint64_t NumElts = getDataLayout()->getTypeAllocSize(I.getType()) / 8;
9908 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
9909 Info.ptrVal = I.getArgOperand(0);
9911 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
9912 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
9913 Info.vol = false; // volatile loads with NEON intrinsics not supported
9914 Info.readMem = true;
9915 Info.writeMem = false;
9918 case Intrinsic::arm_neon_vst1:
9919 case Intrinsic::arm_neon_vst2:
9920 case Intrinsic::arm_neon_vst3:
9921 case Intrinsic::arm_neon_vst4:
9922 case Intrinsic::arm_neon_vst2lane:
9923 case Intrinsic::arm_neon_vst3lane:
9924 case Intrinsic::arm_neon_vst4lane: {
9925 Info.opc = ISD::INTRINSIC_VOID;
9926 // Conservatively set memVT to the entire set of vectors stored.
9927 unsigned NumElts = 0;
9928 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
9929 Type *ArgTy = I.getArgOperand(ArgI)->getType();
9930 if (!ArgTy->isVectorTy())
9932 NumElts += getDataLayout()->getTypeAllocSize(ArgTy) / 8;
9934 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
9935 Info.ptrVal = I.getArgOperand(0);
9937 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
9938 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
9939 Info.vol = false; // volatile stores with NEON intrinsics not supported
9940 Info.readMem = false;
9941 Info.writeMem = true;
9944 case Intrinsic::arm_strexd: {
9945 Info.opc = ISD::INTRINSIC_W_CHAIN;
9946 Info.memVT = MVT::i64;
9947 Info.ptrVal = I.getArgOperand(2);
9951 Info.readMem = false;
9952 Info.writeMem = true;
9955 case Intrinsic::arm_ldrexd: {
9956 Info.opc = ISD::INTRINSIC_W_CHAIN;
9957 Info.memVT = MVT::i64;
9958 Info.ptrVal = I.getArgOperand(0);
9962 Info.readMem = true;
9963 Info.writeMem = false;