1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "arm-isel"
17 #include "ARMAddressingModes.h"
18 #include "ARMCallingConv.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMISelLowering.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMPerfectShuffle.h"
23 #include "ARMRegisterInfo.h"
24 #include "ARMSubtarget.h"
25 #include "ARMTargetMachine.h"
26 #include "ARMTargetObjectFile.h"
27 #include "llvm/CallingConv.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Function.h"
30 #include "llvm/GlobalValue.h"
31 #include "llvm/Instruction.h"
32 #include "llvm/Instructions.h"
33 #include "llvm/Intrinsics.h"
34 #include "llvm/Type.h"
35 #include "llvm/CodeGen/CallingConvLower.h"
36 #include "llvm/CodeGen/IntrinsicLowering.h"
37 #include "llvm/CodeGen/MachineBasicBlock.h"
38 #include "llvm/CodeGen/MachineFrameInfo.h"
39 #include "llvm/CodeGen/MachineFunction.h"
40 #include "llvm/CodeGen/MachineInstrBuilder.h"
41 #include "llvm/CodeGen/MachineRegisterInfo.h"
42 #include "llvm/CodeGen/PseudoSourceValue.h"
43 #include "llvm/CodeGen/SelectionDAG.h"
44 #include "llvm/MC/MCSectionMachO.h"
45 #include "llvm/Target/TargetOptions.h"
46 #include "llvm/ADT/VectorExtras.h"
47 #include "llvm/ADT/StringExtras.h"
48 #include "llvm/ADT/Statistic.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Support/raw_ostream.h"
56 STATISTIC(NumTailCalls, "Number of tail calls");
57 STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt");
59 // This option should go away when tail calls fully work.
61 EnableARMTailCalls("arm-tail-calls", cl::Hidden,
62 cl::desc("Generate tail calls (TEMPORARY OPTION)."),
66 EnableARMLongCalls("arm-long-calls", cl::Hidden,
67 cl::desc("Generate calls via indirect call instructions"),
71 ARMInterworking("arm-interworking", cl::Hidden,
72 cl::desc("Enable / disable ARM interworking (for debugging only)"),
75 // The APCS parameter registers.
76 static const unsigned GPRArgRegs[] = {
77 ARM::R0, ARM::R1, ARM::R2, ARM::R3
80 void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
81 EVT PromotedBitwiseVT) {
82 if (VT != PromotedLdStVT) {
83 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
84 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
85 PromotedLdStVT.getSimpleVT());
87 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
88 AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
89 PromotedLdStVT.getSimpleVT());
92 EVT ElemTy = VT.getVectorElementType();
93 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
94 setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
95 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
96 if (ElemTy != MVT::i32) {
97 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
98 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand);
99 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand);
100 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand);
102 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
103 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
104 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
105 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Legal);
106 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
107 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
108 if (VT.isInteger()) {
109 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
110 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
111 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
112 setLoadExtAction(ISD::SEXTLOAD, VT.getSimpleVT(), Expand);
113 setLoadExtAction(ISD::ZEXTLOAD, VT.getSimpleVT(), Expand);
114 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
115 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
116 setTruncStoreAction(VT.getSimpleVT(),
117 (MVT::SimpleValueType)InnerVT, Expand);
119 setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand);
121 // Promote all bit-wise operations.
122 if (VT.isInteger() && VT != PromotedBitwiseVT) {
123 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
124 AddPromotedToType (ISD::AND, VT.getSimpleVT(),
125 PromotedBitwiseVT.getSimpleVT());
126 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
127 AddPromotedToType (ISD::OR, VT.getSimpleVT(),
128 PromotedBitwiseVT.getSimpleVT());
129 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
130 AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
131 PromotedBitwiseVT.getSimpleVT());
134 // Neon does not support vector divide/remainder operations.
135 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
136 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
137 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand);
138 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
139 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
140 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
143 void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
144 addRegisterClass(VT, ARM::DPRRegisterClass);
145 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
148 void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
149 addRegisterClass(VT, ARM::QPRRegisterClass);
150 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
153 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
154 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
155 return new TargetLoweringObjectFileMachO();
157 return new ARMElfTargetObjectFile();
160 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
161 : TargetLowering(TM, createTLOF(TM)) {
162 Subtarget = &TM.getSubtarget<ARMSubtarget>();
163 RegInfo = TM.getRegisterInfo();
164 Itins = TM.getInstrItineraryData();
166 if (Subtarget->isTargetDarwin()) {
167 // Uses VFP for Thumb libfuncs if available.
168 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
169 // Single-precision floating-point arithmetic.
170 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
171 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
172 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
173 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
175 // Double-precision floating-point arithmetic.
176 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
177 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
178 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
179 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
181 // Single-precision comparisons.
182 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
183 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
184 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
185 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
186 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
187 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
188 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
189 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
191 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
192 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
193 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
194 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
195 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
196 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
197 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
198 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
200 // Double-precision comparisons.
201 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
202 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
203 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
204 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
205 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
206 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
207 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
208 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
210 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
211 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
212 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
213 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
214 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
215 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
216 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
217 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
219 // Floating-point to integer conversions.
220 // i64 conversions are done via library routines even when generating VFP
221 // instructions, so use the same ones.
222 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
223 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
224 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
225 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
227 // Conversions between floating types.
228 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
229 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
231 // Integer to floating-point conversions.
232 // i64 conversions are done via library routines even when generating VFP
233 // instructions, so use the same ones.
234 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
235 // e.g., __floatunsidf vs. __floatunssidfvfp.
236 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
237 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
238 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
239 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
243 // These libcalls are not available in 32-bit.
244 setLibcallName(RTLIB::SHL_I128, 0);
245 setLibcallName(RTLIB::SRL_I128, 0);
246 setLibcallName(RTLIB::SRA_I128, 0);
248 if (Subtarget->isAAPCS_ABI()) {
249 // Double-precision floating-point arithmetic helper functions
250 // RTABI chapter 4.1.2, Table 2
251 setLibcallName(RTLIB::ADD_F64, "__aeabi_dadd");
252 setLibcallName(RTLIB::DIV_F64, "__aeabi_ddiv");
253 setLibcallName(RTLIB::MUL_F64, "__aeabi_dmul");
254 setLibcallName(RTLIB::SUB_F64, "__aeabi_dsub");
255 setLibcallCallingConv(RTLIB::ADD_F64, CallingConv::ARM_AAPCS);
256 setLibcallCallingConv(RTLIB::DIV_F64, CallingConv::ARM_AAPCS);
257 setLibcallCallingConv(RTLIB::MUL_F64, CallingConv::ARM_AAPCS);
258 setLibcallCallingConv(RTLIB::SUB_F64, CallingConv::ARM_AAPCS);
260 // Double-precision floating-point comparison helper functions
261 // RTABI chapter 4.1.2, Table 3
262 setLibcallName(RTLIB::OEQ_F64, "__aeabi_dcmpeq");
263 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
264 setLibcallName(RTLIB::UNE_F64, "__aeabi_dcmpeq");
265 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETEQ);
266 setLibcallName(RTLIB::OLT_F64, "__aeabi_dcmplt");
267 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
268 setLibcallName(RTLIB::OLE_F64, "__aeabi_dcmple");
269 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
270 setLibcallName(RTLIB::OGE_F64, "__aeabi_dcmpge");
271 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
272 setLibcallName(RTLIB::OGT_F64, "__aeabi_dcmpgt");
273 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
274 setLibcallName(RTLIB::UO_F64, "__aeabi_dcmpun");
275 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
276 setLibcallName(RTLIB::O_F64, "__aeabi_dcmpun");
277 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
278 setLibcallCallingConv(RTLIB::OEQ_F64, CallingConv::ARM_AAPCS);
279 setLibcallCallingConv(RTLIB::UNE_F64, CallingConv::ARM_AAPCS);
280 setLibcallCallingConv(RTLIB::OLT_F64, CallingConv::ARM_AAPCS);
281 setLibcallCallingConv(RTLIB::OLE_F64, CallingConv::ARM_AAPCS);
282 setLibcallCallingConv(RTLIB::OGE_F64, CallingConv::ARM_AAPCS);
283 setLibcallCallingConv(RTLIB::OGT_F64, CallingConv::ARM_AAPCS);
284 setLibcallCallingConv(RTLIB::UO_F64, CallingConv::ARM_AAPCS);
285 setLibcallCallingConv(RTLIB::O_F64, CallingConv::ARM_AAPCS);
287 // Single-precision floating-point arithmetic helper functions
288 // RTABI chapter 4.1.2, Table 4
289 setLibcallName(RTLIB::ADD_F32, "__aeabi_fadd");
290 setLibcallName(RTLIB::DIV_F32, "__aeabi_fdiv");
291 setLibcallName(RTLIB::MUL_F32, "__aeabi_fmul");
292 setLibcallName(RTLIB::SUB_F32, "__aeabi_fsub");
293 setLibcallCallingConv(RTLIB::ADD_F32, CallingConv::ARM_AAPCS);
294 setLibcallCallingConv(RTLIB::DIV_F32, CallingConv::ARM_AAPCS);
295 setLibcallCallingConv(RTLIB::MUL_F32, CallingConv::ARM_AAPCS);
296 setLibcallCallingConv(RTLIB::SUB_F32, CallingConv::ARM_AAPCS);
298 // Single-precision floating-point comparison helper functions
299 // RTABI chapter 4.1.2, Table 5
300 setLibcallName(RTLIB::OEQ_F32, "__aeabi_fcmpeq");
301 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
302 setLibcallName(RTLIB::UNE_F32, "__aeabi_fcmpeq");
303 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETEQ);
304 setLibcallName(RTLIB::OLT_F32, "__aeabi_fcmplt");
305 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
306 setLibcallName(RTLIB::OLE_F32, "__aeabi_fcmple");
307 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
308 setLibcallName(RTLIB::OGE_F32, "__aeabi_fcmpge");
309 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
310 setLibcallName(RTLIB::OGT_F32, "__aeabi_fcmpgt");
311 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
312 setLibcallName(RTLIB::UO_F32, "__aeabi_fcmpun");
313 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
314 setLibcallName(RTLIB::O_F32, "__aeabi_fcmpun");
315 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
316 setLibcallCallingConv(RTLIB::OEQ_F32, CallingConv::ARM_AAPCS);
317 setLibcallCallingConv(RTLIB::UNE_F32, CallingConv::ARM_AAPCS);
318 setLibcallCallingConv(RTLIB::OLT_F32, CallingConv::ARM_AAPCS);
319 setLibcallCallingConv(RTLIB::OLE_F32, CallingConv::ARM_AAPCS);
320 setLibcallCallingConv(RTLIB::OGE_F32, CallingConv::ARM_AAPCS);
321 setLibcallCallingConv(RTLIB::OGT_F32, CallingConv::ARM_AAPCS);
322 setLibcallCallingConv(RTLIB::UO_F32, CallingConv::ARM_AAPCS);
323 setLibcallCallingConv(RTLIB::O_F32, CallingConv::ARM_AAPCS);
325 // Floating-point to integer conversions.
326 // RTABI chapter 4.1.2, Table 6
327 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz");
328 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz");
329 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz");
330 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz");
331 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz");
332 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz");
333 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz");
334 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz");
335 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I32, CallingConv::ARM_AAPCS);
336 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I32, CallingConv::ARM_AAPCS);
337 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I64, CallingConv::ARM_AAPCS);
338 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::ARM_AAPCS);
339 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I32, CallingConv::ARM_AAPCS);
340 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I32, CallingConv::ARM_AAPCS);
341 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I64, CallingConv::ARM_AAPCS);
342 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::ARM_AAPCS);
344 // Conversions between floating types.
345 // RTABI chapter 4.1.2, Table 7
346 setLibcallName(RTLIB::FPROUND_F64_F32, "__aeabi_d2f");
347 setLibcallName(RTLIB::FPEXT_F32_F64, "__aeabi_f2d");
348 setLibcallCallingConv(RTLIB::FPROUND_F64_F32, CallingConv::ARM_AAPCS);
349 setLibcallCallingConv(RTLIB::FPEXT_F32_F64, CallingConv::ARM_AAPCS);
351 // Integer to floating-point conversions.
352 // RTABI chapter 4.1.2, Table 8
353 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d");
354 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d");
355 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d");
356 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d");
357 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f");
358 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f");
359 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f");
360 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f");
361 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
362 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
363 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
364 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
365 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
366 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
367 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
368 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
370 // Long long helper functions
371 // RTABI chapter 4.2, Table 9
372 setLibcallName(RTLIB::MUL_I64, "__aeabi_lmul");
373 setLibcallName(RTLIB::SDIV_I64, "__aeabi_ldivmod");
374 setLibcallName(RTLIB::UDIV_I64, "__aeabi_uldivmod");
375 setLibcallName(RTLIB::SHL_I64, "__aeabi_llsl");
376 setLibcallName(RTLIB::SRL_I64, "__aeabi_llsr");
377 setLibcallName(RTLIB::SRA_I64, "__aeabi_lasr");
378 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::ARM_AAPCS);
379 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::ARM_AAPCS);
380 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::ARM_AAPCS);
381 setLibcallCallingConv(RTLIB::SHL_I64, CallingConv::ARM_AAPCS);
382 setLibcallCallingConv(RTLIB::SRL_I64, CallingConv::ARM_AAPCS);
383 setLibcallCallingConv(RTLIB::SRA_I64, CallingConv::ARM_AAPCS);
385 // Integer division functions
386 // RTABI chapter 4.3.1
387 setLibcallName(RTLIB::SDIV_I8, "__aeabi_idiv");
388 setLibcallName(RTLIB::SDIV_I16, "__aeabi_idiv");
389 setLibcallName(RTLIB::SDIV_I32, "__aeabi_idiv");
390 setLibcallName(RTLIB::UDIV_I8, "__aeabi_uidiv");
391 setLibcallName(RTLIB::UDIV_I16, "__aeabi_uidiv");
392 setLibcallName(RTLIB::UDIV_I32, "__aeabi_uidiv");
393 setLibcallCallingConv(RTLIB::SDIV_I8, CallingConv::ARM_AAPCS);
394 setLibcallCallingConv(RTLIB::SDIV_I16, CallingConv::ARM_AAPCS);
395 setLibcallCallingConv(RTLIB::SDIV_I32, CallingConv::ARM_AAPCS);
396 setLibcallCallingConv(RTLIB::UDIV_I8, CallingConv::ARM_AAPCS);
397 setLibcallCallingConv(RTLIB::UDIV_I16, CallingConv::ARM_AAPCS);
398 setLibcallCallingConv(RTLIB::UDIV_I32, CallingConv::ARM_AAPCS);
401 // RTABI chapter 4.3.4
402 setLibcallName(RTLIB::MEMCPY, "__aeabi_memcpy");
403 setLibcallName(RTLIB::MEMMOVE, "__aeabi_memmove");
404 setLibcallName(RTLIB::MEMSET, "__aeabi_memset");
407 if (Subtarget->isThumb1Only())
408 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
410 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
411 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
412 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
413 if (!Subtarget->isFPOnlySP())
414 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
416 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
419 if (Subtarget->hasNEON()) {
420 addDRTypeForNEON(MVT::v2f32);
421 addDRTypeForNEON(MVT::v8i8);
422 addDRTypeForNEON(MVT::v4i16);
423 addDRTypeForNEON(MVT::v2i32);
424 addDRTypeForNEON(MVT::v1i64);
426 addQRTypeForNEON(MVT::v4f32);
427 addQRTypeForNEON(MVT::v2f64);
428 addQRTypeForNEON(MVT::v16i8);
429 addQRTypeForNEON(MVT::v8i16);
430 addQRTypeForNEON(MVT::v4i32);
431 addQRTypeForNEON(MVT::v2i64);
433 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
434 // neither Neon nor VFP support any arithmetic operations on it.
435 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
436 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
437 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
438 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
439 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
440 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
441 setOperationAction(ISD::VSETCC, MVT::v2f64, Expand);
442 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
443 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
444 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
445 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
446 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
447 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
448 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
449 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
450 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
451 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
452 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
453 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
454 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
455 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
456 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
457 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
458 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
460 setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand);
462 // Neon does not support some operations on v1i64 and v2i64 types.
463 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
464 // Custom handling for some quad-vector types to detect VMULL.
465 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
466 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
467 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
468 // Custom handling for some vector types to avoid expensive expansions
469 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
470 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
471 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
472 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
473 setOperationAction(ISD::VSETCC, MVT::v1i64, Expand);
474 setOperationAction(ISD::VSETCC, MVT::v2i64, Expand);
475 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
476 // a destination type that is wider than the source.
477 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
478 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
480 setTargetDAGCombine(ISD::INTRINSIC_VOID);
481 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
482 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
483 setTargetDAGCombine(ISD::SHL);
484 setTargetDAGCombine(ISD::SRL);
485 setTargetDAGCombine(ISD::SRA);
486 setTargetDAGCombine(ISD::SIGN_EXTEND);
487 setTargetDAGCombine(ISD::ZERO_EXTEND);
488 setTargetDAGCombine(ISD::ANY_EXTEND);
489 setTargetDAGCombine(ISD::SELECT_CC);
490 setTargetDAGCombine(ISD::BUILD_VECTOR);
491 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
492 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
493 setTargetDAGCombine(ISD::STORE);
496 computeRegisterProperties();
498 // ARM does not have f32 extending load.
499 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
501 // ARM does not have i1 sign extending load.
502 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
504 // ARM supports all 4 flavors of integer indexed load / store.
505 if (!Subtarget->isThumb1Only()) {
506 for (unsigned im = (unsigned)ISD::PRE_INC;
507 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
508 setIndexedLoadAction(im, MVT::i1, Legal);
509 setIndexedLoadAction(im, MVT::i8, Legal);
510 setIndexedLoadAction(im, MVT::i16, Legal);
511 setIndexedLoadAction(im, MVT::i32, Legal);
512 setIndexedStoreAction(im, MVT::i1, Legal);
513 setIndexedStoreAction(im, MVT::i8, Legal);
514 setIndexedStoreAction(im, MVT::i16, Legal);
515 setIndexedStoreAction(im, MVT::i32, Legal);
519 // i64 operation support.
520 setOperationAction(ISD::MUL, MVT::i64, Expand);
521 setOperationAction(ISD::MULHU, MVT::i32, Expand);
522 if (Subtarget->isThumb1Only()) {
523 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
524 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
526 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops())
527 setOperationAction(ISD::MULHS, MVT::i32, Expand);
529 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
530 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
531 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
532 setOperationAction(ISD::SRL, MVT::i64, Custom);
533 setOperationAction(ISD::SRA, MVT::i64, Custom);
535 // ARM does not have ROTL.
536 setOperationAction(ISD::ROTL, MVT::i32, Expand);
537 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
538 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
539 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
540 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
542 // Only ARMv6 has BSWAP.
543 if (!Subtarget->hasV6Ops())
544 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
546 // These are expanded into libcalls.
547 if (!Subtarget->hasDivide() || !Subtarget->isThumb2()) {
548 // v7M has a hardware divider
549 setOperationAction(ISD::SDIV, MVT::i32, Expand);
550 setOperationAction(ISD::UDIV, MVT::i32, Expand);
552 setOperationAction(ISD::SREM, MVT::i32, Expand);
553 setOperationAction(ISD::UREM, MVT::i32, Expand);
554 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
555 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
557 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
558 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
559 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
560 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
561 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
563 setOperationAction(ISD::TRAP, MVT::Other, Legal);
565 // Use the default implementation.
566 setOperationAction(ISD::VASTART, MVT::Other, Custom);
567 setOperationAction(ISD::VAARG, MVT::Other, Expand);
568 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
569 setOperationAction(ISD::VAEND, MVT::Other, Expand);
570 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
571 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
572 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
573 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
574 setExceptionPointerRegister(ARM::R0);
575 setExceptionSelectorRegister(ARM::R1);
577 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
578 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
579 // the default expansion.
580 if (Subtarget->hasDataBarrier() ||
581 (Subtarget->hasV6Ops() && !Subtarget->isThumb())) {
582 // membarrier needs custom lowering; the rest are legal and handled
584 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
586 // Set them all for expansion, which will force libcalls.
587 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
588 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Expand);
589 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Expand);
590 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
591 setOperationAction(ISD::ATOMIC_SWAP, MVT::i8, Expand);
592 setOperationAction(ISD::ATOMIC_SWAP, MVT::i16, Expand);
593 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
594 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i8, Expand);
595 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i16, Expand);
596 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
597 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Expand);
598 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Expand);
599 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
600 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i8, Expand);
601 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i16, Expand);
602 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
603 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i8, Expand);
604 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i16, Expand);
605 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
606 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i8, Expand);
607 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i16, Expand);
608 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
609 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i8, Expand);
610 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i16, Expand);
611 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
612 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i8, Expand);
613 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i16, Expand);
614 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
615 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i8, Expand);
616 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i16, Expand);
617 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
618 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i8, Expand);
619 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i16, Expand);
620 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
621 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i8, Expand);
622 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i16, Expand);
623 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
624 // Since the libcalls include locking, fold in the fences
625 setShouldFoldAtomicFences(true);
627 // 64-bit versions are always libcalls (for now)
628 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Expand);
629 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Expand);
630 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Expand);
631 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Expand);
632 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Expand);
633 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Expand);
634 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Expand);
635 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Expand);
637 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
639 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
640 if (!Subtarget->hasV6Ops()) {
641 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
642 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
644 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
646 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
647 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
648 // iff target supports vfp2.
649 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
650 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
653 // We want to custom lower some of our intrinsics.
654 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
655 if (Subtarget->isTargetDarwin()) {
656 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
657 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
658 setOperationAction(ISD::EH_SJLJ_DISPATCHSETUP, MVT::Other, Custom);
659 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
662 setOperationAction(ISD::SETCC, MVT::i32, Expand);
663 setOperationAction(ISD::SETCC, MVT::f32, Expand);
664 setOperationAction(ISD::SETCC, MVT::f64, Expand);
665 setOperationAction(ISD::SELECT, MVT::i32, Custom);
666 setOperationAction(ISD::SELECT, MVT::f32, Custom);
667 setOperationAction(ISD::SELECT, MVT::f64, Custom);
668 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
669 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
670 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
672 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
673 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
674 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
675 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
676 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
678 // We don't support sin/cos/fmod/copysign/pow
679 setOperationAction(ISD::FSIN, MVT::f64, Expand);
680 setOperationAction(ISD::FSIN, MVT::f32, Expand);
681 setOperationAction(ISD::FCOS, MVT::f32, Expand);
682 setOperationAction(ISD::FCOS, MVT::f64, Expand);
683 setOperationAction(ISD::FREM, MVT::f64, Expand);
684 setOperationAction(ISD::FREM, MVT::f32, Expand);
685 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
686 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
687 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
689 setOperationAction(ISD::FPOW, MVT::f64, Expand);
690 setOperationAction(ISD::FPOW, MVT::f32, Expand);
692 // Various VFP goodness
693 if (!UseSoftFloat && !Subtarget->isThumb1Only()) {
694 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
695 if (Subtarget->hasVFP2()) {
696 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
697 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
698 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
699 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
701 // Special handling for half-precision FP.
702 if (!Subtarget->hasFP16()) {
703 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
704 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand);
708 // We have target-specific dag combine patterns for the following nodes:
709 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
710 setTargetDAGCombine(ISD::ADD);
711 setTargetDAGCombine(ISD::SUB);
712 setTargetDAGCombine(ISD::MUL);
714 if (Subtarget->hasV6T2Ops() || Subtarget->hasNEON())
715 setTargetDAGCombine(ISD::OR);
716 if (Subtarget->hasNEON())
717 setTargetDAGCombine(ISD::AND);
719 setStackPointerRegisterToSaveRestore(ARM::SP);
721 if (UseSoftFloat || Subtarget->isThumb1Only() || !Subtarget->hasVFP2())
722 setSchedulingPreference(Sched::RegPressure);
724 setSchedulingPreference(Sched::Hybrid);
726 //// temporary - rewrite interface to use type
727 maxStoresPerMemcpy = maxStoresPerMemcpyOptSize = 1;
729 // On ARM arguments smaller than 4 bytes are extended, so all arguments
730 // are at least 4 bytes aligned.
731 setMinStackArgumentAlignment(4);
733 benefitFromCodePlacementOpt = true;
735 setMinFunctionAlignment(Subtarget->isThumb() ? 1 : 2);
738 // FIXME: It might make sense to define the representative register class as the
739 // nearest super-register that has a non-null superset. For example, DPR_VFP2 is
740 // a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
741 // SPR's representative would be DPR_VFP2. This should work well if register
742 // pressure tracking were modified such that a register use would increment the
743 // pressure of the register class's representative and all of it's super
744 // classes' representatives transitively. We have not implemented this because
745 // of the difficulty prior to coalescing of modeling operand register classes
746 // due to the common occurrence of cross class copies and subregister insertions
748 std::pair<const TargetRegisterClass*, uint8_t>
749 ARMTargetLowering::findRepresentativeClass(EVT VT) const{
750 const TargetRegisterClass *RRC = 0;
752 switch (VT.getSimpleVT().SimpleTy) {
754 return TargetLowering::findRepresentativeClass(VT);
755 // Use DPR as representative register class for all floating point
756 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
757 // the cost is 1 for both f32 and f64.
758 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
759 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
760 RRC = ARM::DPRRegisterClass;
761 // When NEON is used for SP, only half of the register file is available
762 // because operations that define both SP and DP results will be constrained
763 // to the VFP2 class (D0-D15). We currently model this constraint prior to
764 // coalescing by double-counting the SP regs. See the FIXME above.
765 if (Subtarget->useNEONForSinglePrecisionFP())
768 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
769 case MVT::v4f32: case MVT::v2f64:
770 RRC = ARM::DPRRegisterClass;
774 RRC = ARM::DPRRegisterClass;
778 RRC = ARM::DPRRegisterClass;
782 return std::make_pair(RRC, Cost);
785 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
788 case ARMISD::Wrapper: return "ARMISD::Wrapper";
789 case ARMISD::WrapperDYN: return "ARMISD::WrapperDYN";
790 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
791 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
792 case ARMISD::CALL: return "ARMISD::CALL";
793 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
794 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
795 case ARMISD::tCALL: return "ARMISD::tCALL";
796 case ARMISD::BRCOND: return "ARMISD::BRCOND";
797 case ARMISD::BR_JT: return "ARMISD::BR_JT";
798 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
799 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
800 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
801 case ARMISD::CMP: return "ARMISD::CMP";
802 case ARMISD::CMPZ: return "ARMISD::CMPZ";
803 case ARMISD::CMPFP: return "ARMISD::CMPFP";
804 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
805 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
806 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
807 case ARMISD::CMOV: return "ARMISD::CMOV";
809 case ARMISD::RBIT: return "ARMISD::RBIT";
811 case ARMISD::FTOSI: return "ARMISD::FTOSI";
812 case ARMISD::FTOUI: return "ARMISD::FTOUI";
813 case ARMISD::SITOF: return "ARMISD::SITOF";
814 case ARMISD::UITOF: return "ARMISD::UITOF";
816 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
817 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
818 case ARMISD::RRX: return "ARMISD::RRX";
820 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
821 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
823 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
824 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
825 case ARMISD::EH_SJLJ_DISPATCHSETUP:return "ARMISD::EH_SJLJ_DISPATCHSETUP";
827 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
829 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
831 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
833 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER";
834 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
836 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
838 case ARMISD::VCEQ: return "ARMISD::VCEQ";
839 case ARMISD::VCEQZ: return "ARMISD::VCEQZ";
840 case ARMISD::VCGE: return "ARMISD::VCGE";
841 case ARMISD::VCGEZ: return "ARMISD::VCGEZ";
842 case ARMISD::VCLEZ: return "ARMISD::VCLEZ";
843 case ARMISD::VCGEU: return "ARMISD::VCGEU";
844 case ARMISD::VCGT: return "ARMISD::VCGT";
845 case ARMISD::VCGTZ: return "ARMISD::VCGTZ";
846 case ARMISD::VCLTZ: return "ARMISD::VCLTZ";
847 case ARMISD::VCGTU: return "ARMISD::VCGTU";
848 case ARMISD::VTST: return "ARMISD::VTST";
850 case ARMISD::VSHL: return "ARMISD::VSHL";
851 case ARMISD::VSHRs: return "ARMISD::VSHRs";
852 case ARMISD::VSHRu: return "ARMISD::VSHRu";
853 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
854 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
855 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
856 case ARMISD::VSHRN: return "ARMISD::VSHRN";
857 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
858 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
859 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
860 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
861 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
862 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
863 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
864 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
865 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
866 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
867 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
868 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
869 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
870 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
871 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
872 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
873 case ARMISD::VDUP: return "ARMISD::VDUP";
874 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
875 case ARMISD::VEXT: return "ARMISD::VEXT";
876 case ARMISD::VREV64: return "ARMISD::VREV64";
877 case ARMISD::VREV32: return "ARMISD::VREV32";
878 case ARMISD::VREV16: return "ARMISD::VREV16";
879 case ARMISD::VZIP: return "ARMISD::VZIP";
880 case ARMISD::VUZP: return "ARMISD::VUZP";
881 case ARMISD::VTRN: return "ARMISD::VTRN";
882 case ARMISD::VTBL1: return "ARMISD::VTBL1";
883 case ARMISD::VTBL2: return "ARMISD::VTBL2";
884 case ARMISD::VMULLs: return "ARMISD::VMULLs";
885 case ARMISD::VMULLu: return "ARMISD::VMULLu";
886 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
887 case ARMISD::FMAX: return "ARMISD::FMAX";
888 case ARMISD::FMIN: return "ARMISD::FMIN";
889 case ARMISD::BFI: return "ARMISD::BFI";
890 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
891 case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
892 case ARMISD::VBSL: return "ARMISD::VBSL";
893 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
894 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
895 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
896 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD";
897 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD";
898 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD";
899 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD";
900 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD";
901 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD";
902 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD";
903 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD";
904 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD";
905 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD";
906 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD";
907 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD";
908 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD";
909 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD";
910 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD";
911 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD";
912 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD";
916 /// getRegClassFor - Return the register class that should be used for the
917 /// specified value type.
918 TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const {
919 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
920 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
921 // load / store 4 to 8 consecutive D registers.
922 if (Subtarget->hasNEON()) {
923 if (VT == MVT::v4i64)
924 return ARM::QQPRRegisterClass;
925 else if (VT == MVT::v8i64)
926 return ARM::QQQQPRRegisterClass;
928 return TargetLowering::getRegClassFor(VT);
931 // Create a fast isel object.
933 ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
934 return ARM::createFastISel(funcInfo);
937 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
938 /// be used for loads / stores from the global.
939 unsigned ARMTargetLowering::getMaximalGlobalOffset() const {
940 return (Subtarget->isThumb1Only() ? 127 : 4095);
943 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
944 unsigned NumVals = N->getNumValues();
946 return Sched::RegPressure;
948 for (unsigned i = 0; i != NumVals; ++i) {
949 EVT VT = N->getValueType(i);
950 if (VT == MVT::Glue || VT == MVT::Other)
952 if (VT.isFloatingPoint() || VT.isVector())
953 return Sched::Latency;
956 if (!N->isMachineOpcode())
957 return Sched::RegPressure;
959 // Load are scheduled for latency even if there instruction itinerary
961 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
962 const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
964 if (TID.getNumDefs() == 0)
965 return Sched::RegPressure;
966 if (!Itins->isEmpty() &&
967 Itins->getOperandCycle(TID.getSchedClass(), 0) > 2)
968 return Sched::Latency;
970 return Sched::RegPressure;
973 //===----------------------------------------------------------------------===//
975 //===----------------------------------------------------------------------===//
977 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
978 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
980 default: llvm_unreachable("Unknown condition code!");
981 case ISD::SETNE: return ARMCC::NE;
982 case ISD::SETEQ: return ARMCC::EQ;
983 case ISD::SETGT: return ARMCC::GT;
984 case ISD::SETGE: return ARMCC::GE;
985 case ISD::SETLT: return ARMCC::LT;
986 case ISD::SETLE: return ARMCC::LE;
987 case ISD::SETUGT: return ARMCC::HI;
988 case ISD::SETUGE: return ARMCC::HS;
989 case ISD::SETULT: return ARMCC::LO;
990 case ISD::SETULE: return ARMCC::LS;
994 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
995 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
996 ARMCC::CondCodes &CondCode2) {
997 CondCode2 = ARMCC::AL;
999 default: llvm_unreachable("Unknown FP condition!");
1001 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
1003 case ISD::SETOGT: CondCode = ARMCC::GT; break;
1005 case ISD::SETOGE: CondCode = ARMCC::GE; break;
1006 case ISD::SETOLT: CondCode = ARMCC::MI; break;
1007 case ISD::SETOLE: CondCode = ARMCC::LS; break;
1008 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
1009 case ISD::SETO: CondCode = ARMCC::VC; break;
1010 case ISD::SETUO: CondCode = ARMCC::VS; break;
1011 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
1012 case ISD::SETUGT: CondCode = ARMCC::HI; break;
1013 case ISD::SETUGE: CondCode = ARMCC::PL; break;
1015 case ISD::SETULT: CondCode = ARMCC::LT; break;
1017 case ISD::SETULE: CondCode = ARMCC::LE; break;
1019 case ISD::SETUNE: CondCode = ARMCC::NE; break;
1023 //===----------------------------------------------------------------------===//
1024 // Calling Convention Implementation
1025 //===----------------------------------------------------------------------===//
1027 #include "ARMGenCallingConv.inc"
1029 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1030 /// given CallingConvention value.
1031 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
1033 bool isVarArg) const {
1036 llvm_unreachable("Unsupported calling convention");
1037 case CallingConv::Fast:
1038 if (Subtarget->hasVFP2() && !isVarArg) {
1039 if (!Subtarget->isAAPCS_ABI())
1040 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1041 // For AAPCS ABI targets, just use VFP variant of the calling convention.
1042 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1045 case CallingConv::C: {
1046 // Use target triple & subtarget features to do actual dispatch.
1047 if (!Subtarget->isAAPCS_ABI())
1048 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1049 else if (Subtarget->hasVFP2() &&
1050 FloatABIType == FloatABI::Hard && !isVarArg)
1051 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1052 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1054 case CallingConv::ARM_AAPCS_VFP:
1055 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1056 case CallingConv::ARM_AAPCS:
1057 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1058 case CallingConv::ARM_APCS:
1059 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1063 /// LowerCallResult - Lower the result values of a call into the
1064 /// appropriate copies out of appropriate physical registers.
1066 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1067 CallingConv::ID CallConv, bool isVarArg,
1068 const SmallVectorImpl<ISD::InputArg> &Ins,
1069 DebugLoc dl, SelectionDAG &DAG,
1070 SmallVectorImpl<SDValue> &InVals) const {
1072 // Assign locations to each value returned by this call.
1073 SmallVector<CCValAssign, 16> RVLocs;
1074 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1075 RVLocs, *DAG.getContext());
1076 CCInfo.AnalyzeCallResult(Ins,
1077 CCAssignFnForNode(CallConv, /* Return*/ true,
1080 // Copy all of the result registers out of their specified physreg.
1081 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1082 CCValAssign VA = RVLocs[i];
1085 if (VA.needsCustom()) {
1086 // Handle f64 or half of a v2f64.
1087 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1089 Chain = Lo.getValue(1);
1090 InFlag = Lo.getValue(2);
1091 VA = RVLocs[++i]; // skip ahead to next loc
1092 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1094 Chain = Hi.getValue(1);
1095 InFlag = Hi.getValue(2);
1096 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1098 if (VA.getLocVT() == MVT::v2f64) {
1099 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1100 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1101 DAG.getConstant(0, MVT::i32));
1103 VA = RVLocs[++i]; // skip ahead to next loc
1104 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1105 Chain = Lo.getValue(1);
1106 InFlag = Lo.getValue(2);
1107 VA = RVLocs[++i]; // skip ahead to next loc
1108 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1109 Chain = Hi.getValue(1);
1110 InFlag = Hi.getValue(2);
1111 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1112 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1113 DAG.getConstant(1, MVT::i32));
1116 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1118 Chain = Val.getValue(1);
1119 InFlag = Val.getValue(2);
1122 switch (VA.getLocInfo()) {
1123 default: llvm_unreachable("Unknown loc info!");
1124 case CCValAssign::Full: break;
1125 case CCValAssign::BCvt:
1126 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1130 InVals.push_back(Val);
1136 /// LowerMemOpCallTo - Store the argument to the stack.
1138 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
1139 SDValue StackPtr, SDValue Arg,
1140 DebugLoc dl, SelectionDAG &DAG,
1141 const CCValAssign &VA,
1142 ISD::ArgFlagsTy Flags) const {
1143 unsigned LocMemOffset = VA.getLocMemOffset();
1144 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1145 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1146 return DAG.getStore(Chain, dl, Arg, PtrOff,
1147 MachinePointerInfo::getStack(LocMemOffset),
1151 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
1152 SDValue Chain, SDValue &Arg,
1153 RegsToPassVector &RegsToPass,
1154 CCValAssign &VA, CCValAssign &NextVA,
1156 SmallVector<SDValue, 8> &MemOpChains,
1157 ISD::ArgFlagsTy Flags) const {
1159 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1160 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1161 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
1163 if (NextVA.isRegLoc())
1164 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
1166 assert(NextVA.isMemLoc());
1167 if (StackPtr.getNode() == 0)
1168 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1170 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
1176 /// LowerCall - Lowering a call into a callseq_start <-
1177 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1180 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1181 CallingConv::ID CallConv, bool isVarArg,
1183 const SmallVectorImpl<ISD::OutputArg> &Outs,
1184 const SmallVectorImpl<SDValue> &OutVals,
1185 const SmallVectorImpl<ISD::InputArg> &Ins,
1186 DebugLoc dl, SelectionDAG &DAG,
1187 SmallVectorImpl<SDValue> &InVals) const {
1188 MachineFunction &MF = DAG.getMachineFunction();
1189 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1190 bool IsSibCall = false;
1191 // Temporarily disable tail calls so things don't break.
1192 if (!EnableARMTailCalls)
1195 // Check if it's really possible to do a tail call.
1196 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1197 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1198 Outs, OutVals, Ins, DAG);
1199 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1200 // detected sibcalls.
1207 // Analyze operands of the call, assigning locations to each operand.
1208 SmallVector<CCValAssign, 16> ArgLocs;
1209 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1211 CCInfo.setCallOrPrologue(Call);
1212 CCInfo.AnalyzeCallOperands(Outs,
1213 CCAssignFnForNode(CallConv, /* Return*/ false,
1216 // Get a count of how many bytes are to be pushed on the stack.
1217 unsigned NumBytes = CCInfo.getNextStackOffset();
1219 // For tail calls, memory operands are available in our caller's stack.
1223 // Adjust the stack pointer for the new arguments...
1224 // These operations are automatically eliminated by the prolog/epilog pass
1226 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1228 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1230 RegsToPassVector RegsToPass;
1231 SmallVector<SDValue, 8> MemOpChains;
1233 // Walk the register/memloc assignments, inserting copies/loads. In the case
1234 // of tail call optimization, arguments are handled later.
1235 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1237 ++i, ++realArgIdx) {
1238 CCValAssign &VA = ArgLocs[i];
1239 SDValue Arg = OutVals[realArgIdx];
1240 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1241 bool isByVal = Flags.isByVal();
1243 // Promote the value if needed.
1244 switch (VA.getLocInfo()) {
1245 default: llvm_unreachable("Unknown loc info!");
1246 case CCValAssign::Full: break;
1247 case CCValAssign::SExt:
1248 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1250 case CCValAssign::ZExt:
1251 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1253 case CCValAssign::AExt:
1254 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1256 case CCValAssign::BCvt:
1257 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1261 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1262 if (VA.needsCustom()) {
1263 if (VA.getLocVT() == MVT::v2f64) {
1264 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1265 DAG.getConstant(0, MVT::i32));
1266 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1267 DAG.getConstant(1, MVT::i32));
1269 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1270 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1272 VA = ArgLocs[++i]; // skip ahead to next loc
1273 if (VA.isRegLoc()) {
1274 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1275 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1277 assert(VA.isMemLoc());
1279 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1280 dl, DAG, VA, Flags));
1283 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1284 StackPtr, MemOpChains, Flags);
1286 } else if (VA.isRegLoc()) {
1287 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1288 } else if (isByVal) {
1289 assert(VA.isMemLoc());
1290 unsigned offset = 0;
1292 // True if this byval aggregate will be split between registers
1294 if (CCInfo.isFirstByValRegValid()) {
1295 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1297 for (i = 0, j = CCInfo.getFirstByValReg(); j < ARM::R4; i++, j++) {
1298 SDValue Const = DAG.getConstant(4*i, MVT::i32);
1299 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
1300 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
1301 MachinePointerInfo(),
1303 MemOpChains.push_back(Load.getValue(1));
1304 RegsToPass.push_back(std::make_pair(j, Load));
1306 offset = ARM::R4 - CCInfo.getFirstByValReg();
1307 CCInfo.clearFirstByValReg();
1310 unsigned LocMemOffset = VA.getLocMemOffset();
1311 SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset);
1312 SDValue Dst = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr,
1314 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset);
1315 SDValue Src = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg, SrcOffset);
1316 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset,
1318 MemOpChains.push_back(DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode,
1319 Flags.getByValAlign(),
1320 /*isVolatile=*/false,
1321 /*AlwaysInline=*/false,
1322 MachinePointerInfo(0),
1323 MachinePointerInfo(0)));
1325 } else if (!IsSibCall) {
1326 assert(VA.isMemLoc());
1328 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1329 dl, DAG, VA, Flags));
1333 if (!MemOpChains.empty())
1334 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1335 &MemOpChains[0], MemOpChains.size());
1337 // Build a sequence of copy-to-reg nodes chained together with token chain
1338 // and flag operands which copy the outgoing args into the appropriate regs.
1340 // Tail call byval lowering might overwrite argument registers so in case of
1341 // tail call optimization the copies to registers are lowered later.
1343 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1344 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1345 RegsToPass[i].second, InFlag);
1346 InFlag = Chain.getValue(1);
1349 // For tail calls lower the arguments to the 'real' stack slot.
1351 // Force all the incoming stack arguments to be loaded from the stack
1352 // before any new outgoing arguments are stored to the stack, because the
1353 // outgoing stack slots may alias the incoming argument stack slots, and
1354 // the alias isn't otherwise explicit. This is slightly more conservative
1355 // than necessary, because it means that each store effectively depends
1356 // on every argument instead of just those arguments it would clobber.
1358 // Do not flag preceding copytoreg stuff together with the following stuff.
1360 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1361 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1362 RegsToPass[i].second, InFlag);
1363 InFlag = Chain.getValue(1);
1368 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1369 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1370 // node so that legalize doesn't hack it.
1371 bool isDirect = false;
1372 bool isARMFunc = false;
1373 bool isLocalARMFunc = false;
1374 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1376 if (EnableARMLongCalls) {
1377 assert (getTargetMachine().getRelocationModel() == Reloc::Static
1378 && "long-calls with non-static relocation model!");
1379 // Handle a global address or an external symbol. If it's not one of
1380 // those, the target's already in a register, so we don't need to do
1382 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1383 const GlobalValue *GV = G->getGlobal();
1384 // Create a constant pool entry for the callee address
1385 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1386 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1389 // Get the address of the callee into a register
1390 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1391 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1392 Callee = DAG.getLoad(getPointerTy(), dl,
1393 DAG.getEntryNode(), CPAddr,
1394 MachinePointerInfo::getConstantPool(),
1396 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1397 const char *Sym = S->getSymbol();
1399 // Create a constant pool entry for the callee address
1400 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1401 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1402 Sym, ARMPCLabelIndex, 0);
1403 // Get the address of the callee into a register
1404 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1405 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1406 Callee = DAG.getLoad(getPointerTy(), dl,
1407 DAG.getEntryNode(), CPAddr,
1408 MachinePointerInfo::getConstantPool(),
1411 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1412 const GlobalValue *GV = G->getGlobal();
1414 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1415 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
1416 getTargetMachine().getRelocationModel() != Reloc::Static;
1417 isARMFunc = !Subtarget->isThumb() || isStub;
1418 // ARM call to a local ARM function is predicable.
1419 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
1420 // tBX takes a register source operand.
1421 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1422 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1423 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1426 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1427 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1428 Callee = DAG.getLoad(getPointerTy(), dl,
1429 DAG.getEntryNode(), CPAddr,
1430 MachinePointerInfo::getConstantPool(),
1432 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1433 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1434 getPointerTy(), Callee, PICLabel);
1436 // On ELF targets for PIC code, direct calls should go through the PLT
1437 unsigned OpFlags = 0;
1438 if (Subtarget->isTargetELF() &&
1439 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1440 OpFlags = ARMII::MO_PLT;
1441 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
1443 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1445 bool isStub = Subtarget->isTargetDarwin() &&
1446 getTargetMachine().getRelocationModel() != Reloc::Static;
1447 isARMFunc = !Subtarget->isThumb() || isStub;
1448 // tBX takes a register source operand.
1449 const char *Sym = S->getSymbol();
1450 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1451 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1452 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1453 Sym, ARMPCLabelIndex, 4);
1454 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1455 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1456 Callee = DAG.getLoad(getPointerTy(), dl,
1457 DAG.getEntryNode(), CPAddr,
1458 MachinePointerInfo::getConstantPool(),
1460 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1461 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1462 getPointerTy(), Callee, PICLabel);
1464 unsigned OpFlags = 0;
1465 // On ELF targets for PIC code, direct calls should go through the PLT
1466 if (Subtarget->isTargetELF() &&
1467 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1468 OpFlags = ARMII::MO_PLT;
1469 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags);
1473 // FIXME: handle tail calls differently.
1475 if (Subtarget->isThumb()) {
1476 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1477 CallOpc = ARMISD::CALL_NOLINK;
1479 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1481 CallOpc = (isDirect || Subtarget->hasV5TOps())
1482 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
1483 : ARMISD::CALL_NOLINK;
1486 std::vector<SDValue> Ops;
1487 Ops.push_back(Chain);
1488 Ops.push_back(Callee);
1490 // Add argument registers to the end of the list so that they are known live
1492 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1493 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1494 RegsToPass[i].second.getValueType()));
1496 if (InFlag.getNode())
1497 Ops.push_back(InFlag);
1499 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1501 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
1503 // Returns a chain and a flag for retval copy to use.
1504 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
1505 InFlag = Chain.getValue(1);
1507 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1508 DAG.getIntPtrConstant(0, true), InFlag);
1510 InFlag = Chain.getValue(1);
1512 // Handle result values, copying them out of physregs into vregs that we
1514 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1518 /// HandleByVal - Every parameter *after* a byval parameter is passed
1519 /// on the stack. Remember the next parameter register to allocate,
1520 /// and then confiscate the rest of the parameter registers to insure
1523 llvm::ARMTargetLowering::HandleByVal(CCState *State, unsigned &size) const {
1524 unsigned reg = State->AllocateReg(GPRArgRegs, 4);
1525 assert((State->getCallOrPrologue() == Prologue ||
1526 State->getCallOrPrologue() == Call) &&
1527 "unhandled ParmContext");
1528 if ((!State->isFirstByValRegValid()) &&
1529 (ARM::R0 <= reg) && (reg <= ARM::R3)) {
1530 State->setFirstByValReg(reg);
1531 // At a call site, a byval parameter that is split between
1532 // registers and memory needs its size truncated here. In a
1533 // function prologue, such byval parameters are reassembled in
1534 // memory, and are not truncated.
1535 if (State->getCallOrPrologue() == Call) {
1536 unsigned excess = 4 * (ARM::R4 - reg);
1537 assert(size >= excess && "expected larger existing stack allocation");
1541 // Confiscate any remaining parameter registers to preclude their
1542 // assignment to subsequent parameters.
1543 while (State->AllocateReg(GPRArgRegs, 4))
1547 /// MatchingStackOffset - Return true if the given stack call argument is
1548 /// already available in the same position (relatively) of the caller's
1549 /// incoming argument stack.
1551 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1552 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1553 const ARMInstrInfo *TII) {
1554 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
1556 if (Arg.getOpcode() == ISD::CopyFromReg) {
1557 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
1558 if (!TargetRegisterInfo::isVirtualRegister(VR))
1560 MachineInstr *Def = MRI->getVRegDef(VR);
1563 if (!Flags.isByVal()) {
1564 if (!TII->isLoadFromStackSlot(Def, FI))
1569 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
1570 if (Flags.isByVal())
1571 // ByVal argument is passed in as a pointer but it's now being
1572 // dereferenced. e.g.
1573 // define @foo(%struct.X* %A) {
1574 // tail call @bar(%struct.X* byval %A)
1577 SDValue Ptr = Ld->getBasePtr();
1578 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
1581 FI = FINode->getIndex();
1585 assert(FI != INT_MAX);
1586 if (!MFI->isFixedObjectIndex(FI))
1588 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
1591 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1592 /// for tail call optimization. Targets which want to do tail call
1593 /// optimization should implement this function.
1595 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1596 CallingConv::ID CalleeCC,
1598 bool isCalleeStructRet,
1599 bool isCallerStructRet,
1600 const SmallVectorImpl<ISD::OutputArg> &Outs,
1601 const SmallVectorImpl<SDValue> &OutVals,
1602 const SmallVectorImpl<ISD::InputArg> &Ins,
1603 SelectionDAG& DAG) const {
1604 const Function *CallerF = DAG.getMachineFunction().getFunction();
1605 CallingConv::ID CallerCC = CallerF->getCallingConv();
1606 bool CCMatch = CallerCC == CalleeCC;
1608 // Look for obvious safe cases to perform tail call optimization that do not
1609 // require ABI changes. This is what gcc calls sibcall.
1611 // Do not sibcall optimize vararg calls unless the call site is not passing
1613 if (isVarArg && !Outs.empty())
1616 // Also avoid sibcall optimization if either caller or callee uses struct
1617 // return semantics.
1618 if (isCalleeStructRet || isCallerStructRet)
1621 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
1622 // emitEpilogue is not ready for them.
1623 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
1624 // LR. This means if we need to reload LR, it takes an extra instructions,
1625 // which outweighs the value of the tail call; but here we don't know yet
1626 // whether LR is going to be used. Probably the right approach is to
1627 // generate the tail call here and turn it back into CALL/RET in
1628 // emitEpilogue if LR is used.
1630 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
1631 // but we need to make sure there are enough registers; the only valid
1632 // registers are the 4 used for parameters. We don't currently do this
1634 if (Subtarget->isThumb1Only())
1637 // If the calling conventions do not match, then we'd better make sure the
1638 // results are returned in the same way as what the caller expects.
1640 SmallVector<CCValAssign, 16> RVLocs1;
1641 CCState CCInfo1(CalleeCC, false, getTargetMachine(),
1642 RVLocs1, *DAG.getContext());
1643 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
1645 SmallVector<CCValAssign, 16> RVLocs2;
1646 CCState CCInfo2(CallerCC, false, getTargetMachine(),
1647 RVLocs2, *DAG.getContext());
1648 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
1650 if (RVLocs1.size() != RVLocs2.size())
1652 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
1653 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
1655 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
1657 if (RVLocs1[i].isRegLoc()) {
1658 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
1661 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
1667 // If the callee takes no arguments then go on to check the results of the
1669 if (!Outs.empty()) {
1670 // Check if stack adjustment is needed. For now, do not do this if any
1671 // argument is passed on the stack.
1672 SmallVector<CCValAssign, 16> ArgLocs;
1673 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
1674 ArgLocs, *DAG.getContext());
1675 CCInfo.AnalyzeCallOperands(Outs,
1676 CCAssignFnForNode(CalleeCC, false, isVarArg));
1677 if (CCInfo.getNextStackOffset()) {
1678 MachineFunction &MF = DAG.getMachineFunction();
1680 // Check if the arguments are already laid out in the right way as
1681 // the caller's fixed stack objects.
1682 MachineFrameInfo *MFI = MF.getFrameInfo();
1683 const MachineRegisterInfo *MRI = &MF.getRegInfo();
1684 const ARMInstrInfo *TII =
1685 ((ARMTargetMachine&)getTargetMachine()).getInstrInfo();
1686 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1688 ++i, ++realArgIdx) {
1689 CCValAssign &VA = ArgLocs[i];
1690 EVT RegVT = VA.getLocVT();
1691 SDValue Arg = OutVals[realArgIdx];
1692 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1693 if (VA.getLocInfo() == CCValAssign::Indirect)
1695 if (VA.needsCustom()) {
1696 // f64 and vector types are split into multiple registers or
1697 // register/stack-slot combinations. The types will not match
1698 // the registers; give up on memory f64 refs until we figure
1699 // out what to do about this.
1702 if (!ArgLocs[++i].isRegLoc())
1704 if (RegVT == MVT::v2f64) {
1705 if (!ArgLocs[++i].isRegLoc())
1707 if (!ArgLocs[++i].isRegLoc())
1710 } else if (!VA.isRegLoc()) {
1711 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
1723 ARMTargetLowering::LowerReturn(SDValue Chain,
1724 CallingConv::ID CallConv, bool isVarArg,
1725 const SmallVectorImpl<ISD::OutputArg> &Outs,
1726 const SmallVectorImpl<SDValue> &OutVals,
1727 DebugLoc dl, SelectionDAG &DAG) const {
1729 // CCValAssign - represent the assignment of the return value to a location.
1730 SmallVector<CCValAssign, 16> RVLocs;
1732 // CCState - Info about the registers and stack slots.
1733 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
1736 // Analyze outgoing return values.
1737 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1740 // If this is the first return lowered for this function, add
1741 // the regs to the liveout set for the function.
1742 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1743 for (unsigned i = 0; i != RVLocs.size(); ++i)
1744 if (RVLocs[i].isRegLoc())
1745 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1750 // Copy the result values into the output registers.
1751 for (unsigned i = 0, realRVLocIdx = 0;
1753 ++i, ++realRVLocIdx) {
1754 CCValAssign &VA = RVLocs[i];
1755 assert(VA.isRegLoc() && "Can only return in registers!");
1757 SDValue Arg = OutVals[realRVLocIdx];
1759 switch (VA.getLocInfo()) {
1760 default: llvm_unreachable("Unknown loc info!");
1761 case CCValAssign::Full: break;
1762 case CCValAssign::BCvt:
1763 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1767 if (VA.needsCustom()) {
1768 if (VA.getLocVT() == MVT::v2f64) {
1769 // Extract the first half and return it in two registers.
1770 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1771 DAG.getConstant(0, MVT::i32));
1772 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
1773 DAG.getVTList(MVT::i32, MVT::i32), Half);
1775 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1776 Flag = Chain.getValue(1);
1777 VA = RVLocs[++i]; // skip ahead to next loc
1778 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1779 HalfGPRs.getValue(1), Flag);
1780 Flag = Chain.getValue(1);
1781 VA = RVLocs[++i]; // skip ahead to next loc
1783 // Extract the 2nd half and fall through to handle it as an f64 value.
1784 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1785 DAG.getConstant(1, MVT::i32));
1787 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1789 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1790 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1791 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1792 Flag = Chain.getValue(1);
1793 VA = RVLocs[++i]; // skip ahead to next loc
1794 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1797 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1799 // Guarantee that all emitted copies are
1800 // stuck together, avoiding something bad.
1801 Flag = Chain.getValue(1);
1806 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1808 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1813 bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N) const {
1814 if (N->getNumValues() != 1)
1816 if (!N->hasNUsesOfValue(1, 0))
1819 unsigned NumCopies = 0;
1821 SDNode *Use = *N->use_begin();
1822 if (Use->getOpcode() == ISD::CopyToReg) {
1823 Copies[NumCopies++] = Use;
1824 } else if (Use->getOpcode() == ARMISD::VMOVRRD) {
1825 // f64 returned in a pair of GPRs.
1826 for (SDNode::use_iterator UI = Use->use_begin(), UE = Use->use_end();
1828 if (UI->getOpcode() != ISD::CopyToReg)
1830 Copies[UI.getUse().getResNo()] = *UI;
1833 } else if (Use->getOpcode() == ISD::BITCAST) {
1834 // f32 returned in a single GPR.
1835 if (!Use->hasNUsesOfValue(1, 0))
1837 Use = *Use->use_begin();
1838 if (Use->getOpcode() != ISD::CopyToReg || !Use->hasNUsesOfValue(1, 0))
1840 Copies[NumCopies++] = Use;
1845 if (NumCopies != 1 && NumCopies != 2)
1848 bool HasRet = false;
1849 for (unsigned i = 0; i < NumCopies; ++i) {
1850 SDNode *Copy = Copies[i];
1851 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1853 if (UI->getOpcode() == ISD::CopyToReg) {
1855 if (Use == Copies[0] || Use == Copies[1])
1859 if (UI->getOpcode() != ARMISD::RET_FLAG)
1868 bool ARMTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1869 if (!EnableARMTailCalls)
1872 if (!CI->isTailCall())
1875 return !Subtarget->isThumb1Only();
1878 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1879 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1880 // one of the above mentioned nodes. It has to be wrapped because otherwise
1881 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1882 // be used to form addressing mode. These wrapped nodes will be selected
1884 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1885 EVT PtrVT = Op.getValueType();
1886 // FIXME there is no actual debug info here
1887 DebugLoc dl = Op.getDebugLoc();
1888 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1890 if (CP->isMachineConstantPoolEntry())
1891 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1892 CP->getAlignment());
1894 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1895 CP->getAlignment());
1896 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1899 unsigned ARMTargetLowering::getJumpTableEncoding() const {
1900 return MachineJumpTableInfo::EK_Inline;
1903 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
1904 SelectionDAG &DAG) const {
1905 MachineFunction &MF = DAG.getMachineFunction();
1906 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1907 unsigned ARMPCLabelIndex = 0;
1908 DebugLoc DL = Op.getDebugLoc();
1909 EVT PtrVT = getPointerTy();
1910 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1911 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1913 if (RelocM == Reloc::Static) {
1914 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
1916 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1917 ARMPCLabelIndex = AFI->createPICLabelUId();
1918 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(BA, ARMPCLabelIndex,
1919 ARMCP::CPBlockAddress,
1921 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1923 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
1924 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
1925 MachinePointerInfo::getConstantPool(),
1927 if (RelocM == Reloc::Static)
1929 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1930 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
1933 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
1935 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1936 SelectionDAG &DAG) const {
1937 DebugLoc dl = GA->getDebugLoc();
1938 EVT PtrVT = getPointerTy();
1939 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1940 MachineFunction &MF = DAG.getMachineFunction();
1941 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1942 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1943 ARMConstantPoolValue *CPV =
1944 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1945 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
1946 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1947 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
1948 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
1949 MachinePointerInfo::getConstantPool(),
1951 SDValue Chain = Argument.getValue(1);
1953 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1954 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
1956 // call __tls_get_addr.
1959 Entry.Node = Argument;
1960 Entry.Ty = (const Type *) Type::getInt32Ty(*DAG.getContext());
1961 Args.push_back(Entry);
1962 // FIXME: is there useful debug info available here?
1963 std::pair<SDValue, SDValue> CallResult =
1964 LowerCallTo(Chain, (const Type *) Type::getInt32Ty(*DAG.getContext()),
1965 false, false, false, false,
1966 0, CallingConv::C, false, /*isReturnValueUsed=*/true,
1967 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
1968 return CallResult.first;
1971 // Lower ISD::GlobalTLSAddress using the "initial exec" or
1972 // "local exec" model.
1974 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
1975 SelectionDAG &DAG) const {
1976 const GlobalValue *GV = GA->getGlobal();
1977 DebugLoc dl = GA->getDebugLoc();
1979 SDValue Chain = DAG.getEntryNode();
1980 EVT PtrVT = getPointerTy();
1981 // Get the Thread Pointer
1982 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1984 if (GV->isDeclaration()) {
1985 MachineFunction &MF = DAG.getMachineFunction();
1986 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1987 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1988 // Initial exec model.
1989 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1990 ARMConstantPoolValue *CPV =
1991 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1992 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF, true);
1993 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1994 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1995 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1996 MachinePointerInfo::getConstantPool(),
1998 Chain = Offset.getValue(1);
2000 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2001 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
2003 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2004 MachinePointerInfo::getConstantPool(),
2008 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMCP::TPOFF);
2009 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2010 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2011 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2012 MachinePointerInfo::getConstantPool(),
2016 // The address of the thread local variable is the add of the thread
2017 // pointer with the offset of the variable.
2018 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
2022 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
2023 // TODO: implement the "local dynamic" model
2024 assert(Subtarget->isTargetELF() &&
2025 "TLS not implemented for non-ELF targets");
2026 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2027 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
2028 // otherwise use the "Local Exec" TLS Model
2029 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
2030 return LowerToTLSGeneralDynamicModel(GA, DAG);
2032 return LowerToTLSExecModels(GA, DAG);
2035 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
2036 SelectionDAG &DAG) const {
2037 EVT PtrVT = getPointerTy();
2038 DebugLoc dl = Op.getDebugLoc();
2039 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2040 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2041 if (RelocM == Reloc::PIC_) {
2042 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
2043 ARMConstantPoolValue *CPV =
2044 new ARMConstantPoolValue(GV, UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
2045 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2046 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2047 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
2049 MachinePointerInfo::getConstantPool(),
2051 SDValue Chain = Result.getValue(1);
2052 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
2053 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
2055 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
2056 MachinePointerInfo::getGOT(), false, false, 0);
2060 // If we have T2 ops, we can materialize the address directly via movt/movw
2061 // pair. This is always cheaper.
2062 if (Subtarget->useMovt()) {
2064 // FIXME: Once remat is capable of dealing with instructions with register
2065 // operands, expand this into two nodes.
2066 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2067 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2069 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
2070 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2071 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2072 MachinePointerInfo::getConstantPool(),
2077 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
2078 SelectionDAG &DAG) const {
2079 EVT PtrVT = getPointerTy();
2080 DebugLoc dl = Op.getDebugLoc();
2081 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2082 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2083 MachineFunction &MF = DAG.getMachineFunction();
2084 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2086 // FIXME: Enable this for static codegen when tool issues are fixed.
2087 if (Subtarget->useMovt() && RelocM != Reloc::Static) {
2089 // FIXME: Once remat is capable of dealing with instructions with register
2090 // operands, expand this into two nodes.
2091 if (RelocM == Reloc::Static)
2092 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2093 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2095 unsigned Wrapper = (RelocM == Reloc::PIC_)
2096 ? ARMISD::WrapperPIC : ARMISD::WrapperDYN;
2097 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT,
2098 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2099 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
2100 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
2101 MachinePointerInfo::getGOT(), false, false, 0);
2105 unsigned ARMPCLabelIndex = 0;
2107 if (RelocM == Reloc::Static) {
2108 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
2110 ARMPCLabelIndex = AFI->createPICLabelUId();
2111 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8);
2112 ARMConstantPoolValue *CPV =
2113 new ARMConstantPoolValue(GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj);
2114 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2116 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2118 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2119 MachinePointerInfo::getConstantPool(),
2121 SDValue Chain = Result.getValue(1);
2123 if (RelocM == Reloc::PIC_) {
2124 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2125 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2128 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
2129 Result = DAG.getLoad(PtrVT, dl, Chain, Result, MachinePointerInfo::getGOT(),
2135 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
2136 SelectionDAG &DAG) const {
2137 assert(Subtarget->isTargetELF() &&
2138 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
2139 MachineFunction &MF = DAG.getMachineFunction();
2140 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2141 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2142 EVT PtrVT = getPointerTy();
2143 DebugLoc dl = Op.getDebugLoc();
2144 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2145 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
2146 "_GLOBAL_OFFSET_TABLE_",
2147 ARMPCLabelIndex, PCAdj);
2148 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2149 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2150 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2151 MachinePointerInfo::getConstantPool(),
2153 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2154 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2158 ARMTargetLowering::LowerEH_SJLJ_DISPATCHSETUP(SDValue Op, SelectionDAG &DAG)
2160 DebugLoc dl = Op.getDebugLoc();
2161 return DAG.getNode(ARMISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other,
2162 Op.getOperand(0), Op.getOperand(1));
2166 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
2167 DebugLoc dl = Op.getDebugLoc();
2168 SDValue Val = DAG.getConstant(0, MVT::i32);
2169 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(0),
2170 Op.getOperand(1), Val);
2174 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
2175 DebugLoc dl = Op.getDebugLoc();
2176 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
2177 Op.getOperand(1), DAG.getConstant(0, MVT::i32));
2181 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
2182 const ARMSubtarget *Subtarget) const {
2183 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2184 DebugLoc dl = Op.getDebugLoc();
2186 default: return SDValue(); // Don't custom lower most intrinsics.
2187 case Intrinsic::arm_thread_pointer: {
2188 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2189 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2191 case Intrinsic::eh_sjlj_lsda: {
2192 MachineFunction &MF = DAG.getMachineFunction();
2193 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2194 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2195 EVT PtrVT = getPointerTy();
2196 DebugLoc dl = Op.getDebugLoc();
2197 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2199 unsigned PCAdj = (RelocM != Reloc::PIC_)
2200 ? 0 : (Subtarget->isThumb() ? 4 : 8);
2201 ARMConstantPoolValue *CPV =
2202 new ARMConstantPoolValue(MF.getFunction(), ARMPCLabelIndex,
2203 ARMCP::CPLSDA, PCAdj);
2204 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2205 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2207 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2208 MachinePointerInfo::getConstantPool(),
2211 if (RelocM == Reloc::PIC_) {
2212 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2213 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2217 case Intrinsic::arm_neon_vmulls:
2218 case Intrinsic::arm_neon_vmullu: {
2219 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
2220 ? ARMISD::VMULLs : ARMISD::VMULLu;
2221 return DAG.getNode(NewOpc, Op.getDebugLoc(), Op.getValueType(),
2222 Op.getOperand(1), Op.getOperand(2));
2227 static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG,
2228 const ARMSubtarget *Subtarget) {
2229 DebugLoc dl = Op.getDebugLoc();
2230 if (!Subtarget->hasDataBarrier()) {
2231 // Some ARMv6 cpus can support data barriers with an mcr instruction.
2232 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
2234 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&
2235 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!");
2236 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2237 DAG.getConstant(0, MVT::i32));
2240 SDValue Op5 = Op.getOperand(5);
2241 bool isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue() != 0;
2242 unsigned isLL = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
2243 unsigned isLS = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
2244 bool isOnlyStoreBarrier = (isLL == 0 && isLS == 0);
2246 ARM_MB::MemBOpt DMBOpt;
2247 if (isDeviceBarrier)
2248 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ST : ARM_MB::SY;
2250 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ISHST : ARM_MB::ISH;
2251 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
2252 DAG.getConstant(DMBOpt, MVT::i32));
2255 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
2256 const ARMSubtarget *Subtarget) {
2257 // ARM pre v5TE and Thumb1 does not have preload instructions.
2258 if (!(Subtarget->isThumb2() ||
2259 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
2260 // Just preserve the chain.
2261 return Op.getOperand(0);
2263 DebugLoc dl = Op.getDebugLoc();
2264 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
2266 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
2267 // ARMv7 with MP extension has PLDW.
2268 return Op.getOperand(0);
2270 if (Subtarget->isThumb())
2272 isRead = ~isRead & 1;
2273 unsigned isData = Subtarget->isThumb() ? 0 : 1;
2275 // Currently there is no intrinsic that matches pli.
2276 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
2277 Op.getOperand(1), DAG.getConstant(isRead, MVT::i32),
2278 DAG.getConstant(isData, MVT::i32));
2281 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
2282 MachineFunction &MF = DAG.getMachineFunction();
2283 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
2285 // vastart just stores the address of the VarArgsFrameIndex slot into the
2286 // memory location argument.
2287 DebugLoc dl = Op.getDebugLoc();
2288 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2289 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2290 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2291 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2292 MachinePointerInfo(SV), false, false, 0);
2296 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
2297 SDValue &Root, SelectionDAG &DAG,
2298 DebugLoc dl) const {
2299 MachineFunction &MF = DAG.getMachineFunction();
2300 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2302 TargetRegisterClass *RC;
2303 if (AFI->isThumb1OnlyFunction())
2304 RC = ARM::tGPRRegisterClass;
2306 RC = ARM::GPRRegisterClass;
2308 // Transform the arguments stored in physical registers into virtual ones.
2309 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2310 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2313 if (NextVA.isMemLoc()) {
2314 MachineFrameInfo *MFI = MF.getFrameInfo();
2315 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
2317 // Create load node to retrieve arguments from the stack.
2318 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2319 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
2320 MachinePointerInfo::getFixedStack(FI),
2323 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2324 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2327 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
2331 ARMTargetLowering::computeRegArea(CCState &CCInfo, MachineFunction &MF,
2332 unsigned &VARegSize, unsigned &VARegSaveSize)
2335 if (CCInfo.isFirstByValRegValid())
2336 NumGPRs = ARM::R4 - CCInfo.getFirstByValReg();
2338 unsigned int firstUnalloced;
2339 firstUnalloced = CCInfo.getFirstUnallocated(GPRArgRegs,
2340 sizeof(GPRArgRegs) /
2341 sizeof(GPRArgRegs[0]));
2342 NumGPRs = (firstUnalloced <= 3) ? (4 - firstUnalloced) : 0;
2345 unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment();
2346 VARegSize = NumGPRs * 4;
2347 VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
2350 // The remaining GPRs hold either the beginning of variable-argument
2351 // data, or the beginning of an aggregate passed by value (usuall
2352 // byval). Either way, we allocate stack slots adjacent to the data
2353 // provided by our caller, and store the unallocated registers there.
2354 // If this is a variadic function, the va_list pointer will begin with
2355 // these values; otherwise, this reassembles a (byval) structure that
2356 // was split between registers and memory.
2358 ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
2359 DebugLoc dl, SDValue &Chain,
2360 unsigned ArgOffset) const {
2361 MachineFunction &MF = DAG.getMachineFunction();
2362 MachineFrameInfo *MFI = MF.getFrameInfo();
2363 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2364 unsigned firstRegToSaveIndex;
2365 if (CCInfo.isFirstByValRegValid())
2366 firstRegToSaveIndex = CCInfo.getFirstByValReg() - ARM::R0;
2368 firstRegToSaveIndex = CCInfo.getFirstUnallocated
2369 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
2372 unsigned VARegSize, VARegSaveSize;
2373 computeRegArea(CCInfo, MF, VARegSize, VARegSaveSize);
2374 if (VARegSaveSize) {
2375 // If this function is vararg, store any remaining integer argument regs
2376 // to their spots on the stack so that they may be loaded by deferencing
2377 // the result of va_next.
2378 AFI->setVarArgsRegSaveSize(VARegSaveSize);
2379 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(VARegSaveSize,
2380 ArgOffset + VARegSaveSize
2383 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(),
2386 SmallVector<SDValue, 4> MemOps;
2387 for (; firstRegToSaveIndex < 4; ++firstRegToSaveIndex) {
2388 TargetRegisterClass *RC;
2389 if (AFI->isThumb1OnlyFunction())
2390 RC = ARM::tGPRRegisterClass;
2392 RC = ARM::GPRRegisterClass;
2394 unsigned VReg = MF.addLiveIn(GPRArgRegs[firstRegToSaveIndex], RC);
2395 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2397 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2398 MachinePointerInfo::getFixedStack(AFI->getVarArgsFrameIndex()),
2400 MemOps.push_back(Store);
2401 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
2402 DAG.getConstant(4, getPointerTy()));
2404 if (!MemOps.empty())
2405 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2406 &MemOps[0], MemOps.size());
2408 // This will point to the next argument passed via stack.
2409 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset, true));
2413 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
2414 CallingConv::ID CallConv, bool isVarArg,
2415 const SmallVectorImpl<ISD::InputArg>
2417 DebugLoc dl, SelectionDAG &DAG,
2418 SmallVectorImpl<SDValue> &InVals)
2420 MachineFunction &MF = DAG.getMachineFunction();
2421 MachineFrameInfo *MFI = MF.getFrameInfo();
2423 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2425 // Assign locations to all of the incoming arguments.
2426 SmallVector<CCValAssign, 16> ArgLocs;
2427 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
2429 CCInfo.setCallOrPrologue(Prologue);
2430 CCInfo.AnalyzeFormalArguments(Ins,
2431 CCAssignFnForNode(CallConv, /* Return*/ false,
2434 SmallVector<SDValue, 16> ArgValues;
2435 int lastInsIndex = -1;
2438 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2439 CCValAssign &VA = ArgLocs[i];
2441 // Arguments stored in registers.
2442 if (VA.isRegLoc()) {
2443 EVT RegVT = VA.getLocVT();
2445 if (VA.needsCustom()) {
2446 // f64 and vector types are split up into multiple registers or
2447 // combinations of registers and stack slots.
2448 if (VA.getLocVT() == MVT::v2f64) {
2449 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
2451 VA = ArgLocs[++i]; // skip ahead to next loc
2453 if (VA.isMemLoc()) {
2454 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
2455 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2456 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
2457 MachinePointerInfo::getFixedStack(FI),
2460 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
2463 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2464 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2465 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
2466 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2467 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
2469 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
2472 TargetRegisterClass *RC;
2474 if (RegVT == MVT::f32)
2475 RC = ARM::SPRRegisterClass;
2476 else if (RegVT == MVT::f64)
2477 RC = ARM::DPRRegisterClass;
2478 else if (RegVT == MVT::v2f64)
2479 RC = ARM::QPRRegisterClass;
2480 else if (RegVT == MVT::i32)
2481 RC = (AFI->isThumb1OnlyFunction() ?
2482 ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
2484 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2486 // Transform the arguments in physical registers into virtual ones.
2487 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2488 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2491 // If this is an 8 or 16-bit value, it is really passed promoted
2492 // to 32 bits. Insert an assert[sz]ext to capture this, then
2493 // truncate to the right size.
2494 switch (VA.getLocInfo()) {
2495 default: llvm_unreachable("Unknown loc info!");
2496 case CCValAssign::Full: break;
2497 case CCValAssign::BCvt:
2498 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2500 case CCValAssign::SExt:
2501 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2502 DAG.getValueType(VA.getValVT()));
2503 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2505 case CCValAssign::ZExt:
2506 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2507 DAG.getValueType(VA.getValVT()));
2508 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2512 InVals.push_back(ArgValue);
2514 } else { // VA.isRegLoc()
2517 assert(VA.isMemLoc());
2518 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
2520 int index = ArgLocs[i].getValNo();
2522 // Some Ins[] entries become multiple ArgLoc[] entries.
2523 // Process them only once.
2524 if (index != lastInsIndex)
2526 ISD::ArgFlagsTy Flags = Ins[index].Flags;
2527 // FIXME: For now, all byval parameter objects are marked mutable.
2528 // This can be changed with more analysis.
2529 // In case of tail call optimization mark all arguments mutable.
2530 // Since they could be overwritten by lowering of arguments in case of
2532 if (Flags.isByVal()) {
2533 unsigned VARegSize, VARegSaveSize;
2534 computeRegArea(CCInfo, MF, VARegSize, VARegSaveSize);
2535 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, 0);
2536 unsigned Bytes = Flags.getByValSize() - VARegSize;
2537 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2538 int FI = MFI->CreateFixedObject(Bytes,
2539 VA.getLocMemOffset(), false);
2540 InVals.push_back(DAG.getFrameIndex(FI, getPointerTy()));
2542 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
2543 VA.getLocMemOffset(), true);
2545 // Create load nodes to retrieve arguments from the stack.
2546 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2547 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2548 MachinePointerInfo::getFixedStack(FI),
2551 lastInsIndex = index;
2558 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, CCInfo.getNextStackOffset());
2563 /// isFloatingPointZero - Return true if this is +0.0.
2564 static bool isFloatingPointZero(SDValue Op) {
2565 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
2566 return CFP->getValueAPF().isPosZero();
2567 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
2568 // Maybe this has already been legalized into the constant pool?
2569 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
2570 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
2571 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
2572 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
2573 return CFP->getValueAPF().isPosZero();
2579 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
2580 /// the given operands.
2582 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2583 SDValue &ARMcc, SelectionDAG &DAG,
2584 DebugLoc dl) const {
2585 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
2586 unsigned C = RHSC->getZExtValue();
2587 if (!isLegalICmpImmediate(C)) {
2588 // Constant does not fit, try adjusting it by one?
2593 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
2594 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
2595 RHS = DAG.getConstant(C-1, MVT::i32);
2600 if (C != 0 && isLegalICmpImmediate(C-1)) {
2601 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
2602 RHS = DAG.getConstant(C-1, MVT::i32);
2607 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
2608 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
2609 RHS = DAG.getConstant(C+1, MVT::i32);
2614 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
2615 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2616 RHS = DAG.getConstant(C+1, MVT::i32);
2623 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2624 ARMISD::NodeType CompareType;
2627 CompareType = ARMISD::CMP;
2632 CompareType = ARMISD::CMPZ;
2635 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2636 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
2639 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
2641 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
2642 DebugLoc dl) const {
2644 if (!isFloatingPointZero(RHS))
2645 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS);
2647 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS);
2648 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
2651 /// duplicateCmp - Glue values can have only one use, so this function
2652 /// duplicates a comparison node.
2654 ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
2655 unsigned Opc = Cmp.getOpcode();
2656 DebugLoc DL = Cmp.getDebugLoc();
2657 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
2658 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
2660 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation");
2661 Cmp = Cmp.getOperand(0);
2662 Opc = Cmp.getOpcode();
2663 if (Opc == ARMISD::CMPFP)
2664 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
2666 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT");
2667 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0));
2669 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
2672 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2673 SDValue Cond = Op.getOperand(0);
2674 SDValue SelectTrue = Op.getOperand(1);
2675 SDValue SelectFalse = Op.getOperand(2);
2676 DebugLoc dl = Op.getDebugLoc();
2680 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
2681 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
2683 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
2684 const ConstantSDNode *CMOVTrue =
2685 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
2686 const ConstantSDNode *CMOVFalse =
2687 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
2689 if (CMOVTrue && CMOVFalse) {
2690 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
2691 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
2695 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
2697 False = SelectFalse;
2698 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
2703 if (True.getNode() && False.getNode()) {
2704 EVT VT = Op.getValueType();
2705 SDValue ARMcc = Cond.getOperand(2);
2706 SDValue CCR = Cond.getOperand(3);
2707 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
2708 assert(True.getValueType() == VT);
2709 return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp);
2714 return DAG.getSelectCC(dl, Cond,
2715 DAG.getConstant(0, Cond.getValueType()),
2716 SelectTrue, SelectFalse, ISD::SETNE);
2719 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
2720 EVT VT = Op.getValueType();
2721 SDValue LHS = Op.getOperand(0);
2722 SDValue RHS = Op.getOperand(1);
2723 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2724 SDValue TrueVal = Op.getOperand(2);
2725 SDValue FalseVal = Op.getOperand(3);
2726 DebugLoc dl = Op.getDebugLoc();
2728 if (LHS.getValueType() == MVT::i32) {
2730 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2731 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2732 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,Cmp);
2735 ARMCC::CondCodes CondCode, CondCode2;
2736 FPCCToARMCC(CC, CondCode, CondCode2);
2738 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2739 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2740 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2741 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
2743 if (CondCode2 != ARMCC::AL) {
2744 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32);
2745 // FIXME: Needs another CMP because flag can have but one use.
2746 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
2747 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
2748 Result, TrueVal, ARMcc2, CCR, Cmp2);
2753 /// canChangeToInt - Given the fp compare operand, return true if it is suitable
2754 /// to morph to an integer compare sequence.
2755 static bool canChangeToInt(SDValue Op, bool &SeenZero,
2756 const ARMSubtarget *Subtarget) {
2757 SDNode *N = Op.getNode();
2758 if (!N->hasOneUse())
2759 // Otherwise it requires moving the value from fp to integer registers.
2761 if (!N->getNumValues())
2763 EVT VT = Op.getValueType();
2764 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
2765 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
2766 // vmrs are very slow, e.g. cortex-a8.
2769 if (isFloatingPointZero(Op)) {
2773 return ISD::isNormalLoad(N);
2776 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
2777 if (isFloatingPointZero(Op))
2778 return DAG.getConstant(0, MVT::i32);
2780 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
2781 return DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2782 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(),
2783 Ld->isVolatile(), Ld->isNonTemporal(),
2784 Ld->getAlignment());
2786 llvm_unreachable("Unknown VFP cmp argument!");
2789 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
2790 SDValue &RetVal1, SDValue &RetVal2) {
2791 if (isFloatingPointZero(Op)) {
2792 RetVal1 = DAG.getConstant(0, MVT::i32);
2793 RetVal2 = DAG.getConstant(0, MVT::i32);
2797 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
2798 SDValue Ptr = Ld->getBasePtr();
2799 RetVal1 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2800 Ld->getChain(), Ptr,
2801 Ld->getPointerInfo(),
2802 Ld->isVolatile(), Ld->isNonTemporal(),
2803 Ld->getAlignment());
2805 EVT PtrType = Ptr.getValueType();
2806 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
2807 SDValue NewPtr = DAG.getNode(ISD::ADD, Op.getDebugLoc(),
2808 PtrType, Ptr, DAG.getConstant(4, PtrType));
2809 RetVal2 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2810 Ld->getChain(), NewPtr,
2811 Ld->getPointerInfo().getWithOffset(4),
2812 Ld->isVolatile(), Ld->isNonTemporal(),
2817 llvm_unreachable("Unknown VFP cmp argument!");
2820 /// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
2821 /// f32 and even f64 comparisons to integer ones.
2823 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
2824 SDValue Chain = Op.getOperand(0);
2825 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2826 SDValue LHS = Op.getOperand(2);
2827 SDValue RHS = Op.getOperand(3);
2828 SDValue Dest = Op.getOperand(4);
2829 DebugLoc dl = Op.getDebugLoc();
2831 bool SeenZero = false;
2832 if (canChangeToInt(LHS, SeenZero, Subtarget) &&
2833 canChangeToInt(RHS, SeenZero, Subtarget) &&
2834 // If one of the operand is zero, it's safe to ignore the NaN case since
2835 // we only care about equality comparisons.
2836 (SeenZero || (DAG.isKnownNeverNaN(LHS) && DAG.isKnownNeverNaN(RHS)))) {
2837 // If unsafe fp math optimization is enabled and there are no other uses of
2838 // the CMP operands, and the condition code is EQ or NE, we can optimize it
2839 // to an integer comparison.
2840 if (CC == ISD::SETOEQ)
2842 else if (CC == ISD::SETUNE)
2846 if (LHS.getValueType() == MVT::f32) {
2847 LHS = bitcastf32Toi32(LHS, DAG);
2848 RHS = bitcastf32Toi32(RHS, DAG);
2849 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2850 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2851 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2852 Chain, Dest, ARMcc, CCR, Cmp);
2857 expandf64Toi32(LHS, DAG, LHS1, LHS2);
2858 expandf64Toi32(RHS, DAG, RHS1, RHS2);
2859 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2860 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2861 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
2862 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
2863 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7);
2869 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2870 SDValue Chain = Op.getOperand(0);
2871 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2872 SDValue LHS = Op.getOperand(2);
2873 SDValue RHS = Op.getOperand(3);
2874 SDValue Dest = Op.getOperand(4);
2875 DebugLoc dl = Op.getDebugLoc();
2877 if (LHS.getValueType() == MVT::i32) {
2879 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2880 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2881 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2882 Chain, Dest, ARMcc, CCR, Cmp);
2885 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
2888 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
2889 CC == ISD::SETNE || CC == ISD::SETUNE)) {
2890 SDValue Result = OptimizeVFPBrcond(Op, DAG);
2891 if (Result.getNode())
2895 ARMCC::CondCodes CondCode, CondCode2;
2896 FPCCToARMCC(CC, CondCode, CondCode2);
2898 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2899 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2900 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2901 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
2902 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
2903 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2904 if (CondCode2 != ARMCC::AL) {
2905 ARMcc = DAG.getConstant(CondCode2, MVT::i32);
2906 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
2907 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2912 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
2913 SDValue Chain = Op.getOperand(0);
2914 SDValue Table = Op.getOperand(1);
2915 SDValue Index = Op.getOperand(2);
2916 DebugLoc dl = Op.getDebugLoc();
2918 EVT PTy = getPointerTy();
2919 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
2920 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
2921 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
2922 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
2923 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
2924 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
2925 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2926 if (Subtarget->isThumb2()) {
2927 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
2928 // which does another jump to the destination. This also makes it easier
2929 // to translate it to TBB / TBH later.
2930 // FIXME: This might not work if the function is extremely large.
2931 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
2932 Addr, Op.getOperand(2), JTI, UId);
2934 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2935 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
2936 MachinePointerInfo::getJumpTable(),
2938 Chain = Addr.getValue(1);
2939 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
2940 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2942 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
2943 MachinePointerInfo::getJumpTable(), false, false, 0);
2944 Chain = Addr.getValue(1);
2945 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2949 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
2950 DebugLoc dl = Op.getDebugLoc();
2953 switch (Op.getOpcode()) {
2955 assert(0 && "Invalid opcode!");
2956 case ISD::FP_TO_SINT:
2957 Opc = ARMISD::FTOSI;
2959 case ISD::FP_TO_UINT:
2960 Opc = ARMISD::FTOUI;
2963 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
2964 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
2967 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
2968 EVT VT = Op.getValueType();
2969 DebugLoc dl = Op.getDebugLoc();
2971 EVT OperandVT = Op.getOperand(0).getValueType();
2972 assert(OperandVT == MVT::v4i16 && "Invalid type for custom lowering!");
2973 if (VT != MVT::v4f32)
2974 return DAG.UnrollVectorOp(Op.getNode());
2978 switch (Op.getOpcode()) {
2980 assert(0 && "Invalid opcode!");
2981 case ISD::SINT_TO_FP:
2982 CastOpc = ISD::SIGN_EXTEND;
2983 Opc = ISD::SINT_TO_FP;
2985 case ISD::UINT_TO_FP:
2986 CastOpc = ISD::ZERO_EXTEND;
2987 Opc = ISD::UINT_TO_FP;
2991 Op = DAG.getNode(CastOpc, dl, MVT::v4i32, Op.getOperand(0));
2992 return DAG.getNode(Opc, dl, VT, Op);
2995 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
2996 EVT VT = Op.getValueType();
2998 return LowerVectorINT_TO_FP(Op, DAG);
3000 DebugLoc dl = Op.getDebugLoc();
3003 switch (Op.getOpcode()) {
3005 assert(0 && "Invalid opcode!");
3006 case ISD::SINT_TO_FP:
3007 Opc = ARMISD::SITOF;
3009 case ISD::UINT_TO_FP:
3010 Opc = ARMISD::UITOF;
3014 Op = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0));
3015 return DAG.getNode(Opc, dl, VT, Op);
3018 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
3019 // Implement fcopysign with a fabs and a conditional fneg.
3020 SDValue Tmp0 = Op.getOperand(0);
3021 SDValue Tmp1 = Op.getOperand(1);
3022 DebugLoc dl = Op.getDebugLoc();
3023 EVT VT = Op.getValueType();
3024 EVT SrcVT = Tmp1.getValueType();
3025 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
3026 Tmp0.getOpcode() == ARMISD::VMOVDRR;
3027 bool UseNEON = !InGPR && Subtarget->hasNEON();
3030 // Use VBSL to copy the sign bit.
3031 unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80);
3032 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
3033 DAG.getTargetConstant(EncodedVal, MVT::i32));
3034 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
3036 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT,
3037 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
3038 DAG.getConstant(32, MVT::i32));
3039 else /*if (VT == MVT::f32)*/
3040 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
3041 if (SrcVT == MVT::f32) {
3042 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
3044 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT,
3045 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
3046 DAG.getConstant(32, MVT::i32));
3047 } else if (VT == MVT::f32)
3048 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64,
3049 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
3050 DAG.getConstant(32, MVT::i32));
3051 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
3052 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
3054 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff),
3056 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
3057 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
3058 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
3060 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
3061 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
3062 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
3063 if (VT == MVT::f32) {
3064 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
3065 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
3066 DAG.getConstant(0, MVT::i32));
3068 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
3074 // Bitcast operand 1 to i32.
3075 if (SrcVT == MVT::f64)
3076 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
3077 &Tmp1, 1).getValue(1);
3078 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
3080 // Or in the signbit with integer operations.
3081 SDValue Mask1 = DAG.getConstant(0x80000000, MVT::i32);
3082 SDValue Mask2 = DAG.getConstant(0x7fffffff, MVT::i32);
3083 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
3084 if (VT == MVT::f32) {
3085 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
3086 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
3087 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3088 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
3091 // f64: Or the high part with signbit and then combine two parts.
3092 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
3094 SDValue Lo = Tmp0.getValue(0);
3095 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
3096 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
3097 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
3100 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
3101 MachineFunction &MF = DAG.getMachineFunction();
3102 MachineFrameInfo *MFI = MF.getFrameInfo();
3103 MFI->setReturnAddressIsTaken(true);
3105 EVT VT = Op.getValueType();
3106 DebugLoc dl = Op.getDebugLoc();
3107 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3109 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
3110 SDValue Offset = DAG.getConstant(4, MVT::i32);
3111 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
3112 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
3113 MachinePointerInfo(), false, false, 0);
3116 // Return LR, which contains the return address. Mark it an implicit live-in.
3117 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
3118 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
3121 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
3122 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3123 MFI->setFrameAddressIsTaken(true);
3125 EVT VT = Op.getValueType();
3126 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
3127 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3128 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
3129 ? ARM::R7 : ARM::R11;
3130 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
3132 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
3133 MachinePointerInfo(),
3138 /// ExpandBITCAST - If the target supports VFP, this function is called to
3139 /// expand a bit convert where either the source or destination type is i64 to
3140 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
3141 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
3142 /// vectors), since the legalizer won't know what to do with that.
3143 static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) {
3144 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3145 DebugLoc dl = N->getDebugLoc();
3146 SDValue Op = N->getOperand(0);
3148 // This function is only supposed to be called for i64 types, either as the
3149 // source or destination of the bit convert.
3150 EVT SrcVT = Op.getValueType();
3151 EVT DstVT = N->getValueType(0);
3152 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
3153 "ExpandBITCAST called for non-i64 type");
3155 // Turn i64->f64 into VMOVDRR.
3156 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
3157 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
3158 DAG.getConstant(0, MVT::i32));
3159 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
3160 DAG.getConstant(1, MVT::i32));
3161 return DAG.getNode(ISD::BITCAST, dl, DstVT,
3162 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
3165 // Turn f64->i64 into VMOVRRD.
3166 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
3167 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
3168 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
3169 // Merge the pieces into a single i64 value.
3170 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
3176 /// getZeroVector - Returns a vector of specified type with all zero elements.
3177 /// Zero vectors are used to represent vector negation and in those cases
3178 /// will be implemented with the NEON VNEG instruction. However, VNEG does
3179 /// not support i64 elements, so sometimes the zero vectors will need to be
3180 /// explicitly constructed. Regardless, use a canonical VMOV to create the
3182 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3183 assert(VT.isVector() && "Expected a vector type");
3184 // The canonical modified immediate encoding of a zero vector is....0!
3185 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32);
3186 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
3187 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
3188 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3191 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
3192 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
3193 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
3194 SelectionDAG &DAG) const {
3195 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3196 EVT VT = Op.getValueType();
3197 unsigned VTBits = VT.getSizeInBits();
3198 DebugLoc dl = Op.getDebugLoc();
3199 SDValue ShOpLo = Op.getOperand(0);
3200 SDValue ShOpHi = Op.getOperand(1);
3201 SDValue ShAmt = Op.getOperand(2);
3203 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
3205 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
3207 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
3208 DAG.getConstant(VTBits, MVT::i32), ShAmt);
3209 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
3210 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
3211 DAG.getConstant(VTBits, MVT::i32));
3212 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
3213 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3214 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
3216 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3217 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
3219 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
3220 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
3223 SDValue Ops[2] = { Lo, Hi };
3224 return DAG.getMergeValues(Ops, 2, dl);
3227 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
3228 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
3229 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
3230 SelectionDAG &DAG) const {
3231 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3232 EVT VT = Op.getValueType();
3233 unsigned VTBits = VT.getSizeInBits();
3234 DebugLoc dl = Op.getDebugLoc();
3235 SDValue ShOpLo = Op.getOperand(0);
3236 SDValue ShOpHi = Op.getOperand(1);
3237 SDValue ShAmt = Op.getOperand(2);
3240 assert(Op.getOpcode() == ISD::SHL_PARTS);
3241 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
3242 DAG.getConstant(VTBits, MVT::i32), ShAmt);
3243 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
3244 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
3245 DAG.getConstant(VTBits, MVT::i32));
3246 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
3247 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
3249 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3250 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3251 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
3253 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
3254 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
3257 SDValue Ops[2] = { Lo, Hi };
3258 return DAG.getMergeValues(Ops, 2, dl);
3261 SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
3262 SelectionDAG &DAG) const {
3263 // The rounding mode is in bits 23:22 of the FPSCR.
3264 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
3265 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
3266 // so that the shift + and get folded into a bitfield extract.
3267 DebugLoc dl = Op.getDebugLoc();
3268 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
3269 DAG.getConstant(Intrinsic::arm_get_fpscr,
3271 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
3272 DAG.getConstant(1U << 22, MVT::i32));
3273 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
3274 DAG.getConstant(22, MVT::i32));
3275 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
3276 DAG.getConstant(3, MVT::i32));
3279 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
3280 const ARMSubtarget *ST) {
3281 EVT VT = N->getValueType(0);
3282 DebugLoc dl = N->getDebugLoc();
3284 if (!ST->hasV6T2Ops())
3287 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
3288 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
3291 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
3292 const ARMSubtarget *ST) {
3293 EVT VT = N->getValueType(0);
3294 DebugLoc dl = N->getDebugLoc();
3299 // Lower vector shifts on NEON to use VSHL.
3300 assert(ST->hasNEON() && "unexpected vector shift");
3302 // Left shifts translate directly to the vshiftu intrinsic.
3303 if (N->getOpcode() == ISD::SHL)
3304 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
3305 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
3306 N->getOperand(0), N->getOperand(1));
3308 assert((N->getOpcode() == ISD::SRA ||
3309 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
3311 // NEON uses the same intrinsics for both left and right shifts. For
3312 // right shifts, the shift amounts are negative, so negate the vector of
3314 EVT ShiftVT = N->getOperand(1).getValueType();
3315 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
3316 getZeroVector(ShiftVT, DAG, dl),
3318 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
3319 Intrinsic::arm_neon_vshifts :
3320 Intrinsic::arm_neon_vshiftu);
3321 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
3322 DAG.getConstant(vshiftInt, MVT::i32),
3323 N->getOperand(0), NegatedCount);
3326 static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
3327 const ARMSubtarget *ST) {
3328 EVT VT = N->getValueType(0);
3329 DebugLoc dl = N->getDebugLoc();
3331 // We can get here for a node like i32 = ISD::SHL i32, i64
3335 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
3336 "Unknown shift to lower!");
3338 // We only lower SRA, SRL of 1 here, all others use generic lowering.
3339 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
3340 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
3343 // If we are in thumb mode, we don't have RRX.
3344 if (ST->isThumb1Only()) return SDValue();
3346 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
3347 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
3348 DAG.getConstant(0, MVT::i32));
3349 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
3350 DAG.getConstant(1, MVT::i32));
3352 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
3353 // captures the result into a carry flag.
3354 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
3355 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), &Hi, 1);
3357 // The low part is an ARMISD::RRX operand, which shifts the carry in.
3358 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
3360 // Merge the pieces into a single i64 value.
3361 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
3364 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
3365 SDValue TmpOp0, TmpOp1;
3366 bool Invert = false;
3370 SDValue Op0 = Op.getOperand(0);
3371 SDValue Op1 = Op.getOperand(1);
3372 SDValue CC = Op.getOperand(2);
3373 EVT VT = Op.getValueType();
3374 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
3375 DebugLoc dl = Op.getDebugLoc();
3377 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
3378 switch (SetCCOpcode) {
3379 default: llvm_unreachable("Illegal FP comparison"); break;
3381 case ISD::SETNE: Invert = true; // Fallthrough
3383 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3385 case ISD::SETLT: Swap = true; // Fallthrough
3387 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3389 case ISD::SETLE: Swap = true; // Fallthrough
3391 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3392 case ISD::SETUGE: Swap = true; // Fallthrough
3393 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
3394 case ISD::SETUGT: Swap = true; // Fallthrough
3395 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
3396 case ISD::SETUEQ: Invert = true; // Fallthrough
3398 // Expand this to (OLT | OGT).
3402 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3403 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
3405 case ISD::SETUO: Invert = true; // Fallthrough
3407 // Expand this to (OLT | OGE).
3411 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3412 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
3416 // Integer comparisons.
3417 switch (SetCCOpcode) {
3418 default: llvm_unreachable("Illegal integer comparison"); break;
3419 case ISD::SETNE: Invert = true;
3420 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3421 case ISD::SETLT: Swap = true;
3422 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3423 case ISD::SETLE: Swap = true;
3424 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3425 case ISD::SETULT: Swap = true;
3426 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
3427 case ISD::SETULE: Swap = true;
3428 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
3431 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
3432 if (Opc == ARMISD::VCEQ) {
3435 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
3437 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
3440 // Ignore bitconvert.
3441 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST)
3442 AndOp = AndOp.getOperand(0);
3444 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
3446 Op0 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(0));
3447 Op1 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(1));
3454 std::swap(Op0, Op1);
3456 // If one of the operands is a constant vector zero, attempt to fold the
3457 // comparison to a specialized compare-against-zero form.
3459 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
3461 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) {
3462 if (Opc == ARMISD::VCGE)
3463 Opc = ARMISD::VCLEZ;
3464 else if (Opc == ARMISD::VCGT)
3465 Opc = ARMISD::VCLTZ;
3470 if (SingleOp.getNode()) {
3473 Result = DAG.getNode(ARMISD::VCEQZ, dl, VT, SingleOp); break;
3475 Result = DAG.getNode(ARMISD::VCGEZ, dl, VT, SingleOp); break;
3477 Result = DAG.getNode(ARMISD::VCLEZ, dl, VT, SingleOp); break;
3479 Result = DAG.getNode(ARMISD::VCGTZ, dl, VT, SingleOp); break;
3481 Result = DAG.getNode(ARMISD::VCLTZ, dl, VT, SingleOp); break;
3483 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3486 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3490 Result = DAG.getNOT(dl, Result, VT);
3495 /// isNEONModifiedImm - Check if the specified splat value corresponds to a
3496 /// valid vector constant for a NEON instruction with a "modified immediate"
3497 /// operand (e.g., VMOV). If so, return the encoded value.
3498 static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
3499 unsigned SplatBitSize, SelectionDAG &DAG,
3500 EVT &VT, bool is128Bits, NEONModImmType type) {
3501 unsigned OpCmode, Imm;
3503 // SplatBitSize is set to the smallest size that splats the vector, so a
3504 // zero vector will always have SplatBitSize == 8. However, NEON modified
3505 // immediate instructions others than VMOV do not support the 8-bit encoding
3506 // of a zero vector, and the default encoding of zero is supposed to be the
3511 switch (SplatBitSize) {
3513 if (type != VMOVModImm)
3515 // Any 1-byte value is OK. Op=0, Cmode=1110.
3516 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
3519 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
3523 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
3524 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
3525 if ((SplatBits & ~0xff) == 0) {
3526 // Value = 0x00nn: Op=x, Cmode=100x.
3531 if ((SplatBits & ~0xff00) == 0) {
3532 // Value = 0xnn00: Op=x, Cmode=101x.
3534 Imm = SplatBits >> 8;
3540 // NEON's 32-bit VMOV supports splat values where:
3541 // * only one byte is nonzero, or
3542 // * the least significant byte is 0xff and the second byte is nonzero, or
3543 // * the least significant 2 bytes are 0xff and the third is nonzero.
3544 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
3545 if ((SplatBits & ~0xff) == 0) {
3546 // Value = 0x000000nn: Op=x, Cmode=000x.
3551 if ((SplatBits & ~0xff00) == 0) {
3552 // Value = 0x0000nn00: Op=x, Cmode=001x.
3554 Imm = SplatBits >> 8;
3557 if ((SplatBits & ~0xff0000) == 0) {
3558 // Value = 0x00nn0000: Op=x, Cmode=010x.
3560 Imm = SplatBits >> 16;
3563 if ((SplatBits & ~0xff000000) == 0) {
3564 // Value = 0xnn000000: Op=x, Cmode=011x.
3566 Imm = SplatBits >> 24;
3570 // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC
3571 if (type == OtherModImm) return SDValue();
3573 if ((SplatBits & ~0xffff) == 0 &&
3574 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
3575 // Value = 0x0000nnff: Op=x, Cmode=1100.
3577 Imm = SplatBits >> 8;
3582 if ((SplatBits & ~0xffffff) == 0 &&
3583 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
3584 // Value = 0x00nnffff: Op=x, Cmode=1101.
3586 Imm = SplatBits >> 16;
3587 SplatBits |= 0xffff;
3591 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
3592 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
3593 // VMOV.I32. A (very) minor optimization would be to replicate the value
3594 // and fall through here to test for a valid 64-bit splat. But, then the
3595 // caller would also need to check and handle the change in size.
3599 if (type != VMOVModImm)
3601 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
3602 uint64_t BitMask = 0xff;
3604 unsigned ImmMask = 1;
3606 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
3607 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
3610 } else if ((SplatBits & BitMask) != 0) {
3616 // Op=1, Cmode=1110.
3619 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
3624 llvm_unreachable("unexpected size for isNEONModifiedImm");
3628 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
3629 return DAG.getTargetConstant(EncodedVal, MVT::i32);
3632 static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT,
3633 bool &ReverseVEXT, unsigned &Imm) {
3634 unsigned NumElts = VT.getVectorNumElements();
3635 ReverseVEXT = false;
3637 // Assume that the first shuffle index is not UNDEF. Fail if it is.
3643 // If this is a VEXT shuffle, the immediate value is the index of the first
3644 // element. The other shuffle indices must be the successive elements after
3646 unsigned ExpectedElt = Imm;
3647 for (unsigned i = 1; i < NumElts; ++i) {
3648 // Increment the expected index. If it wraps around, it may still be
3649 // a VEXT but the source vectors must be swapped.
3651 if (ExpectedElt == NumElts * 2) {
3656 if (M[i] < 0) continue; // ignore UNDEF indices
3657 if (ExpectedElt != static_cast<unsigned>(M[i]))
3661 // Adjust the index value if the source operands will be swapped.
3668 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
3669 /// instruction with the specified blocksize. (The order of the elements
3670 /// within each block of the vector is reversed.)
3671 static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT,
3672 unsigned BlockSize) {
3673 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
3674 "Only possible block sizes for VREV are: 16, 32, 64");
3676 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3680 unsigned NumElts = VT.getVectorNumElements();
3681 unsigned BlockElts = M[0] + 1;
3682 // If the first shuffle index is UNDEF, be optimistic.
3684 BlockElts = BlockSize / EltSz;
3686 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
3689 for (unsigned i = 0; i < NumElts; ++i) {
3690 if (M[i] < 0) continue; // ignore UNDEF indices
3691 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
3698 static bool isVTBLMask(const SmallVectorImpl<int> &M, EVT VT) {
3699 // We can handle <8 x i8> vector shuffles. If the index in the mask is out of
3700 // range, then 0 is placed into the resulting vector. So pretty much any mask
3701 // of 8 elements can work here.
3702 return VT == MVT::v8i8 && M.size() == 8;
3705 static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT,
3706 unsigned &WhichResult) {
3707 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3711 unsigned NumElts = VT.getVectorNumElements();
3712 WhichResult = (M[0] == 0 ? 0 : 1);
3713 for (unsigned i = 0; i < NumElts; i += 2) {
3714 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3715 (M[i+1] >= 0 && (unsigned) M[i+1] != i + NumElts + WhichResult))
3721 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
3722 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3723 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
3724 static bool isVTRN_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3725 unsigned &WhichResult) {
3726 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3730 unsigned NumElts = VT.getVectorNumElements();
3731 WhichResult = (M[0] == 0 ? 0 : 1);
3732 for (unsigned i = 0; i < NumElts; i += 2) {
3733 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3734 (M[i+1] >= 0 && (unsigned) M[i+1] != i + WhichResult))
3740 static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT,
3741 unsigned &WhichResult) {
3742 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3746 unsigned NumElts = VT.getVectorNumElements();
3747 WhichResult = (M[0] == 0 ? 0 : 1);
3748 for (unsigned i = 0; i != NumElts; ++i) {
3749 if (M[i] < 0) continue; // ignore UNDEF indices
3750 if ((unsigned) M[i] != 2 * i + WhichResult)
3754 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3755 if (VT.is64BitVector() && EltSz == 32)
3761 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
3762 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3763 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
3764 static bool isVUZP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3765 unsigned &WhichResult) {
3766 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3770 unsigned Half = VT.getVectorNumElements() / 2;
3771 WhichResult = (M[0] == 0 ? 0 : 1);
3772 for (unsigned j = 0; j != 2; ++j) {
3773 unsigned Idx = WhichResult;
3774 for (unsigned i = 0; i != Half; ++i) {
3775 int MIdx = M[i + j * Half];
3776 if (MIdx >= 0 && (unsigned) MIdx != Idx)
3782 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3783 if (VT.is64BitVector() && EltSz == 32)
3789 static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT,
3790 unsigned &WhichResult) {
3791 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3795 unsigned NumElts = VT.getVectorNumElements();
3796 WhichResult = (M[0] == 0 ? 0 : 1);
3797 unsigned Idx = WhichResult * NumElts / 2;
3798 for (unsigned i = 0; i != NumElts; i += 2) {
3799 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3800 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts))
3805 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3806 if (VT.is64BitVector() && EltSz == 32)
3812 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
3813 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3814 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
3815 static bool isVZIP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3816 unsigned &WhichResult) {
3817 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3821 unsigned NumElts = VT.getVectorNumElements();
3822 WhichResult = (M[0] == 0 ? 0 : 1);
3823 unsigned Idx = WhichResult * NumElts / 2;
3824 for (unsigned i = 0; i != NumElts; i += 2) {
3825 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3826 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx))
3831 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3832 if (VT.is64BitVector() && EltSz == 32)
3838 // If N is an integer constant that can be moved into a register in one
3839 // instruction, return an SDValue of such a constant (will become a MOV
3840 // instruction). Otherwise return null.
3841 static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG,
3842 const ARMSubtarget *ST, DebugLoc dl) {
3844 if (!isa<ConstantSDNode>(N))
3846 Val = cast<ConstantSDNode>(N)->getZExtValue();
3848 if (ST->isThumb1Only()) {
3849 if (Val <= 255 || ~Val <= 255)
3850 return DAG.getConstant(Val, MVT::i32);
3852 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1)
3853 return DAG.getConstant(Val, MVT::i32);
3858 // If this is a case we can't handle, return null and let the default
3859 // expansion code take care of it.
3860 SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
3861 const ARMSubtarget *ST) const {
3862 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
3863 DebugLoc dl = Op.getDebugLoc();
3864 EVT VT = Op.getValueType();
3866 APInt SplatBits, SplatUndef;
3867 unsigned SplatBitSize;
3869 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
3870 if (SplatBitSize <= 64) {
3871 // Check if an immediate VMOV works.
3873 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
3874 SplatUndef.getZExtValue(), SplatBitSize,
3875 DAG, VmovVT, VT.is128BitVector(),
3877 if (Val.getNode()) {
3878 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
3879 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3882 // Try an immediate VMVN.
3883 uint64_t NegatedImm = (SplatBits.getZExtValue() ^
3884 ((1LL << SplatBitSize) - 1));
3885 Val = isNEONModifiedImm(NegatedImm,
3886 SplatUndef.getZExtValue(), SplatBitSize,
3887 DAG, VmovVT, VT.is128BitVector(),
3889 if (Val.getNode()) {
3890 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
3891 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3896 // Scan through the operands to see if only one value is used.
3897 unsigned NumElts = VT.getVectorNumElements();
3898 bool isOnlyLowElement = true;
3899 bool usesOnlyOneValue = true;
3900 bool isConstant = true;
3902 for (unsigned i = 0; i < NumElts; ++i) {
3903 SDValue V = Op.getOperand(i);
3904 if (V.getOpcode() == ISD::UNDEF)
3907 isOnlyLowElement = false;
3908 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
3911 if (!Value.getNode())
3913 else if (V != Value)
3914 usesOnlyOneValue = false;
3917 if (!Value.getNode())
3918 return DAG.getUNDEF(VT);
3920 if (isOnlyLowElement)
3921 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
3923 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3925 // Use VDUP for non-constant splats. For f32 constant splats, reduce to
3926 // i32 and try again.
3927 if (usesOnlyOneValue && EltSize <= 32) {
3929 return DAG.getNode(ARMISD::VDUP, dl, VT, Value);
3930 if (VT.getVectorElementType().isFloatingPoint()) {
3931 SmallVector<SDValue, 8> Ops;
3932 for (unsigned i = 0; i < NumElts; ++i)
3933 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32,
3935 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
3936 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], NumElts);
3937 Val = LowerBUILD_VECTOR(Val, DAG, ST);
3939 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
3941 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
3943 return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
3946 // If all elements are constants and the case above didn't get hit, fall back
3947 // to the default expansion, which will generate a load from the constant
3952 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
3954 SDValue shuffle = ReconstructShuffle(Op, DAG);
3955 if (shuffle != SDValue())
3959 // Vectors with 32- or 64-bit elements can be built by directly assigning
3960 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
3961 // will be legalized.
3962 if (EltSize >= 32) {
3963 // Do the expansion with floating-point types, since that is what the VFP
3964 // registers are defined to use, and since i64 is not legal.
3965 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3966 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3967 SmallVector<SDValue, 8> Ops;
3968 for (unsigned i = 0; i < NumElts; ++i)
3969 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i)));
3970 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
3971 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
3977 // Gather data to see if the operation can be modelled as a
3978 // shuffle in combination with VEXTs.
3979 SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
3980 SelectionDAG &DAG) const {
3981 DebugLoc dl = Op.getDebugLoc();
3982 EVT VT = Op.getValueType();
3983 unsigned NumElts = VT.getVectorNumElements();
3985 SmallVector<SDValue, 2> SourceVecs;
3986 SmallVector<unsigned, 2> MinElts;
3987 SmallVector<unsigned, 2> MaxElts;
3989 for (unsigned i = 0; i < NumElts; ++i) {
3990 SDValue V = Op.getOperand(i);
3991 if (V.getOpcode() == ISD::UNDEF)
3993 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
3994 // A shuffle can only come from building a vector from various
3995 // elements of other vectors.
3999 // Record this extraction against the appropriate vector if possible...
4000 SDValue SourceVec = V.getOperand(0);
4001 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
4002 bool FoundSource = false;
4003 for (unsigned j = 0; j < SourceVecs.size(); ++j) {
4004 if (SourceVecs[j] == SourceVec) {
4005 if (MinElts[j] > EltNo)
4007 if (MaxElts[j] < EltNo)
4014 // Or record a new source if not...
4016 SourceVecs.push_back(SourceVec);
4017 MinElts.push_back(EltNo);
4018 MaxElts.push_back(EltNo);
4022 // Currently only do something sane when at most two source vectors
4024 if (SourceVecs.size() > 2)
4027 SDValue ShuffleSrcs[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT) };
4028 int VEXTOffsets[2] = {0, 0};
4030 // This loop extracts the usage patterns of the source vectors
4031 // and prepares appropriate SDValues for a shuffle if possible.
4032 for (unsigned i = 0; i < SourceVecs.size(); ++i) {
4033 if (SourceVecs[i].getValueType() == VT) {
4034 // No VEXT necessary
4035 ShuffleSrcs[i] = SourceVecs[i];
4038 } else if (SourceVecs[i].getValueType().getVectorNumElements() < NumElts) {
4039 // It probably isn't worth padding out a smaller vector just to
4040 // break it down again in a shuffle.
4044 // Since only 64-bit and 128-bit vectors are legal on ARM and
4045 // we've eliminated the other cases...
4046 assert(SourceVecs[i].getValueType().getVectorNumElements() == 2*NumElts &&
4047 "unexpected vector sizes in ReconstructShuffle");
4049 if (MaxElts[i] - MinElts[i] >= NumElts) {
4050 // Span too large for a VEXT to cope
4054 if (MinElts[i] >= NumElts) {
4055 // The extraction can just take the second half
4056 VEXTOffsets[i] = NumElts;
4057 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4059 DAG.getIntPtrConstant(NumElts));
4060 } else if (MaxElts[i] < NumElts) {
4061 // The extraction can just take the first half
4063 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4065 DAG.getIntPtrConstant(0));
4067 // An actual VEXT is needed
4068 VEXTOffsets[i] = MinElts[i];
4069 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4071 DAG.getIntPtrConstant(0));
4072 SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4074 DAG.getIntPtrConstant(NumElts));
4075 ShuffleSrcs[i] = DAG.getNode(ARMISD::VEXT, dl, VT, VEXTSrc1, VEXTSrc2,
4076 DAG.getConstant(VEXTOffsets[i], MVT::i32));
4080 SmallVector<int, 8> Mask;
4082 for (unsigned i = 0; i < NumElts; ++i) {
4083 SDValue Entry = Op.getOperand(i);
4084 if (Entry.getOpcode() == ISD::UNDEF) {
4089 SDValue ExtractVec = Entry.getOperand(0);
4090 int ExtractElt = cast<ConstantSDNode>(Op.getOperand(i)
4091 .getOperand(1))->getSExtValue();
4092 if (ExtractVec == SourceVecs[0]) {
4093 Mask.push_back(ExtractElt - VEXTOffsets[0]);
4095 Mask.push_back(ExtractElt + NumElts - VEXTOffsets[1]);
4099 // Final check before we try to produce nonsense...
4100 if (isShuffleMaskLegal(Mask, VT))
4101 return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1],
4107 /// isShuffleMaskLegal - Targets can use this to indicate that they only
4108 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
4109 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
4110 /// are assumed to be legal.
4112 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
4114 if (VT.getVectorNumElements() == 4 &&
4115 (VT.is128BitVector() || VT.is64BitVector())) {
4116 unsigned PFIndexes[4];
4117 for (unsigned i = 0; i != 4; ++i) {
4121 PFIndexes[i] = M[i];
4124 // Compute the index in the perfect shuffle table.
4125 unsigned PFTableIndex =
4126 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
4127 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4128 unsigned Cost = (PFEntry >> 30);
4135 unsigned Imm, WhichResult;
4137 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4138 return (EltSize >= 32 ||
4139 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
4140 isVREVMask(M, VT, 64) ||
4141 isVREVMask(M, VT, 32) ||
4142 isVREVMask(M, VT, 16) ||
4143 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
4144 isVTBLMask(M, VT) ||
4145 isVTRNMask(M, VT, WhichResult) ||
4146 isVUZPMask(M, VT, WhichResult) ||
4147 isVZIPMask(M, VT, WhichResult) ||
4148 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
4149 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
4150 isVZIP_v_undef_Mask(M, VT, WhichResult));
4153 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
4154 /// the specified operations to build the shuffle.
4155 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
4156 SDValue RHS, SelectionDAG &DAG,
4158 unsigned OpNum = (PFEntry >> 26) & 0x0F;
4159 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
4160 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
4163 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
4172 OP_VUZPL, // VUZP, left result
4173 OP_VUZPR, // VUZP, right result
4174 OP_VZIPL, // VZIP, left result
4175 OP_VZIPR, // VZIP, right result
4176 OP_VTRNL, // VTRN, left result
4177 OP_VTRNR // VTRN, right result
4180 if (OpNum == OP_COPY) {
4181 if (LHSID == (1*9+2)*9+3) return LHS;
4182 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
4186 SDValue OpLHS, OpRHS;
4187 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
4188 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
4189 EVT VT = OpLHS.getValueType();
4192 default: llvm_unreachable("Unknown shuffle opcode!");
4194 // VREV divides the vector in half and swaps within the half.
4195 if (VT.getVectorElementType() == MVT::i32 ||
4196 VT.getVectorElementType() == MVT::f32)
4197 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
4198 // vrev <4 x i16> -> VREV32
4199 if (VT.getVectorElementType() == MVT::i16)
4200 return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS);
4201 // vrev <4 x i8> -> VREV16
4202 assert(VT.getVectorElementType() == MVT::i8);
4203 return DAG.getNode(ARMISD::VREV16, dl, VT, OpLHS);
4208 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
4209 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
4213 return DAG.getNode(ARMISD::VEXT, dl, VT,
4215 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
4218 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4219 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
4222 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4223 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
4226 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4227 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
4231 static SDValue LowerVECTOR_SHUFFLEv8i8(SDValue Op,
4232 SmallVectorImpl<int> &ShuffleMask,
4233 SelectionDAG &DAG) {
4234 // Check to see if we can use the VTBL instruction.
4235 SDValue V1 = Op.getOperand(0);
4236 SDValue V2 = Op.getOperand(1);
4237 DebugLoc DL = Op.getDebugLoc();
4239 SmallVector<SDValue, 8> VTBLMask;
4240 for (SmallVectorImpl<int>::iterator
4241 I = ShuffleMask.begin(), E = ShuffleMask.end(); I != E; ++I)
4242 VTBLMask.push_back(DAG.getConstant(*I, MVT::i32));
4244 if (V2.getNode()->getOpcode() == ISD::UNDEF)
4245 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1,
4246 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
4249 return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2,
4250 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
4254 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
4255 SDValue V1 = Op.getOperand(0);
4256 SDValue V2 = Op.getOperand(1);
4257 DebugLoc dl = Op.getDebugLoc();
4258 EVT VT = Op.getValueType();
4259 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
4260 SmallVector<int, 8> ShuffleMask;
4262 // Convert shuffles that are directly supported on NEON to target-specific
4263 // DAG nodes, instead of keeping them as shuffles and matching them again
4264 // during code selection. This is more efficient and avoids the possibility
4265 // of inconsistencies between legalization and selection.
4266 // FIXME: floating-point vectors should be canonicalized to integer vectors
4267 // of the same time so that they get CSEd properly.
4268 SVN->getMask(ShuffleMask);
4270 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4271 if (EltSize <= 32) {
4272 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
4273 int Lane = SVN->getSplatIndex();
4274 // If this is undef splat, generate it via "just" vdup, if possible.
4275 if (Lane == -1) Lane = 0;
4277 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4278 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
4280 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
4281 DAG.getConstant(Lane, MVT::i32));
4286 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
4289 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
4290 DAG.getConstant(Imm, MVT::i32));
4293 if (isVREVMask(ShuffleMask, VT, 64))
4294 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
4295 if (isVREVMask(ShuffleMask, VT, 32))
4296 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
4297 if (isVREVMask(ShuffleMask, VT, 16))
4298 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
4300 // Check for Neon shuffles that modify both input vectors in place.
4301 // If both results are used, i.e., if there are two shuffles with the same
4302 // source operands and with masks corresponding to both results of one of
4303 // these operations, DAG memoization will ensure that a single node is
4304 // used for both shuffles.
4305 unsigned WhichResult;
4306 if (isVTRNMask(ShuffleMask, VT, WhichResult))
4307 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4308 V1, V2).getValue(WhichResult);
4309 if (isVUZPMask(ShuffleMask, VT, WhichResult))
4310 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4311 V1, V2).getValue(WhichResult);
4312 if (isVZIPMask(ShuffleMask, VT, WhichResult))
4313 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4314 V1, V2).getValue(WhichResult);
4316 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
4317 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4318 V1, V1).getValue(WhichResult);
4319 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
4320 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4321 V1, V1).getValue(WhichResult);
4322 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
4323 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4324 V1, V1).getValue(WhichResult);
4327 // If the shuffle is not directly supported and it has 4 elements, use
4328 // the PerfectShuffle-generated table to synthesize it from other shuffles.
4329 unsigned NumElts = VT.getVectorNumElements();
4331 unsigned PFIndexes[4];
4332 for (unsigned i = 0; i != 4; ++i) {
4333 if (ShuffleMask[i] < 0)
4336 PFIndexes[i] = ShuffleMask[i];
4339 // Compute the index in the perfect shuffle table.
4340 unsigned PFTableIndex =
4341 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
4342 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4343 unsigned Cost = (PFEntry >> 30);
4346 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
4349 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
4350 if (EltSize >= 32) {
4351 // Do the expansion with floating-point types, since that is what the VFP
4352 // registers are defined to use, and since i64 is not legal.
4353 EVT EltVT = EVT::getFloatingPointVT(EltSize);
4354 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
4355 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1);
4356 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2);
4357 SmallVector<SDValue, 8> Ops;
4358 for (unsigned i = 0; i < NumElts; ++i) {
4359 if (ShuffleMask[i] < 0)
4360 Ops.push_back(DAG.getUNDEF(EltVT));
4362 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
4363 ShuffleMask[i] < (int)NumElts ? V1 : V2,
4364 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
4367 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
4368 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
4371 if (VT == MVT::v8i8) {
4372 SDValue NewOp = LowerVECTOR_SHUFFLEv8i8(Op, ShuffleMask, DAG);
4373 if (NewOp.getNode())
4380 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4381 // EXTRACT_VECTOR_ELT is legal only for immediate indexes.
4382 SDValue Lane = Op.getOperand(1);
4383 if (!isa<ConstantSDNode>(Lane))
4386 SDValue Vec = Op.getOperand(0);
4387 if (Op.getValueType() == MVT::i32 &&
4388 Vec.getValueType().getVectorElementType().getSizeInBits() < 32) {
4389 DebugLoc dl = Op.getDebugLoc();
4390 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
4396 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
4397 // The only time a CONCAT_VECTORS operation can have legal types is when
4398 // two 64-bit vectors are concatenated to a 128-bit vector.
4399 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
4400 "unexpected CONCAT_VECTORS");
4401 DebugLoc dl = Op.getDebugLoc();
4402 SDValue Val = DAG.getUNDEF(MVT::v2f64);
4403 SDValue Op0 = Op.getOperand(0);
4404 SDValue Op1 = Op.getOperand(1);
4405 if (Op0.getOpcode() != ISD::UNDEF)
4406 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
4407 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0),
4408 DAG.getIntPtrConstant(0));
4409 if (Op1.getOpcode() != ISD::UNDEF)
4410 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
4411 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1),
4412 DAG.getIntPtrConstant(1));
4413 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val);
4416 /// isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each
4417 /// element has been zero/sign-extended, depending on the isSigned parameter,
4418 /// from an integer type half its size.
4419 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
4421 // A v2i64 BUILD_VECTOR will have been legalized to a BITCAST from v4i32.
4422 EVT VT = N->getValueType(0);
4423 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) {
4424 SDNode *BVN = N->getOperand(0).getNode();
4425 if (BVN->getValueType(0) != MVT::v4i32 ||
4426 BVN->getOpcode() != ISD::BUILD_VECTOR)
4428 unsigned LoElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
4429 unsigned HiElt = 1 - LoElt;
4430 ConstantSDNode *Lo0 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt));
4431 ConstantSDNode *Hi0 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt));
4432 ConstantSDNode *Lo1 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt+2));
4433 ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2));
4434 if (!Lo0 || !Hi0 || !Lo1 || !Hi1)
4437 if (Hi0->getSExtValue() == Lo0->getSExtValue() >> 32 &&
4438 Hi1->getSExtValue() == Lo1->getSExtValue() >> 32)
4441 if (Hi0->isNullValue() && Hi1->isNullValue())
4447 if (N->getOpcode() != ISD::BUILD_VECTOR)
4450 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
4451 SDNode *Elt = N->getOperand(i).getNode();
4452 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
4453 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4454 unsigned HalfSize = EltSize / 2;
4456 int64_t SExtVal = C->getSExtValue();
4457 if ((SExtVal >> HalfSize) != (SExtVal >> EltSize))
4460 if ((C->getZExtValue() >> HalfSize) != 0)
4471 /// isSignExtended - Check if a node is a vector value that is sign-extended
4472 /// or a constant BUILD_VECTOR with sign-extended elements.
4473 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
4474 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N))
4476 if (isExtendedBUILD_VECTOR(N, DAG, true))
4481 /// isZeroExtended - Check if a node is a vector value that is zero-extended
4482 /// or a constant BUILD_VECTOR with zero-extended elements.
4483 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
4484 if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N))
4486 if (isExtendedBUILD_VECTOR(N, DAG, false))
4491 /// SkipExtension - For a node that is a SIGN_EXTEND, ZERO_EXTEND, extending
4492 /// load, or BUILD_VECTOR with extended elements, return the unextended value.
4493 static SDValue SkipExtension(SDNode *N, SelectionDAG &DAG) {
4494 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
4495 return N->getOperand(0);
4496 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
4497 return DAG.getLoad(LD->getMemoryVT(), N->getDebugLoc(), LD->getChain(),
4498 LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(),
4499 LD->isNonTemporal(), LD->getAlignment());
4500 // Otherwise, the value must be a BUILD_VECTOR. For v2i64, it will
4501 // have been legalized as a BITCAST from v4i32.
4502 if (N->getOpcode() == ISD::BITCAST) {
4503 SDNode *BVN = N->getOperand(0).getNode();
4504 assert(BVN->getOpcode() == ISD::BUILD_VECTOR &&
4505 BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR");
4506 unsigned LowElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
4507 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), MVT::v2i32,
4508 BVN->getOperand(LowElt), BVN->getOperand(LowElt+2));
4510 // Construct a new BUILD_VECTOR with elements truncated to half the size.
4511 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
4512 EVT VT = N->getValueType(0);
4513 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
4514 unsigned NumElts = VT.getVectorNumElements();
4515 MVT TruncVT = MVT::getIntegerVT(EltSize);
4516 SmallVector<SDValue, 8> Ops;
4517 for (unsigned i = 0; i != NumElts; ++i) {
4518 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
4519 const APInt &CInt = C->getAPIntValue();
4520 Ops.push_back(DAG.getConstant(CInt.trunc(EltSize), TruncVT));
4522 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
4523 MVT::getVectorVT(TruncVT, NumElts), Ops.data(), NumElts);
4526 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
4527 unsigned Opcode = N->getOpcode();
4528 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
4529 SDNode *N0 = N->getOperand(0).getNode();
4530 SDNode *N1 = N->getOperand(1).getNode();
4531 return N0->hasOneUse() && N1->hasOneUse() &&
4532 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
4537 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
4538 unsigned Opcode = N->getOpcode();
4539 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
4540 SDNode *N0 = N->getOperand(0).getNode();
4541 SDNode *N1 = N->getOperand(1).getNode();
4542 return N0->hasOneUse() && N1->hasOneUse() &&
4543 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
4548 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
4549 // Multiplications are only custom-lowered for 128-bit vectors so that
4550 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
4551 EVT VT = Op.getValueType();
4552 assert(VT.is128BitVector() && "unexpected type for custom-lowering ISD::MUL");
4553 SDNode *N0 = Op.getOperand(0).getNode();
4554 SDNode *N1 = Op.getOperand(1).getNode();
4555 unsigned NewOpc = 0;
4557 bool isN0SExt = isSignExtended(N0, DAG);
4558 bool isN1SExt = isSignExtended(N1, DAG);
4559 if (isN0SExt && isN1SExt)
4560 NewOpc = ARMISD::VMULLs;
4562 bool isN0ZExt = isZeroExtended(N0, DAG);
4563 bool isN1ZExt = isZeroExtended(N1, DAG);
4564 if (isN0ZExt && isN1ZExt)
4565 NewOpc = ARMISD::VMULLu;
4566 else if (isN1SExt || isN1ZExt) {
4567 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
4568 // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
4569 if (isN1SExt && isAddSubSExt(N0, DAG)) {
4570 NewOpc = ARMISD::VMULLs;
4572 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
4573 NewOpc = ARMISD::VMULLu;
4575 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
4577 NewOpc = ARMISD::VMULLu;
4583 if (VT == MVT::v2i64)
4584 // Fall through to expand this. It is not legal.
4587 // Other vector multiplications are legal.
4592 // Legalize to a VMULL instruction.
4593 DebugLoc DL = Op.getDebugLoc();
4595 SDValue Op1 = SkipExtension(N1, DAG);
4597 Op0 = SkipExtension(N0, DAG);
4598 assert(Op0.getValueType().is64BitVector() &&
4599 Op1.getValueType().is64BitVector() &&
4600 "unexpected types for extended operands to VMULL");
4601 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
4604 // Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during
4605 // isel lowering to take advantage of no-stall back to back vmul + vmla.
4612 SDValue N00 = SkipExtension(N0->getOperand(0).getNode(), DAG);
4613 SDValue N01 = SkipExtension(N0->getOperand(1).getNode(), DAG);
4614 EVT Op1VT = Op1.getValueType();
4615 return DAG.getNode(N0->getOpcode(), DL, VT,
4616 DAG.getNode(NewOpc, DL, VT,
4617 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
4618 DAG.getNode(NewOpc, DL, VT,
4619 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
4623 LowerSDIV_v4i8(SDValue X, SDValue Y, DebugLoc dl, SelectionDAG &DAG) {
4625 // float4 xf = vcvt_f32_s32(vmovl_s16(a.lo));
4626 // float4 yf = vcvt_f32_s32(vmovl_s16(b.lo));
4627 X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X);
4628 Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y);
4629 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X);
4630 Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y);
4631 // Get reciprocal estimate.
4632 // float4 recip = vrecpeq_f32(yf);
4633 Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4634 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), Y);
4635 // Because char has a smaller range than uchar, we can actually get away
4636 // without any newton steps. This requires that we use a weird bias
4637 // of 0xb000, however (again, this has been exhaustively tested).
4638 // float4 result = as_float4(as_int4(xf*recip) + 0xb000);
4639 X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y);
4640 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X);
4641 Y = DAG.getConstant(0xb000, MVT::i32);
4642 Y = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Y, Y, Y, Y);
4643 X = DAG.getNode(ISD::ADD, dl, MVT::v4i32, X, Y);
4644 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X);
4645 // Convert back to short.
4646 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X);
4647 X = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, X);
4652 LowerSDIV_v4i16(SDValue N0, SDValue N1, DebugLoc dl, SelectionDAG &DAG) {
4654 // Convert to float.
4655 // float4 yf = vcvt_f32_s32(vmovl_s16(y));
4656 // float4 xf = vcvt_f32_s32(vmovl_s16(x));
4657 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0);
4658 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1);
4659 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
4660 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
4662 // Use reciprocal estimate and one refinement step.
4663 // float4 recip = vrecpeq_f32(yf);
4664 // recip *= vrecpsq_f32(yf, recip);
4665 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4666 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1);
4667 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4668 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
4670 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
4671 // Because short has a smaller range than ushort, we can actually get away
4672 // with only a single newton step. This requires that we use a weird bias
4673 // of 89, however (again, this has been exhaustively tested).
4674 // float4 result = as_float4(as_int4(xf*recip) + 0x89);
4675 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
4676 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
4677 N1 = DAG.getConstant(0x89, MVT::i32);
4678 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
4679 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
4680 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
4681 // Convert back to integer and return.
4682 // return vmovn_s32(vcvt_s32_f32(result));
4683 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
4684 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
4688 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
4689 EVT VT = Op.getValueType();
4690 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
4691 "unexpected type for custom-lowering ISD::SDIV");
4693 DebugLoc dl = Op.getDebugLoc();
4694 SDValue N0 = Op.getOperand(0);
4695 SDValue N1 = Op.getOperand(1);
4698 if (VT == MVT::v8i8) {
4699 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0);
4700 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1);
4702 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4703 DAG.getIntPtrConstant(4));
4704 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4705 DAG.getIntPtrConstant(4));
4706 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4707 DAG.getIntPtrConstant(0));
4708 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4709 DAG.getIntPtrConstant(0));
4711 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16
4712 N2 = LowerSDIV_v4i8(N2, N3, dl, DAG); // v4i16
4714 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
4715 N0 = LowerCONCAT_VECTORS(N0, DAG);
4717 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0);
4720 return LowerSDIV_v4i16(N0, N1, dl, DAG);
4723 static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG) {
4724 EVT VT = Op.getValueType();
4725 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
4726 "unexpected type for custom-lowering ISD::UDIV");
4728 DebugLoc dl = Op.getDebugLoc();
4729 SDValue N0 = Op.getOperand(0);
4730 SDValue N1 = Op.getOperand(1);
4733 if (VT == MVT::v8i8) {
4734 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0);
4735 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1);
4737 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4738 DAG.getIntPtrConstant(4));
4739 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4740 DAG.getIntPtrConstant(4));
4741 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4742 DAG.getIntPtrConstant(0));
4743 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4744 DAG.getIntPtrConstant(0));
4746 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16
4747 N2 = LowerSDIV_v4i16(N2, N3, dl, DAG); // v4i16
4749 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
4750 N0 = LowerCONCAT_VECTORS(N0, DAG);
4752 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8,
4753 DAG.getConstant(Intrinsic::arm_neon_vqmovnsu, MVT::i32),
4758 // v4i16 sdiv ... Convert to float.
4759 // float4 yf = vcvt_f32_s32(vmovl_u16(y));
4760 // float4 xf = vcvt_f32_s32(vmovl_u16(x));
4761 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0);
4762 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1);
4763 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
4764 SDValue BN1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
4766 // Use reciprocal estimate and two refinement steps.
4767 // float4 recip = vrecpeq_f32(yf);
4768 // recip *= vrecpsq_f32(yf, recip);
4769 // recip *= vrecpsq_f32(yf, recip);
4770 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4771 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), BN1);
4772 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4773 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
4775 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
4776 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4777 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
4779 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
4780 // Simply multiplying by the reciprocal estimate can leave us a few ulps
4781 // too low, so we add 2 ulps (exhaustive testing shows that this is enough,
4782 // and that it will never cause us to return an answer too large).
4783 // float4 result = as_float4(as_int4(xf*recip) + 2);
4784 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
4785 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
4786 N1 = DAG.getConstant(2, MVT::i32);
4787 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
4788 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
4789 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
4790 // Convert back to integer and return.
4791 // return vmovn_u32(vcvt_s32_f32(result));
4792 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
4793 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
4797 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
4798 switch (Op.getOpcode()) {
4799 default: llvm_unreachable("Don't know how to custom lower this!");
4800 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
4801 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
4802 case ISD::GlobalAddress:
4803 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
4804 LowerGlobalAddressELF(Op, DAG);
4805 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
4806 case ISD::SELECT: return LowerSELECT(Op, DAG);
4807 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
4808 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
4809 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
4810 case ISD::VASTART: return LowerVASTART(Op, DAG);
4811 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget);
4812 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget);
4813 case ISD::SINT_TO_FP:
4814 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
4815 case ISD::FP_TO_SINT:
4816 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
4817 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
4818 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
4819 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
4820 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
4821 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
4822 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
4823 case ISD::EH_SJLJ_DISPATCHSETUP: return LowerEH_SJLJ_DISPATCHSETUP(Op, DAG);
4824 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
4826 case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG);
4829 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
4830 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
4831 case ISD::SRL_PARTS:
4832 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
4833 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
4834 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
4835 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
4836 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
4837 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
4838 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
4839 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
4840 case ISD::MUL: return LowerMUL(Op, DAG);
4841 case ISD::SDIV: return LowerSDIV(Op, DAG);
4842 case ISD::UDIV: return LowerUDIV(Op, DAG);
4847 /// ReplaceNodeResults - Replace the results of node with an illegal result
4848 /// type with new values built out of custom code.
4849 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
4850 SmallVectorImpl<SDValue>&Results,
4851 SelectionDAG &DAG) const {
4853 switch (N->getOpcode()) {
4855 llvm_unreachable("Don't know how to custom expand this!");
4858 Res = ExpandBITCAST(N, DAG);
4862 Res = Expand64BitShift(N, DAG, Subtarget);
4866 Results.push_back(Res);
4869 //===----------------------------------------------------------------------===//
4870 // ARM Scheduler Hooks
4871 //===----------------------------------------------------------------------===//
4874 ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
4875 MachineBasicBlock *BB,
4876 unsigned Size) const {
4877 unsigned dest = MI->getOperand(0).getReg();
4878 unsigned ptr = MI->getOperand(1).getReg();
4879 unsigned oldval = MI->getOperand(2).getReg();
4880 unsigned newval = MI->getOperand(3).getReg();
4881 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4882 DebugLoc dl = MI->getDebugLoc();
4883 bool isThumb2 = Subtarget->isThumb2();
4885 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
4887 MRI.createVirtualRegister(isThumb2 ? ARM::rGPRRegisterClass
4888 : ARM::GPRRegisterClass);
4891 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass);
4892 MRI.constrainRegClass(oldval, ARM::rGPRRegisterClass);
4893 MRI.constrainRegClass(newval, ARM::rGPRRegisterClass);
4896 unsigned ldrOpc, strOpc;
4898 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
4900 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
4901 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
4904 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
4905 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
4908 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
4909 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
4913 MachineFunction *MF = BB->getParent();
4914 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4915 MachineFunction::iterator It = BB;
4916 ++It; // insert the new blocks after the current block
4918 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
4919 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
4920 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
4921 MF->insert(It, loop1MBB);
4922 MF->insert(It, loop2MBB);
4923 MF->insert(It, exitMBB);
4925 // Transfer the remainder of BB and its successor edges to exitMBB.
4926 exitMBB->splice(exitMBB->begin(), BB,
4927 llvm::next(MachineBasicBlock::iterator(MI)),
4929 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4933 // fallthrough --> loop1MBB
4934 BB->addSuccessor(loop1MBB);
4937 // ldrex dest, [ptr]
4941 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
4942 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
4943 .addReg(dest).addReg(oldval));
4944 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4945 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
4946 BB->addSuccessor(loop2MBB);
4947 BB->addSuccessor(exitMBB);
4950 // strex scratch, newval, [ptr]
4954 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval)
4956 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4957 .addReg(scratch).addImm(0));
4958 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4959 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
4960 BB->addSuccessor(loop1MBB);
4961 BB->addSuccessor(exitMBB);
4967 MI->eraseFromParent(); // The instruction is gone now.
4973 ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
4974 unsigned Size, unsigned BinOpcode) const {
4975 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4976 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4978 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4979 MachineFunction *MF = BB->getParent();
4980 MachineFunction::iterator It = BB;
4983 unsigned dest = MI->getOperand(0).getReg();
4984 unsigned ptr = MI->getOperand(1).getReg();
4985 unsigned incr = MI->getOperand(2).getReg();
4986 DebugLoc dl = MI->getDebugLoc();
4987 bool isThumb2 = Subtarget->isThumb2();
4989 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
4991 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass);
4992 MRI.constrainRegClass(ptr, ARM::rGPRRegisterClass);
4995 unsigned ldrOpc, strOpc;
4997 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
4999 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
5000 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
5003 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
5004 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
5007 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
5008 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
5012 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5013 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5014 MF->insert(It, loopMBB);
5015 MF->insert(It, exitMBB);
5017 // Transfer the remainder of BB and its successor edges to exitMBB.
5018 exitMBB->splice(exitMBB->begin(), BB,
5019 llvm::next(MachineBasicBlock::iterator(MI)),
5021 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5023 TargetRegisterClass *TRC =
5024 isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
5025 unsigned scratch = MRI.createVirtualRegister(TRC);
5026 unsigned scratch2 = (!BinOpcode) ? incr : MRI.createVirtualRegister(TRC);
5030 // fallthrough --> loopMBB
5031 BB->addSuccessor(loopMBB);
5035 // <binop> scratch2, dest, incr
5036 // strex scratch, scratch2, ptr
5039 // fallthrough --> exitMBB
5041 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
5043 // operand order needs to go the other way for NAND
5044 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr)
5045 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
5046 addReg(incr).addReg(dest)).addReg(0);
5048 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
5049 addReg(dest).addReg(incr)).addReg(0);
5052 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2)
5054 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5055 .addReg(scratch).addImm(0));
5056 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5057 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5059 BB->addSuccessor(loopMBB);
5060 BB->addSuccessor(exitMBB);
5066 MI->eraseFromParent(); // The instruction is gone now.
5072 ARMTargetLowering::EmitAtomicBinaryMinMax(MachineInstr *MI,
5073 MachineBasicBlock *BB,
5076 ARMCC::CondCodes Cond) const {
5077 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5079 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5080 MachineFunction *MF = BB->getParent();
5081 MachineFunction::iterator It = BB;
5084 unsigned dest = MI->getOperand(0).getReg();
5085 unsigned ptr = MI->getOperand(1).getReg();
5086 unsigned incr = MI->getOperand(2).getReg();
5087 unsigned oldval = dest;
5088 DebugLoc dl = MI->getDebugLoc();
5089 bool isThumb2 = Subtarget->isThumb2();
5091 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
5093 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass);
5094 MRI.constrainRegClass(ptr, ARM::rGPRRegisterClass);
5097 unsigned ldrOpc, strOpc, extendOpc;
5099 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
5101 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
5102 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
5103 extendOpc = isThumb2 ? ARM::t2SXTBr : ARM::SXTBr;
5106 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
5107 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
5108 extendOpc = isThumb2 ? ARM::t2SXTHr : ARM::SXTHr;
5111 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
5112 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
5117 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5118 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5119 MF->insert(It, loopMBB);
5120 MF->insert(It, exitMBB);
5122 // Transfer the remainder of BB and its successor edges to exitMBB.
5123 exitMBB->splice(exitMBB->begin(), BB,
5124 llvm::next(MachineBasicBlock::iterator(MI)),
5126 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5128 TargetRegisterClass *TRC =
5129 isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
5130 unsigned scratch = MRI.createVirtualRegister(TRC);
5131 unsigned scratch2 = MRI.createVirtualRegister(TRC);
5135 // fallthrough --> loopMBB
5136 BB->addSuccessor(loopMBB);
5140 // (sign extend dest, if required)
5142 // cmov.cond scratch2, dest, incr
5143 // strex scratch, scratch2, ptr
5146 // fallthrough --> exitMBB
5148 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
5150 // Sign extend the value, if necessary.
5151 if (signExtend && extendOpc) {
5152 oldval = MRI.createVirtualRegister(ARM::GPRRegisterClass);
5153 AddDefaultPred(BuildMI(BB, dl, TII->get(extendOpc), oldval).addReg(dest));
5156 // Build compare and cmov instructions.
5157 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
5158 .addReg(oldval).addReg(incr));
5159 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr), scratch2)
5160 .addReg(oldval).addReg(incr).addImm(Cond).addReg(ARM::CPSR);
5162 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2)
5164 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5165 .addReg(scratch).addImm(0));
5166 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5167 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5169 BB->addSuccessor(loopMBB);
5170 BB->addSuccessor(exitMBB);
5176 MI->eraseFromParent(); // The instruction is gone now.
5182 MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
5183 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
5184 E = MBB->succ_end(); I != E; ++I)
5187 llvm_unreachable("Expecting a BB with two successors!");
5190 // FIXME: This opcode table should obviously be expressed in the target
5191 // description. We probably just need a "machine opcode" value in the pseudo
5192 // instruction. But the ideal solution maybe to simply remove the "S" version
5193 // of the opcode altogether.
5194 struct AddSubFlagsOpcodePair {
5196 unsigned MachineOpc;
5199 static AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
5200 {ARM::ADCSri, ARM::ADCri},
5201 {ARM::ADCSrr, ARM::ADCrr},
5202 {ARM::ADCSrs, ARM::ADCrs},
5203 {ARM::SBCSri, ARM::SBCri},
5204 {ARM::SBCSrr, ARM::SBCrr},
5205 {ARM::SBCSrs, ARM::SBCrs},
5206 {ARM::RSBSri, ARM::RSBri},
5207 {ARM::RSBSrr, ARM::RSBrr},
5208 {ARM::RSBSrs, ARM::RSBrs},
5209 {ARM::RSCSri, ARM::RSCri},
5210 {ARM::RSCSrs, ARM::RSCrs},
5211 {ARM::t2ADCSri, ARM::t2ADCri},
5212 {ARM::t2ADCSrr, ARM::t2ADCrr},
5213 {ARM::t2ADCSrs, ARM::t2ADCrs},
5214 {ARM::t2SBCSri, ARM::t2SBCri},
5215 {ARM::t2SBCSrr, ARM::t2SBCrr},
5216 {ARM::t2SBCSrs, ARM::t2SBCrs},
5217 {ARM::t2RSBSri, ARM::t2RSBri},
5218 {ARM::t2RSBSrs, ARM::t2RSBrs},
5221 // Convert and Add or Subtract with Carry and Flags to a generic opcode with
5222 // CPSR<def> operand. e.g. ADCS (...) -> ADC (... CPSR<def>).
5224 // FIXME: Somewhere we should assert that CPSR<def> is in the correct
5225 // position to be recognized by the target descrition as the 'S' bit.
5226 bool ARMTargetLowering::RemapAddSubWithFlags(MachineInstr *MI,
5227 MachineBasicBlock *BB) const {
5228 unsigned OldOpc = MI->getOpcode();
5229 unsigned NewOpc = 0;
5231 // This is only called for instructions that need remapping, so iterating over
5232 // the tiny opcode table is not costly.
5233 static const int NPairs =
5234 sizeof(AddSubFlagsOpcodeMap) / sizeof(AddSubFlagsOpcodePair);
5235 for (AddSubFlagsOpcodePair *Pair = &AddSubFlagsOpcodeMap[0],
5236 *End = &AddSubFlagsOpcodeMap[NPairs]; Pair != End; ++Pair) {
5237 if (OldOpc == Pair->PseudoOpc) {
5238 NewOpc = Pair->MachineOpc;
5245 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5246 DebugLoc dl = MI->getDebugLoc();
5247 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc));
5248 for (unsigned i = 0; i < MI->getNumOperands(); ++i)
5249 MIB.addOperand(MI->getOperand(i));
5250 AddDefaultPred(MIB);
5251 MIB.addReg(ARM::CPSR, RegState::Define); // S bit
5252 MI->eraseFromParent();
5257 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
5258 MachineBasicBlock *BB) const {
5259 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5260 DebugLoc dl = MI->getDebugLoc();
5261 bool isThumb2 = Subtarget->isThumb2();
5262 switch (MI->getOpcode()) {
5264 if (RemapAddSubWithFlags(MI, BB))
5268 llvm_unreachable("Unexpected instr type to insert");
5270 case ARM::ATOMIC_LOAD_ADD_I8:
5271 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
5272 case ARM::ATOMIC_LOAD_ADD_I16:
5273 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
5274 case ARM::ATOMIC_LOAD_ADD_I32:
5275 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
5277 case ARM::ATOMIC_LOAD_AND_I8:
5278 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
5279 case ARM::ATOMIC_LOAD_AND_I16:
5280 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
5281 case ARM::ATOMIC_LOAD_AND_I32:
5282 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
5284 case ARM::ATOMIC_LOAD_OR_I8:
5285 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
5286 case ARM::ATOMIC_LOAD_OR_I16:
5287 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
5288 case ARM::ATOMIC_LOAD_OR_I32:
5289 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
5291 case ARM::ATOMIC_LOAD_XOR_I8:
5292 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
5293 case ARM::ATOMIC_LOAD_XOR_I16:
5294 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
5295 case ARM::ATOMIC_LOAD_XOR_I32:
5296 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
5298 case ARM::ATOMIC_LOAD_NAND_I8:
5299 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
5300 case ARM::ATOMIC_LOAD_NAND_I16:
5301 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
5302 case ARM::ATOMIC_LOAD_NAND_I32:
5303 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
5305 case ARM::ATOMIC_LOAD_SUB_I8:
5306 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
5307 case ARM::ATOMIC_LOAD_SUB_I16:
5308 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
5309 case ARM::ATOMIC_LOAD_SUB_I32:
5310 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
5312 case ARM::ATOMIC_LOAD_MIN_I8:
5313 return EmitAtomicBinaryMinMax(MI, BB, 1, true, ARMCC::LT);
5314 case ARM::ATOMIC_LOAD_MIN_I16:
5315 return EmitAtomicBinaryMinMax(MI, BB, 2, true, ARMCC::LT);
5316 case ARM::ATOMIC_LOAD_MIN_I32:
5317 return EmitAtomicBinaryMinMax(MI, BB, 4, true, ARMCC::LT);
5319 case ARM::ATOMIC_LOAD_MAX_I8:
5320 return EmitAtomicBinaryMinMax(MI, BB, 1, true, ARMCC::GT);
5321 case ARM::ATOMIC_LOAD_MAX_I16:
5322 return EmitAtomicBinaryMinMax(MI, BB, 2, true, ARMCC::GT);
5323 case ARM::ATOMIC_LOAD_MAX_I32:
5324 return EmitAtomicBinaryMinMax(MI, BB, 4, true, ARMCC::GT);
5326 case ARM::ATOMIC_LOAD_UMIN_I8:
5327 return EmitAtomicBinaryMinMax(MI, BB, 1, false, ARMCC::LO);
5328 case ARM::ATOMIC_LOAD_UMIN_I16:
5329 return EmitAtomicBinaryMinMax(MI, BB, 2, false, ARMCC::LO);
5330 case ARM::ATOMIC_LOAD_UMIN_I32:
5331 return EmitAtomicBinaryMinMax(MI, BB, 4, false, ARMCC::LO);
5333 case ARM::ATOMIC_LOAD_UMAX_I8:
5334 return EmitAtomicBinaryMinMax(MI, BB, 1, false, ARMCC::HI);
5335 case ARM::ATOMIC_LOAD_UMAX_I16:
5336 return EmitAtomicBinaryMinMax(MI, BB, 2, false, ARMCC::HI);
5337 case ARM::ATOMIC_LOAD_UMAX_I32:
5338 return EmitAtomicBinaryMinMax(MI, BB, 4, false, ARMCC::HI);
5340 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0);
5341 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0);
5342 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0);
5344 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1);
5345 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
5346 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
5348 case ARM::tMOVCCr_pseudo: {
5349 // To "insert" a SELECT_CC instruction, we actually have to insert the
5350 // diamond control-flow pattern. The incoming instruction knows the
5351 // destination vreg to set, the condition code register to branch on, the
5352 // true/false values to select between, and a branch opcode to use.
5353 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5354 MachineFunction::iterator It = BB;
5360 // cmpTY ccX, r1, r2
5362 // fallthrough --> copy0MBB
5363 MachineBasicBlock *thisMBB = BB;
5364 MachineFunction *F = BB->getParent();
5365 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
5366 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
5367 F->insert(It, copy0MBB);
5368 F->insert(It, sinkMBB);
5370 // Transfer the remainder of BB and its successor edges to sinkMBB.
5371 sinkMBB->splice(sinkMBB->begin(), BB,
5372 llvm::next(MachineBasicBlock::iterator(MI)),
5374 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
5376 BB->addSuccessor(copy0MBB);
5377 BB->addSuccessor(sinkMBB);
5379 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
5380 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
5383 // %FalseValue = ...
5384 // # fallthrough to sinkMBB
5387 // Update machine-CFG edges
5388 BB->addSuccessor(sinkMBB);
5391 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
5394 BuildMI(*BB, BB->begin(), dl,
5395 TII->get(ARM::PHI), MI->getOperand(0).getReg())
5396 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
5397 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
5399 MI->eraseFromParent(); // The pseudo instruction is gone now.
5404 case ARM::BCCZi64: {
5405 // If there is an unconditional branch to the other successor, remove it.
5406 BB->erase(llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
5408 // Compare both parts that make up the double comparison separately for
5410 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
5412 unsigned LHS1 = MI->getOperand(1).getReg();
5413 unsigned LHS2 = MI->getOperand(2).getReg();
5415 AddDefaultPred(BuildMI(BB, dl,
5416 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5417 .addReg(LHS1).addImm(0));
5418 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5419 .addReg(LHS2).addImm(0)
5420 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
5422 unsigned RHS1 = MI->getOperand(3).getReg();
5423 unsigned RHS2 = MI->getOperand(4).getReg();
5424 AddDefaultPred(BuildMI(BB, dl,
5425 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
5426 .addReg(LHS1).addReg(RHS1));
5427 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
5428 .addReg(LHS2).addReg(RHS2)
5429 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
5432 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB();
5433 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
5434 if (MI->getOperand(0).getImm() == ARMCC::NE)
5435 std::swap(destMBB, exitMBB);
5437 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5438 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
5439 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2B : ARM::B))
5442 MI->eraseFromParent(); // The pseudo instruction is gone now.
5448 //===----------------------------------------------------------------------===//
5449 // ARM Optimization Hooks
5450 //===----------------------------------------------------------------------===//
5453 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
5454 TargetLowering::DAGCombinerInfo &DCI) {
5455 SelectionDAG &DAG = DCI.DAG;
5456 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5457 EVT VT = N->getValueType(0);
5458 unsigned Opc = N->getOpcode();
5459 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
5460 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
5461 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
5462 ISD::CondCode CC = ISD::SETCC_INVALID;
5465 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
5467 SDValue CCOp = Slct.getOperand(0);
5468 if (CCOp.getOpcode() == ISD::SETCC)
5469 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
5472 bool DoXform = false;
5474 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
5477 if (LHS.getOpcode() == ISD::Constant &&
5478 cast<ConstantSDNode>(LHS)->isNullValue()) {
5480 } else if (CC != ISD::SETCC_INVALID &&
5481 RHS.getOpcode() == ISD::Constant &&
5482 cast<ConstantSDNode>(RHS)->isNullValue()) {
5483 std::swap(LHS, RHS);
5484 SDValue Op0 = Slct.getOperand(0);
5485 EVT OpVT = isSlctCC ? Op0.getValueType() :
5486 Op0.getOperand(0).getValueType();
5487 bool isInt = OpVT.isInteger();
5488 CC = ISD::getSetCCInverse(CC, isInt);
5490 if (!TLI.isCondCodeLegal(CC, OpVT))
5491 return SDValue(); // Inverse operator isn't legal.
5498 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
5500 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
5501 Slct.getOperand(0), Slct.getOperand(1), CC);
5502 SDValue CCOp = Slct.getOperand(0);
5504 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
5505 CCOp.getOperand(0), CCOp.getOperand(1), CC);
5506 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
5507 CCOp, OtherOp, Result);
5512 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
5513 /// operands N0 and N1. This is a helper for PerformADDCombine that is
5514 /// called with the default operands, and if that fails, with commuted
5516 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
5517 TargetLowering::DAGCombinerInfo &DCI) {
5518 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
5519 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
5520 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
5521 if (Result.getNode()) return Result;
5526 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
5528 static SDValue PerformADDCombine(SDNode *N,
5529 TargetLowering::DAGCombinerInfo &DCI) {
5530 SDValue N0 = N->getOperand(0);
5531 SDValue N1 = N->getOperand(1);
5533 // First try with the default operand order.
5534 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI);
5535 if (Result.getNode())
5538 // If that didn't work, try again with the operands commuted.
5539 return PerformADDCombineWithOperands(N, N1, N0, DCI);
5542 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
5544 static SDValue PerformSUBCombine(SDNode *N,
5545 TargetLowering::DAGCombinerInfo &DCI) {
5546 SDValue N0 = N->getOperand(0);
5547 SDValue N1 = N->getOperand(1);
5549 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
5550 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
5551 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
5552 if (Result.getNode()) return Result;
5558 /// PerformVMULCombine
5559 /// Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the
5560 /// special multiplier accumulator forwarding.
5566 static SDValue PerformVMULCombine(SDNode *N,
5567 TargetLowering::DAGCombinerInfo &DCI,
5568 const ARMSubtarget *Subtarget) {
5569 if (!Subtarget->hasVMLxForwarding())
5572 SelectionDAG &DAG = DCI.DAG;
5573 SDValue N0 = N->getOperand(0);
5574 SDValue N1 = N->getOperand(1);
5575 unsigned Opcode = N0.getOpcode();
5576 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
5577 Opcode != ISD::FADD && Opcode != ISD::FSUB) {
5578 Opcode = N0.getOpcode();
5579 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
5580 Opcode != ISD::FADD && Opcode != ISD::FSUB)
5585 EVT VT = N->getValueType(0);
5586 DebugLoc DL = N->getDebugLoc();
5587 SDValue N00 = N0->getOperand(0);
5588 SDValue N01 = N0->getOperand(1);
5589 return DAG.getNode(Opcode, DL, VT,
5590 DAG.getNode(ISD::MUL, DL, VT, N00, N1),
5591 DAG.getNode(ISD::MUL, DL, VT, N01, N1));
5594 static SDValue PerformMULCombine(SDNode *N,
5595 TargetLowering::DAGCombinerInfo &DCI,
5596 const ARMSubtarget *Subtarget) {
5597 SelectionDAG &DAG = DCI.DAG;
5599 if (Subtarget->isThumb1Only())
5602 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
5605 EVT VT = N->getValueType(0);
5606 if (VT.is64BitVector() || VT.is128BitVector())
5607 return PerformVMULCombine(N, DCI, Subtarget);
5611 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
5615 uint64_t MulAmt = C->getZExtValue();
5616 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt);
5617 ShiftAmt = ShiftAmt & (32 - 1);
5618 SDValue V = N->getOperand(0);
5619 DebugLoc DL = N->getDebugLoc();
5622 MulAmt >>= ShiftAmt;
5623 if (isPowerOf2_32(MulAmt - 1)) {
5624 // (mul x, 2^N + 1) => (add (shl x, N), x)
5625 Res = DAG.getNode(ISD::ADD, DL, VT,
5626 V, DAG.getNode(ISD::SHL, DL, VT,
5627 V, DAG.getConstant(Log2_32(MulAmt-1),
5629 } else if (isPowerOf2_32(MulAmt + 1)) {
5630 // (mul x, 2^N - 1) => (sub (shl x, N), x)
5631 Res = DAG.getNode(ISD::SUB, DL, VT,
5632 DAG.getNode(ISD::SHL, DL, VT,
5633 V, DAG.getConstant(Log2_32(MulAmt+1),
5640 Res = DAG.getNode(ISD::SHL, DL, VT, Res,
5641 DAG.getConstant(ShiftAmt, MVT::i32));
5643 // Do not add new nodes to DAG combiner worklist.
5644 DCI.CombineTo(N, Res, false);
5648 static SDValue PerformANDCombine(SDNode *N,
5649 TargetLowering::DAGCombinerInfo &DCI) {
5651 // Attempt to use immediate-form VBIC
5652 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
5653 DebugLoc dl = N->getDebugLoc();
5654 EVT VT = N->getValueType(0);
5655 SelectionDAG &DAG = DCI.DAG;
5657 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
5660 APInt SplatBits, SplatUndef;
5661 unsigned SplatBitSize;
5664 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5665 if (SplatBitSize <= 64) {
5667 SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(),
5668 SplatUndef.getZExtValue(), SplatBitSize,
5669 DAG, VbicVT, VT.is128BitVector(),
5671 if (Val.getNode()) {
5673 DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0));
5674 SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val);
5675 return DAG.getNode(ISD::BITCAST, dl, VT, Vbic);
5683 /// PerformORCombine - Target-specific dag combine xforms for ISD::OR
5684 static SDValue PerformORCombine(SDNode *N,
5685 TargetLowering::DAGCombinerInfo &DCI,
5686 const ARMSubtarget *Subtarget) {
5687 // Attempt to use immediate-form VORR
5688 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
5689 DebugLoc dl = N->getDebugLoc();
5690 EVT VT = N->getValueType(0);
5691 SelectionDAG &DAG = DCI.DAG;
5693 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
5696 APInt SplatBits, SplatUndef;
5697 unsigned SplatBitSize;
5699 if (BVN && Subtarget->hasNEON() &&
5700 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5701 if (SplatBitSize <= 64) {
5703 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
5704 SplatUndef.getZExtValue(), SplatBitSize,
5705 DAG, VorrVT, VT.is128BitVector(),
5707 if (Val.getNode()) {
5709 DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0));
5710 SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val);
5711 return DAG.getNode(ISD::BITCAST, dl, VT, Vorr);
5716 SDValue N0 = N->getOperand(0);
5717 if (N0.getOpcode() != ISD::AND)
5719 SDValue N1 = N->getOperand(1);
5721 // (or (and B, A), (and C, ~A)) => (VBSL A, B, C) when A is a constant.
5722 if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() &&
5723 DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
5725 unsigned SplatBitSize;
5728 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1));
5730 if (BVN0 && BVN0->isConstantSplat(SplatBits0, SplatUndef, SplatBitSize,
5731 HasAnyUndefs) && !HasAnyUndefs) {
5732 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(1));
5734 if (BVN1 && BVN1->isConstantSplat(SplatBits1, SplatUndef, SplatBitSize,
5735 HasAnyUndefs) && !HasAnyUndefs &&
5736 SplatBits0 == ~SplatBits1) {
5737 // Canonicalize the vector type to make instruction selection simpler.
5738 EVT CanonicalVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
5739 SDValue Result = DAG.getNode(ARMISD::VBSL, dl, CanonicalVT,
5740 N0->getOperand(1), N0->getOperand(0),
5742 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
5747 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when
5750 // BFI is only available on V6T2+
5751 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops())
5754 DebugLoc DL = N->getDebugLoc();
5755 // 1) or (and A, mask), val => ARMbfi A, val, mask
5756 // iff (val & mask) == val
5758 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
5759 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2)
5760 // && mask == ~mask2
5761 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2)
5762 // && ~mask == mask2
5763 // (i.e., copy a bitfield value into another bitfield of the same width)
5768 SDValue N00 = N0.getOperand(0);
5770 // The value and the mask need to be constants so we can verify this is
5771 // actually a bitfield set. If the mask is 0xffff, we can do better
5772 // via a movt instruction, so don't use BFI in that case.
5773 SDValue MaskOp = N0.getOperand(1);
5774 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(MaskOp);
5777 unsigned Mask = MaskC->getZExtValue();
5781 // Case (1): or (and A, mask), val => ARMbfi A, val, mask
5782 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
5784 unsigned Val = N1C->getZExtValue();
5785 if ((Val & ~Mask) != Val)
5788 if (ARM::isBitFieldInvertedMask(Mask)) {
5789 Val >>= CountTrailingZeros_32(~Mask);
5791 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00,
5792 DAG.getConstant(Val, MVT::i32),
5793 DAG.getConstant(Mask, MVT::i32));
5795 // Do not add new nodes to DAG combiner worklist.
5796 DCI.CombineTo(N, Res, false);
5799 } else if (N1.getOpcode() == ISD::AND) {
5800 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
5801 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
5804 unsigned Mask2 = N11C->getZExtValue();
5806 // Mask and ~Mask2 (or reverse) must be equivalent for the BFI pattern
5808 if (ARM::isBitFieldInvertedMask(Mask) &&
5810 // The pack halfword instruction works better for masks that fit it,
5811 // so use that when it's available.
5812 if (Subtarget->hasT2ExtractPack() &&
5813 (Mask == 0xffff || Mask == 0xffff0000))
5816 unsigned amt = CountTrailingZeros_32(Mask2);
5817 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
5818 DAG.getConstant(amt, MVT::i32));
5819 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res,
5820 DAG.getConstant(Mask, MVT::i32));
5821 // Do not add new nodes to DAG combiner worklist.
5822 DCI.CombineTo(N, Res, false);
5824 } else if (ARM::isBitFieldInvertedMask(~Mask) &&
5826 // The pack halfword instruction works better for masks that fit it,
5827 // so use that when it's available.
5828 if (Subtarget->hasT2ExtractPack() &&
5829 (Mask2 == 0xffff || Mask2 == 0xffff0000))
5832 unsigned lsb = CountTrailingZeros_32(Mask);
5833 Res = DAG.getNode(ISD::SRL, DL, VT, N00,
5834 DAG.getConstant(lsb, MVT::i32));
5835 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
5836 DAG.getConstant(Mask2, MVT::i32));
5837 // Do not add new nodes to DAG combiner worklist.
5838 DCI.CombineTo(N, Res, false);
5843 if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) &&
5844 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) &&
5845 ARM::isBitFieldInvertedMask(~Mask)) {
5846 // Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask
5847 // where lsb(mask) == #shamt and masked bits of B are known zero.
5848 SDValue ShAmt = N00.getOperand(1);
5849 unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue();
5850 unsigned LSB = CountTrailingZeros_32(Mask);
5854 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0),
5855 DAG.getConstant(~Mask, MVT::i32));
5857 // Do not add new nodes to DAG combiner worklist.
5858 DCI.CombineTo(N, Res, false);
5864 /// PerformBFICombine - (bfi A, (and B, C1), C2) -> (bfi A, B, C2) iff
5866 static SDValue PerformBFICombine(SDNode *N,
5867 TargetLowering::DAGCombinerInfo &DCI) {
5868 SDValue N1 = N->getOperand(1);
5869 if (N1.getOpcode() == ISD::AND) {
5870 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
5873 unsigned Mask = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
5874 unsigned Mask2 = N11C->getZExtValue();
5875 if ((Mask & Mask2) == Mask2)
5876 return DCI.DAG.getNode(ARMISD::BFI, N->getDebugLoc(), N->getValueType(0),
5877 N->getOperand(0), N1.getOperand(0),
5883 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
5884 /// ARMISD::VMOVRRD.
5885 static SDValue PerformVMOVRRDCombine(SDNode *N,
5886 TargetLowering::DAGCombinerInfo &DCI) {
5887 // vmovrrd(vmovdrr x, y) -> x,y
5888 SDValue InDouble = N->getOperand(0);
5889 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
5890 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
5892 // vmovrrd(load f64) -> (load i32), (load i32)
5893 SDNode *InNode = InDouble.getNode();
5894 if (ISD::isNormalLoad(InNode) && InNode->hasOneUse() &&
5895 InNode->getValueType(0) == MVT::f64 &&
5896 InNode->getOperand(1).getOpcode() == ISD::FrameIndex &&
5897 !cast<LoadSDNode>(InNode)->isVolatile()) {
5898 // TODO: Should this be done for non-FrameIndex operands?
5899 LoadSDNode *LD = cast<LoadSDNode>(InNode);
5901 SelectionDAG &DAG = DCI.DAG;
5902 DebugLoc DL = LD->getDebugLoc();
5903 SDValue BasePtr = LD->getBasePtr();
5904 SDValue NewLD1 = DAG.getLoad(MVT::i32, DL, LD->getChain(), BasePtr,
5905 LD->getPointerInfo(), LD->isVolatile(),
5906 LD->isNonTemporal(), LD->getAlignment());
5908 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
5909 DAG.getConstant(4, MVT::i32));
5910 SDValue NewLD2 = DAG.getLoad(MVT::i32, DL, NewLD1.getValue(1), OffsetPtr,
5911 LD->getPointerInfo(), LD->isVolatile(),
5912 LD->isNonTemporal(),
5913 std::min(4U, LD->getAlignment() / 2));
5915 DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), NewLD2.getValue(1));
5916 SDValue Result = DCI.CombineTo(N, NewLD1, NewLD2);
5917 DCI.RemoveFromWorklist(LD);
5925 /// PerformVMOVDRRCombine - Target-specific dag combine xforms for
5926 /// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands.
5927 static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) {
5928 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X)
5929 SDValue Op0 = N->getOperand(0);
5930 SDValue Op1 = N->getOperand(1);
5931 if (Op0.getOpcode() == ISD::BITCAST)
5932 Op0 = Op0.getOperand(0);
5933 if (Op1.getOpcode() == ISD::BITCAST)
5934 Op1 = Op1.getOperand(0);
5935 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
5936 Op0.getNode() == Op1.getNode() &&
5937 Op0.getResNo() == 0 && Op1.getResNo() == 1)
5938 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
5939 N->getValueType(0), Op0.getOperand(0));
5943 /// PerformSTORECombine - Target-specific dag combine xforms for
5945 static SDValue PerformSTORECombine(SDNode *N,
5946 TargetLowering::DAGCombinerInfo &DCI) {
5947 // Bitcast an i64 store extracted from a vector to f64.
5948 // Otherwise, the i64 value will be legalized to a pair of i32 values.
5949 StoreSDNode *St = cast<StoreSDNode>(N);
5950 SDValue StVal = St->getValue();
5951 if (!ISD::isNormalStore(St) || St->isVolatile())
5954 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR &&
5955 StVal.getNode()->hasOneUse() && !St->isVolatile()) {
5956 SelectionDAG &DAG = DCI.DAG;
5957 DebugLoc DL = St->getDebugLoc();
5958 SDValue BasePtr = St->getBasePtr();
5959 SDValue NewST1 = DAG.getStore(St->getChain(), DL,
5960 StVal.getNode()->getOperand(0), BasePtr,
5961 St->getPointerInfo(), St->isVolatile(),
5962 St->isNonTemporal(), St->getAlignment());
5964 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
5965 DAG.getConstant(4, MVT::i32));
5966 return DAG.getStore(NewST1.getValue(0), DL, StVal.getNode()->getOperand(1),
5967 OffsetPtr, St->getPointerInfo(), St->isVolatile(),
5968 St->isNonTemporal(),
5969 std::min(4U, St->getAlignment() / 2));
5972 if (StVal.getValueType() != MVT::i64 ||
5973 StVal.getNode()->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5976 SelectionDAG &DAG = DCI.DAG;
5977 DebugLoc dl = StVal.getDebugLoc();
5978 SDValue IntVec = StVal.getOperand(0);
5979 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
5980 IntVec.getValueType().getVectorNumElements());
5981 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec);
5982 SDValue ExtElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
5983 Vec, StVal.getOperand(1));
5984 dl = N->getDebugLoc();
5985 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt);
5986 // Make the DAGCombiner fold the bitcasts.
5987 DCI.AddToWorklist(Vec.getNode());
5988 DCI.AddToWorklist(ExtElt.getNode());
5989 DCI.AddToWorklist(V.getNode());
5990 return DAG.getStore(St->getChain(), dl, V, St->getBasePtr(),
5991 St->getPointerInfo(), St->isVolatile(),
5992 St->isNonTemporal(), St->getAlignment(),
5996 /// hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node
5997 /// are normal, non-volatile loads. If so, it is profitable to bitcast an
5998 /// i64 vector to have f64 elements, since the value can then be loaded
5999 /// directly into a VFP register.
6000 static bool hasNormalLoadOperand(SDNode *N) {
6001 unsigned NumElts = N->getValueType(0).getVectorNumElements();
6002 for (unsigned i = 0; i < NumElts; ++i) {
6003 SDNode *Elt = N->getOperand(i).getNode();
6004 if (ISD::isNormalLoad(Elt) && !cast<LoadSDNode>(Elt)->isVolatile())
6010 /// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for
6011 /// ISD::BUILD_VECTOR.
6012 static SDValue PerformBUILD_VECTORCombine(SDNode *N,
6013 TargetLowering::DAGCombinerInfo &DCI){
6014 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X):
6015 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value
6016 // into a pair of GPRs, which is fine when the value is used as a scalar,
6017 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD.
6018 SelectionDAG &DAG = DCI.DAG;
6019 if (N->getNumOperands() == 2) {
6020 SDValue RV = PerformVMOVDRRCombine(N, DAG);
6025 // Load i64 elements as f64 values so that type legalization does not split
6026 // them up into i32 values.
6027 EVT VT = N->getValueType(0);
6028 if (VT.getVectorElementType() != MVT::i64 || !hasNormalLoadOperand(N))
6030 DebugLoc dl = N->getDebugLoc();
6031 SmallVector<SDValue, 8> Ops;
6032 unsigned NumElts = VT.getVectorNumElements();
6033 for (unsigned i = 0; i < NumElts; ++i) {
6034 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(i));
6036 // Make the DAGCombiner fold the bitcast.
6037 DCI.AddToWorklist(V.getNode());
6039 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, NumElts);
6040 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, FloatVT, Ops.data(), NumElts);
6041 return DAG.getNode(ISD::BITCAST, dl, VT, BV);
6044 /// PerformInsertEltCombine - Target-specific dag combine xforms for
6045 /// ISD::INSERT_VECTOR_ELT.
6046 static SDValue PerformInsertEltCombine(SDNode *N,
6047 TargetLowering::DAGCombinerInfo &DCI) {
6048 // Bitcast an i64 load inserted into a vector to f64.
6049 // Otherwise, the i64 value will be legalized to a pair of i32 values.
6050 EVT VT = N->getValueType(0);
6051 SDNode *Elt = N->getOperand(1).getNode();
6052 if (VT.getVectorElementType() != MVT::i64 ||
6053 !ISD::isNormalLoad(Elt) || cast<LoadSDNode>(Elt)->isVolatile())
6056 SelectionDAG &DAG = DCI.DAG;
6057 DebugLoc dl = N->getDebugLoc();
6058 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
6059 VT.getVectorNumElements());
6060 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, N->getOperand(0));
6061 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(1));
6062 // Make the DAGCombiner fold the bitcasts.
6063 DCI.AddToWorklist(Vec.getNode());
6064 DCI.AddToWorklist(V.getNode());
6065 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT,
6066 Vec, V, N->getOperand(2));
6067 return DAG.getNode(ISD::BITCAST, dl, VT, InsElt);
6070 /// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for
6071 /// ISD::VECTOR_SHUFFLE.
6072 static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) {
6073 // The LLVM shufflevector instruction does not require the shuffle mask
6074 // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does
6075 // have that requirement. When translating to ISD::VECTOR_SHUFFLE, if the
6076 // operands do not match the mask length, they are extended by concatenating
6077 // them with undef vectors. That is probably the right thing for other
6078 // targets, but for NEON it is better to concatenate two double-register
6079 // size vector operands into a single quad-register size vector. Do that
6080 // transformation here:
6081 // shuffle(concat(v1, undef), concat(v2, undef)) ->
6082 // shuffle(concat(v1, v2), undef)
6083 SDValue Op0 = N->getOperand(0);
6084 SDValue Op1 = N->getOperand(1);
6085 if (Op0.getOpcode() != ISD::CONCAT_VECTORS ||
6086 Op1.getOpcode() != ISD::CONCAT_VECTORS ||
6087 Op0.getNumOperands() != 2 ||
6088 Op1.getNumOperands() != 2)
6090 SDValue Concat0Op1 = Op0.getOperand(1);
6091 SDValue Concat1Op1 = Op1.getOperand(1);
6092 if (Concat0Op1.getOpcode() != ISD::UNDEF ||
6093 Concat1Op1.getOpcode() != ISD::UNDEF)
6095 // Skip the transformation if any of the types are illegal.
6096 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6097 EVT VT = N->getValueType(0);
6098 if (!TLI.isTypeLegal(VT) ||
6099 !TLI.isTypeLegal(Concat0Op1.getValueType()) ||
6100 !TLI.isTypeLegal(Concat1Op1.getValueType()))
6103 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT,
6104 Op0.getOperand(0), Op1.getOperand(0));
6105 // Translate the shuffle mask.
6106 SmallVector<int, 16> NewMask;
6107 unsigned NumElts = VT.getVectorNumElements();
6108 unsigned HalfElts = NumElts/2;
6109 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
6110 for (unsigned n = 0; n < NumElts; ++n) {
6111 int MaskElt = SVN->getMaskElt(n);
6113 if (MaskElt < (int)HalfElts)
6115 else if (MaskElt >= (int)NumElts && MaskElt < (int)(NumElts + HalfElts))
6116 NewElt = HalfElts + MaskElt - NumElts;
6117 NewMask.push_back(NewElt);
6119 return DAG.getVectorShuffle(VT, N->getDebugLoc(), NewConcat,
6120 DAG.getUNDEF(VT), NewMask.data());
6123 /// CombineBaseUpdate - Target-specific DAG combine function for VLDDUP and
6124 /// NEON load/store intrinsics to merge base address updates.
6125 static SDValue CombineBaseUpdate(SDNode *N,
6126 TargetLowering::DAGCombinerInfo &DCI) {
6127 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
6130 SelectionDAG &DAG = DCI.DAG;
6131 bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID ||
6132 N->getOpcode() == ISD::INTRINSIC_W_CHAIN);
6133 unsigned AddrOpIdx = (isIntrinsic ? 2 : 1);
6134 SDValue Addr = N->getOperand(AddrOpIdx);
6136 // Search for a use of the address operand that is an increment.
6137 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
6138 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
6140 if (User->getOpcode() != ISD::ADD ||
6141 UI.getUse().getResNo() != Addr.getResNo())
6144 // Check that the add is independent of the load/store. Otherwise, folding
6145 // it would create a cycle.
6146 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
6149 // Find the new opcode for the updating load/store.
6151 bool isLaneOp = false;
6152 unsigned NewOpc = 0;
6153 unsigned NumVecs = 0;
6155 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
6157 default: assert(0 && "unexpected intrinsic for Neon base update");
6158 case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD;
6160 case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD;
6162 case Intrinsic::arm_neon_vld3: NewOpc = ARMISD::VLD3_UPD;
6164 case Intrinsic::arm_neon_vld4: NewOpc = ARMISD::VLD4_UPD;
6166 case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD;
6167 NumVecs = 2; isLaneOp = true; break;
6168 case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD;
6169 NumVecs = 3; isLaneOp = true; break;
6170 case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD;
6171 NumVecs = 4; isLaneOp = true; break;
6172 case Intrinsic::arm_neon_vst1: NewOpc = ARMISD::VST1_UPD;
6173 NumVecs = 1; isLoad = false; break;
6174 case Intrinsic::arm_neon_vst2: NewOpc = ARMISD::VST2_UPD;
6175 NumVecs = 2; isLoad = false; break;
6176 case Intrinsic::arm_neon_vst3: NewOpc = ARMISD::VST3_UPD;
6177 NumVecs = 3; isLoad = false; break;
6178 case Intrinsic::arm_neon_vst4: NewOpc = ARMISD::VST4_UPD;
6179 NumVecs = 4; isLoad = false; break;
6180 case Intrinsic::arm_neon_vst2lane: NewOpc = ARMISD::VST2LN_UPD;
6181 NumVecs = 2; isLoad = false; isLaneOp = true; break;
6182 case Intrinsic::arm_neon_vst3lane: NewOpc = ARMISD::VST3LN_UPD;
6183 NumVecs = 3; isLoad = false; isLaneOp = true; break;
6184 case Intrinsic::arm_neon_vst4lane: NewOpc = ARMISD::VST4LN_UPD;
6185 NumVecs = 4; isLoad = false; isLaneOp = true; break;
6189 switch (N->getOpcode()) {
6190 default: assert(0 && "unexpected opcode for Neon base update");
6191 case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break;
6192 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break;
6193 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break;
6197 // Find the size of memory referenced by the load/store.
6200 VecTy = N->getValueType(0);
6202 VecTy = N->getOperand(AddrOpIdx+1).getValueType();
6203 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
6205 NumBytes /= VecTy.getVectorNumElements();
6207 // If the increment is a constant, it must match the memory ref size.
6208 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
6209 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
6210 uint64_t IncVal = CInc->getZExtValue();
6211 if (IncVal != NumBytes)
6213 } else if (NumBytes >= 3 * 16) {
6214 // VLD3/4 and VST3/4 for 128-bit vectors are implemented with two
6215 // separate instructions that make it harder to use a non-constant update.
6219 // Create the new updating load/store node.
6221 unsigned NumResultVecs = (isLoad ? NumVecs : 0);
6223 for (n = 0; n < NumResultVecs; ++n)
6225 Tys[n++] = MVT::i32;
6226 Tys[n] = MVT::Other;
6227 SDVTList SDTys = DAG.getVTList(Tys, NumResultVecs+2);
6228 SmallVector<SDValue, 8> Ops;
6229 Ops.push_back(N->getOperand(0)); // incoming chain
6230 Ops.push_back(N->getOperand(AddrOpIdx));
6232 for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands(); ++i) {
6233 Ops.push_back(N->getOperand(i));
6235 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
6236 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, N->getDebugLoc(), SDTys,
6237 Ops.data(), Ops.size(),
6238 MemInt->getMemoryVT(),
6239 MemInt->getMemOperand());
6242 std::vector<SDValue> NewResults;
6243 for (unsigned i = 0; i < NumResultVecs; ++i) {
6244 NewResults.push_back(SDValue(UpdN.getNode(), i));
6246 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs+1)); // chain
6247 DCI.CombineTo(N, NewResults);
6248 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
6255 /// CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a
6256 /// vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic
6257 /// are also VDUPLANEs. If so, combine them to a vldN-dup operation and
6259 static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
6260 SelectionDAG &DAG = DCI.DAG;
6261 EVT VT = N->getValueType(0);
6262 // vldN-dup instructions only support 64-bit vectors for N > 1.
6263 if (!VT.is64BitVector())
6266 // Check if the VDUPLANE operand is a vldN-dup intrinsic.
6267 SDNode *VLD = N->getOperand(0).getNode();
6268 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN)
6270 unsigned NumVecs = 0;
6271 unsigned NewOpc = 0;
6272 unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue();
6273 if (IntNo == Intrinsic::arm_neon_vld2lane) {
6275 NewOpc = ARMISD::VLD2DUP;
6276 } else if (IntNo == Intrinsic::arm_neon_vld3lane) {
6278 NewOpc = ARMISD::VLD3DUP;
6279 } else if (IntNo == Intrinsic::arm_neon_vld4lane) {
6281 NewOpc = ARMISD::VLD4DUP;
6286 // First check that all the vldN-lane uses are VDUPLANEs and that the lane
6287 // numbers match the load.
6288 unsigned VLDLaneNo =
6289 cast<ConstantSDNode>(VLD->getOperand(NumVecs+3))->getZExtValue();
6290 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
6292 // Ignore uses of the chain result.
6293 if (UI.getUse().getResNo() == NumVecs)
6296 if (User->getOpcode() != ARMISD::VDUPLANE ||
6297 VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue())
6301 // Create the vldN-dup node.
6304 for (n = 0; n < NumVecs; ++n)
6306 Tys[n] = MVT::Other;
6307 SDVTList SDTys = DAG.getVTList(Tys, NumVecs+1);
6308 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) };
6309 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD);
6310 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, VLD->getDebugLoc(), SDTys,
6311 Ops, 2, VLDMemInt->getMemoryVT(),
6312 VLDMemInt->getMemOperand());
6315 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
6317 unsigned ResNo = UI.getUse().getResNo();
6318 // Ignore uses of the chain result.
6319 if (ResNo == NumVecs)
6322 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo));
6325 // Now the vldN-lane intrinsic is dead except for its chain result.
6326 // Update uses of the chain.
6327 std::vector<SDValue> VLDDupResults;
6328 for (unsigned n = 0; n < NumVecs; ++n)
6329 VLDDupResults.push_back(SDValue(VLDDup.getNode(), n));
6330 VLDDupResults.push_back(SDValue(VLDDup.getNode(), NumVecs));
6331 DCI.CombineTo(VLD, VLDDupResults);
6336 /// PerformVDUPLANECombine - Target-specific dag combine xforms for
6337 /// ARMISD::VDUPLANE.
6338 static SDValue PerformVDUPLANECombine(SDNode *N,
6339 TargetLowering::DAGCombinerInfo &DCI) {
6340 SDValue Op = N->getOperand(0);
6342 // If the source is a vldN-lane (N > 1) intrinsic, and all the other uses
6343 // of that intrinsic are also VDUPLANEs, combine them to a vldN-dup operation.
6344 if (CombineVLDDUP(N, DCI))
6345 return SDValue(N, 0);
6347 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
6348 // redundant. Ignore bit_converts for now; element sizes are checked below.
6349 while (Op.getOpcode() == ISD::BITCAST)
6350 Op = Op.getOperand(0);
6351 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
6354 // Make sure the VMOV element size is not bigger than the VDUPLANE elements.
6355 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits();
6356 // The canonical VMOV for a zero vector uses a 32-bit element size.
6357 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6359 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
6361 EVT VT = N->getValueType(0);
6362 if (EltSize > VT.getVectorElementType().getSizeInBits())
6365 return DCI.DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
6368 /// getVShiftImm - Check if this is a valid build_vector for the immediate
6369 /// operand of a vector shift operation, where all the elements of the
6370 /// build_vector must have the same constant integer value.
6371 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
6372 // Ignore bit_converts.
6373 while (Op.getOpcode() == ISD::BITCAST)
6374 Op = Op.getOperand(0);
6375 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
6376 APInt SplatBits, SplatUndef;
6377 unsigned SplatBitSize;
6379 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
6380 HasAnyUndefs, ElementBits) ||
6381 SplatBitSize > ElementBits)
6383 Cnt = SplatBits.getSExtValue();
6387 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
6388 /// operand of a vector shift left operation. That value must be in the range:
6389 /// 0 <= Value < ElementBits for a left shift; or
6390 /// 0 <= Value <= ElementBits for a long left shift.
6391 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
6392 assert(VT.isVector() && "vector shift count is not a vector type");
6393 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
6394 if (! getVShiftImm(Op, ElementBits, Cnt))
6396 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
6399 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
6400 /// operand of a vector shift right operation. For a shift opcode, the value
6401 /// is positive, but for an intrinsic the value count must be negative. The
6402 /// absolute value must be in the range:
6403 /// 1 <= |Value| <= ElementBits for a right shift; or
6404 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
6405 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
6407 assert(VT.isVector() && "vector shift count is not a vector type");
6408 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
6409 if (! getVShiftImm(Op, ElementBits, Cnt))
6413 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
6416 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
6417 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
6418 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
6421 // Don't do anything for most intrinsics.
6424 // Vector shifts: check for immediate versions and lower them.
6425 // Note: This is done during DAG combining instead of DAG legalizing because
6426 // the build_vectors for 64-bit vector element shift counts are generally
6427 // not legal, and it is hard to see their values after they get legalized to
6428 // loads from a constant pool.
6429 case Intrinsic::arm_neon_vshifts:
6430 case Intrinsic::arm_neon_vshiftu:
6431 case Intrinsic::arm_neon_vshiftls:
6432 case Intrinsic::arm_neon_vshiftlu:
6433 case Intrinsic::arm_neon_vshiftn:
6434 case Intrinsic::arm_neon_vrshifts:
6435 case Intrinsic::arm_neon_vrshiftu:
6436 case Intrinsic::arm_neon_vrshiftn:
6437 case Intrinsic::arm_neon_vqshifts:
6438 case Intrinsic::arm_neon_vqshiftu:
6439 case Intrinsic::arm_neon_vqshiftsu:
6440 case Intrinsic::arm_neon_vqshiftns:
6441 case Intrinsic::arm_neon_vqshiftnu:
6442 case Intrinsic::arm_neon_vqshiftnsu:
6443 case Intrinsic::arm_neon_vqrshiftns:
6444 case Intrinsic::arm_neon_vqrshiftnu:
6445 case Intrinsic::arm_neon_vqrshiftnsu: {
6446 EVT VT = N->getOperand(1).getValueType();
6448 unsigned VShiftOpc = 0;
6451 case Intrinsic::arm_neon_vshifts:
6452 case Intrinsic::arm_neon_vshiftu:
6453 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
6454 VShiftOpc = ARMISD::VSHL;
6457 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
6458 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
6459 ARMISD::VSHRs : ARMISD::VSHRu);
6464 case Intrinsic::arm_neon_vshiftls:
6465 case Intrinsic::arm_neon_vshiftlu:
6466 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
6468 llvm_unreachable("invalid shift count for vshll intrinsic");
6470 case Intrinsic::arm_neon_vrshifts:
6471 case Intrinsic::arm_neon_vrshiftu:
6472 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
6476 case Intrinsic::arm_neon_vqshifts:
6477 case Intrinsic::arm_neon_vqshiftu:
6478 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
6482 case Intrinsic::arm_neon_vqshiftsu:
6483 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
6485 llvm_unreachable("invalid shift count for vqshlu intrinsic");
6487 case Intrinsic::arm_neon_vshiftn:
6488 case Intrinsic::arm_neon_vrshiftn:
6489 case Intrinsic::arm_neon_vqshiftns:
6490 case Intrinsic::arm_neon_vqshiftnu:
6491 case Intrinsic::arm_neon_vqshiftnsu:
6492 case Intrinsic::arm_neon_vqrshiftns:
6493 case Intrinsic::arm_neon_vqrshiftnu:
6494 case Intrinsic::arm_neon_vqrshiftnsu:
6495 // Narrowing shifts require an immediate right shift.
6496 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
6498 llvm_unreachable("invalid shift count for narrowing vector shift "
6502 llvm_unreachable("unhandled vector shift");
6506 case Intrinsic::arm_neon_vshifts:
6507 case Intrinsic::arm_neon_vshiftu:
6508 // Opcode already set above.
6510 case Intrinsic::arm_neon_vshiftls:
6511 case Intrinsic::arm_neon_vshiftlu:
6512 if (Cnt == VT.getVectorElementType().getSizeInBits())
6513 VShiftOpc = ARMISD::VSHLLi;
6515 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
6516 ARMISD::VSHLLs : ARMISD::VSHLLu);
6518 case Intrinsic::arm_neon_vshiftn:
6519 VShiftOpc = ARMISD::VSHRN; break;
6520 case Intrinsic::arm_neon_vrshifts:
6521 VShiftOpc = ARMISD::VRSHRs; break;
6522 case Intrinsic::arm_neon_vrshiftu:
6523 VShiftOpc = ARMISD::VRSHRu; break;
6524 case Intrinsic::arm_neon_vrshiftn:
6525 VShiftOpc = ARMISD::VRSHRN; break;
6526 case Intrinsic::arm_neon_vqshifts:
6527 VShiftOpc = ARMISD::VQSHLs; break;
6528 case Intrinsic::arm_neon_vqshiftu:
6529 VShiftOpc = ARMISD::VQSHLu; break;
6530 case Intrinsic::arm_neon_vqshiftsu:
6531 VShiftOpc = ARMISD::VQSHLsu; break;
6532 case Intrinsic::arm_neon_vqshiftns:
6533 VShiftOpc = ARMISD::VQSHRNs; break;
6534 case Intrinsic::arm_neon_vqshiftnu:
6535 VShiftOpc = ARMISD::VQSHRNu; break;
6536 case Intrinsic::arm_neon_vqshiftnsu:
6537 VShiftOpc = ARMISD::VQSHRNsu; break;
6538 case Intrinsic::arm_neon_vqrshiftns:
6539 VShiftOpc = ARMISD::VQRSHRNs; break;
6540 case Intrinsic::arm_neon_vqrshiftnu:
6541 VShiftOpc = ARMISD::VQRSHRNu; break;
6542 case Intrinsic::arm_neon_vqrshiftnsu:
6543 VShiftOpc = ARMISD::VQRSHRNsu; break;
6546 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
6547 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
6550 case Intrinsic::arm_neon_vshiftins: {
6551 EVT VT = N->getOperand(1).getValueType();
6553 unsigned VShiftOpc = 0;
6555 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
6556 VShiftOpc = ARMISD::VSLI;
6557 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
6558 VShiftOpc = ARMISD::VSRI;
6560 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
6563 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
6564 N->getOperand(1), N->getOperand(2),
6565 DAG.getConstant(Cnt, MVT::i32));
6568 case Intrinsic::arm_neon_vqrshifts:
6569 case Intrinsic::arm_neon_vqrshiftu:
6570 // No immediate versions of these to check for.
6577 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
6578 /// lowers them. As with the vector shift intrinsics, this is done during DAG
6579 /// combining instead of DAG legalizing because the build_vectors for 64-bit
6580 /// vector element shift counts are generally not legal, and it is hard to see
6581 /// their values after they get legalized to loads from a constant pool.
6582 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
6583 const ARMSubtarget *ST) {
6584 EVT VT = N->getValueType(0);
6586 // Nothing to be done for scalar shifts.
6587 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6588 if (!VT.isVector() || !TLI.isTypeLegal(VT))
6591 assert(ST->hasNEON() && "unexpected vector shift");
6594 switch (N->getOpcode()) {
6595 default: llvm_unreachable("unexpected shift opcode");
6598 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
6599 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
6600 DAG.getConstant(Cnt, MVT::i32));
6605 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
6606 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
6607 ARMISD::VSHRs : ARMISD::VSHRu);
6608 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
6609 DAG.getConstant(Cnt, MVT::i32));
6615 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
6616 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
6617 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
6618 const ARMSubtarget *ST) {
6619 SDValue N0 = N->getOperand(0);
6621 // Check for sign- and zero-extensions of vector extract operations of 8-
6622 // and 16-bit vector elements. NEON supports these directly. They are
6623 // handled during DAG combining because type legalization will promote them
6624 // to 32-bit types and it is messy to recognize the operations after that.
6625 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
6626 SDValue Vec = N0.getOperand(0);
6627 SDValue Lane = N0.getOperand(1);
6628 EVT VT = N->getValueType(0);
6629 EVT EltVT = N0.getValueType();
6630 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6632 if (VT == MVT::i32 &&
6633 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
6634 TLI.isTypeLegal(Vec.getValueType()) &&
6635 isa<ConstantSDNode>(Lane)) {
6638 switch (N->getOpcode()) {
6639 default: llvm_unreachable("unexpected opcode");
6640 case ISD::SIGN_EXTEND:
6641 Opc = ARMISD::VGETLANEs;
6643 case ISD::ZERO_EXTEND:
6644 case ISD::ANY_EXTEND:
6645 Opc = ARMISD::VGETLANEu;
6648 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
6655 /// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
6656 /// to match f32 max/min patterns to use NEON vmax/vmin instructions.
6657 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
6658 const ARMSubtarget *ST) {
6659 // If the target supports NEON, try to use vmax/vmin instructions for f32
6660 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set,
6661 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
6662 // a NaN; only do the transformation when it matches that behavior.
6664 // For now only do this when using NEON for FP operations; if using VFP, it
6665 // is not obvious that the benefit outweighs the cost of switching to the
6667 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
6668 N->getValueType(0) != MVT::f32)
6671 SDValue CondLHS = N->getOperand(0);
6672 SDValue CondRHS = N->getOperand(1);
6673 SDValue LHS = N->getOperand(2);
6674 SDValue RHS = N->getOperand(3);
6675 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
6677 unsigned Opcode = 0;
6679 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
6680 IsReversed = false; // x CC y ? x : y
6681 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
6682 IsReversed = true ; // x CC y ? y : x
6696 // If LHS is NaN, an ordered comparison will be false and the result will
6697 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
6698 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
6699 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
6700 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
6702 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
6703 // will return -0, so vmin can only be used for unsafe math or if one of
6704 // the operands is known to be nonzero.
6705 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
6707 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
6709 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
6718 // If LHS is NaN, an ordered comparison will be false and the result will
6719 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
6720 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
6721 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
6722 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
6724 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
6725 // will return +0, so vmax can only be used for unsafe math or if one of
6726 // the operands is known to be nonzero.
6727 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
6729 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
6731 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
6737 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS);
6740 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
6741 DAGCombinerInfo &DCI) const {
6742 switch (N->getOpcode()) {
6744 case ISD::ADD: return PerformADDCombine(N, DCI);
6745 case ISD::SUB: return PerformSUBCombine(N, DCI);
6746 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
6747 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
6748 case ISD::AND: return PerformANDCombine(N, DCI);
6749 case ARMISD::BFI: return PerformBFICombine(N, DCI);
6750 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
6751 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
6752 case ISD::STORE: return PerformSTORECombine(N, DCI);
6753 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI);
6754 case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI);
6755 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
6756 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
6757 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
6760 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
6761 case ISD::SIGN_EXTEND:
6762 case ISD::ZERO_EXTEND:
6763 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
6764 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
6765 case ARMISD::VLD2DUP:
6766 case ARMISD::VLD3DUP:
6767 case ARMISD::VLD4DUP:
6768 return CombineBaseUpdate(N, DCI);
6769 case ISD::INTRINSIC_VOID:
6770 case ISD::INTRINSIC_W_CHAIN:
6771 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
6772 case Intrinsic::arm_neon_vld1:
6773 case Intrinsic::arm_neon_vld2:
6774 case Intrinsic::arm_neon_vld3:
6775 case Intrinsic::arm_neon_vld4:
6776 case Intrinsic::arm_neon_vld2lane:
6777 case Intrinsic::arm_neon_vld3lane:
6778 case Intrinsic::arm_neon_vld4lane:
6779 case Intrinsic::arm_neon_vst1:
6780 case Intrinsic::arm_neon_vst2:
6781 case Intrinsic::arm_neon_vst3:
6782 case Intrinsic::arm_neon_vst4:
6783 case Intrinsic::arm_neon_vst2lane:
6784 case Intrinsic::arm_neon_vst3lane:
6785 case Intrinsic::arm_neon_vst4lane:
6786 return CombineBaseUpdate(N, DCI);
6794 bool ARMTargetLowering::isDesirableToTransformToIntegerOp(unsigned Opc,
6796 return (VT == MVT::f32) && (Opc == ISD::LOAD || Opc == ISD::STORE);
6799 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
6800 if (!Subtarget->allowsUnalignedMem())
6803 switch (VT.getSimpleVT().SimpleTy) {
6810 // FIXME: VLD1 etc with standard alignment is legal.
6814 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
6819 switch (VT.getSimpleVT().SimpleTy) {
6820 default: return false;
6835 if ((V & (Scale - 1)) != 0)
6838 return V == (V & ((1LL << 5) - 1));
6841 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
6842 const ARMSubtarget *Subtarget) {
6849 switch (VT.getSimpleVT().SimpleTy) {
6850 default: return false;
6855 // + imm12 or - imm8
6857 return V == (V & ((1LL << 8) - 1));
6858 return V == (V & ((1LL << 12) - 1));
6861 // Same as ARM mode. FIXME: NEON?
6862 if (!Subtarget->hasVFP2())
6867 return V == (V & ((1LL << 8) - 1));
6871 /// isLegalAddressImmediate - Return true if the integer value can be used
6872 /// as the offset of the target addressing mode for load / store of the
6874 static bool isLegalAddressImmediate(int64_t V, EVT VT,
6875 const ARMSubtarget *Subtarget) {
6882 if (Subtarget->isThumb1Only())
6883 return isLegalT1AddressImmediate(V, VT);
6884 else if (Subtarget->isThumb2())
6885 return isLegalT2AddressImmediate(V, VT, Subtarget);
6890 switch (VT.getSimpleVT().SimpleTy) {
6891 default: return false;
6896 return V == (V & ((1LL << 12) - 1));
6899 return V == (V & ((1LL << 8) - 1));
6902 if (!Subtarget->hasVFP2()) // FIXME: NEON?
6907 return V == (V & ((1LL << 8) - 1));
6911 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
6913 int Scale = AM.Scale;
6917 switch (VT.getSimpleVT().SimpleTy) {
6918 default: return false;
6927 return Scale == 2 || Scale == 4 || Scale == 8;
6930 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
6934 // Note, we allow "void" uses (basically, uses that aren't loads or
6935 // stores), because arm allows folding a scale into many arithmetic
6936 // operations. This should be made more precise and revisited later.
6938 // Allow r << imm, but the imm has to be a multiple of two.
6939 if (Scale & 1) return false;
6940 return isPowerOf2_32(Scale);
6944 /// isLegalAddressingMode - Return true if the addressing mode represented
6945 /// by AM is legal for this target, for a load/store of the specified type.
6946 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
6947 const Type *Ty) const {
6948 EVT VT = getValueType(Ty, true);
6949 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
6952 // Can never fold addr of global into load/store.
6957 case 0: // no scale reg, must be "r+i" or "r", or "i".
6960 if (Subtarget->isThumb1Only())
6964 // ARM doesn't support any R+R*scale+imm addr modes.
6971 if (Subtarget->isThumb2())
6972 return isLegalT2ScaledAddressingMode(AM, VT);
6974 int Scale = AM.Scale;
6975 switch (VT.getSimpleVT().SimpleTy) {
6976 default: return false;
6980 if (Scale < 0) Scale = -Scale;
6984 return isPowerOf2_32(Scale & ~1);
6988 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
6993 // Note, we allow "void" uses (basically, uses that aren't loads or
6994 // stores), because arm allows folding a scale into many arithmetic
6995 // operations. This should be made more precise and revisited later.
6997 // Allow r << imm, but the imm has to be a multiple of two.
6998 if (Scale & 1) return false;
6999 return isPowerOf2_32(Scale);
7006 /// isLegalICmpImmediate - Return true if the specified immediate is legal
7007 /// icmp immediate, that is the target has icmp instructions which can compare
7008 /// a register against the immediate without having to materialize the
7009 /// immediate into a register.
7010 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
7011 if (!Subtarget->isThumb())
7012 return ARM_AM::getSOImmVal(Imm) != -1;
7013 if (Subtarget->isThumb2())
7014 return ARM_AM::getT2SOImmVal(Imm) != -1;
7015 return Imm >= 0 && Imm <= 255;
7018 /// isLegalAddImmediate - Return true if the specified immediate is legal
7019 /// add immediate, that is the target has add instructions which can add
7020 /// a register with the immediate without having to materialize the
7021 /// immediate into a register.
7022 bool ARMTargetLowering::isLegalAddImmediate(int64_t Imm) const {
7023 return ARM_AM::getSOImmVal(Imm) != -1;
7026 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
7027 bool isSEXTLoad, SDValue &Base,
7028 SDValue &Offset, bool &isInc,
7029 SelectionDAG &DAG) {
7030 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
7033 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
7035 Base = Ptr->getOperand(0);
7036 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
7037 int RHSC = (int)RHS->getZExtValue();
7038 if (RHSC < 0 && RHSC > -256) {
7039 assert(Ptr->getOpcode() == ISD::ADD);
7041 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
7045 isInc = (Ptr->getOpcode() == ISD::ADD);
7046 Offset = Ptr->getOperand(1);
7048 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
7050 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
7051 int RHSC = (int)RHS->getZExtValue();
7052 if (RHSC < 0 && RHSC > -0x1000) {
7053 assert(Ptr->getOpcode() == ISD::ADD);
7055 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
7056 Base = Ptr->getOperand(0);
7061 if (Ptr->getOpcode() == ISD::ADD) {
7063 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
7064 if (ShOpcVal != ARM_AM::no_shift) {
7065 Base = Ptr->getOperand(1);
7066 Offset = Ptr->getOperand(0);
7068 Base = Ptr->getOperand(0);
7069 Offset = Ptr->getOperand(1);
7074 isInc = (Ptr->getOpcode() == ISD::ADD);
7075 Base = Ptr->getOperand(0);
7076 Offset = Ptr->getOperand(1);
7080 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
7084 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
7085 bool isSEXTLoad, SDValue &Base,
7086 SDValue &Offset, bool &isInc,
7087 SelectionDAG &DAG) {
7088 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
7091 Base = Ptr->getOperand(0);
7092 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
7093 int RHSC = (int)RHS->getZExtValue();
7094 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
7095 assert(Ptr->getOpcode() == ISD::ADD);
7097 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
7099 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
7100 isInc = Ptr->getOpcode() == ISD::ADD;
7101 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
7109 /// getPreIndexedAddressParts - returns true by value, base pointer and
7110 /// offset pointer and addressing mode by reference if the node's address
7111 /// can be legally represented as pre-indexed load / store address.
7113 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
7115 ISD::MemIndexedMode &AM,
7116 SelectionDAG &DAG) const {
7117 if (Subtarget->isThumb1Only())
7122 bool isSEXTLoad = false;
7123 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
7124 Ptr = LD->getBasePtr();
7125 VT = LD->getMemoryVT();
7126 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
7127 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
7128 Ptr = ST->getBasePtr();
7129 VT = ST->getMemoryVT();
7134 bool isLegal = false;
7135 if (Subtarget->isThumb2())
7136 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
7137 Offset, isInc, DAG);
7139 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
7140 Offset, isInc, DAG);
7144 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
7148 /// getPostIndexedAddressParts - returns true by value, base pointer and
7149 /// offset pointer and addressing mode by reference if this node can be
7150 /// combined with a load / store to form a post-indexed load / store.
7151 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
7154 ISD::MemIndexedMode &AM,
7155 SelectionDAG &DAG) const {
7156 if (Subtarget->isThumb1Only())
7161 bool isSEXTLoad = false;
7162 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
7163 VT = LD->getMemoryVT();
7164 Ptr = LD->getBasePtr();
7165 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
7166 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
7167 VT = ST->getMemoryVT();
7168 Ptr = ST->getBasePtr();
7173 bool isLegal = false;
7174 if (Subtarget->isThumb2())
7175 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
7178 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
7184 // Swap base ptr and offset to catch more post-index load / store when
7185 // it's legal. In Thumb2 mode, offset must be an immediate.
7186 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
7187 !Subtarget->isThumb2())
7188 std::swap(Base, Offset);
7190 // Post-indexed load / store update the base pointer.
7195 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
7199 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
7203 const SelectionDAG &DAG,
7204 unsigned Depth) const {
7205 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
7206 switch (Op.getOpcode()) {
7208 case ARMISD::CMOV: {
7209 // Bits are known zero/one if known on the LHS and RHS.
7210 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
7211 if (KnownZero == 0 && KnownOne == 0) return;
7213 APInt KnownZeroRHS, KnownOneRHS;
7214 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
7215 KnownZeroRHS, KnownOneRHS, Depth+1);
7216 KnownZero &= KnownZeroRHS;
7217 KnownOne &= KnownOneRHS;
7223 //===----------------------------------------------------------------------===//
7224 // ARM Inline Assembly Support
7225 //===----------------------------------------------------------------------===//
7227 bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const {
7228 // Looking for "rev" which is V6+.
7229 if (!Subtarget->hasV6Ops())
7232 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
7233 std::string AsmStr = IA->getAsmString();
7234 SmallVector<StringRef, 4> AsmPieces;
7235 SplitString(AsmStr, AsmPieces, ";\n");
7237 switch (AsmPieces.size()) {
7238 default: return false;
7240 AsmStr = AsmPieces[0];
7242 SplitString(AsmStr, AsmPieces, " \t,");
7245 if (AsmPieces.size() == 3 &&
7246 AsmPieces[0] == "rev" && AsmPieces[1] == "$0" && AsmPieces[2] == "$1" &&
7247 IA->getConstraintString().compare(0, 4, "=l,l") == 0) {
7248 const IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
7249 if (Ty && Ty->getBitWidth() == 32)
7250 return IntrinsicLowering::LowerToByteSwap(CI);
7258 /// getConstraintType - Given a constraint letter, return the type of
7259 /// constraint it is for this target.
7260 ARMTargetLowering::ConstraintType
7261 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
7262 if (Constraint.size() == 1) {
7263 switch (Constraint[0]) {
7265 case 'l': return C_RegisterClass;
7266 case 'w': return C_RegisterClass;
7269 return TargetLowering::getConstraintType(Constraint);
7272 /// Examine constraint type and operand type and determine a weight value.
7273 /// This object must already have been set up with the operand type
7274 /// and the current alternative constraint selected.
7275 TargetLowering::ConstraintWeight
7276 ARMTargetLowering::getSingleConstraintMatchWeight(
7277 AsmOperandInfo &info, const char *constraint) const {
7278 ConstraintWeight weight = CW_Invalid;
7279 Value *CallOperandVal = info.CallOperandVal;
7280 // If we don't have a value, we can't do a match,
7281 // but allow it at the lowest weight.
7282 if (CallOperandVal == NULL)
7284 const Type *type = CallOperandVal->getType();
7285 // Look at the constraint type.
7286 switch (*constraint) {
7288 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
7291 if (type->isIntegerTy()) {
7292 if (Subtarget->isThumb())
7293 weight = CW_SpecificReg;
7295 weight = CW_Register;
7299 if (type->isFloatingPointTy())
7300 weight = CW_Register;
7306 std::pair<unsigned, const TargetRegisterClass*>
7307 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
7309 if (Constraint.size() == 1) {
7310 // GCC ARM Constraint Letters
7311 switch (Constraint[0]) {
7313 if (Subtarget->isThumb())
7314 return std::make_pair(0U, ARM::tGPRRegisterClass);
7316 return std::make_pair(0U, ARM::GPRRegisterClass);
7318 return std::make_pair(0U, ARM::GPRRegisterClass);
7321 return std::make_pair(0U, ARM::SPRRegisterClass);
7322 if (VT.getSizeInBits() == 64)
7323 return std::make_pair(0U, ARM::DPRRegisterClass);
7324 if (VT.getSizeInBits() == 128)
7325 return std::make_pair(0U, ARM::QPRRegisterClass);
7329 if (StringRef("{cc}").equals_lower(Constraint))
7330 return std::make_pair(unsigned(ARM::CPSR), ARM::CCRRegisterClass);
7332 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
7335 std::vector<unsigned> ARMTargetLowering::
7336 getRegClassForInlineAsmConstraint(const std::string &Constraint,
7338 if (Constraint.size() != 1)
7339 return std::vector<unsigned>();
7341 switch (Constraint[0]) { // GCC ARM Constraint Letters
7344 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
7345 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
7348 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
7349 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
7350 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
7351 ARM::R12, ARM::LR, 0);
7354 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
7355 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
7356 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
7357 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
7358 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
7359 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
7360 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
7361 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
7362 if (VT.getSizeInBits() == 64)
7363 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
7364 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
7365 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
7366 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
7367 if (VT.getSizeInBits() == 128)
7368 return make_vector<unsigned>(ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
7369 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 0);
7373 return std::vector<unsigned>();
7376 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
7377 /// vector. If it is invalid, don't add anything to Ops.
7378 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
7379 std::string &Constraint,
7380 std::vector<SDValue>&Ops,
7381 SelectionDAG &DAG) const {
7382 SDValue Result(0, 0);
7384 // Currently only support length 1 constraints.
7385 if (Constraint.length() != 1) return;
7387 char ConstraintLetter = Constraint[0];
7388 switch (ConstraintLetter) {
7390 case 'I': case 'J': case 'K': case 'L':
7391 case 'M': case 'N': case 'O':
7392 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
7396 int64_t CVal64 = C->getSExtValue();
7397 int CVal = (int) CVal64;
7398 // None of these constraints allow values larger than 32 bits. Check
7399 // that the value fits in an int.
7403 switch (ConstraintLetter) {
7405 if (Subtarget->isThumb1Only()) {
7406 // This must be a constant between 0 and 255, for ADD
7408 if (CVal >= 0 && CVal <= 255)
7410 } else if (Subtarget->isThumb2()) {
7411 // A constant that can be used as an immediate value in a
7412 // data-processing instruction.
7413 if (ARM_AM::getT2SOImmVal(CVal) != -1)
7416 // A constant that can be used as an immediate value in a
7417 // data-processing instruction.
7418 if (ARM_AM::getSOImmVal(CVal) != -1)
7424 if (Subtarget->isThumb()) { // FIXME thumb2
7425 // This must be a constant between -255 and -1, for negated ADD
7426 // immediates. This can be used in GCC with an "n" modifier that
7427 // prints the negated value, for use with SUB instructions. It is
7428 // not useful otherwise but is implemented for compatibility.
7429 if (CVal >= -255 && CVal <= -1)
7432 // This must be a constant between -4095 and 4095. It is not clear
7433 // what this constraint is intended for. Implemented for
7434 // compatibility with GCC.
7435 if (CVal >= -4095 && CVal <= 4095)
7441 if (Subtarget->isThumb1Only()) {
7442 // A 32-bit value where only one byte has a nonzero value. Exclude
7443 // zero to match GCC. This constraint is used by GCC internally for
7444 // constants that can be loaded with a move/shift combination.
7445 // It is not useful otherwise but is implemented for compatibility.
7446 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
7448 } else if (Subtarget->isThumb2()) {
7449 // A constant whose bitwise inverse can be used as an immediate
7450 // value in a data-processing instruction. This can be used in GCC
7451 // with a "B" modifier that prints the inverted value, for use with
7452 // BIC and MVN instructions. It is not useful otherwise but is
7453 // implemented for compatibility.
7454 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
7457 // A constant whose bitwise inverse can be used as an immediate
7458 // value in a data-processing instruction. This can be used in GCC
7459 // with a "B" modifier that prints the inverted value, for use with
7460 // BIC and MVN instructions. It is not useful otherwise but is
7461 // implemented for compatibility.
7462 if (ARM_AM::getSOImmVal(~CVal) != -1)
7468 if (Subtarget->isThumb1Only()) {
7469 // This must be a constant between -7 and 7,
7470 // for 3-operand ADD/SUB immediate instructions.
7471 if (CVal >= -7 && CVal < 7)
7473 } else if (Subtarget->isThumb2()) {
7474 // A constant whose negation can be used as an immediate value in a
7475 // data-processing instruction. This can be used in GCC with an "n"
7476 // modifier that prints the negated value, for use with SUB
7477 // instructions. It is not useful otherwise but is implemented for
7479 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
7482 // A constant whose negation can be used as an immediate value in a
7483 // data-processing instruction. This can be used in GCC with an "n"
7484 // modifier that prints the negated value, for use with SUB
7485 // instructions. It is not useful otherwise but is implemented for
7487 if (ARM_AM::getSOImmVal(-CVal) != -1)
7493 if (Subtarget->isThumb()) { // FIXME thumb2
7494 // This must be a multiple of 4 between 0 and 1020, for
7495 // ADD sp + immediate.
7496 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
7499 // A power of two or a constant between 0 and 32. This is used in
7500 // GCC for the shift amount on shifted register operands, but it is
7501 // useful in general for any shift amounts.
7502 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
7508 if (Subtarget->isThumb()) { // FIXME thumb2
7509 // This must be a constant between 0 and 31, for shift amounts.
7510 if (CVal >= 0 && CVal <= 31)
7516 if (Subtarget->isThumb()) { // FIXME thumb2
7517 // This must be a multiple of 4 between -508 and 508, for
7518 // ADD/SUB sp = sp + immediate.
7519 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
7524 Result = DAG.getTargetConstant(CVal, Op.getValueType());
7528 if (Result.getNode()) {
7529 Ops.push_back(Result);
7532 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
7536 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
7537 // The ARM target isn't yet aware of offsets.
7541 int ARM::getVFPf32Imm(const APFloat &FPImm) {
7542 APInt Imm = FPImm.bitcastToAPInt();
7543 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
7544 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127
7545 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits
7547 // We can handle 4 bits of mantissa.
7548 // mantissa = (16+UInt(e:f:g:h))/16.
7549 if (Mantissa & 0x7ffff)
7552 if ((Mantissa & 0xf) != Mantissa)
7555 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
7556 if (Exp < -3 || Exp > 4)
7558 Exp = ((Exp+3) & 0x7) ^ 4;
7560 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
7563 int ARM::getVFPf64Imm(const APFloat &FPImm) {
7564 APInt Imm = FPImm.bitcastToAPInt();
7565 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
7566 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
7567 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffLL;
7569 // We can handle 4 bits of mantissa.
7570 // mantissa = (16+UInt(e:f:g:h))/16.
7571 if (Mantissa & 0xffffffffffffLL)
7574 if ((Mantissa & 0xf) != Mantissa)
7577 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
7578 if (Exp < -3 || Exp > 4)
7580 Exp = ((Exp+3) & 0x7) ^ 4;
7582 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
7585 bool ARM::isBitFieldInvertedMask(unsigned v) {
7586 if (v == 0xffffffff)
7588 // there can be 1's on either or both "outsides", all the "inside"
7590 unsigned int lsb = 0, msb = 31;
7591 while (v & (1 << msb)) --msb;
7592 while (v & (1 << lsb)) ++lsb;
7593 for (unsigned int i = lsb; i <= msb; ++i) {
7600 /// isFPImmLegal - Returns true if the target can instruction select the
7601 /// specified FP immediate natively. If false, the legalizer will
7602 /// materialize the FP immediate as a load from a constant pool.
7603 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
7604 if (!Subtarget->hasVFP3())
7607 return ARM::getVFPf32Imm(Imm) != -1;
7609 return ARM::getVFPf64Imm(Imm) != -1;
7613 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
7614 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
7615 /// specified in the intrinsic calls.
7616 bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
7618 unsigned Intrinsic) const {
7619 switch (Intrinsic) {
7620 case Intrinsic::arm_neon_vld1:
7621 case Intrinsic::arm_neon_vld2:
7622 case Intrinsic::arm_neon_vld3:
7623 case Intrinsic::arm_neon_vld4:
7624 case Intrinsic::arm_neon_vld2lane:
7625 case Intrinsic::arm_neon_vld3lane:
7626 case Intrinsic::arm_neon_vld4lane: {
7627 Info.opc = ISD::INTRINSIC_W_CHAIN;
7628 // Conservatively set memVT to the entire set of vectors loaded.
7629 uint64_t NumElts = getTargetData()->getTypeAllocSize(I.getType()) / 8;
7630 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
7631 Info.ptrVal = I.getArgOperand(0);
7633 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
7634 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
7635 Info.vol = false; // volatile loads with NEON intrinsics not supported
7636 Info.readMem = true;
7637 Info.writeMem = false;
7640 case Intrinsic::arm_neon_vst1:
7641 case Intrinsic::arm_neon_vst2:
7642 case Intrinsic::arm_neon_vst3:
7643 case Intrinsic::arm_neon_vst4:
7644 case Intrinsic::arm_neon_vst2lane:
7645 case Intrinsic::arm_neon_vst3lane:
7646 case Intrinsic::arm_neon_vst4lane: {
7647 Info.opc = ISD::INTRINSIC_VOID;
7648 // Conservatively set memVT to the entire set of vectors stored.
7649 unsigned NumElts = 0;
7650 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
7651 const Type *ArgTy = I.getArgOperand(ArgI)->getType();
7652 if (!ArgTy->isVectorTy())
7654 NumElts += getTargetData()->getTypeAllocSize(ArgTy) / 8;
7656 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
7657 Info.ptrVal = I.getArgOperand(0);
7659 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
7660 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
7661 Info.vol = false; // volatile stores with NEON intrinsics not supported
7662 Info.readMem = false;
7663 Info.writeMem = true;
7666 case Intrinsic::arm_strexd: {
7667 Info.opc = ISD::INTRINSIC_W_CHAIN;
7668 Info.memVT = MVT::i64;
7669 Info.ptrVal = I.getArgOperand(2);
7673 Info.readMem = false;
7674 Info.writeMem = true;
7677 case Intrinsic::arm_ldrexd: {
7678 Info.opc = ISD::INTRINSIC_W_CHAIN;
7679 Info.memVT = MVT::i64;
7680 Info.ptrVal = I.getArgOperand(0);
7684 Info.readMem = true;
7685 Info.writeMem = false;