1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "arm-isel"
17 #include "ARMCallingConv.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMISelLowering.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMPerfectShuffle.h"
22 #include "ARMRegisterInfo.h"
23 #include "ARMSubtarget.h"
24 #include "ARMTargetMachine.h"
25 #include "ARMTargetObjectFile.h"
26 #include "MCTargetDesc/ARMAddressingModes.h"
27 #include "llvm/CallingConv.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Function.h"
30 #include "llvm/GlobalValue.h"
31 #include "llvm/Instruction.h"
32 #include "llvm/Instructions.h"
33 #include "llvm/Intrinsics.h"
34 #include "llvm/Type.h"
35 #include "llvm/CodeGen/CallingConvLower.h"
36 #include "llvm/CodeGen/IntrinsicLowering.h"
37 #include "llvm/CodeGen/MachineBasicBlock.h"
38 #include "llvm/CodeGen/MachineFrameInfo.h"
39 #include "llvm/CodeGen/MachineFunction.h"
40 #include "llvm/CodeGen/MachineInstrBuilder.h"
41 #include "llvm/CodeGen/MachineRegisterInfo.h"
42 #include "llvm/CodeGen/PseudoSourceValue.h"
43 #include "llvm/CodeGen/SelectionDAG.h"
44 #include "llvm/MC/MCSectionMachO.h"
45 #include "llvm/Target/TargetOptions.h"
46 #include "llvm/ADT/VectorExtras.h"
47 #include "llvm/ADT/StringExtras.h"
48 #include "llvm/ADT/Statistic.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Support/raw_ostream.h"
56 STATISTIC(NumTailCalls, "Number of tail calls");
57 STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt");
59 // This option should go away when tail calls fully work.
61 EnableARMTailCalls("arm-tail-calls", cl::Hidden,
62 cl::desc("Generate tail calls (TEMPORARY OPTION)."),
66 EnableARMLongCalls("arm-long-calls", cl::Hidden,
67 cl::desc("Generate calls via indirect call instructions"),
71 ARMInterworking("arm-interworking", cl::Hidden,
72 cl::desc("Enable / disable ARM interworking (for debugging only)"),
76 class ARMCCState : public CCState {
78 ARMCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
79 const TargetMachine &TM, SmallVector<CCValAssign, 16> &locs,
80 LLVMContext &C, ParmContext PC)
81 : CCState(CC, isVarArg, MF, TM, locs, C) {
82 assert(((PC == Call) || (PC == Prologue)) &&
83 "ARMCCState users must specify whether their context is call"
84 "or prologue generation.");
90 // The APCS parameter registers.
91 static const unsigned GPRArgRegs[] = {
92 ARM::R0, ARM::R1, ARM::R2, ARM::R3
95 void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
96 EVT PromotedBitwiseVT) {
97 if (VT != PromotedLdStVT) {
98 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
99 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
100 PromotedLdStVT.getSimpleVT());
102 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
103 AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
104 PromotedLdStVT.getSimpleVT());
107 EVT ElemTy = VT.getVectorElementType();
108 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
109 setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
110 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
111 if (ElemTy != MVT::i32) {
112 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
113 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand);
114 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand);
115 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand);
117 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
118 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
119 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
120 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Legal);
121 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
122 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
123 if (VT.isInteger()) {
124 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
125 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
126 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
127 setLoadExtAction(ISD::SEXTLOAD, VT.getSimpleVT(), Expand);
128 setLoadExtAction(ISD::ZEXTLOAD, VT.getSimpleVT(), Expand);
129 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
130 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
131 setTruncStoreAction(VT.getSimpleVT(),
132 (MVT::SimpleValueType)InnerVT, Expand);
134 setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand);
136 // Promote all bit-wise operations.
137 if (VT.isInteger() && VT != PromotedBitwiseVT) {
138 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
139 AddPromotedToType (ISD::AND, VT.getSimpleVT(),
140 PromotedBitwiseVT.getSimpleVT());
141 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
142 AddPromotedToType (ISD::OR, VT.getSimpleVT(),
143 PromotedBitwiseVT.getSimpleVT());
144 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
145 AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
146 PromotedBitwiseVT.getSimpleVT());
149 // Neon does not support vector divide/remainder operations.
150 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
151 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
152 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand);
153 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
154 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
155 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
158 void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
159 addRegisterClass(VT, ARM::DPRRegisterClass);
160 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
163 void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
164 addRegisterClass(VT, ARM::QPRRegisterClass);
165 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
168 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
169 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
170 return new TargetLoweringObjectFileMachO();
172 return new ARMElfTargetObjectFile();
175 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
176 : TargetLowering(TM, createTLOF(TM)) {
177 Subtarget = &TM.getSubtarget<ARMSubtarget>();
178 RegInfo = TM.getRegisterInfo();
179 Itins = TM.getInstrItineraryData();
181 if (Subtarget->isTargetDarwin()) {
182 // Uses VFP for Thumb libfuncs if available.
183 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
184 // Single-precision floating-point arithmetic.
185 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
186 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
187 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
188 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
190 // Double-precision floating-point arithmetic.
191 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
192 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
193 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
194 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
196 // Single-precision comparisons.
197 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
198 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
199 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
200 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
201 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
202 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
203 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
204 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
206 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
207 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
208 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
209 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
210 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
211 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
212 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
213 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
215 // Double-precision comparisons.
216 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
217 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
218 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
219 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
220 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
221 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
222 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
223 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
225 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
226 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
227 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
228 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
229 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
230 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
231 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
232 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
234 // Floating-point to integer conversions.
235 // i64 conversions are done via library routines even when generating VFP
236 // instructions, so use the same ones.
237 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
238 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
239 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
240 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
242 // Conversions between floating types.
243 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
244 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
246 // Integer to floating-point conversions.
247 // i64 conversions are done via library routines even when generating VFP
248 // instructions, so use the same ones.
249 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
250 // e.g., __floatunsidf vs. __floatunssidfvfp.
251 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
252 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
253 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
254 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
258 // These libcalls are not available in 32-bit.
259 setLibcallName(RTLIB::SHL_I128, 0);
260 setLibcallName(RTLIB::SRL_I128, 0);
261 setLibcallName(RTLIB::SRA_I128, 0);
263 if (Subtarget->isAAPCS_ABI()) {
264 // Double-precision floating-point arithmetic helper functions
265 // RTABI chapter 4.1.2, Table 2
266 setLibcallName(RTLIB::ADD_F64, "__aeabi_dadd");
267 setLibcallName(RTLIB::DIV_F64, "__aeabi_ddiv");
268 setLibcallName(RTLIB::MUL_F64, "__aeabi_dmul");
269 setLibcallName(RTLIB::SUB_F64, "__aeabi_dsub");
270 setLibcallCallingConv(RTLIB::ADD_F64, CallingConv::ARM_AAPCS);
271 setLibcallCallingConv(RTLIB::DIV_F64, CallingConv::ARM_AAPCS);
272 setLibcallCallingConv(RTLIB::MUL_F64, CallingConv::ARM_AAPCS);
273 setLibcallCallingConv(RTLIB::SUB_F64, CallingConv::ARM_AAPCS);
275 // Double-precision floating-point comparison helper functions
276 // RTABI chapter 4.1.2, Table 3
277 setLibcallName(RTLIB::OEQ_F64, "__aeabi_dcmpeq");
278 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
279 setLibcallName(RTLIB::UNE_F64, "__aeabi_dcmpeq");
280 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETEQ);
281 setLibcallName(RTLIB::OLT_F64, "__aeabi_dcmplt");
282 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
283 setLibcallName(RTLIB::OLE_F64, "__aeabi_dcmple");
284 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
285 setLibcallName(RTLIB::OGE_F64, "__aeabi_dcmpge");
286 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
287 setLibcallName(RTLIB::OGT_F64, "__aeabi_dcmpgt");
288 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
289 setLibcallName(RTLIB::UO_F64, "__aeabi_dcmpun");
290 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
291 setLibcallName(RTLIB::O_F64, "__aeabi_dcmpun");
292 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
293 setLibcallCallingConv(RTLIB::OEQ_F64, CallingConv::ARM_AAPCS);
294 setLibcallCallingConv(RTLIB::UNE_F64, CallingConv::ARM_AAPCS);
295 setLibcallCallingConv(RTLIB::OLT_F64, CallingConv::ARM_AAPCS);
296 setLibcallCallingConv(RTLIB::OLE_F64, CallingConv::ARM_AAPCS);
297 setLibcallCallingConv(RTLIB::OGE_F64, CallingConv::ARM_AAPCS);
298 setLibcallCallingConv(RTLIB::OGT_F64, CallingConv::ARM_AAPCS);
299 setLibcallCallingConv(RTLIB::UO_F64, CallingConv::ARM_AAPCS);
300 setLibcallCallingConv(RTLIB::O_F64, CallingConv::ARM_AAPCS);
302 // Single-precision floating-point arithmetic helper functions
303 // RTABI chapter 4.1.2, Table 4
304 setLibcallName(RTLIB::ADD_F32, "__aeabi_fadd");
305 setLibcallName(RTLIB::DIV_F32, "__aeabi_fdiv");
306 setLibcallName(RTLIB::MUL_F32, "__aeabi_fmul");
307 setLibcallName(RTLIB::SUB_F32, "__aeabi_fsub");
308 setLibcallCallingConv(RTLIB::ADD_F32, CallingConv::ARM_AAPCS);
309 setLibcallCallingConv(RTLIB::DIV_F32, CallingConv::ARM_AAPCS);
310 setLibcallCallingConv(RTLIB::MUL_F32, CallingConv::ARM_AAPCS);
311 setLibcallCallingConv(RTLIB::SUB_F32, CallingConv::ARM_AAPCS);
313 // Single-precision floating-point comparison helper functions
314 // RTABI chapter 4.1.2, Table 5
315 setLibcallName(RTLIB::OEQ_F32, "__aeabi_fcmpeq");
316 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
317 setLibcallName(RTLIB::UNE_F32, "__aeabi_fcmpeq");
318 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETEQ);
319 setLibcallName(RTLIB::OLT_F32, "__aeabi_fcmplt");
320 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
321 setLibcallName(RTLIB::OLE_F32, "__aeabi_fcmple");
322 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
323 setLibcallName(RTLIB::OGE_F32, "__aeabi_fcmpge");
324 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
325 setLibcallName(RTLIB::OGT_F32, "__aeabi_fcmpgt");
326 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
327 setLibcallName(RTLIB::UO_F32, "__aeabi_fcmpun");
328 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
329 setLibcallName(RTLIB::O_F32, "__aeabi_fcmpun");
330 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
331 setLibcallCallingConv(RTLIB::OEQ_F32, CallingConv::ARM_AAPCS);
332 setLibcallCallingConv(RTLIB::UNE_F32, CallingConv::ARM_AAPCS);
333 setLibcallCallingConv(RTLIB::OLT_F32, CallingConv::ARM_AAPCS);
334 setLibcallCallingConv(RTLIB::OLE_F32, CallingConv::ARM_AAPCS);
335 setLibcallCallingConv(RTLIB::OGE_F32, CallingConv::ARM_AAPCS);
336 setLibcallCallingConv(RTLIB::OGT_F32, CallingConv::ARM_AAPCS);
337 setLibcallCallingConv(RTLIB::UO_F32, CallingConv::ARM_AAPCS);
338 setLibcallCallingConv(RTLIB::O_F32, CallingConv::ARM_AAPCS);
340 // Floating-point to integer conversions.
341 // RTABI chapter 4.1.2, Table 6
342 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz");
343 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz");
344 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz");
345 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz");
346 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz");
347 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz");
348 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz");
349 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz");
350 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I32, CallingConv::ARM_AAPCS);
351 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I32, CallingConv::ARM_AAPCS);
352 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I64, CallingConv::ARM_AAPCS);
353 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::ARM_AAPCS);
354 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I32, CallingConv::ARM_AAPCS);
355 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I32, CallingConv::ARM_AAPCS);
356 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I64, CallingConv::ARM_AAPCS);
357 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::ARM_AAPCS);
359 // Conversions between floating types.
360 // RTABI chapter 4.1.2, Table 7
361 setLibcallName(RTLIB::FPROUND_F64_F32, "__aeabi_d2f");
362 setLibcallName(RTLIB::FPEXT_F32_F64, "__aeabi_f2d");
363 setLibcallCallingConv(RTLIB::FPROUND_F64_F32, CallingConv::ARM_AAPCS);
364 setLibcallCallingConv(RTLIB::FPEXT_F32_F64, CallingConv::ARM_AAPCS);
366 // Integer to floating-point conversions.
367 // RTABI chapter 4.1.2, Table 8
368 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d");
369 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d");
370 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d");
371 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d");
372 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f");
373 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f");
374 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f");
375 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f");
376 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
377 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
378 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
379 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
380 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
381 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
382 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
383 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
385 // Long long helper functions
386 // RTABI chapter 4.2, Table 9
387 setLibcallName(RTLIB::MUL_I64, "__aeabi_lmul");
388 setLibcallName(RTLIB::SDIV_I64, "__aeabi_ldivmod");
389 setLibcallName(RTLIB::UDIV_I64, "__aeabi_uldivmod");
390 setLibcallName(RTLIB::SHL_I64, "__aeabi_llsl");
391 setLibcallName(RTLIB::SRL_I64, "__aeabi_llsr");
392 setLibcallName(RTLIB::SRA_I64, "__aeabi_lasr");
393 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::ARM_AAPCS);
394 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::ARM_AAPCS);
395 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::ARM_AAPCS);
396 setLibcallCallingConv(RTLIB::SHL_I64, CallingConv::ARM_AAPCS);
397 setLibcallCallingConv(RTLIB::SRL_I64, CallingConv::ARM_AAPCS);
398 setLibcallCallingConv(RTLIB::SRA_I64, CallingConv::ARM_AAPCS);
400 // Integer division functions
401 // RTABI chapter 4.3.1
402 setLibcallName(RTLIB::SDIV_I8, "__aeabi_idiv");
403 setLibcallName(RTLIB::SDIV_I16, "__aeabi_idiv");
404 setLibcallName(RTLIB::SDIV_I32, "__aeabi_idiv");
405 setLibcallName(RTLIB::UDIV_I8, "__aeabi_uidiv");
406 setLibcallName(RTLIB::UDIV_I16, "__aeabi_uidiv");
407 setLibcallName(RTLIB::UDIV_I32, "__aeabi_uidiv");
408 setLibcallCallingConv(RTLIB::SDIV_I8, CallingConv::ARM_AAPCS);
409 setLibcallCallingConv(RTLIB::SDIV_I16, CallingConv::ARM_AAPCS);
410 setLibcallCallingConv(RTLIB::SDIV_I32, CallingConv::ARM_AAPCS);
411 setLibcallCallingConv(RTLIB::UDIV_I8, CallingConv::ARM_AAPCS);
412 setLibcallCallingConv(RTLIB::UDIV_I16, CallingConv::ARM_AAPCS);
413 setLibcallCallingConv(RTLIB::UDIV_I32, CallingConv::ARM_AAPCS);
416 // RTABI chapter 4.3.4
417 setLibcallName(RTLIB::MEMCPY, "__aeabi_memcpy");
418 setLibcallName(RTLIB::MEMMOVE, "__aeabi_memmove");
419 setLibcallName(RTLIB::MEMSET, "__aeabi_memset");
422 if (Subtarget->isThumb1Only())
423 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
425 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
426 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
427 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
428 if (!Subtarget->isFPOnlySP())
429 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
431 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
434 if (Subtarget->hasNEON()) {
435 addDRTypeForNEON(MVT::v2f32);
436 addDRTypeForNEON(MVT::v8i8);
437 addDRTypeForNEON(MVT::v4i16);
438 addDRTypeForNEON(MVT::v2i32);
439 addDRTypeForNEON(MVT::v1i64);
441 addQRTypeForNEON(MVT::v4f32);
442 addQRTypeForNEON(MVT::v2f64);
443 addQRTypeForNEON(MVT::v16i8);
444 addQRTypeForNEON(MVT::v8i16);
445 addQRTypeForNEON(MVT::v4i32);
446 addQRTypeForNEON(MVT::v2i64);
448 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
449 // neither Neon nor VFP support any arithmetic operations on it.
450 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
451 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
452 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
453 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
454 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
455 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
456 setOperationAction(ISD::VSETCC, MVT::v2f64, Expand);
457 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
458 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
459 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
460 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
461 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
462 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
463 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
464 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
465 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
466 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
467 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
468 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
469 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
470 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
471 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
472 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
473 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
475 setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand);
477 // Neon does not support some operations on v1i64 and v2i64 types.
478 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
479 // Custom handling for some quad-vector types to detect VMULL.
480 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
481 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
482 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
483 // Custom handling for some vector types to avoid expensive expansions
484 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
485 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
486 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
487 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
488 setOperationAction(ISD::VSETCC, MVT::v1i64, Expand);
489 setOperationAction(ISD::VSETCC, MVT::v2i64, Expand);
490 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
491 // a destination type that is wider than the source.
492 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
493 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
495 setTargetDAGCombine(ISD::INTRINSIC_VOID);
496 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
497 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
498 setTargetDAGCombine(ISD::SHL);
499 setTargetDAGCombine(ISD::SRL);
500 setTargetDAGCombine(ISD::SRA);
501 setTargetDAGCombine(ISD::SIGN_EXTEND);
502 setTargetDAGCombine(ISD::ZERO_EXTEND);
503 setTargetDAGCombine(ISD::ANY_EXTEND);
504 setTargetDAGCombine(ISD::SELECT_CC);
505 setTargetDAGCombine(ISD::BUILD_VECTOR);
506 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
507 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
508 setTargetDAGCombine(ISD::STORE);
509 setTargetDAGCombine(ISD::FP_TO_SINT);
510 setTargetDAGCombine(ISD::FP_TO_UINT);
511 setTargetDAGCombine(ISD::FDIV);
514 computeRegisterProperties();
516 // ARM does not have f32 extending load.
517 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
519 // ARM does not have i1 sign extending load.
520 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
522 // ARM supports all 4 flavors of integer indexed load / store.
523 if (!Subtarget->isThumb1Only()) {
524 for (unsigned im = (unsigned)ISD::PRE_INC;
525 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
526 setIndexedLoadAction(im, MVT::i1, Legal);
527 setIndexedLoadAction(im, MVT::i8, Legal);
528 setIndexedLoadAction(im, MVT::i16, Legal);
529 setIndexedLoadAction(im, MVT::i32, Legal);
530 setIndexedStoreAction(im, MVT::i1, Legal);
531 setIndexedStoreAction(im, MVT::i8, Legal);
532 setIndexedStoreAction(im, MVT::i16, Legal);
533 setIndexedStoreAction(im, MVT::i32, Legal);
537 // i64 operation support.
538 setOperationAction(ISD::MUL, MVT::i64, Expand);
539 setOperationAction(ISD::MULHU, MVT::i32, Expand);
540 if (Subtarget->isThumb1Only()) {
541 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
542 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
544 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
545 || (Subtarget->isThumb2() && !Subtarget->hasThumb2DSP()))
546 setOperationAction(ISD::MULHS, MVT::i32, Expand);
548 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
549 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
550 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
551 setOperationAction(ISD::SRL, MVT::i64, Custom);
552 setOperationAction(ISD::SRA, MVT::i64, Custom);
554 // ARM does not have ROTL.
555 setOperationAction(ISD::ROTL, MVT::i32, Expand);
556 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
557 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
558 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
559 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
561 // Only ARMv6 has BSWAP.
562 if (!Subtarget->hasV6Ops())
563 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
565 // These are expanded into libcalls.
566 if (!Subtarget->hasDivide() || !Subtarget->isThumb2()) {
567 // v7M has a hardware divider
568 setOperationAction(ISD::SDIV, MVT::i32, Expand);
569 setOperationAction(ISD::UDIV, MVT::i32, Expand);
571 setOperationAction(ISD::SREM, MVT::i32, Expand);
572 setOperationAction(ISD::UREM, MVT::i32, Expand);
573 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
574 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
576 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
577 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
578 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
579 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
580 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
582 setOperationAction(ISD::TRAP, MVT::Other, Legal);
584 // Use the default implementation.
585 setOperationAction(ISD::VASTART, MVT::Other, Custom);
586 setOperationAction(ISD::VAARG, MVT::Other, Expand);
587 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
588 setOperationAction(ISD::VAEND, MVT::Other, Expand);
589 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
590 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
591 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
592 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
593 setExceptionPointerRegister(ARM::R0);
594 setExceptionSelectorRegister(ARM::R1);
596 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
597 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
598 // the default expansion.
599 if (Subtarget->hasDataBarrier() ||
600 (Subtarget->hasV6Ops() && !Subtarget->isThumb())) {
601 // membarrier needs custom lowering; the rest are legal and handled
603 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
604 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
606 // Set them all for expansion, which will force libcalls.
607 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
608 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
609 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Expand);
610 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Expand);
611 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
612 setOperationAction(ISD::ATOMIC_SWAP, MVT::i8, Expand);
613 setOperationAction(ISD::ATOMIC_SWAP, MVT::i16, Expand);
614 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
615 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i8, Expand);
616 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i16, Expand);
617 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
618 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Expand);
619 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Expand);
620 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
621 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i8, Expand);
622 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i16, Expand);
623 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
624 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i8, Expand);
625 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i16, Expand);
626 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
627 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i8, Expand);
628 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i16, Expand);
629 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
630 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i8, Expand);
631 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i16, Expand);
632 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
633 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i8, Expand);
634 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i16, Expand);
635 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
636 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i8, Expand);
637 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i16, Expand);
638 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
639 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i8, Expand);
640 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i16, Expand);
641 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
642 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i8, Expand);
643 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i16, Expand);
644 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
645 // Since the libcalls include locking, fold in the fences
646 setShouldFoldAtomicFences(true);
648 // 64-bit versions are always libcalls (for now)
649 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Expand);
650 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Expand);
651 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Expand);
652 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Expand);
653 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Expand);
654 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Expand);
655 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Expand);
656 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Expand);
658 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
660 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
661 if (!Subtarget->hasV6Ops()) {
662 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
663 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
665 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
667 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
668 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
669 // iff target supports vfp2.
670 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
671 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
674 // We want to custom lower some of our intrinsics.
675 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
676 if (Subtarget->isTargetDarwin()) {
677 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
678 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
679 setOperationAction(ISD::EH_SJLJ_DISPATCHSETUP, MVT::Other, Custom);
680 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
683 setOperationAction(ISD::SETCC, MVT::i32, Expand);
684 setOperationAction(ISD::SETCC, MVT::f32, Expand);
685 setOperationAction(ISD::SETCC, MVT::f64, Expand);
686 setOperationAction(ISD::SELECT, MVT::i32, Custom);
687 setOperationAction(ISD::SELECT, MVT::f32, Custom);
688 setOperationAction(ISD::SELECT, MVT::f64, Custom);
689 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
690 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
691 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
693 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
694 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
695 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
696 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
697 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
699 // We don't support sin/cos/fmod/copysign/pow
700 setOperationAction(ISD::FSIN, MVT::f64, Expand);
701 setOperationAction(ISD::FSIN, MVT::f32, Expand);
702 setOperationAction(ISD::FCOS, MVT::f32, Expand);
703 setOperationAction(ISD::FCOS, MVT::f64, Expand);
704 setOperationAction(ISD::FREM, MVT::f64, Expand);
705 setOperationAction(ISD::FREM, MVT::f32, Expand);
706 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
707 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
708 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
710 setOperationAction(ISD::FPOW, MVT::f64, Expand);
711 setOperationAction(ISD::FPOW, MVT::f32, Expand);
713 setOperationAction(ISD::FMA, MVT::f64, Expand);
714 setOperationAction(ISD::FMA, MVT::f32, Expand);
716 // Various VFP goodness
717 if (!UseSoftFloat && !Subtarget->isThumb1Only()) {
718 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
719 if (Subtarget->hasVFP2()) {
720 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
721 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
722 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
723 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
725 // Special handling for half-precision FP.
726 if (!Subtarget->hasFP16()) {
727 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
728 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand);
732 // We have target-specific dag combine patterns for the following nodes:
733 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
734 setTargetDAGCombine(ISD::ADD);
735 setTargetDAGCombine(ISD::SUB);
736 setTargetDAGCombine(ISD::MUL);
738 if (Subtarget->hasV6T2Ops() || Subtarget->hasNEON())
739 setTargetDAGCombine(ISD::OR);
740 if (Subtarget->hasNEON())
741 setTargetDAGCombine(ISD::AND);
743 setStackPointerRegisterToSaveRestore(ARM::SP);
745 if (UseSoftFloat || Subtarget->isThumb1Only() || !Subtarget->hasVFP2())
746 setSchedulingPreference(Sched::RegPressure);
748 setSchedulingPreference(Sched::Hybrid);
750 //// temporary - rewrite interface to use type
751 maxStoresPerMemcpy = maxStoresPerMemcpyOptSize = 1;
753 // On ARM arguments smaller than 4 bytes are extended, so all arguments
754 // are at least 4 bytes aligned.
755 setMinStackArgumentAlignment(4);
757 benefitFromCodePlacementOpt = true;
759 setMinFunctionAlignment(Subtarget->isThumb() ? 1 : 2);
762 // FIXME: It might make sense to define the representative register class as the
763 // nearest super-register that has a non-null superset. For example, DPR_VFP2 is
764 // a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
765 // SPR's representative would be DPR_VFP2. This should work well if register
766 // pressure tracking were modified such that a register use would increment the
767 // pressure of the register class's representative and all of it's super
768 // classes' representatives transitively. We have not implemented this because
769 // of the difficulty prior to coalescing of modeling operand register classes
770 // due to the common occurrence of cross class copies and subregister insertions
772 std::pair<const TargetRegisterClass*, uint8_t>
773 ARMTargetLowering::findRepresentativeClass(EVT VT) const{
774 const TargetRegisterClass *RRC = 0;
776 switch (VT.getSimpleVT().SimpleTy) {
778 return TargetLowering::findRepresentativeClass(VT);
779 // Use DPR as representative register class for all floating point
780 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
781 // the cost is 1 for both f32 and f64.
782 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
783 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
784 RRC = ARM::DPRRegisterClass;
785 // When NEON is used for SP, only half of the register file is available
786 // because operations that define both SP and DP results will be constrained
787 // to the VFP2 class (D0-D15). We currently model this constraint prior to
788 // coalescing by double-counting the SP regs. See the FIXME above.
789 if (Subtarget->useNEONForSinglePrecisionFP())
792 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
793 case MVT::v4f32: case MVT::v2f64:
794 RRC = ARM::DPRRegisterClass;
798 RRC = ARM::DPRRegisterClass;
802 RRC = ARM::DPRRegisterClass;
806 return std::make_pair(RRC, Cost);
809 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
812 case ARMISD::Wrapper: return "ARMISD::Wrapper";
813 case ARMISD::WrapperDYN: return "ARMISD::WrapperDYN";
814 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
815 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
816 case ARMISD::CALL: return "ARMISD::CALL";
817 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
818 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
819 case ARMISD::tCALL: return "ARMISD::tCALL";
820 case ARMISD::BRCOND: return "ARMISD::BRCOND";
821 case ARMISD::BR_JT: return "ARMISD::BR_JT";
822 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
823 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
824 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
825 case ARMISD::CMP: return "ARMISD::CMP";
826 case ARMISD::CMPZ: return "ARMISD::CMPZ";
827 case ARMISD::CMPFP: return "ARMISD::CMPFP";
828 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
829 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
830 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
831 case ARMISD::CMOV: return "ARMISD::CMOV";
833 case ARMISD::RBIT: return "ARMISD::RBIT";
835 case ARMISD::FTOSI: return "ARMISD::FTOSI";
836 case ARMISD::FTOUI: return "ARMISD::FTOUI";
837 case ARMISD::SITOF: return "ARMISD::SITOF";
838 case ARMISD::UITOF: return "ARMISD::UITOF";
840 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
841 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
842 case ARMISD::RRX: return "ARMISD::RRX";
844 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
845 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
847 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
848 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
849 case ARMISD::EH_SJLJ_DISPATCHSETUP:return "ARMISD::EH_SJLJ_DISPATCHSETUP";
851 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
853 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
855 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
857 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER";
858 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
860 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
862 case ARMISD::VCEQ: return "ARMISD::VCEQ";
863 case ARMISD::VCEQZ: return "ARMISD::VCEQZ";
864 case ARMISD::VCGE: return "ARMISD::VCGE";
865 case ARMISD::VCGEZ: return "ARMISD::VCGEZ";
866 case ARMISD::VCLEZ: return "ARMISD::VCLEZ";
867 case ARMISD::VCGEU: return "ARMISD::VCGEU";
868 case ARMISD::VCGT: return "ARMISD::VCGT";
869 case ARMISD::VCGTZ: return "ARMISD::VCGTZ";
870 case ARMISD::VCLTZ: return "ARMISD::VCLTZ";
871 case ARMISD::VCGTU: return "ARMISD::VCGTU";
872 case ARMISD::VTST: return "ARMISD::VTST";
874 case ARMISD::VSHL: return "ARMISD::VSHL";
875 case ARMISD::VSHRs: return "ARMISD::VSHRs";
876 case ARMISD::VSHRu: return "ARMISD::VSHRu";
877 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
878 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
879 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
880 case ARMISD::VSHRN: return "ARMISD::VSHRN";
881 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
882 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
883 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
884 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
885 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
886 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
887 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
888 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
889 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
890 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
891 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
892 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
893 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
894 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
895 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
896 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
897 case ARMISD::VDUP: return "ARMISD::VDUP";
898 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
899 case ARMISD::VEXT: return "ARMISD::VEXT";
900 case ARMISD::VREV64: return "ARMISD::VREV64";
901 case ARMISD::VREV32: return "ARMISD::VREV32";
902 case ARMISD::VREV16: return "ARMISD::VREV16";
903 case ARMISD::VZIP: return "ARMISD::VZIP";
904 case ARMISD::VUZP: return "ARMISD::VUZP";
905 case ARMISD::VTRN: return "ARMISD::VTRN";
906 case ARMISD::VTBL1: return "ARMISD::VTBL1";
907 case ARMISD::VTBL2: return "ARMISD::VTBL2";
908 case ARMISD::VMULLs: return "ARMISD::VMULLs";
909 case ARMISD::VMULLu: return "ARMISD::VMULLu";
910 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
911 case ARMISD::FMAX: return "ARMISD::FMAX";
912 case ARMISD::FMIN: return "ARMISD::FMIN";
913 case ARMISD::BFI: return "ARMISD::BFI";
914 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
915 case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
916 case ARMISD::VBSL: return "ARMISD::VBSL";
917 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
918 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
919 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
920 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD";
921 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD";
922 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD";
923 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD";
924 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD";
925 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD";
926 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD";
927 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD";
928 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD";
929 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD";
930 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD";
931 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD";
932 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD";
933 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD";
934 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD";
935 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD";
936 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD";
940 /// getRegClassFor - Return the register class that should be used for the
941 /// specified value type.
942 TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const {
943 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
944 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
945 // load / store 4 to 8 consecutive D registers.
946 if (Subtarget->hasNEON()) {
947 if (VT == MVT::v4i64)
948 return ARM::QQPRRegisterClass;
949 else if (VT == MVT::v8i64)
950 return ARM::QQQQPRRegisterClass;
952 return TargetLowering::getRegClassFor(VT);
955 // Create a fast isel object.
957 ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
958 return ARM::createFastISel(funcInfo);
961 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
962 /// be used for loads / stores from the global.
963 unsigned ARMTargetLowering::getMaximalGlobalOffset() const {
964 return (Subtarget->isThumb1Only() ? 127 : 4095);
967 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
968 unsigned NumVals = N->getNumValues();
970 return Sched::RegPressure;
972 for (unsigned i = 0; i != NumVals; ++i) {
973 EVT VT = N->getValueType(i);
974 if (VT == MVT::Glue || VT == MVT::Other)
976 if (VT.isFloatingPoint() || VT.isVector())
977 return Sched::Latency;
980 if (!N->isMachineOpcode())
981 return Sched::RegPressure;
983 // Load are scheduled for latency even if there instruction itinerary
985 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
986 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
988 if (MCID.getNumDefs() == 0)
989 return Sched::RegPressure;
990 if (!Itins->isEmpty() &&
991 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
992 return Sched::Latency;
994 return Sched::RegPressure;
997 //===----------------------------------------------------------------------===//
999 //===----------------------------------------------------------------------===//
1001 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
1002 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
1004 default: llvm_unreachable("Unknown condition code!");
1005 case ISD::SETNE: return ARMCC::NE;
1006 case ISD::SETEQ: return ARMCC::EQ;
1007 case ISD::SETGT: return ARMCC::GT;
1008 case ISD::SETGE: return ARMCC::GE;
1009 case ISD::SETLT: return ARMCC::LT;
1010 case ISD::SETLE: return ARMCC::LE;
1011 case ISD::SETUGT: return ARMCC::HI;
1012 case ISD::SETUGE: return ARMCC::HS;
1013 case ISD::SETULT: return ARMCC::LO;
1014 case ISD::SETULE: return ARMCC::LS;
1018 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
1019 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
1020 ARMCC::CondCodes &CondCode2) {
1021 CondCode2 = ARMCC::AL;
1023 default: llvm_unreachable("Unknown FP condition!");
1025 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
1027 case ISD::SETOGT: CondCode = ARMCC::GT; break;
1029 case ISD::SETOGE: CondCode = ARMCC::GE; break;
1030 case ISD::SETOLT: CondCode = ARMCC::MI; break;
1031 case ISD::SETOLE: CondCode = ARMCC::LS; break;
1032 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
1033 case ISD::SETO: CondCode = ARMCC::VC; break;
1034 case ISD::SETUO: CondCode = ARMCC::VS; break;
1035 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
1036 case ISD::SETUGT: CondCode = ARMCC::HI; break;
1037 case ISD::SETUGE: CondCode = ARMCC::PL; break;
1039 case ISD::SETULT: CondCode = ARMCC::LT; break;
1041 case ISD::SETULE: CondCode = ARMCC::LE; break;
1043 case ISD::SETUNE: CondCode = ARMCC::NE; break;
1047 //===----------------------------------------------------------------------===//
1048 // Calling Convention Implementation
1049 //===----------------------------------------------------------------------===//
1051 #include "ARMGenCallingConv.inc"
1053 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1054 /// given CallingConvention value.
1055 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
1057 bool isVarArg) const {
1060 llvm_unreachable("Unsupported calling convention");
1061 case CallingConv::Fast:
1062 if (Subtarget->hasVFP2() && !isVarArg) {
1063 if (!Subtarget->isAAPCS_ABI())
1064 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1065 // For AAPCS ABI targets, just use VFP variant of the calling convention.
1066 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1069 case CallingConv::C: {
1070 // Use target triple & subtarget features to do actual dispatch.
1071 if (!Subtarget->isAAPCS_ABI())
1072 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1073 else if (Subtarget->hasVFP2() &&
1074 FloatABIType == FloatABI::Hard && !isVarArg)
1075 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1076 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1078 case CallingConv::ARM_AAPCS_VFP:
1079 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1080 case CallingConv::ARM_AAPCS:
1081 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1082 case CallingConv::ARM_APCS:
1083 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1087 /// LowerCallResult - Lower the result values of a call into the
1088 /// appropriate copies out of appropriate physical registers.
1090 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1091 CallingConv::ID CallConv, bool isVarArg,
1092 const SmallVectorImpl<ISD::InputArg> &Ins,
1093 DebugLoc dl, SelectionDAG &DAG,
1094 SmallVectorImpl<SDValue> &InVals) const {
1096 // Assign locations to each value returned by this call.
1097 SmallVector<CCValAssign, 16> RVLocs;
1098 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1099 getTargetMachine(), RVLocs, *DAG.getContext(), Call);
1100 CCInfo.AnalyzeCallResult(Ins,
1101 CCAssignFnForNode(CallConv, /* Return*/ true,
1104 // Copy all of the result registers out of their specified physreg.
1105 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1106 CCValAssign VA = RVLocs[i];
1109 if (VA.needsCustom()) {
1110 // Handle f64 or half of a v2f64.
1111 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1113 Chain = Lo.getValue(1);
1114 InFlag = Lo.getValue(2);
1115 VA = RVLocs[++i]; // skip ahead to next loc
1116 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1118 Chain = Hi.getValue(1);
1119 InFlag = Hi.getValue(2);
1120 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1122 if (VA.getLocVT() == MVT::v2f64) {
1123 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1124 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1125 DAG.getConstant(0, MVT::i32));
1127 VA = RVLocs[++i]; // skip ahead to next loc
1128 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1129 Chain = Lo.getValue(1);
1130 InFlag = Lo.getValue(2);
1131 VA = RVLocs[++i]; // skip ahead to next loc
1132 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1133 Chain = Hi.getValue(1);
1134 InFlag = Hi.getValue(2);
1135 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1136 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1137 DAG.getConstant(1, MVT::i32));
1140 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1142 Chain = Val.getValue(1);
1143 InFlag = Val.getValue(2);
1146 switch (VA.getLocInfo()) {
1147 default: llvm_unreachable("Unknown loc info!");
1148 case CCValAssign::Full: break;
1149 case CCValAssign::BCvt:
1150 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1154 InVals.push_back(Val);
1160 /// LowerMemOpCallTo - Store the argument to the stack.
1162 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
1163 SDValue StackPtr, SDValue Arg,
1164 DebugLoc dl, SelectionDAG &DAG,
1165 const CCValAssign &VA,
1166 ISD::ArgFlagsTy Flags) const {
1167 unsigned LocMemOffset = VA.getLocMemOffset();
1168 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1169 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1170 return DAG.getStore(Chain, dl, Arg, PtrOff,
1171 MachinePointerInfo::getStack(LocMemOffset),
1175 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
1176 SDValue Chain, SDValue &Arg,
1177 RegsToPassVector &RegsToPass,
1178 CCValAssign &VA, CCValAssign &NextVA,
1180 SmallVector<SDValue, 8> &MemOpChains,
1181 ISD::ArgFlagsTy Flags) const {
1183 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1184 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1185 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
1187 if (NextVA.isRegLoc())
1188 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
1190 assert(NextVA.isMemLoc());
1191 if (StackPtr.getNode() == 0)
1192 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1194 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
1200 /// LowerCall - Lowering a call into a callseq_start <-
1201 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1204 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1205 CallingConv::ID CallConv, bool isVarArg,
1207 const SmallVectorImpl<ISD::OutputArg> &Outs,
1208 const SmallVectorImpl<SDValue> &OutVals,
1209 const SmallVectorImpl<ISD::InputArg> &Ins,
1210 DebugLoc dl, SelectionDAG &DAG,
1211 SmallVectorImpl<SDValue> &InVals) const {
1212 MachineFunction &MF = DAG.getMachineFunction();
1213 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1214 bool IsSibCall = false;
1215 // Temporarily disable tail calls so things don't break.
1216 if (!EnableARMTailCalls)
1219 // Check if it's really possible to do a tail call.
1220 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1221 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1222 Outs, OutVals, Ins, DAG);
1223 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1224 // detected sibcalls.
1231 // Analyze operands of the call, assigning locations to each operand.
1232 SmallVector<CCValAssign, 16> ArgLocs;
1233 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1234 getTargetMachine(), ArgLocs, *DAG.getContext(), Call);
1235 CCInfo.AnalyzeCallOperands(Outs,
1236 CCAssignFnForNode(CallConv, /* Return*/ false,
1239 // Get a count of how many bytes are to be pushed on the stack.
1240 unsigned NumBytes = CCInfo.getNextStackOffset();
1242 // For tail calls, memory operands are available in our caller's stack.
1246 // Adjust the stack pointer for the new arguments...
1247 // These operations are automatically eliminated by the prolog/epilog pass
1249 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1251 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1253 RegsToPassVector RegsToPass;
1254 SmallVector<SDValue, 8> MemOpChains;
1256 // Walk the register/memloc assignments, inserting copies/loads. In the case
1257 // of tail call optimization, arguments are handled later.
1258 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1260 ++i, ++realArgIdx) {
1261 CCValAssign &VA = ArgLocs[i];
1262 SDValue Arg = OutVals[realArgIdx];
1263 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1264 bool isByVal = Flags.isByVal();
1266 // Promote the value if needed.
1267 switch (VA.getLocInfo()) {
1268 default: llvm_unreachable("Unknown loc info!");
1269 case CCValAssign::Full: break;
1270 case CCValAssign::SExt:
1271 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1273 case CCValAssign::ZExt:
1274 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1276 case CCValAssign::AExt:
1277 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1279 case CCValAssign::BCvt:
1280 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1284 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1285 if (VA.needsCustom()) {
1286 if (VA.getLocVT() == MVT::v2f64) {
1287 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1288 DAG.getConstant(0, MVT::i32));
1289 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1290 DAG.getConstant(1, MVT::i32));
1292 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1293 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1295 VA = ArgLocs[++i]; // skip ahead to next loc
1296 if (VA.isRegLoc()) {
1297 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1298 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1300 assert(VA.isMemLoc());
1302 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1303 dl, DAG, VA, Flags));
1306 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1307 StackPtr, MemOpChains, Flags);
1309 } else if (VA.isRegLoc()) {
1310 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1311 } else if (isByVal) {
1312 assert(VA.isMemLoc());
1313 unsigned offset = 0;
1315 // True if this byval aggregate will be split between registers
1317 if (CCInfo.isFirstByValRegValid()) {
1318 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1320 for (i = 0, j = CCInfo.getFirstByValReg(); j < ARM::R4; i++, j++) {
1321 SDValue Const = DAG.getConstant(4*i, MVT::i32);
1322 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
1323 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
1324 MachinePointerInfo(),
1326 MemOpChains.push_back(Load.getValue(1));
1327 RegsToPass.push_back(std::make_pair(j, Load));
1329 offset = ARM::R4 - CCInfo.getFirstByValReg();
1330 CCInfo.clearFirstByValReg();
1333 unsigned LocMemOffset = VA.getLocMemOffset();
1334 SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset);
1335 SDValue Dst = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr,
1337 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset);
1338 SDValue Src = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg, SrcOffset);
1339 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset,
1341 MemOpChains.push_back(DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode,
1342 Flags.getByValAlign(),
1343 /*isVolatile=*/false,
1344 /*AlwaysInline=*/false,
1345 MachinePointerInfo(0),
1346 MachinePointerInfo(0)));
1348 } else if (!IsSibCall) {
1349 assert(VA.isMemLoc());
1351 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1352 dl, DAG, VA, Flags));
1356 if (!MemOpChains.empty())
1357 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1358 &MemOpChains[0], MemOpChains.size());
1360 // Build a sequence of copy-to-reg nodes chained together with token chain
1361 // and flag operands which copy the outgoing args into the appropriate regs.
1363 // Tail call byval lowering might overwrite argument registers so in case of
1364 // tail call optimization the copies to registers are lowered later.
1366 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1367 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1368 RegsToPass[i].second, InFlag);
1369 InFlag = Chain.getValue(1);
1372 // For tail calls lower the arguments to the 'real' stack slot.
1374 // Force all the incoming stack arguments to be loaded from the stack
1375 // before any new outgoing arguments are stored to the stack, because the
1376 // outgoing stack slots may alias the incoming argument stack slots, and
1377 // the alias isn't otherwise explicit. This is slightly more conservative
1378 // than necessary, because it means that each store effectively depends
1379 // on every argument instead of just those arguments it would clobber.
1381 // Do not flag preceding copytoreg stuff together with the following stuff.
1383 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1384 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1385 RegsToPass[i].second, InFlag);
1386 InFlag = Chain.getValue(1);
1391 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1392 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1393 // node so that legalize doesn't hack it.
1394 bool isDirect = false;
1395 bool isARMFunc = false;
1396 bool isLocalARMFunc = false;
1397 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1399 if (EnableARMLongCalls) {
1400 assert (getTargetMachine().getRelocationModel() == Reloc::Static
1401 && "long-calls with non-static relocation model!");
1402 // Handle a global address or an external symbol. If it's not one of
1403 // those, the target's already in a register, so we don't need to do
1405 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1406 const GlobalValue *GV = G->getGlobal();
1407 // Create a constant pool entry for the callee address
1408 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1409 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1412 // Get the address of the callee into a register
1413 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1414 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1415 Callee = DAG.getLoad(getPointerTy(), dl,
1416 DAG.getEntryNode(), CPAddr,
1417 MachinePointerInfo::getConstantPool(),
1419 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1420 const char *Sym = S->getSymbol();
1422 // Create a constant pool entry for the callee address
1423 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1424 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1425 Sym, ARMPCLabelIndex, 0);
1426 // Get the address of the callee into a register
1427 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1428 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1429 Callee = DAG.getLoad(getPointerTy(), dl,
1430 DAG.getEntryNode(), CPAddr,
1431 MachinePointerInfo::getConstantPool(),
1434 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1435 const GlobalValue *GV = G->getGlobal();
1437 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1438 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
1439 getTargetMachine().getRelocationModel() != Reloc::Static;
1440 isARMFunc = !Subtarget->isThumb() || isStub;
1441 // ARM call to a local ARM function is predicable.
1442 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
1443 // tBX takes a register source operand.
1444 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1445 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1446 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1449 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1450 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1451 Callee = DAG.getLoad(getPointerTy(), dl,
1452 DAG.getEntryNode(), CPAddr,
1453 MachinePointerInfo::getConstantPool(),
1455 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1456 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1457 getPointerTy(), Callee, PICLabel);
1459 // On ELF targets for PIC code, direct calls should go through the PLT
1460 unsigned OpFlags = 0;
1461 if (Subtarget->isTargetELF() &&
1462 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1463 OpFlags = ARMII::MO_PLT;
1464 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
1466 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1468 bool isStub = Subtarget->isTargetDarwin() &&
1469 getTargetMachine().getRelocationModel() != Reloc::Static;
1470 isARMFunc = !Subtarget->isThumb() || isStub;
1471 // tBX takes a register source operand.
1472 const char *Sym = S->getSymbol();
1473 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1474 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1475 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1476 Sym, ARMPCLabelIndex, 4);
1477 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1478 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1479 Callee = DAG.getLoad(getPointerTy(), dl,
1480 DAG.getEntryNode(), CPAddr,
1481 MachinePointerInfo::getConstantPool(),
1483 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1484 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1485 getPointerTy(), Callee, PICLabel);
1487 unsigned OpFlags = 0;
1488 // On ELF targets for PIC code, direct calls should go through the PLT
1489 if (Subtarget->isTargetELF() &&
1490 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1491 OpFlags = ARMII::MO_PLT;
1492 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags);
1496 // FIXME: handle tail calls differently.
1498 if (Subtarget->isThumb()) {
1499 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1500 CallOpc = ARMISD::CALL_NOLINK;
1502 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1504 CallOpc = (isDirect || Subtarget->hasV5TOps())
1505 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
1506 : ARMISD::CALL_NOLINK;
1509 std::vector<SDValue> Ops;
1510 Ops.push_back(Chain);
1511 Ops.push_back(Callee);
1513 // Add argument registers to the end of the list so that they are known live
1515 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1516 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1517 RegsToPass[i].second.getValueType()));
1519 if (InFlag.getNode())
1520 Ops.push_back(InFlag);
1522 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1524 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
1526 // Returns a chain and a flag for retval copy to use.
1527 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
1528 InFlag = Chain.getValue(1);
1530 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1531 DAG.getIntPtrConstant(0, true), InFlag);
1533 InFlag = Chain.getValue(1);
1535 // Handle result values, copying them out of physregs into vregs that we
1537 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1541 /// HandleByVal - Every parameter *after* a byval parameter is passed
1542 /// on the stack. Remember the next parameter register to allocate,
1543 /// and then confiscate the rest of the parameter registers to insure
1546 llvm::ARMTargetLowering::HandleByVal(CCState *State, unsigned &size) const {
1547 unsigned reg = State->AllocateReg(GPRArgRegs, 4);
1548 assert((State->getCallOrPrologue() == Prologue ||
1549 State->getCallOrPrologue() == Call) &&
1550 "unhandled ParmContext");
1551 if ((!State->isFirstByValRegValid()) &&
1552 (ARM::R0 <= reg) && (reg <= ARM::R3)) {
1553 State->setFirstByValReg(reg);
1554 // At a call site, a byval parameter that is split between
1555 // registers and memory needs its size truncated here. In a
1556 // function prologue, such byval parameters are reassembled in
1557 // memory, and are not truncated.
1558 if (State->getCallOrPrologue() == Call) {
1559 unsigned excess = 4 * (ARM::R4 - reg);
1560 assert(size >= excess && "expected larger existing stack allocation");
1564 // Confiscate any remaining parameter registers to preclude their
1565 // assignment to subsequent parameters.
1566 while (State->AllocateReg(GPRArgRegs, 4))
1570 /// MatchingStackOffset - Return true if the given stack call argument is
1571 /// already available in the same position (relatively) of the caller's
1572 /// incoming argument stack.
1574 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1575 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1576 const ARMInstrInfo *TII) {
1577 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
1579 if (Arg.getOpcode() == ISD::CopyFromReg) {
1580 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
1581 if (!TargetRegisterInfo::isVirtualRegister(VR))
1583 MachineInstr *Def = MRI->getVRegDef(VR);
1586 if (!Flags.isByVal()) {
1587 if (!TII->isLoadFromStackSlot(Def, FI))
1592 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
1593 if (Flags.isByVal())
1594 // ByVal argument is passed in as a pointer but it's now being
1595 // dereferenced. e.g.
1596 // define @foo(%struct.X* %A) {
1597 // tail call @bar(%struct.X* byval %A)
1600 SDValue Ptr = Ld->getBasePtr();
1601 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
1604 FI = FINode->getIndex();
1608 assert(FI != INT_MAX);
1609 if (!MFI->isFixedObjectIndex(FI))
1611 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
1614 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1615 /// for tail call optimization. Targets which want to do tail call
1616 /// optimization should implement this function.
1618 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1619 CallingConv::ID CalleeCC,
1621 bool isCalleeStructRet,
1622 bool isCallerStructRet,
1623 const SmallVectorImpl<ISD::OutputArg> &Outs,
1624 const SmallVectorImpl<SDValue> &OutVals,
1625 const SmallVectorImpl<ISD::InputArg> &Ins,
1626 SelectionDAG& DAG) const {
1627 const Function *CallerF = DAG.getMachineFunction().getFunction();
1628 CallingConv::ID CallerCC = CallerF->getCallingConv();
1629 bool CCMatch = CallerCC == CalleeCC;
1631 // Look for obvious safe cases to perform tail call optimization that do not
1632 // require ABI changes. This is what gcc calls sibcall.
1634 // Do not sibcall optimize vararg calls unless the call site is not passing
1636 if (isVarArg && !Outs.empty())
1639 // Also avoid sibcall optimization if either caller or callee uses struct
1640 // return semantics.
1641 if (isCalleeStructRet || isCallerStructRet)
1644 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
1645 // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
1646 // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
1647 // support in the assembler and linker to be used. This would need to be
1648 // fixed to fully support tail calls in Thumb1.
1650 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
1651 // LR. This means if we need to reload LR, it takes an extra instructions,
1652 // which outweighs the value of the tail call; but here we don't know yet
1653 // whether LR is going to be used. Probably the right approach is to
1654 // generate the tail call here and turn it back into CALL/RET in
1655 // emitEpilogue if LR is used.
1657 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
1658 // but we need to make sure there are enough registers; the only valid
1659 // registers are the 4 used for parameters. We don't currently do this
1661 if (Subtarget->isThumb1Only())
1664 // If the calling conventions do not match, then we'd better make sure the
1665 // results are returned in the same way as what the caller expects.
1667 SmallVector<CCValAssign, 16> RVLocs1;
1668 ARMCCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
1669 getTargetMachine(), RVLocs1, *DAG.getContext(), Call);
1670 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
1672 SmallVector<CCValAssign, 16> RVLocs2;
1673 ARMCCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
1674 getTargetMachine(), RVLocs2, *DAG.getContext(), Call);
1675 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
1677 if (RVLocs1.size() != RVLocs2.size())
1679 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
1680 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
1682 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
1684 if (RVLocs1[i].isRegLoc()) {
1685 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
1688 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
1694 // If the callee takes no arguments then go on to check the results of the
1696 if (!Outs.empty()) {
1697 // Check if stack adjustment is needed. For now, do not do this if any
1698 // argument is passed on the stack.
1699 SmallVector<CCValAssign, 16> ArgLocs;
1700 ARMCCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
1701 getTargetMachine(), ArgLocs, *DAG.getContext(), Call);
1702 CCInfo.AnalyzeCallOperands(Outs,
1703 CCAssignFnForNode(CalleeCC, false, isVarArg));
1704 if (CCInfo.getNextStackOffset()) {
1705 MachineFunction &MF = DAG.getMachineFunction();
1707 // Check if the arguments are already laid out in the right way as
1708 // the caller's fixed stack objects.
1709 MachineFrameInfo *MFI = MF.getFrameInfo();
1710 const MachineRegisterInfo *MRI = &MF.getRegInfo();
1711 const ARMInstrInfo *TII =
1712 ((ARMTargetMachine&)getTargetMachine()).getInstrInfo();
1713 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1715 ++i, ++realArgIdx) {
1716 CCValAssign &VA = ArgLocs[i];
1717 EVT RegVT = VA.getLocVT();
1718 SDValue Arg = OutVals[realArgIdx];
1719 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1720 if (VA.getLocInfo() == CCValAssign::Indirect)
1722 if (VA.needsCustom()) {
1723 // f64 and vector types are split into multiple registers or
1724 // register/stack-slot combinations. The types will not match
1725 // the registers; give up on memory f64 refs until we figure
1726 // out what to do about this.
1729 if (!ArgLocs[++i].isRegLoc())
1731 if (RegVT == MVT::v2f64) {
1732 if (!ArgLocs[++i].isRegLoc())
1734 if (!ArgLocs[++i].isRegLoc())
1737 } else if (!VA.isRegLoc()) {
1738 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
1750 ARMTargetLowering::LowerReturn(SDValue Chain,
1751 CallingConv::ID CallConv, bool isVarArg,
1752 const SmallVectorImpl<ISD::OutputArg> &Outs,
1753 const SmallVectorImpl<SDValue> &OutVals,
1754 DebugLoc dl, SelectionDAG &DAG) const {
1756 // CCValAssign - represent the assignment of the return value to a location.
1757 SmallVector<CCValAssign, 16> RVLocs;
1759 // CCState - Info about the registers and stack slots.
1760 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1761 getTargetMachine(), RVLocs, *DAG.getContext(), Call);
1763 // Analyze outgoing return values.
1764 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1767 // If this is the first return lowered for this function, add
1768 // the regs to the liveout set for the function.
1769 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1770 for (unsigned i = 0; i != RVLocs.size(); ++i)
1771 if (RVLocs[i].isRegLoc())
1772 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1777 // Copy the result values into the output registers.
1778 for (unsigned i = 0, realRVLocIdx = 0;
1780 ++i, ++realRVLocIdx) {
1781 CCValAssign &VA = RVLocs[i];
1782 assert(VA.isRegLoc() && "Can only return in registers!");
1784 SDValue Arg = OutVals[realRVLocIdx];
1786 switch (VA.getLocInfo()) {
1787 default: llvm_unreachable("Unknown loc info!");
1788 case CCValAssign::Full: break;
1789 case CCValAssign::BCvt:
1790 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1794 if (VA.needsCustom()) {
1795 if (VA.getLocVT() == MVT::v2f64) {
1796 // Extract the first half and return it in two registers.
1797 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1798 DAG.getConstant(0, MVT::i32));
1799 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
1800 DAG.getVTList(MVT::i32, MVT::i32), Half);
1802 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1803 Flag = Chain.getValue(1);
1804 VA = RVLocs[++i]; // skip ahead to next loc
1805 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1806 HalfGPRs.getValue(1), Flag);
1807 Flag = Chain.getValue(1);
1808 VA = RVLocs[++i]; // skip ahead to next loc
1810 // Extract the 2nd half and fall through to handle it as an f64 value.
1811 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1812 DAG.getConstant(1, MVT::i32));
1814 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1816 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1817 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1818 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1819 Flag = Chain.getValue(1);
1820 VA = RVLocs[++i]; // skip ahead to next loc
1821 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1824 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1826 // Guarantee that all emitted copies are
1827 // stuck together, avoiding something bad.
1828 Flag = Chain.getValue(1);
1833 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1835 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1840 bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N) const {
1841 if (N->getNumValues() != 1)
1843 if (!N->hasNUsesOfValue(1, 0))
1846 unsigned NumCopies = 0;
1848 SDNode *Use = *N->use_begin();
1849 if (Use->getOpcode() == ISD::CopyToReg) {
1850 Copies[NumCopies++] = Use;
1851 } else if (Use->getOpcode() == ARMISD::VMOVRRD) {
1852 // f64 returned in a pair of GPRs.
1853 for (SDNode::use_iterator UI = Use->use_begin(), UE = Use->use_end();
1855 if (UI->getOpcode() != ISD::CopyToReg)
1857 Copies[UI.getUse().getResNo()] = *UI;
1860 } else if (Use->getOpcode() == ISD::BITCAST) {
1861 // f32 returned in a single GPR.
1862 if (!Use->hasNUsesOfValue(1, 0))
1864 Use = *Use->use_begin();
1865 if (Use->getOpcode() != ISD::CopyToReg || !Use->hasNUsesOfValue(1, 0))
1867 Copies[NumCopies++] = Use;
1872 if (NumCopies != 1 && NumCopies != 2)
1875 bool HasRet = false;
1876 for (unsigned i = 0; i < NumCopies; ++i) {
1877 SDNode *Copy = Copies[i];
1878 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1880 if (UI->getOpcode() == ISD::CopyToReg) {
1882 if (Use == Copies[0] || Use == Copies[1])
1886 if (UI->getOpcode() != ARMISD::RET_FLAG)
1895 bool ARMTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1896 if (!EnableARMTailCalls)
1899 if (!CI->isTailCall())
1902 return !Subtarget->isThumb1Only();
1905 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1906 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1907 // one of the above mentioned nodes. It has to be wrapped because otherwise
1908 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1909 // be used to form addressing mode. These wrapped nodes will be selected
1911 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1912 EVT PtrVT = Op.getValueType();
1913 // FIXME there is no actual debug info here
1914 DebugLoc dl = Op.getDebugLoc();
1915 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1917 if (CP->isMachineConstantPoolEntry())
1918 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1919 CP->getAlignment());
1921 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1922 CP->getAlignment());
1923 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1926 unsigned ARMTargetLowering::getJumpTableEncoding() const {
1927 return MachineJumpTableInfo::EK_Inline;
1930 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
1931 SelectionDAG &DAG) const {
1932 MachineFunction &MF = DAG.getMachineFunction();
1933 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1934 unsigned ARMPCLabelIndex = 0;
1935 DebugLoc DL = Op.getDebugLoc();
1936 EVT PtrVT = getPointerTy();
1937 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1938 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1940 if (RelocM == Reloc::Static) {
1941 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
1943 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1944 ARMPCLabelIndex = AFI->createPICLabelUId();
1945 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(BA, ARMPCLabelIndex,
1946 ARMCP::CPBlockAddress,
1948 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1950 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
1951 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
1952 MachinePointerInfo::getConstantPool(),
1954 if (RelocM == Reloc::Static)
1956 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1957 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
1960 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
1962 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1963 SelectionDAG &DAG) const {
1964 DebugLoc dl = GA->getDebugLoc();
1965 EVT PtrVT = getPointerTy();
1966 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1967 MachineFunction &MF = DAG.getMachineFunction();
1968 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1969 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1970 ARMConstantPoolValue *CPV =
1971 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1972 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
1973 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1974 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
1975 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
1976 MachinePointerInfo::getConstantPool(),
1978 SDValue Chain = Argument.getValue(1);
1980 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1981 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
1983 // call __tls_get_addr.
1986 Entry.Node = Argument;
1987 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
1988 Args.push_back(Entry);
1989 // FIXME: is there useful debug info available here?
1990 std::pair<SDValue, SDValue> CallResult =
1991 LowerCallTo(Chain, (Type *) Type::getInt32Ty(*DAG.getContext()),
1992 false, false, false, false,
1993 0, CallingConv::C, false, /*isReturnValueUsed=*/true,
1994 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
1995 return CallResult.first;
1998 // Lower ISD::GlobalTLSAddress using the "initial exec" or
1999 // "local exec" model.
2001 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
2002 SelectionDAG &DAG) const {
2003 const GlobalValue *GV = GA->getGlobal();
2004 DebugLoc dl = GA->getDebugLoc();
2006 SDValue Chain = DAG.getEntryNode();
2007 EVT PtrVT = getPointerTy();
2008 // Get the Thread Pointer
2009 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2011 if (GV->isDeclaration()) {
2012 MachineFunction &MF = DAG.getMachineFunction();
2013 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2014 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2015 // Initial exec model.
2016 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2017 ARMConstantPoolValue *CPV =
2018 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
2019 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF, true);
2020 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2021 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2022 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2023 MachinePointerInfo::getConstantPool(),
2025 Chain = Offset.getValue(1);
2027 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2028 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
2030 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2031 MachinePointerInfo::getConstantPool(),
2035 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMCP::TPOFF);
2036 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2037 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2038 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2039 MachinePointerInfo::getConstantPool(),
2043 // The address of the thread local variable is the add of the thread
2044 // pointer with the offset of the variable.
2045 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
2049 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
2050 // TODO: implement the "local dynamic" model
2051 assert(Subtarget->isTargetELF() &&
2052 "TLS not implemented for non-ELF targets");
2053 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2054 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
2055 // otherwise use the "Local Exec" TLS Model
2056 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
2057 return LowerToTLSGeneralDynamicModel(GA, DAG);
2059 return LowerToTLSExecModels(GA, DAG);
2062 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
2063 SelectionDAG &DAG) const {
2064 EVT PtrVT = getPointerTy();
2065 DebugLoc dl = Op.getDebugLoc();
2066 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2067 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2068 if (RelocM == Reloc::PIC_) {
2069 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
2070 ARMConstantPoolValue *CPV =
2071 new ARMConstantPoolValue(GV, UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
2072 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2073 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2074 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
2076 MachinePointerInfo::getConstantPool(),
2078 SDValue Chain = Result.getValue(1);
2079 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
2080 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
2082 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
2083 MachinePointerInfo::getGOT(), false, false, 0);
2087 // If we have T2 ops, we can materialize the address directly via movt/movw
2088 // pair. This is always cheaper.
2089 if (Subtarget->useMovt()) {
2091 // FIXME: Once remat is capable of dealing with instructions with register
2092 // operands, expand this into two nodes.
2093 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2094 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2096 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
2097 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2098 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2099 MachinePointerInfo::getConstantPool(),
2104 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
2105 SelectionDAG &DAG) const {
2106 EVT PtrVT = getPointerTy();
2107 DebugLoc dl = Op.getDebugLoc();
2108 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2109 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2110 MachineFunction &MF = DAG.getMachineFunction();
2111 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2113 // FIXME: Enable this for static codegen when tool issues are fixed.
2114 if (Subtarget->useMovt() && RelocM != Reloc::Static) {
2116 // FIXME: Once remat is capable of dealing with instructions with register
2117 // operands, expand this into two nodes.
2118 if (RelocM == Reloc::Static)
2119 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2120 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2122 unsigned Wrapper = (RelocM == Reloc::PIC_)
2123 ? ARMISD::WrapperPIC : ARMISD::WrapperDYN;
2124 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT,
2125 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2126 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
2127 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
2128 MachinePointerInfo::getGOT(), false, false, 0);
2132 unsigned ARMPCLabelIndex = 0;
2134 if (RelocM == Reloc::Static) {
2135 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
2137 ARMPCLabelIndex = AFI->createPICLabelUId();
2138 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8);
2139 ARMConstantPoolValue *CPV =
2140 new ARMConstantPoolValue(GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj);
2141 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2143 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2145 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2146 MachinePointerInfo::getConstantPool(),
2148 SDValue Chain = Result.getValue(1);
2150 if (RelocM == Reloc::PIC_) {
2151 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2152 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2155 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
2156 Result = DAG.getLoad(PtrVT, dl, Chain, Result, MachinePointerInfo::getGOT(),
2162 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
2163 SelectionDAG &DAG) const {
2164 assert(Subtarget->isTargetELF() &&
2165 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
2166 MachineFunction &MF = DAG.getMachineFunction();
2167 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2168 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2169 EVT PtrVT = getPointerTy();
2170 DebugLoc dl = Op.getDebugLoc();
2171 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2172 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
2173 "_GLOBAL_OFFSET_TABLE_",
2174 ARMPCLabelIndex, PCAdj);
2175 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2176 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2177 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2178 MachinePointerInfo::getConstantPool(),
2180 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2181 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2185 ARMTargetLowering::LowerEH_SJLJ_DISPATCHSETUP(SDValue Op, SelectionDAG &DAG)
2187 DebugLoc dl = Op.getDebugLoc();
2188 return DAG.getNode(ARMISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other,
2189 Op.getOperand(0), Op.getOperand(1));
2193 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
2194 DebugLoc dl = Op.getDebugLoc();
2195 SDValue Val = DAG.getConstant(0, MVT::i32);
2196 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(0),
2197 Op.getOperand(1), Val);
2201 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
2202 DebugLoc dl = Op.getDebugLoc();
2203 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
2204 Op.getOperand(1), DAG.getConstant(0, MVT::i32));
2208 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
2209 const ARMSubtarget *Subtarget) const {
2210 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2211 DebugLoc dl = Op.getDebugLoc();
2213 default: return SDValue(); // Don't custom lower most intrinsics.
2214 case Intrinsic::arm_thread_pointer: {
2215 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2216 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2218 case Intrinsic::eh_sjlj_lsda: {
2219 MachineFunction &MF = DAG.getMachineFunction();
2220 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2221 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2222 EVT PtrVT = getPointerTy();
2223 DebugLoc dl = Op.getDebugLoc();
2224 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2226 unsigned PCAdj = (RelocM != Reloc::PIC_)
2227 ? 0 : (Subtarget->isThumb() ? 4 : 8);
2228 ARMConstantPoolValue *CPV =
2229 new ARMConstantPoolValue(MF.getFunction(), ARMPCLabelIndex,
2230 ARMCP::CPLSDA, PCAdj);
2231 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2232 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2234 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2235 MachinePointerInfo::getConstantPool(),
2238 if (RelocM == Reloc::PIC_) {
2239 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2240 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2244 case Intrinsic::arm_neon_vmulls:
2245 case Intrinsic::arm_neon_vmullu: {
2246 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
2247 ? ARMISD::VMULLs : ARMISD::VMULLu;
2248 return DAG.getNode(NewOpc, Op.getDebugLoc(), Op.getValueType(),
2249 Op.getOperand(1), Op.getOperand(2));
2254 static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG,
2255 const ARMSubtarget *Subtarget) {
2256 DebugLoc dl = Op.getDebugLoc();
2257 if (!Subtarget->hasDataBarrier()) {
2258 // Some ARMv6 cpus can support data barriers with an mcr instruction.
2259 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
2261 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&
2262 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!");
2263 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2264 DAG.getConstant(0, MVT::i32));
2267 SDValue Op5 = Op.getOperand(5);
2268 bool isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue() != 0;
2269 unsigned isLL = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
2270 unsigned isLS = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
2271 bool isOnlyStoreBarrier = (isLL == 0 && isLS == 0);
2273 ARM_MB::MemBOpt DMBOpt;
2274 if (isDeviceBarrier)
2275 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ST : ARM_MB::SY;
2277 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ISHST : ARM_MB::ISH;
2278 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
2279 DAG.getConstant(DMBOpt, MVT::i32));
2283 static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
2284 const ARMSubtarget *Subtarget) {
2285 // FIXME: handle "fence singlethread" more efficiently.
2286 DebugLoc dl = Op.getDebugLoc();
2287 if (!Subtarget->hasDataBarrier()) {
2288 // Some ARMv6 cpus can support data barriers with an mcr instruction.
2289 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
2291 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&
2292 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!");
2293 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2294 DAG.getConstant(0, MVT::i32));
2297 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
2298 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
2300 ARM_MB::MemBOpt DMBOpt;
2301 if (FenceOrdering == Release)
2302 DMBOpt = ARM_MB::ISHST;
2304 DMBOpt = ARM_MB::ISH;
2305 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
2306 DAG.getConstant(DMBOpt, MVT::i32));
2309 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
2310 const ARMSubtarget *Subtarget) {
2311 // ARM pre v5TE and Thumb1 does not have preload instructions.
2312 if (!(Subtarget->isThumb2() ||
2313 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
2314 // Just preserve the chain.
2315 return Op.getOperand(0);
2317 DebugLoc dl = Op.getDebugLoc();
2318 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
2320 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
2321 // ARMv7 with MP extension has PLDW.
2322 return Op.getOperand(0);
2324 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
2325 if (Subtarget->isThumb()) {
2327 isRead = ~isRead & 1;
2328 isData = ~isData & 1;
2331 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
2332 Op.getOperand(1), DAG.getConstant(isRead, MVT::i32),
2333 DAG.getConstant(isData, MVT::i32));
2336 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
2337 MachineFunction &MF = DAG.getMachineFunction();
2338 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
2340 // vastart just stores the address of the VarArgsFrameIndex slot into the
2341 // memory location argument.
2342 DebugLoc dl = Op.getDebugLoc();
2343 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2344 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2345 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2346 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2347 MachinePointerInfo(SV), false, false, 0);
2351 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
2352 SDValue &Root, SelectionDAG &DAG,
2353 DebugLoc dl) const {
2354 MachineFunction &MF = DAG.getMachineFunction();
2355 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2357 TargetRegisterClass *RC;
2358 if (AFI->isThumb1OnlyFunction())
2359 RC = ARM::tGPRRegisterClass;
2361 RC = ARM::GPRRegisterClass;
2363 // Transform the arguments stored in physical registers into virtual ones.
2364 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2365 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2368 if (NextVA.isMemLoc()) {
2369 MachineFrameInfo *MFI = MF.getFrameInfo();
2370 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
2372 // Create load node to retrieve arguments from the stack.
2373 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2374 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
2375 MachinePointerInfo::getFixedStack(FI),
2378 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2379 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2382 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
2386 ARMTargetLowering::computeRegArea(CCState &CCInfo, MachineFunction &MF,
2387 unsigned &VARegSize, unsigned &VARegSaveSize)
2390 if (CCInfo.isFirstByValRegValid())
2391 NumGPRs = ARM::R4 - CCInfo.getFirstByValReg();
2393 unsigned int firstUnalloced;
2394 firstUnalloced = CCInfo.getFirstUnallocated(GPRArgRegs,
2395 sizeof(GPRArgRegs) /
2396 sizeof(GPRArgRegs[0]));
2397 NumGPRs = (firstUnalloced <= 3) ? (4 - firstUnalloced) : 0;
2400 unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment();
2401 VARegSize = NumGPRs * 4;
2402 VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
2405 // The remaining GPRs hold either the beginning of variable-argument
2406 // data, or the beginning of an aggregate passed by value (usuall
2407 // byval). Either way, we allocate stack slots adjacent to the data
2408 // provided by our caller, and store the unallocated registers there.
2409 // If this is a variadic function, the va_list pointer will begin with
2410 // these values; otherwise, this reassembles a (byval) structure that
2411 // was split between registers and memory.
2413 ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
2414 DebugLoc dl, SDValue &Chain,
2415 unsigned ArgOffset) const {
2416 MachineFunction &MF = DAG.getMachineFunction();
2417 MachineFrameInfo *MFI = MF.getFrameInfo();
2418 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2419 unsigned firstRegToSaveIndex;
2420 if (CCInfo.isFirstByValRegValid())
2421 firstRegToSaveIndex = CCInfo.getFirstByValReg() - ARM::R0;
2423 firstRegToSaveIndex = CCInfo.getFirstUnallocated
2424 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
2427 unsigned VARegSize, VARegSaveSize;
2428 computeRegArea(CCInfo, MF, VARegSize, VARegSaveSize);
2429 if (VARegSaveSize) {
2430 // If this function is vararg, store any remaining integer argument regs
2431 // to their spots on the stack so that they may be loaded by deferencing
2432 // the result of va_next.
2433 AFI->setVarArgsRegSaveSize(VARegSaveSize);
2434 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(VARegSaveSize,
2435 ArgOffset + VARegSaveSize
2438 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(),
2441 SmallVector<SDValue, 4> MemOps;
2442 for (; firstRegToSaveIndex < 4; ++firstRegToSaveIndex) {
2443 TargetRegisterClass *RC;
2444 if (AFI->isThumb1OnlyFunction())
2445 RC = ARM::tGPRRegisterClass;
2447 RC = ARM::GPRRegisterClass;
2449 unsigned VReg = MF.addLiveIn(GPRArgRegs[firstRegToSaveIndex], RC);
2450 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2452 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2453 MachinePointerInfo::getFixedStack(AFI->getVarArgsFrameIndex()),
2455 MemOps.push_back(Store);
2456 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
2457 DAG.getConstant(4, getPointerTy()));
2459 if (!MemOps.empty())
2460 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2461 &MemOps[0], MemOps.size());
2463 // This will point to the next argument passed via stack.
2464 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset, true));
2468 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
2469 CallingConv::ID CallConv, bool isVarArg,
2470 const SmallVectorImpl<ISD::InputArg>
2472 DebugLoc dl, SelectionDAG &DAG,
2473 SmallVectorImpl<SDValue> &InVals)
2475 MachineFunction &MF = DAG.getMachineFunction();
2476 MachineFrameInfo *MFI = MF.getFrameInfo();
2478 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2480 // Assign locations to all of the incoming arguments.
2481 SmallVector<CCValAssign, 16> ArgLocs;
2482 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2483 getTargetMachine(), ArgLocs, *DAG.getContext(), Prologue);
2484 CCInfo.AnalyzeFormalArguments(Ins,
2485 CCAssignFnForNode(CallConv, /* Return*/ false,
2488 SmallVector<SDValue, 16> ArgValues;
2489 int lastInsIndex = -1;
2492 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2493 CCValAssign &VA = ArgLocs[i];
2495 // Arguments stored in registers.
2496 if (VA.isRegLoc()) {
2497 EVT RegVT = VA.getLocVT();
2499 if (VA.needsCustom()) {
2500 // f64 and vector types are split up into multiple registers or
2501 // combinations of registers and stack slots.
2502 if (VA.getLocVT() == MVT::v2f64) {
2503 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
2505 VA = ArgLocs[++i]; // skip ahead to next loc
2507 if (VA.isMemLoc()) {
2508 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
2509 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2510 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
2511 MachinePointerInfo::getFixedStack(FI),
2514 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
2517 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2518 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2519 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
2520 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2521 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
2523 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
2526 TargetRegisterClass *RC;
2528 if (RegVT == MVT::f32)
2529 RC = ARM::SPRRegisterClass;
2530 else if (RegVT == MVT::f64)
2531 RC = ARM::DPRRegisterClass;
2532 else if (RegVT == MVT::v2f64)
2533 RC = ARM::QPRRegisterClass;
2534 else if (RegVT == MVT::i32)
2535 RC = (AFI->isThumb1OnlyFunction() ?
2536 ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
2538 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2540 // Transform the arguments in physical registers into virtual ones.
2541 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2542 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2545 // If this is an 8 or 16-bit value, it is really passed promoted
2546 // to 32 bits. Insert an assert[sz]ext to capture this, then
2547 // truncate to the right size.
2548 switch (VA.getLocInfo()) {
2549 default: llvm_unreachable("Unknown loc info!");
2550 case CCValAssign::Full: break;
2551 case CCValAssign::BCvt:
2552 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2554 case CCValAssign::SExt:
2555 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2556 DAG.getValueType(VA.getValVT()));
2557 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2559 case CCValAssign::ZExt:
2560 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2561 DAG.getValueType(VA.getValVT()));
2562 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2566 InVals.push_back(ArgValue);
2568 } else { // VA.isRegLoc()
2571 assert(VA.isMemLoc());
2572 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
2574 int index = ArgLocs[i].getValNo();
2576 // Some Ins[] entries become multiple ArgLoc[] entries.
2577 // Process them only once.
2578 if (index != lastInsIndex)
2580 ISD::ArgFlagsTy Flags = Ins[index].Flags;
2581 // FIXME: For now, all byval parameter objects are marked mutable.
2582 // This can be changed with more analysis.
2583 // In case of tail call optimization mark all arguments mutable.
2584 // Since they could be overwritten by lowering of arguments in case of
2586 if (Flags.isByVal()) {
2587 unsigned VARegSize, VARegSaveSize;
2588 computeRegArea(CCInfo, MF, VARegSize, VARegSaveSize);
2589 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, 0);
2590 unsigned Bytes = Flags.getByValSize() - VARegSize;
2591 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2592 int FI = MFI->CreateFixedObject(Bytes,
2593 VA.getLocMemOffset(), false);
2594 InVals.push_back(DAG.getFrameIndex(FI, getPointerTy()));
2596 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
2597 VA.getLocMemOffset(), true);
2599 // Create load nodes to retrieve arguments from the stack.
2600 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2601 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2602 MachinePointerInfo::getFixedStack(FI),
2605 lastInsIndex = index;
2612 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, CCInfo.getNextStackOffset());
2617 /// isFloatingPointZero - Return true if this is +0.0.
2618 static bool isFloatingPointZero(SDValue Op) {
2619 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
2620 return CFP->getValueAPF().isPosZero();
2621 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
2622 // Maybe this has already been legalized into the constant pool?
2623 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
2624 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
2625 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
2626 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
2627 return CFP->getValueAPF().isPosZero();
2633 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
2634 /// the given operands.
2636 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2637 SDValue &ARMcc, SelectionDAG &DAG,
2638 DebugLoc dl) const {
2639 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
2640 unsigned C = RHSC->getZExtValue();
2641 if (!isLegalICmpImmediate(C)) {
2642 // Constant does not fit, try adjusting it by one?
2647 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
2648 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
2649 RHS = DAG.getConstant(C-1, MVT::i32);
2654 if (C != 0 && isLegalICmpImmediate(C-1)) {
2655 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
2656 RHS = DAG.getConstant(C-1, MVT::i32);
2661 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
2662 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
2663 RHS = DAG.getConstant(C+1, MVT::i32);
2668 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
2669 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2670 RHS = DAG.getConstant(C+1, MVT::i32);
2677 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2678 ARMISD::NodeType CompareType;
2681 CompareType = ARMISD::CMP;
2686 CompareType = ARMISD::CMPZ;
2689 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2690 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
2693 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
2695 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
2696 DebugLoc dl) const {
2698 if (!isFloatingPointZero(RHS))
2699 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS);
2701 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS);
2702 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
2705 /// duplicateCmp - Glue values can have only one use, so this function
2706 /// duplicates a comparison node.
2708 ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
2709 unsigned Opc = Cmp.getOpcode();
2710 DebugLoc DL = Cmp.getDebugLoc();
2711 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
2712 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
2714 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation");
2715 Cmp = Cmp.getOperand(0);
2716 Opc = Cmp.getOpcode();
2717 if (Opc == ARMISD::CMPFP)
2718 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
2720 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT");
2721 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0));
2723 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
2726 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2727 SDValue Cond = Op.getOperand(0);
2728 SDValue SelectTrue = Op.getOperand(1);
2729 SDValue SelectFalse = Op.getOperand(2);
2730 DebugLoc dl = Op.getDebugLoc();
2734 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
2735 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
2737 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
2738 const ConstantSDNode *CMOVTrue =
2739 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
2740 const ConstantSDNode *CMOVFalse =
2741 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
2743 if (CMOVTrue && CMOVFalse) {
2744 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
2745 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
2749 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
2751 False = SelectFalse;
2752 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
2757 if (True.getNode() && False.getNode()) {
2758 EVT VT = Op.getValueType();
2759 SDValue ARMcc = Cond.getOperand(2);
2760 SDValue CCR = Cond.getOperand(3);
2761 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
2762 assert(True.getValueType() == VT);
2763 return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp);
2768 return DAG.getSelectCC(dl, Cond,
2769 DAG.getConstant(0, Cond.getValueType()),
2770 SelectTrue, SelectFalse, ISD::SETNE);
2773 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
2774 EVT VT = Op.getValueType();
2775 SDValue LHS = Op.getOperand(0);
2776 SDValue RHS = Op.getOperand(1);
2777 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2778 SDValue TrueVal = Op.getOperand(2);
2779 SDValue FalseVal = Op.getOperand(3);
2780 DebugLoc dl = Op.getDebugLoc();
2782 if (LHS.getValueType() == MVT::i32) {
2784 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2785 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2786 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp);
2789 ARMCC::CondCodes CondCode, CondCode2;
2790 FPCCToARMCC(CC, CondCode, CondCode2);
2792 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2793 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2794 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2795 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
2797 if (CondCode2 != ARMCC::AL) {
2798 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32);
2799 // FIXME: Needs another CMP because flag can have but one use.
2800 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
2801 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
2802 Result, TrueVal, ARMcc2, CCR, Cmp2);
2807 /// canChangeToInt - Given the fp compare operand, return true if it is suitable
2808 /// to morph to an integer compare sequence.
2809 static bool canChangeToInt(SDValue Op, bool &SeenZero,
2810 const ARMSubtarget *Subtarget) {
2811 SDNode *N = Op.getNode();
2812 if (!N->hasOneUse())
2813 // Otherwise it requires moving the value from fp to integer registers.
2815 if (!N->getNumValues())
2817 EVT VT = Op.getValueType();
2818 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
2819 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
2820 // vmrs are very slow, e.g. cortex-a8.
2823 if (isFloatingPointZero(Op)) {
2827 return ISD::isNormalLoad(N);
2830 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
2831 if (isFloatingPointZero(Op))
2832 return DAG.getConstant(0, MVT::i32);
2834 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
2835 return DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2836 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(),
2837 Ld->isVolatile(), Ld->isNonTemporal(),
2838 Ld->getAlignment());
2840 llvm_unreachable("Unknown VFP cmp argument!");
2843 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
2844 SDValue &RetVal1, SDValue &RetVal2) {
2845 if (isFloatingPointZero(Op)) {
2846 RetVal1 = DAG.getConstant(0, MVT::i32);
2847 RetVal2 = DAG.getConstant(0, MVT::i32);
2851 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
2852 SDValue Ptr = Ld->getBasePtr();
2853 RetVal1 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2854 Ld->getChain(), Ptr,
2855 Ld->getPointerInfo(),
2856 Ld->isVolatile(), Ld->isNonTemporal(),
2857 Ld->getAlignment());
2859 EVT PtrType = Ptr.getValueType();
2860 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
2861 SDValue NewPtr = DAG.getNode(ISD::ADD, Op.getDebugLoc(),
2862 PtrType, Ptr, DAG.getConstant(4, PtrType));
2863 RetVal2 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2864 Ld->getChain(), NewPtr,
2865 Ld->getPointerInfo().getWithOffset(4),
2866 Ld->isVolatile(), Ld->isNonTemporal(),
2871 llvm_unreachable("Unknown VFP cmp argument!");
2874 /// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
2875 /// f32 and even f64 comparisons to integer ones.
2877 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
2878 SDValue Chain = Op.getOperand(0);
2879 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2880 SDValue LHS = Op.getOperand(2);
2881 SDValue RHS = Op.getOperand(3);
2882 SDValue Dest = Op.getOperand(4);
2883 DebugLoc dl = Op.getDebugLoc();
2885 bool SeenZero = false;
2886 if (canChangeToInt(LHS, SeenZero, Subtarget) &&
2887 canChangeToInt(RHS, SeenZero, Subtarget) &&
2888 // If one of the operand is zero, it's safe to ignore the NaN case since
2889 // we only care about equality comparisons.
2890 (SeenZero || (DAG.isKnownNeverNaN(LHS) && DAG.isKnownNeverNaN(RHS)))) {
2891 // If unsafe fp math optimization is enabled and there are no other uses of
2892 // the CMP operands, and the condition code is EQ or NE, we can optimize it
2893 // to an integer comparison.
2894 if (CC == ISD::SETOEQ)
2896 else if (CC == ISD::SETUNE)
2900 if (LHS.getValueType() == MVT::f32) {
2901 LHS = bitcastf32Toi32(LHS, DAG);
2902 RHS = bitcastf32Toi32(RHS, DAG);
2903 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2904 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2905 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2906 Chain, Dest, ARMcc, CCR, Cmp);
2911 expandf64Toi32(LHS, DAG, LHS1, LHS2);
2912 expandf64Toi32(RHS, DAG, RHS1, RHS2);
2913 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2914 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2915 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
2916 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
2917 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7);
2923 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2924 SDValue Chain = Op.getOperand(0);
2925 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2926 SDValue LHS = Op.getOperand(2);
2927 SDValue RHS = Op.getOperand(3);
2928 SDValue Dest = Op.getOperand(4);
2929 DebugLoc dl = Op.getDebugLoc();
2931 if (LHS.getValueType() == MVT::i32) {
2933 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2934 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2935 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2936 Chain, Dest, ARMcc, CCR, Cmp);
2939 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
2942 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
2943 CC == ISD::SETNE || CC == ISD::SETUNE)) {
2944 SDValue Result = OptimizeVFPBrcond(Op, DAG);
2945 if (Result.getNode())
2949 ARMCC::CondCodes CondCode, CondCode2;
2950 FPCCToARMCC(CC, CondCode, CondCode2);
2952 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2953 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2954 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2955 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
2956 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
2957 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2958 if (CondCode2 != ARMCC::AL) {
2959 ARMcc = DAG.getConstant(CondCode2, MVT::i32);
2960 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
2961 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2966 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
2967 SDValue Chain = Op.getOperand(0);
2968 SDValue Table = Op.getOperand(1);
2969 SDValue Index = Op.getOperand(2);
2970 DebugLoc dl = Op.getDebugLoc();
2972 EVT PTy = getPointerTy();
2973 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
2974 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
2975 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
2976 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
2977 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
2978 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
2979 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2980 if (Subtarget->isThumb2()) {
2981 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
2982 // which does another jump to the destination. This also makes it easier
2983 // to translate it to TBB / TBH later.
2984 // FIXME: This might not work if the function is extremely large.
2985 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
2986 Addr, Op.getOperand(2), JTI, UId);
2988 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2989 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
2990 MachinePointerInfo::getJumpTable(),
2992 Chain = Addr.getValue(1);
2993 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
2994 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2996 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
2997 MachinePointerInfo::getJumpTable(), false, false, 0);
2998 Chain = Addr.getValue(1);
2999 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
3003 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
3004 DebugLoc dl = Op.getDebugLoc();
3007 switch (Op.getOpcode()) {
3009 assert(0 && "Invalid opcode!");
3010 case ISD::FP_TO_SINT:
3011 Opc = ARMISD::FTOSI;
3013 case ISD::FP_TO_UINT:
3014 Opc = ARMISD::FTOUI;
3017 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
3018 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3021 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
3022 EVT VT = Op.getValueType();
3023 DebugLoc dl = Op.getDebugLoc();
3025 EVT OperandVT = Op.getOperand(0).getValueType();
3026 assert(OperandVT == MVT::v4i16 && "Invalid type for custom lowering!");
3027 if (VT != MVT::v4f32)
3028 return DAG.UnrollVectorOp(Op.getNode());
3032 switch (Op.getOpcode()) {
3034 assert(0 && "Invalid opcode!");
3035 case ISD::SINT_TO_FP:
3036 CastOpc = ISD::SIGN_EXTEND;
3037 Opc = ISD::SINT_TO_FP;
3039 case ISD::UINT_TO_FP:
3040 CastOpc = ISD::ZERO_EXTEND;
3041 Opc = ISD::UINT_TO_FP;
3045 Op = DAG.getNode(CastOpc, dl, MVT::v4i32, Op.getOperand(0));
3046 return DAG.getNode(Opc, dl, VT, Op);
3049 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
3050 EVT VT = Op.getValueType();
3052 return LowerVectorINT_TO_FP(Op, DAG);
3054 DebugLoc dl = Op.getDebugLoc();
3057 switch (Op.getOpcode()) {
3059 assert(0 && "Invalid opcode!");
3060 case ISD::SINT_TO_FP:
3061 Opc = ARMISD::SITOF;
3063 case ISD::UINT_TO_FP:
3064 Opc = ARMISD::UITOF;
3068 Op = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0));
3069 return DAG.getNode(Opc, dl, VT, Op);
3072 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
3073 // Implement fcopysign with a fabs and a conditional fneg.
3074 SDValue Tmp0 = Op.getOperand(0);
3075 SDValue Tmp1 = Op.getOperand(1);
3076 DebugLoc dl = Op.getDebugLoc();
3077 EVT VT = Op.getValueType();
3078 EVT SrcVT = Tmp1.getValueType();
3079 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
3080 Tmp0.getOpcode() == ARMISD::VMOVDRR;
3081 bool UseNEON = !InGPR && Subtarget->hasNEON();
3084 // Use VBSL to copy the sign bit.
3085 unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80);
3086 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
3087 DAG.getTargetConstant(EncodedVal, MVT::i32));
3088 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
3090 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT,
3091 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
3092 DAG.getConstant(32, MVT::i32));
3093 else /*if (VT == MVT::f32)*/
3094 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
3095 if (SrcVT == MVT::f32) {
3096 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
3098 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT,
3099 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
3100 DAG.getConstant(32, MVT::i32));
3101 } else if (VT == MVT::f32)
3102 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64,
3103 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
3104 DAG.getConstant(32, MVT::i32));
3105 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
3106 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
3108 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff),
3110 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
3111 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
3112 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
3114 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
3115 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
3116 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
3117 if (VT == MVT::f32) {
3118 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
3119 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
3120 DAG.getConstant(0, MVT::i32));
3122 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
3128 // Bitcast operand 1 to i32.
3129 if (SrcVT == MVT::f64)
3130 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
3131 &Tmp1, 1).getValue(1);
3132 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
3134 // Or in the signbit with integer operations.
3135 SDValue Mask1 = DAG.getConstant(0x80000000, MVT::i32);
3136 SDValue Mask2 = DAG.getConstant(0x7fffffff, MVT::i32);
3137 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
3138 if (VT == MVT::f32) {
3139 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
3140 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
3141 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3142 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
3145 // f64: Or the high part with signbit and then combine two parts.
3146 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
3148 SDValue Lo = Tmp0.getValue(0);
3149 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
3150 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
3151 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
3154 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
3155 MachineFunction &MF = DAG.getMachineFunction();
3156 MachineFrameInfo *MFI = MF.getFrameInfo();
3157 MFI->setReturnAddressIsTaken(true);
3159 EVT VT = Op.getValueType();
3160 DebugLoc dl = Op.getDebugLoc();
3161 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3163 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
3164 SDValue Offset = DAG.getConstant(4, MVT::i32);
3165 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
3166 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
3167 MachinePointerInfo(), false, false, 0);
3170 // Return LR, which contains the return address. Mark it an implicit live-in.
3171 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
3172 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
3175 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
3176 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3177 MFI->setFrameAddressIsTaken(true);
3179 EVT VT = Op.getValueType();
3180 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
3181 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3182 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
3183 ? ARM::R7 : ARM::R11;
3184 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
3186 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
3187 MachinePointerInfo(),
3192 /// ExpandBITCAST - If the target supports VFP, this function is called to
3193 /// expand a bit convert where either the source or destination type is i64 to
3194 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
3195 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
3196 /// vectors), since the legalizer won't know what to do with that.
3197 static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) {
3198 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3199 DebugLoc dl = N->getDebugLoc();
3200 SDValue Op = N->getOperand(0);
3202 // This function is only supposed to be called for i64 types, either as the
3203 // source or destination of the bit convert.
3204 EVT SrcVT = Op.getValueType();
3205 EVT DstVT = N->getValueType(0);
3206 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
3207 "ExpandBITCAST called for non-i64 type");
3209 // Turn i64->f64 into VMOVDRR.
3210 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
3211 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
3212 DAG.getConstant(0, MVT::i32));
3213 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
3214 DAG.getConstant(1, MVT::i32));
3215 return DAG.getNode(ISD::BITCAST, dl, DstVT,
3216 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
3219 // Turn f64->i64 into VMOVRRD.
3220 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
3221 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
3222 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
3223 // Merge the pieces into a single i64 value.
3224 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
3230 /// getZeroVector - Returns a vector of specified type with all zero elements.
3231 /// Zero vectors are used to represent vector negation and in those cases
3232 /// will be implemented with the NEON VNEG instruction. However, VNEG does
3233 /// not support i64 elements, so sometimes the zero vectors will need to be
3234 /// explicitly constructed. Regardless, use a canonical VMOV to create the
3236 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3237 assert(VT.isVector() && "Expected a vector type");
3238 // The canonical modified immediate encoding of a zero vector is....0!
3239 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32);
3240 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
3241 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
3242 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3245 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
3246 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
3247 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
3248 SelectionDAG &DAG) const {
3249 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3250 EVT VT = Op.getValueType();
3251 unsigned VTBits = VT.getSizeInBits();
3252 DebugLoc dl = Op.getDebugLoc();
3253 SDValue ShOpLo = Op.getOperand(0);
3254 SDValue ShOpHi = Op.getOperand(1);
3255 SDValue ShAmt = Op.getOperand(2);
3257 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
3259 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
3261 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
3262 DAG.getConstant(VTBits, MVT::i32), ShAmt);
3263 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
3264 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
3265 DAG.getConstant(VTBits, MVT::i32));
3266 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
3267 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3268 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
3270 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3271 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
3273 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
3274 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
3277 SDValue Ops[2] = { Lo, Hi };
3278 return DAG.getMergeValues(Ops, 2, dl);
3281 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
3282 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
3283 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
3284 SelectionDAG &DAG) const {
3285 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3286 EVT VT = Op.getValueType();
3287 unsigned VTBits = VT.getSizeInBits();
3288 DebugLoc dl = Op.getDebugLoc();
3289 SDValue ShOpLo = Op.getOperand(0);
3290 SDValue ShOpHi = Op.getOperand(1);
3291 SDValue ShAmt = Op.getOperand(2);
3294 assert(Op.getOpcode() == ISD::SHL_PARTS);
3295 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
3296 DAG.getConstant(VTBits, MVT::i32), ShAmt);
3297 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
3298 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
3299 DAG.getConstant(VTBits, MVT::i32));
3300 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
3301 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
3303 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3304 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3305 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
3307 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
3308 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
3311 SDValue Ops[2] = { Lo, Hi };
3312 return DAG.getMergeValues(Ops, 2, dl);
3315 SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
3316 SelectionDAG &DAG) const {
3317 // The rounding mode is in bits 23:22 of the FPSCR.
3318 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
3319 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
3320 // so that the shift + and get folded into a bitfield extract.
3321 DebugLoc dl = Op.getDebugLoc();
3322 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
3323 DAG.getConstant(Intrinsic::arm_get_fpscr,
3325 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
3326 DAG.getConstant(1U << 22, MVT::i32));
3327 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
3328 DAG.getConstant(22, MVT::i32));
3329 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
3330 DAG.getConstant(3, MVT::i32));
3333 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
3334 const ARMSubtarget *ST) {
3335 EVT VT = N->getValueType(0);
3336 DebugLoc dl = N->getDebugLoc();
3338 if (!ST->hasV6T2Ops())
3341 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
3342 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
3345 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
3346 const ARMSubtarget *ST) {
3347 EVT VT = N->getValueType(0);
3348 DebugLoc dl = N->getDebugLoc();
3353 // Lower vector shifts on NEON to use VSHL.
3354 assert(ST->hasNEON() && "unexpected vector shift");
3356 // Left shifts translate directly to the vshiftu intrinsic.
3357 if (N->getOpcode() == ISD::SHL)
3358 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
3359 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
3360 N->getOperand(0), N->getOperand(1));
3362 assert((N->getOpcode() == ISD::SRA ||
3363 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
3365 // NEON uses the same intrinsics for both left and right shifts. For
3366 // right shifts, the shift amounts are negative, so negate the vector of
3368 EVT ShiftVT = N->getOperand(1).getValueType();
3369 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
3370 getZeroVector(ShiftVT, DAG, dl),
3372 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
3373 Intrinsic::arm_neon_vshifts :
3374 Intrinsic::arm_neon_vshiftu);
3375 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
3376 DAG.getConstant(vshiftInt, MVT::i32),
3377 N->getOperand(0), NegatedCount);
3380 static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
3381 const ARMSubtarget *ST) {
3382 EVT VT = N->getValueType(0);
3383 DebugLoc dl = N->getDebugLoc();
3385 // We can get here for a node like i32 = ISD::SHL i32, i64
3389 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
3390 "Unknown shift to lower!");
3392 // We only lower SRA, SRL of 1 here, all others use generic lowering.
3393 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
3394 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
3397 // If we are in thumb mode, we don't have RRX.
3398 if (ST->isThumb1Only()) return SDValue();
3400 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
3401 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
3402 DAG.getConstant(0, MVT::i32));
3403 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
3404 DAG.getConstant(1, MVT::i32));
3406 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
3407 // captures the result into a carry flag.
3408 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
3409 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), &Hi, 1);
3411 // The low part is an ARMISD::RRX operand, which shifts the carry in.
3412 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
3414 // Merge the pieces into a single i64 value.
3415 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
3418 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
3419 SDValue TmpOp0, TmpOp1;
3420 bool Invert = false;
3424 SDValue Op0 = Op.getOperand(0);
3425 SDValue Op1 = Op.getOperand(1);
3426 SDValue CC = Op.getOperand(2);
3427 EVT VT = Op.getValueType();
3428 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
3429 DebugLoc dl = Op.getDebugLoc();
3431 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
3432 switch (SetCCOpcode) {
3433 default: llvm_unreachable("Illegal FP comparison"); break;
3435 case ISD::SETNE: Invert = true; // Fallthrough
3437 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3439 case ISD::SETLT: Swap = true; // Fallthrough
3441 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3443 case ISD::SETLE: Swap = true; // Fallthrough
3445 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3446 case ISD::SETUGE: Swap = true; // Fallthrough
3447 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
3448 case ISD::SETUGT: Swap = true; // Fallthrough
3449 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
3450 case ISD::SETUEQ: Invert = true; // Fallthrough
3452 // Expand this to (OLT | OGT).
3456 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3457 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
3459 case ISD::SETUO: Invert = true; // Fallthrough
3461 // Expand this to (OLT | OGE).
3465 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3466 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
3470 // Integer comparisons.
3471 switch (SetCCOpcode) {
3472 default: llvm_unreachable("Illegal integer comparison"); break;
3473 case ISD::SETNE: Invert = true;
3474 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3475 case ISD::SETLT: Swap = true;
3476 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3477 case ISD::SETLE: Swap = true;
3478 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3479 case ISD::SETULT: Swap = true;
3480 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
3481 case ISD::SETULE: Swap = true;
3482 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
3485 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
3486 if (Opc == ARMISD::VCEQ) {
3489 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
3491 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
3494 // Ignore bitconvert.
3495 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST)
3496 AndOp = AndOp.getOperand(0);
3498 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
3500 Op0 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(0));
3501 Op1 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(1));
3508 std::swap(Op0, Op1);
3510 // If one of the operands is a constant vector zero, attempt to fold the
3511 // comparison to a specialized compare-against-zero form.
3513 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
3515 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) {
3516 if (Opc == ARMISD::VCGE)
3517 Opc = ARMISD::VCLEZ;
3518 else if (Opc == ARMISD::VCGT)
3519 Opc = ARMISD::VCLTZ;
3524 if (SingleOp.getNode()) {
3527 Result = DAG.getNode(ARMISD::VCEQZ, dl, VT, SingleOp); break;
3529 Result = DAG.getNode(ARMISD::VCGEZ, dl, VT, SingleOp); break;
3531 Result = DAG.getNode(ARMISD::VCLEZ, dl, VT, SingleOp); break;
3533 Result = DAG.getNode(ARMISD::VCGTZ, dl, VT, SingleOp); break;
3535 Result = DAG.getNode(ARMISD::VCLTZ, dl, VT, SingleOp); break;
3537 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3540 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3544 Result = DAG.getNOT(dl, Result, VT);
3549 /// isNEONModifiedImm - Check if the specified splat value corresponds to a
3550 /// valid vector constant for a NEON instruction with a "modified immediate"
3551 /// operand (e.g., VMOV). If so, return the encoded value.
3552 static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
3553 unsigned SplatBitSize, SelectionDAG &DAG,
3554 EVT &VT, bool is128Bits, NEONModImmType type) {
3555 unsigned OpCmode, Imm;
3557 // SplatBitSize is set to the smallest size that splats the vector, so a
3558 // zero vector will always have SplatBitSize == 8. However, NEON modified
3559 // immediate instructions others than VMOV do not support the 8-bit encoding
3560 // of a zero vector, and the default encoding of zero is supposed to be the
3565 switch (SplatBitSize) {
3567 if (type != VMOVModImm)
3569 // Any 1-byte value is OK. Op=0, Cmode=1110.
3570 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
3573 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
3577 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
3578 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
3579 if ((SplatBits & ~0xff) == 0) {
3580 // Value = 0x00nn: Op=x, Cmode=100x.
3585 if ((SplatBits & ~0xff00) == 0) {
3586 // Value = 0xnn00: Op=x, Cmode=101x.
3588 Imm = SplatBits >> 8;
3594 // NEON's 32-bit VMOV supports splat values where:
3595 // * only one byte is nonzero, or
3596 // * the least significant byte is 0xff and the second byte is nonzero, or
3597 // * the least significant 2 bytes are 0xff and the third is nonzero.
3598 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
3599 if ((SplatBits & ~0xff) == 0) {
3600 // Value = 0x000000nn: Op=x, Cmode=000x.
3605 if ((SplatBits & ~0xff00) == 0) {
3606 // Value = 0x0000nn00: Op=x, Cmode=001x.
3608 Imm = SplatBits >> 8;
3611 if ((SplatBits & ~0xff0000) == 0) {
3612 // Value = 0x00nn0000: Op=x, Cmode=010x.
3614 Imm = SplatBits >> 16;
3617 if ((SplatBits & ~0xff000000) == 0) {
3618 // Value = 0xnn000000: Op=x, Cmode=011x.
3620 Imm = SplatBits >> 24;
3624 // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC
3625 if (type == OtherModImm) return SDValue();
3627 if ((SplatBits & ~0xffff) == 0 &&
3628 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
3629 // Value = 0x0000nnff: Op=x, Cmode=1100.
3631 Imm = SplatBits >> 8;
3636 if ((SplatBits & ~0xffffff) == 0 &&
3637 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
3638 // Value = 0x00nnffff: Op=x, Cmode=1101.
3640 Imm = SplatBits >> 16;
3641 SplatBits |= 0xffff;
3645 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
3646 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
3647 // VMOV.I32. A (very) minor optimization would be to replicate the value
3648 // and fall through here to test for a valid 64-bit splat. But, then the
3649 // caller would also need to check and handle the change in size.
3653 if (type != VMOVModImm)
3655 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
3656 uint64_t BitMask = 0xff;
3658 unsigned ImmMask = 1;
3660 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
3661 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
3664 } else if ((SplatBits & BitMask) != 0) {
3670 // Op=1, Cmode=1110.
3673 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
3678 llvm_unreachable("unexpected size for isNEONModifiedImm");
3682 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
3683 return DAG.getTargetConstant(EncodedVal, MVT::i32);
3686 static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT,
3687 bool &ReverseVEXT, unsigned &Imm) {
3688 unsigned NumElts = VT.getVectorNumElements();
3689 ReverseVEXT = false;
3691 // Assume that the first shuffle index is not UNDEF. Fail if it is.
3697 // If this is a VEXT shuffle, the immediate value is the index of the first
3698 // element. The other shuffle indices must be the successive elements after
3700 unsigned ExpectedElt = Imm;
3701 for (unsigned i = 1; i < NumElts; ++i) {
3702 // Increment the expected index. If it wraps around, it may still be
3703 // a VEXT but the source vectors must be swapped.
3705 if (ExpectedElt == NumElts * 2) {
3710 if (M[i] < 0) continue; // ignore UNDEF indices
3711 if (ExpectedElt != static_cast<unsigned>(M[i]))
3715 // Adjust the index value if the source operands will be swapped.
3722 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
3723 /// instruction with the specified blocksize. (The order of the elements
3724 /// within each block of the vector is reversed.)
3725 static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT,
3726 unsigned BlockSize) {
3727 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
3728 "Only possible block sizes for VREV are: 16, 32, 64");
3730 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3734 unsigned NumElts = VT.getVectorNumElements();
3735 unsigned BlockElts = M[0] + 1;
3736 // If the first shuffle index is UNDEF, be optimistic.
3738 BlockElts = BlockSize / EltSz;
3740 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
3743 for (unsigned i = 0; i < NumElts; ++i) {
3744 if (M[i] < 0) continue; // ignore UNDEF indices
3745 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
3752 static bool isVTBLMask(const SmallVectorImpl<int> &M, EVT VT) {
3753 // We can handle <8 x i8> vector shuffles. If the index in the mask is out of
3754 // range, then 0 is placed into the resulting vector. So pretty much any mask
3755 // of 8 elements can work here.
3756 return VT == MVT::v8i8 && M.size() == 8;
3759 static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT,
3760 unsigned &WhichResult) {
3761 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3765 unsigned NumElts = VT.getVectorNumElements();
3766 WhichResult = (M[0] == 0 ? 0 : 1);
3767 for (unsigned i = 0; i < NumElts; i += 2) {
3768 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3769 (M[i+1] >= 0 && (unsigned) M[i+1] != i + NumElts + WhichResult))
3775 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
3776 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3777 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
3778 static bool isVTRN_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3779 unsigned &WhichResult) {
3780 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3784 unsigned NumElts = VT.getVectorNumElements();
3785 WhichResult = (M[0] == 0 ? 0 : 1);
3786 for (unsigned i = 0; i < NumElts; i += 2) {
3787 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3788 (M[i+1] >= 0 && (unsigned) M[i+1] != i + WhichResult))
3794 static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT,
3795 unsigned &WhichResult) {
3796 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3800 unsigned NumElts = VT.getVectorNumElements();
3801 WhichResult = (M[0] == 0 ? 0 : 1);
3802 for (unsigned i = 0; i != NumElts; ++i) {
3803 if (M[i] < 0) continue; // ignore UNDEF indices
3804 if ((unsigned) M[i] != 2 * i + WhichResult)
3808 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3809 if (VT.is64BitVector() && EltSz == 32)
3815 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
3816 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3817 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
3818 static bool isVUZP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3819 unsigned &WhichResult) {
3820 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3824 unsigned Half = VT.getVectorNumElements() / 2;
3825 WhichResult = (M[0] == 0 ? 0 : 1);
3826 for (unsigned j = 0; j != 2; ++j) {
3827 unsigned Idx = WhichResult;
3828 for (unsigned i = 0; i != Half; ++i) {
3829 int MIdx = M[i + j * Half];
3830 if (MIdx >= 0 && (unsigned) MIdx != Idx)
3836 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3837 if (VT.is64BitVector() && EltSz == 32)
3843 static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT,
3844 unsigned &WhichResult) {
3845 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3849 unsigned NumElts = VT.getVectorNumElements();
3850 WhichResult = (M[0] == 0 ? 0 : 1);
3851 unsigned Idx = WhichResult * NumElts / 2;
3852 for (unsigned i = 0; i != NumElts; i += 2) {
3853 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3854 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts))
3859 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3860 if (VT.is64BitVector() && EltSz == 32)
3866 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
3867 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3868 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
3869 static bool isVZIP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3870 unsigned &WhichResult) {
3871 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3875 unsigned NumElts = VT.getVectorNumElements();
3876 WhichResult = (M[0] == 0 ? 0 : 1);
3877 unsigned Idx = WhichResult * NumElts / 2;
3878 for (unsigned i = 0; i != NumElts; i += 2) {
3879 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3880 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx))
3885 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3886 if (VT.is64BitVector() && EltSz == 32)
3892 // If N is an integer constant that can be moved into a register in one
3893 // instruction, return an SDValue of such a constant (will become a MOV
3894 // instruction). Otherwise return null.
3895 static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG,
3896 const ARMSubtarget *ST, DebugLoc dl) {
3898 if (!isa<ConstantSDNode>(N))
3900 Val = cast<ConstantSDNode>(N)->getZExtValue();
3902 if (ST->isThumb1Only()) {
3903 if (Val <= 255 || ~Val <= 255)
3904 return DAG.getConstant(Val, MVT::i32);
3906 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1)
3907 return DAG.getConstant(Val, MVT::i32);
3912 // If this is a case we can't handle, return null and let the default
3913 // expansion code take care of it.
3914 SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
3915 const ARMSubtarget *ST) const {
3916 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
3917 DebugLoc dl = Op.getDebugLoc();
3918 EVT VT = Op.getValueType();
3920 APInt SplatBits, SplatUndef;
3921 unsigned SplatBitSize;
3923 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
3924 if (SplatBitSize <= 64) {
3925 // Check if an immediate VMOV works.
3927 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
3928 SplatUndef.getZExtValue(), SplatBitSize,
3929 DAG, VmovVT, VT.is128BitVector(),
3931 if (Val.getNode()) {
3932 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
3933 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3936 // Try an immediate VMVN.
3937 uint64_t NegatedImm = (SplatBits.getZExtValue() ^
3938 ((1LL << SplatBitSize) - 1));
3939 Val = isNEONModifiedImm(NegatedImm,
3940 SplatUndef.getZExtValue(), SplatBitSize,
3941 DAG, VmovVT, VT.is128BitVector(),
3943 if (Val.getNode()) {
3944 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
3945 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3950 // Scan through the operands to see if only one value is used.
3951 unsigned NumElts = VT.getVectorNumElements();
3952 bool isOnlyLowElement = true;
3953 bool usesOnlyOneValue = true;
3954 bool isConstant = true;
3956 for (unsigned i = 0; i < NumElts; ++i) {
3957 SDValue V = Op.getOperand(i);
3958 if (V.getOpcode() == ISD::UNDEF)
3961 isOnlyLowElement = false;
3962 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
3965 if (!Value.getNode())
3967 else if (V != Value)
3968 usesOnlyOneValue = false;
3971 if (!Value.getNode())
3972 return DAG.getUNDEF(VT);
3974 if (isOnlyLowElement)
3975 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
3977 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3979 // Use VDUP for non-constant splats. For f32 constant splats, reduce to
3980 // i32 and try again.
3981 if (usesOnlyOneValue && EltSize <= 32) {
3983 return DAG.getNode(ARMISD::VDUP, dl, VT, Value);
3984 if (VT.getVectorElementType().isFloatingPoint()) {
3985 SmallVector<SDValue, 8> Ops;
3986 for (unsigned i = 0; i < NumElts; ++i)
3987 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32,
3989 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
3990 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], NumElts);
3991 Val = LowerBUILD_VECTOR(Val, DAG, ST);
3993 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
3995 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
3997 return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
4000 // If all elements are constants and the case above didn't get hit, fall back
4001 // to the default expansion, which will generate a load from the constant
4006 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
4008 SDValue shuffle = ReconstructShuffle(Op, DAG);
4009 if (shuffle != SDValue())
4013 // Vectors with 32- or 64-bit elements can be built by directly assigning
4014 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
4015 // will be legalized.
4016 if (EltSize >= 32) {
4017 // Do the expansion with floating-point types, since that is what the VFP
4018 // registers are defined to use, and since i64 is not legal.
4019 EVT EltVT = EVT::getFloatingPointVT(EltSize);
4020 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
4021 SmallVector<SDValue, 8> Ops;
4022 for (unsigned i = 0; i < NumElts; ++i)
4023 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i)));
4024 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
4025 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
4031 // Gather data to see if the operation can be modelled as a
4032 // shuffle in combination with VEXTs.
4033 SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
4034 SelectionDAG &DAG) const {
4035 DebugLoc dl = Op.getDebugLoc();
4036 EVT VT = Op.getValueType();
4037 unsigned NumElts = VT.getVectorNumElements();
4039 SmallVector<SDValue, 2> SourceVecs;
4040 SmallVector<unsigned, 2> MinElts;
4041 SmallVector<unsigned, 2> MaxElts;
4043 for (unsigned i = 0; i < NumElts; ++i) {
4044 SDValue V = Op.getOperand(i);
4045 if (V.getOpcode() == ISD::UNDEF)
4047 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
4048 // A shuffle can only come from building a vector from various
4049 // elements of other vectors.
4053 // Record this extraction against the appropriate vector if possible...
4054 SDValue SourceVec = V.getOperand(0);
4055 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
4056 bool FoundSource = false;
4057 for (unsigned j = 0; j < SourceVecs.size(); ++j) {
4058 if (SourceVecs[j] == SourceVec) {
4059 if (MinElts[j] > EltNo)
4061 if (MaxElts[j] < EltNo)
4068 // Or record a new source if not...
4070 SourceVecs.push_back(SourceVec);
4071 MinElts.push_back(EltNo);
4072 MaxElts.push_back(EltNo);
4076 // Currently only do something sane when at most two source vectors
4078 if (SourceVecs.size() > 2)
4081 SDValue ShuffleSrcs[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT) };
4082 int VEXTOffsets[2] = {0, 0};
4084 // This loop extracts the usage patterns of the source vectors
4085 // and prepares appropriate SDValues for a shuffle if possible.
4086 for (unsigned i = 0; i < SourceVecs.size(); ++i) {
4087 if (SourceVecs[i].getValueType() == VT) {
4088 // No VEXT necessary
4089 ShuffleSrcs[i] = SourceVecs[i];
4092 } else if (SourceVecs[i].getValueType().getVectorNumElements() < NumElts) {
4093 // It probably isn't worth padding out a smaller vector just to
4094 // break it down again in a shuffle.
4098 // Since only 64-bit and 128-bit vectors are legal on ARM and
4099 // we've eliminated the other cases...
4100 assert(SourceVecs[i].getValueType().getVectorNumElements() == 2*NumElts &&
4101 "unexpected vector sizes in ReconstructShuffle");
4103 if (MaxElts[i] - MinElts[i] >= NumElts) {
4104 // Span too large for a VEXT to cope
4108 if (MinElts[i] >= NumElts) {
4109 // The extraction can just take the second half
4110 VEXTOffsets[i] = NumElts;
4111 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4113 DAG.getIntPtrConstant(NumElts));
4114 } else if (MaxElts[i] < NumElts) {
4115 // The extraction can just take the first half
4117 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4119 DAG.getIntPtrConstant(0));
4121 // An actual VEXT is needed
4122 VEXTOffsets[i] = MinElts[i];
4123 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4125 DAG.getIntPtrConstant(0));
4126 SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4128 DAG.getIntPtrConstant(NumElts));
4129 ShuffleSrcs[i] = DAG.getNode(ARMISD::VEXT, dl, VT, VEXTSrc1, VEXTSrc2,
4130 DAG.getConstant(VEXTOffsets[i], MVT::i32));
4134 SmallVector<int, 8> Mask;
4136 for (unsigned i = 0; i < NumElts; ++i) {
4137 SDValue Entry = Op.getOperand(i);
4138 if (Entry.getOpcode() == ISD::UNDEF) {
4143 SDValue ExtractVec = Entry.getOperand(0);
4144 int ExtractElt = cast<ConstantSDNode>(Op.getOperand(i)
4145 .getOperand(1))->getSExtValue();
4146 if (ExtractVec == SourceVecs[0]) {
4147 Mask.push_back(ExtractElt - VEXTOffsets[0]);
4149 Mask.push_back(ExtractElt + NumElts - VEXTOffsets[1]);
4153 // Final check before we try to produce nonsense...
4154 if (isShuffleMaskLegal(Mask, VT))
4155 return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1],
4161 /// isShuffleMaskLegal - Targets can use this to indicate that they only
4162 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
4163 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
4164 /// are assumed to be legal.
4166 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
4168 if (VT.getVectorNumElements() == 4 &&
4169 (VT.is128BitVector() || VT.is64BitVector())) {
4170 unsigned PFIndexes[4];
4171 for (unsigned i = 0; i != 4; ++i) {
4175 PFIndexes[i] = M[i];
4178 // Compute the index in the perfect shuffle table.
4179 unsigned PFTableIndex =
4180 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
4181 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4182 unsigned Cost = (PFEntry >> 30);
4189 unsigned Imm, WhichResult;
4191 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4192 return (EltSize >= 32 ||
4193 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
4194 isVREVMask(M, VT, 64) ||
4195 isVREVMask(M, VT, 32) ||
4196 isVREVMask(M, VT, 16) ||
4197 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
4198 isVTBLMask(M, VT) ||
4199 isVTRNMask(M, VT, WhichResult) ||
4200 isVUZPMask(M, VT, WhichResult) ||
4201 isVZIPMask(M, VT, WhichResult) ||
4202 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
4203 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
4204 isVZIP_v_undef_Mask(M, VT, WhichResult));
4207 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
4208 /// the specified operations to build the shuffle.
4209 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
4210 SDValue RHS, SelectionDAG &DAG,
4212 unsigned OpNum = (PFEntry >> 26) & 0x0F;
4213 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
4214 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
4217 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
4226 OP_VUZPL, // VUZP, left result
4227 OP_VUZPR, // VUZP, right result
4228 OP_VZIPL, // VZIP, left result
4229 OP_VZIPR, // VZIP, right result
4230 OP_VTRNL, // VTRN, left result
4231 OP_VTRNR // VTRN, right result
4234 if (OpNum == OP_COPY) {
4235 if (LHSID == (1*9+2)*9+3) return LHS;
4236 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
4240 SDValue OpLHS, OpRHS;
4241 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
4242 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
4243 EVT VT = OpLHS.getValueType();
4246 default: llvm_unreachable("Unknown shuffle opcode!");
4248 // VREV divides the vector in half and swaps within the half.
4249 if (VT.getVectorElementType() == MVT::i32 ||
4250 VT.getVectorElementType() == MVT::f32)
4251 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
4252 // vrev <4 x i16> -> VREV32
4253 if (VT.getVectorElementType() == MVT::i16)
4254 return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS);
4255 // vrev <4 x i8> -> VREV16
4256 assert(VT.getVectorElementType() == MVT::i8);
4257 return DAG.getNode(ARMISD::VREV16, dl, VT, OpLHS);
4262 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
4263 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
4267 return DAG.getNode(ARMISD::VEXT, dl, VT,
4269 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
4272 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4273 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
4276 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4277 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
4280 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4281 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
4285 static SDValue LowerVECTOR_SHUFFLEv8i8(SDValue Op,
4286 SmallVectorImpl<int> &ShuffleMask,
4287 SelectionDAG &DAG) {
4288 // Check to see if we can use the VTBL instruction.
4289 SDValue V1 = Op.getOperand(0);
4290 SDValue V2 = Op.getOperand(1);
4291 DebugLoc DL = Op.getDebugLoc();
4293 SmallVector<SDValue, 8> VTBLMask;
4294 for (SmallVectorImpl<int>::iterator
4295 I = ShuffleMask.begin(), E = ShuffleMask.end(); I != E; ++I)
4296 VTBLMask.push_back(DAG.getConstant(*I, MVT::i32));
4298 if (V2.getNode()->getOpcode() == ISD::UNDEF)
4299 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1,
4300 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
4303 return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2,
4304 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
4308 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
4309 SDValue V1 = Op.getOperand(0);
4310 SDValue V2 = Op.getOperand(1);
4311 DebugLoc dl = Op.getDebugLoc();
4312 EVT VT = Op.getValueType();
4313 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
4314 SmallVector<int, 8> ShuffleMask;
4316 // Convert shuffles that are directly supported on NEON to target-specific
4317 // DAG nodes, instead of keeping them as shuffles and matching them again
4318 // during code selection. This is more efficient and avoids the possibility
4319 // of inconsistencies between legalization and selection.
4320 // FIXME: floating-point vectors should be canonicalized to integer vectors
4321 // of the same time so that they get CSEd properly.
4322 SVN->getMask(ShuffleMask);
4324 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4325 if (EltSize <= 32) {
4326 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
4327 int Lane = SVN->getSplatIndex();
4328 // If this is undef splat, generate it via "just" vdup, if possible.
4329 if (Lane == -1) Lane = 0;
4331 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4332 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
4334 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
4335 DAG.getConstant(Lane, MVT::i32));
4340 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
4343 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
4344 DAG.getConstant(Imm, MVT::i32));
4347 if (isVREVMask(ShuffleMask, VT, 64))
4348 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
4349 if (isVREVMask(ShuffleMask, VT, 32))
4350 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
4351 if (isVREVMask(ShuffleMask, VT, 16))
4352 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
4354 // Check for Neon shuffles that modify both input vectors in place.
4355 // If both results are used, i.e., if there are two shuffles with the same
4356 // source operands and with masks corresponding to both results of one of
4357 // these operations, DAG memoization will ensure that a single node is
4358 // used for both shuffles.
4359 unsigned WhichResult;
4360 if (isVTRNMask(ShuffleMask, VT, WhichResult))
4361 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4362 V1, V2).getValue(WhichResult);
4363 if (isVUZPMask(ShuffleMask, VT, WhichResult))
4364 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4365 V1, V2).getValue(WhichResult);
4366 if (isVZIPMask(ShuffleMask, VT, WhichResult))
4367 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4368 V1, V2).getValue(WhichResult);
4370 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
4371 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4372 V1, V1).getValue(WhichResult);
4373 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
4374 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4375 V1, V1).getValue(WhichResult);
4376 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
4377 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4378 V1, V1).getValue(WhichResult);
4381 // If the shuffle is not directly supported and it has 4 elements, use
4382 // the PerfectShuffle-generated table to synthesize it from other shuffles.
4383 unsigned NumElts = VT.getVectorNumElements();
4385 unsigned PFIndexes[4];
4386 for (unsigned i = 0; i != 4; ++i) {
4387 if (ShuffleMask[i] < 0)
4390 PFIndexes[i] = ShuffleMask[i];
4393 // Compute the index in the perfect shuffle table.
4394 unsigned PFTableIndex =
4395 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
4396 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4397 unsigned Cost = (PFEntry >> 30);
4400 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
4403 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
4404 if (EltSize >= 32) {
4405 // Do the expansion with floating-point types, since that is what the VFP
4406 // registers are defined to use, and since i64 is not legal.
4407 EVT EltVT = EVT::getFloatingPointVT(EltSize);
4408 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
4409 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1);
4410 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2);
4411 SmallVector<SDValue, 8> Ops;
4412 for (unsigned i = 0; i < NumElts; ++i) {
4413 if (ShuffleMask[i] < 0)
4414 Ops.push_back(DAG.getUNDEF(EltVT));
4416 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
4417 ShuffleMask[i] < (int)NumElts ? V1 : V2,
4418 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
4421 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
4422 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
4425 if (VT == MVT::v8i8) {
4426 SDValue NewOp = LowerVECTOR_SHUFFLEv8i8(Op, ShuffleMask, DAG);
4427 if (NewOp.getNode())
4434 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4435 // EXTRACT_VECTOR_ELT is legal only for immediate indexes.
4436 SDValue Lane = Op.getOperand(1);
4437 if (!isa<ConstantSDNode>(Lane))
4440 SDValue Vec = Op.getOperand(0);
4441 if (Op.getValueType() == MVT::i32 &&
4442 Vec.getValueType().getVectorElementType().getSizeInBits() < 32) {
4443 DebugLoc dl = Op.getDebugLoc();
4444 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
4450 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
4451 // The only time a CONCAT_VECTORS operation can have legal types is when
4452 // two 64-bit vectors are concatenated to a 128-bit vector.
4453 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
4454 "unexpected CONCAT_VECTORS");
4455 DebugLoc dl = Op.getDebugLoc();
4456 SDValue Val = DAG.getUNDEF(MVT::v2f64);
4457 SDValue Op0 = Op.getOperand(0);
4458 SDValue Op1 = Op.getOperand(1);
4459 if (Op0.getOpcode() != ISD::UNDEF)
4460 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
4461 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0),
4462 DAG.getIntPtrConstant(0));
4463 if (Op1.getOpcode() != ISD::UNDEF)
4464 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
4465 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1),
4466 DAG.getIntPtrConstant(1));
4467 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val);
4470 /// isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each
4471 /// element has been zero/sign-extended, depending on the isSigned parameter,
4472 /// from an integer type half its size.
4473 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
4475 // A v2i64 BUILD_VECTOR will have been legalized to a BITCAST from v4i32.
4476 EVT VT = N->getValueType(0);
4477 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) {
4478 SDNode *BVN = N->getOperand(0).getNode();
4479 if (BVN->getValueType(0) != MVT::v4i32 ||
4480 BVN->getOpcode() != ISD::BUILD_VECTOR)
4482 unsigned LoElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
4483 unsigned HiElt = 1 - LoElt;
4484 ConstantSDNode *Lo0 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt));
4485 ConstantSDNode *Hi0 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt));
4486 ConstantSDNode *Lo1 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt+2));
4487 ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2));
4488 if (!Lo0 || !Hi0 || !Lo1 || !Hi1)
4491 if (Hi0->getSExtValue() == Lo0->getSExtValue() >> 32 &&
4492 Hi1->getSExtValue() == Lo1->getSExtValue() >> 32)
4495 if (Hi0->isNullValue() && Hi1->isNullValue())
4501 if (N->getOpcode() != ISD::BUILD_VECTOR)
4504 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
4505 SDNode *Elt = N->getOperand(i).getNode();
4506 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
4507 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4508 unsigned HalfSize = EltSize / 2;
4510 int64_t SExtVal = C->getSExtValue();
4511 if ((SExtVal >> HalfSize) != (SExtVal >> EltSize))
4514 if ((C->getZExtValue() >> HalfSize) != 0)
4525 /// isSignExtended - Check if a node is a vector value that is sign-extended
4526 /// or a constant BUILD_VECTOR with sign-extended elements.
4527 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
4528 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N))
4530 if (isExtendedBUILD_VECTOR(N, DAG, true))
4535 /// isZeroExtended - Check if a node is a vector value that is zero-extended
4536 /// or a constant BUILD_VECTOR with zero-extended elements.
4537 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
4538 if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N))
4540 if (isExtendedBUILD_VECTOR(N, DAG, false))
4545 /// SkipExtension - For a node that is a SIGN_EXTEND, ZERO_EXTEND, extending
4546 /// load, or BUILD_VECTOR with extended elements, return the unextended value.
4547 static SDValue SkipExtension(SDNode *N, SelectionDAG &DAG) {
4548 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
4549 return N->getOperand(0);
4550 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
4551 return DAG.getLoad(LD->getMemoryVT(), N->getDebugLoc(), LD->getChain(),
4552 LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(),
4553 LD->isNonTemporal(), LD->getAlignment());
4554 // Otherwise, the value must be a BUILD_VECTOR. For v2i64, it will
4555 // have been legalized as a BITCAST from v4i32.
4556 if (N->getOpcode() == ISD::BITCAST) {
4557 SDNode *BVN = N->getOperand(0).getNode();
4558 assert(BVN->getOpcode() == ISD::BUILD_VECTOR &&
4559 BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR");
4560 unsigned LowElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
4561 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), MVT::v2i32,
4562 BVN->getOperand(LowElt), BVN->getOperand(LowElt+2));
4564 // Construct a new BUILD_VECTOR with elements truncated to half the size.
4565 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
4566 EVT VT = N->getValueType(0);
4567 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
4568 unsigned NumElts = VT.getVectorNumElements();
4569 MVT TruncVT = MVT::getIntegerVT(EltSize);
4570 SmallVector<SDValue, 8> Ops;
4571 for (unsigned i = 0; i != NumElts; ++i) {
4572 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
4573 const APInt &CInt = C->getAPIntValue();
4574 Ops.push_back(DAG.getConstant(CInt.trunc(EltSize), TruncVT));
4576 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
4577 MVT::getVectorVT(TruncVT, NumElts), Ops.data(), NumElts);
4580 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
4581 unsigned Opcode = N->getOpcode();
4582 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
4583 SDNode *N0 = N->getOperand(0).getNode();
4584 SDNode *N1 = N->getOperand(1).getNode();
4585 return N0->hasOneUse() && N1->hasOneUse() &&
4586 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
4591 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
4592 unsigned Opcode = N->getOpcode();
4593 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
4594 SDNode *N0 = N->getOperand(0).getNode();
4595 SDNode *N1 = N->getOperand(1).getNode();
4596 return N0->hasOneUse() && N1->hasOneUse() &&
4597 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
4602 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
4603 // Multiplications are only custom-lowered for 128-bit vectors so that
4604 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
4605 EVT VT = Op.getValueType();
4606 assert(VT.is128BitVector() && "unexpected type for custom-lowering ISD::MUL");
4607 SDNode *N0 = Op.getOperand(0).getNode();
4608 SDNode *N1 = Op.getOperand(1).getNode();
4609 unsigned NewOpc = 0;
4611 bool isN0SExt = isSignExtended(N0, DAG);
4612 bool isN1SExt = isSignExtended(N1, DAG);
4613 if (isN0SExt && isN1SExt)
4614 NewOpc = ARMISD::VMULLs;
4616 bool isN0ZExt = isZeroExtended(N0, DAG);
4617 bool isN1ZExt = isZeroExtended(N1, DAG);
4618 if (isN0ZExt && isN1ZExt)
4619 NewOpc = ARMISD::VMULLu;
4620 else if (isN1SExt || isN1ZExt) {
4621 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
4622 // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
4623 if (isN1SExt && isAddSubSExt(N0, DAG)) {
4624 NewOpc = ARMISD::VMULLs;
4626 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
4627 NewOpc = ARMISD::VMULLu;
4629 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
4631 NewOpc = ARMISD::VMULLu;
4637 if (VT == MVT::v2i64)
4638 // Fall through to expand this. It is not legal.
4641 // Other vector multiplications are legal.
4646 // Legalize to a VMULL instruction.
4647 DebugLoc DL = Op.getDebugLoc();
4649 SDValue Op1 = SkipExtension(N1, DAG);
4651 Op0 = SkipExtension(N0, DAG);
4652 assert(Op0.getValueType().is64BitVector() &&
4653 Op1.getValueType().is64BitVector() &&
4654 "unexpected types for extended operands to VMULL");
4655 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
4658 // Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during
4659 // isel lowering to take advantage of no-stall back to back vmul + vmla.
4666 SDValue N00 = SkipExtension(N0->getOperand(0).getNode(), DAG);
4667 SDValue N01 = SkipExtension(N0->getOperand(1).getNode(), DAG);
4668 EVT Op1VT = Op1.getValueType();
4669 return DAG.getNode(N0->getOpcode(), DL, VT,
4670 DAG.getNode(NewOpc, DL, VT,
4671 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
4672 DAG.getNode(NewOpc, DL, VT,
4673 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
4677 LowerSDIV_v4i8(SDValue X, SDValue Y, DebugLoc dl, SelectionDAG &DAG) {
4679 // float4 xf = vcvt_f32_s32(vmovl_s16(a.lo));
4680 // float4 yf = vcvt_f32_s32(vmovl_s16(b.lo));
4681 X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X);
4682 Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y);
4683 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X);
4684 Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y);
4685 // Get reciprocal estimate.
4686 // float4 recip = vrecpeq_f32(yf);
4687 Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4688 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), Y);
4689 // Because char has a smaller range than uchar, we can actually get away
4690 // without any newton steps. This requires that we use a weird bias
4691 // of 0xb000, however (again, this has been exhaustively tested).
4692 // float4 result = as_float4(as_int4(xf*recip) + 0xb000);
4693 X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y);
4694 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X);
4695 Y = DAG.getConstant(0xb000, MVT::i32);
4696 Y = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Y, Y, Y, Y);
4697 X = DAG.getNode(ISD::ADD, dl, MVT::v4i32, X, Y);
4698 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X);
4699 // Convert back to short.
4700 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X);
4701 X = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, X);
4706 LowerSDIV_v4i16(SDValue N0, SDValue N1, DebugLoc dl, SelectionDAG &DAG) {
4708 // Convert to float.
4709 // float4 yf = vcvt_f32_s32(vmovl_s16(y));
4710 // float4 xf = vcvt_f32_s32(vmovl_s16(x));
4711 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0);
4712 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1);
4713 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
4714 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
4716 // Use reciprocal estimate and one refinement step.
4717 // float4 recip = vrecpeq_f32(yf);
4718 // recip *= vrecpsq_f32(yf, recip);
4719 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4720 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1);
4721 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4722 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
4724 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
4725 // Because short has a smaller range than ushort, we can actually get away
4726 // with only a single newton step. This requires that we use a weird bias
4727 // of 89, however (again, this has been exhaustively tested).
4728 // float4 result = as_float4(as_int4(xf*recip) + 0x89);
4729 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
4730 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
4731 N1 = DAG.getConstant(0x89, MVT::i32);
4732 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
4733 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
4734 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
4735 // Convert back to integer and return.
4736 // return vmovn_s32(vcvt_s32_f32(result));
4737 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
4738 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
4742 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
4743 EVT VT = Op.getValueType();
4744 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
4745 "unexpected type for custom-lowering ISD::SDIV");
4747 DebugLoc dl = Op.getDebugLoc();
4748 SDValue N0 = Op.getOperand(0);
4749 SDValue N1 = Op.getOperand(1);
4752 if (VT == MVT::v8i8) {
4753 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0);
4754 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1);
4756 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4757 DAG.getIntPtrConstant(4));
4758 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4759 DAG.getIntPtrConstant(4));
4760 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4761 DAG.getIntPtrConstant(0));
4762 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4763 DAG.getIntPtrConstant(0));
4765 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16
4766 N2 = LowerSDIV_v4i8(N2, N3, dl, DAG); // v4i16
4768 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
4769 N0 = LowerCONCAT_VECTORS(N0, DAG);
4771 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0);
4774 return LowerSDIV_v4i16(N0, N1, dl, DAG);
4777 static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG) {
4778 EVT VT = Op.getValueType();
4779 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
4780 "unexpected type for custom-lowering ISD::UDIV");
4782 DebugLoc dl = Op.getDebugLoc();
4783 SDValue N0 = Op.getOperand(0);
4784 SDValue N1 = Op.getOperand(1);
4787 if (VT == MVT::v8i8) {
4788 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0);
4789 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1);
4791 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4792 DAG.getIntPtrConstant(4));
4793 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4794 DAG.getIntPtrConstant(4));
4795 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4796 DAG.getIntPtrConstant(0));
4797 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4798 DAG.getIntPtrConstant(0));
4800 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16
4801 N2 = LowerSDIV_v4i16(N2, N3, dl, DAG); // v4i16
4803 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
4804 N0 = LowerCONCAT_VECTORS(N0, DAG);
4806 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8,
4807 DAG.getConstant(Intrinsic::arm_neon_vqmovnsu, MVT::i32),
4812 // v4i16 sdiv ... Convert to float.
4813 // float4 yf = vcvt_f32_s32(vmovl_u16(y));
4814 // float4 xf = vcvt_f32_s32(vmovl_u16(x));
4815 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0);
4816 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1);
4817 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
4818 SDValue BN1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
4820 // Use reciprocal estimate and two refinement steps.
4821 // float4 recip = vrecpeq_f32(yf);
4822 // recip *= vrecpsq_f32(yf, recip);
4823 // recip *= vrecpsq_f32(yf, recip);
4824 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4825 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), BN1);
4826 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4827 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
4829 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
4830 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4831 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
4833 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
4834 // Simply multiplying by the reciprocal estimate can leave us a few ulps
4835 // too low, so we add 2 ulps (exhaustive testing shows that this is enough,
4836 // and that it will never cause us to return an answer too large).
4837 // float4 result = as_float4(as_int4(xf*recip) + 2);
4838 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
4839 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
4840 N1 = DAG.getConstant(2, MVT::i32);
4841 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
4842 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
4843 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
4844 // Convert back to integer and return.
4845 // return vmovn_u32(vcvt_s32_f32(result));
4846 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
4847 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
4851 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
4852 switch (Op.getOpcode()) {
4853 default: llvm_unreachable("Don't know how to custom lower this!");
4854 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
4855 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
4856 case ISD::GlobalAddress:
4857 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
4858 LowerGlobalAddressELF(Op, DAG);
4859 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
4860 case ISD::SELECT: return LowerSELECT(Op, DAG);
4861 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
4862 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
4863 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
4864 case ISD::VASTART: return LowerVASTART(Op, DAG);
4865 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget);
4866 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG, Subtarget);
4867 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget);
4868 case ISD::SINT_TO_FP:
4869 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
4870 case ISD::FP_TO_SINT:
4871 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
4872 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
4873 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
4874 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
4875 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
4876 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
4877 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
4878 case ISD::EH_SJLJ_DISPATCHSETUP: return LowerEH_SJLJ_DISPATCHSETUP(Op, DAG);
4879 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
4881 case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG);
4884 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
4885 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
4886 case ISD::SRL_PARTS:
4887 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
4888 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
4889 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
4890 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
4891 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
4892 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
4893 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
4894 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
4895 case ISD::MUL: return LowerMUL(Op, DAG);
4896 case ISD::SDIV: return LowerSDIV(Op, DAG);
4897 case ISD::UDIV: return LowerUDIV(Op, DAG);
4902 /// ReplaceNodeResults - Replace the results of node with an illegal result
4903 /// type with new values built out of custom code.
4904 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
4905 SmallVectorImpl<SDValue>&Results,
4906 SelectionDAG &DAG) const {
4908 switch (N->getOpcode()) {
4910 llvm_unreachable("Don't know how to custom expand this!");
4913 Res = ExpandBITCAST(N, DAG);
4917 Res = Expand64BitShift(N, DAG, Subtarget);
4921 Results.push_back(Res);
4924 //===----------------------------------------------------------------------===//
4925 // ARM Scheduler Hooks
4926 //===----------------------------------------------------------------------===//
4929 ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
4930 MachineBasicBlock *BB,
4931 unsigned Size) const {
4932 unsigned dest = MI->getOperand(0).getReg();
4933 unsigned ptr = MI->getOperand(1).getReg();
4934 unsigned oldval = MI->getOperand(2).getReg();
4935 unsigned newval = MI->getOperand(3).getReg();
4936 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4937 DebugLoc dl = MI->getDebugLoc();
4938 bool isThumb2 = Subtarget->isThumb2();
4940 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
4942 MRI.createVirtualRegister(isThumb2 ? ARM::rGPRRegisterClass
4943 : ARM::GPRRegisterClass);
4946 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass);
4947 MRI.constrainRegClass(oldval, ARM::rGPRRegisterClass);
4948 MRI.constrainRegClass(newval, ARM::rGPRRegisterClass);
4951 unsigned ldrOpc, strOpc;
4953 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
4955 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
4956 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
4959 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
4960 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
4963 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
4964 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
4968 MachineFunction *MF = BB->getParent();
4969 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4970 MachineFunction::iterator It = BB;
4971 ++It; // insert the new blocks after the current block
4973 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
4974 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
4975 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
4976 MF->insert(It, loop1MBB);
4977 MF->insert(It, loop2MBB);
4978 MF->insert(It, exitMBB);
4980 // Transfer the remainder of BB and its successor edges to exitMBB.
4981 exitMBB->splice(exitMBB->begin(), BB,
4982 llvm::next(MachineBasicBlock::iterator(MI)),
4984 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4988 // fallthrough --> loop1MBB
4989 BB->addSuccessor(loop1MBB);
4992 // ldrex dest, [ptr]
4996 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
4997 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
4998 .addReg(dest).addReg(oldval));
4999 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5000 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5001 BB->addSuccessor(loop2MBB);
5002 BB->addSuccessor(exitMBB);
5005 // strex scratch, newval, [ptr]
5009 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval)
5011 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5012 .addReg(scratch).addImm(0));
5013 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5014 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5015 BB->addSuccessor(loop1MBB);
5016 BB->addSuccessor(exitMBB);
5022 MI->eraseFromParent(); // The instruction is gone now.
5028 ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
5029 unsigned Size, unsigned BinOpcode) const {
5030 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
5031 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5033 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5034 MachineFunction *MF = BB->getParent();
5035 MachineFunction::iterator It = BB;
5038 unsigned dest = MI->getOperand(0).getReg();
5039 unsigned ptr = MI->getOperand(1).getReg();
5040 unsigned incr = MI->getOperand(2).getReg();
5041 DebugLoc dl = MI->getDebugLoc();
5042 bool isThumb2 = Subtarget->isThumb2();
5044 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
5046 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass);
5047 MRI.constrainRegClass(ptr, ARM::rGPRRegisterClass);
5050 unsigned ldrOpc, strOpc;
5052 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
5054 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
5055 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
5058 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
5059 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
5062 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
5063 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
5067 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5068 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5069 MF->insert(It, loopMBB);
5070 MF->insert(It, exitMBB);
5072 // Transfer the remainder of BB and its successor edges to exitMBB.
5073 exitMBB->splice(exitMBB->begin(), BB,
5074 llvm::next(MachineBasicBlock::iterator(MI)),
5076 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5078 TargetRegisterClass *TRC =
5079 isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
5080 unsigned scratch = MRI.createVirtualRegister(TRC);
5081 unsigned scratch2 = (!BinOpcode) ? incr : MRI.createVirtualRegister(TRC);
5085 // fallthrough --> loopMBB
5086 BB->addSuccessor(loopMBB);
5090 // <binop> scratch2, dest, incr
5091 // strex scratch, scratch2, ptr
5094 // fallthrough --> exitMBB
5096 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
5098 // operand order needs to go the other way for NAND
5099 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr)
5100 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
5101 addReg(incr).addReg(dest)).addReg(0);
5103 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
5104 addReg(dest).addReg(incr)).addReg(0);
5107 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2)
5109 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5110 .addReg(scratch).addImm(0));
5111 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5112 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5114 BB->addSuccessor(loopMBB);
5115 BB->addSuccessor(exitMBB);
5121 MI->eraseFromParent(); // The instruction is gone now.
5127 ARMTargetLowering::EmitAtomicBinaryMinMax(MachineInstr *MI,
5128 MachineBasicBlock *BB,
5131 ARMCC::CondCodes Cond) const {
5132 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5134 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5135 MachineFunction *MF = BB->getParent();
5136 MachineFunction::iterator It = BB;
5139 unsigned dest = MI->getOperand(0).getReg();
5140 unsigned ptr = MI->getOperand(1).getReg();
5141 unsigned incr = MI->getOperand(2).getReg();
5142 unsigned oldval = dest;
5143 DebugLoc dl = MI->getDebugLoc();
5144 bool isThumb2 = Subtarget->isThumb2();
5146 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
5148 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass);
5149 MRI.constrainRegClass(ptr, ARM::rGPRRegisterClass);
5152 unsigned ldrOpc, strOpc, extendOpc;
5154 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
5156 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
5157 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
5158 extendOpc = isThumb2 ? ARM::t2SXTB : ARM::SXTB;
5161 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
5162 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
5163 extendOpc = isThumb2 ? ARM::t2SXTH : ARM::SXTH;
5166 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
5167 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
5172 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5173 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5174 MF->insert(It, loopMBB);
5175 MF->insert(It, exitMBB);
5177 // Transfer the remainder of BB and its successor edges to exitMBB.
5178 exitMBB->splice(exitMBB->begin(), BB,
5179 llvm::next(MachineBasicBlock::iterator(MI)),
5181 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5183 TargetRegisterClass *TRC =
5184 isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
5185 unsigned scratch = MRI.createVirtualRegister(TRC);
5186 unsigned scratch2 = MRI.createVirtualRegister(TRC);
5190 // fallthrough --> loopMBB
5191 BB->addSuccessor(loopMBB);
5195 // (sign extend dest, if required)
5197 // cmov.cond scratch2, dest, incr
5198 // strex scratch, scratch2, ptr
5201 // fallthrough --> exitMBB
5203 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
5205 // Sign extend the value, if necessary.
5206 if (signExtend && extendOpc) {
5207 oldval = MRI.createVirtualRegister(ARM::GPRRegisterClass);
5208 AddDefaultPred(BuildMI(BB, dl, TII->get(extendOpc), oldval)
5213 // Build compare and cmov instructions.
5214 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
5215 .addReg(oldval).addReg(incr));
5216 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr), scratch2)
5217 .addReg(oldval).addReg(incr).addImm(Cond).addReg(ARM::CPSR);
5219 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2)
5221 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5222 .addReg(scratch).addImm(0));
5223 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5224 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5226 BB->addSuccessor(loopMBB);
5227 BB->addSuccessor(exitMBB);
5233 MI->eraseFromParent(); // The instruction is gone now.
5239 MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
5240 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
5241 E = MBB->succ_end(); I != E; ++I)
5244 llvm_unreachable("Expecting a BB with two successors!");
5247 // FIXME: This opcode table should obviously be expressed in the target
5248 // description. We probably just need a "machine opcode" value in the pseudo
5249 // instruction. But the ideal solution maybe to simply remove the "S" version
5250 // of the opcode altogether.
5251 struct AddSubFlagsOpcodePair {
5253 unsigned MachineOpc;
5256 static AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
5257 {ARM::ADCSri, ARM::ADCri},
5258 {ARM::ADCSrr, ARM::ADCrr},
5259 {ARM::ADCSrsi, ARM::ADCrsi},
5260 {ARM::ADCSrsr, ARM::ADCrsr},
5261 {ARM::SBCSri, ARM::SBCri},
5262 {ARM::SBCSrr, ARM::SBCrr},
5263 {ARM::SBCSrsi, ARM::SBCrsi},
5264 {ARM::SBCSrsr, ARM::SBCrsr},
5265 {ARM::RSBSri, ARM::RSBri},
5266 {ARM::RSBSrr, ARM::RSBrr},
5267 {ARM::RSBSrsi, ARM::RSBrsi},
5268 {ARM::RSBSrsr, ARM::RSBrsr},
5269 {ARM::RSCSri, ARM::RSCri},
5270 {ARM::RSCSrsi, ARM::RSCrsi},
5271 {ARM::RSCSrsr, ARM::RSCrsr},
5272 {ARM::t2ADCSri, ARM::t2ADCri},
5273 {ARM::t2ADCSrr, ARM::t2ADCrr},
5274 {ARM::t2ADCSrs, ARM::t2ADCrs},
5275 {ARM::t2SBCSri, ARM::t2SBCri},
5276 {ARM::t2SBCSrr, ARM::t2SBCrr},
5277 {ARM::t2SBCSrs, ARM::t2SBCrs},
5278 {ARM::t2RSBSri, ARM::t2RSBri},
5279 {ARM::t2RSBSrs, ARM::t2RSBrs},
5282 // Convert and Add or Subtract with Carry and Flags to a generic opcode with
5283 // CPSR<def> operand. e.g. ADCS (...) -> ADC (... CPSR<def>).
5285 // FIXME: Somewhere we should assert that CPSR<def> is in the correct
5286 // position to be recognized by the target descrition as the 'S' bit.
5287 bool ARMTargetLowering::RemapAddSubWithFlags(MachineInstr *MI,
5288 MachineBasicBlock *BB) const {
5289 unsigned OldOpc = MI->getOpcode();
5290 unsigned NewOpc = 0;
5292 // This is only called for instructions that need remapping, so iterating over
5293 // the tiny opcode table is not costly.
5294 static const int NPairs =
5295 sizeof(AddSubFlagsOpcodeMap) / sizeof(AddSubFlagsOpcodePair);
5296 for (AddSubFlagsOpcodePair *Pair = &AddSubFlagsOpcodeMap[0],
5297 *End = &AddSubFlagsOpcodeMap[NPairs]; Pair != End; ++Pair) {
5298 if (OldOpc == Pair->PseudoOpc) {
5299 NewOpc = Pair->MachineOpc;
5306 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5307 DebugLoc dl = MI->getDebugLoc();
5308 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc));
5309 for (unsigned i = 0; i < MI->getNumOperands(); ++i)
5310 MIB.addOperand(MI->getOperand(i));
5311 AddDefaultPred(MIB);
5312 MIB.addReg(ARM::CPSR, RegState::Define); // S bit
5313 MI->eraseFromParent();
5318 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
5319 MachineBasicBlock *BB) const {
5320 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5321 DebugLoc dl = MI->getDebugLoc();
5322 bool isThumb2 = Subtarget->isThumb2();
5323 switch (MI->getOpcode()) {
5325 if (RemapAddSubWithFlags(MI, BB))
5329 llvm_unreachable("Unexpected instr type to insert");
5331 case ARM::ATOMIC_LOAD_ADD_I8:
5332 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
5333 case ARM::ATOMIC_LOAD_ADD_I16:
5334 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
5335 case ARM::ATOMIC_LOAD_ADD_I32:
5336 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
5338 case ARM::ATOMIC_LOAD_AND_I8:
5339 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
5340 case ARM::ATOMIC_LOAD_AND_I16:
5341 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
5342 case ARM::ATOMIC_LOAD_AND_I32:
5343 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
5345 case ARM::ATOMIC_LOAD_OR_I8:
5346 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
5347 case ARM::ATOMIC_LOAD_OR_I16:
5348 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
5349 case ARM::ATOMIC_LOAD_OR_I32:
5350 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
5352 case ARM::ATOMIC_LOAD_XOR_I8:
5353 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
5354 case ARM::ATOMIC_LOAD_XOR_I16:
5355 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
5356 case ARM::ATOMIC_LOAD_XOR_I32:
5357 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
5359 case ARM::ATOMIC_LOAD_NAND_I8:
5360 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
5361 case ARM::ATOMIC_LOAD_NAND_I16:
5362 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
5363 case ARM::ATOMIC_LOAD_NAND_I32:
5364 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
5366 case ARM::ATOMIC_LOAD_SUB_I8:
5367 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
5368 case ARM::ATOMIC_LOAD_SUB_I16:
5369 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
5370 case ARM::ATOMIC_LOAD_SUB_I32:
5371 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
5373 case ARM::ATOMIC_LOAD_MIN_I8:
5374 return EmitAtomicBinaryMinMax(MI, BB, 1, true, ARMCC::LT);
5375 case ARM::ATOMIC_LOAD_MIN_I16:
5376 return EmitAtomicBinaryMinMax(MI, BB, 2, true, ARMCC::LT);
5377 case ARM::ATOMIC_LOAD_MIN_I32:
5378 return EmitAtomicBinaryMinMax(MI, BB, 4, true, ARMCC::LT);
5380 case ARM::ATOMIC_LOAD_MAX_I8:
5381 return EmitAtomicBinaryMinMax(MI, BB, 1, true, ARMCC::GT);
5382 case ARM::ATOMIC_LOAD_MAX_I16:
5383 return EmitAtomicBinaryMinMax(MI, BB, 2, true, ARMCC::GT);
5384 case ARM::ATOMIC_LOAD_MAX_I32:
5385 return EmitAtomicBinaryMinMax(MI, BB, 4, true, ARMCC::GT);
5387 case ARM::ATOMIC_LOAD_UMIN_I8:
5388 return EmitAtomicBinaryMinMax(MI, BB, 1, false, ARMCC::LO);
5389 case ARM::ATOMIC_LOAD_UMIN_I16:
5390 return EmitAtomicBinaryMinMax(MI, BB, 2, false, ARMCC::LO);
5391 case ARM::ATOMIC_LOAD_UMIN_I32:
5392 return EmitAtomicBinaryMinMax(MI, BB, 4, false, ARMCC::LO);
5394 case ARM::ATOMIC_LOAD_UMAX_I8:
5395 return EmitAtomicBinaryMinMax(MI, BB, 1, false, ARMCC::HI);
5396 case ARM::ATOMIC_LOAD_UMAX_I16:
5397 return EmitAtomicBinaryMinMax(MI, BB, 2, false, ARMCC::HI);
5398 case ARM::ATOMIC_LOAD_UMAX_I32:
5399 return EmitAtomicBinaryMinMax(MI, BB, 4, false, ARMCC::HI);
5401 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0);
5402 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0);
5403 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0);
5405 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1);
5406 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
5407 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
5409 case ARM::tMOVCCr_pseudo: {
5410 // To "insert" a SELECT_CC instruction, we actually have to insert the
5411 // diamond control-flow pattern. The incoming instruction knows the
5412 // destination vreg to set, the condition code register to branch on, the
5413 // true/false values to select between, and a branch opcode to use.
5414 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5415 MachineFunction::iterator It = BB;
5421 // cmpTY ccX, r1, r2
5423 // fallthrough --> copy0MBB
5424 MachineBasicBlock *thisMBB = BB;
5425 MachineFunction *F = BB->getParent();
5426 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
5427 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
5428 F->insert(It, copy0MBB);
5429 F->insert(It, sinkMBB);
5431 // Transfer the remainder of BB and its successor edges to sinkMBB.
5432 sinkMBB->splice(sinkMBB->begin(), BB,
5433 llvm::next(MachineBasicBlock::iterator(MI)),
5435 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
5437 BB->addSuccessor(copy0MBB);
5438 BB->addSuccessor(sinkMBB);
5440 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
5441 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
5444 // %FalseValue = ...
5445 // # fallthrough to sinkMBB
5448 // Update machine-CFG edges
5449 BB->addSuccessor(sinkMBB);
5452 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
5455 BuildMI(*BB, BB->begin(), dl,
5456 TII->get(ARM::PHI), MI->getOperand(0).getReg())
5457 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
5458 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
5460 MI->eraseFromParent(); // The pseudo instruction is gone now.
5465 case ARM::BCCZi64: {
5466 // If there is an unconditional branch to the other successor, remove it.
5467 BB->erase(llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
5469 // Compare both parts that make up the double comparison separately for
5471 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
5473 unsigned LHS1 = MI->getOperand(1).getReg();
5474 unsigned LHS2 = MI->getOperand(2).getReg();
5476 AddDefaultPred(BuildMI(BB, dl,
5477 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5478 .addReg(LHS1).addImm(0));
5479 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5480 .addReg(LHS2).addImm(0)
5481 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
5483 unsigned RHS1 = MI->getOperand(3).getReg();
5484 unsigned RHS2 = MI->getOperand(4).getReg();
5485 AddDefaultPred(BuildMI(BB, dl,
5486 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
5487 .addReg(LHS1).addReg(RHS1));
5488 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
5489 .addReg(LHS2).addReg(RHS2)
5490 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
5493 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB();
5494 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
5495 if (MI->getOperand(0).getImm() == ARMCC::NE)
5496 std::swap(destMBB, exitMBB);
5498 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5499 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
5500 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2B : ARM::B))
5503 MI->eraseFromParent(); // The pseudo instruction is gone now.
5509 //===----------------------------------------------------------------------===//
5510 // ARM Optimization Hooks
5511 //===----------------------------------------------------------------------===//
5514 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
5515 TargetLowering::DAGCombinerInfo &DCI) {
5516 SelectionDAG &DAG = DCI.DAG;
5517 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5518 EVT VT = N->getValueType(0);
5519 unsigned Opc = N->getOpcode();
5520 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
5521 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
5522 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
5523 ISD::CondCode CC = ISD::SETCC_INVALID;
5526 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
5528 SDValue CCOp = Slct.getOperand(0);
5529 if (CCOp.getOpcode() == ISD::SETCC)
5530 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
5533 bool DoXform = false;
5535 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
5538 if (LHS.getOpcode() == ISD::Constant &&
5539 cast<ConstantSDNode>(LHS)->isNullValue()) {
5541 } else if (CC != ISD::SETCC_INVALID &&
5542 RHS.getOpcode() == ISD::Constant &&
5543 cast<ConstantSDNode>(RHS)->isNullValue()) {
5544 std::swap(LHS, RHS);
5545 SDValue Op0 = Slct.getOperand(0);
5546 EVT OpVT = isSlctCC ? Op0.getValueType() :
5547 Op0.getOperand(0).getValueType();
5548 bool isInt = OpVT.isInteger();
5549 CC = ISD::getSetCCInverse(CC, isInt);
5551 if (!TLI.isCondCodeLegal(CC, OpVT))
5552 return SDValue(); // Inverse operator isn't legal.
5559 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
5561 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
5562 Slct.getOperand(0), Slct.getOperand(1), CC);
5563 SDValue CCOp = Slct.getOperand(0);
5565 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
5566 CCOp.getOperand(0), CCOp.getOperand(1), CC);
5567 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
5568 CCOp, OtherOp, Result);
5573 // AddCombineToVPADDL- For pair-wise add on neon, use the vpaddl instruction
5574 // (only after legalization).
5575 static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1,
5576 TargetLowering::DAGCombinerInfo &DCI,
5577 const ARMSubtarget *Subtarget) {
5579 // Only perform optimization if after legalize, and if NEON is available. We
5580 // also expected both operands to be BUILD_VECTORs.
5581 if (DCI.isBeforeLegalize() || !Subtarget->hasNEON()
5582 || N0.getOpcode() != ISD::BUILD_VECTOR
5583 || N1.getOpcode() != ISD::BUILD_VECTOR)
5586 // Check output type since VPADDL operand elements can only be 8, 16, or 32.
5587 EVT VT = N->getValueType(0);
5588 if (!VT.isInteger() || VT.getVectorElementType() == MVT::i64)
5591 // Check that the vector operands are of the right form.
5592 // N0 and N1 are BUILD_VECTOR nodes with N number of EXTRACT_VECTOR
5593 // operands, where N is the size of the formed vector.
5594 // Each EXTRACT_VECTOR should have the same input vector and odd or even
5595 // index such that we have a pair wise add pattern.
5597 // Grab the vector that all EXTRACT_VECTOR nodes should be referencing.
5598 if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5600 SDValue Vec = N0->getOperand(0)->getOperand(0);
5601 SDNode *V = Vec.getNode();
5602 unsigned nextIndex = 0;
5604 // For each operands to the ADD which are BUILD_VECTORs,
5605 // check to see if each of their operands are an EXTRACT_VECTOR with
5606 // the same vector and appropriate index.
5607 for (unsigned i = 0, e = N0->getNumOperands(); i != e; ++i) {
5608 if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT
5609 && N1->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
5611 SDValue ExtVec0 = N0->getOperand(i);
5612 SDValue ExtVec1 = N1->getOperand(i);
5614 // First operand is the vector, verify its the same.
5615 if (V != ExtVec0->getOperand(0).getNode() ||
5616 V != ExtVec1->getOperand(0).getNode())
5619 // Second is the constant, verify its correct.
5620 ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(ExtVec0->getOperand(1));
5621 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(ExtVec1->getOperand(1));
5623 // For the constant, we want to see all the even or all the odd.
5624 if (!C0 || !C1 || C0->getZExtValue() != nextIndex
5625 || C1->getZExtValue() != nextIndex+1)
5634 // Create VPADDL node.
5635 SelectionDAG &DAG = DCI.DAG;
5636 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5638 // Build operand list.
5639 SmallVector<SDValue, 8> Ops;
5640 Ops.push_back(DAG.getConstant(Intrinsic::arm_neon_vpaddls,
5641 TLI.getPointerTy()));
5643 // Input is the vector.
5646 // Get widened type and narrowed type.
5648 unsigned numElem = VT.getVectorNumElements();
5649 switch (VT.getVectorElementType().getSimpleVT().SimpleTy) {
5650 case MVT::i8: widenType = MVT::getVectorVT(MVT::i16, numElem); break;
5651 case MVT::i16: widenType = MVT::getVectorVT(MVT::i32, numElem); break;
5652 case MVT::i32: widenType = MVT::getVectorVT(MVT::i64, numElem); break;
5654 assert(0 && "Invalid vector element type for padd optimization.");
5657 SDValue tmp = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(),
5658 widenType, &Ops[0], Ops.size());
5659 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, tmp);
5662 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
5663 /// operands N0 and N1. This is a helper for PerformADDCombine that is
5664 /// called with the default operands, and if that fails, with commuted
5666 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
5667 TargetLowering::DAGCombinerInfo &DCI,
5668 const ARMSubtarget *Subtarget){
5670 // Attempt to create vpaddl for this add.
5671 SDValue Result = AddCombineToVPADDL(N, N0, N1, DCI, Subtarget);
5672 if (Result.getNode())
5675 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
5676 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
5677 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
5678 if (Result.getNode()) return Result;
5683 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
5685 static SDValue PerformADDCombine(SDNode *N,
5686 TargetLowering::DAGCombinerInfo &DCI,
5687 const ARMSubtarget *Subtarget) {
5688 SDValue N0 = N->getOperand(0);
5689 SDValue N1 = N->getOperand(1);
5691 // First try with the default operand order.
5692 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget);
5693 if (Result.getNode())
5696 // If that didn't work, try again with the operands commuted.
5697 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget);
5700 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
5702 static SDValue PerformSUBCombine(SDNode *N,
5703 TargetLowering::DAGCombinerInfo &DCI) {
5704 SDValue N0 = N->getOperand(0);
5705 SDValue N1 = N->getOperand(1);
5707 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
5708 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
5709 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
5710 if (Result.getNode()) return Result;
5716 /// PerformVMULCombine
5717 /// Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the
5718 /// special multiplier accumulator forwarding.
5724 static SDValue PerformVMULCombine(SDNode *N,
5725 TargetLowering::DAGCombinerInfo &DCI,
5726 const ARMSubtarget *Subtarget) {
5727 if (!Subtarget->hasVMLxForwarding())
5730 SelectionDAG &DAG = DCI.DAG;
5731 SDValue N0 = N->getOperand(0);
5732 SDValue N1 = N->getOperand(1);
5733 unsigned Opcode = N0.getOpcode();
5734 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
5735 Opcode != ISD::FADD && Opcode != ISD::FSUB) {
5736 Opcode = N1.getOpcode();
5737 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
5738 Opcode != ISD::FADD && Opcode != ISD::FSUB)
5743 EVT VT = N->getValueType(0);
5744 DebugLoc DL = N->getDebugLoc();
5745 SDValue N00 = N0->getOperand(0);
5746 SDValue N01 = N0->getOperand(1);
5747 return DAG.getNode(Opcode, DL, VT,
5748 DAG.getNode(ISD::MUL, DL, VT, N00, N1),
5749 DAG.getNode(ISD::MUL, DL, VT, N01, N1));
5752 static SDValue PerformMULCombine(SDNode *N,
5753 TargetLowering::DAGCombinerInfo &DCI,
5754 const ARMSubtarget *Subtarget) {
5755 SelectionDAG &DAG = DCI.DAG;
5757 if (Subtarget->isThumb1Only())
5760 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
5763 EVT VT = N->getValueType(0);
5764 if (VT.is64BitVector() || VT.is128BitVector())
5765 return PerformVMULCombine(N, DCI, Subtarget);
5769 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
5773 uint64_t MulAmt = C->getZExtValue();
5774 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt);
5775 ShiftAmt = ShiftAmt & (32 - 1);
5776 SDValue V = N->getOperand(0);
5777 DebugLoc DL = N->getDebugLoc();
5780 MulAmt >>= ShiftAmt;
5781 if (isPowerOf2_32(MulAmt - 1)) {
5782 // (mul x, 2^N + 1) => (add (shl x, N), x)
5783 Res = DAG.getNode(ISD::ADD, DL, VT,
5784 V, DAG.getNode(ISD::SHL, DL, VT,
5785 V, DAG.getConstant(Log2_32(MulAmt-1),
5787 } else if (isPowerOf2_32(MulAmt + 1)) {
5788 // (mul x, 2^N - 1) => (sub (shl x, N), x)
5789 Res = DAG.getNode(ISD::SUB, DL, VT,
5790 DAG.getNode(ISD::SHL, DL, VT,
5791 V, DAG.getConstant(Log2_32(MulAmt+1),
5798 Res = DAG.getNode(ISD::SHL, DL, VT, Res,
5799 DAG.getConstant(ShiftAmt, MVT::i32));
5801 // Do not add new nodes to DAG combiner worklist.
5802 DCI.CombineTo(N, Res, false);
5806 static SDValue PerformANDCombine(SDNode *N,
5807 TargetLowering::DAGCombinerInfo &DCI) {
5809 // Attempt to use immediate-form VBIC
5810 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
5811 DebugLoc dl = N->getDebugLoc();
5812 EVT VT = N->getValueType(0);
5813 SelectionDAG &DAG = DCI.DAG;
5815 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
5818 APInt SplatBits, SplatUndef;
5819 unsigned SplatBitSize;
5822 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5823 if (SplatBitSize <= 64) {
5825 SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(),
5826 SplatUndef.getZExtValue(), SplatBitSize,
5827 DAG, VbicVT, VT.is128BitVector(),
5829 if (Val.getNode()) {
5831 DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0));
5832 SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val);
5833 return DAG.getNode(ISD::BITCAST, dl, VT, Vbic);
5841 /// PerformORCombine - Target-specific dag combine xforms for ISD::OR
5842 static SDValue PerformORCombine(SDNode *N,
5843 TargetLowering::DAGCombinerInfo &DCI,
5844 const ARMSubtarget *Subtarget) {
5845 // Attempt to use immediate-form VORR
5846 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
5847 DebugLoc dl = N->getDebugLoc();
5848 EVT VT = N->getValueType(0);
5849 SelectionDAG &DAG = DCI.DAG;
5851 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
5854 APInt SplatBits, SplatUndef;
5855 unsigned SplatBitSize;
5857 if (BVN && Subtarget->hasNEON() &&
5858 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5859 if (SplatBitSize <= 64) {
5861 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
5862 SplatUndef.getZExtValue(), SplatBitSize,
5863 DAG, VorrVT, VT.is128BitVector(),
5865 if (Val.getNode()) {
5867 DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0));
5868 SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val);
5869 return DAG.getNode(ISD::BITCAST, dl, VT, Vorr);
5874 SDValue N0 = N->getOperand(0);
5875 if (N0.getOpcode() != ISD::AND)
5877 SDValue N1 = N->getOperand(1);
5879 // (or (and B, A), (and C, ~A)) => (VBSL A, B, C) when A is a constant.
5880 if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() &&
5881 DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
5883 unsigned SplatBitSize;
5886 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1));
5888 if (BVN0 && BVN0->isConstantSplat(SplatBits0, SplatUndef, SplatBitSize,
5889 HasAnyUndefs) && !HasAnyUndefs) {
5890 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(1));
5892 if (BVN1 && BVN1->isConstantSplat(SplatBits1, SplatUndef, SplatBitSize,
5893 HasAnyUndefs) && !HasAnyUndefs &&
5894 SplatBits0 == ~SplatBits1) {
5895 // Canonicalize the vector type to make instruction selection simpler.
5896 EVT CanonicalVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
5897 SDValue Result = DAG.getNode(ARMISD::VBSL, dl, CanonicalVT,
5898 N0->getOperand(1), N0->getOperand(0),
5900 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
5905 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when
5908 // BFI is only available on V6T2+
5909 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops())
5912 DebugLoc DL = N->getDebugLoc();
5913 // 1) or (and A, mask), val => ARMbfi A, val, mask
5914 // iff (val & mask) == val
5916 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
5917 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2)
5918 // && mask == ~mask2
5919 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2)
5920 // && ~mask == mask2
5921 // (i.e., copy a bitfield value into another bitfield of the same width)
5926 SDValue N00 = N0.getOperand(0);
5928 // The value and the mask need to be constants so we can verify this is
5929 // actually a bitfield set. If the mask is 0xffff, we can do better
5930 // via a movt instruction, so don't use BFI in that case.
5931 SDValue MaskOp = N0.getOperand(1);
5932 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(MaskOp);
5935 unsigned Mask = MaskC->getZExtValue();
5939 // Case (1): or (and A, mask), val => ARMbfi A, val, mask
5940 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
5942 unsigned Val = N1C->getZExtValue();
5943 if ((Val & ~Mask) != Val)
5946 if (ARM::isBitFieldInvertedMask(Mask)) {
5947 Val >>= CountTrailingZeros_32(~Mask);
5949 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00,
5950 DAG.getConstant(Val, MVT::i32),
5951 DAG.getConstant(Mask, MVT::i32));
5953 // Do not add new nodes to DAG combiner worklist.
5954 DCI.CombineTo(N, Res, false);
5957 } else if (N1.getOpcode() == ISD::AND) {
5958 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
5959 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
5962 unsigned Mask2 = N11C->getZExtValue();
5964 // Mask and ~Mask2 (or reverse) must be equivalent for the BFI pattern
5966 if (ARM::isBitFieldInvertedMask(Mask) &&
5968 // The pack halfword instruction works better for masks that fit it,
5969 // so use that when it's available.
5970 if (Subtarget->hasT2ExtractPack() &&
5971 (Mask == 0xffff || Mask == 0xffff0000))
5974 unsigned amt = CountTrailingZeros_32(Mask2);
5975 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
5976 DAG.getConstant(amt, MVT::i32));
5977 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res,
5978 DAG.getConstant(Mask, MVT::i32));
5979 // Do not add new nodes to DAG combiner worklist.
5980 DCI.CombineTo(N, Res, false);
5982 } else if (ARM::isBitFieldInvertedMask(~Mask) &&
5984 // The pack halfword instruction works better for masks that fit it,
5985 // so use that when it's available.
5986 if (Subtarget->hasT2ExtractPack() &&
5987 (Mask2 == 0xffff || Mask2 == 0xffff0000))
5990 unsigned lsb = CountTrailingZeros_32(Mask);
5991 Res = DAG.getNode(ISD::SRL, DL, VT, N00,
5992 DAG.getConstant(lsb, MVT::i32));
5993 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
5994 DAG.getConstant(Mask2, MVT::i32));
5995 // Do not add new nodes to DAG combiner worklist.
5996 DCI.CombineTo(N, Res, false);
6001 if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) &&
6002 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) &&
6003 ARM::isBitFieldInvertedMask(~Mask)) {
6004 // Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask
6005 // where lsb(mask) == #shamt and masked bits of B are known zero.
6006 SDValue ShAmt = N00.getOperand(1);
6007 unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue();
6008 unsigned LSB = CountTrailingZeros_32(Mask);
6012 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0),
6013 DAG.getConstant(~Mask, MVT::i32));
6015 // Do not add new nodes to DAG combiner worklist.
6016 DCI.CombineTo(N, Res, false);
6022 /// PerformBFICombine - (bfi A, (and B, Mask1), Mask2) -> (bfi A, B, Mask2) iff
6023 /// the bits being cleared by the AND are not demanded by the BFI.
6024 static SDValue PerformBFICombine(SDNode *N,
6025 TargetLowering::DAGCombinerInfo &DCI) {
6026 SDValue N1 = N->getOperand(1);
6027 if (N1.getOpcode() == ISD::AND) {
6028 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
6031 unsigned InvMask = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
6032 unsigned LSB = CountTrailingZeros_32(~InvMask);
6033 unsigned Width = (32 - CountLeadingZeros_32(~InvMask)) - LSB;
6034 unsigned Mask = (1 << Width)-1;
6035 unsigned Mask2 = N11C->getZExtValue();
6036 if ((Mask & (~Mask2)) == 0)
6037 return DCI.DAG.getNode(ARMISD::BFI, N->getDebugLoc(), N->getValueType(0),
6038 N->getOperand(0), N1.getOperand(0),
6044 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
6045 /// ARMISD::VMOVRRD.
6046 static SDValue PerformVMOVRRDCombine(SDNode *N,
6047 TargetLowering::DAGCombinerInfo &DCI) {
6048 // vmovrrd(vmovdrr x, y) -> x,y
6049 SDValue InDouble = N->getOperand(0);
6050 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
6051 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
6053 // vmovrrd(load f64) -> (load i32), (load i32)
6054 SDNode *InNode = InDouble.getNode();
6055 if (ISD::isNormalLoad(InNode) && InNode->hasOneUse() &&
6056 InNode->getValueType(0) == MVT::f64 &&
6057 InNode->getOperand(1).getOpcode() == ISD::FrameIndex &&
6058 !cast<LoadSDNode>(InNode)->isVolatile()) {
6059 // TODO: Should this be done for non-FrameIndex operands?
6060 LoadSDNode *LD = cast<LoadSDNode>(InNode);
6062 SelectionDAG &DAG = DCI.DAG;
6063 DebugLoc DL = LD->getDebugLoc();
6064 SDValue BasePtr = LD->getBasePtr();
6065 SDValue NewLD1 = DAG.getLoad(MVT::i32, DL, LD->getChain(), BasePtr,
6066 LD->getPointerInfo(), LD->isVolatile(),
6067 LD->isNonTemporal(), LD->getAlignment());
6069 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
6070 DAG.getConstant(4, MVT::i32));
6071 SDValue NewLD2 = DAG.getLoad(MVT::i32, DL, NewLD1.getValue(1), OffsetPtr,
6072 LD->getPointerInfo(), LD->isVolatile(),
6073 LD->isNonTemporal(),
6074 std::min(4U, LD->getAlignment() / 2));
6076 DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), NewLD2.getValue(1));
6077 SDValue Result = DCI.CombineTo(N, NewLD1, NewLD2);
6078 DCI.RemoveFromWorklist(LD);
6086 /// PerformVMOVDRRCombine - Target-specific dag combine xforms for
6087 /// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands.
6088 static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) {
6089 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X)
6090 SDValue Op0 = N->getOperand(0);
6091 SDValue Op1 = N->getOperand(1);
6092 if (Op0.getOpcode() == ISD::BITCAST)
6093 Op0 = Op0.getOperand(0);
6094 if (Op1.getOpcode() == ISD::BITCAST)
6095 Op1 = Op1.getOperand(0);
6096 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
6097 Op0.getNode() == Op1.getNode() &&
6098 Op0.getResNo() == 0 && Op1.getResNo() == 1)
6099 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
6100 N->getValueType(0), Op0.getOperand(0));
6104 /// PerformSTORECombine - Target-specific dag combine xforms for
6106 static SDValue PerformSTORECombine(SDNode *N,
6107 TargetLowering::DAGCombinerInfo &DCI) {
6108 // Bitcast an i64 store extracted from a vector to f64.
6109 // Otherwise, the i64 value will be legalized to a pair of i32 values.
6110 StoreSDNode *St = cast<StoreSDNode>(N);
6111 SDValue StVal = St->getValue();
6112 if (!ISD::isNormalStore(St) || St->isVolatile())
6115 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR &&
6116 StVal.getNode()->hasOneUse() && !St->isVolatile()) {
6117 SelectionDAG &DAG = DCI.DAG;
6118 DebugLoc DL = St->getDebugLoc();
6119 SDValue BasePtr = St->getBasePtr();
6120 SDValue NewST1 = DAG.getStore(St->getChain(), DL,
6121 StVal.getNode()->getOperand(0), BasePtr,
6122 St->getPointerInfo(), St->isVolatile(),
6123 St->isNonTemporal(), St->getAlignment());
6125 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
6126 DAG.getConstant(4, MVT::i32));
6127 return DAG.getStore(NewST1.getValue(0), DL, StVal.getNode()->getOperand(1),
6128 OffsetPtr, St->getPointerInfo(), St->isVolatile(),
6129 St->isNonTemporal(),
6130 std::min(4U, St->getAlignment() / 2));
6133 if (StVal.getValueType() != MVT::i64 ||
6134 StVal.getNode()->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
6137 SelectionDAG &DAG = DCI.DAG;
6138 DebugLoc dl = StVal.getDebugLoc();
6139 SDValue IntVec = StVal.getOperand(0);
6140 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
6141 IntVec.getValueType().getVectorNumElements());
6142 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec);
6143 SDValue ExtElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
6144 Vec, StVal.getOperand(1));
6145 dl = N->getDebugLoc();
6146 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt);
6147 // Make the DAGCombiner fold the bitcasts.
6148 DCI.AddToWorklist(Vec.getNode());
6149 DCI.AddToWorklist(ExtElt.getNode());
6150 DCI.AddToWorklist(V.getNode());
6151 return DAG.getStore(St->getChain(), dl, V, St->getBasePtr(),
6152 St->getPointerInfo(), St->isVolatile(),
6153 St->isNonTemporal(), St->getAlignment(),
6157 /// hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node
6158 /// are normal, non-volatile loads. If so, it is profitable to bitcast an
6159 /// i64 vector to have f64 elements, since the value can then be loaded
6160 /// directly into a VFP register.
6161 static bool hasNormalLoadOperand(SDNode *N) {
6162 unsigned NumElts = N->getValueType(0).getVectorNumElements();
6163 for (unsigned i = 0; i < NumElts; ++i) {
6164 SDNode *Elt = N->getOperand(i).getNode();
6165 if (ISD::isNormalLoad(Elt) && !cast<LoadSDNode>(Elt)->isVolatile())
6171 /// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for
6172 /// ISD::BUILD_VECTOR.
6173 static SDValue PerformBUILD_VECTORCombine(SDNode *N,
6174 TargetLowering::DAGCombinerInfo &DCI){
6175 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X):
6176 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value
6177 // into a pair of GPRs, which is fine when the value is used as a scalar,
6178 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD.
6179 SelectionDAG &DAG = DCI.DAG;
6180 if (N->getNumOperands() == 2) {
6181 SDValue RV = PerformVMOVDRRCombine(N, DAG);
6186 // Load i64 elements as f64 values so that type legalization does not split
6187 // them up into i32 values.
6188 EVT VT = N->getValueType(0);
6189 if (VT.getVectorElementType() != MVT::i64 || !hasNormalLoadOperand(N))
6191 DebugLoc dl = N->getDebugLoc();
6192 SmallVector<SDValue, 8> Ops;
6193 unsigned NumElts = VT.getVectorNumElements();
6194 for (unsigned i = 0; i < NumElts; ++i) {
6195 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(i));
6197 // Make the DAGCombiner fold the bitcast.
6198 DCI.AddToWorklist(V.getNode());
6200 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, NumElts);
6201 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, FloatVT, Ops.data(), NumElts);
6202 return DAG.getNode(ISD::BITCAST, dl, VT, BV);
6205 /// PerformInsertEltCombine - Target-specific dag combine xforms for
6206 /// ISD::INSERT_VECTOR_ELT.
6207 static SDValue PerformInsertEltCombine(SDNode *N,
6208 TargetLowering::DAGCombinerInfo &DCI) {
6209 // Bitcast an i64 load inserted into a vector to f64.
6210 // Otherwise, the i64 value will be legalized to a pair of i32 values.
6211 EVT VT = N->getValueType(0);
6212 SDNode *Elt = N->getOperand(1).getNode();
6213 if (VT.getVectorElementType() != MVT::i64 ||
6214 !ISD::isNormalLoad(Elt) || cast<LoadSDNode>(Elt)->isVolatile())
6217 SelectionDAG &DAG = DCI.DAG;
6218 DebugLoc dl = N->getDebugLoc();
6219 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
6220 VT.getVectorNumElements());
6221 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, N->getOperand(0));
6222 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(1));
6223 // Make the DAGCombiner fold the bitcasts.
6224 DCI.AddToWorklist(Vec.getNode());
6225 DCI.AddToWorklist(V.getNode());
6226 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT,
6227 Vec, V, N->getOperand(2));
6228 return DAG.getNode(ISD::BITCAST, dl, VT, InsElt);
6231 /// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for
6232 /// ISD::VECTOR_SHUFFLE.
6233 static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) {
6234 // The LLVM shufflevector instruction does not require the shuffle mask
6235 // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does
6236 // have that requirement. When translating to ISD::VECTOR_SHUFFLE, if the
6237 // operands do not match the mask length, they are extended by concatenating
6238 // them with undef vectors. That is probably the right thing for other
6239 // targets, but for NEON it is better to concatenate two double-register
6240 // size vector operands into a single quad-register size vector. Do that
6241 // transformation here:
6242 // shuffle(concat(v1, undef), concat(v2, undef)) ->
6243 // shuffle(concat(v1, v2), undef)
6244 SDValue Op0 = N->getOperand(0);
6245 SDValue Op1 = N->getOperand(1);
6246 if (Op0.getOpcode() != ISD::CONCAT_VECTORS ||
6247 Op1.getOpcode() != ISD::CONCAT_VECTORS ||
6248 Op0.getNumOperands() != 2 ||
6249 Op1.getNumOperands() != 2)
6251 SDValue Concat0Op1 = Op0.getOperand(1);
6252 SDValue Concat1Op1 = Op1.getOperand(1);
6253 if (Concat0Op1.getOpcode() != ISD::UNDEF ||
6254 Concat1Op1.getOpcode() != ISD::UNDEF)
6256 // Skip the transformation if any of the types are illegal.
6257 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6258 EVT VT = N->getValueType(0);
6259 if (!TLI.isTypeLegal(VT) ||
6260 !TLI.isTypeLegal(Concat0Op1.getValueType()) ||
6261 !TLI.isTypeLegal(Concat1Op1.getValueType()))
6264 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT,
6265 Op0.getOperand(0), Op1.getOperand(0));
6266 // Translate the shuffle mask.
6267 SmallVector<int, 16> NewMask;
6268 unsigned NumElts = VT.getVectorNumElements();
6269 unsigned HalfElts = NumElts/2;
6270 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
6271 for (unsigned n = 0; n < NumElts; ++n) {
6272 int MaskElt = SVN->getMaskElt(n);
6274 if (MaskElt < (int)HalfElts)
6276 else if (MaskElt >= (int)NumElts && MaskElt < (int)(NumElts + HalfElts))
6277 NewElt = HalfElts + MaskElt - NumElts;
6278 NewMask.push_back(NewElt);
6280 return DAG.getVectorShuffle(VT, N->getDebugLoc(), NewConcat,
6281 DAG.getUNDEF(VT), NewMask.data());
6284 /// CombineBaseUpdate - Target-specific DAG combine function for VLDDUP and
6285 /// NEON load/store intrinsics to merge base address updates.
6286 static SDValue CombineBaseUpdate(SDNode *N,
6287 TargetLowering::DAGCombinerInfo &DCI) {
6288 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
6291 SelectionDAG &DAG = DCI.DAG;
6292 bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID ||
6293 N->getOpcode() == ISD::INTRINSIC_W_CHAIN);
6294 unsigned AddrOpIdx = (isIntrinsic ? 2 : 1);
6295 SDValue Addr = N->getOperand(AddrOpIdx);
6297 // Search for a use of the address operand that is an increment.
6298 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
6299 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
6301 if (User->getOpcode() != ISD::ADD ||
6302 UI.getUse().getResNo() != Addr.getResNo())
6305 // Check that the add is independent of the load/store. Otherwise, folding
6306 // it would create a cycle.
6307 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
6310 // Find the new opcode for the updating load/store.
6312 bool isLaneOp = false;
6313 unsigned NewOpc = 0;
6314 unsigned NumVecs = 0;
6316 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
6318 default: assert(0 && "unexpected intrinsic for Neon base update");
6319 case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD;
6321 case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD;
6323 case Intrinsic::arm_neon_vld3: NewOpc = ARMISD::VLD3_UPD;
6325 case Intrinsic::arm_neon_vld4: NewOpc = ARMISD::VLD4_UPD;
6327 case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD;
6328 NumVecs = 2; isLaneOp = true; break;
6329 case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD;
6330 NumVecs = 3; isLaneOp = true; break;
6331 case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD;
6332 NumVecs = 4; isLaneOp = true; break;
6333 case Intrinsic::arm_neon_vst1: NewOpc = ARMISD::VST1_UPD;
6334 NumVecs = 1; isLoad = false; break;
6335 case Intrinsic::arm_neon_vst2: NewOpc = ARMISD::VST2_UPD;
6336 NumVecs = 2; isLoad = false; break;
6337 case Intrinsic::arm_neon_vst3: NewOpc = ARMISD::VST3_UPD;
6338 NumVecs = 3; isLoad = false; break;
6339 case Intrinsic::arm_neon_vst4: NewOpc = ARMISD::VST4_UPD;
6340 NumVecs = 4; isLoad = false; break;
6341 case Intrinsic::arm_neon_vst2lane: NewOpc = ARMISD::VST2LN_UPD;
6342 NumVecs = 2; isLoad = false; isLaneOp = true; break;
6343 case Intrinsic::arm_neon_vst3lane: NewOpc = ARMISD::VST3LN_UPD;
6344 NumVecs = 3; isLoad = false; isLaneOp = true; break;
6345 case Intrinsic::arm_neon_vst4lane: NewOpc = ARMISD::VST4LN_UPD;
6346 NumVecs = 4; isLoad = false; isLaneOp = true; break;
6350 switch (N->getOpcode()) {
6351 default: assert(0 && "unexpected opcode for Neon base update");
6352 case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break;
6353 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break;
6354 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break;
6358 // Find the size of memory referenced by the load/store.
6361 VecTy = N->getValueType(0);
6363 VecTy = N->getOperand(AddrOpIdx+1).getValueType();
6364 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
6366 NumBytes /= VecTy.getVectorNumElements();
6368 // If the increment is a constant, it must match the memory ref size.
6369 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
6370 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
6371 uint64_t IncVal = CInc->getZExtValue();
6372 if (IncVal != NumBytes)
6374 } else if (NumBytes >= 3 * 16) {
6375 // VLD3/4 and VST3/4 for 128-bit vectors are implemented with two
6376 // separate instructions that make it harder to use a non-constant update.
6380 // Create the new updating load/store node.
6382 unsigned NumResultVecs = (isLoad ? NumVecs : 0);
6384 for (n = 0; n < NumResultVecs; ++n)
6386 Tys[n++] = MVT::i32;
6387 Tys[n] = MVT::Other;
6388 SDVTList SDTys = DAG.getVTList(Tys, NumResultVecs+2);
6389 SmallVector<SDValue, 8> Ops;
6390 Ops.push_back(N->getOperand(0)); // incoming chain
6391 Ops.push_back(N->getOperand(AddrOpIdx));
6393 for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands(); ++i) {
6394 Ops.push_back(N->getOperand(i));
6396 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
6397 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, N->getDebugLoc(), SDTys,
6398 Ops.data(), Ops.size(),
6399 MemInt->getMemoryVT(),
6400 MemInt->getMemOperand());
6403 std::vector<SDValue> NewResults;
6404 for (unsigned i = 0; i < NumResultVecs; ++i) {
6405 NewResults.push_back(SDValue(UpdN.getNode(), i));
6407 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs+1)); // chain
6408 DCI.CombineTo(N, NewResults);
6409 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
6416 /// CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a
6417 /// vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic
6418 /// are also VDUPLANEs. If so, combine them to a vldN-dup operation and
6420 static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
6421 SelectionDAG &DAG = DCI.DAG;
6422 EVT VT = N->getValueType(0);
6423 // vldN-dup instructions only support 64-bit vectors for N > 1.
6424 if (!VT.is64BitVector())
6427 // Check if the VDUPLANE operand is a vldN-dup intrinsic.
6428 SDNode *VLD = N->getOperand(0).getNode();
6429 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN)
6431 unsigned NumVecs = 0;
6432 unsigned NewOpc = 0;
6433 unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue();
6434 if (IntNo == Intrinsic::arm_neon_vld2lane) {
6436 NewOpc = ARMISD::VLD2DUP;
6437 } else if (IntNo == Intrinsic::arm_neon_vld3lane) {
6439 NewOpc = ARMISD::VLD3DUP;
6440 } else if (IntNo == Intrinsic::arm_neon_vld4lane) {
6442 NewOpc = ARMISD::VLD4DUP;
6447 // First check that all the vldN-lane uses are VDUPLANEs and that the lane
6448 // numbers match the load.
6449 unsigned VLDLaneNo =
6450 cast<ConstantSDNode>(VLD->getOperand(NumVecs+3))->getZExtValue();
6451 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
6453 // Ignore uses of the chain result.
6454 if (UI.getUse().getResNo() == NumVecs)
6457 if (User->getOpcode() != ARMISD::VDUPLANE ||
6458 VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue())
6462 // Create the vldN-dup node.
6465 for (n = 0; n < NumVecs; ++n)
6467 Tys[n] = MVT::Other;
6468 SDVTList SDTys = DAG.getVTList(Tys, NumVecs+1);
6469 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) };
6470 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD);
6471 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, VLD->getDebugLoc(), SDTys,
6472 Ops, 2, VLDMemInt->getMemoryVT(),
6473 VLDMemInt->getMemOperand());
6476 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
6478 unsigned ResNo = UI.getUse().getResNo();
6479 // Ignore uses of the chain result.
6480 if (ResNo == NumVecs)
6483 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo));
6486 // Now the vldN-lane intrinsic is dead except for its chain result.
6487 // Update uses of the chain.
6488 std::vector<SDValue> VLDDupResults;
6489 for (unsigned n = 0; n < NumVecs; ++n)
6490 VLDDupResults.push_back(SDValue(VLDDup.getNode(), n));
6491 VLDDupResults.push_back(SDValue(VLDDup.getNode(), NumVecs));
6492 DCI.CombineTo(VLD, VLDDupResults);
6497 /// PerformVDUPLANECombine - Target-specific dag combine xforms for
6498 /// ARMISD::VDUPLANE.
6499 static SDValue PerformVDUPLANECombine(SDNode *N,
6500 TargetLowering::DAGCombinerInfo &DCI) {
6501 SDValue Op = N->getOperand(0);
6503 // If the source is a vldN-lane (N > 1) intrinsic, and all the other uses
6504 // of that intrinsic are also VDUPLANEs, combine them to a vldN-dup operation.
6505 if (CombineVLDDUP(N, DCI))
6506 return SDValue(N, 0);
6508 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
6509 // redundant. Ignore bit_converts for now; element sizes are checked below.
6510 while (Op.getOpcode() == ISD::BITCAST)
6511 Op = Op.getOperand(0);
6512 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
6515 // Make sure the VMOV element size is not bigger than the VDUPLANE elements.
6516 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits();
6517 // The canonical VMOV for a zero vector uses a 32-bit element size.
6518 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6520 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
6522 EVT VT = N->getValueType(0);
6523 if (EltSize > VT.getVectorElementType().getSizeInBits())
6526 return DCI.DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
6529 // isConstVecPow2 - Return true if each vector element is a power of 2, all
6530 // elements are the same constant, C, and Log2(C) ranges from 1 to 32.
6531 static bool isConstVecPow2(SDValue ConstVec, bool isSigned, uint64_t &C)
6535 for (unsigned I = 0, E = ConstVec.getValueType().getVectorNumElements();
6537 ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(ConstVec.getOperand(I));
6542 APFloat APF = C->getValueAPF();
6543 if (APF.convertToInteger(&cN, 64, isSigned, APFloat::rmTowardZero, &isExact)
6544 != APFloat::opOK || !isExact)
6547 c0 = (I == 0) ? cN : c0;
6548 if (!isPowerOf2_64(cN) || c0 != cN || Log2_64(c0) < 1 || Log2_64(c0) > 32)
6555 /// PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD)
6556 /// can replace combinations of VMUL and VCVT (floating-point to integer)
6557 /// when the VMUL has a constant operand that is a power of 2.
6559 /// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
6560 /// vmul.f32 d16, d17, d16
6561 /// vcvt.s32.f32 d16, d16
6563 /// vcvt.s32.f32 d16, d16, #3
6564 static SDValue PerformVCVTCombine(SDNode *N,
6565 TargetLowering::DAGCombinerInfo &DCI,
6566 const ARMSubtarget *Subtarget) {
6567 SelectionDAG &DAG = DCI.DAG;
6568 SDValue Op = N->getOperand(0);
6570 if (!Subtarget->hasNEON() || !Op.getValueType().isVector() ||
6571 Op.getOpcode() != ISD::FMUL)
6575 SDValue N0 = Op->getOperand(0);
6576 SDValue ConstVec = Op->getOperand(1);
6577 bool isSigned = N->getOpcode() == ISD::FP_TO_SINT;
6579 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
6580 !isConstVecPow2(ConstVec, isSigned, C))
6583 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfp2fxs :
6584 Intrinsic::arm_neon_vcvtfp2fxu;
6585 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(),
6587 DAG.getConstant(IntrinsicOpcode, MVT::i32), N0,
6588 DAG.getConstant(Log2_64(C), MVT::i32));
6591 /// PerformVDIVCombine - VCVT (fixed-point to floating-point, Advanced SIMD)
6592 /// can replace combinations of VCVT (integer to floating-point) and VDIV
6593 /// when the VDIV has a constant operand that is a power of 2.
6595 /// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
6596 /// vcvt.f32.s32 d16, d16
6597 /// vdiv.f32 d16, d17, d16
6599 /// vcvt.f32.s32 d16, d16, #3
6600 static SDValue PerformVDIVCombine(SDNode *N,
6601 TargetLowering::DAGCombinerInfo &DCI,
6602 const ARMSubtarget *Subtarget) {
6603 SelectionDAG &DAG = DCI.DAG;
6604 SDValue Op = N->getOperand(0);
6605 unsigned OpOpcode = Op.getNode()->getOpcode();
6607 if (!Subtarget->hasNEON() || !N->getValueType(0).isVector() ||
6608 (OpOpcode != ISD::SINT_TO_FP && OpOpcode != ISD::UINT_TO_FP))
6612 SDValue ConstVec = N->getOperand(1);
6613 bool isSigned = OpOpcode == ISD::SINT_TO_FP;
6615 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
6616 !isConstVecPow2(ConstVec, isSigned, C))
6619 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfxs2fp :
6620 Intrinsic::arm_neon_vcvtfxu2fp;
6621 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(),
6623 DAG.getConstant(IntrinsicOpcode, MVT::i32),
6624 Op.getOperand(0), DAG.getConstant(Log2_64(C), MVT::i32));
6627 /// Getvshiftimm - Check if this is a valid build_vector for the immediate
6628 /// operand of a vector shift operation, where all the elements of the
6629 /// build_vector must have the same constant integer value.
6630 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
6631 // Ignore bit_converts.
6632 while (Op.getOpcode() == ISD::BITCAST)
6633 Op = Op.getOperand(0);
6634 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
6635 APInt SplatBits, SplatUndef;
6636 unsigned SplatBitSize;
6638 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
6639 HasAnyUndefs, ElementBits) ||
6640 SplatBitSize > ElementBits)
6642 Cnt = SplatBits.getSExtValue();
6646 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
6647 /// operand of a vector shift left operation. That value must be in the range:
6648 /// 0 <= Value < ElementBits for a left shift; or
6649 /// 0 <= Value <= ElementBits for a long left shift.
6650 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
6651 assert(VT.isVector() && "vector shift count is not a vector type");
6652 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
6653 if (! getVShiftImm(Op, ElementBits, Cnt))
6655 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
6658 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
6659 /// operand of a vector shift right operation. For a shift opcode, the value
6660 /// is positive, but for an intrinsic the value count must be negative. The
6661 /// absolute value must be in the range:
6662 /// 1 <= |Value| <= ElementBits for a right shift; or
6663 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
6664 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
6666 assert(VT.isVector() && "vector shift count is not a vector type");
6667 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
6668 if (! getVShiftImm(Op, ElementBits, Cnt))
6672 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
6675 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
6676 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
6677 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
6680 // Don't do anything for most intrinsics.
6683 // Vector shifts: check for immediate versions and lower them.
6684 // Note: This is done during DAG combining instead of DAG legalizing because
6685 // the build_vectors for 64-bit vector element shift counts are generally
6686 // not legal, and it is hard to see their values after they get legalized to
6687 // loads from a constant pool.
6688 case Intrinsic::arm_neon_vshifts:
6689 case Intrinsic::arm_neon_vshiftu:
6690 case Intrinsic::arm_neon_vshiftls:
6691 case Intrinsic::arm_neon_vshiftlu:
6692 case Intrinsic::arm_neon_vshiftn:
6693 case Intrinsic::arm_neon_vrshifts:
6694 case Intrinsic::arm_neon_vrshiftu:
6695 case Intrinsic::arm_neon_vrshiftn:
6696 case Intrinsic::arm_neon_vqshifts:
6697 case Intrinsic::arm_neon_vqshiftu:
6698 case Intrinsic::arm_neon_vqshiftsu:
6699 case Intrinsic::arm_neon_vqshiftns:
6700 case Intrinsic::arm_neon_vqshiftnu:
6701 case Intrinsic::arm_neon_vqshiftnsu:
6702 case Intrinsic::arm_neon_vqrshiftns:
6703 case Intrinsic::arm_neon_vqrshiftnu:
6704 case Intrinsic::arm_neon_vqrshiftnsu: {
6705 EVT VT = N->getOperand(1).getValueType();
6707 unsigned VShiftOpc = 0;
6710 case Intrinsic::arm_neon_vshifts:
6711 case Intrinsic::arm_neon_vshiftu:
6712 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
6713 VShiftOpc = ARMISD::VSHL;
6716 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
6717 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
6718 ARMISD::VSHRs : ARMISD::VSHRu);
6723 case Intrinsic::arm_neon_vshiftls:
6724 case Intrinsic::arm_neon_vshiftlu:
6725 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
6727 llvm_unreachable("invalid shift count for vshll intrinsic");
6729 case Intrinsic::arm_neon_vrshifts:
6730 case Intrinsic::arm_neon_vrshiftu:
6731 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
6735 case Intrinsic::arm_neon_vqshifts:
6736 case Intrinsic::arm_neon_vqshiftu:
6737 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
6741 case Intrinsic::arm_neon_vqshiftsu:
6742 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
6744 llvm_unreachable("invalid shift count for vqshlu intrinsic");
6746 case Intrinsic::arm_neon_vshiftn:
6747 case Intrinsic::arm_neon_vrshiftn:
6748 case Intrinsic::arm_neon_vqshiftns:
6749 case Intrinsic::arm_neon_vqshiftnu:
6750 case Intrinsic::arm_neon_vqshiftnsu:
6751 case Intrinsic::arm_neon_vqrshiftns:
6752 case Intrinsic::arm_neon_vqrshiftnu:
6753 case Intrinsic::arm_neon_vqrshiftnsu:
6754 // Narrowing shifts require an immediate right shift.
6755 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
6757 llvm_unreachable("invalid shift count for narrowing vector shift "
6761 llvm_unreachable("unhandled vector shift");
6765 case Intrinsic::arm_neon_vshifts:
6766 case Intrinsic::arm_neon_vshiftu:
6767 // Opcode already set above.
6769 case Intrinsic::arm_neon_vshiftls:
6770 case Intrinsic::arm_neon_vshiftlu:
6771 if (Cnt == VT.getVectorElementType().getSizeInBits())
6772 VShiftOpc = ARMISD::VSHLLi;
6774 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
6775 ARMISD::VSHLLs : ARMISD::VSHLLu);
6777 case Intrinsic::arm_neon_vshiftn:
6778 VShiftOpc = ARMISD::VSHRN; break;
6779 case Intrinsic::arm_neon_vrshifts:
6780 VShiftOpc = ARMISD::VRSHRs; break;
6781 case Intrinsic::arm_neon_vrshiftu:
6782 VShiftOpc = ARMISD::VRSHRu; break;
6783 case Intrinsic::arm_neon_vrshiftn:
6784 VShiftOpc = ARMISD::VRSHRN; break;
6785 case Intrinsic::arm_neon_vqshifts:
6786 VShiftOpc = ARMISD::VQSHLs; break;
6787 case Intrinsic::arm_neon_vqshiftu:
6788 VShiftOpc = ARMISD::VQSHLu; break;
6789 case Intrinsic::arm_neon_vqshiftsu:
6790 VShiftOpc = ARMISD::VQSHLsu; break;
6791 case Intrinsic::arm_neon_vqshiftns:
6792 VShiftOpc = ARMISD::VQSHRNs; break;
6793 case Intrinsic::arm_neon_vqshiftnu:
6794 VShiftOpc = ARMISD::VQSHRNu; break;
6795 case Intrinsic::arm_neon_vqshiftnsu:
6796 VShiftOpc = ARMISD::VQSHRNsu; break;
6797 case Intrinsic::arm_neon_vqrshiftns:
6798 VShiftOpc = ARMISD::VQRSHRNs; break;
6799 case Intrinsic::arm_neon_vqrshiftnu:
6800 VShiftOpc = ARMISD::VQRSHRNu; break;
6801 case Intrinsic::arm_neon_vqrshiftnsu:
6802 VShiftOpc = ARMISD::VQRSHRNsu; break;
6805 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
6806 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
6809 case Intrinsic::arm_neon_vshiftins: {
6810 EVT VT = N->getOperand(1).getValueType();
6812 unsigned VShiftOpc = 0;
6814 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
6815 VShiftOpc = ARMISD::VSLI;
6816 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
6817 VShiftOpc = ARMISD::VSRI;
6819 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
6822 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
6823 N->getOperand(1), N->getOperand(2),
6824 DAG.getConstant(Cnt, MVT::i32));
6827 case Intrinsic::arm_neon_vqrshifts:
6828 case Intrinsic::arm_neon_vqrshiftu:
6829 // No immediate versions of these to check for.
6836 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
6837 /// lowers them. As with the vector shift intrinsics, this is done during DAG
6838 /// combining instead of DAG legalizing because the build_vectors for 64-bit
6839 /// vector element shift counts are generally not legal, and it is hard to see
6840 /// their values after they get legalized to loads from a constant pool.
6841 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
6842 const ARMSubtarget *ST) {
6843 EVT VT = N->getValueType(0);
6845 // Nothing to be done for scalar shifts.
6846 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6847 if (!VT.isVector() || !TLI.isTypeLegal(VT))
6850 assert(ST->hasNEON() && "unexpected vector shift");
6853 switch (N->getOpcode()) {
6854 default: llvm_unreachable("unexpected shift opcode");
6857 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
6858 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
6859 DAG.getConstant(Cnt, MVT::i32));
6864 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
6865 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
6866 ARMISD::VSHRs : ARMISD::VSHRu);
6867 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
6868 DAG.getConstant(Cnt, MVT::i32));
6874 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
6875 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
6876 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
6877 const ARMSubtarget *ST) {
6878 SDValue N0 = N->getOperand(0);
6880 // Check for sign- and zero-extensions of vector extract operations of 8-
6881 // and 16-bit vector elements. NEON supports these directly. They are
6882 // handled during DAG combining because type legalization will promote them
6883 // to 32-bit types and it is messy to recognize the operations after that.
6884 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
6885 SDValue Vec = N0.getOperand(0);
6886 SDValue Lane = N0.getOperand(1);
6887 EVT VT = N->getValueType(0);
6888 EVT EltVT = N0.getValueType();
6889 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6891 if (VT == MVT::i32 &&
6892 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
6893 TLI.isTypeLegal(Vec.getValueType()) &&
6894 isa<ConstantSDNode>(Lane)) {
6897 switch (N->getOpcode()) {
6898 default: llvm_unreachable("unexpected opcode");
6899 case ISD::SIGN_EXTEND:
6900 Opc = ARMISD::VGETLANEs;
6902 case ISD::ZERO_EXTEND:
6903 case ISD::ANY_EXTEND:
6904 Opc = ARMISD::VGETLANEu;
6907 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
6914 /// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
6915 /// to match f32 max/min patterns to use NEON vmax/vmin instructions.
6916 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
6917 const ARMSubtarget *ST) {
6918 // If the target supports NEON, try to use vmax/vmin instructions for f32
6919 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set,
6920 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
6921 // a NaN; only do the transformation when it matches that behavior.
6923 // For now only do this when using NEON for FP operations; if using VFP, it
6924 // is not obvious that the benefit outweighs the cost of switching to the
6926 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
6927 N->getValueType(0) != MVT::f32)
6930 SDValue CondLHS = N->getOperand(0);
6931 SDValue CondRHS = N->getOperand(1);
6932 SDValue LHS = N->getOperand(2);
6933 SDValue RHS = N->getOperand(3);
6934 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
6936 unsigned Opcode = 0;
6938 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
6939 IsReversed = false; // x CC y ? x : y
6940 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
6941 IsReversed = true ; // x CC y ? y : x
6955 // If LHS is NaN, an ordered comparison will be false and the result will
6956 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
6957 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
6958 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
6959 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
6961 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
6962 // will return -0, so vmin can only be used for unsafe math or if one of
6963 // the operands is known to be nonzero.
6964 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
6966 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
6968 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
6977 // If LHS is NaN, an ordered comparison will be false and the result will
6978 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
6979 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
6980 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
6981 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
6983 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
6984 // will return +0, so vmax can only be used for unsafe math or if one of
6985 // the operands is known to be nonzero.
6986 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
6988 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
6990 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
6996 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS);
6999 /// PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV.
7001 ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const {
7002 SDValue Cmp = N->getOperand(4);
7003 if (Cmp.getOpcode() != ARMISD::CMPZ)
7004 // Only looking at EQ and NE cases.
7007 EVT VT = N->getValueType(0);
7008 DebugLoc dl = N->getDebugLoc();
7009 SDValue LHS = Cmp.getOperand(0);
7010 SDValue RHS = Cmp.getOperand(1);
7011 SDValue FalseVal = N->getOperand(0);
7012 SDValue TrueVal = N->getOperand(1);
7013 SDValue ARMcc = N->getOperand(2);
7014 ARMCC::CondCodes CC = (ARMCC::CondCodes)cast<ConstantSDNode>(ARMcc)->getZExtValue();
7032 /// FIXME: Turn this into a target neutral optimization?
7034 if (CC == ARMCC::NE && FalseVal == RHS) {
7035 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, TrueVal, ARMcc,
7036 N->getOperand(3), Cmp);
7037 } else if (CC == ARMCC::EQ && TrueVal == RHS) {
7039 SDValue NewCmp = getARMCmp(LHS, RHS, ISD::SETNE, ARMcc, DAG, dl);
7040 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, FalseVal, ARMcc,
7041 N->getOperand(3), NewCmp);
7044 if (Res.getNode()) {
7045 APInt KnownZero, KnownOne;
7046 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
7047 DAG.ComputeMaskedBits(SDValue(N,0), Mask, KnownZero, KnownOne);
7048 // Capture demanded bits information that would be otherwise lost.
7049 if (KnownZero == 0xfffffffe)
7050 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
7051 DAG.getValueType(MVT::i1));
7052 else if (KnownZero == 0xffffff00)
7053 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
7054 DAG.getValueType(MVT::i8));
7055 else if (KnownZero == 0xffff0000)
7056 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
7057 DAG.getValueType(MVT::i16));
7063 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
7064 DAGCombinerInfo &DCI) const {
7065 switch (N->getOpcode()) {
7067 case ISD::ADD: return PerformADDCombine(N, DCI, Subtarget);
7068 case ISD::SUB: return PerformSUBCombine(N, DCI);
7069 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
7070 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
7071 case ISD::AND: return PerformANDCombine(N, DCI);
7072 case ARMISD::BFI: return PerformBFICombine(N, DCI);
7073 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
7074 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
7075 case ISD::STORE: return PerformSTORECombine(N, DCI);
7076 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI);
7077 case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI);
7078 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
7079 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
7080 case ISD::FP_TO_SINT:
7081 case ISD::FP_TO_UINT: return PerformVCVTCombine(N, DCI, Subtarget);
7082 case ISD::FDIV: return PerformVDIVCombine(N, DCI, Subtarget);
7083 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
7086 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
7087 case ISD::SIGN_EXTEND:
7088 case ISD::ZERO_EXTEND:
7089 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
7090 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
7091 case ARMISD::CMOV: return PerformCMOVCombine(N, DCI.DAG);
7092 case ARMISD::VLD2DUP:
7093 case ARMISD::VLD3DUP:
7094 case ARMISD::VLD4DUP:
7095 return CombineBaseUpdate(N, DCI);
7096 case ISD::INTRINSIC_VOID:
7097 case ISD::INTRINSIC_W_CHAIN:
7098 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
7099 case Intrinsic::arm_neon_vld1:
7100 case Intrinsic::arm_neon_vld2:
7101 case Intrinsic::arm_neon_vld3:
7102 case Intrinsic::arm_neon_vld4:
7103 case Intrinsic::arm_neon_vld2lane:
7104 case Intrinsic::arm_neon_vld3lane:
7105 case Intrinsic::arm_neon_vld4lane:
7106 case Intrinsic::arm_neon_vst1:
7107 case Intrinsic::arm_neon_vst2:
7108 case Intrinsic::arm_neon_vst3:
7109 case Intrinsic::arm_neon_vst4:
7110 case Intrinsic::arm_neon_vst2lane:
7111 case Intrinsic::arm_neon_vst3lane:
7112 case Intrinsic::arm_neon_vst4lane:
7113 return CombineBaseUpdate(N, DCI);
7121 bool ARMTargetLowering::isDesirableToTransformToIntegerOp(unsigned Opc,
7123 return (VT == MVT::f32) && (Opc == ISD::LOAD || Opc == ISD::STORE);
7126 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
7127 if (!Subtarget->allowsUnalignedMem())
7130 switch (VT.getSimpleVT().SimpleTy) {
7137 // FIXME: VLD1 etc with standard alignment is legal.
7141 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
7146 switch (VT.getSimpleVT().SimpleTy) {
7147 default: return false;
7162 if ((V & (Scale - 1)) != 0)
7165 return V == (V & ((1LL << 5) - 1));
7168 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
7169 const ARMSubtarget *Subtarget) {
7176 switch (VT.getSimpleVT().SimpleTy) {
7177 default: return false;
7182 // + imm12 or - imm8
7184 return V == (V & ((1LL << 8) - 1));
7185 return V == (V & ((1LL << 12) - 1));
7188 // Same as ARM mode. FIXME: NEON?
7189 if (!Subtarget->hasVFP2())
7194 return V == (V & ((1LL << 8) - 1));
7198 /// isLegalAddressImmediate - Return true if the integer value can be used
7199 /// as the offset of the target addressing mode for load / store of the
7201 static bool isLegalAddressImmediate(int64_t V, EVT VT,
7202 const ARMSubtarget *Subtarget) {
7209 if (Subtarget->isThumb1Only())
7210 return isLegalT1AddressImmediate(V, VT);
7211 else if (Subtarget->isThumb2())
7212 return isLegalT2AddressImmediate(V, VT, Subtarget);
7217 switch (VT.getSimpleVT().SimpleTy) {
7218 default: return false;
7223 return V == (V & ((1LL << 12) - 1));
7226 return V == (V & ((1LL << 8) - 1));
7229 if (!Subtarget->hasVFP2()) // FIXME: NEON?
7234 return V == (V & ((1LL << 8) - 1));
7238 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
7240 int Scale = AM.Scale;
7244 switch (VT.getSimpleVT().SimpleTy) {
7245 default: return false;
7254 return Scale == 2 || Scale == 4 || Scale == 8;
7257 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
7261 // Note, we allow "void" uses (basically, uses that aren't loads or
7262 // stores), because arm allows folding a scale into many arithmetic
7263 // operations. This should be made more precise and revisited later.
7265 // Allow r << imm, but the imm has to be a multiple of two.
7266 if (Scale & 1) return false;
7267 return isPowerOf2_32(Scale);
7271 /// isLegalAddressingMode - Return true if the addressing mode represented
7272 /// by AM is legal for this target, for a load/store of the specified type.
7273 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
7275 EVT VT = getValueType(Ty, true);
7276 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
7279 // Can never fold addr of global into load/store.
7284 case 0: // no scale reg, must be "r+i" or "r", or "i".
7287 if (Subtarget->isThumb1Only())
7291 // ARM doesn't support any R+R*scale+imm addr modes.
7298 if (Subtarget->isThumb2())
7299 return isLegalT2ScaledAddressingMode(AM, VT);
7301 int Scale = AM.Scale;
7302 switch (VT.getSimpleVT().SimpleTy) {
7303 default: return false;
7307 if (Scale < 0) Scale = -Scale;
7311 return isPowerOf2_32(Scale & ~1);
7315 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
7320 // Note, we allow "void" uses (basically, uses that aren't loads or
7321 // stores), because arm allows folding a scale into many arithmetic
7322 // operations. This should be made more precise and revisited later.
7324 // Allow r << imm, but the imm has to be a multiple of two.
7325 if (Scale & 1) return false;
7326 return isPowerOf2_32(Scale);
7333 /// isLegalICmpImmediate - Return true if the specified immediate is legal
7334 /// icmp immediate, that is the target has icmp instructions which can compare
7335 /// a register against the immediate without having to materialize the
7336 /// immediate into a register.
7337 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
7338 if (!Subtarget->isThumb())
7339 return ARM_AM::getSOImmVal(Imm) != -1;
7340 if (Subtarget->isThumb2())
7341 return ARM_AM::getT2SOImmVal(Imm) != -1;
7342 return Imm >= 0 && Imm <= 255;
7345 /// isLegalAddImmediate - Return true if the specified immediate is legal
7346 /// add immediate, that is the target has add instructions which can add
7347 /// a register with the immediate without having to materialize the
7348 /// immediate into a register.
7349 bool ARMTargetLowering::isLegalAddImmediate(int64_t Imm) const {
7350 return ARM_AM::getSOImmVal(Imm) != -1;
7353 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
7354 bool isSEXTLoad, SDValue &Base,
7355 SDValue &Offset, bool &isInc,
7356 SelectionDAG &DAG) {
7357 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
7360 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
7362 Base = Ptr->getOperand(0);
7363 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
7364 int RHSC = (int)RHS->getZExtValue();
7365 if (RHSC < 0 && RHSC > -256) {
7366 assert(Ptr->getOpcode() == ISD::ADD);
7368 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
7372 isInc = (Ptr->getOpcode() == ISD::ADD);
7373 Offset = Ptr->getOperand(1);
7375 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
7377 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
7378 int RHSC = (int)RHS->getZExtValue();
7379 if (RHSC < 0 && RHSC > -0x1000) {
7380 assert(Ptr->getOpcode() == ISD::ADD);
7382 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
7383 Base = Ptr->getOperand(0);
7388 if (Ptr->getOpcode() == ISD::ADD) {
7390 ARM_AM::ShiftOpc ShOpcVal=
7391 ARM_AM::getShiftOpcForNode(Ptr->getOperand(0).getOpcode());
7392 if (ShOpcVal != ARM_AM::no_shift) {
7393 Base = Ptr->getOperand(1);
7394 Offset = Ptr->getOperand(0);
7396 Base = Ptr->getOperand(0);
7397 Offset = Ptr->getOperand(1);
7402 isInc = (Ptr->getOpcode() == ISD::ADD);
7403 Base = Ptr->getOperand(0);
7404 Offset = Ptr->getOperand(1);
7408 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
7412 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
7413 bool isSEXTLoad, SDValue &Base,
7414 SDValue &Offset, bool &isInc,
7415 SelectionDAG &DAG) {
7416 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
7419 Base = Ptr->getOperand(0);
7420 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
7421 int RHSC = (int)RHS->getZExtValue();
7422 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
7423 assert(Ptr->getOpcode() == ISD::ADD);
7425 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
7427 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
7428 isInc = Ptr->getOpcode() == ISD::ADD;
7429 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
7437 /// getPreIndexedAddressParts - returns true by value, base pointer and
7438 /// offset pointer and addressing mode by reference if the node's address
7439 /// can be legally represented as pre-indexed load / store address.
7441 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
7443 ISD::MemIndexedMode &AM,
7444 SelectionDAG &DAG) const {
7445 if (Subtarget->isThumb1Only())
7450 bool isSEXTLoad = false;
7451 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
7452 Ptr = LD->getBasePtr();
7453 VT = LD->getMemoryVT();
7454 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
7455 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
7456 Ptr = ST->getBasePtr();
7457 VT = ST->getMemoryVT();
7462 bool isLegal = false;
7463 if (Subtarget->isThumb2())
7464 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
7465 Offset, isInc, DAG);
7467 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
7468 Offset, isInc, DAG);
7472 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
7476 /// getPostIndexedAddressParts - returns true by value, base pointer and
7477 /// offset pointer and addressing mode by reference if this node can be
7478 /// combined with a load / store to form a post-indexed load / store.
7479 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
7482 ISD::MemIndexedMode &AM,
7483 SelectionDAG &DAG) const {
7484 if (Subtarget->isThumb1Only())
7489 bool isSEXTLoad = false;
7490 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
7491 VT = LD->getMemoryVT();
7492 Ptr = LD->getBasePtr();
7493 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
7494 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
7495 VT = ST->getMemoryVT();
7496 Ptr = ST->getBasePtr();
7501 bool isLegal = false;
7502 if (Subtarget->isThumb2())
7503 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
7506 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
7512 // Swap base ptr and offset to catch more post-index load / store when
7513 // it's legal. In Thumb2 mode, offset must be an immediate.
7514 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
7515 !Subtarget->isThumb2())
7516 std::swap(Base, Offset);
7518 // Post-indexed load / store update the base pointer.
7523 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
7527 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
7531 const SelectionDAG &DAG,
7532 unsigned Depth) const {
7533 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
7534 switch (Op.getOpcode()) {
7536 case ARMISD::CMOV: {
7537 // Bits are known zero/one if known on the LHS and RHS.
7538 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
7539 if (KnownZero == 0 && KnownOne == 0) return;
7541 APInt KnownZeroRHS, KnownOneRHS;
7542 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
7543 KnownZeroRHS, KnownOneRHS, Depth+1);
7544 KnownZero &= KnownZeroRHS;
7545 KnownOne &= KnownOneRHS;
7551 //===----------------------------------------------------------------------===//
7552 // ARM Inline Assembly Support
7553 //===----------------------------------------------------------------------===//
7555 bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const {
7556 // Looking for "rev" which is V6+.
7557 if (!Subtarget->hasV6Ops())
7560 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
7561 std::string AsmStr = IA->getAsmString();
7562 SmallVector<StringRef, 4> AsmPieces;
7563 SplitString(AsmStr, AsmPieces, ";\n");
7565 switch (AsmPieces.size()) {
7566 default: return false;
7568 AsmStr = AsmPieces[0];
7570 SplitString(AsmStr, AsmPieces, " \t,");
7573 if (AsmPieces.size() == 3 &&
7574 AsmPieces[0] == "rev" && AsmPieces[1] == "$0" && AsmPieces[2] == "$1" &&
7575 IA->getConstraintString().compare(0, 4, "=l,l") == 0) {
7576 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
7577 if (Ty && Ty->getBitWidth() == 32)
7578 return IntrinsicLowering::LowerToByteSwap(CI);
7586 /// getConstraintType - Given a constraint letter, return the type of
7587 /// constraint it is for this target.
7588 ARMTargetLowering::ConstraintType
7589 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
7590 if (Constraint.size() == 1) {
7591 switch (Constraint[0]) {
7593 case 'l': return C_RegisterClass;
7594 case 'w': return C_RegisterClass;
7595 case 'h': return C_RegisterClass;
7596 case 'x': return C_RegisterClass;
7597 case 't': return C_RegisterClass;
7598 case 'j': return C_Other; // Constant for movw.
7600 } else if (Constraint.size() == 2) {
7601 switch (Constraint[0]) {
7603 // All 'U+' constraints are addresses.
7604 case 'U': return C_Memory;
7607 return TargetLowering::getConstraintType(Constraint);
7610 /// Examine constraint type and operand type and determine a weight value.
7611 /// This object must already have been set up with the operand type
7612 /// and the current alternative constraint selected.
7613 TargetLowering::ConstraintWeight
7614 ARMTargetLowering::getSingleConstraintMatchWeight(
7615 AsmOperandInfo &info, const char *constraint) const {
7616 ConstraintWeight weight = CW_Invalid;
7617 Value *CallOperandVal = info.CallOperandVal;
7618 // If we don't have a value, we can't do a match,
7619 // but allow it at the lowest weight.
7620 if (CallOperandVal == NULL)
7622 Type *type = CallOperandVal->getType();
7623 // Look at the constraint type.
7624 switch (*constraint) {
7626 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
7629 if (type->isIntegerTy()) {
7630 if (Subtarget->isThumb())
7631 weight = CW_SpecificReg;
7633 weight = CW_Register;
7637 if (type->isFloatingPointTy())
7638 weight = CW_Register;
7644 typedef std::pair<unsigned, const TargetRegisterClass*> RCPair;
7646 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
7648 if (Constraint.size() == 1) {
7649 // GCC ARM Constraint Letters
7650 switch (Constraint[0]) {
7651 case 'l': // Low regs or general regs.
7652 if (Subtarget->isThumb())
7653 return RCPair(0U, ARM::tGPRRegisterClass);
7655 return RCPair(0U, ARM::GPRRegisterClass);
7656 case 'h': // High regs or no regs.
7657 if (Subtarget->isThumb())
7658 return RCPair(0U, ARM::hGPRRegisterClass);
7661 return RCPair(0U, ARM::GPRRegisterClass);
7664 return RCPair(0U, ARM::SPRRegisterClass);
7665 if (VT.getSizeInBits() == 64)
7666 return RCPair(0U, ARM::DPRRegisterClass);
7667 if (VT.getSizeInBits() == 128)
7668 return RCPair(0U, ARM::QPRRegisterClass);
7672 return RCPair(0U, ARM::SPR_8RegisterClass);
7673 if (VT.getSizeInBits() == 64)
7674 return RCPair(0U, ARM::DPR_8RegisterClass);
7675 if (VT.getSizeInBits() == 128)
7676 return RCPair(0U, ARM::QPR_8RegisterClass);
7680 return RCPair(0U, ARM::SPRRegisterClass);
7684 if (StringRef("{cc}").equals_lower(Constraint))
7685 return std::make_pair(unsigned(ARM::CPSR), ARM::CCRRegisterClass);
7687 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
7690 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
7691 /// vector. If it is invalid, don't add anything to Ops.
7692 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
7693 std::string &Constraint,
7694 std::vector<SDValue>&Ops,
7695 SelectionDAG &DAG) const {
7696 SDValue Result(0, 0);
7698 // Currently only support length 1 constraints.
7699 if (Constraint.length() != 1) return;
7701 char ConstraintLetter = Constraint[0];
7702 switch (ConstraintLetter) {
7705 case 'I': case 'J': case 'K': case 'L':
7706 case 'M': case 'N': case 'O':
7707 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
7711 int64_t CVal64 = C->getSExtValue();
7712 int CVal = (int) CVal64;
7713 // None of these constraints allow values larger than 32 bits. Check
7714 // that the value fits in an int.
7718 switch (ConstraintLetter) {
7720 // Constant suitable for movw, must be between 0 and
7722 if (Subtarget->hasV6T2Ops())
7723 if (CVal >= 0 && CVal <= 65535)
7727 if (Subtarget->isThumb1Only()) {
7728 // This must be a constant between 0 and 255, for ADD
7730 if (CVal >= 0 && CVal <= 255)
7732 } else if (Subtarget->isThumb2()) {
7733 // A constant that can be used as an immediate value in a
7734 // data-processing instruction.
7735 if (ARM_AM::getT2SOImmVal(CVal) != -1)
7738 // A constant that can be used as an immediate value in a
7739 // data-processing instruction.
7740 if (ARM_AM::getSOImmVal(CVal) != -1)
7746 if (Subtarget->isThumb()) { // FIXME thumb2
7747 // This must be a constant between -255 and -1, for negated ADD
7748 // immediates. This can be used in GCC with an "n" modifier that
7749 // prints the negated value, for use with SUB instructions. It is
7750 // not useful otherwise but is implemented for compatibility.
7751 if (CVal >= -255 && CVal <= -1)
7754 // This must be a constant between -4095 and 4095. It is not clear
7755 // what this constraint is intended for. Implemented for
7756 // compatibility with GCC.
7757 if (CVal >= -4095 && CVal <= 4095)
7763 if (Subtarget->isThumb1Only()) {
7764 // A 32-bit value where only one byte has a nonzero value. Exclude
7765 // zero to match GCC. This constraint is used by GCC internally for
7766 // constants that can be loaded with a move/shift combination.
7767 // It is not useful otherwise but is implemented for compatibility.
7768 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
7770 } else if (Subtarget->isThumb2()) {
7771 // A constant whose bitwise inverse can be used as an immediate
7772 // value in a data-processing instruction. This can be used in GCC
7773 // with a "B" modifier that prints the inverted value, for use with
7774 // BIC and MVN instructions. It is not useful otherwise but is
7775 // implemented for compatibility.
7776 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
7779 // A constant whose bitwise inverse can be used as an immediate
7780 // value in a data-processing instruction. This can be used in GCC
7781 // with a "B" modifier that prints the inverted value, for use with
7782 // BIC and MVN instructions. It is not useful otherwise but is
7783 // implemented for compatibility.
7784 if (ARM_AM::getSOImmVal(~CVal) != -1)
7790 if (Subtarget->isThumb1Only()) {
7791 // This must be a constant between -7 and 7,
7792 // for 3-operand ADD/SUB immediate instructions.
7793 if (CVal >= -7 && CVal < 7)
7795 } else if (Subtarget->isThumb2()) {
7796 // A constant whose negation can be used as an immediate value in a
7797 // data-processing instruction. This can be used in GCC with an "n"
7798 // modifier that prints the negated value, for use with SUB
7799 // instructions. It is not useful otherwise but is implemented for
7801 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
7804 // A constant whose negation can be used as an immediate value in a
7805 // data-processing instruction. This can be used in GCC with an "n"
7806 // modifier that prints the negated value, for use with SUB
7807 // instructions. It is not useful otherwise but is implemented for
7809 if (ARM_AM::getSOImmVal(-CVal) != -1)
7815 if (Subtarget->isThumb()) { // FIXME thumb2
7816 // This must be a multiple of 4 between 0 and 1020, for
7817 // ADD sp + immediate.
7818 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
7821 // A power of two or a constant between 0 and 32. This is used in
7822 // GCC for the shift amount on shifted register operands, but it is
7823 // useful in general for any shift amounts.
7824 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
7830 if (Subtarget->isThumb()) { // FIXME thumb2
7831 // This must be a constant between 0 and 31, for shift amounts.
7832 if (CVal >= 0 && CVal <= 31)
7838 if (Subtarget->isThumb()) { // FIXME thumb2
7839 // This must be a multiple of 4 between -508 and 508, for
7840 // ADD/SUB sp = sp + immediate.
7841 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
7846 Result = DAG.getTargetConstant(CVal, Op.getValueType());
7850 if (Result.getNode()) {
7851 Ops.push_back(Result);
7854 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
7858 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
7859 // The ARM target isn't yet aware of offsets.
7863 int ARM::getVFPf32Imm(const APFloat &FPImm) {
7864 APInt Imm = FPImm.bitcastToAPInt();
7865 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
7866 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127
7867 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits
7869 // We can handle 4 bits of mantissa.
7870 // mantissa = (16+UInt(e:f:g:h))/16.
7871 if (Mantissa & 0x7ffff)
7874 if ((Mantissa & 0xf) != Mantissa)
7877 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
7878 if (Exp < -3 || Exp > 4)
7880 Exp = ((Exp+3) & 0x7) ^ 4;
7882 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
7885 int ARM::getVFPf64Imm(const APFloat &FPImm) {
7886 APInt Imm = FPImm.bitcastToAPInt();
7887 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
7888 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
7889 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffLL;
7891 // We can handle 4 bits of mantissa.
7892 // mantissa = (16+UInt(e:f:g:h))/16.
7893 if (Mantissa & 0xffffffffffffLL)
7896 if ((Mantissa & 0xf) != Mantissa)
7899 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
7900 if (Exp < -3 || Exp > 4)
7902 Exp = ((Exp+3) & 0x7) ^ 4;
7904 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
7907 bool ARM::isBitFieldInvertedMask(unsigned v) {
7908 if (v == 0xffffffff)
7910 // there can be 1's on either or both "outsides", all the "inside"
7912 unsigned int lsb = 0, msb = 31;
7913 while (v & (1 << msb)) --msb;
7914 while (v & (1 << lsb)) ++lsb;
7915 for (unsigned int i = lsb; i <= msb; ++i) {
7922 /// isFPImmLegal - Returns true if the target can instruction select the
7923 /// specified FP immediate natively. If false, the legalizer will
7924 /// materialize the FP immediate as a load from a constant pool.
7925 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
7926 if (!Subtarget->hasVFP3())
7929 return ARM::getVFPf32Imm(Imm) != -1;
7931 return ARM::getVFPf64Imm(Imm) != -1;
7935 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
7936 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
7937 /// specified in the intrinsic calls.
7938 bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
7940 unsigned Intrinsic) const {
7941 switch (Intrinsic) {
7942 case Intrinsic::arm_neon_vld1:
7943 case Intrinsic::arm_neon_vld2:
7944 case Intrinsic::arm_neon_vld3:
7945 case Intrinsic::arm_neon_vld4:
7946 case Intrinsic::arm_neon_vld2lane:
7947 case Intrinsic::arm_neon_vld3lane:
7948 case Intrinsic::arm_neon_vld4lane: {
7949 Info.opc = ISD::INTRINSIC_W_CHAIN;
7950 // Conservatively set memVT to the entire set of vectors loaded.
7951 uint64_t NumElts = getTargetData()->getTypeAllocSize(I.getType()) / 8;
7952 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
7953 Info.ptrVal = I.getArgOperand(0);
7955 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
7956 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
7957 Info.vol = false; // volatile loads with NEON intrinsics not supported
7958 Info.readMem = true;
7959 Info.writeMem = false;
7962 case Intrinsic::arm_neon_vst1:
7963 case Intrinsic::arm_neon_vst2:
7964 case Intrinsic::arm_neon_vst3:
7965 case Intrinsic::arm_neon_vst4:
7966 case Intrinsic::arm_neon_vst2lane:
7967 case Intrinsic::arm_neon_vst3lane:
7968 case Intrinsic::arm_neon_vst4lane: {
7969 Info.opc = ISD::INTRINSIC_VOID;
7970 // Conservatively set memVT to the entire set of vectors stored.
7971 unsigned NumElts = 0;
7972 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
7973 Type *ArgTy = I.getArgOperand(ArgI)->getType();
7974 if (!ArgTy->isVectorTy())
7976 NumElts += getTargetData()->getTypeAllocSize(ArgTy) / 8;
7978 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
7979 Info.ptrVal = I.getArgOperand(0);
7981 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
7982 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
7983 Info.vol = false; // volatile stores with NEON intrinsics not supported
7984 Info.readMem = false;
7985 Info.writeMem = true;
7988 case Intrinsic::arm_strexd: {
7989 Info.opc = ISD::INTRINSIC_W_CHAIN;
7990 Info.memVT = MVT::i64;
7991 Info.ptrVal = I.getArgOperand(2);
7995 Info.readMem = false;
7996 Info.writeMem = true;
7999 case Intrinsic::arm_ldrexd: {
8000 Info.opc = ISD::INTRINSIC_W_CHAIN;
8001 Info.memVT = MVT::i64;
8002 Info.ptrVal = I.getArgOperand(0);
8006 Info.readMem = true;
8007 Info.writeMem = false;