1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "ARMAddressingModes.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMISelLowering.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMPerfectShuffle.h"
21 #include "ARMRegisterInfo.h"
22 #include "ARMSubtarget.h"
23 #include "ARMTargetMachine.h"
24 #include "ARMTargetObjectFile.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/Constants.h"
27 #include "llvm/Function.h"
28 #include "llvm/Instruction.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/GlobalValue.h"
31 #include "llvm/CodeGen/CallingConvLower.h"
32 #include "llvm/CodeGen/MachineBasicBlock.h"
33 #include "llvm/CodeGen/MachineFrameInfo.h"
34 #include "llvm/CodeGen/MachineFunction.h"
35 #include "llvm/CodeGen/MachineInstrBuilder.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/CodeGen/PseudoSourceValue.h"
38 #include "llvm/CodeGen/SelectionDAG.h"
39 #include "llvm/Target/TargetOptions.h"
40 #include "llvm/ADT/VectorExtras.h"
41 #include "llvm/Support/ErrorHandling.h"
42 #include "llvm/Support/MathExtras.h"
45 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
46 CCValAssign::LocInfo &LocInfo,
47 ISD::ArgFlagsTy &ArgFlags,
49 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
50 CCValAssign::LocInfo &LocInfo,
51 ISD::ArgFlagsTy &ArgFlags,
53 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
54 CCValAssign::LocInfo &LocInfo,
55 ISD::ArgFlagsTy &ArgFlags,
57 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
58 CCValAssign::LocInfo &LocInfo,
59 ISD::ArgFlagsTy &ArgFlags,
62 void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
63 EVT PromotedBitwiseVT) {
64 if (VT != PromotedLdStVT) {
65 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
66 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
67 PromotedLdStVT.getSimpleVT());
69 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
70 AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
71 PromotedLdStVT.getSimpleVT());
74 EVT ElemTy = VT.getVectorElementType();
75 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
76 setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
77 if (ElemTy == MVT::i8 || ElemTy == MVT::i16)
78 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
79 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
80 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
81 setOperationAction(ISD::SCALAR_TO_VECTOR, VT.getSimpleVT(), Expand);
82 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Custom);
83 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Expand);
85 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
86 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
87 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
90 // Promote all bit-wise operations.
91 if (VT.isInteger() && VT != PromotedBitwiseVT) {
92 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
93 AddPromotedToType (ISD::AND, VT.getSimpleVT(),
94 PromotedBitwiseVT.getSimpleVT());
95 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
96 AddPromotedToType (ISD::OR, VT.getSimpleVT(),
97 PromotedBitwiseVT.getSimpleVT());
98 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
99 AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
100 PromotedBitwiseVT.getSimpleVT());
104 void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
105 addRegisterClass(VT, ARM::DPRRegisterClass);
106 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
109 void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
110 addRegisterClass(VT, ARM::QPRRegisterClass);
111 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
114 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
115 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
116 return new TargetLoweringObjectFileMachO();
117 return new ARMElfTargetObjectFile();
120 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
121 : TargetLowering(TM, createTLOF(TM)), ARMPCLabelIndex(0) {
122 Subtarget = &TM.getSubtarget<ARMSubtarget>();
124 if (Subtarget->isTargetDarwin()) {
125 // Uses VFP for Thumb libfuncs if available.
126 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
127 // Single-precision floating-point arithmetic.
128 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
129 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
130 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
131 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
133 // Double-precision floating-point arithmetic.
134 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
135 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
136 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
137 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
139 // Single-precision comparisons.
140 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
141 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
142 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
143 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
144 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
145 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
146 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
147 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
149 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
150 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
151 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
152 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
153 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
154 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
155 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
156 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
158 // Double-precision comparisons.
159 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
160 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
161 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
162 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
163 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
164 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
165 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
166 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
168 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
169 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
170 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
171 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
172 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
173 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
174 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
175 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
177 // Floating-point to integer conversions.
178 // i64 conversions are done via library routines even when generating VFP
179 // instructions, so use the same ones.
180 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
181 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
182 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
183 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
185 // Conversions between floating types.
186 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
187 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
189 // Integer to floating-point conversions.
190 // i64 conversions are done via library routines even when generating VFP
191 // instructions, so use the same ones.
192 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
193 // e.g., __floatunsidf vs. __floatunssidfvfp.
194 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
195 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
196 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
197 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
201 // These libcalls are not available in 32-bit.
202 setLibcallName(RTLIB::SHL_I128, 0);
203 setLibcallName(RTLIB::SRL_I128, 0);
204 setLibcallName(RTLIB::SRA_I128, 0);
206 // Libcalls should use the AAPCS base standard ABI, even if hard float
207 // is in effect, as per the ARM RTABI specification, section 4.1.2.
208 if (Subtarget->isAAPCS_ABI()) {
209 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
210 setLibcallCallingConv(static_cast<RTLIB::Libcall>(i),
211 CallingConv::ARM_AAPCS);
215 if (Subtarget->isThumb1Only())
216 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
218 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
219 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
220 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
221 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
223 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
226 if (Subtarget->hasNEON()) {
227 addDRTypeForNEON(MVT::v2f32);
228 addDRTypeForNEON(MVT::v8i8);
229 addDRTypeForNEON(MVT::v4i16);
230 addDRTypeForNEON(MVT::v2i32);
231 addDRTypeForNEON(MVT::v1i64);
233 addQRTypeForNEON(MVT::v4f32);
234 addQRTypeForNEON(MVT::v2f64);
235 addQRTypeForNEON(MVT::v16i8);
236 addQRTypeForNEON(MVT::v8i16);
237 addQRTypeForNEON(MVT::v4i32);
238 addQRTypeForNEON(MVT::v2i64);
240 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
241 setTargetDAGCombine(ISD::SHL);
242 setTargetDAGCombine(ISD::SRL);
243 setTargetDAGCombine(ISD::SRA);
244 setTargetDAGCombine(ISD::SIGN_EXTEND);
245 setTargetDAGCombine(ISD::ZERO_EXTEND);
246 setTargetDAGCombine(ISD::ANY_EXTEND);
249 computeRegisterProperties();
251 // ARM does not have f32 extending load.
252 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
254 // ARM does not have i1 sign extending load.
255 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
257 // ARM supports all 4 flavors of integer indexed load / store.
258 if (!Subtarget->isThumb1Only()) {
259 for (unsigned im = (unsigned)ISD::PRE_INC;
260 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
261 setIndexedLoadAction(im, MVT::i1, Legal);
262 setIndexedLoadAction(im, MVT::i8, Legal);
263 setIndexedLoadAction(im, MVT::i16, Legal);
264 setIndexedLoadAction(im, MVT::i32, Legal);
265 setIndexedStoreAction(im, MVT::i1, Legal);
266 setIndexedStoreAction(im, MVT::i8, Legal);
267 setIndexedStoreAction(im, MVT::i16, Legal);
268 setIndexedStoreAction(im, MVT::i32, Legal);
272 // i64 operation support.
273 if (Subtarget->isThumb1Only()) {
274 setOperationAction(ISD::MUL, MVT::i64, Expand);
275 setOperationAction(ISD::MULHU, MVT::i32, Expand);
276 setOperationAction(ISD::MULHS, MVT::i32, Expand);
277 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
278 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
280 setOperationAction(ISD::MUL, MVT::i64, Expand);
281 setOperationAction(ISD::MULHU, MVT::i32, Expand);
282 if (!Subtarget->hasV6Ops())
283 setOperationAction(ISD::MULHS, MVT::i32, Expand);
285 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
286 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
287 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
288 setOperationAction(ISD::SRL, MVT::i64, Custom);
289 setOperationAction(ISD::SRA, MVT::i64, Custom);
291 // ARM does not have ROTL.
292 setOperationAction(ISD::ROTL, MVT::i32, Expand);
293 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
294 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
295 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
296 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
298 // Only ARMv6 has BSWAP.
299 if (!Subtarget->hasV6Ops())
300 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
302 // These are expanded into libcalls.
303 setOperationAction(ISD::SDIV, MVT::i32, Expand);
304 setOperationAction(ISD::UDIV, MVT::i32, Expand);
305 setOperationAction(ISD::SREM, MVT::i32, Expand);
306 setOperationAction(ISD::UREM, MVT::i32, Expand);
307 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
308 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
310 // Support label based line numbers.
311 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
312 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
314 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
315 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
316 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
317 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
319 // Use the default implementation.
320 setOperationAction(ISD::VASTART, MVT::Other, Custom);
321 setOperationAction(ISD::VAARG, MVT::Other, Expand);
322 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
323 setOperationAction(ISD::VAEND, MVT::Other, Expand);
324 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
325 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
326 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
327 // FIXME: Shouldn't need this, since no register is used, but the legalizer
328 // doesn't yet know how to not do that for SjLj.
329 setExceptionSelectorRegister(ARM::R0);
330 if (Subtarget->isThumb())
331 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
333 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
334 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
336 if (!Subtarget->hasV6Ops() && !Subtarget->isThumb2()) {
337 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
338 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
340 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
342 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only())
343 // Turn f64->i64 into FMRRD, i64 -> f64 to FMDRR iff target supports vfp2.
344 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
346 // We want to custom lower some of our intrinsics.
347 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
348 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
349 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
351 setOperationAction(ISD::SETCC, MVT::i32, Expand);
352 setOperationAction(ISD::SETCC, MVT::f32, Expand);
353 setOperationAction(ISD::SETCC, MVT::f64, Expand);
354 setOperationAction(ISD::SELECT, MVT::i32, Expand);
355 setOperationAction(ISD::SELECT, MVT::f32, Expand);
356 setOperationAction(ISD::SELECT, MVT::f64, Expand);
357 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
358 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
359 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
361 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
362 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
363 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
364 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
365 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
367 // We don't support sin/cos/fmod/copysign/pow
368 setOperationAction(ISD::FSIN, MVT::f64, Expand);
369 setOperationAction(ISD::FSIN, MVT::f32, Expand);
370 setOperationAction(ISD::FCOS, MVT::f32, Expand);
371 setOperationAction(ISD::FCOS, MVT::f64, Expand);
372 setOperationAction(ISD::FREM, MVT::f64, Expand);
373 setOperationAction(ISD::FREM, MVT::f32, Expand);
374 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
375 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
376 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
378 setOperationAction(ISD::FPOW, MVT::f64, Expand);
379 setOperationAction(ISD::FPOW, MVT::f32, Expand);
381 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
382 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
383 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
384 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
385 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
386 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
389 // We have target-specific dag combine patterns for the following nodes:
390 // ARMISD::FMRRD - No need to call setTargetDAGCombine
391 setTargetDAGCombine(ISD::ADD);
392 setTargetDAGCombine(ISD::SUB);
394 setStackPointerRegisterToSaveRestore(ARM::SP);
395 setSchedulingPreference(SchedulingForRegPressure);
397 // FIXME: If-converter should use instruction latency to determine
398 // profitability rather than relying on fixed limits.
399 if (Subtarget->getCPUString() == "generic") {
400 // Generic (and overly aggressive) if-conversion limits.
401 setIfCvtBlockSizeLimit(10);
402 setIfCvtDupBlockSizeLimit(2);
403 } else if (Subtarget->hasV6Ops()) {
404 setIfCvtBlockSizeLimit(2);
405 setIfCvtDupBlockSizeLimit(1);
407 setIfCvtBlockSizeLimit(3);
408 setIfCvtDupBlockSizeLimit(2);
411 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
412 // Do not enable CodePlacementOpt for now: it currently runs after the
413 // ARMConstantIslandPass and messes up branch relaxation and placement
414 // of constant islands.
415 // benefitFromCodePlacementOpt = true;
418 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
421 case ARMISD::Wrapper: return "ARMISD::Wrapper";
422 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
423 case ARMISD::CALL: return "ARMISD::CALL";
424 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
425 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
426 case ARMISD::tCALL: return "ARMISD::tCALL";
427 case ARMISD::BRCOND: return "ARMISD::BRCOND";
428 case ARMISD::BR_JT: return "ARMISD::BR_JT";
429 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
430 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
431 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
432 case ARMISD::CMP: return "ARMISD::CMP";
433 case ARMISD::CMPZ: return "ARMISD::CMPZ";
434 case ARMISD::CMPFP: return "ARMISD::CMPFP";
435 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
436 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
437 case ARMISD::CMOV: return "ARMISD::CMOV";
438 case ARMISD::CNEG: return "ARMISD::CNEG";
440 case ARMISD::FTOSI: return "ARMISD::FTOSI";
441 case ARMISD::FTOUI: return "ARMISD::FTOUI";
442 case ARMISD::SITOF: return "ARMISD::SITOF";
443 case ARMISD::UITOF: return "ARMISD::UITOF";
445 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
446 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
447 case ARMISD::RRX: return "ARMISD::RRX";
449 case ARMISD::FMRRD: return "ARMISD::FMRRD";
450 case ARMISD::FMDRR: return "ARMISD::FMDRR";
452 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
454 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
456 case ARMISD::VCEQ: return "ARMISD::VCEQ";
457 case ARMISD::VCGE: return "ARMISD::VCGE";
458 case ARMISD::VCGEU: return "ARMISD::VCGEU";
459 case ARMISD::VCGT: return "ARMISD::VCGT";
460 case ARMISD::VCGTU: return "ARMISD::VCGTU";
461 case ARMISD::VTST: return "ARMISD::VTST";
463 case ARMISD::VSHL: return "ARMISD::VSHL";
464 case ARMISD::VSHRs: return "ARMISD::VSHRs";
465 case ARMISD::VSHRu: return "ARMISD::VSHRu";
466 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
467 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
468 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
469 case ARMISD::VSHRN: return "ARMISD::VSHRN";
470 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
471 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
472 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
473 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
474 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
475 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
476 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
477 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
478 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
479 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
480 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
481 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
482 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
483 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
484 case ARMISD::VDUP: return "ARMISD::VDUP";
485 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
486 case ARMISD::VLD2D: return "ARMISD::VLD2D";
487 case ARMISD::VLD3D: return "ARMISD::VLD3D";
488 case ARMISD::VLD4D: return "ARMISD::VLD4D";
489 case ARMISD::VST2D: return "ARMISD::VST2D";
490 case ARMISD::VST3D: return "ARMISD::VST3D";
491 case ARMISD::VST4D: return "ARMISD::VST4D";
492 case ARMISD::VEXT: return "ARMISD::VEXT";
493 case ARMISD::VREV64: return "ARMISD::VREV64";
494 case ARMISD::VREV32: return "ARMISD::VREV32";
495 case ARMISD::VREV16: return "ARMISD::VREV16";
496 case ARMISD::VZIP: return "ARMISD::VZIP";
497 case ARMISD::VUZP: return "ARMISD::VUZP";
498 case ARMISD::VTRN: return "ARMISD::VTRN";
502 /// getFunctionAlignment - Return the Log2 alignment of this function.
503 unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
504 return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 1 : 2;
507 //===----------------------------------------------------------------------===//
509 //===----------------------------------------------------------------------===//
511 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
512 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
514 default: llvm_unreachable("Unknown condition code!");
515 case ISD::SETNE: return ARMCC::NE;
516 case ISD::SETEQ: return ARMCC::EQ;
517 case ISD::SETGT: return ARMCC::GT;
518 case ISD::SETGE: return ARMCC::GE;
519 case ISD::SETLT: return ARMCC::LT;
520 case ISD::SETLE: return ARMCC::LE;
521 case ISD::SETUGT: return ARMCC::HI;
522 case ISD::SETUGE: return ARMCC::HS;
523 case ISD::SETULT: return ARMCC::LO;
524 case ISD::SETULE: return ARMCC::LS;
528 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. It
529 /// returns true if the operands should be inverted to form the proper
531 static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
532 ARMCC::CondCodes &CondCode2) {
534 CondCode2 = ARMCC::AL;
536 default: llvm_unreachable("Unknown FP condition!");
538 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
540 case ISD::SETOGT: CondCode = ARMCC::GT; break;
542 case ISD::SETOGE: CondCode = ARMCC::GE; break;
543 case ISD::SETOLT: CondCode = ARMCC::MI; break;
544 case ISD::SETOLE: CondCode = ARMCC::GT; Invert = true; break;
545 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
546 case ISD::SETO: CondCode = ARMCC::VC; break;
547 case ISD::SETUO: CondCode = ARMCC::VS; break;
548 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
549 case ISD::SETUGT: CondCode = ARMCC::HI; break;
550 case ISD::SETUGE: CondCode = ARMCC::PL; break;
552 case ISD::SETULT: CondCode = ARMCC::LT; break;
554 case ISD::SETULE: CondCode = ARMCC::LE; break;
556 case ISD::SETUNE: CondCode = ARMCC::NE; break;
561 //===----------------------------------------------------------------------===//
562 // Calling Convention Implementation
563 //===----------------------------------------------------------------------===//
565 #include "ARMGenCallingConv.inc"
567 // APCS f64 is in register pairs, possibly split to stack
568 static bool f64AssignAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
569 CCValAssign::LocInfo &LocInfo,
570 CCState &State, bool CanFail) {
571 static const unsigned RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
573 // Try to get the first register.
574 if (unsigned Reg = State.AllocateReg(RegList, 4))
575 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
577 // For the 2nd half of a v2f64, do not fail.
581 // Put the whole thing on the stack.
582 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
583 State.AllocateStack(8, 4),
588 // Try to get the second register.
589 if (unsigned Reg = State.AllocateReg(RegList, 4))
590 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
592 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
593 State.AllocateStack(4, 4),
598 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
599 CCValAssign::LocInfo &LocInfo,
600 ISD::ArgFlagsTy &ArgFlags,
602 if (!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
604 if (LocVT == MVT::v2f64 &&
605 !f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
607 return true; // we handled it
610 // AAPCS f64 is in aligned register pairs
611 static bool f64AssignAAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
612 CCValAssign::LocInfo &LocInfo,
613 CCState &State, bool CanFail) {
614 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
615 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
617 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
619 // For the 2nd half of a v2f64, do not just fail.
623 // Put the whole thing on the stack.
624 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
625 State.AllocateStack(8, 8),
631 for (i = 0; i < 2; ++i)
632 if (HiRegList[i] == Reg)
635 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
636 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
641 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
642 CCValAssign::LocInfo &LocInfo,
643 ISD::ArgFlagsTy &ArgFlags,
645 if (!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
647 if (LocVT == MVT::v2f64 &&
648 !f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
650 return true; // we handled it
653 static bool f64RetAssign(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
654 CCValAssign::LocInfo &LocInfo, CCState &State) {
655 static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
656 static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
658 unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
660 return false; // we didn't handle it
663 for (i = 0; i < 2; ++i)
664 if (HiRegList[i] == Reg)
667 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
668 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
673 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
674 CCValAssign::LocInfo &LocInfo,
675 ISD::ArgFlagsTy &ArgFlags,
677 if (!f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
679 if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
681 return true; // we handled it
684 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
685 CCValAssign::LocInfo &LocInfo,
686 ISD::ArgFlagsTy &ArgFlags,
688 return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags,
692 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
693 /// given CallingConvention value.
694 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(unsigned CC,
696 bool isVarArg) const {
699 llvm_unreachable("Unsupported calling convention");
701 case CallingConv::Fast:
702 // Use target triple & subtarget features to do actual dispatch.
703 if (Subtarget->isAAPCS_ABI()) {
704 if (Subtarget->hasVFP2() &&
705 FloatABIType == FloatABI::Hard && !isVarArg)
706 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
708 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
710 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
711 case CallingConv::ARM_AAPCS_VFP:
712 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
713 case CallingConv::ARM_AAPCS:
714 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
715 case CallingConv::ARM_APCS:
716 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
720 /// LowerCallResult - Lower the result values of a call into the
721 /// appropriate copies out of appropriate physical registers.
723 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
724 unsigned CallConv, bool isVarArg,
725 const SmallVectorImpl<ISD::InputArg> &Ins,
726 DebugLoc dl, SelectionDAG &DAG,
727 SmallVectorImpl<SDValue> &InVals) {
729 // Assign locations to each value returned by this call.
730 SmallVector<CCValAssign, 16> RVLocs;
731 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
732 RVLocs, *DAG.getContext());
733 CCInfo.AnalyzeCallResult(Ins,
734 CCAssignFnForNode(CallConv, /* Return*/ true,
737 // Copy all of the result registers out of their specified physreg.
738 for (unsigned i = 0; i != RVLocs.size(); ++i) {
739 CCValAssign VA = RVLocs[i];
742 if (VA.needsCustom()) {
743 // Handle f64 or half of a v2f64.
744 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
746 Chain = Lo.getValue(1);
747 InFlag = Lo.getValue(2);
748 VA = RVLocs[++i]; // skip ahead to next loc
749 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
751 Chain = Hi.getValue(1);
752 InFlag = Hi.getValue(2);
753 Val = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
755 if (VA.getLocVT() == MVT::v2f64) {
756 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
757 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
758 DAG.getConstant(0, MVT::i32));
760 VA = RVLocs[++i]; // skip ahead to next loc
761 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
762 Chain = Lo.getValue(1);
763 InFlag = Lo.getValue(2);
764 VA = RVLocs[++i]; // skip ahead to next loc
765 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
766 Chain = Hi.getValue(1);
767 InFlag = Hi.getValue(2);
768 Val = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
769 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
770 DAG.getConstant(1, MVT::i32));
773 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
775 Chain = Val.getValue(1);
776 InFlag = Val.getValue(2);
779 switch (VA.getLocInfo()) {
780 default: llvm_unreachable("Unknown loc info!");
781 case CCValAssign::Full: break;
782 case CCValAssign::BCvt:
783 Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val);
787 InVals.push_back(Val);
793 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
794 /// by "Src" to address "Dst" of size "Size". Alignment information is
795 /// specified by the specific parameter attribute. The copy will be passed as
796 /// a byval function parameter.
797 /// Sometimes what we are copying is the end of a larger object, the part that
798 /// does not fit in registers.
800 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
801 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
803 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
804 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
805 /*AlwaysInline=*/false, NULL, 0, NULL, 0);
808 /// LowerMemOpCallTo - Store the argument to the stack.
810 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
811 SDValue StackPtr, SDValue Arg,
812 DebugLoc dl, SelectionDAG &DAG,
813 const CCValAssign &VA,
814 ISD::ArgFlagsTy Flags) {
815 unsigned LocMemOffset = VA.getLocMemOffset();
816 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
817 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
818 if (Flags.isByVal()) {
819 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
821 return DAG.getStore(Chain, dl, Arg, PtrOff,
822 PseudoSourceValue::getStack(), LocMemOffset);
825 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
826 SDValue Chain, SDValue &Arg,
827 RegsToPassVector &RegsToPass,
828 CCValAssign &VA, CCValAssign &NextVA,
830 SmallVector<SDValue, 8> &MemOpChains,
831 ISD::ArgFlagsTy Flags) {
833 SDValue fmrrd = DAG.getNode(ARMISD::FMRRD, dl,
834 DAG.getVTList(MVT::i32, MVT::i32), Arg);
835 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
837 if (NextVA.isRegLoc())
838 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
840 assert(NextVA.isMemLoc());
841 if (StackPtr.getNode() == 0)
842 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
844 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
850 /// LowerCall - Lowering a call into a callseq_start <-
851 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
854 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
855 unsigned CallConv, bool isVarArg,
857 const SmallVectorImpl<ISD::OutputArg> &Outs,
858 const SmallVectorImpl<ISD::InputArg> &Ins,
859 DebugLoc dl, SelectionDAG &DAG,
860 SmallVectorImpl<SDValue> &InVals) {
862 // Analyze operands of the call, assigning locations to each operand.
863 SmallVector<CCValAssign, 16> ArgLocs;
864 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
866 CCInfo.AnalyzeCallOperands(Outs,
867 CCAssignFnForNode(CallConv, /* Return*/ false,
870 // Get a count of how many bytes are to be pushed on the stack.
871 unsigned NumBytes = CCInfo.getNextStackOffset();
873 // Adjust the stack pointer for the new arguments...
874 // These operations are automatically eliminated by the prolog/epilog pass
875 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
877 SDValue StackPtr = DAG.getRegister(ARM::SP, MVT::i32);
879 RegsToPassVector RegsToPass;
880 SmallVector<SDValue, 8> MemOpChains;
882 // Walk the register/memloc assignments, inserting copies/loads. In the case
883 // of tail call optimization, arguments are handled later.
884 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
887 CCValAssign &VA = ArgLocs[i];
888 SDValue Arg = Outs[realArgIdx].Val;
889 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
891 // Promote the value if needed.
892 switch (VA.getLocInfo()) {
893 default: llvm_unreachable("Unknown loc info!");
894 case CCValAssign::Full: break;
895 case CCValAssign::SExt:
896 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
898 case CCValAssign::ZExt:
899 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
901 case CCValAssign::AExt:
902 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
904 case CCValAssign::BCvt:
905 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
909 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
910 if (VA.needsCustom()) {
911 if (VA.getLocVT() == MVT::v2f64) {
912 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
913 DAG.getConstant(0, MVT::i32));
914 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
915 DAG.getConstant(1, MVT::i32));
917 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
918 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
920 VA = ArgLocs[++i]; // skip ahead to next loc
922 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
923 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
925 assert(VA.isMemLoc());
926 if (StackPtr.getNode() == 0)
927 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
929 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
930 dl, DAG, VA, Flags));
933 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
934 StackPtr, MemOpChains, Flags);
936 } else if (VA.isRegLoc()) {
937 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
939 assert(VA.isMemLoc());
940 if (StackPtr.getNode() == 0)
941 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
943 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
944 dl, DAG, VA, Flags));
948 if (!MemOpChains.empty())
949 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
950 &MemOpChains[0], MemOpChains.size());
952 // Build a sequence of copy-to-reg nodes chained together with token chain
953 // and flag operands which copy the outgoing args into the appropriate regs.
955 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
956 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
957 RegsToPass[i].second, InFlag);
958 InFlag = Chain.getValue(1);
961 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
962 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
963 // node so that legalize doesn't hack it.
964 bool isDirect = false;
965 bool isARMFunc = false;
966 bool isLocalARMFunc = false;
967 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
968 GlobalValue *GV = G->getGlobal();
970 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
971 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
972 getTargetMachine().getRelocationModel() != Reloc::Static;
973 isARMFunc = !Subtarget->isThumb() || isStub;
974 // ARM call to a local ARM function is predicable.
975 isLocalARMFunc = !Subtarget->isThumb() && !isExt;
976 // tBX takes a register source operand.
977 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
978 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
980 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
981 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
982 Callee = DAG.getLoad(getPointerTy(), dl,
983 DAG.getEntryNode(), CPAddr, NULL, 0);
984 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
985 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
986 getPointerTy(), Callee, PICLabel);
988 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy());
989 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
991 bool isStub = Subtarget->isTargetDarwin() &&
992 getTargetMachine().getRelocationModel() != Reloc::Static;
993 isARMFunc = !Subtarget->isThumb() || isStub;
994 // tBX takes a register source operand.
995 const char *Sym = S->getSymbol();
996 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
997 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
998 Sym, ARMPCLabelIndex,
1000 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1001 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1002 Callee = DAG.getLoad(getPointerTy(), dl,
1003 DAG.getEntryNode(), CPAddr, NULL, 0);
1004 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1005 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1006 getPointerTy(), Callee, PICLabel);
1008 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
1011 // FIXME: handle tail calls differently.
1013 if (Subtarget->isThumb()) {
1014 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1015 CallOpc = ARMISD::CALL_NOLINK;
1017 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1019 CallOpc = (isDirect || Subtarget->hasV5TOps())
1020 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
1021 : ARMISD::CALL_NOLINK;
1023 if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb1Only()) {
1024 // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK
1025 Chain = DAG.getCopyToReg(Chain, dl, ARM::LR, DAG.getUNDEF(MVT::i32),InFlag);
1026 InFlag = Chain.getValue(1);
1029 std::vector<SDValue> Ops;
1030 Ops.push_back(Chain);
1031 Ops.push_back(Callee);
1033 // Add argument registers to the end of the list so that they are known live
1035 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1036 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1037 RegsToPass[i].second.getValueType()));
1039 if (InFlag.getNode())
1040 Ops.push_back(InFlag);
1041 // Returns a chain and a flag for retval copy to use.
1042 Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(MVT::Other, MVT::Flag),
1043 &Ops[0], Ops.size());
1044 InFlag = Chain.getValue(1);
1046 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1047 DAG.getIntPtrConstant(0, true), InFlag);
1049 InFlag = Chain.getValue(1);
1051 // Handle result values, copying them out of physregs into vregs that we
1053 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1058 ARMTargetLowering::LowerReturn(SDValue Chain,
1059 unsigned CallConv, bool isVarArg,
1060 const SmallVectorImpl<ISD::OutputArg> &Outs,
1061 DebugLoc dl, SelectionDAG &DAG) {
1063 // CCValAssign - represent the assignment of the return value to a location.
1064 SmallVector<CCValAssign, 16> RVLocs;
1066 // CCState - Info about the registers and stack slots.
1067 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
1070 // Analyze outgoing return values.
1071 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1074 // If this is the first return lowered for this function, add
1075 // the regs to the liveout set for the function.
1076 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1077 for (unsigned i = 0; i != RVLocs.size(); ++i)
1078 if (RVLocs[i].isRegLoc())
1079 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1084 // Copy the result values into the output registers.
1085 for (unsigned i = 0, realRVLocIdx = 0;
1087 ++i, ++realRVLocIdx) {
1088 CCValAssign &VA = RVLocs[i];
1089 assert(VA.isRegLoc() && "Can only return in registers!");
1091 SDValue Arg = Outs[realRVLocIdx].Val;
1093 switch (VA.getLocInfo()) {
1094 default: llvm_unreachable("Unknown loc info!");
1095 case CCValAssign::Full: break;
1096 case CCValAssign::BCvt:
1097 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1101 if (VA.needsCustom()) {
1102 if (VA.getLocVT() == MVT::v2f64) {
1103 // Extract the first half and return it in two registers.
1104 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1105 DAG.getConstant(0, MVT::i32));
1106 SDValue HalfGPRs = DAG.getNode(ARMISD::FMRRD, dl,
1107 DAG.getVTList(MVT::i32, MVT::i32), Half);
1109 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1110 Flag = Chain.getValue(1);
1111 VA = RVLocs[++i]; // skip ahead to next loc
1112 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1113 HalfGPRs.getValue(1), Flag);
1114 Flag = Chain.getValue(1);
1115 VA = RVLocs[++i]; // skip ahead to next loc
1117 // Extract the 2nd half and fall through to handle it as an f64 value.
1118 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1119 DAG.getConstant(1, MVT::i32));
1121 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1123 SDValue fmrrd = DAG.getNode(ARMISD::FMRRD, dl,
1124 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1125 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1126 Flag = Chain.getValue(1);
1127 VA = RVLocs[++i]; // skip ahead to next loc
1128 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1131 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1133 // Guarantee that all emitted copies are
1134 // stuck together, avoiding something bad.
1135 Flag = Chain.getValue(1);
1140 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1142 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1147 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1148 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1149 // one of the above mentioned nodes. It has to be wrapped because otherwise
1150 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1151 // be used to form addressing mode. These wrapped nodes will be selected
1153 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1154 EVT PtrVT = Op.getValueType();
1155 // FIXME there is no actual debug info here
1156 DebugLoc dl = Op.getDebugLoc();
1157 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1159 if (CP->isMachineConstantPoolEntry())
1160 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1161 CP->getAlignment());
1163 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1164 CP->getAlignment());
1165 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1168 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
1170 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1171 SelectionDAG &DAG) {
1172 DebugLoc dl = GA->getDebugLoc();
1173 EVT PtrVT = getPointerTy();
1174 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1175 ARMConstantPoolValue *CPV =
1176 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
1177 PCAdj, "tlsgd", true);
1178 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1179 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
1180 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument, NULL, 0);
1181 SDValue Chain = Argument.getValue(1);
1183 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1184 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
1186 // call __tls_get_addr.
1189 Entry.Node = Argument;
1190 Entry.Ty = (const Type *) Type::getInt32Ty(*DAG.getContext());
1191 Args.push_back(Entry);
1192 // FIXME: is there useful debug info available here?
1193 std::pair<SDValue, SDValue> CallResult =
1194 LowerCallTo(Chain, (const Type *) Type::getInt32Ty(*DAG.getContext()),
1195 false, false, false, false,
1196 0, CallingConv::C, false, /*isReturnValueUsed=*/true,
1197 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
1198 return CallResult.first;
1201 // Lower ISD::GlobalTLSAddress using the "initial exec" or
1202 // "local exec" model.
1204 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
1205 SelectionDAG &DAG) {
1206 GlobalValue *GV = GA->getGlobal();
1207 DebugLoc dl = GA->getDebugLoc();
1209 SDValue Chain = DAG.getEntryNode();
1210 EVT PtrVT = getPointerTy();
1211 // Get the Thread Pointer
1212 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1214 if (GV->isDeclaration()) {
1215 // initial exec model
1216 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1217 ARMConstantPoolValue *CPV =
1218 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
1219 PCAdj, "gottpoff", true);
1220 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1221 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1222 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
1223 Chain = Offset.getValue(1);
1225 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1226 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
1228 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
1231 ARMConstantPoolValue *CPV =
1232 new ARMConstantPoolValue(GV, ARMCP::CPValue, "tpoff");
1233 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1234 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1235 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
1238 // The address of the thread local variable is the add of the thread
1239 // pointer with the offset of the variable.
1240 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
1244 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
1245 // TODO: implement the "local dynamic" model
1246 assert(Subtarget->isTargetELF() &&
1247 "TLS not implemented for non-ELF targets");
1248 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1249 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
1250 // otherwise use the "Local Exec" TLS Model
1251 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
1252 return LowerToTLSGeneralDynamicModel(GA, DAG);
1254 return LowerToTLSExecModels(GA, DAG);
1257 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
1258 SelectionDAG &DAG) {
1259 EVT PtrVT = getPointerTy();
1260 DebugLoc dl = Op.getDebugLoc();
1261 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1262 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1263 if (RelocM == Reloc::PIC_) {
1264 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
1265 ARMConstantPoolValue *CPV =
1266 new ARMConstantPoolValue(GV, ARMCP::CPValue, UseGOTOFF ? "GOTOFF":"GOT");
1267 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1268 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1269 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1271 SDValue Chain = Result.getValue(1);
1272 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1273 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
1275 Result = DAG.getLoad(PtrVT, dl, Chain, Result, NULL, 0);
1278 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1279 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1280 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
1284 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol
1285 /// even in non-static mode.
1286 static bool GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model RelocM) {
1287 // If symbol visibility is hidden, the extra load is not needed if
1288 // the symbol is definitely defined in the current translation unit.
1289 bool isDecl = GV->isDeclaration() || GV->hasAvailableExternallyLinkage();
1290 if (GV->hasHiddenVisibility() && (!isDecl && !GV->hasCommonLinkage()))
1292 return RelocM != Reloc::Static && (isDecl || GV->isWeakForLinker());
1295 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
1296 SelectionDAG &DAG) {
1297 EVT PtrVT = getPointerTy();
1298 DebugLoc dl = Op.getDebugLoc();
1299 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1300 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1301 bool IsIndirect = GVIsIndirectSymbol(GV, RelocM);
1303 if (RelocM == Reloc::Static)
1304 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1306 unsigned PCAdj = (RelocM != Reloc::PIC_)
1307 ? 0 : (Subtarget->isThumb() ? 4 : 8);
1308 ARMCP::ARMCPKind Kind = IsIndirect ? ARMCP::CPNonLazyPtr
1310 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
1312 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1314 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1316 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
1317 SDValue Chain = Result.getValue(1);
1319 if (RelocM == Reloc::PIC_) {
1320 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1321 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1324 Result = DAG.getLoad(PtrVT, dl, Chain, Result, NULL, 0);
1329 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
1331 assert(Subtarget->isTargetELF() &&
1332 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
1333 EVT PtrVT = getPointerTy();
1334 DebugLoc dl = Op.getDebugLoc();
1335 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1336 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1337 "_GLOBAL_OFFSET_TABLE_",
1339 ARMCP::CPValue, PCAdj);
1340 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1341 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1342 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
1343 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1344 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1347 static SDValue LowerNeonVLDIntrinsic(SDValue Op, SelectionDAG &DAG,
1349 SDNode *Node = Op.getNode();
1350 EVT VT = Node->getValueType(0);
1351 DebugLoc dl = Op.getDebugLoc();
1353 if (!VT.is64BitVector())
1354 return SDValue(); // unimplemented
1356 SDValue Ops[] = { Node->getOperand(0),
1357 Node->getOperand(2) };
1358 return DAG.getNode(Opcode, dl, Node->getVTList(), Ops, 2);
1361 static SDValue LowerNeonVSTIntrinsic(SDValue Op, SelectionDAG &DAG,
1362 unsigned Opcode, unsigned NumVecs) {
1363 SDNode *Node = Op.getNode();
1364 EVT VT = Node->getOperand(3).getValueType();
1365 DebugLoc dl = Op.getDebugLoc();
1367 if (!VT.is64BitVector())
1368 return SDValue(); // unimplemented
1370 SmallVector<SDValue, 6> Ops;
1371 Ops.push_back(Node->getOperand(0));
1372 Ops.push_back(Node->getOperand(2));
1373 for (unsigned N = 0; N < NumVecs; ++N)
1374 Ops.push_back(Node->getOperand(N + 3));
1375 return DAG.getNode(Opcode, dl, MVT::Other, Ops.data(), Ops.size());
1379 ARMTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) {
1380 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1382 case Intrinsic::arm_neon_vld2:
1383 return LowerNeonVLDIntrinsic(Op, DAG, ARMISD::VLD2D);
1384 case Intrinsic::arm_neon_vld3:
1385 return LowerNeonVLDIntrinsic(Op, DAG, ARMISD::VLD3D);
1386 case Intrinsic::arm_neon_vld4:
1387 return LowerNeonVLDIntrinsic(Op, DAG, ARMISD::VLD4D);
1388 case Intrinsic::arm_neon_vst2:
1389 return LowerNeonVSTIntrinsic(Op, DAG, ARMISD::VST2D, 2);
1390 case Intrinsic::arm_neon_vst3:
1391 return LowerNeonVSTIntrinsic(Op, DAG, ARMISD::VST3D, 3);
1392 case Intrinsic::arm_neon_vst4:
1393 return LowerNeonVSTIntrinsic(Op, DAG, ARMISD::VST4D, 4);
1394 default: return SDValue(); // Don't custom lower most intrinsics.
1399 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
1400 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1401 DebugLoc dl = Op.getDebugLoc();
1403 default: return SDValue(); // Don't custom lower most intrinsics.
1404 case Intrinsic::arm_thread_pointer: {
1405 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1406 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1408 case Intrinsic::eh_sjlj_lsda: {
1409 // blah. horrible, horrible hack with the forced magic name.
1410 // really need to clean this up. It belongs in the target-independent
1411 // layer somehow that doesn't require the coupling with the asm
1413 MachineFunction &MF = DAG.getMachineFunction();
1414 EVT PtrVT = getPointerTy();
1415 DebugLoc dl = Op.getDebugLoc();
1416 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1418 unsigned PCAdj = (RelocM != Reloc::PIC_)
1419 ? 0 : (Subtarget->isThumb() ? 4 : 8);
1420 ARMCP::ARMCPKind Kind = ARMCP::CPValue;
1421 // Save off the LSDA name for the AsmPrinter to use when it's time
1422 // to emit the table
1423 std::string LSDAName = "L_lsda_";
1424 LSDAName += MF.getFunction()->getName();
1425 ARMConstantPoolValue *CPV =
1426 new ARMConstantPoolValue(*DAG.getContext(), LSDAName.c_str(),
1427 ARMPCLabelIndex, Kind, PCAdj);
1428 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1429 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1431 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
1432 SDValue Chain = Result.getValue(1);
1434 if (RelocM == Reloc::PIC_) {
1435 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1436 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1440 case Intrinsic::eh_sjlj_setjmp:
1441 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(1));
1445 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
1446 unsigned VarArgsFrameIndex) {
1447 // vastart just stores the address of the VarArgsFrameIndex slot into the
1448 // memory location argument.
1449 DebugLoc dl = Op.getDebugLoc();
1450 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1451 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1452 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1453 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
1457 ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) {
1458 SDNode *Node = Op.getNode();
1459 DebugLoc dl = Node->getDebugLoc();
1460 EVT VT = Node->getValueType(0);
1461 SDValue Chain = Op.getOperand(0);
1462 SDValue Size = Op.getOperand(1);
1463 SDValue Align = Op.getOperand(2);
1465 // Chain the dynamic stack allocation so that it doesn't modify the stack
1466 // pointer when other instructions are using the stack.
1467 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1469 unsigned AlignVal = cast<ConstantSDNode>(Align)->getZExtValue();
1470 unsigned StackAlign = getTargetMachine().getFrameInfo()->getStackAlignment();
1471 if (AlignVal > StackAlign)
1472 // Do this now since selection pass cannot introduce new target
1473 // independent node.
1474 Align = DAG.getConstant(-(uint64_t)AlignVal, VT);
1476 // In Thumb1 mode, there isn't a "sub r, sp, r" instruction, we will end up
1477 // using a "add r, sp, r" instead. Negate the size now so we don't have to
1478 // do even more horrible hack later.
1479 MachineFunction &MF = DAG.getMachineFunction();
1480 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1481 if (AFI->isThumb1OnlyFunction()) {
1483 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Size);
1485 uint32_t Val = C->getZExtValue();
1486 if (Val <= 508 && ((Val & 3) == 0))
1490 Size = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, VT), Size);
1493 SDVTList VTList = DAG.getVTList(VT, MVT::Other);
1494 SDValue Ops1[] = { Chain, Size, Align };
1495 SDValue Res = DAG.getNode(ARMISD::DYN_ALLOC, dl, VTList, Ops1, 3);
1496 Chain = Res.getValue(1);
1497 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1498 DAG.getIntPtrConstant(0, true), SDValue());
1499 SDValue Ops2[] = { Res, Chain };
1500 return DAG.getMergeValues(Ops2, 2, dl);
1504 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
1505 SDValue &Root, SelectionDAG &DAG,
1507 MachineFunction &MF = DAG.getMachineFunction();
1508 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1510 TargetRegisterClass *RC;
1511 if (AFI->isThumb1OnlyFunction())
1512 RC = ARM::tGPRRegisterClass;
1514 RC = ARM::GPRRegisterClass;
1516 // Transform the arguments stored in physical registers into virtual ones.
1517 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1518 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
1521 if (NextVA.isMemLoc()) {
1522 unsigned ArgSize = NextVA.getLocVT().getSizeInBits()/8;
1523 MachineFrameInfo *MFI = MF.getFrameInfo();
1524 int FI = MFI->CreateFixedObject(ArgSize, NextVA.getLocMemOffset());
1526 // Create load node to retrieve arguments from the stack.
1527 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1528 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN, NULL, 0);
1530 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
1531 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
1534 return DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, ArgValue, ArgValue2);
1538 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
1539 unsigned CallConv, bool isVarArg,
1540 const SmallVectorImpl<ISD::InputArg>
1542 DebugLoc dl, SelectionDAG &DAG,
1543 SmallVectorImpl<SDValue> &InVals) {
1545 MachineFunction &MF = DAG.getMachineFunction();
1546 MachineFrameInfo *MFI = MF.getFrameInfo();
1548 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1550 // Assign locations to all of the incoming arguments.
1551 SmallVector<CCValAssign, 16> ArgLocs;
1552 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1554 CCInfo.AnalyzeFormalArguments(Ins,
1555 CCAssignFnForNode(CallConv, /* Return*/ false,
1558 SmallVector<SDValue, 16> ArgValues;
1560 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1561 CCValAssign &VA = ArgLocs[i];
1563 // Arguments stored in registers.
1564 if (VA.isRegLoc()) {
1565 EVT RegVT = VA.getLocVT();
1568 if (VA.needsCustom()) {
1569 // f64 and vector types are split up into multiple registers or
1570 // combinations of registers and stack slots.
1573 if (VA.getLocVT() == MVT::v2f64) {
1574 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
1576 VA = ArgLocs[++i]; // skip ahead to next loc
1577 SDValue ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
1579 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1580 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
1581 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
1582 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
1583 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
1585 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
1588 TargetRegisterClass *RC;
1590 if (RegVT == MVT::f32)
1591 RC = ARM::SPRRegisterClass;
1592 else if (RegVT == MVT::f64)
1593 RC = ARM::DPRRegisterClass;
1594 else if (RegVT == MVT::v2f64)
1595 RC = ARM::QPRRegisterClass;
1596 else if (RegVT == MVT::i32)
1597 RC = (AFI->isThumb1OnlyFunction() ?
1598 ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
1600 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
1602 // Transform the arguments in physical registers into virtual ones.
1603 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1604 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1607 // If this is an 8 or 16-bit value, it is really passed promoted
1608 // to 32 bits. Insert an assert[sz]ext to capture this, then
1609 // truncate to the right size.
1610 switch (VA.getLocInfo()) {
1611 default: llvm_unreachable("Unknown loc info!");
1612 case CCValAssign::Full: break;
1613 case CCValAssign::BCvt:
1614 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1616 case CCValAssign::SExt:
1617 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1618 DAG.getValueType(VA.getValVT()));
1619 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1621 case CCValAssign::ZExt:
1622 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1623 DAG.getValueType(VA.getValVT()));
1624 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1628 InVals.push_back(ArgValue);
1630 } else { // VA.isRegLoc()
1633 assert(VA.isMemLoc());
1634 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
1636 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
1637 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset());
1639 // Create load nodes to retrieve arguments from the stack.
1640 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1641 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, NULL, 0));
1647 static const unsigned GPRArgRegs[] = {
1648 ARM::R0, ARM::R1, ARM::R2, ARM::R3
1651 unsigned NumGPRs = CCInfo.getFirstUnallocated
1652 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
1654 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1655 unsigned VARegSize = (4 - NumGPRs) * 4;
1656 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
1657 unsigned ArgOffset = 0;
1658 if (VARegSaveSize) {
1659 // If this function is vararg, store any remaining integer argument regs
1660 // to their spots on the stack so that they may be loaded by deferencing
1661 // the result of va_next.
1662 AFI->setVarArgsRegSaveSize(VARegSaveSize);
1663 ArgOffset = CCInfo.getNextStackOffset();
1664 VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset +
1665 VARegSaveSize - VARegSize);
1666 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
1668 SmallVector<SDValue, 4> MemOps;
1669 for (; NumGPRs < 4; ++NumGPRs) {
1670 TargetRegisterClass *RC;
1671 if (AFI->isThumb1OnlyFunction())
1672 RC = ARM::tGPRRegisterClass;
1674 RC = ARM::GPRRegisterClass;
1676 unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
1677 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
1678 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
1679 MemOps.push_back(Store);
1680 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
1681 DAG.getConstant(4, getPointerTy()));
1683 if (!MemOps.empty())
1684 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1685 &MemOps[0], MemOps.size());
1687 // This will point to the next argument passed via stack.
1688 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
1694 /// isFloatingPointZero - Return true if this is +0.0.
1695 static bool isFloatingPointZero(SDValue Op) {
1696 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1697 return CFP->getValueAPF().isPosZero();
1698 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1699 // Maybe this has already been legalized into the constant pool?
1700 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
1701 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
1702 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
1703 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1704 return CFP->getValueAPF().isPosZero();
1710 static bool isLegalCmpImmediate(unsigned C, bool isThumb1Only) {
1711 return ( isThumb1Only && (C & ~255U) == 0) ||
1712 (!isThumb1Only && ARM_AM::getSOImmVal(C) != -1);
1715 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
1716 /// the given operands.
1717 static SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1718 SDValue &ARMCC, SelectionDAG &DAG, bool isThumb1Only,
1720 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1721 unsigned C = RHSC->getZExtValue();
1722 if (!isLegalCmpImmediate(C, isThumb1Only)) {
1723 // Constant does not fit, try adjusting it by one?
1728 if (isLegalCmpImmediate(C-1, isThumb1Only)) {
1729 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1730 RHS = DAG.getConstant(C-1, MVT::i32);
1735 if (C > 0 && isLegalCmpImmediate(C-1, isThumb1Only)) {
1736 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1737 RHS = DAG.getConstant(C-1, MVT::i32);
1742 if (isLegalCmpImmediate(C+1, isThumb1Only)) {
1743 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1744 RHS = DAG.getConstant(C+1, MVT::i32);
1749 if (C < 0xffffffff && isLegalCmpImmediate(C+1, isThumb1Only)) {
1750 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1751 RHS = DAG.getConstant(C+1, MVT::i32);
1758 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
1759 ARMISD::NodeType CompareType;
1762 CompareType = ARMISD::CMP;
1767 CompareType = ARMISD::CMPZ;
1770 ARMCC = DAG.getConstant(CondCode, MVT::i32);
1771 return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS);
1774 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
1775 static SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
1778 if (!isFloatingPointZero(RHS))
1779 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS);
1781 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS);
1782 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp);
1785 static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
1786 const ARMSubtarget *ST) {
1787 EVT VT = Op.getValueType();
1788 SDValue LHS = Op.getOperand(0);
1789 SDValue RHS = Op.getOperand(1);
1790 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1791 SDValue TrueVal = Op.getOperand(2);
1792 SDValue FalseVal = Op.getOperand(3);
1793 DebugLoc dl = Op.getDebugLoc();
1795 if (LHS.getValueType() == MVT::i32) {
1797 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1798 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb1Only(), dl);
1799 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC, CCR,Cmp);
1802 ARMCC::CondCodes CondCode, CondCode2;
1803 if (FPCCToARMCC(CC, CondCode, CondCode2))
1804 std::swap(TrueVal, FalseVal);
1806 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
1807 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1808 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
1809 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
1811 if (CondCode2 != ARMCC::AL) {
1812 SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
1813 // FIXME: Needs another CMP because flag can have but one use.
1814 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
1815 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
1816 Result, TrueVal, ARMCC2, CCR, Cmp2);
1821 static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
1822 const ARMSubtarget *ST) {
1823 SDValue Chain = Op.getOperand(0);
1824 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1825 SDValue LHS = Op.getOperand(2);
1826 SDValue RHS = Op.getOperand(3);
1827 SDValue Dest = Op.getOperand(4);
1828 DebugLoc dl = Op.getDebugLoc();
1830 if (LHS.getValueType() == MVT::i32) {
1832 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1833 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb1Only(), dl);
1834 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
1835 Chain, Dest, ARMCC, CCR,Cmp);
1838 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
1839 ARMCC::CondCodes CondCode, CondCode2;
1840 if (FPCCToARMCC(CC, CondCode, CondCode2))
1841 // Swap the LHS/RHS of the comparison if needed.
1842 std::swap(LHS, RHS);
1844 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
1845 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
1846 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1847 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
1848 SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp };
1849 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
1850 if (CondCode2 != ARMCC::AL) {
1851 ARMCC = DAG.getConstant(CondCode2, MVT::i32);
1852 SDValue Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) };
1853 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
1858 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) {
1859 SDValue Chain = Op.getOperand(0);
1860 SDValue Table = Op.getOperand(1);
1861 SDValue Index = Op.getOperand(2);
1862 DebugLoc dl = Op.getDebugLoc();
1864 EVT PTy = getPointerTy();
1865 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
1866 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
1867 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
1868 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
1869 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
1870 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
1871 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
1872 if (Subtarget->isThumb2()) {
1873 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
1874 // which does another jump to the destination. This also makes it easier
1875 // to translate it to TBB / TBH later.
1876 // FIXME: This might not work if the function is extremely large.
1877 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
1878 Addr, Op.getOperand(2), JTI, UId);
1880 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1881 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr, NULL, 0);
1882 Chain = Addr.getValue(1);
1883 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
1884 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
1886 Addr = DAG.getLoad(PTy, dl, Chain, Addr, NULL, 0);
1887 Chain = Addr.getValue(1);
1888 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
1892 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1893 DebugLoc dl = Op.getDebugLoc();
1895 Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI;
1896 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
1897 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
1900 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1901 EVT VT = Op.getValueType();
1902 DebugLoc dl = Op.getDebugLoc();
1904 Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF;
1906 Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
1907 return DAG.getNode(Opc, dl, VT, Op);
1910 static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
1911 // Implement fcopysign with a fabs and a conditional fneg.
1912 SDValue Tmp0 = Op.getOperand(0);
1913 SDValue Tmp1 = Op.getOperand(1);
1914 DebugLoc dl = Op.getDebugLoc();
1915 EVT VT = Op.getValueType();
1916 EVT SrcVT = Tmp1.getValueType();
1917 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
1918 SDValue Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG, dl);
1919 SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
1920 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1921 return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp);
1924 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
1925 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1926 MFI->setFrameAddressIsTaken(true);
1927 EVT VT = Op.getValueType();
1928 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
1929 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1930 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
1931 ? ARM::R7 : ARM::R11;
1932 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
1934 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0);
1939 ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
1941 SDValue Dst, SDValue Src,
1942 SDValue Size, unsigned Align,
1944 const Value *DstSV, uint64_t DstSVOff,
1945 const Value *SrcSV, uint64_t SrcSVOff){
1946 // Do repeated 4-byte loads and stores. To be improved.
1947 // This requires 4-byte alignment.
1948 if ((Align & 3) != 0)
1950 // This requires the copy size to be a constant, preferrably
1951 // within a subtarget-specific limit.
1952 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
1955 uint64_t SizeVal = ConstantSize->getZExtValue();
1956 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
1959 unsigned BytesLeft = SizeVal & 3;
1960 unsigned NumMemOps = SizeVal >> 2;
1961 unsigned EmittedNumMemOps = 0;
1963 unsigned VTSize = 4;
1965 const unsigned MAX_LOADS_IN_LDM = 6;
1966 SDValue TFOps[MAX_LOADS_IN_LDM];
1967 SDValue Loads[MAX_LOADS_IN_LDM];
1968 uint64_t SrcOff = 0, DstOff = 0;
1970 // Emit up to MAX_LOADS_IN_LDM loads, then a TokenFactor barrier, then the
1971 // same number of stores. The loads and stores will get combined into
1972 // ldm/stm later on.
1973 while (EmittedNumMemOps < NumMemOps) {
1975 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
1976 Loads[i] = DAG.getLoad(VT, dl, Chain,
1977 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
1978 DAG.getConstant(SrcOff, MVT::i32)),
1979 SrcSV, SrcSVOff + SrcOff);
1980 TFOps[i] = Loads[i].getValue(1);
1983 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
1986 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
1987 TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
1988 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
1989 DAG.getConstant(DstOff, MVT::i32)),
1990 DstSV, DstSVOff + DstOff);
1993 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
1995 EmittedNumMemOps += i;
2001 // Issue loads / stores for the trailing (1 - 3) bytes.
2002 unsigned BytesLeftSave = BytesLeft;
2005 if (BytesLeft >= 2) {
2013 Loads[i] = DAG.getLoad(VT, dl, Chain,
2014 DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
2015 DAG.getConstant(SrcOff, MVT::i32)),
2016 SrcSV, SrcSVOff + SrcOff);
2017 TFOps[i] = Loads[i].getValue(1);
2020 BytesLeft -= VTSize;
2022 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
2025 BytesLeft = BytesLeftSave;
2027 if (BytesLeft >= 2) {
2035 TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
2036 DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
2037 DAG.getConstant(DstOff, MVT::i32)),
2038 DstSV, DstSVOff + DstOff);
2041 BytesLeft -= VTSize;
2043 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
2046 static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
2047 SDValue Op = N->getOperand(0);
2048 DebugLoc dl = N->getDebugLoc();
2049 if (N->getValueType(0) == MVT::f64) {
2050 // Turn i64->f64 into FMDRR.
2051 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2052 DAG.getConstant(0, MVT::i32));
2053 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2054 DAG.getConstant(1, MVT::i32));
2055 return DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
2058 // Turn f64->i64 into FMRRD.
2059 SDValue Cvt = DAG.getNode(ARMISD::FMRRD, dl,
2060 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
2062 // Merge the pieces into a single i64 value.
2063 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
2066 /// getZeroVector - Returns a vector of specified type with all zero elements.
2068 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2069 assert(VT.isVector() && "Expected a vector type");
2071 // Zero vectors are used to represent vector negation and in those cases
2072 // will be implemented with the NEON VNEG instruction. However, VNEG does
2073 // not support i64 elements, so sometimes the zero vectors will need to be
2074 // explicitly constructed. For those cases, and potentially other uses in
2075 // the future, always build zero vectors as <4 x i32> or <2 x i32> bitcasted
2076 // to their dest type. This ensures they get CSE'd.
2078 SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
2079 if (VT.getSizeInBits() == 64)
2080 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
2082 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
2084 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2087 /// getOnesVector - Returns a vector of specified type with all bits set.
2089 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2090 assert(VT.isVector() && "Expected a vector type");
2092 // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest
2093 // type. This ensures they get CSE'd.
2095 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
2096 if (VT.getSizeInBits() == 64)
2097 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
2099 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
2101 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2104 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
2105 const ARMSubtarget *ST) {
2106 EVT VT = N->getValueType(0);
2107 DebugLoc dl = N->getDebugLoc();
2109 // Lower vector shifts on NEON to use VSHL.
2110 if (VT.isVector()) {
2111 assert(ST->hasNEON() && "unexpected vector shift");
2113 // Left shifts translate directly to the vshiftu intrinsic.
2114 if (N->getOpcode() == ISD::SHL)
2115 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2116 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
2117 N->getOperand(0), N->getOperand(1));
2119 assert((N->getOpcode() == ISD::SRA ||
2120 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
2122 // NEON uses the same intrinsics for both left and right shifts. For
2123 // right shifts, the shift amounts are negative, so negate the vector of
2125 EVT ShiftVT = N->getOperand(1).getValueType();
2126 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
2127 getZeroVector(ShiftVT, DAG, dl),
2129 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
2130 Intrinsic::arm_neon_vshifts :
2131 Intrinsic::arm_neon_vshiftu);
2132 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2133 DAG.getConstant(vshiftInt, MVT::i32),
2134 N->getOperand(0), NegatedCount);
2137 // We can get here for a node like i32 = ISD::SHL i32, i64
2141 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
2142 "Unknown shift to lower!");
2144 // We only lower SRA, SRL of 1 here, all others use generic lowering.
2145 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
2146 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
2149 // If we are in thumb mode, we don't have RRX.
2150 if (ST->isThumb1Only()) return SDValue();
2152 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
2153 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2154 DAG.getConstant(0, MVT::i32));
2155 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2156 DAG.getConstant(1, MVT::i32));
2158 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
2159 // captures the result into a carry flag.
2160 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
2161 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
2163 // The low part is an ARMISD::RRX operand, which shifts the carry in.
2164 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
2166 // Merge the pieces into a single i64 value.
2167 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
2170 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
2171 SDValue TmpOp0, TmpOp1;
2172 bool Invert = false;
2176 SDValue Op0 = Op.getOperand(0);
2177 SDValue Op1 = Op.getOperand(1);
2178 SDValue CC = Op.getOperand(2);
2179 EVT VT = Op.getValueType();
2180 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
2181 DebugLoc dl = Op.getDebugLoc();
2183 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
2184 switch (SetCCOpcode) {
2185 default: llvm_unreachable("Illegal FP comparison"); break;
2187 case ISD::SETNE: Invert = true; // Fallthrough
2189 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2191 case ISD::SETLT: Swap = true; // Fallthrough
2193 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2195 case ISD::SETLE: Swap = true; // Fallthrough
2197 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2198 case ISD::SETUGE: Swap = true; // Fallthrough
2199 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
2200 case ISD::SETUGT: Swap = true; // Fallthrough
2201 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
2202 case ISD::SETUEQ: Invert = true; // Fallthrough
2204 // Expand this to (OLT | OGT).
2208 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2209 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
2211 case ISD::SETUO: Invert = true; // Fallthrough
2213 // Expand this to (OLT | OGE).
2217 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2218 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
2222 // Integer comparisons.
2223 switch (SetCCOpcode) {
2224 default: llvm_unreachable("Illegal integer comparison"); break;
2225 case ISD::SETNE: Invert = true;
2226 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
2227 case ISD::SETLT: Swap = true;
2228 case ISD::SETGT: Opc = ARMISD::VCGT; break;
2229 case ISD::SETLE: Swap = true;
2230 case ISD::SETGE: Opc = ARMISD::VCGE; break;
2231 case ISD::SETULT: Swap = true;
2232 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
2233 case ISD::SETULE: Swap = true;
2234 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
2237 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
2238 if (Opc == ARMISD::VCEQ) {
2241 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
2243 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
2246 // Ignore bitconvert.
2247 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BIT_CONVERT)
2248 AndOp = AndOp.getOperand(0);
2250 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
2252 Op0 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(0));
2253 Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(1));
2260 std::swap(Op0, Op1);
2262 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
2265 Result = DAG.getNOT(dl, Result, VT);
2270 /// isVMOVSplat - Check if the specified splat value corresponds to an immediate
2271 /// VMOV instruction, and if so, return the constant being splatted.
2272 static SDValue isVMOVSplat(uint64_t SplatBits, uint64_t SplatUndef,
2273 unsigned SplatBitSize, SelectionDAG &DAG) {
2274 switch (SplatBitSize) {
2276 // Any 1-byte value is OK.
2277 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
2278 return DAG.getTargetConstant(SplatBits, MVT::i8);
2281 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
2282 if ((SplatBits & ~0xff) == 0 ||
2283 (SplatBits & ~0xff00) == 0)
2284 return DAG.getTargetConstant(SplatBits, MVT::i16);
2288 // NEON's 32-bit VMOV supports splat values where:
2289 // * only one byte is nonzero, or
2290 // * the least significant byte is 0xff and the second byte is nonzero, or
2291 // * the least significant 2 bytes are 0xff and the third is nonzero.
2292 if ((SplatBits & ~0xff) == 0 ||
2293 (SplatBits & ~0xff00) == 0 ||
2294 (SplatBits & ~0xff0000) == 0 ||
2295 (SplatBits & ~0xff000000) == 0)
2296 return DAG.getTargetConstant(SplatBits, MVT::i32);
2298 if ((SplatBits & ~0xffff) == 0 &&
2299 ((SplatBits | SplatUndef) & 0xff) == 0xff)
2300 return DAG.getTargetConstant(SplatBits | 0xff, MVT::i32);
2302 if ((SplatBits & ~0xffffff) == 0 &&
2303 ((SplatBits | SplatUndef) & 0xffff) == 0xffff)
2304 return DAG.getTargetConstant(SplatBits | 0xffff, MVT::i32);
2306 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
2307 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
2308 // VMOV.I32. A (very) minor optimization would be to replicate the value
2309 // and fall through here to test for a valid 64-bit splat. But, then the
2310 // caller would also need to check and handle the change in size.
2314 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
2315 uint64_t BitMask = 0xff;
2317 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
2318 if (((SplatBits | SplatUndef) & BitMask) == BitMask)
2320 else if ((SplatBits & BitMask) != 0)
2324 return DAG.getTargetConstant(Val, MVT::i64);
2328 llvm_unreachable("unexpected size for isVMOVSplat");
2335 /// getVMOVImm - If this is a build_vector of constants which can be
2336 /// formed by using a VMOV instruction of the specified element size,
2337 /// return the constant being splatted. The ByteSize field indicates the
2338 /// number of bytes of each element [1248].
2339 SDValue ARM::getVMOVImm(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
2340 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N);
2341 APInt SplatBits, SplatUndef;
2342 unsigned SplatBitSize;
2344 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
2345 HasAnyUndefs, ByteSize * 8))
2348 if (SplatBitSize > ByteSize * 8)
2351 return isVMOVSplat(SplatBits.getZExtValue(), SplatUndef.getZExtValue(),
2355 static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT,
2356 bool &ReverseVEXT, unsigned &Imm) {
2357 unsigned NumElts = VT.getVectorNumElements();
2358 ReverseVEXT = false;
2361 // If this is a VEXT shuffle, the immediate value is the index of the first
2362 // element. The other shuffle indices must be the successive elements after
2364 unsigned ExpectedElt = Imm;
2365 for (unsigned i = 1; i < NumElts; ++i) {
2366 // Increment the expected index. If it wraps around, it may still be
2367 // a VEXT but the source vectors must be swapped.
2369 if (ExpectedElt == NumElts * 2) {
2374 if (ExpectedElt != static_cast<unsigned>(M[i]))
2378 // Adjust the index value if the source operands will be swapped.
2385 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
2386 /// instruction with the specified blocksize. (The order of the elements
2387 /// within each block of the vector is reversed.)
2388 static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT,
2389 unsigned BlockSize) {
2390 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
2391 "Only possible block sizes for VREV are: 16, 32, 64");
2393 unsigned NumElts = VT.getVectorNumElements();
2394 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2395 unsigned BlockElts = M[0] + 1;
2397 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
2400 for (unsigned i = 0; i < NumElts; ++i) {
2401 if ((unsigned) M[i] !=
2402 (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
2409 static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT,
2410 unsigned &WhichResult) {
2411 unsigned NumElts = VT.getVectorNumElements();
2412 WhichResult = (M[0] == 0 ? 0 : 1);
2413 for (unsigned i = 0; i < NumElts; i += 2) {
2414 if ((unsigned) M[i] != i + WhichResult ||
2415 (unsigned) M[i+1] != i + NumElts + WhichResult)
2421 static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT,
2422 unsigned &WhichResult) {
2423 unsigned NumElts = VT.getVectorNumElements();
2424 WhichResult = (M[0] == 0 ? 0 : 1);
2425 for (unsigned i = 0; i != NumElts; ++i) {
2426 if ((unsigned) M[i] != 2 * i + WhichResult)
2430 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
2431 if (VT.is64BitVector() && VT.getVectorElementType().getSizeInBits() == 32)
2437 static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT,
2438 unsigned &WhichResult) {
2439 unsigned NumElts = VT.getVectorNumElements();
2440 WhichResult = (M[0] == 0 ? 0 : 1);
2441 unsigned Idx = WhichResult * NumElts / 2;
2442 for (unsigned i = 0; i != NumElts; i += 2) {
2443 if ((unsigned) M[i] != Idx ||
2444 (unsigned) M[i+1] != Idx + NumElts)
2449 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
2450 if (VT.is64BitVector() && VT.getVectorElementType().getSizeInBits() == 32)
2456 static SDValue BuildSplat(SDValue Val, EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2457 // Canonicalize all-zeros and all-ones vectors.
2458 ConstantSDNode *ConstVal = cast<ConstantSDNode>(Val.getNode());
2459 if (ConstVal->isNullValue())
2460 return getZeroVector(VT, DAG, dl);
2461 if (ConstVal->isAllOnesValue())
2462 return getOnesVector(VT, DAG, dl);
2465 if (VT.is64BitVector()) {
2466 switch (Val.getValueType().getSizeInBits()) {
2467 case 8: CanonicalVT = MVT::v8i8; break;
2468 case 16: CanonicalVT = MVT::v4i16; break;
2469 case 32: CanonicalVT = MVT::v2i32; break;
2470 case 64: CanonicalVT = MVT::v1i64; break;
2471 default: llvm_unreachable("unexpected splat element type"); break;
2474 assert(VT.is128BitVector() && "unknown splat vector size");
2475 switch (Val.getValueType().getSizeInBits()) {
2476 case 8: CanonicalVT = MVT::v16i8; break;
2477 case 16: CanonicalVT = MVT::v8i16; break;
2478 case 32: CanonicalVT = MVT::v4i32; break;
2479 case 64: CanonicalVT = MVT::v2i64; break;
2480 default: llvm_unreachable("unexpected splat element type"); break;
2484 // Build a canonical splat for this value.
2485 SmallVector<SDValue, 8> Ops;
2486 Ops.assign(CanonicalVT.getVectorNumElements(), Val);
2487 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, &Ops[0],
2489 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Res);
2492 // If this is a case we can't handle, return null and let the default
2493 // expansion code take care of it.
2494 static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
2495 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
2496 DebugLoc dl = Op.getDebugLoc();
2497 EVT VT = Op.getValueType();
2499 APInt SplatBits, SplatUndef;
2500 unsigned SplatBitSize;
2502 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
2503 SDValue Val = isVMOVSplat(SplatBits.getZExtValue(),
2504 SplatUndef.getZExtValue(), SplatBitSize, DAG);
2506 return BuildSplat(Val, VT, DAG, dl);
2509 // If there are only 2 elements in a 128-bit vector, insert them into an
2510 // undef vector. This handles the common case for 128-bit vector argument
2511 // passing, where the insertions should be translated to subreg accesses
2512 // with no real instructions.
2513 if (VT.is128BitVector() && Op.getNumOperands() == 2) {
2514 SDValue Val = DAG.getUNDEF(VT);
2515 SDValue Op0 = Op.getOperand(0);
2516 SDValue Op1 = Op.getOperand(1);
2517 if (Op0.getOpcode() != ISD::UNDEF)
2518 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, Op0,
2519 DAG.getIntPtrConstant(0));
2520 if (Op1.getOpcode() != ISD::UNDEF)
2521 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, Op1,
2522 DAG.getIntPtrConstant(1));
2529 /// isShuffleMaskLegal - Targets can use this to indicate that they only
2530 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
2531 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
2532 /// are assumed to be legal.
2534 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
2536 if (VT.getVectorNumElements() == 4 &&
2537 (VT.is128BitVector() || VT.is64BitVector())) {
2538 unsigned PFIndexes[4];
2539 for (unsigned i = 0; i != 4; ++i) {
2543 PFIndexes[i] = M[i];
2546 // Compute the index in the perfect shuffle table.
2547 unsigned PFTableIndex =
2548 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
2549 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
2550 unsigned Cost = (PFEntry >> 30);
2557 unsigned Imm, WhichResult;
2559 return (ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
2560 isVREVMask(M, VT, 64) ||
2561 isVREVMask(M, VT, 32) ||
2562 isVREVMask(M, VT, 16) ||
2563 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
2564 isVTRNMask(M, VT, WhichResult) ||
2565 isVUZPMask(M, VT, WhichResult) ||
2566 isVZIPMask(M, VT, WhichResult));
2569 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
2570 /// the specified operations to build the shuffle.
2571 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
2572 SDValue RHS, SelectionDAG &DAG,
2574 unsigned OpNum = (PFEntry >> 26) & 0x0F;
2575 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
2576 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
2579 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
2588 OP_VUZPL, // VUZP, left result
2589 OP_VUZPR, // VUZP, right result
2590 OP_VZIPL, // VZIP, left result
2591 OP_VZIPR, // VZIP, right result
2592 OP_VTRNL, // VTRN, left result
2593 OP_VTRNR // VTRN, right result
2596 if (OpNum == OP_COPY) {
2597 if (LHSID == (1*9+2)*9+3) return LHS;
2598 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
2602 SDValue OpLHS, OpRHS;
2603 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
2604 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
2605 EVT VT = OpLHS.getValueType();
2608 default: llvm_unreachable("Unknown shuffle opcode!");
2610 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
2615 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
2616 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
2620 return DAG.getNode(ARMISD::VEXT, dl, VT,
2622 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
2625 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
2626 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
2629 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
2630 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
2633 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
2634 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
2638 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
2639 SDValue V1 = Op.getOperand(0);
2640 SDValue V2 = Op.getOperand(1);
2641 DebugLoc dl = Op.getDebugLoc();
2642 EVT VT = Op.getValueType();
2643 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
2644 SmallVector<int, 8> ShuffleMask;
2646 // Convert shuffles that are directly supported on NEON to target-specific
2647 // DAG nodes, instead of keeping them as shuffles and matching them again
2648 // during code selection. This is more efficient and avoids the possibility
2649 // of inconsistencies between legalization and selection.
2650 // FIXME: floating-point vectors should be canonicalized to integer vectors
2651 // of the same time so that they get CSEd properly.
2652 SVN->getMask(ShuffleMask);
2654 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
2655 int Lane = SVN->getSplatIndex();
2656 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
2657 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
2659 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
2660 DAG.getConstant(Lane, MVT::i32));
2665 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
2668 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
2669 DAG.getConstant(Imm, MVT::i32));
2672 if (isVREVMask(ShuffleMask, VT, 64))
2673 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
2674 if (isVREVMask(ShuffleMask, VT, 32))
2675 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
2676 if (isVREVMask(ShuffleMask, VT, 16))
2677 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
2679 // Check for Neon shuffles that modify both input vectors in place.
2680 // If both results are used, i.e., if there are two shuffles with the same
2681 // source operands and with masks corresponding to both results of one of
2682 // these operations, DAG memoization will ensure that a single node is
2683 // used for both shuffles.
2684 unsigned WhichResult;
2685 if (isVTRNMask(ShuffleMask, VT, WhichResult))
2686 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
2687 V1, V2).getValue(WhichResult);
2688 if (isVUZPMask(ShuffleMask, VT, WhichResult))
2689 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
2690 V1, V2).getValue(WhichResult);
2691 if (isVZIPMask(ShuffleMask, VT, WhichResult))
2692 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
2693 V1, V2).getValue(WhichResult);
2695 // If the shuffle is not directly supported and it has 4 elements, use
2696 // the PerfectShuffle-generated table to synthesize it from other shuffles.
2697 if (VT.getVectorNumElements() == 4 &&
2698 (VT.is128BitVector() || VT.is64BitVector())) {
2699 unsigned PFIndexes[4];
2700 for (unsigned i = 0; i != 4; ++i) {
2701 if (ShuffleMask[i] < 0)
2704 PFIndexes[i] = ShuffleMask[i];
2707 // Compute the index in the perfect shuffle table.
2708 unsigned PFTableIndex =
2709 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
2711 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
2712 unsigned Cost = (PFEntry >> 30);
2715 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
2721 static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
2725 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
2726 EVT VT = Op.getValueType();
2727 DebugLoc dl = Op.getDebugLoc();
2728 assert((VT == MVT::i8 || VT == MVT::i16) &&
2729 "unexpected type for custom-lowering vector extract");
2730 SDValue Vec = Op.getOperand(0);
2731 SDValue Lane = Op.getOperand(1);
2732 Op = DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
2733 Op = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Op, DAG.getValueType(VT));
2734 return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
2737 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
2738 // The only time a CONCAT_VECTORS operation can have legal types is when
2739 // two 64-bit vectors are concatenated to a 128-bit vector.
2740 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
2741 "unexpected CONCAT_VECTORS");
2742 DebugLoc dl = Op.getDebugLoc();
2743 SDValue Val = DAG.getUNDEF(MVT::v2f64);
2744 SDValue Op0 = Op.getOperand(0);
2745 SDValue Op1 = Op.getOperand(1);
2746 if (Op0.getOpcode() != ISD::UNDEF)
2747 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
2748 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op0),
2749 DAG.getIntPtrConstant(0));
2750 if (Op1.getOpcode() != ISD::UNDEF)
2751 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
2752 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op1),
2753 DAG.getIntPtrConstant(1));
2754 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Val);
2757 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
2758 switch (Op.getOpcode()) {
2759 default: llvm_unreachable("Don't know how to custom lower this!");
2760 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2761 case ISD::GlobalAddress:
2762 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
2763 LowerGlobalAddressELF(Op, DAG);
2764 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
2765 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, Subtarget);
2766 case ISD::BR_CC: return LowerBR_CC(Op, DAG, Subtarget);
2767 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
2768 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
2769 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex);
2770 case ISD::SINT_TO_FP:
2771 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
2772 case ISD::FP_TO_SINT:
2773 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
2774 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
2775 case ISD::RETURNADDR: break;
2776 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
2777 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
2778 case ISD::INTRINSIC_VOID:
2779 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
2780 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2781 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(Op.getNode(), DAG);
2784 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
2785 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
2786 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
2787 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
2788 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
2789 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
2790 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
2795 /// ReplaceNodeResults - Replace the results of node with an illegal result
2796 /// type with new values built out of custom code.
2797 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
2798 SmallVectorImpl<SDValue>&Results,
2799 SelectionDAG &DAG) {
2800 switch (N->getOpcode()) {
2802 llvm_unreachable("Don't know how to custom expand this!");
2804 case ISD::BIT_CONVERT:
2805 Results.push_back(ExpandBIT_CONVERT(N, DAG));
2809 SDValue Res = LowerShift(N, DAG, Subtarget);
2811 Results.push_back(Res);
2817 //===----------------------------------------------------------------------===//
2818 // ARM Scheduler Hooks
2819 //===----------------------------------------------------------------------===//
2822 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
2823 MachineBasicBlock *BB) const {
2824 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2825 DebugLoc dl = MI->getDebugLoc();
2826 switch (MI->getOpcode()) {
2828 llvm_unreachable("Unexpected instr type to insert");
2829 case ARM::tMOVCCr_pseudo: {
2830 // To "insert" a SELECT_CC instruction, we actually have to insert the
2831 // diamond control-flow pattern. The incoming instruction knows the
2832 // destination vreg to set, the condition code register to branch on, the
2833 // true/false values to select between, and a branch opcode to use.
2834 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2835 MachineFunction::iterator It = BB;
2841 // cmpTY ccX, r1, r2
2843 // fallthrough --> copy0MBB
2844 MachineBasicBlock *thisMBB = BB;
2845 MachineFunction *F = BB->getParent();
2846 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
2847 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
2848 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
2849 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
2850 F->insert(It, copy0MBB);
2851 F->insert(It, sinkMBB);
2852 // Update machine-CFG edges by first adding all successors of the current
2853 // block to the new block which will contain the Phi node for the select.
2854 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
2855 e = BB->succ_end(); i != e; ++i)
2856 sinkMBB->addSuccessor(*i);
2857 // Next, remove all successors of the current block, and add the true
2858 // and fallthrough blocks as its successors.
2859 while(!BB->succ_empty())
2860 BB->removeSuccessor(BB->succ_begin());
2861 BB->addSuccessor(copy0MBB);
2862 BB->addSuccessor(sinkMBB);
2865 // %FalseValue = ...
2866 // # fallthrough to sinkMBB
2869 // Update machine-CFG edges
2870 BB->addSuccessor(sinkMBB);
2873 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
2876 BuildMI(BB, dl, TII->get(ARM::PHI), MI->getOperand(0).getReg())
2877 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
2878 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
2880 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
2887 case ARM::t2SUBrSPi_:
2888 case ARM::t2SUBrSPi12_:
2889 case ARM::t2SUBrSPs_: {
2890 MachineFunction *MF = BB->getParent();
2891 unsigned DstReg = MI->getOperand(0).getReg();
2892 unsigned SrcReg = MI->getOperand(1).getReg();
2893 bool DstIsDead = MI->getOperand(0).isDead();
2894 bool SrcIsKill = MI->getOperand(1).isKill();
2896 if (SrcReg != ARM::SP) {
2897 // Copy the source to SP from virtual register.
2898 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(SrcReg);
2899 unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
2900 ? ARM::tMOVtgpr2gpr : ARM::tMOVgpr2gpr;
2901 BuildMI(BB, dl, TII->get(CopyOpc), ARM::SP)
2902 .addReg(SrcReg, getKillRegState(SrcIsKill));
2906 bool NeedPred = false, NeedCC = false, NeedOp3 = false;
2907 switch (MI->getOpcode()) {
2909 llvm_unreachable("Unexpected pseudo instruction!");
2915 OpOpc = ARM::tADDspr;
2918 OpOpc = ARM::tSUBspi;
2920 case ARM::t2SUBrSPi_:
2921 OpOpc = ARM::t2SUBrSPi;
2922 NeedPred = true; NeedCC = true;
2924 case ARM::t2SUBrSPi12_:
2925 OpOpc = ARM::t2SUBrSPi12;
2928 case ARM::t2SUBrSPs_:
2929 OpOpc = ARM::t2SUBrSPs;
2930 NeedPred = true; NeedCC = true; NeedOp3 = true;
2933 MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(OpOpc), ARM::SP);
2934 if (OpOpc == ARM::tAND)
2935 AddDefaultT1CC(MIB);
2936 MIB.addReg(ARM::SP);
2937 MIB.addOperand(MI->getOperand(2));
2939 MIB.addOperand(MI->getOperand(3));
2941 AddDefaultPred(MIB);
2945 // Copy the result from SP to virtual register.
2946 const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(DstReg);
2947 unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
2948 ? ARM::tMOVgpr2tgpr : ARM::tMOVgpr2gpr;
2949 BuildMI(BB, dl, TII->get(CopyOpc))
2950 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead))
2952 MF->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
2958 //===----------------------------------------------------------------------===//
2959 // ARM Optimization Hooks
2960 //===----------------------------------------------------------------------===//
2963 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
2964 TargetLowering::DAGCombinerInfo &DCI) {
2965 SelectionDAG &DAG = DCI.DAG;
2966 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2967 EVT VT = N->getValueType(0);
2968 unsigned Opc = N->getOpcode();
2969 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
2970 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
2971 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
2972 ISD::CondCode CC = ISD::SETCC_INVALID;
2975 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
2977 SDValue CCOp = Slct.getOperand(0);
2978 if (CCOp.getOpcode() == ISD::SETCC)
2979 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
2982 bool DoXform = false;
2984 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
2987 if (LHS.getOpcode() == ISD::Constant &&
2988 cast<ConstantSDNode>(LHS)->isNullValue()) {
2990 } else if (CC != ISD::SETCC_INVALID &&
2991 RHS.getOpcode() == ISD::Constant &&
2992 cast<ConstantSDNode>(RHS)->isNullValue()) {
2993 std::swap(LHS, RHS);
2994 SDValue Op0 = Slct.getOperand(0);
2995 EVT OpVT = isSlctCC ? Op0.getValueType() :
2996 Op0.getOperand(0).getValueType();
2997 bool isInt = OpVT.isInteger();
2998 CC = ISD::getSetCCInverse(CC, isInt);
3000 if (!TLI.isCondCodeLegal(CC, OpVT))
3001 return SDValue(); // Inverse operator isn't legal.
3008 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
3010 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
3011 Slct.getOperand(0), Slct.getOperand(1), CC);
3012 SDValue CCOp = Slct.getOperand(0);
3014 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
3015 CCOp.getOperand(0), CCOp.getOperand(1), CC);
3016 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
3017 CCOp, OtherOp, Result);
3022 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
3023 static SDValue PerformADDCombine(SDNode *N,
3024 TargetLowering::DAGCombinerInfo &DCI) {
3025 // added by evan in r37685 with no testcase.
3026 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
3028 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
3029 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
3030 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
3031 if (Result.getNode()) return Result;
3033 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
3034 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
3035 if (Result.getNode()) return Result;
3041 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
3042 static SDValue PerformSUBCombine(SDNode *N,
3043 TargetLowering::DAGCombinerInfo &DCI) {
3044 // added by evan in r37685 with no testcase.
3045 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
3047 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
3048 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
3049 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
3050 if (Result.getNode()) return Result;
3057 /// PerformFMRRDCombine - Target-specific dag combine xforms for ARMISD::FMRRD.
3058 static SDValue PerformFMRRDCombine(SDNode *N,
3059 TargetLowering::DAGCombinerInfo &DCI) {
3060 // fmrrd(fmdrr x, y) -> x,y
3061 SDValue InDouble = N->getOperand(0);
3062 if (InDouble.getOpcode() == ARMISD::FMDRR)
3063 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
3067 /// getVShiftImm - Check if this is a valid build_vector for the immediate
3068 /// operand of a vector shift operation, where all the elements of the
3069 /// build_vector must have the same constant integer value.
3070 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
3071 // Ignore bit_converts.
3072 while (Op.getOpcode() == ISD::BIT_CONVERT)
3073 Op = Op.getOperand(0);
3074 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
3075 APInt SplatBits, SplatUndef;
3076 unsigned SplatBitSize;
3078 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
3079 HasAnyUndefs, ElementBits) ||
3080 SplatBitSize > ElementBits)
3082 Cnt = SplatBits.getSExtValue();
3086 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
3087 /// operand of a vector shift left operation. That value must be in the range:
3088 /// 0 <= Value < ElementBits for a left shift; or
3089 /// 0 <= Value <= ElementBits for a long left shift.
3090 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
3091 assert(VT.isVector() && "vector shift count is not a vector type");
3092 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
3093 if (! getVShiftImm(Op, ElementBits, Cnt))
3095 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
3098 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
3099 /// operand of a vector shift right operation. For a shift opcode, the value
3100 /// is positive, but for an intrinsic the value count must be negative. The
3101 /// absolute value must be in the range:
3102 /// 1 <= |Value| <= ElementBits for a right shift; or
3103 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
3104 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
3106 assert(VT.isVector() && "vector shift count is not a vector type");
3107 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
3108 if (! getVShiftImm(Op, ElementBits, Cnt))
3112 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
3115 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
3116 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
3117 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
3120 // Don't do anything for most intrinsics.
3123 // Vector shifts: check for immediate versions and lower them.
3124 // Note: This is done during DAG combining instead of DAG legalizing because
3125 // the build_vectors for 64-bit vector element shift counts are generally
3126 // not legal, and it is hard to see their values after they get legalized to
3127 // loads from a constant pool.
3128 case Intrinsic::arm_neon_vshifts:
3129 case Intrinsic::arm_neon_vshiftu:
3130 case Intrinsic::arm_neon_vshiftls:
3131 case Intrinsic::arm_neon_vshiftlu:
3132 case Intrinsic::arm_neon_vshiftn:
3133 case Intrinsic::arm_neon_vrshifts:
3134 case Intrinsic::arm_neon_vrshiftu:
3135 case Intrinsic::arm_neon_vrshiftn:
3136 case Intrinsic::arm_neon_vqshifts:
3137 case Intrinsic::arm_neon_vqshiftu:
3138 case Intrinsic::arm_neon_vqshiftsu:
3139 case Intrinsic::arm_neon_vqshiftns:
3140 case Intrinsic::arm_neon_vqshiftnu:
3141 case Intrinsic::arm_neon_vqshiftnsu:
3142 case Intrinsic::arm_neon_vqrshiftns:
3143 case Intrinsic::arm_neon_vqrshiftnu:
3144 case Intrinsic::arm_neon_vqrshiftnsu: {
3145 EVT VT = N->getOperand(1).getValueType();
3147 unsigned VShiftOpc = 0;
3150 case Intrinsic::arm_neon_vshifts:
3151 case Intrinsic::arm_neon_vshiftu:
3152 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
3153 VShiftOpc = ARMISD::VSHL;
3156 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
3157 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
3158 ARMISD::VSHRs : ARMISD::VSHRu);
3163 case Intrinsic::arm_neon_vshiftls:
3164 case Intrinsic::arm_neon_vshiftlu:
3165 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
3167 llvm_unreachable("invalid shift count for vshll intrinsic");
3169 case Intrinsic::arm_neon_vrshifts:
3170 case Intrinsic::arm_neon_vrshiftu:
3171 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
3175 case Intrinsic::arm_neon_vqshifts:
3176 case Intrinsic::arm_neon_vqshiftu:
3177 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
3181 case Intrinsic::arm_neon_vqshiftsu:
3182 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
3184 llvm_unreachable("invalid shift count for vqshlu intrinsic");
3186 case Intrinsic::arm_neon_vshiftn:
3187 case Intrinsic::arm_neon_vrshiftn:
3188 case Intrinsic::arm_neon_vqshiftns:
3189 case Intrinsic::arm_neon_vqshiftnu:
3190 case Intrinsic::arm_neon_vqshiftnsu:
3191 case Intrinsic::arm_neon_vqrshiftns:
3192 case Intrinsic::arm_neon_vqrshiftnu:
3193 case Intrinsic::arm_neon_vqrshiftnsu:
3194 // Narrowing shifts require an immediate right shift.
3195 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
3197 llvm_unreachable("invalid shift count for narrowing vector shift intrinsic");
3200 llvm_unreachable("unhandled vector shift");
3204 case Intrinsic::arm_neon_vshifts:
3205 case Intrinsic::arm_neon_vshiftu:
3206 // Opcode already set above.
3208 case Intrinsic::arm_neon_vshiftls:
3209 case Intrinsic::arm_neon_vshiftlu:
3210 if (Cnt == VT.getVectorElementType().getSizeInBits())
3211 VShiftOpc = ARMISD::VSHLLi;
3213 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
3214 ARMISD::VSHLLs : ARMISD::VSHLLu);
3216 case Intrinsic::arm_neon_vshiftn:
3217 VShiftOpc = ARMISD::VSHRN; break;
3218 case Intrinsic::arm_neon_vrshifts:
3219 VShiftOpc = ARMISD::VRSHRs; break;
3220 case Intrinsic::arm_neon_vrshiftu:
3221 VShiftOpc = ARMISD::VRSHRu; break;
3222 case Intrinsic::arm_neon_vrshiftn:
3223 VShiftOpc = ARMISD::VRSHRN; break;
3224 case Intrinsic::arm_neon_vqshifts:
3225 VShiftOpc = ARMISD::VQSHLs; break;
3226 case Intrinsic::arm_neon_vqshiftu:
3227 VShiftOpc = ARMISD::VQSHLu; break;
3228 case Intrinsic::arm_neon_vqshiftsu:
3229 VShiftOpc = ARMISD::VQSHLsu; break;
3230 case Intrinsic::arm_neon_vqshiftns:
3231 VShiftOpc = ARMISD::VQSHRNs; break;
3232 case Intrinsic::arm_neon_vqshiftnu:
3233 VShiftOpc = ARMISD::VQSHRNu; break;
3234 case Intrinsic::arm_neon_vqshiftnsu:
3235 VShiftOpc = ARMISD::VQSHRNsu; break;
3236 case Intrinsic::arm_neon_vqrshiftns:
3237 VShiftOpc = ARMISD::VQRSHRNs; break;
3238 case Intrinsic::arm_neon_vqrshiftnu:
3239 VShiftOpc = ARMISD::VQRSHRNu; break;
3240 case Intrinsic::arm_neon_vqrshiftnsu:
3241 VShiftOpc = ARMISD::VQRSHRNsu; break;
3244 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
3245 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
3248 case Intrinsic::arm_neon_vshiftins: {
3249 EVT VT = N->getOperand(1).getValueType();
3251 unsigned VShiftOpc = 0;
3253 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
3254 VShiftOpc = ARMISD::VSLI;
3255 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
3256 VShiftOpc = ARMISD::VSRI;
3258 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
3261 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
3262 N->getOperand(1), N->getOperand(2),
3263 DAG.getConstant(Cnt, MVT::i32));
3266 case Intrinsic::arm_neon_vqrshifts:
3267 case Intrinsic::arm_neon_vqrshiftu:
3268 // No immediate versions of these to check for.
3275 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
3276 /// lowers them. As with the vector shift intrinsics, this is done during DAG
3277 /// combining instead of DAG legalizing because the build_vectors for 64-bit
3278 /// vector element shift counts are generally not legal, and it is hard to see
3279 /// their values after they get legalized to loads from a constant pool.
3280 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
3281 const ARMSubtarget *ST) {
3282 EVT VT = N->getValueType(0);
3284 // Nothing to be done for scalar shifts.
3285 if (! VT.isVector())
3288 assert(ST->hasNEON() && "unexpected vector shift");
3291 switch (N->getOpcode()) {
3292 default: llvm_unreachable("unexpected shift opcode");
3295 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
3296 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
3297 DAG.getConstant(Cnt, MVT::i32));
3302 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
3303 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
3304 ARMISD::VSHRs : ARMISD::VSHRu);
3305 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
3306 DAG.getConstant(Cnt, MVT::i32));
3312 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
3313 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
3314 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
3315 const ARMSubtarget *ST) {
3316 SDValue N0 = N->getOperand(0);
3318 // Check for sign- and zero-extensions of vector extract operations of 8-
3319 // and 16-bit vector elements. NEON supports these directly. They are
3320 // handled during DAG combining because type legalization will promote them
3321 // to 32-bit types and it is messy to recognize the operations after that.
3322 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
3323 SDValue Vec = N0.getOperand(0);
3324 SDValue Lane = N0.getOperand(1);
3325 EVT VT = N->getValueType(0);
3326 EVT EltVT = N0.getValueType();
3327 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3329 if (VT == MVT::i32 &&
3330 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
3331 TLI.isTypeLegal(Vec.getValueType())) {
3334 switch (N->getOpcode()) {
3335 default: llvm_unreachable("unexpected opcode");
3336 case ISD::SIGN_EXTEND:
3337 Opc = ARMISD::VGETLANEs;
3339 case ISD::ZERO_EXTEND:
3340 case ISD::ANY_EXTEND:
3341 Opc = ARMISD::VGETLANEu;
3344 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
3351 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
3352 DAGCombinerInfo &DCI) const {
3353 switch (N->getOpcode()) {
3355 case ISD::ADD: return PerformADDCombine(N, DCI);
3356 case ISD::SUB: return PerformSUBCombine(N, DCI);
3357 case ARMISD::FMRRD: return PerformFMRRDCombine(N, DCI);
3358 case ISD::INTRINSIC_WO_CHAIN:
3359 return PerformIntrinsicCombine(N, DCI.DAG);
3363 return PerformShiftCombine(N, DCI.DAG, Subtarget);
3364 case ISD::SIGN_EXTEND:
3365 case ISD::ZERO_EXTEND:
3366 case ISD::ANY_EXTEND:
3367 return PerformExtendCombine(N, DCI.DAG, Subtarget);
3372 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
3373 if (!Subtarget->hasV6Ops())
3374 // Pre-v6 does not support unaligned mem access.
3376 else if (!Subtarget->hasV6Ops()) {
3377 // v6 may or may not support unaligned mem access.
3378 if (!Subtarget->isTargetDarwin())
3382 switch (VT.getSimpleVT().SimpleTy) {
3389 // FIXME: VLD1 etc with standard alignment is legal.
3393 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
3398 switch (VT.getSimpleVT().SimpleTy) {
3399 default: return false;
3414 if ((V & (Scale - 1)) != 0)
3417 return V == (V & ((1LL << 5) - 1));
3420 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
3421 const ARMSubtarget *Subtarget) {
3428 switch (VT.getSimpleVT().SimpleTy) {
3429 default: return false;
3434 // + imm12 or - imm8
3436 return V == (V & ((1LL << 8) - 1));
3437 return V == (V & ((1LL << 12) - 1));
3440 // Same as ARM mode. FIXME: NEON?
3441 if (!Subtarget->hasVFP2())
3446 return V == (V & ((1LL << 8) - 1));
3450 /// isLegalAddressImmediate - Return true if the integer value can be used
3451 /// as the offset of the target addressing mode for load / store of the
3453 static bool isLegalAddressImmediate(int64_t V, EVT VT,
3454 const ARMSubtarget *Subtarget) {
3461 if (Subtarget->isThumb1Only())
3462 return isLegalT1AddressImmediate(V, VT);
3463 else if (Subtarget->isThumb2())
3464 return isLegalT2AddressImmediate(V, VT, Subtarget);
3469 switch (VT.getSimpleVT().SimpleTy) {
3470 default: return false;
3475 return V == (V & ((1LL << 12) - 1));
3478 return V == (V & ((1LL << 8) - 1));
3481 if (!Subtarget->hasVFP2()) // FIXME: NEON?
3486 return V == (V & ((1LL << 8) - 1));
3490 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
3492 int Scale = AM.Scale;
3496 switch (VT.getSimpleVT().SimpleTy) {
3497 default: return false;
3506 return Scale == 2 || Scale == 4 || Scale == 8;
3509 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
3513 // Note, we allow "void" uses (basically, uses that aren't loads or
3514 // stores), because arm allows folding a scale into many arithmetic
3515 // operations. This should be made more precise and revisited later.
3517 // Allow r << imm, but the imm has to be a multiple of two.
3518 if (Scale & 1) return false;
3519 return isPowerOf2_32(Scale);
3523 /// isLegalAddressingMode - Return true if the addressing mode represented
3524 /// by AM is legal for this target, for a load/store of the specified type.
3525 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
3526 const Type *Ty) const {
3527 EVT VT = getValueType(Ty, true);
3528 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
3531 // Can never fold addr of global into load/store.
3536 case 0: // no scale reg, must be "r+i" or "r", or "i".
3539 if (Subtarget->isThumb1Only())
3543 // ARM doesn't support any R+R*scale+imm addr modes.
3550 if (Subtarget->isThumb2())
3551 return isLegalT2ScaledAddressingMode(AM, VT);
3553 int Scale = AM.Scale;
3554 switch (VT.getSimpleVT().SimpleTy) {
3555 default: return false;
3559 if (Scale < 0) Scale = -Scale;
3563 return isPowerOf2_32(Scale & ~1);
3567 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
3572 // Note, we allow "void" uses (basically, uses that aren't loads or
3573 // stores), because arm allows folding a scale into many arithmetic
3574 // operations. This should be made more precise and revisited later.
3576 // Allow r << imm, but the imm has to be a multiple of two.
3577 if (Scale & 1) return false;
3578 return isPowerOf2_32(Scale);
3585 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
3586 bool isSEXTLoad, SDValue &Base,
3587 SDValue &Offset, bool &isInc,
3588 SelectionDAG &DAG) {
3589 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
3592 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
3594 Base = Ptr->getOperand(0);
3595 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
3596 int RHSC = (int)RHS->getZExtValue();
3597 if (RHSC < 0 && RHSC > -256) {
3598 assert(Ptr->getOpcode() == ISD::ADD);
3600 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
3604 isInc = (Ptr->getOpcode() == ISD::ADD);
3605 Offset = Ptr->getOperand(1);
3607 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
3609 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
3610 int RHSC = (int)RHS->getZExtValue();
3611 if (RHSC < 0 && RHSC > -0x1000) {
3612 assert(Ptr->getOpcode() == ISD::ADD);
3614 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
3615 Base = Ptr->getOperand(0);
3620 if (Ptr->getOpcode() == ISD::ADD) {
3622 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
3623 if (ShOpcVal != ARM_AM::no_shift) {
3624 Base = Ptr->getOperand(1);
3625 Offset = Ptr->getOperand(0);
3627 Base = Ptr->getOperand(0);
3628 Offset = Ptr->getOperand(1);
3633 isInc = (Ptr->getOpcode() == ISD::ADD);
3634 Base = Ptr->getOperand(0);
3635 Offset = Ptr->getOperand(1);
3639 // FIXME: Use FLDM / FSTM to emulate indexed FP load / store.
3643 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
3644 bool isSEXTLoad, SDValue &Base,
3645 SDValue &Offset, bool &isInc,
3646 SelectionDAG &DAG) {
3647 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
3650 Base = Ptr->getOperand(0);
3651 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
3652 int RHSC = (int)RHS->getZExtValue();
3653 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
3654 assert(Ptr->getOpcode() == ISD::ADD);
3656 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
3658 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
3659 isInc = Ptr->getOpcode() == ISD::ADD;
3660 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
3668 /// getPreIndexedAddressParts - returns true by value, base pointer and
3669 /// offset pointer and addressing mode by reference if the node's address
3670 /// can be legally represented as pre-indexed load / store address.
3672 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
3674 ISD::MemIndexedMode &AM,
3675 SelectionDAG &DAG) const {
3676 if (Subtarget->isThumb1Only())
3681 bool isSEXTLoad = false;
3682 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3683 Ptr = LD->getBasePtr();
3684 VT = LD->getMemoryVT();
3685 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
3686 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3687 Ptr = ST->getBasePtr();
3688 VT = ST->getMemoryVT();
3693 bool isLegal = false;
3694 if (Subtarget->isThumb2())
3695 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
3696 Offset, isInc, DAG);
3698 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
3699 Offset, isInc, DAG);
3703 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
3707 /// getPostIndexedAddressParts - returns true by value, base pointer and
3708 /// offset pointer and addressing mode by reference if this node can be
3709 /// combined with a load / store to form a post-indexed load / store.
3710 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
3713 ISD::MemIndexedMode &AM,
3714 SelectionDAG &DAG) const {
3715 if (Subtarget->isThumb1Only())
3720 bool isSEXTLoad = false;
3721 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3722 VT = LD->getMemoryVT();
3723 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
3724 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3725 VT = ST->getMemoryVT();
3730 bool isLegal = false;
3731 if (Subtarget->isThumb2())
3732 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
3735 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
3740 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
3744 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
3748 const SelectionDAG &DAG,
3749 unsigned Depth) const {
3750 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
3751 switch (Op.getOpcode()) {
3753 case ARMISD::CMOV: {
3754 // Bits are known zero/one if known on the LHS and RHS.
3755 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
3756 if (KnownZero == 0 && KnownOne == 0) return;
3758 APInt KnownZeroRHS, KnownOneRHS;
3759 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
3760 KnownZeroRHS, KnownOneRHS, Depth+1);
3761 KnownZero &= KnownZeroRHS;
3762 KnownOne &= KnownOneRHS;
3768 //===----------------------------------------------------------------------===//
3769 // ARM Inline Assembly Support
3770 //===----------------------------------------------------------------------===//
3772 /// getConstraintType - Given a constraint letter, return the type of
3773 /// constraint it is for this target.
3774 ARMTargetLowering::ConstraintType
3775 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
3776 if (Constraint.size() == 1) {
3777 switch (Constraint[0]) {
3779 case 'l': return C_RegisterClass;
3780 case 'w': return C_RegisterClass;
3783 return TargetLowering::getConstraintType(Constraint);
3786 std::pair<unsigned, const TargetRegisterClass*>
3787 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
3789 if (Constraint.size() == 1) {
3790 // GCC RS6000 Constraint Letters
3791 switch (Constraint[0]) {
3793 if (Subtarget->isThumb1Only())
3794 return std::make_pair(0U, ARM::tGPRRegisterClass);
3796 return std::make_pair(0U, ARM::GPRRegisterClass);
3798 return std::make_pair(0U, ARM::GPRRegisterClass);
3801 return std::make_pair(0U, ARM::SPRRegisterClass);
3803 return std::make_pair(0U, ARM::DPRRegisterClass);
3807 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3810 std::vector<unsigned> ARMTargetLowering::
3811 getRegClassForInlineAsmConstraint(const std::string &Constraint,
3813 if (Constraint.size() != 1)
3814 return std::vector<unsigned>();
3816 switch (Constraint[0]) { // GCC ARM Constraint Letters
3819 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
3820 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
3823 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
3824 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
3825 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
3826 ARM::R12, ARM::LR, 0);
3829 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
3830 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
3831 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
3832 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
3833 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
3834 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
3835 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
3836 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
3838 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
3839 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
3840 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
3841 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
3845 return std::vector<unsigned>();
3848 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3849 /// vector. If it is invalid, don't add anything to Ops.
3850 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
3853 std::vector<SDValue>&Ops,
3854 SelectionDAG &DAG) const {
3855 SDValue Result(0, 0);
3857 switch (Constraint) {
3859 case 'I': case 'J': case 'K': case 'L':
3860 case 'M': case 'N': case 'O':
3861 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3865 int64_t CVal64 = C->getSExtValue();
3866 int CVal = (int) CVal64;
3867 // None of these constraints allow values larger than 32 bits. Check
3868 // that the value fits in an int.
3872 switch (Constraint) {
3874 if (Subtarget->isThumb1Only()) {
3875 // This must be a constant between 0 and 255, for ADD
3877 if (CVal >= 0 && CVal <= 255)
3879 } else if (Subtarget->isThumb2()) {
3880 // A constant that can be used as an immediate value in a
3881 // data-processing instruction.
3882 if (ARM_AM::getT2SOImmVal(CVal) != -1)
3885 // A constant that can be used as an immediate value in a
3886 // data-processing instruction.
3887 if (ARM_AM::getSOImmVal(CVal) != -1)
3893 if (Subtarget->isThumb()) { // FIXME thumb2
3894 // This must be a constant between -255 and -1, for negated ADD
3895 // immediates. This can be used in GCC with an "n" modifier that
3896 // prints the negated value, for use with SUB instructions. It is
3897 // not useful otherwise but is implemented for compatibility.
3898 if (CVal >= -255 && CVal <= -1)
3901 // This must be a constant between -4095 and 4095. It is not clear
3902 // what this constraint is intended for. Implemented for
3903 // compatibility with GCC.
3904 if (CVal >= -4095 && CVal <= 4095)
3910 if (Subtarget->isThumb1Only()) {
3911 // A 32-bit value where only one byte has a nonzero value. Exclude
3912 // zero to match GCC. This constraint is used by GCC internally for
3913 // constants that can be loaded with a move/shift combination.
3914 // It is not useful otherwise but is implemented for compatibility.
3915 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
3917 } else if (Subtarget->isThumb2()) {
3918 // A constant whose bitwise inverse can be used as an immediate
3919 // value in a data-processing instruction. This can be used in GCC
3920 // with a "B" modifier that prints the inverted value, for use with
3921 // BIC and MVN instructions. It is not useful otherwise but is
3922 // implemented for compatibility.
3923 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
3926 // A constant whose bitwise inverse can be used as an immediate
3927 // value in a data-processing instruction. This can be used in GCC
3928 // with a "B" modifier that prints the inverted value, for use with
3929 // BIC and MVN instructions. It is not useful otherwise but is
3930 // implemented for compatibility.
3931 if (ARM_AM::getSOImmVal(~CVal) != -1)
3937 if (Subtarget->isThumb1Only()) {
3938 // This must be a constant between -7 and 7,
3939 // for 3-operand ADD/SUB immediate instructions.
3940 if (CVal >= -7 && CVal < 7)
3942 } else if (Subtarget->isThumb2()) {
3943 // A constant whose negation can be used as an immediate value in a
3944 // data-processing instruction. This can be used in GCC with an "n"
3945 // modifier that prints the negated value, for use with SUB
3946 // instructions. It is not useful otherwise but is implemented for
3948 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
3951 // A constant whose negation can be used as an immediate value in a
3952 // data-processing instruction. This can be used in GCC with an "n"
3953 // modifier that prints the negated value, for use with SUB
3954 // instructions. It is not useful otherwise but is implemented for
3956 if (ARM_AM::getSOImmVal(-CVal) != -1)
3962 if (Subtarget->isThumb()) { // FIXME thumb2
3963 // This must be a multiple of 4 between 0 and 1020, for
3964 // ADD sp + immediate.
3965 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
3968 // A power of two or a constant between 0 and 32. This is used in
3969 // GCC for the shift amount on shifted register operands, but it is
3970 // useful in general for any shift amounts.
3971 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
3977 if (Subtarget->isThumb()) { // FIXME thumb2
3978 // This must be a constant between 0 and 31, for shift amounts.
3979 if (CVal >= 0 && CVal <= 31)
3985 if (Subtarget->isThumb()) { // FIXME thumb2
3986 // This must be a multiple of 4 between -508 and 508, for
3987 // ADD/SUB sp = sp + immediate.
3988 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
3993 Result = DAG.getTargetConstant(CVal, Op.getValueType());
3997 if (Result.getNode()) {
3998 Ops.push_back(Result);
4001 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,