1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "arm-isel"
17 #include "ARMAddressingModes.h"
18 #include "ARMCallingConv.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMISelLowering.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMPerfectShuffle.h"
23 #include "ARMRegisterInfo.h"
24 #include "ARMSubtarget.h"
25 #include "ARMTargetMachine.h"
26 #include "ARMTargetObjectFile.h"
27 #include "llvm/CallingConv.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Function.h"
30 #include "llvm/GlobalValue.h"
31 #include "llvm/Instruction.h"
32 #include "llvm/Instructions.h"
33 #include "llvm/Intrinsics.h"
34 #include "llvm/Type.h"
35 #include "llvm/CodeGen/CallingConvLower.h"
36 #include "llvm/CodeGen/MachineBasicBlock.h"
37 #include "llvm/CodeGen/MachineFrameInfo.h"
38 #include "llvm/CodeGen/MachineFunction.h"
39 #include "llvm/CodeGen/MachineInstrBuilder.h"
40 #include "llvm/CodeGen/MachineRegisterInfo.h"
41 #include "llvm/CodeGen/PseudoSourceValue.h"
42 #include "llvm/CodeGen/SelectionDAG.h"
43 #include "llvm/MC/MCSectionMachO.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/ADT/VectorExtras.h"
46 #include "llvm/ADT/Statistic.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Support/raw_ostream.h"
54 STATISTIC(NumTailCalls, "Number of tail calls");
56 // This option should go away when tail calls fully work.
58 EnableARMTailCalls("arm-tail-calls", cl::Hidden,
59 cl::desc("Generate tail calls (TEMPORARY OPTION)."),
63 EnableARMLongCalls("arm-long-calls", cl::Hidden,
64 cl::desc("Generate calls via indirect call instructions"),
68 ARMInterworking("arm-interworking", cl::Hidden,
69 cl::desc("Enable / disable ARM interworking (for debugging only)"),
72 void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
73 EVT PromotedBitwiseVT) {
74 if (VT != PromotedLdStVT) {
75 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
76 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
77 PromotedLdStVT.getSimpleVT());
79 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
80 AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
81 PromotedLdStVT.getSimpleVT());
84 EVT ElemTy = VT.getVectorElementType();
85 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
86 setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
87 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
88 if (ElemTy != MVT::i32) {
89 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
90 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand);
91 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand);
92 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand);
94 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
95 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
96 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
97 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Expand);
98 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
99 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
100 if (VT.isInteger()) {
101 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
102 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
103 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
104 setLoadExtAction(ISD::SEXTLOAD, VT.getSimpleVT(), Expand);
105 setLoadExtAction(ISD::ZEXTLOAD, VT.getSimpleVT(), Expand);
106 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
107 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
108 setTruncStoreAction(VT.getSimpleVT(),
109 (MVT::SimpleValueType)InnerVT, Expand);
111 setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand);
113 // Promote all bit-wise operations.
114 if (VT.isInteger() && VT != PromotedBitwiseVT) {
115 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
116 AddPromotedToType (ISD::AND, VT.getSimpleVT(),
117 PromotedBitwiseVT.getSimpleVT());
118 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
119 AddPromotedToType (ISD::OR, VT.getSimpleVT(),
120 PromotedBitwiseVT.getSimpleVT());
121 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
122 AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
123 PromotedBitwiseVT.getSimpleVT());
126 // Neon does not support vector divide/remainder operations.
127 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
128 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
129 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand);
130 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
131 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
132 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
135 void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
136 addRegisterClass(VT, ARM::DPRRegisterClass);
137 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
140 void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
141 addRegisterClass(VT, ARM::QPRRegisterClass);
142 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
145 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
146 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
147 return new TargetLoweringObjectFileMachO();
149 return new ARMElfTargetObjectFile();
152 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
153 : TargetLowering(TM, createTLOF(TM)) {
154 Subtarget = &TM.getSubtarget<ARMSubtarget>();
155 RegInfo = TM.getRegisterInfo();
156 Itins = TM.getInstrItineraryData();
158 if (Subtarget->isTargetDarwin()) {
159 // Uses VFP for Thumb libfuncs if available.
160 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
161 // Single-precision floating-point arithmetic.
162 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
163 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
164 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
165 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
167 // Double-precision floating-point arithmetic.
168 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
169 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
170 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
171 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
173 // Single-precision comparisons.
174 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
175 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
176 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
177 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
178 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
179 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
180 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
181 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
183 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
184 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
185 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
186 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
187 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
188 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
189 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
190 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
192 // Double-precision comparisons.
193 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
194 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
195 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
196 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
197 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
198 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
199 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
200 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
202 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
203 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
204 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
205 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
206 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
207 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
208 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
209 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
211 // Floating-point to integer conversions.
212 // i64 conversions are done via library routines even when generating VFP
213 // instructions, so use the same ones.
214 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
215 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
216 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
217 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
219 // Conversions between floating types.
220 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
221 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
223 // Integer to floating-point conversions.
224 // i64 conversions are done via library routines even when generating VFP
225 // instructions, so use the same ones.
226 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
227 // e.g., __floatunsidf vs. __floatunssidfvfp.
228 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
229 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
230 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
231 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
235 // These libcalls are not available in 32-bit.
236 setLibcallName(RTLIB::SHL_I128, 0);
237 setLibcallName(RTLIB::SRL_I128, 0);
238 setLibcallName(RTLIB::SRA_I128, 0);
240 if (Subtarget->isAAPCS_ABI()) {
241 // Double-precision floating-point arithmetic helper functions
242 // RTABI chapter 4.1.2, Table 2
243 setLibcallName(RTLIB::ADD_F64, "__aeabi_dadd");
244 setLibcallName(RTLIB::DIV_F64, "__aeabi_ddiv");
245 setLibcallName(RTLIB::MUL_F64, "__aeabi_dmul");
246 setLibcallName(RTLIB::SUB_F64, "__aeabi_dsub");
247 setLibcallCallingConv(RTLIB::ADD_F64, CallingConv::ARM_AAPCS);
248 setLibcallCallingConv(RTLIB::DIV_F64, CallingConv::ARM_AAPCS);
249 setLibcallCallingConv(RTLIB::MUL_F64, CallingConv::ARM_AAPCS);
250 setLibcallCallingConv(RTLIB::SUB_F64, CallingConv::ARM_AAPCS);
252 // Double-precision floating-point comparison helper functions
253 // RTABI chapter 4.1.2, Table 3
254 setLibcallName(RTLIB::OEQ_F64, "__aeabi_dcmpeq");
255 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
256 setLibcallName(RTLIB::UNE_F64, "__aeabi_dcmpeq");
257 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETEQ);
258 setLibcallName(RTLIB::OLT_F64, "__aeabi_dcmplt");
259 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
260 setLibcallName(RTLIB::OLE_F64, "__aeabi_dcmple");
261 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
262 setLibcallName(RTLIB::OGE_F64, "__aeabi_dcmpge");
263 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
264 setLibcallName(RTLIB::OGT_F64, "__aeabi_dcmpgt");
265 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
266 setLibcallName(RTLIB::UO_F64, "__aeabi_dcmpun");
267 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
268 setLibcallName(RTLIB::O_F64, "__aeabi_dcmpun");
269 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
270 setLibcallCallingConv(RTLIB::OEQ_F64, CallingConv::ARM_AAPCS);
271 setLibcallCallingConv(RTLIB::UNE_F64, CallingConv::ARM_AAPCS);
272 setLibcallCallingConv(RTLIB::OLT_F64, CallingConv::ARM_AAPCS);
273 setLibcallCallingConv(RTLIB::OLE_F64, CallingConv::ARM_AAPCS);
274 setLibcallCallingConv(RTLIB::OGE_F64, CallingConv::ARM_AAPCS);
275 setLibcallCallingConv(RTLIB::OGT_F64, CallingConv::ARM_AAPCS);
276 setLibcallCallingConv(RTLIB::UO_F64, CallingConv::ARM_AAPCS);
277 setLibcallCallingConv(RTLIB::O_F64, CallingConv::ARM_AAPCS);
279 // Single-precision floating-point arithmetic helper functions
280 // RTABI chapter 4.1.2, Table 4
281 setLibcallName(RTLIB::ADD_F32, "__aeabi_fadd");
282 setLibcallName(RTLIB::DIV_F32, "__aeabi_fdiv");
283 setLibcallName(RTLIB::MUL_F32, "__aeabi_fmul");
284 setLibcallName(RTLIB::SUB_F32, "__aeabi_fsub");
285 setLibcallCallingConv(RTLIB::ADD_F32, CallingConv::ARM_AAPCS);
286 setLibcallCallingConv(RTLIB::DIV_F32, CallingConv::ARM_AAPCS);
287 setLibcallCallingConv(RTLIB::MUL_F32, CallingConv::ARM_AAPCS);
288 setLibcallCallingConv(RTLIB::SUB_F32, CallingConv::ARM_AAPCS);
290 // Single-precision floating-point comparison helper functions
291 // RTABI chapter 4.1.2, Table 5
292 setLibcallName(RTLIB::OEQ_F32, "__aeabi_fcmpeq");
293 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
294 setLibcallName(RTLIB::UNE_F32, "__aeabi_fcmpeq");
295 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETEQ);
296 setLibcallName(RTLIB::OLT_F32, "__aeabi_fcmplt");
297 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
298 setLibcallName(RTLIB::OLE_F32, "__aeabi_fcmple");
299 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
300 setLibcallName(RTLIB::OGE_F32, "__aeabi_fcmpge");
301 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
302 setLibcallName(RTLIB::OGT_F32, "__aeabi_fcmpgt");
303 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
304 setLibcallName(RTLIB::UO_F32, "__aeabi_fcmpun");
305 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
306 setLibcallName(RTLIB::O_F32, "__aeabi_fcmpun");
307 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
308 setLibcallCallingConv(RTLIB::OEQ_F32, CallingConv::ARM_AAPCS);
309 setLibcallCallingConv(RTLIB::UNE_F32, CallingConv::ARM_AAPCS);
310 setLibcallCallingConv(RTLIB::OLT_F32, CallingConv::ARM_AAPCS);
311 setLibcallCallingConv(RTLIB::OLE_F32, CallingConv::ARM_AAPCS);
312 setLibcallCallingConv(RTLIB::OGE_F32, CallingConv::ARM_AAPCS);
313 setLibcallCallingConv(RTLIB::OGT_F32, CallingConv::ARM_AAPCS);
314 setLibcallCallingConv(RTLIB::UO_F32, CallingConv::ARM_AAPCS);
315 setLibcallCallingConv(RTLIB::O_F32, CallingConv::ARM_AAPCS);
317 // Floating-point to integer conversions.
318 // RTABI chapter 4.1.2, Table 6
319 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz");
320 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz");
321 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz");
322 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz");
323 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz");
324 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz");
325 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz");
326 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz");
327 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I32, CallingConv::ARM_AAPCS);
328 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I32, CallingConv::ARM_AAPCS);
329 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I64, CallingConv::ARM_AAPCS);
330 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::ARM_AAPCS);
331 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I32, CallingConv::ARM_AAPCS);
332 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I32, CallingConv::ARM_AAPCS);
333 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I64, CallingConv::ARM_AAPCS);
334 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::ARM_AAPCS);
336 // Conversions between floating types.
337 // RTABI chapter 4.1.2, Table 7
338 setLibcallName(RTLIB::FPROUND_F64_F32, "__aeabi_d2f");
339 setLibcallName(RTLIB::FPEXT_F32_F64, "__aeabi_f2d");
340 setLibcallCallingConv(RTLIB::FPROUND_F64_F32, CallingConv::ARM_AAPCS);
341 setLibcallCallingConv(RTLIB::FPEXT_F32_F64, CallingConv::ARM_AAPCS);
343 // Integer to floating-point conversions.
344 // RTABI chapter 4.1.2, Table 8
345 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d");
346 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d");
347 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d");
348 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d");
349 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f");
350 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f");
351 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f");
352 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f");
353 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
354 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
355 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
356 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
357 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
358 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
359 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
360 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
362 // Long long helper functions
363 // RTABI chapter 4.2, Table 9
364 setLibcallName(RTLIB::MUL_I64, "__aeabi_lmul");
365 setLibcallName(RTLIB::SDIV_I64, "__aeabi_ldivmod");
366 setLibcallName(RTLIB::UDIV_I64, "__aeabi_uldivmod");
367 setLibcallName(RTLIB::SHL_I64, "__aeabi_llsl");
368 setLibcallName(RTLIB::SRL_I64, "__aeabi_llsr");
369 setLibcallName(RTLIB::SRA_I64, "__aeabi_lasr");
370 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::ARM_AAPCS);
371 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::ARM_AAPCS);
372 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::ARM_AAPCS);
373 setLibcallCallingConv(RTLIB::SHL_I64, CallingConv::ARM_AAPCS);
374 setLibcallCallingConv(RTLIB::SRL_I64, CallingConv::ARM_AAPCS);
375 setLibcallCallingConv(RTLIB::SRA_I64, CallingConv::ARM_AAPCS);
377 // Integer division functions
378 // RTABI chapter 4.3.1
379 setLibcallName(RTLIB::SDIV_I8, "__aeabi_idiv");
380 setLibcallName(RTLIB::SDIV_I16, "__aeabi_idiv");
381 setLibcallName(RTLIB::SDIV_I32, "__aeabi_idiv");
382 setLibcallName(RTLIB::UDIV_I8, "__aeabi_uidiv");
383 setLibcallName(RTLIB::UDIV_I16, "__aeabi_uidiv");
384 setLibcallName(RTLIB::UDIV_I32, "__aeabi_uidiv");
385 setLibcallCallingConv(RTLIB::SDIV_I8, CallingConv::ARM_AAPCS);
386 setLibcallCallingConv(RTLIB::SDIV_I16, CallingConv::ARM_AAPCS);
387 setLibcallCallingConv(RTLIB::SDIV_I32, CallingConv::ARM_AAPCS);
388 setLibcallCallingConv(RTLIB::UDIV_I8, CallingConv::ARM_AAPCS);
389 setLibcallCallingConv(RTLIB::UDIV_I16, CallingConv::ARM_AAPCS);
390 setLibcallCallingConv(RTLIB::UDIV_I32, CallingConv::ARM_AAPCS);
393 if (Subtarget->isThumb1Only())
394 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
396 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
397 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
398 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
399 if (!Subtarget->isFPOnlySP())
400 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
402 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
405 if (Subtarget->hasNEON()) {
406 addDRTypeForNEON(MVT::v2f32);
407 addDRTypeForNEON(MVT::v8i8);
408 addDRTypeForNEON(MVT::v4i16);
409 addDRTypeForNEON(MVT::v2i32);
410 addDRTypeForNEON(MVT::v1i64);
412 addQRTypeForNEON(MVT::v4f32);
413 addQRTypeForNEON(MVT::v2f64);
414 addQRTypeForNEON(MVT::v16i8);
415 addQRTypeForNEON(MVT::v8i16);
416 addQRTypeForNEON(MVT::v4i32);
417 addQRTypeForNEON(MVT::v2i64);
419 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
420 // neither Neon nor VFP support any arithmetic operations on it.
421 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
422 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
423 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
424 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
425 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
426 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
427 setOperationAction(ISD::VSETCC, MVT::v2f64, Expand);
428 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
429 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
430 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
431 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
432 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
433 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
434 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
435 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
436 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
437 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
438 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
439 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
440 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
441 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
442 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
443 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
444 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
446 setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand);
448 // Neon does not support some operations on v1i64 and v2i64 types.
449 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
450 // Custom handling for some quad-vector types to detect VMULL.
451 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
452 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
453 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
454 setOperationAction(ISD::VSETCC, MVT::v1i64, Expand);
455 setOperationAction(ISD::VSETCC, MVT::v2i64, Expand);
457 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
458 setTargetDAGCombine(ISD::SHL);
459 setTargetDAGCombine(ISD::SRL);
460 setTargetDAGCombine(ISD::SRA);
461 setTargetDAGCombine(ISD::SIGN_EXTEND);
462 setTargetDAGCombine(ISD::ZERO_EXTEND);
463 setTargetDAGCombine(ISD::ANY_EXTEND);
464 setTargetDAGCombine(ISD::SELECT_CC);
465 setTargetDAGCombine(ISD::BUILD_VECTOR);
466 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
469 computeRegisterProperties();
471 // ARM does not have f32 extending load.
472 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
474 // ARM does not have i1 sign extending load.
475 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
477 // ARM supports all 4 flavors of integer indexed load / store.
478 if (!Subtarget->isThumb1Only()) {
479 for (unsigned im = (unsigned)ISD::PRE_INC;
480 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
481 setIndexedLoadAction(im, MVT::i1, Legal);
482 setIndexedLoadAction(im, MVT::i8, Legal);
483 setIndexedLoadAction(im, MVT::i16, Legal);
484 setIndexedLoadAction(im, MVT::i32, Legal);
485 setIndexedStoreAction(im, MVT::i1, Legal);
486 setIndexedStoreAction(im, MVT::i8, Legal);
487 setIndexedStoreAction(im, MVT::i16, Legal);
488 setIndexedStoreAction(im, MVT::i32, Legal);
492 // i64 operation support.
493 if (Subtarget->isThumb1Only()) {
494 setOperationAction(ISD::MUL, MVT::i64, Expand);
495 setOperationAction(ISD::MULHU, MVT::i32, Expand);
496 setOperationAction(ISD::MULHS, MVT::i32, Expand);
497 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
498 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
500 setOperationAction(ISD::MUL, MVT::i64, Expand);
501 setOperationAction(ISD::MULHU, MVT::i32, Expand);
502 if (!Subtarget->hasV6Ops())
503 setOperationAction(ISD::MULHS, MVT::i32, Expand);
505 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
506 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
507 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
508 setOperationAction(ISD::SRL, MVT::i64, Custom);
509 setOperationAction(ISD::SRA, MVT::i64, Custom);
511 // ARM does not have ROTL.
512 setOperationAction(ISD::ROTL, MVT::i32, Expand);
513 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
514 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
515 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
516 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
518 // Only ARMv6 has BSWAP.
519 if (!Subtarget->hasV6Ops())
520 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
522 // These are expanded into libcalls.
523 if (!Subtarget->hasDivide() || !Subtarget->isThumb2()) {
524 // v7M has a hardware divider
525 setOperationAction(ISD::SDIV, MVT::i32, Expand);
526 setOperationAction(ISD::UDIV, MVT::i32, Expand);
528 setOperationAction(ISD::SREM, MVT::i32, Expand);
529 setOperationAction(ISD::UREM, MVT::i32, Expand);
530 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
531 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
533 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
534 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
535 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
536 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
537 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
539 setOperationAction(ISD::TRAP, MVT::Other, Legal);
541 // Use the default implementation.
542 setOperationAction(ISD::VASTART, MVT::Other, Custom);
543 setOperationAction(ISD::VAARG, MVT::Other, Expand);
544 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
545 setOperationAction(ISD::VAEND, MVT::Other, Expand);
546 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
547 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
548 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
549 // FIXME: Shouldn't need this, since no register is used, but the legalizer
550 // doesn't yet know how to not do that for SjLj.
551 setExceptionSelectorRegister(ARM::R0);
552 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
553 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
554 // the default expansion.
555 if (Subtarget->hasDataBarrier() ||
556 (Subtarget->hasV6Ops() && !Subtarget->isThumb())) {
557 // membarrier needs custom lowering; the rest are legal and handled
559 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
561 // Set them all for expansion, which will force libcalls.
562 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
563 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Expand);
564 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Expand);
565 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
566 setOperationAction(ISD::ATOMIC_SWAP, MVT::i8, Expand);
567 setOperationAction(ISD::ATOMIC_SWAP, MVT::i16, Expand);
568 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
569 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i8, Expand);
570 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i16, Expand);
571 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
572 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Expand);
573 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Expand);
574 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
575 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i8, Expand);
576 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i16, Expand);
577 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
578 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i8, Expand);
579 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i16, Expand);
580 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
581 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i8, Expand);
582 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i16, Expand);
583 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
584 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i8, Expand);
585 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i16, Expand);
586 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
587 // Since the libcalls include locking, fold in the fences
588 setShouldFoldAtomicFences(true);
590 // 64-bit versions are always libcalls (for now)
591 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Expand);
592 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Expand);
593 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Expand);
594 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Expand);
595 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Expand);
596 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Expand);
597 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Expand);
598 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Expand);
600 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
602 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
603 if (!Subtarget->hasV6Ops()) {
604 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
605 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
607 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
609 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
610 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
611 // iff target supports vfp2.
612 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
613 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
616 // We want to custom lower some of our intrinsics.
617 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
618 if (Subtarget->isTargetDarwin()) {
619 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
620 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
621 setOperationAction(ISD::EH_SJLJ_DISPATCHSETUP, MVT::Other, Custom);
624 setOperationAction(ISD::SETCC, MVT::i32, Expand);
625 setOperationAction(ISD::SETCC, MVT::f32, Expand);
626 setOperationAction(ISD::SETCC, MVT::f64, Expand);
627 setOperationAction(ISD::SELECT, MVT::i32, Custom);
628 setOperationAction(ISD::SELECT, MVT::f32, Custom);
629 setOperationAction(ISD::SELECT, MVT::f64, Custom);
630 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
631 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
632 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
634 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
635 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
636 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
637 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
638 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
640 // We don't support sin/cos/fmod/copysign/pow
641 setOperationAction(ISD::FSIN, MVT::f64, Expand);
642 setOperationAction(ISD::FSIN, MVT::f32, Expand);
643 setOperationAction(ISD::FCOS, MVT::f32, Expand);
644 setOperationAction(ISD::FCOS, MVT::f64, Expand);
645 setOperationAction(ISD::FREM, MVT::f64, Expand);
646 setOperationAction(ISD::FREM, MVT::f32, Expand);
647 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
648 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
649 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
651 setOperationAction(ISD::FPOW, MVT::f64, Expand);
652 setOperationAction(ISD::FPOW, MVT::f32, Expand);
654 // Various VFP goodness
655 if (!UseSoftFloat && !Subtarget->isThumb1Only()) {
656 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
657 if (Subtarget->hasVFP2()) {
658 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
659 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
660 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
661 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
663 // Special handling for half-precision FP.
664 if (!Subtarget->hasFP16()) {
665 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
666 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand);
670 // We have target-specific dag combine patterns for the following nodes:
671 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
672 setTargetDAGCombine(ISD::ADD);
673 setTargetDAGCombine(ISD::SUB);
674 setTargetDAGCombine(ISD::MUL);
676 if (Subtarget->hasV6T2Ops() || Subtarget->hasNEON())
677 setTargetDAGCombine(ISD::OR);
678 if (Subtarget->hasNEON())
679 setTargetDAGCombine(ISD::AND);
681 setStackPointerRegisterToSaveRestore(ARM::SP);
683 if (UseSoftFloat || Subtarget->isThumb1Only() || !Subtarget->hasVFP2())
684 setSchedulingPreference(Sched::RegPressure);
686 setSchedulingPreference(Sched::Hybrid);
688 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
690 // On ARM arguments smaller than 4 bytes are extended, so all arguments
691 // are at least 4 bytes aligned.
692 setMinStackArgumentAlignment(4);
694 benefitFromCodePlacementOpt = true;
697 std::pair<const TargetRegisterClass*, uint8_t>
698 ARMTargetLowering::findRepresentativeClass(EVT VT) const{
699 const TargetRegisterClass *RRC = 0;
701 switch (VT.getSimpleVT().SimpleTy) {
703 return TargetLowering::findRepresentativeClass(VT);
704 // Use DPR as representative register class for all floating point
705 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
706 // the cost is 1 for both f32 and f64.
707 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
708 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
709 RRC = ARM::DPRRegisterClass;
711 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
712 case MVT::v4f32: case MVT::v2f64:
713 RRC = ARM::DPRRegisterClass;
717 RRC = ARM::DPRRegisterClass;
721 RRC = ARM::DPRRegisterClass;
725 return std::make_pair(RRC, Cost);
728 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
731 case ARMISD::Wrapper: return "ARMISD::Wrapper";
732 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
733 case ARMISD::CALL: return "ARMISD::CALL";
734 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
735 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
736 case ARMISD::tCALL: return "ARMISD::tCALL";
737 case ARMISD::BRCOND: return "ARMISD::BRCOND";
738 case ARMISD::BR_JT: return "ARMISD::BR_JT";
739 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
740 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
741 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
742 case ARMISD::CMP: return "ARMISD::CMP";
743 case ARMISD::CMPZ: return "ARMISD::CMPZ";
744 case ARMISD::CMPFP: return "ARMISD::CMPFP";
745 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
746 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
747 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
748 case ARMISD::CMOV: return "ARMISD::CMOV";
749 case ARMISD::CNEG: return "ARMISD::CNEG";
751 case ARMISD::RBIT: return "ARMISD::RBIT";
753 case ARMISD::FTOSI: return "ARMISD::FTOSI";
754 case ARMISD::FTOUI: return "ARMISD::FTOUI";
755 case ARMISD::SITOF: return "ARMISD::SITOF";
756 case ARMISD::UITOF: return "ARMISD::UITOF";
758 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
759 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
760 case ARMISD::RRX: return "ARMISD::RRX";
762 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
763 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
765 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
766 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
767 case ARMISD::EH_SJLJ_DISPATCHSETUP:return "ARMISD::EH_SJLJ_DISPATCHSETUP";
769 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
771 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
773 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
775 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER";
776 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
778 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
780 case ARMISD::VCEQ: return "ARMISD::VCEQ";
781 case ARMISD::VCGE: return "ARMISD::VCGE";
782 case ARMISD::VCGEU: return "ARMISD::VCGEU";
783 case ARMISD::VCGT: return "ARMISD::VCGT";
784 case ARMISD::VCGTU: return "ARMISD::VCGTU";
785 case ARMISD::VTST: return "ARMISD::VTST";
787 case ARMISD::VSHL: return "ARMISD::VSHL";
788 case ARMISD::VSHRs: return "ARMISD::VSHRs";
789 case ARMISD::VSHRu: return "ARMISD::VSHRu";
790 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
791 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
792 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
793 case ARMISD::VSHRN: return "ARMISD::VSHRN";
794 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
795 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
796 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
797 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
798 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
799 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
800 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
801 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
802 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
803 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
804 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
805 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
806 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
807 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
808 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
809 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
810 case ARMISD::VDUP: return "ARMISD::VDUP";
811 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
812 case ARMISD::VEXT: return "ARMISD::VEXT";
813 case ARMISD::VREV64: return "ARMISD::VREV64";
814 case ARMISD::VREV32: return "ARMISD::VREV32";
815 case ARMISD::VREV16: return "ARMISD::VREV16";
816 case ARMISD::VZIP: return "ARMISD::VZIP";
817 case ARMISD::VUZP: return "ARMISD::VUZP";
818 case ARMISD::VTRN: return "ARMISD::VTRN";
819 case ARMISD::VMULLs: return "ARMISD::VMULLs";
820 case ARMISD::VMULLu: return "ARMISD::VMULLu";
821 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
822 case ARMISD::FMAX: return "ARMISD::FMAX";
823 case ARMISD::FMIN: return "ARMISD::FMIN";
824 case ARMISD::BFI: return "ARMISD::BFI";
825 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
829 /// getRegClassFor - Return the register class that should be used for the
830 /// specified value type.
831 TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const {
832 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
833 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
834 // load / store 4 to 8 consecutive D registers.
835 if (Subtarget->hasNEON()) {
836 if (VT == MVT::v4i64)
837 return ARM::QQPRRegisterClass;
838 else if (VT == MVT::v8i64)
839 return ARM::QQQQPRRegisterClass;
841 return TargetLowering::getRegClassFor(VT);
844 // Create a fast isel object.
846 ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
847 return ARM::createFastISel(funcInfo);
850 /// getFunctionAlignment - Return the Log2 alignment of this function.
851 unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
852 return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 1 : 2;
855 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
856 /// be used for loads / stores from the global.
857 unsigned ARMTargetLowering::getMaximalGlobalOffset() const {
858 return (Subtarget->isThumb1Only() ? 127 : 4095);
861 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
862 unsigned NumVals = N->getNumValues();
864 return Sched::RegPressure;
866 for (unsigned i = 0; i != NumVals; ++i) {
867 EVT VT = N->getValueType(i);
868 if (VT == MVT::Flag || VT == MVT::Other)
870 if (VT.isFloatingPoint() || VT.isVector())
871 return Sched::Latency;
874 if (!N->isMachineOpcode())
875 return Sched::RegPressure;
877 // Load are scheduled for latency even if there instruction itinerary
879 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
880 const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
882 if (TID.getNumDefs() == 0)
883 return Sched::RegPressure;
884 if (!Itins->isEmpty() &&
885 Itins->getOperandCycle(TID.getSchedClass(), 0) > 2)
886 return Sched::Latency;
888 return Sched::RegPressure;
892 ARMTargetLowering::getRegPressureLimit(const TargetRegisterClass *RC,
893 MachineFunction &MF) const {
894 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
896 switch (RC->getID()) {
899 case ARM::tGPRRegClassID:
900 return TFI->hasFP(MF) ? 4 : 5;
901 case ARM::GPRRegClassID: {
902 unsigned FP = TFI->hasFP(MF) ? 1 : 0;
903 return 10 - FP - (Subtarget->isR9Reserved() ? 1 : 0);
905 case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
906 case ARM::DPRRegClassID:
911 //===----------------------------------------------------------------------===//
913 //===----------------------------------------------------------------------===//
915 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
916 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
918 default: llvm_unreachable("Unknown condition code!");
919 case ISD::SETNE: return ARMCC::NE;
920 case ISD::SETEQ: return ARMCC::EQ;
921 case ISD::SETGT: return ARMCC::GT;
922 case ISD::SETGE: return ARMCC::GE;
923 case ISD::SETLT: return ARMCC::LT;
924 case ISD::SETLE: return ARMCC::LE;
925 case ISD::SETUGT: return ARMCC::HI;
926 case ISD::SETUGE: return ARMCC::HS;
927 case ISD::SETULT: return ARMCC::LO;
928 case ISD::SETULE: return ARMCC::LS;
932 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
933 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
934 ARMCC::CondCodes &CondCode2) {
935 CondCode2 = ARMCC::AL;
937 default: llvm_unreachable("Unknown FP condition!");
939 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
941 case ISD::SETOGT: CondCode = ARMCC::GT; break;
943 case ISD::SETOGE: CondCode = ARMCC::GE; break;
944 case ISD::SETOLT: CondCode = ARMCC::MI; break;
945 case ISD::SETOLE: CondCode = ARMCC::LS; break;
946 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
947 case ISD::SETO: CondCode = ARMCC::VC; break;
948 case ISD::SETUO: CondCode = ARMCC::VS; break;
949 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
950 case ISD::SETUGT: CondCode = ARMCC::HI; break;
951 case ISD::SETUGE: CondCode = ARMCC::PL; break;
953 case ISD::SETULT: CondCode = ARMCC::LT; break;
955 case ISD::SETULE: CondCode = ARMCC::LE; break;
957 case ISD::SETUNE: CondCode = ARMCC::NE; break;
961 //===----------------------------------------------------------------------===//
962 // Calling Convention Implementation
963 //===----------------------------------------------------------------------===//
965 #include "ARMGenCallingConv.inc"
967 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
968 /// given CallingConvention value.
969 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
971 bool isVarArg) const {
974 llvm_unreachable("Unsupported calling convention");
975 case CallingConv::Fast:
976 if (Subtarget->hasVFP2() && !isVarArg) {
977 if (!Subtarget->isAAPCS_ABI())
978 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
979 // For AAPCS ABI targets, just use VFP variant of the calling convention.
980 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
983 case CallingConv::C: {
984 // Use target triple & subtarget features to do actual dispatch.
985 if (!Subtarget->isAAPCS_ABI())
986 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
987 else if (Subtarget->hasVFP2() &&
988 FloatABIType == FloatABI::Hard && !isVarArg)
989 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
990 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
992 case CallingConv::ARM_AAPCS_VFP:
993 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
994 case CallingConv::ARM_AAPCS:
995 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
996 case CallingConv::ARM_APCS:
997 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1001 /// LowerCallResult - Lower the result values of a call into the
1002 /// appropriate copies out of appropriate physical registers.
1004 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1005 CallingConv::ID CallConv, bool isVarArg,
1006 const SmallVectorImpl<ISD::InputArg> &Ins,
1007 DebugLoc dl, SelectionDAG &DAG,
1008 SmallVectorImpl<SDValue> &InVals) const {
1010 // Assign locations to each value returned by this call.
1011 SmallVector<CCValAssign, 16> RVLocs;
1012 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1013 RVLocs, *DAG.getContext());
1014 CCInfo.AnalyzeCallResult(Ins,
1015 CCAssignFnForNode(CallConv, /* Return*/ true,
1018 // Copy all of the result registers out of their specified physreg.
1019 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1020 CCValAssign VA = RVLocs[i];
1023 if (VA.needsCustom()) {
1024 // Handle f64 or half of a v2f64.
1025 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1027 Chain = Lo.getValue(1);
1028 InFlag = Lo.getValue(2);
1029 VA = RVLocs[++i]; // skip ahead to next loc
1030 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1032 Chain = Hi.getValue(1);
1033 InFlag = Hi.getValue(2);
1034 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1036 if (VA.getLocVT() == MVT::v2f64) {
1037 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1038 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1039 DAG.getConstant(0, MVT::i32));
1041 VA = RVLocs[++i]; // skip ahead to next loc
1042 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1043 Chain = Lo.getValue(1);
1044 InFlag = Lo.getValue(2);
1045 VA = RVLocs[++i]; // skip ahead to next loc
1046 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1047 Chain = Hi.getValue(1);
1048 InFlag = Hi.getValue(2);
1049 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1050 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1051 DAG.getConstant(1, MVT::i32));
1054 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1056 Chain = Val.getValue(1);
1057 InFlag = Val.getValue(2);
1060 switch (VA.getLocInfo()) {
1061 default: llvm_unreachable("Unknown loc info!");
1062 case CCValAssign::Full: break;
1063 case CCValAssign::BCvt:
1064 Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val);
1068 InVals.push_back(Val);
1074 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1075 /// by "Src" to address "Dst" of size "Size". Alignment information is
1076 /// specified by the specific parameter attribute. The copy will be passed as
1077 /// a byval function parameter.
1078 /// Sometimes what we are copying is the end of a larger object, the part that
1079 /// does not fit in registers.
1081 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1082 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1084 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1085 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1086 /*isVolatile=*/false, /*AlwaysInline=*/false,
1087 MachinePointerInfo(0), MachinePointerInfo(0));
1090 /// LowerMemOpCallTo - Store the argument to the stack.
1092 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
1093 SDValue StackPtr, SDValue Arg,
1094 DebugLoc dl, SelectionDAG &DAG,
1095 const CCValAssign &VA,
1096 ISD::ArgFlagsTy Flags) const {
1097 unsigned LocMemOffset = VA.getLocMemOffset();
1098 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1099 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1100 if (Flags.isByVal())
1101 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1103 return DAG.getStore(Chain, dl, Arg, PtrOff,
1104 MachinePointerInfo::getStack(LocMemOffset),
1108 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
1109 SDValue Chain, SDValue &Arg,
1110 RegsToPassVector &RegsToPass,
1111 CCValAssign &VA, CCValAssign &NextVA,
1113 SmallVector<SDValue, 8> &MemOpChains,
1114 ISD::ArgFlagsTy Flags) const {
1116 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1117 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1118 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
1120 if (NextVA.isRegLoc())
1121 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
1123 assert(NextVA.isMemLoc());
1124 if (StackPtr.getNode() == 0)
1125 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1127 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
1133 /// LowerCall - Lowering a call into a callseq_start <-
1134 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1137 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1138 CallingConv::ID CallConv, bool isVarArg,
1140 const SmallVectorImpl<ISD::OutputArg> &Outs,
1141 const SmallVectorImpl<SDValue> &OutVals,
1142 const SmallVectorImpl<ISD::InputArg> &Ins,
1143 DebugLoc dl, SelectionDAG &DAG,
1144 SmallVectorImpl<SDValue> &InVals) const {
1145 MachineFunction &MF = DAG.getMachineFunction();
1146 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1147 bool IsSibCall = false;
1148 // Temporarily disable tail calls so things don't break.
1149 if (!EnableARMTailCalls)
1152 // Check if it's really possible to do a tail call.
1153 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1154 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1155 Outs, OutVals, Ins, DAG);
1156 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1157 // detected sibcalls.
1164 // Analyze operands of the call, assigning locations to each operand.
1165 SmallVector<CCValAssign, 16> ArgLocs;
1166 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1168 CCInfo.AnalyzeCallOperands(Outs,
1169 CCAssignFnForNode(CallConv, /* Return*/ false,
1172 // Get a count of how many bytes are to be pushed on the stack.
1173 unsigned NumBytes = CCInfo.getNextStackOffset();
1175 // For tail calls, memory operands are available in our caller's stack.
1179 // Adjust the stack pointer for the new arguments...
1180 // These operations are automatically eliminated by the prolog/epilog pass
1182 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1184 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1186 RegsToPassVector RegsToPass;
1187 SmallVector<SDValue, 8> MemOpChains;
1189 // Walk the register/memloc assignments, inserting copies/loads. In the case
1190 // of tail call optimization, arguments are handled later.
1191 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1193 ++i, ++realArgIdx) {
1194 CCValAssign &VA = ArgLocs[i];
1195 SDValue Arg = OutVals[realArgIdx];
1196 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1198 // Promote the value if needed.
1199 switch (VA.getLocInfo()) {
1200 default: llvm_unreachable("Unknown loc info!");
1201 case CCValAssign::Full: break;
1202 case CCValAssign::SExt:
1203 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1205 case CCValAssign::ZExt:
1206 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1208 case CCValAssign::AExt:
1209 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1211 case CCValAssign::BCvt:
1212 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1216 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1217 if (VA.needsCustom()) {
1218 if (VA.getLocVT() == MVT::v2f64) {
1219 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1220 DAG.getConstant(0, MVT::i32));
1221 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1222 DAG.getConstant(1, MVT::i32));
1224 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1225 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1227 VA = ArgLocs[++i]; // skip ahead to next loc
1228 if (VA.isRegLoc()) {
1229 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1230 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1232 assert(VA.isMemLoc());
1234 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1235 dl, DAG, VA, Flags));
1238 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1239 StackPtr, MemOpChains, Flags);
1241 } else if (VA.isRegLoc()) {
1242 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1243 } else if (!IsSibCall) {
1244 assert(VA.isMemLoc());
1246 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1247 dl, DAG, VA, Flags));
1251 if (!MemOpChains.empty())
1252 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1253 &MemOpChains[0], MemOpChains.size());
1255 // Build a sequence of copy-to-reg nodes chained together with token chain
1256 // and flag operands which copy the outgoing args into the appropriate regs.
1258 // Tail call byval lowering might overwrite argument registers so in case of
1259 // tail call optimization the copies to registers are lowered later.
1261 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1262 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1263 RegsToPass[i].second, InFlag);
1264 InFlag = Chain.getValue(1);
1267 // For tail calls lower the arguments to the 'real' stack slot.
1269 // Force all the incoming stack arguments to be loaded from the stack
1270 // before any new outgoing arguments are stored to the stack, because the
1271 // outgoing stack slots may alias the incoming argument stack slots, and
1272 // the alias isn't otherwise explicit. This is slightly more conservative
1273 // than necessary, because it means that each store effectively depends
1274 // on every argument instead of just those arguments it would clobber.
1276 // Do not flag preceeding copytoreg stuff together with the following stuff.
1278 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1279 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1280 RegsToPass[i].second, InFlag);
1281 InFlag = Chain.getValue(1);
1286 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1287 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1288 // node so that legalize doesn't hack it.
1289 bool isDirect = false;
1290 bool isARMFunc = false;
1291 bool isLocalARMFunc = false;
1292 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1294 if (EnableARMLongCalls) {
1295 assert (getTargetMachine().getRelocationModel() == Reloc::Static
1296 && "long-calls with non-static relocation model!");
1297 // Handle a global address or an external symbol. If it's not one of
1298 // those, the target's already in a register, so we don't need to do
1300 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1301 const GlobalValue *GV = G->getGlobal();
1302 // Create a constant pool entry for the callee address
1303 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1304 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1307 // Get the address of the callee into a register
1308 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1309 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1310 Callee = DAG.getLoad(getPointerTy(), dl,
1311 DAG.getEntryNode(), CPAddr,
1312 MachinePointerInfo::getConstantPool(),
1314 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1315 const char *Sym = S->getSymbol();
1317 // Create a constant pool entry for the callee address
1318 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1319 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1320 Sym, ARMPCLabelIndex, 0);
1321 // Get the address of the callee into a register
1322 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1323 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1324 Callee = DAG.getLoad(getPointerTy(), dl,
1325 DAG.getEntryNode(), CPAddr,
1326 MachinePointerInfo::getConstantPool(),
1329 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1330 const GlobalValue *GV = G->getGlobal();
1332 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1333 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
1334 getTargetMachine().getRelocationModel() != Reloc::Static;
1335 isARMFunc = !Subtarget->isThumb() || isStub;
1336 // ARM call to a local ARM function is predicable.
1337 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
1338 // tBX takes a register source operand.
1339 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1340 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1341 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1344 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1345 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1346 Callee = DAG.getLoad(getPointerTy(), dl,
1347 DAG.getEntryNode(), CPAddr,
1348 MachinePointerInfo::getConstantPool(),
1350 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1351 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1352 getPointerTy(), Callee, PICLabel);
1354 // On ELF targets for PIC code, direct calls should go through the PLT
1355 unsigned OpFlags = 0;
1356 if (Subtarget->isTargetELF() &&
1357 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1358 OpFlags = ARMII::MO_PLT;
1359 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
1361 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1363 bool isStub = Subtarget->isTargetDarwin() &&
1364 getTargetMachine().getRelocationModel() != Reloc::Static;
1365 isARMFunc = !Subtarget->isThumb() || isStub;
1366 // tBX takes a register source operand.
1367 const char *Sym = S->getSymbol();
1368 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1369 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1370 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1371 Sym, ARMPCLabelIndex, 4);
1372 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1373 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1374 Callee = DAG.getLoad(getPointerTy(), dl,
1375 DAG.getEntryNode(), CPAddr,
1376 MachinePointerInfo::getConstantPool(),
1378 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1379 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1380 getPointerTy(), Callee, PICLabel);
1382 unsigned OpFlags = 0;
1383 // On ELF targets for PIC code, direct calls should go through the PLT
1384 if (Subtarget->isTargetELF() &&
1385 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1386 OpFlags = ARMII::MO_PLT;
1387 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags);
1391 // FIXME: handle tail calls differently.
1393 if (Subtarget->isThumb()) {
1394 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1395 CallOpc = ARMISD::CALL_NOLINK;
1397 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1399 CallOpc = (isDirect || Subtarget->hasV5TOps())
1400 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
1401 : ARMISD::CALL_NOLINK;
1404 std::vector<SDValue> Ops;
1405 Ops.push_back(Chain);
1406 Ops.push_back(Callee);
1408 // Add argument registers to the end of the list so that they are known live
1410 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1411 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1412 RegsToPass[i].second.getValueType()));
1414 if (InFlag.getNode())
1415 Ops.push_back(InFlag);
1417 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
1419 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
1421 // Returns a chain and a flag for retval copy to use.
1422 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
1423 InFlag = Chain.getValue(1);
1425 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1426 DAG.getIntPtrConstant(0, true), InFlag);
1428 InFlag = Chain.getValue(1);
1430 // Handle result values, copying them out of physregs into vregs that we
1432 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1436 /// MatchingStackOffset - Return true if the given stack call argument is
1437 /// already available in the same position (relatively) of the caller's
1438 /// incoming argument stack.
1440 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1441 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1442 const ARMInstrInfo *TII) {
1443 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
1445 if (Arg.getOpcode() == ISD::CopyFromReg) {
1446 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
1447 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR))
1449 MachineInstr *Def = MRI->getVRegDef(VR);
1452 if (!Flags.isByVal()) {
1453 if (!TII->isLoadFromStackSlot(Def, FI))
1458 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
1459 if (Flags.isByVal())
1460 // ByVal argument is passed in as a pointer but it's now being
1461 // dereferenced. e.g.
1462 // define @foo(%struct.X* %A) {
1463 // tail call @bar(%struct.X* byval %A)
1466 SDValue Ptr = Ld->getBasePtr();
1467 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
1470 FI = FINode->getIndex();
1474 assert(FI != INT_MAX);
1475 if (!MFI->isFixedObjectIndex(FI))
1477 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
1480 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1481 /// for tail call optimization. Targets which want to do tail call
1482 /// optimization should implement this function.
1484 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1485 CallingConv::ID CalleeCC,
1487 bool isCalleeStructRet,
1488 bool isCallerStructRet,
1489 const SmallVectorImpl<ISD::OutputArg> &Outs,
1490 const SmallVectorImpl<SDValue> &OutVals,
1491 const SmallVectorImpl<ISD::InputArg> &Ins,
1492 SelectionDAG& DAG) const {
1493 const Function *CallerF = DAG.getMachineFunction().getFunction();
1494 CallingConv::ID CallerCC = CallerF->getCallingConv();
1495 bool CCMatch = CallerCC == CalleeCC;
1497 // Look for obvious safe cases to perform tail call optimization that do not
1498 // require ABI changes. This is what gcc calls sibcall.
1500 // Do not sibcall optimize vararg calls unless the call site is not passing
1502 if (isVarArg && !Outs.empty())
1505 // Also avoid sibcall optimization if either caller or callee uses struct
1506 // return semantics.
1507 if (isCalleeStructRet || isCallerStructRet)
1510 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
1511 // emitEpilogue is not ready for them.
1512 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
1513 // LR. This means if we need to reload LR, it takes an extra instructions,
1514 // which outweighs the value of the tail call; but here we don't know yet
1515 // whether LR is going to be used. Probably the right approach is to
1516 // generate the tail call here and turn it back into CALL/RET in
1517 // emitEpilogue if LR is used.
1518 if (Subtarget->isThumb1Only())
1521 // For the moment, we can only do this to functions defined in this
1522 // compilation, or to indirect calls. A Thumb B to an ARM function,
1523 // or vice versa, is not easily fixed up in the linker unlike BL.
1524 // (We could do this by loading the address of the callee into a register;
1525 // that is an extra instruction over the direct call and burns a register
1526 // as well, so is not likely to be a win.)
1528 // It might be safe to remove this restriction on non-Darwin.
1530 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
1531 // but we need to make sure there are enough registers; the only valid
1532 // registers are the 4 used for parameters. We don't currently do this
1534 if (isa<ExternalSymbolSDNode>(Callee))
1537 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1538 const GlobalValue *GV = G->getGlobal();
1539 if (GV->isDeclaration() || GV->isWeakForLinker())
1543 // If the calling conventions do not match, then we'd better make sure the
1544 // results are returned in the same way as what the caller expects.
1546 SmallVector<CCValAssign, 16> RVLocs1;
1547 CCState CCInfo1(CalleeCC, false, getTargetMachine(),
1548 RVLocs1, *DAG.getContext());
1549 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
1551 SmallVector<CCValAssign, 16> RVLocs2;
1552 CCState CCInfo2(CallerCC, false, getTargetMachine(),
1553 RVLocs2, *DAG.getContext());
1554 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
1556 if (RVLocs1.size() != RVLocs2.size())
1558 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
1559 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
1561 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
1563 if (RVLocs1[i].isRegLoc()) {
1564 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
1567 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
1573 // If the callee takes no arguments then go on to check the results of the
1575 if (!Outs.empty()) {
1576 // Check if stack adjustment is needed. For now, do not do this if any
1577 // argument is passed on the stack.
1578 SmallVector<CCValAssign, 16> ArgLocs;
1579 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
1580 ArgLocs, *DAG.getContext());
1581 CCInfo.AnalyzeCallOperands(Outs,
1582 CCAssignFnForNode(CalleeCC, false, isVarArg));
1583 if (CCInfo.getNextStackOffset()) {
1584 MachineFunction &MF = DAG.getMachineFunction();
1586 // Check if the arguments are already laid out in the right way as
1587 // the caller's fixed stack objects.
1588 MachineFrameInfo *MFI = MF.getFrameInfo();
1589 const MachineRegisterInfo *MRI = &MF.getRegInfo();
1590 const ARMInstrInfo *TII =
1591 ((ARMTargetMachine&)getTargetMachine()).getInstrInfo();
1592 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1594 ++i, ++realArgIdx) {
1595 CCValAssign &VA = ArgLocs[i];
1596 EVT RegVT = VA.getLocVT();
1597 SDValue Arg = OutVals[realArgIdx];
1598 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1599 if (VA.getLocInfo() == CCValAssign::Indirect)
1601 if (VA.needsCustom()) {
1602 // f64 and vector types are split into multiple registers or
1603 // register/stack-slot combinations. The types will not match
1604 // the registers; give up on memory f64 refs until we figure
1605 // out what to do about this.
1608 if (!ArgLocs[++i].isRegLoc())
1610 if (RegVT == MVT::v2f64) {
1611 if (!ArgLocs[++i].isRegLoc())
1613 if (!ArgLocs[++i].isRegLoc())
1616 } else if (!VA.isRegLoc()) {
1617 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
1629 ARMTargetLowering::LowerReturn(SDValue Chain,
1630 CallingConv::ID CallConv, bool isVarArg,
1631 const SmallVectorImpl<ISD::OutputArg> &Outs,
1632 const SmallVectorImpl<SDValue> &OutVals,
1633 DebugLoc dl, SelectionDAG &DAG) const {
1635 // CCValAssign - represent the assignment of the return value to a location.
1636 SmallVector<CCValAssign, 16> RVLocs;
1638 // CCState - Info about the registers and stack slots.
1639 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
1642 // Analyze outgoing return values.
1643 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1646 // If this is the first return lowered for this function, add
1647 // the regs to the liveout set for the function.
1648 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1649 for (unsigned i = 0; i != RVLocs.size(); ++i)
1650 if (RVLocs[i].isRegLoc())
1651 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1656 // Copy the result values into the output registers.
1657 for (unsigned i = 0, realRVLocIdx = 0;
1659 ++i, ++realRVLocIdx) {
1660 CCValAssign &VA = RVLocs[i];
1661 assert(VA.isRegLoc() && "Can only return in registers!");
1663 SDValue Arg = OutVals[realRVLocIdx];
1665 switch (VA.getLocInfo()) {
1666 default: llvm_unreachable("Unknown loc info!");
1667 case CCValAssign::Full: break;
1668 case CCValAssign::BCvt:
1669 Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1673 if (VA.needsCustom()) {
1674 if (VA.getLocVT() == MVT::v2f64) {
1675 // Extract the first half and return it in two registers.
1676 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1677 DAG.getConstant(0, MVT::i32));
1678 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
1679 DAG.getVTList(MVT::i32, MVT::i32), Half);
1681 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1682 Flag = Chain.getValue(1);
1683 VA = RVLocs[++i]; // skip ahead to next loc
1684 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1685 HalfGPRs.getValue(1), Flag);
1686 Flag = Chain.getValue(1);
1687 VA = RVLocs[++i]; // skip ahead to next loc
1689 // Extract the 2nd half and fall through to handle it as an f64 value.
1690 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1691 DAG.getConstant(1, MVT::i32));
1693 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1695 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1696 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1697 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1698 Flag = Chain.getValue(1);
1699 VA = RVLocs[++i]; // skip ahead to next loc
1700 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1703 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1705 // Guarantee that all emitted copies are
1706 // stuck together, avoiding something bad.
1707 Flag = Chain.getValue(1);
1712 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1714 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1719 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1720 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1721 // one of the above mentioned nodes. It has to be wrapped because otherwise
1722 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1723 // be used to form addressing mode. These wrapped nodes will be selected
1725 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1726 EVT PtrVT = Op.getValueType();
1727 // FIXME there is no actual debug info here
1728 DebugLoc dl = Op.getDebugLoc();
1729 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1731 if (CP->isMachineConstantPoolEntry())
1732 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1733 CP->getAlignment());
1735 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1736 CP->getAlignment());
1737 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1740 unsigned ARMTargetLowering::getJumpTableEncoding() const {
1741 return MachineJumpTableInfo::EK_Inline;
1744 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
1745 SelectionDAG &DAG) const {
1746 MachineFunction &MF = DAG.getMachineFunction();
1747 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1748 unsigned ARMPCLabelIndex = 0;
1749 DebugLoc DL = Op.getDebugLoc();
1750 EVT PtrVT = getPointerTy();
1751 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1752 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1754 if (RelocM == Reloc::Static) {
1755 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
1757 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1758 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1759 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(BA, ARMPCLabelIndex,
1760 ARMCP::CPBlockAddress,
1762 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1764 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
1765 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
1766 MachinePointerInfo::getConstantPool(),
1768 if (RelocM == Reloc::Static)
1770 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1771 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
1774 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
1776 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1777 SelectionDAG &DAG) const {
1778 DebugLoc dl = GA->getDebugLoc();
1779 EVT PtrVT = getPointerTy();
1780 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1781 MachineFunction &MF = DAG.getMachineFunction();
1782 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1783 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1784 ARMConstantPoolValue *CPV =
1785 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1786 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
1787 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1788 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
1789 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
1790 MachinePointerInfo::getConstantPool(),
1792 SDValue Chain = Argument.getValue(1);
1794 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1795 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
1797 // call __tls_get_addr.
1800 Entry.Node = Argument;
1801 Entry.Ty = (const Type *) Type::getInt32Ty(*DAG.getContext());
1802 Args.push_back(Entry);
1803 // FIXME: is there useful debug info available here?
1804 std::pair<SDValue, SDValue> CallResult =
1805 LowerCallTo(Chain, (const Type *) Type::getInt32Ty(*DAG.getContext()),
1806 false, false, false, false,
1807 0, CallingConv::C, false, /*isReturnValueUsed=*/true,
1808 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
1809 return CallResult.first;
1812 // Lower ISD::GlobalTLSAddress using the "initial exec" or
1813 // "local exec" model.
1815 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
1816 SelectionDAG &DAG) const {
1817 const GlobalValue *GV = GA->getGlobal();
1818 DebugLoc dl = GA->getDebugLoc();
1820 SDValue Chain = DAG.getEntryNode();
1821 EVT PtrVT = getPointerTy();
1822 // Get the Thread Pointer
1823 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1825 if (GV->isDeclaration()) {
1826 MachineFunction &MF = DAG.getMachineFunction();
1827 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1828 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1829 // Initial exec model.
1830 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1831 ARMConstantPoolValue *CPV =
1832 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1833 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF, true);
1834 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1835 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1836 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1837 MachinePointerInfo::getConstantPool(),
1839 Chain = Offset.getValue(1);
1841 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1842 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
1844 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1845 MachinePointerInfo::getConstantPool(),
1849 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMCP::TPOFF);
1850 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1851 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1852 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1853 MachinePointerInfo::getConstantPool(),
1857 // The address of the thread local variable is the add of the thread
1858 // pointer with the offset of the variable.
1859 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
1863 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
1864 // TODO: implement the "local dynamic" model
1865 assert(Subtarget->isTargetELF() &&
1866 "TLS not implemented for non-ELF targets");
1867 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1868 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
1869 // otherwise use the "Local Exec" TLS Model
1870 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
1871 return LowerToTLSGeneralDynamicModel(GA, DAG);
1873 return LowerToTLSExecModels(GA, DAG);
1876 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
1877 SelectionDAG &DAG) const {
1878 EVT PtrVT = getPointerTy();
1879 DebugLoc dl = Op.getDebugLoc();
1880 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1881 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1882 if (RelocM == Reloc::PIC_) {
1883 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
1884 ARMConstantPoolValue *CPV =
1885 new ARMConstantPoolValue(GV, UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
1886 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1887 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1888 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1890 MachinePointerInfo::getConstantPool(),
1892 SDValue Chain = Result.getValue(1);
1893 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1894 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
1896 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
1897 MachinePointerInfo::getGOT(), false, false, 0);
1900 // If we have T2 ops, we can materialize the address directly via movt/movw
1901 // pair. This is always cheaper.
1902 if (Subtarget->useMovt()) {
1903 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
1904 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
1906 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1907 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1908 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1909 MachinePointerInfo::getConstantPool(),
1915 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
1916 SelectionDAG &DAG) const {
1917 MachineFunction &MF = DAG.getMachineFunction();
1918 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1919 unsigned ARMPCLabelIndex = 0;
1920 EVT PtrVT = getPointerTy();
1921 DebugLoc dl = Op.getDebugLoc();
1922 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1923 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1925 if (RelocM == Reloc::Static)
1926 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1928 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1929 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8);
1930 ARMConstantPoolValue *CPV =
1931 new ARMConstantPoolValue(GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj);
1932 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1934 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1936 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1937 MachinePointerInfo::getConstantPool(),
1939 SDValue Chain = Result.getValue(1);
1941 if (RelocM == Reloc::PIC_) {
1942 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1943 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1946 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
1947 Result = DAG.getLoad(PtrVT, dl, Chain, Result, MachinePointerInfo::getGOT(),
1953 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
1954 SelectionDAG &DAG) const {
1955 assert(Subtarget->isTargetELF() &&
1956 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
1957 MachineFunction &MF = DAG.getMachineFunction();
1958 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1959 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1960 EVT PtrVT = getPointerTy();
1961 DebugLoc dl = Op.getDebugLoc();
1962 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1963 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1964 "_GLOBAL_OFFSET_TABLE_",
1965 ARMPCLabelIndex, PCAdj);
1966 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1967 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1968 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1969 MachinePointerInfo::getConstantPool(),
1971 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1972 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1976 ARMTargetLowering::LowerEH_SJLJ_DISPATCHSETUP(SDValue Op, SelectionDAG &DAG)
1978 DebugLoc dl = Op.getDebugLoc();
1979 return DAG.getNode(ARMISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other,
1980 Op.getOperand(0), Op.getOperand(1));
1984 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
1985 DebugLoc dl = Op.getDebugLoc();
1986 SDValue Val = DAG.getConstant(0, MVT::i32);
1987 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(0),
1988 Op.getOperand(1), Val);
1992 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
1993 DebugLoc dl = Op.getDebugLoc();
1994 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
1995 Op.getOperand(1), DAG.getConstant(0, MVT::i32));
1999 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
2000 const ARMSubtarget *Subtarget) const {
2001 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2002 DebugLoc dl = Op.getDebugLoc();
2004 default: return SDValue(); // Don't custom lower most intrinsics.
2005 case Intrinsic::arm_thread_pointer: {
2006 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2007 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2009 case Intrinsic::eh_sjlj_lsda: {
2010 MachineFunction &MF = DAG.getMachineFunction();
2011 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2012 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
2013 EVT PtrVT = getPointerTy();
2014 DebugLoc dl = Op.getDebugLoc();
2015 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2017 unsigned PCAdj = (RelocM != Reloc::PIC_)
2018 ? 0 : (Subtarget->isThumb() ? 4 : 8);
2019 ARMConstantPoolValue *CPV =
2020 new ARMConstantPoolValue(MF.getFunction(), ARMPCLabelIndex,
2021 ARMCP::CPLSDA, PCAdj);
2022 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2023 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2025 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2026 MachinePointerInfo::getConstantPool(),
2029 if (RelocM == Reloc::PIC_) {
2030 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2031 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2038 static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG,
2039 const ARMSubtarget *Subtarget) {
2040 DebugLoc dl = Op.getDebugLoc();
2041 if (!Subtarget->hasDataBarrier()) {
2042 // Some ARMv6 cpus can support data barriers with an mcr instruction.
2043 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
2045 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&
2046 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!");
2047 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2048 DAG.getConstant(0, MVT::i32));
2051 SDValue Op5 = Op.getOperand(5);
2052 bool isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue() != 0;
2053 unsigned isLL = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
2054 unsigned isLS = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
2055 bool isOnlyStoreBarrier = (isLL == 0 && isLS == 0);
2057 ARM_MB::MemBOpt DMBOpt;
2058 if (isDeviceBarrier)
2059 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ST : ARM_MB::SY;
2061 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ISHST : ARM_MB::ISH;
2062 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
2063 DAG.getConstant(DMBOpt, MVT::i32));
2066 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
2067 const ARMSubtarget *Subtarget) {
2068 // ARM pre v5TE and Thumb1 does not have preload instructions.
2069 if (!(Subtarget->isThumb2() ||
2070 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
2071 // Just preserve the chain.
2072 return Op.getOperand(0);
2074 DebugLoc dl = Op.getDebugLoc();
2075 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
2077 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
2078 // ARMv7 with MP extension has PLDW.
2079 return Op.getOperand(0);
2081 if (Subtarget->isThumb())
2083 isRead = ~isRead & 1;
2084 unsigned isData = Subtarget->isThumb() ? 0 : 1;
2086 // Currently there is no intrinsic that matches pli.
2087 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
2088 Op.getOperand(1), DAG.getConstant(isRead, MVT::i32),
2089 DAG.getConstant(isData, MVT::i32));
2092 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
2093 MachineFunction &MF = DAG.getMachineFunction();
2094 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
2096 // vastart just stores the address of the VarArgsFrameIndex slot into the
2097 // memory location argument.
2098 DebugLoc dl = Op.getDebugLoc();
2099 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2100 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2101 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2102 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2103 MachinePointerInfo(SV), false, false, 0);
2107 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
2108 SDValue &Root, SelectionDAG &DAG,
2109 DebugLoc dl) const {
2110 MachineFunction &MF = DAG.getMachineFunction();
2111 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2113 TargetRegisterClass *RC;
2114 if (AFI->isThumb1OnlyFunction())
2115 RC = ARM::tGPRRegisterClass;
2117 RC = ARM::GPRRegisterClass;
2119 // Transform the arguments stored in physical registers into virtual ones.
2120 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2121 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2124 if (NextVA.isMemLoc()) {
2125 MachineFrameInfo *MFI = MF.getFrameInfo();
2126 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
2128 // Create load node to retrieve arguments from the stack.
2129 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2130 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
2131 MachinePointerInfo::getFixedStack(FI),
2134 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2135 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2138 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
2142 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
2143 CallingConv::ID CallConv, bool isVarArg,
2144 const SmallVectorImpl<ISD::InputArg>
2146 DebugLoc dl, SelectionDAG &DAG,
2147 SmallVectorImpl<SDValue> &InVals)
2150 MachineFunction &MF = DAG.getMachineFunction();
2151 MachineFrameInfo *MFI = MF.getFrameInfo();
2153 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2155 // Assign locations to all of the incoming arguments.
2156 SmallVector<CCValAssign, 16> ArgLocs;
2157 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
2159 CCInfo.AnalyzeFormalArguments(Ins,
2160 CCAssignFnForNode(CallConv, /* Return*/ false,
2163 SmallVector<SDValue, 16> ArgValues;
2165 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2166 CCValAssign &VA = ArgLocs[i];
2168 // Arguments stored in registers.
2169 if (VA.isRegLoc()) {
2170 EVT RegVT = VA.getLocVT();
2173 if (VA.needsCustom()) {
2174 // f64 and vector types are split up into multiple registers or
2175 // combinations of registers and stack slots.
2176 if (VA.getLocVT() == MVT::v2f64) {
2177 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
2179 VA = ArgLocs[++i]; // skip ahead to next loc
2181 if (VA.isMemLoc()) {
2182 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
2183 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2184 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
2185 MachinePointerInfo::getFixedStack(FI),
2188 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
2191 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2192 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2193 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
2194 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2195 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
2197 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
2200 TargetRegisterClass *RC;
2202 if (RegVT == MVT::f32)
2203 RC = ARM::SPRRegisterClass;
2204 else if (RegVT == MVT::f64)
2205 RC = ARM::DPRRegisterClass;
2206 else if (RegVT == MVT::v2f64)
2207 RC = ARM::QPRRegisterClass;
2208 else if (RegVT == MVT::i32)
2209 RC = (AFI->isThumb1OnlyFunction() ?
2210 ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
2212 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2214 // Transform the arguments in physical registers into virtual ones.
2215 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2216 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2219 // If this is an 8 or 16-bit value, it is really passed promoted
2220 // to 32 bits. Insert an assert[sz]ext to capture this, then
2221 // truncate to the right size.
2222 switch (VA.getLocInfo()) {
2223 default: llvm_unreachable("Unknown loc info!");
2224 case CCValAssign::Full: break;
2225 case CCValAssign::BCvt:
2226 ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
2228 case CCValAssign::SExt:
2229 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2230 DAG.getValueType(VA.getValVT()));
2231 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2233 case CCValAssign::ZExt:
2234 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2235 DAG.getValueType(VA.getValVT()));
2236 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2240 InVals.push_back(ArgValue);
2242 } else { // VA.isRegLoc()
2245 assert(VA.isMemLoc());
2246 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
2248 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
2249 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(), true);
2251 // Create load nodes to retrieve arguments from the stack.
2252 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2253 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2254 MachinePointerInfo::getFixedStack(FI),
2261 static const unsigned GPRArgRegs[] = {
2262 ARM::R0, ARM::R1, ARM::R2, ARM::R3
2265 unsigned NumGPRs = CCInfo.getFirstUnallocated
2266 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
2268 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
2269 unsigned VARegSize = (4 - NumGPRs) * 4;
2270 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
2271 unsigned ArgOffset = CCInfo.getNextStackOffset();
2272 if (VARegSaveSize) {
2273 // If this function is vararg, store any remaining integer argument regs
2274 // to their spots on the stack so that they may be loaded by deferencing
2275 // the result of va_next.
2276 AFI->setVarArgsRegSaveSize(VARegSaveSize);
2277 AFI->setVarArgsFrameIndex(
2278 MFI->CreateFixedObject(VARegSaveSize,
2279 ArgOffset + VARegSaveSize - VARegSize,
2281 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(),
2284 SmallVector<SDValue, 4> MemOps;
2285 for (; NumGPRs < 4; ++NumGPRs) {
2286 TargetRegisterClass *RC;
2287 if (AFI->isThumb1OnlyFunction())
2288 RC = ARM::tGPRRegisterClass;
2290 RC = ARM::GPRRegisterClass;
2292 unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
2293 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2295 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2296 MachinePointerInfo::getFixedStack(AFI->getVarArgsFrameIndex()),
2298 MemOps.push_back(Store);
2299 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
2300 DAG.getConstant(4, getPointerTy()));
2302 if (!MemOps.empty())
2303 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2304 &MemOps[0], MemOps.size());
2306 // This will point to the next argument passed via stack.
2307 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset, true));
2313 /// isFloatingPointZero - Return true if this is +0.0.
2314 static bool isFloatingPointZero(SDValue Op) {
2315 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
2316 return CFP->getValueAPF().isPosZero();
2317 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
2318 // Maybe this has already been legalized into the constant pool?
2319 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
2320 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
2321 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
2322 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
2323 return CFP->getValueAPF().isPosZero();
2329 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
2330 /// the given operands.
2332 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2333 SDValue &ARMcc, SelectionDAG &DAG,
2334 DebugLoc dl) const {
2335 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
2336 unsigned C = RHSC->getZExtValue();
2337 if (!isLegalICmpImmediate(C)) {
2338 // Constant does not fit, try adjusting it by one?
2343 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
2344 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
2345 RHS = DAG.getConstant(C-1, MVT::i32);
2350 if (C != 0 && isLegalICmpImmediate(C-1)) {
2351 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
2352 RHS = DAG.getConstant(C-1, MVT::i32);
2357 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
2358 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
2359 RHS = DAG.getConstant(C+1, MVT::i32);
2364 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
2365 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2366 RHS = DAG.getConstant(C+1, MVT::i32);
2373 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2374 ARMISD::NodeType CompareType;
2377 CompareType = ARMISD::CMP;
2382 CompareType = ARMISD::CMPZ;
2385 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2386 return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS);
2389 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
2391 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
2392 DebugLoc dl) const {
2394 if (!isFloatingPointZero(RHS))
2395 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS);
2397 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS);
2398 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp);
2401 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2402 SDValue Cond = Op.getOperand(0);
2403 SDValue SelectTrue = Op.getOperand(1);
2404 SDValue SelectFalse = Op.getOperand(2);
2405 DebugLoc dl = Op.getDebugLoc();
2409 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
2410 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
2412 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
2413 const ConstantSDNode *CMOVTrue =
2414 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
2415 const ConstantSDNode *CMOVFalse =
2416 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
2418 if (CMOVTrue && CMOVFalse) {
2419 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
2420 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
2424 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
2426 False = SelectFalse;
2427 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
2432 if (True.getNode() && False.getNode()) {
2433 EVT VT = Cond.getValueType();
2434 SDValue ARMcc = Cond.getOperand(2);
2435 SDValue CCR = Cond.getOperand(3);
2436 SDValue Cmp = Cond.getOperand(4);
2437 return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp);
2442 return DAG.getSelectCC(dl, Cond,
2443 DAG.getConstant(0, Cond.getValueType()),
2444 SelectTrue, SelectFalse, ISD::SETNE);
2447 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
2448 EVT VT = Op.getValueType();
2449 SDValue LHS = Op.getOperand(0);
2450 SDValue RHS = Op.getOperand(1);
2451 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2452 SDValue TrueVal = Op.getOperand(2);
2453 SDValue FalseVal = Op.getOperand(3);
2454 DebugLoc dl = Op.getDebugLoc();
2456 if (LHS.getValueType() == MVT::i32) {
2458 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2459 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2460 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,Cmp);
2463 ARMCC::CondCodes CondCode, CondCode2;
2464 FPCCToARMCC(CC, CondCode, CondCode2);
2466 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2467 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2468 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2469 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
2471 if (CondCode2 != ARMCC::AL) {
2472 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32);
2473 // FIXME: Needs another CMP because flag can have but one use.
2474 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
2475 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
2476 Result, TrueVal, ARMcc2, CCR, Cmp2);
2481 /// canChangeToInt - Given the fp compare operand, return true if it is suitable
2482 /// to morph to an integer compare sequence.
2483 static bool canChangeToInt(SDValue Op, bool &SeenZero,
2484 const ARMSubtarget *Subtarget) {
2485 SDNode *N = Op.getNode();
2486 if (!N->hasOneUse())
2487 // Otherwise it requires moving the value from fp to integer registers.
2489 if (!N->getNumValues())
2491 EVT VT = Op.getValueType();
2492 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
2493 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
2494 // vmrs are very slow, e.g. cortex-a8.
2497 if (isFloatingPointZero(Op)) {
2501 return ISD::isNormalLoad(N);
2504 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
2505 if (isFloatingPointZero(Op))
2506 return DAG.getConstant(0, MVT::i32);
2508 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
2509 return DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2510 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(),
2511 Ld->isVolatile(), Ld->isNonTemporal(),
2512 Ld->getAlignment());
2514 llvm_unreachable("Unknown VFP cmp argument!");
2517 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
2518 SDValue &RetVal1, SDValue &RetVal2) {
2519 if (isFloatingPointZero(Op)) {
2520 RetVal1 = DAG.getConstant(0, MVT::i32);
2521 RetVal2 = DAG.getConstant(0, MVT::i32);
2525 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
2526 SDValue Ptr = Ld->getBasePtr();
2527 RetVal1 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2528 Ld->getChain(), Ptr,
2529 Ld->getPointerInfo(),
2530 Ld->isVolatile(), Ld->isNonTemporal(),
2531 Ld->getAlignment());
2533 EVT PtrType = Ptr.getValueType();
2534 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
2535 SDValue NewPtr = DAG.getNode(ISD::ADD, Op.getDebugLoc(),
2536 PtrType, Ptr, DAG.getConstant(4, PtrType));
2537 RetVal2 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2538 Ld->getChain(), NewPtr,
2539 Ld->getPointerInfo().getWithOffset(4),
2540 Ld->isVolatile(), Ld->isNonTemporal(),
2545 llvm_unreachable("Unknown VFP cmp argument!");
2548 /// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
2549 /// f32 and even f64 comparisons to integer ones.
2551 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
2552 SDValue Chain = Op.getOperand(0);
2553 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2554 SDValue LHS = Op.getOperand(2);
2555 SDValue RHS = Op.getOperand(3);
2556 SDValue Dest = Op.getOperand(4);
2557 DebugLoc dl = Op.getDebugLoc();
2559 bool SeenZero = false;
2560 if (canChangeToInt(LHS, SeenZero, Subtarget) &&
2561 canChangeToInt(RHS, SeenZero, Subtarget) &&
2562 // If one of the operand is zero, it's safe to ignore the NaN case since
2563 // we only care about equality comparisons.
2564 (SeenZero || (DAG.isKnownNeverNaN(LHS) && DAG.isKnownNeverNaN(RHS)))) {
2565 // If unsafe fp math optimization is enabled and there are no othter uses of
2566 // the CMP operands, and the condition code is EQ oe NE, we can optimize it
2567 // to an integer comparison.
2568 if (CC == ISD::SETOEQ)
2570 else if (CC == ISD::SETUNE)
2574 if (LHS.getValueType() == MVT::f32) {
2575 LHS = bitcastf32Toi32(LHS, DAG);
2576 RHS = bitcastf32Toi32(RHS, DAG);
2577 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2578 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2579 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2580 Chain, Dest, ARMcc, CCR, Cmp);
2585 expandf64Toi32(LHS, DAG, LHS1, LHS2);
2586 expandf64Toi32(RHS, DAG, RHS1, RHS2);
2587 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2588 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2589 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
2590 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
2591 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7);
2597 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2598 SDValue Chain = Op.getOperand(0);
2599 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2600 SDValue LHS = Op.getOperand(2);
2601 SDValue RHS = Op.getOperand(3);
2602 SDValue Dest = Op.getOperand(4);
2603 DebugLoc dl = Op.getDebugLoc();
2605 if (LHS.getValueType() == MVT::i32) {
2607 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2608 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2609 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2610 Chain, Dest, ARMcc, CCR, Cmp);
2613 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
2616 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
2617 CC == ISD::SETNE || CC == ISD::SETUNE)) {
2618 SDValue Result = OptimizeVFPBrcond(Op, DAG);
2619 if (Result.getNode())
2623 ARMCC::CondCodes CondCode, CondCode2;
2624 FPCCToARMCC(CC, CondCode, CondCode2);
2626 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2627 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2628 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2629 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
2630 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
2631 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2632 if (CondCode2 != ARMCC::AL) {
2633 ARMcc = DAG.getConstant(CondCode2, MVT::i32);
2634 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
2635 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2640 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
2641 SDValue Chain = Op.getOperand(0);
2642 SDValue Table = Op.getOperand(1);
2643 SDValue Index = Op.getOperand(2);
2644 DebugLoc dl = Op.getDebugLoc();
2646 EVT PTy = getPointerTy();
2647 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
2648 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
2649 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
2650 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
2651 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
2652 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
2653 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2654 if (Subtarget->isThumb2()) {
2655 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
2656 // which does another jump to the destination. This also makes it easier
2657 // to translate it to TBB / TBH later.
2658 // FIXME: This might not work if the function is extremely large.
2659 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
2660 Addr, Op.getOperand(2), JTI, UId);
2662 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2663 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
2664 MachinePointerInfo::getJumpTable(),
2666 Chain = Addr.getValue(1);
2667 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
2668 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2670 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
2671 MachinePointerInfo::getJumpTable(), false, false, 0);
2672 Chain = Addr.getValue(1);
2673 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2677 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
2678 DebugLoc dl = Op.getDebugLoc();
2681 switch (Op.getOpcode()) {
2683 assert(0 && "Invalid opcode!");
2684 case ISD::FP_TO_SINT:
2685 Opc = ARMISD::FTOSI;
2687 case ISD::FP_TO_UINT:
2688 Opc = ARMISD::FTOUI;
2691 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
2692 return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
2695 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
2696 EVT VT = Op.getValueType();
2697 DebugLoc dl = Op.getDebugLoc();
2700 switch (Op.getOpcode()) {
2702 assert(0 && "Invalid opcode!");
2703 case ISD::SINT_TO_FP:
2704 Opc = ARMISD::SITOF;
2706 case ISD::UINT_TO_FP:
2707 Opc = ARMISD::UITOF;
2711 Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
2712 return DAG.getNode(Opc, dl, VT, Op);
2715 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
2716 // Implement fcopysign with a fabs and a conditional fneg.
2717 SDValue Tmp0 = Op.getOperand(0);
2718 SDValue Tmp1 = Op.getOperand(1);
2719 DebugLoc dl = Op.getDebugLoc();
2720 EVT VT = Op.getValueType();
2721 EVT SrcVT = Tmp1.getValueType();
2722 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
2723 SDValue ARMcc = DAG.getConstant(ARMCC::LT, MVT::i32);
2724 SDValue FP0 = DAG.getConstantFP(0.0, SrcVT);
2725 SDValue Cmp = getVFPCmp(Tmp1, FP0, DAG, dl);
2726 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2727 return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMcc, CCR, Cmp);
2730 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
2731 MachineFunction &MF = DAG.getMachineFunction();
2732 MachineFrameInfo *MFI = MF.getFrameInfo();
2733 MFI->setReturnAddressIsTaken(true);
2735 EVT VT = Op.getValueType();
2736 DebugLoc dl = Op.getDebugLoc();
2737 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2739 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
2740 SDValue Offset = DAG.getConstant(4, MVT::i32);
2741 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
2742 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
2743 MachinePointerInfo(), false, false, 0);
2746 // Return LR, which contains the return address. Mark it an implicit live-in.
2747 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
2748 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
2751 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2752 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2753 MFI->setFrameAddressIsTaken(true);
2755 EVT VT = Op.getValueType();
2756 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
2757 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2758 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
2759 ? ARM::R7 : ARM::R11;
2760 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
2762 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
2763 MachinePointerInfo(),
2768 /// ExpandBIT_CONVERT - If the target supports VFP, this function is called to
2769 /// expand a bit convert where either the source or destination type is i64 to
2770 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
2771 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
2772 /// vectors), since the legalizer won't know what to do with that.
2773 static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
2774 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2775 DebugLoc dl = N->getDebugLoc();
2776 SDValue Op = N->getOperand(0);
2778 // This function is only supposed to be called for i64 types, either as the
2779 // source or destination of the bit convert.
2780 EVT SrcVT = Op.getValueType();
2781 EVT DstVT = N->getValueType(0);
2782 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
2783 "ExpandBIT_CONVERT called for non-i64 type");
2785 // Turn i64->f64 into VMOVDRR.
2786 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
2787 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2788 DAG.getConstant(0, MVT::i32));
2789 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2790 DAG.getConstant(1, MVT::i32));
2791 return DAG.getNode(ISD::BIT_CONVERT, dl, DstVT,
2792 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
2795 // Turn f64->i64 into VMOVRRD.
2796 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
2797 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
2798 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
2799 // Merge the pieces into a single i64 value.
2800 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
2806 /// getZeroVector - Returns a vector of specified type with all zero elements.
2807 /// Zero vectors are used to represent vector negation and in those cases
2808 /// will be implemented with the NEON VNEG instruction. However, VNEG does
2809 /// not support i64 elements, so sometimes the zero vectors will need to be
2810 /// explicitly constructed. Regardless, use a canonical VMOV to create the
2812 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2813 assert(VT.isVector() && "Expected a vector type");
2814 // The canonical modified immediate encoding of a zero vector is....0!
2815 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32);
2816 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
2817 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
2818 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov);
2821 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
2822 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2823 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
2824 SelectionDAG &DAG) const {
2825 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2826 EVT VT = Op.getValueType();
2827 unsigned VTBits = VT.getSizeInBits();
2828 DebugLoc dl = Op.getDebugLoc();
2829 SDValue ShOpLo = Op.getOperand(0);
2830 SDValue ShOpHi = Op.getOperand(1);
2831 SDValue ShAmt = Op.getOperand(2);
2833 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
2835 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
2837 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2838 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2839 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
2840 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2841 DAG.getConstant(VTBits, MVT::i32));
2842 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
2843 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2844 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
2846 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2847 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
2849 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
2850 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
2853 SDValue Ops[2] = { Lo, Hi };
2854 return DAG.getMergeValues(Ops, 2, dl);
2857 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
2858 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2859 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
2860 SelectionDAG &DAG) const {
2861 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2862 EVT VT = Op.getValueType();
2863 unsigned VTBits = VT.getSizeInBits();
2864 DebugLoc dl = Op.getDebugLoc();
2865 SDValue ShOpLo = Op.getOperand(0);
2866 SDValue ShOpHi = Op.getOperand(1);
2867 SDValue ShAmt = Op.getOperand(2);
2870 assert(Op.getOpcode() == ISD::SHL_PARTS);
2871 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2872 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2873 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
2874 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2875 DAG.getConstant(VTBits, MVT::i32));
2876 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
2877 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
2879 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2880 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2881 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
2883 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
2884 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
2887 SDValue Ops[2] = { Lo, Hi };
2888 return DAG.getMergeValues(Ops, 2, dl);
2891 SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
2892 SelectionDAG &DAG) const {
2893 // The rounding mode is in bits 23:22 of the FPSCR.
2894 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
2895 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
2896 // so that the shift + and get folded into a bitfield extract.
2897 DebugLoc dl = Op.getDebugLoc();
2898 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
2899 DAG.getConstant(Intrinsic::arm_get_fpscr,
2901 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
2902 DAG.getConstant(1U << 22, MVT::i32));
2903 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
2904 DAG.getConstant(22, MVT::i32));
2905 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
2906 DAG.getConstant(3, MVT::i32));
2909 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
2910 const ARMSubtarget *ST) {
2911 EVT VT = N->getValueType(0);
2912 DebugLoc dl = N->getDebugLoc();
2914 if (!ST->hasV6T2Ops())
2917 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
2918 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
2921 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
2922 const ARMSubtarget *ST) {
2923 EVT VT = N->getValueType(0);
2924 DebugLoc dl = N->getDebugLoc();
2929 // Lower vector shifts on NEON to use VSHL.
2930 assert(ST->hasNEON() && "unexpected vector shift");
2932 // Left shifts translate directly to the vshiftu intrinsic.
2933 if (N->getOpcode() == ISD::SHL)
2934 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2935 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
2936 N->getOperand(0), N->getOperand(1));
2938 assert((N->getOpcode() == ISD::SRA ||
2939 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
2941 // NEON uses the same intrinsics for both left and right shifts. For
2942 // right shifts, the shift amounts are negative, so negate the vector of
2944 EVT ShiftVT = N->getOperand(1).getValueType();
2945 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
2946 getZeroVector(ShiftVT, DAG, dl),
2948 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
2949 Intrinsic::arm_neon_vshifts :
2950 Intrinsic::arm_neon_vshiftu);
2951 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2952 DAG.getConstant(vshiftInt, MVT::i32),
2953 N->getOperand(0), NegatedCount);
2956 static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
2957 const ARMSubtarget *ST) {
2958 EVT VT = N->getValueType(0);
2959 DebugLoc dl = N->getDebugLoc();
2961 // We can get here for a node like i32 = ISD::SHL i32, i64
2965 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
2966 "Unknown shift to lower!");
2968 // We only lower SRA, SRL of 1 here, all others use generic lowering.
2969 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
2970 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
2973 // If we are in thumb mode, we don't have RRX.
2974 if (ST->isThumb1Only()) return SDValue();
2976 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
2977 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2978 DAG.getConstant(0, MVT::i32));
2979 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2980 DAG.getConstant(1, MVT::i32));
2982 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
2983 // captures the result into a carry flag.
2984 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
2985 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
2987 // The low part is an ARMISD::RRX operand, which shifts the carry in.
2988 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
2990 // Merge the pieces into a single i64 value.
2991 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
2994 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
2995 SDValue TmpOp0, TmpOp1;
2996 bool Invert = false;
3000 SDValue Op0 = Op.getOperand(0);
3001 SDValue Op1 = Op.getOperand(1);
3002 SDValue CC = Op.getOperand(2);
3003 EVT VT = Op.getValueType();
3004 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
3005 DebugLoc dl = Op.getDebugLoc();
3007 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
3008 switch (SetCCOpcode) {
3009 default: llvm_unreachable("Illegal FP comparison"); break;
3011 case ISD::SETNE: Invert = true; // Fallthrough
3013 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3015 case ISD::SETLT: Swap = true; // Fallthrough
3017 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3019 case ISD::SETLE: Swap = true; // Fallthrough
3021 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3022 case ISD::SETUGE: Swap = true; // Fallthrough
3023 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
3024 case ISD::SETUGT: Swap = true; // Fallthrough
3025 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
3026 case ISD::SETUEQ: Invert = true; // Fallthrough
3028 // Expand this to (OLT | OGT).
3032 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3033 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
3035 case ISD::SETUO: Invert = true; // Fallthrough
3037 // Expand this to (OLT | OGE).
3041 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3042 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
3046 // Integer comparisons.
3047 switch (SetCCOpcode) {
3048 default: llvm_unreachable("Illegal integer comparison"); break;
3049 case ISD::SETNE: Invert = true;
3050 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3051 case ISD::SETLT: Swap = true;
3052 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3053 case ISD::SETLE: Swap = true;
3054 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3055 case ISD::SETULT: Swap = true;
3056 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
3057 case ISD::SETULE: Swap = true;
3058 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
3061 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
3062 if (Opc == ARMISD::VCEQ) {
3065 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
3067 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
3070 // Ignore bitconvert.
3071 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BIT_CONVERT)
3072 AndOp = AndOp.getOperand(0);
3074 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
3076 Op0 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(0));
3077 Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(1));
3084 std::swap(Op0, Op1);
3086 // If one of the operands is a constant vector zero, attempt to fold the
3087 // comparison to a specialized compare-against-zero form.
3089 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
3091 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) {
3092 if (Opc == ARMISD::VCGE)
3093 Opc = ARMISD::VCLEZ;
3094 else if (Opc == ARMISD::VCGT)
3095 Opc = ARMISD::VCLTZ;
3100 if (SingleOp.getNode()) {
3103 Result = DAG.getNode(ARMISD::VCEQZ, dl, VT, SingleOp); break;
3105 Result = DAG.getNode(ARMISD::VCGEZ, dl, VT, SingleOp); break;
3107 Result = DAG.getNode(ARMISD::VCLEZ, dl, VT, SingleOp); break;
3109 Result = DAG.getNode(ARMISD::VCGTZ, dl, VT, SingleOp); break;
3111 Result = DAG.getNode(ARMISD::VCLTZ, dl, VT, SingleOp); break;
3113 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3116 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3120 Result = DAG.getNOT(dl, Result, VT);
3125 /// isNEONModifiedImm - Check if the specified splat value corresponds to a
3126 /// valid vector constant for a NEON instruction with a "modified immediate"
3127 /// operand (e.g., VMOV). If so, return the encoded value.
3128 static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
3129 unsigned SplatBitSize, SelectionDAG &DAG,
3130 EVT &VT, bool is128Bits, NEONModImmType type) {
3131 unsigned OpCmode, Imm;
3133 // SplatBitSize is set to the smallest size that splats the vector, so a
3134 // zero vector will always have SplatBitSize == 8. However, NEON modified
3135 // immediate instructions others than VMOV do not support the 8-bit encoding
3136 // of a zero vector, and the default encoding of zero is supposed to be the
3141 switch (SplatBitSize) {
3143 if (type != VMOVModImm)
3145 // Any 1-byte value is OK. Op=0, Cmode=1110.
3146 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
3149 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
3153 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
3154 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
3155 if ((SplatBits & ~0xff) == 0) {
3156 // Value = 0x00nn: Op=x, Cmode=100x.
3161 if ((SplatBits & ~0xff00) == 0) {
3162 // Value = 0xnn00: Op=x, Cmode=101x.
3164 Imm = SplatBits >> 8;
3170 // NEON's 32-bit VMOV supports splat values where:
3171 // * only one byte is nonzero, or
3172 // * the least significant byte is 0xff and the second byte is nonzero, or
3173 // * the least significant 2 bytes are 0xff and the third is nonzero.
3174 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
3175 if ((SplatBits & ~0xff) == 0) {
3176 // Value = 0x000000nn: Op=x, Cmode=000x.
3181 if ((SplatBits & ~0xff00) == 0) {
3182 // Value = 0x0000nn00: Op=x, Cmode=001x.
3184 Imm = SplatBits >> 8;
3187 if ((SplatBits & ~0xff0000) == 0) {
3188 // Value = 0x00nn0000: Op=x, Cmode=010x.
3190 Imm = SplatBits >> 16;
3193 if ((SplatBits & ~0xff000000) == 0) {
3194 // Value = 0xnn000000: Op=x, Cmode=011x.
3196 Imm = SplatBits >> 24;
3200 // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC
3201 if (type == OtherModImm) return SDValue();
3203 if ((SplatBits & ~0xffff) == 0 &&
3204 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
3205 // Value = 0x0000nnff: Op=x, Cmode=1100.
3207 Imm = SplatBits >> 8;
3212 if ((SplatBits & ~0xffffff) == 0 &&
3213 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
3214 // Value = 0x00nnffff: Op=x, Cmode=1101.
3216 Imm = SplatBits >> 16;
3217 SplatBits |= 0xffff;
3221 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
3222 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
3223 // VMOV.I32. A (very) minor optimization would be to replicate the value
3224 // and fall through here to test for a valid 64-bit splat. But, then the
3225 // caller would also need to check and handle the change in size.
3229 if (type != VMOVModImm)
3231 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
3232 uint64_t BitMask = 0xff;
3234 unsigned ImmMask = 1;
3236 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
3237 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
3240 } else if ((SplatBits & BitMask) != 0) {
3246 // Op=1, Cmode=1110.
3249 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
3254 llvm_unreachable("unexpected size for isNEONModifiedImm");
3258 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
3259 return DAG.getTargetConstant(EncodedVal, MVT::i32);
3262 static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT,
3263 bool &ReverseVEXT, unsigned &Imm) {
3264 unsigned NumElts = VT.getVectorNumElements();
3265 ReverseVEXT = false;
3267 // Assume that the first shuffle index is not UNDEF. Fail if it is.
3273 // If this is a VEXT shuffle, the immediate value is the index of the first
3274 // element. The other shuffle indices must be the successive elements after
3276 unsigned ExpectedElt = Imm;
3277 for (unsigned i = 1; i < NumElts; ++i) {
3278 // Increment the expected index. If it wraps around, it may still be
3279 // a VEXT but the source vectors must be swapped.
3281 if (ExpectedElt == NumElts * 2) {
3286 if (M[i] < 0) continue; // ignore UNDEF indices
3287 if (ExpectedElt != static_cast<unsigned>(M[i]))
3291 // Adjust the index value if the source operands will be swapped.
3298 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
3299 /// instruction with the specified blocksize. (The order of the elements
3300 /// within each block of the vector is reversed.)
3301 static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT,
3302 unsigned BlockSize) {
3303 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
3304 "Only possible block sizes for VREV are: 16, 32, 64");
3306 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3310 unsigned NumElts = VT.getVectorNumElements();
3311 unsigned BlockElts = M[0] + 1;
3312 // If the first shuffle index is UNDEF, be optimistic.
3314 BlockElts = BlockSize / EltSz;
3316 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
3319 for (unsigned i = 0; i < NumElts; ++i) {
3320 if (M[i] < 0) continue; // ignore UNDEF indices
3321 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
3328 static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT,
3329 unsigned &WhichResult) {
3330 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3334 unsigned NumElts = VT.getVectorNumElements();
3335 WhichResult = (M[0] == 0 ? 0 : 1);
3336 for (unsigned i = 0; i < NumElts; i += 2) {
3337 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3338 (M[i+1] >= 0 && (unsigned) M[i+1] != i + NumElts + WhichResult))
3344 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
3345 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3346 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
3347 static bool isVTRN_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3348 unsigned &WhichResult) {
3349 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3353 unsigned NumElts = VT.getVectorNumElements();
3354 WhichResult = (M[0] == 0 ? 0 : 1);
3355 for (unsigned i = 0; i < NumElts; i += 2) {
3356 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3357 (M[i+1] >= 0 && (unsigned) M[i+1] != i + WhichResult))
3363 static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT,
3364 unsigned &WhichResult) {
3365 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3369 unsigned NumElts = VT.getVectorNumElements();
3370 WhichResult = (M[0] == 0 ? 0 : 1);
3371 for (unsigned i = 0; i != NumElts; ++i) {
3372 if (M[i] < 0) continue; // ignore UNDEF indices
3373 if ((unsigned) M[i] != 2 * i + WhichResult)
3377 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3378 if (VT.is64BitVector() && EltSz == 32)
3384 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
3385 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3386 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
3387 static bool isVUZP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3388 unsigned &WhichResult) {
3389 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3393 unsigned Half = VT.getVectorNumElements() / 2;
3394 WhichResult = (M[0] == 0 ? 0 : 1);
3395 for (unsigned j = 0; j != 2; ++j) {
3396 unsigned Idx = WhichResult;
3397 for (unsigned i = 0; i != Half; ++i) {
3398 int MIdx = M[i + j * Half];
3399 if (MIdx >= 0 && (unsigned) MIdx != Idx)
3405 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3406 if (VT.is64BitVector() && EltSz == 32)
3412 static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT,
3413 unsigned &WhichResult) {
3414 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3418 unsigned NumElts = VT.getVectorNumElements();
3419 WhichResult = (M[0] == 0 ? 0 : 1);
3420 unsigned Idx = WhichResult * NumElts / 2;
3421 for (unsigned i = 0; i != NumElts; i += 2) {
3422 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3423 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts))
3428 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3429 if (VT.is64BitVector() && EltSz == 32)
3435 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
3436 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3437 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
3438 static bool isVZIP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3439 unsigned &WhichResult) {
3440 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3444 unsigned NumElts = VT.getVectorNumElements();
3445 WhichResult = (M[0] == 0 ? 0 : 1);
3446 unsigned Idx = WhichResult * NumElts / 2;
3447 for (unsigned i = 0; i != NumElts; i += 2) {
3448 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3449 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx))
3454 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3455 if (VT.is64BitVector() && EltSz == 32)
3461 // If N is an integer constant that can be moved into a register in one
3462 // instruction, return an SDValue of such a constant (will become a MOV
3463 // instruction). Otherwise return null.
3464 static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG,
3465 const ARMSubtarget *ST, DebugLoc dl) {
3467 if (!isa<ConstantSDNode>(N))
3469 Val = cast<ConstantSDNode>(N)->getZExtValue();
3471 if (ST->isThumb1Only()) {
3472 if (Val <= 255 || ~Val <= 255)
3473 return DAG.getConstant(Val, MVT::i32);
3475 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1)
3476 return DAG.getConstant(Val, MVT::i32);
3481 // If this is a case we can't handle, return null and let the default
3482 // expansion code take care of it.
3483 static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
3484 const ARMSubtarget *ST) {
3485 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
3486 DebugLoc dl = Op.getDebugLoc();
3487 EVT VT = Op.getValueType();
3489 APInt SplatBits, SplatUndef;
3490 unsigned SplatBitSize;
3492 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
3493 if (SplatBitSize <= 64) {
3494 // Check if an immediate VMOV works.
3496 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
3497 SplatUndef.getZExtValue(), SplatBitSize,
3498 DAG, VmovVT, VT.is128BitVector(),
3500 if (Val.getNode()) {
3501 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
3502 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov);
3505 // Try an immediate VMVN.
3506 uint64_t NegatedImm = (SplatBits.getZExtValue() ^
3507 ((1LL << SplatBitSize) - 1));
3508 Val = isNEONModifiedImm(NegatedImm,
3509 SplatUndef.getZExtValue(), SplatBitSize,
3510 DAG, VmovVT, VT.is128BitVector(),
3512 if (Val.getNode()) {
3513 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
3514 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vmov);
3519 // Scan through the operands to see if only one value is used.
3520 unsigned NumElts = VT.getVectorNumElements();
3521 bool isOnlyLowElement = true;
3522 bool usesOnlyOneValue = true;
3523 bool isConstant = true;
3525 for (unsigned i = 0; i < NumElts; ++i) {
3526 SDValue V = Op.getOperand(i);
3527 if (V.getOpcode() == ISD::UNDEF)
3530 isOnlyLowElement = false;
3531 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
3534 if (!Value.getNode())
3536 else if (V != Value)
3537 usesOnlyOneValue = false;
3540 if (!Value.getNode())
3541 return DAG.getUNDEF(VT);
3543 if (isOnlyLowElement)
3544 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
3546 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3548 // Use VDUP for non-constant splats. For f32 constant splats, reduce to
3549 // i32 and try again.
3550 if (usesOnlyOneValue && EltSize <= 32) {
3552 return DAG.getNode(ARMISD::VDUP, dl, VT, Value);
3553 if (VT.getVectorElementType().isFloatingPoint()) {
3554 SmallVector<SDValue, 8> Ops;
3555 for (unsigned i = 0; i < NumElts; ++i)
3556 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32,
3558 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
3559 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], NumElts);
3560 Val = LowerBUILD_VECTOR(Val, DAG, ST);
3562 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val);
3564 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
3566 return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
3569 // If all elements are constants and the case above didn't get hit, fall back
3570 // to the default expansion, which will generate a load from the constant
3575 // Vectors with 32- or 64-bit elements can be built by directly assigning
3576 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
3577 // will be legalized.
3578 if (EltSize >= 32) {
3579 // Do the expansion with floating-point types, since that is what the VFP
3580 // registers are defined to use, and since i64 is not legal.
3581 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3582 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3583 SmallVector<SDValue, 8> Ops;
3584 for (unsigned i = 0; i < NumElts; ++i)
3585 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, dl, EltVT, Op.getOperand(i)));
3586 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
3587 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val);
3593 /// isShuffleMaskLegal - Targets can use this to indicate that they only
3594 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
3595 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
3596 /// are assumed to be legal.
3598 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
3600 if (VT.getVectorNumElements() == 4 &&
3601 (VT.is128BitVector() || VT.is64BitVector())) {
3602 unsigned PFIndexes[4];
3603 for (unsigned i = 0; i != 4; ++i) {
3607 PFIndexes[i] = M[i];
3610 // Compute the index in the perfect shuffle table.
3611 unsigned PFTableIndex =
3612 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3613 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3614 unsigned Cost = (PFEntry >> 30);
3621 unsigned Imm, WhichResult;
3623 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3624 return (EltSize >= 32 ||
3625 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
3626 isVREVMask(M, VT, 64) ||
3627 isVREVMask(M, VT, 32) ||
3628 isVREVMask(M, VT, 16) ||
3629 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
3630 isVTRNMask(M, VT, WhichResult) ||
3631 isVUZPMask(M, VT, WhichResult) ||
3632 isVZIPMask(M, VT, WhichResult) ||
3633 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
3634 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
3635 isVZIP_v_undef_Mask(M, VT, WhichResult));
3638 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
3639 /// the specified operations to build the shuffle.
3640 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
3641 SDValue RHS, SelectionDAG &DAG,
3643 unsigned OpNum = (PFEntry >> 26) & 0x0F;
3644 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
3645 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
3648 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
3657 OP_VUZPL, // VUZP, left result
3658 OP_VUZPR, // VUZP, right result
3659 OP_VZIPL, // VZIP, left result
3660 OP_VZIPR, // VZIP, right result
3661 OP_VTRNL, // VTRN, left result
3662 OP_VTRNR // VTRN, right result
3665 if (OpNum == OP_COPY) {
3666 if (LHSID == (1*9+2)*9+3) return LHS;
3667 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
3671 SDValue OpLHS, OpRHS;
3672 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
3673 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
3674 EVT VT = OpLHS.getValueType();
3677 default: llvm_unreachable("Unknown shuffle opcode!");
3679 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
3684 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
3685 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
3689 return DAG.getNode(ARMISD::VEXT, dl, VT,
3691 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
3694 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3695 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
3698 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3699 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
3702 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3703 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
3707 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
3708 SDValue V1 = Op.getOperand(0);
3709 SDValue V2 = Op.getOperand(1);
3710 DebugLoc dl = Op.getDebugLoc();
3711 EVT VT = Op.getValueType();
3712 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
3713 SmallVector<int, 8> ShuffleMask;
3715 // Convert shuffles that are directly supported on NEON to target-specific
3716 // DAG nodes, instead of keeping them as shuffles and matching them again
3717 // during code selection. This is more efficient and avoids the possibility
3718 // of inconsistencies between legalization and selection.
3719 // FIXME: floating-point vectors should be canonicalized to integer vectors
3720 // of the same time so that they get CSEd properly.
3721 SVN->getMask(ShuffleMask);
3723 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3724 if (EltSize <= 32) {
3725 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
3726 int Lane = SVN->getSplatIndex();
3727 // If this is undef splat, generate it via "just" vdup, if possible.
3728 if (Lane == -1) Lane = 0;
3730 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
3731 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
3733 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
3734 DAG.getConstant(Lane, MVT::i32));
3739 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
3742 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
3743 DAG.getConstant(Imm, MVT::i32));
3746 if (isVREVMask(ShuffleMask, VT, 64))
3747 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
3748 if (isVREVMask(ShuffleMask, VT, 32))
3749 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
3750 if (isVREVMask(ShuffleMask, VT, 16))
3751 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
3753 // Check for Neon shuffles that modify both input vectors in place.
3754 // If both results are used, i.e., if there are two shuffles with the same
3755 // source operands and with masks corresponding to both results of one of
3756 // these operations, DAG memoization will ensure that a single node is
3757 // used for both shuffles.
3758 unsigned WhichResult;
3759 if (isVTRNMask(ShuffleMask, VT, WhichResult))
3760 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3761 V1, V2).getValue(WhichResult);
3762 if (isVUZPMask(ShuffleMask, VT, WhichResult))
3763 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3764 V1, V2).getValue(WhichResult);
3765 if (isVZIPMask(ShuffleMask, VT, WhichResult))
3766 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3767 V1, V2).getValue(WhichResult);
3769 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
3770 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3771 V1, V1).getValue(WhichResult);
3772 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
3773 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3774 V1, V1).getValue(WhichResult);
3775 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
3776 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3777 V1, V1).getValue(WhichResult);
3780 // If the shuffle is not directly supported and it has 4 elements, use
3781 // the PerfectShuffle-generated table to synthesize it from other shuffles.
3782 unsigned NumElts = VT.getVectorNumElements();
3784 unsigned PFIndexes[4];
3785 for (unsigned i = 0; i != 4; ++i) {
3786 if (ShuffleMask[i] < 0)
3789 PFIndexes[i] = ShuffleMask[i];
3792 // Compute the index in the perfect shuffle table.
3793 unsigned PFTableIndex =
3794 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3795 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3796 unsigned Cost = (PFEntry >> 30);
3799 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
3802 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
3803 if (EltSize >= 32) {
3804 // Do the expansion with floating-point types, since that is what the VFP
3805 // registers are defined to use, and since i64 is not legal.
3806 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3807 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3808 V1 = DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, V1);
3809 V2 = DAG.getNode(ISD::BIT_CONVERT, dl, VecVT, V2);
3810 SmallVector<SDValue, 8> Ops;
3811 for (unsigned i = 0; i < NumElts; ++i) {
3812 if (ShuffleMask[i] < 0)
3813 Ops.push_back(DAG.getUNDEF(EltVT));
3815 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3816 ShuffleMask[i] < (int)NumElts ? V1 : V2,
3817 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
3820 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
3821 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Val);
3827 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
3828 // EXTRACT_VECTOR_ELT is legal only for immediate indexes.
3829 SDValue Lane = Op.getOperand(1);
3830 if (!isa<ConstantSDNode>(Lane))
3833 SDValue Vec = Op.getOperand(0);
3834 if (Op.getValueType() == MVT::i32 &&
3835 Vec.getValueType().getVectorElementType().getSizeInBits() < 32) {
3836 DebugLoc dl = Op.getDebugLoc();
3837 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
3843 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
3844 // The only time a CONCAT_VECTORS operation can have legal types is when
3845 // two 64-bit vectors are concatenated to a 128-bit vector.
3846 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
3847 "unexpected CONCAT_VECTORS");
3848 DebugLoc dl = Op.getDebugLoc();
3849 SDValue Val = DAG.getUNDEF(MVT::v2f64);
3850 SDValue Op0 = Op.getOperand(0);
3851 SDValue Op1 = Op.getOperand(1);
3852 if (Op0.getOpcode() != ISD::UNDEF)
3853 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
3854 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op0),
3855 DAG.getIntPtrConstant(0));
3856 if (Op1.getOpcode() != ISD::UNDEF)
3857 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
3858 DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op1),
3859 DAG.getIntPtrConstant(1));
3860 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Val);
3863 /// SkipExtension - For a node that is either a SIGN_EXTEND, ZERO_EXTEND, or
3864 /// an extending load, return the unextended value.
3865 static SDValue SkipExtension(SDNode *N, SelectionDAG &DAG) {
3866 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
3867 return N->getOperand(0);
3868 LoadSDNode *LD = cast<LoadSDNode>(N);
3869 return DAG.getLoad(LD->getMemoryVT(), N->getDebugLoc(), LD->getChain(),
3870 LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(),
3871 LD->isNonTemporal(), LD->getAlignment());
3874 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
3875 // Multiplications are only custom-lowered for 128-bit vectors so that
3876 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
3877 EVT VT = Op.getValueType();
3878 assert(VT.is128BitVector() && "unexpected type for custom-lowering ISD::MUL");
3879 SDNode *N0 = Op.getOperand(0).getNode();
3880 SDNode *N1 = Op.getOperand(1).getNode();
3881 unsigned NewOpc = 0;
3882 if ((N0->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N0)) &&
3883 (N1->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N1))) {
3884 NewOpc = ARMISD::VMULLs;
3885 } else if ((N0->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N0)) &&
3886 (N1->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N1))) {
3887 NewOpc = ARMISD::VMULLu;
3888 } else if (VT == MVT::v2i64) {
3889 // Fall through to expand this. It is not legal.
3892 // Other vector multiplications are legal.
3896 // Legalize to a VMULL instruction.
3897 DebugLoc DL = Op.getDebugLoc();
3898 SDValue Op0 = SkipExtension(N0, DAG);
3899 SDValue Op1 = SkipExtension(N1, DAG);
3901 assert(Op0.getValueType().is64BitVector() &&
3902 Op1.getValueType().is64BitVector() &&
3903 "unexpected types for extended operands to VMULL");
3904 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
3907 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
3908 switch (Op.getOpcode()) {
3909 default: llvm_unreachable("Don't know how to custom lower this!");
3910 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3911 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
3912 case ISD::GlobalAddress:
3913 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
3914 LowerGlobalAddressELF(Op, DAG);
3915 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
3916 case ISD::SELECT: return LowerSELECT(Op, DAG);
3917 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
3918 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
3919 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
3920 case ISD::VASTART: return LowerVASTART(Op, DAG);
3921 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget);
3922 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget);
3923 case ISD::SINT_TO_FP:
3924 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
3925 case ISD::FP_TO_SINT:
3926 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
3927 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
3928 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
3929 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
3930 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
3931 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
3932 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
3933 case ISD::EH_SJLJ_DISPATCHSETUP: return LowerEH_SJLJ_DISPATCHSETUP(Op, DAG);
3934 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
3936 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(Op.getNode(), DAG);
3939 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
3940 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
3941 case ISD::SRL_PARTS:
3942 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
3943 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
3944 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
3945 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
3946 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
3947 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
3948 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
3949 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
3950 case ISD::MUL: return LowerMUL(Op, DAG);
3955 /// ReplaceNodeResults - Replace the results of node with an illegal result
3956 /// type with new values built out of custom code.
3957 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
3958 SmallVectorImpl<SDValue>&Results,
3959 SelectionDAG &DAG) const {
3961 switch (N->getOpcode()) {
3963 llvm_unreachable("Don't know how to custom expand this!");
3965 case ISD::BIT_CONVERT:
3966 Res = ExpandBIT_CONVERT(N, DAG);
3970 Res = Expand64BitShift(N, DAG, Subtarget);
3974 Results.push_back(Res);
3977 //===----------------------------------------------------------------------===//
3978 // ARM Scheduler Hooks
3979 //===----------------------------------------------------------------------===//
3982 ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
3983 MachineBasicBlock *BB,
3984 unsigned Size) const {
3985 unsigned dest = MI->getOperand(0).getReg();
3986 unsigned ptr = MI->getOperand(1).getReg();
3987 unsigned oldval = MI->getOperand(2).getReg();
3988 unsigned newval = MI->getOperand(3).getReg();
3989 unsigned scratch = BB->getParent()->getRegInfo()
3990 .createVirtualRegister(ARM::GPRRegisterClass);
3991 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3992 DebugLoc dl = MI->getDebugLoc();
3993 bool isThumb2 = Subtarget->isThumb2();
3995 unsigned ldrOpc, strOpc;
3997 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
3999 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
4000 strOpc = isThumb2 ? ARM::t2LDREXB : ARM::STREXB;
4003 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
4004 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
4007 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
4008 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
4012 MachineFunction *MF = BB->getParent();
4013 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4014 MachineFunction::iterator It = BB;
4015 ++It; // insert the new blocks after the current block
4017 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
4018 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
4019 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
4020 MF->insert(It, loop1MBB);
4021 MF->insert(It, loop2MBB);
4022 MF->insert(It, exitMBB);
4024 // Transfer the remainder of BB and its successor edges to exitMBB.
4025 exitMBB->splice(exitMBB->begin(), BB,
4026 llvm::next(MachineBasicBlock::iterator(MI)),
4028 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4032 // fallthrough --> loop1MBB
4033 BB->addSuccessor(loop1MBB);
4036 // ldrex dest, [ptr]
4040 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
4041 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
4042 .addReg(dest).addReg(oldval));
4043 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4044 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
4045 BB->addSuccessor(loop2MBB);
4046 BB->addSuccessor(exitMBB);
4049 // strex scratch, newval, [ptr]
4053 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval)
4055 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4056 .addReg(scratch).addImm(0));
4057 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4058 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
4059 BB->addSuccessor(loop1MBB);
4060 BB->addSuccessor(exitMBB);
4066 MI->eraseFromParent(); // The instruction is gone now.
4072 ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
4073 unsigned Size, unsigned BinOpcode) const {
4074 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4075 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4077 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4078 MachineFunction *MF = BB->getParent();
4079 MachineFunction::iterator It = BB;
4082 unsigned dest = MI->getOperand(0).getReg();
4083 unsigned ptr = MI->getOperand(1).getReg();
4084 unsigned incr = MI->getOperand(2).getReg();
4085 DebugLoc dl = MI->getDebugLoc();
4087 bool isThumb2 = Subtarget->isThumb2();
4088 unsigned ldrOpc, strOpc;
4090 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
4092 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
4093 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
4096 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
4097 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
4100 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
4101 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
4105 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
4106 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
4107 MF->insert(It, loopMBB);
4108 MF->insert(It, exitMBB);
4110 // Transfer the remainder of BB and its successor edges to exitMBB.
4111 exitMBB->splice(exitMBB->begin(), BB,
4112 llvm::next(MachineBasicBlock::iterator(MI)),
4114 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4116 MachineRegisterInfo &RegInfo = MF->getRegInfo();
4117 unsigned scratch = RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
4118 unsigned scratch2 = (!BinOpcode) ? incr :
4119 RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
4123 // fallthrough --> loopMBB
4124 BB->addSuccessor(loopMBB);
4128 // <binop> scratch2, dest, incr
4129 // strex scratch, scratch2, ptr
4132 // fallthrough --> exitMBB
4134 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
4136 // operand order needs to go the other way for NAND
4137 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr)
4138 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
4139 addReg(incr).addReg(dest)).addReg(0);
4141 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
4142 addReg(dest).addReg(incr)).addReg(0);
4145 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2)
4147 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4148 .addReg(scratch).addImm(0));
4149 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4150 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
4152 BB->addSuccessor(loopMBB);
4153 BB->addSuccessor(exitMBB);
4159 MI->eraseFromParent(); // The instruction is gone now.
4165 MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
4166 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
4167 E = MBB->succ_end(); I != E; ++I)
4170 llvm_unreachable("Expecting a BB with two successors!");
4174 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4175 MachineBasicBlock *BB) const {
4176 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4177 DebugLoc dl = MI->getDebugLoc();
4178 bool isThumb2 = Subtarget->isThumb2();
4179 switch (MI->getOpcode()) {
4182 llvm_unreachable("Unexpected instr type to insert");
4184 case ARM::ATOMIC_LOAD_ADD_I8:
4185 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
4186 case ARM::ATOMIC_LOAD_ADD_I16:
4187 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
4188 case ARM::ATOMIC_LOAD_ADD_I32:
4189 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
4191 case ARM::ATOMIC_LOAD_AND_I8:
4192 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
4193 case ARM::ATOMIC_LOAD_AND_I16:
4194 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
4195 case ARM::ATOMIC_LOAD_AND_I32:
4196 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
4198 case ARM::ATOMIC_LOAD_OR_I8:
4199 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
4200 case ARM::ATOMIC_LOAD_OR_I16:
4201 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
4202 case ARM::ATOMIC_LOAD_OR_I32:
4203 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
4205 case ARM::ATOMIC_LOAD_XOR_I8:
4206 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
4207 case ARM::ATOMIC_LOAD_XOR_I16:
4208 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
4209 case ARM::ATOMIC_LOAD_XOR_I32:
4210 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
4212 case ARM::ATOMIC_LOAD_NAND_I8:
4213 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
4214 case ARM::ATOMIC_LOAD_NAND_I16:
4215 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
4216 case ARM::ATOMIC_LOAD_NAND_I32:
4217 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
4219 case ARM::ATOMIC_LOAD_SUB_I8:
4220 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
4221 case ARM::ATOMIC_LOAD_SUB_I16:
4222 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
4223 case ARM::ATOMIC_LOAD_SUB_I32:
4224 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
4226 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0);
4227 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0);
4228 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0);
4230 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1);
4231 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
4232 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
4234 case ARM::tMOVCCr_pseudo: {
4235 // To "insert" a SELECT_CC instruction, we actually have to insert the
4236 // diamond control-flow pattern. The incoming instruction knows the
4237 // destination vreg to set, the condition code register to branch on, the
4238 // true/false values to select between, and a branch opcode to use.
4239 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4240 MachineFunction::iterator It = BB;
4246 // cmpTY ccX, r1, r2
4248 // fallthrough --> copy0MBB
4249 MachineBasicBlock *thisMBB = BB;
4250 MachineFunction *F = BB->getParent();
4251 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4252 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
4253 F->insert(It, copy0MBB);
4254 F->insert(It, sinkMBB);
4256 // Transfer the remainder of BB and its successor edges to sinkMBB.
4257 sinkMBB->splice(sinkMBB->begin(), BB,
4258 llvm::next(MachineBasicBlock::iterator(MI)),
4260 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
4262 BB->addSuccessor(copy0MBB);
4263 BB->addSuccessor(sinkMBB);
4265 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
4266 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
4269 // %FalseValue = ...
4270 // # fallthrough to sinkMBB
4273 // Update machine-CFG edges
4274 BB->addSuccessor(sinkMBB);
4277 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
4280 BuildMI(*BB, BB->begin(), dl,
4281 TII->get(ARM::PHI), MI->getOperand(0).getReg())
4282 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
4283 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
4285 MI->eraseFromParent(); // The pseudo instruction is gone now.
4290 case ARM::BCCZi64: {
4291 // Compare both parts that make up the double comparison separately for
4293 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
4295 unsigned LHS1 = MI->getOperand(1).getReg();
4296 unsigned LHS2 = MI->getOperand(2).getReg();
4298 AddDefaultPred(BuildMI(BB, dl,
4299 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4300 .addReg(LHS1).addImm(0));
4301 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4302 .addReg(LHS2).addImm(0)
4303 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
4305 unsigned RHS1 = MI->getOperand(3).getReg();
4306 unsigned RHS2 = MI->getOperand(4).getReg();
4307 AddDefaultPred(BuildMI(BB, dl,
4308 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
4309 .addReg(LHS1).addReg(RHS1));
4310 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
4311 .addReg(LHS2).addReg(RHS2)
4312 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
4315 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB();
4316 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
4317 if (MI->getOperand(0).getImm() == ARMCC::NE)
4318 std::swap(destMBB, exitMBB);
4320 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4321 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
4322 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2B : ARM::B))
4325 MI->eraseFromParent(); // The pseudo instruction is gone now.
4331 //===----------------------------------------------------------------------===//
4332 // ARM Optimization Hooks
4333 //===----------------------------------------------------------------------===//
4336 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
4337 TargetLowering::DAGCombinerInfo &DCI) {
4338 SelectionDAG &DAG = DCI.DAG;
4339 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4340 EVT VT = N->getValueType(0);
4341 unsigned Opc = N->getOpcode();
4342 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
4343 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
4344 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
4345 ISD::CondCode CC = ISD::SETCC_INVALID;
4348 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
4350 SDValue CCOp = Slct.getOperand(0);
4351 if (CCOp.getOpcode() == ISD::SETCC)
4352 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
4355 bool DoXform = false;
4357 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
4360 if (LHS.getOpcode() == ISD::Constant &&
4361 cast<ConstantSDNode>(LHS)->isNullValue()) {
4363 } else if (CC != ISD::SETCC_INVALID &&
4364 RHS.getOpcode() == ISD::Constant &&
4365 cast<ConstantSDNode>(RHS)->isNullValue()) {
4366 std::swap(LHS, RHS);
4367 SDValue Op0 = Slct.getOperand(0);
4368 EVT OpVT = isSlctCC ? Op0.getValueType() :
4369 Op0.getOperand(0).getValueType();
4370 bool isInt = OpVT.isInteger();
4371 CC = ISD::getSetCCInverse(CC, isInt);
4373 if (!TLI.isCondCodeLegal(CC, OpVT))
4374 return SDValue(); // Inverse operator isn't legal.
4381 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
4383 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
4384 Slct.getOperand(0), Slct.getOperand(1), CC);
4385 SDValue CCOp = Slct.getOperand(0);
4387 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
4388 CCOp.getOperand(0), CCOp.getOperand(1), CC);
4389 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
4390 CCOp, OtherOp, Result);
4395 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
4396 /// operands N0 and N1. This is a helper for PerformADDCombine that is
4397 /// called with the default operands, and if that fails, with commuted
4399 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
4400 TargetLowering::DAGCombinerInfo &DCI) {
4401 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
4402 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
4403 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
4404 if (Result.getNode()) return Result;
4409 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
4411 static SDValue PerformADDCombine(SDNode *N,
4412 TargetLowering::DAGCombinerInfo &DCI) {
4413 SDValue N0 = N->getOperand(0);
4414 SDValue N1 = N->getOperand(1);
4416 // First try with the default operand order.
4417 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI);
4418 if (Result.getNode())
4421 // If that didn't work, try again with the operands commuted.
4422 return PerformADDCombineWithOperands(N, N1, N0, DCI);
4425 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
4427 static SDValue PerformSUBCombine(SDNode *N,
4428 TargetLowering::DAGCombinerInfo &DCI) {
4429 SDValue N0 = N->getOperand(0);
4430 SDValue N1 = N->getOperand(1);
4432 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
4433 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
4434 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
4435 if (Result.getNode()) return Result;
4441 static SDValue PerformMULCombine(SDNode *N,
4442 TargetLowering::DAGCombinerInfo &DCI,
4443 const ARMSubtarget *Subtarget) {
4444 SelectionDAG &DAG = DCI.DAG;
4446 if (Subtarget->isThumb1Only())
4449 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
4452 EVT VT = N->getValueType(0);
4456 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
4460 uint64_t MulAmt = C->getZExtValue();
4461 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt);
4462 ShiftAmt = ShiftAmt & (32 - 1);
4463 SDValue V = N->getOperand(0);
4464 DebugLoc DL = N->getDebugLoc();
4467 MulAmt >>= ShiftAmt;
4468 if (isPowerOf2_32(MulAmt - 1)) {
4469 // (mul x, 2^N + 1) => (add (shl x, N), x)
4470 Res = DAG.getNode(ISD::ADD, DL, VT,
4471 V, DAG.getNode(ISD::SHL, DL, VT,
4472 V, DAG.getConstant(Log2_32(MulAmt-1),
4474 } else if (isPowerOf2_32(MulAmt + 1)) {
4475 // (mul x, 2^N - 1) => (sub (shl x, N), x)
4476 Res = DAG.getNode(ISD::SUB, DL, VT,
4477 DAG.getNode(ISD::SHL, DL, VT,
4478 V, DAG.getConstant(Log2_32(MulAmt+1),
4485 Res = DAG.getNode(ISD::SHL, DL, VT, Res,
4486 DAG.getConstant(ShiftAmt, MVT::i32));
4488 // Do not add new nodes to DAG combiner worklist.
4489 DCI.CombineTo(N, Res, false);
4493 static SDValue PerformANDCombine(SDNode *N,
4494 TargetLowering::DAGCombinerInfo &DCI) {
4495 // Attempt to use immediate-form VBIC
4496 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
4497 DebugLoc dl = N->getDebugLoc();
4498 EVT VT = N->getValueType(0);
4499 SelectionDAG &DAG = DCI.DAG;
4501 APInt SplatBits, SplatUndef;
4502 unsigned SplatBitSize;
4505 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
4506 if (SplatBitSize <= 64) {
4508 SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(),
4509 SplatUndef.getZExtValue(), SplatBitSize,
4510 DAG, VbicVT, VT.is128BitVector(),
4512 if (Val.getNode()) {
4514 DAG.getNode(ISD::BIT_CONVERT, dl, VbicVT, N->getOperand(0));
4515 SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val);
4516 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vbic);
4524 /// PerformORCombine - Target-specific dag combine xforms for ISD::OR
4525 static SDValue PerformORCombine(SDNode *N,
4526 TargetLowering::DAGCombinerInfo &DCI,
4527 const ARMSubtarget *Subtarget) {
4528 // Attempt to use immediate-form VORR
4529 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
4530 DebugLoc dl = N->getDebugLoc();
4531 EVT VT = N->getValueType(0);
4532 SelectionDAG &DAG = DCI.DAG;
4534 APInt SplatBits, SplatUndef;
4535 unsigned SplatBitSize;
4537 if (BVN && Subtarget->hasNEON() &&
4538 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
4539 if (SplatBitSize <= 64) {
4541 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
4542 SplatUndef.getZExtValue(), SplatBitSize,
4543 DAG, VorrVT, VT.is128BitVector(),
4545 if (Val.getNode()) {
4547 DAG.getNode(ISD::BIT_CONVERT, dl, VorrVT, N->getOperand(0));
4548 SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val);
4549 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vorr);
4554 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when
4557 // BFI is only available on V6T2+
4558 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops())
4561 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
4562 DebugLoc DL = N->getDebugLoc();
4563 // 1) or (and A, mask), val => ARMbfi A, val, mask
4564 // iff (val & mask) == val
4566 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
4567 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2)
4568 // && CountPopulation_32(mask) == CountPopulation_32(~mask2)
4569 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2)
4570 // && CountPopulation_32(mask) == CountPopulation_32(~mask2)
4571 // (i.e., copy a bitfield value into another bitfield of the same width)
4572 if (N0.getOpcode() != ISD::AND)
4579 // The value and the mask need to be constants so we can verify this is
4580 // actually a bitfield set. If the mask is 0xffff, we can do better
4581 // via a movt instruction, so don't use BFI in that case.
4582 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
4585 unsigned Mask = C->getZExtValue();
4589 // Case (1): or (and A, mask), val => ARMbfi A, val, mask
4590 if ((C = dyn_cast<ConstantSDNode>(N1))) {
4591 unsigned Val = C->getZExtValue();
4592 if (!ARM::isBitFieldInvertedMask(Mask) || (Val & ~Mask) != Val)
4594 Val >>= CountTrailingZeros_32(~Mask);
4596 Res = DAG.getNode(ARMISD::BFI, DL, VT, N0.getOperand(0),
4597 DAG.getConstant(Val, MVT::i32),
4598 DAG.getConstant(Mask, MVT::i32));
4600 // Do not add new nodes to DAG combiner worklist.
4601 DCI.CombineTo(N, Res, false);
4602 } else if (N1.getOpcode() == ISD::AND) {
4603 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
4604 C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
4607 unsigned Mask2 = C->getZExtValue();
4609 if (ARM::isBitFieldInvertedMask(Mask) &&
4610 ARM::isBitFieldInvertedMask(~Mask2) &&
4611 (CountPopulation_32(Mask) == CountPopulation_32(~Mask2))) {
4612 // The pack halfword instruction works better for masks that fit it,
4613 // so use that when it's available.
4614 if (Subtarget->hasT2ExtractPack() &&
4615 (Mask == 0xffff || Mask == 0xffff0000))
4618 unsigned lsb = CountTrailingZeros_32(Mask2);
4619 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
4620 DAG.getConstant(lsb, MVT::i32));
4621 Res = DAG.getNode(ARMISD::BFI, DL, VT, N0.getOperand(0), Res,
4622 DAG.getConstant(Mask, MVT::i32));
4623 // Do not add new nodes to DAG combiner worklist.
4624 DCI.CombineTo(N, Res, false);
4625 } else if (ARM::isBitFieldInvertedMask(~Mask) &&
4626 ARM::isBitFieldInvertedMask(Mask2) &&
4627 (CountPopulation_32(~Mask) == CountPopulation_32(Mask2))) {
4628 // The pack halfword instruction works better for masks that fit it,
4629 // so use that when it's available.
4630 if (Subtarget->hasT2ExtractPack() &&
4631 (Mask2 == 0xffff || Mask2 == 0xffff0000))
4634 unsigned lsb = CountTrailingZeros_32(Mask);
4635 Res = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0),
4636 DAG.getConstant(lsb, MVT::i32));
4637 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
4638 DAG.getConstant(Mask2, MVT::i32));
4639 // Do not add new nodes to DAG combiner worklist.
4640 DCI.CombineTo(N, Res, false);
4647 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
4648 /// ARMISD::VMOVRRD.
4649 static SDValue PerformVMOVRRDCombine(SDNode *N,
4650 TargetLowering::DAGCombinerInfo &DCI) {
4651 // vmovrrd(vmovdrr x, y) -> x,y
4652 SDValue InDouble = N->getOperand(0);
4653 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
4654 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
4658 /// PerformVMOVDRRCombine - Target-specific dag combine xforms for
4659 /// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands.
4660 static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) {
4661 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X)
4662 SDValue Op0 = N->getOperand(0);
4663 SDValue Op1 = N->getOperand(1);
4664 if (Op0.getOpcode() == ISD::BIT_CONVERT)
4665 Op0 = Op0.getOperand(0);
4666 if (Op1.getOpcode() == ISD::BIT_CONVERT)
4667 Op1 = Op1.getOperand(0);
4668 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
4669 Op0.getNode() == Op1.getNode() &&
4670 Op0.getResNo() == 0 && Op1.getResNo() == 1)
4671 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
4672 N->getValueType(0), Op0.getOperand(0));
4676 /// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for
4677 /// ISD::BUILD_VECTOR.
4678 static SDValue PerformBUILD_VECTORCombine(SDNode *N, SelectionDAG &DAG) {
4679 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X):
4680 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value
4681 // into a pair of GPRs, which is fine when the value is used as a scalar,
4682 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD.
4683 if (N->getNumOperands() == 2)
4684 return PerformVMOVDRRCombine(N, DAG);
4689 /// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for
4690 /// ISD::VECTOR_SHUFFLE.
4691 static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) {
4692 // The LLVM shufflevector instruction does not require the shuffle mask
4693 // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does
4694 // have that requirement. When translating to ISD::VECTOR_SHUFFLE, if the
4695 // operands do not match the mask length, they are extended by concatenating
4696 // them with undef vectors. That is probably the right thing for other
4697 // targets, but for NEON it is better to concatenate two double-register
4698 // size vector operands into a single quad-register size vector. Do that
4699 // transformation here:
4700 // shuffle(concat(v1, undef), concat(v2, undef)) ->
4701 // shuffle(concat(v1, v2), undef)
4702 SDValue Op0 = N->getOperand(0);
4703 SDValue Op1 = N->getOperand(1);
4704 if (Op0.getOpcode() != ISD::CONCAT_VECTORS ||
4705 Op1.getOpcode() != ISD::CONCAT_VECTORS ||
4706 Op0.getNumOperands() != 2 ||
4707 Op1.getNumOperands() != 2)
4709 SDValue Concat0Op1 = Op0.getOperand(1);
4710 SDValue Concat1Op1 = Op1.getOperand(1);
4711 if (Concat0Op1.getOpcode() != ISD::UNDEF ||
4712 Concat1Op1.getOpcode() != ISD::UNDEF)
4714 // Skip the transformation if any of the types are illegal.
4715 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4716 EVT VT = N->getValueType(0);
4717 if (!TLI.isTypeLegal(VT) ||
4718 !TLI.isTypeLegal(Concat0Op1.getValueType()) ||
4719 !TLI.isTypeLegal(Concat1Op1.getValueType()))
4722 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT,
4723 Op0.getOperand(0), Op1.getOperand(0));
4724 // Translate the shuffle mask.
4725 SmallVector<int, 16> NewMask;
4726 unsigned NumElts = VT.getVectorNumElements();
4727 unsigned HalfElts = NumElts/2;
4728 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
4729 for (unsigned n = 0; n < NumElts; ++n) {
4730 int MaskElt = SVN->getMaskElt(n);
4732 if (MaskElt < (int)HalfElts)
4734 else if (MaskElt >= (int)NumElts && MaskElt < (int)(NumElts + HalfElts))
4735 NewElt = HalfElts + MaskElt - NumElts;
4736 NewMask.push_back(NewElt);
4738 return DAG.getVectorShuffle(VT, N->getDebugLoc(), NewConcat,
4739 DAG.getUNDEF(VT), NewMask.data());
4742 /// PerformVDUPLANECombine - Target-specific dag combine xforms for
4743 /// ARMISD::VDUPLANE.
4744 static SDValue PerformVDUPLANECombine(SDNode *N, SelectionDAG &DAG) {
4745 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
4747 SDValue Op = N->getOperand(0);
4748 EVT VT = N->getValueType(0);
4750 // Ignore bit_converts.
4751 while (Op.getOpcode() == ISD::BIT_CONVERT)
4752 Op = Op.getOperand(0);
4753 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
4756 // Make sure the VMOV element size is not bigger than the VDUPLANE elements.
4757 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits();
4758 // The canonical VMOV for a zero vector uses a 32-bit element size.
4759 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
4761 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
4763 if (EltSize > VT.getVectorElementType().getSizeInBits())
4766 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, Op);
4769 /// getVShiftImm - Check if this is a valid build_vector for the immediate
4770 /// operand of a vector shift operation, where all the elements of the
4771 /// build_vector must have the same constant integer value.
4772 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
4773 // Ignore bit_converts.
4774 while (Op.getOpcode() == ISD::BIT_CONVERT)
4775 Op = Op.getOperand(0);
4776 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
4777 APInt SplatBits, SplatUndef;
4778 unsigned SplatBitSize;
4780 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
4781 HasAnyUndefs, ElementBits) ||
4782 SplatBitSize > ElementBits)
4784 Cnt = SplatBits.getSExtValue();
4788 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
4789 /// operand of a vector shift left operation. That value must be in the range:
4790 /// 0 <= Value < ElementBits for a left shift; or
4791 /// 0 <= Value <= ElementBits for a long left shift.
4792 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
4793 assert(VT.isVector() && "vector shift count is not a vector type");
4794 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
4795 if (! getVShiftImm(Op, ElementBits, Cnt))
4797 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
4800 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
4801 /// operand of a vector shift right operation. For a shift opcode, the value
4802 /// is positive, but for an intrinsic the value count must be negative. The
4803 /// absolute value must be in the range:
4804 /// 1 <= |Value| <= ElementBits for a right shift; or
4805 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
4806 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
4808 assert(VT.isVector() && "vector shift count is not a vector type");
4809 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
4810 if (! getVShiftImm(Op, ElementBits, Cnt))
4814 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
4817 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
4818 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
4819 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
4822 // Don't do anything for most intrinsics.
4825 // Vector shifts: check for immediate versions and lower them.
4826 // Note: This is done during DAG combining instead of DAG legalizing because
4827 // the build_vectors for 64-bit vector element shift counts are generally
4828 // not legal, and it is hard to see their values after they get legalized to
4829 // loads from a constant pool.
4830 case Intrinsic::arm_neon_vshifts:
4831 case Intrinsic::arm_neon_vshiftu:
4832 case Intrinsic::arm_neon_vshiftls:
4833 case Intrinsic::arm_neon_vshiftlu:
4834 case Intrinsic::arm_neon_vshiftn:
4835 case Intrinsic::arm_neon_vrshifts:
4836 case Intrinsic::arm_neon_vrshiftu:
4837 case Intrinsic::arm_neon_vrshiftn:
4838 case Intrinsic::arm_neon_vqshifts:
4839 case Intrinsic::arm_neon_vqshiftu:
4840 case Intrinsic::arm_neon_vqshiftsu:
4841 case Intrinsic::arm_neon_vqshiftns:
4842 case Intrinsic::arm_neon_vqshiftnu:
4843 case Intrinsic::arm_neon_vqshiftnsu:
4844 case Intrinsic::arm_neon_vqrshiftns:
4845 case Intrinsic::arm_neon_vqrshiftnu:
4846 case Intrinsic::arm_neon_vqrshiftnsu: {
4847 EVT VT = N->getOperand(1).getValueType();
4849 unsigned VShiftOpc = 0;
4852 case Intrinsic::arm_neon_vshifts:
4853 case Intrinsic::arm_neon_vshiftu:
4854 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
4855 VShiftOpc = ARMISD::VSHL;
4858 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
4859 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
4860 ARMISD::VSHRs : ARMISD::VSHRu);
4865 case Intrinsic::arm_neon_vshiftls:
4866 case Intrinsic::arm_neon_vshiftlu:
4867 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
4869 llvm_unreachable("invalid shift count for vshll intrinsic");
4871 case Intrinsic::arm_neon_vrshifts:
4872 case Intrinsic::arm_neon_vrshiftu:
4873 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
4877 case Intrinsic::arm_neon_vqshifts:
4878 case Intrinsic::arm_neon_vqshiftu:
4879 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
4883 case Intrinsic::arm_neon_vqshiftsu:
4884 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
4886 llvm_unreachable("invalid shift count for vqshlu intrinsic");
4888 case Intrinsic::arm_neon_vshiftn:
4889 case Intrinsic::arm_neon_vrshiftn:
4890 case Intrinsic::arm_neon_vqshiftns:
4891 case Intrinsic::arm_neon_vqshiftnu:
4892 case Intrinsic::arm_neon_vqshiftnsu:
4893 case Intrinsic::arm_neon_vqrshiftns:
4894 case Intrinsic::arm_neon_vqrshiftnu:
4895 case Intrinsic::arm_neon_vqrshiftnsu:
4896 // Narrowing shifts require an immediate right shift.
4897 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
4899 llvm_unreachable("invalid shift count for narrowing vector shift "
4903 llvm_unreachable("unhandled vector shift");
4907 case Intrinsic::arm_neon_vshifts:
4908 case Intrinsic::arm_neon_vshiftu:
4909 // Opcode already set above.
4911 case Intrinsic::arm_neon_vshiftls:
4912 case Intrinsic::arm_neon_vshiftlu:
4913 if (Cnt == VT.getVectorElementType().getSizeInBits())
4914 VShiftOpc = ARMISD::VSHLLi;
4916 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
4917 ARMISD::VSHLLs : ARMISD::VSHLLu);
4919 case Intrinsic::arm_neon_vshiftn:
4920 VShiftOpc = ARMISD::VSHRN; break;
4921 case Intrinsic::arm_neon_vrshifts:
4922 VShiftOpc = ARMISD::VRSHRs; break;
4923 case Intrinsic::arm_neon_vrshiftu:
4924 VShiftOpc = ARMISD::VRSHRu; break;
4925 case Intrinsic::arm_neon_vrshiftn:
4926 VShiftOpc = ARMISD::VRSHRN; break;
4927 case Intrinsic::arm_neon_vqshifts:
4928 VShiftOpc = ARMISD::VQSHLs; break;
4929 case Intrinsic::arm_neon_vqshiftu:
4930 VShiftOpc = ARMISD::VQSHLu; break;
4931 case Intrinsic::arm_neon_vqshiftsu:
4932 VShiftOpc = ARMISD::VQSHLsu; break;
4933 case Intrinsic::arm_neon_vqshiftns:
4934 VShiftOpc = ARMISD::VQSHRNs; break;
4935 case Intrinsic::arm_neon_vqshiftnu:
4936 VShiftOpc = ARMISD::VQSHRNu; break;
4937 case Intrinsic::arm_neon_vqshiftnsu:
4938 VShiftOpc = ARMISD::VQSHRNsu; break;
4939 case Intrinsic::arm_neon_vqrshiftns:
4940 VShiftOpc = ARMISD::VQRSHRNs; break;
4941 case Intrinsic::arm_neon_vqrshiftnu:
4942 VShiftOpc = ARMISD::VQRSHRNu; break;
4943 case Intrinsic::arm_neon_vqrshiftnsu:
4944 VShiftOpc = ARMISD::VQRSHRNsu; break;
4947 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
4948 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
4951 case Intrinsic::arm_neon_vshiftins: {
4952 EVT VT = N->getOperand(1).getValueType();
4954 unsigned VShiftOpc = 0;
4956 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
4957 VShiftOpc = ARMISD::VSLI;
4958 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
4959 VShiftOpc = ARMISD::VSRI;
4961 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
4964 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
4965 N->getOperand(1), N->getOperand(2),
4966 DAG.getConstant(Cnt, MVT::i32));
4969 case Intrinsic::arm_neon_vqrshifts:
4970 case Intrinsic::arm_neon_vqrshiftu:
4971 // No immediate versions of these to check for.
4978 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
4979 /// lowers them. As with the vector shift intrinsics, this is done during DAG
4980 /// combining instead of DAG legalizing because the build_vectors for 64-bit
4981 /// vector element shift counts are generally not legal, and it is hard to see
4982 /// their values after they get legalized to loads from a constant pool.
4983 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
4984 const ARMSubtarget *ST) {
4985 EVT VT = N->getValueType(0);
4987 // Nothing to be done for scalar shifts.
4988 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4989 if (!VT.isVector() || !TLI.isTypeLegal(VT))
4992 assert(ST->hasNEON() && "unexpected vector shift");
4995 switch (N->getOpcode()) {
4996 default: llvm_unreachable("unexpected shift opcode");
4999 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
5000 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
5001 DAG.getConstant(Cnt, MVT::i32));
5006 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
5007 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
5008 ARMISD::VSHRs : ARMISD::VSHRu);
5009 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
5010 DAG.getConstant(Cnt, MVT::i32));
5016 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
5017 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
5018 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
5019 const ARMSubtarget *ST) {
5020 SDValue N0 = N->getOperand(0);
5022 // Check for sign- and zero-extensions of vector extract operations of 8-
5023 // and 16-bit vector elements. NEON supports these directly. They are
5024 // handled during DAG combining because type legalization will promote them
5025 // to 32-bit types and it is messy to recognize the operations after that.
5026 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
5027 SDValue Vec = N0.getOperand(0);
5028 SDValue Lane = N0.getOperand(1);
5029 EVT VT = N->getValueType(0);
5030 EVT EltVT = N0.getValueType();
5031 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5033 if (VT == MVT::i32 &&
5034 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
5035 TLI.isTypeLegal(Vec.getValueType()) &&
5036 isa<ConstantSDNode>(Lane)) {
5039 switch (N->getOpcode()) {
5040 default: llvm_unreachable("unexpected opcode");
5041 case ISD::SIGN_EXTEND:
5042 Opc = ARMISD::VGETLANEs;
5044 case ISD::ZERO_EXTEND:
5045 case ISD::ANY_EXTEND:
5046 Opc = ARMISD::VGETLANEu;
5049 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
5056 /// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
5057 /// to match f32 max/min patterns to use NEON vmax/vmin instructions.
5058 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
5059 const ARMSubtarget *ST) {
5060 // If the target supports NEON, try to use vmax/vmin instructions for f32
5061 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set,
5062 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
5063 // a NaN; only do the transformation when it matches that behavior.
5065 // For now only do this when using NEON for FP operations; if using VFP, it
5066 // is not obvious that the benefit outweighs the cost of switching to the
5068 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
5069 N->getValueType(0) != MVT::f32)
5072 SDValue CondLHS = N->getOperand(0);
5073 SDValue CondRHS = N->getOperand(1);
5074 SDValue LHS = N->getOperand(2);
5075 SDValue RHS = N->getOperand(3);
5076 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
5078 unsigned Opcode = 0;
5080 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
5081 IsReversed = false; // x CC y ? x : y
5082 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
5083 IsReversed = true ; // x CC y ? y : x
5097 // If LHS is NaN, an ordered comparison will be false and the result will
5098 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
5099 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
5100 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
5101 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
5103 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
5104 // will return -0, so vmin can only be used for unsafe math or if one of
5105 // the operands is known to be nonzero.
5106 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
5108 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
5110 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
5119 // If LHS is NaN, an ordered comparison will be false and the result will
5120 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
5121 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
5122 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
5123 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
5125 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
5126 // will return +0, so vmax can only be used for unsafe math or if one of
5127 // the operands is known to be nonzero.
5128 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
5130 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
5132 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
5138 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS);
5141 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
5142 DAGCombinerInfo &DCI) const {
5143 switch (N->getOpcode()) {
5145 case ISD::ADD: return PerformADDCombine(N, DCI);
5146 case ISD::SUB: return PerformSUBCombine(N, DCI);
5147 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
5148 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
5149 case ISD::AND: return PerformANDCombine(N, DCI);
5150 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
5151 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
5152 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI.DAG);
5153 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
5154 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI.DAG);
5155 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
5158 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
5159 case ISD::SIGN_EXTEND:
5160 case ISD::ZERO_EXTEND:
5161 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
5162 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
5167 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
5168 if (!Subtarget->allowsUnalignedMem())
5171 switch (VT.getSimpleVT().SimpleTy) {
5178 // FIXME: VLD1 etc with standard alignment is legal.
5182 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
5187 switch (VT.getSimpleVT().SimpleTy) {
5188 default: return false;
5203 if ((V & (Scale - 1)) != 0)
5206 return V == (V & ((1LL << 5) - 1));
5209 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
5210 const ARMSubtarget *Subtarget) {
5217 switch (VT.getSimpleVT().SimpleTy) {
5218 default: return false;
5223 // + imm12 or - imm8
5225 return V == (V & ((1LL << 8) - 1));
5226 return V == (V & ((1LL << 12) - 1));
5229 // Same as ARM mode. FIXME: NEON?
5230 if (!Subtarget->hasVFP2())
5235 return V == (V & ((1LL << 8) - 1));
5239 /// isLegalAddressImmediate - Return true if the integer value can be used
5240 /// as the offset of the target addressing mode for load / store of the
5242 static bool isLegalAddressImmediate(int64_t V, EVT VT,
5243 const ARMSubtarget *Subtarget) {
5250 if (Subtarget->isThumb1Only())
5251 return isLegalT1AddressImmediate(V, VT);
5252 else if (Subtarget->isThumb2())
5253 return isLegalT2AddressImmediate(V, VT, Subtarget);
5258 switch (VT.getSimpleVT().SimpleTy) {
5259 default: return false;
5264 return V == (V & ((1LL << 12) - 1));
5267 return V == (V & ((1LL << 8) - 1));
5270 if (!Subtarget->hasVFP2()) // FIXME: NEON?
5275 return V == (V & ((1LL << 8) - 1));
5279 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
5281 int Scale = AM.Scale;
5285 switch (VT.getSimpleVT().SimpleTy) {
5286 default: return false;
5295 return Scale == 2 || Scale == 4 || Scale == 8;
5298 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
5302 // Note, we allow "void" uses (basically, uses that aren't loads or
5303 // stores), because arm allows folding a scale into many arithmetic
5304 // operations. This should be made more precise and revisited later.
5306 // Allow r << imm, but the imm has to be a multiple of two.
5307 if (Scale & 1) return false;
5308 return isPowerOf2_32(Scale);
5312 /// isLegalAddressingMode - Return true if the addressing mode represented
5313 /// by AM is legal for this target, for a load/store of the specified type.
5314 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
5315 const Type *Ty) const {
5316 EVT VT = getValueType(Ty, true);
5317 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
5320 // Can never fold addr of global into load/store.
5325 case 0: // no scale reg, must be "r+i" or "r", or "i".
5328 if (Subtarget->isThumb1Only())
5332 // ARM doesn't support any R+R*scale+imm addr modes.
5339 if (Subtarget->isThumb2())
5340 return isLegalT2ScaledAddressingMode(AM, VT);
5342 int Scale = AM.Scale;
5343 switch (VT.getSimpleVT().SimpleTy) {
5344 default: return false;
5348 if (Scale < 0) Scale = -Scale;
5352 return isPowerOf2_32(Scale & ~1);
5356 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
5361 // Note, we allow "void" uses (basically, uses that aren't loads or
5362 // stores), because arm allows folding a scale into many arithmetic
5363 // operations. This should be made more precise and revisited later.
5365 // Allow r << imm, but the imm has to be a multiple of two.
5366 if (Scale & 1) return false;
5367 return isPowerOf2_32(Scale);
5374 /// isLegalICmpImmediate - Return true if the specified immediate is legal
5375 /// icmp immediate, that is the target has icmp instructions which can compare
5376 /// a register against the immediate without having to materialize the
5377 /// immediate into a register.
5378 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
5379 if (!Subtarget->isThumb())
5380 return ARM_AM::getSOImmVal(Imm) != -1;
5381 if (Subtarget->isThumb2())
5382 return ARM_AM::getT2SOImmVal(Imm) != -1;
5383 return Imm >= 0 && Imm <= 255;
5386 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
5387 bool isSEXTLoad, SDValue &Base,
5388 SDValue &Offset, bool &isInc,
5389 SelectionDAG &DAG) {
5390 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
5393 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
5395 Base = Ptr->getOperand(0);
5396 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
5397 int RHSC = (int)RHS->getZExtValue();
5398 if (RHSC < 0 && RHSC > -256) {
5399 assert(Ptr->getOpcode() == ISD::ADD);
5401 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
5405 isInc = (Ptr->getOpcode() == ISD::ADD);
5406 Offset = Ptr->getOperand(1);
5408 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
5410 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
5411 int RHSC = (int)RHS->getZExtValue();
5412 if (RHSC < 0 && RHSC > -0x1000) {
5413 assert(Ptr->getOpcode() == ISD::ADD);
5415 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
5416 Base = Ptr->getOperand(0);
5421 if (Ptr->getOpcode() == ISD::ADD) {
5423 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
5424 if (ShOpcVal != ARM_AM::no_shift) {
5425 Base = Ptr->getOperand(1);
5426 Offset = Ptr->getOperand(0);
5428 Base = Ptr->getOperand(0);
5429 Offset = Ptr->getOperand(1);
5434 isInc = (Ptr->getOpcode() == ISD::ADD);
5435 Base = Ptr->getOperand(0);
5436 Offset = Ptr->getOperand(1);
5440 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
5444 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
5445 bool isSEXTLoad, SDValue &Base,
5446 SDValue &Offset, bool &isInc,
5447 SelectionDAG &DAG) {
5448 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
5451 Base = Ptr->getOperand(0);
5452 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
5453 int RHSC = (int)RHS->getZExtValue();
5454 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
5455 assert(Ptr->getOpcode() == ISD::ADD);
5457 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
5459 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
5460 isInc = Ptr->getOpcode() == ISD::ADD;
5461 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
5469 /// getPreIndexedAddressParts - returns true by value, base pointer and
5470 /// offset pointer and addressing mode by reference if the node's address
5471 /// can be legally represented as pre-indexed load / store address.
5473 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
5475 ISD::MemIndexedMode &AM,
5476 SelectionDAG &DAG) const {
5477 if (Subtarget->isThumb1Only())
5482 bool isSEXTLoad = false;
5483 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5484 Ptr = LD->getBasePtr();
5485 VT = LD->getMemoryVT();
5486 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
5487 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5488 Ptr = ST->getBasePtr();
5489 VT = ST->getMemoryVT();
5494 bool isLegal = false;
5495 if (Subtarget->isThumb2())
5496 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
5497 Offset, isInc, DAG);
5499 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
5500 Offset, isInc, DAG);
5504 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
5508 /// getPostIndexedAddressParts - returns true by value, base pointer and
5509 /// offset pointer and addressing mode by reference if this node can be
5510 /// combined with a load / store to form a post-indexed load / store.
5511 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
5514 ISD::MemIndexedMode &AM,
5515 SelectionDAG &DAG) const {
5516 if (Subtarget->isThumb1Only())
5521 bool isSEXTLoad = false;
5522 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5523 VT = LD->getMemoryVT();
5524 Ptr = LD->getBasePtr();
5525 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
5526 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5527 VT = ST->getMemoryVT();
5528 Ptr = ST->getBasePtr();
5533 bool isLegal = false;
5534 if (Subtarget->isThumb2())
5535 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
5538 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
5544 // Swap base ptr and offset to catch more post-index load / store when
5545 // it's legal. In Thumb2 mode, offset must be an immediate.
5546 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
5547 !Subtarget->isThumb2())
5548 std::swap(Base, Offset);
5550 // Post-indexed load / store update the base pointer.
5555 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
5559 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
5563 const SelectionDAG &DAG,
5564 unsigned Depth) const {
5565 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
5566 switch (Op.getOpcode()) {
5568 case ARMISD::CMOV: {
5569 // Bits are known zero/one if known on the LHS and RHS.
5570 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
5571 if (KnownZero == 0 && KnownOne == 0) return;
5573 APInt KnownZeroRHS, KnownOneRHS;
5574 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
5575 KnownZeroRHS, KnownOneRHS, Depth+1);
5576 KnownZero &= KnownZeroRHS;
5577 KnownOne &= KnownOneRHS;
5583 //===----------------------------------------------------------------------===//
5584 // ARM Inline Assembly Support
5585 //===----------------------------------------------------------------------===//
5587 /// getConstraintType - Given a constraint letter, return the type of
5588 /// constraint it is for this target.
5589 ARMTargetLowering::ConstraintType
5590 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
5591 if (Constraint.size() == 1) {
5592 switch (Constraint[0]) {
5594 case 'l': return C_RegisterClass;
5595 case 'w': return C_RegisterClass;
5598 return TargetLowering::getConstraintType(Constraint);
5601 /// Examine constraint type and operand type and determine a weight value.
5602 /// This object must already have been set up with the operand type
5603 /// and the current alternative constraint selected.
5604 TargetLowering::ConstraintWeight
5605 ARMTargetLowering::getSingleConstraintMatchWeight(
5606 AsmOperandInfo &info, const char *constraint) const {
5607 ConstraintWeight weight = CW_Invalid;
5608 Value *CallOperandVal = info.CallOperandVal;
5609 // If we don't have a value, we can't do a match,
5610 // but allow it at the lowest weight.
5611 if (CallOperandVal == NULL)
5613 const Type *type = CallOperandVal->getType();
5614 // Look at the constraint type.
5615 switch (*constraint) {
5617 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
5620 if (type->isIntegerTy()) {
5621 if (Subtarget->isThumb())
5622 weight = CW_SpecificReg;
5624 weight = CW_Register;
5628 if (type->isFloatingPointTy())
5629 weight = CW_Register;
5635 std::pair<unsigned, const TargetRegisterClass*>
5636 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
5638 if (Constraint.size() == 1) {
5639 // GCC ARM Constraint Letters
5640 switch (Constraint[0]) {
5642 if (Subtarget->isThumb())
5643 return std::make_pair(0U, ARM::tGPRRegisterClass);
5645 return std::make_pair(0U, ARM::GPRRegisterClass);
5647 return std::make_pair(0U, ARM::GPRRegisterClass);
5650 return std::make_pair(0U, ARM::SPRRegisterClass);
5651 if (VT.getSizeInBits() == 64)
5652 return std::make_pair(0U, ARM::DPRRegisterClass);
5653 if (VT.getSizeInBits() == 128)
5654 return std::make_pair(0U, ARM::QPRRegisterClass);
5658 if (StringRef("{cc}").equals_lower(Constraint))
5659 return std::make_pair(unsigned(ARM::CPSR), ARM::CCRRegisterClass);
5661 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
5664 std::vector<unsigned> ARMTargetLowering::
5665 getRegClassForInlineAsmConstraint(const std::string &Constraint,
5667 if (Constraint.size() != 1)
5668 return std::vector<unsigned>();
5670 switch (Constraint[0]) { // GCC ARM Constraint Letters
5673 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
5674 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
5677 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
5678 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
5679 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
5680 ARM::R12, ARM::LR, 0);
5683 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
5684 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
5685 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
5686 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
5687 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
5688 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
5689 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
5690 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
5691 if (VT.getSizeInBits() == 64)
5692 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
5693 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
5694 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
5695 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
5696 if (VT.getSizeInBits() == 128)
5697 return make_vector<unsigned>(ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
5698 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 0);
5702 return std::vector<unsigned>();
5705 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
5706 /// vector. If it is invalid, don't add anything to Ops.
5707 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
5709 std::vector<SDValue>&Ops,
5710 SelectionDAG &DAG) const {
5711 SDValue Result(0, 0);
5713 switch (Constraint) {
5715 case 'I': case 'J': case 'K': case 'L':
5716 case 'M': case 'N': case 'O':
5717 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
5721 int64_t CVal64 = C->getSExtValue();
5722 int CVal = (int) CVal64;
5723 // None of these constraints allow values larger than 32 bits. Check
5724 // that the value fits in an int.
5728 switch (Constraint) {
5730 if (Subtarget->isThumb1Only()) {
5731 // This must be a constant between 0 and 255, for ADD
5733 if (CVal >= 0 && CVal <= 255)
5735 } else if (Subtarget->isThumb2()) {
5736 // A constant that can be used as an immediate value in a
5737 // data-processing instruction.
5738 if (ARM_AM::getT2SOImmVal(CVal) != -1)
5741 // A constant that can be used as an immediate value in a
5742 // data-processing instruction.
5743 if (ARM_AM::getSOImmVal(CVal) != -1)
5749 if (Subtarget->isThumb()) { // FIXME thumb2
5750 // This must be a constant between -255 and -1, for negated ADD
5751 // immediates. This can be used in GCC with an "n" modifier that
5752 // prints the negated value, for use with SUB instructions. It is
5753 // not useful otherwise but is implemented for compatibility.
5754 if (CVal >= -255 && CVal <= -1)
5757 // This must be a constant between -4095 and 4095. It is not clear
5758 // what this constraint is intended for. Implemented for
5759 // compatibility with GCC.
5760 if (CVal >= -4095 && CVal <= 4095)
5766 if (Subtarget->isThumb1Only()) {
5767 // A 32-bit value where only one byte has a nonzero value. Exclude
5768 // zero to match GCC. This constraint is used by GCC internally for
5769 // constants that can be loaded with a move/shift combination.
5770 // It is not useful otherwise but is implemented for compatibility.
5771 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
5773 } else if (Subtarget->isThumb2()) {
5774 // A constant whose bitwise inverse can be used as an immediate
5775 // value in a data-processing instruction. This can be used in GCC
5776 // with a "B" modifier that prints the inverted value, for use with
5777 // BIC and MVN instructions. It is not useful otherwise but is
5778 // implemented for compatibility.
5779 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
5782 // A constant whose bitwise inverse can be used as an immediate
5783 // value in a data-processing instruction. This can be used in GCC
5784 // with a "B" modifier that prints the inverted value, for use with
5785 // BIC and MVN instructions. It is not useful otherwise but is
5786 // implemented for compatibility.
5787 if (ARM_AM::getSOImmVal(~CVal) != -1)
5793 if (Subtarget->isThumb1Only()) {
5794 // This must be a constant between -7 and 7,
5795 // for 3-operand ADD/SUB immediate instructions.
5796 if (CVal >= -7 && CVal < 7)
5798 } else if (Subtarget->isThumb2()) {
5799 // A constant whose negation can be used as an immediate value in a
5800 // data-processing instruction. This can be used in GCC with an "n"
5801 // modifier that prints the negated value, for use with SUB
5802 // instructions. It is not useful otherwise but is implemented for
5804 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
5807 // A constant whose negation can be used as an immediate value in a
5808 // data-processing instruction. This can be used in GCC with an "n"
5809 // modifier that prints the negated value, for use with SUB
5810 // instructions. It is not useful otherwise but is implemented for
5812 if (ARM_AM::getSOImmVal(-CVal) != -1)
5818 if (Subtarget->isThumb()) { // FIXME thumb2
5819 // This must be a multiple of 4 between 0 and 1020, for
5820 // ADD sp + immediate.
5821 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
5824 // A power of two or a constant between 0 and 32. This is used in
5825 // GCC for the shift amount on shifted register operands, but it is
5826 // useful in general for any shift amounts.
5827 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
5833 if (Subtarget->isThumb()) { // FIXME thumb2
5834 // This must be a constant between 0 and 31, for shift amounts.
5835 if (CVal >= 0 && CVal <= 31)
5841 if (Subtarget->isThumb()) { // FIXME thumb2
5842 // This must be a multiple of 4 between -508 and 508, for
5843 // ADD/SUB sp = sp + immediate.
5844 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
5849 Result = DAG.getTargetConstant(CVal, Op.getValueType());
5853 if (Result.getNode()) {
5854 Ops.push_back(Result);
5857 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
5861 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
5862 // The ARM target isn't yet aware of offsets.
5866 int ARM::getVFPf32Imm(const APFloat &FPImm) {
5867 APInt Imm = FPImm.bitcastToAPInt();
5868 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
5869 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127
5870 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits
5872 // We can handle 4 bits of mantissa.
5873 // mantissa = (16+UInt(e:f:g:h))/16.
5874 if (Mantissa & 0x7ffff)
5877 if ((Mantissa & 0xf) != Mantissa)
5880 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
5881 if (Exp < -3 || Exp > 4)
5883 Exp = ((Exp+3) & 0x7) ^ 4;
5885 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
5888 int ARM::getVFPf64Imm(const APFloat &FPImm) {
5889 APInt Imm = FPImm.bitcastToAPInt();
5890 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
5891 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
5892 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffLL;
5894 // We can handle 4 bits of mantissa.
5895 // mantissa = (16+UInt(e:f:g:h))/16.
5896 if (Mantissa & 0xffffffffffffLL)
5899 if ((Mantissa & 0xf) != Mantissa)
5902 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
5903 if (Exp < -3 || Exp > 4)
5905 Exp = ((Exp+3) & 0x7) ^ 4;
5907 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
5910 bool ARM::isBitFieldInvertedMask(unsigned v) {
5911 if (v == 0xffffffff)
5913 // there can be 1's on either or both "outsides", all the "inside"
5915 unsigned int lsb = 0, msb = 31;
5916 while (v & (1 << msb)) --msb;
5917 while (v & (1 << lsb)) ++lsb;
5918 for (unsigned int i = lsb; i <= msb; ++i) {
5925 /// isFPImmLegal - Returns true if the target can instruction select the
5926 /// specified FP immediate natively. If false, the legalizer will
5927 /// materialize the FP immediate as a load from a constant pool.
5928 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
5929 if (!Subtarget->hasVFP3())
5932 return ARM::getVFPf32Imm(Imm) != -1;
5934 return ARM::getVFPf64Imm(Imm) != -1;
5938 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
5939 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
5940 /// specified in the intrinsic calls.
5941 bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
5943 unsigned Intrinsic) const {
5944 switch (Intrinsic) {
5945 case Intrinsic::arm_neon_vld1:
5946 case Intrinsic::arm_neon_vld2:
5947 case Intrinsic::arm_neon_vld3:
5948 case Intrinsic::arm_neon_vld4:
5949 case Intrinsic::arm_neon_vld2lane:
5950 case Intrinsic::arm_neon_vld3lane:
5951 case Intrinsic::arm_neon_vld4lane: {
5952 Info.opc = ISD::INTRINSIC_W_CHAIN;
5953 // Conservatively set memVT to the entire set of vectors loaded.
5954 uint64_t NumElts = getTargetData()->getTypeAllocSize(I.getType()) / 8;
5955 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
5956 Info.ptrVal = I.getArgOperand(0);
5958 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
5959 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
5960 Info.vol = false; // volatile loads with NEON intrinsics not supported
5961 Info.readMem = true;
5962 Info.writeMem = false;
5965 case Intrinsic::arm_neon_vst1:
5966 case Intrinsic::arm_neon_vst2:
5967 case Intrinsic::arm_neon_vst3:
5968 case Intrinsic::arm_neon_vst4:
5969 case Intrinsic::arm_neon_vst2lane:
5970 case Intrinsic::arm_neon_vst3lane:
5971 case Intrinsic::arm_neon_vst4lane: {
5972 Info.opc = ISD::INTRINSIC_VOID;
5973 // Conservatively set memVT to the entire set of vectors stored.
5974 unsigned NumElts = 0;
5975 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
5976 const Type *ArgTy = I.getArgOperand(ArgI)->getType();
5977 if (!ArgTy->isVectorTy())
5979 NumElts += getTargetData()->getTypeAllocSize(ArgTy) / 8;
5981 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
5982 Info.ptrVal = I.getArgOperand(0);
5984 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
5985 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
5986 Info.vol = false; // volatile stores with NEON intrinsics not supported
5987 Info.readMem = false;
5988 Info.writeMem = true;