1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "arm-isel"
17 #include "ARMCallingConv.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMISelLowering.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "ARMPerfectShuffle.h"
22 #include "ARMRegisterInfo.h"
23 #include "ARMSubtarget.h"
24 #include "ARMTargetMachine.h"
25 #include "ARMTargetObjectFile.h"
26 #include "MCTargetDesc/ARMAddressingModes.h"
27 #include "llvm/CallingConv.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Function.h"
30 #include "llvm/GlobalValue.h"
31 #include "llvm/Instruction.h"
32 #include "llvm/Instructions.h"
33 #include "llvm/Intrinsics.h"
34 #include "llvm/Type.h"
35 #include "llvm/CodeGen/CallingConvLower.h"
36 #include "llvm/CodeGen/IntrinsicLowering.h"
37 #include "llvm/CodeGen/MachineBasicBlock.h"
38 #include "llvm/CodeGen/MachineFrameInfo.h"
39 #include "llvm/CodeGen/MachineFunction.h"
40 #include "llvm/CodeGen/MachineInstrBuilder.h"
41 #include "llvm/CodeGen/MachineRegisterInfo.h"
42 #include "llvm/CodeGen/PseudoSourceValue.h"
43 #include "llvm/CodeGen/SelectionDAG.h"
44 #include "llvm/MC/MCSectionMachO.h"
45 #include "llvm/Target/TargetOptions.h"
46 #include "llvm/ADT/VectorExtras.h"
47 #include "llvm/ADT/StringExtras.h"
48 #include "llvm/ADT/Statistic.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/MathExtras.h"
52 #include "llvm/Support/raw_ostream.h"
56 STATISTIC(NumTailCalls, "Number of tail calls");
57 STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt");
59 // This option should go away when tail calls fully work.
61 EnableARMTailCalls("arm-tail-calls", cl::Hidden,
62 cl::desc("Generate tail calls (TEMPORARY OPTION)."),
66 EnableARMLongCalls("arm-long-calls", cl::Hidden,
67 cl::desc("Generate calls via indirect call instructions"),
71 ARMInterworking("arm-interworking", cl::Hidden,
72 cl::desc("Enable / disable ARM interworking (for debugging only)"),
76 class ARMCCState : public CCState {
78 ARMCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
79 const TargetMachine &TM, SmallVector<CCValAssign, 16> &locs,
80 LLVMContext &C, ParmContext PC)
81 : CCState(CC, isVarArg, MF, TM, locs, C) {
82 assert(((PC == Call) || (PC == Prologue)) &&
83 "ARMCCState users must specify whether their context is call"
84 "or prologue generation.");
90 // The APCS parameter registers.
91 static const unsigned GPRArgRegs[] = {
92 ARM::R0, ARM::R1, ARM::R2, ARM::R3
95 void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
96 EVT PromotedBitwiseVT) {
97 if (VT != PromotedLdStVT) {
98 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
99 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
100 PromotedLdStVT.getSimpleVT());
102 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
103 AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
104 PromotedLdStVT.getSimpleVT());
107 EVT ElemTy = VT.getVectorElementType();
108 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
109 setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
110 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
111 if (ElemTy != MVT::i32) {
112 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
113 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand);
114 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand);
115 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand);
117 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
118 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
119 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
120 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Legal);
121 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
122 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
123 if (VT.isInteger()) {
124 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
125 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
126 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
127 setLoadExtAction(ISD::SEXTLOAD, VT.getSimpleVT(), Expand);
128 setLoadExtAction(ISD::ZEXTLOAD, VT.getSimpleVT(), Expand);
129 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
130 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
131 setTruncStoreAction(VT.getSimpleVT(),
132 (MVT::SimpleValueType)InnerVT, Expand);
134 setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand);
136 // Promote all bit-wise operations.
137 if (VT.isInteger() && VT != PromotedBitwiseVT) {
138 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
139 AddPromotedToType (ISD::AND, VT.getSimpleVT(),
140 PromotedBitwiseVT.getSimpleVT());
141 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
142 AddPromotedToType (ISD::OR, VT.getSimpleVT(),
143 PromotedBitwiseVT.getSimpleVT());
144 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
145 AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
146 PromotedBitwiseVT.getSimpleVT());
149 // Neon does not support vector divide/remainder operations.
150 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
151 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
152 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand);
153 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
154 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
155 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
158 void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
159 addRegisterClass(VT, ARM::DPRRegisterClass);
160 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
163 void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
164 addRegisterClass(VT, ARM::QPRRegisterClass);
165 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
168 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
169 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
170 return new TargetLoweringObjectFileMachO();
172 return new ARMElfTargetObjectFile();
175 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
176 : TargetLowering(TM, createTLOF(TM)) {
177 Subtarget = &TM.getSubtarget<ARMSubtarget>();
178 RegInfo = TM.getRegisterInfo();
179 Itins = TM.getInstrItineraryData();
181 if (Subtarget->isTargetDarwin()) {
182 // Uses VFP for Thumb libfuncs if available.
183 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
184 // Single-precision floating-point arithmetic.
185 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
186 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
187 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
188 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
190 // Double-precision floating-point arithmetic.
191 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
192 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
193 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
194 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
196 // Single-precision comparisons.
197 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
198 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
199 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
200 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
201 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
202 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
203 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
204 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
206 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
207 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
208 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
209 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
210 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
211 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
212 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
213 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
215 // Double-precision comparisons.
216 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
217 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
218 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
219 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
220 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
221 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
222 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
223 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
225 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
226 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
227 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
228 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
229 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
230 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
231 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
232 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
234 // Floating-point to integer conversions.
235 // i64 conversions are done via library routines even when generating VFP
236 // instructions, so use the same ones.
237 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
238 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
239 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
240 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
242 // Conversions between floating types.
243 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
244 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
246 // Integer to floating-point conversions.
247 // i64 conversions are done via library routines even when generating VFP
248 // instructions, so use the same ones.
249 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
250 // e.g., __floatunsidf vs. __floatunssidfvfp.
251 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
252 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
253 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
254 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
258 // These libcalls are not available in 32-bit.
259 setLibcallName(RTLIB::SHL_I128, 0);
260 setLibcallName(RTLIB::SRL_I128, 0);
261 setLibcallName(RTLIB::SRA_I128, 0);
263 if (Subtarget->isAAPCS_ABI()) {
264 // Double-precision floating-point arithmetic helper functions
265 // RTABI chapter 4.1.2, Table 2
266 setLibcallName(RTLIB::ADD_F64, "__aeabi_dadd");
267 setLibcallName(RTLIB::DIV_F64, "__aeabi_ddiv");
268 setLibcallName(RTLIB::MUL_F64, "__aeabi_dmul");
269 setLibcallName(RTLIB::SUB_F64, "__aeabi_dsub");
270 setLibcallCallingConv(RTLIB::ADD_F64, CallingConv::ARM_AAPCS);
271 setLibcallCallingConv(RTLIB::DIV_F64, CallingConv::ARM_AAPCS);
272 setLibcallCallingConv(RTLIB::MUL_F64, CallingConv::ARM_AAPCS);
273 setLibcallCallingConv(RTLIB::SUB_F64, CallingConv::ARM_AAPCS);
275 // Double-precision floating-point comparison helper functions
276 // RTABI chapter 4.1.2, Table 3
277 setLibcallName(RTLIB::OEQ_F64, "__aeabi_dcmpeq");
278 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
279 setLibcallName(RTLIB::UNE_F64, "__aeabi_dcmpeq");
280 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETEQ);
281 setLibcallName(RTLIB::OLT_F64, "__aeabi_dcmplt");
282 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
283 setLibcallName(RTLIB::OLE_F64, "__aeabi_dcmple");
284 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
285 setLibcallName(RTLIB::OGE_F64, "__aeabi_dcmpge");
286 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
287 setLibcallName(RTLIB::OGT_F64, "__aeabi_dcmpgt");
288 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
289 setLibcallName(RTLIB::UO_F64, "__aeabi_dcmpun");
290 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
291 setLibcallName(RTLIB::O_F64, "__aeabi_dcmpun");
292 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
293 setLibcallCallingConv(RTLIB::OEQ_F64, CallingConv::ARM_AAPCS);
294 setLibcallCallingConv(RTLIB::UNE_F64, CallingConv::ARM_AAPCS);
295 setLibcallCallingConv(RTLIB::OLT_F64, CallingConv::ARM_AAPCS);
296 setLibcallCallingConv(RTLIB::OLE_F64, CallingConv::ARM_AAPCS);
297 setLibcallCallingConv(RTLIB::OGE_F64, CallingConv::ARM_AAPCS);
298 setLibcallCallingConv(RTLIB::OGT_F64, CallingConv::ARM_AAPCS);
299 setLibcallCallingConv(RTLIB::UO_F64, CallingConv::ARM_AAPCS);
300 setLibcallCallingConv(RTLIB::O_F64, CallingConv::ARM_AAPCS);
302 // Single-precision floating-point arithmetic helper functions
303 // RTABI chapter 4.1.2, Table 4
304 setLibcallName(RTLIB::ADD_F32, "__aeabi_fadd");
305 setLibcallName(RTLIB::DIV_F32, "__aeabi_fdiv");
306 setLibcallName(RTLIB::MUL_F32, "__aeabi_fmul");
307 setLibcallName(RTLIB::SUB_F32, "__aeabi_fsub");
308 setLibcallCallingConv(RTLIB::ADD_F32, CallingConv::ARM_AAPCS);
309 setLibcallCallingConv(RTLIB::DIV_F32, CallingConv::ARM_AAPCS);
310 setLibcallCallingConv(RTLIB::MUL_F32, CallingConv::ARM_AAPCS);
311 setLibcallCallingConv(RTLIB::SUB_F32, CallingConv::ARM_AAPCS);
313 // Single-precision floating-point comparison helper functions
314 // RTABI chapter 4.1.2, Table 5
315 setLibcallName(RTLIB::OEQ_F32, "__aeabi_fcmpeq");
316 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
317 setLibcallName(RTLIB::UNE_F32, "__aeabi_fcmpeq");
318 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETEQ);
319 setLibcallName(RTLIB::OLT_F32, "__aeabi_fcmplt");
320 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
321 setLibcallName(RTLIB::OLE_F32, "__aeabi_fcmple");
322 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
323 setLibcallName(RTLIB::OGE_F32, "__aeabi_fcmpge");
324 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
325 setLibcallName(RTLIB::OGT_F32, "__aeabi_fcmpgt");
326 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
327 setLibcallName(RTLIB::UO_F32, "__aeabi_fcmpun");
328 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
329 setLibcallName(RTLIB::O_F32, "__aeabi_fcmpun");
330 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
331 setLibcallCallingConv(RTLIB::OEQ_F32, CallingConv::ARM_AAPCS);
332 setLibcallCallingConv(RTLIB::UNE_F32, CallingConv::ARM_AAPCS);
333 setLibcallCallingConv(RTLIB::OLT_F32, CallingConv::ARM_AAPCS);
334 setLibcallCallingConv(RTLIB::OLE_F32, CallingConv::ARM_AAPCS);
335 setLibcallCallingConv(RTLIB::OGE_F32, CallingConv::ARM_AAPCS);
336 setLibcallCallingConv(RTLIB::OGT_F32, CallingConv::ARM_AAPCS);
337 setLibcallCallingConv(RTLIB::UO_F32, CallingConv::ARM_AAPCS);
338 setLibcallCallingConv(RTLIB::O_F32, CallingConv::ARM_AAPCS);
340 // Floating-point to integer conversions.
341 // RTABI chapter 4.1.2, Table 6
342 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz");
343 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz");
344 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz");
345 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz");
346 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz");
347 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz");
348 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz");
349 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz");
350 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I32, CallingConv::ARM_AAPCS);
351 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I32, CallingConv::ARM_AAPCS);
352 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I64, CallingConv::ARM_AAPCS);
353 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::ARM_AAPCS);
354 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I32, CallingConv::ARM_AAPCS);
355 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I32, CallingConv::ARM_AAPCS);
356 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I64, CallingConv::ARM_AAPCS);
357 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::ARM_AAPCS);
359 // Conversions between floating types.
360 // RTABI chapter 4.1.2, Table 7
361 setLibcallName(RTLIB::FPROUND_F64_F32, "__aeabi_d2f");
362 setLibcallName(RTLIB::FPEXT_F32_F64, "__aeabi_f2d");
363 setLibcallCallingConv(RTLIB::FPROUND_F64_F32, CallingConv::ARM_AAPCS);
364 setLibcallCallingConv(RTLIB::FPEXT_F32_F64, CallingConv::ARM_AAPCS);
366 // Integer to floating-point conversions.
367 // RTABI chapter 4.1.2, Table 8
368 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d");
369 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d");
370 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d");
371 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d");
372 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f");
373 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f");
374 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f");
375 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f");
376 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
377 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
378 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
379 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
380 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
381 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
382 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
383 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
385 // Long long helper functions
386 // RTABI chapter 4.2, Table 9
387 setLibcallName(RTLIB::MUL_I64, "__aeabi_lmul");
388 setLibcallName(RTLIB::SDIV_I64, "__aeabi_ldivmod");
389 setLibcallName(RTLIB::UDIV_I64, "__aeabi_uldivmod");
390 setLibcallName(RTLIB::SHL_I64, "__aeabi_llsl");
391 setLibcallName(RTLIB::SRL_I64, "__aeabi_llsr");
392 setLibcallName(RTLIB::SRA_I64, "__aeabi_lasr");
393 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::ARM_AAPCS);
394 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::ARM_AAPCS);
395 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::ARM_AAPCS);
396 setLibcallCallingConv(RTLIB::SHL_I64, CallingConv::ARM_AAPCS);
397 setLibcallCallingConv(RTLIB::SRL_I64, CallingConv::ARM_AAPCS);
398 setLibcallCallingConv(RTLIB::SRA_I64, CallingConv::ARM_AAPCS);
400 // Integer division functions
401 // RTABI chapter 4.3.1
402 setLibcallName(RTLIB::SDIV_I8, "__aeabi_idiv");
403 setLibcallName(RTLIB::SDIV_I16, "__aeabi_idiv");
404 setLibcallName(RTLIB::SDIV_I32, "__aeabi_idiv");
405 setLibcallName(RTLIB::UDIV_I8, "__aeabi_uidiv");
406 setLibcallName(RTLIB::UDIV_I16, "__aeabi_uidiv");
407 setLibcallName(RTLIB::UDIV_I32, "__aeabi_uidiv");
408 setLibcallCallingConv(RTLIB::SDIV_I8, CallingConv::ARM_AAPCS);
409 setLibcallCallingConv(RTLIB::SDIV_I16, CallingConv::ARM_AAPCS);
410 setLibcallCallingConv(RTLIB::SDIV_I32, CallingConv::ARM_AAPCS);
411 setLibcallCallingConv(RTLIB::UDIV_I8, CallingConv::ARM_AAPCS);
412 setLibcallCallingConv(RTLIB::UDIV_I16, CallingConv::ARM_AAPCS);
413 setLibcallCallingConv(RTLIB::UDIV_I32, CallingConv::ARM_AAPCS);
416 // RTABI chapter 4.3.4
417 setLibcallName(RTLIB::MEMCPY, "__aeabi_memcpy");
418 setLibcallName(RTLIB::MEMMOVE, "__aeabi_memmove");
419 setLibcallName(RTLIB::MEMSET, "__aeabi_memset");
422 if (Subtarget->isThumb1Only())
423 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
425 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
426 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
427 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
428 if (!Subtarget->isFPOnlySP())
429 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
431 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
434 if (Subtarget->hasNEON()) {
435 addDRTypeForNEON(MVT::v2f32);
436 addDRTypeForNEON(MVT::v8i8);
437 addDRTypeForNEON(MVT::v4i16);
438 addDRTypeForNEON(MVT::v2i32);
439 addDRTypeForNEON(MVT::v1i64);
441 addQRTypeForNEON(MVT::v4f32);
442 addQRTypeForNEON(MVT::v2f64);
443 addQRTypeForNEON(MVT::v16i8);
444 addQRTypeForNEON(MVT::v8i16);
445 addQRTypeForNEON(MVT::v4i32);
446 addQRTypeForNEON(MVT::v2i64);
448 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
449 // neither Neon nor VFP support any arithmetic operations on it.
450 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
451 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
452 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
453 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
454 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
455 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
456 setOperationAction(ISD::VSETCC, MVT::v2f64, Expand);
457 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
458 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
459 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
460 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
461 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
462 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
463 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
464 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
465 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
466 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
467 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
468 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
469 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
470 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
471 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
472 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
473 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
475 setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand);
477 // Neon does not support some operations on v1i64 and v2i64 types.
478 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
479 // Custom handling for some quad-vector types to detect VMULL.
480 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
481 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
482 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
483 // Custom handling for some vector types to avoid expensive expansions
484 setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
485 setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
486 setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
487 setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
488 setOperationAction(ISD::VSETCC, MVT::v1i64, Expand);
489 setOperationAction(ISD::VSETCC, MVT::v2i64, Expand);
490 // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
491 // a destination type that is wider than the source.
492 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
493 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
495 setTargetDAGCombine(ISD::INTRINSIC_VOID);
496 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
497 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
498 setTargetDAGCombine(ISD::SHL);
499 setTargetDAGCombine(ISD::SRL);
500 setTargetDAGCombine(ISD::SRA);
501 setTargetDAGCombine(ISD::SIGN_EXTEND);
502 setTargetDAGCombine(ISD::ZERO_EXTEND);
503 setTargetDAGCombine(ISD::ANY_EXTEND);
504 setTargetDAGCombine(ISD::SELECT_CC);
505 setTargetDAGCombine(ISD::BUILD_VECTOR);
506 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
507 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
508 setTargetDAGCombine(ISD::STORE);
509 setTargetDAGCombine(ISD::FP_TO_SINT);
510 setTargetDAGCombine(ISD::FP_TO_UINT);
511 setTargetDAGCombine(ISD::FDIV);
514 computeRegisterProperties();
516 // ARM does not have f32 extending load.
517 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
519 // ARM does not have i1 sign extending load.
520 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
522 // ARM supports all 4 flavors of integer indexed load / store.
523 if (!Subtarget->isThumb1Only()) {
524 for (unsigned im = (unsigned)ISD::PRE_INC;
525 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
526 setIndexedLoadAction(im, MVT::i1, Legal);
527 setIndexedLoadAction(im, MVT::i8, Legal);
528 setIndexedLoadAction(im, MVT::i16, Legal);
529 setIndexedLoadAction(im, MVT::i32, Legal);
530 setIndexedStoreAction(im, MVT::i1, Legal);
531 setIndexedStoreAction(im, MVT::i8, Legal);
532 setIndexedStoreAction(im, MVT::i16, Legal);
533 setIndexedStoreAction(im, MVT::i32, Legal);
537 // i64 operation support.
538 setOperationAction(ISD::MUL, MVT::i64, Expand);
539 setOperationAction(ISD::MULHU, MVT::i32, Expand);
540 if (Subtarget->isThumb1Only()) {
541 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
542 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
544 if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
545 || (Subtarget->isThumb2() && !Subtarget->hasThumb2DSP()))
546 setOperationAction(ISD::MULHS, MVT::i32, Expand);
548 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
549 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
550 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
551 setOperationAction(ISD::SRL, MVT::i64, Custom);
552 setOperationAction(ISD::SRA, MVT::i64, Custom);
554 // ARM does not have ROTL.
555 setOperationAction(ISD::ROTL, MVT::i32, Expand);
556 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
557 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
558 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
559 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
561 // Only ARMv6 has BSWAP.
562 if (!Subtarget->hasV6Ops())
563 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
565 // These are expanded into libcalls.
566 if (!Subtarget->hasDivide() || !Subtarget->isThumb2()) {
567 // v7M has a hardware divider
568 setOperationAction(ISD::SDIV, MVT::i32, Expand);
569 setOperationAction(ISD::UDIV, MVT::i32, Expand);
571 setOperationAction(ISD::SREM, MVT::i32, Expand);
572 setOperationAction(ISD::UREM, MVT::i32, Expand);
573 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
574 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
576 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
577 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
578 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
579 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
580 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
582 setOperationAction(ISD::TRAP, MVT::Other, Legal);
584 // Use the default implementation.
585 setOperationAction(ISD::VASTART, MVT::Other, Custom);
586 setOperationAction(ISD::VAARG, MVT::Other, Expand);
587 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
588 setOperationAction(ISD::VAEND, MVT::Other, Expand);
589 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
590 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
591 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
592 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
593 setExceptionPointerRegister(ARM::R0);
594 setExceptionSelectorRegister(ARM::R1);
596 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
597 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
598 // the default expansion.
599 if (Subtarget->hasDataBarrier() ||
600 (Subtarget->hasV6Ops() && !Subtarget->isThumb())) {
601 // membarrier needs custom lowering; the rest are legal and handled
603 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
604 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
605 // Automatically insert fences (dmb ist) around ATOMIC_SWAP etc.
606 setInsertFencesForAtomic(true);
608 // Set them all for expansion, which will force libcalls.
609 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
610 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand);
611 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
612 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
613 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
614 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
615 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
616 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
617 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
618 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
619 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
620 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
621 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
622 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
623 // Since the libcalls include locking, fold in the fences
624 setShouldFoldAtomicFences(true);
627 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
629 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
630 if (!Subtarget->hasV6Ops()) {
631 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
632 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
634 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
636 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
637 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
638 // iff target supports vfp2.
639 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
640 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
643 // We want to custom lower some of our intrinsics.
644 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
645 if (Subtarget->isTargetDarwin()) {
646 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
647 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
648 setOperationAction(ISD::EH_SJLJ_DISPATCHSETUP, MVT::Other, Custom);
649 setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
652 setOperationAction(ISD::SETCC, MVT::i32, Expand);
653 setOperationAction(ISD::SETCC, MVT::f32, Expand);
654 setOperationAction(ISD::SETCC, MVT::f64, Expand);
655 setOperationAction(ISD::SELECT, MVT::i32, Custom);
656 setOperationAction(ISD::SELECT, MVT::f32, Custom);
657 setOperationAction(ISD::SELECT, MVT::f64, Custom);
658 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
659 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
660 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
662 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
663 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
664 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
665 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
666 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
668 // We don't support sin/cos/fmod/copysign/pow
669 setOperationAction(ISD::FSIN, MVT::f64, Expand);
670 setOperationAction(ISD::FSIN, MVT::f32, Expand);
671 setOperationAction(ISD::FCOS, MVT::f32, Expand);
672 setOperationAction(ISD::FCOS, MVT::f64, Expand);
673 setOperationAction(ISD::FREM, MVT::f64, Expand);
674 setOperationAction(ISD::FREM, MVT::f32, Expand);
675 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
676 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
677 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
679 setOperationAction(ISD::FPOW, MVT::f64, Expand);
680 setOperationAction(ISD::FPOW, MVT::f32, Expand);
682 setOperationAction(ISD::FMA, MVT::f64, Expand);
683 setOperationAction(ISD::FMA, MVT::f32, Expand);
685 // Various VFP goodness
686 if (!UseSoftFloat && !Subtarget->isThumb1Only()) {
687 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
688 if (Subtarget->hasVFP2()) {
689 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
690 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
691 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
692 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
694 // Special handling for half-precision FP.
695 if (!Subtarget->hasFP16()) {
696 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
697 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand);
701 // We have target-specific dag combine patterns for the following nodes:
702 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
703 setTargetDAGCombine(ISD::ADD);
704 setTargetDAGCombine(ISD::SUB);
705 setTargetDAGCombine(ISD::MUL);
707 if (Subtarget->hasV6T2Ops() || Subtarget->hasNEON())
708 setTargetDAGCombine(ISD::OR);
709 if (Subtarget->hasNEON())
710 setTargetDAGCombine(ISD::AND);
712 setStackPointerRegisterToSaveRestore(ARM::SP);
714 if (UseSoftFloat || Subtarget->isThumb1Only() || !Subtarget->hasVFP2())
715 setSchedulingPreference(Sched::RegPressure);
717 setSchedulingPreference(Sched::Hybrid);
719 //// temporary - rewrite interface to use type
720 maxStoresPerMemcpy = maxStoresPerMemcpyOptSize = 1;
722 // On ARM arguments smaller than 4 bytes are extended, so all arguments
723 // are at least 4 bytes aligned.
724 setMinStackArgumentAlignment(4);
726 benefitFromCodePlacementOpt = true;
728 setMinFunctionAlignment(Subtarget->isThumb() ? 1 : 2);
731 // FIXME: It might make sense to define the representative register class as the
732 // nearest super-register that has a non-null superset. For example, DPR_VFP2 is
733 // a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
734 // SPR's representative would be DPR_VFP2. This should work well if register
735 // pressure tracking were modified such that a register use would increment the
736 // pressure of the register class's representative and all of it's super
737 // classes' representatives transitively. We have not implemented this because
738 // of the difficulty prior to coalescing of modeling operand register classes
739 // due to the common occurrence of cross class copies and subregister insertions
741 std::pair<const TargetRegisterClass*, uint8_t>
742 ARMTargetLowering::findRepresentativeClass(EVT VT) const{
743 const TargetRegisterClass *RRC = 0;
745 switch (VT.getSimpleVT().SimpleTy) {
747 return TargetLowering::findRepresentativeClass(VT);
748 // Use DPR as representative register class for all floating point
749 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
750 // the cost is 1 for both f32 and f64.
751 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
752 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
753 RRC = ARM::DPRRegisterClass;
754 // When NEON is used for SP, only half of the register file is available
755 // because operations that define both SP and DP results will be constrained
756 // to the VFP2 class (D0-D15). We currently model this constraint prior to
757 // coalescing by double-counting the SP regs. See the FIXME above.
758 if (Subtarget->useNEONForSinglePrecisionFP())
761 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
762 case MVT::v4f32: case MVT::v2f64:
763 RRC = ARM::DPRRegisterClass;
767 RRC = ARM::DPRRegisterClass;
771 RRC = ARM::DPRRegisterClass;
775 return std::make_pair(RRC, Cost);
778 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
781 case ARMISD::Wrapper: return "ARMISD::Wrapper";
782 case ARMISD::WrapperDYN: return "ARMISD::WrapperDYN";
783 case ARMISD::WrapperPIC: return "ARMISD::WrapperPIC";
784 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
785 case ARMISD::CALL: return "ARMISD::CALL";
786 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
787 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
788 case ARMISD::tCALL: return "ARMISD::tCALL";
789 case ARMISD::BRCOND: return "ARMISD::BRCOND";
790 case ARMISD::BR_JT: return "ARMISD::BR_JT";
791 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
792 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
793 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
794 case ARMISD::CMP: return "ARMISD::CMP";
795 case ARMISD::CMPZ: return "ARMISD::CMPZ";
796 case ARMISD::CMPFP: return "ARMISD::CMPFP";
797 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
798 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
799 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
800 case ARMISD::CMOV: return "ARMISD::CMOV";
802 case ARMISD::RBIT: return "ARMISD::RBIT";
804 case ARMISD::FTOSI: return "ARMISD::FTOSI";
805 case ARMISD::FTOUI: return "ARMISD::FTOUI";
806 case ARMISD::SITOF: return "ARMISD::SITOF";
807 case ARMISD::UITOF: return "ARMISD::UITOF";
809 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
810 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
811 case ARMISD::RRX: return "ARMISD::RRX";
813 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
814 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
816 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
817 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
818 case ARMISD::EH_SJLJ_DISPATCHSETUP:return "ARMISD::EH_SJLJ_DISPATCHSETUP";
820 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
822 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
824 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
826 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER";
827 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
829 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
831 case ARMISD::VCEQ: return "ARMISD::VCEQ";
832 case ARMISD::VCEQZ: return "ARMISD::VCEQZ";
833 case ARMISD::VCGE: return "ARMISD::VCGE";
834 case ARMISD::VCGEZ: return "ARMISD::VCGEZ";
835 case ARMISD::VCLEZ: return "ARMISD::VCLEZ";
836 case ARMISD::VCGEU: return "ARMISD::VCGEU";
837 case ARMISD::VCGT: return "ARMISD::VCGT";
838 case ARMISD::VCGTZ: return "ARMISD::VCGTZ";
839 case ARMISD::VCLTZ: return "ARMISD::VCLTZ";
840 case ARMISD::VCGTU: return "ARMISD::VCGTU";
841 case ARMISD::VTST: return "ARMISD::VTST";
843 case ARMISD::VSHL: return "ARMISD::VSHL";
844 case ARMISD::VSHRs: return "ARMISD::VSHRs";
845 case ARMISD::VSHRu: return "ARMISD::VSHRu";
846 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
847 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
848 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
849 case ARMISD::VSHRN: return "ARMISD::VSHRN";
850 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
851 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
852 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
853 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
854 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
855 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
856 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
857 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
858 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
859 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
860 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
861 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
862 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
863 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
864 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
865 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
866 case ARMISD::VDUP: return "ARMISD::VDUP";
867 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
868 case ARMISD::VEXT: return "ARMISD::VEXT";
869 case ARMISD::VREV64: return "ARMISD::VREV64";
870 case ARMISD::VREV32: return "ARMISD::VREV32";
871 case ARMISD::VREV16: return "ARMISD::VREV16";
872 case ARMISD::VZIP: return "ARMISD::VZIP";
873 case ARMISD::VUZP: return "ARMISD::VUZP";
874 case ARMISD::VTRN: return "ARMISD::VTRN";
875 case ARMISD::VTBL1: return "ARMISD::VTBL1";
876 case ARMISD::VTBL2: return "ARMISD::VTBL2";
877 case ARMISD::VMULLs: return "ARMISD::VMULLs";
878 case ARMISD::VMULLu: return "ARMISD::VMULLu";
879 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
880 case ARMISD::FMAX: return "ARMISD::FMAX";
881 case ARMISD::FMIN: return "ARMISD::FMIN";
882 case ARMISD::BFI: return "ARMISD::BFI";
883 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
884 case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
885 case ARMISD::VBSL: return "ARMISD::VBSL";
886 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
887 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
888 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
889 case ARMISD::VLD1_UPD: return "ARMISD::VLD1_UPD";
890 case ARMISD::VLD2_UPD: return "ARMISD::VLD2_UPD";
891 case ARMISD::VLD3_UPD: return "ARMISD::VLD3_UPD";
892 case ARMISD::VLD4_UPD: return "ARMISD::VLD4_UPD";
893 case ARMISD::VLD2LN_UPD: return "ARMISD::VLD2LN_UPD";
894 case ARMISD::VLD3LN_UPD: return "ARMISD::VLD3LN_UPD";
895 case ARMISD::VLD4LN_UPD: return "ARMISD::VLD4LN_UPD";
896 case ARMISD::VLD2DUP_UPD: return "ARMISD::VLD2DUP_UPD";
897 case ARMISD::VLD3DUP_UPD: return "ARMISD::VLD3DUP_UPD";
898 case ARMISD::VLD4DUP_UPD: return "ARMISD::VLD4DUP_UPD";
899 case ARMISD::VST1_UPD: return "ARMISD::VST1_UPD";
900 case ARMISD::VST2_UPD: return "ARMISD::VST2_UPD";
901 case ARMISD::VST3_UPD: return "ARMISD::VST3_UPD";
902 case ARMISD::VST4_UPD: return "ARMISD::VST4_UPD";
903 case ARMISD::VST2LN_UPD: return "ARMISD::VST2LN_UPD";
904 case ARMISD::VST3LN_UPD: return "ARMISD::VST3LN_UPD";
905 case ARMISD::VST4LN_UPD: return "ARMISD::VST4LN_UPD";
909 /// getRegClassFor - Return the register class that should be used for the
910 /// specified value type.
911 TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const {
912 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
913 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
914 // load / store 4 to 8 consecutive D registers.
915 if (Subtarget->hasNEON()) {
916 if (VT == MVT::v4i64)
917 return ARM::QQPRRegisterClass;
918 else if (VT == MVT::v8i64)
919 return ARM::QQQQPRRegisterClass;
921 return TargetLowering::getRegClassFor(VT);
924 // Create a fast isel object.
926 ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
927 return ARM::createFastISel(funcInfo);
930 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
931 /// be used for loads / stores from the global.
932 unsigned ARMTargetLowering::getMaximalGlobalOffset() const {
933 return (Subtarget->isThumb1Only() ? 127 : 4095);
936 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
937 unsigned NumVals = N->getNumValues();
939 return Sched::RegPressure;
941 for (unsigned i = 0; i != NumVals; ++i) {
942 EVT VT = N->getValueType(i);
943 if (VT == MVT::Glue || VT == MVT::Other)
945 if (VT.isFloatingPoint() || VT.isVector())
946 return Sched::Latency;
949 if (!N->isMachineOpcode())
950 return Sched::RegPressure;
952 // Load are scheduled for latency even if there instruction itinerary
954 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
955 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
957 if (MCID.getNumDefs() == 0)
958 return Sched::RegPressure;
959 if (!Itins->isEmpty() &&
960 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
961 return Sched::Latency;
963 return Sched::RegPressure;
966 //===----------------------------------------------------------------------===//
968 //===----------------------------------------------------------------------===//
970 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
971 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
973 default: llvm_unreachable("Unknown condition code!");
974 case ISD::SETNE: return ARMCC::NE;
975 case ISD::SETEQ: return ARMCC::EQ;
976 case ISD::SETGT: return ARMCC::GT;
977 case ISD::SETGE: return ARMCC::GE;
978 case ISD::SETLT: return ARMCC::LT;
979 case ISD::SETLE: return ARMCC::LE;
980 case ISD::SETUGT: return ARMCC::HI;
981 case ISD::SETUGE: return ARMCC::HS;
982 case ISD::SETULT: return ARMCC::LO;
983 case ISD::SETULE: return ARMCC::LS;
987 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
988 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
989 ARMCC::CondCodes &CondCode2) {
990 CondCode2 = ARMCC::AL;
992 default: llvm_unreachable("Unknown FP condition!");
994 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
996 case ISD::SETOGT: CondCode = ARMCC::GT; break;
998 case ISD::SETOGE: CondCode = ARMCC::GE; break;
999 case ISD::SETOLT: CondCode = ARMCC::MI; break;
1000 case ISD::SETOLE: CondCode = ARMCC::LS; break;
1001 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
1002 case ISD::SETO: CondCode = ARMCC::VC; break;
1003 case ISD::SETUO: CondCode = ARMCC::VS; break;
1004 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
1005 case ISD::SETUGT: CondCode = ARMCC::HI; break;
1006 case ISD::SETUGE: CondCode = ARMCC::PL; break;
1008 case ISD::SETULT: CondCode = ARMCC::LT; break;
1010 case ISD::SETULE: CondCode = ARMCC::LE; break;
1012 case ISD::SETUNE: CondCode = ARMCC::NE; break;
1016 //===----------------------------------------------------------------------===//
1017 // Calling Convention Implementation
1018 //===----------------------------------------------------------------------===//
1020 #include "ARMGenCallingConv.inc"
1022 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1023 /// given CallingConvention value.
1024 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
1026 bool isVarArg) const {
1029 llvm_unreachable("Unsupported calling convention");
1030 case CallingConv::Fast:
1031 if (Subtarget->hasVFP2() && !isVarArg) {
1032 if (!Subtarget->isAAPCS_ABI())
1033 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1034 // For AAPCS ABI targets, just use VFP variant of the calling convention.
1035 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1038 case CallingConv::C: {
1039 // Use target triple & subtarget features to do actual dispatch.
1040 if (!Subtarget->isAAPCS_ABI())
1041 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1042 else if (Subtarget->hasVFP2() &&
1043 FloatABIType == FloatABI::Hard && !isVarArg)
1044 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1045 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1047 case CallingConv::ARM_AAPCS_VFP:
1048 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1049 case CallingConv::ARM_AAPCS:
1050 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1051 case CallingConv::ARM_APCS:
1052 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1056 /// LowerCallResult - Lower the result values of a call into the
1057 /// appropriate copies out of appropriate physical registers.
1059 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1060 CallingConv::ID CallConv, bool isVarArg,
1061 const SmallVectorImpl<ISD::InputArg> &Ins,
1062 DebugLoc dl, SelectionDAG &DAG,
1063 SmallVectorImpl<SDValue> &InVals) const {
1065 // Assign locations to each value returned by this call.
1066 SmallVector<CCValAssign, 16> RVLocs;
1067 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1068 getTargetMachine(), RVLocs, *DAG.getContext(), Call);
1069 CCInfo.AnalyzeCallResult(Ins,
1070 CCAssignFnForNode(CallConv, /* Return*/ true,
1073 // Copy all of the result registers out of their specified physreg.
1074 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1075 CCValAssign VA = RVLocs[i];
1078 if (VA.needsCustom()) {
1079 // Handle f64 or half of a v2f64.
1080 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1082 Chain = Lo.getValue(1);
1083 InFlag = Lo.getValue(2);
1084 VA = RVLocs[++i]; // skip ahead to next loc
1085 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1087 Chain = Hi.getValue(1);
1088 InFlag = Hi.getValue(2);
1089 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1091 if (VA.getLocVT() == MVT::v2f64) {
1092 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1093 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1094 DAG.getConstant(0, MVT::i32));
1096 VA = RVLocs[++i]; // skip ahead to next loc
1097 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1098 Chain = Lo.getValue(1);
1099 InFlag = Lo.getValue(2);
1100 VA = RVLocs[++i]; // skip ahead to next loc
1101 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1102 Chain = Hi.getValue(1);
1103 InFlag = Hi.getValue(2);
1104 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1105 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1106 DAG.getConstant(1, MVT::i32));
1109 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1111 Chain = Val.getValue(1);
1112 InFlag = Val.getValue(2);
1115 switch (VA.getLocInfo()) {
1116 default: llvm_unreachable("Unknown loc info!");
1117 case CCValAssign::Full: break;
1118 case CCValAssign::BCvt:
1119 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1123 InVals.push_back(Val);
1129 /// LowerMemOpCallTo - Store the argument to the stack.
1131 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
1132 SDValue StackPtr, SDValue Arg,
1133 DebugLoc dl, SelectionDAG &DAG,
1134 const CCValAssign &VA,
1135 ISD::ArgFlagsTy Flags) const {
1136 unsigned LocMemOffset = VA.getLocMemOffset();
1137 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1138 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1139 return DAG.getStore(Chain, dl, Arg, PtrOff,
1140 MachinePointerInfo::getStack(LocMemOffset),
1144 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
1145 SDValue Chain, SDValue &Arg,
1146 RegsToPassVector &RegsToPass,
1147 CCValAssign &VA, CCValAssign &NextVA,
1149 SmallVector<SDValue, 8> &MemOpChains,
1150 ISD::ArgFlagsTy Flags) const {
1152 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1153 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1154 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
1156 if (NextVA.isRegLoc())
1157 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
1159 assert(NextVA.isMemLoc());
1160 if (StackPtr.getNode() == 0)
1161 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1163 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
1169 /// LowerCall - Lowering a call into a callseq_start <-
1170 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1173 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1174 CallingConv::ID CallConv, bool isVarArg,
1176 const SmallVectorImpl<ISD::OutputArg> &Outs,
1177 const SmallVectorImpl<SDValue> &OutVals,
1178 const SmallVectorImpl<ISD::InputArg> &Ins,
1179 DebugLoc dl, SelectionDAG &DAG,
1180 SmallVectorImpl<SDValue> &InVals) const {
1181 MachineFunction &MF = DAG.getMachineFunction();
1182 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1183 bool IsSibCall = false;
1184 // Temporarily disable tail calls so things don't break.
1185 if (!EnableARMTailCalls)
1188 // Check if it's really possible to do a tail call.
1189 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1190 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1191 Outs, OutVals, Ins, DAG);
1192 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1193 // detected sibcalls.
1200 // Analyze operands of the call, assigning locations to each operand.
1201 SmallVector<CCValAssign, 16> ArgLocs;
1202 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1203 getTargetMachine(), ArgLocs, *DAG.getContext(), Call);
1204 CCInfo.AnalyzeCallOperands(Outs,
1205 CCAssignFnForNode(CallConv, /* Return*/ false,
1208 // Get a count of how many bytes are to be pushed on the stack.
1209 unsigned NumBytes = CCInfo.getNextStackOffset();
1211 // For tail calls, memory operands are available in our caller's stack.
1215 // Adjust the stack pointer for the new arguments...
1216 // These operations are automatically eliminated by the prolog/epilog pass
1218 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1220 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1222 RegsToPassVector RegsToPass;
1223 SmallVector<SDValue, 8> MemOpChains;
1225 // Walk the register/memloc assignments, inserting copies/loads. In the case
1226 // of tail call optimization, arguments are handled later.
1227 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1229 ++i, ++realArgIdx) {
1230 CCValAssign &VA = ArgLocs[i];
1231 SDValue Arg = OutVals[realArgIdx];
1232 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1233 bool isByVal = Flags.isByVal();
1235 // Promote the value if needed.
1236 switch (VA.getLocInfo()) {
1237 default: llvm_unreachable("Unknown loc info!");
1238 case CCValAssign::Full: break;
1239 case CCValAssign::SExt:
1240 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1242 case CCValAssign::ZExt:
1243 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1245 case CCValAssign::AExt:
1246 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1248 case CCValAssign::BCvt:
1249 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1253 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1254 if (VA.needsCustom()) {
1255 if (VA.getLocVT() == MVT::v2f64) {
1256 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1257 DAG.getConstant(0, MVT::i32));
1258 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1259 DAG.getConstant(1, MVT::i32));
1261 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1262 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1264 VA = ArgLocs[++i]; // skip ahead to next loc
1265 if (VA.isRegLoc()) {
1266 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1267 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1269 assert(VA.isMemLoc());
1271 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1272 dl, DAG, VA, Flags));
1275 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1276 StackPtr, MemOpChains, Flags);
1278 } else if (VA.isRegLoc()) {
1279 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1280 } else if (isByVal) {
1281 assert(VA.isMemLoc());
1282 unsigned offset = 0;
1284 // True if this byval aggregate will be split between registers
1286 if (CCInfo.isFirstByValRegValid()) {
1287 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1289 for (i = 0, j = CCInfo.getFirstByValReg(); j < ARM::R4; i++, j++) {
1290 SDValue Const = DAG.getConstant(4*i, MVT::i32);
1291 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
1292 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
1293 MachinePointerInfo(),
1295 MemOpChains.push_back(Load.getValue(1));
1296 RegsToPass.push_back(std::make_pair(j, Load));
1298 offset = ARM::R4 - CCInfo.getFirstByValReg();
1299 CCInfo.clearFirstByValReg();
1302 unsigned LocMemOffset = VA.getLocMemOffset();
1303 SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset);
1304 SDValue Dst = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr,
1306 SDValue SrcOffset = DAG.getIntPtrConstant(4*offset);
1307 SDValue Src = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg, SrcOffset);
1308 SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset,
1310 MemOpChains.push_back(DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode,
1311 Flags.getByValAlign(),
1312 /*isVolatile=*/false,
1313 /*AlwaysInline=*/false,
1314 MachinePointerInfo(0),
1315 MachinePointerInfo(0)));
1317 } else if (!IsSibCall) {
1318 assert(VA.isMemLoc());
1320 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1321 dl, DAG, VA, Flags));
1325 if (!MemOpChains.empty())
1326 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1327 &MemOpChains[0], MemOpChains.size());
1329 // Build a sequence of copy-to-reg nodes chained together with token chain
1330 // and flag operands which copy the outgoing args into the appropriate regs.
1332 // Tail call byval lowering might overwrite argument registers so in case of
1333 // tail call optimization the copies to registers are lowered later.
1335 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1336 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1337 RegsToPass[i].second, InFlag);
1338 InFlag = Chain.getValue(1);
1341 // For tail calls lower the arguments to the 'real' stack slot.
1343 // Force all the incoming stack arguments to be loaded from the stack
1344 // before any new outgoing arguments are stored to the stack, because the
1345 // outgoing stack slots may alias the incoming argument stack slots, and
1346 // the alias isn't otherwise explicit. This is slightly more conservative
1347 // than necessary, because it means that each store effectively depends
1348 // on every argument instead of just those arguments it would clobber.
1350 // Do not flag preceding copytoreg stuff together with the following stuff.
1352 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1353 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1354 RegsToPass[i].second, InFlag);
1355 InFlag = Chain.getValue(1);
1360 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1361 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1362 // node so that legalize doesn't hack it.
1363 bool isDirect = false;
1364 bool isARMFunc = false;
1365 bool isLocalARMFunc = false;
1366 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1368 if (EnableARMLongCalls) {
1369 assert (getTargetMachine().getRelocationModel() == Reloc::Static
1370 && "long-calls with non-static relocation model!");
1371 // Handle a global address or an external symbol. If it's not one of
1372 // those, the target's already in a register, so we don't need to do
1374 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1375 const GlobalValue *GV = G->getGlobal();
1376 // Create a constant pool entry for the callee address
1377 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1378 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1381 // Get the address of the callee into a register
1382 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1383 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1384 Callee = DAG.getLoad(getPointerTy(), dl,
1385 DAG.getEntryNode(), CPAddr,
1386 MachinePointerInfo::getConstantPool(),
1388 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1389 const char *Sym = S->getSymbol();
1391 // Create a constant pool entry for the callee address
1392 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1393 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1394 Sym, ARMPCLabelIndex, 0);
1395 // Get the address of the callee into a register
1396 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1397 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1398 Callee = DAG.getLoad(getPointerTy(), dl,
1399 DAG.getEntryNode(), CPAddr,
1400 MachinePointerInfo::getConstantPool(),
1403 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1404 const GlobalValue *GV = G->getGlobal();
1406 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1407 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
1408 getTargetMachine().getRelocationModel() != Reloc::Static;
1409 isARMFunc = !Subtarget->isThumb() || isStub;
1410 // ARM call to a local ARM function is predicable.
1411 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
1412 // tBX takes a register source operand.
1413 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1414 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1415 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1418 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1419 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1420 Callee = DAG.getLoad(getPointerTy(), dl,
1421 DAG.getEntryNode(), CPAddr,
1422 MachinePointerInfo::getConstantPool(),
1424 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1425 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1426 getPointerTy(), Callee, PICLabel);
1428 // On ELF targets for PIC code, direct calls should go through the PLT
1429 unsigned OpFlags = 0;
1430 if (Subtarget->isTargetELF() &&
1431 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1432 OpFlags = ARMII::MO_PLT;
1433 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
1435 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1437 bool isStub = Subtarget->isTargetDarwin() &&
1438 getTargetMachine().getRelocationModel() != Reloc::Static;
1439 isARMFunc = !Subtarget->isThumb() || isStub;
1440 // tBX takes a register source operand.
1441 const char *Sym = S->getSymbol();
1442 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1443 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1444 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1445 Sym, ARMPCLabelIndex, 4);
1446 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1447 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1448 Callee = DAG.getLoad(getPointerTy(), dl,
1449 DAG.getEntryNode(), CPAddr,
1450 MachinePointerInfo::getConstantPool(),
1452 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1453 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1454 getPointerTy(), Callee, PICLabel);
1456 unsigned OpFlags = 0;
1457 // On ELF targets for PIC code, direct calls should go through the PLT
1458 if (Subtarget->isTargetELF() &&
1459 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1460 OpFlags = ARMII::MO_PLT;
1461 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags);
1465 // FIXME: handle tail calls differently.
1467 if (Subtarget->isThumb()) {
1468 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1469 CallOpc = ARMISD::CALL_NOLINK;
1471 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1473 CallOpc = (isDirect || Subtarget->hasV5TOps())
1474 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
1475 : ARMISD::CALL_NOLINK;
1478 std::vector<SDValue> Ops;
1479 Ops.push_back(Chain);
1480 Ops.push_back(Callee);
1482 // Add argument registers to the end of the list so that they are known live
1484 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1485 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1486 RegsToPass[i].second.getValueType()));
1488 if (InFlag.getNode())
1489 Ops.push_back(InFlag);
1491 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1493 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
1495 // Returns a chain and a flag for retval copy to use.
1496 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
1497 InFlag = Chain.getValue(1);
1499 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1500 DAG.getIntPtrConstant(0, true), InFlag);
1502 InFlag = Chain.getValue(1);
1504 // Handle result values, copying them out of physregs into vregs that we
1506 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1510 /// HandleByVal - Every parameter *after* a byval parameter is passed
1511 /// on the stack. Remember the next parameter register to allocate,
1512 /// and then confiscate the rest of the parameter registers to insure
1515 llvm::ARMTargetLowering::HandleByVal(CCState *State, unsigned &size) const {
1516 unsigned reg = State->AllocateReg(GPRArgRegs, 4);
1517 assert((State->getCallOrPrologue() == Prologue ||
1518 State->getCallOrPrologue() == Call) &&
1519 "unhandled ParmContext");
1520 if ((!State->isFirstByValRegValid()) &&
1521 (ARM::R0 <= reg) && (reg <= ARM::R3)) {
1522 State->setFirstByValReg(reg);
1523 // At a call site, a byval parameter that is split between
1524 // registers and memory needs its size truncated here. In a
1525 // function prologue, such byval parameters are reassembled in
1526 // memory, and are not truncated.
1527 if (State->getCallOrPrologue() == Call) {
1528 unsigned excess = 4 * (ARM::R4 - reg);
1529 assert(size >= excess && "expected larger existing stack allocation");
1533 // Confiscate any remaining parameter registers to preclude their
1534 // assignment to subsequent parameters.
1535 while (State->AllocateReg(GPRArgRegs, 4))
1539 /// MatchingStackOffset - Return true if the given stack call argument is
1540 /// already available in the same position (relatively) of the caller's
1541 /// incoming argument stack.
1543 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1544 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1545 const ARMInstrInfo *TII) {
1546 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
1548 if (Arg.getOpcode() == ISD::CopyFromReg) {
1549 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
1550 if (!TargetRegisterInfo::isVirtualRegister(VR))
1552 MachineInstr *Def = MRI->getVRegDef(VR);
1555 if (!Flags.isByVal()) {
1556 if (!TII->isLoadFromStackSlot(Def, FI))
1561 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
1562 if (Flags.isByVal())
1563 // ByVal argument is passed in as a pointer but it's now being
1564 // dereferenced. e.g.
1565 // define @foo(%struct.X* %A) {
1566 // tail call @bar(%struct.X* byval %A)
1569 SDValue Ptr = Ld->getBasePtr();
1570 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
1573 FI = FINode->getIndex();
1577 assert(FI != INT_MAX);
1578 if (!MFI->isFixedObjectIndex(FI))
1580 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
1583 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1584 /// for tail call optimization. Targets which want to do tail call
1585 /// optimization should implement this function.
1587 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1588 CallingConv::ID CalleeCC,
1590 bool isCalleeStructRet,
1591 bool isCallerStructRet,
1592 const SmallVectorImpl<ISD::OutputArg> &Outs,
1593 const SmallVectorImpl<SDValue> &OutVals,
1594 const SmallVectorImpl<ISD::InputArg> &Ins,
1595 SelectionDAG& DAG) const {
1596 const Function *CallerF = DAG.getMachineFunction().getFunction();
1597 CallingConv::ID CallerCC = CallerF->getCallingConv();
1598 bool CCMatch = CallerCC == CalleeCC;
1600 // Look for obvious safe cases to perform tail call optimization that do not
1601 // require ABI changes. This is what gcc calls sibcall.
1603 // Do not sibcall optimize vararg calls unless the call site is not passing
1605 if (isVarArg && !Outs.empty())
1608 // Also avoid sibcall optimization if either caller or callee uses struct
1609 // return semantics.
1610 if (isCalleeStructRet || isCallerStructRet)
1613 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
1614 // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
1615 // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
1616 // support in the assembler and linker to be used. This would need to be
1617 // fixed to fully support tail calls in Thumb1.
1619 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
1620 // LR. This means if we need to reload LR, it takes an extra instructions,
1621 // which outweighs the value of the tail call; but here we don't know yet
1622 // whether LR is going to be used. Probably the right approach is to
1623 // generate the tail call here and turn it back into CALL/RET in
1624 // emitEpilogue if LR is used.
1626 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
1627 // but we need to make sure there are enough registers; the only valid
1628 // registers are the 4 used for parameters. We don't currently do this
1630 if (Subtarget->isThumb1Only())
1633 // If the calling conventions do not match, then we'd better make sure the
1634 // results are returned in the same way as what the caller expects.
1636 SmallVector<CCValAssign, 16> RVLocs1;
1637 ARMCCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
1638 getTargetMachine(), RVLocs1, *DAG.getContext(), Call);
1639 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
1641 SmallVector<CCValAssign, 16> RVLocs2;
1642 ARMCCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
1643 getTargetMachine(), RVLocs2, *DAG.getContext(), Call);
1644 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
1646 if (RVLocs1.size() != RVLocs2.size())
1648 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
1649 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
1651 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
1653 if (RVLocs1[i].isRegLoc()) {
1654 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
1657 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
1663 // If the callee takes no arguments then go on to check the results of the
1665 if (!Outs.empty()) {
1666 // Check if stack adjustment is needed. For now, do not do this if any
1667 // argument is passed on the stack.
1668 SmallVector<CCValAssign, 16> ArgLocs;
1669 ARMCCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
1670 getTargetMachine(), ArgLocs, *DAG.getContext(), Call);
1671 CCInfo.AnalyzeCallOperands(Outs,
1672 CCAssignFnForNode(CalleeCC, false, isVarArg));
1673 if (CCInfo.getNextStackOffset()) {
1674 MachineFunction &MF = DAG.getMachineFunction();
1676 // Check if the arguments are already laid out in the right way as
1677 // the caller's fixed stack objects.
1678 MachineFrameInfo *MFI = MF.getFrameInfo();
1679 const MachineRegisterInfo *MRI = &MF.getRegInfo();
1680 const ARMInstrInfo *TII =
1681 ((ARMTargetMachine&)getTargetMachine()).getInstrInfo();
1682 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1684 ++i, ++realArgIdx) {
1685 CCValAssign &VA = ArgLocs[i];
1686 EVT RegVT = VA.getLocVT();
1687 SDValue Arg = OutVals[realArgIdx];
1688 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1689 if (VA.getLocInfo() == CCValAssign::Indirect)
1691 if (VA.needsCustom()) {
1692 // f64 and vector types are split into multiple registers or
1693 // register/stack-slot combinations. The types will not match
1694 // the registers; give up on memory f64 refs until we figure
1695 // out what to do about this.
1698 if (!ArgLocs[++i].isRegLoc())
1700 if (RegVT == MVT::v2f64) {
1701 if (!ArgLocs[++i].isRegLoc())
1703 if (!ArgLocs[++i].isRegLoc())
1706 } else if (!VA.isRegLoc()) {
1707 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
1719 ARMTargetLowering::LowerReturn(SDValue Chain,
1720 CallingConv::ID CallConv, bool isVarArg,
1721 const SmallVectorImpl<ISD::OutputArg> &Outs,
1722 const SmallVectorImpl<SDValue> &OutVals,
1723 DebugLoc dl, SelectionDAG &DAG) const {
1725 // CCValAssign - represent the assignment of the return value to a location.
1726 SmallVector<CCValAssign, 16> RVLocs;
1728 // CCState - Info about the registers and stack slots.
1729 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1730 getTargetMachine(), RVLocs, *DAG.getContext(), Call);
1732 // Analyze outgoing return values.
1733 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1736 // If this is the first return lowered for this function, add
1737 // the regs to the liveout set for the function.
1738 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1739 for (unsigned i = 0; i != RVLocs.size(); ++i)
1740 if (RVLocs[i].isRegLoc())
1741 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1746 // Copy the result values into the output registers.
1747 for (unsigned i = 0, realRVLocIdx = 0;
1749 ++i, ++realRVLocIdx) {
1750 CCValAssign &VA = RVLocs[i];
1751 assert(VA.isRegLoc() && "Can only return in registers!");
1753 SDValue Arg = OutVals[realRVLocIdx];
1755 switch (VA.getLocInfo()) {
1756 default: llvm_unreachable("Unknown loc info!");
1757 case CCValAssign::Full: break;
1758 case CCValAssign::BCvt:
1759 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1763 if (VA.needsCustom()) {
1764 if (VA.getLocVT() == MVT::v2f64) {
1765 // Extract the first half and return it in two registers.
1766 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1767 DAG.getConstant(0, MVT::i32));
1768 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
1769 DAG.getVTList(MVT::i32, MVT::i32), Half);
1771 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1772 Flag = Chain.getValue(1);
1773 VA = RVLocs[++i]; // skip ahead to next loc
1774 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1775 HalfGPRs.getValue(1), Flag);
1776 Flag = Chain.getValue(1);
1777 VA = RVLocs[++i]; // skip ahead to next loc
1779 // Extract the 2nd half and fall through to handle it as an f64 value.
1780 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1781 DAG.getConstant(1, MVT::i32));
1783 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1785 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1786 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1787 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1788 Flag = Chain.getValue(1);
1789 VA = RVLocs[++i]; // skip ahead to next loc
1790 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1793 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1795 // Guarantee that all emitted copies are
1796 // stuck together, avoiding something bad.
1797 Flag = Chain.getValue(1);
1802 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1804 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1809 bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N) const {
1810 if (N->getNumValues() != 1)
1812 if (!N->hasNUsesOfValue(1, 0))
1815 unsigned NumCopies = 0;
1817 SDNode *Use = *N->use_begin();
1818 if (Use->getOpcode() == ISD::CopyToReg) {
1819 Copies[NumCopies++] = Use;
1820 } else if (Use->getOpcode() == ARMISD::VMOVRRD) {
1821 // f64 returned in a pair of GPRs.
1822 for (SDNode::use_iterator UI = Use->use_begin(), UE = Use->use_end();
1824 if (UI->getOpcode() != ISD::CopyToReg)
1826 Copies[UI.getUse().getResNo()] = *UI;
1829 } else if (Use->getOpcode() == ISD::BITCAST) {
1830 // f32 returned in a single GPR.
1831 if (!Use->hasNUsesOfValue(1, 0))
1833 Use = *Use->use_begin();
1834 if (Use->getOpcode() != ISD::CopyToReg || !Use->hasNUsesOfValue(1, 0))
1836 Copies[NumCopies++] = Use;
1841 if (NumCopies != 1 && NumCopies != 2)
1844 bool HasRet = false;
1845 for (unsigned i = 0; i < NumCopies; ++i) {
1846 SDNode *Copy = Copies[i];
1847 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1849 if (UI->getOpcode() == ISD::CopyToReg) {
1851 if (Use == Copies[0] || Use == Copies[1])
1855 if (UI->getOpcode() != ARMISD::RET_FLAG)
1864 bool ARMTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
1865 if (!EnableARMTailCalls)
1868 if (!CI->isTailCall())
1871 return !Subtarget->isThumb1Only();
1874 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1875 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1876 // one of the above mentioned nodes. It has to be wrapped because otherwise
1877 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1878 // be used to form addressing mode. These wrapped nodes will be selected
1880 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1881 EVT PtrVT = Op.getValueType();
1882 // FIXME there is no actual debug info here
1883 DebugLoc dl = Op.getDebugLoc();
1884 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1886 if (CP->isMachineConstantPoolEntry())
1887 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1888 CP->getAlignment());
1890 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1891 CP->getAlignment());
1892 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1895 unsigned ARMTargetLowering::getJumpTableEncoding() const {
1896 return MachineJumpTableInfo::EK_Inline;
1899 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
1900 SelectionDAG &DAG) const {
1901 MachineFunction &MF = DAG.getMachineFunction();
1902 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1903 unsigned ARMPCLabelIndex = 0;
1904 DebugLoc DL = Op.getDebugLoc();
1905 EVT PtrVT = getPointerTy();
1906 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1907 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1909 if (RelocM == Reloc::Static) {
1910 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
1912 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1913 ARMPCLabelIndex = AFI->createPICLabelUId();
1914 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(BA, ARMPCLabelIndex,
1915 ARMCP::CPBlockAddress,
1917 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1919 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
1920 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
1921 MachinePointerInfo::getConstantPool(),
1923 if (RelocM == Reloc::Static)
1925 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1926 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
1929 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
1931 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1932 SelectionDAG &DAG) const {
1933 DebugLoc dl = GA->getDebugLoc();
1934 EVT PtrVT = getPointerTy();
1935 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1936 MachineFunction &MF = DAG.getMachineFunction();
1937 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1938 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1939 ARMConstantPoolValue *CPV =
1940 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1941 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
1942 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1943 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
1944 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
1945 MachinePointerInfo::getConstantPool(),
1947 SDValue Chain = Argument.getValue(1);
1949 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1950 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
1952 // call __tls_get_addr.
1955 Entry.Node = Argument;
1956 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
1957 Args.push_back(Entry);
1958 // FIXME: is there useful debug info available here?
1959 std::pair<SDValue, SDValue> CallResult =
1960 LowerCallTo(Chain, (Type *) Type::getInt32Ty(*DAG.getContext()),
1961 false, false, false, false,
1962 0, CallingConv::C, false, /*isReturnValueUsed=*/true,
1963 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
1964 return CallResult.first;
1967 // Lower ISD::GlobalTLSAddress using the "initial exec" or
1968 // "local exec" model.
1970 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
1971 SelectionDAG &DAG) const {
1972 const GlobalValue *GV = GA->getGlobal();
1973 DebugLoc dl = GA->getDebugLoc();
1975 SDValue Chain = DAG.getEntryNode();
1976 EVT PtrVT = getPointerTy();
1977 // Get the Thread Pointer
1978 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1980 if (GV->isDeclaration()) {
1981 MachineFunction &MF = DAG.getMachineFunction();
1982 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1983 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1984 // Initial exec model.
1985 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1986 ARMConstantPoolValue *CPV =
1987 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1988 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF, true);
1989 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1990 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1991 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1992 MachinePointerInfo::getConstantPool(),
1994 Chain = Offset.getValue(1);
1996 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1997 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
1999 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2000 MachinePointerInfo::getConstantPool(),
2004 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMCP::TPOFF);
2005 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2006 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2007 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2008 MachinePointerInfo::getConstantPool(),
2012 // The address of the thread local variable is the add of the thread
2013 // pointer with the offset of the variable.
2014 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
2018 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
2019 // TODO: implement the "local dynamic" model
2020 assert(Subtarget->isTargetELF() &&
2021 "TLS not implemented for non-ELF targets");
2022 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2023 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
2024 // otherwise use the "Local Exec" TLS Model
2025 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
2026 return LowerToTLSGeneralDynamicModel(GA, DAG);
2028 return LowerToTLSExecModels(GA, DAG);
2031 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
2032 SelectionDAG &DAG) const {
2033 EVT PtrVT = getPointerTy();
2034 DebugLoc dl = Op.getDebugLoc();
2035 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2036 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2037 if (RelocM == Reloc::PIC_) {
2038 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
2039 ARMConstantPoolValue *CPV =
2040 new ARMConstantPoolValue(GV, UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
2041 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2042 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2043 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
2045 MachinePointerInfo::getConstantPool(),
2047 SDValue Chain = Result.getValue(1);
2048 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
2049 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
2051 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
2052 MachinePointerInfo::getGOT(), false, false, 0);
2056 // If we have T2 ops, we can materialize the address directly via movt/movw
2057 // pair. This is always cheaper.
2058 if (Subtarget->useMovt()) {
2060 // FIXME: Once remat is capable of dealing with instructions with register
2061 // operands, expand this into two nodes.
2062 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2063 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2065 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
2066 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2067 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2068 MachinePointerInfo::getConstantPool(),
2073 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
2074 SelectionDAG &DAG) const {
2075 EVT PtrVT = getPointerTy();
2076 DebugLoc dl = Op.getDebugLoc();
2077 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2078 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2079 MachineFunction &MF = DAG.getMachineFunction();
2080 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2082 // FIXME: Enable this for static codegen when tool issues are fixed.
2083 if (Subtarget->useMovt() && RelocM != Reloc::Static) {
2085 // FIXME: Once remat is capable of dealing with instructions with register
2086 // operands, expand this into two nodes.
2087 if (RelocM == Reloc::Static)
2088 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2089 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2091 unsigned Wrapper = (RelocM == Reloc::PIC_)
2092 ? ARMISD::WrapperPIC : ARMISD::WrapperDYN;
2093 SDValue Result = DAG.getNode(Wrapper, dl, PtrVT,
2094 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2095 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
2096 Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
2097 MachinePointerInfo::getGOT(), false, false, 0);
2101 unsigned ARMPCLabelIndex = 0;
2103 if (RelocM == Reloc::Static) {
2104 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
2106 ARMPCLabelIndex = AFI->createPICLabelUId();
2107 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8);
2108 ARMConstantPoolValue *CPV =
2109 new ARMConstantPoolValue(GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj);
2110 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2112 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2114 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2115 MachinePointerInfo::getConstantPool(),
2117 SDValue Chain = Result.getValue(1);
2119 if (RelocM == Reloc::PIC_) {
2120 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2121 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2124 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
2125 Result = DAG.getLoad(PtrVT, dl, Chain, Result, MachinePointerInfo::getGOT(),
2131 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
2132 SelectionDAG &DAG) const {
2133 assert(Subtarget->isTargetELF() &&
2134 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
2135 MachineFunction &MF = DAG.getMachineFunction();
2136 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2137 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2138 EVT PtrVT = getPointerTy();
2139 DebugLoc dl = Op.getDebugLoc();
2140 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2141 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
2142 "_GLOBAL_OFFSET_TABLE_",
2143 ARMPCLabelIndex, PCAdj);
2144 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2145 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2146 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2147 MachinePointerInfo::getConstantPool(),
2149 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2150 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2154 ARMTargetLowering::LowerEH_SJLJ_DISPATCHSETUP(SDValue Op, SelectionDAG &DAG)
2156 DebugLoc dl = Op.getDebugLoc();
2157 return DAG.getNode(ARMISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other,
2158 Op.getOperand(0), Op.getOperand(1));
2162 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
2163 DebugLoc dl = Op.getDebugLoc();
2164 SDValue Val = DAG.getConstant(0, MVT::i32);
2165 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(0),
2166 Op.getOperand(1), Val);
2170 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
2171 DebugLoc dl = Op.getDebugLoc();
2172 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
2173 Op.getOperand(1), DAG.getConstant(0, MVT::i32));
2177 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
2178 const ARMSubtarget *Subtarget) const {
2179 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2180 DebugLoc dl = Op.getDebugLoc();
2182 default: return SDValue(); // Don't custom lower most intrinsics.
2183 case Intrinsic::arm_thread_pointer: {
2184 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2185 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2187 case Intrinsic::eh_sjlj_lsda: {
2188 MachineFunction &MF = DAG.getMachineFunction();
2189 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2190 unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2191 EVT PtrVT = getPointerTy();
2192 DebugLoc dl = Op.getDebugLoc();
2193 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2195 unsigned PCAdj = (RelocM != Reloc::PIC_)
2196 ? 0 : (Subtarget->isThumb() ? 4 : 8);
2197 ARMConstantPoolValue *CPV =
2198 new ARMConstantPoolValue(MF.getFunction(), ARMPCLabelIndex,
2199 ARMCP::CPLSDA, PCAdj);
2200 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2201 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2203 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2204 MachinePointerInfo::getConstantPool(),
2207 if (RelocM == Reloc::PIC_) {
2208 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2209 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2213 case Intrinsic::arm_neon_vmulls:
2214 case Intrinsic::arm_neon_vmullu: {
2215 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
2216 ? ARMISD::VMULLs : ARMISD::VMULLu;
2217 return DAG.getNode(NewOpc, Op.getDebugLoc(), Op.getValueType(),
2218 Op.getOperand(1), Op.getOperand(2));
2223 static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG,
2224 const ARMSubtarget *Subtarget) {
2225 DebugLoc dl = Op.getDebugLoc();
2226 if (!Subtarget->hasDataBarrier()) {
2227 // Some ARMv6 cpus can support data barriers with an mcr instruction.
2228 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
2230 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&
2231 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!");
2232 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2233 DAG.getConstant(0, MVT::i32));
2236 SDValue Op5 = Op.getOperand(5);
2237 bool isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue() != 0;
2238 unsigned isLL = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
2239 unsigned isLS = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
2240 bool isOnlyStoreBarrier = (isLL == 0 && isLS == 0);
2242 ARM_MB::MemBOpt DMBOpt;
2243 if (isDeviceBarrier)
2244 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ST : ARM_MB::SY;
2246 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ISHST : ARM_MB::ISH;
2247 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
2248 DAG.getConstant(DMBOpt, MVT::i32));
2252 static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
2253 const ARMSubtarget *Subtarget) {
2254 // FIXME: handle "fence singlethread" more efficiently.
2255 DebugLoc dl = Op.getDebugLoc();
2256 if (!Subtarget->hasDataBarrier()) {
2257 // Some ARMv6 cpus can support data barriers with an mcr instruction.
2258 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
2260 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&
2261 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!");
2262 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2263 DAG.getConstant(0, MVT::i32));
2266 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
2267 DAG.getConstant(ARM_MB::ISH, MVT::i32));
2270 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
2271 const ARMSubtarget *Subtarget) {
2272 // ARM pre v5TE and Thumb1 does not have preload instructions.
2273 if (!(Subtarget->isThumb2() ||
2274 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
2275 // Just preserve the chain.
2276 return Op.getOperand(0);
2278 DebugLoc dl = Op.getDebugLoc();
2279 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
2281 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
2282 // ARMv7 with MP extension has PLDW.
2283 return Op.getOperand(0);
2285 unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
2286 if (Subtarget->isThumb()) {
2288 isRead = ~isRead & 1;
2289 isData = ~isData & 1;
2292 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
2293 Op.getOperand(1), DAG.getConstant(isRead, MVT::i32),
2294 DAG.getConstant(isData, MVT::i32));
2297 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
2298 MachineFunction &MF = DAG.getMachineFunction();
2299 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
2301 // vastart just stores the address of the VarArgsFrameIndex slot into the
2302 // memory location argument.
2303 DebugLoc dl = Op.getDebugLoc();
2304 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2305 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2306 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2307 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2308 MachinePointerInfo(SV), false, false, 0);
2312 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
2313 SDValue &Root, SelectionDAG &DAG,
2314 DebugLoc dl) const {
2315 MachineFunction &MF = DAG.getMachineFunction();
2316 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2318 TargetRegisterClass *RC;
2319 if (AFI->isThumb1OnlyFunction())
2320 RC = ARM::tGPRRegisterClass;
2322 RC = ARM::GPRRegisterClass;
2324 // Transform the arguments stored in physical registers into virtual ones.
2325 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2326 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2329 if (NextVA.isMemLoc()) {
2330 MachineFrameInfo *MFI = MF.getFrameInfo();
2331 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
2333 // Create load node to retrieve arguments from the stack.
2334 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2335 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
2336 MachinePointerInfo::getFixedStack(FI),
2339 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2340 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2343 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
2347 ARMTargetLowering::computeRegArea(CCState &CCInfo, MachineFunction &MF,
2348 unsigned &VARegSize, unsigned &VARegSaveSize)
2351 if (CCInfo.isFirstByValRegValid())
2352 NumGPRs = ARM::R4 - CCInfo.getFirstByValReg();
2354 unsigned int firstUnalloced;
2355 firstUnalloced = CCInfo.getFirstUnallocated(GPRArgRegs,
2356 sizeof(GPRArgRegs) /
2357 sizeof(GPRArgRegs[0]));
2358 NumGPRs = (firstUnalloced <= 3) ? (4 - firstUnalloced) : 0;
2361 unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment();
2362 VARegSize = NumGPRs * 4;
2363 VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
2366 // The remaining GPRs hold either the beginning of variable-argument
2367 // data, or the beginning of an aggregate passed by value (usuall
2368 // byval). Either way, we allocate stack slots adjacent to the data
2369 // provided by our caller, and store the unallocated registers there.
2370 // If this is a variadic function, the va_list pointer will begin with
2371 // these values; otherwise, this reassembles a (byval) structure that
2372 // was split between registers and memory.
2374 ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
2375 DebugLoc dl, SDValue &Chain,
2376 unsigned ArgOffset) const {
2377 MachineFunction &MF = DAG.getMachineFunction();
2378 MachineFrameInfo *MFI = MF.getFrameInfo();
2379 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2380 unsigned firstRegToSaveIndex;
2381 if (CCInfo.isFirstByValRegValid())
2382 firstRegToSaveIndex = CCInfo.getFirstByValReg() - ARM::R0;
2384 firstRegToSaveIndex = CCInfo.getFirstUnallocated
2385 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
2388 unsigned VARegSize, VARegSaveSize;
2389 computeRegArea(CCInfo, MF, VARegSize, VARegSaveSize);
2390 if (VARegSaveSize) {
2391 // If this function is vararg, store any remaining integer argument regs
2392 // to their spots on the stack so that they may be loaded by deferencing
2393 // the result of va_next.
2394 AFI->setVarArgsRegSaveSize(VARegSaveSize);
2395 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(VARegSaveSize,
2396 ArgOffset + VARegSaveSize
2399 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(),
2402 SmallVector<SDValue, 4> MemOps;
2403 for (; firstRegToSaveIndex < 4; ++firstRegToSaveIndex) {
2404 TargetRegisterClass *RC;
2405 if (AFI->isThumb1OnlyFunction())
2406 RC = ARM::tGPRRegisterClass;
2408 RC = ARM::GPRRegisterClass;
2410 unsigned VReg = MF.addLiveIn(GPRArgRegs[firstRegToSaveIndex], RC);
2411 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2413 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2414 MachinePointerInfo::getFixedStack(AFI->getVarArgsFrameIndex()),
2416 MemOps.push_back(Store);
2417 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
2418 DAG.getConstant(4, getPointerTy()));
2420 if (!MemOps.empty())
2421 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2422 &MemOps[0], MemOps.size());
2424 // This will point to the next argument passed via stack.
2425 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset, true));
2429 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
2430 CallingConv::ID CallConv, bool isVarArg,
2431 const SmallVectorImpl<ISD::InputArg>
2433 DebugLoc dl, SelectionDAG &DAG,
2434 SmallVectorImpl<SDValue> &InVals)
2436 MachineFunction &MF = DAG.getMachineFunction();
2437 MachineFrameInfo *MFI = MF.getFrameInfo();
2439 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2441 // Assign locations to all of the incoming arguments.
2442 SmallVector<CCValAssign, 16> ArgLocs;
2443 ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2444 getTargetMachine(), ArgLocs, *DAG.getContext(), Prologue);
2445 CCInfo.AnalyzeFormalArguments(Ins,
2446 CCAssignFnForNode(CallConv, /* Return*/ false,
2449 SmallVector<SDValue, 16> ArgValues;
2450 int lastInsIndex = -1;
2453 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2454 CCValAssign &VA = ArgLocs[i];
2456 // Arguments stored in registers.
2457 if (VA.isRegLoc()) {
2458 EVT RegVT = VA.getLocVT();
2460 if (VA.needsCustom()) {
2461 // f64 and vector types are split up into multiple registers or
2462 // combinations of registers and stack slots.
2463 if (VA.getLocVT() == MVT::v2f64) {
2464 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
2466 VA = ArgLocs[++i]; // skip ahead to next loc
2468 if (VA.isMemLoc()) {
2469 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
2470 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2471 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
2472 MachinePointerInfo::getFixedStack(FI),
2475 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
2478 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2479 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2480 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
2481 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2482 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
2484 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
2487 TargetRegisterClass *RC;
2489 if (RegVT == MVT::f32)
2490 RC = ARM::SPRRegisterClass;
2491 else if (RegVT == MVT::f64)
2492 RC = ARM::DPRRegisterClass;
2493 else if (RegVT == MVT::v2f64)
2494 RC = ARM::QPRRegisterClass;
2495 else if (RegVT == MVT::i32)
2496 RC = (AFI->isThumb1OnlyFunction() ?
2497 ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
2499 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2501 // Transform the arguments in physical registers into virtual ones.
2502 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2503 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2506 // If this is an 8 or 16-bit value, it is really passed promoted
2507 // to 32 bits. Insert an assert[sz]ext to capture this, then
2508 // truncate to the right size.
2509 switch (VA.getLocInfo()) {
2510 default: llvm_unreachable("Unknown loc info!");
2511 case CCValAssign::Full: break;
2512 case CCValAssign::BCvt:
2513 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2515 case CCValAssign::SExt:
2516 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2517 DAG.getValueType(VA.getValVT()));
2518 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2520 case CCValAssign::ZExt:
2521 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2522 DAG.getValueType(VA.getValVT()));
2523 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2527 InVals.push_back(ArgValue);
2529 } else { // VA.isRegLoc()
2532 assert(VA.isMemLoc());
2533 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
2535 int index = ArgLocs[i].getValNo();
2537 // Some Ins[] entries become multiple ArgLoc[] entries.
2538 // Process them only once.
2539 if (index != lastInsIndex)
2541 ISD::ArgFlagsTy Flags = Ins[index].Flags;
2542 // FIXME: For now, all byval parameter objects are marked mutable.
2543 // This can be changed with more analysis.
2544 // In case of tail call optimization mark all arguments mutable.
2545 // Since they could be overwritten by lowering of arguments in case of
2547 if (Flags.isByVal()) {
2548 unsigned VARegSize, VARegSaveSize;
2549 computeRegArea(CCInfo, MF, VARegSize, VARegSaveSize);
2550 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, 0);
2551 unsigned Bytes = Flags.getByValSize() - VARegSize;
2552 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects.
2553 int FI = MFI->CreateFixedObject(Bytes,
2554 VA.getLocMemOffset(), false);
2555 InVals.push_back(DAG.getFrameIndex(FI, getPointerTy()));
2557 int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
2558 VA.getLocMemOffset(), true);
2560 // Create load nodes to retrieve arguments from the stack.
2561 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2562 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2563 MachinePointerInfo::getFixedStack(FI),
2566 lastInsIndex = index;
2573 VarArgStyleRegisters(CCInfo, DAG, dl, Chain, CCInfo.getNextStackOffset());
2578 /// isFloatingPointZero - Return true if this is +0.0.
2579 static bool isFloatingPointZero(SDValue Op) {
2580 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
2581 return CFP->getValueAPF().isPosZero();
2582 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
2583 // Maybe this has already been legalized into the constant pool?
2584 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
2585 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
2586 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
2587 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
2588 return CFP->getValueAPF().isPosZero();
2594 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
2595 /// the given operands.
2597 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2598 SDValue &ARMcc, SelectionDAG &DAG,
2599 DebugLoc dl) const {
2600 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
2601 unsigned C = RHSC->getZExtValue();
2602 if (!isLegalICmpImmediate(C)) {
2603 // Constant does not fit, try adjusting it by one?
2608 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
2609 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
2610 RHS = DAG.getConstant(C-1, MVT::i32);
2615 if (C != 0 && isLegalICmpImmediate(C-1)) {
2616 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
2617 RHS = DAG.getConstant(C-1, MVT::i32);
2622 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
2623 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
2624 RHS = DAG.getConstant(C+1, MVT::i32);
2629 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
2630 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2631 RHS = DAG.getConstant(C+1, MVT::i32);
2638 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2639 ARMISD::NodeType CompareType;
2642 CompareType = ARMISD::CMP;
2647 CompareType = ARMISD::CMPZ;
2650 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2651 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
2654 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
2656 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
2657 DebugLoc dl) const {
2659 if (!isFloatingPointZero(RHS))
2660 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS);
2662 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS);
2663 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
2666 /// duplicateCmp - Glue values can have only one use, so this function
2667 /// duplicates a comparison node.
2669 ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
2670 unsigned Opc = Cmp.getOpcode();
2671 DebugLoc DL = Cmp.getDebugLoc();
2672 if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
2673 return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
2675 assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation");
2676 Cmp = Cmp.getOperand(0);
2677 Opc = Cmp.getOpcode();
2678 if (Opc == ARMISD::CMPFP)
2679 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
2681 assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT");
2682 Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0));
2684 return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
2687 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2688 SDValue Cond = Op.getOperand(0);
2689 SDValue SelectTrue = Op.getOperand(1);
2690 SDValue SelectFalse = Op.getOperand(2);
2691 DebugLoc dl = Op.getDebugLoc();
2695 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
2696 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
2698 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
2699 const ConstantSDNode *CMOVTrue =
2700 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
2701 const ConstantSDNode *CMOVFalse =
2702 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
2704 if (CMOVTrue && CMOVFalse) {
2705 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
2706 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
2710 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
2712 False = SelectFalse;
2713 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
2718 if (True.getNode() && False.getNode()) {
2719 EVT VT = Op.getValueType();
2720 SDValue ARMcc = Cond.getOperand(2);
2721 SDValue CCR = Cond.getOperand(3);
2722 SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
2723 assert(True.getValueType() == VT);
2724 return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp);
2729 return DAG.getSelectCC(dl, Cond,
2730 DAG.getConstant(0, Cond.getValueType()),
2731 SelectTrue, SelectFalse, ISD::SETNE);
2734 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
2735 EVT VT = Op.getValueType();
2736 SDValue LHS = Op.getOperand(0);
2737 SDValue RHS = Op.getOperand(1);
2738 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2739 SDValue TrueVal = Op.getOperand(2);
2740 SDValue FalseVal = Op.getOperand(3);
2741 DebugLoc dl = Op.getDebugLoc();
2743 if (LHS.getValueType() == MVT::i32) {
2745 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2746 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2747 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp);
2750 ARMCC::CondCodes CondCode, CondCode2;
2751 FPCCToARMCC(CC, CondCode, CondCode2);
2753 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2754 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2755 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2756 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
2758 if (CondCode2 != ARMCC::AL) {
2759 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32);
2760 // FIXME: Needs another CMP because flag can have but one use.
2761 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
2762 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
2763 Result, TrueVal, ARMcc2, CCR, Cmp2);
2768 /// canChangeToInt - Given the fp compare operand, return true if it is suitable
2769 /// to morph to an integer compare sequence.
2770 static bool canChangeToInt(SDValue Op, bool &SeenZero,
2771 const ARMSubtarget *Subtarget) {
2772 SDNode *N = Op.getNode();
2773 if (!N->hasOneUse())
2774 // Otherwise it requires moving the value from fp to integer registers.
2776 if (!N->getNumValues())
2778 EVT VT = Op.getValueType();
2779 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
2780 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
2781 // vmrs are very slow, e.g. cortex-a8.
2784 if (isFloatingPointZero(Op)) {
2788 return ISD::isNormalLoad(N);
2791 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
2792 if (isFloatingPointZero(Op))
2793 return DAG.getConstant(0, MVT::i32);
2795 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
2796 return DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2797 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(),
2798 Ld->isVolatile(), Ld->isNonTemporal(),
2799 Ld->getAlignment());
2801 llvm_unreachable("Unknown VFP cmp argument!");
2804 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
2805 SDValue &RetVal1, SDValue &RetVal2) {
2806 if (isFloatingPointZero(Op)) {
2807 RetVal1 = DAG.getConstant(0, MVT::i32);
2808 RetVal2 = DAG.getConstant(0, MVT::i32);
2812 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
2813 SDValue Ptr = Ld->getBasePtr();
2814 RetVal1 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2815 Ld->getChain(), Ptr,
2816 Ld->getPointerInfo(),
2817 Ld->isVolatile(), Ld->isNonTemporal(),
2818 Ld->getAlignment());
2820 EVT PtrType = Ptr.getValueType();
2821 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
2822 SDValue NewPtr = DAG.getNode(ISD::ADD, Op.getDebugLoc(),
2823 PtrType, Ptr, DAG.getConstant(4, PtrType));
2824 RetVal2 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2825 Ld->getChain(), NewPtr,
2826 Ld->getPointerInfo().getWithOffset(4),
2827 Ld->isVolatile(), Ld->isNonTemporal(),
2832 llvm_unreachable("Unknown VFP cmp argument!");
2835 /// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
2836 /// f32 and even f64 comparisons to integer ones.
2838 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
2839 SDValue Chain = Op.getOperand(0);
2840 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2841 SDValue LHS = Op.getOperand(2);
2842 SDValue RHS = Op.getOperand(3);
2843 SDValue Dest = Op.getOperand(4);
2844 DebugLoc dl = Op.getDebugLoc();
2846 bool SeenZero = false;
2847 if (canChangeToInt(LHS, SeenZero, Subtarget) &&
2848 canChangeToInt(RHS, SeenZero, Subtarget) &&
2849 // If one of the operand is zero, it's safe to ignore the NaN case since
2850 // we only care about equality comparisons.
2851 (SeenZero || (DAG.isKnownNeverNaN(LHS) && DAG.isKnownNeverNaN(RHS)))) {
2852 // If unsafe fp math optimization is enabled and there are no other uses of
2853 // the CMP operands, and the condition code is EQ or NE, we can optimize it
2854 // to an integer comparison.
2855 if (CC == ISD::SETOEQ)
2857 else if (CC == ISD::SETUNE)
2861 if (LHS.getValueType() == MVT::f32) {
2862 LHS = bitcastf32Toi32(LHS, DAG);
2863 RHS = bitcastf32Toi32(RHS, DAG);
2864 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2865 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2866 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2867 Chain, Dest, ARMcc, CCR, Cmp);
2872 expandf64Toi32(LHS, DAG, LHS1, LHS2);
2873 expandf64Toi32(RHS, DAG, RHS1, RHS2);
2874 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2875 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2876 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
2877 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
2878 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7);
2884 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2885 SDValue Chain = Op.getOperand(0);
2886 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2887 SDValue LHS = Op.getOperand(2);
2888 SDValue RHS = Op.getOperand(3);
2889 SDValue Dest = Op.getOperand(4);
2890 DebugLoc dl = Op.getDebugLoc();
2892 if (LHS.getValueType() == MVT::i32) {
2894 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2895 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2896 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2897 Chain, Dest, ARMcc, CCR, Cmp);
2900 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
2903 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
2904 CC == ISD::SETNE || CC == ISD::SETUNE)) {
2905 SDValue Result = OptimizeVFPBrcond(Op, DAG);
2906 if (Result.getNode())
2910 ARMCC::CondCodes CondCode, CondCode2;
2911 FPCCToARMCC(CC, CondCode, CondCode2);
2913 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2914 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2915 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2916 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
2917 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
2918 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2919 if (CondCode2 != ARMCC::AL) {
2920 ARMcc = DAG.getConstant(CondCode2, MVT::i32);
2921 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
2922 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2927 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
2928 SDValue Chain = Op.getOperand(0);
2929 SDValue Table = Op.getOperand(1);
2930 SDValue Index = Op.getOperand(2);
2931 DebugLoc dl = Op.getDebugLoc();
2933 EVT PTy = getPointerTy();
2934 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
2935 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
2936 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
2937 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
2938 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
2939 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
2940 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2941 if (Subtarget->isThumb2()) {
2942 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
2943 // which does another jump to the destination. This also makes it easier
2944 // to translate it to TBB / TBH later.
2945 // FIXME: This might not work if the function is extremely large.
2946 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
2947 Addr, Op.getOperand(2), JTI, UId);
2949 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2950 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
2951 MachinePointerInfo::getJumpTable(),
2953 Chain = Addr.getValue(1);
2954 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
2955 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2957 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
2958 MachinePointerInfo::getJumpTable(), false, false, 0);
2959 Chain = Addr.getValue(1);
2960 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2964 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
2965 DebugLoc dl = Op.getDebugLoc();
2968 switch (Op.getOpcode()) {
2970 assert(0 && "Invalid opcode!");
2971 case ISD::FP_TO_SINT:
2972 Opc = ARMISD::FTOSI;
2974 case ISD::FP_TO_UINT:
2975 Opc = ARMISD::FTOUI;
2978 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
2979 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
2982 static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
2983 EVT VT = Op.getValueType();
2984 DebugLoc dl = Op.getDebugLoc();
2986 EVT OperandVT = Op.getOperand(0).getValueType();
2987 assert(OperandVT == MVT::v4i16 && "Invalid type for custom lowering!");
2988 if (VT != MVT::v4f32)
2989 return DAG.UnrollVectorOp(Op.getNode());
2993 switch (Op.getOpcode()) {
2995 assert(0 && "Invalid opcode!");
2996 case ISD::SINT_TO_FP:
2997 CastOpc = ISD::SIGN_EXTEND;
2998 Opc = ISD::SINT_TO_FP;
3000 case ISD::UINT_TO_FP:
3001 CastOpc = ISD::ZERO_EXTEND;
3002 Opc = ISD::UINT_TO_FP;
3006 Op = DAG.getNode(CastOpc, dl, MVT::v4i32, Op.getOperand(0));
3007 return DAG.getNode(Opc, dl, VT, Op);
3010 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
3011 EVT VT = Op.getValueType();
3013 return LowerVectorINT_TO_FP(Op, DAG);
3015 DebugLoc dl = Op.getDebugLoc();
3018 switch (Op.getOpcode()) {
3020 assert(0 && "Invalid opcode!");
3021 case ISD::SINT_TO_FP:
3022 Opc = ARMISD::SITOF;
3024 case ISD::UINT_TO_FP:
3025 Opc = ARMISD::UITOF;
3029 Op = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0));
3030 return DAG.getNode(Opc, dl, VT, Op);
3033 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
3034 // Implement fcopysign with a fabs and a conditional fneg.
3035 SDValue Tmp0 = Op.getOperand(0);
3036 SDValue Tmp1 = Op.getOperand(1);
3037 DebugLoc dl = Op.getDebugLoc();
3038 EVT VT = Op.getValueType();
3039 EVT SrcVT = Tmp1.getValueType();
3040 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
3041 Tmp0.getOpcode() == ARMISD::VMOVDRR;
3042 bool UseNEON = !InGPR && Subtarget->hasNEON();
3045 // Use VBSL to copy the sign bit.
3046 unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80);
3047 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
3048 DAG.getTargetConstant(EncodedVal, MVT::i32));
3049 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
3051 Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT,
3052 DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
3053 DAG.getConstant(32, MVT::i32));
3054 else /*if (VT == MVT::f32)*/
3055 Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
3056 if (SrcVT == MVT::f32) {
3057 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
3059 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT,
3060 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
3061 DAG.getConstant(32, MVT::i32));
3062 } else if (VT == MVT::f32)
3063 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64,
3064 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
3065 DAG.getConstant(32, MVT::i32));
3066 Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
3067 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
3069 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff),
3071 AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
3072 SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
3073 DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
3075 SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
3076 DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
3077 DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
3078 if (VT == MVT::f32) {
3079 Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
3080 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
3081 DAG.getConstant(0, MVT::i32));
3083 Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
3089 // Bitcast operand 1 to i32.
3090 if (SrcVT == MVT::f64)
3091 Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
3092 &Tmp1, 1).getValue(1);
3093 Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
3095 // Or in the signbit with integer operations.
3096 SDValue Mask1 = DAG.getConstant(0x80000000, MVT::i32);
3097 SDValue Mask2 = DAG.getConstant(0x7fffffff, MVT::i32);
3098 Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
3099 if (VT == MVT::f32) {
3100 Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
3101 DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
3102 return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3103 DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
3106 // f64: Or the high part with signbit and then combine two parts.
3107 Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
3109 SDValue Lo = Tmp0.getValue(0);
3110 SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
3111 Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
3112 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
3115 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
3116 MachineFunction &MF = DAG.getMachineFunction();
3117 MachineFrameInfo *MFI = MF.getFrameInfo();
3118 MFI->setReturnAddressIsTaken(true);
3120 EVT VT = Op.getValueType();
3121 DebugLoc dl = Op.getDebugLoc();
3122 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3124 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
3125 SDValue Offset = DAG.getConstant(4, MVT::i32);
3126 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
3127 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
3128 MachinePointerInfo(), false, false, 0);
3131 // Return LR, which contains the return address. Mark it an implicit live-in.
3132 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
3133 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
3136 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
3137 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3138 MFI->setFrameAddressIsTaken(true);
3140 EVT VT = Op.getValueType();
3141 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
3142 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3143 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
3144 ? ARM::R7 : ARM::R11;
3145 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
3147 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
3148 MachinePointerInfo(),
3153 /// ExpandBITCAST - If the target supports VFP, this function is called to
3154 /// expand a bit convert where either the source or destination type is i64 to
3155 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
3156 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
3157 /// vectors), since the legalizer won't know what to do with that.
3158 static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) {
3159 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3160 DebugLoc dl = N->getDebugLoc();
3161 SDValue Op = N->getOperand(0);
3163 // This function is only supposed to be called for i64 types, either as the
3164 // source or destination of the bit convert.
3165 EVT SrcVT = Op.getValueType();
3166 EVT DstVT = N->getValueType(0);
3167 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
3168 "ExpandBITCAST called for non-i64 type");
3170 // Turn i64->f64 into VMOVDRR.
3171 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
3172 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
3173 DAG.getConstant(0, MVT::i32));
3174 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
3175 DAG.getConstant(1, MVT::i32));
3176 return DAG.getNode(ISD::BITCAST, dl, DstVT,
3177 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
3180 // Turn f64->i64 into VMOVRRD.
3181 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
3182 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
3183 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
3184 // Merge the pieces into a single i64 value.
3185 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
3191 /// getZeroVector - Returns a vector of specified type with all zero elements.
3192 /// Zero vectors are used to represent vector negation and in those cases
3193 /// will be implemented with the NEON VNEG instruction. However, VNEG does
3194 /// not support i64 elements, so sometimes the zero vectors will need to be
3195 /// explicitly constructed. Regardless, use a canonical VMOV to create the
3197 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3198 assert(VT.isVector() && "Expected a vector type");
3199 // The canonical modified immediate encoding of a zero vector is....0!
3200 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32);
3201 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
3202 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
3203 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3206 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
3207 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
3208 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
3209 SelectionDAG &DAG) const {
3210 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3211 EVT VT = Op.getValueType();
3212 unsigned VTBits = VT.getSizeInBits();
3213 DebugLoc dl = Op.getDebugLoc();
3214 SDValue ShOpLo = Op.getOperand(0);
3215 SDValue ShOpHi = Op.getOperand(1);
3216 SDValue ShAmt = Op.getOperand(2);
3218 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
3220 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
3222 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
3223 DAG.getConstant(VTBits, MVT::i32), ShAmt);
3224 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
3225 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
3226 DAG.getConstant(VTBits, MVT::i32));
3227 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
3228 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3229 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
3231 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3232 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
3234 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
3235 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
3238 SDValue Ops[2] = { Lo, Hi };
3239 return DAG.getMergeValues(Ops, 2, dl);
3242 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
3243 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
3244 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
3245 SelectionDAG &DAG) const {
3246 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3247 EVT VT = Op.getValueType();
3248 unsigned VTBits = VT.getSizeInBits();
3249 DebugLoc dl = Op.getDebugLoc();
3250 SDValue ShOpLo = Op.getOperand(0);
3251 SDValue ShOpHi = Op.getOperand(1);
3252 SDValue ShAmt = Op.getOperand(2);
3255 assert(Op.getOpcode() == ISD::SHL_PARTS);
3256 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
3257 DAG.getConstant(VTBits, MVT::i32), ShAmt);
3258 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
3259 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
3260 DAG.getConstant(VTBits, MVT::i32));
3261 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
3262 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
3264 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3265 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3266 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
3268 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
3269 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
3272 SDValue Ops[2] = { Lo, Hi };
3273 return DAG.getMergeValues(Ops, 2, dl);
3276 SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
3277 SelectionDAG &DAG) const {
3278 // The rounding mode is in bits 23:22 of the FPSCR.
3279 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
3280 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
3281 // so that the shift + and get folded into a bitfield extract.
3282 DebugLoc dl = Op.getDebugLoc();
3283 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
3284 DAG.getConstant(Intrinsic::arm_get_fpscr,
3286 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
3287 DAG.getConstant(1U << 22, MVT::i32));
3288 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
3289 DAG.getConstant(22, MVT::i32));
3290 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
3291 DAG.getConstant(3, MVT::i32));
3294 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
3295 const ARMSubtarget *ST) {
3296 EVT VT = N->getValueType(0);
3297 DebugLoc dl = N->getDebugLoc();
3299 if (!ST->hasV6T2Ops())
3302 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
3303 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
3306 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
3307 const ARMSubtarget *ST) {
3308 EVT VT = N->getValueType(0);
3309 DebugLoc dl = N->getDebugLoc();
3314 // Lower vector shifts on NEON to use VSHL.
3315 assert(ST->hasNEON() && "unexpected vector shift");
3317 // Left shifts translate directly to the vshiftu intrinsic.
3318 if (N->getOpcode() == ISD::SHL)
3319 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
3320 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
3321 N->getOperand(0), N->getOperand(1));
3323 assert((N->getOpcode() == ISD::SRA ||
3324 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
3326 // NEON uses the same intrinsics for both left and right shifts. For
3327 // right shifts, the shift amounts are negative, so negate the vector of
3329 EVT ShiftVT = N->getOperand(1).getValueType();
3330 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
3331 getZeroVector(ShiftVT, DAG, dl),
3333 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
3334 Intrinsic::arm_neon_vshifts :
3335 Intrinsic::arm_neon_vshiftu);
3336 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
3337 DAG.getConstant(vshiftInt, MVT::i32),
3338 N->getOperand(0), NegatedCount);
3341 static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
3342 const ARMSubtarget *ST) {
3343 EVT VT = N->getValueType(0);
3344 DebugLoc dl = N->getDebugLoc();
3346 // We can get here for a node like i32 = ISD::SHL i32, i64
3350 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
3351 "Unknown shift to lower!");
3353 // We only lower SRA, SRL of 1 here, all others use generic lowering.
3354 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
3355 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
3358 // If we are in thumb mode, we don't have RRX.
3359 if (ST->isThumb1Only()) return SDValue();
3361 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
3362 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
3363 DAG.getConstant(0, MVT::i32));
3364 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
3365 DAG.getConstant(1, MVT::i32));
3367 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
3368 // captures the result into a carry flag.
3369 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
3370 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), &Hi, 1);
3372 // The low part is an ARMISD::RRX operand, which shifts the carry in.
3373 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
3375 // Merge the pieces into a single i64 value.
3376 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
3379 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
3380 SDValue TmpOp0, TmpOp1;
3381 bool Invert = false;
3385 SDValue Op0 = Op.getOperand(0);
3386 SDValue Op1 = Op.getOperand(1);
3387 SDValue CC = Op.getOperand(2);
3388 EVT VT = Op.getValueType();
3389 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
3390 DebugLoc dl = Op.getDebugLoc();
3392 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
3393 switch (SetCCOpcode) {
3394 default: llvm_unreachable("Illegal FP comparison"); break;
3396 case ISD::SETNE: Invert = true; // Fallthrough
3398 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3400 case ISD::SETLT: Swap = true; // Fallthrough
3402 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3404 case ISD::SETLE: Swap = true; // Fallthrough
3406 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3407 case ISD::SETUGE: Swap = true; // Fallthrough
3408 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
3409 case ISD::SETUGT: Swap = true; // Fallthrough
3410 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
3411 case ISD::SETUEQ: Invert = true; // Fallthrough
3413 // Expand this to (OLT | OGT).
3417 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3418 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
3420 case ISD::SETUO: Invert = true; // Fallthrough
3422 // Expand this to (OLT | OGE).
3426 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3427 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
3431 // Integer comparisons.
3432 switch (SetCCOpcode) {
3433 default: llvm_unreachable("Illegal integer comparison"); break;
3434 case ISD::SETNE: Invert = true;
3435 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3436 case ISD::SETLT: Swap = true;
3437 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3438 case ISD::SETLE: Swap = true;
3439 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3440 case ISD::SETULT: Swap = true;
3441 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
3442 case ISD::SETULE: Swap = true;
3443 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
3446 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
3447 if (Opc == ARMISD::VCEQ) {
3450 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
3452 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
3455 // Ignore bitconvert.
3456 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST)
3457 AndOp = AndOp.getOperand(0);
3459 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
3461 Op0 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(0));
3462 Op1 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(1));
3469 std::swap(Op0, Op1);
3471 // If one of the operands is a constant vector zero, attempt to fold the
3472 // comparison to a specialized compare-against-zero form.
3474 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
3476 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) {
3477 if (Opc == ARMISD::VCGE)
3478 Opc = ARMISD::VCLEZ;
3479 else if (Opc == ARMISD::VCGT)
3480 Opc = ARMISD::VCLTZ;
3485 if (SingleOp.getNode()) {
3488 Result = DAG.getNode(ARMISD::VCEQZ, dl, VT, SingleOp); break;
3490 Result = DAG.getNode(ARMISD::VCGEZ, dl, VT, SingleOp); break;
3492 Result = DAG.getNode(ARMISD::VCLEZ, dl, VT, SingleOp); break;
3494 Result = DAG.getNode(ARMISD::VCGTZ, dl, VT, SingleOp); break;
3496 Result = DAG.getNode(ARMISD::VCLTZ, dl, VT, SingleOp); break;
3498 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3501 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3505 Result = DAG.getNOT(dl, Result, VT);
3510 /// isNEONModifiedImm - Check if the specified splat value corresponds to a
3511 /// valid vector constant for a NEON instruction with a "modified immediate"
3512 /// operand (e.g., VMOV). If so, return the encoded value.
3513 static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
3514 unsigned SplatBitSize, SelectionDAG &DAG,
3515 EVT &VT, bool is128Bits, NEONModImmType type) {
3516 unsigned OpCmode, Imm;
3518 // SplatBitSize is set to the smallest size that splats the vector, so a
3519 // zero vector will always have SplatBitSize == 8. However, NEON modified
3520 // immediate instructions others than VMOV do not support the 8-bit encoding
3521 // of a zero vector, and the default encoding of zero is supposed to be the
3526 switch (SplatBitSize) {
3528 if (type != VMOVModImm)
3530 // Any 1-byte value is OK. Op=0, Cmode=1110.
3531 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
3534 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
3538 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
3539 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
3540 if ((SplatBits & ~0xff) == 0) {
3541 // Value = 0x00nn: Op=x, Cmode=100x.
3546 if ((SplatBits & ~0xff00) == 0) {
3547 // Value = 0xnn00: Op=x, Cmode=101x.
3549 Imm = SplatBits >> 8;
3555 // NEON's 32-bit VMOV supports splat values where:
3556 // * only one byte is nonzero, or
3557 // * the least significant byte is 0xff and the second byte is nonzero, or
3558 // * the least significant 2 bytes are 0xff and the third is nonzero.
3559 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
3560 if ((SplatBits & ~0xff) == 0) {
3561 // Value = 0x000000nn: Op=x, Cmode=000x.
3566 if ((SplatBits & ~0xff00) == 0) {
3567 // Value = 0x0000nn00: Op=x, Cmode=001x.
3569 Imm = SplatBits >> 8;
3572 if ((SplatBits & ~0xff0000) == 0) {
3573 // Value = 0x00nn0000: Op=x, Cmode=010x.
3575 Imm = SplatBits >> 16;
3578 if ((SplatBits & ~0xff000000) == 0) {
3579 // Value = 0xnn000000: Op=x, Cmode=011x.
3581 Imm = SplatBits >> 24;
3585 // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC
3586 if (type == OtherModImm) return SDValue();
3588 if ((SplatBits & ~0xffff) == 0 &&
3589 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
3590 // Value = 0x0000nnff: Op=x, Cmode=1100.
3592 Imm = SplatBits >> 8;
3597 if ((SplatBits & ~0xffffff) == 0 &&
3598 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
3599 // Value = 0x00nnffff: Op=x, Cmode=1101.
3601 Imm = SplatBits >> 16;
3602 SplatBits |= 0xffff;
3606 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
3607 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
3608 // VMOV.I32. A (very) minor optimization would be to replicate the value
3609 // and fall through here to test for a valid 64-bit splat. But, then the
3610 // caller would also need to check and handle the change in size.
3614 if (type != VMOVModImm)
3616 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
3617 uint64_t BitMask = 0xff;
3619 unsigned ImmMask = 1;
3621 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
3622 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
3625 } else if ((SplatBits & BitMask) != 0) {
3631 // Op=1, Cmode=1110.
3634 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
3639 llvm_unreachable("unexpected size for isNEONModifiedImm");
3643 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
3644 return DAG.getTargetConstant(EncodedVal, MVT::i32);
3647 static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT,
3648 bool &ReverseVEXT, unsigned &Imm) {
3649 unsigned NumElts = VT.getVectorNumElements();
3650 ReverseVEXT = false;
3652 // Assume that the first shuffle index is not UNDEF. Fail if it is.
3658 // If this is a VEXT shuffle, the immediate value is the index of the first
3659 // element. The other shuffle indices must be the successive elements after
3661 unsigned ExpectedElt = Imm;
3662 for (unsigned i = 1; i < NumElts; ++i) {
3663 // Increment the expected index. If it wraps around, it may still be
3664 // a VEXT but the source vectors must be swapped.
3666 if (ExpectedElt == NumElts * 2) {
3671 if (M[i] < 0) continue; // ignore UNDEF indices
3672 if (ExpectedElt != static_cast<unsigned>(M[i]))
3676 // Adjust the index value if the source operands will be swapped.
3683 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
3684 /// instruction with the specified blocksize. (The order of the elements
3685 /// within each block of the vector is reversed.)
3686 static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT,
3687 unsigned BlockSize) {
3688 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
3689 "Only possible block sizes for VREV are: 16, 32, 64");
3691 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3695 unsigned NumElts = VT.getVectorNumElements();
3696 unsigned BlockElts = M[0] + 1;
3697 // If the first shuffle index is UNDEF, be optimistic.
3699 BlockElts = BlockSize / EltSz;
3701 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
3704 for (unsigned i = 0; i < NumElts; ++i) {
3705 if (M[i] < 0) continue; // ignore UNDEF indices
3706 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
3713 static bool isVTBLMask(const SmallVectorImpl<int> &M, EVT VT) {
3714 // We can handle <8 x i8> vector shuffles. If the index in the mask is out of
3715 // range, then 0 is placed into the resulting vector. So pretty much any mask
3716 // of 8 elements can work here.
3717 return VT == MVT::v8i8 && M.size() == 8;
3720 static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT,
3721 unsigned &WhichResult) {
3722 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3726 unsigned NumElts = VT.getVectorNumElements();
3727 WhichResult = (M[0] == 0 ? 0 : 1);
3728 for (unsigned i = 0; i < NumElts; i += 2) {
3729 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3730 (M[i+1] >= 0 && (unsigned) M[i+1] != i + NumElts + WhichResult))
3736 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
3737 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3738 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
3739 static bool isVTRN_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3740 unsigned &WhichResult) {
3741 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3745 unsigned NumElts = VT.getVectorNumElements();
3746 WhichResult = (M[0] == 0 ? 0 : 1);
3747 for (unsigned i = 0; i < NumElts; i += 2) {
3748 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3749 (M[i+1] >= 0 && (unsigned) M[i+1] != i + WhichResult))
3755 static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT,
3756 unsigned &WhichResult) {
3757 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3761 unsigned NumElts = VT.getVectorNumElements();
3762 WhichResult = (M[0] == 0 ? 0 : 1);
3763 for (unsigned i = 0; i != NumElts; ++i) {
3764 if (M[i] < 0) continue; // ignore UNDEF indices
3765 if ((unsigned) M[i] != 2 * i + WhichResult)
3769 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3770 if (VT.is64BitVector() && EltSz == 32)
3776 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
3777 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3778 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
3779 static bool isVUZP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3780 unsigned &WhichResult) {
3781 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3785 unsigned Half = VT.getVectorNumElements() / 2;
3786 WhichResult = (M[0] == 0 ? 0 : 1);
3787 for (unsigned j = 0; j != 2; ++j) {
3788 unsigned Idx = WhichResult;
3789 for (unsigned i = 0; i != Half; ++i) {
3790 int MIdx = M[i + j * Half];
3791 if (MIdx >= 0 && (unsigned) MIdx != Idx)
3797 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3798 if (VT.is64BitVector() && EltSz == 32)
3804 static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT,
3805 unsigned &WhichResult) {
3806 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3810 unsigned NumElts = VT.getVectorNumElements();
3811 WhichResult = (M[0] == 0 ? 0 : 1);
3812 unsigned Idx = WhichResult * NumElts / 2;
3813 for (unsigned i = 0; i != NumElts; i += 2) {
3814 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3815 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts))
3820 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3821 if (VT.is64BitVector() && EltSz == 32)
3827 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
3828 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3829 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
3830 static bool isVZIP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3831 unsigned &WhichResult) {
3832 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3836 unsigned NumElts = VT.getVectorNumElements();
3837 WhichResult = (M[0] == 0 ? 0 : 1);
3838 unsigned Idx = WhichResult * NumElts / 2;
3839 for (unsigned i = 0; i != NumElts; i += 2) {
3840 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3841 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx))
3846 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3847 if (VT.is64BitVector() && EltSz == 32)
3853 // If N is an integer constant that can be moved into a register in one
3854 // instruction, return an SDValue of such a constant (will become a MOV
3855 // instruction). Otherwise return null.
3856 static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG,
3857 const ARMSubtarget *ST, DebugLoc dl) {
3859 if (!isa<ConstantSDNode>(N))
3861 Val = cast<ConstantSDNode>(N)->getZExtValue();
3863 if (ST->isThumb1Only()) {
3864 if (Val <= 255 || ~Val <= 255)
3865 return DAG.getConstant(Val, MVT::i32);
3867 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1)
3868 return DAG.getConstant(Val, MVT::i32);
3873 // If this is a case we can't handle, return null and let the default
3874 // expansion code take care of it.
3875 SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
3876 const ARMSubtarget *ST) const {
3877 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
3878 DebugLoc dl = Op.getDebugLoc();
3879 EVT VT = Op.getValueType();
3881 APInt SplatBits, SplatUndef;
3882 unsigned SplatBitSize;
3884 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
3885 if (SplatBitSize <= 64) {
3886 // Check if an immediate VMOV works.
3888 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
3889 SplatUndef.getZExtValue(), SplatBitSize,
3890 DAG, VmovVT, VT.is128BitVector(),
3892 if (Val.getNode()) {
3893 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
3894 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3897 // Try an immediate VMVN.
3898 uint64_t NegatedImm = (SplatBits.getZExtValue() ^
3899 ((1LL << SplatBitSize) - 1));
3900 Val = isNEONModifiedImm(NegatedImm,
3901 SplatUndef.getZExtValue(), SplatBitSize,
3902 DAG, VmovVT, VT.is128BitVector(),
3904 if (Val.getNode()) {
3905 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
3906 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3911 // Scan through the operands to see if only one value is used.
3912 unsigned NumElts = VT.getVectorNumElements();
3913 bool isOnlyLowElement = true;
3914 bool usesOnlyOneValue = true;
3915 bool isConstant = true;
3917 for (unsigned i = 0; i < NumElts; ++i) {
3918 SDValue V = Op.getOperand(i);
3919 if (V.getOpcode() == ISD::UNDEF)
3922 isOnlyLowElement = false;
3923 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
3926 if (!Value.getNode())
3928 else if (V != Value)
3929 usesOnlyOneValue = false;
3932 if (!Value.getNode())
3933 return DAG.getUNDEF(VT);
3935 if (isOnlyLowElement)
3936 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
3938 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3940 // Use VDUP for non-constant splats. For f32 constant splats, reduce to
3941 // i32 and try again.
3942 if (usesOnlyOneValue && EltSize <= 32) {
3944 return DAG.getNode(ARMISD::VDUP, dl, VT, Value);
3945 if (VT.getVectorElementType().isFloatingPoint()) {
3946 SmallVector<SDValue, 8> Ops;
3947 for (unsigned i = 0; i < NumElts; ++i)
3948 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32,
3950 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
3951 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], NumElts);
3952 Val = LowerBUILD_VECTOR(Val, DAG, ST);
3954 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
3956 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
3958 return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
3961 // If all elements are constants and the case above didn't get hit, fall back
3962 // to the default expansion, which will generate a load from the constant
3967 // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
3969 SDValue shuffle = ReconstructShuffle(Op, DAG);
3970 if (shuffle != SDValue())
3974 // Vectors with 32- or 64-bit elements can be built by directly assigning
3975 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
3976 // will be legalized.
3977 if (EltSize >= 32) {
3978 // Do the expansion with floating-point types, since that is what the VFP
3979 // registers are defined to use, and since i64 is not legal.
3980 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3981 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3982 SmallVector<SDValue, 8> Ops;
3983 for (unsigned i = 0; i < NumElts; ++i)
3984 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i)));
3985 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
3986 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
3992 // Gather data to see if the operation can be modelled as a
3993 // shuffle in combination with VEXTs.
3994 SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
3995 SelectionDAG &DAG) const {
3996 DebugLoc dl = Op.getDebugLoc();
3997 EVT VT = Op.getValueType();
3998 unsigned NumElts = VT.getVectorNumElements();
4000 SmallVector<SDValue, 2> SourceVecs;
4001 SmallVector<unsigned, 2> MinElts;
4002 SmallVector<unsigned, 2> MaxElts;
4004 for (unsigned i = 0; i < NumElts; ++i) {
4005 SDValue V = Op.getOperand(i);
4006 if (V.getOpcode() == ISD::UNDEF)
4008 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
4009 // A shuffle can only come from building a vector from various
4010 // elements of other vectors.
4014 // Record this extraction against the appropriate vector if possible...
4015 SDValue SourceVec = V.getOperand(0);
4016 unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
4017 bool FoundSource = false;
4018 for (unsigned j = 0; j < SourceVecs.size(); ++j) {
4019 if (SourceVecs[j] == SourceVec) {
4020 if (MinElts[j] > EltNo)
4022 if (MaxElts[j] < EltNo)
4029 // Or record a new source if not...
4031 SourceVecs.push_back(SourceVec);
4032 MinElts.push_back(EltNo);
4033 MaxElts.push_back(EltNo);
4037 // Currently only do something sane when at most two source vectors
4039 if (SourceVecs.size() > 2)
4042 SDValue ShuffleSrcs[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT) };
4043 int VEXTOffsets[2] = {0, 0};
4045 // This loop extracts the usage patterns of the source vectors
4046 // and prepares appropriate SDValues for a shuffle if possible.
4047 for (unsigned i = 0; i < SourceVecs.size(); ++i) {
4048 if (SourceVecs[i].getValueType() == VT) {
4049 // No VEXT necessary
4050 ShuffleSrcs[i] = SourceVecs[i];
4053 } else if (SourceVecs[i].getValueType().getVectorNumElements() < NumElts) {
4054 // It probably isn't worth padding out a smaller vector just to
4055 // break it down again in a shuffle.
4059 // Since only 64-bit and 128-bit vectors are legal on ARM and
4060 // we've eliminated the other cases...
4061 assert(SourceVecs[i].getValueType().getVectorNumElements() == 2*NumElts &&
4062 "unexpected vector sizes in ReconstructShuffle");
4064 if (MaxElts[i] - MinElts[i] >= NumElts) {
4065 // Span too large for a VEXT to cope
4069 if (MinElts[i] >= NumElts) {
4070 // The extraction can just take the second half
4071 VEXTOffsets[i] = NumElts;
4072 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4074 DAG.getIntPtrConstant(NumElts));
4075 } else if (MaxElts[i] < NumElts) {
4076 // The extraction can just take the first half
4078 ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4080 DAG.getIntPtrConstant(0));
4082 // An actual VEXT is needed
4083 VEXTOffsets[i] = MinElts[i];
4084 SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4086 DAG.getIntPtrConstant(0));
4087 SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
4089 DAG.getIntPtrConstant(NumElts));
4090 ShuffleSrcs[i] = DAG.getNode(ARMISD::VEXT, dl, VT, VEXTSrc1, VEXTSrc2,
4091 DAG.getConstant(VEXTOffsets[i], MVT::i32));
4095 SmallVector<int, 8> Mask;
4097 for (unsigned i = 0; i < NumElts; ++i) {
4098 SDValue Entry = Op.getOperand(i);
4099 if (Entry.getOpcode() == ISD::UNDEF) {
4104 SDValue ExtractVec = Entry.getOperand(0);
4105 int ExtractElt = cast<ConstantSDNode>(Op.getOperand(i)
4106 .getOperand(1))->getSExtValue();
4107 if (ExtractVec == SourceVecs[0]) {
4108 Mask.push_back(ExtractElt - VEXTOffsets[0]);
4110 Mask.push_back(ExtractElt + NumElts - VEXTOffsets[1]);
4114 // Final check before we try to produce nonsense...
4115 if (isShuffleMaskLegal(Mask, VT))
4116 return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1],
4122 /// isShuffleMaskLegal - Targets can use this to indicate that they only
4123 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
4124 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
4125 /// are assumed to be legal.
4127 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
4129 if (VT.getVectorNumElements() == 4 &&
4130 (VT.is128BitVector() || VT.is64BitVector())) {
4131 unsigned PFIndexes[4];
4132 for (unsigned i = 0; i != 4; ++i) {
4136 PFIndexes[i] = M[i];
4139 // Compute the index in the perfect shuffle table.
4140 unsigned PFTableIndex =
4141 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
4142 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4143 unsigned Cost = (PFEntry >> 30);
4150 unsigned Imm, WhichResult;
4152 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4153 return (EltSize >= 32 ||
4154 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
4155 isVREVMask(M, VT, 64) ||
4156 isVREVMask(M, VT, 32) ||
4157 isVREVMask(M, VT, 16) ||
4158 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
4159 isVTBLMask(M, VT) ||
4160 isVTRNMask(M, VT, WhichResult) ||
4161 isVUZPMask(M, VT, WhichResult) ||
4162 isVZIPMask(M, VT, WhichResult) ||
4163 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
4164 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
4165 isVZIP_v_undef_Mask(M, VT, WhichResult));
4168 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
4169 /// the specified operations to build the shuffle.
4170 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
4171 SDValue RHS, SelectionDAG &DAG,
4173 unsigned OpNum = (PFEntry >> 26) & 0x0F;
4174 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
4175 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
4178 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
4187 OP_VUZPL, // VUZP, left result
4188 OP_VUZPR, // VUZP, right result
4189 OP_VZIPL, // VZIP, left result
4190 OP_VZIPR, // VZIP, right result
4191 OP_VTRNL, // VTRN, left result
4192 OP_VTRNR // VTRN, right result
4195 if (OpNum == OP_COPY) {
4196 if (LHSID == (1*9+2)*9+3) return LHS;
4197 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
4201 SDValue OpLHS, OpRHS;
4202 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
4203 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
4204 EVT VT = OpLHS.getValueType();
4207 default: llvm_unreachable("Unknown shuffle opcode!");
4209 // VREV divides the vector in half and swaps within the half.
4210 if (VT.getVectorElementType() == MVT::i32 ||
4211 VT.getVectorElementType() == MVT::f32)
4212 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
4213 // vrev <4 x i16> -> VREV32
4214 if (VT.getVectorElementType() == MVT::i16)
4215 return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS);
4216 // vrev <4 x i8> -> VREV16
4217 assert(VT.getVectorElementType() == MVT::i8);
4218 return DAG.getNode(ARMISD::VREV16, dl, VT, OpLHS);
4223 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
4224 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
4228 return DAG.getNode(ARMISD::VEXT, dl, VT,
4230 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
4233 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4234 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
4237 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4238 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
4241 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4242 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
4246 static SDValue LowerVECTOR_SHUFFLEv8i8(SDValue Op,
4247 SmallVectorImpl<int> &ShuffleMask,
4248 SelectionDAG &DAG) {
4249 // Check to see if we can use the VTBL instruction.
4250 SDValue V1 = Op.getOperand(0);
4251 SDValue V2 = Op.getOperand(1);
4252 DebugLoc DL = Op.getDebugLoc();
4254 SmallVector<SDValue, 8> VTBLMask;
4255 for (SmallVectorImpl<int>::iterator
4256 I = ShuffleMask.begin(), E = ShuffleMask.end(); I != E; ++I)
4257 VTBLMask.push_back(DAG.getConstant(*I, MVT::i32));
4259 if (V2.getNode()->getOpcode() == ISD::UNDEF)
4260 return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1,
4261 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
4264 return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2,
4265 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
4269 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
4270 SDValue V1 = Op.getOperand(0);
4271 SDValue V2 = Op.getOperand(1);
4272 DebugLoc dl = Op.getDebugLoc();
4273 EVT VT = Op.getValueType();
4274 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
4275 SmallVector<int, 8> ShuffleMask;
4277 // Convert shuffles that are directly supported on NEON to target-specific
4278 // DAG nodes, instead of keeping them as shuffles and matching them again
4279 // during code selection. This is more efficient and avoids the possibility
4280 // of inconsistencies between legalization and selection.
4281 // FIXME: floating-point vectors should be canonicalized to integer vectors
4282 // of the same time so that they get CSEd properly.
4283 SVN->getMask(ShuffleMask);
4285 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4286 if (EltSize <= 32) {
4287 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
4288 int Lane = SVN->getSplatIndex();
4289 // If this is undef splat, generate it via "just" vdup, if possible.
4290 if (Lane == -1) Lane = 0;
4292 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4293 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
4295 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
4296 DAG.getConstant(Lane, MVT::i32));
4301 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
4304 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
4305 DAG.getConstant(Imm, MVT::i32));
4308 if (isVREVMask(ShuffleMask, VT, 64))
4309 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
4310 if (isVREVMask(ShuffleMask, VT, 32))
4311 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
4312 if (isVREVMask(ShuffleMask, VT, 16))
4313 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
4315 // Check for Neon shuffles that modify both input vectors in place.
4316 // If both results are used, i.e., if there are two shuffles with the same
4317 // source operands and with masks corresponding to both results of one of
4318 // these operations, DAG memoization will ensure that a single node is
4319 // used for both shuffles.
4320 unsigned WhichResult;
4321 if (isVTRNMask(ShuffleMask, VT, WhichResult))
4322 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4323 V1, V2).getValue(WhichResult);
4324 if (isVUZPMask(ShuffleMask, VT, WhichResult))
4325 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4326 V1, V2).getValue(WhichResult);
4327 if (isVZIPMask(ShuffleMask, VT, WhichResult))
4328 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4329 V1, V2).getValue(WhichResult);
4331 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
4332 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
4333 V1, V1).getValue(WhichResult);
4334 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
4335 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
4336 V1, V1).getValue(WhichResult);
4337 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
4338 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
4339 V1, V1).getValue(WhichResult);
4342 // If the shuffle is not directly supported and it has 4 elements, use
4343 // the PerfectShuffle-generated table to synthesize it from other shuffles.
4344 unsigned NumElts = VT.getVectorNumElements();
4346 unsigned PFIndexes[4];
4347 for (unsigned i = 0; i != 4; ++i) {
4348 if (ShuffleMask[i] < 0)
4351 PFIndexes[i] = ShuffleMask[i];
4354 // Compute the index in the perfect shuffle table.
4355 unsigned PFTableIndex =
4356 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
4357 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4358 unsigned Cost = (PFEntry >> 30);
4361 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
4364 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
4365 if (EltSize >= 32) {
4366 // Do the expansion with floating-point types, since that is what the VFP
4367 // registers are defined to use, and since i64 is not legal.
4368 EVT EltVT = EVT::getFloatingPointVT(EltSize);
4369 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
4370 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1);
4371 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2);
4372 SmallVector<SDValue, 8> Ops;
4373 for (unsigned i = 0; i < NumElts; ++i) {
4374 if (ShuffleMask[i] < 0)
4375 Ops.push_back(DAG.getUNDEF(EltVT));
4377 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
4378 ShuffleMask[i] < (int)NumElts ? V1 : V2,
4379 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
4382 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
4383 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
4386 if (VT == MVT::v8i8) {
4387 SDValue NewOp = LowerVECTOR_SHUFFLEv8i8(Op, ShuffleMask, DAG);
4388 if (NewOp.getNode())
4395 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
4396 // EXTRACT_VECTOR_ELT is legal only for immediate indexes.
4397 SDValue Lane = Op.getOperand(1);
4398 if (!isa<ConstantSDNode>(Lane))
4401 SDValue Vec = Op.getOperand(0);
4402 if (Op.getValueType() == MVT::i32 &&
4403 Vec.getValueType().getVectorElementType().getSizeInBits() < 32) {
4404 DebugLoc dl = Op.getDebugLoc();
4405 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
4411 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
4412 // The only time a CONCAT_VECTORS operation can have legal types is when
4413 // two 64-bit vectors are concatenated to a 128-bit vector.
4414 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
4415 "unexpected CONCAT_VECTORS");
4416 DebugLoc dl = Op.getDebugLoc();
4417 SDValue Val = DAG.getUNDEF(MVT::v2f64);
4418 SDValue Op0 = Op.getOperand(0);
4419 SDValue Op1 = Op.getOperand(1);
4420 if (Op0.getOpcode() != ISD::UNDEF)
4421 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
4422 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0),
4423 DAG.getIntPtrConstant(0));
4424 if (Op1.getOpcode() != ISD::UNDEF)
4425 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
4426 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1),
4427 DAG.getIntPtrConstant(1));
4428 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val);
4431 /// isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each
4432 /// element has been zero/sign-extended, depending on the isSigned parameter,
4433 /// from an integer type half its size.
4434 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
4436 // A v2i64 BUILD_VECTOR will have been legalized to a BITCAST from v4i32.
4437 EVT VT = N->getValueType(0);
4438 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) {
4439 SDNode *BVN = N->getOperand(0).getNode();
4440 if (BVN->getValueType(0) != MVT::v4i32 ||
4441 BVN->getOpcode() != ISD::BUILD_VECTOR)
4443 unsigned LoElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
4444 unsigned HiElt = 1 - LoElt;
4445 ConstantSDNode *Lo0 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt));
4446 ConstantSDNode *Hi0 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt));
4447 ConstantSDNode *Lo1 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt+2));
4448 ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2));
4449 if (!Lo0 || !Hi0 || !Lo1 || !Hi1)
4452 if (Hi0->getSExtValue() == Lo0->getSExtValue() >> 32 &&
4453 Hi1->getSExtValue() == Lo1->getSExtValue() >> 32)
4456 if (Hi0->isNullValue() && Hi1->isNullValue())
4462 if (N->getOpcode() != ISD::BUILD_VECTOR)
4465 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
4466 SDNode *Elt = N->getOperand(i).getNode();
4467 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
4468 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4469 unsigned HalfSize = EltSize / 2;
4471 int64_t SExtVal = C->getSExtValue();
4472 if ((SExtVal >> HalfSize) != (SExtVal >> EltSize))
4475 if ((C->getZExtValue() >> HalfSize) != 0)
4486 /// isSignExtended - Check if a node is a vector value that is sign-extended
4487 /// or a constant BUILD_VECTOR with sign-extended elements.
4488 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
4489 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N))
4491 if (isExtendedBUILD_VECTOR(N, DAG, true))
4496 /// isZeroExtended - Check if a node is a vector value that is zero-extended
4497 /// or a constant BUILD_VECTOR with zero-extended elements.
4498 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
4499 if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N))
4501 if (isExtendedBUILD_VECTOR(N, DAG, false))
4506 /// SkipExtension - For a node that is a SIGN_EXTEND, ZERO_EXTEND, extending
4507 /// load, or BUILD_VECTOR with extended elements, return the unextended value.
4508 static SDValue SkipExtension(SDNode *N, SelectionDAG &DAG) {
4509 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
4510 return N->getOperand(0);
4511 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
4512 return DAG.getLoad(LD->getMemoryVT(), N->getDebugLoc(), LD->getChain(),
4513 LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(),
4514 LD->isNonTemporal(), LD->getAlignment());
4515 // Otherwise, the value must be a BUILD_VECTOR. For v2i64, it will
4516 // have been legalized as a BITCAST from v4i32.
4517 if (N->getOpcode() == ISD::BITCAST) {
4518 SDNode *BVN = N->getOperand(0).getNode();
4519 assert(BVN->getOpcode() == ISD::BUILD_VECTOR &&
4520 BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR");
4521 unsigned LowElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
4522 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), MVT::v2i32,
4523 BVN->getOperand(LowElt), BVN->getOperand(LowElt+2));
4525 // Construct a new BUILD_VECTOR with elements truncated to half the size.
4526 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
4527 EVT VT = N->getValueType(0);
4528 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
4529 unsigned NumElts = VT.getVectorNumElements();
4530 MVT TruncVT = MVT::getIntegerVT(EltSize);
4531 SmallVector<SDValue, 8> Ops;
4532 for (unsigned i = 0; i != NumElts; ++i) {
4533 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
4534 const APInt &CInt = C->getAPIntValue();
4535 Ops.push_back(DAG.getConstant(CInt.trunc(EltSize), TruncVT));
4537 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
4538 MVT::getVectorVT(TruncVT, NumElts), Ops.data(), NumElts);
4541 static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
4542 unsigned Opcode = N->getOpcode();
4543 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
4544 SDNode *N0 = N->getOperand(0).getNode();
4545 SDNode *N1 = N->getOperand(1).getNode();
4546 return N0->hasOneUse() && N1->hasOneUse() &&
4547 isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
4552 static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
4553 unsigned Opcode = N->getOpcode();
4554 if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
4555 SDNode *N0 = N->getOperand(0).getNode();
4556 SDNode *N1 = N->getOperand(1).getNode();
4557 return N0->hasOneUse() && N1->hasOneUse() &&
4558 isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
4563 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
4564 // Multiplications are only custom-lowered for 128-bit vectors so that
4565 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
4566 EVT VT = Op.getValueType();
4567 assert(VT.is128BitVector() && "unexpected type for custom-lowering ISD::MUL");
4568 SDNode *N0 = Op.getOperand(0).getNode();
4569 SDNode *N1 = Op.getOperand(1).getNode();
4570 unsigned NewOpc = 0;
4572 bool isN0SExt = isSignExtended(N0, DAG);
4573 bool isN1SExt = isSignExtended(N1, DAG);
4574 if (isN0SExt && isN1SExt)
4575 NewOpc = ARMISD::VMULLs;
4577 bool isN0ZExt = isZeroExtended(N0, DAG);
4578 bool isN1ZExt = isZeroExtended(N1, DAG);
4579 if (isN0ZExt && isN1ZExt)
4580 NewOpc = ARMISD::VMULLu;
4581 else if (isN1SExt || isN1ZExt) {
4582 // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
4583 // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
4584 if (isN1SExt && isAddSubSExt(N0, DAG)) {
4585 NewOpc = ARMISD::VMULLs;
4587 } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
4588 NewOpc = ARMISD::VMULLu;
4590 } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
4592 NewOpc = ARMISD::VMULLu;
4598 if (VT == MVT::v2i64)
4599 // Fall through to expand this. It is not legal.
4602 // Other vector multiplications are legal.
4607 // Legalize to a VMULL instruction.
4608 DebugLoc DL = Op.getDebugLoc();
4610 SDValue Op1 = SkipExtension(N1, DAG);
4612 Op0 = SkipExtension(N0, DAG);
4613 assert(Op0.getValueType().is64BitVector() &&
4614 Op1.getValueType().is64BitVector() &&
4615 "unexpected types for extended operands to VMULL");
4616 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
4619 // Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during
4620 // isel lowering to take advantage of no-stall back to back vmul + vmla.
4627 SDValue N00 = SkipExtension(N0->getOperand(0).getNode(), DAG);
4628 SDValue N01 = SkipExtension(N0->getOperand(1).getNode(), DAG);
4629 EVT Op1VT = Op1.getValueType();
4630 return DAG.getNode(N0->getOpcode(), DL, VT,
4631 DAG.getNode(NewOpc, DL, VT,
4632 DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
4633 DAG.getNode(NewOpc, DL, VT,
4634 DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
4638 LowerSDIV_v4i8(SDValue X, SDValue Y, DebugLoc dl, SelectionDAG &DAG) {
4640 // float4 xf = vcvt_f32_s32(vmovl_s16(a.lo));
4641 // float4 yf = vcvt_f32_s32(vmovl_s16(b.lo));
4642 X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X);
4643 Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y);
4644 X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X);
4645 Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y);
4646 // Get reciprocal estimate.
4647 // float4 recip = vrecpeq_f32(yf);
4648 Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4649 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), Y);
4650 // Because char has a smaller range than uchar, we can actually get away
4651 // without any newton steps. This requires that we use a weird bias
4652 // of 0xb000, however (again, this has been exhaustively tested).
4653 // float4 result = as_float4(as_int4(xf*recip) + 0xb000);
4654 X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y);
4655 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X);
4656 Y = DAG.getConstant(0xb000, MVT::i32);
4657 Y = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Y, Y, Y, Y);
4658 X = DAG.getNode(ISD::ADD, dl, MVT::v4i32, X, Y);
4659 X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X);
4660 // Convert back to short.
4661 X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X);
4662 X = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, X);
4667 LowerSDIV_v4i16(SDValue N0, SDValue N1, DebugLoc dl, SelectionDAG &DAG) {
4669 // Convert to float.
4670 // float4 yf = vcvt_f32_s32(vmovl_s16(y));
4671 // float4 xf = vcvt_f32_s32(vmovl_s16(x));
4672 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0);
4673 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1);
4674 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
4675 N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
4677 // Use reciprocal estimate and one refinement step.
4678 // float4 recip = vrecpeq_f32(yf);
4679 // recip *= vrecpsq_f32(yf, recip);
4680 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4681 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1);
4682 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4683 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
4685 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
4686 // Because short has a smaller range than ushort, we can actually get away
4687 // with only a single newton step. This requires that we use a weird bias
4688 // of 89, however (again, this has been exhaustively tested).
4689 // float4 result = as_float4(as_int4(xf*recip) + 0x89);
4690 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
4691 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
4692 N1 = DAG.getConstant(0x89, MVT::i32);
4693 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
4694 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
4695 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
4696 // Convert back to integer and return.
4697 // return vmovn_s32(vcvt_s32_f32(result));
4698 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
4699 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
4703 static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
4704 EVT VT = Op.getValueType();
4705 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
4706 "unexpected type for custom-lowering ISD::SDIV");
4708 DebugLoc dl = Op.getDebugLoc();
4709 SDValue N0 = Op.getOperand(0);
4710 SDValue N1 = Op.getOperand(1);
4713 if (VT == MVT::v8i8) {
4714 N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0);
4715 N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1);
4717 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4718 DAG.getIntPtrConstant(4));
4719 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4720 DAG.getIntPtrConstant(4));
4721 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4722 DAG.getIntPtrConstant(0));
4723 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4724 DAG.getIntPtrConstant(0));
4726 N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16
4727 N2 = LowerSDIV_v4i8(N2, N3, dl, DAG); // v4i16
4729 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
4730 N0 = LowerCONCAT_VECTORS(N0, DAG);
4732 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0);
4735 return LowerSDIV_v4i16(N0, N1, dl, DAG);
4738 static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG) {
4739 EVT VT = Op.getValueType();
4740 assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
4741 "unexpected type for custom-lowering ISD::UDIV");
4743 DebugLoc dl = Op.getDebugLoc();
4744 SDValue N0 = Op.getOperand(0);
4745 SDValue N1 = Op.getOperand(1);
4748 if (VT == MVT::v8i8) {
4749 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0);
4750 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1);
4752 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4753 DAG.getIntPtrConstant(4));
4754 N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4755 DAG.getIntPtrConstant(4));
4756 N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
4757 DAG.getIntPtrConstant(0));
4758 N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
4759 DAG.getIntPtrConstant(0));
4761 N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16
4762 N2 = LowerSDIV_v4i16(N2, N3, dl, DAG); // v4i16
4764 N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
4765 N0 = LowerCONCAT_VECTORS(N0, DAG);
4767 N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8,
4768 DAG.getConstant(Intrinsic::arm_neon_vqmovnsu, MVT::i32),
4773 // v4i16 sdiv ... Convert to float.
4774 // float4 yf = vcvt_f32_s32(vmovl_u16(y));
4775 // float4 xf = vcvt_f32_s32(vmovl_u16(x));
4776 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0);
4777 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1);
4778 N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
4779 SDValue BN1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
4781 // Use reciprocal estimate and two refinement steps.
4782 // float4 recip = vrecpeq_f32(yf);
4783 // recip *= vrecpsq_f32(yf, recip);
4784 // recip *= vrecpsq_f32(yf, recip);
4785 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4786 DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), BN1);
4787 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4788 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
4790 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
4791 N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
4792 DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
4794 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
4795 // Simply multiplying by the reciprocal estimate can leave us a few ulps
4796 // too low, so we add 2 ulps (exhaustive testing shows that this is enough,
4797 // and that it will never cause us to return an answer too large).
4798 // float4 result = as_float4(as_int4(xf*recip) + 2);
4799 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
4800 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
4801 N1 = DAG.getConstant(2, MVT::i32);
4802 N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
4803 N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
4804 N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
4805 // Convert back to integer and return.
4806 // return vmovn_u32(vcvt_s32_f32(result));
4807 N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
4808 N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
4812 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
4813 switch (Op.getOpcode()) {
4814 default: llvm_unreachable("Don't know how to custom lower this!");
4815 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
4816 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
4817 case ISD::GlobalAddress:
4818 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
4819 LowerGlobalAddressELF(Op, DAG);
4820 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
4821 case ISD::SELECT: return LowerSELECT(Op, DAG);
4822 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
4823 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
4824 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
4825 case ISD::VASTART: return LowerVASTART(Op, DAG);
4826 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget);
4827 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG, Subtarget);
4828 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget);
4829 case ISD::SINT_TO_FP:
4830 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
4831 case ISD::FP_TO_SINT:
4832 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
4833 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
4834 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
4835 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
4836 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
4837 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
4838 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
4839 case ISD::EH_SJLJ_DISPATCHSETUP: return LowerEH_SJLJ_DISPATCHSETUP(Op, DAG);
4840 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
4842 case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG);
4845 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
4846 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
4847 case ISD::SRL_PARTS:
4848 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
4849 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
4850 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
4851 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
4852 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
4853 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
4854 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
4855 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
4856 case ISD::MUL: return LowerMUL(Op, DAG);
4857 case ISD::SDIV: return LowerSDIV(Op, DAG);
4858 case ISD::UDIV: return LowerUDIV(Op, DAG);
4863 /// ReplaceNodeResults - Replace the results of node with an illegal result
4864 /// type with new values built out of custom code.
4865 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
4866 SmallVectorImpl<SDValue>&Results,
4867 SelectionDAG &DAG) const {
4869 switch (N->getOpcode()) {
4871 llvm_unreachable("Don't know how to custom expand this!");
4874 Res = ExpandBITCAST(N, DAG);
4878 Res = Expand64BitShift(N, DAG, Subtarget);
4882 Results.push_back(Res);
4885 //===----------------------------------------------------------------------===//
4886 // ARM Scheduler Hooks
4887 //===----------------------------------------------------------------------===//
4890 ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
4891 MachineBasicBlock *BB,
4892 unsigned Size) const {
4893 unsigned dest = MI->getOperand(0).getReg();
4894 unsigned ptr = MI->getOperand(1).getReg();
4895 unsigned oldval = MI->getOperand(2).getReg();
4896 unsigned newval = MI->getOperand(3).getReg();
4897 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4898 DebugLoc dl = MI->getDebugLoc();
4899 bool isThumb2 = Subtarget->isThumb2();
4901 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
4903 MRI.createVirtualRegister(isThumb2 ? ARM::rGPRRegisterClass
4904 : ARM::GPRRegisterClass);
4907 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass);
4908 MRI.constrainRegClass(oldval, ARM::rGPRRegisterClass);
4909 MRI.constrainRegClass(newval, ARM::rGPRRegisterClass);
4912 unsigned ldrOpc, strOpc;
4914 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
4916 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
4917 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
4920 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
4921 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
4924 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
4925 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
4929 MachineFunction *MF = BB->getParent();
4930 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4931 MachineFunction::iterator It = BB;
4932 ++It; // insert the new blocks after the current block
4934 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
4935 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
4936 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
4937 MF->insert(It, loop1MBB);
4938 MF->insert(It, loop2MBB);
4939 MF->insert(It, exitMBB);
4941 // Transfer the remainder of BB and its successor edges to exitMBB.
4942 exitMBB->splice(exitMBB->begin(), BB,
4943 llvm::next(MachineBasicBlock::iterator(MI)),
4945 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4949 // fallthrough --> loop1MBB
4950 BB->addSuccessor(loop1MBB);
4953 // ldrex dest, [ptr]
4957 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
4958 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
4959 .addReg(dest).addReg(oldval));
4960 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4961 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
4962 BB->addSuccessor(loop2MBB);
4963 BB->addSuccessor(exitMBB);
4966 // strex scratch, newval, [ptr]
4970 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval)
4972 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4973 .addReg(scratch).addImm(0));
4974 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4975 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
4976 BB->addSuccessor(loop1MBB);
4977 BB->addSuccessor(exitMBB);
4983 MI->eraseFromParent(); // The instruction is gone now.
4989 ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
4990 unsigned Size, unsigned BinOpcode) const {
4991 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4992 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4994 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4995 MachineFunction *MF = BB->getParent();
4996 MachineFunction::iterator It = BB;
4999 unsigned dest = MI->getOperand(0).getReg();
5000 unsigned ptr = MI->getOperand(1).getReg();
5001 unsigned incr = MI->getOperand(2).getReg();
5002 DebugLoc dl = MI->getDebugLoc();
5003 bool isThumb2 = Subtarget->isThumb2();
5005 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
5007 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass);
5008 MRI.constrainRegClass(ptr, ARM::rGPRRegisterClass);
5011 unsigned ldrOpc, strOpc;
5013 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
5015 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
5016 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
5019 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
5020 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
5023 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
5024 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
5028 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5029 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5030 MF->insert(It, loopMBB);
5031 MF->insert(It, exitMBB);
5033 // Transfer the remainder of BB and its successor edges to exitMBB.
5034 exitMBB->splice(exitMBB->begin(), BB,
5035 llvm::next(MachineBasicBlock::iterator(MI)),
5037 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5039 TargetRegisterClass *TRC =
5040 isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
5041 unsigned scratch = MRI.createVirtualRegister(TRC);
5042 unsigned scratch2 = (!BinOpcode) ? incr : MRI.createVirtualRegister(TRC);
5046 // fallthrough --> loopMBB
5047 BB->addSuccessor(loopMBB);
5051 // <binop> scratch2, dest, incr
5052 // strex scratch, scratch2, ptr
5055 // fallthrough --> exitMBB
5057 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
5059 // operand order needs to go the other way for NAND
5060 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr)
5061 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
5062 addReg(incr).addReg(dest)).addReg(0);
5064 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
5065 addReg(dest).addReg(incr)).addReg(0);
5068 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2)
5070 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5071 .addReg(scratch).addImm(0));
5072 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5073 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5075 BB->addSuccessor(loopMBB);
5076 BB->addSuccessor(exitMBB);
5082 MI->eraseFromParent(); // The instruction is gone now.
5088 ARMTargetLowering::EmitAtomicBinaryMinMax(MachineInstr *MI,
5089 MachineBasicBlock *BB,
5092 ARMCC::CondCodes Cond) const {
5093 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5095 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5096 MachineFunction *MF = BB->getParent();
5097 MachineFunction::iterator It = BB;
5100 unsigned dest = MI->getOperand(0).getReg();
5101 unsigned ptr = MI->getOperand(1).getReg();
5102 unsigned incr = MI->getOperand(2).getReg();
5103 unsigned oldval = dest;
5104 DebugLoc dl = MI->getDebugLoc();
5105 bool isThumb2 = Subtarget->isThumb2();
5107 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
5109 MRI.constrainRegClass(dest, ARM::rGPRRegisterClass);
5110 MRI.constrainRegClass(ptr, ARM::rGPRRegisterClass);
5113 unsigned ldrOpc, strOpc, extendOpc;
5115 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
5117 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
5118 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
5119 extendOpc = isThumb2 ? ARM::t2SXTB : ARM::SXTB;
5122 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
5123 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
5124 extendOpc = isThumb2 ? ARM::t2SXTH : ARM::SXTH;
5127 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
5128 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
5133 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5134 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
5135 MF->insert(It, loopMBB);
5136 MF->insert(It, exitMBB);
5138 // Transfer the remainder of BB and its successor edges to exitMBB.
5139 exitMBB->splice(exitMBB->begin(), BB,
5140 llvm::next(MachineBasicBlock::iterator(MI)),
5142 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5144 TargetRegisterClass *TRC =
5145 isThumb2 ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass;
5146 unsigned scratch = MRI.createVirtualRegister(TRC);
5147 unsigned scratch2 = MRI.createVirtualRegister(TRC);
5151 // fallthrough --> loopMBB
5152 BB->addSuccessor(loopMBB);
5156 // (sign extend dest, if required)
5158 // cmov.cond scratch2, dest, incr
5159 // strex scratch, scratch2, ptr
5162 // fallthrough --> exitMBB
5164 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
5166 // Sign extend the value, if necessary.
5167 if (signExtend && extendOpc) {
5168 oldval = MRI.createVirtualRegister(ARM::GPRRegisterClass);
5169 AddDefaultPred(BuildMI(BB, dl, TII->get(extendOpc), oldval)
5174 // Build compare and cmov instructions.
5175 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
5176 .addReg(oldval).addReg(incr));
5177 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr), scratch2)
5178 .addReg(oldval).addReg(incr).addImm(Cond).addReg(ARM::CPSR);
5180 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2)
5182 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5183 .addReg(scratch).addImm(0));
5184 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5185 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5187 BB->addSuccessor(loopMBB);
5188 BB->addSuccessor(exitMBB);
5194 MI->eraseFromParent(); // The instruction is gone now.
5200 MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
5201 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
5202 E = MBB->succ_end(); I != E; ++I)
5205 llvm_unreachable("Expecting a BB with two successors!");
5208 // FIXME: This opcode table should obviously be expressed in the target
5209 // description. We probably just need a "machine opcode" value in the pseudo
5210 // instruction. But the ideal solution maybe to simply remove the "S" version
5211 // of the opcode altogether.
5212 struct AddSubFlagsOpcodePair {
5214 unsigned MachineOpc;
5217 static AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
5218 {ARM::ADCSri, ARM::ADCri},
5219 {ARM::ADCSrr, ARM::ADCrr},
5220 {ARM::ADCSrsi, ARM::ADCrsi},
5221 {ARM::ADCSrsr, ARM::ADCrsr},
5222 {ARM::SBCSri, ARM::SBCri},
5223 {ARM::SBCSrr, ARM::SBCrr},
5224 {ARM::SBCSrsi, ARM::SBCrsi},
5225 {ARM::SBCSrsr, ARM::SBCrsr},
5226 {ARM::RSBSri, ARM::RSBri},
5227 {ARM::RSBSrr, ARM::RSBrr},
5228 {ARM::RSBSrsi, ARM::RSBrsi},
5229 {ARM::RSBSrsr, ARM::RSBrsr},
5230 {ARM::RSCSri, ARM::RSCri},
5231 {ARM::RSCSrsi, ARM::RSCrsi},
5232 {ARM::RSCSrsr, ARM::RSCrsr},
5233 {ARM::t2ADCSri, ARM::t2ADCri},
5234 {ARM::t2ADCSrr, ARM::t2ADCrr},
5235 {ARM::t2ADCSrs, ARM::t2ADCrs},
5236 {ARM::t2SBCSri, ARM::t2SBCri},
5237 {ARM::t2SBCSrr, ARM::t2SBCrr},
5238 {ARM::t2SBCSrs, ARM::t2SBCrs},
5239 {ARM::t2RSBSri, ARM::t2RSBri},
5240 {ARM::t2RSBSrs, ARM::t2RSBrs},
5243 // Convert and Add or Subtract with Carry and Flags to a generic opcode with
5244 // CPSR<def> operand. e.g. ADCS (...) -> ADC (... CPSR<def>).
5246 // FIXME: Somewhere we should assert that CPSR<def> is in the correct
5247 // position to be recognized by the target descrition as the 'S' bit.
5248 bool ARMTargetLowering::RemapAddSubWithFlags(MachineInstr *MI,
5249 MachineBasicBlock *BB) const {
5250 unsigned OldOpc = MI->getOpcode();
5251 unsigned NewOpc = 0;
5253 // This is only called for instructions that need remapping, so iterating over
5254 // the tiny opcode table is not costly.
5255 static const int NPairs =
5256 sizeof(AddSubFlagsOpcodeMap) / sizeof(AddSubFlagsOpcodePair);
5257 for (AddSubFlagsOpcodePair *Pair = &AddSubFlagsOpcodeMap[0],
5258 *End = &AddSubFlagsOpcodeMap[NPairs]; Pair != End; ++Pair) {
5259 if (OldOpc == Pair->PseudoOpc) {
5260 NewOpc = Pair->MachineOpc;
5267 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5268 DebugLoc dl = MI->getDebugLoc();
5269 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc));
5270 for (unsigned i = 0; i < MI->getNumOperands(); ++i)
5271 MIB.addOperand(MI->getOperand(i));
5272 AddDefaultPred(MIB);
5273 MIB.addReg(ARM::CPSR, RegState::Define); // S bit
5274 MI->eraseFromParent();
5279 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
5280 MachineBasicBlock *BB) const {
5281 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5282 DebugLoc dl = MI->getDebugLoc();
5283 bool isThumb2 = Subtarget->isThumb2();
5284 switch (MI->getOpcode()) {
5286 if (RemapAddSubWithFlags(MI, BB))
5290 llvm_unreachable("Unexpected instr type to insert");
5292 case ARM::ATOMIC_LOAD_ADD_I8:
5293 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
5294 case ARM::ATOMIC_LOAD_ADD_I16:
5295 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
5296 case ARM::ATOMIC_LOAD_ADD_I32:
5297 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
5299 case ARM::ATOMIC_LOAD_AND_I8:
5300 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
5301 case ARM::ATOMIC_LOAD_AND_I16:
5302 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
5303 case ARM::ATOMIC_LOAD_AND_I32:
5304 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
5306 case ARM::ATOMIC_LOAD_OR_I8:
5307 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
5308 case ARM::ATOMIC_LOAD_OR_I16:
5309 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
5310 case ARM::ATOMIC_LOAD_OR_I32:
5311 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
5313 case ARM::ATOMIC_LOAD_XOR_I8:
5314 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
5315 case ARM::ATOMIC_LOAD_XOR_I16:
5316 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
5317 case ARM::ATOMIC_LOAD_XOR_I32:
5318 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
5320 case ARM::ATOMIC_LOAD_NAND_I8:
5321 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
5322 case ARM::ATOMIC_LOAD_NAND_I16:
5323 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
5324 case ARM::ATOMIC_LOAD_NAND_I32:
5325 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
5327 case ARM::ATOMIC_LOAD_SUB_I8:
5328 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
5329 case ARM::ATOMIC_LOAD_SUB_I16:
5330 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
5331 case ARM::ATOMIC_LOAD_SUB_I32:
5332 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
5334 case ARM::ATOMIC_LOAD_MIN_I8:
5335 return EmitAtomicBinaryMinMax(MI, BB, 1, true, ARMCC::LT);
5336 case ARM::ATOMIC_LOAD_MIN_I16:
5337 return EmitAtomicBinaryMinMax(MI, BB, 2, true, ARMCC::LT);
5338 case ARM::ATOMIC_LOAD_MIN_I32:
5339 return EmitAtomicBinaryMinMax(MI, BB, 4, true, ARMCC::LT);
5341 case ARM::ATOMIC_LOAD_MAX_I8:
5342 return EmitAtomicBinaryMinMax(MI, BB, 1, true, ARMCC::GT);
5343 case ARM::ATOMIC_LOAD_MAX_I16:
5344 return EmitAtomicBinaryMinMax(MI, BB, 2, true, ARMCC::GT);
5345 case ARM::ATOMIC_LOAD_MAX_I32:
5346 return EmitAtomicBinaryMinMax(MI, BB, 4, true, ARMCC::GT);
5348 case ARM::ATOMIC_LOAD_UMIN_I8:
5349 return EmitAtomicBinaryMinMax(MI, BB, 1, false, ARMCC::LO);
5350 case ARM::ATOMIC_LOAD_UMIN_I16:
5351 return EmitAtomicBinaryMinMax(MI, BB, 2, false, ARMCC::LO);
5352 case ARM::ATOMIC_LOAD_UMIN_I32:
5353 return EmitAtomicBinaryMinMax(MI, BB, 4, false, ARMCC::LO);
5355 case ARM::ATOMIC_LOAD_UMAX_I8:
5356 return EmitAtomicBinaryMinMax(MI, BB, 1, false, ARMCC::HI);
5357 case ARM::ATOMIC_LOAD_UMAX_I16:
5358 return EmitAtomicBinaryMinMax(MI, BB, 2, false, ARMCC::HI);
5359 case ARM::ATOMIC_LOAD_UMAX_I32:
5360 return EmitAtomicBinaryMinMax(MI, BB, 4, false, ARMCC::HI);
5362 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0);
5363 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0);
5364 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0);
5366 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1);
5367 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
5368 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
5370 case ARM::tMOVCCr_pseudo: {
5371 // To "insert" a SELECT_CC instruction, we actually have to insert the
5372 // diamond control-flow pattern. The incoming instruction knows the
5373 // destination vreg to set, the condition code register to branch on, the
5374 // true/false values to select between, and a branch opcode to use.
5375 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5376 MachineFunction::iterator It = BB;
5382 // cmpTY ccX, r1, r2
5384 // fallthrough --> copy0MBB
5385 MachineBasicBlock *thisMBB = BB;
5386 MachineFunction *F = BB->getParent();
5387 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
5388 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
5389 F->insert(It, copy0MBB);
5390 F->insert(It, sinkMBB);
5392 // Transfer the remainder of BB and its successor edges to sinkMBB.
5393 sinkMBB->splice(sinkMBB->begin(), BB,
5394 llvm::next(MachineBasicBlock::iterator(MI)),
5396 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
5398 BB->addSuccessor(copy0MBB);
5399 BB->addSuccessor(sinkMBB);
5401 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
5402 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
5405 // %FalseValue = ...
5406 // # fallthrough to sinkMBB
5409 // Update machine-CFG edges
5410 BB->addSuccessor(sinkMBB);
5413 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
5416 BuildMI(*BB, BB->begin(), dl,
5417 TII->get(ARM::PHI), MI->getOperand(0).getReg())
5418 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
5419 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
5421 MI->eraseFromParent(); // The pseudo instruction is gone now.
5426 case ARM::BCCZi64: {
5427 // If there is an unconditional branch to the other successor, remove it.
5428 BB->erase(llvm::next(MachineBasicBlock::iterator(MI)), BB->end());
5430 // Compare both parts that make up the double comparison separately for
5432 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
5434 unsigned LHS1 = MI->getOperand(1).getReg();
5435 unsigned LHS2 = MI->getOperand(2).getReg();
5437 AddDefaultPred(BuildMI(BB, dl,
5438 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5439 .addReg(LHS1).addImm(0));
5440 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
5441 .addReg(LHS2).addImm(0)
5442 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
5444 unsigned RHS1 = MI->getOperand(3).getReg();
5445 unsigned RHS2 = MI->getOperand(4).getReg();
5446 AddDefaultPred(BuildMI(BB, dl,
5447 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
5448 .addReg(LHS1).addReg(RHS1));
5449 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
5450 .addReg(LHS2).addReg(RHS2)
5451 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
5454 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB();
5455 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
5456 if (MI->getOperand(0).getImm() == ARMCC::NE)
5457 std::swap(destMBB, exitMBB);
5459 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
5460 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
5461 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2B : ARM::B))
5464 MI->eraseFromParent(); // The pseudo instruction is gone now.
5470 //===----------------------------------------------------------------------===//
5471 // ARM Optimization Hooks
5472 //===----------------------------------------------------------------------===//
5475 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
5476 TargetLowering::DAGCombinerInfo &DCI) {
5477 SelectionDAG &DAG = DCI.DAG;
5478 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5479 EVT VT = N->getValueType(0);
5480 unsigned Opc = N->getOpcode();
5481 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
5482 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
5483 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
5484 ISD::CondCode CC = ISD::SETCC_INVALID;
5487 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
5489 SDValue CCOp = Slct.getOperand(0);
5490 if (CCOp.getOpcode() == ISD::SETCC)
5491 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
5494 bool DoXform = false;
5496 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
5499 if (LHS.getOpcode() == ISD::Constant &&
5500 cast<ConstantSDNode>(LHS)->isNullValue()) {
5502 } else if (CC != ISD::SETCC_INVALID &&
5503 RHS.getOpcode() == ISD::Constant &&
5504 cast<ConstantSDNode>(RHS)->isNullValue()) {
5505 std::swap(LHS, RHS);
5506 SDValue Op0 = Slct.getOperand(0);
5507 EVT OpVT = isSlctCC ? Op0.getValueType() :
5508 Op0.getOperand(0).getValueType();
5509 bool isInt = OpVT.isInteger();
5510 CC = ISD::getSetCCInverse(CC, isInt);
5512 if (!TLI.isCondCodeLegal(CC, OpVT))
5513 return SDValue(); // Inverse operator isn't legal.
5520 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
5522 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
5523 Slct.getOperand(0), Slct.getOperand(1), CC);
5524 SDValue CCOp = Slct.getOperand(0);
5526 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
5527 CCOp.getOperand(0), CCOp.getOperand(1), CC);
5528 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
5529 CCOp, OtherOp, Result);
5534 // AddCombineToVPADDL- For pair-wise add on neon, use the vpaddl instruction
5535 // (only after legalization).
5536 static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1,
5537 TargetLowering::DAGCombinerInfo &DCI,
5538 const ARMSubtarget *Subtarget) {
5540 // Only perform optimization if after legalize, and if NEON is available. We
5541 // also expected both operands to be BUILD_VECTORs.
5542 if (DCI.isBeforeLegalize() || !Subtarget->hasNEON()
5543 || N0.getOpcode() != ISD::BUILD_VECTOR
5544 || N1.getOpcode() != ISD::BUILD_VECTOR)
5547 // Check output type since VPADDL operand elements can only be 8, 16, or 32.
5548 EVT VT = N->getValueType(0);
5549 if (!VT.isInteger() || VT.getVectorElementType() == MVT::i64)
5552 // Check that the vector operands are of the right form.
5553 // N0 and N1 are BUILD_VECTOR nodes with N number of EXTRACT_VECTOR
5554 // operands, where N is the size of the formed vector.
5555 // Each EXTRACT_VECTOR should have the same input vector and odd or even
5556 // index such that we have a pair wise add pattern.
5558 // Grab the vector that all EXTRACT_VECTOR nodes should be referencing.
5559 if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
5561 SDValue Vec = N0->getOperand(0)->getOperand(0);
5562 SDNode *V = Vec.getNode();
5563 unsigned nextIndex = 0;
5565 // For each operands to the ADD which are BUILD_VECTORs,
5566 // check to see if each of their operands are an EXTRACT_VECTOR with
5567 // the same vector and appropriate index.
5568 for (unsigned i = 0, e = N0->getNumOperands(); i != e; ++i) {
5569 if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT
5570 && N1->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
5572 SDValue ExtVec0 = N0->getOperand(i);
5573 SDValue ExtVec1 = N1->getOperand(i);
5575 // First operand is the vector, verify its the same.
5576 if (V != ExtVec0->getOperand(0).getNode() ||
5577 V != ExtVec1->getOperand(0).getNode())
5580 // Second is the constant, verify its correct.
5581 ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(ExtVec0->getOperand(1));
5582 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(ExtVec1->getOperand(1));
5584 // For the constant, we want to see all the even or all the odd.
5585 if (!C0 || !C1 || C0->getZExtValue() != nextIndex
5586 || C1->getZExtValue() != nextIndex+1)
5595 // Create VPADDL node.
5596 SelectionDAG &DAG = DCI.DAG;
5597 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5599 // Build operand list.
5600 SmallVector<SDValue, 8> Ops;
5601 Ops.push_back(DAG.getConstant(Intrinsic::arm_neon_vpaddls,
5602 TLI.getPointerTy()));
5604 // Input is the vector.
5607 // Get widened type and narrowed type.
5609 unsigned numElem = VT.getVectorNumElements();
5610 switch (VT.getVectorElementType().getSimpleVT().SimpleTy) {
5611 case MVT::i8: widenType = MVT::getVectorVT(MVT::i16, numElem); break;
5612 case MVT::i16: widenType = MVT::getVectorVT(MVT::i32, numElem); break;
5613 case MVT::i32: widenType = MVT::getVectorVT(MVT::i64, numElem); break;
5615 assert(0 && "Invalid vector element type for padd optimization.");
5618 SDValue tmp = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(),
5619 widenType, &Ops[0], Ops.size());
5620 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, tmp);
5623 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
5624 /// operands N0 and N1. This is a helper for PerformADDCombine that is
5625 /// called with the default operands, and if that fails, with commuted
5627 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
5628 TargetLowering::DAGCombinerInfo &DCI,
5629 const ARMSubtarget *Subtarget){
5631 // Attempt to create vpaddl for this add.
5632 SDValue Result = AddCombineToVPADDL(N, N0, N1, DCI, Subtarget);
5633 if (Result.getNode())
5636 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
5637 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
5638 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
5639 if (Result.getNode()) return Result;
5644 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
5646 static SDValue PerformADDCombine(SDNode *N,
5647 TargetLowering::DAGCombinerInfo &DCI,
5648 const ARMSubtarget *Subtarget) {
5649 SDValue N0 = N->getOperand(0);
5650 SDValue N1 = N->getOperand(1);
5652 // First try with the default operand order.
5653 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget);
5654 if (Result.getNode())
5657 // If that didn't work, try again with the operands commuted.
5658 return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget);
5661 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
5663 static SDValue PerformSUBCombine(SDNode *N,
5664 TargetLowering::DAGCombinerInfo &DCI) {
5665 SDValue N0 = N->getOperand(0);
5666 SDValue N1 = N->getOperand(1);
5668 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
5669 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
5670 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
5671 if (Result.getNode()) return Result;
5677 /// PerformVMULCombine
5678 /// Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the
5679 /// special multiplier accumulator forwarding.
5685 static SDValue PerformVMULCombine(SDNode *N,
5686 TargetLowering::DAGCombinerInfo &DCI,
5687 const ARMSubtarget *Subtarget) {
5688 if (!Subtarget->hasVMLxForwarding())
5691 SelectionDAG &DAG = DCI.DAG;
5692 SDValue N0 = N->getOperand(0);
5693 SDValue N1 = N->getOperand(1);
5694 unsigned Opcode = N0.getOpcode();
5695 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
5696 Opcode != ISD::FADD && Opcode != ISD::FSUB) {
5697 Opcode = N1.getOpcode();
5698 if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
5699 Opcode != ISD::FADD && Opcode != ISD::FSUB)
5704 EVT VT = N->getValueType(0);
5705 DebugLoc DL = N->getDebugLoc();
5706 SDValue N00 = N0->getOperand(0);
5707 SDValue N01 = N0->getOperand(1);
5708 return DAG.getNode(Opcode, DL, VT,
5709 DAG.getNode(ISD::MUL, DL, VT, N00, N1),
5710 DAG.getNode(ISD::MUL, DL, VT, N01, N1));
5713 static SDValue PerformMULCombine(SDNode *N,
5714 TargetLowering::DAGCombinerInfo &DCI,
5715 const ARMSubtarget *Subtarget) {
5716 SelectionDAG &DAG = DCI.DAG;
5718 if (Subtarget->isThumb1Only())
5721 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
5724 EVT VT = N->getValueType(0);
5725 if (VT.is64BitVector() || VT.is128BitVector())
5726 return PerformVMULCombine(N, DCI, Subtarget);
5730 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
5734 uint64_t MulAmt = C->getZExtValue();
5735 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt);
5736 ShiftAmt = ShiftAmt & (32 - 1);
5737 SDValue V = N->getOperand(0);
5738 DebugLoc DL = N->getDebugLoc();
5741 MulAmt >>= ShiftAmt;
5742 if (isPowerOf2_32(MulAmt - 1)) {
5743 // (mul x, 2^N + 1) => (add (shl x, N), x)
5744 Res = DAG.getNode(ISD::ADD, DL, VT,
5745 V, DAG.getNode(ISD::SHL, DL, VT,
5746 V, DAG.getConstant(Log2_32(MulAmt-1),
5748 } else if (isPowerOf2_32(MulAmt + 1)) {
5749 // (mul x, 2^N - 1) => (sub (shl x, N), x)
5750 Res = DAG.getNode(ISD::SUB, DL, VT,
5751 DAG.getNode(ISD::SHL, DL, VT,
5752 V, DAG.getConstant(Log2_32(MulAmt+1),
5759 Res = DAG.getNode(ISD::SHL, DL, VT, Res,
5760 DAG.getConstant(ShiftAmt, MVT::i32));
5762 // Do not add new nodes to DAG combiner worklist.
5763 DCI.CombineTo(N, Res, false);
5767 static SDValue PerformANDCombine(SDNode *N,
5768 TargetLowering::DAGCombinerInfo &DCI) {
5770 // Attempt to use immediate-form VBIC
5771 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
5772 DebugLoc dl = N->getDebugLoc();
5773 EVT VT = N->getValueType(0);
5774 SelectionDAG &DAG = DCI.DAG;
5776 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
5779 APInt SplatBits, SplatUndef;
5780 unsigned SplatBitSize;
5783 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5784 if (SplatBitSize <= 64) {
5786 SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(),
5787 SplatUndef.getZExtValue(), SplatBitSize,
5788 DAG, VbicVT, VT.is128BitVector(),
5790 if (Val.getNode()) {
5792 DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0));
5793 SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val);
5794 return DAG.getNode(ISD::BITCAST, dl, VT, Vbic);
5802 /// PerformORCombine - Target-specific dag combine xforms for ISD::OR
5803 static SDValue PerformORCombine(SDNode *N,
5804 TargetLowering::DAGCombinerInfo &DCI,
5805 const ARMSubtarget *Subtarget) {
5806 // Attempt to use immediate-form VORR
5807 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
5808 DebugLoc dl = N->getDebugLoc();
5809 EVT VT = N->getValueType(0);
5810 SelectionDAG &DAG = DCI.DAG;
5812 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
5815 APInt SplatBits, SplatUndef;
5816 unsigned SplatBitSize;
5818 if (BVN && Subtarget->hasNEON() &&
5819 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
5820 if (SplatBitSize <= 64) {
5822 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
5823 SplatUndef.getZExtValue(), SplatBitSize,
5824 DAG, VorrVT, VT.is128BitVector(),
5826 if (Val.getNode()) {
5828 DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0));
5829 SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val);
5830 return DAG.getNode(ISD::BITCAST, dl, VT, Vorr);
5835 SDValue N0 = N->getOperand(0);
5836 if (N0.getOpcode() != ISD::AND)
5838 SDValue N1 = N->getOperand(1);
5840 // (or (and B, A), (and C, ~A)) => (VBSL A, B, C) when A is a constant.
5841 if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() &&
5842 DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
5844 unsigned SplatBitSize;
5847 BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1));
5849 if (BVN0 && BVN0->isConstantSplat(SplatBits0, SplatUndef, SplatBitSize,
5850 HasAnyUndefs) && !HasAnyUndefs) {
5851 BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(1));
5853 if (BVN1 && BVN1->isConstantSplat(SplatBits1, SplatUndef, SplatBitSize,
5854 HasAnyUndefs) && !HasAnyUndefs &&
5855 SplatBits0 == ~SplatBits1) {
5856 // Canonicalize the vector type to make instruction selection simpler.
5857 EVT CanonicalVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
5858 SDValue Result = DAG.getNode(ARMISD::VBSL, dl, CanonicalVT,
5859 N0->getOperand(1), N0->getOperand(0),
5861 return DAG.getNode(ISD::BITCAST, dl, VT, Result);
5866 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when
5869 // BFI is only available on V6T2+
5870 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops())
5873 DebugLoc DL = N->getDebugLoc();
5874 // 1) or (and A, mask), val => ARMbfi A, val, mask
5875 // iff (val & mask) == val
5877 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
5878 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2)
5879 // && mask == ~mask2
5880 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2)
5881 // && ~mask == mask2
5882 // (i.e., copy a bitfield value into another bitfield of the same width)
5887 SDValue N00 = N0.getOperand(0);
5889 // The value and the mask need to be constants so we can verify this is
5890 // actually a bitfield set. If the mask is 0xffff, we can do better
5891 // via a movt instruction, so don't use BFI in that case.
5892 SDValue MaskOp = N0.getOperand(1);
5893 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(MaskOp);
5896 unsigned Mask = MaskC->getZExtValue();
5900 // Case (1): or (and A, mask), val => ARMbfi A, val, mask
5901 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
5903 unsigned Val = N1C->getZExtValue();
5904 if ((Val & ~Mask) != Val)
5907 if (ARM::isBitFieldInvertedMask(Mask)) {
5908 Val >>= CountTrailingZeros_32(~Mask);
5910 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00,
5911 DAG.getConstant(Val, MVT::i32),
5912 DAG.getConstant(Mask, MVT::i32));
5914 // Do not add new nodes to DAG combiner worklist.
5915 DCI.CombineTo(N, Res, false);
5918 } else if (N1.getOpcode() == ISD::AND) {
5919 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
5920 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
5923 unsigned Mask2 = N11C->getZExtValue();
5925 // Mask and ~Mask2 (or reverse) must be equivalent for the BFI pattern
5927 if (ARM::isBitFieldInvertedMask(Mask) &&
5929 // The pack halfword instruction works better for masks that fit it,
5930 // so use that when it's available.
5931 if (Subtarget->hasT2ExtractPack() &&
5932 (Mask == 0xffff || Mask == 0xffff0000))
5935 unsigned amt = CountTrailingZeros_32(Mask2);
5936 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
5937 DAG.getConstant(amt, MVT::i32));
5938 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res,
5939 DAG.getConstant(Mask, MVT::i32));
5940 // Do not add new nodes to DAG combiner worklist.
5941 DCI.CombineTo(N, Res, false);
5943 } else if (ARM::isBitFieldInvertedMask(~Mask) &&
5945 // The pack halfword instruction works better for masks that fit it,
5946 // so use that when it's available.
5947 if (Subtarget->hasT2ExtractPack() &&
5948 (Mask2 == 0xffff || Mask2 == 0xffff0000))
5951 unsigned lsb = CountTrailingZeros_32(Mask);
5952 Res = DAG.getNode(ISD::SRL, DL, VT, N00,
5953 DAG.getConstant(lsb, MVT::i32));
5954 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
5955 DAG.getConstant(Mask2, MVT::i32));
5956 // Do not add new nodes to DAG combiner worklist.
5957 DCI.CombineTo(N, Res, false);
5962 if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) &&
5963 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) &&
5964 ARM::isBitFieldInvertedMask(~Mask)) {
5965 // Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask
5966 // where lsb(mask) == #shamt and masked bits of B are known zero.
5967 SDValue ShAmt = N00.getOperand(1);
5968 unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue();
5969 unsigned LSB = CountTrailingZeros_32(Mask);
5973 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0),
5974 DAG.getConstant(~Mask, MVT::i32));
5976 // Do not add new nodes to DAG combiner worklist.
5977 DCI.CombineTo(N, Res, false);
5983 /// PerformBFICombine - (bfi A, (and B, Mask1), Mask2) -> (bfi A, B, Mask2) iff
5984 /// the bits being cleared by the AND are not demanded by the BFI.
5985 static SDValue PerformBFICombine(SDNode *N,
5986 TargetLowering::DAGCombinerInfo &DCI) {
5987 SDValue N1 = N->getOperand(1);
5988 if (N1.getOpcode() == ISD::AND) {
5989 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
5992 unsigned InvMask = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
5993 unsigned LSB = CountTrailingZeros_32(~InvMask);
5994 unsigned Width = (32 - CountLeadingZeros_32(~InvMask)) - LSB;
5995 unsigned Mask = (1 << Width)-1;
5996 unsigned Mask2 = N11C->getZExtValue();
5997 if ((Mask & (~Mask2)) == 0)
5998 return DCI.DAG.getNode(ARMISD::BFI, N->getDebugLoc(), N->getValueType(0),
5999 N->getOperand(0), N1.getOperand(0),
6005 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
6006 /// ARMISD::VMOVRRD.
6007 static SDValue PerformVMOVRRDCombine(SDNode *N,
6008 TargetLowering::DAGCombinerInfo &DCI) {
6009 // vmovrrd(vmovdrr x, y) -> x,y
6010 SDValue InDouble = N->getOperand(0);
6011 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
6012 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
6014 // vmovrrd(load f64) -> (load i32), (load i32)
6015 SDNode *InNode = InDouble.getNode();
6016 if (ISD::isNormalLoad(InNode) && InNode->hasOneUse() &&
6017 InNode->getValueType(0) == MVT::f64 &&
6018 InNode->getOperand(1).getOpcode() == ISD::FrameIndex &&
6019 !cast<LoadSDNode>(InNode)->isVolatile()) {
6020 // TODO: Should this be done for non-FrameIndex operands?
6021 LoadSDNode *LD = cast<LoadSDNode>(InNode);
6023 SelectionDAG &DAG = DCI.DAG;
6024 DebugLoc DL = LD->getDebugLoc();
6025 SDValue BasePtr = LD->getBasePtr();
6026 SDValue NewLD1 = DAG.getLoad(MVT::i32, DL, LD->getChain(), BasePtr,
6027 LD->getPointerInfo(), LD->isVolatile(),
6028 LD->isNonTemporal(), LD->getAlignment());
6030 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
6031 DAG.getConstant(4, MVT::i32));
6032 SDValue NewLD2 = DAG.getLoad(MVT::i32, DL, NewLD1.getValue(1), OffsetPtr,
6033 LD->getPointerInfo(), LD->isVolatile(),
6034 LD->isNonTemporal(),
6035 std::min(4U, LD->getAlignment() / 2));
6037 DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), NewLD2.getValue(1));
6038 SDValue Result = DCI.CombineTo(N, NewLD1, NewLD2);
6039 DCI.RemoveFromWorklist(LD);
6047 /// PerformVMOVDRRCombine - Target-specific dag combine xforms for
6048 /// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands.
6049 static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) {
6050 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X)
6051 SDValue Op0 = N->getOperand(0);
6052 SDValue Op1 = N->getOperand(1);
6053 if (Op0.getOpcode() == ISD::BITCAST)
6054 Op0 = Op0.getOperand(0);
6055 if (Op1.getOpcode() == ISD::BITCAST)
6056 Op1 = Op1.getOperand(0);
6057 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
6058 Op0.getNode() == Op1.getNode() &&
6059 Op0.getResNo() == 0 && Op1.getResNo() == 1)
6060 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
6061 N->getValueType(0), Op0.getOperand(0));
6065 /// PerformSTORECombine - Target-specific dag combine xforms for
6067 static SDValue PerformSTORECombine(SDNode *N,
6068 TargetLowering::DAGCombinerInfo &DCI) {
6069 // Bitcast an i64 store extracted from a vector to f64.
6070 // Otherwise, the i64 value will be legalized to a pair of i32 values.
6071 StoreSDNode *St = cast<StoreSDNode>(N);
6072 SDValue StVal = St->getValue();
6073 if (!ISD::isNormalStore(St) || St->isVolatile())
6076 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR &&
6077 StVal.getNode()->hasOneUse() && !St->isVolatile()) {
6078 SelectionDAG &DAG = DCI.DAG;
6079 DebugLoc DL = St->getDebugLoc();
6080 SDValue BasePtr = St->getBasePtr();
6081 SDValue NewST1 = DAG.getStore(St->getChain(), DL,
6082 StVal.getNode()->getOperand(0), BasePtr,
6083 St->getPointerInfo(), St->isVolatile(),
6084 St->isNonTemporal(), St->getAlignment());
6086 SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
6087 DAG.getConstant(4, MVT::i32));
6088 return DAG.getStore(NewST1.getValue(0), DL, StVal.getNode()->getOperand(1),
6089 OffsetPtr, St->getPointerInfo(), St->isVolatile(),
6090 St->isNonTemporal(),
6091 std::min(4U, St->getAlignment() / 2));
6094 if (StVal.getValueType() != MVT::i64 ||
6095 StVal.getNode()->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
6098 SelectionDAG &DAG = DCI.DAG;
6099 DebugLoc dl = StVal.getDebugLoc();
6100 SDValue IntVec = StVal.getOperand(0);
6101 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
6102 IntVec.getValueType().getVectorNumElements());
6103 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec);
6104 SDValue ExtElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
6105 Vec, StVal.getOperand(1));
6106 dl = N->getDebugLoc();
6107 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt);
6108 // Make the DAGCombiner fold the bitcasts.
6109 DCI.AddToWorklist(Vec.getNode());
6110 DCI.AddToWorklist(ExtElt.getNode());
6111 DCI.AddToWorklist(V.getNode());
6112 return DAG.getStore(St->getChain(), dl, V, St->getBasePtr(),
6113 St->getPointerInfo(), St->isVolatile(),
6114 St->isNonTemporal(), St->getAlignment(),
6118 /// hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node
6119 /// are normal, non-volatile loads. If so, it is profitable to bitcast an
6120 /// i64 vector to have f64 elements, since the value can then be loaded
6121 /// directly into a VFP register.
6122 static bool hasNormalLoadOperand(SDNode *N) {
6123 unsigned NumElts = N->getValueType(0).getVectorNumElements();
6124 for (unsigned i = 0; i < NumElts; ++i) {
6125 SDNode *Elt = N->getOperand(i).getNode();
6126 if (ISD::isNormalLoad(Elt) && !cast<LoadSDNode>(Elt)->isVolatile())
6132 /// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for
6133 /// ISD::BUILD_VECTOR.
6134 static SDValue PerformBUILD_VECTORCombine(SDNode *N,
6135 TargetLowering::DAGCombinerInfo &DCI){
6136 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X):
6137 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value
6138 // into a pair of GPRs, which is fine when the value is used as a scalar,
6139 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD.
6140 SelectionDAG &DAG = DCI.DAG;
6141 if (N->getNumOperands() == 2) {
6142 SDValue RV = PerformVMOVDRRCombine(N, DAG);
6147 // Load i64 elements as f64 values so that type legalization does not split
6148 // them up into i32 values.
6149 EVT VT = N->getValueType(0);
6150 if (VT.getVectorElementType() != MVT::i64 || !hasNormalLoadOperand(N))
6152 DebugLoc dl = N->getDebugLoc();
6153 SmallVector<SDValue, 8> Ops;
6154 unsigned NumElts = VT.getVectorNumElements();
6155 for (unsigned i = 0; i < NumElts; ++i) {
6156 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(i));
6158 // Make the DAGCombiner fold the bitcast.
6159 DCI.AddToWorklist(V.getNode());
6161 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, NumElts);
6162 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, FloatVT, Ops.data(), NumElts);
6163 return DAG.getNode(ISD::BITCAST, dl, VT, BV);
6166 /// PerformInsertEltCombine - Target-specific dag combine xforms for
6167 /// ISD::INSERT_VECTOR_ELT.
6168 static SDValue PerformInsertEltCombine(SDNode *N,
6169 TargetLowering::DAGCombinerInfo &DCI) {
6170 // Bitcast an i64 load inserted into a vector to f64.
6171 // Otherwise, the i64 value will be legalized to a pair of i32 values.
6172 EVT VT = N->getValueType(0);
6173 SDNode *Elt = N->getOperand(1).getNode();
6174 if (VT.getVectorElementType() != MVT::i64 ||
6175 !ISD::isNormalLoad(Elt) || cast<LoadSDNode>(Elt)->isVolatile())
6178 SelectionDAG &DAG = DCI.DAG;
6179 DebugLoc dl = N->getDebugLoc();
6180 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
6181 VT.getVectorNumElements());
6182 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, N->getOperand(0));
6183 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(1));
6184 // Make the DAGCombiner fold the bitcasts.
6185 DCI.AddToWorklist(Vec.getNode());
6186 DCI.AddToWorklist(V.getNode());
6187 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT,
6188 Vec, V, N->getOperand(2));
6189 return DAG.getNode(ISD::BITCAST, dl, VT, InsElt);
6192 /// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for
6193 /// ISD::VECTOR_SHUFFLE.
6194 static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) {
6195 // The LLVM shufflevector instruction does not require the shuffle mask
6196 // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does
6197 // have that requirement. When translating to ISD::VECTOR_SHUFFLE, if the
6198 // operands do not match the mask length, they are extended by concatenating
6199 // them with undef vectors. That is probably the right thing for other
6200 // targets, but for NEON it is better to concatenate two double-register
6201 // size vector operands into a single quad-register size vector. Do that
6202 // transformation here:
6203 // shuffle(concat(v1, undef), concat(v2, undef)) ->
6204 // shuffle(concat(v1, v2), undef)
6205 SDValue Op0 = N->getOperand(0);
6206 SDValue Op1 = N->getOperand(1);
6207 if (Op0.getOpcode() != ISD::CONCAT_VECTORS ||
6208 Op1.getOpcode() != ISD::CONCAT_VECTORS ||
6209 Op0.getNumOperands() != 2 ||
6210 Op1.getNumOperands() != 2)
6212 SDValue Concat0Op1 = Op0.getOperand(1);
6213 SDValue Concat1Op1 = Op1.getOperand(1);
6214 if (Concat0Op1.getOpcode() != ISD::UNDEF ||
6215 Concat1Op1.getOpcode() != ISD::UNDEF)
6217 // Skip the transformation if any of the types are illegal.
6218 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6219 EVT VT = N->getValueType(0);
6220 if (!TLI.isTypeLegal(VT) ||
6221 !TLI.isTypeLegal(Concat0Op1.getValueType()) ||
6222 !TLI.isTypeLegal(Concat1Op1.getValueType()))
6225 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT,
6226 Op0.getOperand(0), Op1.getOperand(0));
6227 // Translate the shuffle mask.
6228 SmallVector<int, 16> NewMask;
6229 unsigned NumElts = VT.getVectorNumElements();
6230 unsigned HalfElts = NumElts/2;
6231 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
6232 for (unsigned n = 0; n < NumElts; ++n) {
6233 int MaskElt = SVN->getMaskElt(n);
6235 if (MaskElt < (int)HalfElts)
6237 else if (MaskElt >= (int)NumElts && MaskElt < (int)(NumElts + HalfElts))
6238 NewElt = HalfElts + MaskElt - NumElts;
6239 NewMask.push_back(NewElt);
6241 return DAG.getVectorShuffle(VT, N->getDebugLoc(), NewConcat,
6242 DAG.getUNDEF(VT), NewMask.data());
6245 /// CombineBaseUpdate - Target-specific DAG combine function for VLDDUP and
6246 /// NEON load/store intrinsics to merge base address updates.
6247 static SDValue CombineBaseUpdate(SDNode *N,
6248 TargetLowering::DAGCombinerInfo &DCI) {
6249 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
6252 SelectionDAG &DAG = DCI.DAG;
6253 bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID ||
6254 N->getOpcode() == ISD::INTRINSIC_W_CHAIN);
6255 unsigned AddrOpIdx = (isIntrinsic ? 2 : 1);
6256 SDValue Addr = N->getOperand(AddrOpIdx);
6258 // Search for a use of the address operand that is an increment.
6259 for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
6260 UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
6262 if (User->getOpcode() != ISD::ADD ||
6263 UI.getUse().getResNo() != Addr.getResNo())
6266 // Check that the add is independent of the load/store. Otherwise, folding
6267 // it would create a cycle.
6268 if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
6271 // Find the new opcode for the updating load/store.
6273 bool isLaneOp = false;
6274 unsigned NewOpc = 0;
6275 unsigned NumVecs = 0;
6277 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
6279 default: assert(0 && "unexpected intrinsic for Neon base update");
6280 case Intrinsic::arm_neon_vld1: NewOpc = ARMISD::VLD1_UPD;
6282 case Intrinsic::arm_neon_vld2: NewOpc = ARMISD::VLD2_UPD;
6284 case Intrinsic::arm_neon_vld3: NewOpc = ARMISD::VLD3_UPD;
6286 case Intrinsic::arm_neon_vld4: NewOpc = ARMISD::VLD4_UPD;
6288 case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD;
6289 NumVecs = 2; isLaneOp = true; break;
6290 case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD;
6291 NumVecs = 3; isLaneOp = true; break;
6292 case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD;
6293 NumVecs = 4; isLaneOp = true; break;
6294 case Intrinsic::arm_neon_vst1: NewOpc = ARMISD::VST1_UPD;
6295 NumVecs = 1; isLoad = false; break;
6296 case Intrinsic::arm_neon_vst2: NewOpc = ARMISD::VST2_UPD;
6297 NumVecs = 2; isLoad = false; break;
6298 case Intrinsic::arm_neon_vst3: NewOpc = ARMISD::VST3_UPD;
6299 NumVecs = 3; isLoad = false; break;
6300 case Intrinsic::arm_neon_vst4: NewOpc = ARMISD::VST4_UPD;
6301 NumVecs = 4; isLoad = false; break;
6302 case Intrinsic::arm_neon_vst2lane: NewOpc = ARMISD::VST2LN_UPD;
6303 NumVecs = 2; isLoad = false; isLaneOp = true; break;
6304 case Intrinsic::arm_neon_vst3lane: NewOpc = ARMISD::VST3LN_UPD;
6305 NumVecs = 3; isLoad = false; isLaneOp = true; break;
6306 case Intrinsic::arm_neon_vst4lane: NewOpc = ARMISD::VST4LN_UPD;
6307 NumVecs = 4; isLoad = false; isLaneOp = true; break;
6311 switch (N->getOpcode()) {
6312 default: assert(0 && "unexpected opcode for Neon base update");
6313 case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break;
6314 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break;
6315 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break;
6319 // Find the size of memory referenced by the load/store.
6322 VecTy = N->getValueType(0);
6324 VecTy = N->getOperand(AddrOpIdx+1).getValueType();
6325 unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
6327 NumBytes /= VecTy.getVectorNumElements();
6329 // If the increment is a constant, it must match the memory ref size.
6330 SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
6331 if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
6332 uint64_t IncVal = CInc->getZExtValue();
6333 if (IncVal != NumBytes)
6335 } else if (NumBytes >= 3 * 16) {
6336 // VLD3/4 and VST3/4 for 128-bit vectors are implemented with two
6337 // separate instructions that make it harder to use a non-constant update.
6341 // Create the new updating load/store node.
6343 unsigned NumResultVecs = (isLoad ? NumVecs : 0);
6345 for (n = 0; n < NumResultVecs; ++n)
6347 Tys[n++] = MVT::i32;
6348 Tys[n] = MVT::Other;
6349 SDVTList SDTys = DAG.getVTList(Tys, NumResultVecs+2);
6350 SmallVector<SDValue, 8> Ops;
6351 Ops.push_back(N->getOperand(0)); // incoming chain
6352 Ops.push_back(N->getOperand(AddrOpIdx));
6354 for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands(); ++i) {
6355 Ops.push_back(N->getOperand(i));
6357 MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
6358 SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, N->getDebugLoc(), SDTys,
6359 Ops.data(), Ops.size(),
6360 MemInt->getMemoryVT(),
6361 MemInt->getMemOperand());
6364 std::vector<SDValue> NewResults;
6365 for (unsigned i = 0; i < NumResultVecs; ++i) {
6366 NewResults.push_back(SDValue(UpdN.getNode(), i));
6368 NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs+1)); // chain
6369 DCI.CombineTo(N, NewResults);
6370 DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
6377 /// CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a
6378 /// vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic
6379 /// are also VDUPLANEs. If so, combine them to a vldN-dup operation and
6381 static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
6382 SelectionDAG &DAG = DCI.DAG;
6383 EVT VT = N->getValueType(0);
6384 // vldN-dup instructions only support 64-bit vectors for N > 1.
6385 if (!VT.is64BitVector())
6388 // Check if the VDUPLANE operand is a vldN-dup intrinsic.
6389 SDNode *VLD = N->getOperand(0).getNode();
6390 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN)
6392 unsigned NumVecs = 0;
6393 unsigned NewOpc = 0;
6394 unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue();
6395 if (IntNo == Intrinsic::arm_neon_vld2lane) {
6397 NewOpc = ARMISD::VLD2DUP;
6398 } else if (IntNo == Intrinsic::arm_neon_vld3lane) {
6400 NewOpc = ARMISD::VLD3DUP;
6401 } else if (IntNo == Intrinsic::arm_neon_vld4lane) {
6403 NewOpc = ARMISD::VLD4DUP;
6408 // First check that all the vldN-lane uses are VDUPLANEs and that the lane
6409 // numbers match the load.
6410 unsigned VLDLaneNo =
6411 cast<ConstantSDNode>(VLD->getOperand(NumVecs+3))->getZExtValue();
6412 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
6414 // Ignore uses of the chain result.
6415 if (UI.getUse().getResNo() == NumVecs)
6418 if (User->getOpcode() != ARMISD::VDUPLANE ||
6419 VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue())
6423 // Create the vldN-dup node.
6426 for (n = 0; n < NumVecs; ++n)
6428 Tys[n] = MVT::Other;
6429 SDVTList SDTys = DAG.getVTList(Tys, NumVecs+1);
6430 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) };
6431 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD);
6432 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, VLD->getDebugLoc(), SDTys,
6433 Ops, 2, VLDMemInt->getMemoryVT(),
6434 VLDMemInt->getMemOperand());
6437 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
6439 unsigned ResNo = UI.getUse().getResNo();
6440 // Ignore uses of the chain result.
6441 if (ResNo == NumVecs)
6444 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo));
6447 // Now the vldN-lane intrinsic is dead except for its chain result.
6448 // Update uses of the chain.
6449 std::vector<SDValue> VLDDupResults;
6450 for (unsigned n = 0; n < NumVecs; ++n)
6451 VLDDupResults.push_back(SDValue(VLDDup.getNode(), n));
6452 VLDDupResults.push_back(SDValue(VLDDup.getNode(), NumVecs));
6453 DCI.CombineTo(VLD, VLDDupResults);
6458 /// PerformVDUPLANECombine - Target-specific dag combine xforms for
6459 /// ARMISD::VDUPLANE.
6460 static SDValue PerformVDUPLANECombine(SDNode *N,
6461 TargetLowering::DAGCombinerInfo &DCI) {
6462 SDValue Op = N->getOperand(0);
6464 // If the source is a vldN-lane (N > 1) intrinsic, and all the other uses
6465 // of that intrinsic are also VDUPLANEs, combine them to a vldN-dup operation.
6466 if (CombineVLDDUP(N, DCI))
6467 return SDValue(N, 0);
6469 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
6470 // redundant. Ignore bit_converts for now; element sizes are checked below.
6471 while (Op.getOpcode() == ISD::BITCAST)
6472 Op = Op.getOperand(0);
6473 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
6476 // Make sure the VMOV element size is not bigger than the VDUPLANE elements.
6477 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits();
6478 // The canonical VMOV for a zero vector uses a 32-bit element size.
6479 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6481 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
6483 EVT VT = N->getValueType(0);
6484 if (EltSize > VT.getVectorElementType().getSizeInBits())
6487 return DCI.DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
6490 // isConstVecPow2 - Return true if each vector element is a power of 2, all
6491 // elements are the same constant, C, and Log2(C) ranges from 1 to 32.
6492 static bool isConstVecPow2(SDValue ConstVec, bool isSigned, uint64_t &C)
6496 for (unsigned I = 0, E = ConstVec.getValueType().getVectorNumElements();
6498 ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(ConstVec.getOperand(I));
6503 APFloat APF = C->getValueAPF();
6504 if (APF.convertToInteger(&cN, 64, isSigned, APFloat::rmTowardZero, &isExact)
6505 != APFloat::opOK || !isExact)
6508 c0 = (I == 0) ? cN : c0;
6509 if (!isPowerOf2_64(cN) || c0 != cN || Log2_64(c0) < 1 || Log2_64(c0) > 32)
6516 /// PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD)
6517 /// can replace combinations of VMUL and VCVT (floating-point to integer)
6518 /// when the VMUL has a constant operand that is a power of 2.
6520 /// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
6521 /// vmul.f32 d16, d17, d16
6522 /// vcvt.s32.f32 d16, d16
6524 /// vcvt.s32.f32 d16, d16, #3
6525 static SDValue PerformVCVTCombine(SDNode *N,
6526 TargetLowering::DAGCombinerInfo &DCI,
6527 const ARMSubtarget *Subtarget) {
6528 SelectionDAG &DAG = DCI.DAG;
6529 SDValue Op = N->getOperand(0);
6531 if (!Subtarget->hasNEON() || !Op.getValueType().isVector() ||
6532 Op.getOpcode() != ISD::FMUL)
6536 SDValue N0 = Op->getOperand(0);
6537 SDValue ConstVec = Op->getOperand(1);
6538 bool isSigned = N->getOpcode() == ISD::FP_TO_SINT;
6540 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
6541 !isConstVecPow2(ConstVec, isSigned, C))
6544 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfp2fxs :
6545 Intrinsic::arm_neon_vcvtfp2fxu;
6546 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(),
6548 DAG.getConstant(IntrinsicOpcode, MVT::i32), N0,
6549 DAG.getConstant(Log2_64(C), MVT::i32));
6552 /// PerformVDIVCombine - VCVT (fixed-point to floating-point, Advanced SIMD)
6553 /// can replace combinations of VCVT (integer to floating-point) and VDIV
6554 /// when the VDIV has a constant operand that is a power of 2.
6556 /// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
6557 /// vcvt.f32.s32 d16, d16
6558 /// vdiv.f32 d16, d17, d16
6560 /// vcvt.f32.s32 d16, d16, #3
6561 static SDValue PerformVDIVCombine(SDNode *N,
6562 TargetLowering::DAGCombinerInfo &DCI,
6563 const ARMSubtarget *Subtarget) {
6564 SelectionDAG &DAG = DCI.DAG;
6565 SDValue Op = N->getOperand(0);
6566 unsigned OpOpcode = Op.getNode()->getOpcode();
6568 if (!Subtarget->hasNEON() || !N->getValueType(0).isVector() ||
6569 (OpOpcode != ISD::SINT_TO_FP && OpOpcode != ISD::UINT_TO_FP))
6573 SDValue ConstVec = N->getOperand(1);
6574 bool isSigned = OpOpcode == ISD::SINT_TO_FP;
6576 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
6577 !isConstVecPow2(ConstVec, isSigned, C))
6580 unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfxs2fp :
6581 Intrinsic::arm_neon_vcvtfxu2fp;
6582 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(),
6584 DAG.getConstant(IntrinsicOpcode, MVT::i32),
6585 Op.getOperand(0), DAG.getConstant(Log2_64(C), MVT::i32));
6588 /// Getvshiftimm - Check if this is a valid build_vector for the immediate
6589 /// operand of a vector shift operation, where all the elements of the
6590 /// build_vector must have the same constant integer value.
6591 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
6592 // Ignore bit_converts.
6593 while (Op.getOpcode() == ISD::BITCAST)
6594 Op = Op.getOperand(0);
6595 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
6596 APInt SplatBits, SplatUndef;
6597 unsigned SplatBitSize;
6599 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
6600 HasAnyUndefs, ElementBits) ||
6601 SplatBitSize > ElementBits)
6603 Cnt = SplatBits.getSExtValue();
6607 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
6608 /// operand of a vector shift left operation. That value must be in the range:
6609 /// 0 <= Value < ElementBits for a left shift; or
6610 /// 0 <= Value <= ElementBits for a long left shift.
6611 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
6612 assert(VT.isVector() && "vector shift count is not a vector type");
6613 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
6614 if (! getVShiftImm(Op, ElementBits, Cnt))
6616 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
6619 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
6620 /// operand of a vector shift right operation. For a shift opcode, the value
6621 /// is positive, but for an intrinsic the value count must be negative. The
6622 /// absolute value must be in the range:
6623 /// 1 <= |Value| <= ElementBits for a right shift; or
6624 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
6625 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
6627 assert(VT.isVector() && "vector shift count is not a vector type");
6628 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
6629 if (! getVShiftImm(Op, ElementBits, Cnt))
6633 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
6636 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
6637 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
6638 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
6641 // Don't do anything for most intrinsics.
6644 // Vector shifts: check for immediate versions and lower them.
6645 // Note: This is done during DAG combining instead of DAG legalizing because
6646 // the build_vectors for 64-bit vector element shift counts are generally
6647 // not legal, and it is hard to see their values after they get legalized to
6648 // loads from a constant pool.
6649 case Intrinsic::arm_neon_vshifts:
6650 case Intrinsic::arm_neon_vshiftu:
6651 case Intrinsic::arm_neon_vshiftls:
6652 case Intrinsic::arm_neon_vshiftlu:
6653 case Intrinsic::arm_neon_vshiftn:
6654 case Intrinsic::arm_neon_vrshifts:
6655 case Intrinsic::arm_neon_vrshiftu:
6656 case Intrinsic::arm_neon_vrshiftn:
6657 case Intrinsic::arm_neon_vqshifts:
6658 case Intrinsic::arm_neon_vqshiftu:
6659 case Intrinsic::arm_neon_vqshiftsu:
6660 case Intrinsic::arm_neon_vqshiftns:
6661 case Intrinsic::arm_neon_vqshiftnu:
6662 case Intrinsic::arm_neon_vqshiftnsu:
6663 case Intrinsic::arm_neon_vqrshiftns:
6664 case Intrinsic::arm_neon_vqrshiftnu:
6665 case Intrinsic::arm_neon_vqrshiftnsu: {
6666 EVT VT = N->getOperand(1).getValueType();
6668 unsigned VShiftOpc = 0;
6671 case Intrinsic::arm_neon_vshifts:
6672 case Intrinsic::arm_neon_vshiftu:
6673 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
6674 VShiftOpc = ARMISD::VSHL;
6677 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
6678 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
6679 ARMISD::VSHRs : ARMISD::VSHRu);
6684 case Intrinsic::arm_neon_vshiftls:
6685 case Intrinsic::arm_neon_vshiftlu:
6686 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
6688 llvm_unreachable("invalid shift count for vshll intrinsic");
6690 case Intrinsic::arm_neon_vrshifts:
6691 case Intrinsic::arm_neon_vrshiftu:
6692 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
6696 case Intrinsic::arm_neon_vqshifts:
6697 case Intrinsic::arm_neon_vqshiftu:
6698 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
6702 case Intrinsic::arm_neon_vqshiftsu:
6703 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
6705 llvm_unreachable("invalid shift count for vqshlu intrinsic");
6707 case Intrinsic::arm_neon_vshiftn:
6708 case Intrinsic::arm_neon_vrshiftn:
6709 case Intrinsic::arm_neon_vqshiftns:
6710 case Intrinsic::arm_neon_vqshiftnu:
6711 case Intrinsic::arm_neon_vqshiftnsu:
6712 case Intrinsic::arm_neon_vqrshiftns:
6713 case Intrinsic::arm_neon_vqrshiftnu:
6714 case Intrinsic::arm_neon_vqrshiftnsu:
6715 // Narrowing shifts require an immediate right shift.
6716 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
6718 llvm_unreachable("invalid shift count for narrowing vector shift "
6722 llvm_unreachable("unhandled vector shift");
6726 case Intrinsic::arm_neon_vshifts:
6727 case Intrinsic::arm_neon_vshiftu:
6728 // Opcode already set above.
6730 case Intrinsic::arm_neon_vshiftls:
6731 case Intrinsic::arm_neon_vshiftlu:
6732 if (Cnt == VT.getVectorElementType().getSizeInBits())
6733 VShiftOpc = ARMISD::VSHLLi;
6735 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
6736 ARMISD::VSHLLs : ARMISD::VSHLLu);
6738 case Intrinsic::arm_neon_vshiftn:
6739 VShiftOpc = ARMISD::VSHRN; break;
6740 case Intrinsic::arm_neon_vrshifts:
6741 VShiftOpc = ARMISD::VRSHRs; break;
6742 case Intrinsic::arm_neon_vrshiftu:
6743 VShiftOpc = ARMISD::VRSHRu; break;
6744 case Intrinsic::arm_neon_vrshiftn:
6745 VShiftOpc = ARMISD::VRSHRN; break;
6746 case Intrinsic::arm_neon_vqshifts:
6747 VShiftOpc = ARMISD::VQSHLs; break;
6748 case Intrinsic::arm_neon_vqshiftu:
6749 VShiftOpc = ARMISD::VQSHLu; break;
6750 case Intrinsic::arm_neon_vqshiftsu:
6751 VShiftOpc = ARMISD::VQSHLsu; break;
6752 case Intrinsic::arm_neon_vqshiftns:
6753 VShiftOpc = ARMISD::VQSHRNs; break;
6754 case Intrinsic::arm_neon_vqshiftnu:
6755 VShiftOpc = ARMISD::VQSHRNu; break;
6756 case Intrinsic::arm_neon_vqshiftnsu:
6757 VShiftOpc = ARMISD::VQSHRNsu; break;
6758 case Intrinsic::arm_neon_vqrshiftns:
6759 VShiftOpc = ARMISD::VQRSHRNs; break;
6760 case Intrinsic::arm_neon_vqrshiftnu:
6761 VShiftOpc = ARMISD::VQRSHRNu; break;
6762 case Intrinsic::arm_neon_vqrshiftnsu:
6763 VShiftOpc = ARMISD::VQRSHRNsu; break;
6766 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
6767 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
6770 case Intrinsic::arm_neon_vshiftins: {
6771 EVT VT = N->getOperand(1).getValueType();
6773 unsigned VShiftOpc = 0;
6775 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
6776 VShiftOpc = ARMISD::VSLI;
6777 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
6778 VShiftOpc = ARMISD::VSRI;
6780 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
6783 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
6784 N->getOperand(1), N->getOperand(2),
6785 DAG.getConstant(Cnt, MVT::i32));
6788 case Intrinsic::arm_neon_vqrshifts:
6789 case Intrinsic::arm_neon_vqrshiftu:
6790 // No immediate versions of these to check for.
6797 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
6798 /// lowers them. As with the vector shift intrinsics, this is done during DAG
6799 /// combining instead of DAG legalizing because the build_vectors for 64-bit
6800 /// vector element shift counts are generally not legal, and it is hard to see
6801 /// their values after they get legalized to loads from a constant pool.
6802 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
6803 const ARMSubtarget *ST) {
6804 EVT VT = N->getValueType(0);
6806 // Nothing to be done for scalar shifts.
6807 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6808 if (!VT.isVector() || !TLI.isTypeLegal(VT))
6811 assert(ST->hasNEON() && "unexpected vector shift");
6814 switch (N->getOpcode()) {
6815 default: llvm_unreachable("unexpected shift opcode");
6818 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
6819 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
6820 DAG.getConstant(Cnt, MVT::i32));
6825 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
6826 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
6827 ARMISD::VSHRs : ARMISD::VSHRu);
6828 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
6829 DAG.getConstant(Cnt, MVT::i32));
6835 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
6836 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
6837 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
6838 const ARMSubtarget *ST) {
6839 SDValue N0 = N->getOperand(0);
6841 // Check for sign- and zero-extensions of vector extract operations of 8-
6842 // and 16-bit vector elements. NEON supports these directly. They are
6843 // handled during DAG combining because type legalization will promote them
6844 // to 32-bit types and it is messy to recognize the operations after that.
6845 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
6846 SDValue Vec = N0.getOperand(0);
6847 SDValue Lane = N0.getOperand(1);
6848 EVT VT = N->getValueType(0);
6849 EVT EltVT = N0.getValueType();
6850 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6852 if (VT == MVT::i32 &&
6853 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
6854 TLI.isTypeLegal(Vec.getValueType()) &&
6855 isa<ConstantSDNode>(Lane)) {
6858 switch (N->getOpcode()) {
6859 default: llvm_unreachable("unexpected opcode");
6860 case ISD::SIGN_EXTEND:
6861 Opc = ARMISD::VGETLANEs;
6863 case ISD::ZERO_EXTEND:
6864 case ISD::ANY_EXTEND:
6865 Opc = ARMISD::VGETLANEu;
6868 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
6875 /// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
6876 /// to match f32 max/min patterns to use NEON vmax/vmin instructions.
6877 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
6878 const ARMSubtarget *ST) {
6879 // If the target supports NEON, try to use vmax/vmin instructions for f32
6880 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set,
6881 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
6882 // a NaN; only do the transformation when it matches that behavior.
6884 // For now only do this when using NEON for FP operations; if using VFP, it
6885 // is not obvious that the benefit outweighs the cost of switching to the
6887 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
6888 N->getValueType(0) != MVT::f32)
6891 SDValue CondLHS = N->getOperand(0);
6892 SDValue CondRHS = N->getOperand(1);
6893 SDValue LHS = N->getOperand(2);
6894 SDValue RHS = N->getOperand(3);
6895 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
6897 unsigned Opcode = 0;
6899 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
6900 IsReversed = false; // x CC y ? x : y
6901 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
6902 IsReversed = true ; // x CC y ? y : x
6916 // If LHS is NaN, an ordered comparison will be false and the result will
6917 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
6918 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
6919 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
6920 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
6922 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
6923 // will return -0, so vmin can only be used for unsafe math or if one of
6924 // the operands is known to be nonzero.
6925 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
6927 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
6929 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
6938 // If LHS is NaN, an ordered comparison will be false and the result will
6939 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
6940 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
6941 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
6942 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
6944 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
6945 // will return +0, so vmax can only be used for unsafe math or if one of
6946 // the operands is known to be nonzero.
6947 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
6949 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
6951 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
6957 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS);
6960 /// PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV.
6962 ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const {
6963 SDValue Cmp = N->getOperand(4);
6964 if (Cmp.getOpcode() != ARMISD::CMPZ)
6965 // Only looking at EQ and NE cases.
6968 EVT VT = N->getValueType(0);
6969 DebugLoc dl = N->getDebugLoc();
6970 SDValue LHS = Cmp.getOperand(0);
6971 SDValue RHS = Cmp.getOperand(1);
6972 SDValue FalseVal = N->getOperand(0);
6973 SDValue TrueVal = N->getOperand(1);
6974 SDValue ARMcc = N->getOperand(2);
6975 ARMCC::CondCodes CC = (ARMCC::CondCodes)cast<ConstantSDNode>(ARMcc)->getZExtValue();
6993 /// FIXME: Turn this into a target neutral optimization?
6995 if (CC == ARMCC::NE && FalseVal == RHS) {
6996 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, TrueVal, ARMcc,
6997 N->getOperand(3), Cmp);
6998 } else if (CC == ARMCC::EQ && TrueVal == RHS) {
7000 SDValue NewCmp = getARMCmp(LHS, RHS, ISD::SETNE, ARMcc, DAG, dl);
7001 Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, FalseVal, ARMcc,
7002 N->getOperand(3), NewCmp);
7005 if (Res.getNode()) {
7006 APInt KnownZero, KnownOne;
7007 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits());
7008 DAG.ComputeMaskedBits(SDValue(N,0), Mask, KnownZero, KnownOne);
7009 // Capture demanded bits information that would be otherwise lost.
7010 if (KnownZero == 0xfffffffe)
7011 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
7012 DAG.getValueType(MVT::i1));
7013 else if (KnownZero == 0xffffff00)
7014 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
7015 DAG.getValueType(MVT::i8));
7016 else if (KnownZero == 0xffff0000)
7017 Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
7018 DAG.getValueType(MVT::i16));
7024 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
7025 DAGCombinerInfo &DCI) const {
7026 switch (N->getOpcode()) {
7028 case ISD::ADD: return PerformADDCombine(N, DCI, Subtarget);
7029 case ISD::SUB: return PerformSUBCombine(N, DCI);
7030 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
7031 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
7032 case ISD::AND: return PerformANDCombine(N, DCI);
7033 case ARMISD::BFI: return PerformBFICombine(N, DCI);
7034 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
7035 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
7036 case ISD::STORE: return PerformSTORECombine(N, DCI);
7037 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI);
7038 case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI);
7039 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
7040 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
7041 case ISD::FP_TO_SINT:
7042 case ISD::FP_TO_UINT: return PerformVCVTCombine(N, DCI, Subtarget);
7043 case ISD::FDIV: return PerformVDIVCombine(N, DCI, Subtarget);
7044 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
7047 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
7048 case ISD::SIGN_EXTEND:
7049 case ISD::ZERO_EXTEND:
7050 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
7051 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
7052 case ARMISD::CMOV: return PerformCMOVCombine(N, DCI.DAG);
7053 case ARMISD::VLD2DUP:
7054 case ARMISD::VLD3DUP:
7055 case ARMISD::VLD4DUP:
7056 return CombineBaseUpdate(N, DCI);
7057 case ISD::INTRINSIC_VOID:
7058 case ISD::INTRINSIC_W_CHAIN:
7059 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
7060 case Intrinsic::arm_neon_vld1:
7061 case Intrinsic::arm_neon_vld2:
7062 case Intrinsic::arm_neon_vld3:
7063 case Intrinsic::arm_neon_vld4:
7064 case Intrinsic::arm_neon_vld2lane:
7065 case Intrinsic::arm_neon_vld3lane:
7066 case Intrinsic::arm_neon_vld4lane:
7067 case Intrinsic::arm_neon_vst1:
7068 case Intrinsic::arm_neon_vst2:
7069 case Intrinsic::arm_neon_vst3:
7070 case Intrinsic::arm_neon_vst4:
7071 case Intrinsic::arm_neon_vst2lane:
7072 case Intrinsic::arm_neon_vst3lane:
7073 case Intrinsic::arm_neon_vst4lane:
7074 return CombineBaseUpdate(N, DCI);
7082 bool ARMTargetLowering::isDesirableToTransformToIntegerOp(unsigned Opc,
7084 return (VT == MVT::f32) && (Opc == ISD::LOAD || Opc == ISD::STORE);
7087 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
7088 if (!Subtarget->allowsUnalignedMem())
7091 switch (VT.getSimpleVT().SimpleTy) {
7098 // FIXME: VLD1 etc with standard alignment is legal.
7102 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
7107 switch (VT.getSimpleVT().SimpleTy) {
7108 default: return false;
7123 if ((V & (Scale - 1)) != 0)
7126 return V == (V & ((1LL << 5) - 1));
7129 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
7130 const ARMSubtarget *Subtarget) {
7137 switch (VT.getSimpleVT().SimpleTy) {
7138 default: return false;
7143 // + imm12 or - imm8
7145 return V == (V & ((1LL << 8) - 1));
7146 return V == (V & ((1LL << 12) - 1));
7149 // Same as ARM mode. FIXME: NEON?
7150 if (!Subtarget->hasVFP2())
7155 return V == (V & ((1LL << 8) - 1));
7159 /// isLegalAddressImmediate - Return true if the integer value can be used
7160 /// as the offset of the target addressing mode for load / store of the
7162 static bool isLegalAddressImmediate(int64_t V, EVT VT,
7163 const ARMSubtarget *Subtarget) {
7170 if (Subtarget->isThumb1Only())
7171 return isLegalT1AddressImmediate(V, VT);
7172 else if (Subtarget->isThumb2())
7173 return isLegalT2AddressImmediate(V, VT, Subtarget);
7178 switch (VT.getSimpleVT().SimpleTy) {
7179 default: return false;
7184 return V == (V & ((1LL << 12) - 1));
7187 return V == (V & ((1LL << 8) - 1));
7190 if (!Subtarget->hasVFP2()) // FIXME: NEON?
7195 return V == (V & ((1LL << 8) - 1));
7199 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
7201 int Scale = AM.Scale;
7205 switch (VT.getSimpleVT().SimpleTy) {
7206 default: return false;
7215 return Scale == 2 || Scale == 4 || Scale == 8;
7218 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
7222 // Note, we allow "void" uses (basically, uses that aren't loads or
7223 // stores), because arm allows folding a scale into many arithmetic
7224 // operations. This should be made more precise and revisited later.
7226 // Allow r << imm, but the imm has to be a multiple of two.
7227 if (Scale & 1) return false;
7228 return isPowerOf2_32(Scale);
7232 /// isLegalAddressingMode - Return true if the addressing mode represented
7233 /// by AM is legal for this target, for a load/store of the specified type.
7234 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
7236 EVT VT = getValueType(Ty, true);
7237 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
7240 // Can never fold addr of global into load/store.
7245 case 0: // no scale reg, must be "r+i" or "r", or "i".
7248 if (Subtarget->isThumb1Only())
7252 // ARM doesn't support any R+R*scale+imm addr modes.
7259 if (Subtarget->isThumb2())
7260 return isLegalT2ScaledAddressingMode(AM, VT);
7262 int Scale = AM.Scale;
7263 switch (VT.getSimpleVT().SimpleTy) {
7264 default: return false;
7268 if (Scale < 0) Scale = -Scale;
7272 return isPowerOf2_32(Scale & ~1);
7276 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
7281 // Note, we allow "void" uses (basically, uses that aren't loads or
7282 // stores), because arm allows folding a scale into many arithmetic
7283 // operations. This should be made more precise and revisited later.
7285 // Allow r << imm, but the imm has to be a multiple of two.
7286 if (Scale & 1) return false;
7287 return isPowerOf2_32(Scale);
7294 /// isLegalICmpImmediate - Return true if the specified immediate is legal
7295 /// icmp immediate, that is the target has icmp instructions which can compare
7296 /// a register against the immediate without having to materialize the
7297 /// immediate into a register.
7298 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
7299 if (!Subtarget->isThumb())
7300 return ARM_AM::getSOImmVal(Imm) != -1;
7301 if (Subtarget->isThumb2())
7302 return ARM_AM::getT2SOImmVal(Imm) != -1;
7303 return Imm >= 0 && Imm <= 255;
7306 /// isLegalAddImmediate - Return true if the specified immediate is legal
7307 /// add immediate, that is the target has add instructions which can add
7308 /// a register with the immediate without having to materialize the
7309 /// immediate into a register.
7310 bool ARMTargetLowering::isLegalAddImmediate(int64_t Imm) const {
7311 return ARM_AM::getSOImmVal(Imm) != -1;
7314 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
7315 bool isSEXTLoad, SDValue &Base,
7316 SDValue &Offset, bool &isInc,
7317 SelectionDAG &DAG) {
7318 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
7321 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
7323 Base = Ptr->getOperand(0);
7324 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
7325 int RHSC = (int)RHS->getZExtValue();
7326 if (RHSC < 0 && RHSC > -256) {
7327 assert(Ptr->getOpcode() == ISD::ADD);
7329 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
7333 isInc = (Ptr->getOpcode() == ISD::ADD);
7334 Offset = Ptr->getOperand(1);
7336 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
7338 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
7339 int RHSC = (int)RHS->getZExtValue();
7340 if (RHSC < 0 && RHSC > -0x1000) {
7341 assert(Ptr->getOpcode() == ISD::ADD);
7343 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
7344 Base = Ptr->getOperand(0);
7349 if (Ptr->getOpcode() == ISD::ADD) {
7351 ARM_AM::ShiftOpc ShOpcVal=
7352 ARM_AM::getShiftOpcForNode(Ptr->getOperand(0).getOpcode());
7353 if (ShOpcVal != ARM_AM::no_shift) {
7354 Base = Ptr->getOperand(1);
7355 Offset = Ptr->getOperand(0);
7357 Base = Ptr->getOperand(0);
7358 Offset = Ptr->getOperand(1);
7363 isInc = (Ptr->getOpcode() == ISD::ADD);
7364 Base = Ptr->getOperand(0);
7365 Offset = Ptr->getOperand(1);
7369 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
7373 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
7374 bool isSEXTLoad, SDValue &Base,
7375 SDValue &Offset, bool &isInc,
7376 SelectionDAG &DAG) {
7377 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
7380 Base = Ptr->getOperand(0);
7381 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
7382 int RHSC = (int)RHS->getZExtValue();
7383 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
7384 assert(Ptr->getOpcode() == ISD::ADD);
7386 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
7388 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
7389 isInc = Ptr->getOpcode() == ISD::ADD;
7390 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
7398 /// getPreIndexedAddressParts - returns true by value, base pointer and
7399 /// offset pointer and addressing mode by reference if the node's address
7400 /// can be legally represented as pre-indexed load / store address.
7402 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
7404 ISD::MemIndexedMode &AM,
7405 SelectionDAG &DAG) const {
7406 if (Subtarget->isThumb1Only())
7411 bool isSEXTLoad = false;
7412 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
7413 Ptr = LD->getBasePtr();
7414 VT = LD->getMemoryVT();
7415 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
7416 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
7417 Ptr = ST->getBasePtr();
7418 VT = ST->getMemoryVT();
7423 bool isLegal = false;
7424 if (Subtarget->isThumb2())
7425 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
7426 Offset, isInc, DAG);
7428 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
7429 Offset, isInc, DAG);
7433 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
7437 /// getPostIndexedAddressParts - returns true by value, base pointer and
7438 /// offset pointer and addressing mode by reference if this node can be
7439 /// combined with a load / store to form a post-indexed load / store.
7440 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
7443 ISD::MemIndexedMode &AM,
7444 SelectionDAG &DAG) const {
7445 if (Subtarget->isThumb1Only())
7450 bool isSEXTLoad = false;
7451 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
7452 VT = LD->getMemoryVT();
7453 Ptr = LD->getBasePtr();
7454 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
7455 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
7456 VT = ST->getMemoryVT();
7457 Ptr = ST->getBasePtr();
7462 bool isLegal = false;
7463 if (Subtarget->isThumb2())
7464 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
7467 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
7473 // Swap base ptr and offset to catch more post-index load / store when
7474 // it's legal. In Thumb2 mode, offset must be an immediate.
7475 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
7476 !Subtarget->isThumb2())
7477 std::swap(Base, Offset);
7479 // Post-indexed load / store update the base pointer.
7484 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
7488 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
7492 const SelectionDAG &DAG,
7493 unsigned Depth) const {
7494 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
7495 switch (Op.getOpcode()) {
7497 case ARMISD::CMOV: {
7498 // Bits are known zero/one if known on the LHS and RHS.
7499 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
7500 if (KnownZero == 0 && KnownOne == 0) return;
7502 APInt KnownZeroRHS, KnownOneRHS;
7503 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
7504 KnownZeroRHS, KnownOneRHS, Depth+1);
7505 KnownZero &= KnownZeroRHS;
7506 KnownOne &= KnownOneRHS;
7512 //===----------------------------------------------------------------------===//
7513 // ARM Inline Assembly Support
7514 //===----------------------------------------------------------------------===//
7516 bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const {
7517 // Looking for "rev" which is V6+.
7518 if (!Subtarget->hasV6Ops())
7521 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
7522 std::string AsmStr = IA->getAsmString();
7523 SmallVector<StringRef, 4> AsmPieces;
7524 SplitString(AsmStr, AsmPieces, ";\n");
7526 switch (AsmPieces.size()) {
7527 default: return false;
7529 AsmStr = AsmPieces[0];
7531 SplitString(AsmStr, AsmPieces, " \t,");
7534 if (AsmPieces.size() == 3 &&
7535 AsmPieces[0] == "rev" && AsmPieces[1] == "$0" && AsmPieces[2] == "$1" &&
7536 IA->getConstraintString().compare(0, 4, "=l,l") == 0) {
7537 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
7538 if (Ty && Ty->getBitWidth() == 32)
7539 return IntrinsicLowering::LowerToByteSwap(CI);
7547 /// getConstraintType - Given a constraint letter, return the type of
7548 /// constraint it is for this target.
7549 ARMTargetLowering::ConstraintType
7550 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
7551 if (Constraint.size() == 1) {
7552 switch (Constraint[0]) {
7554 case 'l': return C_RegisterClass;
7555 case 'w': return C_RegisterClass;
7556 case 'h': return C_RegisterClass;
7557 case 'x': return C_RegisterClass;
7558 case 't': return C_RegisterClass;
7559 case 'j': return C_Other; // Constant for movw.
7560 // An address with a single base register. Due to the way we
7561 // currently handle addresses it is the same as an 'r' memory constraint.
7562 case 'Q': return C_Memory;
7564 } else if (Constraint.size() == 2) {
7565 switch (Constraint[0]) {
7567 // All 'U+' constraints are addresses.
7568 case 'U': return C_Memory;
7571 return TargetLowering::getConstraintType(Constraint);
7574 /// Examine constraint type and operand type and determine a weight value.
7575 /// This object must already have been set up with the operand type
7576 /// and the current alternative constraint selected.
7577 TargetLowering::ConstraintWeight
7578 ARMTargetLowering::getSingleConstraintMatchWeight(
7579 AsmOperandInfo &info, const char *constraint) const {
7580 ConstraintWeight weight = CW_Invalid;
7581 Value *CallOperandVal = info.CallOperandVal;
7582 // If we don't have a value, we can't do a match,
7583 // but allow it at the lowest weight.
7584 if (CallOperandVal == NULL)
7586 Type *type = CallOperandVal->getType();
7587 // Look at the constraint type.
7588 switch (*constraint) {
7590 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
7593 if (type->isIntegerTy()) {
7594 if (Subtarget->isThumb())
7595 weight = CW_SpecificReg;
7597 weight = CW_Register;
7601 if (type->isFloatingPointTy())
7602 weight = CW_Register;
7608 typedef std::pair<unsigned, const TargetRegisterClass*> RCPair;
7610 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
7612 if (Constraint.size() == 1) {
7613 // GCC ARM Constraint Letters
7614 switch (Constraint[0]) {
7615 case 'l': // Low regs or general regs.
7616 if (Subtarget->isThumb())
7617 return RCPair(0U, ARM::tGPRRegisterClass);
7619 return RCPair(0U, ARM::GPRRegisterClass);
7620 case 'h': // High regs or no regs.
7621 if (Subtarget->isThumb())
7622 return RCPair(0U, ARM::hGPRRegisterClass);
7625 return RCPair(0U, ARM::GPRRegisterClass);
7628 return RCPair(0U, ARM::SPRRegisterClass);
7629 if (VT.getSizeInBits() == 64)
7630 return RCPair(0U, ARM::DPRRegisterClass);
7631 if (VT.getSizeInBits() == 128)
7632 return RCPair(0U, ARM::QPRRegisterClass);
7636 return RCPair(0U, ARM::SPR_8RegisterClass);
7637 if (VT.getSizeInBits() == 64)
7638 return RCPair(0U, ARM::DPR_8RegisterClass);
7639 if (VT.getSizeInBits() == 128)
7640 return RCPair(0U, ARM::QPR_8RegisterClass);
7644 return RCPair(0U, ARM::SPRRegisterClass);
7648 if (StringRef("{cc}").equals_lower(Constraint))
7649 return std::make_pair(unsigned(ARM::CPSR), ARM::CCRRegisterClass);
7651 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
7654 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
7655 /// vector. If it is invalid, don't add anything to Ops.
7656 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
7657 std::string &Constraint,
7658 std::vector<SDValue>&Ops,
7659 SelectionDAG &DAG) const {
7660 SDValue Result(0, 0);
7662 // Currently only support length 1 constraints.
7663 if (Constraint.length() != 1) return;
7665 char ConstraintLetter = Constraint[0];
7666 switch (ConstraintLetter) {
7669 case 'I': case 'J': case 'K': case 'L':
7670 case 'M': case 'N': case 'O':
7671 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
7675 int64_t CVal64 = C->getSExtValue();
7676 int CVal = (int) CVal64;
7677 // None of these constraints allow values larger than 32 bits. Check
7678 // that the value fits in an int.
7682 switch (ConstraintLetter) {
7684 // Constant suitable for movw, must be between 0 and
7686 if (Subtarget->hasV6T2Ops())
7687 if (CVal >= 0 && CVal <= 65535)
7691 if (Subtarget->isThumb1Only()) {
7692 // This must be a constant between 0 and 255, for ADD
7694 if (CVal >= 0 && CVal <= 255)
7696 } else if (Subtarget->isThumb2()) {
7697 // A constant that can be used as an immediate value in a
7698 // data-processing instruction.
7699 if (ARM_AM::getT2SOImmVal(CVal) != -1)
7702 // A constant that can be used as an immediate value in a
7703 // data-processing instruction.
7704 if (ARM_AM::getSOImmVal(CVal) != -1)
7710 if (Subtarget->isThumb()) { // FIXME thumb2
7711 // This must be a constant between -255 and -1, for negated ADD
7712 // immediates. This can be used in GCC with an "n" modifier that
7713 // prints the negated value, for use with SUB instructions. It is
7714 // not useful otherwise but is implemented for compatibility.
7715 if (CVal >= -255 && CVal <= -1)
7718 // This must be a constant between -4095 and 4095. It is not clear
7719 // what this constraint is intended for. Implemented for
7720 // compatibility with GCC.
7721 if (CVal >= -4095 && CVal <= 4095)
7727 if (Subtarget->isThumb1Only()) {
7728 // A 32-bit value where only one byte has a nonzero value. Exclude
7729 // zero to match GCC. This constraint is used by GCC internally for
7730 // constants that can be loaded with a move/shift combination.
7731 // It is not useful otherwise but is implemented for compatibility.
7732 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
7734 } else if (Subtarget->isThumb2()) {
7735 // A constant whose bitwise inverse can be used as an immediate
7736 // value in a data-processing instruction. This can be used in GCC
7737 // with a "B" modifier that prints the inverted value, for use with
7738 // BIC and MVN instructions. It is not useful otherwise but is
7739 // implemented for compatibility.
7740 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
7743 // A constant whose bitwise inverse can be used as an immediate
7744 // value in a data-processing instruction. This can be used in GCC
7745 // with a "B" modifier that prints the inverted value, for use with
7746 // BIC and MVN instructions. It is not useful otherwise but is
7747 // implemented for compatibility.
7748 if (ARM_AM::getSOImmVal(~CVal) != -1)
7754 if (Subtarget->isThumb1Only()) {
7755 // This must be a constant between -7 and 7,
7756 // for 3-operand ADD/SUB immediate instructions.
7757 if (CVal >= -7 && CVal < 7)
7759 } else if (Subtarget->isThumb2()) {
7760 // A constant whose negation can be used as an immediate value in a
7761 // data-processing instruction. This can be used in GCC with an "n"
7762 // modifier that prints the negated value, for use with SUB
7763 // instructions. It is not useful otherwise but is implemented for
7765 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
7768 // A constant whose negation can be used as an immediate value in a
7769 // data-processing instruction. This can be used in GCC with an "n"
7770 // modifier that prints the negated value, for use with SUB
7771 // instructions. It is not useful otherwise but is implemented for
7773 if (ARM_AM::getSOImmVal(-CVal) != -1)
7779 if (Subtarget->isThumb()) { // FIXME thumb2
7780 // This must be a multiple of 4 between 0 and 1020, for
7781 // ADD sp + immediate.
7782 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
7785 // A power of two or a constant between 0 and 32. This is used in
7786 // GCC for the shift amount on shifted register operands, but it is
7787 // useful in general for any shift amounts.
7788 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
7794 if (Subtarget->isThumb()) { // FIXME thumb2
7795 // This must be a constant between 0 and 31, for shift amounts.
7796 if (CVal >= 0 && CVal <= 31)
7802 if (Subtarget->isThumb()) { // FIXME thumb2
7803 // This must be a multiple of 4 between -508 and 508, for
7804 // ADD/SUB sp = sp + immediate.
7805 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
7810 Result = DAG.getTargetConstant(CVal, Op.getValueType());
7814 if (Result.getNode()) {
7815 Ops.push_back(Result);
7818 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
7822 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
7823 // The ARM target isn't yet aware of offsets.
7827 int ARM::getVFPf32Imm(const APFloat &FPImm) {
7828 APInt Imm = FPImm.bitcastToAPInt();
7829 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
7830 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127
7831 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits
7833 // We can handle 4 bits of mantissa.
7834 // mantissa = (16+UInt(e:f:g:h))/16.
7835 if (Mantissa & 0x7ffff)
7838 if ((Mantissa & 0xf) != Mantissa)
7841 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
7842 if (Exp < -3 || Exp > 4)
7844 Exp = ((Exp+3) & 0x7) ^ 4;
7846 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
7849 int ARM::getVFPf64Imm(const APFloat &FPImm) {
7850 APInt Imm = FPImm.bitcastToAPInt();
7851 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
7852 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
7853 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffLL;
7855 // We can handle 4 bits of mantissa.
7856 // mantissa = (16+UInt(e:f:g:h))/16.
7857 if (Mantissa & 0xffffffffffffLL)
7860 if ((Mantissa & 0xf) != Mantissa)
7863 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
7864 if (Exp < -3 || Exp > 4)
7866 Exp = ((Exp+3) & 0x7) ^ 4;
7868 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
7871 bool ARM::isBitFieldInvertedMask(unsigned v) {
7872 if (v == 0xffffffff)
7874 // there can be 1's on either or both "outsides", all the "inside"
7876 unsigned int lsb = 0, msb = 31;
7877 while (v & (1 << msb)) --msb;
7878 while (v & (1 << lsb)) ++lsb;
7879 for (unsigned int i = lsb; i <= msb; ++i) {
7886 /// isFPImmLegal - Returns true if the target can instruction select the
7887 /// specified FP immediate natively. If false, the legalizer will
7888 /// materialize the FP immediate as a load from a constant pool.
7889 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
7890 if (!Subtarget->hasVFP3())
7893 return ARM::getVFPf32Imm(Imm) != -1;
7895 return ARM::getVFPf64Imm(Imm) != -1;
7899 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
7900 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
7901 /// specified in the intrinsic calls.
7902 bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
7904 unsigned Intrinsic) const {
7905 switch (Intrinsic) {
7906 case Intrinsic::arm_neon_vld1:
7907 case Intrinsic::arm_neon_vld2:
7908 case Intrinsic::arm_neon_vld3:
7909 case Intrinsic::arm_neon_vld4:
7910 case Intrinsic::arm_neon_vld2lane:
7911 case Intrinsic::arm_neon_vld3lane:
7912 case Intrinsic::arm_neon_vld4lane: {
7913 Info.opc = ISD::INTRINSIC_W_CHAIN;
7914 // Conservatively set memVT to the entire set of vectors loaded.
7915 uint64_t NumElts = getTargetData()->getTypeAllocSize(I.getType()) / 8;
7916 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
7917 Info.ptrVal = I.getArgOperand(0);
7919 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
7920 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
7921 Info.vol = false; // volatile loads with NEON intrinsics not supported
7922 Info.readMem = true;
7923 Info.writeMem = false;
7926 case Intrinsic::arm_neon_vst1:
7927 case Intrinsic::arm_neon_vst2:
7928 case Intrinsic::arm_neon_vst3:
7929 case Intrinsic::arm_neon_vst4:
7930 case Intrinsic::arm_neon_vst2lane:
7931 case Intrinsic::arm_neon_vst3lane:
7932 case Intrinsic::arm_neon_vst4lane: {
7933 Info.opc = ISD::INTRINSIC_VOID;
7934 // Conservatively set memVT to the entire set of vectors stored.
7935 unsigned NumElts = 0;
7936 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
7937 Type *ArgTy = I.getArgOperand(ArgI)->getType();
7938 if (!ArgTy->isVectorTy())
7940 NumElts += getTargetData()->getTypeAllocSize(ArgTy) / 8;
7942 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
7943 Info.ptrVal = I.getArgOperand(0);
7945 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
7946 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
7947 Info.vol = false; // volatile stores with NEON intrinsics not supported
7948 Info.readMem = false;
7949 Info.writeMem = true;
7952 case Intrinsic::arm_strexd: {
7953 Info.opc = ISD::INTRINSIC_W_CHAIN;
7954 Info.memVT = MVT::i64;
7955 Info.ptrVal = I.getArgOperand(2);
7959 Info.readMem = false;
7960 Info.writeMem = true;
7963 case Intrinsic::arm_ldrexd: {
7964 Info.opc = ISD::INTRINSIC_W_CHAIN;
7965 Info.memVT = MVT::i64;
7966 Info.ptrVal = I.getArgOperand(0);
7970 Info.readMem = true;
7971 Info.writeMem = false;