1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Evan Cheng and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
16 #include "ARMAddressingModes.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMISelLowering.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMRegisterInfo.h"
21 #include "ARMSubtarget.h"
22 #include "ARMTargetMachine.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/Constants.h"
25 #include "llvm/Instruction.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/CodeGen/MachineBasicBlock.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineFunction.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/SelectionDAG.h"
32 #include "llvm/CodeGen/SSARegMap.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/ADT/VectorExtras.h"
35 #include "llvm/Support/MathExtras.h"
38 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
39 : TargetLowering(TM), ARMPCLabelIndex(0) {
40 Subtarget = &TM.getSubtarget<ARMSubtarget>();
42 if (Subtarget->isTargetDarwin()) {
44 setLibcallName(RTLIB::UINTTOFP_I64_F32, NULL);
45 setLibcallName(RTLIB::UINTTOFP_I64_F64, NULL);
47 // Uses VFP for Thumb libfuncs if available.
48 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
49 // Single-precision floating-point arithmetic.
50 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
51 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
52 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
53 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
55 // Double-precision floating-point arithmetic.
56 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
57 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
58 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
59 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
61 // Single-precision comparisons.
62 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
63 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
64 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
65 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
66 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
67 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
68 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
69 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
71 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
72 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
73 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
74 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
75 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
76 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
77 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
78 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
80 // Double-precision comparisons.
81 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
82 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
83 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
84 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
85 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
86 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
87 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
88 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
90 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
91 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
92 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
93 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
94 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
95 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
96 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
97 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
99 // Floating-point to integer conversions.
100 // i64 conversions are done via library routines even when generating VFP
101 // instructions, so use the same ones.
102 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
103 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
104 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
105 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
107 // Conversions between floating types.
108 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
109 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
111 // Integer to floating-point conversions.
112 // i64 conversions are done via library routines even when generating VFP
113 // instructions, so use the same ones.
114 // FIXME: There appears to be some naming inconsistency in ARM libgcc: e.g.
115 // __floatunsidf vs. __floatunssidfvfp.
116 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
117 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
118 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
119 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
123 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
124 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) {
125 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
126 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
128 computeRegisterProperties();
130 // ARM does not have f32 extending load.
131 setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
133 // ARM supports all 4 flavors of integer indexed load / store.
134 for (unsigned im = (unsigned)ISD::PRE_INC;
135 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
136 setIndexedLoadAction(im, MVT::i1, Legal);
137 setIndexedLoadAction(im, MVT::i8, Legal);
138 setIndexedLoadAction(im, MVT::i16, Legal);
139 setIndexedLoadAction(im, MVT::i32, Legal);
140 setIndexedStoreAction(im, MVT::i1, Legal);
141 setIndexedStoreAction(im, MVT::i8, Legal);
142 setIndexedStoreAction(im, MVT::i16, Legal);
143 setIndexedStoreAction(im, MVT::i32, Legal);
146 // i64 operation support.
147 if (Subtarget->isThumb()) {
148 setOperationAction(ISD::MUL, MVT::i64, Expand);
149 setOperationAction(ISD::MULHU, MVT::i32, Expand);
150 setOperationAction(ISD::MULHS, MVT::i32, Expand);
151 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
152 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
154 setOperationAction(ISD::MUL, MVT::i64, Expand);
155 setOperationAction(ISD::MULHU, MVT::i32, Expand);
156 if (!Subtarget->hasV6Ops())
157 setOperationAction(ISD::MULHS, MVT::i32, Expand);
159 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
160 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
161 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
162 setOperationAction(ISD::SRL, MVT::i64, Custom);
163 setOperationAction(ISD::SRA, MVT::i64, Custom);
165 // ARM does not have ROTL.
166 setOperationAction(ISD::ROTL, MVT::i32, Expand);
167 setOperationAction(ISD::CTTZ , MVT::i32, Expand);
168 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
169 if (!Subtarget->hasV5TOps() || Subtarget->isThumb())
170 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
172 // Only ARMv6 has BSWAP.
173 if (!Subtarget->hasV6Ops())
174 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
176 // These are expanded into libcalls.
177 setOperationAction(ISD::SDIV, MVT::i32, Expand);
178 setOperationAction(ISD::UDIV, MVT::i32, Expand);
179 setOperationAction(ISD::SREM, MVT::i32, Expand);
180 setOperationAction(ISD::UREM, MVT::i32, Expand);
181 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
182 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
184 // Support label based line numbers.
185 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
186 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
188 setOperationAction(ISD::RET, MVT::Other, Custom);
189 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
190 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
191 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
192 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
194 // Expand mem operations genericly.
195 setOperationAction(ISD::MEMSET , MVT::Other, Expand);
196 setOperationAction(ISD::MEMCPY , MVT::Other, Custom);
197 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
199 // Use the default implementation.
200 setOperationAction(ISD::VASTART , MVT::Other, Expand);
201 setOperationAction(ISD::VAARG , MVT::Other, Expand);
202 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
203 setOperationAction(ISD::VAEND , MVT::Other, Expand);
204 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
205 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
206 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
208 if (!Subtarget->hasV6Ops()) {
209 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
210 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
212 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
214 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb())
215 // Turn f64->i64 into FMRRD iff target supports vfp2.
216 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
218 // We want to custom lower some of our intrinsics.
219 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
221 setOperationAction(ISD::SETCC , MVT::i32, Expand);
222 setOperationAction(ISD::SETCC , MVT::f32, Expand);
223 setOperationAction(ISD::SETCC , MVT::f64, Expand);
224 setOperationAction(ISD::SELECT , MVT::i32, Expand);
225 setOperationAction(ISD::SELECT , MVT::f32, Expand);
226 setOperationAction(ISD::SELECT , MVT::f64, Expand);
227 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
228 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
229 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
231 setOperationAction(ISD::BRCOND , MVT::Other, Expand);
232 setOperationAction(ISD::BR_CC , MVT::i32, Custom);
233 setOperationAction(ISD::BR_CC , MVT::f32, Custom);
234 setOperationAction(ISD::BR_CC , MVT::f64, Custom);
235 setOperationAction(ISD::BR_JT , MVT::Other, Custom);
237 setOperationAction(ISD::VASTART, MVT::Other, Custom);
238 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
239 setOperationAction(ISD::VAEND, MVT::Other, Expand);
240 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
241 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
243 // FP Constants can't be immediates.
244 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
245 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
247 // We don't support sin/cos/fmod/copysign/pow
248 setOperationAction(ISD::FSIN , MVT::f64, Expand);
249 setOperationAction(ISD::FSIN , MVT::f32, Expand);
250 setOperationAction(ISD::FCOS , MVT::f32, Expand);
251 setOperationAction(ISD::FCOS , MVT::f64, Expand);
252 setOperationAction(ISD::FREM , MVT::f64, Expand);
253 setOperationAction(ISD::FREM , MVT::f32, Expand);
254 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
255 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
256 setOperationAction(ISD::FPOW , MVT::f64, Expand);
257 setOperationAction(ISD::FPOW , MVT::f32, Expand);
259 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
260 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
261 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
262 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
263 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
265 setStackPointerRegisterToSaveRestore(ARM::SP);
266 setSchedulingPreference(SchedulingForRegPressure);
267 setIfCvtBlockSizeLimit(Subtarget->isThumb() ? 0 : 10);
268 setIfCvtDupBlockSizeLimit(Subtarget->isThumb() ? 0 : 2);
270 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
274 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
277 case ARMISD::Wrapper: return "ARMISD::Wrapper";
278 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
279 case ARMISD::CALL: return "ARMISD::CALL";
280 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
281 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
282 case ARMISD::tCALL: return "ARMISD::tCALL";
283 case ARMISD::BRCOND: return "ARMISD::BRCOND";
284 case ARMISD::BR_JT: return "ARMISD::BR_JT";
285 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
286 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
287 case ARMISD::CMP: return "ARMISD::CMP";
288 case ARMISD::CMPNZ: return "ARMISD::CMPNZ";
289 case ARMISD::CMPFP: return "ARMISD::CMPFP";
290 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
291 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
292 case ARMISD::CMOV: return "ARMISD::CMOV";
293 case ARMISD::CNEG: return "ARMISD::CNEG";
295 case ARMISD::FTOSI: return "ARMISD::FTOSI";
296 case ARMISD::FTOUI: return "ARMISD::FTOUI";
297 case ARMISD::SITOF: return "ARMISD::SITOF";
298 case ARMISD::UITOF: return "ARMISD::UITOF";
300 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
301 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
302 case ARMISD::RRX: return "ARMISD::RRX";
304 case ARMISD::FMRRD: return "ARMISD::FMRRD";
305 case ARMISD::FMDRR: return "ARMISD::FMDRR";
307 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
311 //===----------------------------------------------------------------------===//
313 //===----------------------------------------------------------------------===//
316 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
317 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
319 default: assert(0 && "Unknown condition code!");
320 case ISD::SETNE: return ARMCC::NE;
321 case ISD::SETEQ: return ARMCC::EQ;
322 case ISD::SETGT: return ARMCC::GT;
323 case ISD::SETGE: return ARMCC::GE;
324 case ISD::SETLT: return ARMCC::LT;
325 case ISD::SETLE: return ARMCC::LE;
326 case ISD::SETUGT: return ARMCC::HI;
327 case ISD::SETUGE: return ARMCC::HS;
328 case ISD::SETULT: return ARMCC::LO;
329 case ISD::SETULE: return ARMCC::LS;
333 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. It
334 /// returns true if the operands should be inverted to form the proper
336 static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
337 ARMCC::CondCodes &CondCode2) {
339 CondCode2 = ARMCC::AL;
341 default: assert(0 && "Unknown FP condition!");
343 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
345 case ISD::SETOGT: CondCode = ARMCC::GT; break;
347 case ISD::SETOGE: CondCode = ARMCC::GE; break;
348 case ISD::SETOLT: CondCode = ARMCC::MI; break;
349 case ISD::SETOLE: CondCode = ARMCC::GT; Invert = true; break;
350 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
351 case ISD::SETO: CondCode = ARMCC::VC; break;
352 case ISD::SETUO: CondCode = ARMCC::VS; break;
353 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
354 case ISD::SETUGT: CondCode = ARMCC::HI; break;
355 case ISD::SETUGE: CondCode = ARMCC::PL; break;
357 case ISD::SETULT: CondCode = ARMCC::LT; break;
359 case ISD::SETULE: CondCode = ARMCC::LE; break;
361 case ISD::SETUNE: CondCode = ARMCC::NE; break;
367 HowToPassArgument(MVT::ValueType ObjectVT, unsigned NumGPRs,
368 unsigned StackOffset, unsigned &NeededGPRs,
369 unsigned &NeededStackSize, unsigned &GPRPad,
370 unsigned &StackPad, unsigned Flags) {
375 unsigned align = (Flags >> ISD::ParamFlags::OrigAlignmentOffs);
376 GPRPad = NumGPRs % ((align + 3)/4);
377 StackPad = StackOffset % align;
378 unsigned firstGPR = NumGPRs + GPRPad;
380 default: assert(0 && "Unhandled argument type!");
392 else if (firstGPR == 3) {
400 /// LowerCALL - Lowering a ISD::CALL node into a callseq_start <-
401 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
403 SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) {
404 MVT::ValueType RetVT= Op.Val->getValueType(0);
405 SDOperand Chain = Op.getOperand(0);
406 unsigned CallConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
407 assert((CallConv == CallingConv::C ||
408 CallConv == CallingConv::Fast) && "unknown calling convention");
409 SDOperand Callee = Op.getOperand(4);
410 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
411 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
412 unsigned NumGPRs = 0; // GPRs used for parameter passing.
414 // Count how many bytes are to be pushed on the stack.
415 unsigned NumBytes = 0;
417 // Add up all the space actually used.
418 for (unsigned i = 0; i < NumOps; ++i) {
423 MVT::ValueType ObjectVT = Op.getOperand(5+2*i).getValueType();
424 unsigned Flags = Op.getConstantOperandVal(5+2*i+1);
425 HowToPassArgument(ObjectVT, NumGPRs, NumBytes, ObjGPRs, ObjSize,
426 GPRPad, StackPad, Flags);
427 NumBytes += ObjSize + StackPad;
428 NumGPRs += ObjGPRs + GPRPad;
431 // Adjust the stack pointer for the new arguments...
432 // These operations are automatically eliminated by the prolog/epilog pass
433 Chain = DAG.getCALLSEQ_START(Chain,
434 DAG.getConstant(NumBytes, MVT::i32));
436 SDOperand StackPtr = DAG.getRegister(ARM::SP, MVT::i32);
438 static const unsigned GPRArgRegs[] = {
439 ARM::R0, ARM::R1, ARM::R2, ARM::R3
443 std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
444 std::vector<SDOperand> MemOpChains;
445 for (unsigned i = 0; i != NumOps; ++i) {
446 SDOperand Arg = Op.getOperand(5+2*i);
447 unsigned Flags = Op.getConstantOperandVal(5+2*i+1);
448 MVT::ValueType ArgVT = Arg.getValueType();
454 HowToPassArgument(ArgVT, NumGPRs, ArgOffset, ObjGPRs,
455 ObjSize, GPRPad, StackPad, Flags);
457 ArgOffset += StackPad;
460 default: assert(0 && "Unexpected ValueType for argument!");
462 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Arg));
465 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs],
466 DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Arg)));
469 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg,
470 DAG.getConstant(0, getPointerTy()));
471 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg,
472 DAG.getConstant(1, getPointerTy()));
473 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Lo));
475 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1], Hi));
477 SDOperand PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType());
478 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
479 MemOpChains.push_back(DAG.getStore(Chain, Hi, PtrOff, NULL, 0));
484 SDOperand Cvt = DAG.getNode(ARMISD::FMRRD,
485 DAG.getVTList(MVT::i32, MVT::i32),
487 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Cvt));
489 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1],
492 SDOperand PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType());
493 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
494 MemOpChains.push_back(DAG.getStore(Chain, Cvt.getValue(1), PtrOff,
501 assert(ObjSize != 0);
502 SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
503 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
504 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
508 ArgOffset += ObjSize;
511 if (!MemOpChains.empty())
512 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
513 &MemOpChains[0], MemOpChains.size());
515 // Build a sequence of copy-to-reg nodes chained together with token chain
516 // and flag operands which copy the outgoing args into the appropriate regs.
518 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
519 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
521 InFlag = Chain.getValue(1);
524 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
525 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
526 // node so that legalize doesn't hack it.
527 bool isDirect = false;
528 bool isARMFunc = false;
529 bool isLocalARMFunc = false;
530 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
531 GlobalValue *GV = G->getGlobal();
533 bool isExt = (GV->isDeclaration() || GV->hasWeakLinkage() ||
534 GV->hasLinkOnceLinkage());
535 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
536 getTargetMachine().getRelocationModel() != Reloc::Static;
537 isARMFunc = !Subtarget->isThumb() || isStub;
538 // ARM call to a local ARM function is predicable.
539 isLocalARMFunc = !Subtarget->isThumb() && !isExt;
540 // tBX takes a register source operand.
541 if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) {
542 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
544 SDOperand CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2);
545 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
546 Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0);
547 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
548 Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel);
550 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy());
551 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
553 bool isStub = Subtarget->isTargetDarwin() &&
554 getTargetMachine().getRelocationModel() != Reloc::Static;
555 isARMFunc = !Subtarget->isThumb() || isStub;
556 // tBX takes a register source operand.
557 const char *Sym = S->getSymbol();
558 if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) {
559 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(Sym, ARMPCLabelIndex,
561 SDOperand CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2);
562 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
563 Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0);
564 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
565 Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel);
567 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
570 // FIXME: handle tail calls differently.
572 if (Subtarget->isThumb()) {
573 if (!Subtarget->hasV5TOps() && (!isDirect || isARMFunc))
574 CallOpc = ARMISD::CALL_NOLINK;
576 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
578 CallOpc = (isDirect || Subtarget->hasV5TOps())
579 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
580 : ARMISD::CALL_NOLINK;
582 if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb()) {
583 // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK
584 Chain = DAG.getCopyToReg(Chain, ARM::LR,
585 DAG.getNode(ISD::UNDEF, MVT::i32), InFlag);
586 InFlag = Chain.getValue(1);
589 std::vector<MVT::ValueType> NodeTys;
590 NodeTys.push_back(MVT::Other); // Returns a chain
591 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
593 std::vector<SDOperand> Ops;
594 Ops.push_back(Chain);
595 Ops.push_back(Callee);
597 // Add argument registers to the end of the list so that they are known live
599 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
600 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
601 RegsToPass[i].second.getValueType()));
604 Ops.push_back(InFlag);
605 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
606 InFlag = Chain.getValue(1);
608 Chain = DAG.getCALLSEQ_END(Chain,
609 DAG.getConstant(NumBytes, MVT::i32),
610 DAG.getConstant(0, MVT::i32),
612 if (RetVT != MVT::Other)
613 InFlag = Chain.getValue(1);
615 std::vector<SDOperand> ResultVals;
618 // If the call has results, copy the values out of the ret val registers.
620 default: assert(0 && "Unexpected ret value!");
624 Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1);
625 ResultVals.push_back(Chain.getValue(0));
626 if (Op.Val->getValueType(1) == MVT::i32) {
627 // Returns a i64 value.
628 Chain = DAG.getCopyFromReg(Chain, ARM::R1, MVT::i32,
629 Chain.getValue(2)).getValue(1);
630 ResultVals.push_back(Chain.getValue(0));
631 NodeTys.push_back(MVT::i32);
633 NodeTys.push_back(MVT::i32);
636 Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1);
637 ResultVals.push_back(DAG.getNode(ISD::BIT_CONVERT, MVT::f32,
639 NodeTys.push_back(MVT::f32);
642 SDOperand Lo = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag);
643 SDOperand Hi = DAG.getCopyFromReg(Lo, ARM::R1, MVT::i32, Lo.getValue(2));
644 ResultVals.push_back(DAG.getNode(ARMISD::FMDRR, MVT::f64, Lo, Hi));
645 NodeTys.push_back(MVT::f64);
650 NodeTys.push_back(MVT::Other);
652 if (ResultVals.empty())
655 ResultVals.push_back(Chain);
656 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, &ResultVals[0],
658 return Res.getValue(Op.ResNo);
661 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
663 SDOperand Chain = Op.getOperand(0);
664 switch(Op.getNumOperands()) {
666 assert(0 && "Do not know how to return this many arguments!");
669 SDOperand LR = DAG.getRegister(ARM::LR, MVT::i32);
670 return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Chain);
673 Op = Op.getOperand(1);
674 if (Op.getValueType() == MVT::f32) {
675 Op = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
676 } else if (Op.getValueType() == MVT::f64) {
677 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
679 Op = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32), &Op,1);
680 SDOperand Sign = DAG.getConstant(0, MVT::i32);
681 return DAG.getNode(ISD::RET, MVT::Other, Chain, Op, Sign,
682 Op.getValue(1), Sign);
684 Copy = DAG.getCopyToReg(Chain, ARM::R0, Op, SDOperand());
685 if (DAG.getMachineFunction().liveout_empty())
686 DAG.getMachineFunction().addLiveOut(ARM::R0);
689 Copy = DAG.getCopyToReg(Chain, ARM::R1, Op.getOperand(3), SDOperand());
690 Copy = DAG.getCopyToReg(Copy, ARM::R0, Op.getOperand(1), Copy.getValue(1));
691 // If we haven't noted the R0+R1 are live out, do so now.
692 if (DAG.getMachineFunction().liveout_empty()) {
693 DAG.getMachineFunction().addLiveOut(ARM::R0);
694 DAG.getMachineFunction().addLiveOut(ARM::R1);
699 //We must use RET_FLAG instead of BRIND because BRIND doesn't have a flag
700 return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
703 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
704 // their target countpart wrapped in the ARMISD::Wrapper node. Suppose N is
705 // one of the above mentioned nodes. It has to be wrapped because otherwise
706 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
707 // be used to form addressing mode. These wrapped nodes will be selected
709 static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
710 MVT::ValueType PtrVT = Op.getValueType();
711 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
713 if (CP->isMachineConstantPoolEntry())
714 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
717 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
719 return DAG.getNode(ARMISD::Wrapper, MVT::i32, Res);
722 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
724 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
726 MVT::ValueType PtrVT = getPointerTy();
727 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
728 ARMConstantPoolValue *CPV =
729 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
730 PCAdj, "tlsgd", true);
731 SDOperand Argument = DAG.getTargetConstantPool(CPV, PtrVT, 2);
732 Argument = DAG.getNode(ARMISD::Wrapper, MVT::i32, Argument);
733 Argument = DAG.getLoad(PtrVT, DAG.getEntryNode(), Argument, NULL, 0);
734 SDOperand Chain = Argument.getValue(1);
736 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
737 Argument = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Argument, PICLabel);
739 // call __tls_get_addr.
742 Entry.Node = Argument;
743 Entry.Ty = (const Type *) Type::Int32Ty;
744 Args.push_back(Entry);
745 std::pair<SDOperand, SDOperand> CallResult =
746 LowerCallTo(Chain, (const Type *) Type::Int32Ty, false, false,
747 CallingConv::C, false,
748 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG);
749 return CallResult.first;
752 // Lower ISD::GlobalTLSAddress using the "initial exec" or
753 // "local exec" model.
755 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
757 GlobalValue *GV = GA->getGlobal();
759 SDOperand Chain = DAG.getEntryNode();
760 MVT::ValueType PtrVT = getPointerTy();
761 // Get the Thread Pointer
762 SDOperand ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, PtrVT);
764 if (GV->isDeclaration()){
765 // initial exec model
766 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
767 ARMConstantPoolValue *CPV =
768 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue,
769 PCAdj, "gottpoff", true);
770 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 2);
771 Offset = DAG.getNode(ARMISD::Wrapper, MVT::i32, Offset);
772 Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0);
773 Chain = Offset.getValue(1);
775 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
776 Offset = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Offset, PICLabel);
778 Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0);
781 ARMConstantPoolValue *CPV =
782 new ARMConstantPoolValue(GV, ARMCP::CPValue, "tpoff");
783 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 2);
784 Offset = DAG.getNode(ARMISD::Wrapper, MVT::i32, Offset);
785 Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0);
788 // The address of the thread local variable is the add of the thread
789 // pointer with the offset of the variable.
790 return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset);
794 ARMTargetLowering::LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) {
795 // TODO: implement the "local dynamic" model
796 assert(Subtarget->isTargetELF() &&
797 "TLS not implemented for non-ELF targets");
798 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
799 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
800 // otherwise use the "Local Exec" TLS Model
801 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
802 return LowerToTLSGeneralDynamicModel(GA, DAG);
804 return LowerToTLSExecModels(GA, DAG);
807 SDOperand ARMTargetLowering::LowerGlobalAddressELF(SDOperand Op,
809 MVT::ValueType PtrVT = getPointerTy();
810 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
811 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
812 if (RelocM == Reloc::PIC_) {
813 bool UseGOTOFF = GV->hasInternalLinkage() || GV->hasHiddenVisibility();
814 ARMConstantPoolValue *CPV =
815 new ARMConstantPoolValue(GV, ARMCP::CPValue, UseGOTOFF ? "GOTOFF":"GOT");
816 SDOperand CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
817 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
818 SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
819 SDOperand Chain = Result.getValue(1);
820 SDOperand GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PtrVT);
821 Result = DAG.getNode(ISD::ADD, PtrVT, Result, GOT);
823 Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0);
826 SDOperand CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2);
827 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
828 return DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
832 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol
833 /// even in non-static mode.
834 static bool GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model RelocM) {
835 return RelocM != Reloc::Static &&
836 (GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
837 (GV->isDeclaration() && !GV->hasNotBeenReadFromBitcode()));
840 SDOperand ARMTargetLowering::LowerGlobalAddressDarwin(SDOperand Op,
842 MVT::ValueType PtrVT = getPointerTy();
843 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
844 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
845 bool IsIndirect = GVIsIndirectSymbol(GV, RelocM);
847 if (RelocM == Reloc::Static)
848 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2);
850 unsigned PCAdj = (RelocM != Reloc::PIC_)
851 ? 0 : (Subtarget->isThumb() ? 4 : 8);
852 ARMCP::ARMCPKind Kind = IsIndirect ? ARMCP::CPNonLazyPtr
854 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex,
856 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
858 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
860 SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
861 SDOperand Chain = Result.getValue(1);
863 if (RelocM == Reloc::PIC_) {
864 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
865 Result = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel);
868 Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0);
873 SDOperand ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDOperand Op,
875 assert(Subtarget->isTargetELF() &&
876 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
877 MVT::ValueType PtrVT = getPointerTy();
878 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
879 ARMConstantPoolValue *CPV = new ARMConstantPoolValue("_GLOBAL_OFFSET_TABLE_",
881 ARMCP::CPValue, PCAdj);
882 SDOperand CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2);
883 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr);
884 SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0);
885 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
886 return DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel);
889 static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
890 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
891 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue();
893 default: return SDOperand(); // Don't custom lower most intrinsics.
894 case Intrinsic::arm_thread_pointer:
895 return DAG.getNode(ARMISD::THREAD_POINTER, PtrVT);
899 static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
900 unsigned VarArgsFrameIndex) {
901 // vastart just stores the address of the VarArgsFrameIndex slot into the
902 // memory location argument.
903 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
904 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
905 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
906 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(),
910 static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG,
911 unsigned *vRegs, unsigned ArgNo,
912 unsigned &NumGPRs, unsigned &ArgOffset) {
913 MachineFunction &MF = DAG.getMachineFunction();
914 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
915 SDOperand Root = Op.getOperand(0);
916 std::vector<SDOperand> ArgValues;
917 SSARegMap *RegMap = MF.getSSARegMap();
919 static const unsigned GPRArgRegs[] = {
920 ARM::R0, ARM::R1, ARM::R2, ARM::R3
927 unsigned Flags = Op.getConstantOperandVal(ArgNo + 3);
928 HowToPassArgument(ObjectVT, NumGPRs, ArgOffset, ObjGPRs,
929 ObjSize, GPRPad, StackPad, Flags);
931 ArgOffset += StackPad;
935 unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass);
936 MF.addLiveIn(GPRArgRegs[NumGPRs], VReg);
937 vRegs[NumGPRs] = VReg;
938 ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32);
939 if (ObjectVT == MVT::f32)
940 ArgValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, ArgValue);
941 } else if (ObjGPRs == 2) {
942 unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass);
943 MF.addLiveIn(GPRArgRegs[NumGPRs], VReg);
944 vRegs[NumGPRs] = VReg;
945 ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32);
947 VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass);
948 MF.addLiveIn(GPRArgRegs[NumGPRs+1], VReg);
949 vRegs[NumGPRs+1] = VReg;
950 SDOperand ArgValue2 = DAG.getCopyFromReg(Root, VReg, MVT::i32);
952 assert(ObjectVT != MVT::i64 && "i64 should already be lowered");
953 ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2);
958 // If the argument is actually used, emit a load from the right stack
960 if (!Op.Val->hasNUsesOfValue(0, ArgNo)) {
961 MachineFrameInfo *MFI = MF.getFrameInfo();
962 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
963 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
965 ArgValue = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
967 SDOperand ArgValue2 = DAG.getLoad(MVT::i32, Root, FIN, NULL, 0);
968 assert(ObjectVT != MVT::i64 && "i64 should already be lowered");
969 ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2);
972 // Don't emit a dead load.
973 ArgValue = DAG.getNode(ISD::UNDEF, ObjectVT);
976 ArgOffset += ObjSize; // Move on to the next argument.
983 ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) {
984 std::vector<SDOperand> ArgValues;
985 SDOperand Root = Op.getOperand(0);
986 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
987 unsigned NumGPRs = 0; // GPRs used for parameter passing.
990 unsigned NumArgs = Op.Val->getNumValues()-1;
991 for (unsigned ArgNo = 0; ArgNo < NumArgs; ++ArgNo)
992 ArgValues.push_back(LowerFORMAL_ARGUMENT(Op, DAG, VRegs, ArgNo,
993 NumGPRs, ArgOffset));
995 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
997 static const unsigned GPRArgRegs[] = {
998 ARM::R0, ARM::R1, ARM::R2, ARM::R3
1001 MachineFunction &MF = DAG.getMachineFunction();
1002 SSARegMap *RegMap = MF.getSSARegMap();
1003 MachineFrameInfo *MFI = MF.getFrameInfo();
1004 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1005 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1006 unsigned VARegSize = (4 - NumGPRs) * 4;
1007 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
1008 if (VARegSaveSize) {
1009 // If this function is vararg, store any remaining integer argument regs
1010 // to their spots on the stack so that they may be loaded by deferencing
1011 // the result of va_next.
1012 AFI->setVarArgsRegSaveSize(VARegSaveSize);
1013 VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset +
1014 VARegSaveSize - VARegSize);
1015 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
1017 SmallVector<SDOperand, 4> MemOps;
1018 for (; NumGPRs < 4; ++NumGPRs) {
1019 unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass);
1020 MF.addLiveIn(GPRArgRegs[NumGPRs], VReg);
1021 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i32);
1022 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1023 MemOps.push_back(Store);
1024 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN,
1025 DAG.getConstant(4, getPointerTy()));
1027 if (!MemOps.empty())
1028 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,
1029 &MemOps[0], MemOps.size());
1031 // This will point to the next argument passed via stack.
1032 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
1035 ArgValues.push_back(Root);
1037 // Return the new list of results.
1038 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
1039 Op.Val->value_end());
1040 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
1043 /// isFloatingPointZero - Return true if this is +0.0.
1044 static bool isFloatingPointZero(SDOperand Op) {
1045 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1046 return CFP->getValueAPF().isPosZero();
1047 else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
1048 // Maybe this has already been legalized into the constant pool?
1049 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
1050 SDOperand WrapperOp = Op.getOperand(1).getOperand(0);
1051 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
1052 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1053 return CFP->getValueAPF().isPosZero();
1059 static bool isLegalCmpImmediate(unsigned C, bool isThumb) {
1060 return ( isThumb && (C & ~255U) == 0) ||
1061 (!isThumb && ARM_AM::getSOImmVal(C) != -1);
1064 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
1065 /// the given operands.
1066 static SDOperand getARMCmp(SDOperand LHS, SDOperand RHS, ISD::CondCode CC,
1067 SDOperand &ARMCC, SelectionDAG &DAG, bool isThumb) {
1068 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.Val)) {
1069 unsigned C = RHSC->getValue();
1070 if (!isLegalCmpImmediate(C, isThumb)) {
1071 // Constant does not fit, try adjusting it by one?
1076 if (isLegalCmpImmediate(C-1, isThumb)) {
1077 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1078 RHS = DAG.getConstant(C-1, MVT::i32);
1083 if (C > 0 && isLegalCmpImmediate(C-1, isThumb)) {
1084 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1085 RHS = DAG.getConstant(C-1, MVT::i32);
1090 if (isLegalCmpImmediate(C+1, isThumb)) {
1091 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1092 RHS = DAG.getConstant(C+1, MVT::i32);
1097 if (C < 0xffffffff && isLegalCmpImmediate(C+1, isThumb)) {
1098 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1099 RHS = DAG.getConstant(C+1, MVT::i32);
1106 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
1107 ARMISD::NodeType CompareType;
1110 CompareType = ARMISD::CMP;
1116 // Uses only N and Z Flags
1117 CompareType = ARMISD::CMPNZ;
1120 ARMCC = DAG.getConstant(CondCode, MVT::i32);
1121 return DAG.getNode(CompareType, MVT::Flag, LHS, RHS);
1124 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
1125 static SDOperand getVFPCmp(SDOperand LHS, SDOperand RHS, SelectionDAG &DAG) {
1127 if (!isFloatingPointZero(RHS))
1128 Cmp = DAG.getNode(ARMISD::CMPFP, MVT::Flag, LHS, RHS);
1130 Cmp = DAG.getNode(ARMISD::CMPFPw0, MVT::Flag, LHS);
1131 return DAG.getNode(ARMISD::FMSTAT, MVT::Flag, Cmp);
1134 static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG,
1135 const ARMSubtarget *ST) {
1136 MVT::ValueType VT = Op.getValueType();
1137 SDOperand LHS = Op.getOperand(0);
1138 SDOperand RHS = Op.getOperand(1);
1139 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1140 SDOperand TrueVal = Op.getOperand(2);
1141 SDOperand FalseVal = Op.getOperand(3);
1143 if (LHS.getValueType() == MVT::i32) {
1145 SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1146 SDOperand Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb());
1147 return DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal, ARMCC, CCR, Cmp);
1150 ARMCC::CondCodes CondCode, CondCode2;
1151 if (FPCCToARMCC(CC, CondCode, CondCode2))
1152 std::swap(TrueVal, FalseVal);
1154 SDOperand ARMCC = DAG.getConstant(CondCode, MVT::i32);
1155 SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1156 SDOperand Cmp = getVFPCmp(LHS, RHS, DAG);
1157 SDOperand Result = DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal,
1159 if (CondCode2 != ARMCC::AL) {
1160 SDOperand ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
1161 // FIXME: Needs another CMP because flag can have but one use.
1162 SDOperand Cmp2 = getVFPCmp(LHS, RHS, DAG);
1163 Result = DAG.getNode(ARMISD::CMOV, VT, Result, TrueVal, ARMCC2, CCR, Cmp2);
1168 static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG,
1169 const ARMSubtarget *ST) {
1170 SDOperand Chain = Op.getOperand(0);
1171 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1172 SDOperand LHS = Op.getOperand(2);
1173 SDOperand RHS = Op.getOperand(3);
1174 SDOperand Dest = Op.getOperand(4);
1176 if (LHS.getValueType() == MVT::i32) {
1178 SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1179 SDOperand Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb());
1180 return DAG.getNode(ARMISD::BRCOND, MVT::Other, Chain, Dest, ARMCC, CCR,Cmp);
1183 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
1184 ARMCC::CondCodes CondCode, CondCode2;
1185 if (FPCCToARMCC(CC, CondCode, CondCode2))
1186 // Swap the LHS/RHS of the comparison if needed.
1187 std::swap(LHS, RHS);
1189 SDOperand Cmp = getVFPCmp(LHS, RHS, DAG);
1190 SDOperand ARMCC = DAG.getConstant(CondCode, MVT::i32);
1191 SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1192 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
1193 SDOperand Ops[] = { Chain, Dest, ARMCC, CCR, Cmp };
1194 SDOperand Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5);
1195 if (CondCode2 != ARMCC::AL) {
1196 ARMCC = DAG.getConstant(CondCode2, MVT::i32);
1197 SDOperand Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) };
1198 Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5);
1203 SDOperand ARMTargetLowering::LowerBR_JT(SDOperand Op, SelectionDAG &DAG) {
1204 SDOperand Chain = Op.getOperand(0);
1205 SDOperand Table = Op.getOperand(1);
1206 SDOperand Index = Op.getOperand(2);
1208 MVT::ValueType PTy = getPointerTy();
1209 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
1210 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
1211 SDOperand UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
1212 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
1213 Table = DAG.getNode(ARMISD::WrapperJT, MVT::i32, JTI, UId);
1214 Index = DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(4, PTy));
1215 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table);
1216 bool isPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
1217 Addr = DAG.getLoad(isPIC ? (MVT::ValueType)MVT::i32 : PTy,
1218 Chain, Addr, NULL, 0);
1219 Chain = Addr.getValue(1);
1221 Addr = DAG.getNode(ISD::ADD, PTy, Addr, Table);
1222 return DAG.getNode(ARMISD::BR_JT, MVT::Other, Chain, Addr, JTI, UId);
1225 static SDOperand LowerFP_TO_INT(SDOperand Op, SelectionDAG &DAG) {
1227 Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI;
1228 Op = DAG.getNode(Opc, MVT::f32, Op.getOperand(0));
1229 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
1232 static SDOperand LowerINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
1233 MVT::ValueType VT = Op.getValueType();
1235 Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF;
1237 Op = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
1238 return DAG.getNode(Opc, VT, Op);
1241 static SDOperand LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) {
1242 // Implement fcopysign with a fabs and a conditional fneg.
1243 SDOperand Tmp0 = Op.getOperand(0);
1244 SDOperand Tmp1 = Op.getOperand(1);
1245 MVT::ValueType VT = Op.getValueType();
1246 MVT::ValueType SrcVT = Tmp1.getValueType();
1247 SDOperand AbsVal = DAG.getNode(ISD::FABS, VT, Tmp0);
1248 SDOperand Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG);
1249 SDOperand ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
1250 SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1251 return DAG.getNode(ARMISD::CNEG, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp);
1254 SDOperand ARMTargetLowering::LowerMEMCPYInline(SDOperand Chain,
1259 SelectionDAG &DAG) {
1260 // Do repeated 4-byte loads and stores. To be improved.
1261 assert((Align & 3) == 0 && "Expected 4-byte aligned addresses!");
1262 unsigned BytesLeft = Size & 3;
1263 unsigned NumMemOps = Size >> 2;
1264 unsigned EmittedNumMemOps = 0;
1265 unsigned SrcOff = 0, DstOff = 0;
1266 MVT::ValueType VT = MVT::i32;
1267 unsigned VTSize = 4;
1269 const unsigned MAX_LOADS_IN_LDM = 6;
1270 SDOperand TFOps[MAX_LOADS_IN_LDM];
1271 SDOperand Loads[MAX_LOADS_IN_LDM];
1273 // Emit up to MAX_LOADS_IN_LDM loads, then a TokenFactor barrier, then the
1274 // same number of stores. The loads and stores will get combined into
1275 // ldm/stm later on.
1276 while (EmittedNumMemOps < NumMemOps) {
1278 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
1279 Loads[i] = DAG.getLoad(VT, Chain,
1280 DAG.getNode(ISD::ADD, MVT::i32, Source,
1281 DAG.getConstant(SrcOff, MVT::i32)),
1283 TFOps[i] = Loads[i].getValue(1);
1286 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i);
1289 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
1290 TFOps[i] = DAG.getStore(Chain, Loads[i],
1291 DAG.getNode(ISD::ADD, MVT::i32, Dest,
1292 DAG.getConstant(DstOff, MVT::i32)),
1296 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i);
1298 EmittedNumMemOps += i;
1304 // Issue loads / stores for the trailing (1 - 3) bytes.
1305 unsigned BytesLeftSave = BytesLeft;
1308 if (BytesLeft >= 2) {
1316 Loads[i] = DAG.getLoad(VT, Chain,
1317 DAG.getNode(ISD::ADD, MVT::i32, Source,
1318 DAG.getConstant(SrcOff, MVT::i32)),
1320 TFOps[i] = Loads[i].getValue(1);
1323 BytesLeft -= VTSize;
1325 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i);
1328 BytesLeft = BytesLeftSave;
1330 if (BytesLeft >= 2) {
1338 TFOps[i] = DAG.getStore(Chain, Loads[i],
1339 DAG.getNode(ISD::ADD, MVT::i32, Dest,
1340 DAG.getConstant(DstOff, MVT::i32)),
1344 BytesLeft -= VTSize;
1346 return DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i);
1349 static SDNode *ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
1350 // Turn f64->i64 into FMRRD.
1351 assert(N->getValueType(0) == MVT::i64 &&
1352 N->getOperand(0).getValueType() == MVT::f64);
1354 SDOperand Op = N->getOperand(0);
1355 SDOperand Cvt = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32),
1358 // Merge the pieces into a single i64 value.
1359 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Cvt, Cvt.getValue(1)).Val;
1362 static SDNode *ExpandSRx(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) {
1363 assert(N->getValueType(0) == MVT::i64 &&
1364 (N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
1365 "Unknown shift to lower!");
1367 // We only lower SRA, SRL of 1 here, all others use generic lowering.
1368 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
1369 cast<ConstantSDNode>(N->getOperand(1))->getValue() != 1)
1372 // If we are in thumb mode, we don't have RRX.
1373 if (ST->isThumb()) return 0;
1375 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
1376 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0),
1377 DAG.getConstant(0, MVT::i32));
1378 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0),
1379 DAG.getConstant(1, MVT::i32));
1381 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
1382 // captures the result into a carry flag.
1383 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
1384 Hi = DAG.getNode(Opc, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
1386 // The low part is an ARMISD::RRX operand, which shifts the carry in.
1387 Lo = DAG.getNode(ARMISD::RRX, MVT::i32, Lo, Hi.getValue(1));
1389 // Merge the pieces into a single i64 value.
1390 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi).Val;
1394 SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
1395 switch (Op.getOpcode()) {
1396 default: assert(0 && "Don't know how to custom lower this!"); abort();
1397 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
1398 case ISD::GlobalAddress:
1399 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
1400 LowerGlobalAddressELF(Op, DAG);
1401 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
1402 case ISD::CALL: return LowerCALL(Op, DAG);
1403 case ISD::RET: return LowerRET(Op, DAG);
1404 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, Subtarget);
1405 case ISD::BR_CC: return LowerBR_CC(Op, DAG, Subtarget);
1406 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
1407 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex);
1408 case ISD::SINT_TO_FP:
1409 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
1410 case ISD::FP_TO_SINT:
1411 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
1412 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
1413 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
1414 case ISD::RETURNADDR: break;
1415 case ISD::FRAMEADDR: break;
1416 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
1417 case ISD::MEMCPY: return LowerMEMCPY(Op, DAG);
1418 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
1421 // FIXME: Remove these when LegalizeDAGTypes lands.
1422 case ISD::BIT_CONVERT: return SDOperand(ExpandBIT_CONVERT(Op.Val, DAG), 0);
1424 case ISD::SRA: return SDOperand(ExpandSRx(Op.Val, DAG,Subtarget),0);
1430 /// ExpandOperationResult - Provide custom lowering hooks for expanding
1432 SDNode *ARMTargetLowering::ExpandOperationResult(SDNode *N, SelectionDAG &DAG) {
1433 switch (N->getOpcode()) {
1434 default: assert(0 && "Don't know how to custom expand this!"); abort();
1435 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(N, DAG);
1437 case ISD::SRA: return ExpandSRx(N, DAG, Subtarget);
1442 //===----------------------------------------------------------------------===//
1443 // ARM Scheduler Hooks
1444 //===----------------------------------------------------------------------===//
1447 ARMTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
1448 MachineBasicBlock *BB) {
1449 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1450 switch (MI->getOpcode()) {
1451 default: assert(false && "Unexpected instr type to insert");
1452 case ARM::tMOVCCr: {
1453 // To "insert" a SELECT_CC instruction, we actually have to insert the
1454 // diamond control-flow pattern. The incoming instruction knows the
1455 // destination vreg to set, the condition code register to branch on, the
1456 // true/false values to select between, and a branch opcode to use.
1457 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1458 ilist<MachineBasicBlock>::iterator It = BB;
1464 // cmpTY ccX, r1, r2
1466 // fallthrough --> copy0MBB
1467 MachineBasicBlock *thisMBB = BB;
1468 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
1469 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
1470 BuildMI(BB, TII->get(ARM::tBcc)).addMBB(sinkMBB)
1471 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
1472 MachineFunction *F = BB->getParent();
1473 F->getBasicBlockList().insert(It, copy0MBB);
1474 F->getBasicBlockList().insert(It, sinkMBB);
1475 // Update machine-CFG edges by first adding all successors of the current
1476 // block to the new block which will contain the Phi node for the select.
1477 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
1478 e = BB->succ_end(); i != e; ++i)
1479 sinkMBB->addSuccessor(*i);
1480 // Next, remove all successors of the current block, and add the true
1481 // and fallthrough blocks as its successors.
1482 while(!BB->succ_empty())
1483 BB->removeSuccessor(BB->succ_begin());
1484 BB->addSuccessor(copy0MBB);
1485 BB->addSuccessor(sinkMBB);
1488 // %FalseValue = ...
1489 // # fallthrough to sinkMBB
1492 // Update machine-CFG edges
1493 BB->addSuccessor(sinkMBB);
1496 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1499 BuildMI(BB, TII->get(ARM::PHI), MI->getOperand(0).getReg())
1500 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
1501 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
1503 delete MI; // The pseudo instruction is gone now.
1509 //===----------------------------------------------------------------------===//
1510 // ARM Optimization Hooks
1511 //===----------------------------------------------------------------------===//
1513 /// isLegalAddressImmediate - Return true if the integer value can be used
1514 /// as the offset of the target addressing mode for load / store of the
1516 static bool isLegalAddressImmediate(int64_t V, MVT::ValueType VT,
1517 const ARMSubtarget *Subtarget) {
1521 if (Subtarget->isThumb()) {
1527 default: return false;
1542 if ((V & (Scale - 1)) != 0)
1545 return V == V & ((1LL << 5) - 1);
1551 default: return false;
1556 return V == V & ((1LL << 12) - 1);
1559 return V == V & ((1LL << 8) - 1);
1562 if (!Subtarget->hasVFP2())
1567 return V == V & ((1LL << 8) - 1);
1571 /// isLegalAddressingMode - Return true if the addressing mode represented
1572 /// by AM is legal for this target, for a load/store of the specified type.
1573 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
1574 const Type *Ty) const {
1575 if (!isLegalAddressImmediate(AM.BaseOffs, getValueType(Ty), Subtarget))
1578 // Can never fold addr of global into load/store.
1583 case 0: // no scale reg, must be "r+i" or "r", or "i".
1586 if (Subtarget->isThumb())
1590 // ARM doesn't support any R+R*scale+imm addr modes.
1594 int Scale = AM.Scale;
1595 switch (getValueType(Ty)) {
1596 default: return false;
1601 // This assumes i64 is legalized to a pair of i32. If not (i.e.
1602 // ldrd / strd are used, then its address mode is same as i16.
1604 if (Scale < 0) Scale = -Scale;
1608 return isPowerOf2_32(Scale & ~1);
1611 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
1616 // Note, we allow "void" uses (basically, uses that aren't loads or
1617 // stores), because arm allows folding a scale into many arithmetic
1618 // operations. This should be made more precise and revisited later.
1620 // Allow r << imm, but the imm has to be a multiple of two.
1621 if (AM.Scale & 1) return false;
1622 return isPowerOf2_32(AM.Scale);
1630 static bool getIndexedAddressParts(SDNode *Ptr, MVT::ValueType VT,
1631 bool isSEXTLoad, SDOperand &Base,
1632 SDOperand &Offset, bool &isInc,
1633 SelectionDAG &DAG) {
1634 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
1637 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
1639 Base = Ptr->getOperand(0);
1640 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
1641 int RHSC = (int)RHS->getValue();
1642 if (RHSC < 0 && RHSC > -256) {
1644 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
1648 isInc = (Ptr->getOpcode() == ISD::ADD);
1649 Offset = Ptr->getOperand(1);
1651 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
1653 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
1654 int RHSC = (int)RHS->getValue();
1655 if (RHSC < 0 && RHSC > -0x1000) {
1657 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
1658 Base = Ptr->getOperand(0);
1663 if (Ptr->getOpcode() == ISD::ADD) {
1665 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
1666 if (ShOpcVal != ARM_AM::no_shift) {
1667 Base = Ptr->getOperand(1);
1668 Offset = Ptr->getOperand(0);
1670 Base = Ptr->getOperand(0);
1671 Offset = Ptr->getOperand(1);
1676 isInc = (Ptr->getOpcode() == ISD::ADD);
1677 Base = Ptr->getOperand(0);
1678 Offset = Ptr->getOperand(1);
1682 // FIXME: Use FLDM / FSTM to emulate indexed FP load / store.
1686 /// getPreIndexedAddressParts - returns true by value, base pointer and
1687 /// offset pointer and addressing mode by reference if the node's address
1688 /// can be legally represented as pre-indexed load / store address.
1690 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
1692 ISD::MemIndexedMode &AM,
1693 SelectionDAG &DAG) {
1694 if (Subtarget->isThumb())
1699 bool isSEXTLoad = false;
1700 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1701 Ptr = LD->getBasePtr();
1702 VT = LD->getLoadedVT();
1703 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
1704 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1705 Ptr = ST->getBasePtr();
1706 VT = ST->getStoredVT();
1711 bool isLegal = getIndexedAddressParts(Ptr.Val, VT, isSEXTLoad, Base, Offset,
1714 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
1720 /// getPostIndexedAddressParts - returns true by value, base pointer and
1721 /// offset pointer and addressing mode by reference if this node can be
1722 /// combined with a load / store to form a post-indexed load / store.
1723 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
1726 ISD::MemIndexedMode &AM,
1727 SelectionDAG &DAG) {
1728 if (Subtarget->isThumb())
1733 bool isSEXTLoad = false;
1734 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1735 VT = LD->getLoadedVT();
1736 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
1737 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1738 VT = ST->getStoredVT();
1743 bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
1746 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
1752 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
1754 uint64_t &KnownZero,
1756 const SelectionDAG &DAG,
1757 unsigned Depth) const {
1760 switch (Op.getOpcode()) {
1762 case ARMISD::CMOV: {
1763 // Bits are known zero/one if known on the LHS and RHS.
1764 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
1765 if (KnownZero == 0 && KnownOne == 0) return;
1767 uint64_t KnownZeroRHS, KnownOneRHS;
1768 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
1769 KnownZeroRHS, KnownOneRHS, Depth+1);
1770 KnownZero &= KnownZeroRHS;
1771 KnownOne &= KnownOneRHS;
1777 //===----------------------------------------------------------------------===//
1778 // ARM Inline Assembly Support
1779 //===----------------------------------------------------------------------===//
1781 /// getConstraintType - Given a constraint letter, return the type of
1782 /// constraint it is for this target.
1783 ARMTargetLowering::ConstraintType
1784 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
1785 if (Constraint.size() == 1) {
1786 switch (Constraint[0]) {
1788 case 'l': return C_RegisterClass;
1789 case 'w': return C_RegisterClass;
1792 return TargetLowering::getConstraintType(Constraint);
1795 std::pair<unsigned, const TargetRegisterClass*>
1796 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
1797 MVT::ValueType VT) const {
1798 if (Constraint.size() == 1) {
1799 // GCC RS6000 Constraint Letters
1800 switch (Constraint[0]) {
1802 // FIXME: in thumb mode, 'l' is only low-regs.
1805 return std::make_pair(0U, ARM::GPRRegisterClass);
1808 return std::make_pair(0U, ARM::SPRRegisterClass);
1810 return std::make_pair(0U, ARM::DPRRegisterClass);
1814 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1817 std::vector<unsigned> ARMTargetLowering::
1818 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1819 MVT::ValueType VT) const {
1820 if (Constraint.size() != 1)
1821 return std::vector<unsigned>();
1823 switch (Constraint[0]) { // GCC ARM Constraint Letters
1827 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
1828 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
1829 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
1830 ARM::R12, ARM::LR, 0);
1833 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
1834 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
1835 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
1836 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
1837 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
1838 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
1839 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
1840 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
1842 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1843 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1844 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
1845 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
1849 return std::vector<unsigned>();