1 //===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that ARM uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "arm-isel"
17 #include "ARMAddressingModes.h"
18 #include "ARMCallingConv.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMISelLowering.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMPerfectShuffle.h"
23 #include "ARMRegisterInfo.h"
24 #include "ARMSubtarget.h"
25 #include "ARMTargetMachine.h"
26 #include "ARMTargetObjectFile.h"
27 #include "llvm/CallingConv.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Function.h"
30 #include "llvm/GlobalValue.h"
31 #include "llvm/Instruction.h"
32 #include "llvm/Instructions.h"
33 #include "llvm/Intrinsics.h"
34 #include "llvm/Type.h"
35 #include "llvm/CodeGen/CallingConvLower.h"
36 #include "llvm/CodeGen/MachineBasicBlock.h"
37 #include "llvm/CodeGen/MachineFrameInfo.h"
38 #include "llvm/CodeGen/MachineFunction.h"
39 #include "llvm/CodeGen/MachineInstrBuilder.h"
40 #include "llvm/CodeGen/MachineRegisterInfo.h"
41 #include "llvm/CodeGen/PseudoSourceValue.h"
42 #include "llvm/CodeGen/SelectionDAG.h"
43 #include "llvm/MC/MCSectionMachO.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/ADT/VectorExtras.h"
46 #include "llvm/ADT/Statistic.h"
47 #include "llvm/Support/CommandLine.h"
48 #include "llvm/Support/ErrorHandling.h"
49 #include "llvm/Support/MathExtras.h"
50 #include "llvm/Support/raw_ostream.h"
54 STATISTIC(NumTailCalls, "Number of tail calls");
56 // This option should go away when tail calls fully work.
58 EnableARMTailCalls("arm-tail-calls", cl::Hidden,
59 cl::desc("Generate tail calls (TEMPORARY OPTION)."),
63 EnableARMLongCalls("arm-long-calls", cl::Hidden,
64 cl::desc("Generate calls via indirect call instructions"),
68 ARMInterworking("arm-interworking", cl::Hidden,
69 cl::desc("Enable / disable ARM interworking (for debugging only)"),
72 void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
73 EVT PromotedBitwiseVT) {
74 if (VT != PromotedLdStVT) {
75 setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
76 AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
77 PromotedLdStVT.getSimpleVT());
79 setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
80 AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
81 PromotedLdStVT.getSimpleVT());
84 EVT ElemTy = VT.getVectorElementType();
85 if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
86 setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
87 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
88 if (ElemTy != MVT::i32) {
89 setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
90 setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand);
91 setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand);
92 setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand);
94 setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
95 setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
96 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal);
97 setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Expand);
98 setOperationAction(ISD::SELECT, VT.getSimpleVT(), Expand);
99 setOperationAction(ISD::SELECT_CC, VT.getSimpleVT(), Expand);
100 if (VT.isInteger()) {
101 setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
102 setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
103 setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
104 setLoadExtAction(ISD::SEXTLOAD, VT.getSimpleVT(), Expand);
105 setLoadExtAction(ISD::ZEXTLOAD, VT.getSimpleVT(), Expand);
106 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
107 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
108 setTruncStoreAction(VT.getSimpleVT(),
109 (MVT::SimpleValueType)InnerVT, Expand);
111 setLoadExtAction(ISD::EXTLOAD, VT.getSimpleVT(), Expand);
113 // Promote all bit-wise operations.
114 if (VT.isInteger() && VT != PromotedBitwiseVT) {
115 setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
116 AddPromotedToType (ISD::AND, VT.getSimpleVT(),
117 PromotedBitwiseVT.getSimpleVT());
118 setOperationAction(ISD::OR, VT.getSimpleVT(), Promote);
119 AddPromotedToType (ISD::OR, VT.getSimpleVT(),
120 PromotedBitwiseVT.getSimpleVT());
121 setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
122 AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
123 PromotedBitwiseVT.getSimpleVT());
126 // Neon does not support vector divide/remainder operations.
127 setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
128 setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
129 setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand);
130 setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
131 setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
132 setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
135 void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
136 addRegisterClass(VT, ARM::DPRRegisterClass);
137 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
140 void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
141 addRegisterClass(VT, ARM::QPRRegisterClass);
142 addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
145 static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
146 if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
147 return new TargetLoweringObjectFileMachO();
149 return new ARMElfTargetObjectFile();
152 ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
153 : TargetLowering(TM, createTLOF(TM)) {
154 Subtarget = &TM.getSubtarget<ARMSubtarget>();
155 RegInfo = TM.getRegisterInfo();
156 Itins = TM.getInstrItineraryData();
158 if (Subtarget->isTargetDarwin()) {
159 // Uses VFP for Thumb libfuncs if available.
160 if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
161 // Single-precision floating-point arithmetic.
162 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
163 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
164 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
165 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
167 // Double-precision floating-point arithmetic.
168 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
169 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
170 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
171 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
173 // Single-precision comparisons.
174 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
175 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
176 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
177 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
178 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
179 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
180 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp");
181 setLibcallName(RTLIB::O_F32, "__unordsf2vfp");
183 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
184 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
185 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
186 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
187 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
188 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
189 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
190 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
192 // Double-precision comparisons.
193 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
194 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
195 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
196 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
197 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
198 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
199 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp");
200 setLibcallName(RTLIB::O_F64, "__unorddf2vfp");
202 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
203 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
204 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
205 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
206 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
207 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
208 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
209 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
211 // Floating-point to integer conversions.
212 // i64 conversions are done via library routines even when generating VFP
213 // instructions, so use the same ones.
214 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
215 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
216 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
217 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
219 // Conversions between floating types.
220 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
221 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp");
223 // Integer to floating-point conversions.
224 // i64 conversions are done via library routines even when generating VFP
225 // instructions, so use the same ones.
226 // FIXME: There appears to be some naming inconsistency in ARM libgcc:
227 // e.g., __floatunsidf vs. __floatunssidfvfp.
228 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
229 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
230 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
231 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
235 // These libcalls are not available in 32-bit.
236 setLibcallName(RTLIB::SHL_I128, 0);
237 setLibcallName(RTLIB::SRL_I128, 0);
238 setLibcallName(RTLIB::SRA_I128, 0);
240 if (Subtarget->isAAPCS_ABI()) {
241 // Double-precision floating-point arithmetic helper functions
242 // RTABI chapter 4.1.2, Table 2
243 setLibcallName(RTLIB::ADD_F64, "__aeabi_dadd");
244 setLibcallName(RTLIB::DIV_F64, "__aeabi_ddiv");
245 setLibcallName(RTLIB::MUL_F64, "__aeabi_dmul");
246 setLibcallName(RTLIB::SUB_F64, "__aeabi_dsub");
247 setLibcallCallingConv(RTLIB::ADD_F64, CallingConv::ARM_AAPCS);
248 setLibcallCallingConv(RTLIB::DIV_F64, CallingConv::ARM_AAPCS);
249 setLibcallCallingConv(RTLIB::MUL_F64, CallingConv::ARM_AAPCS);
250 setLibcallCallingConv(RTLIB::SUB_F64, CallingConv::ARM_AAPCS);
252 // Double-precision floating-point comparison helper functions
253 // RTABI chapter 4.1.2, Table 3
254 setLibcallName(RTLIB::OEQ_F64, "__aeabi_dcmpeq");
255 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
256 setLibcallName(RTLIB::UNE_F64, "__aeabi_dcmpeq");
257 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETEQ);
258 setLibcallName(RTLIB::OLT_F64, "__aeabi_dcmplt");
259 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
260 setLibcallName(RTLIB::OLE_F64, "__aeabi_dcmple");
261 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
262 setLibcallName(RTLIB::OGE_F64, "__aeabi_dcmpge");
263 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
264 setLibcallName(RTLIB::OGT_F64, "__aeabi_dcmpgt");
265 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
266 setLibcallName(RTLIB::UO_F64, "__aeabi_dcmpun");
267 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE);
268 setLibcallName(RTLIB::O_F64, "__aeabi_dcmpun");
269 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ);
270 setLibcallCallingConv(RTLIB::OEQ_F64, CallingConv::ARM_AAPCS);
271 setLibcallCallingConv(RTLIB::UNE_F64, CallingConv::ARM_AAPCS);
272 setLibcallCallingConv(RTLIB::OLT_F64, CallingConv::ARM_AAPCS);
273 setLibcallCallingConv(RTLIB::OLE_F64, CallingConv::ARM_AAPCS);
274 setLibcallCallingConv(RTLIB::OGE_F64, CallingConv::ARM_AAPCS);
275 setLibcallCallingConv(RTLIB::OGT_F64, CallingConv::ARM_AAPCS);
276 setLibcallCallingConv(RTLIB::UO_F64, CallingConv::ARM_AAPCS);
277 setLibcallCallingConv(RTLIB::O_F64, CallingConv::ARM_AAPCS);
279 // Single-precision floating-point arithmetic helper functions
280 // RTABI chapter 4.1.2, Table 4
281 setLibcallName(RTLIB::ADD_F32, "__aeabi_fadd");
282 setLibcallName(RTLIB::DIV_F32, "__aeabi_fdiv");
283 setLibcallName(RTLIB::MUL_F32, "__aeabi_fmul");
284 setLibcallName(RTLIB::SUB_F32, "__aeabi_fsub");
285 setLibcallCallingConv(RTLIB::ADD_F32, CallingConv::ARM_AAPCS);
286 setLibcallCallingConv(RTLIB::DIV_F32, CallingConv::ARM_AAPCS);
287 setLibcallCallingConv(RTLIB::MUL_F32, CallingConv::ARM_AAPCS);
288 setLibcallCallingConv(RTLIB::SUB_F32, CallingConv::ARM_AAPCS);
290 // Single-precision floating-point comparison helper functions
291 // RTABI chapter 4.1.2, Table 5
292 setLibcallName(RTLIB::OEQ_F32, "__aeabi_fcmpeq");
293 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
294 setLibcallName(RTLIB::UNE_F32, "__aeabi_fcmpeq");
295 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETEQ);
296 setLibcallName(RTLIB::OLT_F32, "__aeabi_fcmplt");
297 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
298 setLibcallName(RTLIB::OLE_F32, "__aeabi_fcmple");
299 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
300 setLibcallName(RTLIB::OGE_F32, "__aeabi_fcmpge");
301 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
302 setLibcallName(RTLIB::OGT_F32, "__aeabi_fcmpgt");
303 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
304 setLibcallName(RTLIB::UO_F32, "__aeabi_fcmpun");
305 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE);
306 setLibcallName(RTLIB::O_F32, "__aeabi_fcmpun");
307 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ);
308 setLibcallCallingConv(RTLIB::OEQ_F32, CallingConv::ARM_AAPCS);
309 setLibcallCallingConv(RTLIB::UNE_F32, CallingConv::ARM_AAPCS);
310 setLibcallCallingConv(RTLIB::OLT_F32, CallingConv::ARM_AAPCS);
311 setLibcallCallingConv(RTLIB::OLE_F32, CallingConv::ARM_AAPCS);
312 setLibcallCallingConv(RTLIB::OGE_F32, CallingConv::ARM_AAPCS);
313 setLibcallCallingConv(RTLIB::OGT_F32, CallingConv::ARM_AAPCS);
314 setLibcallCallingConv(RTLIB::UO_F32, CallingConv::ARM_AAPCS);
315 setLibcallCallingConv(RTLIB::O_F32, CallingConv::ARM_AAPCS);
317 // Floating-point to integer conversions.
318 // RTABI chapter 4.1.2, Table 6
319 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz");
320 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz");
321 setLibcallName(RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz");
322 setLibcallName(RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz");
323 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz");
324 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz");
325 setLibcallName(RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz");
326 setLibcallName(RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz");
327 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I32, CallingConv::ARM_AAPCS);
328 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I32, CallingConv::ARM_AAPCS);
329 setLibcallCallingConv(RTLIB::FPTOSINT_F64_I64, CallingConv::ARM_AAPCS);
330 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::ARM_AAPCS);
331 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I32, CallingConv::ARM_AAPCS);
332 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I32, CallingConv::ARM_AAPCS);
333 setLibcallCallingConv(RTLIB::FPTOSINT_F32_I64, CallingConv::ARM_AAPCS);
334 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::ARM_AAPCS);
336 // Conversions between floating types.
337 // RTABI chapter 4.1.2, Table 7
338 setLibcallName(RTLIB::FPROUND_F64_F32, "__aeabi_d2f");
339 setLibcallName(RTLIB::FPEXT_F32_F64, "__aeabi_f2d");
340 setLibcallCallingConv(RTLIB::FPROUND_F64_F32, CallingConv::ARM_AAPCS);
341 setLibcallCallingConv(RTLIB::FPEXT_F32_F64, CallingConv::ARM_AAPCS);
343 // Integer to floating-point conversions.
344 // RTABI chapter 4.1.2, Table 8
345 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d");
346 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d");
347 setLibcallName(RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d");
348 setLibcallName(RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d");
349 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f");
350 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f");
351 setLibcallName(RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f");
352 setLibcallName(RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f");
353 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
354 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
355 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
356 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
357 setLibcallCallingConv(RTLIB::SINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
358 setLibcallCallingConv(RTLIB::UINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
359 setLibcallCallingConv(RTLIB::SINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
360 setLibcallCallingConv(RTLIB::UINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
362 // Long long helper functions
363 // RTABI chapter 4.2, Table 9
364 setLibcallName(RTLIB::MUL_I64, "__aeabi_lmul");
365 setLibcallName(RTLIB::SDIV_I64, "__aeabi_ldivmod");
366 setLibcallName(RTLIB::UDIV_I64, "__aeabi_uldivmod");
367 setLibcallName(RTLIB::SHL_I64, "__aeabi_llsl");
368 setLibcallName(RTLIB::SRL_I64, "__aeabi_llsr");
369 setLibcallName(RTLIB::SRA_I64, "__aeabi_lasr");
370 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::ARM_AAPCS);
371 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::ARM_AAPCS);
372 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::ARM_AAPCS);
373 setLibcallCallingConv(RTLIB::SHL_I64, CallingConv::ARM_AAPCS);
374 setLibcallCallingConv(RTLIB::SRL_I64, CallingConv::ARM_AAPCS);
375 setLibcallCallingConv(RTLIB::SRA_I64, CallingConv::ARM_AAPCS);
377 // Integer division functions
378 // RTABI chapter 4.3.1
379 setLibcallName(RTLIB::SDIV_I8, "__aeabi_idiv");
380 setLibcallName(RTLIB::SDIV_I16, "__aeabi_idiv");
381 setLibcallName(RTLIB::SDIV_I32, "__aeabi_idiv");
382 setLibcallName(RTLIB::UDIV_I8, "__aeabi_uidiv");
383 setLibcallName(RTLIB::UDIV_I16, "__aeabi_uidiv");
384 setLibcallName(RTLIB::UDIV_I32, "__aeabi_uidiv");
385 setLibcallCallingConv(RTLIB::SDIV_I8, CallingConv::ARM_AAPCS);
386 setLibcallCallingConv(RTLIB::SDIV_I16, CallingConv::ARM_AAPCS);
387 setLibcallCallingConv(RTLIB::SDIV_I32, CallingConv::ARM_AAPCS);
388 setLibcallCallingConv(RTLIB::UDIV_I8, CallingConv::ARM_AAPCS);
389 setLibcallCallingConv(RTLIB::UDIV_I16, CallingConv::ARM_AAPCS);
390 setLibcallCallingConv(RTLIB::UDIV_I32, CallingConv::ARM_AAPCS);
393 if (Subtarget->isThumb1Only())
394 addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
396 addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
397 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
398 addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
399 if (!Subtarget->isFPOnlySP())
400 addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
402 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
405 if (Subtarget->hasNEON()) {
406 addDRTypeForNEON(MVT::v2f32);
407 addDRTypeForNEON(MVT::v8i8);
408 addDRTypeForNEON(MVT::v4i16);
409 addDRTypeForNEON(MVT::v2i32);
410 addDRTypeForNEON(MVT::v1i64);
412 addQRTypeForNEON(MVT::v4f32);
413 addQRTypeForNEON(MVT::v2f64);
414 addQRTypeForNEON(MVT::v16i8);
415 addQRTypeForNEON(MVT::v8i16);
416 addQRTypeForNEON(MVT::v4i32);
417 addQRTypeForNEON(MVT::v2i64);
419 // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
420 // neither Neon nor VFP support any arithmetic operations on it.
421 setOperationAction(ISD::FADD, MVT::v2f64, Expand);
422 setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
423 setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
424 setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
425 setOperationAction(ISD::FREM, MVT::v2f64, Expand);
426 setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
427 setOperationAction(ISD::VSETCC, MVT::v2f64, Expand);
428 setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
429 setOperationAction(ISD::FABS, MVT::v2f64, Expand);
430 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
431 setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
432 setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
433 setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
434 setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
435 setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
436 setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
437 setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
438 setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
439 setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
440 setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
441 setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
442 setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
443 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
444 setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
446 setTruncStoreAction(MVT::v2f64, MVT::v2f32, Expand);
448 // Neon does not support some operations on v1i64 and v2i64 types.
449 setOperationAction(ISD::MUL, MVT::v1i64, Expand);
450 // Custom handling for some quad-vector types to detect VMULL.
451 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
452 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
453 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
454 setOperationAction(ISD::VSETCC, MVT::v1i64, Expand);
455 setOperationAction(ISD::VSETCC, MVT::v2i64, Expand);
457 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
458 setTargetDAGCombine(ISD::SHL);
459 setTargetDAGCombine(ISD::SRL);
460 setTargetDAGCombine(ISD::SRA);
461 setTargetDAGCombine(ISD::SIGN_EXTEND);
462 setTargetDAGCombine(ISD::ZERO_EXTEND);
463 setTargetDAGCombine(ISD::ANY_EXTEND);
464 setTargetDAGCombine(ISD::SELECT_CC);
465 setTargetDAGCombine(ISD::BUILD_VECTOR);
466 setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
467 setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
468 setTargetDAGCombine(ISD::STORE);
471 computeRegisterProperties();
473 // ARM does not have f32 extending load.
474 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
476 // ARM does not have i1 sign extending load.
477 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
479 // ARM supports all 4 flavors of integer indexed load / store.
480 if (!Subtarget->isThumb1Only()) {
481 for (unsigned im = (unsigned)ISD::PRE_INC;
482 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
483 setIndexedLoadAction(im, MVT::i1, Legal);
484 setIndexedLoadAction(im, MVT::i8, Legal);
485 setIndexedLoadAction(im, MVT::i16, Legal);
486 setIndexedLoadAction(im, MVT::i32, Legal);
487 setIndexedStoreAction(im, MVT::i1, Legal);
488 setIndexedStoreAction(im, MVT::i8, Legal);
489 setIndexedStoreAction(im, MVT::i16, Legal);
490 setIndexedStoreAction(im, MVT::i32, Legal);
494 // i64 operation support.
495 if (Subtarget->isThumb1Only()) {
496 setOperationAction(ISD::MUL, MVT::i64, Expand);
497 setOperationAction(ISD::MULHU, MVT::i32, Expand);
498 setOperationAction(ISD::MULHS, MVT::i32, Expand);
499 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
500 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
502 setOperationAction(ISD::MUL, MVT::i64, Expand);
503 setOperationAction(ISD::MULHU, MVT::i32, Expand);
504 if (!Subtarget->hasV6Ops())
505 setOperationAction(ISD::MULHS, MVT::i32, Expand);
507 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
508 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
509 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
510 setOperationAction(ISD::SRL, MVT::i64, Custom);
511 setOperationAction(ISD::SRA, MVT::i64, Custom);
513 // ARM does not have ROTL.
514 setOperationAction(ISD::ROTL, MVT::i32, Expand);
515 setOperationAction(ISD::CTTZ, MVT::i32, Custom);
516 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
517 if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
518 setOperationAction(ISD::CTLZ, MVT::i32, Expand);
520 // Only ARMv6 has BSWAP.
521 if (!Subtarget->hasV6Ops())
522 setOperationAction(ISD::BSWAP, MVT::i32, Expand);
524 // These are expanded into libcalls.
525 if (!Subtarget->hasDivide() || !Subtarget->isThumb2()) {
526 // v7M has a hardware divider
527 setOperationAction(ISD::SDIV, MVT::i32, Expand);
528 setOperationAction(ISD::UDIV, MVT::i32, Expand);
530 setOperationAction(ISD::SREM, MVT::i32, Expand);
531 setOperationAction(ISD::UREM, MVT::i32, Expand);
532 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
533 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
535 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
536 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
537 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
538 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
539 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
541 setOperationAction(ISD::TRAP, MVT::Other, Legal);
543 // Use the default implementation.
544 setOperationAction(ISD::VASTART, MVT::Other, Custom);
545 setOperationAction(ISD::VAARG, MVT::Other, Expand);
546 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
547 setOperationAction(ISD::VAEND, MVT::Other, Expand);
548 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
549 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
550 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
551 // FIXME: Shouldn't need this, since no register is used, but the legalizer
552 // doesn't yet know how to not do that for SjLj.
553 setExceptionSelectorRegister(ARM::R0);
554 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
555 // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
556 // the default expansion.
557 if (Subtarget->hasDataBarrier() ||
558 (Subtarget->hasV6Ops() && !Subtarget->isThumb())) {
559 // membarrier needs custom lowering; the rest are legal and handled
561 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom);
563 // Set them all for expansion, which will force libcalls.
564 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
565 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Expand);
566 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Expand);
567 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
568 setOperationAction(ISD::ATOMIC_SWAP, MVT::i8, Expand);
569 setOperationAction(ISD::ATOMIC_SWAP, MVT::i16, Expand);
570 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
571 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i8, Expand);
572 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i16, Expand);
573 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
574 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Expand);
575 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Expand);
576 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
577 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i8, Expand);
578 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i16, Expand);
579 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
580 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i8, Expand);
581 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i16, Expand);
582 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
583 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i8, Expand);
584 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i16, Expand);
585 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
586 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i8, Expand);
587 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i16, Expand);
588 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
589 // Since the libcalls include locking, fold in the fences
590 setShouldFoldAtomicFences(true);
592 // 64-bit versions are always libcalls (for now)
593 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Expand);
594 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Expand);
595 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Expand);
596 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Expand);
597 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Expand);
598 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Expand);
599 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Expand);
600 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Expand);
602 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
604 // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
605 if (!Subtarget->hasV6Ops()) {
606 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
607 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
609 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
611 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
612 // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
613 // iff target supports vfp2.
614 setOperationAction(ISD::BITCAST, MVT::i64, Custom);
615 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
618 // We want to custom lower some of our intrinsics.
619 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
620 if (Subtarget->isTargetDarwin()) {
621 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
622 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
623 setOperationAction(ISD::EH_SJLJ_DISPATCHSETUP, MVT::Other, Custom);
626 setOperationAction(ISD::SETCC, MVT::i32, Expand);
627 setOperationAction(ISD::SETCC, MVT::f32, Expand);
628 setOperationAction(ISD::SETCC, MVT::f64, Expand);
629 setOperationAction(ISD::SELECT, MVT::i32, Custom);
630 setOperationAction(ISD::SELECT, MVT::f32, Custom);
631 setOperationAction(ISD::SELECT, MVT::f64, Custom);
632 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
633 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
634 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
636 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
637 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
638 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
639 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
640 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
642 // We don't support sin/cos/fmod/copysign/pow
643 setOperationAction(ISD::FSIN, MVT::f64, Expand);
644 setOperationAction(ISD::FSIN, MVT::f32, Expand);
645 setOperationAction(ISD::FCOS, MVT::f32, Expand);
646 setOperationAction(ISD::FCOS, MVT::f64, Expand);
647 setOperationAction(ISD::FREM, MVT::f64, Expand);
648 setOperationAction(ISD::FREM, MVT::f32, Expand);
649 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
650 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
651 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
653 setOperationAction(ISD::FPOW, MVT::f64, Expand);
654 setOperationAction(ISD::FPOW, MVT::f32, Expand);
656 // Various VFP goodness
657 if (!UseSoftFloat && !Subtarget->isThumb1Only()) {
658 // int <-> fp are custom expanded into bit_convert + ARMISD ops.
659 if (Subtarget->hasVFP2()) {
660 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
661 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
662 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
663 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
665 // Special handling for half-precision FP.
666 if (!Subtarget->hasFP16()) {
667 setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
668 setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand);
672 // We have target-specific dag combine patterns for the following nodes:
673 // ARMISD::VMOVRRD - No need to call setTargetDAGCombine
674 setTargetDAGCombine(ISD::ADD);
675 setTargetDAGCombine(ISD::SUB);
676 setTargetDAGCombine(ISD::MUL);
678 if (Subtarget->hasV6T2Ops() || Subtarget->hasNEON())
679 setTargetDAGCombine(ISD::OR);
680 if (Subtarget->hasNEON())
681 setTargetDAGCombine(ISD::AND);
683 setStackPointerRegisterToSaveRestore(ARM::SP);
685 if (UseSoftFloat || Subtarget->isThumb1Only() || !Subtarget->hasVFP2())
686 setSchedulingPreference(Sched::RegPressure);
688 setSchedulingPreference(Sched::Hybrid);
690 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type
692 // On ARM arguments smaller than 4 bytes are extended, so all arguments
693 // are at least 4 bytes aligned.
694 setMinStackArgumentAlignment(4);
696 benefitFromCodePlacementOpt = true;
699 std::pair<const TargetRegisterClass*, uint8_t>
700 ARMTargetLowering::findRepresentativeClass(EVT VT) const{
701 const TargetRegisterClass *RRC = 0;
703 switch (VT.getSimpleVT().SimpleTy) {
705 return TargetLowering::findRepresentativeClass(VT);
706 // Use DPR as representative register class for all floating point
707 // and vector types. Since there are 32 SPR registers and 32 DPR registers so
708 // the cost is 1 for both f32 and f64.
709 case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
710 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
711 RRC = ARM::DPRRegisterClass;
713 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
714 case MVT::v4f32: case MVT::v2f64:
715 RRC = ARM::DPRRegisterClass;
719 RRC = ARM::DPRRegisterClass;
723 RRC = ARM::DPRRegisterClass;
727 return std::make_pair(RRC, Cost);
730 const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
733 case ARMISD::Wrapper: return "ARMISD::Wrapper";
734 case ARMISD::WrapperJT: return "ARMISD::WrapperJT";
735 case ARMISD::CALL: return "ARMISD::CALL";
736 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED";
737 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK";
738 case ARMISD::tCALL: return "ARMISD::tCALL";
739 case ARMISD::BRCOND: return "ARMISD::BRCOND";
740 case ARMISD::BR_JT: return "ARMISD::BR_JT";
741 case ARMISD::BR2_JT: return "ARMISD::BR2_JT";
742 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG";
743 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD";
744 case ARMISD::CMP: return "ARMISD::CMP";
745 case ARMISD::CMPZ: return "ARMISD::CMPZ";
746 case ARMISD::CMPFP: return "ARMISD::CMPFP";
747 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0";
748 case ARMISD::BCC_i64: return "ARMISD::BCC_i64";
749 case ARMISD::FMSTAT: return "ARMISD::FMSTAT";
750 case ARMISD::CMOV: return "ARMISD::CMOV";
751 case ARMISD::CNEG: return "ARMISD::CNEG";
753 case ARMISD::RBIT: return "ARMISD::RBIT";
755 case ARMISD::FTOSI: return "ARMISD::FTOSI";
756 case ARMISD::FTOUI: return "ARMISD::FTOUI";
757 case ARMISD::SITOF: return "ARMISD::SITOF";
758 case ARMISD::UITOF: return "ARMISD::UITOF";
760 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG";
761 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG";
762 case ARMISD::RRX: return "ARMISD::RRX";
764 case ARMISD::VMOVRRD: return "ARMISD::VMOVRRD";
765 case ARMISD::VMOVDRR: return "ARMISD::VMOVDRR";
767 case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
768 case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
769 case ARMISD::EH_SJLJ_DISPATCHSETUP:return "ARMISD::EH_SJLJ_DISPATCHSETUP";
771 case ARMISD::TC_RETURN: return "ARMISD::TC_RETURN";
773 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
775 case ARMISD::DYN_ALLOC: return "ARMISD::DYN_ALLOC";
777 case ARMISD::MEMBARRIER: return "ARMISD::MEMBARRIER";
778 case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
780 case ARMISD::PRELOAD: return "ARMISD::PRELOAD";
782 case ARMISD::VCEQ: return "ARMISD::VCEQ";
783 case ARMISD::VCEQZ: return "ARMISD::VCEQZ";
784 case ARMISD::VCGE: return "ARMISD::VCGE";
785 case ARMISD::VCGEZ: return "ARMISD::VCGEZ";
786 case ARMISD::VCLEZ: return "ARMISD::VCLEZ";
787 case ARMISD::VCGEU: return "ARMISD::VCGEU";
788 case ARMISD::VCGT: return "ARMISD::VCGT";
789 case ARMISD::VCGTZ: return "ARMISD::VCGTZ";
790 case ARMISD::VCLTZ: return "ARMISD::VCLTZ";
791 case ARMISD::VCGTU: return "ARMISD::VCGTU";
792 case ARMISD::VTST: return "ARMISD::VTST";
794 case ARMISD::VSHL: return "ARMISD::VSHL";
795 case ARMISD::VSHRs: return "ARMISD::VSHRs";
796 case ARMISD::VSHRu: return "ARMISD::VSHRu";
797 case ARMISD::VSHLLs: return "ARMISD::VSHLLs";
798 case ARMISD::VSHLLu: return "ARMISD::VSHLLu";
799 case ARMISD::VSHLLi: return "ARMISD::VSHLLi";
800 case ARMISD::VSHRN: return "ARMISD::VSHRN";
801 case ARMISD::VRSHRs: return "ARMISD::VRSHRs";
802 case ARMISD::VRSHRu: return "ARMISD::VRSHRu";
803 case ARMISD::VRSHRN: return "ARMISD::VRSHRN";
804 case ARMISD::VQSHLs: return "ARMISD::VQSHLs";
805 case ARMISD::VQSHLu: return "ARMISD::VQSHLu";
806 case ARMISD::VQSHLsu: return "ARMISD::VQSHLsu";
807 case ARMISD::VQSHRNs: return "ARMISD::VQSHRNs";
808 case ARMISD::VQSHRNu: return "ARMISD::VQSHRNu";
809 case ARMISD::VQSHRNsu: return "ARMISD::VQSHRNsu";
810 case ARMISD::VQRSHRNs: return "ARMISD::VQRSHRNs";
811 case ARMISD::VQRSHRNu: return "ARMISD::VQRSHRNu";
812 case ARMISD::VQRSHRNsu: return "ARMISD::VQRSHRNsu";
813 case ARMISD::VGETLANEu: return "ARMISD::VGETLANEu";
814 case ARMISD::VGETLANEs: return "ARMISD::VGETLANEs";
815 case ARMISD::VMOVIMM: return "ARMISD::VMOVIMM";
816 case ARMISD::VMVNIMM: return "ARMISD::VMVNIMM";
817 case ARMISD::VDUP: return "ARMISD::VDUP";
818 case ARMISD::VDUPLANE: return "ARMISD::VDUPLANE";
819 case ARMISD::VEXT: return "ARMISD::VEXT";
820 case ARMISD::VREV64: return "ARMISD::VREV64";
821 case ARMISD::VREV32: return "ARMISD::VREV32";
822 case ARMISD::VREV16: return "ARMISD::VREV16";
823 case ARMISD::VZIP: return "ARMISD::VZIP";
824 case ARMISD::VUZP: return "ARMISD::VUZP";
825 case ARMISD::VTRN: return "ARMISD::VTRN";
826 case ARMISD::VMULLs: return "ARMISD::VMULLs";
827 case ARMISD::VMULLu: return "ARMISD::VMULLu";
828 case ARMISD::BUILD_VECTOR: return "ARMISD::BUILD_VECTOR";
829 case ARMISD::FMAX: return "ARMISD::FMAX";
830 case ARMISD::FMIN: return "ARMISD::FMIN";
831 case ARMISD::BFI: return "ARMISD::BFI";
832 case ARMISD::VORRIMM: return "ARMISD::VORRIMM";
833 case ARMISD::VBICIMM: return "ARMISD::VBICIMM";
834 case ARMISD::VLD2DUP: return "ARMISD::VLD2DUP";
835 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP";
836 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP";
840 /// getRegClassFor - Return the register class that should be used for the
841 /// specified value type.
842 TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const {
843 // Map v4i64 to QQ registers but do not make the type legal. Similarly map
844 // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
845 // load / store 4 to 8 consecutive D registers.
846 if (Subtarget->hasNEON()) {
847 if (VT == MVT::v4i64)
848 return ARM::QQPRRegisterClass;
849 else if (VT == MVT::v8i64)
850 return ARM::QQQQPRRegisterClass;
852 return TargetLowering::getRegClassFor(VT);
855 // Create a fast isel object.
857 ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const {
858 return ARM::createFastISel(funcInfo);
861 /// getFunctionAlignment - Return the Log2 alignment of this function.
862 unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
863 return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 1 : 2;
866 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
867 /// be used for loads / stores from the global.
868 unsigned ARMTargetLowering::getMaximalGlobalOffset() const {
869 return (Subtarget->isThumb1Only() ? 127 : 4095);
872 Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
873 unsigned NumVals = N->getNumValues();
875 return Sched::RegPressure;
877 for (unsigned i = 0; i != NumVals; ++i) {
878 EVT VT = N->getValueType(i);
879 if (VT == MVT::Glue || VT == MVT::Other)
881 if (VT.isFloatingPoint() || VT.isVector())
882 return Sched::Latency;
885 if (!N->isMachineOpcode())
886 return Sched::RegPressure;
888 // Load are scheduled for latency even if there instruction itinerary
890 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
891 const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
893 if (TID.getNumDefs() == 0)
894 return Sched::RegPressure;
895 if (!Itins->isEmpty() &&
896 Itins->getOperandCycle(TID.getSchedClass(), 0) > 2)
897 return Sched::Latency;
899 return Sched::RegPressure;
903 ARMTargetLowering::getRegPressureLimit(const TargetRegisterClass *RC,
904 MachineFunction &MF) const {
905 const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo();
907 switch (RC->getID()) {
910 case ARM::tGPRRegClassID:
911 return TFI->hasFP(MF) ? 4 : 5;
912 case ARM::GPRRegClassID: {
913 unsigned FP = TFI->hasFP(MF) ? 1 : 0;
914 return 10 - FP - (Subtarget->isR9Reserved() ? 1 : 0);
916 case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
917 case ARM::DPRRegClassID:
922 //===----------------------------------------------------------------------===//
924 //===----------------------------------------------------------------------===//
926 /// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
927 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
929 default: llvm_unreachable("Unknown condition code!");
930 case ISD::SETNE: return ARMCC::NE;
931 case ISD::SETEQ: return ARMCC::EQ;
932 case ISD::SETGT: return ARMCC::GT;
933 case ISD::SETGE: return ARMCC::GE;
934 case ISD::SETLT: return ARMCC::LT;
935 case ISD::SETLE: return ARMCC::LE;
936 case ISD::SETUGT: return ARMCC::HI;
937 case ISD::SETUGE: return ARMCC::HS;
938 case ISD::SETULT: return ARMCC::LO;
939 case ISD::SETULE: return ARMCC::LS;
943 /// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
944 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
945 ARMCC::CondCodes &CondCode2) {
946 CondCode2 = ARMCC::AL;
948 default: llvm_unreachable("Unknown FP condition!");
950 case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
952 case ISD::SETOGT: CondCode = ARMCC::GT; break;
954 case ISD::SETOGE: CondCode = ARMCC::GE; break;
955 case ISD::SETOLT: CondCode = ARMCC::MI; break;
956 case ISD::SETOLE: CondCode = ARMCC::LS; break;
957 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
958 case ISD::SETO: CondCode = ARMCC::VC; break;
959 case ISD::SETUO: CondCode = ARMCC::VS; break;
960 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
961 case ISD::SETUGT: CondCode = ARMCC::HI; break;
962 case ISD::SETUGE: CondCode = ARMCC::PL; break;
964 case ISD::SETULT: CondCode = ARMCC::LT; break;
966 case ISD::SETULE: CondCode = ARMCC::LE; break;
968 case ISD::SETUNE: CondCode = ARMCC::NE; break;
972 //===----------------------------------------------------------------------===//
973 // Calling Convention Implementation
974 //===----------------------------------------------------------------------===//
976 #include "ARMGenCallingConv.inc"
978 /// CCAssignFnForNode - Selects the correct CCAssignFn for a the
979 /// given CallingConvention value.
980 CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
982 bool isVarArg) const {
985 llvm_unreachable("Unsupported calling convention");
986 case CallingConv::Fast:
987 if (Subtarget->hasVFP2() && !isVarArg) {
988 if (!Subtarget->isAAPCS_ABI())
989 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
990 // For AAPCS ABI targets, just use VFP variant of the calling convention.
991 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
994 case CallingConv::C: {
995 // Use target triple & subtarget features to do actual dispatch.
996 if (!Subtarget->isAAPCS_ABI())
997 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
998 else if (Subtarget->hasVFP2() &&
999 FloatABIType == FloatABI::Hard && !isVarArg)
1000 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1001 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1003 case CallingConv::ARM_AAPCS_VFP:
1004 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1005 case CallingConv::ARM_AAPCS:
1006 return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1007 case CallingConv::ARM_APCS:
1008 return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1012 /// LowerCallResult - Lower the result values of a call into the
1013 /// appropriate copies out of appropriate physical registers.
1015 ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1016 CallingConv::ID CallConv, bool isVarArg,
1017 const SmallVectorImpl<ISD::InputArg> &Ins,
1018 DebugLoc dl, SelectionDAG &DAG,
1019 SmallVectorImpl<SDValue> &InVals) const {
1021 // Assign locations to each value returned by this call.
1022 SmallVector<CCValAssign, 16> RVLocs;
1023 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1024 RVLocs, *DAG.getContext());
1025 CCInfo.AnalyzeCallResult(Ins,
1026 CCAssignFnForNode(CallConv, /* Return*/ true,
1029 // Copy all of the result registers out of their specified physreg.
1030 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1031 CCValAssign VA = RVLocs[i];
1034 if (VA.needsCustom()) {
1035 // Handle f64 or half of a v2f64.
1036 SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1038 Chain = Lo.getValue(1);
1039 InFlag = Lo.getValue(2);
1040 VA = RVLocs[++i]; // skip ahead to next loc
1041 SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1043 Chain = Hi.getValue(1);
1044 InFlag = Hi.getValue(2);
1045 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1047 if (VA.getLocVT() == MVT::v2f64) {
1048 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1049 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1050 DAG.getConstant(0, MVT::i32));
1052 VA = RVLocs[++i]; // skip ahead to next loc
1053 Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1054 Chain = Lo.getValue(1);
1055 InFlag = Lo.getValue(2);
1056 VA = RVLocs[++i]; // skip ahead to next loc
1057 Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1058 Chain = Hi.getValue(1);
1059 InFlag = Hi.getValue(2);
1060 Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1061 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1062 DAG.getConstant(1, MVT::i32));
1065 Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1067 Chain = Val.getValue(1);
1068 InFlag = Val.getValue(2);
1071 switch (VA.getLocInfo()) {
1072 default: llvm_unreachable("Unknown loc info!");
1073 case CCValAssign::Full: break;
1074 case CCValAssign::BCvt:
1075 Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1079 InVals.push_back(Val);
1085 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1086 /// by "Src" to address "Dst" of size "Size". Alignment information is
1087 /// specified by the specific parameter attribute. The copy will be passed as
1088 /// a byval function parameter.
1089 /// Sometimes what we are copying is the end of a larger object, the part that
1090 /// does not fit in registers.
1092 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
1093 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1095 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
1096 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
1097 /*isVolatile=*/false, /*AlwaysInline=*/false,
1098 MachinePointerInfo(0), MachinePointerInfo(0));
1101 /// LowerMemOpCallTo - Store the argument to the stack.
1103 ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
1104 SDValue StackPtr, SDValue Arg,
1105 DebugLoc dl, SelectionDAG &DAG,
1106 const CCValAssign &VA,
1107 ISD::ArgFlagsTy Flags) const {
1108 unsigned LocMemOffset = VA.getLocMemOffset();
1109 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1110 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1111 if (Flags.isByVal())
1112 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
1114 return DAG.getStore(Chain, dl, Arg, PtrOff,
1115 MachinePointerInfo::getStack(LocMemOffset),
1119 void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
1120 SDValue Chain, SDValue &Arg,
1121 RegsToPassVector &RegsToPass,
1122 CCValAssign &VA, CCValAssign &NextVA,
1124 SmallVector<SDValue, 8> &MemOpChains,
1125 ISD::ArgFlagsTy Flags) const {
1127 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1128 DAG.getVTList(MVT::i32, MVT::i32), Arg);
1129 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
1131 if (NextVA.isRegLoc())
1132 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
1134 assert(NextVA.isMemLoc());
1135 if (StackPtr.getNode() == 0)
1136 StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1138 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
1144 /// LowerCall - Lowering a call into a callseq_start <-
1145 /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1148 ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
1149 CallingConv::ID CallConv, bool isVarArg,
1151 const SmallVectorImpl<ISD::OutputArg> &Outs,
1152 const SmallVectorImpl<SDValue> &OutVals,
1153 const SmallVectorImpl<ISD::InputArg> &Ins,
1154 DebugLoc dl, SelectionDAG &DAG,
1155 SmallVectorImpl<SDValue> &InVals) const {
1156 MachineFunction &MF = DAG.getMachineFunction();
1157 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1158 bool IsSibCall = false;
1159 // Temporarily disable tail calls so things don't break.
1160 if (!EnableARMTailCalls)
1163 // Check if it's really possible to do a tail call.
1164 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1165 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(),
1166 Outs, OutVals, Ins, DAG);
1167 // We don't support GuaranteedTailCallOpt for ARM, only automatically
1168 // detected sibcalls.
1175 // Analyze operands of the call, assigning locations to each operand.
1176 SmallVector<CCValAssign, 16> ArgLocs;
1177 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1179 CCInfo.AnalyzeCallOperands(Outs,
1180 CCAssignFnForNode(CallConv, /* Return*/ false,
1183 // Get a count of how many bytes are to be pushed on the stack.
1184 unsigned NumBytes = CCInfo.getNextStackOffset();
1186 // For tail calls, memory operands are available in our caller's stack.
1190 // Adjust the stack pointer for the new arguments...
1191 // These operations are automatically eliminated by the prolog/epilog pass
1193 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
1195 SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1197 RegsToPassVector RegsToPass;
1198 SmallVector<SDValue, 8> MemOpChains;
1200 // Walk the register/memloc assignments, inserting copies/loads. In the case
1201 // of tail call optimization, arguments are handled later.
1202 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1204 ++i, ++realArgIdx) {
1205 CCValAssign &VA = ArgLocs[i];
1206 SDValue Arg = OutVals[realArgIdx];
1207 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1209 // Promote the value if needed.
1210 switch (VA.getLocInfo()) {
1211 default: llvm_unreachable("Unknown loc info!");
1212 case CCValAssign::Full: break;
1213 case CCValAssign::SExt:
1214 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1216 case CCValAssign::ZExt:
1217 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1219 case CCValAssign::AExt:
1220 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1222 case CCValAssign::BCvt:
1223 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1227 // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1228 if (VA.needsCustom()) {
1229 if (VA.getLocVT() == MVT::v2f64) {
1230 SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1231 DAG.getConstant(0, MVT::i32));
1232 SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1233 DAG.getConstant(1, MVT::i32));
1235 PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1236 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1238 VA = ArgLocs[++i]; // skip ahead to next loc
1239 if (VA.isRegLoc()) {
1240 PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1241 VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1243 assert(VA.isMemLoc());
1245 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1246 dl, DAG, VA, Flags));
1249 PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1250 StackPtr, MemOpChains, Flags);
1252 } else if (VA.isRegLoc()) {
1253 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1254 } else if (!IsSibCall) {
1255 assert(VA.isMemLoc());
1257 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1258 dl, DAG, VA, Flags));
1262 if (!MemOpChains.empty())
1263 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1264 &MemOpChains[0], MemOpChains.size());
1266 // Build a sequence of copy-to-reg nodes chained together with token chain
1267 // and flag operands which copy the outgoing args into the appropriate regs.
1269 // Tail call byval lowering might overwrite argument registers so in case of
1270 // tail call optimization the copies to registers are lowered later.
1272 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1273 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1274 RegsToPass[i].second, InFlag);
1275 InFlag = Chain.getValue(1);
1278 // For tail calls lower the arguments to the 'real' stack slot.
1280 // Force all the incoming stack arguments to be loaded from the stack
1281 // before any new outgoing arguments are stored to the stack, because the
1282 // outgoing stack slots may alias the incoming argument stack slots, and
1283 // the alias isn't otherwise explicit. This is slightly more conservative
1284 // than necessary, because it means that each store effectively depends
1285 // on every argument instead of just those arguments it would clobber.
1287 // Do not flag preceeding copytoreg stuff together with the following stuff.
1289 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1290 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1291 RegsToPass[i].second, InFlag);
1292 InFlag = Chain.getValue(1);
1297 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1298 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1299 // node so that legalize doesn't hack it.
1300 bool isDirect = false;
1301 bool isARMFunc = false;
1302 bool isLocalARMFunc = false;
1303 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1305 if (EnableARMLongCalls) {
1306 assert (getTargetMachine().getRelocationModel() == Reloc::Static
1307 && "long-calls with non-static relocation model!");
1308 // Handle a global address or an external symbol. If it's not one of
1309 // those, the target's already in a register, so we don't need to do
1311 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1312 const GlobalValue *GV = G->getGlobal();
1313 // Create a constant pool entry for the callee address
1314 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1315 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1318 // Get the address of the callee into a register
1319 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1320 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1321 Callee = DAG.getLoad(getPointerTy(), dl,
1322 DAG.getEntryNode(), CPAddr,
1323 MachinePointerInfo::getConstantPool(),
1325 } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1326 const char *Sym = S->getSymbol();
1328 // Create a constant pool entry for the callee address
1329 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1330 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1331 Sym, ARMPCLabelIndex, 0);
1332 // Get the address of the callee into a register
1333 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1334 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1335 Callee = DAG.getLoad(getPointerTy(), dl,
1336 DAG.getEntryNode(), CPAddr,
1337 MachinePointerInfo::getConstantPool(),
1340 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1341 const GlobalValue *GV = G->getGlobal();
1343 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1344 bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
1345 getTargetMachine().getRelocationModel() != Reloc::Static;
1346 isARMFunc = !Subtarget->isThumb() || isStub;
1347 // ARM call to a local ARM function is predicable.
1348 isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
1349 // tBX takes a register source operand.
1350 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1351 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1352 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1355 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1356 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1357 Callee = DAG.getLoad(getPointerTy(), dl,
1358 DAG.getEntryNode(), CPAddr,
1359 MachinePointerInfo::getConstantPool(),
1361 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1362 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1363 getPointerTy(), Callee, PICLabel);
1365 // On ELF targets for PIC code, direct calls should go through the PLT
1366 unsigned OpFlags = 0;
1367 if (Subtarget->isTargetELF() &&
1368 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1369 OpFlags = ARMII::MO_PLT;
1370 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
1372 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1374 bool isStub = Subtarget->isTargetDarwin() &&
1375 getTargetMachine().getRelocationModel() != Reloc::Static;
1376 isARMFunc = !Subtarget->isThumb() || isStub;
1377 // tBX takes a register source operand.
1378 const char *Sym = S->getSymbol();
1379 if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1380 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1381 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1382 Sym, ARMPCLabelIndex, 4);
1383 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1384 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1385 Callee = DAG.getLoad(getPointerTy(), dl,
1386 DAG.getEntryNode(), CPAddr,
1387 MachinePointerInfo::getConstantPool(),
1389 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1390 Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1391 getPointerTy(), Callee, PICLabel);
1393 unsigned OpFlags = 0;
1394 // On ELF targets for PIC code, direct calls should go through the PLT
1395 if (Subtarget->isTargetELF() &&
1396 getTargetMachine().getRelocationModel() == Reloc::PIC_)
1397 OpFlags = ARMII::MO_PLT;
1398 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags);
1402 // FIXME: handle tail calls differently.
1404 if (Subtarget->isThumb()) {
1405 if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1406 CallOpc = ARMISD::CALL_NOLINK;
1408 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1410 CallOpc = (isDirect || Subtarget->hasV5TOps())
1411 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
1412 : ARMISD::CALL_NOLINK;
1415 std::vector<SDValue> Ops;
1416 Ops.push_back(Chain);
1417 Ops.push_back(Callee);
1419 // Add argument registers to the end of the list so that they are known live
1421 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1422 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1423 RegsToPass[i].second.getValueType()));
1425 if (InFlag.getNode())
1426 Ops.push_back(InFlag);
1428 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1430 return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
1432 // Returns a chain and a flag for retval copy to use.
1433 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
1434 InFlag = Chain.getValue(1);
1436 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1437 DAG.getIntPtrConstant(0, true), InFlag);
1439 InFlag = Chain.getValue(1);
1441 // Handle result values, copying them out of physregs into vregs that we
1443 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1447 /// MatchingStackOffset - Return true if the given stack call argument is
1448 /// already available in the same position (relatively) of the caller's
1449 /// incoming argument stack.
1451 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1452 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1453 const ARMInstrInfo *TII) {
1454 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
1456 if (Arg.getOpcode() == ISD::CopyFromReg) {
1457 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
1458 if (!VR || TargetRegisterInfo::isPhysicalRegister(VR))
1460 MachineInstr *Def = MRI->getVRegDef(VR);
1463 if (!Flags.isByVal()) {
1464 if (!TII->isLoadFromStackSlot(Def, FI))
1469 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
1470 if (Flags.isByVal())
1471 // ByVal argument is passed in as a pointer but it's now being
1472 // dereferenced. e.g.
1473 // define @foo(%struct.X* %A) {
1474 // tail call @bar(%struct.X* byval %A)
1477 SDValue Ptr = Ld->getBasePtr();
1478 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
1481 FI = FINode->getIndex();
1485 assert(FI != INT_MAX);
1486 if (!MFI->isFixedObjectIndex(FI))
1488 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
1491 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
1492 /// for tail call optimization. Targets which want to do tail call
1493 /// optimization should implement this function.
1495 ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1496 CallingConv::ID CalleeCC,
1498 bool isCalleeStructRet,
1499 bool isCallerStructRet,
1500 const SmallVectorImpl<ISD::OutputArg> &Outs,
1501 const SmallVectorImpl<SDValue> &OutVals,
1502 const SmallVectorImpl<ISD::InputArg> &Ins,
1503 SelectionDAG& DAG) const {
1504 const Function *CallerF = DAG.getMachineFunction().getFunction();
1505 CallingConv::ID CallerCC = CallerF->getCallingConv();
1506 bool CCMatch = CallerCC == CalleeCC;
1508 // Look for obvious safe cases to perform tail call optimization that do not
1509 // require ABI changes. This is what gcc calls sibcall.
1511 // Do not sibcall optimize vararg calls unless the call site is not passing
1513 if (isVarArg && !Outs.empty())
1516 // Also avoid sibcall optimization if either caller or callee uses struct
1517 // return semantics.
1518 if (isCalleeStructRet || isCallerStructRet)
1521 // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
1522 // emitEpilogue is not ready for them.
1523 // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
1524 // LR. This means if we need to reload LR, it takes an extra instructions,
1525 // which outweighs the value of the tail call; but here we don't know yet
1526 // whether LR is going to be used. Probably the right approach is to
1527 // generate the tail call here and turn it back into CALL/RET in
1528 // emitEpilogue if LR is used.
1530 // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
1531 // but we need to make sure there are enough registers; the only valid
1532 // registers are the 4 used for parameters. We don't currently do this
1534 if (Subtarget->isThumb1Only())
1537 // If the calling conventions do not match, then we'd better make sure the
1538 // results are returned in the same way as what the caller expects.
1540 SmallVector<CCValAssign, 16> RVLocs1;
1541 CCState CCInfo1(CalleeCC, false, getTargetMachine(),
1542 RVLocs1, *DAG.getContext());
1543 CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
1545 SmallVector<CCValAssign, 16> RVLocs2;
1546 CCState CCInfo2(CallerCC, false, getTargetMachine(),
1547 RVLocs2, *DAG.getContext());
1548 CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
1550 if (RVLocs1.size() != RVLocs2.size())
1552 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
1553 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
1555 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
1557 if (RVLocs1[i].isRegLoc()) {
1558 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
1561 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
1567 // If the callee takes no arguments then go on to check the results of the
1569 if (!Outs.empty()) {
1570 // Check if stack adjustment is needed. For now, do not do this if any
1571 // argument is passed on the stack.
1572 SmallVector<CCValAssign, 16> ArgLocs;
1573 CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(),
1574 ArgLocs, *DAG.getContext());
1575 CCInfo.AnalyzeCallOperands(Outs,
1576 CCAssignFnForNode(CalleeCC, false, isVarArg));
1577 if (CCInfo.getNextStackOffset()) {
1578 MachineFunction &MF = DAG.getMachineFunction();
1580 // Check if the arguments are already laid out in the right way as
1581 // the caller's fixed stack objects.
1582 MachineFrameInfo *MFI = MF.getFrameInfo();
1583 const MachineRegisterInfo *MRI = &MF.getRegInfo();
1584 const ARMInstrInfo *TII =
1585 ((ARMTargetMachine&)getTargetMachine()).getInstrInfo();
1586 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1588 ++i, ++realArgIdx) {
1589 CCValAssign &VA = ArgLocs[i];
1590 EVT RegVT = VA.getLocVT();
1591 SDValue Arg = OutVals[realArgIdx];
1592 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1593 if (VA.getLocInfo() == CCValAssign::Indirect)
1595 if (VA.needsCustom()) {
1596 // f64 and vector types are split into multiple registers or
1597 // register/stack-slot combinations. The types will not match
1598 // the registers; give up on memory f64 refs until we figure
1599 // out what to do about this.
1602 if (!ArgLocs[++i].isRegLoc())
1604 if (RegVT == MVT::v2f64) {
1605 if (!ArgLocs[++i].isRegLoc())
1607 if (!ArgLocs[++i].isRegLoc())
1610 } else if (!VA.isRegLoc()) {
1611 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
1623 ARMTargetLowering::LowerReturn(SDValue Chain,
1624 CallingConv::ID CallConv, bool isVarArg,
1625 const SmallVectorImpl<ISD::OutputArg> &Outs,
1626 const SmallVectorImpl<SDValue> &OutVals,
1627 DebugLoc dl, SelectionDAG &DAG) const {
1629 // CCValAssign - represent the assignment of the return value to a location.
1630 SmallVector<CCValAssign, 16> RVLocs;
1632 // CCState - Info about the registers and stack slots.
1633 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
1636 // Analyze outgoing return values.
1637 CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1640 // If this is the first return lowered for this function, add
1641 // the regs to the liveout set for the function.
1642 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1643 for (unsigned i = 0; i != RVLocs.size(); ++i)
1644 if (RVLocs[i].isRegLoc())
1645 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1650 // Copy the result values into the output registers.
1651 for (unsigned i = 0, realRVLocIdx = 0;
1653 ++i, ++realRVLocIdx) {
1654 CCValAssign &VA = RVLocs[i];
1655 assert(VA.isRegLoc() && "Can only return in registers!");
1657 SDValue Arg = OutVals[realRVLocIdx];
1659 switch (VA.getLocInfo()) {
1660 default: llvm_unreachable("Unknown loc info!");
1661 case CCValAssign::Full: break;
1662 case CCValAssign::BCvt:
1663 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1667 if (VA.needsCustom()) {
1668 if (VA.getLocVT() == MVT::v2f64) {
1669 // Extract the first half and return it in two registers.
1670 SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1671 DAG.getConstant(0, MVT::i32));
1672 SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
1673 DAG.getVTList(MVT::i32, MVT::i32), Half);
1675 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1676 Flag = Chain.getValue(1);
1677 VA = RVLocs[++i]; // skip ahead to next loc
1678 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1679 HalfGPRs.getValue(1), Flag);
1680 Flag = Chain.getValue(1);
1681 VA = RVLocs[++i]; // skip ahead to next loc
1683 // Extract the 2nd half and fall through to handle it as an f64 value.
1684 Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1685 DAG.getConstant(1, MVT::i32));
1687 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is
1689 SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1690 DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1691 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1692 Flag = Chain.getValue(1);
1693 VA = RVLocs[++i]; // skip ahead to next loc
1694 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1697 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1699 // Guarantee that all emitted copies are
1700 // stuck together, avoiding something bad.
1701 Flag = Chain.getValue(1);
1706 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1708 result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1713 bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N) const {
1714 if (N->getNumValues() != 1)
1716 if (!N->hasNUsesOfValue(1, 0))
1719 unsigned NumCopies = 0;
1721 SDNode *Use = *N->use_begin();
1722 if (Use->getOpcode() == ISD::CopyToReg) {
1723 Copies[NumCopies++] = Use;
1724 } else if (Use->getOpcode() == ARMISD::VMOVRRD) {
1725 // f64 returned in a pair of GPRs.
1726 for (SDNode::use_iterator UI = Use->use_begin(), UE = Use->use_end();
1728 if (UI->getOpcode() != ISD::CopyToReg)
1730 Copies[UI.getUse().getResNo()] = *UI;
1733 } else if (Use->getOpcode() == ISD::BITCAST) {
1734 // f32 returned in a single GPR.
1735 if (!Use->hasNUsesOfValue(1, 0))
1737 Use = *Use->use_begin();
1738 if (Use->getOpcode() != ISD::CopyToReg || !Use->hasNUsesOfValue(1, 0))
1740 Copies[NumCopies++] = Use;
1745 if (NumCopies != 1 && NumCopies != 2)
1748 bool HasRet = false;
1749 for (unsigned i = 0; i < NumCopies; ++i) {
1750 SDNode *Copy = Copies[i];
1751 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
1753 if (UI->getOpcode() == ISD::CopyToReg) {
1755 if (Use == Copies[0] || Use == Copies[1])
1759 if (UI->getOpcode() != ARMISD::RET_FLAG)
1768 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1769 // their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1770 // one of the above mentioned nodes. It has to be wrapped because otherwise
1771 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1772 // be used to form addressing mode. These wrapped nodes will be selected
1774 static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1775 EVT PtrVT = Op.getValueType();
1776 // FIXME there is no actual debug info here
1777 DebugLoc dl = Op.getDebugLoc();
1778 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1780 if (CP->isMachineConstantPoolEntry())
1781 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1782 CP->getAlignment());
1784 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1785 CP->getAlignment());
1786 return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1789 unsigned ARMTargetLowering::getJumpTableEncoding() const {
1790 return MachineJumpTableInfo::EK_Inline;
1793 SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
1794 SelectionDAG &DAG) const {
1795 MachineFunction &MF = DAG.getMachineFunction();
1796 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1797 unsigned ARMPCLabelIndex = 0;
1798 DebugLoc DL = Op.getDebugLoc();
1799 EVT PtrVT = getPointerTy();
1800 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1801 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1803 if (RelocM == Reloc::Static) {
1804 CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
1806 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1807 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1808 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(BA, ARMPCLabelIndex,
1809 ARMCP::CPBlockAddress,
1811 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1813 CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
1814 SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
1815 MachinePointerInfo::getConstantPool(),
1817 if (RelocM == Reloc::Static)
1819 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1820 return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
1823 // Lower ISD::GlobalTLSAddress using the "general dynamic" model
1825 ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1826 SelectionDAG &DAG) const {
1827 DebugLoc dl = GA->getDebugLoc();
1828 EVT PtrVT = getPointerTy();
1829 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1830 MachineFunction &MF = DAG.getMachineFunction();
1831 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1832 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1833 ARMConstantPoolValue *CPV =
1834 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1835 ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
1836 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1837 Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
1838 Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
1839 MachinePointerInfo::getConstantPool(),
1841 SDValue Chain = Argument.getValue(1);
1843 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1844 Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
1846 // call __tls_get_addr.
1849 Entry.Node = Argument;
1850 Entry.Ty = (const Type *) Type::getInt32Ty(*DAG.getContext());
1851 Args.push_back(Entry);
1852 // FIXME: is there useful debug info available here?
1853 std::pair<SDValue, SDValue> CallResult =
1854 LowerCallTo(Chain, (const Type *) Type::getInt32Ty(*DAG.getContext()),
1855 false, false, false, false,
1856 0, CallingConv::C, false, /*isReturnValueUsed=*/true,
1857 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
1858 return CallResult.first;
1861 // Lower ISD::GlobalTLSAddress using the "initial exec" or
1862 // "local exec" model.
1864 ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
1865 SelectionDAG &DAG) const {
1866 const GlobalValue *GV = GA->getGlobal();
1867 DebugLoc dl = GA->getDebugLoc();
1869 SDValue Chain = DAG.getEntryNode();
1870 EVT PtrVT = getPointerTy();
1871 // Get the Thread Pointer
1872 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1874 if (GV->isDeclaration()) {
1875 MachineFunction &MF = DAG.getMachineFunction();
1876 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1877 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1878 // Initial exec model.
1879 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1880 ARMConstantPoolValue *CPV =
1881 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1882 ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF, true);
1883 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1884 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1885 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1886 MachinePointerInfo::getConstantPool(),
1888 Chain = Offset.getValue(1);
1890 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1891 Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
1893 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1894 MachinePointerInfo::getConstantPool(),
1898 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMCP::TPOFF);
1899 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1900 Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1901 Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
1902 MachinePointerInfo::getConstantPool(),
1906 // The address of the thread local variable is the add of the thread
1907 // pointer with the offset of the variable.
1908 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
1912 ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
1913 // TODO: implement the "local dynamic" model
1914 assert(Subtarget->isTargetELF() &&
1915 "TLS not implemented for non-ELF targets");
1916 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1917 // If the relocation model is PIC, use the "General Dynamic" TLS Model,
1918 // otherwise use the "Local Exec" TLS Model
1919 if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
1920 return LowerToTLSGeneralDynamicModel(GA, DAG);
1922 return LowerToTLSExecModels(GA, DAG);
1925 SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
1926 SelectionDAG &DAG) const {
1927 EVT PtrVT = getPointerTy();
1928 DebugLoc dl = Op.getDebugLoc();
1929 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1930 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1931 if (RelocM == Reloc::PIC_) {
1932 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
1933 ARMConstantPoolValue *CPV =
1934 new ARMConstantPoolValue(GV, UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
1935 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1936 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1937 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1939 MachinePointerInfo::getConstantPool(),
1941 SDValue Chain = Result.getValue(1);
1942 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1943 Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
1945 Result = DAG.getLoad(PtrVT, dl, Chain, Result,
1946 MachinePointerInfo::getGOT(), false, false, 0);
1949 // If we have T2 ops, we can materialize the address directly via movt/movw
1950 // pair. This is always cheaper.
1951 if (Subtarget->useMovt()) {
1952 return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
1953 DAG.getTargetGlobalAddress(GV, dl, PtrVT));
1955 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1956 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1957 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1958 MachinePointerInfo::getConstantPool(),
1964 SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
1965 SelectionDAG &DAG) const {
1966 MachineFunction &MF = DAG.getMachineFunction();
1967 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1968 unsigned ARMPCLabelIndex = 0;
1969 EVT PtrVT = getPointerTy();
1970 DebugLoc dl = Op.getDebugLoc();
1971 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1972 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1974 if (RelocM == Reloc::Static)
1975 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1977 ARMPCLabelIndex = AFI->createConstPoolEntryUId();
1978 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8);
1979 ARMConstantPoolValue *CPV =
1980 new ARMConstantPoolValue(GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj);
1981 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1983 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1985 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
1986 MachinePointerInfo::getConstantPool(),
1988 SDValue Chain = Result.getValue(1);
1990 if (RelocM == Reloc::PIC_) {
1991 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1992 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1995 if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
1996 Result = DAG.getLoad(PtrVT, dl, Chain, Result, MachinePointerInfo::getGOT(),
2002 SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
2003 SelectionDAG &DAG) const {
2004 assert(Subtarget->isTargetELF() &&
2005 "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
2006 MachineFunction &MF = DAG.getMachineFunction();
2007 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2008 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
2009 EVT PtrVT = getPointerTy();
2010 DebugLoc dl = Op.getDebugLoc();
2011 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2012 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
2013 "_GLOBAL_OFFSET_TABLE_",
2014 ARMPCLabelIndex, PCAdj);
2015 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2016 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2017 SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2018 MachinePointerInfo::getConstantPool(),
2020 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2021 return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2025 ARMTargetLowering::LowerEH_SJLJ_DISPATCHSETUP(SDValue Op, SelectionDAG &DAG)
2027 DebugLoc dl = Op.getDebugLoc();
2028 return DAG.getNode(ARMISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other,
2029 Op.getOperand(0), Op.getOperand(1));
2033 ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
2034 DebugLoc dl = Op.getDebugLoc();
2035 SDValue Val = DAG.getConstant(0, MVT::i32);
2036 return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(0),
2037 Op.getOperand(1), Val);
2041 ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
2042 DebugLoc dl = Op.getDebugLoc();
2043 return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
2044 Op.getOperand(1), DAG.getConstant(0, MVT::i32));
2048 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
2049 const ARMSubtarget *Subtarget) const {
2050 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2051 DebugLoc dl = Op.getDebugLoc();
2053 default: return SDValue(); // Don't custom lower most intrinsics.
2054 case Intrinsic::arm_thread_pointer: {
2055 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2056 return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2058 case Intrinsic::eh_sjlj_lsda: {
2059 MachineFunction &MF = DAG.getMachineFunction();
2060 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2061 unsigned ARMPCLabelIndex = AFI->createConstPoolEntryUId();
2062 EVT PtrVT = getPointerTy();
2063 DebugLoc dl = Op.getDebugLoc();
2064 Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2066 unsigned PCAdj = (RelocM != Reloc::PIC_)
2067 ? 0 : (Subtarget->isThumb() ? 4 : 8);
2068 ARMConstantPoolValue *CPV =
2069 new ARMConstantPoolValue(MF.getFunction(), ARMPCLabelIndex,
2070 ARMCP::CPLSDA, PCAdj);
2071 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2072 CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2074 DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2075 MachinePointerInfo::getConstantPool(),
2078 if (RelocM == Reloc::PIC_) {
2079 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2080 Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2087 static SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG,
2088 const ARMSubtarget *Subtarget) {
2089 DebugLoc dl = Op.getDebugLoc();
2090 if (!Subtarget->hasDataBarrier()) {
2091 // Some ARMv6 cpus can support data barriers with an mcr instruction.
2092 // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
2094 assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&
2095 "Unexpected ISD::MEMBARRIER encountered. Should be libcall!");
2096 return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2097 DAG.getConstant(0, MVT::i32));
2100 SDValue Op5 = Op.getOperand(5);
2101 bool isDeviceBarrier = cast<ConstantSDNode>(Op5)->getZExtValue() != 0;
2102 unsigned isLL = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
2103 unsigned isLS = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
2104 bool isOnlyStoreBarrier = (isLL == 0 && isLS == 0);
2106 ARM_MB::MemBOpt DMBOpt;
2107 if (isDeviceBarrier)
2108 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ST : ARM_MB::SY;
2110 DMBOpt = isOnlyStoreBarrier ? ARM_MB::ISHST : ARM_MB::ISH;
2111 return DAG.getNode(ARMISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0),
2112 DAG.getConstant(DMBOpt, MVT::i32));
2115 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
2116 const ARMSubtarget *Subtarget) {
2117 // ARM pre v5TE and Thumb1 does not have preload instructions.
2118 if (!(Subtarget->isThumb2() ||
2119 (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
2120 // Just preserve the chain.
2121 return Op.getOperand(0);
2123 DebugLoc dl = Op.getDebugLoc();
2124 unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
2126 (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
2127 // ARMv7 with MP extension has PLDW.
2128 return Op.getOperand(0);
2130 if (Subtarget->isThumb())
2132 isRead = ~isRead & 1;
2133 unsigned isData = Subtarget->isThumb() ? 0 : 1;
2135 // Currently there is no intrinsic that matches pli.
2136 return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
2137 Op.getOperand(1), DAG.getConstant(isRead, MVT::i32),
2138 DAG.getConstant(isData, MVT::i32));
2141 static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
2142 MachineFunction &MF = DAG.getMachineFunction();
2143 ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
2145 // vastart just stores the address of the VarArgsFrameIndex slot into the
2146 // memory location argument.
2147 DebugLoc dl = Op.getDebugLoc();
2148 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2149 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2150 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2151 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2152 MachinePointerInfo(SV), false, false, 0);
2156 ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
2157 SDValue &Root, SelectionDAG &DAG,
2158 DebugLoc dl) const {
2159 MachineFunction &MF = DAG.getMachineFunction();
2160 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2162 TargetRegisterClass *RC;
2163 if (AFI->isThumb1OnlyFunction())
2164 RC = ARM::tGPRRegisterClass;
2166 RC = ARM::GPRRegisterClass;
2168 // Transform the arguments stored in physical registers into virtual ones.
2169 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2170 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2173 if (NextVA.isMemLoc()) {
2174 MachineFrameInfo *MFI = MF.getFrameInfo();
2175 int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
2177 // Create load node to retrieve arguments from the stack.
2178 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2179 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
2180 MachinePointerInfo::getFixedStack(FI),
2183 Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2184 ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2187 return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
2191 ARMTargetLowering::LowerFormalArguments(SDValue Chain,
2192 CallingConv::ID CallConv, bool isVarArg,
2193 const SmallVectorImpl<ISD::InputArg>
2195 DebugLoc dl, SelectionDAG &DAG,
2196 SmallVectorImpl<SDValue> &InVals)
2199 MachineFunction &MF = DAG.getMachineFunction();
2200 MachineFrameInfo *MFI = MF.getFrameInfo();
2202 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2204 // Assign locations to all of the incoming arguments.
2205 SmallVector<CCValAssign, 16> ArgLocs;
2206 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
2208 CCInfo.AnalyzeFormalArguments(Ins,
2209 CCAssignFnForNode(CallConv, /* Return*/ false,
2212 SmallVector<SDValue, 16> ArgValues;
2214 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2215 CCValAssign &VA = ArgLocs[i];
2217 // Arguments stored in registers.
2218 if (VA.isRegLoc()) {
2219 EVT RegVT = VA.getLocVT();
2222 if (VA.needsCustom()) {
2223 // f64 and vector types are split up into multiple registers or
2224 // combinations of registers and stack slots.
2225 if (VA.getLocVT() == MVT::v2f64) {
2226 SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
2228 VA = ArgLocs[++i]; // skip ahead to next loc
2230 if (VA.isMemLoc()) {
2231 int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
2232 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2233 ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
2234 MachinePointerInfo::getFixedStack(FI),
2237 ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
2240 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2241 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2242 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
2243 ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2244 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
2246 ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
2249 TargetRegisterClass *RC;
2251 if (RegVT == MVT::f32)
2252 RC = ARM::SPRRegisterClass;
2253 else if (RegVT == MVT::f64)
2254 RC = ARM::DPRRegisterClass;
2255 else if (RegVT == MVT::v2f64)
2256 RC = ARM::QPRRegisterClass;
2257 else if (RegVT == MVT::i32)
2258 RC = (AFI->isThumb1OnlyFunction() ?
2259 ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
2261 llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2263 // Transform the arguments in physical registers into virtual ones.
2264 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2265 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2268 // If this is an 8 or 16-bit value, it is really passed promoted
2269 // to 32 bits. Insert an assert[sz]ext to capture this, then
2270 // truncate to the right size.
2271 switch (VA.getLocInfo()) {
2272 default: llvm_unreachable("Unknown loc info!");
2273 case CCValAssign::Full: break;
2274 case CCValAssign::BCvt:
2275 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2277 case CCValAssign::SExt:
2278 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2279 DAG.getValueType(VA.getValVT()));
2280 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2282 case CCValAssign::ZExt:
2283 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2284 DAG.getValueType(VA.getValVT()));
2285 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2289 InVals.push_back(ArgValue);
2291 } else { // VA.isRegLoc()
2294 assert(VA.isMemLoc());
2295 assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
2297 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
2298 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(), true);
2300 // Create load nodes to retrieve arguments from the stack.
2301 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2302 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2303 MachinePointerInfo::getFixedStack(FI),
2310 static const unsigned GPRArgRegs[] = {
2311 ARM::R0, ARM::R1, ARM::R2, ARM::R3
2314 unsigned NumGPRs = CCInfo.getFirstUnallocated
2315 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
2317 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
2318 unsigned VARegSize = (4 - NumGPRs) * 4;
2319 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
2320 unsigned ArgOffset = CCInfo.getNextStackOffset();
2321 if (VARegSaveSize) {
2322 // If this function is vararg, store any remaining integer argument regs
2323 // to their spots on the stack so that they may be loaded by deferencing
2324 // the result of va_next.
2325 AFI->setVarArgsRegSaveSize(VARegSaveSize);
2326 AFI->setVarArgsFrameIndex(
2327 MFI->CreateFixedObject(VARegSaveSize,
2328 ArgOffset + VARegSaveSize - VARegSize,
2330 SDValue FIN = DAG.getFrameIndex(AFI->getVarArgsFrameIndex(),
2333 SmallVector<SDValue, 4> MemOps;
2334 for (; NumGPRs < 4; ++NumGPRs) {
2335 TargetRegisterClass *RC;
2336 if (AFI->isThumb1OnlyFunction())
2337 RC = ARM::tGPRRegisterClass;
2339 RC = ARM::GPRRegisterClass;
2341 unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
2342 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2344 DAG.getStore(Val.getValue(1), dl, Val, FIN,
2345 MachinePointerInfo::getFixedStack(AFI->getVarArgsFrameIndex()),
2347 MemOps.push_back(Store);
2348 FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
2349 DAG.getConstant(4, getPointerTy()));
2351 if (!MemOps.empty())
2352 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2353 &MemOps[0], MemOps.size());
2355 // This will point to the next argument passed via stack.
2356 AFI->setVarArgsFrameIndex(MFI->CreateFixedObject(4, ArgOffset, true));
2362 /// isFloatingPointZero - Return true if this is +0.0.
2363 static bool isFloatingPointZero(SDValue Op) {
2364 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
2365 return CFP->getValueAPF().isPosZero();
2366 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
2367 // Maybe this has already been legalized into the constant pool?
2368 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
2369 SDValue WrapperOp = Op.getOperand(1).getOperand(0);
2370 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
2371 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
2372 return CFP->getValueAPF().isPosZero();
2378 /// Returns appropriate ARM CMP (cmp) and corresponding condition code for
2379 /// the given operands.
2381 ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
2382 SDValue &ARMcc, SelectionDAG &DAG,
2383 DebugLoc dl) const {
2384 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
2385 unsigned C = RHSC->getZExtValue();
2386 if (!isLegalICmpImmediate(C)) {
2387 // Constant does not fit, try adjusting it by one?
2392 if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
2393 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
2394 RHS = DAG.getConstant(C-1, MVT::i32);
2399 if (C != 0 && isLegalICmpImmediate(C-1)) {
2400 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
2401 RHS = DAG.getConstant(C-1, MVT::i32);
2406 if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
2407 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
2408 RHS = DAG.getConstant(C+1, MVT::i32);
2413 if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
2414 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
2415 RHS = DAG.getConstant(C+1, MVT::i32);
2422 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2423 ARMISD::NodeType CompareType;
2426 CompareType = ARMISD::CMP;
2431 CompareType = ARMISD::CMPZ;
2434 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2435 return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
2438 /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
2440 ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
2441 DebugLoc dl) const {
2443 if (!isFloatingPointZero(RHS))
2444 Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS);
2446 Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS);
2447 return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
2450 SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2451 SDValue Cond = Op.getOperand(0);
2452 SDValue SelectTrue = Op.getOperand(1);
2453 SDValue SelectFalse = Op.getOperand(2);
2454 DebugLoc dl = Op.getDebugLoc();
2458 // (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
2459 // (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
2461 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
2462 const ConstantSDNode *CMOVTrue =
2463 dyn_cast<ConstantSDNode>(Cond.getOperand(0));
2464 const ConstantSDNode *CMOVFalse =
2465 dyn_cast<ConstantSDNode>(Cond.getOperand(1));
2467 if (CMOVTrue && CMOVFalse) {
2468 unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
2469 unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
2473 if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
2475 False = SelectFalse;
2476 } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
2481 if (True.getNode() && False.getNode()) {
2482 EVT VT = Cond.getValueType();
2483 SDValue ARMcc = Cond.getOperand(2);
2484 SDValue CCR = Cond.getOperand(3);
2485 SDValue Cmp = Cond.getOperand(4);
2486 return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp);
2491 return DAG.getSelectCC(dl, Cond,
2492 DAG.getConstant(0, Cond.getValueType()),
2493 SelectTrue, SelectFalse, ISD::SETNE);
2496 SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
2497 EVT VT = Op.getValueType();
2498 SDValue LHS = Op.getOperand(0);
2499 SDValue RHS = Op.getOperand(1);
2500 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2501 SDValue TrueVal = Op.getOperand(2);
2502 SDValue FalseVal = Op.getOperand(3);
2503 DebugLoc dl = Op.getDebugLoc();
2505 if (LHS.getValueType() == MVT::i32) {
2507 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2508 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2509 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,Cmp);
2512 ARMCC::CondCodes CondCode, CondCode2;
2513 FPCCToARMCC(CC, CondCode, CondCode2);
2515 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2516 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2517 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2518 SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
2520 if (CondCode2 != ARMCC::AL) {
2521 SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32);
2522 // FIXME: Needs another CMP because flag can have but one use.
2523 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
2524 Result = DAG.getNode(ARMISD::CMOV, dl, VT,
2525 Result, TrueVal, ARMcc2, CCR, Cmp2);
2530 /// canChangeToInt - Given the fp compare operand, return true if it is suitable
2531 /// to morph to an integer compare sequence.
2532 static bool canChangeToInt(SDValue Op, bool &SeenZero,
2533 const ARMSubtarget *Subtarget) {
2534 SDNode *N = Op.getNode();
2535 if (!N->hasOneUse())
2536 // Otherwise it requires moving the value from fp to integer registers.
2538 if (!N->getNumValues())
2540 EVT VT = Op.getValueType();
2541 if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
2542 // f32 case is generally profitable. f64 case only makes sense when vcmpe +
2543 // vmrs are very slow, e.g. cortex-a8.
2546 if (isFloatingPointZero(Op)) {
2550 return ISD::isNormalLoad(N);
2553 static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
2554 if (isFloatingPointZero(Op))
2555 return DAG.getConstant(0, MVT::i32);
2557 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
2558 return DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2559 Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(),
2560 Ld->isVolatile(), Ld->isNonTemporal(),
2561 Ld->getAlignment());
2563 llvm_unreachable("Unknown VFP cmp argument!");
2566 static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
2567 SDValue &RetVal1, SDValue &RetVal2) {
2568 if (isFloatingPointZero(Op)) {
2569 RetVal1 = DAG.getConstant(0, MVT::i32);
2570 RetVal2 = DAG.getConstant(0, MVT::i32);
2574 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
2575 SDValue Ptr = Ld->getBasePtr();
2576 RetVal1 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2577 Ld->getChain(), Ptr,
2578 Ld->getPointerInfo(),
2579 Ld->isVolatile(), Ld->isNonTemporal(),
2580 Ld->getAlignment());
2582 EVT PtrType = Ptr.getValueType();
2583 unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
2584 SDValue NewPtr = DAG.getNode(ISD::ADD, Op.getDebugLoc(),
2585 PtrType, Ptr, DAG.getConstant(4, PtrType));
2586 RetVal2 = DAG.getLoad(MVT::i32, Op.getDebugLoc(),
2587 Ld->getChain(), NewPtr,
2588 Ld->getPointerInfo().getWithOffset(4),
2589 Ld->isVolatile(), Ld->isNonTemporal(),
2594 llvm_unreachable("Unknown VFP cmp argument!");
2597 /// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
2598 /// f32 and even f64 comparisons to integer ones.
2600 ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
2601 SDValue Chain = Op.getOperand(0);
2602 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2603 SDValue LHS = Op.getOperand(2);
2604 SDValue RHS = Op.getOperand(3);
2605 SDValue Dest = Op.getOperand(4);
2606 DebugLoc dl = Op.getDebugLoc();
2608 bool SeenZero = false;
2609 if (canChangeToInt(LHS, SeenZero, Subtarget) &&
2610 canChangeToInt(RHS, SeenZero, Subtarget) &&
2611 // If one of the operand is zero, it's safe to ignore the NaN case since
2612 // we only care about equality comparisons.
2613 (SeenZero || (DAG.isKnownNeverNaN(LHS) && DAG.isKnownNeverNaN(RHS)))) {
2614 // If unsafe fp math optimization is enabled and there are no othter uses of
2615 // the CMP operands, and the condition code is EQ oe NE, we can optimize it
2616 // to an integer comparison.
2617 if (CC == ISD::SETOEQ)
2619 else if (CC == ISD::SETUNE)
2623 if (LHS.getValueType() == MVT::f32) {
2624 LHS = bitcastf32Toi32(LHS, DAG);
2625 RHS = bitcastf32Toi32(RHS, DAG);
2626 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2627 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2628 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2629 Chain, Dest, ARMcc, CCR, Cmp);
2634 expandf64Toi32(LHS, DAG, LHS1, LHS2);
2635 expandf64Toi32(RHS, DAG, RHS1, RHS2);
2636 ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
2637 ARMcc = DAG.getConstant(CondCode, MVT::i32);
2638 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
2639 SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
2640 return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7);
2646 SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2647 SDValue Chain = Op.getOperand(0);
2648 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2649 SDValue LHS = Op.getOperand(2);
2650 SDValue RHS = Op.getOperand(3);
2651 SDValue Dest = Op.getOperand(4);
2652 DebugLoc dl = Op.getDebugLoc();
2654 if (LHS.getValueType() == MVT::i32) {
2656 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
2657 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2658 return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
2659 Chain, Dest, ARMcc, CCR, Cmp);
2662 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
2665 (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
2666 CC == ISD::SETNE || CC == ISD::SETUNE)) {
2667 SDValue Result = OptimizeVFPBrcond(Op, DAG);
2668 if (Result.getNode())
2672 ARMCC::CondCodes CondCode, CondCode2;
2673 FPCCToARMCC(CC, CondCode, CondCode2);
2675 SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
2676 SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
2677 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2678 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
2679 SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
2680 SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2681 if (CondCode2 != ARMCC::AL) {
2682 ARMcc = DAG.getConstant(CondCode2, MVT::i32);
2683 SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
2684 Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
2689 SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
2690 SDValue Chain = Op.getOperand(0);
2691 SDValue Table = Op.getOperand(1);
2692 SDValue Index = Op.getOperand(2);
2693 DebugLoc dl = Op.getDebugLoc();
2695 EVT PTy = getPointerTy();
2696 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
2697 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
2698 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
2699 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
2700 Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
2701 Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
2702 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
2703 if (Subtarget->isThumb2()) {
2704 // Thumb2 uses a two-level jump. That is, it jumps into the jump table
2705 // which does another jump to the destination. This also makes it easier
2706 // to translate it to TBB / TBH later.
2707 // FIXME: This might not work if the function is extremely large.
2708 return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
2709 Addr, Op.getOperand(2), JTI, UId);
2711 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2712 Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
2713 MachinePointerInfo::getJumpTable(),
2715 Chain = Addr.getValue(1);
2716 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
2717 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2719 Addr = DAG.getLoad(PTy, dl, Chain, Addr,
2720 MachinePointerInfo::getJumpTable(), false, false, 0);
2721 Chain = Addr.getValue(1);
2722 return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
2726 static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
2727 DebugLoc dl = Op.getDebugLoc();
2730 switch (Op.getOpcode()) {
2732 assert(0 && "Invalid opcode!");
2733 case ISD::FP_TO_SINT:
2734 Opc = ARMISD::FTOSI;
2736 case ISD::FP_TO_UINT:
2737 Opc = ARMISD::FTOUI;
2740 Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
2741 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
2744 static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
2745 EVT VT = Op.getValueType();
2746 DebugLoc dl = Op.getDebugLoc();
2749 switch (Op.getOpcode()) {
2751 assert(0 && "Invalid opcode!");
2752 case ISD::SINT_TO_FP:
2753 Opc = ARMISD::SITOF;
2755 case ISD::UINT_TO_FP:
2756 Opc = ARMISD::UITOF;
2760 Op = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0));
2761 return DAG.getNode(Opc, dl, VT, Op);
2764 SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
2765 // Implement fcopysign with a fabs and a conditional fneg.
2766 SDValue Tmp0 = Op.getOperand(0);
2767 SDValue Tmp1 = Op.getOperand(1);
2768 DebugLoc dl = Op.getDebugLoc();
2769 EVT VT = Op.getValueType();
2770 EVT SrcVT = Tmp1.getValueType();
2771 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
2772 SDValue ARMcc = DAG.getConstant(ARMCC::LT, MVT::i32);
2773 SDValue FP0 = DAG.getConstantFP(0.0, SrcVT);
2774 SDValue Cmp = getVFPCmp(Tmp1, FP0, DAG, dl);
2775 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2776 return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMcc, CCR, Cmp);
2779 SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
2780 MachineFunction &MF = DAG.getMachineFunction();
2781 MachineFrameInfo *MFI = MF.getFrameInfo();
2782 MFI->setReturnAddressIsTaken(true);
2784 EVT VT = Op.getValueType();
2785 DebugLoc dl = Op.getDebugLoc();
2786 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2788 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
2789 SDValue Offset = DAG.getConstant(4, MVT::i32);
2790 return DAG.getLoad(VT, dl, DAG.getEntryNode(),
2791 DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
2792 MachinePointerInfo(), false, false, 0);
2795 // Return LR, which contains the return address. Mark it an implicit live-in.
2796 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
2797 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
2800 SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
2801 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
2802 MFI->setFrameAddressIsTaken(true);
2804 EVT VT = Op.getValueType();
2805 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful
2806 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2807 unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
2808 ? ARM::R7 : ARM::R11;
2809 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
2811 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
2812 MachinePointerInfo(),
2817 /// ExpandBITCAST - If the target supports VFP, this function is called to
2818 /// expand a bit convert where either the source or destination type is i64 to
2819 /// use a VMOVDRR or VMOVRRD node. This should not be done when the non-i64
2820 /// operand type is illegal (e.g., v2f32 for a target that doesn't support
2821 /// vectors), since the legalizer won't know what to do with that.
2822 static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) {
2823 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2824 DebugLoc dl = N->getDebugLoc();
2825 SDValue Op = N->getOperand(0);
2827 // This function is only supposed to be called for i64 types, either as the
2828 // source or destination of the bit convert.
2829 EVT SrcVT = Op.getValueType();
2830 EVT DstVT = N->getValueType(0);
2831 assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
2832 "ExpandBITCAST called for non-i64 type");
2834 // Turn i64->f64 into VMOVDRR.
2835 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
2836 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2837 DAG.getConstant(0, MVT::i32));
2838 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2839 DAG.getConstant(1, MVT::i32));
2840 return DAG.getNode(ISD::BITCAST, dl, DstVT,
2841 DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
2844 // Turn f64->i64 into VMOVRRD.
2845 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
2846 SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
2847 DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
2848 // Merge the pieces into a single i64 value.
2849 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
2855 /// getZeroVector - Returns a vector of specified type with all zero elements.
2856 /// Zero vectors are used to represent vector negation and in those cases
2857 /// will be implemented with the NEON VNEG instruction. However, VNEG does
2858 /// not support i64 elements, so sometimes the zero vectors will need to be
2859 /// explicitly constructed. Regardless, use a canonical VMOV to create the
2861 static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2862 assert(VT.isVector() && "Expected a vector type");
2863 // The canonical modified immediate encoding of a zero vector is....0!
2864 SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32);
2865 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
2866 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
2867 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
2870 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
2871 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2872 SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
2873 SelectionDAG &DAG) const {
2874 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2875 EVT VT = Op.getValueType();
2876 unsigned VTBits = VT.getSizeInBits();
2877 DebugLoc dl = Op.getDebugLoc();
2878 SDValue ShOpLo = Op.getOperand(0);
2879 SDValue ShOpHi = Op.getOperand(1);
2880 SDValue ShAmt = Op.getOperand(2);
2882 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
2884 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
2886 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2887 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2888 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
2889 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2890 DAG.getConstant(VTBits, MVT::i32));
2891 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
2892 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2893 SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
2895 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2896 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
2898 SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
2899 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
2902 SDValue Ops[2] = { Lo, Hi };
2903 return DAG.getMergeValues(Ops, 2, dl);
2906 /// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
2907 /// i32 values and take a 2 x i32 value to shift plus a shift amount.
2908 SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
2909 SelectionDAG &DAG) const {
2910 assert(Op.getNumOperands() == 3 && "Not a double-shift!");
2911 EVT VT = Op.getValueType();
2912 unsigned VTBits = VT.getSizeInBits();
2913 DebugLoc dl = Op.getDebugLoc();
2914 SDValue ShOpLo = Op.getOperand(0);
2915 SDValue ShOpHi = Op.getOperand(1);
2916 SDValue ShAmt = Op.getOperand(2);
2919 assert(Op.getOpcode() == ISD::SHL_PARTS);
2920 SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
2921 DAG.getConstant(VTBits, MVT::i32), ShAmt);
2922 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
2923 SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
2924 DAG.getConstant(VTBits, MVT::i32));
2925 SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
2926 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
2928 SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2929 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2930 SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
2932 SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
2933 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
2936 SDValue Ops[2] = { Lo, Hi };
2937 return DAG.getMergeValues(Ops, 2, dl);
2940 SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
2941 SelectionDAG &DAG) const {
2942 // The rounding mode is in bits 23:22 of the FPSCR.
2943 // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
2944 // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
2945 // so that the shift + and get folded into a bitfield extract.
2946 DebugLoc dl = Op.getDebugLoc();
2947 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
2948 DAG.getConstant(Intrinsic::arm_get_fpscr,
2950 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
2951 DAG.getConstant(1U << 22, MVT::i32));
2952 SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
2953 DAG.getConstant(22, MVT::i32));
2954 return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
2955 DAG.getConstant(3, MVT::i32));
2958 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
2959 const ARMSubtarget *ST) {
2960 EVT VT = N->getValueType(0);
2961 DebugLoc dl = N->getDebugLoc();
2963 if (!ST->hasV6T2Ops())
2966 SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
2967 return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
2970 static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
2971 const ARMSubtarget *ST) {
2972 EVT VT = N->getValueType(0);
2973 DebugLoc dl = N->getDebugLoc();
2978 // Lower vector shifts on NEON to use VSHL.
2979 assert(ST->hasNEON() && "unexpected vector shift");
2981 // Left shifts translate directly to the vshiftu intrinsic.
2982 if (N->getOpcode() == ISD::SHL)
2983 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2984 DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
2985 N->getOperand(0), N->getOperand(1));
2987 assert((N->getOpcode() == ISD::SRA ||
2988 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
2990 // NEON uses the same intrinsics for both left and right shifts. For
2991 // right shifts, the shift amounts are negative, so negate the vector of
2993 EVT ShiftVT = N->getOperand(1).getValueType();
2994 SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
2995 getZeroVector(ShiftVT, DAG, dl),
2997 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
2998 Intrinsic::arm_neon_vshifts :
2999 Intrinsic::arm_neon_vshiftu);
3000 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
3001 DAG.getConstant(vshiftInt, MVT::i32),
3002 N->getOperand(0), NegatedCount);
3005 static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
3006 const ARMSubtarget *ST) {
3007 EVT VT = N->getValueType(0);
3008 DebugLoc dl = N->getDebugLoc();
3010 // We can get here for a node like i32 = ISD::SHL i32, i64
3014 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
3015 "Unknown shift to lower!");
3017 // We only lower SRA, SRL of 1 here, all others use generic lowering.
3018 if (!isa<ConstantSDNode>(N->getOperand(1)) ||
3019 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
3022 // If we are in thumb mode, we don't have RRX.
3023 if (ST->isThumb1Only()) return SDValue();
3025 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr.
3026 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
3027 DAG.getConstant(0, MVT::i32));
3028 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
3029 DAG.getConstant(1, MVT::i32));
3031 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
3032 // captures the result into a carry flag.
3033 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
3034 Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), &Hi, 1);
3036 // The low part is an ARMISD::RRX operand, which shifts the carry in.
3037 Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
3039 // Merge the pieces into a single i64 value.
3040 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
3043 static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
3044 SDValue TmpOp0, TmpOp1;
3045 bool Invert = false;
3049 SDValue Op0 = Op.getOperand(0);
3050 SDValue Op1 = Op.getOperand(1);
3051 SDValue CC = Op.getOperand(2);
3052 EVT VT = Op.getValueType();
3053 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
3054 DebugLoc dl = Op.getDebugLoc();
3056 if (Op.getOperand(1).getValueType().isFloatingPoint()) {
3057 switch (SetCCOpcode) {
3058 default: llvm_unreachable("Illegal FP comparison"); break;
3060 case ISD::SETNE: Invert = true; // Fallthrough
3062 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3064 case ISD::SETLT: Swap = true; // Fallthrough
3066 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3068 case ISD::SETLE: Swap = true; // Fallthrough
3070 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3071 case ISD::SETUGE: Swap = true; // Fallthrough
3072 case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
3073 case ISD::SETUGT: Swap = true; // Fallthrough
3074 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
3075 case ISD::SETUEQ: Invert = true; // Fallthrough
3077 // Expand this to (OLT | OGT).
3081 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3082 Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
3084 case ISD::SETUO: Invert = true; // Fallthrough
3086 // Expand this to (OLT | OGE).
3090 Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
3091 Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
3095 // Integer comparisons.
3096 switch (SetCCOpcode) {
3097 default: llvm_unreachable("Illegal integer comparison"); break;
3098 case ISD::SETNE: Invert = true;
3099 case ISD::SETEQ: Opc = ARMISD::VCEQ; break;
3100 case ISD::SETLT: Swap = true;
3101 case ISD::SETGT: Opc = ARMISD::VCGT; break;
3102 case ISD::SETLE: Swap = true;
3103 case ISD::SETGE: Opc = ARMISD::VCGE; break;
3104 case ISD::SETULT: Swap = true;
3105 case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
3106 case ISD::SETULE: Swap = true;
3107 case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
3110 // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
3111 if (Opc == ARMISD::VCEQ) {
3114 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
3116 else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
3119 // Ignore bitconvert.
3120 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST)
3121 AndOp = AndOp.getOperand(0);
3123 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
3125 Op0 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(0));
3126 Op1 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(1));
3133 std::swap(Op0, Op1);
3135 // If one of the operands is a constant vector zero, attempt to fold the
3136 // comparison to a specialized compare-against-zero form.
3138 if (ISD::isBuildVectorAllZeros(Op1.getNode()))
3140 else if (ISD::isBuildVectorAllZeros(Op0.getNode())) {
3141 if (Opc == ARMISD::VCGE)
3142 Opc = ARMISD::VCLEZ;
3143 else if (Opc == ARMISD::VCGT)
3144 Opc = ARMISD::VCLTZ;
3149 if (SingleOp.getNode()) {
3152 Result = DAG.getNode(ARMISD::VCEQZ, dl, VT, SingleOp); break;
3154 Result = DAG.getNode(ARMISD::VCGEZ, dl, VT, SingleOp); break;
3156 Result = DAG.getNode(ARMISD::VCLEZ, dl, VT, SingleOp); break;
3158 Result = DAG.getNode(ARMISD::VCGTZ, dl, VT, SingleOp); break;
3160 Result = DAG.getNode(ARMISD::VCLTZ, dl, VT, SingleOp); break;
3162 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3165 Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
3169 Result = DAG.getNOT(dl, Result, VT);
3174 /// isNEONModifiedImm - Check if the specified splat value corresponds to a
3175 /// valid vector constant for a NEON instruction with a "modified immediate"
3176 /// operand (e.g., VMOV). If so, return the encoded value.
3177 static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
3178 unsigned SplatBitSize, SelectionDAG &DAG,
3179 EVT &VT, bool is128Bits, NEONModImmType type) {
3180 unsigned OpCmode, Imm;
3182 // SplatBitSize is set to the smallest size that splats the vector, so a
3183 // zero vector will always have SplatBitSize == 8. However, NEON modified
3184 // immediate instructions others than VMOV do not support the 8-bit encoding
3185 // of a zero vector, and the default encoding of zero is supposed to be the
3190 switch (SplatBitSize) {
3192 if (type != VMOVModImm)
3194 // Any 1-byte value is OK. Op=0, Cmode=1110.
3195 assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
3198 VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
3202 // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
3203 VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
3204 if ((SplatBits & ~0xff) == 0) {
3205 // Value = 0x00nn: Op=x, Cmode=100x.
3210 if ((SplatBits & ~0xff00) == 0) {
3211 // Value = 0xnn00: Op=x, Cmode=101x.
3213 Imm = SplatBits >> 8;
3219 // NEON's 32-bit VMOV supports splat values where:
3220 // * only one byte is nonzero, or
3221 // * the least significant byte is 0xff and the second byte is nonzero, or
3222 // * the least significant 2 bytes are 0xff and the third is nonzero.
3223 VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
3224 if ((SplatBits & ~0xff) == 0) {
3225 // Value = 0x000000nn: Op=x, Cmode=000x.
3230 if ((SplatBits & ~0xff00) == 0) {
3231 // Value = 0x0000nn00: Op=x, Cmode=001x.
3233 Imm = SplatBits >> 8;
3236 if ((SplatBits & ~0xff0000) == 0) {
3237 // Value = 0x00nn0000: Op=x, Cmode=010x.
3239 Imm = SplatBits >> 16;
3242 if ((SplatBits & ~0xff000000) == 0) {
3243 // Value = 0xnn000000: Op=x, Cmode=011x.
3245 Imm = SplatBits >> 24;
3249 // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC
3250 if (type == OtherModImm) return SDValue();
3252 if ((SplatBits & ~0xffff) == 0 &&
3253 ((SplatBits | SplatUndef) & 0xff) == 0xff) {
3254 // Value = 0x0000nnff: Op=x, Cmode=1100.
3256 Imm = SplatBits >> 8;
3261 if ((SplatBits & ~0xffffff) == 0 &&
3262 ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
3263 // Value = 0x00nnffff: Op=x, Cmode=1101.
3265 Imm = SplatBits >> 16;
3266 SplatBits |= 0xffff;
3270 // Note: there are a few 32-bit splat values (specifically: 00ffff00,
3271 // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
3272 // VMOV.I32. A (very) minor optimization would be to replicate the value
3273 // and fall through here to test for a valid 64-bit splat. But, then the
3274 // caller would also need to check and handle the change in size.
3278 if (type != VMOVModImm)
3280 // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
3281 uint64_t BitMask = 0xff;
3283 unsigned ImmMask = 1;
3285 for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
3286 if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
3289 } else if ((SplatBits & BitMask) != 0) {
3295 // Op=1, Cmode=1110.
3298 VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
3303 llvm_unreachable("unexpected size for isNEONModifiedImm");
3307 unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
3308 return DAG.getTargetConstant(EncodedVal, MVT::i32);
3311 static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT,
3312 bool &ReverseVEXT, unsigned &Imm) {
3313 unsigned NumElts = VT.getVectorNumElements();
3314 ReverseVEXT = false;
3316 // Assume that the first shuffle index is not UNDEF. Fail if it is.
3322 // If this is a VEXT shuffle, the immediate value is the index of the first
3323 // element. The other shuffle indices must be the successive elements after
3325 unsigned ExpectedElt = Imm;
3326 for (unsigned i = 1; i < NumElts; ++i) {
3327 // Increment the expected index. If it wraps around, it may still be
3328 // a VEXT but the source vectors must be swapped.
3330 if (ExpectedElt == NumElts * 2) {
3335 if (M[i] < 0) continue; // ignore UNDEF indices
3336 if (ExpectedElt != static_cast<unsigned>(M[i]))
3340 // Adjust the index value if the source operands will be swapped.
3347 /// isVREVMask - Check if a vector shuffle corresponds to a VREV
3348 /// instruction with the specified blocksize. (The order of the elements
3349 /// within each block of the vector is reversed.)
3350 static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT,
3351 unsigned BlockSize) {
3352 assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
3353 "Only possible block sizes for VREV are: 16, 32, 64");
3355 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3359 unsigned NumElts = VT.getVectorNumElements();
3360 unsigned BlockElts = M[0] + 1;
3361 // If the first shuffle index is UNDEF, be optimistic.
3363 BlockElts = BlockSize / EltSz;
3365 if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
3368 for (unsigned i = 0; i < NumElts; ++i) {
3369 if (M[i] < 0) continue; // ignore UNDEF indices
3370 if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
3377 static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT,
3378 unsigned &WhichResult) {
3379 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3383 unsigned NumElts = VT.getVectorNumElements();
3384 WhichResult = (M[0] == 0 ? 0 : 1);
3385 for (unsigned i = 0; i < NumElts; i += 2) {
3386 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3387 (M[i+1] >= 0 && (unsigned) M[i+1] != i + NumElts + WhichResult))
3393 /// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
3394 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3395 /// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
3396 static bool isVTRN_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3397 unsigned &WhichResult) {
3398 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3402 unsigned NumElts = VT.getVectorNumElements();
3403 WhichResult = (M[0] == 0 ? 0 : 1);
3404 for (unsigned i = 0; i < NumElts; i += 2) {
3405 if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
3406 (M[i+1] >= 0 && (unsigned) M[i+1] != i + WhichResult))
3412 static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT,
3413 unsigned &WhichResult) {
3414 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3418 unsigned NumElts = VT.getVectorNumElements();
3419 WhichResult = (M[0] == 0 ? 0 : 1);
3420 for (unsigned i = 0; i != NumElts; ++i) {
3421 if (M[i] < 0) continue; // ignore UNDEF indices
3422 if ((unsigned) M[i] != 2 * i + WhichResult)
3426 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3427 if (VT.is64BitVector() && EltSz == 32)
3433 /// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
3434 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3435 /// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
3436 static bool isVUZP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3437 unsigned &WhichResult) {
3438 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3442 unsigned Half = VT.getVectorNumElements() / 2;
3443 WhichResult = (M[0] == 0 ? 0 : 1);
3444 for (unsigned j = 0; j != 2; ++j) {
3445 unsigned Idx = WhichResult;
3446 for (unsigned i = 0; i != Half; ++i) {
3447 int MIdx = M[i + j * Half];
3448 if (MIdx >= 0 && (unsigned) MIdx != Idx)
3454 // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3455 if (VT.is64BitVector() && EltSz == 32)
3461 static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT,
3462 unsigned &WhichResult) {
3463 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3467 unsigned NumElts = VT.getVectorNumElements();
3468 WhichResult = (M[0] == 0 ? 0 : 1);
3469 unsigned Idx = WhichResult * NumElts / 2;
3470 for (unsigned i = 0; i != NumElts; i += 2) {
3471 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3472 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts))
3477 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3478 if (VT.is64BitVector() && EltSz == 32)
3484 /// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
3485 /// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
3486 /// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
3487 static bool isVZIP_v_undef_Mask(const SmallVectorImpl<int> &M, EVT VT,
3488 unsigned &WhichResult) {
3489 unsigned EltSz = VT.getVectorElementType().getSizeInBits();
3493 unsigned NumElts = VT.getVectorNumElements();
3494 WhichResult = (M[0] == 0 ? 0 : 1);
3495 unsigned Idx = WhichResult * NumElts / 2;
3496 for (unsigned i = 0; i != NumElts; i += 2) {
3497 if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
3498 (M[i+1] >= 0 && (unsigned) M[i+1] != Idx))
3503 // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
3504 if (VT.is64BitVector() && EltSz == 32)
3510 // If N is an integer constant that can be moved into a register in one
3511 // instruction, return an SDValue of such a constant (will become a MOV
3512 // instruction). Otherwise return null.
3513 static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG,
3514 const ARMSubtarget *ST, DebugLoc dl) {
3516 if (!isa<ConstantSDNode>(N))
3518 Val = cast<ConstantSDNode>(N)->getZExtValue();
3520 if (ST->isThumb1Only()) {
3521 if (Val <= 255 || ~Val <= 255)
3522 return DAG.getConstant(Val, MVT::i32);
3524 if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1)
3525 return DAG.getConstant(Val, MVT::i32);
3530 // If this is a case we can't handle, return null and let the default
3531 // expansion code take care of it.
3532 static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
3533 const ARMSubtarget *ST) {
3534 BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
3535 DebugLoc dl = Op.getDebugLoc();
3536 EVT VT = Op.getValueType();
3538 APInt SplatBits, SplatUndef;
3539 unsigned SplatBitSize;
3541 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
3542 if (SplatBitSize <= 64) {
3543 // Check if an immediate VMOV works.
3545 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
3546 SplatUndef.getZExtValue(), SplatBitSize,
3547 DAG, VmovVT, VT.is128BitVector(),
3549 if (Val.getNode()) {
3550 SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
3551 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3554 // Try an immediate VMVN.
3555 uint64_t NegatedImm = (SplatBits.getZExtValue() ^
3556 ((1LL << SplatBitSize) - 1));
3557 Val = isNEONModifiedImm(NegatedImm,
3558 SplatUndef.getZExtValue(), SplatBitSize,
3559 DAG, VmovVT, VT.is128BitVector(),
3561 if (Val.getNode()) {
3562 SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
3563 return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3568 // Scan through the operands to see if only one value is used.
3569 unsigned NumElts = VT.getVectorNumElements();
3570 bool isOnlyLowElement = true;
3571 bool usesOnlyOneValue = true;
3572 bool isConstant = true;
3574 for (unsigned i = 0; i < NumElts; ++i) {
3575 SDValue V = Op.getOperand(i);
3576 if (V.getOpcode() == ISD::UNDEF)
3579 isOnlyLowElement = false;
3580 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
3583 if (!Value.getNode())
3585 else if (V != Value)
3586 usesOnlyOneValue = false;
3589 if (!Value.getNode())
3590 return DAG.getUNDEF(VT);
3592 if (isOnlyLowElement)
3593 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
3595 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3597 // Use VDUP for non-constant splats. For f32 constant splats, reduce to
3598 // i32 and try again.
3599 if (usesOnlyOneValue && EltSize <= 32) {
3601 return DAG.getNode(ARMISD::VDUP, dl, VT, Value);
3602 if (VT.getVectorElementType().isFloatingPoint()) {
3603 SmallVector<SDValue, 8> Ops;
3604 for (unsigned i = 0; i < NumElts; ++i)
3605 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32,
3607 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
3608 SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], NumElts);
3609 Val = LowerBUILD_VECTOR(Val, DAG, ST);
3611 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
3613 SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
3615 return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
3618 // If all elements are constants and the case above didn't get hit, fall back
3619 // to the default expansion, which will generate a load from the constant
3624 // Vectors with 32- or 64-bit elements can be built by directly assigning
3625 // the subregisters. Lower it to an ARMISD::BUILD_VECTOR so the operands
3626 // will be legalized.
3627 if (EltSize >= 32) {
3628 // Do the expansion with floating-point types, since that is what the VFP
3629 // registers are defined to use, and since i64 is not legal.
3630 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3631 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3632 SmallVector<SDValue, 8> Ops;
3633 for (unsigned i = 0; i < NumElts; ++i)
3634 Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i)));
3635 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
3636 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
3642 /// isShuffleMaskLegal - Targets can use this to indicate that they only
3643 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
3644 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
3645 /// are assumed to be legal.
3647 ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
3649 if (VT.getVectorNumElements() == 4 &&
3650 (VT.is128BitVector() || VT.is64BitVector())) {
3651 unsigned PFIndexes[4];
3652 for (unsigned i = 0; i != 4; ++i) {
3656 PFIndexes[i] = M[i];
3659 // Compute the index in the perfect shuffle table.
3660 unsigned PFTableIndex =
3661 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3662 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3663 unsigned Cost = (PFEntry >> 30);
3670 unsigned Imm, WhichResult;
3672 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3673 return (EltSize >= 32 ||
3674 ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
3675 isVREVMask(M, VT, 64) ||
3676 isVREVMask(M, VT, 32) ||
3677 isVREVMask(M, VT, 16) ||
3678 isVEXTMask(M, VT, ReverseVEXT, Imm) ||
3679 isVTRNMask(M, VT, WhichResult) ||
3680 isVUZPMask(M, VT, WhichResult) ||
3681 isVZIPMask(M, VT, WhichResult) ||
3682 isVTRN_v_undef_Mask(M, VT, WhichResult) ||
3683 isVUZP_v_undef_Mask(M, VT, WhichResult) ||
3684 isVZIP_v_undef_Mask(M, VT, WhichResult));
3687 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
3688 /// the specified operations to build the shuffle.
3689 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
3690 SDValue RHS, SelectionDAG &DAG,
3692 unsigned OpNum = (PFEntry >> 26) & 0x0F;
3693 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
3694 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
3697 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
3706 OP_VUZPL, // VUZP, left result
3707 OP_VUZPR, // VUZP, right result
3708 OP_VZIPL, // VZIP, left result
3709 OP_VZIPR, // VZIP, right result
3710 OP_VTRNL, // VTRN, left result
3711 OP_VTRNR // VTRN, right result
3714 if (OpNum == OP_COPY) {
3715 if (LHSID == (1*9+2)*9+3) return LHS;
3716 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
3720 SDValue OpLHS, OpRHS;
3721 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
3722 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
3723 EVT VT = OpLHS.getValueType();
3726 default: llvm_unreachable("Unknown shuffle opcode!");
3728 return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
3733 return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
3734 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
3738 return DAG.getNode(ARMISD::VEXT, dl, VT,
3740 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
3743 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3744 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
3747 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3748 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
3751 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3752 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
3756 static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
3757 SDValue V1 = Op.getOperand(0);
3758 SDValue V2 = Op.getOperand(1);
3759 DebugLoc dl = Op.getDebugLoc();
3760 EVT VT = Op.getValueType();
3761 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
3762 SmallVector<int, 8> ShuffleMask;
3764 // Convert shuffles that are directly supported on NEON to target-specific
3765 // DAG nodes, instead of keeping them as shuffles and matching them again
3766 // during code selection. This is more efficient and avoids the possibility
3767 // of inconsistencies between legalization and selection.
3768 // FIXME: floating-point vectors should be canonicalized to integer vectors
3769 // of the same time so that they get CSEd properly.
3770 SVN->getMask(ShuffleMask);
3772 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3773 if (EltSize <= 32) {
3774 if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
3775 int Lane = SVN->getSplatIndex();
3776 // If this is undef splat, generate it via "just" vdup, if possible.
3777 if (Lane == -1) Lane = 0;
3779 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
3780 return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
3782 return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
3783 DAG.getConstant(Lane, MVT::i32));
3788 if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
3791 return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
3792 DAG.getConstant(Imm, MVT::i32));
3795 if (isVREVMask(ShuffleMask, VT, 64))
3796 return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
3797 if (isVREVMask(ShuffleMask, VT, 32))
3798 return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
3799 if (isVREVMask(ShuffleMask, VT, 16))
3800 return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
3802 // Check for Neon shuffles that modify both input vectors in place.
3803 // If both results are used, i.e., if there are two shuffles with the same
3804 // source operands and with masks corresponding to both results of one of
3805 // these operations, DAG memoization will ensure that a single node is
3806 // used for both shuffles.
3807 unsigned WhichResult;
3808 if (isVTRNMask(ShuffleMask, VT, WhichResult))
3809 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3810 V1, V2).getValue(WhichResult);
3811 if (isVUZPMask(ShuffleMask, VT, WhichResult))
3812 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3813 V1, V2).getValue(WhichResult);
3814 if (isVZIPMask(ShuffleMask, VT, WhichResult))
3815 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3816 V1, V2).getValue(WhichResult);
3818 if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
3819 return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
3820 V1, V1).getValue(WhichResult);
3821 if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
3822 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
3823 V1, V1).getValue(WhichResult);
3824 if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
3825 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
3826 V1, V1).getValue(WhichResult);
3829 // If the shuffle is not directly supported and it has 4 elements, use
3830 // the PerfectShuffle-generated table to synthesize it from other shuffles.
3831 unsigned NumElts = VT.getVectorNumElements();
3833 unsigned PFIndexes[4];
3834 for (unsigned i = 0; i != 4; ++i) {
3835 if (ShuffleMask[i] < 0)
3838 PFIndexes[i] = ShuffleMask[i];
3841 // Compute the index in the perfect shuffle table.
3842 unsigned PFTableIndex =
3843 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3844 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3845 unsigned Cost = (PFEntry >> 30);
3848 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
3851 // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
3852 if (EltSize >= 32) {
3853 // Do the expansion with floating-point types, since that is what the VFP
3854 // registers are defined to use, and since i64 is not legal.
3855 EVT EltVT = EVT::getFloatingPointVT(EltSize);
3856 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
3857 V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1);
3858 V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2);
3859 SmallVector<SDValue, 8> Ops;
3860 for (unsigned i = 0; i < NumElts; ++i) {
3861 if (ShuffleMask[i] < 0)
3862 Ops.push_back(DAG.getUNDEF(EltVT));
3864 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
3865 ShuffleMask[i] < (int)NumElts ? V1 : V2,
3866 DAG.getConstant(ShuffleMask[i] & (NumElts-1),
3869 SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
3870 return DAG.getNode(ISD::BITCAST, dl, VT, Val);
3876 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
3877 // EXTRACT_VECTOR_ELT is legal only for immediate indexes.
3878 SDValue Lane = Op.getOperand(1);
3879 if (!isa<ConstantSDNode>(Lane))
3882 SDValue Vec = Op.getOperand(0);
3883 if (Op.getValueType() == MVT::i32 &&
3884 Vec.getValueType().getVectorElementType().getSizeInBits() < 32) {
3885 DebugLoc dl = Op.getDebugLoc();
3886 return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
3892 static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
3893 // The only time a CONCAT_VECTORS operation can have legal types is when
3894 // two 64-bit vectors are concatenated to a 128-bit vector.
3895 assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
3896 "unexpected CONCAT_VECTORS");
3897 DebugLoc dl = Op.getDebugLoc();
3898 SDValue Val = DAG.getUNDEF(MVT::v2f64);
3899 SDValue Op0 = Op.getOperand(0);
3900 SDValue Op1 = Op.getOperand(1);
3901 if (Op0.getOpcode() != ISD::UNDEF)
3902 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
3903 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0),
3904 DAG.getIntPtrConstant(0));
3905 if (Op1.getOpcode() != ISD::UNDEF)
3906 Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
3907 DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1),
3908 DAG.getIntPtrConstant(1));
3909 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val);
3912 /// isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each
3913 /// element has been zero/sign-extended, depending on the isSigned parameter,
3914 /// from an integer type half its size.
3915 static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
3917 // A v2i64 BUILD_VECTOR will have been legalized to a BITCAST from v4i32.
3918 EVT VT = N->getValueType(0);
3919 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) {
3920 SDNode *BVN = N->getOperand(0).getNode();
3921 if (BVN->getValueType(0) != MVT::v4i32 ||
3922 BVN->getOpcode() != ISD::BUILD_VECTOR)
3924 unsigned LoElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
3925 unsigned HiElt = 1 - LoElt;
3926 ConstantSDNode *Lo0 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt));
3927 ConstantSDNode *Hi0 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt));
3928 ConstantSDNode *Lo1 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt+2));
3929 ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2));
3930 if (!Lo0 || !Hi0 || !Lo1 || !Hi1)
3933 if (Hi0->getSExtValue() == Lo0->getSExtValue() >> 32 &&
3934 Hi1->getSExtValue() == Lo1->getSExtValue() >> 32)
3937 if (Hi0->isNullValue() && Hi1->isNullValue())
3943 if (N->getOpcode() != ISD::BUILD_VECTOR)
3946 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
3947 SDNode *Elt = N->getOperand(i).getNode();
3948 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
3949 unsigned EltSize = VT.getVectorElementType().getSizeInBits();
3950 unsigned HalfSize = EltSize / 2;
3952 int64_t SExtVal = C->getSExtValue();
3953 if ((SExtVal >> HalfSize) != (SExtVal >> EltSize))
3956 if ((C->getZExtValue() >> HalfSize) != 0)
3967 /// isSignExtended - Check if a node is a vector value that is sign-extended
3968 /// or a constant BUILD_VECTOR with sign-extended elements.
3969 static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
3970 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N))
3972 if (isExtendedBUILD_VECTOR(N, DAG, true))
3977 /// isZeroExtended - Check if a node is a vector value that is zero-extended
3978 /// or a constant BUILD_VECTOR with zero-extended elements.
3979 static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
3980 if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N))
3982 if (isExtendedBUILD_VECTOR(N, DAG, false))
3987 /// SkipExtension - For a node that is a SIGN_EXTEND, ZERO_EXTEND, extending
3988 /// load, or BUILD_VECTOR with extended elements, return the unextended value.
3989 static SDValue SkipExtension(SDNode *N, SelectionDAG &DAG) {
3990 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
3991 return N->getOperand(0);
3992 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
3993 return DAG.getLoad(LD->getMemoryVT(), N->getDebugLoc(), LD->getChain(),
3994 LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(),
3995 LD->isNonTemporal(), LD->getAlignment());
3996 // Otherwise, the value must be a BUILD_VECTOR. For v2i64, it will
3997 // have been legalized as a BITCAST from v4i32.
3998 if (N->getOpcode() == ISD::BITCAST) {
3999 SDNode *BVN = N->getOperand(0).getNode();
4000 assert(BVN->getOpcode() == ISD::BUILD_VECTOR &&
4001 BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR");
4002 unsigned LowElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
4003 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), MVT::v2i32,
4004 BVN->getOperand(LowElt), BVN->getOperand(LowElt+2));
4006 // Construct a new BUILD_VECTOR with elements truncated to half the size.
4007 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
4008 EVT VT = N->getValueType(0);
4009 unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
4010 unsigned NumElts = VT.getVectorNumElements();
4011 MVT TruncVT = MVT::getIntegerVT(EltSize);
4012 SmallVector<SDValue, 8> Ops;
4013 for (unsigned i = 0; i != NumElts; ++i) {
4014 ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
4015 const APInt &CInt = C->getAPIntValue();
4016 Ops.push_back(DAG.getConstant(CInt.trunc(EltSize), TruncVT));
4018 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
4019 MVT::getVectorVT(TruncVT, NumElts), Ops.data(), NumElts);
4022 static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
4023 // Multiplications are only custom-lowered for 128-bit vectors so that
4024 // VMULL can be detected. Otherwise v2i64 multiplications are not legal.
4025 EVT VT = Op.getValueType();
4026 assert(VT.is128BitVector() && "unexpected type for custom-lowering ISD::MUL");
4027 SDNode *N0 = Op.getOperand(0).getNode();
4028 SDNode *N1 = Op.getOperand(1).getNode();
4029 unsigned NewOpc = 0;
4030 if (isSignExtended(N0, DAG) && isSignExtended(N1, DAG))
4031 NewOpc = ARMISD::VMULLs;
4032 else if (isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG))
4033 NewOpc = ARMISD::VMULLu;
4034 else if (VT == MVT::v2i64)
4035 // Fall through to expand this. It is not legal.
4038 // Other vector multiplications are legal.
4041 // Legalize to a VMULL instruction.
4042 DebugLoc DL = Op.getDebugLoc();
4043 SDValue Op0 = SkipExtension(N0, DAG);
4044 SDValue Op1 = SkipExtension(N1, DAG);
4046 assert(Op0.getValueType().is64BitVector() &&
4047 Op1.getValueType().is64BitVector() &&
4048 "unexpected types for extended operands to VMULL");
4049 return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
4052 SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
4053 switch (Op.getOpcode()) {
4054 default: llvm_unreachable("Don't know how to custom lower this!");
4055 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
4056 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
4057 case ISD::GlobalAddress:
4058 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
4059 LowerGlobalAddressELF(Op, DAG);
4060 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
4061 case ISD::SELECT: return LowerSELECT(Op, DAG);
4062 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
4063 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
4064 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
4065 case ISD::VASTART: return LowerVASTART(Op, DAG);
4066 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG, Subtarget);
4067 case ISD::PREFETCH: return LowerPREFETCH(Op, DAG, Subtarget);
4068 case ISD::SINT_TO_FP:
4069 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
4070 case ISD::FP_TO_SINT:
4071 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG);
4072 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
4073 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
4074 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
4075 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
4076 case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
4077 case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
4078 case ISD::EH_SJLJ_DISPATCHSETUP: return LowerEH_SJLJ_DISPATCHSETUP(Op, DAG);
4079 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
4081 case ISD::BITCAST: return ExpandBITCAST(Op.getNode(), DAG);
4084 case ISD::SRA: return LowerShift(Op.getNode(), DAG, Subtarget);
4085 case ISD::SHL_PARTS: return LowerShiftLeftParts(Op, DAG);
4086 case ISD::SRL_PARTS:
4087 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
4088 case ISD::CTTZ: return LowerCTTZ(Op.getNode(), DAG, Subtarget);
4089 case ISD::VSETCC: return LowerVSETCC(Op, DAG);
4090 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG, Subtarget);
4091 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
4092 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
4093 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
4094 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
4095 case ISD::MUL: return LowerMUL(Op, DAG);
4100 /// ReplaceNodeResults - Replace the results of node with an illegal result
4101 /// type with new values built out of custom code.
4102 void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
4103 SmallVectorImpl<SDValue>&Results,
4104 SelectionDAG &DAG) const {
4106 switch (N->getOpcode()) {
4108 llvm_unreachable("Don't know how to custom expand this!");
4111 Res = ExpandBITCAST(N, DAG);
4115 Res = Expand64BitShift(N, DAG, Subtarget);
4119 Results.push_back(Res);
4122 //===----------------------------------------------------------------------===//
4123 // ARM Scheduler Hooks
4124 //===----------------------------------------------------------------------===//
4127 ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
4128 MachineBasicBlock *BB,
4129 unsigned Size) const {
4130 unsigned dest = MI->getOperand(0).getReg();
4131 unsigned ptr = MI->getOperand(1).getReg();
4132 unsigned oldval = MI->getOperand(2).getReg();
4133 unsigned newval = MI->getOperand(3).getReg();
4134 unsigned scratch = BB->getParent()->getRegInfo()
4135 .createVirtualRegister(ARM::GPRRegisterClass);
4136 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4137 DebugLoc dl = MI->getDebugLoc();
4138 bool isThumb2 = Subtarget->isThumb2();
4140 unsigned ldrOpc, strOpc;
4142 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
4144 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
4145 strOpc = isThumb2 ? ARM::t2LDREXB : ARM::STREXB;
4148 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
4149 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
4152 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
4153 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
4157 MachineFunction *MF = BB->getParent();
4158 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4159 MachineFunction::iterator It = BB;
4160 ++It; // insert the new blocks after the current block
4162 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB);
4163 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB);
4164 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
4165 MF->insert(It, loop1MBB);
4166 MF->insert(It, loop2MBB);
4167 MF->insert(It, exitMBB);
4169 // Transfer the remainder of BB and its successor edges to exitMBB.
4170 exitMBB->splice(exitMBB->begin(), BB,
4171 llvm::next(MachineBasicBlock::iterator(MI)),
4173 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4177 // fallthrough --> loop1MBB
4178 BB->addSuccessor(loop1MBB);
4181 // ldrex dest, [ptr]
4185 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
4186 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
4187 .addReg(dest).addReg(oldval));
4188 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4189 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
4190 BB->addSuccessor(loop2MBB);
4191 BB->addSuccessor(exitMBB);
4194 // strex scratch, newval, [ptr]
4198 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(newval)
4200 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4201 .addReg(scratch).addImm(0));
4202 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4203 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
4204 BB->addSuccessor(loop1MBB);
4205 BB->addSuccessor(exitMBB);
4211 MI->eraseFromParent(); // The instruction is gone now.
4217 ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
4218 unsigned Size, unsigned BinOpcode) const {
4219 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4220 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4222 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4223 MachineFunction *MF = BB->getParent();
4224 MachineFunction::iterator It = BB;
4227 unsigned dest = MI->getOperand(0).getReg();
4228 unsigned ptr = MI->getOperand(1).getReg();
4229 unsigned incr = MI->getOperand(2).getReg();
4230 DebugLoc dl = MI->getDebugLoc();
4232 bool isThumb2 = Subtarget->isThumb2();
4233 unsigned ldrOpc, strOpc;
4235 default: llvm_unreachable("unsupported size for AtomicCmpSwap!");
4237 ldrOpc = isThumb2 ? ARM::t2LDREXB : ARM::LDREXB;
4238 strOpc = isThumb2 ? ARM::t2STREXB : ARM::STREXB;
4241 ldrOpc = isThumb2 ? ARM::t2LDREXH : ARM::LDREXH;
4242 strOpc = isThumb2 ? ARM::t2STREXH : ARM::STREXH;
4245 ldrOpc = isThumb2 ? ARM::t2LDREX : ARM::LDREX;
4246 strOpc = isThumb2 ? ARM::t2STREX : ARM::STREX;
4250 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
4251 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
4252 MF->insert(It, loopMBB);
4253 MF->insert(It, exitMBB);
4255 // Transfer the remainder of BB and its successor edges to exitMBB.
4256 exitMBB->splice(exitMBB->begin(), BB,
4257 llvm::next(MachineBasicBlock::iterator(MI)),
4259 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4261 MachineRegisterInfo &RegInfo = MF->getRegInfo();
4262 unsigned scratch = RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
4263 unsigned scratch2 = (!BinOpcode) ? incr :
4264 RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
4268 // fallthrough --> loopMBB
4269 BB->addSuccessor(loopMBB);
4273 // <binop> scratch2, dest, incr
4274 // strex scratch, scratch2, ptr
4277 // fallthrough --> exitMBB
4279 AddDefaultPred(BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr));
4281 // operand order needs to go the other way for NAND
4282 if (BinOpcode == ARM::BICrr || BinOpcode == ARM::t2BICrr)
4283 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
4284 addReg(incr).addReg(dest)).addReg(0);
4286 AddDefaultPred(BuildMI(BB, dl, TII->get(BinOpcode), scratch2).
4287 addReg(dest).addReg(incr)).addReg(0);
4290 AddDefaultPred(BuildMI(BB, dl, TII->get(strOpc), scratch).addReg(scratch2)
4292 AddDefaultPred(BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4293 .addReg(scratch).addImm(0));
4294 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4295 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
4297 BB->addSuccessor(loopMBB);
4298 BB->addSuccessor(exitMBB);
4304 MI->eraseFromParent(); // The instruction is gone now.
4310 MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
4311 for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
4312 E = MBB->succ_end(); I != E; ++I)
4315 llvm_unreachable("Expecting a BB with two successors!");
4319 ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4320 MachineBasicBlock *BB) const {
4321 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4322 DebugLoc dl = MI->getDebugLoc();
4323 bool isThumb2 = Subtarget->isThumb2();
4324 switch (MI->getOpcode()) {
4327 llvm_unreachable("Unexpected instr type to insert");
4329 case ARM::ATOMIC_LOAD_ADD_I8:
4330 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
4331 case ARM::ATOMIC_LOAD_ADD_I16:
4332 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
4333 case ARM::ATOMIC_LOAD_ADD_I32:
4334 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ADDrr : ARM::ADDrr);
4336 case ARM::ATOMIC_LOAD_AND_I8:
4337 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
4338 case ARM::ATOMIC_LOAD_AND_I16:
4339 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
4340 case ARM::ATOMIC_LOAD_AND_I32:
4341 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ANDrr : ARM::ANDrr);
4343 case ARM::ATOMIC_LOAD_OR_I8:
4344 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
4345 case ARM::ATOMIC_LOAD_OR_I16:
4346 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
4347 case ARM::ATOMIC_LOAD_OR_I32:
4348 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2ORRrr : ARM::ORRrr);
4350 case ARM::ATOMIC_LOAD_XOR_I8:
4351 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
4352 case ARM::ATOMIC_LOAD_XOR_I16:
4353 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
4354 case ARM::ATOMIC_LOAD_XOR_I32:
4355 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2EORrr : ARM::EORrr);
4357 case ARM::ATOMIC_LOAD_NAND_I8:
4358 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
4359 case ARM::ATOMIC_LOAD_NAND_I16:
4360 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
4361 case ARM::ATOMIC_LOAD_NAND_I32:
4362 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2BICrr : ARM::BICrr);
4364 case ARM::ATOMIC_LOAD_SUB_I8:
4365 return EmitAtomicBinary(MI, BB, 1, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
4366 case ARM::ATOMIC_LOAD_SUB_I16:
4367 return EmitAtomicBinary(MI, BB, 2, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
4368 case ARM::ATOMIC_LOAD_SUB_I32:
4369 return EmitAtomicBinary(MI, BB, 4, isThumb2 ? ARM::t2SUBrr : ARM::SUBrr);
4371 case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0);
4372 case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0);
4373 case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0);
4375 case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1);
4376 case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
4377 case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
4379 case ARM::tMOVCCr_pseudo: {
4380 // To "insert" a SELECT_CC instruction, we actually have to insert the
4381 // diamond control-flow pattern. The incoming instruction knows the
4382 // destination vreg to set, the condition code register to branch on, the
4383 // true/false values to select between, and a branch opcode to use.
4384 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4385 MachineFunction::iterator It = BB;
4391 // cmpTY ccX, r1, r2
4393 // fallthrough --> copy0MBB
4394 MachineBasicBlock *thisMBB = BB;
4395 MachineFunction *F = BB->getParent();
4396 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4397 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
4398 F->insert(It, copy0MBB);
4399 F->insert(It, sinkMBB);
4401 // Transfer the remainder of BB and its successor edges to sinkMBB.
4402 sinkMBB->splice(sinkMBB->begin(), BB,
4403 llvm::next(MachineBasicBlock::iterator(MI)),
4405 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
4407 BB->addSuccessor(copy0MBB);
4408 BB->addSuccessor(sinkMBB);
4410 BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
4411 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
4414 // %FalseValue = ...
4415 // # fallthrough to sinkMBB
4418 // Update machine-CFG edges
4419 BB->addSuccessor(sinkMBB);
4422 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
4425 BuildMI(*BB, BB->begin(), dl,
4426 TII->get(ARM::PHI), MI->getOperand(0).getReg())
4427 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
4428 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
4430 MI->eraseFromParent(); // The pseudo instruction is gone now.
4435 case ARM::BCCZi64: {
4436 // Compare both parts that make up the double comparison separately for
4438 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
4440 unsigned LHS1 = MI->getOperand(1).getReg();
4441 unsigned LHS2 = MI->getOperand(2).getReg();
4443 AddDefaultPred(BuildMI(BB, dl,
4444 TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4445 .addReg(LHS1).addImm(0));
4446 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
4447 .addReg(LHS2).addImm(0)
4448 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
4450 unsigned RHS1 = MI->getOperand(3).getReg();
4451 unsigned RHS2 = MI->getOperand(4).getReg();
4452 AddDefaultPred(BuildMI(BB, dl,
4453 TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
4454 .addReg(LHS1).addReg(RHS1));
4455 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
4456 .addReg(LHS2).addReg(RHS2)
4457 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
4460 MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB();
4461 MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
4462 if (MI->getOperand(0).getImm() == ARMCC::NE)
4463 std::swap(destMBB, exitMBB);
4465 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
4466 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
4467 BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2B : ARM::B))
4470 MI->eraseFromParent(); // The pseudo instruction is gone now.
4476 //===----------------------------------------------------------------------===//
4477 // ARM Optimization Hooks
4478 //===----------------------------------------------------------------------===//
4481 SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
4482 TargetLowering::DAGCombinerInfo &DCI) {
4483 SelectionDAG &DAG = DCI.DAG;
4484 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
4485 EVT VT = N->getValueType(0);
4486 unsigned Opc = N->getOpcode();
4487 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
4488 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
4489 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
4490 ISD::CondCode CC = ISD::SETCC_INVALID;
4493 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
4495 SDValue CCOp = Slct.getOperand(0);
4496 if (CCOp.getOpcode() == ISD::SETCC)
4497 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
4500 bool DoXform = false;
4502 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
4505 if (LHS.getOpcode() == ISD::Constant &&
4506 cast<ConstantSDNode>(LHS)->isNullValue()) {
4508 } else if (CC != ISD::SETCC_INVALID &&
4509 RHS.getOpcode() == ISD::Constant &&
4510 cast<ConstantSDNode>(RHS)->isNullValue()) {
4511 std::swap(LHS, RHS);
4512 SDValue Op0 = Slct.getOperand(0);
4513 EVT OpVT = isSlctCC ? Op0.getValueType() :
4514 Op0.getOperand(0).getValueType();
4515 bool isInt = OpVT.isInteger();
4516 CC = ISD::getSetCCInverse(CC, isInt);
4518 if (!TLI.isCondCodeLegal(CC, OpVT))
4519 return SDValue(); // Inverse operator isn't legal.
4526 SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
4528 return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
4529 Slct.getOperand(0), Slct.getOperand(1), CC);
4530 SDValue CCOp = Slct.getOperand(0);
4532 CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
4533 CCOp.getOperand(0), CCOp.getOperand(1), CC);
4534 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
4535 CCOp, OtherOp, Result);
4540 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
4541 /// operands N0 and N1. This is a helper for PerformADDCombine that is
4542 /// called with the default operands, and if that fails, with commuted
4544 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
4545 TargetLowering::DAGCombinerInfo &DCI) {
4546 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
4547 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
4548 SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
4549 if (Result.getNode()) return Result;
4554 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
4556 static SDValue PerformADDCombine(SDNode *N,
4557 TargetLowering::DAGCombinerInfo &DCI) {
4558 SDValue N0 = N->getOperand(0);
4559 SDValue N1 = N->getOperand(1);
4561 // First try with the default operand order.
4562 SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI);
4563 if (Result.getNode())
4566 // If that didn't work, try again with the operands commuted.
4567 return PerformADDCombineWithOperands(N, N1, N0, DCI);
4570 /// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
4572 static SDValue PerformSUBCombine(SDNode *N,
4573 TargetLowering::DAGCombinerInfo &DCI) {
4574 SDValue N0 = N->getOperand(0);
4575 SDValue N1 = N->getOperand(1);
4577 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
4578 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
4579 SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
4580 if (Result.getNode()) return Result;
4586 static SDValue PerformMULCombine(SDNode *N,
4587 TargetLowering::DAGCombinerInfo &DCI,
4588 const ARMSubtarget *Subtarget) {
4589 SelectionDAG &DAG = DCI.DAG;
4591 if (Subtarget->isThumb1Only())
4594 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
4597 EVT VT = N->getValueType(0);
4601 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
4605 uint64_t MulAmt = C->getZExtValue();
4606 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt);
4607 ShiftAmt = ShiftAmt & (32 - 1);
4608 SDValue V = N->getOperand(0);
4609 DebugLoc DL = N->getDebugLoc();
4612 MulAmt >>= ShiftAmt;
4613 if (isPowerOf2_32(MulAmt - 1)) {
4614 // (mul x, 2^N + 1) => (add (shl x, N), x)
4615 Res = DAG.getNode(ISD::ADD, DL, VT,
4616 V, DAG.getNode(ISD::SHL, DL, VT,
4617 V, DAG.getConstant(Log2_32(MulAmt-1),
4619 } else if (isPowerOf2_32(MulAmt + 1)) {
4620 // (mul x, 2^N - 1) => (sub (shl x, N), x)
4621 Res = DAG.getNode(ISD::SUB, DL, VT,
4622 DAG.getNode(ISD::SHL, DL, VT,
4623 V, DAG.getConstant(Log2_32(MulAmt+1),
4630 Res = DAG.getNode(ISD::SHL, DL, VT, Res,
4631 DAG.getConstant(ShiftAmt, MVT::i32));
4633 // Do not add new nodes to DAG combiner worklist.
4634 DCI.CombineTo(N, Res, false);
4638 static SDValue PerformANDCombine(SDNode *N,
4639 TargetLowering::DAGCombinerInfo &DCI) {
4640 // Attempt to use immediate-form VBIC
4641 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
4642 DebugLoc dl = N->getDebugLoc();
4643 EVT VT = N->getValueType(0);
4644 SelectionDAG &DAG = DCI.DAG;
4646 APInt SplatBits, SplatUndef;
4647 unsigned SplatBitSize;
4650 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
4651 if (SplatBitSize <= 64) {
4653 SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(),
4654 SplatUndef.getZExtValue(), SplatBitSize,
4655 DAG, VbicVT, VT.is128BitVector(),
4657 if (Val.getNode()) {
4659 DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0));
4660 SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val);
4661 return DAG.getNode(ISD::BITCAST, dl, VT, Vbic);
4669 /// PerformORCombine - Target-specific dag combine xforms for ISD::OR
4670 static SDValue PerformORCombine(SDNode *N,
4671 TargetLowering::DAGCombinerInfo &DCI,
4672 const ARMSubtarget *Subtarget) {
4673 // Attempt to use immediate-form VORR
4674 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
4675 DebugLoc dl = N->getDebugLoc();
4676 EVT VT = N->getValueType(0);
4677 SelectionDAG &DAG = DCI.DAG;
4679 APInt SplatBits, SplatUndef;
4680 unsigned SplatBitSize;
4682 if (BVN && Subtarget->hasNEON() &&
4683 BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
4684 if (SplatBitSize <= 64) {
4686 SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
4687 SplatUndef.getZExtValue(), SplatBitSize,
4688 DAG, VorrVT, VT.is128BitVector(),
4690 if (Val.getNode()) {
4692 DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0));
4693 SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val);
4694 return DAG.getNode(ISD::BITCAST, dl, VT, Vorr);
4699 // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when
4702 // BFI is only available on V6T2+
4703 if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops())
4706 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
4707 DebugLoc DL = N->getDebugLoc();
4708 // 1) or (and A, mask), val => ARMbfi A, val, mask
4709 // iff (val & mask) == val
4711 // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
4712 // 2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2)
4713 // && CountPopulation_32(mask) == CountPopulation_32(~mask2)
4714 // 2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2)
4715 // && CountPopulation_32(mask) == CountPopulation_32(~mask2)
4716 // (i.e., copy a bitfield value into another bitfield of the same width)
4717 if (N0.getOpcode() != ISD::AND)
4723 SDValue N00 = N0.getOperand(0);
4725 // The value and the mask need to be constants so we can verify this is
4726 // actually a bitfield set. If the mask is 0xffff, we can do better
4727 // via a movt instruction, so don't use BFI in that case.
4728 SDValue MaskOp = N0.getOperand(1);
4729 ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(MaskOp);
4732 unsigned Mask = MaskC->getZExtValue();
4736 // Case (1): or (and A, mask), val => ARMbfi A, val, mask
4737 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
4739 unsigned Val = N1C->getZExtValue();
4740 if ((Val & ~Mask) != Val)
4743 if (ARM::isBitFieldInvertedMask(Mask)) {
4744 Val >>= CountTrailingZeros_32(~Mask);
4746 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00,
4747 DAG.getConstant(Val, MVT::i32),
4748 DAG.getConstant(Mask, MVT::i32));
4750 // Do not add new nodes to DAG combiner worklist.
4751 DCI.CombineTo(N, Res, false);
4754 } else if (N1.getOpcode() == ISD::AND) {
4755 // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
4756 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
4759 unsigned Mask2 = N11C->getZExtValue();
4761 if (ARM::isBitFieldInvertedMask(Mask) &&
4762 ARM::isBitFieldInvertedMask(~Mask2) &&
4763 (CountPopulation_32(Mask) == CountPopulation_32(~Mask2))) {
4764 // The pack halfword instruction works better for masks that fit it,
4765 // so use that when it's available.
4766 if (Subtarget->hasT2ExtractPack() &&
4767 (Mask == 0xffff || Mask == 0xffff0000))
4770 unsigned lsb = CountTrailingZeros_32(Mask2);
4771 Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
4772 DAG.getConstant(lsb, MVT::i32));
4773 Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res,
4774 DAG.getConstant(Mask, MVT::i32));
4775 // Do not add new nodes to DAG combiner worklist.
4776 DCI.CombineTo(N, Res, false);
4778 } else if (ARM::isBitFieldInvertedMask(~Mask) &&
4779 ARM::isBitFieldInvertedMask(Mask2) &&
4780 (CountPopulation_32(~Mask) == CountPopulation_32(Mask2))) {
4781 // The pack halfword instruction works better for masks that fit it,
4782 // so use that when it's available.
4783 if (Subtarget->hasT2ExtractPack() &&
4784 (Mask2 == 0xffff || Mask2 == 0xffff0000))
4787 unsigned lsb = CountTrailingZeros_32(Mask);
4788 Res = DAG.getNode(ISD::SRL, DL, VT, N00,
4789 DAG.getConstant(lsb, MVT::i32));
4790 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
4791 DAG.getConstant(Mask2, MVT::i32));
4792 // Do not add new nodes to DAG combiner worklist.
4793 DCI.CombineTo(N, Res, false);
4798 if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) &&
4799 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) &&
4800 ARM::isBitFieldInvertedMask(~Mask)) {
4801 // Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask
4802 // where lsb(mask) == #shamt and masked bits of B are known zero.
4803 SDValue ShAmt = N00.getOperand(1);
4804 unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue();
4805 unsigned LSB = CountTrailingZeros_32(Mask);
4809 Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0),
4810 DAG.getConstant(~Mask, MVT::i32));
4812 // Do not add new nodes to DAG combiner worklist.
4813 DCI.CombineTo(N, Res, false);
4819 /// PerformBFICombine - (bfi A, (and B, C1), C2) -> (bfi A, B, C2) iff
4821 static SDValue PerformBFICombine(SDNode *N,
4822 TargetLowering::DAGCombinerInfo &DCI) {
4823 SDValue N1 = N->getOperand(1);
4824 if (N1.getOpcode() == ISD::AND) {
4825 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
4828 unsigned Mask = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
4829 unsigned Mask2 = N11C->getZExtValue();
4830 if ((Mask & Mask2) == Mask2)
4831 return DCI.DAG.getNode(ARMISD::BFI, N->getDebugLoc(), N->getValueType(0),
4832 N->getOperand(0), N1.getOperand(0),
4838 /// PerformVMOVRRDCombine - Target-specific dag combine xforms for
4839 /// ARMISD::VMOVRRD.
4840 static SDValue PerformVMOVRRDCombine(SDNode *N,
4841 TargetLowering::DAGCombinerInfo &DCI) {
4842 // vmovrrd(vmovdrr x, y) -> x,y
4843 SDValue InDouble = N->getOperand(0);
4844 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
4845 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
4849 /// PerformVMOVDRRCombine - Target-specific dag combine xforms for
4850 /// ARMISD::VMOVDRR. This is also used for BUILD_VECTORs with 2 operands.
4851 static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) {
4852 // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X)
4853 SDValue Op0 = N->getOperand(0);
4854 SDValue Op1 = N->getOperand(1);
4855 if (Op0.getOpcode() == ISD::BITCAST)
4856 Op0 = Op0.getOperand(0);
4857 if (Op1.getOpcode() == ISD::BITCAST)
4858 Op1 = Op1.getOperand(0);
4859 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
4860 Op0.getNode() == Op1.getNode() &&
4861 Op0.getResNo() == 0 && Op1.getResNo() == 1)
4862 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(),
4863 N->getValueType(0), Op0.getOperand(0));
4867 /// PerformSTORECombine - Target-specific dag combine xforms for
4869 static SDValue PerformSTORECombine(SDNode *N,
4870 TargetLowering::DAGCombinerInfo &DCI) {
4871 // Bitcast an i64 store extracted from a vector to f64.
4872 // Otherwise, the i64 value will be legalized to a pair of i32 values.
4873 StoreSDNode *St = cast<StoreSDNode>(N);
4874 SDValue StVal = St->getValue();
4875 if (!ISD::isNormalStore(St) || St->isVolatile() ||
4876 StVal.getValueType() != MVT::i64 ||
4877 StVal.getNode()->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
4880 SelectionDAG &DAG = DCI.DAG;
4881 DebugLoc dl = StVal.getDebugLoc();
4882 SDValue IntVec = StVal.getOperand(0);
4883 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
4884 IntVec.getValueType().getVectorNumElements());
4885 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec);
4886 SDValue ExtElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
4887 Vec, StVal.getOperand(1));
4888 dl = N->getDebugLoc();
4889 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt);
4890 // Make the DAGCombiner fold the bitcasts.
4891 DCI.AddToWorklist(Vec.getNode());
4892 DCI.AddToWorklist(ExtElt.getNode());
4893 DCI.AddToWorklist(V.getNode());
4894 return DAG.getStore(St->getChain(), dl, V, St->getBasePtr(),
4895 St->getPointerInfo(), St->isVolatile(),
4896 St->isNonTemporal(), St->getAlignment(),
4900 /// hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node
4901 /// are normal, non-volatile loads. If so, it is profitable to bitcast an
4902 /// i64 vector to have f64 elements, since the value can then be loaded
4903 /// directly into a VFP register.
4904 static bool hasNormalLoadOperand(SDNode *N) {
4905 unsigned NumElts = N->getValueType(0).getVectorNumElements();
4906 for (unsigned i = 0; i < NumElts; ++i) {
4907 SDNode *Elt = N->getOperand(i).getNode();
4908 if (ISD::isNormalLoad(Elt) && !cast<LoadSDNode>(Elt)->isVolatile())
4914 /// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for
4915 /// ISD::BUILD_VECTOR.
4916 static SDValue PerformBUILD_VECTORCombine(SDNode *N,
4917 TargetLowering::DAGCombinerInfo &DCI){
4918 // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X):
4919 // VMOVRRD is introduced when legalizing i64 types. It forces the i64 value
4920 // into a pair of GPRs, which is fine when the value is used as a scalar,
4921 // but if the i64 value is converted to a vector, we need to undo the VMOVRRD.
4922 SelectionDAG &DAG = DCI.DAG;
4923 if (N->getNumOperands() == 2) {
4924 SDValue RV = PerformVMOVDRRCombine(N, DAG);
4929 // Load i64 elements as f64 values so that type legalization does not split
4930 // them up into i32 values.
4931 EVT VT = N->getValueType(0);
4932 if (VT.getVectorElementType() != MVT::i64 || !hasNormalLoadOperand(N))
4934 DebugLoc dl = N->getDebugLoc();
4935 SmallVector<SDValue, 8> Ops;
4936 unsigned NumElts = VT.getVectorNumElements();
4937 for (unsigned i = 0; i < NumElts; ++i) {
4938 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(i));
4940 // Make the DAGCombiner fold the bitcast.
4941 DCI.AddToWorklist(V.getNode());
4943 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, NumElts);
4944 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, FloatVT, Ops.data(), NumElts);
4945 return DAG.getNode(ISD::BITCAST, dl, VT, BV);
4948 /// PerformInsertEltCombine - Target-specific dag combine xforms for
4949 /// ISD::INSERT_VECTOR_ELT.
4950 static SDValue PerformInsertEltCombine(SDNode *N,
4951 TargetLowering::DAGCombinerInfo &DCI) {
4952 // Bitcast an i64 load inserted into a vector to f64.
4953 // Otherwise, the i64 value will be legalized to a pair of i32 values.
4954 EVT VT = N->getValueType(0);
4955 SDNode *Elt = N->getOperand(1).getNode();
4956 if (VT.getVectorElementType() != MVT::i64 ||
4957 !ISD::isNormalLoad(Elt) || cast<LoadSDNode>(Elt)->isVolatile())
4960 SelectionDAG &DAG = DCI.DAG;
4961 DebugLoc dl = N->getDebugLoc();
4962 EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
4963 VT.getVectorNumElements());
4964 SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, N->getOperand(0));
4965 SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(1));
4966 // Make the DAGCombiner fold the bitcasts.
4967 DCI.AddToWorklist(Vec.getNode());
4968 DCI.AddToWorklist(V.getNode());
4969 SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT,
4970 Vec, V, N->getOperand(2));
4971 return DAG.getNode(ISD::BITCAST, dl, VT, InsElt);
4974 /// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for
4975 /// ISD::VECTOR_SHUFFLE.
4976 static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) {
4977 // The LLVM shufflevector instruction does not require the shuffle mask
4978 // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does
4979 // have that requirement. When translating to ISD::VECTOR_SHUFFLE, if the
4980 // operands do not match the mask length, they are extended by concatenating
4981 // them with undef vectors. That is probably the right thing for other
4982 // targets, but for NEON it is better to concatenate two double-register
4983 // size vector operands into a single quad-register size vector. Do that
4984 // transformation here:
4985 // shuffle(concat(v1, undef), concat(v2, undef)) ->
4986 // shuffle(concat(v1, v2), undef)
4987 SDValue Op0 = N->getOperand(0);
4988 SDValue Op1 = N->getOperand(1);
4989 if (Op0.getOpcode() != ISD::CONCAT_VECTORS ||
4990 Op1.getOpcode() != ISD::CONCAT_VECTORS ||
4991 Op0.getNumOperands() != 2 ||
4992 Op1.getNumOperands() != 2)
4994 SDValue Concat0Op1 = Op0.getOperand(1);
4995 SDValue Concat1Op1 = Op1.getOperand(1);
4996 if (Concat0Op1.getOpcode() != ISD::UNDEF ||
4997 Concat1Op1.getOpcode() != ISD::UNDEF)
4999 // Skip the transformation if any of the types are illegal.
5000 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5001 EVT VT = N->getValueType(0);
5002 if (!TLI.isTypeLegal(VT) ||
5003 !TLI.isTypeLegal(Concat0Op1.getValueType()) ||
5004 !TLI.isTypeLegal(Concat1Op1.getValueType()))
5007 SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT,
5008 Op0.getOperand(0), Op1.getOperand(0));
5009 // Translate the shuffle mask.
5010 SmallVector<int, 16> NewMask;
5011 unsigned NumElts = VT.getVectorNumElements();
5012 unsigned HalfElts = NumElts/2;
5013 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
5014 for (unsigned n = 0; n < NumElts; ++n) {
5015 int MaskElt = SVN->getMaskElt(n);
5017 if (MaskElt < (int)HalfElts)
5019 else if (MaskElt >= (int)NumElts && MaskElt < (int)(NumElts + HalfElts))
5020 NewElt = HalfElts + MaskElt - NumElts;
5021 NewMask.push_back(NewElt);
5023 return DAG.getVectorShuffle(VT, N->getDebugLoc(), NewConcat,
5024 DAG.getUNDEF(VT), NewMask.data());
5027 /// CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a
5028 /// vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic
5029 /// are also VDUPLANEs. If so, combine them to a vldN-dup operation and
5031 static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
5032 SelectionDAG &DAG = DCI.DAG;
5033 EVT VT = N->getValueType(0);
5034 // vldN-dup instructions only support 64-bit vectors for N > 1.
5035 if (!VT.is64BitVector())
5038 // Check if the VDUPLANE operand is a vldN-dup intrinsic.
5039 SDNode *VLD = N->getOperand(0).getNode();
5040 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN)
5042 unsigned NumVecs = 0;
5043 unsigned NewOpc = 0;
5044 unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue();
5045 if (IntNo == Intrinsic::arm_neon_vld2lane) {
5047 NewOpc = ARMISD::VLD2DUP;
5048 } else if (IntNo == Intrinsic::arm_neon_vld3lane) {
5050 NewOpc = ARMISD::VLD3DUP;
5051 } else if (IntNo == Intrinsic::arm_neon_vld4lane) {
5053 NewOpc = ARMISD::VLD4DUP;
5058 // First check that all the vldN-lane uses are VDUPLANEs and that the lane
5059 // numbers match the load.
5060 unsigned VLDLaneNo =
5061 cast<ConstantSDNode>(VLD->getOperand(NumVecs+3))->getZExtValue();
5062 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
5064 // Ignore uses of the chain result.
5065 if (UI.getUse().getResNo() == NumVecs)
5068 if (User->getOpcode() != ARMISD::VDUPLANE ||
5069 VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue())
5073 // Create the vldN-dup node.
5076 for (n = 0; n < NumVecs; ++n)
5078 Tys[n] = MVT::Other;
5079 SDVTList SDTys = DAG.getVTList(Tys, NumVecs+1);
5080 SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) };
5081 MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD);
5082 SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, VLD->getDebugLoc(), SDTys,
5083 Ops, 2, VLDMemInt->getMemoryVT(),
5084 VLDMemInt->getMemOperand());
5087 for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
5089 unsigned ResNo = UI.getUse().getResNo();
5090 // Ignore uses of the chain result.
5091 if (ResNo == NumVecs)
5094 DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo));
5097 // Now the vldN-lane intrinsic is dead except for its chain result.
5098 // Update uses of the chain.
5099 std::vector<SDValue> VLDDupResults;
5100 for (unsigned n = 0; n < NumVecs; ++n)
5101 VLDDupResults.push_back(SDValue(VLDDup.getNode(), n));
5102 VLDDupResults.push_back(SDValue(VLDDup.getNode(), NumVecs));
5103 DCI.CombineTo(VLD, VLDDupResults);
5108 /// PerformVDUPLANECombine - Target-specific dag combine xforms for
5109 /// ARMISD::VDUPLANE.
5110 static SDValue PerformVDUPLANECombine(SDNode *N,
5111 TargetLowering::DAGCombinerInfo &DCI) {
5112 SDValue Op = N->getOperand(0);
5114 // If the source is a vldN-lane (N > 1) intrinsic, and all the other uses
5115 // of that intrinsic are also VDUPLANEs, combine them to a vldN-dup operation.
5116 if (CombineVLDDUP(N, DCI))
5117 return SDValue(N, 0);
5119 // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
5120 // redundant. Ignore bit_converts for now; element sizes are checked below.
5121 while (Op.getOpcode() == ISD::BITCAST)
5122 Op = Op.getOperand(0);
5123 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
5126 // Make sure the VMOV element size is not bigger than the VDUPLANE elements.
5127 unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits();
5128 // The canonical VMOV for a zero vector uses a 32-bit element size.
5129 unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5131 if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
5133 EVT VT = N->getValueType(0);
5134 if (EltSize > VT.getVectorElementType().getSizeInBits())
5137 return DCI.DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
5140 /// getVShiftImm - Check if this is a valid build_vector for the immediate
5141 /// operand of a vector shift operation, where all the elements of the
5142 /// build_vector must have the same constant integer value.
5143 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
5144 // Ignore bit_converts.
5145 while (Op.getOpcode() == ISD::BITCAST)
5146 Op = Op.getOperand(0);
5147 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5148 APInt SplatBits, SplatUndef;
5149 unsigned SplatBitSize;
5151 if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
5152 HasAnyUndefs, ElementBits) ||
5153 SplatBitSize > ElementBits)
5155 Cnt = SplatBits.getSExtValue();
5159 /// isVShiftLImm - Check if this is a valid build_vector for the immediate
5160 /// operand of a vector shift left operation. That value must be in the range:
5161 /// 0 <= Value < ElementBits for a left shift; or
5162 /// 0 <= Value <= ElementBits for a long left shift.
5163 static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
5164 assert(VT.isVector() && "vector shift count is not a vector type");
5165 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
5166 if (! getVShiftImm(Op, ElementBits, Cnt))
5168 return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
5171 /// isVShiftRImm - Check if this is a valid build_vector for the immediate
5172 /// operand of a vector shift right operation. For a shift opcode, the value
5173 /// is positive, but for an intrinsic the value count must be negative. The
5174 /// absolute value must be in the range:
5175 /// 1 <= |Value| <= ElementBits for a right shift; or
5176 /// 1 <= |Value| <= ElementBits/2 for a narrow right shift.
5177 static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
5179 assert(VT.isVector() && "vector shift count is not a vector type");
5180 unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
5181 if (! getVShiftImm(Op, ElementBits, Cnt))
5185 return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
5188 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
5189 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
5190 unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
5193 // Don't do anything for most intrinsics.
5196 // Vector shifts: check for immediate versions and lower them.
5197 // Note: This is done during DAG combining instead of DAG legalizing because
5198 // the build_vectors for 64-bit vector element shift counts are generally
5199 // not legal, and it is hard to see their values after they get legalized to
5200 // loads from a constant pool.
5201 case Intrinsic::arm_neon_vshifts:
5202 case Intrinsic::arm_neon_vshiftu:
5203 case Intrinsic::arm_neon_vshiftls:
5204 case Intrinsic::arm_neon_vshiftlu:
5205 case Intrinsic::arm_neon_vshiftn:
5206 case Intrinsic::arm_neon_vrshifts:
5207 case Intrinsic::arm_neon_vrshiftu:
5208 case Intrinsic::arm_neon_vrshiftn:
5209 case Intrinsic::arm_neon_vqshifts:
5210 case Intrinsic::arm_neon_vqshiftu:
5211 case Intrinsic::arm_neon_vqshiftsu:
5212 case Intrinsic::arm_neon_vqshiftns:
5213 case Intrinsic::arm_neon_vqshiftnu:
5214 case Intrinsic::arm_neon_vqshiftnsu:
5215 case Intrinsic::arm_neon_vqrshiftns:
5216 case Intrinsic::arm_neon_vqrshiftnu:
5217 case Intrinsic::arm_neon_vqrshiftnsu: {
5218 EVT VT = N->getOperand(1).getValueType();
5220 unsigned VShiftOpc = 0;
5223 case Intrinsic::arm_neon_vshifts:
5224 case Intrinsic::arm_neon_vshiftu:
5225 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
5226 VShiftOpc = ARMISD::VSHL;
5229 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
5230 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
5231 ARMISD::VSHRs : ARMISD::VSHRu);
5236 case Intrinsic::arm_neon_vshiftls:
5237 case Intrinsic::arm_neon_vshiftlu:
5238 if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
5240 llvm_unreachable("invalid shift count for vshll intrinsic");
5242 case Intrinsic::arm_neon_vrshifts:
5243 case Intrinsic::arm_neon_vrshiftu:
5244 if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
5248 case Intrinsic::arm_neon_vqshifts:
5249 case Intrinsic::arm_neon_vqshiftu:
5250 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
5254 case Intrinsic::arm_neon_vqshiftsu:
5255 if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
5257 llvm_unreachable("invalid shift count for vqshlu intrinsic");
5259 case Intrinsic::arm_neon_vshiftn:
5260 case Intrinsic::arm_neon_vrshiftn:
5261 case Intrinsic::arm_neon_vqshiftns:
5262 case Intrinsic::arm_neon_vqshiftnu:
5263 case Intrinsic::arm_neon_vqshiftnsu:
5264 case Intrinsic::arm_neon_vqrshiftns:
5265 case Intrinsic::arm_neon_vqrshiftnu:
5266 case Intrinsic::arm_neon_vqrshiftnsu:
5267 // Narrowing shifts require an immediate right shift.
5268 if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
5270 llvm_unreachable("invalid shift count for narrowing vector shift "
5274 llvm_unreachable("unhandled vector shift");
5278 case Intrinsic::arm_neon_vshifts:
5279 case Intrinsic::arm_neon_vshiftu:
5280 // Opcode already set above.
5282 case Intrinsic::arm_neon_vshiftls:
5283 case Intrinsic::arm_neon_vshiftlu:
5284 if (Cnt == VT.getVectorElementType().getSizeInBits())
5285 VShiftOpc = ARMISD::VSHLLi;
5287 VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
5288 ARMISD::VSHLLs : ARMISD::VSHLLu);
5290 case Intrinsic::arm_neon_vshiftn:
5291 VShiftOpc = ARMISD::VSHRN; break;
5292 case Intrinsic::arm_neon_vrshifts:
5293 VShiftOpc = ARMISD::VRSHRs; break;
5294 case Intrinsic::arm_neon_vrshiftu:
5295 VShiftOpc = ARMISD::VRSHRu; break;
5296 case Intrinsic::arm_neon_vrshiftn:
5297 VShiftOpc = ARMISD::VRSHRN; break;
5298 case Intrinsic::arm_neon_vqshifts:
5299 VShiftOpc = ARMISD::VQSHLs; break;
5300 case Intrinsic::arm_neon_vqshiftu:
5301 VShiftOpc = ARMISD::VQSHLu; break;
5302 case Intrinsic::arm_neon_vqshiftsu:
5303 VShiftOpc = ARMISD::VQSHLsu; break;
5304 case Intrinsic::arm_neon_vqshiftns:
5305 VShiftOpc = ARMISD::VQSHRNs; break;
5306 case Intrinsic::arm_neon_vqshiftnu:
5307 VShiftOpc = ARMISD::VQSHRNu; break;
5308 case Intrinsic::arm_neon_vqshiftnsu:
5309 VShiftOpc = ARMISD::VQSHRNsu; break;
5310 case Intrinsic::arm_neon_vqrshiftns:
5311 VShiftOpc = ARMISD::VQRSHRNs; break;
5312 case Intrinsic::arm_neon_vqrshiftnu:
5313 VShiftOpc = ARMISD::VQRSHRNu; break;
5314 case Intrinsic::arm_neon_vqrshiftnsu:
5315 VShiftOpc = ARMISD::VQRSHRNsu; break;
5318 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
5319 N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
5322 case Intrinsic::arm_neon_vshiftins: {
5323 EVT VT = N->getOperand(1).getValueType();
5325 unsigned VShiftOpc = 0;
5327 if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
5328 VShiftOpc = ARMISD::VSLI;
5329 else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
5330 VShiftOpc = ARMISD::VSRI;
5332 llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
5335 return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
5336 N->getOperand(1), N->getOperand(2),
5337 DAG.getConstant(Cnt, MVT::i32));
5340 case Intrinsic::arm_neon_vqrshifts:
5341 case Intrinsic::arm_neon_vqrshiftu:
5342 // No immediate versions of these to check for.
5349 /// PerformShiftCombine - Checks for immediate versions of vector shifts and
5350 /// lowers them. As with the vector shift intrinsics, this is done during DAG
5351 /// combining instead of DAG legalizing because the build_vectors for 64-bit
5352 /// vector element shift counts are generally not legal, and it is hard to see
5353 /// their values after they get legalized to loads from a constant pool.
5354 static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
5355 const ARMSubtarget *ST) {
5356 EVT VT = N->getValueType(0);
5358 // Nothing to be done for scalar shifts.
5359 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5360 if (!VT.isVector() || !TLI.isTypeLegal(VT))
5363 assert(ST->hasNEON() && "unexpected vector shift");
5366 switch (N->getOpcode()) {
5367 default: llvm_unreachable("unexpected shift opcode");
5370 if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
5371 return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
5372 DAG.getConstant(Cnt, MVT::i32));
5377 if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
5378 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
5379 ARMISD::VSHRs : ARMISD::VSHRu);
5380 return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
5381 DAG.getConstant(Cnt, MVT::i32));
5387 /// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
5388 /// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
5389 static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
5390 const ARMSubtarget *ST) {
5391 SDValue N0 = N->getOperand(0);
5393 // Check for sign- and zero-extensions of vector extract operations of 8-
5394 // and 16-bit vector elements. NEON supports these directly. They are
5395 // handled during DAG combining because type legalization will promote them
5396 // to 32-bit types and it is messy to recognize the operations after that.
5397 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
5398 SDValue Vec = N0.getOperand(0);
5399 SDValue Lane = N0.getOperand(1);
5400 EVT VT = N->getValueType(0);
5401 EVT EltVT = N0.getValueType();
5402 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5404 if (VT == MVT::i32 &&
5405 (EltVT == MVT::i8 || EltVT == MVT::i16) &&
5406 TLI.isTypeLegal(Vec.getValueType()) &&
5407 isa<ConstantSDNode>(Lane)) {
5410 switch (N->getOpcode()) {
5411 default: llvm_unreachable("unexpected opcode");
5412 case ISD::SIGN_EXTEND:
5413 Opc = ARMISD::VGETLANEs;
5415 case ISD::ZERO_EXTEND:
5416 case ISD::ANY_EXTEND:
5417 Opc = ARMISD::VGETLANEu;
5420 return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
5427 /// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
5428 /// to match f32 max/min patterns to use NEON vmax/vmin instructions.
5429 static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
5430 const ARMSubtarget *ST) {
5431 // If the target supports NEON, try to use vmax/vmin instructions for f32
5432 // selects like "x < y ? x : y". Unless the NoNaNsFPMath option is set,
5433 // be careful about NaNs: NEON's vmax/vmin return NaN if either operand is
5434 // a NaN; only do the transformation when it matches that behavior.
5436 // For now only do this when using NEON for FP operations; if using VFP, it
5437 // is not obvious that the benefit outweighs the cost of switching to the
5439 if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
5440 N->getValueType(0) != MVT::f32)
5443 SDValue CondLHS = N->getOperand(0);
5444 SDValue CondRHS = N->getOperand(1);
5445 SDValue LHS = N->getOperand(2);
5446 SDValue RHS = N->getOperand(3);
5447 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
5449 unsigned Opcode = 0;
5451 if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
5452 IsReversed = false; // x CC y ? x : y
5453 } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
5454 IsReversed = true ; // x CC y ? y : x
5468 // If LHS is NaN, an ordered comparison will be false and the result will
5469 // be the RHS, but vmin(NaN, RHS) = NaN. Avoid this by checking that LHS
5470 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
5471 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
5472 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
5474 // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
5475 // will return -0, so vmin can only be used for unsafe math or if one of
5476 // the operands is known to be nonzero.
5477 if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
5479 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
5481 Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
5490 // If LHS is NaN, an ordered comparison will be false and the result will
5491 // be the RHS, but vmax(NaN, RHS) = NaN. Avoid this by checking that LHS
5492 // != NaN. Likewise, for unordered comparisons, check for RHS != NaN.
5493 IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
5494 if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
5496 // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
5497 // will return +0, so vmax can only be used for unsafe math or if one of
5498 // the operands is known to be nonzero.
5499 if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
5501 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
5503 Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
5509 return DAG.getNode(Opcode, N->getDebugLoc(), N->getValueType(0), LHS, RHS);
5512 SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
5513 DAGCombinerInfo &DCI) const {
5514 switch (N->getOpcode()) {
5516 case ISD::ADD: return PerformADDCombine(N, DCI);
5517 case ISD::SUB: return PerformSUBCombine(N, DCI);
5518 case ISD::MUL: return PerformMULCombine(N, DCI, Subtarget);
5519 case ISD::OR: return PerformORCombine(N, DCI, Subtarget);
5520 case ISD::AND: return PerformANDCombine(N, DCI);
5521 case ARMISD::BFI: return PerformBFICombine(N, DCI);
5522 case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
5523 case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
5524 case ISD::STORE: return PerformSTORECombine(N, DCI);
5525 case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI);
5526 case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI);
5527 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
5528 case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
5529 case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
5532 case ISD::SRL: return PerformShiftCombine(N, DCI.DAG, Subtarget);
5533 case ISD::SIGN_EXTEND:
5534 case ISD::ZERO_EXTEND:
5535 case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
5536 case ISD::SELECT_CC: return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
5541 bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
5542 if (!Subtarget->allowsUnalignedMem())
5545 switch (VT.getSimpleVT().SimpleTy) {
5552 // FIXME: VLD1 etc with standard alignment is legal.
5556 static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
5561 switch (VT.getSimpleVT().SimpleTy) {
5562 default: return false;
5577 if ((V & (Scale - 1)) != 0)
5580 return V == (V & ((1LL << 5) - 1));
5583 static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
5584 const ARMSubtarget *Subtarget) {
5591 switch (VT.getSimpleVT().SimpleTy) {
5592 default: return false;
5597 // + imm12 or - imm8
5599 return V == (V & ((1LL << 8) - 1));
5600 return V == (V & ((1LL << 12) - 1));
5603 // Same as ARM mode. FIXME: NEON?
5604 if (!Subtarget->hasVFP2())
5609 return V == (V & ((1LL << 8) - 1));
5613 /// isLegalAddressImmediate - Return true if the integer value can be used
5614 /// as the offset of the target addressing mode for load / store of the
5616 static bool isLegalAddressImmediate(int64_t V, EVT VT,
5617 const ARMSubtarget *Subtarget) {
5624 if (Subtarget->isThumb1Only())
5625 return isLegalT1AddressImmediate(V, VT);
5626 else if (Subtarget->isThumb2())
5627 return isLegalT2AddressImmediate(V, VT, Subtarget);
5632 switch (VT.getSimpleVT().SimpleTy) {
5633 default: return false;
5638 return V == (V & ((1LL << 12) - 1));
5641 return V == (V & ((1LL << 8) - 1));
5644 if (!Subtarget->hasVFP2()) // FIXME: NEON?
5649 return V == (V & ((1LL << 8) - 1));
5653 bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
5655 int Scale = AM.Scale;
5659 switch (VT.getSimpleVT().SimpleTy) {
5660 default: return false;
5669 return Scale == 2 || Scale == 4 || Scale == 8;
5672 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
5676 // Note, we allow "void" uses (basically, uses that aren't loads or
5677 // stores), because arm allows folding a scale into many arithmetic
5678 // operations. This should be made more precise and revisited later.
5680 // Allow r << imm, but the imm has to be a multiple of two.
5681 if (Scale & 1) return false;
5682 return isPowerOf2_32(Scale);
5686 /// isLegalAddressingMode - Return true if the addressing mode represented
5687 /// by AM is legal for this target, for a load/store of the specified type.
5688 bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
5689 const Type *Ty) const {
5690 EVT VT = getValueType(Ty, true);
5691 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
5694 // Can never fold addr of global into load/store.
5699 case 0: // no scale reg, must be "r+i" or "r", or "i".
5702 if (Subtarget->isThumb1Only())
5706 // ARM doesn't support any R+R*scale+imm addr modes.
5713 if (Subtarget->isThumb2())
5714 return isLegalT2ScaledAddressingMode(AM, VT);
5716 int Scale = AM.Scale;
5717 switch (VT.getSimpleVT().SimpleTy) {
5718 default: return false;
5722 if (Scale < 0) Scale = -Scale;
5726 return isPowerOf2_32(Scale & ~1);
5730 if (((unsigned)AM.HasBaseReg + Scale) <= 2)
5735 // Note, we allow "void" uses (basically, uses that aren't loads or
5736 // stores), because arm allows folding a scale into many arithmetic
5737 // operations. This should be made more precise and revisited later.
5739 // Allow r << imm, but the imm has to be a multiple of two.
5740 if (Scale & 1) return false;
5741 return isPowerOf2_32(Scale);
5748 /// isLegalICmpImmediate - Return true if the specified immediate is legal
5749 /// icmp immediate, that is the target has icmp instructions which can compare
5750 /// a register against the immediate without having to materialize the
5751 /// immediate into a register.
5752 bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
5753 if (!Subtarget->isThumb())
5754 return ARM_AM::getSOImmVal(Imm) != -1;
5755 if (Subtarget->isThumb2())
5756 return ARM_AM::getT2SOImmVal(Imm) != -1;
5757 return Imm >= 0 && Imm <= 255;
5760 static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
5761 bool isSEXTLoad, SDValue &Base,
5762 SDValue &Offset, bool &isInc,
5763 SelectionDAG &DAG) {
5764 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
5767 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
5769 Base = Ptr->getOperand(0);
5770 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
5771 int RHSC = (int)RHS->getZExtValue();
5772 if (RHSC < 0 && RHSC > -256) {
5773 assert(Ptr->getOpcode() == ISD::ADD);
5775 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
5779 isInc = (Ptr->getOpcode() == ISD::ADD);
5780 Offset = Ptr->getOperand(1);
5782 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
5784 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
5785 int RHSC = (int)RHS->getZExtValue();
5786 if (RHSC < 0 && RHSC > -0x1000) {
5787 assert(Ptr->getOpcode() == ISD::ADD);
5789 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
5790 Base = Ptr->getOperand(0);
5795 if (Ptr->getOpcode() == ISD::ADD) {
5797 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
5798 if (ShOpcVal != ARM_AM::no_shift) {
5799 Base = Ptr->getOperand(1);
5800 Offset = Ptr->getOperand(0);
5802 Base = Ptr->getOperand(0);
5803 Offset = Ptr->getOperand(1);
5808 isInc = (Ptr->getOpcode() == ISD::ADD);
5809 Base = Ptr->getOperand(0);
5810 Offset = Ptr->getOperand(1);
5814 // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
5818 static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
5819 bool isSEXTLoad, SDValue &Base,
5820 SDValue &Offset, bool &isInc,
5821 SelectionDAG &DAG) {
5822 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
5825 Base = Ptr->getOperand(0);
5826 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
5827 int RHSC = (int)RHS->getZExtValue();
5828 if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
5829 assert(Ptr->getOpcode() == ISD::ADD);
5831 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
5833 } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
5834 isInc = Ptr->getOpcode() == ISD::ADD;
5835 Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
5843 /// getPreIndexedAddressParts - returns true by value, base pointer and
5844 /// offset pointer and addressing mode by reference if the node's address
5845 /// can be legally represented as pre-indexed load / store address.
5847 ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
5849 ISD::MemIndexedMode &AM,
5850 SelectionDAG &DAG) const {
5851 if (Subtarget->isThumb1Only())
5856 bool isSEXTLoad = false;
5857 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5858 Ptr = LD->getBasePtr();
5859 VT = LD->getMemoryVT();
5860 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
5861 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5862 Ptr = ST->getBasePtr();
5863 VT = ST->getMemoryVT();
5868 bool isLegal = false;
5869 if (Subtarget->isThumb2())
5870 isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
5871 Offset, isInc, DAG);
5873 isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
5874 Offset, isInc, DAG);
5878 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
5882 /// getPostIndexedAddressParts - returns true by value, base pointer and
5883 /// offset pointer and addressing mode by reference if this node can be
5884 /// combined with a load / store to form a post-indexed load / store.
5885 bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
5888 ISD::MemIndexedMode &AM,
5889 SelectionDAG &DAG) const {
5890 if (Subtarget->isThumb1Only())
5895 bool isSEXTLoad = false;
5896 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
5897 VT = LD->getMemoryVT();
5898 Ptr = LD->getBasePtr();
5899 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
5900 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
5901 VT = ST->getMemoryVT();
5902 Ptr = ST->getBasePtr();
5907 bool isLegal = false;
5908 if (Subtarget->isThumb2())
5909 isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
5912 isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
5918 // Swap base ptr and offset to catch more post-index load / store when
5919 // it's legal. In Thumb2 mode, offset must be an immediate.
5920 if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
5921 !Subtarget->isThumb2())
5922 std::swap(Base, Offset);
5924 // Post-indexed load / store update the base pointer.
5929 AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
5933 void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
5937 const SelectionDAG &DAG,
5938 unsigned Depth) const {
5939 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
5940 switch (Op.getOpcode()) {
5942 case ARMISD::CMOV: {
5943 // Bits are known zero/one if known on the LHS and RHS.
5944 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
5945 if (KnownZero == 0 && KnownOne == 0) return;
5947 APInt KnownZeroRHS, KnownOneRHS;
5948 DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
5949 KnownZeroRHS, KnownOneRHS, Depth+1);
5950 KnownZero &= KnownZeroRHS;
5951 KnownOne &= KnownOneRHS;
5957 //===----------------------------------------------------------------------===//
5958 // ARM Inline Assembly Support
5959 //===----------------------------------------------------------------------===//
5961 /// getConstraintType - Given a constraint letter, return the type of
5962 /// constraint it is for this target.
5963 ARMTargetLowering::ConstraintType
5964 ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
5965 if (Constraint.size() == 1) {
5966 switch (Constraint[0]) {
5968 case 'l': return C_RegisterClass;
5969 case 'w': return C_RegisterClass;
5972 return TargetLowering::getConstraintType(Constraint);
5975 /// Examine constraint type and operand type and determine a weight value.
5976 /// This object must already have been set up with the operand type
5977 /// and the current alternative constraint selected.
5978 TargetLowering::ConstraintWeight
5979 ARMTargetLowering::getSingleConstraintMatchWeight(
5980 AsmOperandInfo &info, const char *constraint) const {
5981 ConstraintWeight weight = CW_Invalid;
5982 Value *CallOperandVal = info.CallOperandVal;
5983 // If we don't have a value, we can't do a match,
5984 // but allow it at the lowest weight.
5985 if (CallOperandVal == NULL)
5987 const Type *type = CallOperandVal->getType();
5988 // Look at the constraint type.
5989 switch (*constraint) {
5991 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
5994 if (type->isIntegerTy()) {
5995 if (Subtarget->isThumb())
5996 weight = CW_SpecificReg;
5998 weight = CW_Register;
6002 if (type->isFloatingPointTy())
6003 weight = CW_Register;
6009 std::pair<unsigned, const TargetRegisterClass*>
6010 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
6012 if (Constraint.size() == 1) {
6013 // GCC ARM Constraint Letters
6014 switch (Constraint[0]) {
6016 if (Subtarget->isThumb())
6017 return std::make_pair(0U, ARM::tGPRRegisterClass);
6019 return std::make_pair(0U, ARM::GPRRegisterClass);
6021 return std::make_pair(0U, ARM::GPRRegisterClass);
6024 return std::make_pair(0U, ARM::SPRRegisterClass);
6025 if (VT.getSizeInBits() == 64)
6026 return std::make_pair(0U, ARM::DPRRegisterClass);
6027 if (VT.getSizeInBits() == 128)
6028 return std::make_pair(0U, ARM::QPRRegisterClass);
6032 if (StringRef("{cc}").equals_lower(Constraint))
6033 return std::make_pair(unsigned(ARM::CPSR), ARM::CCRRegisterClass);
6035 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
6038 std::vector<unsigned> ARMTargetLowering::
6039 getRegClassForInlineAsmConstraint(const std::string &Constraint,
6041 if (Constraint.size() != 1)
6042 return std::vector<unsigned>();
6044 switch (Constraint[0]) { // GCC ARM Constraint Letters
6047 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
6048 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
6051 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
6052 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
6053 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
6054 ARM::R12, ARM::LR, 0);
6057 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
6058 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
6059 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
6060 ARM::S12,ARM::S13,ARM::S14,ARM::S15,
6061 ARM::S16,ARM::S17,ARM::S18,ARM::S19,
6062 ARM::S20,ARM::S21,ARM::S22,ARM::S23,
6063 ARM::S24,ARM::S25,ARM::S26,ARM::S27,
6064 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
6065 if (VT.getSizeInBits() == 64)
6066 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
6067 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
6068 ARM::D8, ARM::D9, ARM::D10,ARM::D11,
6069 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
6070 if (VT.getSizeInBits() == 128)
6071 return make_vector<unsigned>(ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
6072 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 0);
6076 return std::vector<unsigned>();
6079 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
6080 /// vector. If it is invalid, don't add anything to Ops.
6081 void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
6083 std::vector<SDValue>&Ops,
6084 SelectionDAG &DAG) const {
6085 SDValue Result(0, 0);
6087 switch (Constraint) {
6089 case 'I': case 'J': case 'K': case 'L':
6090 case 'M': case 'N': case 'O':
6091 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
6095 int64_t CVal64 = C->getSExtValue();
6096 int CVal = (int) CVal64;
6097 // None of these constraints allow values larger than 32 bits. Check
6098 // that the value fits in an int.
6102 switch (Constraint) {
6104 if (Subtarget->isThumb1Only()) {
6105 // This must be a constant between 0 and 255, for ADD
6107 if (CVal >= 0 && CVal <= 255)
6109 } else if (Subtarget->isThumb2()) {
6110 // A constant that can be used as an immediate value in a
6111 // data-processing instruction.
6112 if (ARM_AM::getT2SOImmVal(CVal) != -1)
6115 // A constant that can be used as an immediate value in a
6116 // data-processing instruction.
6117 if (ARM_AM::getSOImmVal(CVal) != -1)
6123 if (Subtarget->isThumb()) { // FIXME thumb2
6124 // This must be a constant between -255 and -1, for negated ADD
6125 // immediates. This can be used in GCC with an "n" modifier that
6126 // prints the negated value, for use with SUB instructions. It is
6127 // not useful otherwise but is implemented for compatibility.
6128 if (CVal >= -255 && CVal <= -1)
6131 // This must be a constant between -4095 and 4095. It is not clear
6132 // what this constraint is intended for. Implemented for
6133 // compatibility with GCC.
6134 if (CVal >= -4095 && CVal <= 4095)
6140 if (Subtarget->isThumb1Only()) {
6141 // A 32-bit value where only one byte has a nonzero value. Exclude
6142 // zero to match GCC. This constraint is used by GCC internally for
6143 // constants that can be loaded with a move/shift combination.
6144 // It is not useful otherwise but is implemented for compatibility.
6145 if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
6147 } else if (Subtarget->isThumb2()) {
6148 // A constant whose bitwise inverse can be used as an immediate
6149 // value in a data-processing instruction. This can be used in GCC
6150 // with a "B" modifier that prints the inverted value, for use with
6151 // BIC and MVN instructions. It is not useful otherwise but is
6152 // implemented for compatibility.
6153 if (ARM_AM::getT2SOImmVal(~CVal) != -1)
6156 // A constant whose bitwise inverse can be used as an immediate
6157 // value in a data-processing instruction. This can be used in GCC
6158 // with a "B" modifier that prints the inverted value, for use with
6159 // BIC and MVN instructions. It is not useful otherwise but is
6160 // implemented for compatibility.
6161 if (ARM_AM::getSOImmVal(~CVal) != -1)
6167 if (Subtarget->isThumb1Only()) {
6168 // This must be a constant between -7 and 7,
6169 // for 3-operand ADD/SUB immediate instructions.
6170 if (CVal >= -7 && CVal < 7)
6172 } else if (Subtarget->isThumb2()) {
6173 // A constant whose negation can be used as an immediate value in a
6174 // data-processing instruction. This can be used in GCC with an "n"
6175 // modifier that prints the negated value, for use with SUB
6176 // instructions. It is not useful otherwise but is implemented for
6178 if (ARM_AM::getT2SOImmVal(-CVal) != -1)
6181 // A constant whose negation can be used as an immediate value in a
6182 // data-processing instruction. This can be used in GCC with an "n"
6183 // modifier that prints the negated value, for use with SUB
6184 // instructions. It is not useful otherwise but is implemented for
6186 if (ARM_AM::getSOImmVal(-CVal) != -1)
6192 if (Subtarget->isThumb()) { // FIXME thumb2
6193 // This must be a multiple of 4 between 0 and 1020, for
6194 // ADD sp + immediate.
6195 if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
6198 // A power of two or a constant between 0 and 32. This is used in
6199 // GCC for the shift amount on shifted register operands, but it is
6200 // useful in general for any shift amounts.
6201 if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
6207 if (Subtarget->isThumb()) { // FIXME thumb2
6208 // This must be a constant between 0 and 31, for shift amounts.
6209 if (CVal >= 0 && CVal <= 31)
6215 if (Subtarget->isThumb()) { // FIXME thumb2
6216 // This must be a multiple of 4 between -508 and 508, for
6217 // ADD/SUB sp = sp + immediate.
6218 if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
6223 Result = DAG.getTargetConstant(CVal, Op.getValueType());
6227 if (Result.getNode()) {
6228 Ops.push_back(Result);
6231 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
6235 ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
6236 // The ARM target isn't yet aware of offsets.
6240 int ARM::getVFPf32Imm(const APFloat &FPImm) {
6241 APInt Imm = FPImm.bitcastToAPInt();
6242 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
6243 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127
6244 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits
6246 // We can handle 4 bits of mantissa.
6247 // mantissa = (16+UInt(e:f:g:h))/16.
6248 if (Mantissa & 0x7ffff)
6251 if ((Mantissa & 0xf) != Mantissa)
6254 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
6255 if (Exp < -3 || Exp > 4)
6257 Exp = ((Exp+3) & 0x7) ^ 4;
6259 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
6262 int ARM::getVFPf64Imm(const APFloat &FPImm) {
6263 APInt Imm = FPImm.bitcastToAPInt();
6264 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
6265 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
6266 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffLL;
6268 // We can handle 4 bits of mantissa.
6269 // mantissa = (16+UInt(e:f:g:h))/16.
6270 if (Mantissa & 0xffffffffffffLL)
6273 if ((Mantissa & 0xf) != Mantissa)
6276 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
6277 if (Exp < -3 || Exp > 4)
6279 Exp = ((Exp+3) & 0x7) ^ 4;
6281 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
6284 bool ARM::isBitFieldInvertedMask(unsigned v) {
6285 if (v == 0xffffffff)
6287 // there can be 1's on either or both "outsides", all the "inside"
6289 unsigned int lsb = 0, msb = 31;
6290 while (v & (1 << msb)) --msb;
6291 while (v & (1 << lsb)) ++lsb;
6292 for (unsigned int i = lsb; i <= msb; ++i) {
6299 /// isFPImmLegal - Returns true if the target can instruction select the
6300 /// specified FP immediate natively. If false, the legalizer will
6301 /// materialize the FP immediate as a load from a constant pool.
6302 bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
6303 if (!Subtarget->hasVFP3())
6306 return ARM::getVFPf32Imm(Imm) != -1;
6308 return ARM::getVFPf64Imm(Imm) != -1;
6312 /// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
6313 /// MemIntrinsicNodes. The associated MachineMemOperands record the alignment
6314 /// specified in the intrinsic calls.
6315 bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
6317 unsigned Intrinsic) const {
6318 switch (Intrinsic) {
6319 case Intrinsic::arm_neon_vld1:
6320 case Intrinsic::arm_neon_vld2:
6321 case Intrinsic::arm_neon_vld3:
6322 case Intrinsic::arm_neon_vld4:
6323 case Intrinsic::arm_neon_vld2lane:
6324 case Intrinsic::arm_neon_vld3lane:
6325 case Intrinsic::arm_neon_vld4lane: {
6326 Info.opc = ISD::INTRINSIC_W_CHAIN;
6327 // Conservatively set memVT to the entire set of vectors loaded.
6328 uint64_t NumElts = getTargetData()->getTypeAllocSize(I.getType()) / 8;
6329 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6330 Info.ptrVal = I.getArgOperand(0);
6332 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
6333 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
6334 Info.vol = false; // volatile loads with NEON intrinsics not supported
6335 Info.readMem = true;
6336 Info.writeMem = false;
6339 case Intrinsic::arm_neon_vst1:
6340 case Intrinsic::arm_neon_vst2:
6341 case Intrinsic::arm_neon_vst3:
6342 case Intrinsic::arm_neon_vst4:
6343 case Intrinsic::arm_neon_vst2lane:
6344 case Intrinsic::arm_neon_vst3lane:
6345 case Intrinsic::arm_neon_vst4lane: {
6346 Info.opc = ISD::INTRINSIC_VOID;
6347 // Conservatively set memVT to the entire set of vectors stored.
6348 unsigned NumElts = 0;
6349 for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
6350 const Type *ArgTy = I.getArgOperand(ArgI)->getType();
6351 if (!ArgTy->isVectorTy())
6353 NumElts += getTargetData()->getTypeAllocSize(ArgTy) / 8;
6355 Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
6356 Info.ptrVal = I.getArgOperand(0);
6358 Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
6359 Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
6360 Info.vol = false; // volatile stores with NEON intrinsics not supported
6361 Info.readMem = false;
6362 Info.writeMem = true;